/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the AMDGPU target                          *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 168;
using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const uint8_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
  bool testSimplePredicate(unsigned PredicateID) const override;
  bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(6),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// LLT Objects.
enum {
  GILLT_p0s64,
  GILLT_p1s64,
  GILLT_p2s32,
  GILLT_p3s32,
  GILLT_p4s64,
  GILLT_p5s32,
  GILLT_p6s32,
  GILLT_s1,
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_v2s16,
  GILLT_v2s32,
  GILLT_v2s64,
  GILLT_v3s32,
  GILLT_v3s64,
  GILLT_v4s16,
  GILLT_v4s32,
  GILLT_v4s64,
  GILLT_v5s32,
  GILLT_v6s32,
  GILLT_v7s32,
  GILLT_v8s16,
  GILLT_v8s32,
  GILLT_v8s64,
  GILLT_v9s32,
  GILLT_v10s32,
  GILLT_v11s32,
  GILLT_v12s32,
  GILLT_v16s16,
  GILLT_v16s32,
  GILLT_v16s64,
  GILLT_v32s16,
  GILLT_v32s32,
};
const static size_t NumTypeObjects = 34;
const static LLT TypeObjects[] = {
  LLT::pointer(0, 64),
  LLT::pointer(1, 64),
  LLT::pointer(2, 32),
  LLT::pointer(3, 32),
  LLT::pointer(4, 64),
  LLT::pointer(5, 32),
  LLT::pointer(6, 32),
  LLT::scalar(1),
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::vector(ElementCount::getFixed(2), 16),
  LLT::vector(ElementCount::getFixed(2), 32),
  LLT::vector(ElementCount::getFixed(2), 64),
  LLT::vector(ElementCount::getFixed(3), 32),
  LLT::vector(ElementCount::getFixed(3), 64),
  LLT::vector(ElementCount::getFixed(4), 16),
  LLT::vector(ElementCount::getFixed(4), 32),
  LLT::vector(ElementCount::getFixed(4), 64),
  LLT::vector(ElementCount::getFixed(5), 32),
  LLT::vector(ElementCount::getFixed(6), 32),
  LLT::vector(ElementCount::getFixed(7), 32),
  LLT::vector(ElementCount::getFixed(8), 16),
  LLT::vector(ElementCount::getFixed(8), 32),
  LLT::vector(ElementCount::getFixed(8), 64),
  LLT::vector(ElementCount::getFixed(9), 32),
  LLT::vector(ElementCount::getFixed(10), 32),
  LLT::vector(ElementCount::getFixed(11), 32),
  LLT::vector(ElementCount::getFixed(12), 32),
  LLT::vector(ElementCount::getFixed(16), 16),
  LLT::vector(ElementCount::getFixed(16), 32),
  LLT::vector(ElementCount::getFixed(16), 64),
  LLT::vector(ElementCount::getFixed(32), 16),
  LLT::vector(ElementCount::getFixed(32), 32),
};

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_FalsePredicateBit = 145,
  Feature_isGFX6Bit = 65,
  Feature_isGFX6GFX7Bit = 12,
  Feature_isGFX6GFX7GFX10Bit = 141,
  Feature_isGFX7OnlyBit = 106,
  Feature_isGFX7GFX10GFX11Bit = 123,
  Feature_isGFX7GFX8GFX9Bit = 61,
  Feature_isGFX6GFX7GFX8GFX9Bit = 82,
  Feature_isGFX6GFX7GFX8GFX9GFX10Bit = 157,
  Feature_isNotGFX12PlusBit = 28,
  Feature_isGFX8GFX9GFX10GFX11Bit = 31,
  Feature_isGFX7PlusBit = 18,
  Feature_isGFX8PlusBit = 4,
  Feature_isGFX8OnlyBit = 32,
  Feature_isGFX9PlusBit = 0,
  Feature_isNotGFX9PlusBit = 71,
  Feature_isGFX90APlusBit = 54,
  Feature_isNotGFX90APlusBit = 33,
  Feature_isGFX908orGFX90ABit = 55,
  Feature_isGFX940PlusBit = 56,
  Feature_isNotGFX940PlusBit = 66,
  Feature_HasGFX950InstsBit = 39,
  Feature_isGFX8GFX9Bit = 22,
  Feature_isGFX10OnlyBit = 21,
  Feature_isGFX10PlusBit = 9,
  Feature_isGFX9GFX10Bit = 72,
  Feature_isGFX11OnlyBit = 79,
  Feature_isGFX11PlusBit = 1,
  Feature_isGFX12OnlyBit = 80,
  Feature_isGFX12PlusBit = 3,
  Feature_isGFX12PlusNot12_50Bit = 77,
  Feature_isGFX125xOnlyBit = 40,
  Feature_isGFX1250PlusBit = 8,
  Feature_isNotGFX1250PlusBit = 5,
  Feature_HasIEEEMinimumMaximumInstsBit = 24,
  Feature_HasMinimum3Maximum3F32Bit = 30,
  Feature_HasMinimum3Maximum3F16Bit = 35,
  Feature_HasMin3Max3PKF16Bit = 46,
  Feature_HasMinimum3Maximum3PKF16Bit = 47,
  Feature_HasFlatAddressSpaceBit = 108,
  Feature_HasFlatBufferGlobalAtomicFaddF64InstBit = 129,
  Feature_HasAtomicFMinFMaxF32GlobalInstsBit = 137,
  Feature_HasAtomicFMinFMaxF64GlobalInstsBit = 128,
  Feature_HasAtomicFMinFMaxF32FlatInstsBit = 116,
  Feature_HasAtomicFMinFMaxF64FlatInstsBit = 117,
  Feature_HasAtomicCondSubClampFlatInstsBit = 118,
  Feature_HasLdsAtomicAddF64Bit = 161,
  Feature_HasFlatGlobalInstsBit = 110,
  Feature_HasFlatScratchInstsBit = 114,
  Feature_HasD16LoadStoreBit = 119,
  Feature_HasFlatScratchSVSModeBit = 115,
  Feature_HasFlatGVSModeBit = 109,
  Feature_HasGFX10_BEncodingBit = 120,
  Feature_HasUnpackedD16VMemBit = 135,
  Feature_HasPackedD16VMemBit = 136,
  Feature_HasUnrestrictedSOffsetBit = 133,
  Feature_D16PreservesUnusedBitsBit = 111,
  Feature_LDSRequiresM0InitBit = 152,
  Feature_NotLDSRequiresM0InitBit = 153,
  Feature_HasMTBUFInstsBit = 139,
  Feature_HasFormattedMUBUFInstsBit = 134,
  Feature_HasExportInstsBit = 11,
  Feature_HasLDSFPAtomicAddF32Bit = 160,
  Feature_HasAddNoCarryInstsBit = 81,
  Feature_NotHasAddNoCarryInstsBit = 150,
  Feature_HasXNACKEnabledBit = 105,
  Feature_Has16BitInstsBit = 13,
  Feature_NotHasTrue16BitInstsBit = 14,
  Feature_UseRealTrue16InstsBit = 15,
  Feature_NotUseRealTrue16InstsBit = 78,
  Feature_UseFakeTrue16InstsBit = 16,
  Feature_UseTrue16WithSramECCBit = 112,
  Feature_HasVOP3PInstsBit = 97,
  Feature_HasMed3_16Bit = 151,
  Feature_HasMinMaxDenormModesBit = 144,
  Feature_NotHasMinMaxDenormModesBit = 146,
  Feature_HasSDWABit = 76,
  Feature_HasPackedFP32OpsBit = 59,
  Feature_HasAddMinMaxInstsBit = 36,
  Feature_HasPkAddMinMaxInstsBit = 48,
  Feature_HasPkMinMax3InstsBit = 102,
  Feature_HasSGetShaderCyclesInstBit = 7,
  Feature_HasImageInstsBit = 10,
  Feature_HasIntClampBit = 87,
  Feature_HasMadMixInstsBit = 98,
  Feature_HasScalarStoresBit = 62,
  Feature_has16BankLDSBit = 67,
  Feature_has32BankLDSBit = 34,
  Feature_HasFmaMixInstsBit = 100,
  Feature_HasFmaMixBF16InstsBit = 101,
  Feature_HasDLInstsBit = 23,
  Feature_HasFmacF64InstBit = 149,
  Feature_HasDot1InstsBit = 52,
  Feature_HasDot2InstsBit = 49,
  Feature_HasDot3InstsBit = 86,
  Feature_HasDot4InstsBit = 85,
  Feature_HasDot5InstsBit = 83,
  Feature_HasDot6InstsBit = 84,
  Feature_HasDot7InstsBit = 51,
  Feature_HasDot8InstsBit = 103,
  Feature_HasDot9InstsBit = 43,
  Feature_HasDot10InstsBit = 50,
  Feature_HasDot11InstsBit = 104,
  Feature_HasGetWaveIdInstBit = 64,
  Feature_HasMAIInstsBit = 53,
  Feature_HasSMemRealTimeBit = 63,
  Feature_HasSMemTimeInstBit = 60,
  Feature_HasShaderCyclesRegisterBit = 107,
  Feature_HasShaderCyclesHiLoRegistersBit = 69,
  Feature_HasFP8InstsBit = 58,
  Feature_HasFP8ConversionInstsBit = 74,
  Feature_HasCubeInstsBit = 29,
  Feature_HasLerpInstBit = 27,
  Feature_HasCvtPkNormVOP2InstsBit = 20,
  Feature_HasFP8E5M3InstsBit = 88,
  Feature_NotHasFP8E5M3InstsBit = 89,
  Feature_HasMadMacF32InstsBit = 25,
  Feature_HasFmaLegacy32Bit = 26,
  Feature_HasFmacLegacy32Bit = 142,
  Feature_HasAtomicDsPkAdd16InstsBit = 158,
  Feature_HasAtomicDsCondSubClampInstsBit = 159,
  Feature_HasAtomicFlatPkAdd16InstsBit = 131,
  Feature_HasAtomicFaddRtnInstsBit = 126,
  Feature_HasAtomicFaddNoRtnInstsBit = 124,
  Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit = 125,
  Feature_HasAtomicBufferGlobalPkAddF16InstsBit = 127,
  Feature_HasFlatAtomicFaddF32InstBit = 130,
  Feature_EnableFlatScratchBit = 113,
  Feature_DisableFlatScratchBit = 138,
  Feature_HasUnalignedAccessModeBit = 156,
  Feature_HasMADIntraFwdBugBit = 93,
  Feature_HasNotMADIntraFwdBugBit = 92,
  Feature_HasSALUFloatInstsBit = 2,
  Feature_NotHasSALUFloatInstsBit = 140,
  Feature_HasPseudoScalarTransBit = 44,
  Feature_HasBitOp3InstsBit = 95,
  Feature_HasTanhInstsBit = 17,
  Feature_HasTensorCvtLutInstsBit = 42,
  Feature_HasTransposeLoadF4F6InstsBit = 122,
  Feature_HasPrngInstBit = 19,
  Feature_Has64BitLiteralsBit = 70,
  Feature_HasFP6BF6ConversionScaleInstsBit = 37,
  Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit = 38,
  Feature_HasCvtPkF16F32InstBit = 94,
  Feature_HasF32ToF16BF16ConversionSRInstsBit = 96,
  Feature_HasGDSBit = 154,
  Feature_HasCvtFP8VOP1BugBit = 73,
  Feature_HasNoCvtFP8VOP1BugBit = 75,
  Feature_HasAtomicCSubNoRtnInstsBit = 121,
  Feature_HasXF32InstsBit = 57,
  Feature_HasVmemPrefInstsBit = 132,
  Feature_HasAshrPkInstsBit = 45,
  Feature_HasLshlAddU64InstBit = 91,
  Feature_HasMadU32InstBit = 90,
  Feature_HasLdsBarrierArriveAtomicBit = 155,
  Feature_HasSetPrioIncWgInstBit = 6,
  Feature_isWave32Bit = 41,
  Feature_isWave64Bit = 68,
  Feature_FP16DenormalsBit = 148,
  Feature_FP64DenormalsBit = 147,
  Feature_NoFP32DenormalsBit = 99,
  Feature_IEEEModeDisabledBit = 143,
  Feature_HwMode5Bit = 167,
  Feature_HwMode4Bit = 166,
  Feature_HwMode1Bit = 163,
  Feature_HwMode2Bit = 164,
  Feature_HwMode0Bit = 162,
  Feature_HwMode3Bit = 165,
};

PredicateBitset AMDGPUInstructionSelector::
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
  PredicateBitset Features{};
  if (false)
    Features.set(Feature_FalsePredicateBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
    Features.set(Feature_isGFX6Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
    Features.set(Feature_isGFX6GFX7Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX6GFX7GFX10Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
    Features.set(Feature_isGFX7OnlyBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX7GFX10GFX11Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX7GFX8GFX9Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX6GFX7GFX8GFX9Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX6GFX7GFX8GFX9GFX10Bit);
  if (Subtarget->getGeneration() <= AMDGPUSubtarget::GFX11)
    Features.set(Feature_isNotGFX12PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX8GFX9GFX10GFX11Bit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
    Features.set(Feature_isGFX7PlusBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
    Features.set(Feature_isGFX8PlusBit);
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
    Features.set(Feature_isGFX8OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX9PlusBit);
  if (Subtarget->getGeneration() < AMDGPUSubtarget::GFX9)
    Features.set(Feature_isNotGFX9PlusBit);
  if (Subtarget->hasGFX90AInsts())
    Features.set(Feature_isGFX90APlusBit);
  if (!Subtarget->hasGFX90AInsts())
    Features.set(Feature_isNotGFX90APlusBit);
  if (Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts())
    Features.set(Feature_isGFX908orGFX90ABit);
  if (Subtarget->hasGFX940Insts())
    Features.set(Feature_isGFX940PlusBit);
  if (!Subtarget->hasGFX940Insts())
    Features.set(Feature_isNotGFX940PlusBit);
  if (Subtarget->hasGFX950Insts())
    Features.set(Feature_HasGFX950InstsBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX8GFX9Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX10OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX10PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX9GFX10Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX11OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX11PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX12)
    Features.set(Feature_isGFX12OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12)
    Features.set(Feature_isGFX12PlusBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12 && !Subtarget->hasGFX1250Insts())
    Features.set(Feature_isGFX12PlusNot12_50Bit);
  if (Subtarget->hasGFX1250Insts())
    Features.set(Feature_isGFX125xOnlyBit);
  if (Subtarget->hasGFX1250Insts())
    Features.set(Feature_isGFX1250PlusBit);
  if (!Subtarget->hasGFX1250Insts())
    Features.set(Feature_isNotGFX1250PlusBit);
  if (Subtarget->hasIEEEMinimumMaximumInsts())
    Features.set(Feature_HasIEEEMinimumMaximumInstsBit);
  if (Subtarget->hasMinimum3Maximum3F32())
    Features.set(Feature_HasMinimum3Maximum3F32Bit);
  if (Subtarget->hasMinimum3Maximum3F16())
    Features.set(Feature_HasMinimum3Maximum3F16Bit);
  if (Subtarget->hasMin3Max3PKF16())
    Features.set(Feature_HasMin3Max3PKF16Bit);
  if (Subtarget->hasMinimum3Maximum3PKF16())
    Features.set(Feature_HasMinimum3Maximum3PKF16Bit);
  if (Subtarget->hasFlatAddressSpace())
    Features.set(Feature_HasFlatAddressSpaceBit);
  if (Subtarget->hasFlatBufferGlobalAtomicFaddF64Inst())
    Features.set(Feature_HasFlatBufferGlobalAtomicFaddF64InstBit);
  if (Subtarget->hasAtomicFMinFMaxF32GlobalInsts())
    Features.set(Feature_HasAtomicFMinFMaxF32GlobalInstsBit);
  if (Subtarget->hasAtomicFMinFMaxF64GlobalInsts())
    Features.set(Feature_HasAtomicFMinFMaxF64GlobalInstsBit);
  if (Subtarget->hasAtomicFMinFMaxF32FlatInsts())
    Features.set(Feature_HasAtomicFMinFMaxF32FlatInstsBit);
  if (Subtarget->hasAtomicFMinFMaxF64FlatInsts())
    Features.set(Feature_HasAtomicFMinFMaxF64FlatInstsBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12)
    Features.set(Feature_HasAtomicCondSubClampFlatInstsBit);
  if (Subtarget->hasLdsAtomicAddF64())
    Features.set(Feature_HasLdsAtomicAddF64Bit);
  if (Subtarget->hasFlatGlobalInsts())
    Features.set(Feature_HasFlatGlobalInstsBit);
  if (Subtarget->hasFlatScratchInsts())
    Features.set(Feature_HasFlatScratchInstsBit);
  if (Subtarget->hasD16LoadStore())
    Features.set(Feature_HasD16LoadStoreBit);
  if (Subtarget->hasFlatScratchSVSMode())
    Features.set(Feature_HasFlatScratchSVSModeBit);
  if (Subtarget->hasFlatGVSMode())
    Features.set(Feature_HasFlatGVSModeBit);
  if (Subtarget->hasGFX10_BEncoding())
    Features.set(Feature_HasGFX10_BEncodingBit);
  if (Subtarget->hasUnpackedD16VMem())
    Features.set(Feature_HasUnpackedD16VMemBit);
  if (!Subtarget->hasUnpackedD16VMem())
    Features.set(Feature_HasPackedD16VMemBit);
  if (!Subtarget->hasRestrictedSOffset())
    Features.set(Feature_HasUnrestrictedSOffsetBit);
  if (Subtarget->d16PreservesUnusedBits())
    Features.set(Feature_D16PreservesUnusedBitsBit);
  if (Subtarget->ldsRequiresM0Init())
    Features.set(Feature_LDSRequiresM0InitBit);
  if (!Subtarget->ldsRequiresM0Init())
    Features.set(Feature_NotLDSRequiresM0InitBit);
  if (Subtarget->hasMTBUFInsts())
    Features.set(Feature_HasMTBUFInstsBit);
  if (Subtarget->hasFormattedMUBUFInsts())
    Features.set(Feature_HasFormattedMUBUFInstsBit);
  if (Subtarget->hasExportInsts())
    Features.set(Feature_HasExportInstsBit);
  if (Subtarget->hasLDSFPAtomicAddF32())
    Features.set(Feature_HasLDSFPAtomicAddF32Bit);
  if (Subtarget->hasAddNoCarry())
    Features.set(Feature_HasAddNoCarryInstsBit);
  if (!Subtarget->hasAddNoCarry())
    Features.set(Feature_NotHasAddNoCarryInstsBit);
  if (Subtarget->isXNACKEnabled())
    Features.set(Feature_HasXNACKEnabledBit);
  if (Subtarget->has16BitInsts())
    Features.set(Feature_Has16BitInstsBit);
  if (!Subtarget->hasTrue16BitInsts())
    Features.set(Feature_NotHasTrue16BitInstsBit);
  if (Subtarget->useRealTrue16Insts())
    Features.set(Feature_UseRealTrue16InstsBit);
  if (!Subtarget->useRealTrue16Insts())
    Features.set(Feature_NotUseRealTrue16InstsBit);
  if (Subtarget->hasTrue16BitInsts() && !Subtarget->useRealTrue16Insts())
    Features.set(Feature_UseFakeTrue16InstsBit);
  if (Subtarget->useRealTrue16Insts() && !Subtarget->d16PreservesUnusedBits())
    Features.set(Feature_UseTrue16WithSramECCBit);
  if (Subtarget->hasVOP3PInsts())
    Features.set(Feature_HasVOP3PInstsBit);
  if (Subtarget->hasMed3_16())
    Features.set(Feature_HasMed3_16Bit);
  if (Subtarget->supportsMinMaxDenormModes())
    Features.set(Feature_HasMinMaxDenormModesBit);
  if (!Subtarget->supportsMinMaxDenormModes())
    Features.set(Feature_NotHasMinMaxDenormModesBit);
  if (Subtarget->hasSDWA())
    Features.set(Feature_HasSDWABit);
  if (Subtarget->hasPackedFP32Ops())
    Features.set(Feature_HasPackedFP32OpsBit);
  if (Subtarget->hasAddMinMaxInsts())
    Features.set(Feature_HasAddMinMaxInstsBit);
  if (Subtarget->hasPkAddMinMaxInsts())
    Features.set(Feature_HasPkAddMinMaxInstsBit);
  if (Subtarget->hasPkMinMax3Insts())
    Features.set(Feature_HasPkMinMax3InstsBit);
  if (Subtarget->hasSGetShaderCyclesInst())
    Features.set(Feature_HasSGetShaderCyclesInstBit);
  if (Subtarget->hasImageInsts())
    Features.set(Feature_HasImageInstsBit);
  if (Subtarget->hasIntClamp())
    Features.set(Feature_HasIntClampBit);
  if (Subtarget->hasMadMixInsts())
    Features.set(Feature_HasMadMixInstsBit);
  if (Subtarget->hasScalarStores())
    Features.set(Feature_HasScalarStoresBit);
  if (Subtarget->getLDSBankCount() == 16)
    Features.set(Feature_has16BankLDSBit);
  if (Subtarget->getLDSBankCount() == 32)
    Features.set(Feature_has32BankLDSBit);
  if (Subtarget->hasFmaMixInsts())
    Features.set(Feature_HasFmaMixInstsBit);
  if (Subtarget->hasFmaMixBF16Insts())
    Features.set(Feature_HasFmaMixBF16InstsBit);
  if (Subtarget->hasDLInsts())
    Features.set(Feature_HasDLInstsBit);
  if (Subtarget->hasFmacF64Inst())
    Features.set(Feature_HasFmacF64InstBit);
  if (Subtarget->hasDot1Insts())
    Features.set(Feature_HasDot1InstsBit);
  if (Subtarget->hasDot2Insts())
    Features.set(Feature_HasDot2InstsBit);
  if (Subtarget->hasDot3Insts())
    Features.set(Feature_HasDot3InstsBit);
  if (Subtarget->hasDot4Insts())
    Features.set(Feature_HasDot4InstsBit);
  if (Subtarget->hasDot5Insts())
    Features.set(Feature_HasDot5InstsBit);
  if (Subtarget->hasDot6Insts())
    Features.set(Feature_HasDot6InstsBit);
  if (Subtarget->hasDot7Insts())
    Features.set(Feature_HasDot7InstsBit);
  if (Subtarget->hasDot8Insts())
    Features.set(Feature_HasDot8InstsBit);
  if (Subtarget->hasDot9Insts())
    Features.set(Feature_HasDot9InstsBit);
  if (Subtarget->hasDot10Insts())
    Features.set(Feature_HasDot10InstsBit);
  if (Subtarget->hasDot11Insts())
    Features.set(Feature_HasDot11InstsBit);
  if (Subtarget->hasGetWaveIdInst())
    Features.set(Feature_HasGetWaveIdInstBit);
  if (Subtarget->hasMAIInsts())
    Features.set(Feature_HasMAIInstsBit);
  if (Subtarget->hasSMemRealTime())
    Features.set(Feature_HasSMemRealTimeBit);
  if (Subtarget->hasSMemTimeInst())
    Features.set(Feature_HasSMemTimeInstBit);
  if (Subtarget->hasShaderCyclesRegister())
    Features.set(Feature_HasShaderCyclesRegisterBit);
  if (Subtarget->hasShaderCyclesHiLoRegisters())
    Features.set(Feature_HasShaderCyclesHiLoRegistersBit);
  if (Subtarget->hasFP8Insts())
    Features.set(Feature_HasFP8InstsBit);
  if (Subtarget->hasFP8ConversionInsts())
    Features.set(Feature_HasFP8ConversionInstsBit);
  if (Subtarget->hasCubeInsts())
    Features.set(Feature_HasCubeInstsBit);
  if (Subtarget->hasLerpInst())
    Features.set(Feature_HasLerpInstBit);
  if (Subtarget->hasCvtPkNormVOP2Insts())
    Features.set(Feature_HasCvtPkNormVOP2InstsBit);
  if (Subtarget->hasFP8E5M3Insts())
    Features.set(Feature_HasFP8E5M3InstsBit);
  if (!Subtarget->hasFP8E5M3Insts())
    Features.set(Feature_NotHasFP8E5M3InstsBit);
  if (Subtarget->hasMadMacF32Insts())
    Features.set(Feature_HasMadMacF32InstsBit);
  if (Subtarget->hasGFX10_3Insts())
    Features.set(Feature_HasFmaLegacy32Bit);
  if (Subtarget->hasGFX10_3Insts() && Subtarget->getGeneration() < AMDGPUSubtarget::GFX12)
    Features.set(Feature_HasFmacLegacy32Bit);
  if (Subtarget->hasAtomicDsPkAdd16Insts())
    Features.set(Feature_HasAtomicDsPkAdd16InstsBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12)
    Features.set(Feature_HasAtomicDsCondSubClampInstsBit);
  if (Subtarget->hasAtomicFlatPkAdd16Insts())
    Features.set(Feature_HasAtomicFlatPkAdd16InstsBit);
  if (Subtarget->hasAtomicFaddRtnInsts())
    Features.set(Feature_HasAtomicFaddRtnInstsBit);
  if (Subtarget->hasAtomicFaddNoRtnInsts())
    Features.set(Feature_HasAtomicFaddNoRtnInstsBit);
  if (Subtarget->hasAtomicBufferGlobalPkAddF16NoRtnInsts() || Subtarget->hasAtomicBufferGlobalPkAddF16Insts())
    Features.set(Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit);
  if (Subtarget->hasAtomicBufferGlobalPkAddF16Insts())
    Features.set(Feature_HasAtomicBufferGlobalPkAddF16InstsBit);
  if (Subtarget->hasFlatAtomicFaddF32Inst())
    Features.set(Feature_HasFlatAtomicFaddF32InstBit);
  if (Subtarget->enableFlatScratch())
    Features.set(Feature_EnableFlatScratchBit);
  if (!Subtarget->enableFlatScratch())
    Features.set(Feature_DisableFlatScratchBit);
  if (Subtarget->hasUnalignedAccessMode())
    Features.set(Feature_HasUnalignedAccessModeBit);
  if (Subtarget->hasMADIntraFwdBug())
    Features.set(Feature_HasMADIntraFwdBugBit);
  if (!Subtarget->hasMADIntraFwdBug())
    Features.set(Feature_HasNotMADIntraFwdBugBit);
  if (Subtarget->hasSALUFloatInsts())
    Features.set(Feature_HasSALUFloatInstsBit);
  if (!Subtarget->hasSALUFloatInsts())
    Features.set(Feature_NotHasSALUFloatInstsBit);
  if (Subtarget->hasPseudoScalarTrans())
    Features.set(Feature_HasPseudoScalarTransBit);
  if (Subtarget->hasBitOp3Insts())
    Features.set(Feature_HasBitOp3InstsBit);
  if (Subtarget->hasTanhInsts())
    Features.set(Feature_HasTanhInstsBit);
  if (Subtarget->hasTensorCvtLutInsts())
    Features.set(Feature_HasTensorCvtLutInstsBit);
  if (Subtarget->hasTransposeLoadF4F6Insts())
    Features.set(Feature_HasTransposeLoadF4F6InstsBit);
  if (Subtarget->hasPrngInst())
    Features.set(Feature_HasPrngInstBit);
  if (Subtarget->has64BitLiterals())
    Features.set(Feature_Has64BitLiteralsBit);
  if (Subtarget->hasFP6BF6ConversionScaleInsts())
    Features.set(Feature_HasFP6BF6ConversionScaleInstsBit);
  if (Subtarget->hasF16BF16ToFP6BF6ConversionScaleInsts())
    Features.set(Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit);
  if (Subtarget->hasCvtPkF16F32Inst())
    Features.set(Feature_HasCvtPkF16F32InstBit);
  if (Subtarget->hasF32ToF16BF16ConversionSRInsts())
    Features.set(Feature_HasF32ToF16BF16ConversionSRInstsBit);
  if (Subtarget->hasGDS())
    Features.set(Feature_HasGDSBit);
  if (Subtarget->hasCvtFP8VOP1Bug())
    Features.set(Feature_HasCvtFP8VOP1BugBit);
  if (!Subtarget->hasCvtFP8VOP1Bug())
    Features.set(Feature_HasNoCvtFP8VOP1BugBit);
  if (Subtarget->hasAtomicCSubNoRtnInsts())
    Features.set(Feature_HasAtomicCSubNoRtnInstsBit);
  if (Subtarget->hasXF32Insts())
    Features.set(Feature_HasXF32InstsBit);
  if (Subtarget->hasVmemPrefInsts())
    Features.set(Feature_HasVmemPrefInstsBit);
  if (Subtarget->hasAshrPkInsts())
    Features.set(Feature_HasAshrPkInstsBit);
  if (Subtarget->hasLshlAddU64Inst())
    Features.set(Feature_HasLshlAddU64InstBit);
  if (Subtarget->hasMadU32Inst())
    Features.set(Feature_HasMadU32InstBit);
  if (Subtarget->hasLdsBarrierArriveAtomic())
    Features.set(Feature_HasLdsBarrierArriveAtomicBit);
  if (Subtarget->hasSetPrioIncWgInst())
    Features.set(Feature_HasSetPrioIncWgInstBit);
  if (Subtarget->isWave32())
    Features.set(Feature_isWave32Bit);
  if (Subtarget->isWave64())
    Features.set(Feature_isWave64Bit);
  if (!((Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs())))
    Features.set(Feature_HwMode5Bit);
  if (!((Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs())) && !((!Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()) && (Subtarget->isWave32())) && !((!Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()) && (Subtarget->isWave64())) && !((Subtarget->isWave32()) && (!Subtarget->needsAlignedVGPRs())))
    Features.set(Feature_HwMode4Bit);
  if ((!Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()) && (Subtarget->isWave32()))
    Features.set(Feature_HwMode1Bit);
  if ((!Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()) && (Subtarget->isWave64()))
    Features.set(Feature_HwMode2Bit);
  if ((Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()))
    Features.set(Feature_HwMode0Bit);
  if ((Subtarget->isWave32()) && (!Subtarget->needsAlignedVGPRs()))
    Features.set(Feature_HwMode3Bit);
  return Features;
}

void AMDGPUInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AMDGPUSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset AMDGPUInstructionSelector::
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features{};
  if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign())
    Features.set(Feature_FP16DenormalsBit);
  if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign())
    Features.set(Feature_FP64DenormalsBit);
  if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals == DenormalMode::getPreserveSign())
    Features.set(Feature_NoFP32DenormalsBit);
  if (!MF->getInfo<SIMachineFunctionInfo>()->getMode().IEEE)
    Features.set(Feature_IEEEModeDisabledBit);
  return Features;
}

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_HwMode0,
  GIFBS_HwMode1,
  GIFBS_HwMode2,
  GIFBS_HwMode3,
  GIFBS_HwMode4,
  GIFBS_D16PreservesUnusedBits_HwMode0,
  GIFBS_D16PreservesUnusedBits_HwMode1,
  GIFBS_D16PreservesUnusedBits_HwMode2,
  GIFBS_D16PreservesUnusedBits_HwMode3,
  GIFBS_D16PreservesUnusedBits_HwMode4,
  GIFBS_DisableFlatScratch_HwMode0,
  GIFBS_DisableFlatScratch_HwMode1,
  GIFBS_DisableFlatScratch_HwMode2,
  GIFBS_DisableFlatScratch_HwMode3,
  GIFBS_DisableFlatScratch_HwMode4,
  GIFBS_Has16BitInsts,
  GIFBS_Has16BitInsts_HwMode0,
  GIFBS_Has16BitInsts_HwMode1,
  GIFBS_Has16BitInsts_HwMode2,
  GIFBS_Has16BitInsts_HwMode3,
  GIFBS_Has16BitInsts_HwMode4,
  GIFBS_HasAddMinMaxInsts,
  GIFBS_HasAddNoCarryInsts,
  GIFBS_HasAshrPkInsts,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode0,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode1,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode2,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode3,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode4,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode0,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode1,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode2,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode3,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode4,
  GIFBS_HasAtomicCSubNoRtnInsts,
  GIFBS_HasAtomicCSubNoRtnInsts_HwMode0,
  GIFBS_HasAtomicCSubNoRtnInsts_HwMode1,
  GIFBS_HasAtomicCSubNoRtnInsts_HwMode2,
  GIFBS_HasAtomicCSubNoRtnInsts_HwMode3,
  GIFBS_HasAtomicCSubNoRtnInsts_HwMode4,
  GIFBS_HasAtomicCondSubClampFlatInsts_HwMode0,
  GIFBS_HasAtomicCondSubClampFlatInsts_HwMode1,
  GIFBS_HasAtomicCondSubClampFlatInsts_HwMode2,
  GIFBS_HasAtomicCondSubClampFlatInsts_HwMode3,
  GIFBS_HasAtomicCondSubClampFlatInsts_HwMode4,
  GIFBS_HasAtomicDsCondSubClampInsts,
  GIFBS_HasAtomicDsCondSubClampInsts_HwMode0,
  GIFBS_HasAtomicDsCondSubClampInsts_HwMode1,
  GIFBS_HasAtomicDsCondSubClampInsts_HwMode2,
  GIFBS_HasAtomicDsCondSubClampInsts_HwMode3,
  GIFBS_HasAtomicDsCondSubClampInsts_HwMode4,
  GIFBS_HasAtomicDsPkAdd16Insts,
  GIFBS_HasAtomicDsPkAdd16Insts_HwMode0,
  GIFBS_HasAtomicDsPkAdd16Insts_HwMode1,
  GIFBS_HasAtomicDsPkAdd16Insts_HwMode2,
  GIFBS_HasAtomicDsPkAdd16Insts_HwMode3,
  GIFBS_HasAtomicDsPkAdd16Insts_HwMode4,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4,
  GIFBS_HasAtomicFaddNoRtnInsts_HwMode0,
  GIFBS_HasAtomicFaddNoRtnInsts_HwMode1,
  GIFBS_HasAtomicFaddNoRtnInsts_HwMode2,
  GIFBS_HasAtomicFaddNoRtnInsts_HwMode3,
  GIFBS_HasAtomicFaddNoRtnInsts_HwMode4,
  GIFBS_HasAtomicFaddRtnInsts,
  GIFBS_HasAtomicFaddRtnInsts_HwMode0,
  GIFBS_HasAtomicFaddRtnInsts_HwMode1,
  GIFBS_HasAtomicFaddRtnInsts_HwMode2,
  GIFBS_HasAtomicFaddRtnInsts_HwMode3,
  GIFBS_HasAtomicFaddRtnInsts_HwMode4,
  GIFBS_HasAtomicFlatPkAdd16Insts_HwMode0,
  GIFBS_HasAtomicFlatPkAdd16Insts_HwMode1,
  GIFBS_HasAtomicFlatPkAdd16Insts_HwMode2,
  GIFBS_HasAtomicFlatPkAdd16Insts_HwMode3,
  GIFBS_HasAtomicFlatPkAdd16Insts_HwMode4,
  GIFBS_HasBitOp3Insts,
  GIFBS_HasCubeInsts,
  GIFBS_HasCvtPkF16F32Inst,
  GIFBS_HasCvtPkF16F32Inst_HwMode0,
  GIFBS_HasCvtPkF16F32Inst_HwMode1,
  GIFBS_HasCvtPkF16F32Inst_HwMode2,
  GIFBS_HasCvtPkF16F32Inst_HwMode3,
  GIFBS_HasCvtPkF16F32Inst_HwMode4,
  GIFBS_HasCvtPkNormVOP2Insts,
  GIFBS_HasD16LoadStore_HwMode0,
  GIFBS_HasD16LoadStore_HwMode1,
  GIFBS_HasD16LoadStore_HwMode2,
  GIFBS_HasD16LoadStore_HwMode3,
  GIFBS_HasD16LoadStore_HwMode4,
  GIFBS_HasDLInsts,
  GIFBS_HasDot10Insts,
  GIFBS_HasDot1Insts,
  GIFBS_HasDot2Insts,
  GIFBS_HasDot3Insts,
  GIFBS_HasDot4Insts,
  GIFBS_HasDot5Insts,
  GIFBS_HasDot6Insts,
  GIFBS_HasDot7Insts,
  GIFBS_HasDot8Insts,
  GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0,
  GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1,
  GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2,
  GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3,
  GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4,
  GIFBS_HasF32ToF16BF16ConversionSRInsts,
  GIFBS_HasFP6BF6ConversionScaleInsts_HwMode0,
  GIFBS_HasFP6BF6ConversionScaleInsts_HwMode1,
  GIFBS_HasFP6BF6ConversionScaleInsts_HwMode2,
  GIFBS_HasFP6BF6ConversionScaleInsts_HwMode3,
  GIFBS_HasFP6BF6ConversionScaleInsts_HwMode4,
  GIFBS_HasFP8Insts,
  GIFBS_HasFP8Insts_HwMode0,
  GIFBS_HasFP8Insts_HwMode1,
  GIFBS_HasFP8Insts_HwMode2,
  GIFBS_HasFP8Insts_HwMode3,
  GIFBS_HasFP8Insts_HwMode4,
  GIFBS_HasFlatAddressSpace_HwMode0,
  GIFBS_HasFlatAddressSpace_HwMode1,
  GIFBS_HasFlatAddressSpace_HwMode2,
  GIFBS_HasFlatAddressSpace_HwMode3,
  GIFBS_HasFlatAddressSpace_HwMode4,
  GIFBS_HasFlatAtomicFaddF32Inst_HwMode0,
  GIFBS_HasFlatAtomicFaddF32Inst_HwMode1,
  GIFBS_HasFlatAtomicFaddF32Inst_HwMode2,
  GIFBS_HasFlatAtomicFaddF32Inst_HwMode3,
  GIFBS_HasFlatAtomicFaddF32Inst_HwMode4,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4,
  GIFBS_HasFlatGVSMode_HwMode0,
  GIFBS_HasFlatGVSMode_HwMode1,
  GIFBS_HasFlatGVSMode_HwMode2,
  GIFBS_HasFlatGVSMode_HwMode3,
  GIFBS_HasFlatGVSMode_HwMode4,
  GIFBS_HasFlatGlobalInsts,
  GIFBS_HasFlatGlobalInsts_HwMode0,
  GIFBS_HasFlatGlobalInsts_HwMode1,
  GIFBS_HasFlatGlobalInsts_HwMode2,
  GIFBS_HasFlatGlobalInsts_HwMode3,
  GIFBS_HasFlatGlobalInsts_HwMode4,
  GIFBS_HasFmaLegacy32,
  GIFBS_HasFmaMixInsts,
  GIFBS_HasFmacF64Inst_HwMode0,
  GIFBS_HasFmacF64Inst_HwMode1,
  GIFBS_HasFmacF64Inst_HwMode2,
  GIFBS_HasFmacF64Inst_HwMode3,
  GIFBS_HasFmacF64Inst_HwMode4,
  GIFBS_HasFmacLegacy32,
  GIFBS_HasFormattedMUBUFInsts_HwMode0,
  GIFBS_HasFormattedMUBUFInsts_HwMode1,
  GIFBS_HasFormattedMUBUFInsts_HwMode2,
  GIFBS_HasFormattedMUBUFInsts_HwMode3,
  GIFBS_HasFormattedMUBUFInsts_HwMode4,
  GIFBS_HasGDS,
  GIFBS_HasGDS_HwMode0,
  GIFBS_HasGDS_HwMode1,
  GIFBS_HasGDS_HwMode2,
  GIFBS_HasGDS_HwMode3,
  GIFBS_HasGDS_HwMode4,
  GIFBS_HasGFX10_BEncoding,
  GIFBS_HasGFX10_BEncoding_HwMode0,
  GIFBS_HasGFX10_BEncoding_HwMode1,
  GIFBS_HasGFX10_BEncoding_HwMode2,
  GIFBS_HasGFX10_BEncoding_HwMode3,
  GIFBS_HasGFX10_BEncoding_HwMode4,
  GIFBS_HasGFX950Insts,
  GIFBS_HasGFX950Insts_HwMode0,
  GIFBS_HasGFX950Insts_HwMode1,
  GIFBS_HasGFX950Insts_HwMode2,
  GIFBS_HasGFX950Insts_HwMode3,
  GIFBS_HasGFX950Insts_HwMode4,
  GIFBS_HasGetWaveIdInst,
  GIFBS_HasIEEEMinimumMaximumInsts,
  GIFBS_HasIEEEMinimumMaximumInsts_HwMode0,
  GIFBS_HasIEEEMinimumMaximumInsts_HwMode1,
  GIFBS_HasIEEEMinimumMaximumInsts_HwMode2,
  GIFBS_HasIEEEMinimumMaximumInsts_HwMode3,
  GIFBS_HasIEEEMinimumMaximumInsts_HwMode4,
  GIFBS_HasIntClamp_HwMode0,
  GIFBS_HasIntClamp_HwMode1,
  GIFBS_HasIntClamp_HwMode2,
  GIFBS_HasIntClamp_HwMode3,
  GIFBS_HasIntClamp_HwMode4,
  GIFBS_HasLdsAtomicAddF64_HwMode0,
  GIFBS_HasLdsAtomicAddF64_HwMode1,
  GIFBS_HasLdsAtomicAddF64_HwMode2,
  GIFBS_HasLdsAtomicAddF64_HwMode3,
  GIFBS_HasLdsAtomicAddF64_HwMode4,
  GIFBS_HasLerpInst,
  GIFBS_HasLshlAddU64Inst_HwMode0,
  GIFBS_HasLshlAddU64Inst_HwMode1,
  GIFBS_HasLshlAddU64Inst_HwMode2,
  GIFBS_HasLshlAddU64Inst_HwMode3,
  GIFBS_HasLshlAddU64Inst_HwMode4,
  GIFBS_HasMAIInsts_HwMode0,
  GIFBS_HasMAIInsts_HwMode1,
  GIFBS_HasMAIInsts_HwMode2,
  GIFBS_HasMAIInsts_HwMode3,
  GIFBS_HasMAIInsts_HwMode4,
  GIFBS_HasMAIInsts_HwMode5,
  GIFBS_HasMTBUFInsts_HwMode0,
  GIFBS_HasMTBUFInsts_HwMode1,
  GIFBS_HasMTBUFInsts_HwMode2,
  GIFBS_HasMTBUFInsts_HwMode3,
  GIFBS_HasMTBUFInsts_HwMode4,
  GIFBS_HasMadMacF32Insts,
  GIFBS_HasMadU32Inst,
  GIFBS_HasMinMaxDenormModes,
  GIFBS_HasMinimum3Maximum3F32,
  GIFBS_HasMinimum3Maximum3PKF16,
  GIFBS_HasPackedFP32Ops_HwMode0,
  GIFBS_HasPackedFP32Ops_HwMode1,
  GIFBS_HasPackedFP32Ops_HwMode2,
  GIFBS_HasPackedFP32Ops_HwMode3,
  GIFBS_HasPackedFP32Ops_HwMode4,
  GIFBS_HasPkAddMinMaxInsts,
  GIFBS_HasPkMinMax3Insts,
  GIFBS_HasPrngInst,
  GIFBS_HasPseudoScalarTrans,
  GIFBS_HasSALUFloatInsts,
  GIFBS_HasSGetShaderCyclesInst,
  GIFBS_HasSMemRealTime,
  GIFBS_HasSMemTimeInst,
  GIFBS_HasSetPrioIncWgInst,
  GIFBS_HasShaderCyclesHiLoRegisters,
  GIFBS_HasShaderCyclesRegister,
  GIFBS_HasTanhInsts,
  GIFBS_HasTensorCvtLutInsts_HwMode0,
  GIFBS_HasTensorCvtLutInsts_HwMode1,
  GIFBS_HasTensorCvtLutInsts_HwMode2,
  GIFBS_HasTensorCvtLutInsts_HwMode3,
  GIFBS_HasTensorCvtLutInsts_HwMode4,
  GIFBS_HasUnrestrictedSOffset,
  GIFBS_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasVOP3PInsts,
  GIFBS_HasVmemPrefInsts,
  GIFBS_HasVmemPrefInsts_HwMode0,
  GIFBS_HasVmemPrefInsts_HwMode1,
  GIFBS_HasVmemPrefInsts_HwMode2,
  GIFBS_HasVmemPrefInsts_HwMode3,
  GIFBS_HasVmemPrefInsts_HwMode4,
  GIFBS_HasXF32Insts_HwMode0,
  GIFBS_HasXF32Insts_HwMode1,
  GIFBS_HasXF32Insts_HwMode2,
  GIFBS_HasXF32Insts_HwMode3,
  GIFBS_HasXF32Insts_HwMode4,
  GIFBS_HasXNACKEnabled,
  GIFBS_IEEEModeDisabled,
  GIFBS_IEEEModeDisabled_HwMode0,
  GIFBS_IEEEModeDisabled_HwMode1,
  GIFBS_IEEEModeDisabled_HwMode2,
  GIFBS_IEEEModeDisabled_HwMode3,
  GIFBS_IEEEModeDisabled_HwMode4,
  GIFBS_LDSRequiresM0Init,
  GIFBS_LDSRequiresM0Init_HwMode0,
  GIFBS_LDSRequiresM0Init_HwMode1,
  GIFBS_LDSRequiresM0Init_HwMode2,
  GIFBS_LDSRequiresM0Init_HwMode3,
  GIFBS_LDSRequiresM0Init_HwMode4,
  GIFBS_NotHasAddNoCarryInsts_HwMode0,
  GIFBS_NotHasAddNoCarryInsts_HwMode1,
  GIFBS_NotHasAddNoCarryInsts_HwMode2,
  GIFBS_NotHasAddNoCarryInsts_HwMode3,
  GIFBS_NotHasAddNoCarryInsts_HwMode4,
  GIFBS_NotHasTrue16BitInsts,
  GIFBS_NotHasTrue16BitInsts_HwMode0,
  GIFBS_NotHasTrue16BitInsts_HwMode1,
  GIFBS_NotHasTrue16BitInsts_HwMode2,
  GIFBS_NotHasTrue16BitInsts_HwMode3,
  GIFBS_NotHasTrue16BitInsts_HwMode4,
  GIFBS_NotLDSRequiresM0Init,
  GIFBS_NotLDSRequiresM0Init_HwMode0,
  GIFBS_NotLDSRequiresM0Init_HwMode1,
  GIFBS_NotLDSRequiresM0Init_HwMode2,
  GIFBS_NotLDSRequiresM0Init_HwMode3,
  GIFBS_NotLDSRequiresM0Init_HwMode4,
  GIFBS_NotUseRealTrue16Insts,
  GIFBS_NotUseRealTrue16Insts_HwMode0,
  GIFBS_NotUseRealTrue16Insts_HwMode1,
  GIFBS_NotUseRealTrue16Insts_HwMode2,
  GIFBS_NotUseRealTrue16Insts_HwMode3,
  GIFBS_NotUseRealTrue16Insts_HwMode4,
  GIFBS_UseFakeTrue16Insts,
  GIFBS_UseFakeTrue16Insts_HwMode0,
  GIFBS_UseFakeTrue16Insts_HwMode1,
  GIFBS_UseFakeTrue16Insts_HwMode2,
  GIFBS_UseFakeTrue16Insts_HwMode3,
  GIFBS_UseFakeTrue16Insts_HwMode4,
  GIFBS_UseRealTrue16Insts,
  GIFBS_UseRealTrue16Insts_HwMode0,
  GIFBS_UseRealTrue16Insts_HwMode1,
  GIFBS_UseRealTrue16Insts_HwMode2,
  GIFBS_UseRealTrue16Insts_HwMode3,
  GIFBS_UseRealTrue16Insts_HwMode4,
  GIFBS_UseTrue16WithSramECC_HwMode0,
  GIFBS_UseTrue16WithSramECC_HwMode1,
  GIFBS_UseTrue16WithSramECC_HwMode2,
  GIFBS_UseTrue16WithSramECC_HwMode3,
  GIFBS_UseTrue16WithSramECC_HwMode4,
  GIFBS_isGFX10Only,
  GIFBS_isGFX10Plus,
  GIFBS_isGFX10Plus_HwMode0,
  GIFBS_isGFX10Plus_HwMode1,
  GIFBS_isGFX10Plus_HwMode2,
  GIFBS_isGFX10Plus_HwMode3,
  GIFBS_isGFX10Plus_HwMode4,
  GIFBS_isGFX11Only,
  GIFBS_isGFX11Plus,
  GIFBS_isGFX11Plus_HwMode0,
  GIFBS_isGFX11Plus_HwMode1,
  GIFBS_isGFX11Plus_HwMode2,
  GIFBS_isGFX11Plus_HwMode3,
  GIFBS_isGFX11Plus_HwMode4,
  GIFBS_isGFX1250Plus,
  GIFBS_isGFX1250Plus_HwMode0,
  GIFBS_isGFX1250Plus_HwMode1,
  GIFBS_isGFX1250Plus_HwMode2,
  GIFBS_isGFX1250Plus_HwMode3,
  GIFBS_isGFX1250Plus_HwMode4,
  GIFBS_isGFX125xOnly,
  GIFBS_isGFX125xOnly_HwMode0,
  GIFBS_isGFX125xOnly_HwMode1,
  GIFBS_isGFX125xOnly_HwMode2,
  GIFBS_isGFX125xOnly_HwMode3,
  GIFBS_isGFX125xOnly_HwMode4,
  GIFBS_isGFX12Only,
  GIFBS_isGFX12Only_HwMode0,
  GIFBS_isGFX12Only_HwMode1,
  GIFBS_isGFX12Only_HwMode2,
  GIFBS_isGFX12Only_HwMode3,
  GIFBS_isGFX12Only_HwMode4,
  GIFBS_isGFX12Plus,
  GIFBS_isGFX12Plus_HwMode0,
  GIFBS_isGFX12Plus_HwMode1,
  GIFBS_isGFX12Plus_HwMode2,
  GIFBS_isGFX12Plus_HwMode3,
  GIFBS_isGFX12Plus_HwMode4,
  GIFBS_isGFX12PlusNot12_50,
  GIFBS_isGFX12PlusNot12_50_HwMode0,
  GIFBS_isGFX12PlusNot12_50_HwMode1,
  GIFBS_isGFX12PlusNot12_50_HwMode2,
  GIFBS_isGFX12PlusNot12_50_HwMode3,
  GIFBS_isGFX12PlusNot12_50_HwMode4,
  GIFBS_isGFX6,
  GIFBS_isGFX6_HwMode0,
  GIFBS_isGFX6_HwMode1,
  GIFBS_isGFX6_HwMode2,
  GIFBS_isGFX6_HwMode3,
  GIFBS_isGFX6_HwMode4,
  GIFBS_isGFX6GFX7,
  GIFBS_isGFX6GFX7_HwMode0,
  GIFBS_isGFX6GFX7_HwMode1,
  GIFBS_isGFX6GFX7_HwMode2,
  GIFBS_isGFX6GFX7_HwMode3,
  GIFBS_isGFX6GFX7_HwMode4,
  GIFBS_isGFX6GFX7GFX8GFX9_HwMode0,
  GIFBS_isGFX6GFX7GFX8GFX9_HwMode1,
  GIFBS_isGFX6GFX7GFX8GFX9_HwMode2,
  GIFBS_isGFX6GFX7GFX8GFX9_HwMode3,
  GIFBS_isGFX6GFX7GFX8GFX9_HwMode4,
  GIFBS_isGFX7GFX10GFX11_HwMode0,
  GIFBS_isGFX7GFX10GFX11_HwMode1,
  GIFBS_isGFX7GFX10GFX11_HwMode2,
  GIFBS_isGFX7GFX10GFX11_HwMode3,
  GIFBS_isGFX7GFX10GFX11_HwMode4,
  GIFBS_isGFX7GFX8GFX9,
  GIFBS_isGFX7Only,
  GIFBS_isGFX7Plus_HwMode0,
  GIFBS_isGFX7Plus_HwMode1,
  GIFBS_isGFX7Plus_HwMode2,
  GIFBS_isGFX7Plus_HwMode3,
  GIFBS_isGFX7Plus_HwMode4,
  GIFBS_isGFX8GFX9,
  GIFBS_isGFX8GFX9GFX10GFX11_HwMode0,
  GIFBS_isGFX8GFX9GFX10GFX11_HwMode1,
  GIFBS_isGFX8GFX9GFX10GFX11_HwMode2,
  GIFBS_isGFX8GFX9GFX10GFX11_HwMode3,
  GIFBS_isGFX8GFX9GFX10GFX11_HwMode4,
  GIFBS_isGFX8Plus,
  GIFBS_isGFX8Plus_HwMode0,
  GIFBS_isGFX8Plus_HwMode1,
  GIFBS_isGFX8Plus_HwMode2,
  GIFBS_isGFX8Plus_HwMode3,
  GIFBS_isGFX8Plus_HwMode4,
  GIFBS_isGFX908orGFX90A_HwMode0,
  GIFBS_isGFX908orGFX90A_HwMode5,
  GIFBS_isGFX90APlus_HwMode0,
  GIFBS_isGFX90APlus_HwMode1,
  GIFBS_isGFX90APlus_HwMode2,
  GIFBS_isGFX90APlus_HwMode3,
  GIFBS_isGFX90APlus_HwMode4,
  GIFBS_isGFX940Plus,
  GIFBS_isGFX940Plus_HwMode0,
  GIFBS_isGFX940Plus_HwMode1,
  GIFBS_isGFX940Plus_HwMode2,
  GIFBS_isGFX940Plus_HwMode3,
  GIFBS_isGFX940Plus_HwMode4,
  GIFBS_isGFX9GFX10,
  GIFBS_isGFX9Plus,
  GIFBS_isNotGFX1250Plus,
  GIFBS_isNotGFX12Plus,
  GIFBS_isNotGFX12Plus_HwMode0,
  GIFBS_isNotGFX12Plus_HwMode1,
  GIFBS_isNotGFX12Plus_HwMode2,
  GIFBS_isNotGFX12Plus_HwMode3,
  GIFBS_isNotGFX12Plus_HwMode4,
  GIFBS_isNotGFX90APlus,
  GIFBS_isNotGFX940Plus,
  GIFBS_isNotGFX9Plus,
  GIFBS_isWave32,
  GIFBS_isWave32_HwMode0,
  GIFBS_isWave32_HwMode1,
  GIFBS_isWave32_HwMode2,
  GIFBS_isWave32_HwMode3,
  GIFBS_isWave32_HwMode4,
  GIFBS_isWave64,
  GIFBS_isWave64_HwMode0,
  GIFBS_isWave64_HwMode1,
  GIFBS_isWave64_HwMode2,
  GIFBS_isWave64_HwMode3,
  GIFBS_isWave64_HwMode4,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HwMode0,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HwMode1,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HwMode2,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HwMode3,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HwMode4,
  GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_HwMode0,
  GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_HwMode1,
  GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_HwMode2,
  GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_HwMode3,
  GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_HwMode4,
  GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts,
  GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0,
  GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1,
  GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2,
  GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3,
  GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode0,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode1,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode2,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode3,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode4,
  GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0,
  GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1,
  GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2,
  GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3,
  GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4,
  GIFBS_FP16Denormals_NotHasMinMaxDenormModes,
  GIFBS_FalsePredicate_NotHasMinMaxDenormModes,
  GIFBS_Has16BitInsts_HasIntClamp,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode0,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode1,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode2,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode3,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode4,
  GIFBS_Has16BitInsts_UseFakeTrue16Insts_HwMode0,
  GIFBS_Has16BitInsts_UseFakeTrue16Insts_HwMode1,
  GIFBS_Has16BitInsts_UseFakeTrue16Insts_HwMode2,
  GIFBS_Has16BitInsts_UseFakeTrue16Insts_HwMode3,
  GIFBS_Has16BitInsts_UseFakeTrue16Insts_HwMode4,
  GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0,
  GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1,
  GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2,
  GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode3,
  GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode4,
  GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9,
  GIFBS_Has16BitInsts_isGFX8GFX9,
  GIFBS_Has16BitInsts_isGFX8Only,
  GIFBS_Has16BitInsts_isNotGFX90APlus,
  GIFBS_HasAddNoCarryInsts_HasIntClamp,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicCSubNoRtnInsts_HasUnrestrictedSOffset,
  GIFBS_HasAtomicCSubNoRtnInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicCSubNoRtnInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicCSubNoRtnInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicCSubNoRtnInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicCSubNoRtnInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicCondSubClampFlatInsts_HasFlatGVSMode,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode0,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode1,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode2,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode3,
  GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode4,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3,
  GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode,
  GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode0,
  GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode1,
  GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode2,
  GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode3,
  GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode4,
  GIFBS_HasBitOp3Insts_isGFX940Plus,
  GIFBS_HasCvtFP8VOP1Bug_HasFP8ConversionInsts,
  GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode0,
  GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode1,
  GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode2,
  GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode3,
  GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode4,
  GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode0,
  GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode1,
  GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode2,
  GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode3,
  GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode4,
  GIFBS_HasDot11Insts_isGFX12Plus,
  GIFBS_HasDot9Insts_NotHasTrue16BitInsts,
  GIFBS_HasDot9Insts_UseFakeTrue16Insts,
  GIFBS_HasDot9Insts_UseRealTrue16Insts,
  GIFBS_HasExportInsts_isGFX12Plus,
  GIFBS_HasFP8ConversionInsts_HasSDWA,
  GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode0,
  GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode1,
  GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode2,
  GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode3,
  GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode4,
  GIFBS_HasFP8ConversionInsts_isGFX125xOnly,
  GIFBS_HasFP8ConversionInsts_isGFX12Plus,
  GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode0,
  GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode1,
  GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode2,
  GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode3,
  GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode4,
  GIFBS_HasFP8ConversionInsts_isGFX12PlusNot12_50,
  GIFBS_HasFP8ConversionInsts_isGFX940Plus,
  GIFBS_HasFP8Insts_isGFX90APlus_HwMode0,
  GIFBS_HasFP8Insts_isGFX90APlus_HwMode1,
  GIFBS_HasFP8Insts_isGFX90APlus_HwMode2,
  GIFBS_HasFP8Insts_isGFX90APlus_HwMode3,
  GIFBS_HasFP8Insts_isGFX90APlus_HwMode4,
  GIFBS_HasFlatAddressSpace_HasFlatGVSMode,
  GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0,
  GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1,
  GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2,
  GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3,
  GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4,
  GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0,
  GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1,
  GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2,
  GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3,
  GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4,
  GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0,
  GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1,
  GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2,
  GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3,
  GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4,
  GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode,
  GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode0,
  GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode1,
  GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode2,
  GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode3,
  GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode4,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode0,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode1,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode2,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode3,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode4,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0,
  GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1,
  GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2,
  GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3,
  GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4,
  GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0,
  GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1,
  GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2,
  GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3,
  GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4,
  GIFBS_HasFlatGVSMode_isGFX12Only,
  GIFBS_HasFlatGVSMode_isGFX12Only_HwMode0,
  GIFBS_HasFlatGVSMode_isGFX12Only_HwMode1,
  GIFBS_HasFlatGVSMode_isGFX12Only_HwMode2,
  GIFBS_HasFlatGVSMode_isGFX12Only_HwMode3,
  GIFBS_HasFlatGVSMode_isGFX12Only_HwMode4,
  GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11,
  GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode0,
  GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode1,
  GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode2,
  GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode3,
  GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode4,
  GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0,
  GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1,
  GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2,
  GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3,
  GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4,
  GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts,
  GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode0,
  GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode1,
  GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode2,
  GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode3,
  GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode4,
  GIFBS_HasFmaMixBF16Insts_UseRealTrue16Insts,
  GIFBS_HasFmaMixInsts_NotUseRealTrue16Insts,
  GIFBS_HasFmaMixInsts_UseRealTrue16Insts,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HwMode0,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HwMode1,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HwMode2,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HwMode3,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HwMode4,
  GIFBS_HasFormattedMUBUFInsts_HasUnpackedD16VMem_HwMode0,
  GIFBS_HasFormattedMUBUFInsts_HasUnpackedD16VMem_HwMode1,
  GIFBS_HasFormattedMUBUFInsts_HasUnpackedD16VMem_HwMode2,
  GIFBS_HasFormattedMUBUFInsts_HasUnpackedD16VMem_HwMode3,
  GIFBS_HasFormattedMUBUFInsts_HasUnpackedD16VMem_HwMode4,
  GIFBS_HasFormattedMUBUFInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasFormattedMUBUFInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasFormattedMUBUFInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasFormattedMUBUFInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasFormattedMUBUFInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasGDS_HasLDSFPAtomicAddF32,
  GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode0,
  GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode1,
  GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode2,
  GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode3,
  GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode4,
  GIFBS_HasGDS_isGFX11Plus,
  GIFBS_HasGDS_isGFX11Plus_HwMode0,
  GIFBS_HasGDS_isGFX11Plus_HwMode1,
  GIFBS_HasGDS_isGFX11Plus_HwMode2,
  GIFBS_HasGDS_isGFX11Plus_HwMode3,
  GIFBS_HasGDS_isGFX11Plus_HwMode4,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode0,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode1,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode2,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode3,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode4,
  GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0,
  GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1,
  GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2,
  GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3,
  GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4,
  GIFBS_HasIEEEMinimumMaximumInsts_NotHasTrue16BitInsts,
  GIFBS_HasIEEEMinimumMaximumInsts_UseFakeTrue16Insts,
  GIFBS_HasIEEEMinimumMaximumInsts_UseRealTrue16Insts,
  GIFBS_HasImageInsts_isGFX12Plus,
  GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init,
  GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode0,
  GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode1,
  GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode2,
  GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode3,
  GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode4,
  GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init,
  GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode0,
  GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode1,
  GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode2,
  GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode3,
  GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode4,
  GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus,
  GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode0,
  GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode1,
  GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode2,
  GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode3,
  GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode4,
  GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0,
  GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1,
  GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2,
  GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3,
  GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4,
  GIFBS_HasMAIInsts_isGFX90APlus_HwMode0,
  GIFBS_HasMAIInsts_isGFX90APlus_HwMode1,
  GIFBS_HasMAIInsts_isGFX90APlus_HwMode2,
  GIFBS_HasMAIInsts_isGFX90APlus_HwMode3,
  GIFBS_HasMAIInsts_isGFX90APlus_HwMode4,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HwMode0,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HwMode1,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HwMode2,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HwMode3,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HwMode4,
  GIFBS_HasMTBUFInsts_HasUnpackedD16VMem_HwMode0,
  GIFBS_HasMTBUFInsts_HasUnpackedD16VMem_HwMode1,
  GIFBS_HasMTBUFInsts_HasUnpackedD16VMem_HwMode2,
  GIFBS_HasMTBUFInsts_HasUnpackedD16VMem_HwMode3,
  GIFBS_HasMTBUFInsts_HasUnpackedD16VMem_HwMode4,
  GIFBS_HasMTBUFInsts_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasMTBUFInsts_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasMTBUFInsts_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasMTBUFInsts_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasMTBUFInsts_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasMadMacF32Insts_NoFP32Denormals,
  GIFBS_HasMadMixInsts_NoFP32Denormals,
  GIFBS_HasMed3_16_NotHasTrue16BitInsts,
  GIFBS_HasMed3_16_UseFakeTrue16Insts,
  GIFBS_HasMed3_16_UseRealTrue16Insts,
  GIFBS_HasMinMaxDenormModes_isGFX12Plus_HwMode0,
  GIFBS_HasMinMaxDenormModes_isGFX12Plus_HwMode1,
  GIFBS_HasMinMaxDenormModes_isGFX12Plus_HwMode2,
  GIFBS_HasMinMaxDenormModes_isGFX12Plus_HwMode3,
  GIFBS_HasMinMaxDenormModes_isGFX12Plus_HwMode4,
  GIFBS_HasMinMaxDenormModes_isNotGFX12Plus_HwMode0,
  GIFBS_HasMinMaxDenormModes_isNotGFX12Plus_HwMode1,
  GIFBS_HasMinMaxDenormModes_isNotGFX12Plus_HwMode2,
  GIFBS_HasMinMaxDenormModes_isNotGFX12Plus_HwMode3,
  GIFBS_HasMinMaxDenormModes_isNotGFX12Plus_HwMode4,
  GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0,
  GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1,
  GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2,
  GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3,
  GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4,
  GIFBS_HasScalarStores_isGFX8Plus,
  GIFBS_HasTanhInsts_UseFakeTrue16Insts,
  GIFBS_HasTanhInsts_UseRealTrue16Insts,
  GIFBS_HasTransposeLoadF4F6Insts_isWave32,
  GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode0,
  GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode1,
  GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode2,
  GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode3,
  GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode4,
  GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0,
  GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1,
  GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2,
  GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3,
  GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4,
  GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0,
  GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1,
  GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2,
  GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3,
  GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4,
  GIFBS_HasVOP3PInsts_IEEEModeDisabled,
  GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts,
  GIFBS_HasVOP3PInsts_UseFakeTrue16Insts,
  GIFBS_HasVOP3PInsts_UseRealTrue16Insts,
  GIFBS_HasXF32Insts_isGFX90APlus_HwMode0,
  GIFBS_HasXF32Insts_isGFX90APlus_HwMode1,
  GIFBS_HasXF32Insts_isGFX90APlus_HwMode2,
  GIFBS_HasXF32Insts_isGFX90APlus_HwMode3,
  GIFBS_HasXF32Insts_isGFX90APlus_HwMode4,
  GIFBS_HasXNACKEnabled_isGFX7Only,
  GIFBS_HasXNACKEnabled_isGFX9Plus,
  GIFBS_HasXNACKEnabled_isNotGFX9Plus,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode0,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode1,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode2,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode3,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode4,
  GIFBS_LDSRequiresM0Init_isGFX7Plus,
  GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0,
  GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1,
  GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2,
  GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3,
  GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4,
  GIFBS_NotHasTrue16BitInsts_isGFX10Plus,
  GIFBS_NotHasTrue16BitInsts_isGFX125xOnly,
  GIFBS_NotHasTrue16BitInsts_isGFX9GFX10,
  GIFBS_NotHasTrue16BitInsts_isGFX9Plus,
  GIFBS_NotHasTrue16BitInsts_isNotGFX9Plus,
  GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0,
  GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1,
  GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2,
  GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3,
  GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4,
  GIFBS_NotLDSRequiresM0Init_UseRealTrue16Insts,
  GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0,
  GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1,
  GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2,
  GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3,
  GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode0,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode1,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode2,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode3,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode4,
  GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0,
  GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1,
  GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2,
  GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3,
  GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4,
  GIFBS_NotUseRealTrue16Insts_isGFX11Plus,
  GIFBS_NotUseRealTrue16Insts_isGFX8Plus,
  GIFBS_UseFakeTrue16Insts_isGFX10Plus,
  GIFBS_UseFakeTrue16Insts_isGFX1250Plus,
  GIFBS_UseFakeTrue16Insts_isGFX125xOnly,
  GIFBS_UseFakeTrue16Insts_isGFX9Plus,
  GIFBS_UseRealTrue16Insts_isGFX10Plus,
  GIFBS_UseRealTrue16Insts_isGFX11Plus,
  GIFBS_UseRealTrue16Insts_isGFX1250Plus,
  GIFBS_UseRealTrue16Insts_isGFX125xOnly,
  GIFBS_UseRealTrue16Insts_isGFX8Plus,
  GIFBS_UseRealTrue16Insts_isGFX9Plus,
  GIFBS_has16BankLDS_isNotGFX90APlus,
  GIFBS_has32BankLDS_isNotGFX90APlus,
  GIFBS_isGFX11Only_isWave32_HwMode0,
  GIFBS_isGFX11Only_isWave32_HwMode1,
  GIFBS_isGFX11Only_isWave32_HwMode2,
  GIFBS_isGFX11Only_isWave32_HwMode3,
  GIFBS_isGFX11Only_isWave32_HwMode4,
  GIFBS_isGFX11Only_isWave64_HwMode0,
  GIFBS_isGFX11Only_isWave64_HwMode1,
  GIFBS_isGFX11Only_isWave64_HwMode2,
  GIFBS_isGFX11Only_isWave64_HwMode3,
  GIFBS_isGFX11Only_isWave64_HwMode4,
  GIFBS_isGFX1250Plus_isWave32,
  GIFBS_isGFX1250Plus_isWave32_HwMode0,
  GIFBS_isGFX1250Plus_isWave32_HwMode1,
  GIFBS_isGFX1250Plus_isWave32_HwMode2,
  GIFBS_isGFX1250Plus_isWave32_HwMode3,
  GIFBS_isGFX1250Plus_isWave32_HwMode4,
  GIFBS_isGFX125xOnly_isWave32_HwMode0,
  GIFBS_isGFX125xOnly_isWave32_HwMode1,
  GIFBS_isGFX125xOnly_isWave32_HwMode2,
  GIFBS_isGFX125xOnly_isWave32_HwMode3,
  GIFBS_isGFX125xOnly_isWave32_HwMode4,
  GIFBS_isGFX12Plus_isWave32_HwMode0,
  GIFBS_isGFX12Plus_isWave32_HwMode1,
  GIFBS_isGFX12Plus_isWave32_HwMode2,
  GIFBS_isGFX12Plus_isWave32_HwMode3,
  GIFBS_isGFX12Plus_isWave32_HwMode4,
  GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0,
  GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1,
  GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2,
  GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3,
  GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4,
  GIFBS_isGFX12PlusNot12_50_isWave64,
  GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0,
  GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1,
  GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2,
  GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3,
  GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4,
  GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0,
  GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1,
  GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2,
  GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3,
  GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4,
  GIFBS_isGFX90APlus_isGFX940Plus_HwMode0,
  GIFBS_isGFX90APlus_isGFX940Plus_HwMode1,
  GIFBS_isGFX90APlus_isGFX940Plus_HwMode2,
  GIFBS_isGFX90APlus_isGFX940Plus_HwMode3,
  GIFBS_isGFX90APlus_isGFX940Plus_HwMode4,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3,
  GIFBS_D16PreservesUnusedBits_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HwMode0,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HwMode1,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HwMode2,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HwMode3,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HwMode4,
  GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0,
  GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1,
  GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2,
  GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3,
  GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4,
  GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_UseRealTrue16Insts,
  GIFBS_D16PreservesUnusedBits_HasFlatScratchSVSMode_UseRealTrue16Insts,
  GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode0,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode1,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode2,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode3,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode4,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode0,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode1,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode2,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode3,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode4,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseRealTrue16Insts,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus_HwMode0,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus_HwMode1,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus_HwMode2,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus_HwMode3,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus_HwMode4,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus_HwMode0,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus_HwMode1,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus_HwMode2,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus_HwMode3,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus_HwMode4,
  GIFBS_Has16BitInsts_HasMinMaxDenormModes_NotHasTrue16BitInsts,
  GIFBS_Has16BitInsts_HasMinMaxDenormModes_UseFakeTrue16Insts,
  GIFBS_Has16BitInsts_HasMinMaxDenormModes_UseRealTrue16Insts,
  GIFBS_Has16BitInsts_HasTanhInsts_NotHasTrue16BitInsts,
  GIFBS_Has16BitInsts_IEEEModeDisabled_NotHasTrue16BitInsts,
  GIFBS_Has16BitInsts_IEEEModeDisabled_UseFakeTrue16Insts,
  GIFBS_Has16BitInsts_IEEEModeDisabled_UseRealTrue16Insts,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Plus,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX1250Plus,
  GIFBS_Has16BitInsts_has32BankLDS_isNotGFX90APlus,
  GIFBS_HasBitOp3Insts_UseFakeTrue16Insts_isGFX1250Plus,
  GIFBS_HasBitOp3Insts_UseRealTrue16Insts_isGFX1250Plus,
  GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_isGFX12Plus,
  GIFBS_HasFP8ConversionInsts_HasNoCvtFP8VOP1Bug_HasSDWA,
  GIFBS_HasFP8ConversionInsts_NotHasFP8E5M3Insts_isGFX12Plus,
  GIFBS_HasFP8ConversionInsts_NotHasTrue16BitInsts_isGFX9Plus,
  GIFBS_HasFP8ConversionInsts_UseFakeTrue16Insts_isGFX9Plus,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasFormattedMUBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode0,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode1,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode2,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode3,
  GIFBS_HasMTBUFInsts_HasPackedD16VMem_HasUnrestrictedSOffset_HwMode4,
  GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10,
  GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32,
  GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode0,
  GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode1,
  GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode2,
  GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode3,
  GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode4,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3,
  GIFBS_D16PreservesUnusedBits_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4,
  GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseRealTrue16Insts,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode0,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode1,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode2,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode3,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode4,
  GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_NotHasTrue16BitInsts,
  GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_UseFakeTrue16Insts,
  GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_UseRealTrue16Insts,
  GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_UseFakeTrue16Insts_isGFX9Plus,
  GIFBS_HasFP8ConversionInsts_NotHasFP8E5M3Insts_NotHasTrue16BitInsts_isGFX9Plus,
};
constexpr static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_HwMode0Bit, },
  {Feature_HwMode1Bit, },
  {Feature_HwMode2Bit, },
  {Feature_HwMode3Bit, },
  {Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HwMode4Bit, },
  {Feature_DisableFlatScratchBit, Feature_HwMode0Bit, },
  {Feature_DisableFlatScratchBit, Feature_HwMode1Bit, },
  {Feature_DisableFlatScratchBit, Feature_HwMode2Bit, },
  {Feature_DisableFlatScratchBit, Feature_HwMode3Bit, },
  {Feature_DisableFlatScratchBit, Feature_HwMode4Bit, },
  {Feature_Has16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_HwMode0Bit, },
  {Feature_Has16BitInstsBit, Feature_HwMode1Bit, },
  {Feature_Has16BitInstsBit, Feature_HwMode2Bit, },
  {Feature_Has16BitInstsBit, Feature_HwMode3Bit, },
  {Feature_Has16BitInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAddMinMaxInstsBit, },
  {Feature_HasAddNoCarryInstsBit, },
  {Feature_HasAshrPkInstsBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicCondSubClampFlatInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicCondSubClampFlatInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicCondSubClampFlatInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicCondSubClampFlatInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicCondSubClampFlatInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicDsCondSubClampInstsBit, },
  {Feature_HasAtomicDsCondSubClampInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicDsCondSubClampInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicDsCondSubClampInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicDsCondSubClampInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicDsCondSubClampInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasBitOp3InstsBit, },
  {Feature_HasCubeInstsBit, },
  {Feature_HasCvtPkF16F32InstBit, },
  {Feature_HasCvtPkF16F32InstBit, Feature_HwMode0Bit, },
  {Feature_HasCvtPkF16F32InstBit, Feature_HwMode1Bit, },
  {Feature_HasCvtPkF16F32InstBit, Feature_HwMode2Bit, },
  {Feature_HasCvtPkF16F32InstBit, Feature_HwMode3Bit, },
  {Feature_HasCvtPkF16F32InstBit, Feature_HwMode4Bit, },
  {Feature_HasCvtPkNormVOP2InstsBit, },
  {Feature_HasD16LoadStoreBit, Feature_HwMode0Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HwMode1Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HwMode2Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HwMode3Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HwMode4Bit, },
  {Feature_HasDLInstsBit, },
  {Feature_HasDot10InstsBit, },
  {Feature_HasDot1InstsBit, },
  {Feature_HasDot2InstsBit, },
  {Feature_HasDot3InstsBit, },
  {Feature_HasDot4InstsBit, },
  {Feature_HasDot5InstsBit, },
  {Feature_HasDot6InstsBit, },
  {Feature_HasDot7InstsBit, },
  {Feature_HasDot8InstsBit, },
  {Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit, Feature_HwMode0Bit, },
  {Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit, Feature_HwMode1Bit, },
  {Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit, Feature_HwMode2Bit, },
  {Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit, Feature_HwMode3Bit, },
  {Feature_HasF16BF16ToFP6BF6ConversionScaleInstsBit, Feature_HwMode4Bit, },
  {Feature_HasF32ToF16BF16ConversionSRInstsBit, },
  {Feature_HasFP6BF6ConversionScaleInstsBit, Feature_HwMode0Bit, },
  {Feature_HasFP6BF6ConversionScaleInstsBit, Feature_HwMode1Bit, },
  {Feature_HasFP6BF6ConversionScaleInstsBit, Feature_HwMode2Bit, },
  {Feature_HasFP6BF6ConversionScaleInstsBit, Feature_HwMode3Bit, },
  {Feature_HasFP6BF6ConversionScaleInstsBit, Feature_HwMode4Bit, },
  {Feature_HasFP8InstsBit, },
  {Feature_HasFP8InstsBit, Feature_HwMode0Bit, },
  {Feature_HasFP8InstsBit, Feature_HwMode1Bit, },
  {Feature_HasFP8InstsBit, Feature_HwMode2Bit, },
  {Feature_HasFP8InstsBit, Feature_HwMode3Bit, },
  {Feature_HasFP8InstsBit, Feature_HwMode4Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HwMode0Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HwMode1Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HwMode2Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HwMode3Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HwMode4Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HwMode0Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HwMode1Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HwMode2Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HwMode3Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HwMode4Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HwMode0Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HwMode1Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HwMode2Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HwMode3Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGlobalInstsBit, },
  {Feature_HasFlatGlobalInstsBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_HwMode4Bit, },
  {Feature_HasFmaLegacy32Bit, },
  {Feature_HasFmaMixInstsBit, },
  {Feature_HasFmacF64InstBit, Feature_HwMode0Bit, },
  {Feature_HasFmacF64InstBit, Feature_HwMode1Bit, },
  {Feature_HasFmacF64InstBit, Feature_HwMode2Bit, },
  {Feature_HasFmacF64InstBit, Feature_HwMode3Bit, },
  {Feature_HasFmacF64InstBit, Feature_HwMode4Bit, },
  {Feature_HasFmacLegacy32Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HwMode0Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HwMode1Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HwMode2Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HwMode3Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HwMode4Bit, },
  {Feature_HasGDSBit, },
  {Feature_HasGDSBit, Feature_HwMode0Bit, },
  {Feature_HasGDSBit, Feature_HwMode1Bit, },
  {Feature_HasGDSBit, Feature_HwMode2Bit, },
  {Feature_HasGDSBit, Feature_HwMode3Bit, },
  {Feature_HasGDSBit, Feature_HwMode4Bit, },
  {Feature_HasGFX10_BEncodingBit, },
  {Feature_HasGFX10_BEncodingBit, Feature_HwMode0Bit, },
  {Feature_HasGFX10_BEncodingBit, Feature_HwMode1Bit, },
  {Feature_HasGFX10_BEncodingBit, Feature_HwMode2Bit, },
  {Feature_HasGFX10_BEncodingBit, Feature_HwMode3Bit, },
  {Feature_HasGFX10_BEncodingBit, Feature_HwMode4Bit, },
  {Feature_HasGFX950InstsBit, },
  {Feature_HasGFX950InstsBit, Feature_HwMode0Bit, },
  {Feature_HasGFX950InstsBit, Feature_HwMode1Bit, },
  {Feature_HasGFX950InstsBit, Feature_HwMode2Bit, },
  {Feature_HasGFX950InstsBit, Feature_HwMode3Bit, },
  {Feature_HasGFX950InstsBit, Feature_HwMode4Bit, },
  {Feature_HasGetWaveIdInstBit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_HwMode0Bit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_HwMode1Bit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_HwMode2Bit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_HwMode3Bit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_HwMode4Bit, },
  {Feature_HasIntClampBit, Feature_HwMode0Bit, },
  {Feature_HasIntClampBit, Feature_HwMode1Bit, },
  {Feature_HasIntClampBit, Feature_HwMode2Bit, },
  {Feature_HasIntClampBit, Feature_HwMode3Bit, },
  {Feature_HasIntClampBit, Feature_HwMode4Bit, },
  {Feature_HasLdsAtomicAddF64Bit, Feature_HwMode0Bit, },
  {Feature_HasLdsAtomicAddF64Bit, Feature_HwMode1Bit, },
  {Feature_HasLdsAtomicAddF64Bit, Feature_HwMode2Bit, },
  {Feature_HasLdsAtomicAddF64Bit, Feature_HwMode3Bit, },
  {Feature_HasLdsAtomicAddF64Bit, Feature_HwMode4Bit, },
  {Feature_HasLerpInstBit, },
  {Feature_HasLshlAddU64InstBit, Feature_HwMode0Bit, },
  {Feature_HasLshlAddU64InstBit, Feature_HwMode1Bit, },
  {Feature_HasLshlAddU64InstBit, Feature_HwMode2Bit, },
  {Feature_HasLshlAddU64InstBit, Feature_HwMode3Bit, },
  {Feature_HasLshlAddU64InstBit, Feature_HwMode4Bit, },
  {Feature_HasMAIInstsBit, Feature_HwMode0Bit, },
  {Feature_HasMAIInstsBit, Feature_HwMode1Bit, },
  {Feature_HasMAIInstsBit, Feature_HwMode2Bit, },
  {Feature_HasMAIInstsBit, Feature_HwMode3Bit, },
  {Feature_HasMAIInstsBit, Feature_HwMode4Bit, },
  {Feature_HasMAIInstsBit, Feature_HwMode5Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HwMode0Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HwMode1Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HwMode2Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HwMode3Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HwMode4Bit, },
  {Feature_HasMadMacF32InstsBit, },
  {Feature_HasMadU32InstBit, },
  {Feature_HasMinMaxDenormModesBit, },
  {Feature_HasMinimum3Maximum3F32Bit, },
  {Feature_HasMinimum3Maximum3PKF16Bit, },
  {Feature_HasPackedFP32OpsBit, Feature_HwMode0Bit, },
  {Feature_HasPackedFP32OpsBit, Feature_HwMode1Bit, },
  {Feature_HasPackedFP32OpsBit, Feature_HwMode2Bit, },
  {Feature_HasPackedFP32OpsBit, Feature_HwMode3Bit, },
  {Feature_HasPackedFP32OpsBit, Feature_HwMode4Bit, },
  {Feature_HasPkAddMinMaxInstsBit, },
  {Feature_HasPkMinMax3InstsBit, },
  {Feature_HasPrngInstBit, },
  {Feature_HasPseudoScalarTransBit, },
  {Feature_HasSALUFloatInstsBit, },
  {Feature_HasSGetShaderCyclesInstBit, },
  {Feature_HasSMemRealTimeBit, },
  {Feature_HasSMemTimeInstBit, },
  {Feature_HasSetPrioIncWgInstBit, },
  {Feature_HasShaderCyclesHiLoRegistersBit, },
  {Feature_HasShaderCyclesRegisterBit, },
  {Feature_HasTanhInstsBit, },
  {Feature_HasTensorCvtLutInstsBit, Feature_HwMode0Bit, },
  {Feature_HasTensorCvtLutInstsBit, Feature_HwMode1Bit, },
  {Feature_HasTensorCvtLutInstsBit, Feature_HwMode2Bit, },
  {Feature_HasTensorCvtLutInstsBit, Feature_HwMode3Bit, },
  {Feature_HasTensorCvtLutInstsBit, Feature_HwMode4Bit, },
  {Feature_HasUnrestrictedSOffsetBit, },
  {Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasVOP3PInstsBit, },
  {Feature_HasVmemPrefInstsBit, },
  {Feature_HasVmemPrefInstsBit, Feature_HwMode0Bit, },
  {Feature_HasVmemPrefInstsBit, Feature_HwMode1Bit, },
  {Feature_HasVmemPrefInstsBit, Feature_HwMode2Bit, },
  {Feature_HasVmemPrefInstsBit, Feature_HwMode3Bit, },
  {Feature_HasVmemPrefInstsBit, Feature_HwMode4Bit, },
  {Feature_HasXF32InstsBit, Feature_HwMode0Bit, },
  {Feature_HasXF32InstsBit, Feature_HwMode1Bit, },
  {Feature_HasXF32InstsBit, Feature_HwMode2Bit, },
  {Feature_HasXF32InstsBit, Feature_HwMode3Bit, },
  {Feature_HasXF32InstsBit, Feature_HwMode4Bit, },
  {Feature_HasXNACKEnabledBit, },
  {Feature_IEEEModeDisabledBit, },
  {Feature_IEEEModeDisabledBit, Feature_HwMode0Bit, },
  {Feature_IEEEModeDisabledBit, Feature_HwMode1Bit, },
  {Feature_IEEEModeDisabledBit, Feature_HwMode2Bit, },
  {Feature_IEEEModeDisabledBit, Feature_HwMode3Bit, },
  {Feature_IEEEModeDisabledBit, Feature_HwMode4Bit, },
  {Feature_LDSRequiresM0InitBit, },
  {Feature_LDSRequiresM0InitBit, Feature_HwMode0Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_HwMode1Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_HwMode2Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_HwMode3Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_HwMode4Bit, },
  {Feature_NotHasAddNoCarryInstsBit, Feature_HwMode0Bit, },
  {Feature_NotHasAddNoCarryInstsBit, Feature_HwMode1Bit, },
  {Feature_NotHasAddNoCarryInstsBit, Feature_HwMode2Bit, },
  {Feature_NotHasAddNoCarryInstsBit, Feature_HwMode3Bit, },
  {Feature_NotHasAddNoCarryInstsBit, Feature_HwMode4Bit, },
  {Feature_NotHasTrue16BitInstsBit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_HwMode0Bit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_HwMode1Bit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_HwMode2Bit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_HwMode3Bit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_HwMode4Bit, },
  {Feature_NotLDSRequiresM0InitBit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_HwMode0Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_HwMode1Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_HwMode2Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_HwMode3Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_HwMode4Bit, },
  {Feature_NotUseRealTrue16InstsBit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_UseFakeTrue16InstsBit, },
  {Feature_UseFakeTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_UseFakeTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_UseFakeTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_UseFakeTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_UseFakeTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_UseRealTrue16InstsBit, },
  {Feature_UseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_UseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_UseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_UseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_UseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_UseTrue16WithSramECCBit, Feature_HwMode0Bit, },
  {Feature_UseTrue16WithSramECCBit, Feature_HwMode1Bit, },
  {Feature_UseTrue16WithSramECCBit, Feature_HwMode2Bit, },
  {Feature_UseTrue16WithSramECCBit, Feature_HwMode3Bit, },
  {Feature_UseTrue16WithSramECCBit, Feature_HwMode4Bit, },
  {Feature_isGFX10OnlyBit, },
  {Feature_isGFX10PlusBit, },
  {Feature_isGFX10PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX10PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX10PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX10PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX10PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX11OnlyBit, },
  {Feature_isGFX11PlusBit, },
  {Feature_isGFX11PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX11PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX11PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX11PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX11PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX1250PlusBit, },
  {Feature_isGFX1250PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX1250PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX1250PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX1250PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX1250PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX125xOnlyBit, },
  {Feature_isGFX125xOnlyBit, Feature_HwMode0Bit, },
  {Feature_isGFX125xOnlyBit, Feature_HwMode1Bit, },
  {Feature_isGFX125xOnlyBit, Feature_HwMode2Bit, },
  {Feature_isGFX125xOnlyBit, Feature_HwMode3Bit, },
  {Feature_isGFX125xOnlyBit, Feature_HwMode4Bit, },
  {Feature_isGFX12OnlyBit, },
  {Feature_isGFX12OnlyBit, Feature_HwMode0Bit, },
  {Feature_isGFX12OnlyBit, Feature_HwMode1Bit, },
  {Feature_isGFX12OnlyBit, Feature_HwMode2Bit, },
  {Feature_isGFX12OnlyBit, Feature_HwMode3Bit, },
  {Feature_isGFX12OnlyBit, Feature_HwMode4Bit, },
  {Feature_isGFX12PlusBit, },
  {Feature_isGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX12PlusNot12_50Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_HwMode0Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_HwMode1Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_HwMode2Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_HwMode3Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_HwMode4Bit, },
  {Feature_isGFX6Bit, },
  {Feature_isGFX6Bit, Feature_HwMode0Bit, },
  {Feature_isGFX6Bit, Feature_HwMode1Bit, },
  {Feature_isGFX6Bit, Feature_HwMode2Bit, },
  {Feature_isGFX6Bit, Feature_HwMode3Bit, },
  {Feature_isGFX6Bit, Feature_HwMode4Bit, },
  {Feature_isGFX6GFX7Bit, },
  {Feature_isGFX6GFX7Bit, Feature_HwMode0Bit, },
  {Feature_isGFX6GFX7Bit, Feature_HwMode1Bit, },
  {Feature_isGFX6GFX7Bit, Feature_HwMode2Bit, },
  {Feature_isGFX6GFX7Bit, Feature_HwMode3Bit, },
  {Feature_isGFX6GFX7Bit, Feature_HwMode4Bit, },
  {Feature_isGFX6GFX7GFX8GFX9Bit, Feature_HwMode0Bit, },
  {Feature_isGFX6GFX7GFX8GFX9Bit, Feature_HwMode1Bit, },
  {Feature_isGFX6GFX7GFX8GFX9Bit, Feature_HwMode2Bit, },
  {Feature_isGFX6GFX7GFX8GFX9Bit, Feature_HwMode3Bit, },
  {Feature_isGFX6GFX7GFX8GFX9Bit, Feature_HwMode4Bit, },
  {Feature_isGFX7GFX10GFX11Bit, Feature_HwMode0Bit, },
  {Feature_isGFX7GFX10GFX11Bit, Feature_HwMode1Bit, },
  {Feature_isGFX7GFX10GFX11Bit, Feature_HwMode2Bit, },
  {Feature_isGFX7GFX10GFX11Bit, Feature_HwMode3Bit, },
  {Feature_isGFX7GFX10GFX11Bit, Feature_HwMode4Bit, },
  {Feature_isGFX7GFX8GFX9Bit, },
  {Feature_isGFX7OnlyBit, },
  {Feature_isGFX7PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX7PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX7PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX7PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX7PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX8GFX9Bit, },
  {Feature_isGFX8GFX9GFX10GFX11Bit, Feature_HwMode0Bit, },
  {Feature_isGFX8GFX9GFX10GFX11Bit, Feature_HwMode1Bit, },
  {Feature_isGFX8GFX9GFX10GFX11Bit, Feature_HwMode2Bit, },
  {Feature_isGFX8GFX9GFX10GFX11Bit, Feature_HwMode3Bit, },
  {Feature_isGFX8GFX9GFX10GFX11Bit, Feature_HwMode4Bit, },
  {Feature_isGFX8PlusBit, },
  {Feature_isGFX8PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX8PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX8PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX8PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX8PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX908orGFX90ABit, Feature_HwMode0Bit, },
  {Feature_isGFX908orGFX90ABit, Feature_HwMode5Bit, },
  {Feature_isGFX90APlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX90APlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX90APlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX90APlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX90APlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX940PlusBit, },
  {Feature_isGFX940PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX940PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX940PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX940PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX940PlusBit, Feature_HwMode4Bit, },
  {Feature_isGFX9GFX10Bit, },
  {Feature_isGFX9PlusBit, },
  {Feature_isNotGFX1250PlusBit, },
  {Feature_isNotGFX12PlusBit, },
  {Feature_isNotGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_isNotGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_isNotGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_isNotGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_isNotGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_isNotGFX90APlusBit, },
  {Feature_isNotGFX940PlusBit, },
  {Feature_isNotGFX9PlusBit, },
  {Feature_isWave32Bit, },
  {Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_isWave64Bit, },
  {Feature_isWave64Bit, Feature_HwMode0Bit, },
  {Feature_isWave64Bit, Feature_HwMode1Bit, },
  {Feature_isWave64Bit, Feature_HwMode2Bit, },
  {Feature_isWave64Bit, Feature_HwMode3Bit, },
  {Feature_isWave64Bit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HwMode0Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HwMode1Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HwMode2Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HwMode3Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HwMode4Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode4Bit, },
  {Feature_FP16DenormalsBit, Feature_NotHasMinMaxDenormModesBit, },
  {Feature_FalsePredicateBit, Feature_NotHasMinMaxDenormModesBit, },
  {Feature_Has16BitInstsBit, Feature_HasIntClampBit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_HwMode0Bit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_HwMode1Bit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_HwMode2Bit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_HwMode3Bit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_HwMode4Bit, },
  {Feature_Has16BitInstsBit, Feature_UseFakeTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_Has16BitInstsBit, Feature_UseFakeTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_Has16BitInstsBit, Feature_UseFakeTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_Has16BitInstsBit, Feature_UseFakeTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_Has16BitInstsBit, Feature_UseFakeTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_Has16BitInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_Has16BitInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_Has16BitInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_Has16BitInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_Has16BitInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_Has16BitInstsBit, Feature_isGFX6GFX7GFX8GFX9Bit, },
  {Feature_Has16BitInstsBit, Feature_isGFX8GFX9Bit, },
  {Feature_Has16BitInstsBit, Feature_isGFX8OnlyBit, },
  {Feature_Has16BitInstsBit, Feature_isNotGFX90APlusBit, },
  {Feature_HasAddNoCarryInstsBit, Feature_HasIntClampBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicCondSubClampFlatInstsBit, Feature_HasFlatGVSModeBit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGVSModeBit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HasFlatGVSModeBit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasBitOp3InstsBit, Feature_isGFX940PlusBit, },
  {Feature_HasCvtFP8VOP1BugBit, Feature_HasFP8ConversionInstsBit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGlobalInstsBit, Feature_HwMode0Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGlobalInstsBit, Feature_HwMode1Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGlobalInstsBit, Feature_HwMode2Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGlobalInstsBit, Feature_HwMode3Bit, },
  {Feature_HasD16LoadStoreBit, Feature_HasFlatGlobalInstsBit, Feature_HwMode4Bit, },
  {Feature_HasDot11InstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasDot9InstsBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_HasDot9InstsBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_HasDot9InstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasExportInstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasSDWABit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasSDWABit, Feature_HwMode0Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasSDWABit, Feature_HwMode1Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasSDWABit, Feature_HwMode2Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasSDWABit, Feature_HwMode3Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasSDWABit, Feature_HwMode4Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX125xOnlyBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusNot12_50Bit, },
  {Feature_HasFP8ConversionInstsBit, Feature_isGFX940PlusBit, },
  {Feature_HasFP8InstsBit, Feature_isGFX90APlusBit, Feature_HwMode0Bit, },
  {Feature_HasFP8InstsBit, Feature_isGFX90APlusBit, Feature_HwMode1Bit, },
  {Feature_HasFP8InstsBit, Feature_isGFX90APlusBit, Feature_HwMode2Bit, },
  {Feature_HasFP8InstsBit, Feature_isGFX90APlusBit, Feature_HwMode3Bit, },
  {Feature_HasFP8InstsBit, Feature_isGFX90APlusBit, Feature_HwMode4Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode0Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode1Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode2Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode3Bit, },
  {Feature_HasFlatAddressSpaceBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode4Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HasFlatGVSModeBit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasFlatAtomicFaddF32InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode0Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode1Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode2Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode3Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasFlatGVSModeBit, Feature_HwMode4Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX12OnlyBit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX12OnlyBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX12OnlyBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX12OnlyBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX12OnlyBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX12OnlyBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX7GFX10GFX11Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX7GFX10GFX11Bit, Feature_HwMode0Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX7GFX10GFX11Bit, Feature_HwMode1Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX7GFX10GFX11Bit, Feature_HwMode2Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX7GFX10GFX11Bit, Feature_HwMode3Bit, },
  {Feature_HasFlatGVSModeBit, Feature_isGFX7GFX10GFX11Bit, Feature_HwMode4Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasFlatGlobalInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_HasFlatGlobalInstsBit, Feature_UseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_HasFmaMixBF16InstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasFmaMixInstsBit, Feature_NotUseRealTrue16InstsBit, },
  {Feature_HasFmaMixInstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode0Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode1Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode2Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode3Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode4Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode0Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode1Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode2Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode3Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode4Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, Feature_HwMode0Bit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, Feature_HwMode1Bit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, Feature_HwMode2Bit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, Feature_HwMode3Bit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, Feature_HwMode4Bit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, Feature_HwMode0Bit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, Feature_HwMode1Bit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, Feature_HwMode2Bit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, Feature_HwMode3Bit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, Feature_HwMode4Bit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode0Bit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode1Bit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode2Bit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode3Bit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode4Bit, },
  {Feature_HasGFX950InstsBit, Feature_isGFX90APlusBit, Feature_HwMode0Bit, },
  {Feature_HasGFX950InstsBit, Feature_isGFX90APlusBit, Feature_HwMode1Bit, },
  {Feature_HasGFX950InstsBit, Feature_isGFX90APlusBit, Feature_HwMode2Bit, },
  {Feature_HasGFX950InstsBit, Feature_isGFX90APlusBit, Feature_HwMode3Bit, },
  {Feature_HasGFX950InstsBit, Feature_isGFX90APlusBit, Feature_HwMode4Bit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_HasIEEEMinimumMaximumInstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasImageInstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, Feature_HwMode0Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, Feature_HwMode1Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, Feature_HwMode2Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, Feature_HwMode3Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, Feature_HwMode4Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode0Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode1Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode2Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode3Bit, },
  {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode4Bit, },
  {Feature_HasLdsBarrierArriveAtomicBit, Feature_isGFX1250PlusBit, },
  {Feature_HasLdsBarrierArriveAtomicBit, Feature_isGFX1250PlusBit, Feature_HwMode0Bit, },
  {Feature_HasLdsBarrierArriveAtomicBit, Feature_isGFX1250PlusBit, Feature_HwMode1Bit, },
  {Feature_HasLdsBarrierArriveAtomicBit, Feature_isGFX1250PlusBit, Feature_HwMode2Bit, },
  {Feature_HasLdsBarrierArriveAtomicBit, Feature_isGFX1250PlusBit, Feature_HwMode3Bit, },
  {Feature_HasLdsBarrierArriveAtomicBit, Feature_isGFX1250PlusBit, Feature_HwMode4Bit, },
  {Feature_HasMADIntraFwdBugBit, Feature_isGFX11OnlyBit, Feature_HwMode0Bit, },
  {Feature_HasMADIntraFwdBugBit, Feature_isGFX11OnlyBit, Feature_HwMode1Bit, },
  {Feature_HasMADIntraFwdBugBit, Feature_isGFX11OnlyBit, Feature_HwMode2Bit, },
  {Feature_HasMADIntraFwdBugBit, Feature_isGFX11OnlyBit, Feature_HwMode3Bit, },
  {Feature_HasMADIntraFwdBugBit, Feature_isGFX11OnlyBit, Feature_HwMode4Bit, },
  {Feature_HasMAIInstsBit, Feature_isGFX90APlusBit, Feature_HwMode0Bit, },
  {Feature_HasMAIInstsBit, Feature_isGFX90APlusBit, Feature_HwMode1Bit, },
  {Feature_HasMAIInstsBit, Feature_isGFX90APlusBit, Feature_HwMode2Bit, },
  {Feature_HasMAIInstsBit, Feature_isGFX90APlusBit, Feature_HwMode3Bit, },
  {Feature_HasMAIInstsBit, Feature_isGFX90APlusBit, Feature_HwMode4Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode0Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode1Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode2Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode3Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HwMode4Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode0Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode1Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode2Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode3Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnpackedD16VMemBit, Feature_HwMode4Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasMadMacF32InstsBit, Feature_NoFP32DenormalsBit, },
  {Feature_HasMadMixInstsBit, Feature_NoFP32DenormalsBit, },
  {Feature_HasMed3_16Bit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_HasMed3_16Bit, Feature_UseFakeTrue16InstsBit, },
  {Feature_HasMed3_16Bit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_HasNotMADIntraFwdBugBit, Feature_isGFX9PlusBit, Feature_HwMode0Bit, },
  {Feature_HasNotMADIntraFwdBugBit, Feature_isGFX9PlusBit, Feature_HwMode1Bit, },
  {Feature_HasNotMADIntraFwdBugBit, Feature_isGFX9PlusBit, Feature_HwMode2Bit, },
  {Feature_HasNotMADIntraFwdBugBit, Feature_isGFX9PlusBit, Feature_HwMode3Bit, },
  {Feature_HasNotMADIntraFwdBugBit, Feature_isGFX9PlusBit, Feature_HwMode4Bit, },
  {Feature_HasScalarStoresBit, Feature_isGFX8PlusBit, },
  {Feature_HasTanhInstsBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_HasTanhInstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isWave32Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, Feature_HwMode0Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, Feature_HwMode1Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, Feature_HwMode2Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, Feature_HwMode3Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, Feature_HwMode4Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode0Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode1Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode2Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode3Bit, },
  {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, Feature_HwMode4Bit, },
  {Feature_HasVOP3PInstsBit, Feature_IEEEModeDisabledBit, },
  {Feature_HasVOP3PInstsBit, Feature_NotUseRealTrue16InstsBit, },
  {Feature_HasVOP3PInstsBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_HasVOP3PInstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasXF32InstsBit, Feature_isGFX90APlusBit, Feature_HwMode0Bit, },
  {Feature_HasXF32InstsBit, Feature_isGFX90APlusBit, Feature_HwMode1Bit, },
  {Feature_HasXF32InstsBit, Feature_isGFX90APlusBit, Feature_HwMode2Bit, },
  {Feature_HasXF32InstsBit, Feature_isGFX90APlusBit, Feature_HwMode3Bit, },
  {Feature_HasXF32InstsBit, Feature_isGFX90APlusBit, Feature_HwMode4Bit, },
  {Feature_HasXNACKEnabledBit, Feature_isGFX7OnlyBit, },
  {Feature_HasXNACKEnabledBit, Feature_isGFX9PlusBit, },
  {Feature_HasXNACKEnabledBit, Feature_isNotGFX9PlusBit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode0Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode1Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode2Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode3Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode4Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode0Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode1Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode2Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode3Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode4Bit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_isGFX10PlusBit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_isGFX125xOnlyBit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_isGFX9GFX10Bit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_isGFX9PlusBit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_isNotGFX9PlusBit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_UseRealTrue16InstsBit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode0Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode1Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode2Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode3Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode4Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode0Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode1Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode2Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode3Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, Feature_HwMode4Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode0Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode1Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode2Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode3Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, Feature_HwMode4Bit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_isGFX11PlusBit, },
  {Feature_NotUseRealTrue16InstsBit, Feature_isGFX8PlusBit, },
  {Feature_UseFakeTrue16InstsBit, Feature_isGFX10PlusBit, },
  {Feature_UseFakeTrue16InstsBit, Feature_isGFX1250PlusBit, },
  {Feature_UseFakeTrue16InstsBit, Feature_isGFX125xOnlyBit, },
  {Feature_UseFakeTrue16InstsBit, Feature_isGFX9PlusBit, },
  {Feature_UseRealTrue16InstsBit, Feature_isGFX10PlusBit, },
  {Feature_UseRealTrue16InstsBit, Feature_isGFX11PlusBit, },
  {Feature_UseRealTrue16InstsBit, Feature_isGFX1250PlusBit, },
  {Feature_UseRealTrue16InstsBit, Feature_isGFX125xOnlyBit, },
  {Feature_UseRealTrue16InstsBit, Feature_isGFX8PlusBit, },
  {Feature_UseRealTrue16InstsBit, Feature_isGFX9PlusBit, },
  {Feature_has16BankLDSBit, Feature_isNotGFX90APlusBit, },
  {Feature_has32BankLDSBit, Feature_isNotGFX90APlusBit, },
  {Feature_isGFX11OnlyBit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave64Bit, Feature_HwMode0Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave64Bit, Feature_HwMode1Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave64Bit, Feature_HwMode2Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave64Bit, Feature_HwMode3Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave64Bit, Feature_HwMode4Bit, },
  {Feature_isGFX1250PlusBit, Feature_isWave32Bit, },
  {Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_isGFX125xOnlyBit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_isGFX125xOnlyBit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_isGFX125xOnlyBit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_isGFX125xOnlyBit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_isGFX125xOnlyBit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave64Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave64Bit, Feature_HwMode0Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave64Bit, Feature_HwMode1Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave64Bit, Feature_HwMode2Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave64Bit, Feature_HwMode3Bit, },
  {Feature_isGFX12PlusNot12_50Bit, Feature_isWave64Bit, Feature_HwMode4Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX908orGFX90ABit, Feature_HwMode0Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX908orGFX90ABit, Feature_HwMode1Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX908orGFX90ABit, Feature_HwMode2Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX908orGFX90ABit, Feature_HwMode3Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX908orGFX90ABit, Feature_HwMode4Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX940PlusBit, Feature_HwMode0Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX940PlusBit, Feature_HwMode1Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX940PlusBit, Feature_HwMode2Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX940PlusBit, Feature_HwMode3Bit, },
  {Feature_isGFX90APlusBit, Feature_isGFX940PlusBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatAddressSpaceBit, Feature_UseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatAddressSpaceBit, Feature_UseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatAddressSpaceBit, Feature_UseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatAddressSpaceBit, Feature_UseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatAddressSpaceBit, Feature_UseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatGVSModeBit, Feature_UseRealTrue16InstsBit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseRealTrue16InstsBit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_NotLDSRequiresM0InitBit, Feature_UseRealTrue16InstsBit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_UseRealTrue16InstsBit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode4Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode0Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode1Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode2Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode3Bit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, Feature_HwMode4Bit, },
  {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_UseRealTrue16InstsBit, },
  {Feature_Has16BitInstsBit, Feature_HasTanhInstsBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_IEEEModeDisabledBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_IEEEModeDisabledBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_Has16BitInstsBit, Feature_IEEEModeDisabledBit, Feature_UseRealTrue16InstsBit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_isGFX10OnlyBit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_isGFX10PlusBit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_isGFX1250PlusBit, },
  {Feature_Has16BitInstsBit, Feature_has32BankLDSBit, Feature_isNotGFX90APlusBit, },
  {Feature_HasBitOp3InstsBit, Feature_UseFakeTrue16InstsBit, Feature_isGFX1250PlusBit, },
  {Feature_HasBitOp3InstsBit, Feature_UseRealTrue16InstsBit, Feature_isGFX1250PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasFP8E5M3InstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasNoCvtFP8VOP1BugBit, Feature_HasSDWABit, },
  {Feature_HasFP8ConversionInstsBit, Feature_NotHasFP8E5M3InstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_NotHasTrue16BitInstsBit, Feature_isGFX9PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_UseFakeTrue16InstsBit, Feature_isGFX9PlusBit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasFormattedMUBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode0Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode1Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode2Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode3Bit, },
  {Feature_HasMTBUFInstsBit, Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, Feature_HwMode4Bit, },
  {Feature_HasMadMacF32InstsBit, Feature_NoFP32DenormalsBit, Feature_isGFX6GFX7GFX10Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isGFX1250PlusBit, Feature_isWave32Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode0Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode1Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode2Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode3Bit, },
  {Feature_HasTransposeLoadF4F6InstsBit, Feature_isGFX1250PlusBit, Feature_isWave32Bit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode0Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode1Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode2Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode3Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode4Bit, },
  {Feature_D16PreservesUnusedBitsBit, Feature_HasFlatAddressSpaceBit, Feature_HasFlatGVSModeBit, Feature_UseRealTrue16InstsBit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_NotUseRealTrue16InstsBit, Feature_HwMode4Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseRealTrue16InstsBit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode0Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode1Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode2Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode3Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, Feature_UseTrue16WithSramECCBit, Feature_HwMode4Bit, },
  {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, Feature_UseFakeTrue16InstsBit, },
  {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, Feature_UseRealTrue16InstsBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_HasFP8E5M3InstsBit, Feature_UseFakeTrue16InstsBit, Feature_isGFX9PlusBit, },
  {Feature_HasFP8ConversionInstsBit, Feature_NotHasFP8E5M3InstsBit, Feature_NotHasTrue16BitInstsBit, Feature_isGFX9PlusBit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
  GICP_gi_buf_soffset,
  GICP_gi_ds_128bit_8byte_aligned,
  GICP_gi_ds_1addr_1offset,
  GICP_gi_ds_64bit_4byte_aligned,
  GICP_gi_flat_offset,
  GICP_gi_flat_scratch_offset,
  GICP_gi_flat_scratch_saddr,
  GICP_gi_flat_scratch_svaddr,
  GICP_gi_global_offset,
  GICP_gi_global_saddr,
  GICP_gi_global_saddr_cpol,
  GICP_gi_global_saddr_cpol_m0,
  GICP_gi_global_saddr_glc,
  GICP_gi_global_saddr_no_ioffset,
  GICP_gi_global_saddr_no_ioffset_m0,
  GICP_gi_mubuf_addr64,
  GICP_gi_mubuf_offset,
  GICP_gi_mubuf_scratch_offen,
  GICP_gi_mubuf_scratch_offset,
  GICP_gi_smrd_buffer_imm,
  GICP_gi_smrd_buffer_imm32,
  GICP_gi_smrd_buffer_sgpr_imm,
  GICP_gi_smrd_imm,
  GICP_gi_smrd_imm32,
  GICP_gi_smrd_sgpr,
  GICP_gi_smrd_sgpr_imm,
  GICP_gi_swmmacindex16,
  GICP_gi_swmmacindex32,
  GICP_gi_swmmacindex8,
  GICP_gi_vcsrc,
  GICP_gi_vinterpmods,
  GICP_gi_vinterpmods_hi,
  GICP_gi_vop3_mad_mix_mods,
  GICP_gi_vop3_mad_mix_mods_ext,
  GICP_gi_vop3_no_mods,
  GICP_gi_vop3mods,
  GICP_gi_vop3mods0,
  GICP_gi_vop3modsnoncanonicalizing,
  GICP_gi_vop3omods,
  GICP_gi_vop3opsel,
  GICP_gi_vop3opselmods,
  GICP_gi_vop3pmods,
  GICP_gi_vop3pmodsdot,
  GICP_gi_vsrc0,
  GICP_gi_wmmamods,
  GICP_gi_wmmamodsf16Neg,
  GICP_gi_wmmamodsf16NegAbs,
  GICP_gi_wmmaopselvop3pmods,
  GICP_gi_wmmavisrc,
};
// See constructor for table contents

AMDGPUInstructionSelector::ComplexMatcherMemFn
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
  &AMDGPUInstructionSelector::selectBUFSOffset, // gi_buf_soffset
  &AMDGPUInstructionSelector::selectDS128Bit8ByteAligned, // gi_ds_128bit_8byte_aligned
  &AMDGPUInstructionSelector::selectDS1Addr1Offset, // gi_ds_1addr_1offset
  &AMDGPUInstructionSelector::selectDS64Bit4ByteAligned, // gi_ds_64bit_4byte_aligned
  &AMDGPUInstructionSelector::selectFlatOffset, // gi_flat_offset
  &AMDGPUInstructionSelector::selectScratchOffset, // gi_flat_scratch_offset
  &AMDGPUInstructionSelector::selectScratchSAddr, // gi_flat_scratch_saddr
  &AMDGPUInstructionSelector::selectScratchSVAddr, // gi_flat_scratch_svaddr
  &AMDGPUInstructionSelector::selectGlobalOffset, // gi_global_offset
  &AMDGPUInstructionSelector::selectGlobalSAddr, // gi_global_saddr
  &AMDGPUInstructionSelector::selectGlobalSAddrCPol, // gi_global_saddr_cpol
  &AMDGPUInstructionSelector::selectGlobalSAddrCPolM0, // gi_global_saddr_cpol_m0
  &AMDGPUInstructionSelector::selectGlobalSAddrGLC, // gi_global_saddr_glc
  &AMDGPUInstructionSelector::selectGlobalSAddrNoIOffset, // gi_global_saddr_no_ioffset
  &AMDGPUInstructionSelector::selectGlobalSAddrNoIOffsetM0, // gi_global_saddr_no_ioffset_m0
  &AMDGPUInstructionSelector::selectMUBUFAddr64, // gi_mubuf_addr64
  &AMDGPUInstructionSelector::selectMUBUFOffset, // gi_mubuf_offset
  &AMDGPUInstructionSelector::selectMUBUFScratchOffen, // gi_mubuf_scratch_offen
  &AMDGPUInstructionSelector::selectMUBUFScratchOffset, // gi_mubuf_scratch_offset
  &AMDGPUInstructionSelector::selectSMRDBufferImm, // gi_smrd_buffer_imm
  &AMDGPUInstructionSelector::selectSMRDBufferImm32, // gi_smrd_buffer_imm32
  &AMDGPUInstructionSelector::selectSMRDBufferSgprImm, // gi_smrd_buffer_sgpr_imm
  &AMDGPUInstructionSelector::selectSmrdImm, // gi_smrd_imm
  &AMDGPUInstructionSelector::selectSmrdImm32, // gi_smrd_imm32
  &AMDGPUInstructionSelector::selectSmrdSgpr, // gi_smrd_sgpr
  &AMDGPUInstructionSelector::selectSmrdSgprImm, // gi_smrd_sgpr_imm
  &AMDGPUInstructionSelector::selectSWMMACIndex16, // gi_swmmacindex16
  &AMDGPUInstructionSelector::selectSWMMACIndex32, // gi_swmmacindex32
  &AMDGPUInstructionSelector::selectSWMMACIndex8, // gi_swmmacindex8
  &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
  &AMDGPUInstructionSelector::selectVINTERPMods, // gi_vinterpmods
  &AMDGPUInstructionSelector::selectVINTERPModsHi, // gi_vinterpmods_hi
  &AMDGPUInstructionSelector::selectVOP3PMadMixMods, // gi_vop3_mad_mix_mods
  &AMDGPUInstructionSelector::selectVOP3PMadMixModsExt, // gi_vop3_mad_mix_mods_ext
  &AMDGPUInstructionSelector::selectVOP3NoMods, // gi_vop3_no_mods
  &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
  &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
  &AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing, // gi_vop3modsnoncanonicalizing
  &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
  &AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opsel
  &AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opselmods
  &AMDGPUInstructionSelector::selectVOP3PMods, // gi_vop3pmods
  &AMDGPUInstructionSelector::selectVOP3PModsDOT, // gi_vop3pmodsdot
  &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
  &AMDGPUInstructionSelector::selectWMMAModsF32NegAbs, // gi_wmmamods
  &AMDGPUInstructionSelector::selectWMMAModsF16Neg, // gi_wmmamodsf16Neg
  &AMDGPUInstructionSelector::selectWMMAModsF16NegAbs, // gi_wmmamodsf16NegAbs
  &AMDGPUInstructionSelector::selectWMMAOpSelVOP3PMods, // gi_wmmaopselvop3pmods
  &AMDGPUInstructionSelector::selectWMMAVISrc, // gi_wmmavisrc
};

// PatFrag predicates.
enum {
  GICXXPred_MI_Predicate_aligned_smrd_load = GICXXPred_Invalid + 1,
  GICXXPred_MI_Predicate_anonymous_20748,
  GICXXPred_MI_Predicate_anonymous_20751,
  GICXXPred_MI_Predicate_anonymous_20752,
  GICXXPred_MI_Predicate_anonymous_20753,
  GICXXPred_MI_Predicate_anonymous_20754,
  GICXXPred_MI_Predicate_anonymous_20755,
  GICXXPred_MI_Predicate_anonymous_20758,
  GICXXPred_MI_Predicate_anonymous_20759,
  GICXXPred_MI_Predicate_anonymous_20760,
  GICXXPred_MI_Predicate_anonymous_20761,
  GICXXPred_MI_Predicate_anonymous_20762,
  GICXXPred_MI_Predicate_anonymous_20763,
  GICXXPred_MI_Predicate_anonymous_20764,
  GICXXPred_MI_Predicate_anonymous_20765,
  GICXXPred_MI_Predicate_anonymous_20766,
  GICXXPred_MI_Predicate_anonymous_20767,
  GICXXPred_MI_Predicate_anonymous_20768,
  GICXXPred_MI_Predicate_anonymous_20771,
  GICXXPred_MI_Predicate_anonymous_20772,
  GICXXPred_MI_Predicate_anonymous_20773,
  GICXXPred_MI_Predicate_anonymous_20774,
  GICXXPred_MI_Predicate_anonymous_20775,
  GICXXPred_MI_Predicate_anonymous_20776,
  GICXXPred_MI_Predicate_anonymous_20777,
  GICXXPred_MI_Predicate_anonymous_20778,
  GICXXPred_MI_Predicate_anonymous_20779,
  GICXXPred_MI_Predicate_anonymous_20780,
  GICXXPred_MI_Predicate_anonymous_20781,
  GICXXPred_MI_Predicate_anonymous_20782,
  GICXXPred_MI_Predicate_anonymous_20783,
  GICXXPred_MI_Predicate_anonymous_20784,
  GICXXPred_MI_Predicate_anonymous_20785,
  GICXXPred_MI_Predicate_anonymous_20786,
  GICXXPred_MI_Predicate_anonymous_20787,
  GICXXPred_MI_Predicate_anonymous_20788,
  GICXXPred_MI_Predicate_anonymous_20789,
  GICXXPred_MI_Predicate_anonymous_20790,
  GICXXPred_MI_Predicate_anonymous_20791,
  GICXXPred_MI_Predicate_anonymous_20792,
  GICXXPred_MI_Predicate_anonymous_20793,
  GICXXPred_MI_Predicate_anonymous_20794,
  GICXXPred_MI_Predicate_anonymous_20795,
  GICXXPred_MI_Predicate_anonymous_20796,
  GICXXPred_MI_Predicate_anonymous_20797,
  GICXXPred_MI_Predicate_anonymous_20798,
  GICXXPred_MI_Predicate_anonymous_20799,
  GICXXPred_MI_Predicate_anonymous_20800,
  GICXXPred_MI_Predicate_anonymous_20801,
  GICXXPred_MI_Predicate_anonymous_20802,
  GICXXPred_MI_Predicate_anonymous_20803,
  GICXXPred_MI_Predicate_anonymous_20813,
  GICXXPred_MI_Predicate_anonymous_20825,
  GICXXPred_MI_Predicate_anonymous_25402,
  GICXXPred_MI_Predicate_anonymous_26713,
  GICXXPred_MI_Predicate_anonymous_26715,
  GICXXPred_MI_Predicate_anonymous_26719,
  GICXXPred_MI_Predicate_anonymous_26721,
  GICXXPred_MI_Predicate_anonymous_27064,
  GICXXPred_MI_Predicate_anonymous_27126,
  GICXXPred_MI_Predicate_anonymous_27128,
  GICXXPred_MI_Predicate_anonymous_27130,
  GICXXPred_MI_Predicate_anonymous_27132,
  GICXXPred_MI_Predicate_anonymous_27134,
  GICXXPred_MI_Predicate_anonymous_27138,
  GICXXPred_MI_Predicate_anonymous_27140,
  GICXXPred_MI_Predicate_anonymous_27142,
  GICXXPred_MI_Predicate_anonymous_27144,
  GICXXPred_MI_Predicate_anonymous_27146,
  GICXXPred_MI_Predicate_anonymous_27412,
  GICXXPred_MI_Predicate_anonymous_27414,
  GICXXPred_MI_Predicate_anonymous_27871,
  GICXXPred_MI_Predicate_anonymous_28479,
  GICXXPred_MI_Predicate_anonymous_28482,
  GICXXPred_MI_Predicate_anonymous_28485,
  GICXXPred_MI_Predicate_anonymous_28487,
  GICXXPred_MI_Predicate_anonymous_28490,
  GICXXPred_MI_Predicate_anonymous_28492,
  GICXXPred_MI_Predicate_anonymous_28495,
  GICXXPred_MI_Predicate_anonymous_28498,
  GICXXPred_MI_Predicate_anonymous_28501,
  GICXXPred_MI_Predicate_anonymous_28505,
  GICXXPred_MI_Predicate_anonymous_28508,
  GICXXPred_MI_Predicate_anonymous_28510,
  GICXXPred_MI_Predicate_anonymous_28513,
  GICXXPred_MI_Predicate_anonymous_28516,
  GICXXPred_MI_Predicate_anonymous_28518,
  GICXXPred_MI_Predicate_anonymous_28971,
  GICXXPred_MI_Predicate_anonymous_29882,
  GICXXPred_MI_Predicate_anonymous_29885,
  GICXXPred_MI_Predicate_anonymous_29887,
  GICXXPred_MI_Predicate_anonymous_29889,
  GICXXPred_MI_Predicate_anonymous_29891,
  GICXXPred_MI_Predicate_anonymous_29893,
  GICXXPred_MI_Predicate_anonymous_29895,
  GICXXPred_MI_Predicate_anonymous_30191,
  GICXXPred_MI_Predicate_anonymous_30194,
  GICXXPred_MI_Predicate_anonymous_30197,
  GICXXPred_MI_Predicate_anonymous_30200,
  GICXXPred_MI_Predicate_anonymous_31712,
  GICXXPred_MI_Predicate_anonymous_31718,
  GICXXPred_MI_Predicate_anonymous_31722,
  GICXXPred_MI_Predicate_anonymous_31728,
  GICXXPred_MI_Predicate_anonymous_31732,
  GICXXPred_MI_Predicate_anonymous_31736,
  GICXXPred_MI_Predicate_anonymous_31740,
  GICXXPred_MI_Predicate_anonymous_31746,
  GICXXPred_MI_Predicate_anonymous_31750,
  GICXXPred_MI_Predicate_anonymous_31756,
  GICXXPred_MI_Predicate_anonymous_31762,
  GICXXPred_MI_Predicate_anonymous_31766,
  GICXXPred_MI_Predicate_anonymous_31772,
  GICXXPred_MI_Predicate_anonymous_31776,
  GICXXPred_MI_Predicate_anonymous_31780,
  GICXXPred_MI_Predicate_anonymous_31784,
  GICXXPred_MI_Predicate_anonymous_31790,
  GICXXPred_MI_Predicate_anonymous_31794,
  GICXXPred_MI_Predicate_anonymous_31800,
  GICXXPred_MI_Predicate_anonymous_31804,
  GICXXPred_MI_Predicate_anonymous_31808,
  GICXXPred_MI_Predicate_anonymous_31814,
  GICXXPred_MI_Predicate_anonymous_31818,
  GICXXPred_MI_Predicate_anonymous_31822,
  GICXXPred_MI_Predicate_anonymous_31828,
  GICXXPred_MI_Predicate_anonymous_31834,
  GICXXPred_MI_Predicate_anonymous_31838,
  GICXXPred_MI_Predicate_anonymous_31860,
  GICXXPred_MI_Predicate_anonymous_31896,
  GICXXPred_MI_Predicate_anonymous_31918,
  GICXXPred_MI_Predicate_anonymous_31958,
  GICXXPred_MI_Predicate_anonymous_31964,
  GICXXPred_MI_Predicate_anonymous_31968,
  GICXXPred_MI_Predicate_anonymous_31972,
  GICXXPred_MI_Predicate_anonymous_31976,
  GICXXPred_MI_Predicate_anonymous_31982,
  GICXXPred_MI_Predicate_anonymous_31986,
  GICXXPred_MI_Predicate_anonymous_31992,
  GICXXPred_MI_Predicate_anonymous_31996,
  GICXXPred_MI_Predicate_anonymous_32000,
  GICXXPred_MI_Predicate_anonymous_32006,
  GICXXPred_MI_Predicate_anonymous_32010,
  GICXXPred_MI_Predicate_anonymous_32014,
  GICXXPred_MI_Predicate_anonymous_32018,
  GICXXPred_MI_Predicate_anonymous_32022,
  GICXXPred_MI_Predicate_anonymous_32028,
  GICXXPred_MI_Predicate_anonymous_32032,
  GICXXPred_MI_Predicate_anonymous_32036,
  GICXXPred_MI_Predicate_anonymous_32040,
  GICXXPred_MI_Predicate_anonymous_44406,
  GICXXPred_MI_Predicate_anonymous_44477,
  GICXXPred_MI_Predicate_anonymous_44482,
  GICXXPred_MI_Predicate_anonymous_44484,
  GICXXPred_MI_Predicate_anonymous_44933,
  GICXXPred_MI_Predicate_anonymous_44935,
  GICXXPred_MI_Predicate_anonymous_44982,
  GICXXPred_MI_Predicate_anonymous_44985,
  GICXXPred_MI_Predicate_anonymous_45032,
  GICXXPred_MI_Predicate_anonymous_45033,
  GICXXPred_MI_Predicate_anonymous_45036,
  GICXXPred_MI_Predicate_anonymous_45039,
  GICXXPred_MI_Predicate_anonymous_45042,
  GICXXPred_MI_Predicate_anonymous_45046,
  GICXXPred_MI_Predicate_anonymous_45049,
  GICXXPred_MI_Predicate_anonymous_45052,
  GICXXPred_MI_Predicate_anonymous_45054,
  GICXXPred_MI_Predicate_anonymous_45055,
  GICXXPred_MI_Predicate_anonymous_45061,
  GICXXPred_MI_Predicate_anonymous_45063,
  GICXXPred_MI_Predicate_anonymous_45071,
  GICXXPred_MI_Predicate_anonymous_45076,
  GICXXPred_MI_Predicate_anonymous_45080,
  GICXXPred_MI_Predicate_anonymous_45084,
  GICXXPred_MI_Predicate_anonymous_45094,
  GICXXPred_MI_Predicate_anonymous_45280,
  GICXXPred_MI_Predicate_anonymous_45283,
  GICXXPred_MI_Predicate_anonymous_45298,
  GICXXPred_MI_Predicate_anonymous_45359,
  GICXXPred_MI_Predicate_anonymous_45361,
  GICXXPred_MI_Predicate_anonymous_45417,
  GICXXPred_MI_Predicate_anonymous_45448,
  GICXXPred_MI_Predicate_anonymous_45450,
  GICXXPred_MI_Predicate_anonymous_45479,
  GICXXPred_MI_Predicate_anonymous_45481,
  GICXXPred_MI_Predicate_anonymous_45483,
  GICXXPred_MI_Predicate_anonymous_45485,
  GICXXPred_MI_Predicate_anonymous_45487,
  GICXXPred_MI_Predicate_anonymous_45517,
  GICXXPred_MI_Predicate_anonymous_45519,
  GICXXPred_MI_Predicate_bf16_fpround,
  GICXXPred_MI_Predicate_csh_mask_16,
  GICXXPred_MI_Predicate_csh_mask_32,
  GICXXPred_MI_Predicate_csh_mask_64,
  GICXXPred_MI_Predicate_fmaxnum_like_nnan,
  GICXXPred_MI_Predicate_fminnum_like_nnan,
  GICXXPred_MI_Predicate_is_canonicalized,
  GICXXPred_MI_Predicate_load_align_less_than_4_local,
  GICXXPred_MI_Predicate_load_align_less_than_4_local_m0,
  GICXXPred_MI_Predicate_or_disjoint,
  GICXXPred_MI_Predicate_prefetch_flat,
  GICXXPred_MI_Predicate_prefetch_global,
  GICXXPred_MI_Predicate_shl_0_to_4,
  GICXXPred_MI_Predicate_smrd_extloadi8,
  GICXXPred_MI_Predicate_smrd_extloadi16,
  GICXXPred_MI_Predicate_smrd_load,
  GICXXPred_MI_Predicate_smrd_prefetch,
  GICXXPred_MI_Predicate_smrd_sextloadi8,
  GICXXPred_MI_Predicate_smrd_sextloadi16,
  GICXXPred_MI_Predicate_smrd_zextloadi8,
  GICXXPred_MI_Predicate_smrd_zextloadi16,
  GICXXPred_MI_Predicate_store_align_less_than_4_local,
  GICXXPred_MI_Predicate_store_align_less_than_4_local_m0,
};
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  const auto &Operands = State.RecordedOperands;
  (void)Operands;
  (void)MRI;
  switch (PredicateID) {
  case GICXXPred_MI_Predicate_aligned_smrd_load: {
    
      auto &Ld = cast<GLoad>(MI);
      TypeSize Size = Ld.getMMO().getSize().getValue();
      return Size <= 4 || Ld.getMMO().getAlign().value() >= Size;
      
    llvm_unreachable("aligned_smrd_load should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_20748: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20751: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20752: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20753: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20754: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20755: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20758: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20759: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20760: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20761: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20762: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20763: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20764: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20765: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20766: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20767: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20768: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20771: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20772: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20773: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20774: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20775: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20776: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20777: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20778: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20779: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20780: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20781: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20782: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20783: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20784: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20785: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20786: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20787: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20788: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20789: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20790: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20791: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20792: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20793: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20794: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20795: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20796: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20797: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20798: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20799: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20800: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20801: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20802: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20803: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20813: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_20825: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_25402: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_26713: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_26715: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_26719: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_26721: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27064: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27126: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27128: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27130: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27132: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27134: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27138: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27140: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27142: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27144: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27146: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27412: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27414: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_27871: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_28479: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28479 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28482: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28482 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28485: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28485 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28487: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28487 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28490: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28490 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28492: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28492 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28495: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28495 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28498: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28498 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28501: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28501 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28505: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28505 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28508: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28508 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28510: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28510 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28513: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28513 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28516: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28516 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28518: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28518 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_28971: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_28971 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_29882: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_29885: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_29887: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_29889: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_29891: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_29893: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_29895: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_30191: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_30191 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_30194: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_30194 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_30197: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_30197 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_30200: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_30200 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_31712: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31718: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31722: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31728: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      32);
  }
  case GICXXPred_MI_Predicate_anonymous_31732: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31736: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31740: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31746: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31750: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31756: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31762: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      32);
  }
  case GICXXPred_MI_Predicate_anonymous_31766: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31772: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      32);
  }
  case GICXXPred_MI_Predicate_anonymous_31776: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31780: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31784: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31790: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31794: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31800: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      32);
  }
  case GICXXPred_MI_Predicate_anonymous_31804: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31808: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31814: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31818: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31822: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31828: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31834: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31838: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31860: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31896: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31918: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31958: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      32);
  }
  case GICXXPred_MI_Predicate_anonymous_31964: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31968: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31972: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31976: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_31982: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      8);
  }
  case GICXXPred_MI_Predicate_anonymous_31986: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      2);
  }
  case GICXXPred_MI_Predicate_anonymous_31992: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_31996: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_32000: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_32006: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_32010: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_32014: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_32018: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_32022: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      4);
  }
  case GICXXPred_MI_Predicate_anonymous_32028: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_32032: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_32036: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_32040: {
    
        return !Subtarget->hasGFX90AInsts() ||
          MF.getInfo<SIMachineFunctionInfo>()->selectAGPRFormMFMA(
      16);
  }
  case GICXXPred_MI_Predicate_anonymous_44406: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44477: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44482: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44484: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44933: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44935: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44982: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_44985: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45032: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45033: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45036: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45039: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45042: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45046: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45049: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45052: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45054: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45055: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45061: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45063: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45071: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45076: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45080: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45084: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45094: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45280: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45283: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45298: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45359: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45361: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45417: {
    
        const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
          MF.getSubtarget().getTargetLowering());
    
        return TLI->isCanonicalized(MI.getOperand(1).getReg(), MF) &&
          TLI->isCanonicalized(MI.getOperand(2).getReg(), MF);
      
    llvm_unreachable("anonymous_45417 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_45448: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45450: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45479: {
    
        const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
          MF.getSubtarget().getTargetLowering());
    
        return TLI->isCanonicalized(MI.getOperand(1).getReg(), MF);
      
    llvm_unreachable("anonymous_45479 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_45481: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45483: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45485: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45487: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45517: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_45519: {
    return true;
  }
  case GICXXPred_MI_Predicate_bf16_fpround: {
    return false;
  }
  case GICXXPred_MI_Predicate_csh_mask_16: {
     return isUnneededShiftMask(MI, 4); 
  }
  case GICXXPred_MI_Predicate_csh_mask_32: {
     return isUnneededShiftMask(MI, 5); 
  }
  case GICXXPred_MI_Predicate_csh_mask_64: {
     return isUnneededShiftMask(MI, 6); 
  }
  case GICXXPred_MI_Predicate_fmaxnum_like_nnan: {
    
        return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI);
      
  }
  case GICXXPred_MI_Predicate_fminnum_like_nnan: {
    
        return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI);
      
  }
  case GICXXPred_MI_Predicate_is_canonicalized: {
    
        const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
            MF.getSubtarget().getTargetLowering());
        const MachineOperand &Dst = MI.getOperand(0);
        assert(Dst.isDef());
        return TLI->isCanonicalized(Dst.getReg(), MF);
       
    llvm_unreachable("is_canonicalized should have returned");
  }
  case GICXXPred_MI_Predicate_load_align_less_than_4_local: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_load_align_less_than_4_local_m0: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_or_disjoint: {
    
        return MI.getFlag(MachineInstr::Disjoint);
      
  }
  case GICXXPred_MI_Predicate_prefetch_flat: {
    
        return (*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::FLAT_ADDRESS;
      
  }
  case GICXXPred_MI_Predicate_prefetch_global: {
    
        return (*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
                ((*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
                 !Subtarget->hasSafeSmemPrefetch());
      
  }
  case GICXXPred_MI_Predicate_shl_0_to_4: {
    
        int64_t Imm = 0;
        if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) &&
            !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm))))
          return false;
        return (uint64_t)Imm <= 4;
      
    llvm_unreachable("shl_0_to_4 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_extloadi8: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_extloadi8 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_extloadi16: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_extloadi16 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_load: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_load should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_prefetch: {
    
        return isInstrUniform(MI) && Subtarget->hasSafeSmemPrefetch();
      
  }
  case GICXXPred_MI_Predicate_smrd_sextloadi8: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_sextloadi8 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_sextloadi16: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_sextloadi16 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_zextloadi8: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_zextloadi8 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_zextloadi16: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_zextloadi16 should have returned");
  }
  case GICXXPred_MI_Predicate_store_align_less_than_4_local: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_store_align_less_than_4_local_m0: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
bool AMDGPUInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
  const auto &Operands = State.RecordedOperands;
  Register Reg = MO.getReg();
  (void)Operands;
  (void)Reg;
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask = GICXXPred_Invalid + 1,
  GICXXPred_I64_Predicate_MFMALdScaleModifierOp,
  GICXXPred_I64_Predicate_NegSubInlineConst32,
  GICXXPred_I64_Predicate_NegSubInlineIntConst16,
  GICXXPred_I64_Predicate_SIMM16bit,
  GICXXPred_I64_Predicate_ShiftAmt32Imm,
  GICXXPred_I64_Predicate_SupportedRoundMode,
  GICXXPred_I64_Predicate_i32imm_one,
  GICXXPred_I64_Predicate_i32imm_zero,
  GICXXPred_I64_Predicate_i64imm_32bit,
};
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask: {
    
      return isMask_32(Imm);
    
  }
  case GICXXPred_I64_Predicate_MFMALdScaleModifierOp: {
    
      return isUInt<2>(Imm);
    
  }
  case GICXXPred_I64_Predicate_NegSubInlineConst32: {
    
      return Imm < -16 && Imm >= -64;
    
  }
  case GICXXPred_I64_Predicate_NegSubInlineIntConst16: {
    
      return Imm < -16 && Imm >= -64;
    
  }
  case GICXXPred_I64_Predicate_SIMM16bit: {
    return isInt<16>(Imm) || isUInt<16>(Imm);
  }
  case GICXXPred_I64_Predicate_ShiftAmt32Imm: {
    
      return Imm < 32;
    
  }
  case GICXXPred_I64_Predicate_SupportedRoundMode: {
    
      return Imm == (int)RoundingMode::TowardZero ||
             Imm == (int)RoundingMode::NearestTiesToEven ||
             Imm == (int)RoundingMode::TowardPositive ||
             Imm == (int)RoundingMode::TowardNegative;
    
  }
  case GICXXPred_I64_Predicate_i32imm_one: {
    
      return Imm == 1;
    
  }
  case GICXXPred_I64_Predicate_i32imm_zero: {
    
      return Imm == 0;
    
  }
  case GICXXPred_I64_Predicate_i64imm_32bit: {
    
      return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APFloat_Predicate_InlineImmFP32 = GICXXPred_Invalid + 1,
  GICXXPred_APFloat_Predicate_InlineImmFP64,
  GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64,
  GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64,
  GICXXPred_APFloat_Predicate_fpimm_pos_zero,
};
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APFloat_Predicate_InlineImmFP32: {
    
      return isInlineImmediate(Imm);
    
  }
  case GICXXPred_APFloat_Predicate_InlineImmFP64: {
    
      return isInlineImmediate(Imm);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64: {
    
        if (!Imm.isNegative())
          return false;
        int Exp = Imm.getExactLog2Abs();
        // Prefer leaving the FP inline immediates as they are.
        // 0.5, 1.0, 2.0, 4.0
    
        // For f64 ldexp is always better than materializing a 64-bit
        // constant.
        return Exp != INT_MIN && (Exp < -1 || Exp > 2);
      
    llvm_unreachable("fpimm_neg_pow2_prefer_ldexp_f64 should have returned");
  }
  case GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64: {
    
        if (Imm.isNegative())
          return false;
    
        int Exp = Imm.getExactLog2Abs();
        // Prefer leaving the FP inline immediates as they are.
        // 0.5, 1.0, 2.0, 4.0
    
        // For f64 ldexp is always better than materializing a 64-bit
        // constant.
        return Exp != INT_MIN && (Exp < -1 || Exp > 2);
      
    llvm_unreachable("fpimm_pos_pow2_prefer_ldexp_f64 should have returned");
  }
  case GICXXPred_APFloat_Predicate_fpimm_pos_zero: {
    
      return Imm.isZero() && !Imm.isNegative();
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APInt_Predicate_InlineImm64 = GICXXPred_Invalid + 1,
};
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APInt_Predicate_InlineImm64: {
    
      return isInlineImmediate(Imm);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
bool AMDGPUInstructionSelector::testSimplePredicate(unsigned) const {
    llvm_unreachable("AMDGPUInstructionSelector does not support simple predicates!");
  return false;
}
// Custom renderers.
enum {
  GICR_Invalid,
  GICR_renderBitcastFPImm32,
  GICR_renderBitcastFPImm64,
  GICR_renderDstSelToOpSel3XFormXForm,
  GICR_renderDstSelToOpSelXForm,
  GICR_renderExtractCPol,
  GICR_renderExtractCpolSetGLC,
  GICR_renderExtractSWZ,
  GICR_renderFPPow2ToExponent,
  GICR_renderFrameIndex,
  GICR_renderNegateImm,
  GICR_renderOpSelTImm,
  GICR_renderPopcntImm,
  GICR_renderPrefetchLoc,
  GICR_renderRoundMode,
  GICR_renderScaledMAIIntrinsicOperand,
  GICR_renderSrcAndDstSelToOpSelXForm_0_0,
  GICR_renderSrcAndDstSelToOpSelXForm_0_1,
  GICR_renderSrcAndDstSelToOpSelXForm_1_0,
  GICR_renderSrcAndDstSelToOpSelXForm_1_1,
  GICR_renderSrcAndDstSelToOpSelXForm_2_0,
  GICR_renderSrcSelToOpSelXForm,
  GICR_renderTruncTImm,
  GICR_renderVOP3PModsNeg,
  GICR_renderVOP3PModsNegAbs,
  GICR_renderVOP3PModsNegs,
  GICR_renderZextBoolTImm,
};
AMDGPUInstructionSelector::CustomRendererFn
AMDGPUInstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
  &AMDGPUInstructionSelector::renderBitcastFPImm32,
  &AMDGPUInstructionSelector::renderBitcastFPImm64,
  &AMDGPUInstructionSelector::renderDstSelToOpSel3XFormXForm,
  &AMDGPUInstructionSelector::renderDstSelToOpSelXForm,
  &AMDGPUInstructionSelector::renderExtractCPol,
  &AMDGPUInstructionSelector::renderExtractCpolSetGLC,
  &AMDGPUInstructionSelector::renderExtractSWZ,
  &AMDGPUInstructionSelector::renderFPPow2ToExponent,
  &AMDGPUInstructionSelector::renderFrameIndex,
  &AMDGPUInstructionSelector::renderNegateImm,
  &AMDGPUInstructionSelector::renderOpSelTImm,
  &AMDGPUInstructionSelector::renderPopcntImm,
  &AMDGPUInstructionSelector::renderPrefetchLoc,
  &AMDGPUInstructionSelector::renderRoundMode,
  &AMDGPUInstructionSelector::renderScaledMAIIntrinsicOperand,
  &AMDGPUInstructionSelector::renderSrcAndDstSelToOpSelXForm_0_0,
  &AMDGPUInstructionSelector::renderSrcAndDstSelToOpSelXForm_0_1,
  &AMDGPUInstructionSelector::renderSrcAndDstSelToOpSelXForm_1_0,
  &AMDGPUInstructionSelector::renderSrcAndDstSelToOpSelXForm_1_1,
  &AMDGPUInstructionSelector::renderSrcAndDstSelToOpSelXForm_2_0,
  &AMDGPUInstructionSelector::renderSrcSelToOpSelXForm,
  &AMDGPUInstructionSelector::renderTruncTImm,
  &AMDGPUInstructionSelector::renderVOP3PModsNeg,
  &AMDGPUInstructionSelector::renderVOP3PModsNegAbs,
  &AMDGPUInstructionSelector::renderVOP3PModsNegs,
  &AMDGPUInstructionSelector::renderZextBoolTImm,
};

bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  MachineIRBuilder B(I);
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
    return true;
  }

  return false;
}

bool AMDGPUInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
    llvm_unreachable("AMDGPUInstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24),  uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
#else
#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32),  uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
#endif
const uint8_t *AMDGPUInstructionSelector::getMatchTable() const {
  constexpr static uint8_t MatchTable0[] = {
     /*       0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(4055), /*)*//*default:*//*Label 178*/ GIMT_Encode4(2132257),
     /*      10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(16010),
     /*      14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(46681),
     /*      18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(47591), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*      46 */ /*TargetOpcode::G_AND*//*Label 3*/ GIMT_Encode4(48137),
     /*      50 */ /*TargetOpcode::G_OR*//*Label 4*/ GIMT_Encode4(50111),
     /*      54 */ /*TargetOpcode::G_XOR*//*Label 5*/ GIMT_Encode4(66390), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*      90 */ /*TargetOpcode::G_FRAME_INDEX*//*Label 6*/ GIMT_Encode4(73948), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     122 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 7*/ GIMT_Encode4(74003), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     142 */ /*TargetOpcode::G_BITCAST*//*Label 8*/ GIMT_Encode4(77607), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     154 */ /*TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND*//*Label 9*/ GIMT_Encode4(86771),
     /*     158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ GIMT_Encode4(86966), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 11*/ GIMT_Encode4(87468),
     /*     178 */ /*TargetOpcode::G_READCYCLECOUNTER*//*Label 12*/ GIMT_Encode4(87970),
     /*     182 */ /*TargetOpcode::G_READSTEADYCOUNTER*//*Label 13*/ GIMT_Encode4(88131),
     /*     186 */ /*TargetOpcode::G_LOAD*//*Label 14*/ GIMT_Encode4(88189),
     /*     190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 15*/ GIMT_Encode4(314856),
     /*     194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 16*/ GIMT_Encode4(353262), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     210 */ /*TargetOpcode::G_STORE*//*Label 17*/ GIMT_Encode4(395069), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     222 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 18*/ GIMT_Encode4(570165),
     /*     226 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 19*/ GIMT_Encode4(573451),
     /*     230 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 20*/ GIMT_Encode4(585563),
     /*     234 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 21*/ GIMT_Encode4(599175),
     /*     238 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 22*/ GIMT_Encode4(612787), GIMT_Encode4(0),
     /*     246 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 23*/ GIMT_Encode4(626399),
     /*     250 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 24*/ GIMT_Encode4(640011),
     /*     254 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 25*/ GIMT_Encode4(653623),
     /*     258 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 26*/ GIMT_Encode4(667235),
     /*     262 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 27*/ GIMT_Encode4(680847),
     /*     266 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 28*/ GIMT_Encode4(694459),
     /*     270 */ /*TargetOpcode::G_ATOMICRMW_FADD*//*Label 29*/ GIMT_Encode4(708071), GIMT_Encode4(0),
     /*     278 */ /*TargetOpcode::G_ATOMICRMW_FMAX*//*Label 30*/ GIMT_Encode4(716664),
     /*     282 */ /*TargetOpcode::G_ATOMICRMW_FMIN*//*Label 31*/ GIMT_Encode4(731190), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     294 */ /*TargetOpcode::G_ATOMICRMW_UINC_WRAP*//*Label 32*/ GIMT_Encode4(745716),
     /*     298 */ /*TargetOpcode::G_ATOMICRMW_UDEC_WRAP*//*Label 33*/ GIMT_Encode4(759328),
     /*     302 */ /*TargetOpcode::G_ATOMICRMW_USUB_COND*//*Label 34*/ GIMT_Encode4(772940),
     /*     306 */ /*TargetOpcode::G_ATOMICRMW_USUB_SAT*//*Label 35*/ GIMT_Encode4(774957),
     /*     310 */ /*TargetOpcode::G_FENCE*//*Label 36*/ GIMT_Encode4(775846),
     /*     314 */ /*TargetOpcode::G_PREFETCH*//*Label 37*/ GIMT_Encode4(775865), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     330 */ /*TargetOpcode::G_INTRINSIC*//*Label 38*/ GIMT_Encode4(777542),
     /*     334 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 39*/ GIMT_Encode4(813646),
     /*     338 */ /*TargetOpcode::G_INTRINSIC_CONVERGENT*//*Label 40*/ GIMT_Encode4(828367),
     /*     342 */ /*TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS*//*Label 41*/ GIMT_Encode4(976705),
     /*     346 */ /*TargetOpcode::G_ANYEXT*//*Label 42*/ GIMT_Encode4(988952),
     /*     350 */ /*TargetOpcode::G_TRUNC*//*Label 43*/ GIMT_Encode4(990237), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     366 */ /*TargetOpcode::G_CONSTANT*//*Label 44*/ GIMT_Encode4(991139),
     /*     370 */ /*TargetOpcode::G_FCONSTANT*//*Label 45*/ GIMT_Encode4(992374), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     382 */ /*TargetOpcode::G_SEXT*//*Label 46*/ GIMT_Encode4(992864), GIMT_Encode4(0),
     /*     390 */ /*TargetOpcode::G_ZEXT*//*Label 47*/ GIMT_Encode4(994744),
     /*     394 */ /*TargetOpcode::G_SHL*//*Label 48*/ GIMT_Encode4(998776),
     /*     398 */ /*TargetOpcode::G_LSHR*//*Label 49*/ GIMT_Encode4(1001548),
     /*     402 */ /*TargetOpcode::G_ASHR*//*Label 50*/ GIMT_Encode4(1003634), GIMT_Encode4(0),
     /*     410 */ /*TargetOpcode::G_FSHR*//*Label 51*/ GIMT_Encode4(1005720), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     422 */ /*TargetOpcode::G_ICMP*//*Label 52*/ GIMT_Encode4(1006259),
     /*     426 */ /*TargetOpcode::G_FCMP*//*Label 53*/ GIMT_Encode4(1014031), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     438 */ /*TargetOpcode::G_SELECT*//*Label 54*/ GIMT_Encode4(1034966), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     482 */ /*TargetOpcode::G_UMULH*//*Label 55*/ GIMT_Encode4(1036182),
     /*     486 */ /*TargetOpcode::G_SMULH*//*Label 56*/ GIMT_Encode4(1036291),
     /*     490 */ /*TargetOpcode::G_UADDSAT*//*Label 57*/ GIMT_Encode4(1036400),
     /*     494 */ /*TargetOpcode::G_SADDSAT*//*Label 58*/ GIMT_Encode4(1036908),
     /*     498 */ /*TargetOpcode::G_USUBSAT*//*Label 59*/ GIMT_Encode4(1037234),
     /*     502 */ /*TargetOpcode::G_SSUBSAT*//*Label 60*/ GIMT_Encode4(1037742), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     546 */ /*TargetOpcode::G_FADD*//*Label 61*/ GIMT_Encode4(1038068),
     /*     550 */ /*TargetOpcode::G_FSUB*//*Label 62*/ GIMT_Encode4(1040632),
     /*     554 */ /*TargetOpcode::G_FMUL*//*Label 63*/ GIMT_Encode4(1040996),
     /*     558 */ /*TargetOpcode::G_FMA*//*Label 64*/ GIMT_Encode4(1045374),
     /*     562 */ /*TargetOpcode::G_FMAD*//*Label 65*/ GIMT_Encode4(1048451), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     578 */ /*TargetOpcode::G_FPOW*//*Label 66*/ GIMT_Encode4(1049397), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     590 */ /*TargetOpcode::G_FEXP2*//*Label 67*/ GIMT_Encode4(1049515), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     602 */ /*TargetOpcode::G_FLOG2*//*Label 68*/ GIMT_Encode4(1049738), GIMT_Encode4(0),
     /*     610 */ /*TargetOpcode::G_FLDEXP*//*Label 69*/ GIMT_Encode4(1049961), GIMT_Encode4(0),
     /*     618 */ /*TargetOpcode::G_FNEG*//*Label 70*/ GIMT_Encode4(1050569),
     /*     622 */ /*TargetOpcode::G_FPEXT*//*Label 71*/ GIMT_Encode4(1052481),
     /*     626 */ /*TargetOpcode::G_FPTRUNC*//*Label 72*/ GIMT_Encode4(1053716),
     /*     630 */ /*TargetOpcode::G_FPTOSI*//*Label 73*/ GIMT_Encode4(1055795),
     /*     634 */ /*TargetOpcode::G_FPTOUI*//*Label 74*/ GIMT_Encode4(1057988),
     /*     638 */ /*TargetOpcode::G_SITOFP*//*Label 75*/ GIMT_Encode4(1060181),
     /*     642 */ /*TargetOpcode::G_UITOFP*//*Label 76*/ GIMT_Encode4(1062319), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     654 */ /*TargetOpcode::G_FABS*//*Label 77*/ GIMT_Encode4(1064457),
     /*     658 */ /*TargetOpcode::G_FCOPYSIGN*//*Label 78*/ GIMT_Encode4(1065206),
     /*     662 */ /*TargetOpcode::G_IS_FPCLASS*//*Label 79*/ GIMT_Encode4(1067451),
     /*     666 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 80*/ GIMT_Encode4(1068896),
     /*     670 */ /*TargetOpcode::G_FMINNUM*//*Label 81*/ GIMT_Encode4(1071328),
     /*     674 */ /*TargetOpcode::G_FMAXNUM*//*Label 82*/ GIMT_Encode4(1144051),
     /*     678 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 83*/ GIMT_Encode4(1216774),
     /*     682 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 84*/ GIMT_Encode4(1289497),
     /*     686 */ /*TargetOpcode::G_FMINIMUM*//*Label 85*/ GIMT_Encode4(1362220),
     /*     690 */ /*TargetOpcode::G_FMAXIMUM*//*Label 86*/ GIMT_Encode4(1364807),
     /*     694 */ /*TargetOpcode::G_FMINIMUMNUM*//*Label 87*/ GIMT_Encode4(1367394),
     /*     698 */ /*TargetOpcode::G_FMAXIMUMNUM*//*Label 88*/ GIMT_Encode4(1368048), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     714 */ /*TargetOpcode::G_GET_FPMODE*//*Label 89*/ GIMT_Encode4(1368702), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     734 */ /*TargetOpcode::G_PTR_ADD*//*Label 90*/ GIMT_Encode4(1368826), GIMT_Encode4(0),
     /*     742 */ /*TargetOpcode::G_SMIN*//*Label 91*/ GIMT_Encode4(1370958),
     /*     746 */ /*TargetOpcode::G_SMAX*//*Label 92*/ GIMT_Encode4(1378162),
     /*     750 */ /*TargetOpcode::G_UMIN*//*Label 93*/ GIMT_Encode4(1385534),
     /*     754 */ /*TargetOpcode::G_UMAX*//*Label 94*/ GIMT_Encode4(1392738),
     /*     758 */ /*TargetOpcode::G_ABS*//*Label 95*/ GIMT_Encode4(1399942), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     770 */ /*TargetOpcode::G_BR*//*Label 96*/ GIMT_Encode4(1400130), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     818 */ /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 97*/ GIMT_Encode4(1400164), GIMT_Encode4(0),
     /*     826 */ /*TargetOpcode::G_CTLZ_ZERO_UNDEF*//*Label 98*/ GIMT_Encode4(1400263),
     /*     830 */ /*TargetOpcode::G_CTPOP*//*Label 99*/ GIMT_Encode4(1400365),
     /*     834 */ /*TargetOpcode::G_BSWAP*//*Label 100*/ GIMT_Encode4(1400580),
     /*     838 */ /*TargetOpcode::G_BITREVERSE*//*Label 101*/ GIMT_Encode4(1402278),
     /*     842 */ /*TargetOpcode::G_FCEIL*//*Label 102*/ GIMT_Encode4(1402526), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     890 */ /*TargetOpcode::G_FSQRT*//*Label 103*/ GIMT_Encode4(1403028),
     /*     894 */ /*TargetOpcode::G_FFLOOR*//*Label 104*/ GIMT_Encode4(1403320), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     930 */ /*TargetOpcode::G_STRICT_FADD*//*Label 105*/ GIMT_Encode4(1404722),
     /*     934 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 106*/ GIMT_Encode4(1406890),
     /*     938 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 107*/ GIMT_Encode4(1407254), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     950 */ /*TargetOpcode::G_STRICT_FMA*//*Label 108*/ GIMT_Encode4(1411042), GIMT_Encode4(0),
     /*     958 */ /*TargetOpcode::G_STRICT_FLDEXP*//*Label 109*/ GIMT_Encode4(1413032), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), 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GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   15670 */ /*AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG*//*Label 110*/ GIMT_Encode4(1413640),
     /*   15674 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD*//*Label 111*/ GIMT_Encode4(1427620),
     /*   15678 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND*//*Label 112*/ GIMT_Encode4(1439524),
     /*   15682 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP*//*Label 113*/ GIMT_Encode4(1451428),
     /*   15686 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32*//*Label 114*/ GIMT_Encode4(1472858),
     /*   15690 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC*//*Label 115*/ GIMT_Encode4(1474175),
     /*   15694 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD*//*Label 116*/ GIMT_Encode4(1486079),
     /*   15698 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX*//*Label 117*/ GIMT_Encode4(1503929),
     /*   15702 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN*//*Label 118*/ GIMT_Encode4(1521753),
     /*   15706 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC*//*Label 119*/ GIMT_Encode4(1539577),
     /*   15710 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR*//*Label 120*/ GIMT_Encode4(1551481),
     /*   15714 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX*//*Label 121*/ GIMT_Encode4(1563385),
     /*   15718 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN*//*Label 122*/ GIMT_Encode4(1575289),
     /*   15722 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB*//*Label 123*/ GIMT_Encode4(1587193),
     /*   15726 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB_CLAMP_U32*//*Label 124*/ GIMT_Encode4(1599097),
     /*   15730 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP*//*Label 125*/ GIMT_Encode4(1601561),
     /*   15734 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX*//*Label 126*/ GIMT_Encode4(1619385),
     /*   15738 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN*//*Label 127*/ GIMT_Encode4(1631289),
     /*   15742 */ /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR*//*Label 128*/ GIMT_Encode4(1643193),
     /*   15746 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD*//*Label 129*/ GIMT_Encode4(1655097),
     /*   15750 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT*//*Label 130*/ GIMT_Encode4(1731569),
     /*   15754 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16*//*Label 131*/ GIMT_Encode4(1756029),
     /*   15758 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE*//*Label 132*/ GIMT_Encode4(1793918),
     /*   15762 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE*//*Label 133*/ GIMT_Encode4(1806214),
     /*   15766 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE_TFE*//*Label 134*/ GIMT_Encode4(1809024),
     /*   15770 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT*//*Label 135*/ GIMT_Encode4(1811834),
     /*   15774 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT_TFE*//*Label 136*/ GIMT_Encode4(1814644),
     /*   15778 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_TFE*//*Label 137*/ GIMT_Encode4(1817454),
     /*   15782 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE*//*Label 138*/ GIMT_Encode4(1829750),
     /*   15786 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE_TFE*//*Label 139*/ GIMT_Encode4(1832560),
     /*   15790 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT*//*Label 140*/ GIMT_Encode4(1835370),
     /*   15794 */ /*AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT_TFE*//*Label 141*/ GIMT_Encode4(1838180),
     /*   15798 */ /*AMDGPU::G_AMDGPU_BUFFER_STORE*//*Label 142*/ GIMT_Encode4(1840990),
     /*   15802 */ /*AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE*//*Label 143*/ GIMT_Encode4(1917398),
     /*   15806 */ /*AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT*//*Label 144*/ GIMT_Encode4(1920204),
     /*   15810 */ /*AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16*//*Label 145*/ GIMT_Encode4(1944648),
     /*   15814 */ /*AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT*//*Label 146*/ GIMT_Encode4(1981873), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   15830 */ /*AMDGPU::G_AMDGPU_CLAMP*//*Label 147*/ GIMT_Encode4(1984679), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   15842 */ /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE0*//*Label 148*/ GIMT_Encode4(1986776),
     /*   15846 */ /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE1*//*Label 149*/ GIMT_Encode4(1986821),
     /*   15850 */ /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE2*//*Label 150*/ GIMT_Encode4(1986866),
     /*   15854 */ /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE3*//*Label 151*/ GIMT_Encode4(1986911),
     /*   15858 */ /*AMDGPU::G_AMDGPU_CVT_PK_I16_I32*//*Label 152*/ GIMT_Encode4(1986956),
     /*   15862 */ /*AMDGPU::G_AMDGPU_FFBH_U32*//*Label 153*/ GIMT_Encode4(1986986),
     /*   15866 */ /*AMDGPU::G_AMDGPU_FFBL_B32*//*Label 154*/ GIMT_Encode4(1987088),
     /*   15870 */ /*AMDGPU::G_AMDGPU_FMAX_LEGACY*//*Label 155*/ GIMT_Encode4(1987187),
     /*   15874 */ /*AMDGPU::G_AMDGPU_FMED3*//*Label 156*/ GIMT_Encode4(1987260),
     /*   15878 */ /*AMDGPU::G_AMDGPU_FMIN_LEGACY*//*Label 157*/ GIMT_Encode4(1987620), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   15902 */ /*AMDGPU::G_AMDGPU_LOAD_D16_HI*//*Label 158*/ GIMT_Encode4(1987693),
     /*   15906 */ /*AMDGPU::G_AMDGPU_LOAD_D16_HI_I8*//*Label 159*/ GIMT_Encode4(1993337),
     /*   15910 */ /*AMDGPU::G_AMDGPU_LOAD_D16_HI_U8*//*Label 160*/ GIMT_Encode4(1998981),
     /*   15914 */ /*AMDGPU::G_AMDGPU_LOAD_D16_LO*//*Label 161*/ GIMT_Encode4(2004625),
     /*   15918 */ /*AMDGPU::G_AMDGPU_LOAD_D16_LO_I8*//*Label 162*/ GIMT_Encode4(2010269),
     /*   15922 */ /*AMDGPU::G_AMDGPU_LOAD_D16_LO_U8*//*Label 163*/ GIMT_Encode4(2015913), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   15934 */ /*AMDGPU::G_AMDGPU_RCP_IFLAG*//*Label 164*/ GIMT_Encode4(2021557), GIMT_Encode4(0),
     /*   15942 */ /*AMDGPU::G_AMDGPU_SMED3*//*Label 165*/ GIMT_Encode4(2021607),
     /*   15946 */ /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD*//*Label 166*/ GIMT_Encode4(2021913),
     /*   15950 */ /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE*//*Label 167*/ GIMT_Encode4(2024215),
     /*   15954 */ /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT*//*Label 168*/ GIMT_Encode4(2024353),
     /*   15958 */ /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE*//*Label 169*/ GIMT_Encode4(2024491),
     /*   15962 */ /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT*//*Label 170*/ GIMT_Encode4(2024629),
     /*   15966 */ /*AMDGPU::G_AMDGPU_S_BUFFER_PREFETCH*//*Label 171*/ GIMT_Encode4(2024767), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   15978 */ /*AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT*//*Label 172*/ GIMT_Encode4(2024874),
     /*   15982 */ /*AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16*//*Label 173*/ GIMT_Encode4(2052214),
     /*   15986 */ /*AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT*//*Label 174*/ GIMT_Encode4(2078523),
     /*   15990 */ /*AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16*//*Label 175*/ GIMT_Encode4(2105847),
     /*   15994 */ /*AMDGPU::G_AMDGPU_UMED3*//*Label 176*/ GIMT_Encode4(2131812), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   16006 */ /*AMDGPU::G_AMDGPU_WHOLE_WAVE_FUNC_SETUP*//*Label 177*/ GIMT_Encode4(2132118),
     /*   16010 */ // Label 0: @16010
     /*   16010 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 184*/ GIMT_Encode4(46680),
     /*   16021 */ /*GILLT_s1*//*Label 179*/ GIMT_Encode4(16041),
     /*   16025 */ /*GILLT_s16*//*Label 180*/ GIMT_Encode4(16160),
     /*   16029 */ /*GILLT_s32*//*Label 181*/ GIMT_Encode4(17151),
     /*   16033 */ /*GILLT_s64*//*Label 182*/ GIMT_Encode4(44196),
     /*   16037 */ /*GILLT_v2s16*//*Label 183*/ GIMT_Encode4(46410),
     /*   16041 */ // Label 179: @16041
     /*   16041 */ GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(16159),
     /*   16046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*   16049 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*   16052 */   GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(16080), // Rule ID 28197 //
     /*   16057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   16060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   16064 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   16068 */     // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
     /*   16068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64),
     /*   16071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   16073 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   16075 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   16078 */     GIR_RootConstrainSelectedInstOperands,
     /*   16079 */     // GIR_Coverage, 28197,
     /*   16079 */     GIR_EraseRootFromParent_Done,
     /*   16080 */   // Label 186: @16080
     /*   16080 */   GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(16108), // Rule ID 28204 //
     /*   16085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   16088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   16092 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   16096 */     // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
     /*   16096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32),
     /*   16099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   16101 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   16103 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   16106 */     GIR_RootConstrainSelectedInstOperands,
     /*   16107 */     // GIR_Coverage, 28204,
     /*   16107 */     GIR_EraseRootFromParent_Done,
     /*   16108 */   // Label 187: @16108
     /*   16108 */   GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(16133), // Rule ID 28195 //
     /*   16113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   16116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   16120 */     // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   16120 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
     /*   16125 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   16131 */     GIR_RootConstrainSelectedInstOperands,
     /*   16132 */     // GIR_Coverage, 28195,
     /*   16132 */     GIR_Done,
     /*   16133 */   // Label 188: @16133
     /*   16133 */   GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(16158), // Rule ID 28202 //
     /*   16138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   16141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   16145 */     // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   16145 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
     /*   16150 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   16156 */     GIR_RootConstrainSelectedInstOperands,
     /*   16157 */     // GIR_Coverage, 28202,
     /*   16157 */     GIR_Done,
     /*   16158 */   // Label 189: @16158
     /*   16158 */   GIM_Reject,
     /*   16159 */ // Label 185: @16159
     /*   16159 */ GIM_Reject,
     /*   16160 */ // Label 180: @16160
     /*   16160 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(17150),
     /*   16165 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   16168 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   16171 */   GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(16223), // Rule ID 27517 //
     /*   16176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   16184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   16188 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   16192 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   16196 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CTPOP),
     /*   16200 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   16204 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_44477),
     /*   16208 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   16210 */     // (add:{ *:[i16] } (trunc:{ *:[i16] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$popcnt)<<P:Predicate_anonymous_44477>>), i16:{ *:[i16] }:$val)  =>  (V_BCNT_U32_B32_e64:{ *:[i16] } ?:{ *:[i32] }:$popcnt, ?:{ *:[i16] }:$val)
     /*   16210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
     /*   16213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // popcnt
     /*   16219 */     GIR_RootToRootCopy, /*OpIdx*/2, // val
     /*   16221 */     GIR_RootConstrainSelectedInstOperands,
     /*   16222 */     // GIR_Coverage, 27517,
     /*   16222 */     GIR_EraseRootFromParent_Done,
     /*   16223 */   // Label 191: @16223
     /*   16223 */   GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(16275), // Rule ID 34050 //
     /*   16228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16232 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16236 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   16240 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   16244 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   16248 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CTPOP),
     /*   16252 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   16256 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_44477),
     /*   16260 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   16262 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$val, (trunc:{ *:[i16] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$popcnt)<<P:Predicate_anonymous_44477>>))  =>  (V_BCNT_U32_B32_e64:{ *:[i16] } ?:{ *:[i32] }:$popcnt, ?:{ *:[i16] }:$val)
     /*   16262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
     /*   16265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16267 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // popcnt
     /*   16271 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /*   16273 */     GIR_RootConstrainSelectedInstOperands,
     /*   16274 */     // GIR_Coverage, 34050,
     /*   16274 */     GIR_EraseRootFromParent_Done,
     /*   16275 */   // Label 192: @16275
     /*   16275 */   GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(16318), // Rule ID 7168 //
     /*   16280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*   16283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16287 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16291 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   16295 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
     /*   16299 */     // MIs[1] Operand 1
     /*   16299 */     // No operand predicates
     /*   16299 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16301 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)  =>  (V_SUB_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1))
     /*   16301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
     /*   16304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16306 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   16308 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   16313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16316 */     GIR_RootConstrainSelectedInstOperands,
     /*   16317 */     // GIR_Coverage, 7168,
     /*   16317 */     GIR_EraseRootFromParent_Done,
     /*   16318 */   // Label 193: @16318
     /*   16318 */   GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(16370), // Rule ID 7464 //
     /*   16323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX10Plus),
     /*   16326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   16338 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
     /*   16342 */     // MIs[1] Operand 1
     /*   16342 */     // No operand predicates
     /*   16342 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16344 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)  =>  (V_SUB_NC_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1), 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   16344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64),
     /*   16347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16352 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   16354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16357 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   16362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16368 */     GIR_RootConstrainSelectedInstOperands,
     /*   16369 */     // GIR_Coverage, 7464,
     /*   16369 */     GIR_EraseRootFromParent_Done,
     /*   16370 */   // Label 194: @16370
     /*   16370 */   GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(16422), // Rule ID 7467 //
     /*   16375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   16378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   16382 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16386 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   16390 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
     /*   16394 */     // MIs[1] Operand 1
     /*   16394 */     // No operand predicates
     /*   16394 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16396 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)  =>  (V_SUB_NC_U16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, (NegateImm:{ *:[i16 bf16 f16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1), 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   16396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_t16_e64),
     /*   16399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16404 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   16406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16409 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   16414 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16420 */     GIR_RootConstrainSelectedInstOperands,
     /*   16421 */     // GIR_Coverage, 7467,
     /*   16421 */     GIR_EraseRootFromParent_Done,
     /*   16422 */   // Label 195: @16422
     /*   16422 */   GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(16474), // Rule ID 7470 //
     /*   16427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   16430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   16442 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
     /*   16446 */     // MIs[1] Operand 1
     /*   16446 */     // No operand predicates
     /*   16446 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16448 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)  =>  (V_SUB_NC_U16_fake16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1), 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   16448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_fake16_e64),
     /*   16451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16456 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   16458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16461 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   16466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16472 */     GIR_RootConstrainSelectedInstOperands,
     /*   16473 */     // GIR_Coverage, 7470,
     /*   16473 */     GIR_EraseRootFromParent_Done,
     /*   16474 */   // Label 196: @16474
     /*   16474 */   GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(16524), // Rule ID 7231 //
     /*   16479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9),
     /*   16482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   16490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16498 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16502 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16504 */     // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
     /*   16507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16513 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16517 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   16519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16522 */     GIR_RootConstrainSelectedInstOperands,
     /*   16523 */     // GIR_Coverage, 7231,
     /*   16523 */     GIR_EraseRootFromParent_Done,
     /*   16524 */   // Label 197: @16524
     /*   16524 */   GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(16586), // Rule ID 7232 //
     /*   16529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   16532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   16536 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   16540 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16544 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16548 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16554 */     // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16_gfx9_t16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i16] }:$src1, 0:{ *:[i32] }, ?:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_gfx9_t16_e64),
     /*   16557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16562 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16569 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16576 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   16578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16584 */     GIR_RootConstrainSelectedInstOperands,
     /*   16585 */     // GIR_Coverage, 7232,
     /*   16585 */     GIR_EraseRootFromParent_Done,
     /*   16586 */   // Label 198: @16586
     /*   16586 */   GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(16648), // Rule ID 7233 //
     /*   16591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   16594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   16602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16610 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16614 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16616 */     // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16_gfx9_fake16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i16] }:$src1, 0:{ *:[i32] }, ?:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_gfx9_fake16_e64),
     /*   16619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16624 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16638 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   16640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16646 */     GIR_RootConstrainSelectedInstOperands,
     /*   16647 */     // GIR_Coverage, 7233,
     /*   16647 */     GIR_EraseRootFromParent_Done,
     /*   16648 */   // Label 199: @16648
     /*   16648 */   GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(16710), // Rule ID 7234 //
     /*   16653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Plus),
     /*   16656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   16664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16668 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16672 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16676 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16678 */     // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16_gfx9_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i16] }:$src1, 0:{ *:[i32] }, ?:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_gfx9_e64),
     /*   16681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16686 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16693 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16700 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   16702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16708 */     GIR_RootConstrainSelectedInstOperands,
     /*   16709 */     // GIR_Coverage, 7234,
     /*   16709 */     GIR_EraseRootFromParent_Done,
     /*   16710 */   // Label 200: @16710
     /*   16710 */   GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(16760), // Rule ID 31337 //
     /*   16715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9),
     /*   16718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16730 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16734 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16738 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16740 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
     /*   16743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16745 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16753 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   16755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16758 */     GIR_RootConstrainSelectedInstOperands,
     /*   16759 */     // GIR_Coverage, 31337,
     /*   16759 */     GIR_EraseRootFromParent_Done,
     /*   16760 */   // Label 201: @16760
     /*   16760 */   GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(16822), // Rule ID 31338 //
     /*   16765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   16768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   16772 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16776 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16780 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16784 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16788 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16790 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16_gfx9_t16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i16] }:$src1, 0:{ *:[i32] }, ?:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_gfx9_t16_e64),
     /*   16793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16798 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16812 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   16814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16820 */     GIR_RootConstrainSelectedInstOperands,
     /*   16821 */     // GIR_Coverage, 31338,
     /*   16821 */     GIR_EraseRootFromParent_Done,
     /*   16822 */   // Label 202: @16822
     /*   16822 */   GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(16884), // Rule ID 31339 //
     /*   16827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   16830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16838 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16842 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16846 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16850 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16852 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16_gfx9_fake16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i16] }:$src1, 0:{ *:[i32] }, ?:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_gfx9_fake16_e64),
     /*   16855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16874 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   16876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16882 */     GIR_RootConstrainSelectedInstOperands,
     /*   16883 */     // GIR_Coverage, 31339,
     /*   16883 */     GIR_EraseRootFromParent_Done,
     /*   16884 */   // Label 203: @16884
     /*   16884 */   GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(16946), // Rule ID 31340 //
     /*   16889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Plus),
     /*   16892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   16900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   16904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   16908 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   16912 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   16914 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16_gfx9_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i16] }:$src1, 0:{ *:[i32] }, ?:{ *:[i16] }:$src2, 0:{ *:[i1] })
     /*   16914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_gfx9_e64),
     /*   16917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   16926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16929 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   16933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16936 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   16938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   16944 */     GIR_RootConstrainSelectedInstOperands,
     /*   16945 */     // GIR_Coverage, 31340,
     /*   16945 */     GIR_EraseRootFromParent_Done,
     /*   16946 */   // Label 204: @16946
     /*   16946 */   GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(17005), // Rule ID 3114 //
     /*   16951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX10Plus),
     /*   16954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   16958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /*   16965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /*   16972 */     // (add:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_NC_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   16972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_e64),
     /*   16975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   16977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   16982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   16987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   16992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   16997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17003 */     GIR_RootConstrainSelectedInstOperands,
     /*   17004 */     // GIR_Coverage, 3114,
     /*   17004 */     GIR_EraseRootFromParent_Done,
     /*   17005 */   // Label 205: @17005
     /*   17005 */   GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(17064), // Rule ID 3115 //
     /*   17010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX10Plus),
     /*   17013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   17017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   17024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   17031 */     // (add:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_NC_U16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   17031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_t16_e64),
     /*   17034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   17036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   17041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   17046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   17051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   17056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17062 */     GIR_RootConstrainSelectedInstOperands,
     /*   17063 */     // GIR_Coverage, 3115,
     /*   17063 */     GIR_EraseRootFromParent_Done,
     /*   17064 */   // Label 206: @17064
     /*   17064 */   GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(17123), // Rule ID 3116 //
     /*   17069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX10Plus),
     /*   17072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   17076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   17083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   17090 */     // (add:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_NC_U16_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   17090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_fake16_e64),
     /*   17093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   17095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   17100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   17105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   17110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   17115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17121 */     GIR_RootConstrainSelectedInstOperands,
     /*   17122 */     // GIR_Coverage, 3116,
     /*   17122 */     GIR_EraseRootFromParent_Done,
     /*   17123 */   // Label 207: @17123
     /*   17123 */   GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(17149), // Rule ID 2733 //
     /*   17128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9),
     /*   17131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   17135 */     // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_ADD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   17135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64),
     /*   17138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   17140 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   17142 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   17144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17147 */     GIR_RootConstrainSelectedInstOperands,
     /*   17148 */     // GIR_Coverage, 2733,
     /*   17148 */     GIR_EraseRootFromParent_Done,
     /*   17149 */   // Label 208: @17149
     /*   17149 */   GIM_Reject,
     /*   17150 */ // Label 190: @17150
     /*   17150 */ GIM_Reject,
     /*   17151 */ // Label 181: @17151
     /*   17151 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(44195),
     /*   17156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   17159 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   17162 */   GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(17661), // Rule ID 31495 //
     /*   17167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   17170 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   17172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   17176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   17180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17184 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   17187 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17192 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   17196 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   17200 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   17202 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   17206 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17210 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   17214 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   17218 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   17222 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   17226 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17230 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   17234 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   17238 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   17242 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   17246 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   17250 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   17254 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   17258 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   17260 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   17264 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17268 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   17271 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17276 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   17280 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   17284 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   17286 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   17290 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17294 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   17298 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   17302 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   17306 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17310 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   17314 */     // MIs[7] src0
     /*   17314 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   17319 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   17323 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   17334 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   17338 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17342 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   17346 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   17350 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   17354 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17358 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   17362 */     // MIs[9] src1
     /*   17362 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   17367 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   17371 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   17382 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   17386 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   17390 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   17394 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   17398 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   17400 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   17404 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17408 */     GIM_CheckNumOperands, /*MI*/11, /*Expected*/4,
     /*   17411 */     GIM_CheckIntrinsicID, /*MI*/11, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17416 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   17420 */     GIM_CheckType, /*MI*/11, /*Op*/3, /*Type*/GILLT_s32,
     /*   17424 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   17426 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   17430 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17434 */     GIM_CheckType, /*MI*/12, /*Op*/1, /*Type*/GILLT_s32,
     /*   17438 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   17442 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/1, // MIs[13]
     /*   17446 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17450 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   17454 */     // MIs[13] src0
     /*   17454 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   17459 */     GIM_CheckConstantInt8, /*MI*/13, /*Op*/2, 8,
     /*   17463 */     GIM_CheckConstantInt, /*MI*/12, /*Op*/2, GIMT_Encode8(255),
     /*   17474 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/11, /*OpIdx*/3, // MIs[14]
     /*   17478 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17482 */     GIM_CheckType, /*MI*/14, /*Op*/1, /*Type*/GILLT_s32,
     /*   17486 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   17490 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/1, // MIs[15]
     /*   17494 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17498 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   17502 */     // MIs[15] src1
     /*   17502 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   17507 */     GIM_CheckConstantInt8, /*MI*/15, /*Op*/2, 8,
     /*   17511 */     GIM_CheckConstantInt, /*MI*/14, /*Op*/2, GIMT_Encode8(255),
     /*   17522 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/10, /*OpIdx*/2, // MIs[16]
     /*   17526 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   17530 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   17534 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   17538 */     GIM_CheckHasOneUse, /*MI*/16,
     /*   17540 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   17544 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17548 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   17551 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17556 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   17560 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   17564 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   17566 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   17570 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17574 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   17578 */     // MIs[18] src0
     /*   17578 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   17583 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   17594 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   17598 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17602 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   17606 */     // MIs[19] src1
     /*   17606 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   17611 */     GIM_CheckConstantInt, /*MI*/19, /*Op*/2, GIMT_Encode8(255),
     /*   17622 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   17624 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   17624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   17627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   17629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   17632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   17636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   17639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   17643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   17646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/16, /*OpIdx*/2, // src2
     /*   17650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   17659 */     GIR_RootConstrainSelectedInstOperands,
     /*   17660 */     // GIR_Coverage, 31495,
     /*   17660 */     GIR_EraseRootFromParent_Done,
     /*   17661 */   // Label 210: @17661
     /*   17661 */   GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(18160), // Rule ID 31494 //
     /*   17666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   17669 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   17671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   17675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   17679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17683 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   17686 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17691 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   17695 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   17699 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   17701 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   17705 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17709 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   17713 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   17717 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   17721 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   17725 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17729 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   17733 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   17737 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   17741 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   17745 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   17749 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   17753 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   17757 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   17759 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   17763 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17767 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   17770 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17775 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   17779 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   17783 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   17785 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   17789 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17793 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   17797 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   17801 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   17805 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17809 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   17813 */     // MIs[7] src0
     /*   17813 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   17818 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   17822 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   17833 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   17837 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17841 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   17845 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   17849 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   17853 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17857 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   17861 */     // MIs[9] src1
     /*   17861 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   17866 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   17870 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   17881 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   17885 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   17889 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   17893 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   17897 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   17899 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   17903 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   17907 */     GIM_CheckNumOperands, /*MI*/11, /*Expected*/4,
     /*   17910 */     GIM_CheckIntrinsicID, /*MI*/11, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   17915 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   17919 */     GIM_CheckType, /*MI*/11, /*Op*/3, /*Type*/GILLT_s32,
     /*   17923 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   17925 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   17929 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17933 */     GIM_CheckType, /*MI*/12, /*Op*/1, /*Type*/GILLT_s32,
     /*   17937 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   17941 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/1, // MIs[13]
     /*   17945 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17949 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   17953 */     // MIs[13] src0
     /*   17953 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   17958 */     GIM_CheckConstantInt8, /*MI*/13, /*Op*/2, 8,
     /*   17962 */     GIM_CheckConstantInt, /*MI*/12, /*Op*/2, GIMT_Encode8(255),
     /*   17973 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/11, /*OpIdx*/3, // MIs[14]
     /*   17977 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_AND),
     /*   17981 */     GIM_CheckType, /*MI*/14, /*Op*/1, /*Type*/GILLT_s32,
     /*   17985 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   17989 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/1, // MIs[15]
     /*   17993 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   17997 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   18001 */     // MIs[15] src1
     /*   18001 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18006 */     GIM_CheckConstantInt8, /*MI*/15, /*Op*/2, 8,
     /*   18010 */     GIM_CheckConstantInt, /*MI*/14, /*Op*/2, GIMT_Encode8(255),
     /*   18021 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/10, /*OpIdx*/2, // MIs[16]
     /*   18025 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18029 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   18033 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   18037 */     GIM_CheckHasOneUse, /*MI*/16,
     /*   18039 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/2, // MIs[17]
     /*   18043 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18047 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   18050 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18055 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   18059 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   18063 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   18065 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   18069 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18073 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   18077 */     // MIs[18] src0
     /*   18077 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   18082 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   18093 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   18097 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18101 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   18105 */     // MIs[19] src1
     /*   18105 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18110 */     GIM_CheckConstantInt, /*MI*/19, /*Op*/2, GIMT_Encode8(255),
     /*   18121 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   18123 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   18123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   18126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   18128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   18131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   18135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   18138 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   18142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   18145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/16, /*OpIdx*/1, // src2
     /*   18149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   18152 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   18155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   18158 */     GIR_RootConstrainSelectedInstOperands,
     /*   18159 */     // GIR_Coverage, 31494,
     /*   18159 */     GIR_EraseRootFromParent_Done,
     /*   18160 */   // Label 211: @18160
     /*   18160 */   GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(18659), // Rule ID 31493 //
     /*   18165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   18168 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   18170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   18174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   18178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18182 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   18185 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18190 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   18194 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   18198 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   18200 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   18204 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18208 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   18212 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   18216 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   18220 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   18224 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18228 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   18232 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   18236 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   18240 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   18244 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18248 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   18252 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   18256 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   18258 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   18262 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18266 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   18269 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18274 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   18278 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   18282 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   18284 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   18288 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18292 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   18296 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   18300 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   18304 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18308 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   18312 */     // MIs[7] src0
     /*   18312 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   18317 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   18321 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   18332 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   18336 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18340 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   18344 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   18348 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   18352 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18356 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   18360 */     // MIs[9] src1
     /*   18360 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18365 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   18369 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   18380 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   18384 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18388 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   18392 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   18396 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   18398 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   18402 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18406 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   18410 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   18414 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   18416 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   18420 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18424 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   18427 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18432 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   18436 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   18440 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   18442 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   18446 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18450 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   18454 */     // MIs[13] src0
     /*   18454 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   18459 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   18470 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   18474 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18478 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   18482 */     // MIs[14] src1
     /*   18482 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18487 */     GIM_CheckConstantInt, /*MI*/14, /*Op*/2, GIMT_Encode8(255),
     /*   18498 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/10, /*OpIdx*/2, // MIs[15]
     /*   18502 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18506 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   18509 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18514 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   18518 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   18522 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   18524 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   18528 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18532 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   18536 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   18540 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   18544 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18548 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   18552 */     // MIs[17] src0
     /*   18552 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   18557 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 8,
     /*   18561 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   18572 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   18576 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18580 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   18584 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   18588 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   18592 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18596 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   18600 */     // MIs[19] src1
     /*   18600 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18605 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 8,
     /*   18609 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   18620 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   18622 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   18622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   18625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   18627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   18630 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   18634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   18637 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   18641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   18644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/2, // src2
     /*   18648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   18651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   18654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   18657 */     GIR_RootConstrainSelectedInstOperands,
     /*   18658 */     // GIR_Coverage, 31493,
     /*   18658 */     GIR_EraseRootFromParent_Done,
     /*   18659 */   // Label 212: @18659
     /*   18659 */   GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(19158), // Rule ID 31492 //
     /*   18664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   18667 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   18669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   18673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   18677 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18681 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   18684 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18689 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   18693 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   18697 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   18699 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   18703 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18707 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   18711 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   18715 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   18719 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   18723 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18727 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   18731 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   18735 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   18739 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   18743 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18747 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   18751 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   18755 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   18757 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   18761 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18765 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   18768 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18773 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   18777 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   18781 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   18783 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   18787 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18791 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   18795 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   18799 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   18803 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18807 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   18811 */     // MIs[7] src0
     /*   18811 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   18816 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   18820 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   18831 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   18835 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18839 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   18843 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   18847 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   18851 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   18855 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   18859 */     // MIs[9] src1
     /*   18859 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18864 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   18868 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   18879 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   18883 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18887 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   18891 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   18895 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   18897 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   18901 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   18905 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   18909 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   18913 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   18915 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   18919 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   18923 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   18926 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   18931 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   18935 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   18939 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   18941 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   18945 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18949 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   18953 */     // MIs[13] src0
     /*   18953 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   18958 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   18969 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   18973 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_AND),
     /*   18977 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   18981 */     // MIs[14] src1
     /*   18981 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   18986 */     GIM_CheckConstantInt, /*MI*/14, /*Op*/2, GIMT_Encode8(255),
     /*   18997 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/10, /*OpIdx*/2, // MIs[15]
     /*   19001 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19005 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   19008 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19013 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   19017 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   19021 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   19023 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   19027 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19031 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   19035 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   19039 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   19043 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19047 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   19051 */     // MIs[17] src0
     /*   19051 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   19056 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 8,
     /*   19060 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   19071 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   19075 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19079 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   19083 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   19087 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   19091 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19095 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   19099 */     // MIs[19] src1
     /*   19099 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   19104 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 8,
     /*   19108 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   19119 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   19121 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   19121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   19124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   19126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   19129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   19133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   19136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   19140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   19143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/1, // src2
     /*   19147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   19150 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   19153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   19156 */     GIR_RootConstrainSelectedInstOperands,
     /*   19157 */     // GIR_Coverage, 31492,
     /*   19157 */     GIR_EraseRootFromParent_Done,
     /*   19158 */   // Label 213: @19158
     /*   19158 */   GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(19657), // Rule ID 31491 //
     /*   19163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   19166 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   19168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   19172 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   19176 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19180 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   19183 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   19192 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   19196 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   19198 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   19202 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19206 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   19210 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   19214 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   19218 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   19222 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19226 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   19230 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   19234 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   19238 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   19242 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   19246 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   19250 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   19254 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   19256 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   19260 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   19264 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   19268 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   19272 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   19274 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   19278 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19282 */     GIM_CheckNumOperands, /*MI*/6, /*Expected*/4,
     /*   19285 */     GIM_CheckIntrinsicID, /*MI*/6, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19290 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   19294 */     GIM_CheckType, /*MI*/6, /*Op*/3, /*Type*/GILLT_s32,
     /*   19298 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   19300 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/2, // MIs[7]
     /*   19304 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19308 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   19312 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   19316 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   19320 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19324 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   19328 */     // MIs[8] src0
     /*   19328 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   19333 */     GIM_CheckConstantInt8, /*MI*/8, /*Op*/2, 8,
     /*   19337 */     GIM_CheckConstantInt, /*MI*/7, /*Op*/2, GIMT_Encode8(255),
     /*   19348 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/6, /*OpIdx*/3, // MIs[9]
     /*   19352 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19356 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   19360 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   19364 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   19368 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19372 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   19376 */     // MIs[10] src1
     /*   19376 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   19381 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   19385 */     GIM_CheckConstantInt, /*MI*/9, /*Op*/2, GIMT_Encode8(255),
     /*   19396 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/5, /*OpIdx*/2, // MIs[11]
     /*   19400 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   19404 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   19408 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   19412 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   19414 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   19418 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19422 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   19425 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19430 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   19434 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   19438 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   19440 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   19444 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19448 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   19452 */     // MIs[13] src0
     /*   19452 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   19457 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   19468 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   19472 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19476 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   19480 */     // MIs[14] src1
     /*   19480 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   19485 */     GIM_CheckConstantInt, /*MI*/14, /*Op*/2, GIMT_Encode8(255),
     /*   19496 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   19500 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19504 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   19507 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19512 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   19516 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   19520 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   19522 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   19526 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19530 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   19534 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   19538 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   19542 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19546 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   19550 */     // MIs[17] src0
     /*   19550 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   19555 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   19559 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   19570 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   19574 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19578 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   19582 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   19586 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   19590 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19594 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   19598 */     // MIs[19] src1
     /*   19598 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   19603 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   19607 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   19618 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   19620 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   19620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   19623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   19625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   19628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   19632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   19635 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   19639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   19642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/2, // src2
     /*   19646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   19649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   19652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   19655 */     GIR_RootConstrainSelectedInstOperands,
     /*   19656 */     // GIR_Coverage, 31491,
     /*   19656 */     GIR_EraseRootFromParent_Done,
     /*   19657 */   // Label 214: @19657
     /*   19657 */   GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(20156), // Rule ID 31490 //
     /*   19662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   19665 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   19667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   19671 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   19675 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19679 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   19682 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19687 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   19691 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   19695 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   19697 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   19701 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19705 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   19709 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   19713 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   19717 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   19721 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19725 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   19729 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   19733 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   19737 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   19741 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   19745 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   19749 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   19753 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   19755 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   19759 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   19763 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   19767 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   19771 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   19773 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   19777 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19781 */     GIM_CheckNumOperands, /*MI*/6, /*Expected*/4,
     /*   19784 */     GIM_CheckIntrinsicID, /*MI*/6, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19789 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   19793 */     GIM_CheckType, /*MI*/6, /*Op*/3, /*Type*/GILLT_s32,
     /*   19797 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   19799 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/2, // MIs[7]
     /*   19803 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19807 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   19811 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   19815 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   19819 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19823 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   19827 */     // MIs[8] src0
     /*   19827 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   19832 */     GIM_CheckConstantInt8, /*MI*/8, /*Op*/2, 8,
     /*   19836 */     GIM_CheckConstantInt, /*MI*/7, /*Op*/2, GIMT_Encode8(255),
     /*   19847 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/6, /*OpIdx*/3, // MIs[9]
     /*   19851 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19855 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   19859 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   19863 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   19867 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   19871 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   19875 */     // MIs[10] src1
     /*   19875 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   19880 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   19884 */     GIM_CheckConstantInt, /*MI*/9, /*Op*/2, GIMT_Encode8(255),
     /*   19895 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/5, /*OpIdx*/2, // MIs[11]
     /*   19899 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   19903 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   19907 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   19911 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   19913 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   19917 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   19921 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   19924 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   19929 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   19933 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   19937 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   19939 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   19943 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19947 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   19951 */     // MIs[13] src0
     /*   19951 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   19956 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   19967 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   19971 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_AND),
     /*   19975 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   19979 */     // MIs[14] src1
     /*   19979 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   19984 */     GIM_CheckConstantInt, /*MI*/14, /*Op*/2, GIMT_Encode8(255),
     /*   19995 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   19999 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20003 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   20006 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20011 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   20015 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   20019 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   20021 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   20025 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20029 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   20033 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   20037 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   20041 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20045 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   20049 */     // MIs[17] src0
     /*   20049 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   20054 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   20058 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   20069 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   20073 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20077 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   20081 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   20085 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   20089 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20093 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   20097 */     // MIs[19] src1
     /*   20097 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   20102 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   20106 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   20117 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   20119 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   20119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   20122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   20124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   20127 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   20131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   20134 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   20138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   20141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/1, // src2
     /*   20145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   20148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   20151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   20154 */     GIR_RootConstrainSelectedInstOperands,
     /*   20155 */     // GIR_Coverage, 31490,
     /*   20155 */     GIR_EraseRootFromParent_Done,
     /*   20156 */   // Label 215: @20156
     /*   20156 */   GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(20655), // Rule ID 31489 //
     /*   20161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   20164 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   20166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   20170 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   20174 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20178 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   20181 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20186 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   20190 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   20194 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   20196 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   20200 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20204 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   20208 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   20212 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   20216 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   20220 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20224 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   20228 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   20232 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   20236 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   20240 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   20244 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   20248 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   20252 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   20254 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   20258 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   20262 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   20266 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   20270 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   20272 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   20276 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   20280 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   20284 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   20288 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   20290 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   20294 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20298 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   20301 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20306 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   20310 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   20314 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   20316 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   20320 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20324 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   20328 */     // MIs[8] src0
     /*   20328 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   20333 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   20344 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/7, /*OpIdx*/3, // MIs[9]
     /*   20348 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20352 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   20356 */     // MIs[9] src1
     /*   20356 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   20361 */     GIM_CheckConstantInt, /*MI*/9, /*Op*/2, GIMT_Encode8(255),
     /*   20372 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/5, /*OpIdx*/2, // MIs[10]
     /*   20376 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20380 */     GIM_CheckNumOperands, /*MI*/10, /*Expected*/4,
     /*   20383 */     GIM_CheckIntrinsicID, /*MI*/10, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20388 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   20392 */     GIM_CheckType, /*MI*/10, /*Op*/3, /*Type*/GILLT_s32,
     /*   20396 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   20398 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/2, // MIs[11]
     /*   20402 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20406 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   20410 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   20414 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   20418 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20422 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   20426 */     // MIs[12] src0
     /*   20426 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   20431 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   20435 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   20446 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/10, /*OpIdx*/3, // MIs[13]
     /*   20450 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20454 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   20458 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   20462 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   20466 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20470 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   20474 */     // MIs[14] src1
     /*   20474 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   20479 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   20483 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   20494 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   20498 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20502 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   20505 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20510 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   20514 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   20518 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   20520 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   20524 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20528 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   20532 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   20536 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   20540 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20544 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   20548 */     // MIs[17] src0
     /*   20548 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   20553 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   20557 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   20568 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   20572 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20576 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   20580 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   20584 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   20588 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20592 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   20596 */     // MIs[19] src1
     /*   20596 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   20601 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   20605 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   20616 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   20618 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   20618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   20621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   20623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   20626 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   20630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   20633 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   20637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   20640 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // src2
     /*   20644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   20647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   20650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   20653 */     GIR_RootConstrainSelectedInstOperands,
     /*   20654 */     // GIR_Coverage, 31489,
     /*   20654 */     GIR_EraseRootFromParent_Done,
     /*   20655 */   // Label 216: @20655
     /*   20655 */   GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(21154), // Rule ID 31488 //
     /*   20660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   20663 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   20665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   20669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   20673 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20677 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   20680 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20685 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   20689 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   20693 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   20695 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   20699 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20703 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   20707 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   20711 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   20715 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   20719 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20723 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   20727 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   20731 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   20735 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   20739 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   20743 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   20747 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   20751 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   20753 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   20757 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   20761 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   20765 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   20769 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   20771 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   20775 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   20779 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   20783 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   20787 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   20789 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/2, // MIs[7]
     /*   20793 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20797 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   20800 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20805 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   20809 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   20813 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   20815 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   20819 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20823 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   20827 */     // MIs[8] src0
     /*   20827 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   20832 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   20843 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/7, /*OpIdx*/3, // MIs[9]
     /*   20847 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20851 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   20855 */     // MIs[9] src1
     /*   20855 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   20860 */     GIM_CheckConstantInt, /*MI*/9, /*Op*/2, GIMT_Encode8(255),
     /*   20871 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/5, /*OpIdx*/2, // MIs[10]
     /*   20875 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   20879 */     GIM_CheckNumOperands, /*MI*/10, /*Expected*/4,
     /*   20882 */     GIM_CheckIntrinsicID, /*MI*/10, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   20887 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   20891 */     GIM_CheckType, /*MI*/10, /*Op*/3, /*Type*/GILLT_s32,
     /*   20895 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   20897 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/2, // MIs[11]
     /*   20901 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20905 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   20909 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   20913 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   20917 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20921 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   20925 */     // MIs[12] src0
     /*   20925 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   20930 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   20934 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   20945 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/10, /*OpIdx*/3, // MIs[13]
     /*   20949 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   20953 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   20957 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   20961 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   20965 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   20969 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   20973 */     // MIs[14] src1
     /*   20973 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   20978 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   20982 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   20993 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   20997 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21001 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   21004 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21009 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   21013 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   21017 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   21019 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   21023 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21027 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   21031 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   21035 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   21039 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21043 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   21047 */     // MIs[17] src0
     /*   21047 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   21052 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   21056 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   21067 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   21071 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21075 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   21079 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   21083 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   21087 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21091 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   21095 */     // MIs[19] src1
     /*   21095 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   21100 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   21104 */     GIM_CheckConstantInt, /*MI*/18, /*Op*/2, GIMT_Encode8(255),
     /*   21115 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   21117 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   21117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   21120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   21122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   21125 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   21129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   21132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   21136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   21139 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src2
     /*   21143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   21146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   21149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   21152 */     GIR_RootConstrainSelectedInstOperands,
     /*   21153 */     // GIR_Coverage, 31488,
     /*   21153 */     GIR_EraseRootFromParent_Done,
     /*   21154 */   // Label 217: @21154
     /*   21154 */   GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(21653), // Rule ID 31487 //
     /*   21159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   21162 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   21164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   21168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   21172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   21176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   21180 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   21184 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   21186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   21190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21194 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   21197 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21202 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   21206 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   21210 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   21212 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   21216 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21220 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   21224 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   21228 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   21232 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21236 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   21240 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   21244 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   21248 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
     /*   21259 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   21263 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21267 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   21271 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   21275 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   21279 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21283 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   21287 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   21291 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   21295 */     GIM_CheckConstantInt, /*MI*/5, /*Op*/2, GIMT_Encode8(255),
     /*   21306 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   21310 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   21314 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   21318 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   21322 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   21324 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   21328 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21332 */     GIM_CheckNumOperands, /*MI*/8, /*Expected*/4,
     /*   21335 */     GIM_CheckIntrinsicID, /*MI*/8, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21340 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   21344 */     GIM_CheckType, /*MI*/8, /*Op*/3, /*Type*/GILLT_s32,
     /*   21348 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   21350 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   21354 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21358 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   21362 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   21366 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   21370 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21374 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   21378 */     // MIs[10] src0
     /*   21378 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   21383 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   21387 */     GIM_CheckConstantInt, /*MI*/9, /*Op*/2, GIMT_Encode8(255),
     /*   21398 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/8, /*OpIdx*/3, // MIs[11]
     /*   21402 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21406 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   21410 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   21414 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   21418 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21422 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   21426 */     // MIs[12] src1
     /*   21426 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   21431 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   21435 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   21446 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/7, /*OpIdx*/2, // MIs[13]
     /*   21450 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   21454 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   21458 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   21462 */     GIM_CheckHasOneUse, /*MI*/13,
     /*   21464 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   21468 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21472 */     GIM_CheckNumOperands, /*MI*/14, /*Expected*/4,
     /*   21475 */     GIM_CheckIntrinsicID, /*MI*/14, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21480 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   21484 */     GIM_CheckType, /*MI*/14, /*Op*/3, /*Type*/GILLT_s32,
     /*   21488 */     GIM_CheckHasOneUse, /*MI*/14,
     /*   21490 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/2, // MIs[15]
     /*   21494 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21498 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   21502 */     // MIs[15] src0
     /*   21502 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   21507 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   21518 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/14, /*OpIdx*/3, // MIs[16]
     /*   21522 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21526 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   21530 */     // MIs[16] src1
     /*   21530 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   21535 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   21546 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   21550 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21554 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   21557 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21562 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   21566 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   21570 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   21572 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   21576 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21580 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   21584 */     // MIs[18] src0
     /*   21584 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   21589 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   21593 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   21597 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21601 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   21605 */     // MIs[19] src1
     /*   21605 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   21610 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   21614 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   21616 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   21616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   21619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   21621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   21624 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   21628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   21631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   21635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   21638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/13, /*OpIdx*/2, // src2
     /*   21642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   21645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   21648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   21651 */     GIR_RootConstrainSelectedInstOperands,
     /*   21652 */     // GIR_Coverage, 31487,
     /*   21652 */     GIR_EraseRootFromParent_Done,
     /*   21653 */   // Label 218: @21653
     /*   21653 */   GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(22152), // Rule ID 31486 //
     /*   21658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   21661 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   21663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   21667 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   21671 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   21675 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   21679 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   21683 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   21685 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   21689 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21693 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   21696 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21701 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   21705 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   21709 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   21711 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   21715 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21719 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   21723 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   21727 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   21731 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21735 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   21739 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   21743 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   21747 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
     /*   21758 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   21762 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21766 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   21770 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   21774 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   21778 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21782 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   21786 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   21790 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   21794 */     GIM_CheckConstantInt, /*MI*/5, /*Op*/2, GIMT_Encode8(255),
     /*   21805 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   21809 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   21813 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   21817 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   21821 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   21823 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   21827 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21831 */     GIM_CheckNumOperands, /*MI*/8, /*Expected*/4,
     /*   21834 */     GIM_CheckIntrinsicID, /*MI*/8, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21839 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   21843 */     GIM_CheckType, /*MI*/8, /*Op*/3, /*Type*/GILLT_s32,
     /*   21847 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   21849 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   21853 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21857 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   21861 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   21865 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   21869 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21873 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   21877 */     // MIs[10] src0
     /*   21877 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   21882 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   21886 */     GIM_CheckConstantInt, /*MI*/9, /*Op*/2, GIMT_Encode8(255),
     /*   21897 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/8, /*OpIdx*/3, // MIs[11]
     /*   21901 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21905 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   21909 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   21913 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   21917 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   21921 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   21925 */     // MIs[12] src1
     /*   21925 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   21930 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   21934 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   21945 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/7, /*OpIdx*/2, // MIs[13]
     /*   21949 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   21953 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   21957 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   21961 */     GIM_CheckHasOneUse, /*MI*/13,
     /*   21963 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/2, // MIs[14]
     /*   21967 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   21971 */     GIM_CheckNumOperands, /*MI*/14, /*Expected*/4,
     /*   21974 */     GIM_CheckIntrinsicID, /*MI*/14, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   21979 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   21983 */     GIM_CheckType, /*MI*/14, /*Op*/3, /*Type*/GILLT_s32,
     /*   21987 */     GIM_CheckHasOneUse, /*MI*/14,
     /*   21989 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/2, // MIs[15]
     /*   21993 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   21997 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   22001 */     // MIs[15] src0
     /*   22001 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22006 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   22017 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/14, /*OpIdx*/3, // MIs[16]
     /*   22021 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22025 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   22029 */     // MIs[16] src1
     /*   22029 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   22034 */     GIM_CheckConstantInt, /*MI*/16, /*Op*/2, GIMT_Encode8(255),
     /*   22045 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   22049 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22053 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   22056 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22061 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   22065 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   22069 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   22071 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   22075 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22079 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   22083 */     // MIs[18] src0
     /*   22083 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22088 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   22092 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   22096 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22100 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   22104 */     // MIs[19] src1
     /*   22104 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   22109 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   22113 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   22115 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   22115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   22118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   22120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   22123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   22127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   22130 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   22134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   22137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/13, /*OpIdx*/1, // src2
     /*   22141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   22144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   22147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   22150 */     GIR_RootConstrainSelectedInstOperands,
     /*   22151 */     // GIR_Coverage, 31486,
     /*   22151 */     GIR_EraseRootFromParent_Done,
     /*   22152 */   // Label 219: @22152
     /*   22152 */   GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(22651), // Rule ID 31485 //
     /*   22157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   22160 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   22162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   22166 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   22170 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   22174 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   22178 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   22182 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   22184 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   22188 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22192 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   22195 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22200 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   22204 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   22208 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   22210 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   22214 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22218 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   22222 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   22226 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   22230 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22234 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   22238 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   22242 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   22246 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
     /*   22257 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   22261 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22265 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   22269 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   22273 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   22277 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22281 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   22285 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   22289 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   22293 */     GIM_CheckConstantInt, /*MI*/5, /*Op*/2, GIMT_Encode8(255),
     /*   22304 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   22308 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   22312 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   22316 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   22320 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   22322 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   22326 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   22330 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   22334 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   22338 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   22340 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   22344 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22348 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   22351 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22356 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   22360 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   22364 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   22366 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   22370 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22374 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   22378 */     // MIs[10] src0
     /*   22378 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22383 */     GIM_CheckConstantInt, /*MI*/10, /*Op*/2, GIMT_Encode8(255),
     /*   22394 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   22398 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22402 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   22406 */     // MIs[11] src1
     /*   22406 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   22411 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   22422 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/7, /*OpIdx*/2, // MIs[12]
     /*   22426 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22430 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   22433 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22438 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   22442 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   22446 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   22448 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   22452 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22456 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   22460 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   22464 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   22468 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22472 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   22476 */     // MIs[14] src0
     /*   22476 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22481 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   22485 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   22496 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   22500 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22504 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   22508 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   22512 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   22516 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22520 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   22524 */     // MIs[16] src1
     /*   22524 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   22529 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 8,
     /*   22533 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   22544 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   22548 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22552 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   22555 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22560 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   22564 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   22568 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   22570 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   22574 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22578 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   22582 */     // MIs[18] src0
     /*   22582 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22587 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   22591 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   22595 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22599 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   22603 */     // MIs[19] src1
     /*   22603 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   22608 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   22612 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   22614 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   22614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   22617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   22619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   22622 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   22626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   22629 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   22633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   22636 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/2, // src2
     /*   22640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   22643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   22646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   22649 */     GIR_RootConstrainSelectedInstOperands,
     /*   22650 */     // GIR_Coverage, 31485,
     /*   22650 */     GIR_EraseRootFromParent_Done,
     /*   22651 */   // Label 220: @22651
     /*   22651 */   GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(23150), // Rule ID 31484 //
     /*   22656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   22659 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   22661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   22665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   22669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   22673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   22677 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   22681 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   22683 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   22687 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22691 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   22694 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22699 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   22703 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   22707 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   22709 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   22713 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22717 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   22721 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   22725 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   22729 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22733 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   22737 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   22741 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   22745 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
     /*   22756 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   22760 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22764 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   22768 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   22772 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   22776 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22780 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   22784 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   22788 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   22792 */     GIM_CheckConstantInt, /*MI*/5, /*Op*/2, GIMT_Encode8(255),
     /*   22803 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   22807 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   22811 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   22815 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   22819 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   22821 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   22825 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   22829 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   22833 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   22837 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   22839 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   22843 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22847 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   22850 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22855 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   22859 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   22863 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   22865 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   22869 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22873 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   22877 */     // MIs[10] src0
     /*   22877 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22882 */     GIM_CheckConstantInt, /*MI*/10, /*Op*/2, GIMT_Encode8(255),
     /*   22893 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   22897 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22901 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   22905 */     // MIs[11] src1
     /*   22905 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   22910 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   22921 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/7, /*OpIdx*/2, // MIs[12]
     /*   22925 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   22929 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   22932 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   22937 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   22941 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   22945 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   22947 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   22951 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   22955 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   22959 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   22963 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   22967 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   22971 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   22975 */     // MIs[14] src0
     /*   22975 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   22980 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   22984 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   22995 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   22999 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23003 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   23007 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   23011 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   23015 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23019 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   23023 */     // MIs[16] src1
     /*   23023 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   23028 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 8,
     /*   23032 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   23043 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   23047 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23051 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   23054 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23059 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   23063 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   23067 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   23069 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   23073 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23077 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   23081 */     // MIs[18] src0
     /*   23081 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   23086 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   23090 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   23094 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23098 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   23102 */     // MIs[19] src1
     /*   23102 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   23107 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   23111 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   23113 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   23113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   23116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   23118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   23121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   23125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   23128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   23132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   23135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/1, // src2
     /*   23139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   23142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   23145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   23148 */     GIR_RootConstrainSelectedInstOperands,
     /*   23149 */     // GIR_Coverage, 31484,
     /*   23149 */     GIR_EraseRootFromParent_Done,
     /*   23150 */   // Label 221: @23150
     /*   23150 */   GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(23649), // Rule ID 31483 //
     /*   23155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   23158 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   23160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   23164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   23168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   23172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   23176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   23180 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   23182 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   23186 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   23190 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   23194 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   23198 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   23200 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   23204 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23208 */     GIM_CheckNumOperands, /*MI*/3, /*Expected*/4,
     /*   23211 */     GIM_CheckIntrinsicID, /*MI*/3, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23216 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   23220 */     GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
     /*   23224 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   23226 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*   23230 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23234 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   23238 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   23242 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   23246 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23250 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   23254 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   23258 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/2, 8,
     /*   23262 */     GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(255),
     /*   23273 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/3, // MIs[6]
     /*   23277 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23281 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   23285 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   23289 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   23293 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23297 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   23301 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   23305 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 8,
     /*   23309 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   23320 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/2, // MIs[8]
     /*   23324 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   23328 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   23332 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   23336 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   23338 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   23342 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23346 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   23349 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23354 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   23358 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   23362 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   23364 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   23368 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23372 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   23376 */     // MIs[10] src0
     /*   23376 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   23381 */     GIM_CheckConstantInt, /*MI*/10, /*Op*/2, GIMT_Encode8(255),
     /*   23392 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   23396 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23400 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   23404 */     // MIs[11] src1
     /*   23404 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   23409 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   23420 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   23424 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23428 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   23431 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23436 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   23440 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   23444 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   23446 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   23450 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23454 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   23458 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   23462 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   23466 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23470 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   23474 */     // MIs[14] src0
     /*   23474 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   23479 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   23483 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   23494 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   23498 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23502 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   23506 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   23510 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   23514 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23518 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   23522 */     // MIs[16] src1
     /*   23522 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   23527 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   23531 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   23542 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   23546 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23550 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   23553 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23558 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   23562 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   23566 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   23568 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   23572 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23576 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   23580 */     // MIs[18] src0
     /*   23580 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   23585 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   23589 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   23593 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23597 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   23601 */     // MIs[19] src1
     /*   23601 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   23606 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   23610 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   23612 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   23612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   23615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   23617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   23620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   23624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   23627 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/7, /*OpIdx*/1, // src1
     /*   23631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   23634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/2, // src2
     /*   23638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   23641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   23644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   23647 */     GIR_RootConstrainSelectedInstOperands,
     /*   23648 */     // GIR_Coverage, 31483,
     /*   23648 */     GIR_EraseRootFromParent_Done,
     /*   23649 */   // Label 222: @23649
     /*   23649 */   GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(24148), // Rule ID 31482 //
     /*   23654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   23657 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   23659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   23663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   23667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   23671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   23675 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   23679 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   23681 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   23685 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   23689 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   23693 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   23697 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   23699 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   23703 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23707 */     GIM_CheckNumOperands, /*MI*/3, /*Expected*/4,
     /*   23710 */     GIM_CheckIntrinsicID, /*MI*/3, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23715 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   23719 */     GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
     /*   23723 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   23725 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*   23729 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23733 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   23737 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   23741 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   23745 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23749 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   23753 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   23757 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/2, 8,
     /*   23761 */     GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(255),
     /*   23772 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/3, // MIs[6]
     /*   23776 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23780 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   23784 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   23788 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   23792 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23796 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   23800 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   23804 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 8,
     /*   23808 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   23819 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/2, // MIs[8]
     /*   23823 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   23827 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   23831 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   23835 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   23837 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   23841 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23845 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   23848 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23853 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   23857 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   23861 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   23863 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   23867 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23871 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   23875 */     // MIs[10] src0
     /*   23875 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   23880 */     GIM_CheckConstantInt, /*MI*/10, /*Op*/2, GIMT_Encode8(255),
     /*   23891 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   23895 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23899 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   23903 */     // MIs[11] src1
     /*   23903 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   23908 */     GIM_CheckConstantInt, /*MI*/11, /*Op*/2, GIMT_Encode8(255),
     /*   23919 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   23923 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   23927 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   23930 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   23935 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   23939 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   23943 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   23945 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   23949 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   23953 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   23957 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   23961 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   23965 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   23969 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   23973 */     // MIs[14] src0
     /*   23973 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   23978 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   23982 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   23993 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   23997 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24001 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   24005 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   24009 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   24013 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24017 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   24021 */     // MIs[16] src1
     /*   24021 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   24026 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   24030 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   24041 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   24045 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24049 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   24052 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24057 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   24061 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   24065 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   24067 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   24071 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24075 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   24079 */     // MIs[18] src0
     /*   24079 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   24084 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   24088 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   24092 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24096 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   24100 */     // MIs[19] src1
     /*   24100 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   24105 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   24109 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   24111 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   24111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   24114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   24116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   24119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   24123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   24126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/7, /*OpIdx*/1, // src1
     /*   24130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   24133 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/1, // src2
     /*   24137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   24140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   24143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   24146 */     GIR_RootConstrainSelectedInstOperands,
     /*   24147 */     // GIR_Coverage, 31482,
     /*   24147 */     GIR_EraseRootFromParent_Done,
     /*   24148 */   // Label 223: @24148
     /*   24148 */   GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(24647), // Rule ID 31481 //
     /*   24153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   24156 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   24158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   24162 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   24166 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   24170 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   24174 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   24178 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   24180 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   24184 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   24188 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   24192 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   24196 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   24198 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   24202 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   24206 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   24210 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   24214 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   24216 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   24220 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24224 */     GIM_CheckNumOperands, /*MI*/4, /*Expected*/4,
     /*   24227 */     GIM_CheckIntrinsicID, /*MI*/4, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24232 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   24236 */     GIM_CheckType, /*MI*/4, /*Op*/3, /*Type*/GILLT_s32,
     /*   24240 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   24242 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*   24246 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24250 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   24254 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   24258 */     GIM_CheckConstantInt, /*MI*/5, /*Op*/2, GIMT_Encode8(255),
     /*   24269 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/3, // MIs[6]
     /*   24273 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24277 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   24281 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   24285 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   24296 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/2, // MIs[7]
     /*   24300 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24304 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   24307 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24312 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   24316 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   24320 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   24322 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   24326 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24330 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   24334 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   24338 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   24342 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24346 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   24350 */     // MIs[9] src0
     /*   24350 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   24355 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 8,
     /*   24359 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   24370 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/7, /*OpIdx*/3, // MIs[10]
     /*   24374 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24378 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   24382 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   24386 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   24390 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24394 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   24398 */     // MIs[11] src1
     /*   24398 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   24403 */     GIM_CheckConstantInt8, /*MI*/11, /*Op*/2, 8,
     /*   24407 */     GIM_CheckConstantInt, /*MI*/10, /*Op*/2, GIMT_Encode8(255),
     /*   24418 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   24422 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24426 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   24429 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24434 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   24438 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   24442 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   24444 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   24448 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24452 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   24456 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   24460 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   24464 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24468 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   24472 */     // MIs[14] src0
     /*   24472 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   24477 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   24481 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   24492 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   24496 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24500 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   24504 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   24508 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   24512 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24516 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   24520 */     // MIs[16] src1
     /*   24520 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   24525 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   24529 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   24540 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   24544 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24548 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   24551 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24556 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   24560 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   24564 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   24566 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   24570 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24574 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   24578 */     // MIs[18] src0
     /*   24578 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   24583 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   24587 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   24591 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24595 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   24599 */     // MIs[19] src1
     /*   24599 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   24604 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   24608 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   24610 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   24610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   24613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   24615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   24618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   24622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   24625 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   24629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   24632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // src2
     /*   24636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   24639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   24642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   24645 */     GIR_RootConstrainSelectedInstOperands,
     /*   24646 */     // GIR_Coverage, 31481,
     /*   24646 */     GIR_EraseRootFromParent_Done,
     /*   24647 */   // Label 224: @24647
     /*   24647 */   GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(25146), // Rule ID 7612 //
     /*   24652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*   24655 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   24657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   24661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   24665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   24669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   24673 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   24677 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   24679 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   24683 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   24687 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   24691 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   24695 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   24697 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   24701 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   24705 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   24709 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   24713 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   24715 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*   24719 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24723 */     GIM_CheckNumOperands, /*MI*/4, /*Expected*/4,
     /*   24726 */     GIM_CheckIntrinsicID, /*MI*/4, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24731 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   24735 */     GIM_CheckType, /*MI*/4, /*Op*/3, /*Type*/GILLT_s32,
     /*   24739 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   24741 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*   24745 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24749 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   24753 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   24757 */     GIM_CheckConstantInt, /*MI*/5, /*Op*/2, GIMT_Encode8(255),
     /*   24768 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/3, // MIs[6]
     /*   24772 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24776 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   24780 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   24784 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(255),
     /*   24795 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/2, // MIs[7]
     /*   24799 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24803 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   24806 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24811 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   24815 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   24819 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   24821 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   24825 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24829 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   24833 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   24837 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   24841 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24845 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   24849 */     // MIs[9] src0
     /*   24849 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   24854 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 8,
     /*   24858 */     GIM_CheckConstantInt, /*MI*/8, /*Op*/2, GIMT_Encode8(255),
     /*   24869 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/7, /*OpIdx*/3, // MIs[10]
     /*   24873 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24877 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   24881 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   24885 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   24889 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24893 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   24897 */     // MIs[11] src1
     /*   24897 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   24902 */     GIM_CheckConstantInt8, /*MI*/11, /*Op*/2, 8,
     /*   24906 */     GIM_CheckConstantInt, /*MI*/10, /*Op*/2, GIMT_Encode8(255),
     /*   24917 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   24921 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   24925 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   24928 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   24933 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   24937 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   24941 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   24943 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   24947 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24951 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   24955 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   24959 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   24963 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   24967 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   24971 */     // MIs[14] src0
     /*   24971 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   24976 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   24980 */     GIM_CheckConstantInt, /*MI*/13, /*Op*/2, GIMT_Encode8(255),
     /*   24991 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   24995 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_AND),
     /*   24999 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   25003 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   25007 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   25011 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25015 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   25019 */     // MIs[16] src1
     /*   25019 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   25024 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   25028 */     GIM_CheckConstantInt, /*MI*/15, /*Op*/2, GIMT_Encode8(255),
     /*   25039 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   25043 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25047 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   25050 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   25055 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   25059 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   25063 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   25065 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   25069 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25073 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   25077 */     // MIs[18] src0
     /*   25077 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   25082 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   25086 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   25090 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25094 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   25098 */     // MIs[19] src1
     /*   25098 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   25103 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   25107 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   25109 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 255:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), 255:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), 255:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_U32_U8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   25109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*   25112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   25114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   25117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   25121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   25124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   25128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   25131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
     /*   25135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   25138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   25141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   25144 */     GIR_RootConstrainSelectedInstOperands,
     /*   25145 */     // GIR_Coverage, 7612,
     /*   25145 */     GIR_EraseRootFromParent_Done,
     /*   25146 */   // Label 225: @25146
     /*   25146 */   GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(25621), // Rule ID 32775 //
     /*   25151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   25154 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   25156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   25160 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   25164 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25168 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   25171 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   25180 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   25184 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   25186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   25190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   25194 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   25198 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   25202 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   25206 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   25210 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   25214 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   25218 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   25222 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   25226 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   25230 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   25234 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   25238 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   25242 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   25244 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   25248 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25252 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   25255 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25260 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   25264 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   25268 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   25270 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   25274 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25278 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   25282 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   25286 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25290 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   25294 */     // MIs[7] src0
     /*   25294 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   25299 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   25303 */     // MIs[6] Operand 2
     /*   25303 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   25314 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   25318 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25322 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   25326 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   25330 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25334 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   25338 */     // MIs[9] src1
     /*   25338 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   25343 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   25347 */     // MIs[8] Operand 2
     /*   25347 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   25358 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   25362 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   25366 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   25370 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   25374 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   25376 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   25380 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25384 */     GIM_CheckNumOperands, /*MI*/11, /*Expected*/4,
     /*   25387 */     GIM_CheckIntrinsicID, /*MI*/11, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25392 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   25396 */     GIM_CheckType, /*MI*/11, /*Op*/3, /*Type*/GILLT_s32,
     /*   25400 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   25402 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   25406 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25410 */     GIM_CheckType, /*MI*/12, /*Op*/1, /*Type*/GILLT_s32,
     /*   25414 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/1, // MIs[13]
     /*   25418 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25422 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   25426 */     // MIs[13] src0
     /*   25426 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   25431 */     GIM_CheckConstantInt8, /*MI*/13, /*Op*/2, 8,
     /*   25435 */     // MIs[12] Operand 2
     /*   25435 */     GIM_CheckLiteralInt, /*MI*/12, /*Op*/2, GIMT_Encode8(8),
     /*   25446 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/11, /*OpIdx*/3, // MIs[14]
     /*   25450 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25454 */     GIM_CheckType, /*MI*/14, /*Op*/1, /*Type*/GILLT_s32,
     /*   25458 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/1, // MIs[15]
     /*   25462 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25466 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   25470 */     // MIs[15] src1
     /*   25470 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   25475 */     GIM_CheckConstantInt8, /*MI*/15, /*Op*/2, 8,
     /*   25479 */     // MIs[14] Operand 2
     /*   25479 */     GIM_CheckLiteralInt, /*MI*/14, /*Op*/2, GIMT_Encode8(8),
     /*   25490 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/10, /*OpIdx*/2, // MIs[16]
     /*   25494 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   25498 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   25502 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   25506 */     GIM_CheckHasOneUse, /*MI*/16,
     /*   25508 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   25512 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25516 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   25519 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25524 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   25528 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   25532 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   25534 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   25538 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25542 */     // MIs[18] src0
     /*   25542 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   25547 */     // MIs[18] Operand 2
     /*   25547 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   25558 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   25562 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25566 */     // MIs[19] src1
     /*   25566 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   25571 */     // MIs[19] Operand 2
     /*   25571 */     GIM_CheckLiteralInt, /*MI*/19, /*Op*/2, GIMT_Encode8(8),
     /*   25582 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   25584 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   25584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   25587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   25589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   25592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   25596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   25599 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   25603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   25606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/16, /*OpIdx*/2, // src2
     /*   25610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   25613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   25616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   25619 */     GIR_RootConstrainSelectedInstOperands,
     /*   25620 */     // GIR_Coverage, 32775,
     /*   25620 */     GIR_EraseRootFromParent_Done,
     /*   25621 */   // Label 226: @25621
     /*   25621 */   GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(26096), // Rule ID 32774 //
     /*   25626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   25629 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   25631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   25635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   25639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25643 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   25646 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25651 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   25655 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   25659 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   25661 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   25665 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   25669 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   25673 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   25677 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   25681 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   25685 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   25689 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   25693 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   25697 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   25701 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   25705 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   25709 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   25713 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   25717 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   25719 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   25723 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25727 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   25730 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25735 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   25739 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   25743 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   25745 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   25749 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25753 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   25757 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   25761 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25765 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   25769 */     // MIs[7] src0
     /*   25769 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   25774 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   25778 */     // MIs[6] Operand 2
     /*   25778 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   25789 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   25793 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25797 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   25801 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   25805 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25809 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   25813 */     // MIs[9] src1
     /*   25813 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   25818 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   25822 */     // MIs[8] Operand 2
     /*   25822 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   25833 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   25837 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   25841 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   25845 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   25849 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   25851 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   25855 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25859 */     GIM_CheckNumOperands, /*MI*/11, /*Expected*/4,
     /*   25862 */     GIM_CheckIntrinsicID, /*MI*/11, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25867 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   25871 */     GIM_CheckType, /*MI*/11, /*Op*/3, /*Type*/GILLT_s32,
     /*   25875 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   25877 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   25881 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25885 */     GIM_CheckType, /*MI*/12, /*Op*/1, /*Type*/GILLT_s32,
     /*   25889 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/1, // MIs[13]
     /*   25893 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25897 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   25901 */     // MIs[13] src0
     /*   25901 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   25906 */     GIM_CheckConstantInt8, /*MI*/13, /*Op*/2, 8,
     /*   25910 */     // MIs[12] Operand 2
     /*   25910 */     GIM_CheckLiteralInt, /*MI*/12, /*Op*/2, GIMT_Encode8(8),
     /*   25921 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/11, /*OpIdx*/3, // MIs[14]
     /*   25925 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   25929 */     GIM_CheckType, /*MI*/14, /*Op*/1, /*Type*/GILLT_s32,
     /*   25933 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/1, // MIs[15]
     /*   25937 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   25941 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   25945 */     // MIs[15] src1
     /*   25945 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   25950 */     GIM_CheckConstantInt8, /*MI*/15, /*Op*/2, 8,
     /*   25954 */     // MIs[14] Operand 2
     /*   25954 */     GIM_CheckLiteralInt, /*MI*/14, /*Op*/2, GIMT_Encode8(8),
     /*   25965 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/10, /*OpIdx*/2, // MIs[16]
     /*   25969 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   25973 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   25977 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   25981 */     GIM_CheckHasOneUse, /*MI*/16,
     /*   25983 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/2, // MIs[17]
     /*   25987 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   25991 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   25994 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   25999 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   26003 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   26007 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   26009 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   26013 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26017 */     // MIs[18] src0
     /*   26017 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26022 */     // MIs[18] Operand 2
     /*   26022 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   26033 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   26037 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26041 */     // MIs[19] src1
     /*   26041 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26046 */     // MIs[19] Operand 2
     /*   26046 */     GIM_CheckLiteralInt, /*MI*/19, /*Op*/2, GIMT_Encode8(8),
     /*   26057 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   26059 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   26059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   26062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   26064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   26067 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   26071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   26074 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   26078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   26081 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/16, /*OpIdx*/1, // src2
     /*   26085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   26088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   26091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   26094 */     GIR_RootConstrainSelectedInstOperands,
     /*   26095 */     // GIR_Coverage, 32774,
     /*   26095 */     GIR_EraseRootFromParent_Done,
     /*   26096 */   // Label 227: @26096
     /*   26096 */   GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(26571), // Rule ID 32773 //
     /*   26101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   26104 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   26106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   26110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   26114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26118 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   26121 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26126 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   26130 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   26134 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   26136 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   26140 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   26144 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   26148 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   26152 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   26156 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   26160 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   26164 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   26168 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   26172 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   26176 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   26180 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   26184 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   26188 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   26192 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   26194 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   26198 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26202 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   26205 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26210 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   26214 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   26218 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   26220 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   26224 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26228 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   26232 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   26236 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26240 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   26244 */     // MIs[7] src0
     /*   26244 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26249 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   26253 */     // MIs[6] Operand 2
     /*   26253 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   26264 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   26268 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26272 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   26276 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   26280 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26284 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   26288 */     // MIs[9] src1
     /*   26288 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26293 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   26297 */     // MIs[8] Operand 2
     /*   26297 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   26308 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   26312 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   26316 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   26320 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   26324 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   26326 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   26330 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   26334 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   26338 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   26342 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   26344 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   26348 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26352 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   26355 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26360 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   26364 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   26368 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   26370 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   26374 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26378 */     // MIs[13] src0
     /*   26378 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26383 */     // MIs[13] Operand 2
     /*   26383 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   26394 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   26398 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26402 */     // MIs[14] src1
     /*   26402 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26407 */     // MIs[14] Operand 2
     /*   26407 */     GIM_CheckLiteralInt, /*MI*/14, /*Op*/2, GIMT_Encode8(8),
     /*   26418 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/10, /*OpIdx*/2, // MIs[15]
     /*   26422 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26426 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   26429 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26434 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   26438 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   26442 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   26444 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   26448 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26452 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   26456 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   26460 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26464 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   26468 */     // MIs[17] src0
     /*   26468 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26473 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 8,
     /*   26477 */     // MIs[16] Operand 2
     /*   26477 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   26488 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   26492 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26496 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   26500 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   26504 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26508 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   26512 */     // MIs[19] src1
     /*   26512 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26517 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 8,
     /*   26521 */     // MIs[18] Operand 2
     /*   26521 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   26532 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   26534 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   26534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   26537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   26539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   26542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   26546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   26549 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   26553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   26556 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/2, // src2
     /*   26560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   26563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   26566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   26569 */     GIR_RootConstrainSelectedInstOperands,
     /*   26570 */     // GIR_Coverage, 32773,
     /*   26570 */     GIR_EraseRootFromParent_Done,
     /*   26571 */   // Label 228: @26571
     /*   26571 */   GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(27046), // Rule ID 32772 //
     /*   26576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   26579 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   26581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   26585 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   26589 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26593 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   26596 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26601 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   26605 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   26609 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   26611 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   26615 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   26619 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   26623 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   26627 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   26631 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   26635 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   26639 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   26643 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   26647 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   26651 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   26655 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   26659 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   26663 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   26667 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   26669 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   26673 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26677 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   26680 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26685 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   26689 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   26693 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   26695 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   26699 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26703 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   26707 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   26711 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26715 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   26719 */     // MIs[7] src0
     /*   26719 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26724 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   26728 */     // MIs[6] Operand 2
     /*   26728 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   26739 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/5, /*OpIdx*/3, // MIs[8]
     /*   26743 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26747 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   26751 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   26755 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26759 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   26763 */     // MIs[9] src1
     /*   26763 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26768 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 16,
     /*   26772 */     // MIs[8] Operand 2
     /*   26772 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   26783 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/4, /*OpIdx*/2, // MIs[10]
     /*   26787 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   26791 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   26795 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   26799 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   26801 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   26805 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   26809 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   26813 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   26817 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   26819 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   26823 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26827 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   26830 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26835 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   26839 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   26843 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   26845 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   26849 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26853 */     // MIs[13] src0
     /*   26853 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26858 */     // MIs[13] Operand 2
     /*   26858 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   26869 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   26873 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26877 */     // MIs[14] src1
     /*   26877 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26882 */     // MIs[14] Operand 2
     /*   26882 */     GIM_CheckLiteralInt, /*MI*/14, /*Op*/2, GIMT_Encode8(8),
     /*   26893 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/10, /*OpIdx*/2, // MIs[15]
     /*   26897 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   26901 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   26904 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   26909 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   26913 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   26917 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   26919 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   26923 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26927 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   26931 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   26935 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26939 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   26943 */     // MIs[17] src0
     /*   26943 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   26948 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 8,
     /*   26952 */     // MIs[16] Operand 2
     /*   26952 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   26963 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   26967 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   26971 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   26975 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   26979 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   26983 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   26987 */     // MIs[19] src1
     /*   26987 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   26992 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 8,
     /*   26996 */     // MIs[18] Operand 2
     /*   26996 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   27007 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   27009 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   27009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   27012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   27014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27017 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   27021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   27028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27031 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/1, // src2
     /*   27035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27044 */     GIR_RootConstrainSelectedInstOperands,
     /*   27045 */     // GIR_Coverage, 32772,
     /*   27045 */     GIR_EraseRootFromParent_Done,
     /*   27046 */   // Label 229: @27046
     /*   27046 */   GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(27521), // Rule ID 32771 //
     /*   27051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   27054 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   27056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   27060 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   27064 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27068 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   27071 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27076 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   27080 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   27084 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   27086 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   27090 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   27094 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   27098 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   27102 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   27106 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   27110 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   27114 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   27118 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   27122 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   27126 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   27130 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   27134 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   27138 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   27142 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   27144 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   27148 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   27152 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   27156 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   27160 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   27162 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   27166 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27170 */     GIM_CheckNumOperands, /*MI*/6, /*Expected*/4,
     /*   27173 */     GIM_CheckIntrinsicID, /*MI*/6, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27178 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   27182 */     GIM_CheckType, /*MI*/6, /*Op*/3, /*Type*/GILLT_s32,
     /*   27186 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   27188 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/2, // MIs[7]
     /*   27192 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27196 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   27200 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   27204 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27208 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   27212 */     // MIs[8] src0
     /*   27212 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   27217 */     GIM_CheckConstantInt8, /*MI*/8, /*Op*/2, 8,
     /*   27221 */     // MIs[7] Operand 2
     /*   27221 */     GIM_CheckLiteralInt, /*MI*/7, /*Op*/2, GIMT_Encode8(8),
     /*   27232 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/6, /*OpIdx*/3, // MIs[9]
     /*   27236 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27240 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   27244 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   27248 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27252 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   27256 */     // MIs[10] src1
     /*   27256 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   27261 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   27265 */     // MIs[9] Operand 2
     /*   27265 */     GIM_CheckLiteralInt, /*MI*/9, /*Op*/2, GIMT_Encode8(8),
     /*   27276 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/5, /*OpIdx*/2, // MIs[11]
     /*   27280 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   27284 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   27288 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   27292 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   27294 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   27298 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27302 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   27305 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27310 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   27314 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   27318 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   27320 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   27324 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27328 */     // MIs[13] src0
     /*   27328 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   27333 */     // MIs[13] Operand 2
     /*   27333 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   27344 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   27348 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27352 */     // MIs[14] src1
     /*   27352 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   27357 */     // MIs[14] Operand 2
     /*   27357 */     GIM_CheckLiteralInt, /*MI*/14, /*Op*/2, GIMT_Encode8(8),
     /*   27368 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   27372 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27376 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   27379 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27384 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   27388 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   27392 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   27394 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   27398 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27402 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   27406 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   27410 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27414 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   27418 */     // MIs[17] src0
     /*   27418 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   27423 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   27427 */     // MIs[16] Operand 2
     /*   27427 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   27438 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   27442 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27446 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   27450 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   27454 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27458 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   27462 */     // MIs[19] src1
     /*   27462 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   27467 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   27471 */     // MIs[18] Operand 2
     /*   27471 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   27482 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   27484 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   27484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   27487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   27489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   27496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   27503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27506 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/2, // src2
     /*   27510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27519 */     GIR_RootConstrainSelectedInstOperands,
     /*   27520 */     // GIR_Coverage, 32771,
     /*   27520 */     GIR_EraseRootFromParent_Done,
     /*   27521 */   // Label 230: @27521
     /*   27521 */   GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(27996), // Rule ID 32770 //
     /*   27526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   27529 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   27531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   27535 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   27539 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27543 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   27546 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27551 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   27555 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   27559 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   27561 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   27565 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   27569 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   27573 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   27577 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   27581 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   27585 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   27589 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   27593 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   27597 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   27601 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   27605 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   27609 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   27613 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   27617 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   27619 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   27623 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   27627 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   27631 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   27635 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   27637 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   27641 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27645 */     GIM_CheckNumOperands, /*MI*/6, /*Expected*/4,
     /*   27648 */     GIM_CheckIntrinsicID, /*MI*/6, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27653 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   27657 */     GIM_CheckType, /*MI*/6, /*Op*/3, /*Type*/GILLT_s32,
     /*   27661 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   27663 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/2, // MIs[7]
     /*   27667 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27671 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   27675 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   27679 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27683 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   27687 */     // MIs[8] src0
     /*   27687 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   27692 */     GIM_CheckConstantInt8, /*MI*/8, /*Op*/2, 8,
     /*   27696 */     // MIs[7] Operand 2
     /*   27696 */     GIM_CheckLiteralInt, /*MI*/7, /*Op*/2, GIMT_Encode8(8),
     /*   27707 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/6, /*OpIdx*/3, // MIs[9]
     /*   27711 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27715 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   27719 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   27723 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27727 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   27731 */     // MIs[10] src1
     /*   27731 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   27736 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   27740 */     // MIs[9] Operand 2
     /*   27740 */     GIM_CheckLiteralInt, /*MI*/9, /*Op*/2, GIMT_Encode8(8),
     /*   27751 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/5, /*OpIdx*/2, // MIs[11]
     /*   27755 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   27759 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   27763 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   27767 */     GIM_CheckHasOneUse, /*MI*/11,
     /*   27769 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/2, // MIs[12]
     /*   27773 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27777 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   27780 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27785 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   27789 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   27793 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   27795 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   27799 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27803 */     // MIs[13] src0
     /*   27803 */     GIM_CheckIsSameOperand, /*MI*/13, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   27808 */     // MIs[13] Operand 2
     /*   27808 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   27819 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/12, /*OpIdx*/3, // MIs[14]
     /*   27823 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27827 */     // MIs[14] src1
     /*   27827 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   27832 */     // MIs[14] Operand 2
     /*   27832 */     GIM_CheckLiteralInt, /*MI*/14, /*Op*/2, GIMT_Encode8(8),
     /*   27843 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   27847 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   27851 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   27854 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   27859 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   27863 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   27867 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   27869 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   27873 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27877 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   27881 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   27885 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27889 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   27893 */     // MIs[17] src0
     /*   27893 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   27898 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   27902 */     // MIs[16] Operand 2
     /*   27902 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   27913 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   27917 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   27921 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   27925 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   27929 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   27933 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   27937 */     // MIs[19] src1
     /*   27937 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   27942 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   27946 */     // MIs[18] Operand 2
     /*   27946 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   27957 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   27959 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   27959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   27962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   27964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   27971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   27978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   27981 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/11, /*OpIdx*/1, // src2
     /*   27985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   27994 */     GIR_RootConstrainSelectedInstOperands,
     /*   27995 */     // GIR_Coverage, 32770,
     /*   27995 */     GIR_EraseRootFromParent_Done,
     /*   27996 */   // Label 231: @27996
     /*   27996 */   GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(28471), // Rule ID 32769 //
     /*   28001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   28004 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   28006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   28010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   28014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28018 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   28021 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28026 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   28030 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   28034 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   28036 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   28040 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   28044 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   28048 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   28052 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   28056 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   28060 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   28064 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   28068 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   28072 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   28076 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   28080 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28084 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   28088 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   28092 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   28094 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   28098 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28102 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   28106 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   28110 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   28112 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   28116 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28120 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   28124 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   28128 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   28130 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   28134 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28138 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   28141 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28146 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   28150 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   28154 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   28156 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   28160 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28164 */     // MIs[8] src0
     /*   28164 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   28169 */     // MIs[8] Operand 2
     /*   28169 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   28180 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/7, /*OpIdx*/3, // MIs[9]
     /*   28184 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28188 */     // MIs[9] src1
     /*   28188 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   28193 */     // MIs[9] Operand 2
     /*   28193 */     GIM_CheckLiteralInt, /*MI*/9, /*Op*/2, GIMT_Encode8(8),
     /*   28204 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/5, /*OpIdx*/2, // MIs[10]
     /*   28208 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28212 */     GIM_CheckNumOperands, /*MI*/10, /*Expected*/4,
     /*   28215 */     GIM_CheckIntrinsicID, /*MI*/10, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28220 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   28224 */     GIM_CheckType, /*MI*/10, /*Op*/3, /*Type*/GILLT_s32,
     /*   28228 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   28230 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/2, // MIs[11]
     /*   28234 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28238 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   28242 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   28246 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28250 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   28254 */     // MIs[12] src0
     /*   28254 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   28259 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   28263 */     // MIs[11] Operand 2
     /*   28263 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   28274 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/10, /*OpIdx*/3, // MIs[13]
     /*   28278 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28282 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   28286 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   28290 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28294 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   28298 */     // MIs[14] src1
     /*   28298 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   28303 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   28307 */     // MIs[13] Operand 2
     /*   28307 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   28318 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   28322 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28326 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   28329 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28334 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   28338 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   28342 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   28344 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   28348 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28352 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   28356 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   28360 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28364 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   28368 */     // MIs[17] src0
     /*   28368 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   28373 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   28377 */     // MIs[16] Operand 2
     /*   28377 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   28388 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   28392 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28396 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   28400 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   28404 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28408 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   28412 */     // MIs[19] src1
     /*   28412 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   28417 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   28421 */     // MIs[18] Operand 2
     /*   28421 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   28432 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   28434 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   28434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   28437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   28439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   28442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   28446 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   28449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   28453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   28456 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // src2
     /*   28460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   28463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   28466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   28469 */     GIR_RootConstrainSelectedInstOperands,
     /*   28470 */     // GIR_Coverage, 32769,
     /*   28470 */     GIR_EraseRootFromParent_Done,
     /*   28471 */   // Label 232: @28471
     /*   28471 */   GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(28946), // Rule ID 32768 //
     /*   28476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   28479 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   28481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   28485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   28489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28493 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   28496 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28501 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   28505 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   28509 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   28511 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   28515 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   28519 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   28523 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   28527 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
     /*   28531 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   28535 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   28539 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   28543 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   28547 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
     /*   28551 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   28555 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28559 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   28563 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   28567 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   28569 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   28573 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28577 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   28581 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   28585 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   28587 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   28591 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28595 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   28599 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   28603 */     GIM_CheckHasOneUse, /*MI*/6,
     /*   28605 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/2, // MIs[7]
     /*   28609 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28613 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   28616 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28621 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   28625 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   28629 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   28631 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   28635 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28639 */     // MIs[8] src0
     /*   28639 */     GIM_CheckIsSameOperand, /*MI*/8, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   28644 */     // MIs[8] Operand 2
     /*   28644 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   28655 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/7, /*OpIdx*/3, // MIs[9]
     /*   28659 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28663 */     // MIs[9] src1
     /*   28663 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   28668 */     // MIs[9] Operand 2
     /*   28668 */     GIM_CheckLiteralInt, /*MI*/9, /*Op*/2, GIMT_Encode8(8),
     /*   28679 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/5, /*OpIdx*/2, // MIs[10]
     /*   28683 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28687 */     GIM_CheckNumOperands, /*MI*/10, /*Expected*/4,
     /*   28690 */     GIM_CheckIntrinsicID, /*MI*/10, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28695 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   28699 */     GIM_CheckType, /*MI*/10, /*Op*/3, /*Type*/GILLT_s32,
     /*   28703 */     GIM_CheckHasOneUse, /*MI*/10,
     /*   28705 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/2, // MIs[11]
     /*   28709 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28713 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   28717 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   28721 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28725 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   28729 */     // MIs[12] src0
     /*   28729 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   28734 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   28738 */     // MIs[11] Operand 2
     /*   28738 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   28749 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/10, /*OpIdx*/3, // MIs[13]
     /*   28753 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28757 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   28761 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   28765 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28769 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   28773 */     // MIs[14] src1
     /*   28773 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   28778 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   28782 */     // MIs[13] Operand 2
     /*   28782 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   28793 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/4, /*OpIdx*/2, // MIs[15]
     /*   28797 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28801 */     GIM_CheckNumOperands, /*MI*/15, /*Expected*/4,
     /*   28804 */     GIM_CheckIntrinsicID, /*MI*/15, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28809 */     GIM_CheckType, /*MI*/15, /*Op*/2, /*Type*/GILLT_s32,
     /*   28813 */     GIM_CheckType, /*MI*/15, /*Op*/3, /*Type*/GILLT_s32,
     /*   28817 */     GIM_CheckHasOneUse, /*MI*/15,
     /*   28819 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/2, // MIs[16]
     /*   28823 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28827 */     GIM_CheckType, /*MI*/16, /*Op*/1, /*Type*/GILLT_s32,
     /*   28831 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/16, /*OpIdx*/1, // MIs[17]
     /*   28835 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28839 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   28843 */     // MIs[17] src0
     /*   28843 */     GIM_CheckIsSameOperand, /*MI*/17, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   28848 */     GIM_CheckConstantInt8, /*MI*/17, /*Op*/2, 16,
     /*   28852 */     // MIs[16] Operand 2
     /*   28852 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   28863 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/15, /*OpIdx*/3, // MIs[18]
     /*   28867 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   28871 */     GIM_CheckType, /*MI*/18, /*Op*/1, /*Type*/GILLT_s32,
     /*   28875 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/18, /*OpIdx*/1, // MIs[19]
     /*   28879 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   28883 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   28887 */     // MIs[19] src1
     /*   28887 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   28892 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 16,
     /*   28896 */     // MIs[18] Operand 2
     /*   28896 */     GIM_CheckLiteralInt, /*MI*/18, /*Op*/2, GIMT_Encode8(8),
     /*   28907 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   28909 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   28909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   28912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   28914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   28917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   28921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   28924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   28928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   28931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src2
     /*   28935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   28938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   28941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   28944 */     GIR_RootConstrainSelectedInstOperands,
     /*   28945 */     // GIR_Coverage, 32768,
     /*   28945 */     GIR_EraseRootFromParent_Done,
     /*   28946 */   // Label 233: @28946
     /*   28946 */   GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(29421), // Rule ID 32767 //
     /*   28951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   28954 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   28956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   28960 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   28964 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   28968 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   28972 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   28976 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   28978 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   28982 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   28986 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   28989 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   28994 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   28998 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   29002 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   29004 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   29008 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29012 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   29016 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   29020 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29024 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   29028 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   29032 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   29036 */     // MIs[3] Operand 2
     /*   29036 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(8),
     /*   29047 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   29051 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29055 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   29059 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   29063 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29067 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   29071 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   29075 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   29079 */     // MIs[5] Operand 2
     /*   29079 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(8),
     /*   29090 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   29094 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   29098 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   29102 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   29106 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   29108 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   29112 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29116 */     GIM_CheckNumOperands, /*MI*/8, /*Expected*/4,
     /*   29119 */     GIM_CheckIntrinsicID, /*MI*/8, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29124 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   29128 */     GIM_CheckType, /*MI*/8, /*Op*/3, /*Type*/GILLT_s32,
     /*   29132 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   29134 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   29138 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29142 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   29146 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   29150 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29154 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   29158 */     // MIs[10] src0
     /*   29158 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   29163 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   29167 */     // MIs[9] Operand 2
     /*   29167 */     GIM_CheckLiteralInt, /*MI*/9, /*Op*/2, GIMT_Encode8(8),
     /*   29178 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/8, /*OpIdx*/3, // MIs[11]
     /*   29182 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29186 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   29190 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   29194 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29198 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   29202 */     // MIs[12] src1
     /*   29202 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   29207 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   29211 */     // MIs[11] Operand 2
     /*   29211 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   29222 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/7, /*OpIdx*/2, // MIs[13]
     /*   29226 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   29230 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   29234 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   29238 */     GIM_CheckHasOneUse, /*MI*/13,
     /*   29240 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   29244 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29248 */     GIM_CheckNumOperands, /*MI*/14, /*Expected*/4,
     /*   29251 */     GIM_CheckIntrinsicID, /*MI*/14, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29256 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   29260 */     GIM_CheckType, /*MI*/14, /*Op*/3, /*Type*/GILLT_s32,
     /*   29264 */     GIM_CheckHasOneUse, /*MI*/14,
     /*   29266 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/2, // MIs[15]
     /*   29270 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29274 */     // MIs[15] src0
     /*   29274 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   29279 */     // MIs[15] Operand 2
     /*   29279 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   29290 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/14, /*OpIdx*/3, // MIs[16]
     /*   29294 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29298 */     // MIs[16] src1
     /*   29298 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   29303 */     // MIs[16] Operand 2
     /*   29303 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   29314 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   29318 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29322 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   29325 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29330 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   29334 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   29338 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   29340 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   29344 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   29348 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   29352 */     // MIs[18] src0
     /*   29352 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   29357 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   29361 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   29365 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   29369 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   29373 */     // MIs[19] src1
     /*   29373 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   29378 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   29382 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   29384 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   29384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   29387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   29389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   29392 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   29396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   29399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   29403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   29406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/13, /*OpIdx*/2, // src2
     /*   29410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   29413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   29416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   29419 */     GIR_RootConstrainSelectedInstOperands,
     /*   29420 */     // GIR_Coverage, 32767,
     /*   29420 */     GIR_EraseRootFromParent_Done,
     /*   29421 */   // Label 234: @29421
     /*   29421 */   GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(29896), // Rule ID 32766 //
     /*   29426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   29429 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   29431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   29435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   29439 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   29443 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   29447 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   29451 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   29453 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   29457 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29461 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   29464 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29469 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   29473 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   29477 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   29479 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   29483 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29487 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   29491 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   29495 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29499 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   29503 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   29507 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   29511 */     // MIs[3] Operand 2
     /*   29511 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(8),
     /*   29522 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   29526 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29530 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   29534 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   29538 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29542 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   29546 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   29550 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   29554 */     // MIs[5] Operand 2
     /*   29554 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(8),
     /*   29565 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   29569 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   29573 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   29577 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   29581 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   29583 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   29587 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29591 */     GIM_CheckNumOperands, /*MI*/8, /*Expected*/4,
     /*   29594 */     GIM_CheckIntrinsicID, /*MI*/8, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29599 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   29603 */     GIM_CheckType, /*MI*/8, /*Op*/3, /*Type*/GILLT_s32,
     /*   29607 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   29609 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   29613 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29617 */     GIM_CheckType, /*MI*/9, /*Op*/1, /*Type*/GILLT_s32,
     /*   29621 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/1, // MIs[10]
     /*   29625 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29629 */     GIM_CheckType, /*MI*/10, /*Op*/2, /*Type*/GILLT_s32,
     /*   29633 */     // MIs[10] src0
     /*   29633 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   29638 */     GIM_CheckConstantInt8, /*MI*/10, /*Op*/2, 8,
     /*   29642 */     // MIs[9] Operand 2
     /*   29642 */     GIM_CheckLiteralInt, /*MI*/9, /*Op*/2, GIMT_Encode8(8),
     /*   29653 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/8, /*OpIdx*/3, // MIs[11]
     /*   29657 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29661 */     GIM_CheckType, /*MI*/11, /*Op*/1, /*Type*/GILLT_s32,
     /*   29665 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/11, /*OpIdx*/1, // MIs[12]
     /*   29669 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29673 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   29677 */     // MIs[12] src1
     /*   29677 */     GIM_CheckIsSameOperand, /*MI*/12, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   29682 */     GIM_CheckConstantInt8, /*MI*/12, /*Op*/2, 8,
     /*   29686 */     // MIs[11] Operand 2
     /*   29686 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   29697 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/7, /*OpIdx*/2, // MIs[13]
     /*   29701 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   29705 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   29709 */     GIM_CheckType, /*MI*/13, /*Op*/2, /*Type*/GILLT_s32,
     /*   29713 */     GIM_CheckHasOneUse, /*MI*/13,
     /*   29715 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/2, // MIs[14]
     /*   29719 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29723 */     GIM_CheckNumOperands, /*MI*/14, /*Expected*/4,
     /*   29726 */     GIM_CheckIntrinsicID, /*MI*/14, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29731 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   29735 */     GIM_CheckType, /*MI*/14, /*Op*/3, /*Type*/GILLT_s32,
     /*   29739 */     GIM_CheckHasOneUse, /*MI*/14,
     /*   29741 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/14, /*OpIdx*/2, // MIs[15]
     /*   29745 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29749 */     // MIs[15] src0
     /*   29749 */     GIM_CheckIsSameOperand, /*MI*/15, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   29754 */     // MIs[15] Operand 2
     /*   29754 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   29765 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/14, /*OpIdx*/3, // MIs[16]
     /*   29769 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29773 */     // MIs[16] src1
     /*   29773 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   29778 */     // MIs[16] Operand 2
     /*   29778 */     GIM_CheckLiteralInt, /*MI*/16, /*Op*/2, GIMT_Encode8(8),
     /*   29789 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   29793 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29797 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   29800 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29805 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   29809 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   29813 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   29815 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   29819 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   29823 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   29827 */     // MIs[18] src0
     /*   29827 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   29832 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   29836 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   29840 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   29844 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   29848 */     // MIs[19] src1
     /*   29848 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   29853 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   29857 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   29859 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   29859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   29862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   29864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   29867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   29871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   29874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   29878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   29881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/13, /*OpIdx*/1, // src2
     /*   29885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   29888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   29891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   29894 */     GIR_RootConstrainSelectedInstOperands,
     /*   29895 */     // GIR_Coverage, 32766,
     /*   29895 */     GIR_EraseRootFromParent_Done,
     /*   29896 */   // Label 235: @29896
     /*   29896 */   GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(30371), // Rule ID 32765 //
     /*   29901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   29904 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   29906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   29910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   29914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   29918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   29922 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   29926 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   29928 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   29932 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   29936 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   29939 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   29944 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   29948 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   29952 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   29954 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   29958 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   29962 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   29966 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   29970 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   29974 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   29978 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   29982 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   29986 */     // MIs[3] Operand 2
     /*   29986 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(8),
     /*   29997 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   30001 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30005 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   30009 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   30013 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30017 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   30021 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   30025 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   30029 */     // MIs[5] Operand 2
     /*   30029 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(8),
     /*   30040 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   30044 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30048 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   30052 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   30056 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   30058 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   30062 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30066 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   30070 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   30074 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   30076 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   30080 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30084 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   30087 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30092 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   30096 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   30100 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   30102 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   30106 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30110 */     // MIs[10] src0
     /*   30110 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   30115 */     // MIs[10] Operand 2
     /*   30115 */     GIM_CheckLiteralInt, /*MI*/10, /*Op*/2, GIMT_Encode8(8),
     /*   30126 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   30130 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30134 */     // MIs[11] src1
     /*   30134 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   30139 */     // MIs[11] Operand 2
     /*   30139 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   30150 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/7, /*OpIdx*/2, // MIs[12]
     /*   30154 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30158 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   30161 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30166 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   30170 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   30174 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   30176 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   30180 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30184 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   30188 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   30192 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30196 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   30200 */     // MIs[14] src0
     /*   30200 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   30205 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   30209 */     // MIs[13] Operand 2
     /*   30209 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   30220 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   30224 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30228 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   30232 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   30236 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30240 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   30244 */     // MIs[16] src1
     /*   30244 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   30249 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 8,
     /*   30253 */     // MIs[15] Operand 2
     /*   30253 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   30264 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   30268 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30272 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   30275 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30280 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   30284 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   30288 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   30290 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   30294 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   30298 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   30302 */     // MIs[18] src0
     /*   30302 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   30307 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   30311 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   30315 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   30319 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   30323 */     // MIs[19] src1
     /*   30323 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   30328 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   30332 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   30334 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   30334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   30337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   30339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   30342 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   30346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   30349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   30353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   30356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/2, // src2
     /*   30360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   30363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   30366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   30369 */     GIR_RootConstrainSelectedInstOperands,
     /*   30370 */     // GIR_Coverage, 32765,
     /*   30370 */     GIR_EraseRootFromParent_Done,
     /*   30371 */   // Label 236: @30371
     /*   30371 */   GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(30846), // Rule ID 32764 //
     /*   30376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   30379 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   30381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   30385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   30389 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30393 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   30397 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   30401 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   30403 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   30407 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30411 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   30414 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30419 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   30423 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   30427 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   30429 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   30433 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30437 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   30441 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   30445 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30449 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   30453 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   30457 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   30461 */     // MIs[3] Operand 2
     /*   30461 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(8),
     /*   30472 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /*   30476 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30480 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   30484 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   30488 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30492 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   30496 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   30500 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   30504 */     // MIs[5] Operand 2
     /*   30504 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(8),
     /*   30515 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/1, /*OpIdx*/2, // MIs[7]
     /*   30519 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30523 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   30527 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   30531 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   30533 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/1, // MIs[8]
     /*   30537 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30541 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   30545 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   30549 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   30551 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   30555 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30559 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   30562 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30567 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   30571 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   30575 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   30577 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   30581 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30585 */     // MIs[10] src0
     /*   30585 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   30590 */     // MIs[10] Operand 2
     /*   30590 */     GIM_CheckLiteralInt, /*MI*/10, /*Op*/2, GIMT_Encode8(8),
     /*   30601 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   30605 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30609 */     // MIs[11] src1
     /*   30609 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   30614 */     // MIs[11] Operand 2
     /*   30614 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   30625 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/7, /*OpIdx*/2, // MIs[12]
     /*   30629 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30633 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   30636 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30641 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   30645 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   30649 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   30651 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   30655 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30659 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   30663 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   30667 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30671 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   30675 */     // MIs[14] src0
     /*   30675 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   30680 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 8,
     /*   30684 */     // MIs[13] Operand 2
     /*   30684 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   30695 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   30699 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30703 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   30707 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   30711 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30715 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   30719 */     // MIs[16] src1
     /*   30719 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   30724 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 8,
     /*   30728 */     // MIs[15] Operand 2
     /*   30728 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   30739 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   30743 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30747 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   30750 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30755 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   30759 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   30763 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   30765 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   30769 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   30773 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   30777 */     // MIs[18] src0
     /*   30777 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   30782 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   30786 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   30790 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   30794 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   30798 */     // MIs[19] src1
     /*   30798 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   30803 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   30807 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   30809 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   30809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   30812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   30814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   30817 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src0
     /*   30821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   30824 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   30828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   30831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/1, // src2
     /*   30835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   30838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   30841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   30844 */     GIR_RootConstrainSelectedInstOperands,
     /*   30845 */     // GIR_Coverage, 32764,
     /*   30845 */     GIR_EraseRootFromParent_Done,
     /*   30846 */   // Label 237: @30846
     /*   30846 */   GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(31321), // Rule ID 32763 //
     /*   30851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   30854 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   30856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   30860 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   30864 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30868 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   30872 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   30876 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   30878 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   30882 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   30886 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   30890 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   30894 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   30896 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   30900 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   30904 */     GIM_CheckNumOperands, /*MI*/3, /*Expected*/4,
     /*   30907 */     GIM_CheckIntrinsicID, /*MI*/3, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   30912 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   30916 */     GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
     /*   30920 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   30922 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*   30926 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30930 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   30934 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   30938 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30942 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   30946 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   30950 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/2, 8,
     /*   30954 */     // MIs[4] Operand 2
     /*   30954 */     GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(8),
     /*   30965 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/3, // MIs[6]
     /*   30969 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   30973 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   30977 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   30981 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   30985 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   30989 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   30993 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 8,
     /*   30997 */     // MIs[6] Operand 2
     /*   30997 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   31008 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/2, // MIs[8]
     /*   31012 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31016 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   31020 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   31024 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   31026 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   31030 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31034 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   31037 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31042 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   31046 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   31050 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   31052 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   31056 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31060 */     // MIs[10] src0
     /*   31060 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31065 */     // MIs[10] Operand 2
     /*   31065 */     GIM_CheckLiteralInt, /*MI*/10, /*Op*/2, GIMT_Encode8(8),
     /*   31076 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   31080 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31084 */     // MIs[11] src1
     /*   31084 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   31089 */     // MIs[11] Operand 2
     /*   31089 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   31100 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   31104 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31108 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   31111 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31116 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   31120 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   31124 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   31126 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   31130 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31134 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   31138 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   31142 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31146 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   31150 */     // MIs[14] src0
     /*   31150 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31155 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   31159 */     // MIs[13] Operand 2
     /*   31159 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   31170 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   31174 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31178 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   31182 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   31186 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31190 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   31194 */     // MIs[16] src1
     /*   31194 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   31199 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   31203 */     // MIs[15] Operand 2
     /*   31203 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   31214 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   31218 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31222 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   31225 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31230 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   31234 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   31238 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   31240 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   31244 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   31248 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   31252 */     // MIs[18] src0
     /*   31252 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31257 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   31261 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   31265 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   31269 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   31273 */     // MIs[19] src1
     /*   31273 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   31278 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   31282 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   31284 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   31284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   31287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   31289 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   31292 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   31296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   31299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/7, /*OpIdx*/1, // src1
     /*   31303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   31306 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/2, // src2
     /*   31310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   31313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   31316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   31319 */     GIR_RootConstrainSelectedInstOperands,
     /*   31320 */     // GIR_Coverage, 32763,
     /*   31320 */     GIR_EraseRootFromParent_Done,
     /*   31321 */   // Label 238: @31321
     /*   31321 */   GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(31796), // Rule ID 32762 //
     /*   31326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   31329 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   31331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   31335 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   31339 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31343 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   31347 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   31351 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   31353 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   31357 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31361 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   31365 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   31369 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   31371 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   31375 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31379 */     GIM_CheckNumOperands, /*MI*/3, /*Expected*/4,
     /*   31382 */     GIM_CheckIntrinsicID, /*MI*/3, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31387 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   31391 */     GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
     /*   31395 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   31397 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*   31401 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31405 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   31409 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   31413 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31417 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   31421 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   31425 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/2, 8,
     /*   31429 */     // MIs[4] Operand 2
     /*   31429 */     GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(8),
     /*   31440 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/3, /*OpIdx*/3, // MIs[6]
     /*   31444 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31448 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   31452 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7]
     /*   31456 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31460 */     GIM_CheckType, /*MI*/7, /*Op*/1, /*Type*/GILLT_s32,
     /*   31464 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   31468 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 8,
     /*   31472 */     // MIs[6] Operand 2
     /*   31472 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   31483 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/2, // MIs[8]
     /*   31487 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31491 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   31495 */     GIM_CheckType, /*MI*/8, /*Op*/2, /*Type*/GILLT_s32,
     /*   31499 */     GIM_CheckHasOneUse, /*MI*/8,
     /*   31501 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/2, // MIs[9]
     /*   31505 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31509 */     GIM_CheckNumOperands, /*MI*/9, /*Expected*/4,
     /*   31512 */     GIM_CheckIntrinsicID, /*MI*/9, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31517 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   31521 */     GIM_CheckType, /*MI*/9, /*Op*/3, /*Type*/GILLT_s32,
     /*   31525 */     GIM_CheckHasOneUse, /*MI*/9,
     /*   31527 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/9, /*OpIdx*/2, // MIs[10]
     /*   31531 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31535 */     // MIs[10] src0
     /*   31535 */     GIM_CheckIsSameOperand, /*MI*/10, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31540 */     // MIs[10] Operand 2
     /*   31540 */     GIM_CheckLiteralInt, /*MI*/10, /*Op*/2, GIMT_Encode8(8),
     /*   31551 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/9, /*OpIdx*/3, // MIs[11]
     /*   31555 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31559 */     // MIs[11] src1
     /*   31559 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   31564 */     // MIs[11] Operand 2
     /*   31564 */     GIM_CheckLiteralInt, /*MI*/11, /*Op*/2, GIMT_Encode8(8),
     /*   31575 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   31579 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31583 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   31586 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31591 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   31595 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   31599 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   31601 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   31605 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31609 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   31613 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   31617 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31621 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   31625 */     // MIs[14] src0
     /*   31625 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31630 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   31634 */     // MIs[13] Operand 2
     /*   31634 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   31645 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   31649 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31653 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   31657 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   31661 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31665 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   31669 */     // MIs[16] src1
     /*   31669 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   31674 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   31678 */     // MIs[15] Operand 2
     /*   31678 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   31689 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   31693 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31697 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   31700 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31705 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   31709 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   31713 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   31715 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   31719 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   31723 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   31727 */     // MIs[18] src0
     /*   31727 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31732 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   31736 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   31740 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   31744 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   31748 */     // MIs[19] src1
     /*   31748 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/7, /*OtherOpIdx*/1,
     /*   31753 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   31757 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   31759 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   31759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   31762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   31764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   31767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   31771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   31774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/7, /*OpIdx*/1, // src1
     /*   31778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   31781 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/8, /*OpIdx*/1, // src2
     /*   31785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   31788 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   31791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   31794 */     GIR_RootConstrainSelectedInstOperands,
     /*   31795 */     // GIR_Coverage, 32762,
     /*   31795 */     GIR_EraseRootFromParent_Done,
     /*   31796 */   // Label 239: @31796
     /*   31796 */   GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(32271), // Rule ID 32761 //
     /*   31801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   31804 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   31806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   31810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   31814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   31822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   31826 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   31828 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   31832 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31836 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   31840 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   31844 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   31846 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   31850 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   31854 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   31858 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   31862 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   31864 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   31868 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31872 */     GIM_CheckNumOperands, /*MI*/4, /*Expected*/4,
     /*   31875 */     GIM_CheckIntrinsicID, /*MI*/4, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31880 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   31884 */     GIM_CheckType, /*MI*/4, /*Op*/3, /*Type*/GILLT_s32,
     /*   31888 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   31890 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*   31894 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31898 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   31902 */     // MIs[5] Operand 2
     /*   31902 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(8),
     /*   31913 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/3, // MIs[6]
     /*   31917 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31921 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   31925 */     // MIs[6] Operand 2
     /*   31925 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   31936 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/2, // MIs[7]
     /*   31940 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   31944 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   31947 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   31952 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   31956 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   31960 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   31962 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   31966 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   31970 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   31974 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   31978 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   31982 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   31986 */     // MIs[9] src0
     /*   31986 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   31991 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 8,
     /*   31995 */     // MIs[8] Operand 2
     /*   31995 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   32006 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/7, /*OpIdx*/3, // MIs[10]
     /*   32010 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32014 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   32018 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   32022 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32026 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   32030 */     // MIs[11] src1
     /*   32030 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   32035 */     GIM_CheckConstantInt8, /*MI*/11, /*Op*/2, 8,
     /*   32039 */     // MIs[10] Operand 2
     /*   32039 */     GIM_CheckLiteralInt, /*MI*/10, /*Op*/2, GIMT_Encode8(8),
     /*   32050 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   32054 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32058 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   32061 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   32066 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   32070 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   32074 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   32076 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   32080 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32084 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   32088 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   32092 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32096 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   32100 */     // MIs[14] src0
     /*   32100 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   32105 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   32109 */     // MIs[13] Operand 2
     /*   32109 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   32120 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   32124 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32128 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   32132 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   32136 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32140 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   32144 */     // MIs[16] src1
     /*   32144 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   32149 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   32153 */     // MIs[15] Operand 2
     /*   32153 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   32164 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   32168 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32172 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   32175 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   32180 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   32184 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   32188 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   32190 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   32194 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   32198 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   32202 */     // MIs[18] src0
     /*   32202 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   32207 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   32211 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   32215 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   32219 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   32223 */     // MIs[19] src1
     /*   32223 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   32228 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   32232 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   32234 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   32234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   32237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   32239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   32246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   32253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // src2
     /*   32260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32269 */     GIR_RootConstrainSelectedInstOperands,
     /*   32270 */     // GIR_Coverage, 32761,
     /*   32270 */     GIR_EraseRootFromParent_Done,
     /*   32271 */   // Label 240: @32271
     /*   32271 */   GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(32746), // Rule ID 7628 //
     /*   32276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*   32279 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   32281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   32285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   32289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   32293 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   32297 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   32301 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   32303 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   32307 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   32311 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   32315 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   32319 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   32321 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   32325 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   32329 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   32333 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   32337 */     GIM_CheckHasOneUse, /*MI*/3,
     /*   32339 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*   32343 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32347 */     GIM_CheckNumOperands, /*MI*/4, /*Expected*/4,
     /*   32350 */     GIM_CheckIntrinsicID, /*MI*/4, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   32355 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   32359 */     GIM_CheckType, /*MI*/4, /*Op*/3, /*Type*/GILLT_s32,
     /*   32363 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   32365 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*   32369 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32373 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   32377 */     // MIs[5] Operand 2
     /*   32377 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(8),
     /*   32388 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/3, // MIs[6]
     /*   32392 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32396 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   32400 */     // MIs[6] Operand 2
     /*   32400 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(8),
     /*   32411 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/2, // MIs[7]
     /*   32415 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32419 */     GIM_CheckNumOperands, /*MI*/7, /*Expected*/4,
     /*   32422 */     GIM_CheckIntrinsicID, /*MI*/7, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   32427 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   32431 */     GIM_CheckType, /*MI*/7, /*Op*/3, /*Type*/GILLT_s32,
     /*   32435 */     GIM_CheckHasOneUse, /*MI*/7,
     /*   32437 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/7, /*OpIdx*/2, // MIs[8]
     /*   32441 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32445 */     GIM_CheckType, /*MI*/8, /*Op*/1, /*Type*/GILLT_s32,
     /*   32449 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/8, /*OpIdx*/1, // MIs[9]
     /*   32453 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32457 */     GIM_CheckType, /*MI*/9, /*Op*/2, /*Type*/GILLT_s32,
     /*   32461 */     // MIs[9] src0
     /*   32461 */     GIM_CheckIsSameOperand, /*MI*/9, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   32466 */     GIM_CheckConstantInt8, /*MI*/9, /*Op*/2, 8,
     /*   32470 */     // MIs[8] Operand 2
     /*   32470 */     GIM_CheckLiteralInt, /*MI*/8, /*Op*/2, GIMT_Encode8(8),
     /*   32481 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/7, /*OpIdx*/3, // MIs[10]
     /*   32485 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32489 */     GIM_CheckType, /*MI*/10, /*Op*/1, /*Type*/GILLT_s32,
     /*   32493 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/10, /*OpIdx*/1, // MIs[11]
     /*   32497 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32501 */     GIM_CheckType, /*MI*/11, /*Op*/2, /*Type*/GILLT_s32,
     /*   32505 */     // MIs[11] src1
     /*   32505 */     GIM_CheckIsSameOperand, /*MI*/11, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   32510 */     GIM_CheckConstantInt8, /*MI*/11, /*Op*/2, 8,
     /*   32514 */     // MIs[10] Operand 2
     /*   32514 */     GIM_CheckLiteralInt, /*MI*/10, /*Op*/2, GIMT_Encode8(8),
     /*   32525 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/1, /*OpIdx*/2, // MIs[12]
     /*   32529 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32533 */     GIM_CheckNumOperands, /*MI*/12, /*Expected*/4,
     /*   32536 */     GIM_CheckIntrinsicID, /*MI*/12, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   32541 */     GIM_CheckType, /*MI*/12, /*Op*/2, /*Type*/GILLT_s32,
     /*   32545 */     GIM_CheckType, /*MI*/12, /*Op*/3, /*Type*/GILLT_s32,
     /*   32549 */     GIM_CheckHasOneUse, /*MI*/12,
     /*   32551 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/12, /*OpIdx*/2, // MIs[13]
     /*   32555 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32559 */     GIM_CheckType, /*MI*/13, /*Op*/1, /*Type*/GILLT_s32,
     /*   32563 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/13, /*OpIdx*/1, // MIs[14]
     /*   32567 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32571 */     GIM_CheckType, /*MI*/14, /*Op*/2, /*Type*/GILLT_s32,
     /*   32575 */     // MIs[14] src0
     /*   32575 */     GIM_CheckIsSameOperand, /*MI*/14, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   32580 */     GIM_CheckConstantInt8, /*MI*/14, /*Op*/2, 16,
     /*   32584 */     // MIs[13] Operand 2
     /*   32584 */     GIM_CheckLiteralInt, /*MI*/13, /*Op*/2, GIMT_Encode8(8),
     /*   32595 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/12, /*OpIdx*/3, // MIs[15]
     /*   32599 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   32603 */     GIM_CheckType, /*MI*/15, /*Op*/1, /*Type*/GILLT_s32,
     /*   32607 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/15, /*OpIdx*/1, // MIs[16]
     /*   32611 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32615 */     GIM_CheckType, /*MI*/16, /*Op*/2, /*Type*/GILLT_s32,
     /*   32619 */     // MIs[16] src1
     /*   32619 */     GIM_CheckIsSameOperand, /*MI*/16, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   32624 */     GIM_CheckConstantInt8, /*MI*/16, /*Op*/2, 16,
     /*   32628 */     // MIs[15] Operand 2
     /*   32628 */     GIM_CheckLiteralInt, /*MI*/15, /*Op*/2, GIMT_Encode8(8),
     /*   32639 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/0, /*OpIdx*/2, // MIs[17]
     /*   32643 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32647 */     GIM_CheckNumOperands, /*MI*/17, /*Expected*/4,
     /*   32650 */     GIM_CheckIntrinsicID, /*MI*/17, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   32655 */     GIM_CheckType, /*MI*/17, /*Op*/2, /*Type*/GILLT_s32,
     /*   32659 */     GIM_CheckType, /*MI*/17, /*Op*/3, /*Type*/GILLT_s32,
     /*   32663 */     GIM_CheckHasOneUse, /*MI*/17,
     /*   32665 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/17, /*OpIdx*/2, // MIs[18]
     /*   32669 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   32673 */     GIM_CheckType, /*MI*/18, /*Op*/2, /*Type*/GILLT_s32,
     /*   32677 */     // MIs[18] src0
     /*   32677 */     GIM_CheckIsSameOperand, /*MI*/18, /*OpIdx*/1, /*OtherMI*/5, /*OtherOpIdx*/1,
     /*   32682 */     GIM_CheckConstantInt8, /*MI*/18, /*Op*/2, 24,
     /*   32686 */     GIM_RecordInsn, /*DefineMI*/19, /*MI*/17, /*OpIdx*/3, // MIs[19]
     /*   32690 */     GIM_CheckOpcode, /*MI*/19, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   32694 */     GIM_CheckType, /*MI*/19, /*Op*/2, /*Type*/GILLT_s32,
     /*   32698 */     // MIs[19] src1
     /*   32698 */     GIM_CheckIsSameOperand, /*MI*/19, /*OpIdx*/1, /*OtherMI*/6, /*OtherOpIdx*/1,
     /*   32703 */     GIM_CheckConstantInt8, /*MI*/19, /*Op*/2, 24,
     /*   32707 */     GIM_CheckIsSafeToFold, /*NumInsns*/19,
     /*   32709 */     // (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 8:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 8:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), i8:{ *:[Other] }), (sext_inreg:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }), i8:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 24:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 24:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>  =>  (V_DOT4_I32_I8:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   32709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*   32712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   32714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32717 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   32721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32724 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   32728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
     /*   32735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32744 */     GIR_RootConstrainSelectedInstOperands,
     /*   32745 */     // GIR_Coverage, 7628,
     /*   32745 */     GIR_EraseRootFromParent_Done,
     /*   32746 */   // Label 241: @32746
     /*   32746 */   GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(32969), // Rule ID 31418 //
     /*   32751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   32754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   32758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   32762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32766 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   32769 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   32774 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   32778 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   32782 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   32784 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   32788 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   32792 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   32796 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   32800 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
     /*   32811 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   32815 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   32819 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   32823 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   32827 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
     /*   32838 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   32842 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   32846 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   32850 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   32854 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   32856 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   32860 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32864 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   32867 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   32872 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   32876 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   32880 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   32882 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   32886 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32890 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   32894 */     // MIs[6] src0
     /*   32894 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   32899 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   32903 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   32907 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   32911 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   32915 */     // MIs[7] src1
     /*   32915 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   32920 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   32924 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   32926 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 65535:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 65535:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)  =>  (V_DOT2_U32_U16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   32926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16),
     /*   32929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   32931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32934 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   32938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   32945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   32948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // src2
     /*   32952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   32967 */     GIR_RootConstrainSelectedInstOperands,
     /*   32968 */     // GIR_Coverage, 31418,
     /*   32968 */     GIR_EraseRootFromParent_Done,
     /*   32969 */   // Label 242: @32969
     /*   32969 */   GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(33192), // Rule ID 31419 //
     /*   32974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   32977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   32981 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   32985 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   32989 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   32992 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   32997 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   33001 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   33005 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   33007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   33011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   33015 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   33019 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   33023 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
     /*   33034 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   33038 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   33042 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   33046 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   33050 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
     /*   33061 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   33065 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   33069 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   33073 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   33077 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   33079 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*   33083 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33087 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   33090 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   33095 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   33099 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   33103 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   33105 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   33109 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   33113 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   33117 */     // MIs[6] src0
     /*   33117 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   33122 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   33126 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   33130 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   33134 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   33138 */     // MIs[7] src1
     /*   33138 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   33143 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   33147 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   33149 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 65535:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 65535:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>)  =>  (V_DOT2_U32_U16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   33149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16),
     /*   33152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   33154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33157 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   33161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   33168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src2
     /*   33175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33190 */     GIR_RootConstrainSelectedInstOperands,
     /*   33191 */     // GIR_Coverage, 31419,
     /*   33191 */     GIR_EraseRootFromParent_Done,
     /*   33192 */   // Label 243: @33192
     /*   33192 */   GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(33415), // Rule ID 7604 //
     /*   33197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   33200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   33204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   33208 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   33212 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   33216 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   33220 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   33222 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   33226 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33230 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   33233 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   33238 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   33242 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   33246 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   33248 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   33252 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   33256 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   33260 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   33264 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   33268 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/3, // MIs[4]
     /*   33272 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   33276 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   33280 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   33284 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   33288 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
     /*   33292 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33296 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   33299 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   33304 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   33308 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   33312 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   33314 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   33318 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   33322 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   33326 */     // MIs[6] src0
     /*   33326 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   33331 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(65535),
     /*   33342 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   33346 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_AND),
     /*   33350 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   33354 */     // MIs[7] src1
     /*   33354 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   33359 */     GIM_CheckConstantInt, /*MI*/7, /*Op*/2, GIMT_Encode8(65535),
     /*   33370 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   33372 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 65535:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 65535:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)  =>  (V_DOT2_U32_U16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   33372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16),
     /*   33375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   33377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src0
     /*   33384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
     /*   33391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /*   33398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33413 */     GIR_RootConstrainSelectedInstOperands,
     /*   33414 */     // GIR_Coverage, 7604,
     /*   33414 */     GIR_EraseRootFromParent_Done,
     /*   33415 */   // Label 244: @33415
     /*   33415 */   GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(33638), // Rule ID 31417 //
     /*   33420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   33423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   33427 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   33431 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   33435 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   33439 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   33443 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   33445 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   33449 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33453 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   33456 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   33461 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   33465 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   33469 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   33471 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   33475 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   33479 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   33483 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   33487 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   33491 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/3, // MIs[4]
     /*   33495 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   33499 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   33503 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   33507 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   33511 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
     /*   33515 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33519 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   33522 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   33527 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   33531 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   33535 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   33537 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   33541 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*   33545 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   33549 */     // MIs[6] src0
     /*   33549 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   33554 */     GIM_CheckConstantInt, /*MI*/6, /*Op*/2, GIMT_Encode8(65535),
     /*   33565 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   33569 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_AND),
     /*   33573 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   33577 */     // MIs[7] src1
     /*   33577 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   33582 */     GIM_CheckConstantInt, /*MI*/7, /*Op*/2, GIMT_Encode8(65535),
     /*   33593 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   33595 */     // (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, 65535:{ *:[i32] }), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, 65535:{ *:[i32] }))<<P:Predicate_AMDGPUmul_u24_oneuse>>)  =>  (V_DOT2_U32_U16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   33595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16),
     /*   33598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   33600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src0
     /*   33607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
     /*   33614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
     /*   33621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33636 */     GIR_RootConstrainSelectedInstOperands,
     /*   33637 */     // GIR_Coverage, 31417,
     /*   33637 */     GIR_EraseRootFromParent_Done,
     /*   33638 */   // Label 245: @33638
     /*   33638 */   GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(33853), // Rule ID 31450 //
     /*   33643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   33646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   33650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   33654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33658 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   33661 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   33666 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   33670 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   33674 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   33676 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   33680 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   33684 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   33688 */     // MIs[2] Operand 2
     /*   33688 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /*   33699 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   33703 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   33707 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   33711 */     // MIs[3] Operand 2
     /*   33711 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
     /*   33722 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   33726 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   33730 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   33734 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   33738 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   33740 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   33744 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33748 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   33751 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   33756 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   33760 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   33764 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   33766 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   33770 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   33774 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   33778 */     // MIs[6] src0
     /*   33778 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   33783 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   33787 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   33791 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   33795 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   33799 */     // MIs[7] src1
     /*   33799 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   33804 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   33808 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   33810 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i16:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>)  =>  (V_DOT2_I32_I16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   33810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16),
     /*   33813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   33815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   33822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33825 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   33829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   33832 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // src2
     /*   33836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33839 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   33851 */     GIR_RootConstrainSelectedInstOperands,
     /*   33852 */     // GIR_Coverage, 31450,
     /*   33852 */     GIR_EraseRootFromParent_Done,
     /*   33853 */   // Label 246: @33853
     /*   33853 */   GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(34068), // Rule ID 31451 //
     /*   33858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   33861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   33865 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   33869 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33873 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   33876 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   33881 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   33885 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   33889 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   33891 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   33895 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   33899 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   33903 */     // MIs[2] Operand 2
     /*   33903 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /*   33914 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*   33918 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   33922 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   33926 */     // MIs[3] Operand 2
     /*   33926 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
     /*   33937 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   33941 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   33945 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   33949 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   33953 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   33955 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*   33959 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   33963 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   33966 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   33971 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   33975 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   33979 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   33981 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   33985 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   33989 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   33993 */     // MIs[6] src0
     /*   33993 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   33998 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   34002 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   34006 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   34010 */     GIM_CheckType, /*MI*/7, /*Op*/2, /*Type*/GILLT_s32,
     /*   34014 */     // MIs[7] src1
     /*   34014 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   34019 */     GIM_CheckConstantInt8, /*MI*/7, /*Op*/2, 16,
     /*   34023 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   34025 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i16:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>)  =>  (V_DOT2_I32_I16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   34025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16),
     /*   34028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34033 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   34037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   34044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34047 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src2
     /*   34051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34066 */     GIR_RootConstrainSelectedInstOperands,
     /*   34067 */     // GIR_Coverage, 31451,
     /*   34067 */     GIR_EraseRootFromParent_Done,
     /*   34068 */   // Label 247: @34068
     /*   34068 */   GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(34283), // Rule ID 7608 //
     /*   34073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   34076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   34088 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34092 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34096 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34098 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   34102 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   34106 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   34109 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   34114 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   34118 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   34122 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   34124 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   34128 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   34132 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   34136 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   34140 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   34144 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/3, // MIs[4]
     /*   34148 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   34152 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   34156 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   34160 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   34164 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
     /*   34168 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   34172 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   34175 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   34180 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   34184 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   34188 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   34190 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   34194 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   34198 */     // MIs[6] src0
     /*   34198 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   34203 */     // MIs[6] Operand 2
     /*   34203 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(16),
     /*   34214 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   34218 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   34222 */     // MIs[7] src1
     /*   34222 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   34227 */     // MIs[7] Operand 2
     /*   34227 */     GIM_CheckLiteralInt, /*MI*/7, /*Op*/2, GIMT_Encode8(16),
     /*   34238 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   34240 */     // (add:{ *:[i32] } (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i16:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)  =>  (V_DOT2_I32_I16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   34240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16),
     /*   34243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src0
     /*   34252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
     /*   34259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /*   34266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34281 */     GIR_RootConstrainSelectedInstOperands,
     /*   34282 */     // GIR_Coverage, 7608,
     /*   34282 */     GIR_EraseRootFromParent_Done,
     /*   34283 */   // Label 248: @34283
     /*   34283 */   GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(34498), // Rule ID 31449 //
     /*   34288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*   34291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   34303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34307 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34311 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34313 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   34317 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   34321 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   34324 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   34329 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   34333 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   34337 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   34339 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   34343 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   34347 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   34351 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   34355 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   34359 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/3, // MIs[4]
     /*   34363 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   34367 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   34371 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   34375 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   34379 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/2, // MIs[5]
     /*   34383 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   34387 */     GIM_CheckNumOperands, /*MI*/5, /*Expected*/4,
     /*   34390 */     GIM_CheckIntrinsicID, /*MI*/5, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   34395 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   34399 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   34403 */     GIM_CheckHasOneUse, /*MI*/5,
     /*   34405 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*   34409 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   34413 */     // MIs[6] src0
     /*   34413 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*   34418 */     // MIs[6] Operand 2
     /*   34418 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(16),
     /*   34429 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/5, /*OpIdx*/3, // MIs[7]
     /*   34433 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   34437 */     // MIs[7] src1
     /*   34437 */     GIM_CheckIsSameOperand, /*MI*/7, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*   34442 */     // MIs[7] Operand 2
     /*   34442 */     GIM_CheckLiteralInt, /*MI*/7, /*Op*/2, GIMT_Encode8(16),
     /*   34453 */     GIM_CheckIsSafeToFold, /*NumInsns*/7,
     /*   34455 */     // (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, 16:{ *:[i32] }), (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, 16:{ *:[i32] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)<<P:Predicate_add_oneuse>>, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src0, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } i32:{ *:[i32] }:$src1, i16:{ *:[Other] }))<<P:Predicate_AMDGPUmul_i24_oneuse>>)  =>  (V_DOT2_I32_I16:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src0, 8:{ *:[i32] }, ?:{ *:[i32] }:$src1, 8:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   34455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16),
     /*   34458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src0
     /*   34467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
     /*   34474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*   34477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
     /*   34481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34484 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34496 */     GIR_RootConstrainSelectedInstOperands,
     /*   34497 */     // GIR_Coverage, 31449,
     /*   34497 */     GIR_EraseRootFromParent_Done,
     /*   34498 */   // Label 249: @34498
     /*   34498 */   GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(34563), // Rule ID 7278 //
     /*   34503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadU32Inst),
     /*   34506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   34518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34522 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34526 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34528 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x
     /*   34532 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y
     /*   34536 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:9:z
     /*   34540 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   34544 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   34546 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:9:x, i32:{ *:[i32] }:$src1:$pred:9:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:9:z)<<P:9:Predicate_anonymous_28501>>  =>  (V_MAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   34546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U32_e64),
     /*   34549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34551 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   34555 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   34559 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   34561 */     GIR_RootConstrainSelectedInstOperands,
     /*   34562 */     // GIR_Coverage, 7278,
     /*   34562 */     GIR_EraseRootFromParent_Done,
     /*   34563 */   // Label 250: @34563
     /*   34563 */   GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(34628), // Rule ID 31349 //
     /*   34568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadU32Inst),
     /*   34571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34575 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:9:z
     /*   34579 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   34583 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   34587 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34591 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34595 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34597 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x
     /*   34601 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y
     /*   34605 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   34609 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   34611 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:9:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:9:x, i32:{ *:[i32] }:$src1:$pred:9:y)<<P:Predicate_anonymous_28502>>)<<P:9:Predicate_anonymous_28501>>  =>  (V_MAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   34611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U32_e64),
     /*   34614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   34620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   34624 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   34626 */     GIR_RootConstrainSelectedInstOperands,
     /*   34627 */     // GIR_Coverage, 31349,
     /*   34627 */     GIR_EraseRootFromParent_Done,
     /*   34628 */   // Label 251: @34628
     /*   34628 */   GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(34681), // Rule ID 28494 //
     /*   34633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   34637 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34641 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   34645 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34649 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34653 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1,
     /*   34657 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   34661 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20771),
     /*   34665 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   34667 */     // (add:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), -1:{ *:[i32] })<<P:Predicate_anonymous_20771>>  =>  (S_BFM_B32:{ *:[i32] } ?:{ *:[i32] }:$a, 0:{ *:[i32] })
     /*   34667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BFM_B32),
     /*   34670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   34672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /*   34676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34679 */     GIR_RootConstrainSelectedInstOperands,
     /*   34680 */     // GIR_Coverage, 28494,
     /*   34680 */     GIR_EraseRootFromParent_Done,
     /*   34681 */   // Label 252: @34681
     /*   34681 */   GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(34734), // Rule ID 28496 //
     /*   34686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34694 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   34698 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34702 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34706 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 1,
     /*   34710 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   34714 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   34718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   34720 */     // (add:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), -1:{ *:[i32] })<<P:Predicate_anonymous_27132>>  =>  (V_BFM_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$a, 0:{ *:[i32] })
     /*   34720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFM_B32_e64),
     /*   34723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34725 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /*   34729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34732 */     GIR_RootConstrainSelectedInstOperands,
     /*   34733 */     // GIR_Coverage, 28496,
     /*   34733 */     GIR_EraseRootFromParent_Done,
     /*   34734 */   // Label 253: @34734
     /*   34734 */   GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(34844), // Rule ID 28102 //
     /*   34739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SELECT),
     /*   34751 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*   34755 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34759 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   34763 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34765 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   34769 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*   34773 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   34777 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   34781 */     // MIs[2] Operand 1
     /*   34781 */     GIM_CheckCmpPredicate, /*MI*/2, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /*   34786 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   34790 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   34794 */     // MIs[3] src0
     /*   34794 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   34799 */     // MIs[3] src1
     /*   34799 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/3,
     /*   34804 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/3, // MIs[4]
     /*   34808 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   34812 */     // MIs[4] src1
     /*   34812 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/3,
     /*   34817 */     // MIs[4] src0
     /*   34817 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   34822 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   34824 */     // (add:{ *:[i32] } (select:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETUGT:{ *:[Other] }), (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (sub:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))<<P:Predicate_select_oneuse>>, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   34824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   34827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34829 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
     /*   34833 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // src1
     /*   34837 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   34839 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34842 */     GIR_RootConstrainSelectedInstOperands,
     /*   34843 */     // GIR_Coverage, 28102,
     /*   34843 */     GIR_EraseRootFromParent_Done,
     /*   34844 */   // Label 254: @34844
     /*   34844 */   GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(34954), // Rule ID 34102 //
     /*   34849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   34857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SELECT),
     /*   34861 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*   34865 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34869 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   34873 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   34879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*   34883 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   34887 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   34891 */     // MIs[2] Operand 1
     /*   34891 */     GIM_CheckCmpPredicate, /*MI*/2, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /*   34896 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   34900 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   34904 */     // MIs[3] src0
     /*   34904 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   34909 */     // MIs[3] src1
     /*   34909 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/3,
     /*   34914 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/3, // MIs[4]
     /*   34918 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   34922 */     // MIs[4] src1
     /*   34922 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/3,
     /*   34927 */     // MIs[4] src0
     /*   34927 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   34932 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   34934 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (select:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETUGT:{ *:[Other] }), (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (sub:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))<<P:Predicate_select_oneuse>>)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   34934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   34937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   34939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
     /*   34943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // src1
     /*   34947 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   34949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   34952 */     GIR_RootConstrainSelectedInstOperands,
     /*   34953 */     // GIR_Coverage, 34102,
     /*   34953 */     GIR_EraseRootFromParent_Done,
     /*   34954 */   // Label 255: @34954
     /*   34954 */   GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(35047), // Rule ID 7268 //
     /*   34959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   34962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   34966 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   34970 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   34974 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   34978 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   34982 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   34984 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
     /*   34988 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   34992 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   34996 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35000 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35004 */     GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y
     /*   35008 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   35012 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   35016 */     // MIs[3] Operand 1
     /*   35016 */     // No operand predicates
     /*   35016 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*   35020 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z
     /*   35024 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28479),
     /*   35028 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35030 */     // (add:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:1:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_28480>>, i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_anonymous_28479>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   35030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
     /*   35033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35035 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   35039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   35043 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35045 */     GIR_RootConstrainSelectedInstOperands,
     /*   35046 */     // GIR_Coverage, 7268,
     /*   35046 */     GIR_EraseRootFromParent_Done,
     /*   35047 */   // Label 256: @35047
     /*   35047 */   GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(35140), // Rule ID 31342 //
     /*   35052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   35055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35059 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:1:z
     /*   35063 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35067 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   35071 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35075 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35079 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35081 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
     /*   35085 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   35089 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   35093 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35097 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35101 */     GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y
     /*   35105 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   35109 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   35113 */     // MIs[3] Operand 1
     /*   35113 */     // No operand predicates
     /*   35113 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*   35117 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28479),
     /*   35121 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35123 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:1:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:1:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_28480>>)<<P:1:Predicate_anonymous_28479>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   35123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
     /*   35126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   35132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   35136 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   35138 */     GIR_RootConstrainSelectedInstOperands,
     /*   35139 */     // GIR_Coverage, 31342,
     /*   35139 */     GIR_EraseRootFromParent_Done,
     /*   35140 */   // Label 257: @35140
     /*   35140 */   GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(35195), // Rule ID 28017 //
     /*   35145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   35153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   35157 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   35160 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   35165 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35169 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   35173 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   35175 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)  =>  (V_MAD_I32_I24_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_I32_I24_e64),
     /*   35178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35180 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   35184 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   35188 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35193 */     GIR_RootConstrainSelectedInstOperands,
     /*   35194 */     // GIR_Coverage, 28017,
     /*   35194 */     GIR_EraseRootFromParent_Done,
     /*   35195 */   // Label 258: @35195
     /*   35195 */   GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(35250), // Rule ID 28019 //
     /*   35200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   35208 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   35212 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   35215 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   35220 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35224 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   35228 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   35230 */     // (add:{ *:[i32] } (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)  =>  (V_MAD_U32_U24_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U32_U24_e64),
     /*   35233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   35239 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   35243 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35248 */     GIR_RootConstrainSelectedInstOperands,
     /*   35249 */     // GIR_Coverage, 28019,
     /*   35249 */     GIR_EraseRootFromParent_Done,
     /*   35250 */   // Label 259: @35250
     /*   35250 */   GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(35333), // Rule ID 28101 //
     /*   35255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35259 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   35263 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35267 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35271 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35275 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35277 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35281 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35285 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35289 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35293 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35297 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35301 */     // MIs[3] src0
     /*   35301 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35306 */     // MIs[3] src1
     /*   35306 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35311 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35313 */     // (add:{ *:[i32] } (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))<<P:Predicate_sub_oneuse>>, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35318 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   35322 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
     /*   35326 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35331 */     GIR_RootConstrainSelectedInstOperands,
     /*   35332 */     // GIR_Coverage, 28101,
     /*   35332 */     GIR_EraseRootFromParent_Done,
     /*   35333 */   // Label 260: @35333
     /*   35333 */   GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(35416), // Rule ID 34095 //
     /*   35338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   35346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35354 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35358 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35360 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35364 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35368 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35372 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35376 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35380 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35384 */     // MIs[3] src1
     /*   35384 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35389 */     // MIs[3] src0
     /*   35389 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35394 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35396 */     // (add:{ *:[i32] } (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))<<P:Predicate_sub_oneuse>>, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35401 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   35405 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
     /*   35409 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35414 */     GIR_RootConstrainSelectedInstOperands,
     /*   35415 */     // GIR_Coverage, 34095,
     /*   35415 */     GIR_EraseRootFromParent_Done,
     /*   35416 */   // Label 261: @35416
     /*   35416 */   GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(35499), // Rule ID 34096 //
     /*   35421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35425 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   35429 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35433 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35437 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35441 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35443 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35447 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35451 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35455 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35459 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35463 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35467 */     // MIs[3] src0
     /*   35467 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35472 */     // MIs[3] src1
     /*   35472 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35477 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35479 */     // (add:{ *:[i32] } (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))<<P:Predicate_sub_oneuse>>, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35484 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
     /*   35488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   35492 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35497 */     GIR_RootConstrainSelectedInstOperands,
     /*   35498 */     // GIR_Coverage, 34096,
     /*   35498 */     GIR_EraseRootFromParent_Done,
     /*   35499 */   // Label 262: @35499
     /*   35499 */   GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(35582), // Rule ID 34097 //
     /*   35504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35508 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   35512 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35516 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35520 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35524 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35526 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35530 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35534 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35538 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35542 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35546 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35550 */     // MIs[3] src1
     /*   35550 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35555 */     // MIs[3] src0
     /*   35555 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35560 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35562 */     // (add:{ *:[i32] } (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))<<P:Predicate_sub_oneuse>>, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
     /*   35571 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   35575 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   35577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35580 */     GIR_RootConstrainSelectedInstOperands,
     /*   35581 */     // GIR_Coverage, 34097,
     /*   35581 */     GIR_EraseRootFromParent_Done,
     /*   35582 */   // Label 263: @35582
     /*   35582 */   GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(35637), // Rule ID 34051 //
     /*   35587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35591 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35595 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   35599 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   35602 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*   35607 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35611 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   35615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   35617 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_I32_I24_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_I32_I24_e64),
     /*   35620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35622 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   35626 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   35630 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   35632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35635 */     GIR_RootConstrainSelectedInstOperands,
     /*   35636 */     // GIR_Coverage, 34051,
     /*   35636 */     GIR_EraseRootFromParent_Done,
     /*   35637 */   // Label 264: @35637
     /*   35637 */   GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(35692), // Rule ID 34053 //
     /*   35642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   35654 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   35657 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   35662 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35666 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   35670 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   35672 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U32_U24_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U32_U24_e64),
     /*   35675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   35681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   35685 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   35687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35690 */     GIR_RootConstrainSelectedInstOperands,
     /*   35691 */     // GIR_Coverage, 34053,
     /*   35691 */     GIR_EraseRootFromParent_Done,
     /*   35692 */   // Label 265: @35692
     /*   35692 */   GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(35775), // Rule ID 34098 //
     /*   35697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35709 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35713 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35717 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35719 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35723 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35727 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35731 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35735 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35739 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35743 */     // MIs[3] src0
     /*   35743 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35748 */     // MIs[3] src1
     /*   35748 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35753 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35755 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))<<P:Predicate_sub_oneuse>>)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   35764 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
     /*   35768 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   35770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35773 */     GIR_RootConstrainSelectedInstOperands,
     /*   35774 */     // GIR_Coverage, 34098,
     /*   35774 */     GIR_EraseRootFromParent_Done,
     /*   35775 */   // Label 266: @35775
     /*   35775 */   GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(35858), // Rule ID 34099 //
     /*   35780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35792 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35796 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35800 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35802 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35806 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35810 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35814 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35818 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35822 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35826 */     // MIs[3] src1
     /*   35826 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35831 */     // MIs[3] src0
     /*   35831 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35836 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35838 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))<<P:Predicate_sub_oneuse>>)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35843 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   35847 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
     /*   35851 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   35853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35856 */     GIR_RootConstrainSelectedInstOperands,
     /*   35857 */     // GIR_Coverage, 34099,
     /*   35857 */     GIR_EraseRootFromParent_Done,
     /*   35858 */   // Label 267: @35858
     /*   35858 */   GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(35941), // Rule ID 34100 //
     /*   35863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35867 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35871 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35875 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35879 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35883 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35897 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35901 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35905 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35909 */     // MIs[3] src0
     /*   35909 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   35914 */     // MIs[3] src1
     /*   35914 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35919 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   35921 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))<<P:Predicate_sub_oneuse>>)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   35921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   35924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   35926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
     /*   35930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   35934 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   35936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   35939 */     GIR_RootConstrainSelectedInstOperands,
     /*   35940 */     // GIR_Coverage, 34100,
     /*   35940 */     GIR_EraseRootFromParent_Done,
     /*   35941 */   // Label 268: @35941
     /*   35941 */   GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(36024), // Rule ID 34101 //
     /*   35946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   35950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   35954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*   35958 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   35962 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   35966 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   35968 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   35972 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*   35976 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   35980 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   35984 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   35988 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*   35992 */     // MIs[3] src1
     /*   35992 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   35997 */     // MIs[3] src0
     /*   35997 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   36002 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   36004 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2, (sub:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))<<P:Predicate_sub_oneuse>>)  =>  (V_SAD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*   36004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U32_e64),
     /*   36007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   36009 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
     /*   36013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   36017 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   36019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   36022 */     GIR_RootConstrainSelectedInstOperands,
     /*   36023 */     // GIR_Coverage, 34101,
     /*   36023 */     GIR_EraseRootFromParent_Done,
     /*   36024 */   // Label 269: @36024
     /*   36024 */   GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(36085), // Rule ID 83 //
     /*   36029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   36040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36048 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36052 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36054 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36059 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /*   36063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36067 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36069 */     // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 1:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)  =>  (S_LSHL1_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL1_ADD_U32),
     /*   36072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36074 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36078 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   36080 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36083 */     GIR_RootConstrainSelectedInstOperands,
     /*   36084 */     // GIR_Coverage, 83,
     /*   36084 */     GIR_EraseRootFromParent_Done,
     /*   36085 */   // Label 270: @36085
     /*   36085 */   GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(36146), // Rule ID 84 //
     /*   36090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   36101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36105 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36109 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36113 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36115 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36120 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2,
     /*   36124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36128 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36130 */     // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 2:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)  =>  (S_LSHL2_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL2_ADD_U32),
     /*   36133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36139 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   36141 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36144 */     GIR_RootConstrainSelectedInstOperands,
     /*   36145 */     // GIR_Coverage, 84,
     /*   36145 */     GIR_EraseRootFromParent_Done,
     /*   36146 */   // Label 271: @36146
     /*   36146 */   GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(36207), // Rule ID 85 //
     /*   36151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   36162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36166 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36174 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36176 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36181 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3,
     /*   36185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36189 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36191 */     // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 3:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)  =>  (S_LSHL3_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL3_ADD_U32),
     /*   36194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36196 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36200 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   36202 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36205 */     GIR_RootConstrainSelectedInstOperands,
     /*   36206 */     // GIR_Coverage, 85,
     /*   36206 */     GIR_EraseRootFromParent_Done,
     /*   36207 */   // Label 272: @36207
     /*   36207 */   GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(36268), // Rule ID 86 //
     /*   36212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   36223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36227 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36231 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36235 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36242 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 4,
     /*   36246 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36250 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36252 */     // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 4:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)  =>  (S_LSHL4_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL4_ADD_U32),
     /*   36255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36261 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   36263 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36266 */     GIR_RootConstrainSelectedInstOperands,
     /*   36267 */     // GIR_Coverage, 86,
     /*   36267 */     GIR_EraseRootFromParent_Done,
     /*   36268 */   // Label 273: @36268
     /*   36268 */   GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(36329), // Rule ID 31163 //
     /*   36273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36280 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36296 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36300 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36307 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /*   36311 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36313 */     // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 1:{ *:[i32] })<<P:Predicate_shl_oneuse>>)  =>  (S_LSHL1_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL1_ADD_U32),
     /*   36316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36318 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36322 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   36324 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36327 */     GIR_RootConstrainSelectedInstOperands,
     /*   36328 */     // GIR_Coverage, 31163,
     /*   36328 */     GIR_EraseRootFromParent_Done,
     /*   36329 */   // Label 274: @36329
     /*   36329 */   GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(36390), // Rule ID 31164 //
     /*   36334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36341 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36345 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36349 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36353 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36357 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36361 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36363 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36368 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2,
     /*   36372 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36374 */     // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 2:{ *:[i32] })<<P:Predicate_shl_oneuse>>)  =>  (S_LSHL2_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL2_ADD_U32),
     /*   36377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36379 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36383 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   36385 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36388 */     GIR_RootConstrainSelectedInstOperands,
     /*   36389 */     // GIR_Coverage, 31164,
     /*   36389 */     GIR_EraseRootFromParent_Done,
     /*   36390 */   // Label 275: @36390
     /*   36390 */   GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(36451), // Rule ID 31165 //
     /*   36395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36402 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36406 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36410 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36414 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36418 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36422 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36424 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36429 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3,
     /*   36433 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36435 */     // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 3:{ *:[i32] })<<P:Predicate_shl_oneuse>>)  =>  (S_LSHL3_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL3_ADD_U32),
     /*   36438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36440 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36444 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   36446 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36449 */     GIR_RootConstrainSelectedInstOperands,
     /*   36450 */     // GIR_Coverage, 31165,
     /*   36450 */     GIR_EraseRootFromParent_Done,
     /*   36451 */   // Label 276: @36451
     /*   36451 */   GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(36512), // Rule ID 31166 //
     /*   36456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   36459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36463 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36467 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36471 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   36475 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36479 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36483 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36485 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   36490 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 4,
     /*   36494 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36496 */     // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 4:{ *:[i32] })<<P:Predicate_shl_oneuse>>)  =>  (S_LSHL4_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   36496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL4_ADD_U32),
     /*   36499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   36501 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36505 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   36507 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   36510 */     GIR_RootConstrainSelectedInstOperands,
     /*   36511 */     // GIR_Coverage, 31166,
     /*   36511 */     GIR_EraseRootFromParent_Done,
     /*   36512 */   // Label 277: @36512
     /*   36512 */   GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(36677), // Rule ID 31365 //
     /*   36517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0),
     /*   36520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36524 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:17:z
     /*   36528 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36536 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   36540 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36544 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36548 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36550 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   36554 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   36558 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   36562 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36564 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:17:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   36564 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   36567 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   36571 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36576 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   36578 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   36581 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   36585 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36590 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   36594 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   36597 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   36600 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   36603 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   36608 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36613 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36618 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   36621 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   36624 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   36628 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36633 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   36638 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36642 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   36646 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   36649 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   36652 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   36654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   36657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   36659 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   36666 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36671 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   36676 */     // GIR_Coverage, 31365,
     /*   36676 */     GIR_EraseRootFromParent_Done,
     /*   36677 */   // Label 278: @36677
     /*   36677 */   GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(36842), // Rule ID 31366 //
     /*   36682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1),
     /*   36685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36689 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:17:z
     /*   36693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   36705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36709 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36713 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36715 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   36719 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   36723 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   36727 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36729 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:17:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   36729 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   36732 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   36736 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36741 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   36743 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   36746 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   36750 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36755 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   36759 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   36762 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   36765 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   36768 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   36773 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36778 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36783 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   36786 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   36789 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   36793 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36798 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   36803 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36807 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   36811 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   36814 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   36817 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   36819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   36822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   36824 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   36831 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36836 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   36841 */     // GIR_Coverage, 31366,
     /*   36841 */     GIR_EraseRootFromParent_Done,
     /*   36842 */   // Label 279: @36842
     /*   36842 */   GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(37007), // Rule ID 31367 //
     /*   36847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2),
     /*   36850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36854 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:17:z
     /*   36858 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   36866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   36870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   36874 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   36878 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   36880 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   36884 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   36888 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   36892 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   36894 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:17:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   36894 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   36897 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   36901 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36906 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   36908 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   36911 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   36915 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36920 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   36924 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   36927 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   36930 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   36933 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   36938 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36943 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   36948 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   36951 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   36954 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   36958 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   36963 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   36968 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   36972 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   36976 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   36979 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   36982 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   36984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   36987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   36989 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   36996 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37001 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37006 */     // GIR_Coverage, 31367,
     /*   37006 */     GIR_EraseRootFromParent_Done,
     /*   37007 */   // Label 280: @37007
     /*   37007 */   GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(37172), // Rule ID 31368 //
     /*   37012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3),
     /*   37015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37019 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:17:z
     /*   37023 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37027 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   37031 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   37035 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   37039 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   37043 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   37045 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   37049 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   37053 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   37057 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   37059 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:17:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   37059 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   37062 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   37066 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37071 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   37073 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   37076 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   37080 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37085 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   37089 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   37092 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   37095 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   37098 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37103 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37108 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37113 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   37116 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   37119 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   37123 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37128 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   37133 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   37137 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   37141 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   37144 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   37147 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   37149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   37152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   37154 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   37161 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37166 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37171 */     // GIR_Coverage, 31368,
     /*   37171 */     GIR_EraseRootFromParent_Done,
     /*   37172 */   // Label 281: @37172
     /*   37172 */   GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(37337), // Rule ID 31369 //
     /*   37177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4),
     /*   37180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37184 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:17:z
     /*   37188 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37192 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   37196 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   37200 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   37204 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   37208 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   37210 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   37214 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   37218 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   37222 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   37224 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:17:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   37224 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   37227 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   37231 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37236 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   37238 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   37241 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   37245 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37250 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   37254 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   37257 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   37260 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   37263 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37268 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37273 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37278 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   37281 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   37284 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   37288 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37293 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   37298 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   37302 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   37306 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   37309 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   37312 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   37314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   37317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   37319 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   37326 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37331 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37336 */     // GIR_Coverage, 31369,
     /*   37336 */     GIR_EraseRootFromParent_Done,
     /*   37337 */   // Label 282: @37337
     /*   37337 */   GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(37502), // Rule ID 31385 //
     /*   37342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0),
     /*   37345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37349 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:20:z
     /*   37353 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   37361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   37365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   37369 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   37373 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   37375 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   37379 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   37383 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   37387 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   37389 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:20:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   37389 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   37392 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   37396 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37401 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   37403 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   37406 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   37410 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37415 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   37419 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   37422 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   37425 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   37428 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37433 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37438 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37443 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   37446 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   37449 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   37453 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37458 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   37463 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   37467 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   37471 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   37474 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   37477 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   37479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   37482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   37484 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   37491 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37496 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37501 */     // GIR_Coverage, 31385,
     /*   37501 */     GIR_EraseRootFromParent_Done,
     /*   37502 */   // Label 283: @37502
     /*   37502 */   GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(37667), // Rule ID 31386 //
     /*   37507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1),
     /*   37510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37514 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:20:z
     /*   37518 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37522 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   37526 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   37530 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   37534 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   37538 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   37540 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   37544 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   37548 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   37552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   37554 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:20:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   37554 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   37557 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   37561 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   37568 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   37571 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   37575 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37580 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   37584 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   37587 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   37590 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   37593 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37598 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37603 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37608 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   37611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   37614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   37618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37623 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   37628 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   37632 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   37636 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   37639 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   37642 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   37644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   37647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   37649 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   37656 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37661 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37666 */     // GIR_Coverage, 31386,
     /*   37666 */     GIR_EraseRootFromParent_Done,
     /*   37667 */   // Label 284: @37667
     /*   37667 */   GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(37832), // Rule ID 31387 //
     /*   37672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2),
     /*   37675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37679 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:20:z
     /*   37683 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37687 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   37691 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   37695 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   37699 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   37703 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   37705 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   37709 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   37713 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   37717 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   37719 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:20:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   37719 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   37722 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   37726 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37731 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   37733 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   37736 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   37740 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37745 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   37749 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   37752 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   37755 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   37758 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37763 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37768 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37773 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   37776 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   37779 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   37783 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37788 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   37793 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   37797 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   37801 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   37804 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   37807 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   37809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   37812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   37814 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   37821 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37826 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37831 */     // GIR_Coverage, 31387,
     /*   37831 */     GIR_EraseRootFromParent_Done,
     /*   37832 */   // Label 285: @37832
     /*   37832 */   GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(37997), // Rule ID 31388 //
     /*   37837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3),
     /*   37840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37844 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:20:z
     /*   37848 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   37856 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   37860 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   37864 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   37868 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   37870 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   37874 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   37878 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   37882 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   37884 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:20:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   37884 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   37887 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   37891 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   37898 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   37901 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   37905 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37910 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   37914 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   37917 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   37920 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   37923 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37928 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37933 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37938 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   37941 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   37944 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   37948 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   37953 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   37958 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   37962 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   37966 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   37969 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   37972 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   37974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   37977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   37979 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   37986 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   37991 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   37996 */     // GIR_Coverage, 31388,
     /*   37996 */     GIR_EraseRootFromParent_Done,
     /*   37997 */   // Label 286: @37997
     /*   37997 */   GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(38162), // Rule ID 31389 //
     /*   38002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4),
     /*   38005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38009 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:20:z
     /*   38013 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   38021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   38025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38033 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38035 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   38039 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   38043 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   38047 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38049 */     // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:20:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   38049 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   38052 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   38056 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38061 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   38063 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   38066 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   38070 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38075 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   38079 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   38082 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   38085 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   38088 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38093 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38098 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38103 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   38106 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   38109 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   38113 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38118 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   38123 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   38127 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   38131 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   38134 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   38137 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   38139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   38142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   38144 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   38151 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38156 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38161 */     // GIR_Coverage, 31389,
     /*   38161 */     GIR_EraseRootFromParent_Done,
     /*   38162 */   // Label 287: @38162
     /*   38162 */   GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(38227), // Rule ID 7271 //
     /*   38167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   38170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   38178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   38182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38186 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38190 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38192 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x
     /*   38196 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
     /*   38200 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z
     /*   38204 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28485),
     /*   38208 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38210 */     // (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:3:x, i32:{ *:[i32] }:$src1:$pred:3:y)<<P:Predicate_anonymous_28483>>, i32:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_anonymous_28485>>  =>  (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   38210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64),
     /*   38213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   38215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   38219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   38223 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   38225 */     GIR_RootConstrainSelectedInstOperands,
     /*   38226 */     // GIR_Coverage, 7271,
     /*   38226 */     GIR_EraseRootFromParent_Done,
     /*   38227 */   // Label 288: @38227
     /*   38227 */   GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(38392), // Rule ID 7313 //
     /*   38232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0),
     /*   38235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   38243 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   38247 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38251 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38255 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38257 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   38261 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   38265 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:17:z
     /*   38269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38273 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   38277 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38279 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:17:z)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   38279 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   38282 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   38286 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38291 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   38293 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   38296 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   38300 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38305 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   38309 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   38312 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   38315 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   38318 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38323 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38328 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38333 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   38336 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   38339 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   38343 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38348 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   38353 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   38357 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   38361 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   38364 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   38367 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   38369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   38372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   38374 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   38381 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38386 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38391 */     // GIR_Coverage, 7313,
     /*   38391 */     GIR_EraseRootFromParent_Done,
     /*   38392 */   // Label 289: @38392
     /*   38392 */   GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(38557), // Rule ID 7314 //
     /*   38397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1),
     /*   38400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38404 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   38408 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   38412 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38416 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38420 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38422 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   38426 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   38430 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:17:z
     /*   38434 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38438 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   38442 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38444 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:17:z)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   38444 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   38447 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   38451 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38456 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   38458 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   38461 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   38465 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38470 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   38474 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   38477 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   38480 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   38483 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38488 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38493 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38498 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   38501 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   38504 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   38508 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38513 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   38518 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   38522 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   38526 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   38529 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   38532 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   38534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   38537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   38539 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   38546 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38551 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38556 */     // GIR_Coverage, 7314,
     /*   38556 */     GIR_EraseRootFromParent_Done,
     /*   38557 */   // Label 290: @38557
     /*   38557 */   GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(38722), // Rule ID 7315 //
     /*   38562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2),
     /*   38565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   38573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   38577 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38581 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38585 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38587 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   38591 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   38595 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:17:z
     /*   38599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38603 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   38607 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38609 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:17:z)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   38609 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   38612 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   38616 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38621 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   38623 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   38626 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   38630 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38635 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   38639 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   38642 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   38645 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   38648 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38653 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38658 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38663 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   38666 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   38669 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   38673 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38678 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   38683 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   38687 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   38691 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   38694 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   38697 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   38699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   38702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   38704 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   38711 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38716 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38721 */     // GIR_Coverage, 7315,
     /*   38721 */     GIR_EraseRootFromParent_Done,
     /*   38722 */   // Label 291: @38722
     /*   38722 */   GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(38887), // Rule ID 7316 //
     /*   38727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3),
     /*   38730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38734 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   38738 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   38742 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38746 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38750 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38752 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   38756 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   38760 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:17:z
     /*   38764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38768 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   38772 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38774 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:17:z)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   38774 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   38777 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   38781 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38786 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   38788 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   38791 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   38795 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38800 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   38804 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   38807 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   38810 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   38813 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38818 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38823 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38828 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   38831 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   38834 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   38838 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38843 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   38848 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   38852 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   38856 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   38859 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   38862 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   38864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   38867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   38869 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   38876 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38881 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38886 */     // GIR_Coverage, 7316,
     /*   38886 */     GIR_EraseRootFromParent_Done,
     /*   38887 */   // Label 292: @38887
     /*   38887 */   GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(39052), // Rule ID 7317 //
     /*   38892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4),
     /*   38895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38899 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   38903 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   38907 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   38911 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   38915 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   38917 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:17:x
     /*   38921 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:17:y
     /*   38925 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:17:z
     /*   38929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38933 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   38937 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   38939 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:17:x, i32:{ *:[i32] }:$src1:$pred:17:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:17:z)<<P:17:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   38939 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   38942 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   38946 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38951 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   38953 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   38956 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   38960 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   38965 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   38969 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   38972 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   38975 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   38978 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   38983 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38988 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   38993 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   38996 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   38999 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   39003 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39008 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39013 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   39017 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   39021 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   39024 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   39027 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   39029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   39032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   39034 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   39041 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39046 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39051 */     // GIR_Coverage, 7317,
     /*   39051 */     GIR_EraseRootFromParent_Done,
     /*   39052 */   // Label 293: @39052
     /*   39052 */   GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(39217), // Rule ID 7358 //
     /*   39057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0),
     /*   39060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   39068 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   39072 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   39076 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   39080 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   39082 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   39086 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   39090 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:20:z
     /*   39094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39098 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   39102 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   39104 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:20:z)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   39104 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   39107 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   39111 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39116 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   39118 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   39121 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   39125 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39130 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   39134 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   39137 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   39140 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   39143 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39148 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39153 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39158 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   39161 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   39164 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   39168 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39173 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39178 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   39182 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   39186 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   39189 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   39192 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   39194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   39197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   39199 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   39206 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39211 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39216 */     // GIR_Coverage, 7358,
     /*   39216 */     GIR_EraseRootFromParent_Done,
     /*   39217 */   // Label 294: @39217
     /*   39217 */   GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(39382), // Rule ID 7359 //
     /*   39222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1),
     /*   39225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39229 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   39233 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   39237 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   39241 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   39245 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   39247 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   39251 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   39255 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:20:z
     /*   39259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39263 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   39267 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   39269 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:20:z)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   39269 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   39272 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   39276 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39281 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   39283 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   39286 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   39290 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39295 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   39299 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   39302 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   39305 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   39308 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39313 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39318 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39323 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   39326 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   39329 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   39333 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39338 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39343 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   39347 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   39351 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   39354 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   39357 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   39359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   39362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   39364 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   39371 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39376 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39381 */     // GIR_Coverage, 7359,
     /*   39381 */     GIR_EraseRootFromParent_Done,
     /*   39382 */   // Label 295: @39382
     /*   39382 */   GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(39547), // Rule ID 7360 //
     /*   39387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2),
     /*   39390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   39398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   39402 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   39406 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   39410 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   39412 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   39416 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   39420 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:20:z
     /*   39424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39428 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   39432 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   39434 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:20:z)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   39434 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   39437 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   39441 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39446 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   39448 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   39451 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   39455 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39460 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   39464 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   39467 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   39470 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   39473 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39478 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39483 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39488 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   39491 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   39494 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   39498 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39503 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39508 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   39512 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   39516 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   39519 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   39522 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   39524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   39527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   39529 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   39536 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39541 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39546 */     // GIR_Coverage, 7360,
     /*   39546 */     GIR_EraseRootFromParent_Done,
     /*   39547 */   // Label 296: @39547
     /*   39547 */   GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(39712), // Rule ID 7361 //
     /*   39552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3),
     /*   39555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39559 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   39563 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   39567 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   39571 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   39575 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   39577 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   39581 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   39585 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:20:z
     /*   39589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39593 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   39597 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   39599 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:20:z)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   39599 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   39602 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   39606 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39611 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   39613 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   39616 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   39620 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39625 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   39629 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   39632 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   39635 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   39638 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39643 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39648 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39653 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   39656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   39659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   39663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39668 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39673 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   39677 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   39681 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   39684 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   39687 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   39689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   39692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   39694 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   39701 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39706 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39711 */     // GIR_Coverage, 7361,
     /*   39711 */     GIR_EraseRootFromParent_Done,
     /*   39712 */   // Label 297: @39712
     /*   39712 */   GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(39877), // Rule ID 7362 //
     /*   39717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4),
     /*   39720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   39728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   39732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   39736 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   39740 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   39742 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:20:x
     /*   39746 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:20:y
     /*   39750 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:20:z
     /*   39754 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39758 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   39762 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   39764 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:20:x, i32:{ *:[i32] }:$src1:$pred:20:y)<<P:Predicate_anonymous_28502>>, VGPR_32:{ *:[i32] }:$src2:$pred:20:z)<<P:20:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   39764 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   39767 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   39771 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39776 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   39778 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   39781 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   39785 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39790 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   39794 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   39797 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   39800 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   39803 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39808 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39813 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39818 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   39821 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   39824 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   39828 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39833 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39838 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   39842 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   39846 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   39849 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   39852 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   39854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   39857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   39859 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   39866 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39871 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   39876 */     // GIR_Coverage, 7362,
     /*   39876 */     GIR_EraseRootFromParent_Done,
     /*   39877 */   // Label 298: @39877
     /*   39877 */   GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(40038), // Rule ID 7308 //
     /*   39882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0),
     /*   39885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   39889 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   39893 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   39897 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   39901 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   39905 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   39907 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   39911 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   39915 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:16:z
     /*   39919 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   39923 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   39925 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:16:z)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   39925 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   39928 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   39932 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39937 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   39939 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   39942 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   39946 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39951 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   39955 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   39958 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   39961 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   39964 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   39969 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   39974 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   39979 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   39982 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   39985 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   39989 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   39994 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   39999 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40003 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40007 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40010 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40013 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40020 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40027 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40032 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   40037 */     // GIR_Coverage, 7308,
     /*   40037 */     GIR_EraseRootFromParent_Done,
     /*   40038 */   // Label 299: @40038
     /*   40038 */   GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(40199), // Rule ID 7309 //
     /*   40043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1),
     /*   40046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40050 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   40054 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   40058 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   40062 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   40066 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   40068 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   40072 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   40076 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:16:z
     /*   40080 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   40084 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   40086 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:16:z)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   40086 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   40089 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   40093 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40098 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   40100 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   40103 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   40107 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40112 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   40116 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   40119 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   40122 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   40125 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   40130 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   40135 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   40140 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   40143 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   40146 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   40150 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40155 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   40160 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40164 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40168 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40171 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40174 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40181 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40188 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40193 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   40198 */     // GIR_Coverage, 7309,
     /*   40198 */     GIR_EraseRootFromParent_Done,
     /*   40199 */   // Label 300: @40199
     /*   40199 */   GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(40360), // Rule ID 7310 //
     /*   40204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2),
     /*   40207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40211 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   40215 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   40219 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   40223 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   40227 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   40229 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   40233 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   40237 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:16:z
     /*   40241 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   40245 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   40247 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:16:z)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   40247 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   40250 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   40254 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40259 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   40261 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   40264 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   40268 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40273 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   40277 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   40280 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   40283 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   40286 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   40291 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   40296 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   40301 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   40304 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   40307 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   40311 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40316 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   40321 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40325 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40329 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40332 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40335 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40342 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40349 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40354 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   40359 */     // GIR_Coverage, 7310,
     /*   40359 */     GIR_EraseRootFromParent_Done,
     /*   40360 */   // Label 301: @40360
     /*   40360 */   GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(40521), // Rule ID 7311 //
     /*   40365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3),
     /*   40368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   40376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   40380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   40384 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   40388 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   40390 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   40394 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   40398 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:16:z
     /*   40402 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   40406 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   40408 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:16:z)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   40408 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   40411 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   40415 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40420 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   40422 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   40425 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   40429 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40434 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   40438 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   40441 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   40444 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   40447 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   40452 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   40457 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   40462 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   40465 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   40468 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   40472 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40477 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   40482 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40486 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40490 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40493 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40496 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40503 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40510 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40515 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   40520 */     // GIR_Coverage, 7311,
     /*   40520 */     GIR_EraseRootFromParent_Done,
     /*   40521 */   // Label 302: @40521
     /*   40521 */   GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(40682), // Rule ID 7312 //
     /*   40526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4),
     /*   40529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40533 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   40537 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   40541 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   40545 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   40549 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   40551 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   40555 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   40559 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:16:z
     /*   40563 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   40567 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   40569 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:16:z)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   40569 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   40572 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   40576 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40581 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   40583 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   40586 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   40590 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40595 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   40599 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   40602 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   40605 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   40608 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   40613 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   40618 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   40623 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   40626 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   40629 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   40633 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40638 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   40643 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40647 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40651 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40654 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40657 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40664 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40671 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40676 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   40681 */     // GIR_Coverage, 7312,
     /*   40681 */     GIR_EraseRootFromParent_Done,
     /*   40682 */   // Label 303: @40682
     /*   40682 */   GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(40843), // Rule ID 7353 //
     /*   40687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0),
     /*   40690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   40698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   40702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   40706 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   40710 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   40712 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   40716 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   40720 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:19:z
     /*   40724 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   40728 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   40730 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:19:z)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   40730 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   40733 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   40737 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40742 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   40744 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   40747 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   40751 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40756 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   40760 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   40763 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   40766 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   40769 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   40774 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   40779 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   40784 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   40787 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   40790 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   40794 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40799 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   40804 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40808 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40812 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40815 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40818 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40825 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40832 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40837 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   40842 */     // GIR_Coverage, 7353,
     /*   40842 */     GIR_EraseRootFromParent_Done,
     /*   40843 */   // Label 304: @40843
     /*   40843 */   GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(41004), // Rule ID 7354 //
     /*   40848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1),
     /*   40851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40855 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   40859 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   40863 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   40867 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   40871 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   40873 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   40877 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   40881 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:19:z
     /*   40885 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   40889 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   40891 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:19:z)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   40891 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   40894 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   40898 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40903 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   40905 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   40908 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   40912 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40917 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   40921 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   40924 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   40927 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   40930 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   40935 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   40940 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   40945 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   40948 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   40951 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   40955 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   40960 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   40965 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   40969 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   40973 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   40976 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   40979 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   40981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   40984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   40986 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   40993 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   40998 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   41003 */     // GIR_Coverage, 7354,
     /*   41003 */     GIR_EraseRootFromParent_Done,
     /*   41004 */   // Label 305: @41004
     /*   41004 */   GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(41165), // Rule ID 7355 //
     /*   41009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2),
     /*   41012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41016 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   41020 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   41024 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41028 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41032 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41034 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   41038 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   41042 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:19:z
     /*   41046 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   41050 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41052 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:19:z)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   41052 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   41055 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   41059 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41064 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   41066 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   41069 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   41073 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41078 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   41082 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   41085 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   41088 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   41091 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   41096 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   41101 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   41106 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   41109 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   41112 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   41116 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41121 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   41126 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41130 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41134 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   41137 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   41140 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   41142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   41145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   41147 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   41154 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41159 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   41164 */     // GIR_Coverage, 7355,
     /*   41164 */     GIR_EraseRootFromParent_Done,
     /*   41165 */   // Label 306: @41165
     /*   41165 */   GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(41326), // Rule ID 7356 //
     /*   41170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3),
     /*   41173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   41181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   41185 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41189 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41193 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41195 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   41199 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   41203 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:19:z
     /*   41207 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   41211 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41213 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:19:z)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   41213 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   41216 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   41220 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41225 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   41227 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   41230 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   41234 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41239 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   41243 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   41246 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   41249 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   41252 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   41257 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   41262 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   41267 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   41270 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   41273 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   41277 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41282 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   41287 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41291 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41295 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   41298 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   41301 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   41303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   41306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   41308 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   41315 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41320 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   41325 */     // GIR_Coverage, 7356,
     /*   41325 */     GIR_EraseRootFromParent_Done,
     /*   41326 */   // Label 307: @41326
     /*   41326 */   GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(41487), // Rule ID 7357 //
     /*   41331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4),
     /*   41334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41338 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   41342 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   41346 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41350 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41354 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41356 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   41360 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   41364 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:19:z
     /*   41368 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   41372 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41374 */     // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>, i32:{ *:[i32] }:$src2:$pred:19:z)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   41374 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   41377 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   41381 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41386 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   41388 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   41391 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   41395 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41400 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2
     /*   41404 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   41407 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   41410 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   41413 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   41418 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   41423 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   41428 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   41431 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   41434 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   41438 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41443 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   41448 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41452 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41456 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   41459 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   41462 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   41464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   41467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   41469 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   41476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41481 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   41486 */     // GIR_Coverage, 7357,
     /*   41486 */     GIR_EraseRootFromParent_Done,
     /*   41487 */   // Label 308: @41487
     /*   41487 */   GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(41552), // Rule ID 7267 //
     /*   41492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   41495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   41503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   41507 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41511 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41515 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41517 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
     /*   41521 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y
     /*   41525 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z
     /*   41529 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28479),
     /*   41533 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41535 */     // (add:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y)<<P:Predicate_anonymous_28480>>, i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_anonymous_28479>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   41535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
     /*   41538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   41540 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41544 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41548 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   41550 */     GIR_RootConstrainSelectedInstOperands,
     /*   41551 */     // GIR_Coverage, 7267,
     /*   41551 */     GIR_EraseRootFromParent_Done,
     /*   41552 */   // Label 309: @41552
     /*   41552 */   GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(41617), // Rule ID 7277 //
     /*   41557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   41560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41564 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   41568 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   41572 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41576 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41580 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41582 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x
     /*   41586 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y
     /*   41590 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:8:z
     /*   41594 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28498),
     /*   41598 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41600 */     // (add:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:8:x, i32:{ *:[i32] }:$src1:$pred:8:y)<<P:Predicate_anonymous_28499>>, i32:{ *:[i32] }:$src2:$pred:8:z)<<P:8:Predicate_anonymous_28498>>  =>  (V_XAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   41600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XAD_U32_e64),
     /*   41603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   41605 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41613 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   41615 */     GIR_RootConstrainSelectedInstOperands,
     /*   41616 */     // GIR_Coverage, 7277,
     /*   41616 */     GIR_EraseRootFromParent_Done,
     /*   41617 */   // Label 310: @41617
     /*   41617 */   GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(41657), // Rule ID 27515 //
     /*   41622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41626 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   41630 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP),
     /*   41634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41638 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_44477),
     /*   41642 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41644 */     // (add:{ *:[i32] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$popcnt)<<P:Predicate_anonymous_44477>>, i32:{ *:[i32] }:$val)  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$popcnt, ?:{ *:[i32] }:$val)
     /*   41644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
     /*   41647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   41649 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // popcnt
     /*   41653 */     GIR_RootToRootCopy, /*OpIdx*/2, // val
     /*   41655 */     GIR_RootConstrainSelectedInstOperands,
     /*   41656 */     // GIR_Coverage, 27515,
     /*   41656 */     GIR_EraseRootFromParent_Done,
     /*   41657 */   // Label 311: @41657
     /*   41657 */   GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(41722), // Rule ID 31343 //
     /*   41662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   41665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41669 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z
     /*   41673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   41677 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   41681 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41685 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41689 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41691 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x
     /*   41695 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
     /*   41699 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28485),
     /*   41703 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41705 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:3:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:3:x, i32:{ *:[i32] }:$src1:$pred:3:y)<<P:Predicate_anonymous_28483>>)<<P:3:Predicate_anonymous_28485>>  =>  (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   41705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64),
     /*   41708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   41710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41718 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   41720 */     GIR_RootConstrainSelectedInstOperands,
     /*   41721 */     // GIR_Coverage, 31343,
     /*   41721 */     GIR_EraseRootFromParent_Done,
     /*   41722 */   // Label 312: @41722
     /*   41722 */   GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(41883), // Rule ID 31360 //
     /*   41727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0),
     /*   41730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41734 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:16:z
     /*   41738 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   41742 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   41746 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41750 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41754 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41756 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   41760 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   41764 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   41768 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41770 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:16:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   41770 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   41773 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   41777 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41782 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   41784 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   41787 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   41791 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41796 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   41800 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   41803 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   41806 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   41809 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   41814 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   41819 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   41824 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   41827 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   41830 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   41834 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41839 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   41844 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   41848 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   41852 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   41855 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   41858 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   41860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   41863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   41865 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   41872 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41877 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   41882 */     // GIR_Coverage, 31360,
     /*   41882 */     GIR_EraseRootFromParent_Done,
     /*   41883 */   // Label 313: @41883
     /*   41883 */   GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(42044), // Rule ID 31361 //
     /*   41888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1),
     /*   41891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   41895 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:16:z
     /*   41899 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   41903 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   41907 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   41911 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   41915 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   41917 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   41921 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   41925 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   41929 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   41931 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:16:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   41931 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   41934 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   41938 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41943 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   41945 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   41948 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   41952 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   41957 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   41961 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   41964 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   41967 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   41970 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   41975 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   41980 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   41985 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   41988 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   41991 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   41995 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42000 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42005 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42009 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42013 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42016 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42019 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42026 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42033 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42038 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   42043 */     // GIR_Coverage, 31361,
     /*   42043 */     GIR_EraseRootFromParent_Done,
     /*   42044 */   // Label 314: @42044
     /*   42044 */   GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(42205), // Rule ID 31362 //
     /*   42049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2),
     /*   42052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42056 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:16:z
     /*   42060 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   42064 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   42068 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   42072 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   42076 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   42078 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   42082 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   42086 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   42090 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   42092 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:16:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   42092 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   42095 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   42099 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42104 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   42106 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   42109 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   42113 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42118 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   42122 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   42125 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   42128 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   42131 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   42136 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   42141 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   42146 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   42149 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   42152 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   42156 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42161 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42166 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42170 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42174 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42177 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42180 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42187 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42194 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42199 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   42204 */     // GIR_Coverage, 31362,
     /*   42204 */     GIR_EraseRootFromParent_Done,
     /*   42205 */   // Label 315: @42205
     /*   42205 */   GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(42366), // Rule ID 31363 //
     /*   42210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3),
     /*   42213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42217 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:16:z
     /*   42221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   42225 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   42229 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   42233 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   42237 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   42239 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   42243 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   42247 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   42251 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   42253 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:16:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   42253 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   42256 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   42260 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42265 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   42267 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   42270 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   42274 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42279 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   42283 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   42286 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   42289 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   42292 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   42297 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   42302 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   42307 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   42310 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   42313 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   42317 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42322 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42327 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42331 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42335 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42338 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42341 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42348 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42355 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42360 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   42365 */     // GIR_Coverage, 31363,
     /*   42365 */     GIR_EraseRootFromParent_Done,
     /*   42366 */   // Label 316: @42366
     /*   42366 */   GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(42527), // Rule ID 31364 //
     /*   42371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4),
     /*   42374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42378 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:16:z
     /*   42382 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   42386 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   42390 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   42394 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   42398 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   42400 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x
     /*   42404 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y
     /*   42408 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   42412 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   42414 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:16:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_28502>>)<<P:16:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   42414 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   42417 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   42421 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42426 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   42428 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   42431 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   42435 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42440 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   42444 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   42447 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   42450 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   42453 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   42458 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   42463 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   42468 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   42471 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   42474 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   42478 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42483 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42488 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42492 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42496 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42499 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42502 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42509 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42516 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42521 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   42526 */     // GIR_Coverage, 31364,
     /*   42526 */     GIR_EraseRootFromParent_Done,
     /*   42527 */   // Label 317: @42527
     /*   42527 */   GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(42688), // Rule ID 31380 //
     /*   42532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0),
     /*   42535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42539 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:19:z
     /*   42543 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   42547 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   42551 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   42555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   42559 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   42561 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   42565 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   42569 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   42573 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   42575 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:19:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   42575 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   42578 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   42582 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42587 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   42589 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   42592 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   42596 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42601 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   42605 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   42608 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   42611 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   42614 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   42619 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   42624 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   42629 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   42632 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   42635 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   42639 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42644 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42649 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42653 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42657 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42660 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42663 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42670 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42677 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42682 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   42687 */     // GIR_Coverage, 31380,
     /*   42687 */     GIR_EraseRootFromParent_Done,
     /*   42688 */   // Label 318: @42688
     /*   42688 */   GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(42849), // Rule ID 31381 //
     /*   42693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1),
     /*   42696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42700 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:19:z
     /*   42704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   42708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   42712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   42716 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   42720 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   42722 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   42726 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   42730 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   42734 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   42736 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:19:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   42736 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   42739 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   42743 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42748 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   42750 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   42753 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   42757 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42762 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   42766 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   42769 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   42772 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   42775 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   42780 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   42785 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   42790 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   42793 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   42796 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   42800 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42805 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42810 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42814 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42818 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42821 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42824 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42831 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42838 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42843 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   42848 */     // GIR_Coverage, 31381,
     /*   42848 */     GIR_EraseRootFromParent_Done,
     /*   42849 */   // Label 319: @42849
     /*   42849 */   GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(43010), // Rule ID 31382 //
     /*   42854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2),
     /*   42857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   42861 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:19:z
     /*   42865 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   42869 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   42873 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   42877 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   42881 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   42883 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   42887 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   42891 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   42895 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   42897 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:19:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   42897 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   42900 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   42904 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42909 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   42911 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   42914 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   42918 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42923 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   42927 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   42930 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   42933 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   42936 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   42941 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   42946 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   42951 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   42954 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   42957 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   42961 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   42966 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   42971 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   42975 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   42979 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   42982 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   42985 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   42987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   42990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   42992 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   42999 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43004 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   43009 */     // GIR_Coverage, 31382,
     /*   43009 */     GIR_EraseRootFromParent_Done,
     /*   43010 */   // Label 320: @43010
     /*   43010 */   GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(43171), // Rule ID 31383 //
     /*   43015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3),
     /*   43018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43022 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:19:z
     /*   43026 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43030 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   43034 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   43038 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   43042 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   43044 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   43048 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   43052 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   43056 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43058 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:19:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   43058 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   43061 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   43065 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   43070 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   43072 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   43075 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   43079 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   43084 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   43088 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   43091 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   43094 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   43097 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   43102 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   43107 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   43112 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   43115 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   43118 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   43122 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   43127 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43132 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   43136 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   43140 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   43143 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   43146 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   43148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   43151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   43153 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   43160 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43165 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   43170 */     // GIR_Coverage, 31383,
     /*   43170 */     GIR_EraseRootFromParent_Done,
     /*   43171 */   // Label 321: @43171
     /*   43171 */   GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(43332), // Rule ID 31384 //
     /*   43176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4),
     /*   43179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43183 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:19:z
     /*   43187 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43191 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   43195 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   43199 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   43203 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   43205 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:19:x
     /*   43209 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:19:y
     /*   43213 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28501),
     /*   43217 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43219 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:19:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:19:x, i32:{ *:[i32] }:$src1:$pred:19:y)<<P:Predicate_anonymous_28502>>)<<P:19:Predicate_anonymous_28501>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] })
     /*   43219 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   43222 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   43226 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   43231 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   43233 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   43236 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   43240 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   43245 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2
     /*   43249 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /*   43252 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   43255 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /*   43258 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   43263 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   43268 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   43273 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   43276 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   43279 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   43283 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   43288 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43293 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   43297 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   43301 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   43304 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   43307 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   43309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   43312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   43314 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*   43321 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43326 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   43331 */     // GIR_Coverage, 31384,
     /*   43331 */     GIR_EraseRootFromParent_Done,
     /*   43332 */   // Label 322: @43332
     /*   43332 */   GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(43397), // Rule ID 31341 //
     /*   43337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   43340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43344 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:1:z
     /*   43348 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43352 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   43356 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   43360 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   43364 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   43366 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
     /*   43370 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y
     /*   43374 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28479),
     /*   43378 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43380 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:1:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y)<<P:Predicate_anonymous_28480>>)<<P:1:Predicate_anonymous_28479>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   43380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
     /*   43383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   43389 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   43393 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   43395 */     GIR_RootConstrainSelectedInstOperands,
     /*   43396 */     // GIR_Coverage, 31341,
     /*   43396 */     GIR_EraseRootFromParent_Done,
     /*   43397 */   // Label 323: @43397
     /*   43397 */   GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(43462), // Rule ID 31348 //
     /*   43402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   43405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43409 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:8:z
     /*   43413 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43417 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   43421 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   43425 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   43429 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   43431 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x
     /*   43435 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y
     /*   43439 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28498),
     /*   43443 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43445 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:8:z, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:8:x, i32:{ *:[i32] }:$src1:$pred:8:y)<<P:Predicate_anonymous_28499>>)<<P:8:Predicate_anonymous_28498>>  =>  (V_XAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   43445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XAD_U32_e64),
     /*   43448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43450 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   43454 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   43458 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   43460 */     GIR_RootConstrainSelectedInstOperands,
     /*   43461 */     // GIR_Coverage, 31348,
     /*   43461 */     GIR_EraseRootFromParent_Done,
     /*   43462 */   // Label 324: @43462
     /*   43462 */   GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(43502), // Rule ID 34049 //
     /*   43467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43471 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43475 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP),
     /*   43479 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   43483 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_44477),
     /*   43487 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43489 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$val, (ctpop:{ *:[i32] } i32:{ *:[i32] }:$popcnt)<<P:Predicate_anonymous_44477>>)  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$popcnt, ?:{ *:[i32] }:$val)
     /*   43489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
     /*   43492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // popcnt
     /*   43498 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /*   43500 */     GIR_RootConstrainSelectedInstOperands,
     /*   43501 */     // GIR_Coverage, 34049,
     /*   43501 */     GIR_EraseRootFromParent_Done,
     /*   43502 */   // Label 325: @43502
     /*   43502 */   GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(43546), // Rule ID 28485 //
     /*   43507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   43511 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43515 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43519 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43523 */     // MIs[1] Operand 1
     /*   43523 */     // No operand predicates
     /*   43523 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20771),
     /*   43527 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43529 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_20771>>  =>  (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i1 i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_I32),
     /*   43532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   43534 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43536 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43541 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   43544 */     GIR_RootConstrainSelectedInstOperands,
     /*   43545 */     // GIR_Coverage, 28485,
     /*   43545 */     GIR_EraseRootFromParent_Done,
     /*   43546 */   // Label 326: @43546
     /*   43546 */   GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(43593), // Rule ID 28486 //
     /*   43551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
     /*   43554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43566 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43570 */     // MIs[1] Operand 1
     /*   43570 */     // No operand predicates
     /*   43570 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43576 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_SUB_U32_e64:{ *:[i32] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64),
     /*   43579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43581 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43583 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43591 */     GIR_RootConstrainSelectedInstOperands,
     /*   43592 */     // GIR_Coverage, 28486,
     /*   43592 */     GIR_EraseRootFromParent_Done,
     /*   43593 */   // Label 327: @43593
     /*   43593 */   GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(43648), // Rule ID 28487 //
     /*   43598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts_HwMode0),
     /*   43601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43613 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43617 */     // MIs[1] Operand 1
     /*   43617 */     // No operand predicates
     /*   43617 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43621 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43623 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43623 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   43629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43631 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43636 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43638 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43646 */     GIR_RootConstrainSelectedInstOperands,
     /*   43647 */     // GIR_Coverage, 28487,
     /*   43647 */     GIR_EraseRootFromParent_Done,
     /*   43648 */   // Label 328: @43648
     /*   43648 */   GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(43703), // Rule ID 28488 //
     /*   43653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts_HwMode1),
     /*   43656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43668 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43672 */     // MIs[1] Operand 1
     /*   43672 */     // No operand predicates
     /*   43672 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43676 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43678 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43678 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   43684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43686 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43691 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43693 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43701 */     GIR_RootConstrainSelectedInstOperands,
     /*   43702 */     // GIR_Coverage, 28488,
     /*   43702 */     GIR_EraseRootFromParent_Done,
     /*   43703 */   // Label 329: @43703
     /*   43703 */   GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(43758), // Rule ID 28489 //
     /*   43708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts_HwMode2),
     /*   43711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43719 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43723 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43727 */     // MIs[1] Operand 1
     /*   43727 */     // No operand predicates
     /*   43727 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43731 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43733 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43733 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   43739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43741 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43746 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43748 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43756 */     GIR_RootConstrainSelectedInstOperands,
     /*   43757 */     // GIR_Coverage, 28489,
     /*   43757 */     GIR_EraseRootFromParent_Done,
     /*   43758 */   // Label 330: @43758
     /*   43758 */   GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(43813), // Rule ID 28490 //
     /*   43763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts_HwMode3),
     /*   43766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43778 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43782 */     // MIs[1] Operand 1
     /*   43782 */     // No operand predicates
     /*   43782 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43786 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43788 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43788 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   43794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43796 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43801 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43803 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43811 */     GIR_RootConstrainSelectedInstOperands,
     /*   43812 */     // GIR_Coverage, 28490,
     /*   43812 */     GIR_EraseRootFromParent_Done,
     /*   43813 */   // Label 331: @43813
     /*   43813 */   GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(43868), // Rule ID 28491 //
     /*   43818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts_HwMode4),
     /*   43821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43825 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   43829 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   43833 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
     /*   43837 */     // MIs[1] Operand 1
     /*   43837 */     // No operand predicates
     /*   43837 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43841 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   43843 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
     /*   43843 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   43849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43851 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43856 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43858 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*   43863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43866 */     GIR_RootConstrainSelectedInstOperands,
     /*   43867 */     // GIR_Coverage, 28491,
     /*   43867 */     GIR_EraseRootFromParent_Done,
     /*   43868 */   // Label 332: @43868
     /*   43868 */   GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(43902), // Rule ID 43 //
     /*   43873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   43877 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   43881 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   43885 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20771),
     /*   43889 */     // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20771>>  =>  (S_ADD_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   43889 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_I32),
     /*   43894 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   43900 */     GIR_RootConstrainSelectedInstOperands,
     /*   43901 */     // GIR_Coverage, 43,
     /*   43901 */     GIR_Done,
     /*   43902 */   // Label 333: @43902
     /*   43902 */   GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(43932), // Rule ID 7121 //
     /*   43907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
     /*   43910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43914 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43918 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   43918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U32_e64),
     /*   43921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43923 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43925 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   43927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43930 */     GIR_RootConstrainSelectedInstOperands,
     /*   43931 */     // GIR_Coverage, 7121,
     /*   43931 */     GIR_EraseRootFromParent_Done,
     /*   43932 */   // Label 334: @43932
     /*   43932 */   GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(43970), // Rule ID 7123 //
     /*   43937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode0),
     /*   43940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43944 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43948 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   43948 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
     /*   43954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43956 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43961 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   43963 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   43965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   43968 */     GIR_RootConstrainSelectedInstOperands,
     /*   43969 */     // GIR_Coverage, 7123,
     /*   43969 */     GIR_EraseRootFromParent_Done,
     /*   43970 */   // Label 335: @43970
     /*   43970 */   GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(44008), // Rule ID 7124 //
     /*   43975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode1),
     /*   43978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   43982 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   43986 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   43986 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   43989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
     /*   43992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   43994 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   43999 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   44001 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   44003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44006 */     GIR_RootConstrainSelectedInstOperands,
     /*   44007 */     // GIR_Coverage, 7124,
     /*   44007 */     GIR_EraseRootFromParent_Done,
     /*   44008 */   // Label 336: @44008
     /*   44008 */   GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(44046), // Rule ID 7125 //
     /*   44013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode2),
     /*   44016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   44020 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   44024 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   44024 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
     /*   44030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44032 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44037 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   44039 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   44041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44044 */     GIR_RootConstrainSelectedInstOperands,
     /*   44045 */     // GIR_Coverage, 7125,
     /*   44045 */     GIR_EraseRootFromParent_Done,
     /*   44046 */   // Label 337: @44046
     /*   44046 */   GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(44084), // Rule ID 7126 //
     /*   44051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode3),
     /*   44054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   44058 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   44062 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   44062 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
     /*   44068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44070 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44075 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   44077 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   44079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44082 */     GIR_RootConstrainSelectedInstOperands,
     /*   44083 */     // GIR_Coverage, 7126,
     /*   44083 */     GIR_EraseRootFromParent_Done,
     /*   44084 */   // Label 338: @44084
     /*   44084 */   GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(44122), // Rule ID 7127 //
     /*   44089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode4),
     /*   44092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   44096 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   44100 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   44100 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
     /*   44106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44108 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44113 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   44115 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   44117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44120 */     GIR_RootConstrainSelectedInstOperands,
     /*   44121 */     // GIR_Coverage, 7127,
     /*   44121 */     GIR_EraseRootFromParent_Done,
     /*   44122 */   // Label 339: @44122
     /*   44122 */   GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(44158), // Rule ID 2630 //
     /*   44127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   44131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP),
     /*   44139 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   44143 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44145 */     // (add:{ *:[i32] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   44145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
     /*   44148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   44154 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   44156 */     GIR_RootConstrainSelectedInstOperands,
     /*   44157 */     // GIR_Coverage, 2630,
     /*   44157 */     GIR_EraseRootFromParent_Done,
     /*   44158 */   // Label 340: @44158
     /*   44158 */   GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(44194), // Rule ID 31178 //
     /*   44163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   44167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   44171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP),
     /*   44175 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   44179 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44181 */     // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   44181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
     /*   44184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   44190 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   44192 */     GIR_RootConstrainSelectedInstOperands,
     /*   44193 */     // GIR_Coverage, 31178,
     /*   44193 */     GIR_EraseRootFromParent_Done,
     /*   44194 */   // Label 341: @44194
     /*   44194 */   GIM_Reject,
     /*   44195 */ // Label 209: @44195
     /*   44195 */ GIM_Reject,
     /*   44196 */ // Label 182: @44196
     /*   44196 */ GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(46409),
     /*   44201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   44204 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   44207 */   GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(44273), // Rule ID 7323 //
     /*   44212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0),
     /*   44215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44227 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44230 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44239 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44243 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44245 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44245 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44253 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44266 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44271 */     GIR_RootConstrainSelectedInstOperands,
     /*   44272 */     // GIR_Coverage, 7323,
     /*   44272 */     GIR_EraseRootFromParent_Done,
     /*   44273 */   // Label 343: @44273
     /*   44273 */   GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(44339), // Rule ID 7324 //
     /*   44278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1),
     /*   44281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44293 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44296 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44301 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44305 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44309 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44311 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44311 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44319 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44324 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44328 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44332 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44337 */     GIR_RootConstrainSelectedInstOperands,
     /*   44338 */     // GIR_Coverage, 7324,
     /*   44338 */     GIR_EraseRootFromParent_Done,
     /*   44339 */   // Label 344: @44339
     /*   44339 */   GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(44405), // Rule ID 7325 //
     /*   44344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2),
     /*   44347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44359 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44362 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44367 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44371 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44375 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44377 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44377 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44385 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44398 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44403 */     GIR_RootConstrainSelectedInstOperands,
     /*   44404 */     // GIR_Coverage, 7325,
     /*   44404 */     GIR_EraseRootFromParent_Done,
     /*   44405 */   // Label 345: @44405
     /*   44405 */   GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(44471), // Rule ID 7326 //
     /*   44410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3),
     /*   44413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44417 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44421 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44425 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44428 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44433 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44437 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44441 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44443 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44443 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44451 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44456 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44460 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44464 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44469 */     GIR_RootConstrainSelectedInstOperands,
     /*   44470 */     // GIR_Coverage, 7326,
     /*   44470 */     GIR_EraseRootFromParent_Done,
     /*   44471 */   // Label 346: @44471
     /*   44471 */   GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(44537), // Rule ID 7327 //
     /*   44476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4),
     /*   44479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44483 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44487 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44491 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44494 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44503 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44507 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44509 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44509 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44517 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44526 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44530 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44535 */     GIR_RootConstrainSelectedInstOperands,
     /*   44536 */     // GIR_Coverage, 7327,
     /*   44536 */     GIR_EraseRootFromParent_Done,
     /*   44537 */   // Label 347: @44537
     /*   44537 */   GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(44603), // Rule ID 7368 //
     /*   44542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0),
     /*   44545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44553 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44557 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44560 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44565 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44569 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44573 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44575 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44575 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   44581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44583 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44588 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44596 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44601 */     GIR_RootConstrainSelectedInstOperands,
     /*   44602 */     // GIR_Coverage, 7368,
     /*   44602 */     GIR_EraseRootFromParent_Done,
     /*   44603 */   // Label 348: @44603
     /*   44603 */   GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(44669), // Rule ID 7369 //
     /*   44608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1),
     /*   44611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44615 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44619 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44623 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44626 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44631 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44635 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44639 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44641 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44641 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   44647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44649 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44654 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44658 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44662 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44667 */     GIR_RootConstrainSelectedInstOperands,
     /*   44668 */     // GIR_Coverage, 7369,
     /*   44668 */     GIR_EraseRootFromParent_Done,
     /*   44669 */   // Label 349: @44669
     /*   44669 */   GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(44735), // Rule ID 7370 //
     /*   44674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2),
     /*   44677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44681 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44685 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44689 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44692 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44697 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44701 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44705 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44707 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44707 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   44713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44715 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44720 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44724 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44728 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44733 */     GIR_RootConstrainSelectedInstOperands,
     /*   44734 */     // GIR_Coverage, 7370,
     /*   44734 */     GIR_EraseRootFromParent_Done,
     /*   44735 */   // Label 350: @44735
     /*   44735 */   GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(44801), // Rule ID 7371 //
     /*   44740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3),
     /*   44743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44747 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44751 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44755 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44758 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44763 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44767 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44771 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44773 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44773 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   44779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44781 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44786 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44794 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44799 */     GIR_RootConstrainSelectedInstOperands,
     /*   44800 */     // GIR_Coverage, 7371,
     /*   44800 */     GIR_EraseRootFromParent_Done,
     /*   44801 */   // Label 351: @44801
     /*   44801 */   GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(44867), // Rule ID 7372 //
     /*   44806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4),
     /*   44809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   44817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44821 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44824 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44829 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44833 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44837 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44839 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i64:{ *:[i64] }:$src2)  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44839 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   44845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44847 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44856 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44860 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   44862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44865 */     GIR_RootConstrainSelectedInstOperands,
     /*   44866 */     // GIR_Coverage, 7372,
     /*   44866 */     GIR_EraseRootFromParent_Done,
     /*   44867 */   // Label 352: @44867
     /*   44867 */   GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(44933), // Rule ID 31370 //
     /*   44872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode0),
     /*   44875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   44883 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44887 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44890 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44895 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44899 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44903 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44905 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44905 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44913 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44926 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   44928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44931 */     GIR_RootConstrainSelectedInstOperands,
     /*   44932 */     // GIR_Coverage, 31370,
     /*   44932 */     GIR_EraseRootFromParent_Done,
     /*   44933 */   // Label 353: @44933
     /*   44933 */   GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(44999), // Rule ID 31371 //
     /*   44938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode1),
     /*   44941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   44945 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   44949 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   44953 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   44956 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   44961 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   44965 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   44969 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   44971 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   44971 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   44974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   44977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   44979 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   44984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   44988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   44992 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   44994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   44997 */     GIR_RootConstrainSelectedInstOperands,
     /*   44998 */     // GIR_Coverage, 31371,
     /*   44998 */     GIR_EraseRootFromParent_Done,
     /*   44999 */   // Label 354: @44999
     /*   44999 */   GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(45065), // Rule ID 31372 //
     /*   45004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode2),
     /*   45007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45019 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45022 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45027 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45031 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45035 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45037 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45037 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   45043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45045 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45050 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45054 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45058 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45063 */     GIR_RootConstrainSelectedInstOperands,
     /*   45064 */     // GIR_Coverage, 31372,
     /*   45064 */     GIR_EraseRootFromParent_Done,
     /*   45065 */   // Label 355: @45065
     /*   45065 */   GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(45131), // Rule ID 31373 //
     /*   45070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode3),
     /*   45073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45085 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45088 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45093 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45097 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45101 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45103 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45103 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   45109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45111 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45116 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45120 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45124 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45129 */     GIR_RootConstrainSelectedInstOperands,
     /*   45130 */     // GIR_Coverage, 31373,
     /*   45130 */     GIR_EraseRootFromParent_Done,
     /*   45131 */   // Label 356: @45131
     /*   45131 */   GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(45197), // Rule ID 31374 //
     /*   45136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus_HwMode4),
     /*   45139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45151 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45154 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45159 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45163 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45167 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45169 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45169 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64),
     /*   45175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45177 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45190 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45195 */     GIR_RootConstrainSelectedInstOperands,
     /*   45196 */     // GIR_Coverage, 31374,
     /*   45196 */     GIR_EraseRootFromParent_Done,
     /*   45197 */   // Label 357: @45197
     /*   45197 */   GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(45263), // Rule ID 31390 //
     /*   45202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode0),
     /*   45205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45209 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45213 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45217 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45220 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45225 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45229 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45233 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45235 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45235 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   45241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45243 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45252 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45256 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45261 */     GIR_RootConstrainSelectedInstOperands,
     /*   45262 */     // GIR_Coverage, 31390,
     /*   45262 */     GIR_EraseRootFromParent_Done,
     /*   45263 */   // Label 358: @45263
     /*   45263 */   GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(45329), // Rule ID 31391 //
     /*   45268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode1),
     /*   45271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45275 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45279 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45283 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45286 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45295 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45299 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45301 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45301 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   45307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45309 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45314 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45318 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45322 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45324 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45327 */     GIR_RootConstrainSelectedInstOperands,
     /*   45328 */     // GIR_Coverage, 31391,
     /*   45328 */     GIR_EraseRootFromParent_Done,
     /*   45329 */   // Label 359: @45329
     /*   45329 */   GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(45395), // Rule ID 31392 //
     /*   45334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode2),
     /*   45337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45341 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45345 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45349 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45352 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45357 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45361 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45365 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45367 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45367 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   45373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45375 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45384 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45388 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45393 */     GIR_RootConstrainSelectedInstOperands,
     /*   45394 */     // GIR_Coverage, 31392,
     /*   45394 */     GIR_EraseRootFromParent_Done,
     /*   45395 */   // Label 360: @45395
     /*   45395 */   GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(45461), // Rule ID 31393 //
     /*   45400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode3),
     /*   45403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45407 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45411 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45415 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45418 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45423 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45427 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45431 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45433 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45433 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   45439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45441 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45450 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45454 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45459 */     GIR_RootConstrainSelectedInstOperands,
     /*   45460 */     // GIR_Coverage, 31393,
     /*   45460 */     GIR_EraseRootFromParent_Done,
     /*   45461 */   // Label 361: @45461
     /*   45461 */   GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(45527), // Rule ID 31394 //
     /*   45466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only_HwMode4),
     /*   45469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45473 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45477 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   45481 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*   45484 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*   45489 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45493 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   45497 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45499 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2, (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*   45499 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   45502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64),
     /*   45505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45507 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   45512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*   45516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // src1
     /*   45520 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   45525 */     GIR_RootConstrainSelectedInstOperands,
     /*   45526 */     // GIR_Coverage, 31394,
     /*   45526 */     GIR_EraseRootFromParent_Done,
     /*   45527 */   // Label 362: @45527
     /*   45527 */   GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(45596), // Rule ID 7280 //
     /*   45532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode0),
     /*   45535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   45543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45551 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45555 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45557 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45561 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45565 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45569 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:10:z
     /*   45573 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45577 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45579 */     // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>, i64:{ *:[i64] }:$src2:$pred:10:z)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45584 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   45588 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   45592 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   45594 */     GIR_RootConstrainSelectedInstOperands,
     /*   45595 */     // GIR_Coverage, 7280,
     /*   45595 */     GIR_EraseRootFromParent_Done,
     /*   45596 */   // Label 363: @45596
     /*   45596 */   GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(45665), // Rule ID 7281 //
     /*   45601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode1),
     /*   45604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45608 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   45612 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45616 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45620 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45624 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45626 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45630 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45634 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45638 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:10:z
     /*   45642 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45646 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45648 */     // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>, i64:{ *:[i64] }:$src2:$pred:10:z)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45653 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   45657 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   45661 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   45663 */     GIR_RootConstrainSelectedInstOperands,
     /*   45664 */     // GIR_Coverage, 7281,
     /*   45664 */     GIR_EraseRootFromParent_Done,
     /*   45665 */   // Label 364: @45665
     /*   45665 */   GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(45734), // Rule ID 7282 //
     /*   45670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode2),
     /*   45673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45677 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   45681 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45685 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45689 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45693 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45695 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45699 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45703 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45707 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:10:z
     /*   45711 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45715 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45717 */     // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>, i64:{ *:[i64] }:$src2:$pred:10:z)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45722 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   45726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   45730 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   45732 */     GIR_RootConstrainSelectedInstOperands,
     /*   45733 */     // GIR_Coverage, 7282,
     /*   45733 */     GIR_EraseRootFromParent_Done,
     /*   45734 */   // Label 365: @45734
     /*   45734 */   GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(45803), // Rule ID 7283 //
     /*   45739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode3),
     /*   45742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45746 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   45750 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45754 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45758 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45762 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45764 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45768 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45772 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45776 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:10:z
     /*   45780 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45784 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45786 */     // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>, i64:{ *:[i64] }:$src2:$pred:10:z)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45791 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   45795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   45799 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   45801 */     GIR_RootConstrainSelectedInstOperands,
     /*   45802 */     // GIR_Coverage, 7283,
     /*   45802 */     GIR_EraseRootFromParent_Done,
     /*   45803 */   // Label 366: @45803
     /*   45803 */   GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(45872), // Rule ID 7284 //
     /*   45808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode4),
     /*   45811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   45819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45827 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45831 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45833 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45837 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45841 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45845 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:10:z
     /*   45849 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45853 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45855 */     // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>, i64:{ *:[i64] }:$src2:$pred:10:z)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   45864 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   45868 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   45870 */     GIR_RootConstrainSelectedInstOperands,
     /*   45871 */     // GIR_Coverage, 7284,
     /*   45871 */     GIR_EraseRootFromParent_Done,
     /*   45872 */   // Label 367: @45872
     /*   45872 */   GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(45941), // Rule ID 31350 //
     /*   45877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode0),
     /*   45880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45884 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:10:z
     /*   45888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45896 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45904 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45906 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45910 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45914 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45918 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45922 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45924 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:10:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45929 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   45933 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   45937 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   45939 */     GIR_RootConstrainSelectedInstOperands,
     /*   45940 */     // GIR_Coverage, 31350,
     /*   45940 */     GIR_EraseRootFromParent_Done,
     /*   45941 */   // Label 368: @45941
     /*   45941 */   GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(46010), // Rule ID 31351 //
     /*   45946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode1),
     /*   45949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   45953 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:10:z
     /*   45957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   45961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   45965 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   45969 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   45973 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   45975 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   45979 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   45983 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   45987 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   45991 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   45993 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:10:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   45993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   45996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   45998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   46002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   46006 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   46008 */     GIR_RootConstrainSelectedInstOperands,
     /*   46009 */     // GIR_Coverage, 31351,
     /*   46009 */     GIR_EraseRootFromParent_Done,
     /*   46010 */   // Label 369: @46010
     /*   46010 */   GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(46079), // Rule ID 31352 //
     /*   46015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode2),
     /*   46018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46022 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:10:z
     /*   46026 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   46030 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   46034 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   46038 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   46042 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   46044 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   46048 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   46052 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   46056 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   46060 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   46062 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:10:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   46062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   46065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46067 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   46071 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   46075 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   46077 */     GIR_RootConstrainSelectedInstOperands,
     /*   46078 */     // GIR_Coverage, 31352,
     /*   46078 */     GIR_EraseRootFromParent_Done,
     /*   46079 */   // Label 370: @46079
     /*   46079 */   GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(46148), // Rule ID 31353 //
     /*   46084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode3),
     /*   46087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46091 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:10:z
     /*   46095 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   46099 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   46103 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   46107 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   46111 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   46113 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   46117 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   46121 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   46125 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   46129 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   46131 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:10:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   46131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   46134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   46140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   46144 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   46146 */     GIR_RootConstrainSelectedInstOperands,
     /*   46147 */     // GIR_Coverage, 31353,
     /*   46147 */     GIR_EraseRootFromParent_Done,
     /*   46148 */   // Label 371: @46148
     /*   46148 */   GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(46217), // Rule ID 31354 //
     /*   46153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLshlAddU64Inst_HwMode4),
     /*   46156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46160 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:10:z
     /*   46164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   46168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   46172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   46176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   46180 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   46182 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x
     /*   46186 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y
     /*   46190 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
     /*   46194 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28505),
     /*   46198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   46200 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:10:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_28506>>)<<P:10:Predicate_anonymous_28505>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
     /*   46200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
     /*   46203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   46209 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   46213 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   46215 */     GIR_RootConstrainSelectedInstOperands,
     /*   46216 */     // GIR_Coverage, 31354,
     /*   46216 */     GIR_EraseRootFromParent_Done,
     /*   46217 */   // Label 372: @46217
     /*   46217 */   GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(46250), // Rule ID 4227 //
     /*   46222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   46225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46229 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   46233 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   46233 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO),
     /*   46238 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   46244 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   46248 */     GIR_RootConstrainSelectedInstOperands,
     /*   46249 */     // GIR_Coverage, 4227,
     /*   46249 */     GIR_Done,
     /*   46250 */   // Label 373: @46250
     /*   46250 */   GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(46283), // Rule ID 4228 //
     /*   46255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   46258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46262 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   46266 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   46266 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO),
     /*   46271 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   46277 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   46281 */     GIR_RootConstrainSelectedInstOperands,
     /*   46282 */     // GIR_Coverage, 4228,
     /*   46282 */     GIR_Done,
     /*   46283 */   // Label 374: @46283
     /*   46283 */   GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(46316), // Rule ID 4229 //
     /*   46288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   46291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46295 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   46299 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   46299 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO),
     /*   46304 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   46310 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   46314 */     GIR_RootConstrainSelectedInstOperands,
     /*   46315 */     // GIR_Coverage, 4229,
     /*   46315 */     GIR_Done,
     /*   46316 */   // Label 375: @46316
     /*   46316 */   GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(46349), // Rule ID 4230 //
     /*   46321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   46324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46328 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   46332 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   46332 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO),
     /*   46337 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   46343 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   46347 */     GIR_RootConstrainSelectedInstOperands,
     /*   46348 */     // GIR_Coverage, 4230,
     /*   46348 */     GIR_Done,
     /*   46349 */   // Label 376: @46349
     /*   46349 */   GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(46382), // Rule ID 4231 //
     /*   46354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   46357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   46361 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27132),
     /*   46365 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27132>>  =>  (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   46365 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO),
     /*   46370 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   46376 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   46380 */     GIR_RootConstrainSelectedInstOperands,
     /*   46381 */     // GIR_Coverage, 4231,
     /*   46381 */     GIR_Done,
     /*   46382 */   // Label 377: @46382
     /*   46382 */   GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(46408), // Rule ID 4237 //
     /*   46387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   46391 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20771),
     /*   46395 */     // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_20771>>  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   46395 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_U64_PSEUDO),
     /*   46400 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   46406 */     GIR_RootConstrainSelectedInstOperands,
     /*   46407 */     // GIR_Coverage, 4237,
     /*   46407 */     GIR_Done,
     /*   46408 */   // Label 378: @46408
     /*   46408 */   GIM_Reject,
     /*   46409 */ // Label 342: @46409
     /*   46409 */ GIM_Reject,
     /*   46410 */ // Label 183: @46410
     /*   46410 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(46679),
     /*   46415 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   46418 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   46421 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   46425 */   GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(46521), // Rule ID 31324 //
     /*   46430 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   46434 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   46438 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   46442 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   46446 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   46448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46455 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46462 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46469 */     // (add:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))  =>  (V_PK_MAD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2)
     /*   46469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAD_U16),
     /*   46472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*   46479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*   46484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_modifiers
     /*   46489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
     /*   46494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*   46499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*   46504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46519 */     GIR_RootConstrainSelectedInstOperands,
     /*   46520 */     // GIR_Coverage, 31324,
     /*   46520 */     GIR_EraseRootFromParent_Done,
     /*   46521 */   // Label 380: @46521
     /*   46521 */   GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(46617), // Rule ID 3307 //
     /*   46526 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   46530 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   46534 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   46538 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   46542 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   46544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46551 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46558 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46565 */     // (add:{ *:[v2i16] } (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_PK_MAD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2)
     /*   46565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAD_U16),
     /*   46568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   46575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   46580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   46585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   46590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*   46595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*   46600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46615 */     GIR_RootConstrainSelectedInstOperands,
     /*   46616 */     // GIR_Coverage, 3307,
     /*   46616 */     GIR_EraseRootFromParent_Done,
     /*   46617 */   // Label 381: @46617
     /*   46617 */   GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(46678), // Rule ID 3318 //
     /*   46622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   46636 */     // (add:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /*   46636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_U16),
     /*   46639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   46646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   46651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   46656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   46661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46673 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46676 */     GIR_RootConstrainSelectedInstOperands,
     /*   46677 */     // GIR_Coverage, 3318,
     /*   46677 */     GIR_EraseRootFromParent_Done,
     /*   46678 */   // Label 382: @46678
     /*   46678 */   GIM_Reject,
     /*   46679 */ // Label 379: @46679
     /*   46679 */ GIM_Reject,
     /*   46680 */ // Label 184: @46680
     /*   46680 */ GIM_Reject,
     /*   46681 */ // Label 1: @46681
     /*   46681 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 388*/ GIMT_Encode4(47590),
     /*   46692 */ /*GILLT_s1*//*Label 383*/ GIMT_Encode4(46712),
     /*   46696 */ /*GILLT_s16*//*Label 384*/ GIMT_Encode4(46831),
     /*   46700 */ /*GILLT_s32*//*Label 385*/ GIMT_Encode4(47047),
     /*   46704 */ /*GILLT_s64*//*Label 386*/ GIMT_Encode4(47314),
     /*   46708 */ /*GILLT_v2s16*//*Label 387*/ GIMT_Encode4(47518),
     /*   46712 */ // Label 383: @46712
     /*   46712 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(46830),
     /*   46717 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*   46720 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*   46723 */   GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(46751), // Rule ID 28198 //
     /*   46728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   46731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   46735 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   46739 */     // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
     /*   46739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64),
     /*   46742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   46744 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   46746 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   46749 */     GIR_RootConstrainSelectedInstOperands,
     /*   46750 */     // GIR_Coverage, 28198,
     /*   46750 */     GIR_EraseRootFromParent_Done,
     /*   46751 */   // Label 390: @46751
     /*   46751 */   GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(46779), // Rule ID 28205 //
     /*   46756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   46759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   46763 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   46767 */     // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
     /*   46767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32),
     /*   46770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   46772 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   46774 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   46777 */     GIR_RootConstrainSelectedInstOperands,
     /*   46778 */     // GIR_Coverage, 28205,
     /*   46778 */     GIR_EraseRootFromParent_Done,
     /*   46779 */   // Label 391: @46779
     /*   46779 */   GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(46804), // Rule ID 28196 //
     /*   46784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   46787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   46791 */     // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   46791 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
     /*   46796 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   46802 */     GIR_RootConstrainSelectedInstOperands,
     /*   46803 */     // GIR_Coverage, 28196,
     /*   46803 */     GIR_Done,
     /*   46804 */   // Label 392: @46804
     /*   46804 */   GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(46829), // Rule ID 28203 //
     /*   46809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   46812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   46816 */     // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   46816 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
     /*   46821 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   46827 */     GIR_RootConstrainSelectedInstOperands,
     /*   46828 */     // GIR_Coverage, 28203,
     /*   46828 */     GIR_Done,
     /*   46829 */   // Label 393: @46829
     /*   46829 */   GIM_Reject,
     /*   46830 */ // Label 389: @46830
     /*   46830 */ GIM_Reject,
     /*   46831 */ // Label 384: @46831
     /*   46831 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(47046),
     /*   46836 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   46839 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   46842 */   GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(46901), // Rule ID 3117 //
     /*   46847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX10Plus),
     /*   46850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   46854 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /*   46861 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /*   46868 */     // (sub:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_NC_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   46868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64),
     /*   46871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   46878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   46883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   46888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   46893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46899 */     GIR_RootConstrainSelectedInstOperands,
     /*   46900 */     // GIR_Coverage, 3117,
     /*   46900 */     GIR_EraseRootFromParent_Done,
     /*   46901 */   // Label 395: @46901
     /*   46901 */   GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(46960), // Rule ID 3118 //
     /*   46906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX10Plus),
     /*   46909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   46913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   46920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   46927 */     // (sub:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_NC_U16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   46927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_t16_e64),
     /*   46930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   46937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   46942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   46947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   46952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   46958 */     GIR_RootConstrainSelectedInstOperands,
     /*   46959 */     // GIR_Coverage, 3118,
     /*   46959 */     GIR_EraseRootFromParent_Done,
     /*   46960 */   // Label 396: @46960
     /*   46960 */   GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(47019), // Rule ID 3119 //
     /*   46965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX10Plus),
     /*   46968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   46972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   46979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   46986 */     // (sub:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_NC_U16_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   46986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_fake16_e64),
     /*   46989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   46991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   46996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   47001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   47006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   47011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47017 */     GIR_RootConstrainSelectedInstOperands,
     /*   47018 */     // GIR_Coverage, 3119,
     /*   47018 */     GIR_EraseRootFromParent_Done,
     /*   47019 */   // Label 397: @47019
     /*   47019 */   GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(47045), // Rule ID 2734 //
     /*   47024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9),
     /*   47027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47031 */     // (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_SUB_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   47031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
     /*   47034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47036 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47038 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47043 */     GIR_RootConstrainSelectedInstOperands,
     /*   47044 */     // GIR_Coverage, 2734,
     /*   47044 */     GIR_EraseRootFromParent_Done,
     /*   47045 */   // Label 398: @47045
     /*   47045 */   GIM_Reject,
     /*   47046 */ // Label 394: @47046
     /*   47046 */ GIM_Reject,
     /*   47047 */ // Label 385: @47047
     /*   47047 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(47313),
     /*   47052 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   47055 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   47058 */   GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(47092), // Rule ID 44 //
     /*   47063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   47067 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   47071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   47075 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20772),
     /*   47079 */     // (sub:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20772>>  =>  (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*   47079 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_I32),
     /*   47084 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   47090 */     GIR_RootConstrainSelectedInstOperands,
     /*   47091 */     // GIR_Coverage, 44,
     /*   47091 */     GIR_Done,
     /*   47092 */   // Label 400: @47092
     /*   47092 */   GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(47122), // Rule ID 7122 //
     /*   47097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
     /*   47100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47104 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47108 */     // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   47108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64),
     /*   47111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47113 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47115 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47120 */     GIR_RootConstrainSelectedInstOperands,
     /*   47121 */     // GIR_Coverage, 7122,
     /*   47121 */     GIR_EraseRootFromParent_Done,
     /*   47122 */   // Label 401: @47122
     /*   47122 */   GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(47160), // Rule ID 7128 //
     /*   47127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode0),
     /*   47130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47134 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47138 */     // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   47138 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   47141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   47144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47146 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   47151 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47153 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47158 */     GIR_RootConstrainSelectedInstOperands,
     /*   47159 */     // GIR_Coverage, 7128,
     /*   47159 */     GIR_EraseRootFromParent_Done,
     /*   47160 */   // Label 402: @47160
     /*   47160 */   GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(47198), // Rule ID 7129 //
     /*   47165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode1),
     /*   47168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47172 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47176 */     // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   47176 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   47179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   47182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47184 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   47189 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47191 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47196 */     GIR_RootConstrainSelectedInstOperands,
     /*   47197 */     // GIR_Coverage, 7129,
     /*   47197 */     GIR_EraseRootFromParent_Done,
     /*   47198 */   // Label 403: @47198
     /*   47198 */   GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(47236), // Rule ID 7130 //
     /*   47203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode2),
     /*   47206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47210 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47214 */     // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   47214 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   47217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   47220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47222 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   47227 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47229 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47234 */     GIR_RootConstrainSelectedInstOperands,
     /*   47235 */     // GIR_Coverage, 7130,
     /*   47235 */     GIR_EraseRootFromParent_Done,
     /*   47236 */   // Label 404: @47236
     /*   47236 */   GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(47274), // Rule ID 7131 //
     /*   47241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode3),
     /*   47244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47248 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47252 */     // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   47252 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   47255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   47258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47260 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   47265 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47267 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47272 */     GIR_RootConstrainSelectedInstOperands,
     /*   47273 */     // GIR_Coverage, 7131,
     /*   47273 */     GIR_EraseRootFromParent_Done,
     /*   47274 */   // Label 405: @47274
     /*   47274 */   GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(47312), // Rule ID 7132 //
     /*   47279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9_HwMode4),
     /*   47282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47286 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47290 */     // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
     /*   47290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   47293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
     /*   47296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47298 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /*   47303 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   47305 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47310 */     GIR_RootConstrainSelectedInstOperands,
     /*   47311 */     // GIR_Coverage, 7132,
     /*   47311 */     GIR_EraseRootFromParent_Done,
     /*   47312 */   // Label 406: @47312
     /*   47312 */   GIM_Reject,
     /*   47313 */ // Label 399: @47313
     /*   47313 */ GIM_Reject,
     /*   47314 */ // Label 386: @47314
     /*   47314 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(47517),
     /*   47319 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   47322 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   47325 */   GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(47358), // Rule ID 4232 //
     /*   47330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   47333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47337 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47341 */     // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47341 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO),
     /*   47346 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   47352 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47356 */     GIR_RootConstrainSelectedInstOperands,
     /*   47357 */     // GIR_Coverage, 4232,
     /*   47357 */     GIR_Done,
     /*   47358 */   // Label 408: @47358
     /*   47358 */   GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(47391), // Rule ID 4233 //
     /*   47363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   47366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47370 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47374 */     // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47374 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO),
     /*   47379 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   47385 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47389 */     GIR_RootConstrainSelectedInstOperands,
     /*   47390 */     // GIR_Coverage, 4233,
     /*   47390 */     GIR_Done,
     /*   47391 */   // Label 409: @47391
     /*   47391 */   GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(47424), // Rule ID 4234 //
     /*   47396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   47399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47403 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47407 */     // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47407 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO),
     /*   47412 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   47418 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47422 */     GIR_RootConstrainSelectedInstOperands,
     /*   47423 */     // GIR_Coverage, 4234,
     /*   47423 */     GIR_Done,
     /*   47424 */   // Label 410: @47424
     /*   47424 */   GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(47457), // Rule ID 4235 //
     /*   47429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   47432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47436 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47440 */     // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47440 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO),
     /*   47445 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   47451 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47455 */     GIR_RootConstrainSelectedInstOperands,
     /*   47456 */     // GIR_Coverage, 4235,
     /*   47456 */     GIR_Done,
     /*   47457 */   // Label 411: @47457
     /*   47457 */   GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(47490), // Rule ID 4236 //
     /*   47462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   47465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47469 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27134),
     /*   47473 */     // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27134>>  =>  (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47473 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO),
     /*   47478 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
     /*   47484 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47488 */     GIR_RootConstrainSelectedInstOperands,
     /*   47489 */     // GIR_Coverage, 4236,
     /*   47489 */     GIR_Done,
     /*   47490 */   // Label 412: @47490
     /*   47490 */   GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(47516), // Rule ID 4238 //
     /*   47495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   47499 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20772),
     /*   47503 */     // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_20772>>  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47503 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_U64_PSEUDO),
     /*   47508 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   47514 */     GIR_RootConstrainSelectedInstOperands,
     /*   47515 */     // GIR_Coverage, 4238,
     /*   47515 */     GIR_Done,
     /*   47516 */   // Label 413: @47516
     /*   47516 */   GIM_Reject,
     /*   47517 */ // Label 407: @47517
     /*   47517 */ GIM_Reject,
     /*   47518 */ // Label 387: @47518
     /*   47518 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(47589), // Rule ID 3326 //
     /*   47523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   47526 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   47529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   47540 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   47547 */   // (sub:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_SUB_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /*   47547 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_I16),
     /*   47550 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   47557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   47562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   47567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   47572 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47575 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47578 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47581 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47584 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47587 */   GIR_RootConstrainSelectedInstOperands,
     /*   47588 */   // GIR_Coverage, 3326,
     /*   47588 */   GIR_EraseRootFromParent_Done,
     /*   47589 */ // Label 414: @47589
     /*   47589 */ GIM_Reject,
     /*   47590 */ // Label 388: @47590
     /*   47590 */ GIM_Reject,
     /*   47591 */ // Label 2: @47591
     /*   47591 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 419*/ GIMT_Encode4(48136),
     /*   47602 */ /*GILLT_s16*//*Label 415*/ GIMT_Encode4(47618),
     /*   47606 */ /*GILLT_s32*//*Label 416*/ GIMT_Encode4(47792),
     /*   47610 */ /*GILLT_s64*//*Label 417*/ GIMT_Encode4(47893),
     /*   47614 */ /*GILLT_v2s16*//*Label 418*/ GIMT_Encode4(48064),
     /*   47618 */ // Label 415: @47618
     /*   47618 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(47791),
     /*   47623 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   47626 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   47629 */   GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(47688), // Rule ID 2696 //
     /*   47634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /*   47637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /*   47648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /*   47655 */     // (mul:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_LO_U16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   47655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_opsel_e64),
     /*   47658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   47665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   47670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   47675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   47680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47686 */     GIR_RootConstrainSelectedInstOperands,
     /*   47687 */     // GIR_Coverage, 2696,
     /*   47687 */     GIR_EraseRootFromParent_Done,
     /*   47688 */   // Label 421: @47688
     /*   47688 */   GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(47744), // Rule ID 2697 //
     /*   47693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   47696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   47700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   47707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   47714 */     // (mul:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_LO_U16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   47714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_t16_e64),
     /*   47717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   47724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   47729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   47734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   47739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   47742 */     GIR_RootConstrainSelectedInstOperands,
     /*   47743 */     // GIR_Coverage, 2697,
     /*   47743 */     GIR_EraseRootFromParent_Done,
     /*   47744 */   // Label 422: @47744
     /*   47744 */   GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(47767), // Rule ID 2695 //
     /*   47749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*   47752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47756 */     // (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MUL_LO_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   47756 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64),
     /*   47761 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47765 */     GIR_RootConstrainSelectedInstOperands,
     /*   47766 */     // GIR_Coverage, 2695,
     /*   47766 */     GIR_Done,
     /*   47767 */   // Label 423: @47767
     /*   47767 */   GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(47790), // Rule ID 2698 //
     /*   47772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   47775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47779 */     // (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MUL_LO_U16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   47779 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_fake16_e64),
     /*   47784 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47788 */     GIR_RootConstrainSelectedInstOperands,
     /*   47789 */     // GIR_Coverage, 2698,
     /*   47789 */     GIR_Done,
     /*   47790 */   // Label 424: @47790
     /*   47790 */   GIM_Reject,
     /*   47791 */ // Label 420: @47791
     /*   47791 */ GIM_Reject,
     /*   47792 */ // Label 416: @47792
     /*   47792 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(47892),
     /*   47797 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   47800 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   47803 */   GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(47823), // Rule ID 81 //
     /*   47808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   47812 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20779),
     /*   47816 */     // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20779>>  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   47816 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_I32),
     /*   47821 */     GIR_RootConstrainSelectedInstOperands,
     /*   47822 */     // GIR_Coverage, 81,
     /*   47822 */     GIR_Done,
     /*   47823 */   // Label 426: @47823
     /*   47823 */   GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(47857), // Rule ID 2838 //
     /*   47828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47832 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   47836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   47843 */     // (mul:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27064>>  =>  (V_MUL_LO_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   47843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U32_e64),
     /*   47846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   47853 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   47855 */     GIR_RootConstrainSelectedInstOperands,
     /*   47856 */     // GIR_Coverage, 2838,
     /*   47856 */     GIR_EraseRootFromParent_Done,
     /*   47857 */   // Label 427: @47857
     /*   47857 */   GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(47891), // Rule ID 31286 //
     /*   47862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   47866 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   47870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   47877 */     // (mul:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))<<P:Predicate_anonymous_27064>>  =>  (V_MUL_LO_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   47877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U32_e64),
     /*   47880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   47882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   47887 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   47889 */     GIR_RootConstrainSelectedInstOperands,
     /*   47890 */     // GIR_Coverage, 31286,
     /*   47890 */     GIR_EraseRootFromParent_Done,
     /*   47891 */   // Label 428: @47891
     /*   47891 */   GIM_Reject,
     /*   47892 */ // Label 425: @47892
     /*   47892 */ GIM_Reject,
     /*   47893 */ // Label 417: @47893
     /*   47893 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(48063),
     /*   47898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   47901 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   47904 */   GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(47927), // Rule ID 51 //
     /*   47909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*   47912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   47916 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20779),
     /*   47920 */     // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_20779>>  =>  (S_MUL_U64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47920 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_U64),
     /*   47925 */     GIR_RootConstrainSelectedInstOperands,
     /*   47926 */     // GIR_Coverage, 51,
     /*   47926 */     GIR_Done,
     /*   47927 */   // Label 430: @47927
     /*   47927 */   GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(47954), // Rule ID 2625 //
     /*   47932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*   47935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47939 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   47943 */     // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27064>>  =>  (V_MUL_U64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47943 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U64_e64),
     /*   47948 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47952 */     GIR_RootConstrainSelectedInstOperands,
     /*   47953 */     // GIR_Coverage, 2625,
     /*   47953 */     GIR_Done,
     /*   47954 */   // Label 431: @47954
     /*   47954 */   GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(47981), // Rule ID 2626 //
     /*   47959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*   47962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47966 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   47970 */     // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27064>>  =>  (V_MUL_U64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47970 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U64_e64),
     /*   47975 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   47979 */     GIR_RootConstrainSelectedInstOperands,
     /*   47980 */     // GIR_Coverage, 2626,
     /*   47980 */     GIR_Done,
     /*   47981 */   // Label 432: @47981
     /*   47981 */   GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(48008), // Rule ID 2627 //
     /*   47986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*   47989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   47993 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   47997 */     // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27064>>  =>  (V_MUL_U64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   47997 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U64_e64),
     /*   48002 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   48006 */     GIR_RootConstrainSelectedInstOperands,
     /*   48007 */     // GIR_Coverage, 2627,
     /*   48007 */     GIR_Done,
     /*   48008 */   // Label 433: @48008
     /*   48008 */   GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(48035), // Rule ID 2628 //
     /*   48013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*   48016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   48020 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   48024 */     // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27064>>  =>  (V_MUL_U64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   48024 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U64_e64),
     /*   48029 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   48033 */     GIR_RootConstrainSelectedInstOperands,
     /*   48034 */     // GIR_Coverage, 2628,
     /*   48034 */     GIR_Done,
     /*   48035 */   // Label 434: @48035
     /*   48035 */   GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(48062), // Rule ID 2629 //
     /*   48040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*   48043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   48047 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27064),
     /*   48051 */     // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_27064>>  =>  (V_MUL_U64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   48051 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U64_e64),
     /*   48056 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   48060 */     GIR_RootConstrainSelectedInstOperands,
     /*   48061 */     // GIR_Coverage, 2629,
     /*   48061 */     GIR_Done,
     /*   48062 */   // Label 435: @48062
     /*   48062 */   GIM_Reject,
     /*   48063 */ // Label 429: @48063
     /*   48063 */ GIM_Reject,
     /*   48064 */ // Label 418: @48064
     /*   48064 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(48135), // Rule ID 3319 //
     /*   48069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   48072 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   48075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48079 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   48086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*   48093 */   // (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MUL_LO_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /*   48093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_LO_U16),
     /*   48096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   48103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   48108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   48113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   48118 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48121 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48124 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48127 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48133 */   GIR_RootConstrainSelectedInstOperands,
     /*   48134 */   // GIR_Coverage, 3319,
     /*   48134 */   GIR_EraseRootFromParent_Done,
     /*   48135 */ // Label 436: @48135
     /*   48135 */ GIM_Reject,
     /*   48136 */ // Label 419: @48136
     /*   48136 */ GIM_Reject,
     /*   48137 */ // Label 3: @48137
     /*   48137 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(17), /*)*//*default:*//*Label 444*/ GIMT_Encode4(50110),
     /*   48148 */ /*GILLT_s1*//*Label 437*/ GIMT_Encode4(48188),
     /*   48152 */ /*GILLT_s16*//*Label 438*/ GIMT_Encode4(48251),
     /*   48156 */ /*GILLT_s32*//*Label 439*/ GIMT_Encode4(48468),
     /*   48160 */ /*GILLT_s64*//*Label 440*/ GIMT_Encode4(49098),
     /*   48164 */ /*GILLT_v2s16*//*Label 441*/ GIMT_Encode4(49695),
     /*   48168 */ /*GILLT_v2s32*//*Label 442*/ GIMT_Encode4(49846), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   48184 */ /*GILLT_v4s16*//*Label 443*/ GIMT_Encode4(49987),
     /*   48188 */ // Label 437: @48188
     /*   48188 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(48250),
     /*   48193 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*   48196 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*   48199 */   GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(48224), // Rule ID 28192 //
     /*   48204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   48207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   48211 */     // (and:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_AND_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   48211 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64),
     /*   48216 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   48222 */     GIR_RootConstrainSelectedInstOperands,
     /*   48223 */     // GIR_Coverage, 28192,
     /*   48223 */     GIR_Done,
     /*   48224 */   // Label 446: @48224
     /*   48224 */   GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(48249), // Rule ID 28199 //
     /*   48229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   48232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   48236 */     // (and:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_AND_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   48236 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*   48241 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   48247 */     GIR_RootConstrainSelectedInstOperands,
     /*   48248 */     // GIR_Coverage, 28199,
     /*   48248 */     GIR_Done,
     /*   48249 */   // Label 447: @48249
     /*   48249 */   GIM_Reject,
     /*   48250 */ // Label 445: @48250
     /*   48250 */ GIM_Reject,
     /*   48251 */ // Label 438: @48251
     /*   48251 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(48467),
     /*   48256 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   48259 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   48262 */   GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(48313), // Rule ID 31326 //
     /*   48267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   48271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   48275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48279 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   48283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   48287 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48291 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   48295 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   48297 */     // (and:{ *:[i16] } (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }), i16:{ *:[i16] }:$src0)<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
     /*   48297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
     /*   48300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   48302 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   48304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   48308 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   48311 */     GIR_RootConstrainSelectedInstOperands,
     /*   48312 */     // GIR_Coverage, 31326,
     /*   48312 */     GIR_EraseRootFromParent_Done,
     /*   48313 */   // Label 449: @48313
     /*   48313 */   GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(48364), // Rule ID 4814 //
     /*   48318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   48322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   48326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   48334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   48338 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48342 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   48346 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   48348 */     // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }))<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
     /*   48348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
     /*   48351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   48353 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   48355 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   48359 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   48362 */     GIR_RootConstrainSelectedInstOperands,
     /*   48363 */     // GIR_Coverage, 4814,
     /*   48363 */     GIR_EraseRootFromParent_Done,
     /*   48364 */   // Label 450: @48364
     /*   48364 */   GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(48387), // Rule ID 7162 //
     /*   48369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   48372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48376 */     // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_AND_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
     /*   48376 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   48381 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   48385 */     GIR_RootConstrainSelectedInstOperands,
     /*   48386 */     // GIR_Coverage, 7162,
     /*   48386 */     GIR_Done,
     /*   48387 */   // Label 451: @48387
     /*   48387 */   GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(48443), // Rule ID 2727 //
     /*   48392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   48395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   48399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   48406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   48413 */     // (and:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_AND_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   48413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
     /*   48416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   48423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   48428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   48433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   48438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48441 */     GIR_RootConstrainSelectedInstOperands,
     /*   48442 */     // GIR_Coverage, 2727,
     /*   48442 */     GIR_EraseRootFromParent_Done,
     /*   48443 */   // Label 452: @48443
     /*   48443 */   GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(48466), // Rule ID 2728 //
     /*   48448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   48451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48455 */     // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_AND_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   48455 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_fake16_e64),
     /*   48460 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   48464 */     GIR_RootConstrainSelectedInstOperands,
     /*   48465 */     // GIR_Coverage, 2728,
     /*   48465 */     GIR_Done,
     /*   48466 */   // Label 453: @48466
     /*   48466 */   GIM_Reject,
     /*   48467 */ // Label 448: @48467
     /*   48467 */ GIM_Reject,
     /*   48468 */ // Label 439: @48468
     /*   48468 */ GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(49097),
     /*   48473 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   48476 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   48479 */   GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(48554), // Rule ID 34103 //
     /*   48484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48488 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   48492 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   48496 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48500 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48504 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   48506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   48510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   48514 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   48518 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   48522 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   48524 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1,
     /*   48528 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48532 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   48536 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   48538 */     // (and:{ *:[i32] } (add:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$width)<<P:Predicate_shl_oneuse>>, -1:{ *:[i32] })<<P:Predicate_add_oneuse>>, i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_27142>>  =>  (V_BFE_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src, 0:{ *:[i32] }, ?:{ *:[i32] }:$width)
     /*   48538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
     /*   48541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48543 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*   48545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // width
     /*   48552 */     GIR_RootConstrainSelectedInstOperands,
     /*   48553 */     // GIR_Coverage, 34103,
     /*   48553 */     GIR_EraseRootFromParent_Done,
     /*   48554 */   // Label 455: @48554
     /*   48554 */   GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(48629), // Rule ID 34104 //
     /*   48559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48563 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   48567 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48571 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48575 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48579 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   48581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   48585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   48589 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   48593 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   48597 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   48599 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*   48603 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48607 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   48611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   48613 */     // (and:{ *:[i32] } (xor:{ *:[i32] } (shl:{ *:[i32] } -1:{ *:[i32] }, i32:{ *:[i32] }:$width)<<P:Predicate_shl_oneuse>>, -1:{ *:[i32] })<<P:Predicate_xor_oneuse>>, i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_27142>>  =>  (V_BFE_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src, 0:{ *:[i32] }, ?:{ *:[i32] }:$width)
     /*   48613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
     /*   48616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48618 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*   48620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // width
     /*   48627 */     GIR_RootConstrainSelectedInstOperands,
     /*   48628 */     // GIR_Coverage, 34104,
     /*   48628 */     GIR_EraseRootFromParent_Done,
     /*   48629 */   // Label 456: @48629
     /*   48629 */   GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(48704), // Rule ID 28498 //
     /*   48634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48638 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   48642 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*   48646 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48650 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48654 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   48656 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   48660 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   48664 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   48668 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   48672 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   48674 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1,
     /*   48678 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48682 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   48686 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   48688 */     // (and:{ *:[i32] } i32:{ *:[i32] }:$src, (add:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$width)<<P:Predicate_shl_oneuse>>, -1:{ *:[i32] })<<P:Predicate_add_oneuse>>)<<P:Predicate_anonymous_27142>>  =>  (V_BFE_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src, 0:{ *:[i32] }, ?:{ *:[i32] }:$width)
     /*   48688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
     /*   48691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48693 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*   48695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // width
     /*   48702 */     GIR_RootConstrainSelectedInstOperands,
     /*   48703 */     // GIR_Coverage, 28498,
     /*   48703 */     GIR_EraseRootFromParent_Done,
     /*   48704 */   // Label 457: @48704
     /*   48704 */   GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(48779), // Rule ID 28499 //
     /*   48709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48713 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   48717 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48721 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48725 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48729 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   48731 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   48735 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   48739 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   48743 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   48747 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   48749 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*   48753 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48757 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   48761 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   48763 */     // (and:{ *:[i32] } i32:{ *:[i32] }:$src, (xor:{ *:[i32] } (shl:{ *:[i32] } -1:{ *:[i32] }, i32:{ *:[i32] }:$width)<<P:Predicate_shl_oneuse>>, -1:{ *:[i32] })<<P:Predicate_xor_oneuse>>)<<P:Predicate_anonymous_27142>>  =>  (V_BFE_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src, 0:{ *:[i32] }, ?:{ *:[i32] }:$width)
     /*   48763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
     /*   48766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48768 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*   48770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48773 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // width
     /*   48777 */     GIR_RootConstrainSelectedInstOperands,
     /*   48778 */     // GIR_Coverage, 28499,
     /*   48778 */     GIR_EraseRootFromParent_Done,
     /*   48779 */   // Label 458: @48779
     /*   48779 */   GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(48832), // Rule ID 34070 //
     /*   48784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48788 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   48792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48800 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48804 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   48806 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48810 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   48814 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   48816 */     // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })<<P:Predicate_not_oneuse>>, i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_27142>>  =>  (V_BFI_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$x, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$z)
     /*   48816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   48819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   48825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48828 */     GIR_RootToRootCopy, /*OpIdx*/2, // z
     /*   48830 */     GIR_RootConstrainSelectedInstOperands,
     /*   48831 */     // GIR_Coverage, 34070,
     /*   48831 */     GIR_EraseRootFromParent_Done,
     /*   48832 */   // Label 459: @48832
     /*   48832 */   GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(48885), // Rule ID 28024 //
     /*   48837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48841 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   48845 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48849 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48853 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48857 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   48859 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48863 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   48867 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   48869 */     // (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })<<P:Predicate_not_oneuse>>)<<P:Predicate_anonymous_27142>>  =>  (V_BFI_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$x, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$z)
     /*   48869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   48872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   48874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   48878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   48881 */     GIR_RootToRootCopy, /*OpIdx*/1, // z
     /*   48883 */     GIR_RootConstrainSelectedInstOperands,
     /*   48884 */     // GIR_Coverage, 28024,
     /*   48884 */     GIR_EraseRootFromParent_Done,
     /*   48885 */   // Label 460: @48885
     /*   48885 */   GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(48936), // Rule ID 31159 //
     /*   48890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   48894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   48898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48906 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48910 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48914 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   48918 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   48920 */     // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }), i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   48920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
     /*   48923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   48925 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   48927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   48931 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   48934 */     GIR_RootConstrainSelectedInstOperands,
     /*   48935 */     // GIR_Coverage, 31159,
     /*   48935 */     GIR_EraseRootFromParent_Done,
     /*   48936 */   // Label 461: @48936
     /*   48936 */   GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(48987), // Rule ID 64 //
     /*   48941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   48945 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   48949 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   48953 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   48957 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   48961 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   48965 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   48969 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   48971 */     // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }))<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   48971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
     /*   48974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   48976 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   48978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   48982 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   48985 */     GIR_RootConstrainSelectedInstOperands,
     /*   48986 */     // GIR_Coverage, 64,
     /*   48986 */     GIR_EraseRootFromParent_Done,
     /*   48987 */   // Label 462: @48987
     /*   48987 */   GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(49050), // Rule ID 28497 //
     /*   48992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   48996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   49000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   49004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   49008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   49012 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   49016 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   49020 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask),
     /*   49024 */     // MIs[2] Operand 1
     /*   49024 */     // No operand predicates
     /*   49024 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   49028 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   49030 */     // (and:{ *:[i32] } (srl:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$rshift), (imm:{ *:[i32] })<<P:Predicate_IMMZeroBasedBitfieldMask>>:$mask)<<P:Predicate_anonymous_27142>>  =>  (V_BFE_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src, ?:{ *:[i32] }:$rshift, (IMMPopCount:{ *:[i32] } ?:{ *:[i32] }:$mask))
     /*   49030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
     /*   49033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   49035 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*   49039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rshift
     /*   49043 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderPopcntImm), // mask
     /*   49048 */     GIR_RootConstrainSelectedInstOperands,
     /*   49049 */     // GIR_Coverage, 28497,
     /*   49049 */     GIR_EraseRootFromParent_Done,
     /*   49050 */   // Label 463: @49050
     /*   49050 */   GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(49076), // Rule ID 52 //
     /*   49055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   49059 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49063 */     // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20780>>  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   49063 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*   49068 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   49074 */     GIR_RootConstrainSelectedInstOperands,
     /*   49075 */     // GIR_Coverage, 52,
     /*   49075 */     GIR_Done,
     /*   49076 */   // Label 464: @49076
     /*   49076 */   GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(49096), // Rule ID 2622 //
     /*   49081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49085 */     // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   49085 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   49090 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   49094 */     GIR_RootConstrainSelectedInstOperands,
     /*   49095 */     // GIR_Coverage, 2622,
     /*   49095 */     GIR_Done,
     /*   49096 */   // Label 465: @49096
     /*   49096 */   GIM_Reject,
     /*   49097 */ // Label 454: @49097
     /*   49097 */ GIM_Reject,
     /*   49098 */ // Label 440: @49098
     /*   49098 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(49694),
     /*   49103 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   49106 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   49109 */   GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(49337), // Rule ID 34071 //
     /*   49114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49118 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   49122 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49126 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   49130 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   49134 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   49136 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   49140 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   49144 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   49146 */     // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })<<P:Predicate_not_oneuse>>, i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_27142>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   49146 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   49149 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49153 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49158 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   49164 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49169 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49174 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   49177 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49181 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49186 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   49192 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49197 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49202 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   49205 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   49209 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49214 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*   49217 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /*   49220 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/5,
     /*   49223 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*   49225 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   49228 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49232 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49237 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   49243 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49248 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49253 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   49256 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49260 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49265 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   49271 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49276 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49281 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   49284 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   49288 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49293 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   49296 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   49299 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   49302 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   49304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   49307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   49309 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   49312 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   49315 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   49318 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   49321 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49326 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49331 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49336 */     // GIR_Coverage, 34071,
     /*   49336 */     GIR_EraseRootFromParent_Done,
     /*   49337 */   // Label 467: @49337
     /*   49337 */   GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(49565), // Rule ID 28025 //
     /*   49342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49346 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   49350 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49354 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   49358 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   49362 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   49364 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   49368 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27142),
     /*   49372 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   49374 */     // (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })<<P:Predicate_not_oneuse>>)<<P:Predicate_anonymous_27142>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   49374 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   49377 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49381 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49386 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   49392 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49397 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49402 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   49405 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49409 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49414 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   49420 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49425 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49430 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   49433 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   49437 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49442 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*   49445 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /*   49448 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/5,
     /*   49451 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*   49453 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   49456 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49460 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49465 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   49471 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49476 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49481 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   49484 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   49488 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49493 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   49499 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49504 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49509 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   49512 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   49516 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   49521 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   49524 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*   49527 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   49530 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   49532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   49535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   49537 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   49540 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   49543 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   49546 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   49549 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   49554 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49559 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49564 */     // GIR_Coverage, 28025,
     /*   49564 */     GIR_EraseRootFromParent_Done,
     /*   49565 */   // Label 468: @49565
     /*   49565 */   GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(49616), // Rule ID 31160 //
     /*   49570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   49574 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   49578 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49582 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   49586 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   49590 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   49594 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49598 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   49600 */     // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }), i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   49600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
     /*   49603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   49605 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   49607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   49611 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   49614 */     GIR_RootConstrainSelectedInstOperands,
     /*   49615 */     // GIR_Coverage, 31160,
     /*   49615 */     GIR_EraseRootFromParent_Done,
     /*   49616 */   // Label 469: @49616
     /*   49616 */   GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(49667), // Rule ID 65 //
     /*   49621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   49625 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   49629 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49633 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   49637 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   49641 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   49645 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49649 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   49651 */     // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }))<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   49651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
     /*   49654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   49656 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   49658 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   49662 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   49665 */     GIR_RootConstrainSelectedInstOperands,
     /*   49666 */     // GIR_Coverage, 65,
     /*   49666 */     GIR_EraseRootFromParent_Done,
     /*   49667 */   // Label 470: @49667
     /*   49667 */   GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(49693), // Rule ID 53 //
     /*   49672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   49676 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49680 */     // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_20780>>  =>  (S_AND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   49680 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64),
     /*   49685 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   49691 */     GIR_RootConstrainSelectedInstOperands,
     /*   49692 */     // GIR_Coverage, 53,
     /*   49692 */     GIR_Done,
     /*   49693 */   // Label 471: @49693
     /*   49693 */   GIM_Reject,
     /*   49694 */ // Label 466: @49694
     /*   49694 */ GIM_Reject,
     /*   49695 */ // Label 441: @49695
     /*   49695 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(49845),
     /*   49700 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   49703 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   49706 */   GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(49765), // Rule ID 31327 //
     /*   49711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   49715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   49719 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49723 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   49727 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   49731 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   49735 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   49741 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   49743 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49747 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   49749 */     // (and:{ *:[v2i16] } (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }), v2i16:{ *:[v2i16] }:$src0)<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
     /*   49749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
     /*   49752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   49754 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   49756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   49760 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   49763 */     GIR_RootConstrainSelectedInstOperands,
     /*   49764 */     // GIR_Coverage, 31327,
     /*   49764 */     GIR_EraseRootFromParent_Done,
     /*   49765 */   // Label 473: @49765
     /*   49765 */   GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(49824), // Rule ID 4815 //
     /*   49770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   49774 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   49778 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49782 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   49786 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   49790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   49794 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   49800 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   49802 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49806 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   49808 */     // (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }))<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
     /*   49808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
     /*   49811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   49813 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   49815 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   49819 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   49822 */     GIR_RootConstrainSelectedInstOperands,
     /*   49823 */     // GIR_Coverage, 4815,
     /*   49823 */     GIR_EraseRootFromParent_Done,
     /*   49824 */   // Label 474: @49824
     /*   49824 */   GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(49844), // Rule ID 7165 //
     /*   49829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   49833 */     // (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1)  =>  (V_AND_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
     /*   49833 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   49838 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   49842 */     GIR_RootConstrainSelectedInstOperands,
     /*   49843 */     // GIR_Coverage, 7165,
     /*   49843 */     GIR_Done,
     /*   49844 */   // Label 475: @49844
     /*   49844 */   GIM_Reject,
     /*   49845 */ // Label 472: @49845
     /*   49845 */ GIM_Reject,
     /*   49846 */ // Label 442: @49846
     /*   49846 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(49986),
     /*   49851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   49854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   49857 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   49861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   49865 */   GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(49916), // Rule ID 31329 //
     /*   49870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   49874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49878 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   49882 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   49886 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   49890 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   49896 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   49898 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   49900 */     // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }), v2i32:{ *:[v2i32] }:$src0)<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
     /*   49900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
     /*   49903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   49905 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   49907 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   49911 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   49914 */     GIR_RootConstrainSelectedInstOperands,
     /*   49915 */     // GIR_Coverage, 31329,
     /*   49915 */     GIR_EraseRootFromParent_Done,
     /*   49916 */   // Label 477: @49916
     /*   49916 */   GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(49967), // Rule ID 4817 //
     /*   49921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   49925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   49929 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   49933 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   49937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   49941 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   49947 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   49949 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   49951 */     // (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }))<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
     /*   49951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
     /*   49954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   49956 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   49958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   49962 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   49965 */     GIR_RootConstrainSelectedInstOperands,
     /*   49966 */     // GIR_Coverage, 4817,
     /*   49966 */     GIR_EraseRootFromParent_Done,
     /*   49967 */   // Label 478: @49967
     /*   49967 */   GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(49985), // Rule ID 4799 //
     /*   49972 */     // (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, v2i32:{ *:[v2i32] }:$y)<<P:Predicate_anonymous_20780>>  =>  (S_AND_B64:{ *:[v2i32] }:{ *:[i1] } SReg_64:{ *:[v2i32] }:$x, SReg_64:{ *:[v2i32] }:$y)
     /*   49972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64),
     /*   49977 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   49983 */     GIR_RootConstrainSelectedInstOperands,
     /*   49984 */     // GIR_Coverage, 4799,
     /*   49984 */     GIR_Done,
     /*   49985 */   // Label 479: @49985
     /*   49985 */   GIM_Reject,
     /*   49986 */ // Label 476: @49986
     /*   49986 */ GIM_Reject,
     /*   49987 */ // Label 443: @49987
     /*   49987 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(50109),
     /*   49992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   49995 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*   49998 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20780),
     /*   50002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   50006 */   GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(50057), // Rule ID 31328 //
     /*   50011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   50015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   50019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   50023 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*   50027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   50031 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   50037 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   50039 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   50041 */     // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }), v4i16:{ *:[v4i16] }:$src0)<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
     /*   50041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
     /*   50044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   50046 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   50048 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   50052 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   50055 */     GIR_RootConstrainSelectedInstOperands,
     /*   50056 */     // GIR_Coverage, 31328,
     /*   50056 */     GIR_EraseRootFromParent_Done,
     /*   50057 */   // Label 481: @50057
     /*   50057 */   GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(50108), // Rule ID 4816 //
     /*   50062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   50066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   50070 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   50074 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*   50078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   50082 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   50088 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   50090 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   50092 */     // (and:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src0, (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }))<<P:Predicate_anonymous_20780>>  =>  (S_ANDN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
     /*   50092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
     /*   50095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   50097 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   50099 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   50103 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   50106 */     GIR_RootConstrainSelectedInstOperands,
     /*   50107 */     // GIR_Coverage, 4816,
     /*   50107 */     GIR_EraseRootFromParent_Done,
     /*   50108 */   // Label 482: @50108
     /*   50108 */   GIM_Reject,
     /*   50109 */ // Label 480: @50109
     /*   50109 */ GIM_Reject,
     /*   50110 */ // Label 444: @50110
     /*   50110 */ GIM_Reject,
     /*   50111 */ // Label 4: @50111
     /*   50111 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(17), /*)*//*default:*//*Label 490*/ GIMT_Encode4(66389),
     /*   50122 */ /*GILLT_s1*//*Label 483*/ GIMT_Encode4(50162),
     /*   50126 */ /*GILLT_s16*//*Label 484*/ GIMT_Encode4(50225),
     /*   50130 */ /*GILLT_s32*//*Label 485*/ GIMT_Encode4(50442),
     /*   50134 */ /*GILLT_s64*//*Label 486*/ GIMT_Encode4(56329),
     /*   50138 */ /*GILLT_v2s16*//*Label 487*/ GIMT_Encode4(65974),
     /*   50142 */ /*GILLT_v2s32*//*Label 488*/ GIMT_Encode4(66125), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   50158 */ /*GILLT_v4s16*//*Label 489*/ GIMT_Encode4(66266),
     /*   50162 */ // Label 483: @50162
     /*   50162 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(50224),
     /*   50167 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*   50170 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*   50173 */   GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(50198), // Rule ID 28193 //
     /*   50178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   50181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   50185 */     // (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_OR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   50185 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64),
     /*   50190 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   50196 */     GIR_RootConstrainSelectedInstOperands,
     /*   50197 */     // GIR_Coverage, 28193,
     /*   50197 */     GIR_Done,
     /*   50198 */   // Label 492: @50198
     /*   50198 */   GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(50223), // Rule ID 28200 //
     /*   50203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   50206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   50210 */     // (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_OR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   50210 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
     /*   50215 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   50221 */     GIR_RootConstrainSelectedInstOperands,
     /*   50222 */     // GIR_Coverage, 28200,
     /*   50222 */     GIR_Done,
     /*   50223 */   // Label 493: @50223
     /*   50223 */   GIM_Reject,
     /*   50224 */ // Label 491: @50224
     /*   50224 */ GIM_Reject,
     /*   50225 */ // Label 484: @50225
     /*   50225 */ GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(50441),
     /*   50230 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   50233 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   50236 */   GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(50287), // Rule ID 31330 //
     /*   50241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   50245 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   50249 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   50253 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   50257 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   50261 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   50265 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   50269 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   50271 */     // (or:{ *:[i16] } (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }), i16:{ *:[i16] }:$src0)<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
     /*   50271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
     /*   50274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   50276 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   50278 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   50282 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   50285 */     GIR_RootConstrainSelectedInstOperands,
     /*   50286 */     // GIR_Coverage, 31330,
     /*   50286 */     GIR_EraseRootFromParent_Done,
     /*   50287 */   // Label 495: @50287
     /*   50287 */   GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(50338), // Rule ID 4818 //
     /*   50292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   50296 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   50300 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   50304 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   50308 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*   50312 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   50316 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   50320 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   50322 */     // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }))<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
     /*   50322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
     /*   50325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   50327 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   50329 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   50333 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   50336 */     GIR_RootConstrainSelectedInstOperands,
     /*   50337 */     // GIR_Coverage, 4818,
     /*   50337 */     GIR_EraseRootFromParent_Done,
     /*   50338 */   // Label 496: @50338
     /*   50338 */   GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(50361), // Rule ID 7163 //
     /*   50343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   50346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   50350 */     // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_OR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
     /*   50350 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
     /*   50355 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   50359 */     GIR_RootConstrainSelectedInstOperands,
     /*   50360 */     // GIR_Coverage, 7163,
     /*   50360 */     GIR_Done,
     /*   50361 */   // Label 497: @50361
     /*   50361 */   GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(50417), // Rule ID 2729 //
     /*   50366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   50369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   50373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   50380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   50387 */     // (or:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_OR_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   50387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B16_t16_e64),
     /*   50390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   50392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   50397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   50402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   50407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   50412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50415 */     GIR_RootConstrainSelectedInstOperands,
     /*   50416 */     // GIR_Coverage, 2729,
     /*   50416 */     GIR_EraseRootFromParent_Done,
     /*   50417 */   // Label 498: @50417
     /*   50417 */   GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(50440), // Rule ID 2730 //
     /*   50422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   50425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   50429 */     // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_OR_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   50429 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B16_fake16_e64),
     /*   50434 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   50438 */     GIR_RootConstrainSelectedInstOperands,
     /*   50439 */     // GIR_Coverage, 2730,
     /*   50439 */     GIR_Done,
     /*   50440 */   // Label 499: @50440
     /*   50440 */   GIM_Reject,
     /*   50441 */ // Label 494: @50441
     /*   50441 */ GIM_Reject,
     /*   50442 */ // Label 485: @50442
     /*   50442 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(56328),
     /*   50447 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   50450 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   50453 */   GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(50634), // Rule ID 31401 //
     /*   50458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAshrPkInsts),
     /*   50461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   50465 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   50469 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   50473 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   50477 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   50481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   50485 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   50489 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   50493 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   50497 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   50501 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   50505 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   50509 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   50513 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   50517 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 128,
     /*   50521 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/3, 127,
     /*   50525 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
     /*   50536 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   50540 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   50544 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   50548 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   50552 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   50556 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   50560 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   50564 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   50568 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   50572 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   50576 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   50580 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   50584 */     // MIs[6] src2
     /*   50584 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
     /*   50589 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/2, 128,
     /*   50593 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/3, 127,
     /*   50597 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
     /*   50601 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*   50603 */     // (or:{ *:[i32] } (and:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src2), -128:{ *:[i32] }, 127:{ *:[i32] }), 255:{ *:[i32] }), (shl:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2), -128:{ *:[i32] }, 127:{ *:[i32] }), 8:{ *:[i32] }))  =>  (V_ASHR_PK_I8_I32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src0, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src2, 0:{ *:[i32] })
     /*   50603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_PK_I8_I32_e64),
     /*   50606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   50608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50611 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src0
     /*   50615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src1
     /*   50622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50625 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // src2
     /*   50629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50632 */     GIR_RootConstrainSelectedInstOperands,
     /*   50633 */     // GIR_Coverage, 31401,
     /*   50633 */     GIR_EraseRootFromParent_Done,
     /*   50634 */   // Label 501: @50634
     /*   50634 */   GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(50815), // Rule ID 7531 //
     /*   50639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAshrPkInsts),
     /*   50642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   50646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   50650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   50654 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   50658 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   50662 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   50666 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   50670 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   50674 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   50678 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   50682 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   50686 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   50690 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   50694 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   50698 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 128,
     /*   50702 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/3, 127,
     /*   50706 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
     /*   50710 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   50714 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*   50718 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   50722 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   50726 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   50730 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   50734 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   50738 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
     /*   50742 */     GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
     /*   50746 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   50750 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   50754 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   50758 */     // MIs[6] src2
     /*   50758 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
     /*   50763 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/2, 128,
     /*   50767 */     GIM_CheckConstantInt8, /*MI*/5, /*Op*/3, 127,
     /*   50771 */     GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(255),
     /*   50782 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*   50784 */     // (or:{ *:[i32] } (shl:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2), -128:{ *:[i32] }, 127:{ *:[i32] }), 8:{ *:[i32] }), (and:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src2), -128:{ *:[i32] }, 127:{ *:[i32] }), 255:{ *:[i32] }))  =>  (V_ASHR_PK_I8_I32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src0, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src2, 0:{ *:[i32] })
     /*   50784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_PK_I8_I32_e64),
     /*   50787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   50789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // src0
     /*   50796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   50803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50806 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // src2
     /*   50810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50813 */     GIR_RootConstrainSelectedInstOperands,
     /*   50814 */     // GIR_Coverage, 7531,
     /*   50814 */     GIR_EraseRootFromParent_Done,
     /*   50815 */   // Label 502: @50815
     /*   50815 */   GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(50983), // Rule ID 31402 //
     /*   50820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAshrPkInsts),
     /*   50823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   50827 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   50831 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   50835 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   50839 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   50843 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /*   50847 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   50851 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   50855 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   50859 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   50863 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /*   50867 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/3, GIMT_Encode8(255),
     /*   50878 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   50882 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   50886 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   50890 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   50894 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   50898 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   50902 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   50906 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   50910 */     GIM_CheckType, /*MI*/4, /*Op*/3, /*Type*/GILLT_s32,
     /*   50914 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   50918 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   50922 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   50926 */     // MIs[5] src2
     /*   50926 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   50931 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /*   50935 */     GIM_CheckConstantInt, /*MI*/4, /*Op*/3, GIMT_Encode8(255),
     /*   50946 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
     /*   50950 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*   50952 */     // (or:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src2), 0:{ *:[i32] }, 255:{ *:[i32] }), (shl:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2), 0:{ *:[i32] }, 255:{ *:[i32] }), 8:{ *:[i32] }))  =>  (V_ASHR_PK_U8_I32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src0, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src2, 0:{ *:[i32] })
     /*   50952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_PK_U8_I32_e64),
     /*   50955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   50957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50960 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   50964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src1
     /*   50971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
     /*   50978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   50981 */     GIR_RootConstrainSelectedInstOperands,
     /*   50982 */     // GIR_Coverage, 31402,
     /*   50982 */     GIR_EraseRootFromParent_Done,
     /*   50983 */   // Label 503: @50983
     /*   50983 */   GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(51151), // Rule ID 7532 //
     /*   50988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAshrPkInsts),
     /*   50991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   50995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   50999 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   51003 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51007 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51011 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   51015 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   51019 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51023 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51027 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   51031 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   51035 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   51039 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   51043 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   51047 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /*   51051 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/3, GIMT_Encode8(255),
     /*   51062 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
     /*   51066 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   51070 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AMDGPU::G_AMDGPU_SMED3),
     /*   51074 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   51078 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   51082 */     GIM_CheckType, /*MI*/4, /*Op*/3, /*Type*/GILLT_s32,
     /*   51086 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   51090 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*   51094 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   51098 */     // MIs[5] src2
     /*   51098 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/2,
     /*   51103 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /*   51107 */     GIM_CheckConstantInt, /*MI*/4, /*Op*/3, GIMT_Encode8(255),
     /*   51118 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*   51120 */     // (or:{ *:[i32] } (shl:{ *:[i32] } (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2), 0:{ *:[i32] }, 255:{ *:[i32] }), 8:{ *:[i32] }), (AMDGPUsmed3:{ *:[i32] } (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src2), 0:{ *:[i32] }, 255:{ *:[i32] }))  =>  (V_ASHR_PK_U8_I32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src0, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src2, 0:{ *:[i32] })
     /*   51120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_PK_U8_I32_e64),
     /*   51123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   51125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   51128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // src0
     /*   51132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   51135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
     /*   51139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   51142 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // src2
     /*   51146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   51149 */     GIR_RootConstrainSelectedInstOperands,
     /*   51150 */     // GIR_Coverage, 7532,
     /*   51150 */     GIR_EraseRootFromParent_Done,
     /*   51151 */   // Label 504: @51151
     /*   51151 */   GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(51298), // Rule ID 34061 //
     /*   51156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51160 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   51164 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51168 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51172 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51176 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   51180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   51184 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51188 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51192 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   51196 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   51200 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51204 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   51208 */     // MIs[3] x
     /*   51208 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   51213 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   51217 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   51219 */     // (or:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   51219 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   51222 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51226 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51231 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // z
     /*   51235 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51240 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   51243 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51247 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51252 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // y
     /*   51256 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51261 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   51264 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51268 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51273 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   51277 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   51285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   51287 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   51290 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   51293 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   51296 */     GIR_RootConstrainSelectedInstOperands,
     /*   51297 */     // GIR_Coverage, 34061,
     /*   51297 */     GIR_EraseRootFromParent_Done,
     /*   51298 */   // Label 505: @51298
     /*   51298 */   GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(51445), // Rule ID 34060 //
     /*   51303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51307 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   51311 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51315 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51319 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51323 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   51327 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   51331 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51335 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51339 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   51343 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   51347 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51351 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   51355 */     // MIs[3] x
     /*   51355 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   51360 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   51364 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   51366 */     // (or:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   51366 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   51369 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51373 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51378 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // z
     /*   51382 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51387 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   51390 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51394 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51399 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, // y
     /*   51403 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51408 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   51411 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51415 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51420 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   51424 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   51432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   51434 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   51437 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   51440 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   51443 */     GIR_RootConstrainSelectedInstOperands,
     /*   51444 */     // GIR_Coverage, 34060,
     /*   51444 */     GIR_EraseRootFromParent_Done,
     /*   51445 */   // Label 506: @51445
     /*   51445 */   GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(51592), // Rule ID 34059 //
     /*   51450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51454 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   51458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51462 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51466 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51470 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   51474 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   51478 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51482 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51486 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   51490 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   51494 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51498 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   51502 */     // MIs[3] x
     /*   51502 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   51507 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   51511 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   51513 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   51513 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   51516 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51520 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51525 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // z
     /*   51529 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51534 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   51537 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51541 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51546 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // y
     /*   51550 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51555 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   51558 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51562 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51567 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   51571 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   51579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   51581 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   51584 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   51587 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   51590 */     GIR_RootConstrainSelectedInstOperands,
     /*   51591 */     // GIR_Coverage, 34059,
     /*   51591 */     GIR_EraseRootFromParent_Done,
     /*   51592 */   // Label 507: @51592
     /*   51592 */   GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(51739), // Rule ID 34058 //
     /*   51597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51601 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   51605 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51609 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51613 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51617 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   51621 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   51625 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51629 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51633 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   51637 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   51641 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51645 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   51649 */     // MIs[3] x
     /*   51649 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   51654 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   51658 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   51660 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })), (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   51660 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   51663 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51667 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51672 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // z
     /*   51676 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51681 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   51684 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51688 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51693 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, // y
     /*   51697 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51702 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   51705 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51709 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51714 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   51718 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   51726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   51728 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   51731 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   51734 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   51737 */     GIR_RootConstrainSelectedInstOperands,
     /*   51738 */     // GIR_Coverage, 34058,
     /*   51738 */     GIR_EraseRootFromParent_Done,
     /*   51739 */   // Label 508: @51739
     /*   51739 */   GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(51886), // Rule ID 34055 //
     /*   51744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51748 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   51752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51756 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51760 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51764 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   51768 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51772 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51776 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51780 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   51784 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   51788 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   51792 */     // MIs[3] x
     /*   51792 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   51797 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   51801 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   51805 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   51807 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   51807 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   51810 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51814 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51819 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   51823 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51828 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   51831 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51835 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51840 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   51844 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51849 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   51852 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51856 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51861 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   51865 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   51873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   51875 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   51878 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   51881 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   51884 */     GIR_RootConstrainSelectedInstOperands,
     /*   51885 */     // GIR_Coverage, 34055,
     /*   51885 */     GIR_EraseRootFromParent_Done,
     /*   51886 */   // Label 509: @51886
     /*   51886 */   GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(52033), // Rule ID 34057 //
     /*   51891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51895 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   51899 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51903 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   51907 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   51911 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   51915 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   51919 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   51923 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   51927 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   51931 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   51935 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   51939 */     // MIs[3] x
     /*   51939 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   51944 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   51948 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   51952 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   51954 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   51954 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   51957 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51961 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51966 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   51970 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51975 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   51978 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   51982 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   51987 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   51991 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   51996 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   51999 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52003 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52008 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   52012 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   52020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   52022 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   52025 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   52028 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   52031 */     GIR_RootConstrainSelectedInstOperands,
     /*   52032 */     // GIR_Coverage, 34057,
     /*   52032 */     GIR_EraseRootFromParent_Done,
     /*   52033 */   // Label 510: @52033
     /*   52033 */   GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(52180), // Rule ID 28021 //
     /*   52038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52042 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   52054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   52058 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   52062 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52066 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   52070 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   52074 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   52078 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   52082 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   52086 */     // MIs[3] x
     /*   52086 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   52091 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   52095 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   52099 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52101 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   52101 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   52104 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52108 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52113 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   52117 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52122 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   52125 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52129 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52134 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   52138 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52143 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   52146 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52150 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52155 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   52159 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   52167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   52169 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   52172 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   52175 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   52178 */     GIR_RootConstrainSelectedInstOperands,
     /*   52179 */     // GIR_Coverage, 28021,
     /*   52179 */     GIR_EraseRootFromParent_Done,
     /*   52180 */   // Label 511: @52180
     /*   52180 */   GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(52327), // Rule ID 34056 //
     /*   52185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52189 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52193 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52197 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   52201 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   52205 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   52209 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52213 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   52217 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   52221 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   52225 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   52229 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   52233 */     // MIs[3] x
     /*   52233 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   52238 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   52242 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   52246 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52248 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   52248 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   52251 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52255 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52260 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   52264 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52269 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   52272 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52276 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52281 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   52285 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   52293 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52297 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52302 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   52306 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   52314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   52316 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   52319 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   52322 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   52325 */     GIR_RootConstrainSelectedInstOperands,
     /*   52326 */     // GIR_Coverage, 34056,
     /*   52326 */     GIR_EraseRootFromParent_Done,
     /*   52327 */   // Label 512: @52327
     /*   52327 */   GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(52432), // Rule ID 28392 //
     /*   52332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   52335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   52347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   52351 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   52355 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /*   52359 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   52362 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*   52366 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*   52370 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 0,
     /*   52374 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   52379 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   52383 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   52387 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /*   52391 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   52395 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52397 */     // (or:{ *:[i32] } (bitconvert:{ *:[i32] } (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, VGPR_16:{ *:[i16] }:$src_hi)), (zext:{ *:[i32] } i16:{ *:[i16] }:$src_lo))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i32] } VGPR_32:{ *:[i32] }, ?:{ *:[i16] }:$src_lo, lo16:{ *:[i32] }, ?:{ *:[i16] }:$src_hi, hi16:{ *:[i32] })
     /*   52397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   52400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   52402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src_lo
     /*   52406 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   52409 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src_hi
     /*   52413 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   52416 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52421 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   52426 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   52431 */     // GIR_Coverage, 28392,
     /*   52431 */     GIR_EraseRootFromParent_Done,
     /*   52432 */   // Label 513: @52432
     /*   52432 */   GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(52537), // Rule ID 28391 //
     /*   52437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   52440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   52452 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   52456 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   52460 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   52464 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   52468 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   52472 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /*   52476 */     GIM_CheckNumOperands, /*MI*/3, /*Expected*/3,
     /*   52479 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /*   52483 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s16,
     /*   52487 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 0,
     /*   52491 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   52496 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   52500 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52502 */     // (or:{ *:[i32] } (zext:{ *:[i32] } i16:{ *:[i16] }:$src_lo), (bitconvert:{ *:[i32] } (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, VGPR_16:{ *:[i16] }:$src_hi)))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i32] } VGPR_32:{ *:[i32] }, ?:{ *:[i16] }:$src_lo, lo16:{ *:[i32] }, ?:{ *:[i16] }:$src_hi, hi16:{ *:[i32] })
     /*   52502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   52505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   52507 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src_lo
     /*   52511 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   52514 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // src_hi
     /*   52518 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   52521 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52526 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   52531 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   52536 */     // GIR_Coverage, 28391,
     /*   52536 */     GIR_EraseRootFromParent_Done,
     /*   52537 */   // Label 514: @52537
     /*   52537 */   GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(52630), // Rule ID 7274 //
     /*   52542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   52545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52553 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   52557 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   52561 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   52565 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   52567 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
     /*   52571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   52575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52579 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   52583 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   52587 */     GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y
     /*   52591 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   52595 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   52599 */     // MIs[3] Operand 1
     /*   52599 */     // No operand predicates
     /*   52599 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*   52603 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:5:z
     /*   52607 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28490),
     /*   52611 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52613 */     // (or:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:5:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_28480>>, i32:{ *:[i32] }:$src2:$pred:5:z)<<P:5:Predicate_anonymous_28490>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   52613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
     /*   52616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   52618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   52622 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   52626 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   52628 */     GIR_RootConstrainSelectedInstOperands,
     /*   52629 */     // GIR_Coverage, 7274,
     /*   52629 */     GIR_EraseRootFromParent_Done,
     /*   52630 */   // Label 515: @52630
     /*   52630 */   GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(52723), // Rule ID 31345 //
     /*   52635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   52638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52642 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:5:z
     /*   52646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   52650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   52654 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   52658 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   52662 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   52664 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
     /*   52668 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   52672 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52676 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   52680 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   52684 */     GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y
     /*   52688 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   52692 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   52696 */     // MIs[3] Operand 1
     /*   52696 */     // No operand predicates
     /*   52696 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*   52700 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28490),
     /*   52704 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52706 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:5:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:5:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_28480>>)<<P:5:Predicate_anonymous_28490>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   52706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
     /*   52709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   52711 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   52715 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   52719 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   52721 */     GIR_RootConstrainSelectedInstOperands,
     /*   52722 */     // GIR_Coverage, 31345,
     /*   52722 */     GIR_EraseRootFromParent_Done,
     /*   52723 */   // Label 516: @52723
     /*   52723 */   GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(52908), // Rule ID 34117 //
     /*   52728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52732 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52736 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52740 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   52744 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   52748 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   52752 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   52756 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   52760 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   52764 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   52768 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52772 */     // MIs[3] x
     /*   52772 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   52777 */     // MIs[3] z
     /*   52777 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   52782 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   52786 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52788 */     // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   52788 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   52791 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52795 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52800 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   52804 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52809 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   52812 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52816 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52821 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   52825 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52830 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   52833 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52837 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52842 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   52846 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52851 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   52854 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52858 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52863 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   52867 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52872 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   52875 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   52879 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52884 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   52887 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   52890 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   52892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   52895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   52897 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   52900 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   52903 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   52906 */     GIR_RootConstrainSelectedInstOperands,
     /*   52907 */     // GIR_Coverage, 34117,
     /*   52907 */     GIR_EraseRootFromParent_Done,
     /*   52908 */   // Label 517: @52908
     /*   52908 */   GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(53093), // Rule ID 34118 //
     /*   52913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52917 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   52921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52925 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   52929 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   52933 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   52937 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   52941 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   52945 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   52949 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   52953 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   52957 */     // MIs[3] z
     /*   52957 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   52962 */     // MIs[3] x
     /*   52962 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   52967 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   52971 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   52973 */     // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   52973 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   52976 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   52980 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   52985 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   52989 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   52994 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   52997 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53001 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53006 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   53010 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53015 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   53018 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53022 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53027 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   53031 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53036 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   53039 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53043 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53048 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   53052 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53057 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   53060 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   53064 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53069 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   53072 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   53075 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   53077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   53080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   53082 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   53085 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   53088 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   53091 */     GIR_RootConstrainSelectedInstOperands,
     /*   53092 */     // GIR_Coverage, 34118,
     /*   53092 */     GIR_EraseRootFromParent_Done,
     /*   53093 */   // Label 518: @53093
     /*   53093 */   GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(53278), // Rule ID 34119 //
     /*   53098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53102 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   53106 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53110 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   53114 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   53118 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   53122 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   53126 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   53130 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   53134 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   53138 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53142 */     // MIs[3] x
     /*   53142 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   53147 */     // MIs[3] z
     /*   53147 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   53152 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   53156 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   53158 */     // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   53158 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   53161 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53165 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53170 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   53174 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53179 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   53182 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53186 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53191 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   53195 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53200 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   53203 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53207 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53212 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   53216 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53221 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   53224 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53228 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53233 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
     /*   53237 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53242 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   53245 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   53249 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53254 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   53257 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   53260 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   53262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   53265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   53267 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   53270 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   53273 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   53276 */     GIR_RootConstrainSelectedInstOperands,
     /*   53277 */     // GIR_Coverage, 34119,
     /*   53277 */     GIR_EraseRootFromParent_Done,
     /*   53278 */   // Label 519: @53278
     /*   53278 */   GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(53463), // Rule ID 34120 //
     /*   53283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53287 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   53291 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53295 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   53299 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   53303 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   53307 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   53311 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   53315 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   53319 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   53323 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53327 */     // MIs[3] z
     /*   53327 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   53332 */     // MIs[3] x
     /*   53332 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   53337 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   53341 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   53343 */     // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   53343 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   53346 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53350 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53355 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   53359 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53364 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   53367 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53371 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53376 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   53380 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53385 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   53388 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53392 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53397 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
     /*   53401 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53406 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   53409 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53413 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53418 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
     /*   53422 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53427 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   53430 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   53434 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53439 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   53442 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   53445 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   53447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   53450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   53452 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   53455 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   53458 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   53461 */     GIR_RootConstrainSelectedInstOperands,
     /*   53462 */     // GIR_Coverage, 34120,
     /*   53462 */     GIR_EraseRootFromParent_Done,
     /*   53463 */   // Label 520: @53463
     /*   53463 */   GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(53648), // Rule ID 34113 //
     /*   53468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53472 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   53476 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53480 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   53484 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   53488 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   53492 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   53496 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   53500 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   53504 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   53508 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53512 */     // MIs[3] x
     /*   53512 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   53517 */     // MIs[3] z
     /*   53517 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   53522 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   53526 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   53528 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   53528 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   53531 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53535 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53540 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   53544 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53549 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   53552 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53556 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53561 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   53565 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53570 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   53573 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53577 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53582 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   53586 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53591 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   53594 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53598 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53603 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   53607 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53612 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   53615 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   53619 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53624 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   53627 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   53630 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   53632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   53635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   53637 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   53640 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   53643 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   53646 */     GIR_RootConstrainSelectedInstOperands,
     /*   53647 */     // GIR_Coverage, 34113,
     /*   53647 */     GIR_EraseRootFromParent_Done,
     /*   53648 */   // Label 521: @53648
     /*   53648 */   GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(53833), // Rule ID 34114 //
     /*   53653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53657 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   53661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   53669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   53673 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   53677 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   53681 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   53685 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   53689 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   53693 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53697 */     // MIs[3] z
     /*   53697 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   53702 */     // MIs[3] x
     /*   53702 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   53707 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   53711 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   53713 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   53713 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   53716 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53720 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53725 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   53729 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53734 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   53737 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53741 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53746 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   53750 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53755 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   53758 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53762 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53767 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   53771 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53776 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   53779 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53783 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53788 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
     /*   53792 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53797 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   53800 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   53804 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53809 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   53812 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   53815 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   53817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   53820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   53822 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   53825 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   53828 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   53831 */     GIR_RootConstrainSelectedInstOperands,
     /*   53832 */     // GIR_Coverage, 34114,
     /*   53832 */     GIR_EraseRootFromParent_Done,
     /*   53833 */   // Label 522: @53833
     /*   53833 */   GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(54018), // Rule ID 34115 //
     /*   53838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53842 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   53846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53850 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   53854 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   53858 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   53862 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   53866 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   53870 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   53874 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   53878 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   53882 */     // MIs[3] x
     /*   53882 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   53887 */     // MIs[3] z
     /*   53887 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   53892 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   53896 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   53898 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   53898 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   53901 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53905 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53910 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   53914 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53919 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   53922 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53926 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53931 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   53935 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53940 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   53943 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53947 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53952 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   53956 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53961 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   53964 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   53968 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53973 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
     /*   53977 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   53982 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   53985 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   53989 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   53994 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   53997 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   54000 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   54002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   54005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   54007 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   54010 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   54013 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   54016 */     GIR_RootConstrainSelectedInstOperands,
     /*   54017 */     // GIR_Coverage, 34115,
     /*   54017 */     GIR_EraseRootFromParent_Done,
     /*   54018 */   // Label 523: @54018
     /*   54018 */   GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(54203), // Rule ID 34116 //
     /*   54023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54027 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   54031 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54035 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   54039 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   54043 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   54047 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   54051 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   54055 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   54059 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   54063 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54067 */     // MIs[3] z
     /*   54067 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   54072 */     // MIs[3] x
     /*   54072 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   54077 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   54081 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   54083 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   54083 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   54086 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54090 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54095 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   54099 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54104 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   54107 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54111 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54116 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   54120 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54125 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   54128 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54132 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54137 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
     /*   54141 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54146 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   54149 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54153 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54158 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
     /*   54162 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54167 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   54170 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   54174 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54179 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   54182 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   54185 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   54187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   54190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   54192 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   54195 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   54198 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   54201 */     GIR_RootConstrainSelectedInstOperands,
     /*   54202 */     // GIR_Coverage, 34116,
     /*   54202 */     GIR_EraseRootFromParent_Done,
     /*   54203 */   // Label 524: @54203
     /*   54203 */   GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(54388), // Rule ID 34107 //
     /*   54208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54212 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   54216 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54220 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   54224 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   54228 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   54232 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54236 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   54240 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   54244 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   54248 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   54252 */     // MIs[3] x
     /*   54252 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   54257 */     // MIs[3] z
     /*   54257 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   54262 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   54266 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   54268 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   54268 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   54271 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54275 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54280 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54284 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54289 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   54292 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54296 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54301 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
     /*   54305 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54310 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   54313 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54317 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54322 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54326 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54331 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   54334 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54338 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54343 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   54347 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54352 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   54355 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   54359 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54364 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   54367 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   54370 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   54372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   54375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   54377 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   54380 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   54383 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   54386 */     GIR_RootConstrainSelectedInstOperands,
     /*   54387 */     // GIR_Coverage, 34107,
     /*   54387 */     GIR_EraseRootFromParent_Done,
     /*   54388 */   // Label 525: @54388
     /*   54388 */   GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(54573), // Rule ID 34108 //
     /*   54393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54397 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   54401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   54409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   54413 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   54417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54421 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   54425 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   54429 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   54433 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   54437 */     // MIs[3] z
     /*   54437 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   54442 */     // MIs[3] x
     /*   54442 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   54447 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   54451 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   54453 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   54453 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   54456 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54460 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54465 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54469 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54474 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   54477 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54481 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54486 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
     /*   54490 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54495 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   54498 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54502 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54507 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54511 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54516 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   54519 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54523 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54528 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   54532 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54537 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   54540 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   54544 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54549 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   54552 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   54555 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   54557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   54560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   54562 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   54565 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   54568 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   54571 */     GIR_RootConstrainSelectedInstOperands,
     /*   54572 */     // GIR_Coverage, 34108,
     /*   54572 */     GIR_EraseRootFromParent_Done,
     /*   54573 */   // Label 526: @54573
     /*   54573 */   GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(54758), // Rule ID 34111 //
     /*   54578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54582 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   54586 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54590 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   54594 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   54598 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   54602 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54606 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   54610 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   54614 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   54618 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   54622 */     // MIs[3] x
     /*   54622 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   54627 */     // MIs[3] z
     /*   54627 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   54632 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   54636 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   54638 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   54638 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   54641 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54645 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54650 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54654 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54659 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   54662 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54666 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54671 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
     /*   54675 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54680 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   54683 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54687 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54692 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54696 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54701 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   54704 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54708 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54713 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   54717 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54722 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   54725 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   54729 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54734 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   54737 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   54740 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   54742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   54745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   54747 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   54750 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   54753 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   54756 */     GIR_RootConstrainSelectedInstOperands,
     /*   54757 */     // GIR_Coverage, 34111,
     /*   54757 */     GIR_EraseRootFromParent_Done,
     /*   54758 */   // Label 527: @54758
     /*   54758 */   GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(54943), // Rule ID 34112 //
     /*   54763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54767 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   54771 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54775 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   54779 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   54783 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   54787 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54791 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   54795 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   54799 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   54803 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   54807 */     // MIs[3] z
     /*   54807 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   54812 */     // MIs[3] x
     /*   54812 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   54817 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   54821 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   54823 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   54823 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   54826 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54830 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54835 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54839 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54844 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   54847 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54851 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54856 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
     /*   54860 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54865 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   54868 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54872 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54877 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   54881 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54886 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   54889 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   54893 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54898 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   54902 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54907 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   54910 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   54914 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   54919 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   54922 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   54925 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   54927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   54930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   54932 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   54935 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   54938 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   54941 */     GIR_RootConstrainSelectedInstOperands,
     /*   54942 */     // GIR_Coverage, 34112,
     /*   54942 */     GIR_EraseRootFromParent_Done,
     /*   54943 */   // Label 528: @54943
     /*   54943 */   GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(55128), // Rule ID 28501 //
     /*   54948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   54952 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   54956 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54960 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   54964 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   54968 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   54972 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   54976 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   54980 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   54984 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   54988 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   54992 */     // MIs[3] x
     /*   54992 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   54997 */     // MIs[3] z
     /*   54997 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   55002 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   55006 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   55008 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   55008 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   55011 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55015 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55020 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55024 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55029 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   55032 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55036 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55041 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
     /*   55045 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55050 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   55053 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55057 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55062 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55066 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55071 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   55074 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55078 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55083 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   55087 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55092 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   55095 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   55099 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55104 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   55107 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   55110 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   55112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   55115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55117 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   55120 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   55123 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   55126 */     GIR_RootConstrainSelectedInstOperands,
     /*   55127 */     // GIR_Coverage, 28501,
     /*   55127 */     GIR_EraseRootFromParent_Done,
     /*   55128 */   // Label 529: @55128
     /*   55128 */   GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(55313), // Rule ID 34106 //
     /*   55133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55137 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55141 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55145 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55149 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55153 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   55157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55161 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   55165 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   55169 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   55173 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   55177 */     // MIs[3] z
     /*   55177 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   55182 */     // MIs[3] x
     /*   55182 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   55187 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   55191 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   55193 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   55193 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   55196 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55200 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55205 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55209 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55214 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   55217 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55221 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55226 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
     /*   55230 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55235 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   55238 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55242 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55247 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55251 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55256 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   55259 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55263 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55268 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   55272 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55277 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   55280 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   55284 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55289 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   55292 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   55295 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   55297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   55300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55302 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   55305 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   55308 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   55311 */     GIR_RootConstrainSelectedInstOperands,
     /*   55312 */     // GIR_Coverage, 34106,
     /*   55312 */     GIR_EraseRootFromParent_Done,
     /*   55313 */   // Label 530: @55313
     /*   55313 */   GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(55498), // Rule ID 34109 //
     /*   55318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55322 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55338 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   55342 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55346 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   55350 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   55354 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   55358 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   55362 */     // MIs[3] x
     /*   55362 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   55367 */     // MIs[3] z
     /*   55367 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   55372 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   55376 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   55378 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   55378 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   55381 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55385 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55390 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55394 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55399 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   55402 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55406 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55411 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
     /*   55415 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55420 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   55423 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55427 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55432 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55436 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55441 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   55444 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55448 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55453 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   55457 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55462 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   55465 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   55469 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55474 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   55477 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   55480 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   55482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   55485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55487 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   55490 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   55493 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   55496 */     GIR_RootConstrainSelectedInstOperands,
     /*   55497 */     // GIR_Coverage, 34109,
     /*   55497 */     GIR_EraseRootFromParent_Done,
     /*   55498 */   // Label 531: @55498
     /*   55498 */   GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(55683), // Rule ID 34110 //
     /*   55503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55507 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55511 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55515 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55519 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55523 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   55527 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55531 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   55535 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   55539 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   55543 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   55547 */     // MIs[3] z
     /*   55547 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   55552 */     // MIs[3] x
     /*   55552 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   55557 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   55561 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   55563 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
     /*   55563 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   55566 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55570 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55575 */     GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55579 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55584 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   55587 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55591 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55596 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
     /*   55600 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55605 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   55608 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55612 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55617 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   55621 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55626 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   55629 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   55633 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55638 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   55642 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55647 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   55650 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   55654 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   55659 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   55662 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   55665 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   55667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   55670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55672 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   55675 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   55678 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   55681 */     GIR_RootConstrainSelectedInstOperands,
     /*   55682 */     // GIR_Coverage, 34110,
     /*   55682 */     GIR_EraseRootFromParent_Done,
     /*   55683 */   // Label 532: @55683
     /*   55683 */   GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(55736), // Rule ID 34072 //
     /*   55688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55692 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55696 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   55700 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55704 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55708 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   55710 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   55714 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   55718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   55720 */     // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })<<P:Predicate_not_oneuse>>, i32:{ *:[i32] }:$y)<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$x, VSrc_b32:{ *:[i32] }:$y, -1:{ *:[i32] })
     /*   55720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   55723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55725 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   55729 */     GIR_RootToRootCopy, /*OpIdx*/2, // y
     /*   55731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*   55734 */     GIR_RootConstrainSelectedInstOperands,
     /*   55735 */     // GIR_Coverage, 34072,
     /*   55735 */     GIR_EraseRootFromParent_Done,
     /*   55736 */   // Label 533: @55736
     /*   55736 */   GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(55789), // Rule ID 28026 //
     /*   55741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55745 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   55749 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   55753 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55757 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55761 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   55763 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   55767 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   55771 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   55773 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$y, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })<<P:Predicate_not_oneuse>>)<<P:Predicate_anonymous_27144>>  =>  (V_BFI_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$x, VSrc_b32:{ *:[i32] }:$y, -1:{ *:[i32] })
     /*   55773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   55776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   55782 */     GIR_RootToRootCopy, /*OpIdx*/1, // y
     /*   55784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*   55787 */     GIR_RootConstrainSelectedInstOperands,
     /*   55788 */     // GIR_Coverage, 28026,
     /*   55788 */     GIR_EraseRootFromParent_Done,
     /*   55789 */   // Label 534: @55789
     /*   55789 */   GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(55840), // Rule ID 31161 //
     /*   55794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   55798 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55802 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   55806 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55810 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55814 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   55818 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   55822 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   55824 */     // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }), i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   55824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
     /*   55827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   55829 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   55831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   55835 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   55838 */     GIR_RootConstrainSelectedInstOperands,
     /*   55839 */     // GIR_Coverage, 31161,
     /*   55839 */     GIR_EraseRootFromParent_Done,
     /*   55840 */   // Label 535: @55840
     /*   55840 */   GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(55891), // Rule ID 66 //
     /*   55845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   55849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   55853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   55857 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55861 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55865 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   55869 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   55873 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   55875 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }))<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   55875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
     /*   55878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   55880 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   55882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   55886 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   55889 */     GIR_RootConstrainSelectedInstOperands,
     /*   55890 */     // GIR_Coverage, 66,
     /*   55890 */     GIR_EraseRootFromParent_Done,
     /*   55891 */   // Label 536: @55891
     /*   55891 */   GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(55956), // Rule ID 7275 //
     /*   55896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   55899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   55911 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55915 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55919 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   55921 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x
     /*   55925 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y
     /*   55929 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:6:z
     /*   55933 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28492),
     /*   55937 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   55939 */     // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:6:x, i32:{ *:[i32] }:$src1:$pred:6:y)<<P:Predicate_anonymous_28493>>, i32:{ *:[i32] }:$src2:$pred:6:z)<<P:6:Predicate_anonymous_28492>>  =>  (V_AND_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   55939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_OR_B32_e64),
     /*   55942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   55944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   55948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   55952 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   55954 */     GIR_RootConstrainSelectedInstOperands,
     /*   55955 */     // GIR_Coverage, 7275,
     /*   55955 */     GIR_EraseRootFromParent_Done,
     /*   55956 */   // Label 537: @55956
     /*   55956 */   GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(56021), // Rule ID 7276 //
     /*   55961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   55964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   55968 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   55972 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*   55976 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   55980 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   55984 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   55986 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x
     /*   55990 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y
     /*   55994 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:7:z
     /*   55998 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28495),
     /*   56002 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   56004 */     // (or:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:7:x, i32:{ *:[i32] }:$src1:$pred:7:y)<<P:Predicate_anonymous_28496>>, i32:{ *:[i32] }:$src2:$pred:7:z)<<P:7:Predicate_anonymous_28495>>  =>  (V_OR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   56004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR3_B32_e64),
     /*   56007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   56009 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   56013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   56017 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   56019 */     GIR_RootConstrainSelectedInstOperands,
     /*   56020 */     // GIR_Coverage, 7276,
     /*   56020 */     GIR_EraseRootFromParent_Done,
     /*   56021 */   // Label 538: @56021
     /*   56021 */   GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(56086), // Rule ID 7273 //
     /*   56026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   56029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56033 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   56037 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   56041 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   56045 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   56049 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   56051 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
     /*   56055 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y
     /*   56059 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:5:z
     /*   56063 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28490),
     /*   56067 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   56069 */     // (or:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, i32:{ *:[i32] }:$src1:$pred:5:y)<<P:Predicate_anonymous_28480>>, i32:{ *:[i32] }:$src2:$pred:5:z)<<P:5:Predicate_anonymous_28490>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   56069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
     /*   56072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   56074 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   56078 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   56082 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   56084 */     GIR_RootConstrainSelectedInstOperands,
     /*   56085 */     // GIR_Coverage, 7273,
     /*   56085 */     GIR_EraseRootFromParent_Done,
     /*   56086 */   // Label 539: @56086
     /*   56086 */   GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(56151), // Rule ID 31346 //
     /*   56091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   56094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56098 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:6:z
     /*   56102 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   56106 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   56110 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   56114 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   56118 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   56120 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x
     /*   56124 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y
     /*   56128 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28492),
     /*   56132 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   56134 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:6:z, (and:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:6:x, i32:{ *:[i32] }:$src1:$pred:6:y)<<P:Predicate_anonymous_28493>>)<<P:6:Predicate_anonymous_28492>>  =>  (V_AND_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   56134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_OR_B32_e64),
     /*   56137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   56139 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   56143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   56147 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   56149 */     GIR_RootConstrainSelectedInstOperands,
     /*   56150 */     // GIR_Coverage, 31346,
     /*   56150 */     GIR_EraseRootFromParent_Done,
     /*   56151 */   // Label 540: @56151
     /*   56151 */   GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(56216), // Rule ID 31347 //
     /*   56156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   56159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56163 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:7:z
     /*   56167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   56171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*   56175 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   56179 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   56183 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   56185 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x
     /*   56189 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y
     /*   56193 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28495),
     /*   56197 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   56199 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:7:z, (or:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:7:x, i32:{ *:[i32] }:$src1:$pred:7:y)<<P:Predicate_anonymous_28496>>)<<P:7:Predicate_anonymous_28495>>  =>  (V_OR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   56199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR3_B32_e64),
     /*   56202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   56204 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   56208 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   56212 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   56214 */     GIR_RootConstrainSelectedInstOperands,
     /*   56215 */     // GIR_Coverage, 31347,
     /*   56215 */     GIR_EraseRootFromParent_Done,
     /*   56216 */   // Label 541: @56216
     /*   56216 */   GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(56281), // Rule ID 31344 //
     /*   56221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   56224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56228 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:5:z
     /*   56232 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   56236 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*   56240 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   56244 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   56248 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   56250 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
     /*   56254 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y
     /*   56258 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28490),
     /*   56262 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   56264 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:5:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, i32:{ *:[i32] }:$src1:$pred:5:y)<<P:Predicate_anonymous_28480>>)<<P:5:Predicate_anonymous_28490>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   56264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
     /*   56267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   56269 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   56273 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   56277 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   56279 */     GIR_RootConstrainSelectedInstOperands,
     /*   56280 */     // GIR_Coverage, 31344,
     /*   56280 */     GIR_EraseRootFromParent_Done,
     /*   56281 */   // Label 542: @56281
     /*   56281 */   GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(56307), // Rule ID 54 //
     /*   56286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   56290 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   56294 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20781>>  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   56294 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
     /*   56299 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   56305 */     GIR_RootConstrainSelectedInstOperands,
     /*   56306 */     // GIR_Coverage, 54,
     /*   56306 */     GIR_Done,
     /*   56307 */   // Label 543: @56307
     /*   56307 */   GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(56327), // Rule ID 2623 //
     /*   56312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56316 */     // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   56316 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
     /*   56321 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   56325 */     GIR_RootConstrainSelectedInstOperands,
     /*   56326 */     // GIR_Coverage, 2623,
     /*   56326 */     GIR_Done,
     /*   56327 */   // Label 544: @56327
     /*   56327 */   GIM_Reject,
     /*   56328 */ // Label 500: @56328
     /*   56328 */ GIM_Reject,
     /*   56329 */ // Label 486: @56329
     /*   56329 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(65973),
     /*   56334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   56337 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   56340 */   GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(56655), // Rule ID 34069 //
     /*   56345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56349 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   56353 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   56357 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   56361 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   56365 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   56369 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   56373 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   56377 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   56381 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   56385 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   56389 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   56393 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*   56397 */     // MIs[3] x
     /*   56397 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   56402 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   56406 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   56408 */     // (or:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   56408 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   56411 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56415 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56420 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   56426 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56431 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56436 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   56439 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56443 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56448 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   56454 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56459 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56464 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   56467 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56471 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56476 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   56482 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56487 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56492 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   56495 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   56499 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56504 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   56507 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   56510 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   56513 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   56515 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   56518 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56522 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56527 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   56533 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56538 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56543 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   56546 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56550 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56555 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   56561 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56566 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56571 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   56574 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56578 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56583 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   56589 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56594 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56599 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   56602 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   56606 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56611 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   56614 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   56617 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   56620 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   56622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   56625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   56627 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   56630 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   56633 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   56636 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   56639 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56644 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56649 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56654 */     // GIR_Coverage, 34069,
     /*   56654 */     GIR_EraseRootFromParent_Done,
     /*   56655 */   // Label 546: @56655
     /*   56655 */   GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(56970), // Rule ID 34068 //
     /*   56660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56664 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   56668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   56672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   56676 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   56680 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   56684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   56688 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   56692 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   56696 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   56700 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   56704 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   56708 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /*   56712 */     // MIs[3] x
     /*   56712 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   56717 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   56721 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   56723 */     // (or:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   56723 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   56726 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56730 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56735 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   56741 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56746 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56751 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   56754 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56758 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56763 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   56769 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56774 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56779 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   56782 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56786 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56791 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   56797 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56802 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56807 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   56810 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   56814 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56819 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   56822 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   56825 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   56828 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   56830 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   56833 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56837 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56842 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   56848 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56853 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56858 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   56861 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56865 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56870 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   56876 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56881 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56886 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   56889 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   56893 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56898 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   56904 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56909 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   56917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   56921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   56926 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   56929 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   56932 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   56935 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   56937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   56940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   56942 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   56945 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   56948 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   56951 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   56954 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56959 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56964 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   56969 */     // GIR_Coverage, 34068,
     /*   56969 */     GIR_EraseRootFromParent_Done,
     /*   56970 */   // Label 547: @56970
     /*   56970 */   GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(57285), // Rule ID 34067 //
     /*   56975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   56979 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   56983 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   56987 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   56991 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   56995 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   56999 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   57003 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   57007 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   57011 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   57015 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   57019 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57023 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*   57027 */     // MIs[3] x
     /*   57027 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   57032 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   57036 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   57038 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   57038 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   57041 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57045 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57050 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   57056 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57061 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57066 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   57069 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57073 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57078 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   57084 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57089 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57094 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   57097 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57101 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57106 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   57112 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57117 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57122 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   57125 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   57129 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57134 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   57137 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   57140 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   57143 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   57145 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   57148 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57152 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57157 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   57163 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57168 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57173 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   57176 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57180 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57185 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   57191 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57196 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57201 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   57204 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57208 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57213 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   57219 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57224 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57229 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   57232 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   57236 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57241 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   57244 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   57247 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   57250 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   57252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   57255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   57257 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   57260 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   57263 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   57266 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   57269 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57274 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57279 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57284 */     // GIR_Coverage, 34067,
     /*   57284 */     GIR_EraseRootFromParent_Done,
     /*   57285 */   // Label 548: @57285
     /*   57285 */   GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(57600), // Rule ID 34066 //
     /*   57290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57294 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   57298 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57302 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   57306 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   57310 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   57314 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   57318 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   57322 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   57326 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 255,
     /*   57330 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   57334 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57338 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /*   57342 */     // MIs[3] x
     /*   57342 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   57347 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   57351 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   57353 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })), (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   57353 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   57356 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57360 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57365 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   57371 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57376 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57381 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   57384 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57388 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57393 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   57399 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57404 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57409 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   57412 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57416 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57421 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   57427 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57432 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57437 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   57440 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   57444 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57449 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   57452 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   57455 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   57458 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   57460 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   57463 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57467 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57472 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   57478 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57483 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57488 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   57491 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57495 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57500 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   57506 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57511 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57516 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   57519 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57523 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57528 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   57534 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57539 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57544 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   57547 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   57551 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57556 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   57559 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   57562 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   57565 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   57567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   57570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   57572 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   57575 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   57578 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   57581 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   57584 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57589 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57594 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57599 */     // GIR_Coverage, 34066,
     /*   57599 */     GIR_EraseRootFromParent_Done,
     /*   57600 */   // Label 549: @57600
     /*   57600 */   GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(57915), // Rule ID 34063 //
     /*   57605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57609 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   57613 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57617 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   57621 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   57625 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   57629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57633 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   57637 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   57641 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   57645 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   57649 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*   57653 */     // MIs[3] x
     /*   57653 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   57658 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   57662 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   57666 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   57668 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   57668 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   57671 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57675 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57680 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   57686 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57691 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57696 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   57699 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57703 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57708 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   57714 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57719 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57724 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   57727 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57731 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57736 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   57742 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57747 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57752 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   57755 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   57759 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57764 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   57767 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   57770 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   57773 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   57775 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   57778 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57782 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57787 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   57793 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57798 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57803 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   57806 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57810 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57815 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   57821 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57826 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57831 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   57834 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57838 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57843 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   57849 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57854 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57859 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   57862 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   57866 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57871 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   57874 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   57877 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   57880 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   57882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   57885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   57887 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   57890 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   57893 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   57896 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   57899 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57904 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57909 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   57914 */     // GIR_Coverage, 34063,
     /*   57914 */     GIR_EraseRootFromParent_Done,
     /*   57915 */   // Label 550: @57915
     /*   57915 */   GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(58230), // Rule ID 34065 //
     /*   57920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   57924 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   57928 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57932 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   57936 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   57940 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   57944 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   57948 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   57952 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   57956 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   57960 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   57964 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*   57968 */     // MIs[3] x
     /*   57968 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   57973 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   57977 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   57981 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   57983 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y), (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   57983 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   57986 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   57990 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   57995 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   58001 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58006 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58011 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   58014 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58018 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58023 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   58029 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58034 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58039 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   58042 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58046 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58051 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   58057 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58062 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58067 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   58070 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   58074 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58079 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   58082 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   58085 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   58088 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   58090 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   58093 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58097 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58102 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   58108 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58113 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58118 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   58121 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58125 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58130 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   58136 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58141 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58146 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   58149 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58153 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58158 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   58164 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58169 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58174 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   58177 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   58181 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58186 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   58189 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   58192 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   58195 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   58197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   58200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   58202 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   58205 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   58208 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   58211 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   58214 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58219 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58224 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58229 */     // GIR_Coverage, 34065,
     /*   58229 */     GIR_EraseRootFromParent_Done,
     /*   58230 */   // Label 551: @58230
     /*   58230 */   GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(58545), // Rule ID 28023 //
     /*   58235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58239 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   58243 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   58247 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   58251 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   58255 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   58259 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   58263 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   58267 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   58271 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   58275 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   58279 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*   58283 */     // MIs[3] x
     /*   58283 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   58288 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   58292 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   58296 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   58298 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   58298 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   58301 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58305 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58310 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   58316 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58321 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58326 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   58329 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58333 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58338 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   58344 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58349 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58354 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   58357 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58361 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58366 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   58372 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58377 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58382 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   58385 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   58389 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58394 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   58397 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   58400 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   58403 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   58405 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   58408 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58412 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58417 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   58423 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58428 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58433 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   58436 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58440 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58445 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   58451 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58456 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58461 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   58464 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58468 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58473 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   58479 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58484 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58489 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   58492 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   58496 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58501 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   58504 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   58507 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   58510 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   58512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   58515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   58517 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   58520 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   58523 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   58526 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   58529 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58534 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58539 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58544 */     // GIR_Coverage, 28023,
     /*   58544 */     GIR_EraseRootFromParent_Done,
     /*   58545 */   // Label 552: @58545
     /*   58545 */   GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(58860), // Rule ID 34064 //
     /*   58550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58554 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   58558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   58562 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   58566 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   58570 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   58574 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   58578 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   58582 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   58586 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   58590 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   58594 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*   58598 */     // MIs[3] x
     /*   58598 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   58603 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 255,
     /*   58607 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   58611 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   58613 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   58613 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   58616 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58620 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58625 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   58631 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58636 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58641 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   58644 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58648 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58653 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   58659 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58664 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58669 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   58672 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58676 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58681 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   58687 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58692 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58697 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   58700 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   58704 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58709 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   58712 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   58715 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   58718 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   58720 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   58723 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58727 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58732 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   58738 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58743 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58748 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   58751 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58755 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58760 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   58766 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58771 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58776 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   58779 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58783 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58788 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   58794 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58799 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58804 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   58807 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   58811 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58816 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   58819 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   58822 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   58825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   58827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   58830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   58832 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   58835 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   58838 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   58841 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   58844 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58849 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58854 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58859 */     // GIR_Coverage, 34064,
     /*   58859 */     GIR_EraseRootFromParent_Done,
     /*   58860 */   // Label 553: @58860
     /*   58860 */   GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(59268), // Rule ID 34132 //
     /*   58865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58869 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   58873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   58877 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   58881 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   58885 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   58889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   58893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   58897 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   58901 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   58905 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   58909 */     // MIs[3] x
     /*   58909 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   58914 */     // MIs[3] z
     /*   58914 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   58919 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   58923 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   58925 */     // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   58925 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   58928 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58932 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58937 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   58943 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58948 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58953 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   58956 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58960 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58965 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   58971 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   58976 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   58981 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   58984 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   58988 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   58993 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   58999 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59004 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59009 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   59012 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59016 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59021 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   59027 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59032 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59037 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   59040 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   59044 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59049 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   59052 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   59055 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   59057 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   59060 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   59064 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59069 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   59072 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   59075 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   59078 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   59080 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   59083 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59087 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59092 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   59098 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59103 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59108 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   59111 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59115 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59120 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   59126 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59131 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59136 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   59139 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59143 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59148 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   59154 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59159 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59164 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   59167 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59171 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59176 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   59182 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59187 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59192 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   59195 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   59199 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59204 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   59207 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   59210 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   59212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   59215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   59219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59224 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   59227 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   59230 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   59233 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   59235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   59238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   59240 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   59243 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   59246 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   59249 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   59252 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59257 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59262 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59267 */     // GIR_Coverage, 34132,
     /*   59267 */     GIR_EraseRootFromParent_Done,
     /*   59268 */   // Label 554: @59268
     /*   59268 */   GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(59676), // Rule ID 34133 //
     /*   59273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59277 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   59281 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   59285 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   59289 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   59293 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   59297 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   59301 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   59305 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   59309 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   59313 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   59317 */     // MIs[3] z
     /*   59317 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   59322 */     // MIs[3] x
     /*   59322 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   59327 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   59331 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   59333 */     // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   59333 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   59336 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59340 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59345 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   59351 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59356 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59361 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   59364 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59368 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59373 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   59379 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59384 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59389 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   59392 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59396 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59401 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   59407 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59412 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59417 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   59420 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59424 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59429 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   59435 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59440 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59445 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   59448 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   59452 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59457 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   59460 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   59463 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   59465 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   59468 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   59472 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59477 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   59480 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   59483 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   59486 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   59488 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   59491 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59495 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59500 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   59506 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59511 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59516 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   59519 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59523 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59528 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   59534 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59539 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59544 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   59547 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59551 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59556 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   59562 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59567 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59572 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   59575 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59579 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59584 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   59590 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59595 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59600 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   59603 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   59607 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59612 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   59615 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   59618 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   59620 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   59623 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   59627 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59632 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   59635 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   59638 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   59641 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   59643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   59646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   59648 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   59651 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   59654 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   59657 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   59660 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59665 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59670 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59675 */     // GIR_Coverage, 34133,
     /*   59675 */     GIR_EraseRootFromParent_Done,
     /*   59676 */   // Label 555: @59676
     /*   59676 */   GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(60084), // Rule ID 34134 //
     /*   59681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59685 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   59689 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   59693 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   59697 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   59701 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   59705 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   59709 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   59713 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   59717 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   59721 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   59725 */     // MIs[3] x
     /*   59725 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   59730 */     // MIs[3] z
     /*   59730 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   59735 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   59739 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   59741 */     // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   59741 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   59744 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59748 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59753 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   59759 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59764 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59769 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   59772 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59776 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59781 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   59787 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59792 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59797 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   59800 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59804 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59809 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   59815 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59820 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59825 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   59828 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59832 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59837 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   59843 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59848 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59853 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   59856 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   59860 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59865 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   59868 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   59871 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   59873 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   59876 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   59880 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59885 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   59888 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   59891 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   59894 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   59896 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   59899 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59903 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59908 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   59914 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59919 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59924 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   59927 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59931 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59936 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   59942 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59947 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59952 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   59955 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59959 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59964 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   59970 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   59975 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   59980 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   59983 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   59987 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   59992 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   59998 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60003 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60008 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   60011 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   60015 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60020 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   60023 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   60026 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   60028 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   60031 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   60035 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60040 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   60043 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   60046 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   60049 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   60051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   60054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   60056 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   60059 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   60062 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   60065 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   60068 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60073 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60078 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60083 */     // GIR_Coverage, 34134,
     /*   60083 */     GIR_EraseRootFromParent_Done,
     /*   60084 */   // Label 556: @60084
     /*   60084 */   GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(60492), // Rule ID 34135 //
     /*   60089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60093 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   60097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   60101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   60105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   60109 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   60113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   60117 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   60121 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   60125 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   60129 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   60133 */     // MIs[3] z
     /*   60133 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   60138 */     // MIs[3] x
     /*   60138 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   60143 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   60147 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   60149 */     // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   60149 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   60152 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60156 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60161 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   60167 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60172 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60177 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   60180 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60184 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60189 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   60195 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60200 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60205 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   60208 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60212 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60217 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   60223 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60228 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60233 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   60236 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60240 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60245 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   60251 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60256 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60261 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   60264 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   60268 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60273 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   60276 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   60279 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   60281 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   60284 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   60288 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60293 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   60296 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   60299 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   60302 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   60304 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   60307 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60311 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60316 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   60322 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60327 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60332 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   60335 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60339 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60344 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   60350 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60355 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60360 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   60363 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60367 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60372 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   60378 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60383 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60388 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   60391 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60395 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60400 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   60406 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60411 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60416 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   60419 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   60423 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60428 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   60431 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   60434 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   60436 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   60439 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   60443 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60448 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   60451 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   60454 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   60457 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   60459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   60462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   60464 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   60467 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   60470 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   60473 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   60476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60481 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60486 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60491 */     // GIR_Coverage, 34135,
     /*   60491 */     GIR_EraseRootFromParent_Done,
     /*   60492 */   // Label 557: @60492
     /*   60492 */   GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(60900), // Rule ID 34128 //
     /*   60497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60501 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   60505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   60509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   60513 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   60517 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   60521 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   60525 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   60529 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   60533 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   60537 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   60541 */     // MIs[3] x
     /*   60541 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   60546 */     // MIs[3] z
     /*   60546 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   60551 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   60555 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   60557 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   60557 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   60560 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60564 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60569 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   60575 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60580 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60585 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   60588 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60592 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60597 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   60603 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60608 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60613 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   60616 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60620 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60625 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   60631 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60636 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60641 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   60644 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60648 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60653 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   60659 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60664 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60669 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   60672 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   60676 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60681 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   60684 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   60687 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   60689 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   60692 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   60696 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60701 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   60704 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   60707 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   60710 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   60712 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   60715 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60719 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60724 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   60730 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60735 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60740 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   60743 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60747 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60752 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   60758 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60763 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60768 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   60771 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60775 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60780 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   60786 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60791 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60796 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   60799 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60803 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60808 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   60814 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60819 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60824 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   60827 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   60831 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60836 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   60839 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   60842 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   60844 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   60847 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   60851 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60856 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   60859 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   60862 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   60865 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   60867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   60870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   60872 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   60875 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   60878 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   60881 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   60884 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60889 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60894 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60899 */     // GIR_Coverage, 34128,
     /*   60899 */     GIR_EraseRootFromParent_Done,
     /*   60900 */   // Label 558: @60900
     /*   60900 */   GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(61308), // Rule ID 34129 //
     /*   60905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60909 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   60913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   60917 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   60921 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   60925 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   60929 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   60933 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   60937 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   60941 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   60945 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   60949 */     // MIs[3] z
     /*   60949 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   60954 */     // MIs[3] x
     /*   60954 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   60959 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   60963 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   60965 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   60965 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   60968 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   60972 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   60977 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   60983 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   60988 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   60993 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   60996 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61000 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61005 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   61011 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61016 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61021 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   61024 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61028 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61033 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   61039 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61044 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61049 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   61052 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61056 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61061 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   61067 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61072 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61077 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   61080 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   61084 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61089 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   61092 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   61095 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   61097 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   61100 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   61104 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61109 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   61112 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   61115 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   61118 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   61120 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   61123 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61127 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61132 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   61138 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61143 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61148 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   61151 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61155 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61160 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   61166 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61171 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61176 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   61179 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61183 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61188 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   61194 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61199 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61204 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   61207 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61211 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61216 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   61222 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61227 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61232 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   61235 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   61239 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61244 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   61247 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   61250 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   61252 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   61255 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   61259 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61264 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   61267 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   61270 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   61273 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   61275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   61278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   61280 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   61283 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   61286 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   61289 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   61292 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61297 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61302 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61307 */     // GIR_Coverage, 34129,
     /*   61307 */     GIR_EraseRootFromParent_Done,
     /*   61308 */   // Label 559: @61308
     /*   61308 */   GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(61716), // Rule ID 34130 //
     /*   61313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61317 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   61321 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   61325 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   61329 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   61333 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   61337 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   61341 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   61345 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   61349 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   61353 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   61357 */     // MIs[3] x
     /*   61357 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   61362 */     // MIs[3] z
     /*   61362 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   61367 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   61371 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   61373 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   61373 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   61376 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61380 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61385 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   61391 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61396 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61401 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   61404 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61408 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61413 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   61419 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61424 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61429 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   61432 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61436 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61441 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   61447 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61452 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61457 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   61460 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61464 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61469 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   61475 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61480 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61485 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   61488 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   61492 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61497 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   61500 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   61503 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   61505 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   61508 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   61512 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61517 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   61520 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   61523 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   61526 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   61528 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   61531 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61535 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61540 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   61546 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61551 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61556 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   61559 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61563 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61568 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   61574 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61579 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61584 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   61587 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61591 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61596 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   61602 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61607 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61612 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   61615 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61619 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61624 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   61630 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61635 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61640 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   61643 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   61647 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61652 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   61655 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   61658 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   61660 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   61663 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   61667 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61672 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   61675 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   61678 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   61681 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   61683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   61686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   61688 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   61691 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   61694 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   61697 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   61700 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61705 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61710 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61715 */     // GIR_Coverage, 34130,
     /*   61715 */     GIR_EraseRootFromParent_Done,
     /*   61716 */   // Label 560: @61716
     /*   61716 */   GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(62124), // Rule ID 34131 //
     /*   61721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61725 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   61729 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   61733 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   61737 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   61741 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   61745 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*   61749 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   61753 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   61757 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   61761 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*   61765 */     // MIs[3] z
     /*   61765 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   61770 */     // MIs[3] x
     /*   61770 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   61775 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   61779 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   61781 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   61781 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   61784 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61788 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61793 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   61799 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61804 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61809 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   61812 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61816 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61821 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   61827 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61832 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61837 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   61840 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61844 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61849 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   61855 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61860 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61865 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   61868 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61872 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61877 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   61883 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61888 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61893 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   61896 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   61900 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61905 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   61908 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   61911 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   61913 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   61916 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   61920 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61925 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   61928 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   61931 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   61934 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   61936 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   61939 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61943 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61948 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   61954 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61959 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61964 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   61967 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61971 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   61976 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   61982 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   61987 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   61992 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   61995 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   61999 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62004 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   62010 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62015 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62020 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   62023 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62027 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62032 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   62038 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62043 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62048 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   62051 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   62055 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62060 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   62063 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   62066 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   62068 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   62071 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   62075 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62080 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   62083 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   62086 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   62089 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   62091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   62094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   62096 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   62099 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   62102 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   62105 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   62108 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62113 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62118 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62123 */     // GIR_Coverage, 34131,
     /*   62123 */     GIR_EraseRootFromParent_Done,
     /*   62124 */   // Label 561: @62124
     /*   62124 */   GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(62532), // Rule ID 34122 //
     /*   62129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62133 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   62137 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   62141 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   62145 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   62149 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   62153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   62157 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   62161 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   62165 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   62169 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   62173 */     // MIs[3] x
     /*   62173 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   62178 */     // MIs[3] z
     /*   62178 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   62183 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   62187 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   62189 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   62189 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   62192 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62196 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62201 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   62207 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62212 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62217 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   62220 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62224 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62229 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   62235 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62240 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62245 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   62248 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62252 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62257 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   62263 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62268 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62273 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   62276 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62280 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62285 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   62291 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62296 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62301 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   62304 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   62308 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62313 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   62316 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   62319 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   62321 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   62324 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   62328 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62333 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   62336 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   62339 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   62342 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   62344 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   62347 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62351 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62356 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   62362 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62367 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62372 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   62375 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62379 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62384 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   62390 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62395 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62400 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   62403 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62407 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62412 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   62418 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62423 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62428 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   62431 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62435 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62440 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   62446 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62451 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62456 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   62459 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   62463 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62468 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   62471 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   62474 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   62476 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   62479 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   62483 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62488 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   62491 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   62494 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   62497 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   62499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   62502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   62504 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   62507 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   62510 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   62513 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   62516 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62521 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62526 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62531 */     // GIR_Coverage, 34122,
     /*   62531 */     GIR_EraseRootFromParent_Done,
     /*   62532 */   // Label 562: @62532
     /*   62532 */   GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(62940), // Rule ID 34123 //
     /*   62537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62541 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   62545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   62549 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   62553 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   62557 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   62561 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   62565 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   62569 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   62573 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   62577 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   62581 */     // MIs[3] z
     /*   62581 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   62586 */     // MIs[3] x
     /*   62586 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   62591 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   62595 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   62597 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   62597 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   62600 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62604 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62609 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   62615 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62620 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62625 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   62628 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62632 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62637 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   62643 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62648 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62653 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   62656 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62660 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62665 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   62671 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62676 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62681 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   62684 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62688 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62693 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   62699 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62704 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62709 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   62712 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   62716 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62721 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   62724 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   62727 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   62729 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   62732 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   62736 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62741 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   62744 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   62747 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   62750 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   62752 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   62755 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62759 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62764 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   62770 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62775 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62780 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   62783 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62787 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62792 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   62798 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62803 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62808 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   62811 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62815 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62820 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   62826 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62831 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62836 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   62839 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   62843 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62848 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   62854 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62859 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62864 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   62867 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   62871 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62876 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   62879 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   62882 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   62884 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   62887 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   62891 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   62896 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   62899 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   62902 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   62905 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   62907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   62910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   62912 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   62915 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   62918 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   62921 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   62924 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62929 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62934 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   62939 */     // GIR_Coverage, 34123,
     /*   62939 */     GIR_EraseRootFromParent_Done,
     /*   62940 */   // Label 563: @62940
     /*   62940 */   GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(63348), // Rule ID 34126 //
     /*   62945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   62949 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   62953 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   62957 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   62961 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   62965 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   62969 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   62973 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   62977 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   62981 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   62985 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   62989 */     // MIs[3] x
     /*   62989 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   62994 */     // MIs[3] z
     /*   62994 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   62999 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   63003 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   63005 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   63005 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   63008 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63012 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63017 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   63023 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63028 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63033 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   63036 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63040 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63045 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   63051 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63056 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63061 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   63064 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63068 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63073 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   63079 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63084 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63089 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   63092 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63096 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63101 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   63107 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63112 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63117 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   63120 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   63124 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63129 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   63132 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   63135 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   63137 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   63140 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   63144 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63149 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   63152 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   63155 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   63158 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   63160 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   63163 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63167 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63172 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   63178 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63183 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63188 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   63191 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63195 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63200 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   63206 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63211 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63216 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   63219 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63223 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63228 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   63234 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63239 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63244 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   63247 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63251 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63256 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   63262 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63267 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63272 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   63275 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   63279 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63284 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   63287 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   63290 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   63292 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   63295 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   63299 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63304 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   63307 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   63310 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   63313 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   63315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   63318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   63320 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   63323 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   63326 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   63329 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   63332 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63337 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63342 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63347 */     // GIR_Coverage, 34126,
     /*   63347 */     GIR_EraseRootFromParent_Done,
     /*   63348 */   // Label 564: @63348
     /*   63348 */   GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(63756), // Rule ID 34127 //
     /*   63353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63357 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   63361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   63365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   63369 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   63373 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   63377 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   63381 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   63385 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   63389 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   63393 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   63397 */     // MIs[3] z
     /*   63397 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   63402 */     // MIs[3] x
     /*   63402 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   63407 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   63411 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   63413 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   63413 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   63416 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63420 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63425 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   63431 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63436 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63441 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   63444 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63448 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63453 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   63459 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63464 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63469 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   63472 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63476 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63481 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   63487 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63492 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63497 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   63500 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63504 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63509 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   63515 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63520 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63525 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   63528 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   63532 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63537 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   63540 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   63543 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   63545 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   63548 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   63552 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63557 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   63560 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   63563 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   63566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   63568 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   63571 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63575 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63580 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   63586 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63591 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63596 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   63599 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63603 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63608 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   63614 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63619 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63624 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   63627 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63631 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63636 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   63642 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63647 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63652 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   63655 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63659 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63664 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   63670 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63675 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63680 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   63683 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   63687 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63692 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   63695 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   63698 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   63700 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   63703 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   63707 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63712 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   63715 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   63718 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   63721 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   63723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   63726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   63728 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   63731 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   63734 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   63737 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   63740 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63745 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63750 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63755 */     // GIR_Coverage, 34127,
     /*   63755 */     GIR_EraseRootFromParent_Done,
     /*   63756 */   // Label 565: @63756
     /*   63756 */   GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(64164), // Rule ID 28502 //
     /*   63761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63765 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   63769 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   63773 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   63777 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   63781 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   63785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   63789 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   63793 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   63797 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   63801 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   63805 */     // MIs[3] x
     /*   63805 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   63810 */     // MIs[3] z
     /*   63810 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   63815 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   63819 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   63821 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   63821 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   63824 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63828 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63833 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   63839 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63844 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63849 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   63852 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63856 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63861 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   63867 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63872 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63877 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   63880 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63884 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63889 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   63895 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63900 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63905 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   63908 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63912 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63917 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   63923 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63928 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   63933 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   63936 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   63940 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63945 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   63948 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   63951 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   63953 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   63956 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   63960 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63965 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   63968 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   63971 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   63974 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   63976 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   63979 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   63983 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   63988 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   63994 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   63999 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64004 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   64007 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64011 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64016 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   64022 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64027 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64032 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   64035 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64039 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64044 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   64050 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64055 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64060 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   64063 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64067 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64072 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   64078 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64083 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64088 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   64091 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   64095 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64100 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   64103 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   64106 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   64108 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   64111 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   64115 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64120 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   64123 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   64126 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   64129 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   64131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   64134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   64136 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   64139 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   64142 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   64145 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   64148 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64153 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64158 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64163 */     // GIR_Coverage, 28502,
     /*   64163 */     GIR_EraseRootFromParent_Done,
     /*   64164 */   // Label 566: @64164
     /*   64164 */   GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(64572), // Rule ID 34121 //
     /*   64169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64173 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   64177 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   64181 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   64185 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   64189 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   64193 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   64197 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   64201 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   64205 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   64209 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   64213 */     // MIs[3] z
     /*   64213 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   64218 */     // MIs[3] x
     /*   64218 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   64223 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   64227 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   64229 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   64229 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   64232 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64236 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64241 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   64247 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64252 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64257 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   64260 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64264 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64269 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   64275 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64280 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64285 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   64288 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64292 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64297 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   64303 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64308 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64313 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   64316 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64320 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64325 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   64331 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64336 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64341 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   64344 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   64348 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64353 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   64356 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   64359 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   64361 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   64364 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   64368 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64373 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   64376 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   64379 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   64382 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   64384 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   64387 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64391 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64396 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   64402 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64407 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64412 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   64415 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64419 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64424 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   64430 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64435 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64440 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   64443 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64447 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64452 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   64458 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64463 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64468 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   64471 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64475 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64480 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   64486 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64491 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64496 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   64499 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   64503 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64508 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   64511 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   64514 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   64516 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   64519 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   64523 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64528 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   64531 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   64534 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   64537 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   64539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   64542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   64544 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   64547 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   64550 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   64553 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   64556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64561 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64566 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64571 */     // GIR_Coverage, 34121,
     /*   64571 */     GIR_EraseRootFromParent_Done,
     /*   64572 */   // Label 567: @64572
     /*   64572 */   GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(64980), // Rule ID 34124 //
     /*   64577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64581 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   64585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   64589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   64593 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   64597 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   64601 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   64605 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   64609 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   64613 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   64617 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   64621 */     // MIs[3] x
     /*   64621 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   64626 */     // MIs[3] z
     /*   64626 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   64631 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   64635 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   64637 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   64637 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   64640 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64644 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64649 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   64655 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64660 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64665 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   64668 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64672 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64677 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   64683 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64688 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64693 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   64696 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64700 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64705 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   64711 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64716 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64721 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   64724 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64728 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64733 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   64739 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64744 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64749 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   64752 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   64756 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64761 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   64764 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   64767 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   64769 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   64772 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   64776 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64781 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   64784 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   64787 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   64790 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   64792 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   64795 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64799 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64804 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   64810 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64815 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64820 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   64823 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64827 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64832 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   64838 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64843 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64848 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   64851 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64855 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64860 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   64866 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64871 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64876 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   64879 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   64883 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64888 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   64894 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64899 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64904 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   64907 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   64911 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64916 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   64919 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   64922 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   64924 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   64927 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   64931 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   64936 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   64939 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   64942 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   64945 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   64947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   64950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   64952 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   64955 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   64958 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   64961 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   64964 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64969 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64974 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   64979 */     // GIR_Coverage, 34124,
     /*   64979 */     GIR_EraseRootFromParent_Done,
     /*   64980 */   // Label 568: @64980
     /*   64980 */   GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(65388), // Rule ID 34125 //
     /*   64985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   64989 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   64993 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   64997 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   65001 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   65005 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   65009 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*   65013 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   65017 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   65021 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*   65025 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*   65029 */     // MIs[3] z
     /*   65029 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   65034 */     // MIs[3] x
     /*   65034 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*   65039 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   65043 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   65045 */     // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)))<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   65045 */     GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
     /*   65048 */     GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65052 */     GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65057 */     GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   65063 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65068 */     GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65073 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
     /*   65076 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65080 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65085 */     GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   65091 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65096 */     GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65101 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
     /*   65104 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65108 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65113 */     GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   65119 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65124 */     GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65129 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*   65132 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65136 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65141 */     GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   65147 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65152 */     GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65157 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*   65160 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   65164 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65169 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
     /*   65172 */     GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
     /*   65175 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*   65177 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*   65180 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   65184 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65189 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*   65192 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
     /*   65195 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
     /*   65198 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*   65200 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   65203 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65207 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65212 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   65218 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65223 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65228 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   65231 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65235 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65240 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   65246 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65251 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65256 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   65259 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65263 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65268 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   65274 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65279 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65284 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   65287 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65291 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65296 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   65302 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65307 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65312 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   65315 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   65319 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65324 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   65327 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /*   65330 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   65332 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   65335 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   65339 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65344 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   65347 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*   65350 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*   65353 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   65355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   65358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   65360 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   65363 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   65366 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /*   65369 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   65372 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65377 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65382 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65387 */     // GIR_Coverage, 34125,
     /*   65387 */     GIR_EraseRootFromParent_Done,
     /*   65388 */   // Label 569: @65388
     /*   65388 */   GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(65616), // Rule ID 34073 //
     /*   65393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65397 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   65401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   65405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   65409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   65413 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   65415 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   65419 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   65423 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   65425 */     // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })<<P:Predicate_not_oneuse>>, i64:{ *:[i64] }:$y)<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), -1:{ *:[i32] }), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), -1:{ *:[i32] }), sub1:{ *:[i32] })
     /*   65425 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   65428 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65432 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65437 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   65443 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65448 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65453 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   65456 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65460 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65465 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   65471 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65476 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65481 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   65484 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   65488 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65493 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*   65496 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/5,
     /*   65499 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/255,
     /*   65502 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*   65504 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   65507 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65511 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65516 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   65522 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65527 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65532 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   65535 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65539 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65544 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   65550 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65555 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65560 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   65563 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   65567 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65572 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   65575 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   65578 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*   65581 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   65583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   65586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   65588 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   65591 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   65594 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   65597 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   65600 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65605 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65610 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65615 */     // GIR_Coverage, 34073,
     /*   65615 */     GIR_EraseRootFromParent_Done,
     /*   65616 */   // Label 570: @65616
     /*   65616 */   GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(65844), // Rule ID 28027 //
     /*   65621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65625 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   65629 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   65633 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   65637 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   65641 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   65643 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   65647 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27144),
     /*   65651 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   65653 */     // (or:{ *:[i64] } i64:{ *:[i64] }:$y, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })<<P:Predicate_not_oneuse>>)<<P:Predicate_anonymous_27144>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), -1:{ *:[i32] }), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), -1:{ *:[i32] }), sub1:{ *:[i32] })
     /*   65653 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   65656 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65660 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65665 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   65671 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65676 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65681 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /*   65684 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65688 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65693 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   65699 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65704 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65709 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*   65712 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   65716 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65721 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*   65724 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/5,
     /*   65727 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/255,
     /*   65730 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*   65732 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   65735 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65739 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65744 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   65750 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65755 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65760 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   65763 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   65767 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65772 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   65778 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65783 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65788 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   65791 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   65795 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   65800 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   65803 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   65806 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*   65809 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   65811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   65814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   65816 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   65819 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   65822 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*   65825 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   65828 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   65833 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65838 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   65843 */     // GIR_Coverage, 28027,
     /*   65843 */     GIR_EraseRootFromParent_Done,
     /*   65844 */   // Label 571: @65844
     /*   65844 */   GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(65895), // Rule ID 31162 //
     /*   65849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   65853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   65857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   65861 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   65865 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   65869 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   65873 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   65877 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   65879 */     // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }), i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   65879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
     /*   65882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   65884 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   65886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   65890 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   65893 */     GIR_RootConstrainSelectedInstOperands,
     /*   65894 */     // GIR_Coverage, 31162,
     /*   65894 */     GIR_EraseRootFromParent_Done,
     /*   65895 */   // Label 572: @65895
     /*   65895 */   GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(65946), // Rule ID 67 //
     /*   65900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   65904 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   65908 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   65912 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   65916 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   65920 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   65924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   65928 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   65930 */     // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }))<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   65930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
     /*   65933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   65935 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   65937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   65941 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   65944 */     GIR_RootConstrainSelectedInstOperands,
     /*   65945 */     // GIR_Coverage, 67,
     /*   65945 */     GIR_EraseRootFromParent_Done,
     /*   65946 */   // Label 573: @65946
     /*   65946 */   GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(65972), // Rule ID 55 //
     /*   65951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   65955 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   65959 */     // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_20781>>  =>  (S_OR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   65959 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64),
     /*   65964 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   65970 */     GIR_RootConstrainSelectedInstOperands,
     /*   65971 */     // GIR_Coverage, 55,
     /*   65971 */     GIR_Done,
     /*   65972 */   // Label 574: @65972
     /*   65972 */   GIM_Reject,
     /*   65973 */ // Label 545: @65973
     /*   65973 */ GIM_Reject,
     /*   65974 */ // Label 487: @65974
     /*   65974 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(66124),
     /*   65979 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   65982 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   65985 */   GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(66044), // Rule ID 31331 //
     /*   65990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   65994 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   65998 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   66002 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   66006 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   66010 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   66014 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   66020 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   66022 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   66026 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   66028 */     // (or:{ *:[v2i16] } (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }), v2i16:{ *:[v2i16] }:$src0)<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
     /*   66028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
     /*   66031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66033 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   66035 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   66039 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66042 */     GIR_RootConstrainSelectedInstOperands,
     /*   66043 */     // GIR_Coverage, 31331,
     /*   66043 */     GIR_EraseRootFromParent_Done,
     /*   66044 */   // Label 576: @66044
     /*   66044 */   GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(66103), // Rule ID 4819 //
     /*   66049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   66053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   66057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   66061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   66065 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   66069 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   66073 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   66079 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   66081 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   66085 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   66087 */     // (or:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }))<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
     /*   66087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
     /*   66090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66092 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   66094 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   66098 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66101 */     GIR_RootConstrainSelectedInstOperands,
     /*   66102 */     // GIR_Coverage, 4819,
     /*   66102 */     GIR_EraseRootFromParent_Done,
     /*   66103 */   // Label 577: @66103
     /*   66103 */   GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(66123), // Rule ID 7166 //
     /*   66108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   66112 */     // (or:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1)  =>  (V_OR_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
     /*   66112 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
     /*   66117 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   66121 */     GIR_RootConstrainSelectedInstOperands,
     /*   66122 */     // GIR_Coverage, 7166,
     /*   66122 */     GIR_Done,
     /*   66123 */   // Label 578: @66123
     /*   66123 */   GIM_Reject,
     /*   66124 */ // Label 575: @66124
     /*   66124 */ GIM_Reject,
     /*   66125 */ // Label 488: @66125
     /*   66125 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(66265),
     /*   66130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   66133 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   66136 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   66140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66144 */   GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(66195), // Rule ID 31333 //
     /*   66149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   66157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   66161 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   66165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   66169 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   66175 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   66177 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   66179 */     // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }), v2i32:{ *:[v2i32] }:$src0)<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
     /*   66179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
     /*   66182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66184 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   66186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   66190 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66193 */     GIR_RootConstrainSelectedInstOperands,
     /*   66194 */     // GIR_Coverage, 31333,
     /*   66194 */     GIR_EraseRootFromParent_Done,
     /*   66195 */   // Label 580: @66195
     /*   66195 */   GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(66246), // Rule ID 4821 //
     /*   66200 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   66204 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   66208 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   66212 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   66216 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   66220 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   66226 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   66228 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   66230 */     // (or:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }))<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
     /*   66230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
     /*   66233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66235 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   66237 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   66241 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66244 */     GIR_RootConstrainSelectedInstOperands,
     /*   66245 */     // GIR_Coverage, 4821,
     /*   66245 */     GIR_EraseRootFromParent_Done,
     /*   66246 */   // Label 581: @66246
     /*   66246 */   GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(66264), // Rule ID 4800 //
     /*   66251 */     // (or:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, v2i32:{ *:[v2i32] }:$y)<<P:Predicate_anonymous_20781>>  =>  (S_OR_B64:{ *:[v2i32] }:{ *:[i1] } SReg_64:{ *:[v2i32] }:$x, SReg_64:{ *:[v2i32] }:$y)
     /*   66251 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64),
     /*   66256 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   66262 */     GIR_RootConstrainSelectedInstOperands,
     /*   66263 */     // GIR_Coverage, 4800,
     /*   66263 */     GIR_Done,
     /*   66264 */   // Label 582: @66264
     /*   66264 */   GIM_Reject,
     /*   66265 */ // Label 579: @66265
     /*   66265 */ GIM_Reject,
     /*   66266 */ // Label 489: @66266
     /*   66266 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(66388),
     /*   66271 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   66274 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*   66277 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20781),
     /*   66281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66285 */   GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(66336), // Rule ID 31332 //
     /*   66290 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66294 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   66298 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   66302 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*   66306 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   66310 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   66316 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   66318 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   66320 */     // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }), v4i16:{ *:[v4i16] }:$src0)<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
     /*   66320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
     /*   66323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66325 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*   66327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   66331 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66334 */     GIR_RootConstrainSelectedInstOperands,
     /*   66335 */     // GIR_Coverage, 31332,
     /*   66335 */     GIR_EraseRootFromParent_Done,
     /*   66336 */   // Label 584: @66336
     /*   66336 */   GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(66387), // Rule ID 4820 //
     /*   66341 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   66345 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   66349 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   66353 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*   66357 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   66361 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*   66367 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*   66369 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   66371 */     // (or:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src0, (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }))<<P:Predicate_anonymous_20781>>  =>  (S_ORN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
     /*   66371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
     /*   66374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66376 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   66378 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*   66382 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66385 */     GIR_RootConstrainSelectedInstOperands,
     /*   66386 */     // GIR_Coverage, 4820,
     /*   66386 */     GIR_EraseRootFromParent_Done,
     /*   66387 */   // Label 585: @66387
     /*   66387 */   GIM_Reject,
     /*   66388 */ // Label 583: @66388
     /*   66388 */ GIM_Reject,
     /*   66389 */ // Label 490: @66389
     /*   66389 */ GIM_Reject,
     /*   66390 */ // Label 5: @66390
     /*   66390 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 592*/ GIMT_Encode4(73947),
     /*   66401 */ /*GILLT_s1*//*Label 586*/ GIMT_Encode4(66425),
     /*   66405 */ /*GILLT_s16*//*Label 587*/ GIMT_Encode4(66946),
     /*   66409 */ /*GILLT_s32*//*Label 588*/ GIMT_Encode4(67061),
     /*   66413 */ /*GILLT_s64*//*Label 589*/ GIMT_Encode4(68860),
     /*   66417 */ /*GILLT_v2s16*//*Label 590*/ GIMT_Encode4(71493),
     /*   66421 */ /*GILLT_v2s32*//*Label 591*/ GIMT_Encode4(71520),
     /*   66425 */ // Label 586: @66425
     /*   66425 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(66945),
     /*   66430 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*   66433 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*   66436 */   GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(66490), // Rule ID 4822 //
     /*   66441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   66444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   66448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*   66456 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*   66460 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*   66464 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66466 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66470 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66472 */     // (xor:{ *:[i1] } (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i1] })  =>  (S_NOR_B32:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)
     /*   66472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B32),
     /*   66475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   66481 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   66485 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66488 */     GIR_RootConstrainSelectedInstOperands,
     /*   66489 */     // GIR_Coverage, 4822,
     /*   66489 */     GIR_EraseRootFromParent_Done,
     /*   66490 */   // Label 594: @66490
     /*   66490 */   GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(66544), // Rule ID 4823 //
     /*   66495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   66498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66502 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66506 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*   66510 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*   66514 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*   66518 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66520 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66524 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66526 */     // (xor:{ *:[i1] } (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i1] })  =>  (S_NOR_B64:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)
     /*   66526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B64),
     /*   66529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   66535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   66539 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   66542 */     GIR_RootConstrainSelectedInstOperands,
     /*   66543 */     // GIR_Coverage, 4823,
     /*   66543 */     GIR_EraseRootFromParent_Done,
     /*   66544 */   // Label 595: @66544
     /*   66544 */   GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(66614), // Rule ID 28285 //
     /*   66549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   66552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66560 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   66564 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   66568 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66570 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45298),
     /*   66574 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66578 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66580 */     // (xor:{ *:[i1] } (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_45297>><<P:Predicate_anonymous_45298>>, -1:{ *:[i1] })  =>  (V_CMP_NE_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*   66580 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   66583 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   66587 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   66592 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   66595 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*   66599 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   66601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64),
     /*   66604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66606 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   66609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   66612 */     GIR_RootConstrainSelectedInstOperands,
     /*   66613 */     // GIR_Coverage, 28285,
     /*   66613 */     GIR_EraseRootFromParent_Done,
     /*   66614 */   // Label 596: @66614
     /*   66614 */   GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(66684), // Rule ID 28286 //
     /*   66619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   66622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66626 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66630 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   66634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   66638 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66640 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45298),
     /*   66644 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66648 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66650 */     // (xor:{ *:[i1] } (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_45297>><<P:Predicate_anonymous_45298>>, -1:{ *:[i1] })  =>  (V_CMP_NE_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*   66650 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   66653 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   66657 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   66662 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   66665 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*   66669 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   66671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64),
     /*   66674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66676 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   66679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   66682 */     GIR_RootConstrainSelectedInstOperands,
     /*   66683 */     // GIR_Coverage, 28286,
     /*   66683 */     GIR_EraseRootFromParent_Done,
     /*   66684 */   // Label 597: @66684
     /*   66684 */   GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(66754), // Rule ID 28287 //
     /*   66689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   66692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   66704 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   66708 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66710 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45298),
     /*   66714 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66720 */     // (xor:{ *:[i1] } (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_45297>><<P:Predicate_anonymous_45298>>, -1:{ *:[i1] })  =>  (V_CMP_NE_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*   66720 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   66723 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   66727 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   66732 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   66735 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*   66739 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   66741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64),
     /*   66744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66746 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   66749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   66752 */     GIR_RootConstrainSelectedInstOperands,
     /*   66753 */     // GIR_Coverage, 28287,
     /*   66753 */     GIR_EraseRootFromParent_Done,
     /*   66754 */   // Label 598: @66754
     /*   66754 */   GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(66824), // Rule ID 28288 //
     /*   66759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   66762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66766 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66770 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   66774 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   66778 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66780 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45298),
     /*   66784 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66788 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66790 */     // (xor:{ *:[i1] } (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_45297>><<P:Predicate_anonymous_45298>>, -1:{ *:[i1] })  =>  (V_CMP_NE_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*   66790 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   66793 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   66797 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   66802 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   66805 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*   66809 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   66811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64),
     /*   66814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66816 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   66819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   66822 */     GIR_RootConstrainSelectedInstOperands,
     /*   66823 */     // GIR_Coverage, 28288,
     /*   66823 */     GIR_EraseRootFromParent_Done,
     /*   66824 */   // Label 599: @66824
     /*   66824 */   GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(66894), // Rule ID 28289 //
     /*   66829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   66832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   66840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   66844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   66848 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   66850 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45298),
     /*   66854 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   66858 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   66860 */     // (xor:{ *:[i1] } (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_45297>><<P:Predicate_anonymous_45298>>, -1:{ *:[i1] })  =>  (V_CMP_NE_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*   66860 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   66863 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   66867 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   66872 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   66875 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*   66879 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   66881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64),
     /*   66884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   66886 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   66889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   66892 */     GIR_RootConstrainSelectedInstOperands,
     /*   66893 */     // GIR_Coverage, 28289,
     /*   66893 */     GIR_EraseRootFromParent_Done,
     /*   66894 */   // Label 600: @66894
     /*   66894 */   GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(66919), // Rule ID 28194 //
     /*   66899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*   66902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   66906 */     // (xor:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   66906 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
     /*   66911 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   66917 */     GIR_RootConstrainSelectedInstOperands,
     /*   66918 */     // GIR_Coverage, 28194,
     /*   66918 */     GIR_Done,
     /*   66919 */   // Label 601: @66919
     /*   66919 */   GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(66944), // Rule ID 28201 //
     /*   66924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*   66927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   66931 */     // (xor:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
     /*   66931 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
     /*   66936 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   66942 */     GIR_RootConstrainSelectedInstOperands,
     /*   66943 */     // GIR_Coverage, 28201,
     /*   66943 */     GIR_Done,
     /*   66944 */   // Label 602: @66944
     /*   66944 */   GIM_Reject,
     /*   66945 */ // Label 593: @66945
     /*   66945 */ GIM_Reject,
     /*   66946 */ // Label 587: @66946
     /*   66946 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(67060),
     /*   66951 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   66954 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   66957 */   GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(66980), // Rule ID 7164 //
     /*   66962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   66965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   66969 */     // (xor:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
     /*   66969 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   66974 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   66978 */     GIR_RootConstrainSelectedInstOperands,
     /*   66979 */     // GIR_Coverage, 7164,
     /*   66979 */     GIR_Done,
     /*   66980 */   // Label 604: @66980
     /*   66980 */   GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(67036), // Rule ID 2731 //
     /*   66985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   66988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   66992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   66999 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   67006 */     // (xor:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_XOR_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*   67006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B16_t16_e64),
     /*   67009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   67016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   67021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   67026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   67031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   67034 */     GIR_RootConstrainSelectedInstOperands,
     /*   67035 */     // GIR_Coverage, 2731,
     /*   67035 */     GIR_EraseRootFromParent_Done,
     /*   67036 */   // Label 605: @67036
     /*   67036 */   GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(67059), // Rule ID 2732 //
     /*   67041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   67044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67048 */     // (xor:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_XOR_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*   67048 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B16_fake16_e64),
     /*   67053 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   67057 */     GIR_RootConstrainSelectedInstOperands,
     /*   67058 */     // GIR_Coverage, 2732,
     /*   67058 */     GIR_Done,
     /*   67059 */   // Label 606: @67059
     /*   67059 */   GIM_Reject,
     /*   67060 */ // Label 603: @67060
     /*   67060 */ GIM_Reject,
     /*   67061 */ // Label 588: @67061
     /*   67061 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(68859),
     /*   67066 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   67069 */   GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(67127), // Rule ID 60 //
     /*   67074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   67081 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67085 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   67089 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67093 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67097 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   67099 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   67103 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   67107 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   67109 */     // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_and_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_20748>>  =>  (S_NAND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   67109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NAND_B32),
     /*   67112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   67114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   67118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   67122 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   67125 */     GIR_RootConstrainSelectedInstOperands,
     /*   67126 */     // GIR_Coverage, 60,
     /*   67126 */     GIR_EraseRootFromParent_Done,
     /*   67127 */   // Label 608: @67127
     /*   67127 */   GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(67185), // Rule ID 62 //
     /*   67132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   67139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*   67147 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67151 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67155 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   67157 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   67161 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   67165 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   67167 */     // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_20748>>  =>  (S_NOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   67167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B32),
     /*   67170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   67172 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   67176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   67180 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   67183 */     GIR_RootConstrainSelectedInstOperands,
     /*   67184 */     // GIR_Coverage, 62,
     /*   67184 */     GIR_EraseRootFromParent_Done,
     /*   67185 */   // Label 609: @67185
     /*   67185 */   GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(67243), // Rule ID 58 //
     /*   67190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   67197 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67201 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67205 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67209 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67213 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   67215 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   67219 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   67223 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   67225 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_20748>>  =>  (S_XNOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   67225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XNOR_B32),
     /*   67228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   67230 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   67234 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   67238 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   67241 */     GIR_RootConstrainSelectedInstOperands,
     /*   67242 */     // GIR_Coverage, 58,
     /*   67242 */     GIR_EraseRootFromParent_Done,
     /*   67243 */   // Label 610: @67243
     /*   67243 */   GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(67301), // Rule ID 7151 //
     /*   67248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
     /*   67251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67266 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67270 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67274 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   67276 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   67280 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27412),
     /*   67284 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   67286 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_27412>>  =>  (V_XNOR_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1)
     /*   67286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
     /*   67289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67291 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   67295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   67299 */     GIR_RootConstrainSelectedInstOperands,
     /*   67300 */     // GIR_Coverage, 7151,
     /*   67300 */     GIR_EraseRootFromParent_Done,
     /*   67301 */   // Label 611: @67301
     /*   67301 */   GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(67357), // Rule ID 7152 //
     /*   67306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
     /*   67309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67312 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   67314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67326 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67330 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67334 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   67338 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27414),
     /*   67342 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   67344 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }), i32:{ *:[i32] }:$src1)<<P:Predicate_xor_oneuse>><<P:Predicate_anonymous_27414>>  =>  (V_XNOR_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1)
     /*   67344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
     /*   67347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   67353 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   67355 */     GIR_RootConstrainSelectedInstOperands,
     /*   67356 */     // GIR_Coverage, 7152,
     /*   67356 */     GIR_EraseRootFromParent_Done,
     /*   67357 */   // Label 612: @67357
     /*   67357 */   GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(67413), // Rule ID 31334 //
     /*   67362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
     /*   67365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67368 */     GIM_CheckHasOneUse, /*MI*/0,
     /*   67370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   67378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67386 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67390 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   67394 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27414),
     /*   67398 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   67400 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }))<<P:Predicate_xor_oneuse>><<P:Predicate_anonymous_27414>>  =>  (V_XNOR_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1)
     /*   67400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
     /*   67403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67405 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   67409 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   67411 */     GIR_RootConstrainSelectedInstOperands,
     /*   67412 */     // GIR_Coverage, 31334,
     /*   67412 */     GIR_EraseRootFromParent_Done,
     /*   67413 */   // Label 613: @67413
     /*   67413 */   GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(67544), // Rule ID 34079 //
     /*   67418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67422 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67426 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   67430 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67434 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67438 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   67442 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67446 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   67450 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   67454 */     // MIs[0] z
     /*   67454 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   67459 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   67463 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   67465 */     // (xor:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   67465 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   67468 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67472 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67477 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   67481 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67486 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   67489 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67493 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67498 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   67502 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67507 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   67510 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67514 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67519 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   67523 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   67531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67533 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   67536 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   67539 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   67542 */     GIR_RootConstrainSelectedInstOperands,
     /*   67543 */     // GIR_Coverage, 34079,
     /*   67543 */     GIR_EraseRootFromParent_Done,
     /*   67544 */   // Label 614: @67544
     /*   67544 */   GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(67675), // Rule ID 34080 //
     /*   67549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67553 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67557 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   67561 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67565 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67569 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   67573 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67577 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   67581 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   67585 */     // MIs[0] z
     /*   67585 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   67590 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   67594 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   67596 */     // (xor:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   67596 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   67599 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67603 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67608 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   67612 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67617 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   67620 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67624 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67629 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   67633 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67638 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   67641 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67645 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67650 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   67654 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   67662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67664 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   67667 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   67670 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   67673 */     GIR_RootConstrainSelectedInstOperands,
     /*   67674 */     // GIR_Coverage, 34080,
     /*   67674 */     GIR_EraseRootFromParent_Done,
     /*   67675 */   // Label 615: @67675
     /*   67675 */   GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(67806), // Rule ID 34077 //
     /*   67680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67684 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67688 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   67692 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67696 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67700 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   67704 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67708 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   67712 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   67716 */     // MIs[0] z
     /*   67716 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   67721 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   67725 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   67727 */     // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z)), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   67727 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   67730 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67734 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67739 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
     /*   67743 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67748 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   67751 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67755 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67760 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   67764 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67769 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   67772 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67776 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67781 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   67785 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   67793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67795 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   67798 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   67801 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   67804 */     GIR_RootConstrainSelectedInstOperands,
     /*   67805 */     // GIR_Coverage, 34077,
     /*   67805 */     GIR_EraseRootFromParent_Done,
     /*   67806 */   // Label 616: @67806
     /*   67806 */   GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(67937), // Rule ID 34078 //
     /*   67811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67815 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   67819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   67823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67827 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67831 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   67835 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67839 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   67843 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   67847 */     // MIs[0] z
     /*   67847 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   67852 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   67856 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   67858 */     // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   67858 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   67861 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67865 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67870 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
     /*   67874 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67879 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   67882 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67886 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67891 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   67895 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67900 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   67903 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67907 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   67912 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   67916 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   67924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   67926 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   67929 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   67932 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   67935 */     GIR_RootConstrainSelectedInstOperands,
     /*   67936 */     // GIR_Coverage, 34078,
     /*   67936 */     GIR_EraseRootFromParent_Done,
     /*   67937 */   // Label 617: @67937
     /*   67937 */   GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(68067), // Rule ID 34076 //
     /*   67942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   67945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   67949 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   67953 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   67957 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   67961 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   67965 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   67969 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   67973 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   67977 */     // MIs[2] z
     /*   67977 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   67982 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   67986 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   67988 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   67988 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   67991 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   67995 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68000 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
     /*   68004 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68009 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   68012 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68016 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68021 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   68025 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68030 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   68033 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68037 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68042 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   68046 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   68054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68056 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   68059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   68062 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   68065 */     GIR_RootConstrainSelectedInstOperands,
     /*   68066 */     // GIR_Coverage, 34076,
     /*   68066 */     GIR_EraseRootFromParent_Done,
     /*   68067 */   // Label 618: @68067
     /*   68067 */   GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(68197), // Rule ID 34075 //
     /*   68072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68079 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   68083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   68087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68091 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68095 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   68099 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68103 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   68107 */     // MIs[2] z
     /*   68107 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   68112 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   68116 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   68118 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   68118 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   68121 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68125 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68130 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
     /*   68134 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68139 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   68142 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68146 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68151 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   68155 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68160 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   68163 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68167 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68172 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     /*   68176 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   68184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68186 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   68189 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   68192 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   68195 */     GIR_RootConstrainSelectedInstOperands,
     /*   68196 */     // GIR_Coverage, 34075,
     /*   68196 */     GIR_EraseRootFromParent_Done,
     /*   68197 */   // Label 619: @68197
     /*   68197 */   GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(68327), // Rule ID 34074 //
     /*   68202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68209 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   68213 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   68217 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68221 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68225 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   68229 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68233 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   68237 */     // MIs[2] z
     /*   68237 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   68242 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   68246 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   68248 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)))<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   68248 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   68251 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68255 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68260 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
     /*   68264 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68269 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   68272 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68276 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68281 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
     /*   68285 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   68293 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68297 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68302 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   68306 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   68314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68316 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   68319 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   68322 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   68325 */     GIR_RootConstrainSelectedInstOperands,
     /*   68326 */     // GIR_Coverage, 34074,
     /*   68326 */     GIR_EraseRootFromParent_Done,
     /*   68327 */   // Label 620: @68327
     /*   68327 */   GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(68457), // Rule ID 28028 //
     /*   68332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68339 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   68343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   68347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68351 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68355 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   68359 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68363 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   68367 */     // MIs[2] z
     /*   68367 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   68372 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   68376 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   68378 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_27146>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
     /*   68378 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*   68381 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68385 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68390 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
     /*   68394 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68399 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   68402 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68406 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68411 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
     /*   68415 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68420 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   68423 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   68427 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   68432 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     /*   68436 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   68444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68446 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   68449 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   68452 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*   68455 */     GIR_RootConstrainSelectedInstOperands,
     /*   68456 */     // GIR_Coverage, 28028,
     /*   68456 */     GIR_EraseRootFromParent_Done,
     /*   68457 */   // Label 621: @68457
     /*   68457 */   GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(68489), // Rule ID 0 //
     /*   68462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   68469 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   68473 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   68477 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })<<P:Predicate_anonymous_20748>>  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
     /*   68477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32),
     /*   68480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   68482 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   68484 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   68487 */     GIR_RootConstrainSelectedInstOperands,
     /*   68488 */     // GIR_Coverage, 0,
     /*   68488 */     GIR_EraseRootFromParent_Done,
     /*   68489 */   // Label 622: @68489
     /*   68489 */   GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(68518), // Rule ID 28206 //
     /*   68494 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68501 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   68505 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   68509 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })<<P:Predicate_anonymous_27146>>  =>  (V_NOT_B32_e32:{ *:[i32] } ?:{ *:[i32] }:$src0)
     /*   68509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_NOT_B32_e32),
     /*   68512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68514 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   68516 */     GIR_RootConstrainSelectedInstOperands,
     /*   68517 */     // GIR_Coverage, 28206,
     /*   68517 */     GIR_EraseRootFromParent_Done,
     /*   68518 */   // Label 623: @68518
     /*   68518 */   GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(68586), // Rule ID 7445 //
     /*   68523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*   68526 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68533 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   68537 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68541 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68545 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68549 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   68551 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:22:x
     /*   68555 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:22:y
     /*   68559 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:22:z
     /*   68563 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28971),
     /*   68567 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68569 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:22:x, i32:{ *:[i32] }:$src1:$pred:22:y)<<P:Predicate_anonymous_28499>>, i32:{ *:[i32] }:$src2:$pred:22:z)<<P:22:Predicate_anonymous_28971>>  =>  (V_XOR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   68569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR3_B32_e64),
     /*   68572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68578 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   68582 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*   68584 */     GIR_RootConstrainSelectedInstOperands,
     /*   68585 */     // GIR_Coverage, 7445,
     /*   68585 */     GIR_EraseRootFromParent_Done,
     /*   68586 */   // Label 624: @68586
     /*   68586 */   GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(68654), // Rule ID 31400 //
     /*   68591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*   68594 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68601 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:22:z
     /*   68605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   68609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68617 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68621 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   68623 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:22:x
     /*   68627 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:22:y
     /*   68631 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28971),
     /*   68635 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68637 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:22:z, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:22:x, i32:{ *:[i32] }:$src1:$pred:22:y)<<P:Predicate_anonymous_28499>>)<<P:22:Predicate_anonymous_28971>>  =>  (V_XOR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*   68637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR3_B32_e64),
     /*   68640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   68650 */     GIR_RootToRootCopy, /*OpIdx*/1, // src2
     /*   68652 */     GIR_RootConstrainSelectedInstOperands,
     /*   68653 */     // GIR_Coverage, 31400,
     /*   68653 */     GIR_EraseRootFromParent_Done,
     /*   68654 */   // Label 625: @68654
     /*   68654 */   GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(68683), // Rule ID 56 //
     /*   68659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   68666 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20782),
     /*   68670 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20782>>  =>  (S_XOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   68670 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
     /*   68675 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   68681 */     GIR_RootConstrainSelectedInstOperands,
     /*   68682 */     // GIR_Coverage, 56,
     /*   68682 */     GIR_Done,
     /*   68683 */   // Label 626: @68683
     /*   68683 */   GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(68733), // Rule ID 31195 //
     /*   68688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
     /*   68691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68698 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   68702 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68706 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68710 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68714 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   68718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68720 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }), i32:{ *:[i32] }:$src1)  =>  (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   68720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
     /*   68723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68725 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68729 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   68731 */     GIR_RootConstrainSelectedInstOperands,
     /*   68732 */     // GIR_Coverage, 31195,
     /*   68732 */     GIR_EraseRootFromParent_Done,
     /*   68733 */   // Label 627: @68733
     /*   68733 */   GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(68785), // Rule ID 2735 //
     /*   68738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
     /*   68741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   68752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68756 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68760 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68764 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   68768 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68770 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), -1:{ *:[i32] })  =>  (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   68770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
     /*   68773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68775 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68779 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   68783 */     GIR_RootConstrainSelectedInstOperands,
     /*   68784 */     // GIR_Coverage, 2735,
     /*   68784 */     GIR_EraseRootFromParent_Done,
     /*   68785 */   // Label 628: @68785
     /*   68785 */   GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(68835), // Rule ID 31196 //
     /*   68790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
     /*   68793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   68804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   68808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   68812 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*   68816 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*   68820 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68822 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }))  =>  (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   68822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
     /*   68825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   68827 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68831 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   68833 */     GIR_RootConstrainSelectedInstOperands,
     /*   68834 */     // GIR_Coverage, 31196,
     /*   68834 */     GIR_EraseRootFromParent_Done,
     /*   68835 */   // Label 629: @68835
     /*   68835 */   GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(68858), // Rule ID 2624 //
     /*   68840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   68843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   68847 */     // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*   68847 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   68852 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   68856 */     GIR_RootConstrainSelectedInstOperands,
     /*   68857 */     // GIR_Coverage, 2624,
     /*   68857 */     GIR_Done,
     /*   68858 */   // Label 630: @68858
     /*   68858 */   GIM_Reject,
     /*   68859 */ // Label 607: @68859
     /*   68859 */ GIM_Reject,
     /*   68860 */ // Label 589: @68860
     /*   68860 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(71492),
     /*   68865 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   68868 */   GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(68926), // Rule ID 61 //
     /*   68873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   68876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   68880 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   68884 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   68888 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   68892 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   68896 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   68898 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   68902 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   68906 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68908 */     // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_and_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_20748>>  =>  (S_NAND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   68908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NAND_B64),
     /*   68911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   68913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   68921 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   68924 */     GIR_RootConstrainSelectedInstOperands,
     /*   68925 */     // GIR_Coverage, 61,
     /*   68925 */     GIR_EraseRootFromParent_Done,
     /*   68926 */   // Label 632: @68926
     /*   68926 */   GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(68984), // Rule ID 63 //
     /*   68931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   68934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   68938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   68942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*   68946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   68950 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   68954 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   68956 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   68960 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   68964 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   68966 */     // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_20748>>  =>  (S_NOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   68966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B64),
     /*   68969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   68971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   68975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   68979 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   68982 */     GIR_RootConstrainSelectedInstOperands,
     /*   68983 */     // GIR_Coverage, 63,
     /*   68983 */     GIR_EraseRootFromParent_Done,
     /*   68984 */   // Label 633: @68984
     /*   68984 */   GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(69042), // Rule ID 59 //
     /*   68989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   68992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   68996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   69000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   69004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   69008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   69012 */     GIM_CheckHasOneUse, /*MI*/1,
     /*   69014 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   69018 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   69022 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   69024 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_20748>>  =>  (S_XNOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   69024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XNOR_B64),
     /*   69027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   69029 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*   69033 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*   69037 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   69040 */     GIR_RootConstrainSelectedInstOperands,
     /*   69041 */     // GIR_Coverage, 59,
     /*   69041 */     GIR_EraseRootFromParent_Done,
     /*   69042 */   // Label 634: @69042
     /*   69042 */   GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(69341), // Rule ID 34086 //
     /*   69047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69051 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   69055 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   69059 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   69063 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   69067 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   69071 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   69075 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   69079 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   69083 */     // MIs[0] z
     /*   69083 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   69088 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   69092 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   69094 */     // (xor:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   69094 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   69097 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69101 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69106 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   69112 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69117 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69122 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   69125 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69129 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69134 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   69140 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69145 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69150 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   69153 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69157 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69162 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   69168 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69173 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69178 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   69181 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   69185 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69190 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   69193 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   69196 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   69199 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   69201 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   69204 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69208 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69213 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   69219 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69224 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69229 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   69232 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69236 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69241 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   69247 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69252 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69257 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   69260 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69264 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69269 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   69275 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69280 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69285 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   69288 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   69292 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69297 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   69300 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   69303 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   69306 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   69308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   69311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   69313 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   69316 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   69319 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   69322 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   69325 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69330 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69335 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69340 */     // GIR_Coverage, 34086,
     /*   69340 */     GIR_EraseRootFromParent_Done,
     /*   69341 */   // Label 635: @69341
     /*   69341 */   GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(69640), // Rule ID 34087 //
     /*   69346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69350 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   69354 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   69358 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   69362 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   69366 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   69370 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   69374 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   69378 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   69382 */     // MIs[0] z
     /*   69382 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   69387 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   69391 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   69393 */     // (xor:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y), i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   69393 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   69396 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69400 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69405 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   69411 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69416 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69421 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   69424 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69428 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69433 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   69439 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69444 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69449 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   69452 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69456 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69461 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   69467 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69472 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69477 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   69480 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   69484 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69489 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   69492 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   69495 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   69498 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   69500 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   69503 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69507 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69512 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   69518 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69523 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69528 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   69531 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69535 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69540 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   69546 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69551 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69556 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   69559 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69563 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69568 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   69574 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69579 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69584 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   69587 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   69591 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69596 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   69599 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   69602 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   69605 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   69607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   69610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   69612 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   69615 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   69618 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   69621 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   69624 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69629 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69634 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69639 */     // GIR_Coverage, 34087,
     /*   69639 */     GIR_EraseRootFromParent_Done,
     /*   69640 */   // Label 636: @69640
     /*   69640 */   GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(69939), // Rule ID 34084 //
     /*   69645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69649 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   69653 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   69657 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   69661 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   69665 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   69669 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   69673 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   69677 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   69681 */     // MIs[0] z
     /*   69681 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   69686 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   69690 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   69692 */     // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z)), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   69692 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   69695 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69699 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69704 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   69710 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69715 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69720 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   69723 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69727 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69732 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   69738 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69743 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69748 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   69751 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69755 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69760 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   69766 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69771 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69776 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   69779 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   69783 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69788 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   69791 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   69794 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   69797 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   69799 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   69802 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69806 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69811 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   69817 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69822 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69827 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   69830 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69834 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69839 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   69845 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69850 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69855 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   69858 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69862 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69867 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   69873 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69878 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69883 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   69886 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   69890 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   69895 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   69898 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   69901 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   69904 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   69906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   69909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   69911 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   69914 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   69917 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   69920 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   69923 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69928 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69933 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   69938 */     // GIR_Coverage, 34084,
     /*   69938 */     GIR_EraseRootFromParent_Done,
     /*   69939 */   // Label 637: @69939
     /*   69939 */   GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(70238), // Rule ID 34085 //
     /*   69944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   69948 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   69952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   69956 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   69960 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   69964 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   69968 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   69972 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   69976 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   69980 */     // MIs[0] z
     /*   69980 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   69985 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   69989 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   69991 */     // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y)), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   69991 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   69994 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   69998 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70003 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   70009 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70014 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70019 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   70022 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70026 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70031 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   70037 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70042 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70047 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   70050 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70054 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70059 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   70065 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70070 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70075 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   70078 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70082 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70087 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   70090 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   70093 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   70096 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   70098 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   70101 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70105 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70110 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   70116 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70121 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70126 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   70129 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70133 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70138 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   70144 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70149 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70154 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   70157 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70161 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70166 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   70172 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70177 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70182 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   70185 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70189 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70194 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   70197 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   70200 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   70203 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   70205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   70208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   70210 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   70213 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   70216 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   70219 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   70222 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70227 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70232 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70237 */     // GIR_Coverage, 34085,
     /*   70237 */     GIR_EraseRootFromParent_Done,
     /*   70238 */   // Label 638: @70238
     /*   70238 */   GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(70536), // Rule ID 34083 //
     /*   70243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   70246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70250 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   70254 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   70258 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   70262 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   70266 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   70270 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   70274 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   70278 */     // MIs[2] z
     /*   70278 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   70283 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   70287 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   70289 */     // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y), i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   70289 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   70292 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70296 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70301 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   70307 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70312 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70317 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   70320 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70324 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70329 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   70335 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70340 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70345 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   70348 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70352 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70357 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   70363 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70368 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70373 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   70376 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70380 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70385 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   70388 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   70391 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   70394 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   70396 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   70399 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70403 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70408 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   70414 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70419 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70424 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   70427 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70431 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70436 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   70442 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70447 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70452 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   70455 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70459 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70464 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   70470 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70475 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70480 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   70483 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70487 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70492 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   70495 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   70498 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   70501 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   70503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   70506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   70508 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   70511 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   70514 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   70517 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   70520 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70525 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70530 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70535 */     // GIR_Coverage, 34083,
     /*   70535 */     GIR_EraseRootFromParent_Done,
     /*   70536 */   // Label 639: @70536
     /*   70536 */   GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(70834), // Rule ID 34082 //
     /*   70541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   70544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70548 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   70552 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   70556 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   70560 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   70564 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   70568 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   70572 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   70576 */     // MIs[2] z
     /*   70576 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   70581 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   70585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   70587 */     // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   70587 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   70590 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70594 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70599 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   70605 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70610 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70615 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   70618 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70622 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70627 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   70633 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70638 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70643 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   70646 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70650 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70655 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   70661 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70666 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70671 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   70674 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70678 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70683 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   70686 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   70689 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   70692 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   70694 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   70697 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70701 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70706 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   70712 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70717 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70722 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   70725 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70729 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70734 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   70740 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70745 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70750 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   70753 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70757 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70762 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   70768 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70773 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70778 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   70781 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70785 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70790 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   70793 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   70796 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   70799 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   70801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   70804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   70806 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   70809 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   70812 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   70815 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   70818 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70823 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70828 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70833 */     // GIR_Coverage, 34082,
     /*   70833 */     GIR_EraseRootFromParent_Done,
     /*   70834 */   // Label 640: @70834
     /*   70834 */   GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(71132), // Rule ID 34081 //
     /*   70839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   70842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70846 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   70850 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   70854 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   70858 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   70862 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   70866 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   70870 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   70874 */     // MIs[2] z
     /*   70874 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   70879 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   70883 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   70885 */     // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y)))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   70885 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   70888 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70892 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70897 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   70903 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70908 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70913 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   70916 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70920 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70925 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   70931 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70936 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70941 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   70944 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70948 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70953 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   70959 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   70964 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   70969 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   70972 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   70976 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   70981 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   70984 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   70987 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   70990 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   70992 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   70995 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   70999 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71004 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   71010 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71015 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71020 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   71023 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71027 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71032 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   71038 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71043 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71048 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   71051 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71055 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71060 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   71066 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71071 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71076 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   71079 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   71083 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71088 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   71091 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   71094 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   71097 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   71099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   71102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   71104 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   71107 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   71110 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   71113 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   71116 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71121 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71126 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71131 */     // GIR_Coverage, 34081,
     /*   71131 */     GIR_EraseRootFromParent_Done,
     /*   71132 */   // Label 641: @71132
     /*   71132 */   GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(71430), // Rule ID 28029 //
     /*   71137 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   71140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71144 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   71148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   71152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   71156 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   71160 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   71164 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   71168 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   71172 */     // MIs[2] z
     /*   71172 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   71177 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   71181 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   71183 */     // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   71183 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   71186 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71190 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71195 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   71201 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71206 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71211 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   71214 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71218 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71223 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   71229 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71234 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71239 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   71242 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71246 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71251 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   71257 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71262 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71267 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   71270 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   71274 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71279 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   71282 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   71285 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   71288 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   71290 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   71293 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71297 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71302 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   71308 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71313 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71318 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   71321 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71325 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71330 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   71336 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71341 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71346 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   71349 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71353 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71358 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   71364 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71369 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71374 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   71377 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   71381 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71386 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   71389 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   71392 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   71395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   71397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   71400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   71402 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   71405 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   71408 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   71411 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   71414 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71419 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71424 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71429 */     // GIR_Coverage, 28029,
     /*   71429 */     GIR_EraseRootFromParent_Done,
     /*   71430 */   // Label 642: @71430
     /*   71430 */   GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(71462), // Rule ID 1 //
     /*   71435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   71438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   71442 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*   71446 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20748),
     /*   71450 */     // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })<<P:Predicate_anonymous_20748>>  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
     /*   71450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64),
     /*   71453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   71455 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   71457 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   71460 */     GIR_RootConstrainSelectedInstOperands,
     /*   71461 */     // GIR_Coverage, 1,
     /*   71461 */     GIR_EraseRootFromParent_Done,
     /*   71462 */   // Label 643: @71462
     /*   71462 */   GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(71491), // Rule ID 57 //
     /*   71467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   71470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   71474 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20782),
     /*   71478 */     // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_20782>>  =>  (S_XOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     /*   71478 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
     /*   71483 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   71489 */     GIR_RootConstrainSelectedInstOperands,
     /*   71490 */     // GIR_Coverage, 57,
     /*   71490 */     GIR_Done,
     /*   71491 */   // Label 644: @71491
     /*   71491 */   GIM_Reject,
     /*   71492 */ // Label 631: @71492
     /*   71492 */ GIM_Reject,
     /*   71493 */ // Label 590: @71493
     /*   71493 */ GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(71519), // Rule ID 7167 //
     /*   71498 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   71501 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*   71504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71508 */   // (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1)  =>  (V_XOR_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
     /*   71508 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
     /*   71513 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*   71517 */   GIR_RootConstrainSelectedInstOperands,
     /*   71518 */   // GIR_Coverage, 7167,
     /*   71518 */   GIR_Done,
     /*   71519 */ // Label 645: @71519
     /*   71519 */ GIM_Reject,
     /*   71520 */ // Label 591: @71520
     /*   71520 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(73946),
     /*   71525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   71528 */   GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(71827), // Rule ID 34093 //
     /*   71533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71537 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   71541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   71545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   71549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   71553 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   71557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   71561 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   71565 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   71569 */     // MIs[0] z
     /*   71569 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   71574 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   71578 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   71580 */     // (xor:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$y, v2i32:{ *:[v2i32] }:$z), v2i32:{ *:[v2i32] }:$x), v2i32:{ *:[v2i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   71580 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   71583 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71587 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71592 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   71598 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71603 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71608 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   71611 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71615 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71620 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   71626 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71631 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71636 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   71639 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71643 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71648 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   71654 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71659 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71664 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   71667 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   71671 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71676 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   71679 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   71682 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   71685 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   71687 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   71690 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71694 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71699 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   71705 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71710 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71715 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   71718 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71722 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71727 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   71733 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71738 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71743 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   71746 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71750 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71755 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   71761 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71766 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71771 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   71774 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   71778 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71783 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   71786 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   71789 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   71792 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   71794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   71797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   71799 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   71802 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   71805 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   71808 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   71811 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71816 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71821 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71826 */     // GIR_Coverage, 34093,
     /*   71826 */     GIR_EraseRootFromParent_Done,
     /*   71827 */   // Label 647: @71827
     /*   71827 */   GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(72126), // Rule ID 34094 //
     /*   71832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71836 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   71840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   71844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   71848 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   71852 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   71856 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   71860 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   71864 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   71868 */     // MIs[0] z
     /*   71868 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   71873 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   71877 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   71879 */     // (xor:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, v2i32:{ *:[v2i32] }:$y), v2i32:{ *:[v2i32] }:$x), v2i32:{ *:[v2i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   71879 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   71882 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71886 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71891 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   71897 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71902 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71907 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   71910 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71914 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71919 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   71925 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71930 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71935 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   71938 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71942 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71947 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   71953 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   71958 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   71963 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   71966 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   71970 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71975 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   71978 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   71981 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   71984 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   71986 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   71989 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   71993 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   71998 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   72004 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72009 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72014 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   72017 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72021 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72026 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   72032 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72037 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72042 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   72045 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72049 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72054 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   72060 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72065 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72070 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   72073 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72077 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72082 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   72085 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   72088 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   72091 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   72093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   72096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   72098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   72101 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   72104 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   72107 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   72110 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72115 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72120 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72125 */     // GIR_Coverage, 34094,
     /*   72125 */     GIR_EraseRootFromParent_Done,
     /*   72126 */   // Label 648: @72126
     /*   72126 */   GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(72425), // Rule ID 34091 //
     /*   72131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72135 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   72139 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   72143 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   72147 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72151 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   72155 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   72159 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   72163 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72167 */     // MIs[0] z
     /*   72167 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   72172 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   72176 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   72178 */     // (xor:{ *:[v2i32] } (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$y, v2i32:{ *:[v2i32] }:$z)), v2i32:{ *:[v2i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   72178 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   72181 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72185 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72190 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   72196 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72201 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72206 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   72209 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72213 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72218 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   72224 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72229 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72234 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   72237 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72241 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72246 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   72252 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72257 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72262 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   72265 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72269 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72274 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   72277 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   72280 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   72283 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   72285 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   72288 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72292 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72297 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   72303 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72308 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72313 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   72316 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72320 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72325 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   72331 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72336 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72341 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   72344 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72348 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72353 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   72359 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72364 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72369 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   72372 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72376 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72381 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   72384 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   72387 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   72390 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   72392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   72395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   72397 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   72400 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   72403 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   72406 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   72409 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72414 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72419 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72424 */     // GIR_Coverage, 34091,
     /*   72424 */     GIR_EraseRootFromParent_Done,
     /*   72425 */   // Label 649: @72425
     /*   72425 */   GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(72724), // Rule ID 34092 //
     /*   72430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72434 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   72438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   72442 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   72446 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72450 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   72454 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   72458 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   72462 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72466 */     // MIs[0] z
     /*   72466 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*   72471 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   72475 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   72477 */     // (xor:{ *:[v2i32] } (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, v2i32:{ *:[v2i32] }:$y)), v2i32:{ *:[v2i32] }:$z)<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   72477 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   72480 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72484 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72489 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   72495 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72500 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72505 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   72508 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72512 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72517 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   72523 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72528 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72533 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   72536 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72540 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72545 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   72551 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72556 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72561 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   72564 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72568 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72573 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   72576 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   72579 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   72582 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   72584 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   72587 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72591 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72596 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   72602 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72607 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72612 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   72615 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72619 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72624 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   72630 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72635 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72640 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   72643 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72647 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72652 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   72658 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72663 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72668 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   72671 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72675 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72680 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   72683 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   72686 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   72689 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   72691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   72694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   72696 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   72699 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   72702 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   72705 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   72708 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72713 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72718 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72723 */     // GIR_Coverage, 34092,
     /*   72723 */     GIR_EraseRootFromParent_Done,
     /*   72724 */   // Label 650: @72724
     /*   72724 */   GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(73022), // Rule ID 34090 //
     /*   72729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72736 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   72740 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   72744 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   72748 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72752 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   72756 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   72760 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   72764 */     // MIs[2] z
     /*   72764 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   72769 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   72773 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   72775 */     // (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, v2i32:{ *:[v2i32] }:$y), v2i32:{ *:[v2i32] }:$x))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   72775 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   72778 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72782 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72787 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   72793 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72798 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72803 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   72806 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72810 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72815 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   72821 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72826 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72831 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   72834 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72838 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72843 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   72849 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72854 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72859 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   72862 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72866 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72871 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   72874 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   72877 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   72880 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   72882 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   72885 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72889 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72894 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   72900 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72905 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72910 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   72913 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72917 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72922 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   72928 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72933 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72938 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   72941 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   72945 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72950 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   72956 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   72961 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   72966 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   72969 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   72973 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   72978 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   72981 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   72984 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   72987 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   72989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   72992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   72994 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   72997 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   73000 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   73003 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   73006 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73011 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73016 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73021 */     // GIR_Coverage, 34090,
     /*   73021 */     GIR_EraseRootFromParent_Done,
     /*   73022 */   // Label 651: @73022
     /*   73022 */   GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(73320), // Rule ID 34089 //
     /*   73027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73034 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   73038 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   73042 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   73046 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73050 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   73054 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   73058 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   73062 */     // MIs[2] z
     /*   73062 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   73067 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   73071 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   73073 */     // (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$y, v2i32:{ *:[v2i32] }:$z), v2i32:{ *:[v2i32] }:$x))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   73073 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   73076 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73080 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73085 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   73091 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73096 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73101 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   73104 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73108 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73113 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   73119 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73124 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73129 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   73132 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73136 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73141 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   73147 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73152 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73157 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   73160 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   73164 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73169 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   73172 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   73175 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   73178 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   73180 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   73183 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73187 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73192 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   73198 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73203 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73208 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   73211 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73215 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73220 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   73226 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73231 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73236 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   73239 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73243 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73248 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   73254 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73259 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73264 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   73267 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   73271 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73276 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   73279 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   73282 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   73285 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   73287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   73290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   73292 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   73295 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   73298 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   73301 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   73304 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73309 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73314 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73319 */     // GIR_Coverage, 34089,
     /*   73319 */     GIR_EraseRootFromParent_Done,
     /*   73320 */   // Label 652: @73320
     /*   73320 */   GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(73618), // Rule ID 34088 //
     /*   73325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73332 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   73336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   73340 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   73344 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73348 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   73352 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   73356 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73360 */     // MIs[2] z
     /*   73360 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   73365 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   73369 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   73371 */     // (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, v2i32:{ *:[v2i32] }:$y)))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   73371 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   73374 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73378 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73383 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   73389 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73394 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73399 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   73402 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73406 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73411 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   73417 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73422 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73427 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   73430 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73434 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73439 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   73445 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73450 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73455 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   73458 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   73462 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73467 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   73470 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   73473 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   73476 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   73478 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   73481 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73485 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73490 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   73496 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73501 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73506 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   73509 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73513 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73518 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   73524 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73529 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73534 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   73537 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73541 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73546 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   73552 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73557 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73562 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   73565 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   73569 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73574 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   73577 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   73580 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   73583 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   73585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   73588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   73590 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   73593 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   73596 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   73599 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   73602 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73607 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73612 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73617 */     // GIR_Coverage, 34088,
     /*   73617 */     GIR_EraseRootFromParent_Done,
     /*   73618 */   // Label 653: @73618
     /*   73618 */   GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(73916), // Rule ID 28030 //
     /*   73623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73630 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   73634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*   73638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   73642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73646 */     GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   73650 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*   73654 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   73658 */     // MIs[2] z
     /*   73658 */     GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*   73663 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27146),
     /*   73667 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   73669 */     // (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$z, (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$y, v2i32:{ *:[v2i32] }:$z)))<<P:Predicate_anonymous_27146>>  =>  (REG_SEQUENCE:{ *:[v2i32] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
     /*   73669 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
     /*   73672 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73676 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73681 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
     /*   73687 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73692 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73697 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*   73700 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73704 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73709 */     GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
     /*   73715 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73720 */     GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73725 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*   73728 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73732 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73737 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
     /*   73743 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73748 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73753 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*   73756 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   73760 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73765 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*   73768 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*   73771 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
     /*   73774 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*   73776 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*   73779 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73783 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73788 */     GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
     /*   73794 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73799 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73804 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /*   73807 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73811 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73816 */     GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
     /*   73822 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73827 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73832 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   73835 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   73839 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73844 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
     /*   73850 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73855 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73860 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   73863 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   73867 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   73872 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   73875 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*   73878 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*   73881 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   73883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   73886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   73888 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   73891 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   73894 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
     /*   73897 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   73900 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   73905 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73910 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73915 */     // GIR_Coverage, 28030,
     /*   73915 */     GIR_EraseRootFromParent_Done,
     /*   73916 */   // Label 654: @73916
     /*   73916 */   GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(73945), // Rule ID 4801 //
     /*   73921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   73924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   73928 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20782),
     /*   73932 */     // (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$x, v2i32:{ *:[v2i32] }:$y)<<P:Predicate_anonymous_20782>>  =>  (S_XOR_B64:{ *:[v2i32] }:{ *:[i1] } SReg_64:{ *:[v2i32] }:$x, SReg_64:{ *:[v2i32] }:$y)
     /*   73932 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
     /*   73937 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   73943 */     GIR_RootConstrainSelectedInstOperands,
     /*   73944 */     // GIR_Coverage, 4801,
     /*   73944 */     GIR_Done,
     /*   73945 */   // Label 655: @73945
     /*   73945 */   GIM_Reject,
     /*   73946 */ // Label 646: @73946
     /*   73946 */ GIM_Reject,
     /*   73947 */ // Label 592: @73947
     /*   73947 */ GIM_Reject,
     /*   73948 */ // Label 6: @73948
     /*   73948 */ GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(73977), // Rule ID 27938 //
     /*   73953 */   // MIs[0] DstI[vdst]
     /*   73953 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
     /*   73957 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   73961 */   // MIs[0] Operand 1
     /*   73961 */   // No operand predicates
     /*   73961 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45046),
     /*   73965 */   // (frameindex:{ *:[i32] })<<P:Predicate_anonymous_45046>>:$fi  =>  (V_MOV_B32_e32:{ *:[i32] } (frameindex_to_targetframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi))
     /*   73965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*   73968 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   73970 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi
     /*   73975 */   GIR_RootConstrainSelectedInstOperands,
     /*   73976 */   // GIR_Coverage, 27938,
     /*   73976 */   GIR_EraseRootFromParent_Done,
     /*   73977 */ // Label 656: @73977
     /*   73977 */ GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(74002), // Rule ID 27939 //
     /*   73982 */   // MIs[0] DstI[sdst]
     /*   73982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
     /*   73986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   73990 */   // MIs[0] Operand 1
     /*   73990 */   // No operand predicates
     /*   73990 */   // (frameindex:{ *:[i32] }):$fi  =>  (S_MOV_B32:{ *:[i32] } (frameindex_to_targetframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi))
     /*   73990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   73993 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   73995 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi
     /*   74000 */   GIR_RootConstrainSelectedInstOperands,
     /*   74001 */   // GIR_Coverage, 27939,
     /*   74001 */   GIR_EraseRootFromParent_Done,
     /*   74002 */ // Label 657: @74002
     /*   74002 */ GIM_Reject,
     /*   74003 */ // Label 7: @74003
     /*   74003 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(77606),
     /*   74008 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*   74011 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*   74014 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   74017 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*   74020 */   GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(74498),
     /*   74025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   74029 */     GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(74152), // Rule ID 7583 //
     /*   74034 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts_NotUseRealTrue16Insts),
     /*   74037 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   74041 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_CLAMP),
     /*   74045 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   74049 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   74053 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   74057 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74061 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   74065 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMA),
     /*   74069 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   74073 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   74077 */       GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
     /*   74081 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   74083 */       GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74090 */       GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74097 */       GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74104 */       // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (AMDGPUclamp:{ *:[f16] } (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 1:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
     /*   74104 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
     /*   74107 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74109 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   74114 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74119 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   74124 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74129 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*   74134 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*   74139 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   74142 */       GIR_RootToRootCopy, /*OpIdx*/1, // elt0
     /*   74144 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74147 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74150 */       GIR_RootConstrainSelectedInstOperands,
     /*   74151 */       // GIR_Coverage, 7583,
     /*   74151 */       GIR_EraseRootFromParent_Done,
     /*   74152 */     // Label 660: @74152
     /*   74152 */     GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(74275), // Rule ID 7568 //
     /*   74157 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
     /*   74160 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   74164 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_CLAMP),
     /*   74168 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   74172 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   74176 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   74180 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74184 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   74188 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAD),
     /*   74192 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   74196 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   74200 */       GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
     /*   74204 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   74206 */       GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74213 */       GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74220 */       GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74227 */       // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (AMDGPUclamp:{ *:[f16] } (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 1:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
     /*   74227 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
     /*   74230 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74232 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   74237 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74242 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   74247 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74252 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*   74257 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*   74262 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   74265 */       GIR_RootToRootCopy, /*OpIdx*/1, // elt0
     /*   74267 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74270 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74273 */       GIR_RootConstrainSelectedInstOperands,
     /*   74274 */       // GIR_Coverage, 7568,
     /*   74274 */       GIR_EraseRootFromParent_Done,
     /*   74275 */     // Label 661: @74275
     /*   74275 */     GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(74386), // Rule ID 7582 //
     /*   74280 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts_NotUseRealTrue16Insts),
     /*   74283 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   74287 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   74291 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   74295 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   74299 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMA),
     /*   74303 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74307 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   74311 */       GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   74315 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   74317 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74324 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74331 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74338 */       // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
     /*   74338 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
     /*   74341 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74343 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   74348 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74353 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   74358 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74363 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*   74368 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*   74373 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74376 */       GIR_RootToRootCopy, /*OpIdx*/1, // elt0
     /*   74378 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74381 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74384 */       GIR_RootConstrainSelectedInstOperands,
     /*   74385 */       // GIR_Coverage, 7582,
     /*   74385 */       GIR_EraseRootFromParent_Done,
     /*   74386 */     // Label 662: @74386
     /*   74386 */     GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(74497), // Rule ID 7567 //
     /*   74391 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
     /*   74394 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   74398 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   74402 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   74406 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   74410 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAD),
     /*   74414 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74418 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   74422 */       GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /*   74426 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   74428 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74435 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74442 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   74449 */       // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
     /*   74449 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
     /*   74452 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74454 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   74459 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74464 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   74469 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74474 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*   74479 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*   74484 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74487 */       GIR_RootToRootCopy, /*OpIdx*/1, // elt0
     /*   74489 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74492 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74495 */       GIR_RootConstrainSelectedInstOperands,
     /*   74496 */       // GIR_Coverage, 7567,
     /*   74496 */       GIR_EraseRootFromParent_Done,
     /*   74497 */     // Label 663: @74497
     /*   74497 */     GIM_Reject,
     /*   74498 */   // Label 659: @74498
     /*   74498 */   GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(74656), // Rule ID 28418 //
     /*   74503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   74506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   74510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   74514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   74518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   74522 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   74526 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   74530 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74534 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   74538 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   74542 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   74546 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   74550 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   74555 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   74559 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*   74563 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   74567 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s16,
     /*   74571 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*   74575 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   74579 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
     /*   74583 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
     /*   74587 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   74591 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
     /*   74595 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
     /*   74599 */     GIM_CheckRegBankForClass, /*MI*/6, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   74604 */     GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
     /*   74608 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   74612 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*   74614 */     // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_45361>>  =>  (V_PERM_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] }))
     /*   74614 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   74617 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   74621 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   74626 */     GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498),
     /*   74636 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   74638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*   74641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // b
     /*   74647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a
     /*   74651 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   74654 */     GIR_RootConstrainSelectedInstOperands,
     /*   74655 */     // GIR_Coverage, 28418,
     /*   74655 */     GIR_EraseRootFromParent_Done,
     /*   74656 */   // Label 664: @74656
     /*   74656 */   GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(74767), // Rule ID 28396 //
     /*   74661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
     /*   74664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   74668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   74672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   74676 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   74680 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   74684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   74688 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74692 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   74696 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   74698 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   74703 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   74707 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   74711 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   74715 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   74719 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   74723 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   74727 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   74731 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   74735 */     GIM_CheckHasOneUse, /*MI*/4,
     /*   74737 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   74742 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   74746 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   74750 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   74752 */     // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>), (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src1, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>))<<P:Predicate_anonymous_45359>>  =>  (S_PACK_HH_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)
     /*   74752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_HH_B32_B16),
     /*   74755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   74757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   74761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
     /*   74765 */     GIR_RootConstrainSelectedInstOperands,
     /*   74766 */     // GIR_Coverage, 28396,
     /*   74766 */     GIR_EraseRootFromParent_Done,
     /*   74767 */   // Label 665: @74767
     /*   74767 */   GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(74891),
     /*   74772 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45417),
     /*   74776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   74780 */     GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(74835), // Rule ID 28419 //
     /*   74785 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX9Plus),
     /*   74788 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*   74795 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*   74802 */       // (build_vector:{ *:[v2f16] } (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_anonymous_45417>>  =>  (V_PACK_B32_F16_e64:{ *:[v2f16] } ?:{ *:[i32] }:$src0_mods, VGPR_32:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, VGPR_32:{ *:[f16] }:$src1)
     /*   74802 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PACK_B32_F16_e64),
     /*   74805 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74807 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
     /*   74812 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74817 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
     /*   74822 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74827 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74830 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74833 */       GIR_RootConstrainSelectedInstOperands,
     /*   74834 */       // GIR_Coverage, 28419,
     /*   74834 */       GIR_EraseRootFromParent_Done,
     /*   74835 */     // Label 667: @74835
     /*   74835 */     GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(74890), // Rule ID 28420 //
     /*   74840 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX9Plus),
     /*   74843 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*   74850 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*   74857 */       // (build_vector:{ *:[v2f16] } (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_anonymous_45417>>  =>  (V_PACK_B32_F16_fake16_e64:{ *:[v2f16] } ?:{ *:[i32] }:$src0_mods, VGPR_32:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, VGPR_32:{ *:[f16] }:$src1)
     /*   74857 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PACK_B32_F16_fake16_e64),
     /*   74860 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74862 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
     /*   74867 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74872 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
     /*   74877 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74882 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74885 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74888 */       GIR_RootConstrainSelectedInstOperands,
     /*   74889 */       // GIR_Coverage, 28420,
     /*   74889 */       GIR_EraseRootFromParent_Done,
     /*   74890 */     // Label 668: @74890
     /*   74890 */     GIM_Reject,
     /*   74891 */   // Label 666: @74891
     /*   74891 */   GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(75330),
     /*   74896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   74900 */     GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(74978), // Rule ID 7510 //
     /*   74905 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   74908 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   74912 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /*   74916 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   74920 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   74924 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /*   74928 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   74932 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   74934 */       GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*   74941 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*   74948 */       // (build_vector:{ *:[v2i16] } (fp_to_sint:{ *:[i16] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers)), (fp_to_sint:{ *:[i16] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))  =>  (V_CVT_PK_I16_F32_e64:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1)
     /*   74948 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_I16_F32_e64),
     /*   74951 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   74953 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   74958 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   74963 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   74968 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   74973 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   74976 */       GIR_RootConstrainSelectedInstOperands,
     /*   74977 */       // GIR_Coverage, 7510,
     /*   74977 */       GIR_EraseRootFromParent_Done,
     /*   74978 */     // Label 670: @74978
     /*   74978 */     GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(75056), // Rule ID 7511 //
     /*   74983 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   74986 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   74990 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /*   74994 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   74998 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   75002 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /*   75006 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75010 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   75012 */       GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*   75019 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*   75026 */       // (build_vector:{ *:[v2i16] } (fp_to_uint:{ *:[i16] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers)), (fp_to_uint:{ *:[i16] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))  =>  (V_CVT_PK_U16_F32_e64:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1)
     /*   75026 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U16_F32_e64),
     /*   75029 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75031 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   75036 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   75041 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   75046 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   75051 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75054 */       GIR_RootConstrainSelectedInstOperands,
     /*   75055 */       // GIR_Coverage, 7511,
     /*   75055 */       GIR_EraseRootFromParent_Done,
     /*   75056 */     // Label 671: @75056
     /*   75056 */     GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(75137), // Rule ID 7404 //
     /*   75061 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtPkF16F32Inst),
     /*   75064 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   75068 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   75072 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   75076 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   75080 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   75084 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75088 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   75090 */       GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*   75097 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*   75104 */       // (build_vector:{ *:[v2f16] } (fpround:{ *:[f16] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers)), (fpround:{ *:[f16] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))  =>  (V_CVT_PK_F16_F32_e64:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1)
     /*   75104 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_F32_e64),
     /*   75107 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75109 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   75114 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   75119 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   75124 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   75129 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75132 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75135 */       GIR_RootConstrainSelectedInstOperands,
     /*   75136 */       // GIR_Coverage, 7404,
     /*   75136 */       GIR_EraseRootFromParent_Done,
     /*   75137 */     // Label 672: @75137
     /*   75137 */     GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(75233), // Rule ID 7565 //
     /*   75142 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
     /*   75145 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   75149 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   75153 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   75157 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75161 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /*   75165 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75169 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   75173 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   75175 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   75182 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   75189 */       // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
     /*   75189 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
     /*   75192 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75194 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   75199 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   75204 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   75209 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   75214 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75217 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75220 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75223 */       GIR_RootToRootCopy, /*OpIdx*/1, // elt0
     /*   75225 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75228 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75231 */       GIR_RootConstrainSelectedInstOperands,
     /*   75232 */       // GIR_Coverage, 7565,
     /*   75232 */       GIR_EraseRootFromParent_Done,
     /*   75233 */     // Label 673: @75233
     /*   75233 */     GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(75329), // Rule ID 7580 //
     /*   75238 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts_NotUseRealTrue16Insts),
     /*   75241 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   75245 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /*   75249 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   75253 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75257 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /*   75261 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75265 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   75269 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   75271 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   75278 */       GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
     /*   75285 */       // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
     /*   75285 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
     /*   75288 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75290 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   75295 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   75300 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*   75305 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*   75310 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75313 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75316 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75319 */       GIR_RootToRootCopy, /*OpIdx*/1, // elt0
     /*   75321 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75324 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75327 */       GIR_RootConstrainSelectedInstOperands,
     /*   75328 */       // GIR_Coverage, 7580,
     /*   75328 */       GIR_EraseRootFromParent_Done,
     /*   75329 */     // Label 674: @75329
     /*   75329 */     GIM_Reject,
     /*   75330 */   // Label 669: @75330
     /*   75330 */   GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(75840),
     /*   75335 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   75339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75343 */     GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(75469), // Rule ID 28407 //
     /*   75348 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   75351 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   75355 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75359 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   75363 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75367 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75371 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75375 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   75379 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75384 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   75388 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   75392 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75396 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   75400 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   75404 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75408 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /*   75412 */       GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
     /*   75416 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75421 */       GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
     /*   75425 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   75427 */       // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] })))<<P:Predicate_anonymous_45361>>  =>  (V_PERM_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] }))
     /*   75427 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   75430 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   75434 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   75439 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498),
     /*   75449 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   75451 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*   75454 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75456 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // b
     /*   75460 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a
     /*   75464 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   75467 */       GIR_RootConstrainSelectedInstOperands,
     /*   75468 */       // GIR_Coverage, 28407,
     /*   75468 */       GIR_EraseRootFromParent_Done,
     /*   75469 */     // Label 676: @75469
     /*   75469 */     GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(75548), // Rule ID 28415 //
     /*   75474 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isNotGFX9Plus),
     /*   75477 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   75481 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   75485 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   75489 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75493 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75497 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75501 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   75505 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75509 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   75513 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   75517 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75522 */       GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   75526 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75530 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   75532 */       // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_ALIGNBIT_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })
     /*   75532 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
     /*   75535 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75537 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   75539 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a
     /*   75543 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   75546 */       GIR_RootConstrainSelectedInstOperands,
     /*   75547 */       // GIR_Coverage, 28415,
     /*   75547 */       GIR_EraseRootFromParent_Done,
     /*   75548 */     // Label 677: @75548
     /*   75548 */     GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(75642), // Rule ID 28416 //
     /*   75553 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX9GFX10),
     /*   75556 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   75560 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   75564 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   75568 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75572 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75576 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75580 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   75584 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75588 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   75592 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   75596 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75601 */       GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   75605 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75609 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   75611 */       // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_ALIGNBIT_B32_opsel_e64:{ *:[v2f16] } 0:{ *:[i32] }, VGPR_32:{ *:[f16] }:$b, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$a, 0:{ *:[i32] }, 16:{ *:[i32] }, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   75611 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_opsel_e64),
     /*   75614 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75616 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75619 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   75621 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75624 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a
     /*   75628 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75631 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   75634 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75637 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75640 */       GIR_RootConstrainSelectedInstOperands,
     /*   75641 */       // GIR_Coverage, 28416,
     /*   75641 */       GIR_EraseRootFromParent_Done,
     /*   75642 */     // Label 678: @75642
     /*   75642 */     GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(75736), // Rule ID 28417 //
     /*   75647 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseFakeTrue16Insts),
     /*   75650 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   75654 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   75658 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   75662 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75666 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75670 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75674 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   75678 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75682 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   75686 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   75690 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75695 */       GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   75699 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75703 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   75705 */       // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_ALIGNBIT_B32_fake16_e64:{ *:[v2f16] } 0:{ *:[i32] }, VGPR_32:{ *:[f16] }:$b, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$a, 0:{ *:[i32] }, 16:{ *:[i16] }, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   75705 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_fake16_e64),
     /*   75708 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75710 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75713 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   75715 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75718 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a
     /*   75722 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75725 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   75728 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75731 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   75734 */       GIR_RootConstrainSelectedInstOperands,
     /*   75735 */       // GIR_Coverage, 28417,
     /*   75735 */       GIR_EraseRootFromParent_Done,
     /*   75736 */     // Label 679: @75736
     /*   75736 */     GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(75839), // Rule ID 28410 //
     /*   75741 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   75744 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75748 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   75752 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*   75756 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*   75760 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75764 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75768 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75772 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*   75776 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75780 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   75784 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /*   75788 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75793 */       GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
     /*   75797 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   75799 */       // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$a, (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_45361>>  =>  (V_BFI_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[f16] }:$a, VGPR_32:{ *:[i32] }:$b)
     /*   75799 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   75802 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   75806 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   75811 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
     /*   75821 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   75823 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   75826 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75828 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   75831 */       GIR_RootToRootCopy, /*OpIdx*/1, // a
     /*   75833 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // b
     /*   75837 */       GIR_RootConstrainSelectedInstOperands,
     /*   75838 */       // GIR_Coverage, 28410,
     /*   75838 */       GIR_EraseRootFromParent_Done,
     /*   75839 */     // Label 680: @75839
     /*   75839 */     GIM_Reject,
     /*   75840 */   // Label 675: @75840
     /*   75840 */   GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(75914), // Rule ID 28395 //
     /*   75845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
     /*   75848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   75852 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   75856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   75860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75864 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   75868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75872 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75876 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75880 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   75884 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   75886 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   75891 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   75895 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   75899 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   75901 */     // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src1, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>))<<P:Predicate_anonymous_45359>>  =>  (S_PACK_LH_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i32] }:$src1)
     /*   75901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LH_B32_B16),
     /*   75904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   75906 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   75908 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
     /*   75912 */     GIR_RootConstrainSelectedInstOperands,
     /*   75913 */     // GIR_Coverage, 28395,
     /*   75913 */     GIR_EraseRootFromParent_Done,
     /*   75914 */   // Label 681: @75914
     /*   75914 */   GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(76151),
     /*   75919 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   75923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75927 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75931 */     GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(75994), // Rule ID 28404 //
     /*   75936 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isNotGFX9Plus),
     /*   75939 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   75943 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   75947 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   75951 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   75955 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   75959 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   75963 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   75967 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   75972 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   75976 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   75978 */       // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_ALIGNBIT_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })
     /*   75978 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
     /*   75981 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   75983 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   75985 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a
     /*   75989 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   75992 */       GIR_RootConstrainSelectedInstOperands,
     /*   75993 */       // GIR_Coverage, 28404,
     /*   75993 */       GIR_EraseRootFromParent_Done,
     /*   75994 */     // Label 683: @75994
     /*   75994 */     GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(76072), // Rule ID 28405 //
     /*   75999 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX9GFX10),
     /*   76002 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76006 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   76010 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   76014 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   76018 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   76022 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   76026 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   76030 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76035 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   76039 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   76041 */       // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_ALIGNBIT_B32_opsel_e64:{ *:[v2i16] } 0:{ *:[i32] }, VGPR_32:{ *:[i16] }:$b, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$a, 0:{ *:[i32] }, 16:{ *:[i32] }, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   76041 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_opsel_e64),
     /*   76044 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76046 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76049 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   76051 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76054 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a
     /*   76058 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76061 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76064 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76067 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76070 */       GIR_RootConstrainSelectedInstOperands,
     /*   76071 */       // GIR_Coverage, 28405,
     /*   76071 */       GIR_EraseRootFromParent_Done,
     /*   76072 */     // Label 684: @76072
     /*   76072 */     GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(76150), // Rule ID 28406 //
     /*   76077 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseFakeTrue16Insts),
     /*   76080 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76084 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   76088 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   76092 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   76096 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   76100 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   76104 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   76108 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76113 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   76117 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   76119 */       // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_ALIGNBIT_B32_fake16_e64:{ *:[v2i16] } 0:{ *:[i32] }, VGPR_32:{ *:[i16] }:$b, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$a, 0:{ *:[i32] }, 16:{ *:[i16] }, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*   76119 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_fake16_e64),
     /*   76122 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76124 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76127 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   76129 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76132 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a
     /*   76136 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76139 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76142 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76145 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   76148 */       GIR_RootConstrainSelectedInstOperands,
     /*   76149 */       // GIR_Coverage, 28406,
     /*   76149 */       GIR_EraseRootFromParent_Done,
     /*   76150 */     // Label 685: @76150
     /*   76150 */     GIM_Reject,
     /*   76151 */   // Label 682: @76151
     /*   76151 */   GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(76221), // Rule ID 28421 //
     /*   76156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   76159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   76171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   76175 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   76179 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   76183 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   76187 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   76191 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   76193 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76198 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   76202 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76206 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   76208 */     // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>), SReg_32:{ *:[i16] }:$src1)  =>  (S_PACK_HL_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i16] }:$src1)
     /*   76208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_HL_B32_B16),
     /*   76211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   76213 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*   76217 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76219 */     GIR_RootConstrainSelectedInstOperands,
     /*   76220 */     // GIR_Coverage, 28421,
     /*   76220 */     GIR_EraseRootFromParent_Done,
     /*   76221 */   // Label 686: @76221
     /*   76221 */   GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(76431),
     /*   76226 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   76230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76234 */     GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(76325), // Rule ID 28399 //
     /*   76239 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   76242 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76246 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   76250 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   76254 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*   76258 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   76262 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*   76266 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   76270 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*   76274 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76279 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
     /*   76283 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   76285 */       // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$a, (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] })))<<P:Predicate_anonymous_45361>>  =>  (V_BFI_B32_e64:{ *:[v2i16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[i16] }:$a, VGPR_32:{ *:[i32] }:$b)
     /*   76285 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   76288 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   76292 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   76297 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
     /*   76307 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   76309 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
     /*   76312 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76314 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   76317 */       GIR_RootToRootCopy, /*OpIdx*/1, // a
     /*   76319 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // b
     /*   76323 */       GIR_RootConstrainSelectedInstOperands,
     /*   76324 */       // GIR_Coverage, 28399,
     /*   76324 */       GIR_EraseRootFromParent_Done,
     /*   76325 */     // Label 688: @76325
     /*   76325 */     GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(76430), // Rule ID 28393 //
     /*   76330 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   76333 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76337 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76341 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   76345 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   76349 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   76353 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   76355 */       // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), (trunc:{ *:[i16] } i32:{ *:[i32] }:$src1))<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2i16] } VGPR_32:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), lo16:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i16] } VGPR_32:{ *:[i32] }:$src1, lo16:{ *:[i32] }), hi16:{ *:[i32] })
     /*   76355 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*   76358 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   76362 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   76367 */       GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(2), // src1
     /*   76373 */       GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   76378 */       GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76383 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   76386 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   76390 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   76395 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   76397 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   76400 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   76402 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   76405 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   76408 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   76411 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   76414 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76419 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   76424 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   76429 */       // GIR_Coverage, 28393,
     /*   76429 */       GIR_EraseRootFromParent_Done,
     /*   76430 */     // Label 689: @76430
     /*   76430 */     GIM_Reject,
     /*   76431 */   // Label 687: @76431
     /*   76431 */   GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(76467), // Rule ID 28377 //
     /*   76436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76440 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*   76444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76448 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   76452 */     // (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45359>>  =>  (S_LSHL_B32:{ *:[v2i16] }:{ *:[i1] } SReg_32:{ *:[i16] }:$src1, 16:{ *:[i16] })
     /*   76452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
     /*   76455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   76457 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76462 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   76465 */     GIR_RootConstrainSelectedInstOperands,
     /*   76466 */     // GIR_Coverage, 28377,
     /*   76466 */     GIR_EraseRootFromParent_Done,
     /*   76467 */   // Label 690: @76467
     /*   76467 */   GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(76561),
     /*   76472 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   76476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76480 */     GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(76508), // Rule ID 28378 //
     /*   76485 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76488 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*   76492 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76496 */       // (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45361>>  =>  (V_LSHLREV_B32_e64:{ *:[v2i16] } 16:{ *:[i16] }, VGPR_32:{ *:[i16] }:$src1)
     /*   76496 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*   76499 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76501 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76504 */       GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76506 */       GIR_RootConstrainSelectedInstOperands,
     /*   76507 */       // GIR_Coverage, 28378,
     /*   76507 */       GIR_EraseRootFromParent_Done,
     /*   76508 */     // Label 692: @76508
     /*   76508 */     GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(76560), // Rule ID 28379 //
     /*   76513 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76516 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76520 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /*   76524 */       // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src1, 0:{ *:[i16] })<<P:Predicate_anonymous_45361>>  =>  (V_AND_B32_e64:{ *:[v2i16] } (V_MOV_B32_e32:{ *:[i32] } 65535:{ *:[i32] }), VGPR_32:{ *:[i16] }:$src1)
     /*   76524 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   76527 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*   76531 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   76536 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
     /*   76546 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   76548 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   76551 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76553 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   76556 */       GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   76558 */       GIR_RootConstrainSelectedInstOperands,
     /*   76559 */       // GIR_Coverage, 28379,
     /*   76559 */       GIR_EraseRootFromParent_Done,
     /*   76560 */     // Label 693: @76560
     /*   76560 */     GIM_Reject,
     /*   76561 */   // Label 691: @76561
     /*   76561 */   GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(76664),
     /*   76566 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   76570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76574 */     GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(76626), // Rule ID 28381 //
     /*   76579 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76583 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /*   76587 */       // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src1, 0:{ *:[i16] })<<P:Predicate_anonymous_45359>>  =>  (S_AND_B32:{ *:[v2i16] }:{ *:[i1] } (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] }), SReg_32:{ *:[i16] }:$src1)
     /*   76587 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   76590 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   76594 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   76599 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
     /*   76609 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   76611 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*   76614 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   76616 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   76619 */       GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*   76621 */       GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   76624 */       GIR_RootConstrainSelectedInstOperands,
     /*   76625 */       // GIR_Coverage, 28381,
     /*   76625 */       GIR_EraseRootFromParent_Done,
     /*   76626 */     // Label 695: @76626
     /*   76626 */     GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(76663), // Rule ID 28385 //
     /*   76631 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76634 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76638 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76642 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76646 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76648 */       // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45359>>  =>  (S_LSHL_B32:{ *:[v2i16] }:{ *:[i1] } SReg_32:{ *:[i16] }:$src1, 16:{ *:[i32] })
     /*   76648 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
     /*   76651 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   76653 */       GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76655 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76658 */       GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   76661 */       GIR_RootConstrainSelectedInstOperands,
     /*   76662 */       // GIR_Coverage, 28385,
     /*   76662 */       GIR_EraseRootFromParent_Done,
     /*   76663 */     // Label 696: @76663
     /*   76663 */     GIM_Reject,
     /*   76664 */   // Label 694: @76664
     /*   76664 */   GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(76706), // Rule ID 28386 //
     /*   76669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76676 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76680 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76688 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   76692 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76694 */     // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45361>>  =>  (V_LSHLREV_B32_e64:{ *:[v2i16] } 16:{ *:[i32] }, VGPR_32:{ *:[i16] }:$src1)
     /*   76694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*   76697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76702 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76704 */     GIR_RootConstrainSelectedInstOperands,
     /*   76705 */     // GIR_Coverage, 28386,
     /*   76705 */     GIR_EraseRootFromParent_Done,
     /*   76706 */   // Label 697: @76706
     /*   76706 */   GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(76751), // Rule ID 28389 //
     /*   76711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76718 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76722 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76730 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   76734 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76736 */     // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), SReg_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_45359>>  =>  (S_LSHL_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src1, 16:{ *:[i32] })
     /*   76736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
     /*   76739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   76741 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76746 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*   76749 */     GIR_RootConstrainSelectedInstOperands,
     /*   76750 */     // GIR_Coverage, 28389,
     /*   76750 */     GIR_EraseRootFromParent_Done,
     /*   76751 */   // Label 698: @76751
     /*   76751 */   GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(76793), // Rule ID 28390 //
     /*   76756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76771 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76775 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   76779 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76781 */     // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), VGPR_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_45361>>  =>  (V_LSHLREV_B32_e64:{ *:[v2f16] } 16:{ *:[i32] }, VGPR_32:{ *:[f16] }:$src1)
     /*   76781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*   76784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   76786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   76789 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   76791 */     GIR_RootConstrainSelectedInstOperands,
     /*   76792 */     // GIR_Coverage, 28390,
     /*   76792 */     GIR_EraseRootFromParent_Done,
     /*   76793 */   // Label 699: @76793
     /*   76793 */   GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(76833), // Rule ID 28383 //
     /*   76798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76802 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   76810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76814 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   76818 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76820 */     // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_45359>>  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i32] })
     /*   76820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   76823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   76825 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   76827 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76832 */     // GIR_Coverage, 28383,
     /*   76832 */     GIR_EraseRootFromParent_Done,
     /*   76833 */   // Label 700: @76833
     /*   76833 */   GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(76876), // Rule ID 28384 //
     /*   76838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76845 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   76853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76857 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   76861 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76863 */     // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_45361>>  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, VGPR_32:{ *:[i32] })
     /*   76863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   76866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   76868 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   76870 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76875 */     // GIR_Coverage, 28384,
     /*   76875 */     GIR_EraseRootFromParent_Done,
     /*   76876 */   // Label 701: @76876
     /*   76876 */   GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(76916), // Rule ID 28387 //
     /*   76881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76885 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76889 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   76893 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76897 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   76901 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76903 */     // (build_vector:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, (undef:{ *:[f16] }))<<P:Predicate_anonymous_45359>>  =>  (COPY_TO_REGCLASS:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[i32] })
     /*   76903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   76906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   76908 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   76910 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   76915 */     // GIR_Coverage, 28387,
     /*   76915 */     GIR_EraseRootFromParent_Done,
     /*   76916 */   // Label 702: @76916
     /*   76916 */   GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(77313),
     /*   76921 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   76925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76929 */     GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(76964), // Rule ID 28388 //
     /*   76934 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*   76937 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76941 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   76945 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76949 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76951 */       // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$src0, (undef:{ *:[f16] }))<<P:Predicate_anonymous_45361>>  =>  (COPY_TO_REGCLASS:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$src0, VGPR_32:{ *:[i32] })
     /*   76951 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   76954 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   76956 */       GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   76958 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   76963 */       // GIR_Coverage, 28388,
     /*   76963 */       GIR_EraseRootFromParent_Done,
     /*   76964 */     // Label 704: @76964
     /*   76964 */     GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(77032), // Rule ID 28402 //
     /*   76969 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseRealTrue16Insts),
     /*   76972 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   76976 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   76980 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   76984 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   76986 */       // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), VGPR_16:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2i16] } VGPR_32:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), lo16:{ *:[i32] }, VGPR_16:{ *:[i16] }:$src1, hi16:{ *:[i32] })
     /*   76986 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   76989 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   76993 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   76998 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77000 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   77003 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   77005 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77008 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   77011 */       GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   77013 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   77016 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77021 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77026 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77031 */       // GIR_Coverage, 28402,
     /*   77031 */       GIR_EraseRootFromParent_Done,
     /*   77032 */     // Label 705: @77032
     /*   77032 */     GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(77100), // Rule ID 28413 //
     /*   77037 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseRealTrue16Insts),
     /*   77040 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   77044 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   77048 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77052 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   77054 */       // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), VGPR_16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2f16] } VGPR_32:{ *:[i32] }, (IMPLICIT_DEF:{ *:[f16] }), lo16:{ *:[i32] }, VGPR_16:{ *:[f16] }:$src1, hi16:{ *:[i32] })
     /*   77054 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   77057 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   77061 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77066 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77068 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   77071 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   77073 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77076 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   77079 */       GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   77081 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   77084 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77089 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77094 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77099 */       // GIR_Coverage, 28413,
     /*   77099 */       GIR_EraseRootFromParent_Done,
     /*   77100 */     // Label 706: @77100
     /*   77100 */     GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(77168), // Rule ID 28401 //
     /*   77105 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseRealTrue16Insts),
     /*   77108 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77112 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   77116 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   77120 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   77122 */       // (build_vector:{ *:[v2i16] } VGPR_16:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2i16] } VGPR_32:{ *:[i32] }, ?:{ *:[i16] }:$src0, lo16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), hi16:{ *:[i32] })
     /*   77122 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   77125 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   77129 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77134 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77136 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   77139 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   77141 */       GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77143 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   77146 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77149 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   77152 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77157 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77162 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77167 */       // GIR_Coverage, 28401,
     /*   77167 */       GIR_EraseRootFromParent_Done,
     /*   77168 */     // Label 707: @77168
     /*   77168 */     GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(77236), // Rule ID 28412 //
     /*   77173 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseRealTrue16Insts),
     /*   77176 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77180 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   77184 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*   77188 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   77190 */       // (build_vector:{ *:[v2f16] } VGPR_16:{ *:[f16] }:$src0, (undef:{ *:[f16] }))<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2f16] } VGPR_32:{ *:[i32] }, ?:{ *:[f16] }:$src0, lo16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[f16] }), hi16:{ *:[i32] })
     /*   77190 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   77193 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   77197 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77202 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77204 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   77207 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   77209 */       GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77211 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   77214 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77217 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   77220 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77225 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77230 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77235 */       // GIR_Coverage, 28412,
     /*   77235 */       GIR_EraseRootFromParent_Done,
     /*   77236 */     // Label 708: @77236
     /*   77236 */     GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(77312), // Rule ID 28394 //
     /*   77241 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   77244 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77248 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77252 */       // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45361>>  =>  (V_LSHL_OR_B32_e64:{ *:[v2i16] } ?:{ *:[i16] }:$src1, 16:{ *:[i32] }, (V_AND_B32_e64:{ *:[i32] } (V_MOV_B32_e32:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src0))
     /*   77252 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   77255 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*   77259 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77264 */       GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(65535),
     /*   77274 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   77276 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   77279 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*   77283 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77288 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   77291 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src0
     /*   77295 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77297 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
     /*   77300 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   77302 */       GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*   77304 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*   77307 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77310 */       GIR_RootConstrainSelectedInstOperands,
     /*   77311 */       // GIR_Coverage, 28394,
     /*   77311 */       GIR_EraseRootFromParent_Done,
     /*   77312 */     // Label 709: @77312
     /*   77312 */     GIM_Reject,
     /*   77313 */   // Label 703: @77313
     /*   77313 */   GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(77344), // Rule ID 28397 //
     /*   77318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
     /*   77321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77325 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77329 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77333 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   77337 */     // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_45359>>  =>  (S_PACK_LL_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i16] }:$src1)
     /*   77337 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16),
     /*   77342 */     GIR_RootConstrainSelectedInstOperands,
     /*   77343 */     // GIR_Coverage, 28397,
     /*   77343 */     GIR_Done,
     /*   77344 */   // Label 710: @77344
     /*   77344 */   GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(77459),
     /*   77349 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   77353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77357 */     GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(77411), // Rule ID 28398 //
     /*   77362 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   77365 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77369 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77373 */       // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$a, VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_PERM_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$b, VGPR_32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] }))
     /*   77373 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   77376 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   77380 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77385 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480),
     /*   77395 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77397 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*   77400 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   77402 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   77404 */       GIR_RootToRootCopy, /*OpIdx*/1, // a
     /*   77406 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77409 */       GIR_RootConstrainSelectedInstOperands,
     /*   77410 */       // GIR_Coverage, 28398,
     /*   77410 */       GIR_EraseRootFromParent_Done,
     /*   77411 */     // Label 712: @77411
     /*   77411 */     GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(77458), // Rule ID 28400 //
     /*   77416 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseRealTrue16Insts),
     /*   77419 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77423 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77427 */       // (build_vector:{ *:[v2i16] } VGPR_16:{ *:[i16] }:$a, VGPR_16:{ *:[i16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2i16] } VGPR_32:{ *:[i32] }, VGPR_16:{ *:[i16] }:$a, lo16:{ *:[i32] }, VGPR_16:{ *:[i16] }:$b, hi16:{ *:[i32] })
     /*   77427 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   77430 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   77432 */       GIR_RootToRootCopy, /*OpIdx*/1, // a
     /*   77434 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   77437 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   77439 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   77442 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77447 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77452 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77457 */       // GIR_Coverage, 28400,
     /*   77457 */       GIR_EraseRootFromParent_Done,
     /*   77458 */     // Label 713: @77458
     /*   77458 */     GIM_Reject,
     /*   77459 */   // Label 711: @77459
     /*   77459 */   GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(77490), // Rule ID 28408 //
     /*   77464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
     /*   77467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77471 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77479 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45359),
     /*   77483 */     // (build_vector:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_45359>>  =>  (S_PACK_LL_B32_B16:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[f16] }:$src1)
     /*   77483 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16),
     /*   77488 */     GIR_RootConstrainSelectedInstOperands,
     /*   77489 */     // GIR_Coverage, 28408,
     /*   77489 */     GIR_Done,
     /*   77490 */   // Label 714: @77490
     /*   77490 */   GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(77605),
     /*   77495 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45361),
     /*   77499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77503 */     GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(77557), // Rule ID 28409 //
     /*   77508 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_NotUseRealTrue16Insts),
     /*   77511 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77515 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77519 */       // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$a, VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (V_PERM_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$b, VGPR_32:{ *:[f16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] }))
     /*   77519 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*   77522 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   77526 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   77531 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480),
     /*   77541 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   77543 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*   77546 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   77548 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   77550 */       GIR_RootToRootCopy, /*OpIdx*/1, // a
     /*   77552 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   77555 */       GIR_RootConstrainSelectedInstOperands,
     /*   77556 */       // GIR_Coverage, 28409,
     /*   77556 */       GIR_EraseRootFromParent_Done,
     /*   77557 */     // Label 716: @77557
     /*   77557 */     GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(77604), // Rule ID 28411 //
     /*   77562 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts_UseRealTrue16Insts),
     /*   77565 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77569 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77573 */       // (build_vector:{ *:[v2f16] } VGPR_16:{ *:[f16] }:$a, VGPR_16:{ *:[f16] }:$b)<<P:Predicate_anonymous_45361>>  =>  (REG_SEQUENCE:{ *:[v2f16] } VGPR_32:{ *:[i32] }, VGPR_16:{ *:[f16] }:$a, lo16:{ *:[i32] }, VGPR_16:{ *:[f16] }:$b, hi16:{ *:[i32] })
     /*   77573 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   77576 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   77578 */       GIR_RootToRootCopy, /*OpIdx*/1, // a
     /*   77580 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*   77583 */       GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*   77585 */       GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*   77588 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77593 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77598 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   77603 */       // GIR_Coverage, 28411,
     /*   77603 */       GIR_EraseRootFromParent_Done,
     /*   77604 */     // Label 717: @77604
     /*   77604 */     GIM_Reject,
     /*   77605 */   // Label 715: @77605
     /*   77605 */   GIM_Reject,
     /*   77606 */ // Label 658: @77606
     /*   77606 */ GIM_Reject,
     /*   77607 */ // Label 8: @77607
     /*   77607 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(34), /*)*//*default:*//*Label 744*/ GIMT_Encode4(86770),
     /*   77618 */ /*GILLT_s16*//*Label 718*/ GIMT_Encode4(77722),
     /*   77622 */ /*GILLT_s32*//*Label 719*/ GIMT_Encode4(77836),
     /*   77626 */ /*GILLT_s64*//*Label 720*/ GIMT_Encode4(78185),
     /*   77630 */ /*GILLT_v2s16*//*Label 721*/ GIMT_Encode4(78476),
     /*   77634 */ /*GILLT_v2s32*//*Label 722*/ GIMT_Encode4(78825),
     /*   77638 */ /*GILLT_v2s64*//*Label 723*/ GIMT_Encode4(79116),
     /*   77642 */ /*GILLT_v3s32*//*Label 724*/ GIMT_Encode4(79697),
     /*   77646 */ /*GILLT_v3s64*//*Label 725*/ GIMT_Encode4(79751),
     /*   77650 */ /*GILLT_v4s16*//*Label 726*/ GIMT_Encode4(80100),
     /*   77654 */ /*GILLT_v4s32*//*Label 727*/ GIMT_Encode4(80391),
     /*   77658 */ /*GILLT_v4s64*//*Label 728*/ GIMT_Encode4(80972),
     /*   77662 */ /*GILLT_v5s32*//*Label 729*/ GIMT_Encode4(81553),
     /*   77666 */ /*GILLT_v6s32*//*Label 730*/ GIMT_Encode4(81667),
     /*   77670 */ /*GILLT_v7s32*//*Label 731*/ GIMT_Encode4(82016),
     /*   77674 */ /*GILLT_v8s16*//*Label 732*/ GIMT_Encode4(82130),
     /*   77678 */ /*GILLT_v8s32*//*Label 733*/ GIMT_Encode4(82711),
     /*   77682 */ /*GILLT_v8s64*//*Label 734*/ GIMT_Encode4(83292),
     /*   77686 */ /*GILLT_v9s32*//*Label 735*/ GIMT_Encode4(83873),
     /*   77690 */ /*GILLT_v10s32*//*Label 736*/ GIMT_Encode4(83987),
     /*   77694 */ /*GILLT_v11s32*//*Label 737*/ GIMT_Encode4(84101),
     /*   77698 */ /*GILLT_v12s32*//*Label 738*/ GIMT_Encode4(84215),
     /*   77702 */ /*GILLT_v16s16*//*Label 739*/ GIMT_Encode4(84329),
     /*   77706 */ /*GILLT_v16s32*//*Label 740*/ GIMT_Encode4(84910),
     /*   77710 */ /*GILLT_v16s64*//*Label 741*/ GIMT_Encode4(85491),
     /*   77714 */ /*GILLT_v32s16*//*Label 742*/ GIMT_Encode4(85840),
     /*   77718 */ /*GILLT_v32s32*//*Label 743*/ GIMT_Encode4(86421),
     /*   77722 */ // Label 718: @77722
     /*   77722 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(77835),
     /*   77727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   77730 */   GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(77756), // Rule ID 27543 //
     /*   77735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77739 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77743 */     // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
     /*   77743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77746 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77748 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77750 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77755 */     // GIR_Coverage, 27543,
     /*   77755 */     GIR_EraseRootFromParent_Done,
     /*   77756 */   // Label 746: @77756
     /*   77756 */   GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(77782), // Rule ID 27544 //
     /*   77761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77769 */     // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
     /*   77769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77772 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77774 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77776 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77781 */     // GIR_Coverage, 27544,
     /*   77781 */     GIR_EraseRootFromParent_Done,
     /*   77782 */   // Label 747: @77782
     /*   77782 */   GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(77808), // Rule ID 27545 //
     /*   77787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77791 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77795 */     // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
     /*   77795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77798 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77800 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77802 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77807 */     // GIR_Coverage, 27545,
     /*   77807 */     GIR_EraseRootFromParent_Done,
     /*   77808 */   // Label 748: @77808
     /*   77808 */   GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(77834), // Rule ID 27546 //
     /*   77813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77821 */     // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
     /*   77821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77824 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77826 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77828 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77833 */     // GIR_Coverage, 27546,
     /*   77833 */     GIR_EraseRootFromParent_Done,
     /*   77834 */   // Label 749: @77834
     /*   77834 */   GIM_Reject,
     /*   77835 */ // Label 745: @77835
     /*   77835 */ GIM_Reject,
     /*   77836 */ // Label 719: @77836
     /*   77836 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(77865), // Rule ID 27547 //
     /*   77841 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   77844 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77848 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77852 */   // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
     /*   77852 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77855 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77857 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77859 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77864 */   // GIR_Coverage, 27547,
     /*   77864 */   GIR_EraseRootFromParent_Done,
     /*   77865 */ // Label 750: @77865
     /*   77865 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(77894), // Rule ID 27548 //
     /*   77870 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   77873 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77877 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77881 */   // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
     /*   77881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77884 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77886 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77888 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77893 */   // GIR_Coverage, 27548,
     /*   77893 */   GIR_EraseRootFromParent_Done,
     /*   77894 */ // Label 751: @77894
     /*   77894 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(77923), // Rule ID 27549 //
     /*   77899 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   77902 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77906 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77910 */   // (bitconvert:{ *:[i32] } VGPR_32:{ *:[v2i16] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
     /*   77910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77913 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77915 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77917 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77922 */   // GIR_Coverage, 27549,
     /*   77922 */   GIR_EraseRootFromParent_Done,
     /*   77923 */ // Label 752: @77923
     /*   77923 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(77952), // Rule ID 27550 //
     /*   77928 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   77931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77935 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77939 */   // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
     /*   77939 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77942 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77944 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77946 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77951 */   // GIR_Coverage, 27550,
     /*   77951 */   GIR_EraseRootFromParent_Done,
     /*   77952 */ // Label 753: @77952
     /*   77952 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(77981), // Rule ID 27551 //
     /*   77957 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   77960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77964 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77968 */   // (bitconvert:{ *:[i32] } VGPR_32:{ *:[v2f16] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
     /*   77968 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   77971 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   77973 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   77975 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   77980 */   // GIR_Coverage, 27551,
     /*   77980 */   GIR_EraseRootFromParent_Done,
     /*   77981 */ // Label 754: @77981
     /*   77981 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(78010), // Rule ID 27552 //
     /*   77986 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   77989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77993 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   77997 */   // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
     /*   77997 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78000 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78002 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78004 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78009 */   // GIR_Coverage, 27552,
     /*   78009 */   GIR_EraseRootFromParent_Done,
     /*   78010 */ // Label 755: @78010
     /*   78010 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(78039), // Rule ID 27553 //
     /*   78015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78026 */   // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
     /*   78026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78029 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78031 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78033 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78038 */   // GIR_Coverage, 27553,
     /*   78038 */   GIR_EraseRootFromParent_Done,
     /*   78039 */ // Label 756: @78039
     /*   78039 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(78068), // Rule ID 27554 //
     /*   78044 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78047 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78051 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78055 */   // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
     /*   78055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78058 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78060 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78062 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78067 */   // GIR_Coverage, 27554,
     /*   78067 */   GIR_EraseRootFromParent_Done,
     /*   78068 */ // Label 757: @78068
     /*   78068 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(78097), // Rule ID 27555 //
     /*   78073 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78080 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78084 */   // (bitconvert:{ *:[f32] } VGPR_32:{ *:[v2i16] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
     /*   78084 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78087 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78089 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78091 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78096 */   // GIR_Coverage, 27555,
     /*   78096 */   GIR_EraseRootFromParent_Done,
     /*   78097 */ // Label 758: @78097
     /*   78097 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(78126), // Rule ID 27556 //
     /*   78102 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78105 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78109 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78113 */   // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
     /*   78113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78116 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78118 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78120 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78125 */   // GIR_Coverage, 27556,
     /*   78125 */   GIR_EraseRootFromParent_Done,
     /*   78126 */ // Label 759: @78126
     /*   78126 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(78155), // Rule ID 27557 //
     /*   78131 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78138 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78142 */   // (bitconvert:{ *:[f32] } VGPR_32:{ *:[v2f16] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
     /*   78142 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78145 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78147 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78149 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78154 */   // GIR_Coverage, 27557,
     /*   78154 */   GIR_EraseRootFromParent_Done,
     /*   78155 */ // Label 760: @78155
     /*   78155 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(78184), // Rule ID 27558 //
     /*   78160 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78167 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78171 */   // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
     /*   78171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78174 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78176 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78178 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78183 */   // GIR_Coverage, 27558,
     /*   78183 */   GIR_EraseRootFromParent_Done,
     /*   78184 */ // Label 761: @78184
     /*   78184 */ GIM_Reject,
     /*   78185 */ // Label 720: @78185
     /*   78185 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(78214), // Rule ID 27571 //
     /*   78190 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   78193 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78197 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78201 */   // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
     /*   78201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78204 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78206 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78208 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78213 */   // GIR_Coverage, 27571,
     /*   78213 */   GIR_EraseRootFromParent_Done,
     /*   78214 */ // Label 762: @78214
     /*   78214 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(78243), // Rule ID 27572 //
     /*   78219 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   78222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78226 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78230 */   // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
     /*   78230 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78233 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78235 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78237 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78242 */   // GIR_Coverage, 27572,
     /*   78242 */   GIR_EraseRootFromParent_Done,
     /*   78243 */ // Label 763: @78243
     /*   78243 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(78272), // Rule ID 27573 //
     /*   78248 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   78251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78255 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78259 */   // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
     /*   78259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78262 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78264 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78266 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78271 */   // GIR_Coverage, 27573,
     /*   78271 */   GIR_EraseRootFromParent_Done,
     /*   78272 */ // Label 764: @78272
     /*   78272 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(78301), // Rule ID 27574 //
     /*   78277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   78280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78284 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78288 */   // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
     /*   78288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78291 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78293 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78295 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78300 */   // GIR_Coverage, 27574,
     /*   78300 */   GIR_EraseRootFromParent_Done,
     /*   78301 */ // Label 765: @78301
     /*   78301 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(78330), // Rule ID 27575 //
     /*   78306 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   78309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78313 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78317 */   // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
     /*   78317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78320 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78322 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78324 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78329 */   // GIR_Coverage, 27575,
     /*   78329 */   GIR_EraseRootFromParent_Done,
     /*   78330 */ // Label 766: @78330
     /*   78330 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(78359), // Rule ID 27576 //
     /*   78335 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   78338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78342 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78346 */   // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
     /*   78346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78349 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78351 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78353 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78358 */   // GIR_Coverage, 27576,
     /*   78358 */   GIR_EraseRootFromParent_Done,
     /*   78359 */ // Label 767: @78359
     /*   78359 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(78388), // Rule ID 27577 //
     /*   78364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   78367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78371 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78375 */   // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
     /*   78375 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78378 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78380 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78382 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78387 */   // GIR_Coverage, 27577,
     /*   78387 */   GIR_EraseRootFromParent_Done,
     /*   78388 */ // Label 768: @78388
     /*   78388 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(78417), // Rule ID 27578 //
     /*   78393 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   78396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78400 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78404 */   // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
     /*   78404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78407 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78409 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78411 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78416 */   // GIR_Coverage, 27578,
     /*   78416 */   GIR_EraseRootFromParent_Done,
     /*   78417 */ // Label 769: @78417
     /*   78417 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(78446), // Rule ID 27579 //
     /*   78422 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   78425 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78429 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78433 */   // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
     /*   78433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78436 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78438 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78440 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78445 */   // GIR_Coverage, 27579,
     /*   78445 */   GIR_EraseRootFromParent_Done,
     /*   78446 */ // Label 770: @78446
     /*   78446 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(78475), // Rule ID 27580 //
     /*   78451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   78454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78458 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78462 */   // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
     /*   78462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78465 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78467 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78469 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78474 */   // GIR_Coverage, 27580,
     /*   78474 */   GIR_EraseRootFromParent_Done,
     /*   78475 */ // Label 771: @78475
     /*   78475 */ GIM_Reject,
     /*   78476 */ // Label 721: @78476
     /*   78476 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(78505), // Rule ID 27559 //
     /*   78481 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78488 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78492 */   // (bitconvert:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[v2i16] }:$src0
     /*   78492 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78495 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78497 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78499 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78504 */   // GIR_Coverage, 27559,
     /*   78504 */   GIR_EraseRootFromParent_Done,
     /*   78505 */ // Label 772: @78505
     /*   78505 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(78534), // Rule ID 27560 //
     /*   78510 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78517 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78521 */   // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
     /*   78521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78524 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78526 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78528 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78533 */   // GIR_Coverage, 27560,
     /*   78533 */   GIR_EraseRootFromParent_Done,
     /*   78534 */ // Label 773: @78534
     /*   78534 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(78563), // Rule ID 27561 //
     /*   78539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78546 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78550 */   // (bitconvert:{ *:[v2i16] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[v2i16] }:$src0
     /*   78550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78553 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78555 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78557 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78562 */   // GIR_Coverage, 27561,
     /*   78562 */   GIR_EraseRootFromParent_Done,
     /*   78563 */ // Label 774: @78563
     /*   78563 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(78592), // Rule ID 27562 //
     /*   78568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78571 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78575 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78579 */   // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
     /*   78579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78582 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78584 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78586 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78591 */   // GIR_Coverage, 27562,
     /*   78591 */   GIR_EraseRootFromParent_Done,
     /*   78592 */ // Label 775: @78592
     /*   78592 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(78621), // Rule ID 27563 //
     /*   78597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78604 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78608 */   // (bitconvert:{ *:[v2i16] } VGPR_32:{ *:[v2f16] }:$src0)  =>  VGPR_32:{ *:[v2i16] }:$src0
     /*   78608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78611 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78613 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78615 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78620 */   // GIR_Coverage, 27563,
     /*   78620 */   GIR_EraseRootFromParent_Done,
     /*   78621 */ // Label 776: @78621
     /*   78621 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(78650), // Rule ID 27564 //
     /*   78626 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78629 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78633 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78637 */   // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
     /*   78637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78640 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78642 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78644 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78649 */   // GIR_Coverage, 27564,
     /*   78649 */   GIR_EraseRootFromParent_Done,
     /*   78650 */ // Label 777: @78650
     /*   78650 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(78679), // Rule ID 27565 //
     /*   78655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78662 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78666 */   // (bitconvert:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[v2f16] }:$src0
     /*   78666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78669 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78671 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78673 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78678 */   // GIR_Coverage, 27565,
     /*   78678 */   GIR_EraseRootFromParent_Done,
     /*   78679 */ // Label 778: @78679
     /*   78679 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(78708), // Rule ID 27566 //
     /*   78684 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78691 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78695 */   // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
     /*   78695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78698 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78700 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78702 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78707 */   // GIR_Coverage, 27566,
     /*   78707 */   GIR_EraseRootFromParent_Done,
     /*   78708 */ // Label 779: @78708
     /*   78708 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(78737), // Rule ID 27567 //
     /*   78713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78720 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78724 */   // (bitconvert:{ *:[v2f16] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[v2f16] }:$src0
     /*   78724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78727 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78729 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78731 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78736 */   // GIR_Coverage, 27567,
     /*   78736 */   GIR_EraseRootFromParent_Done,
     /*   78737 */ // Label 780: @78737
     /*   78737 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(78766), // Rule ID 27568 //
     /*   78742 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   78745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78749 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78753 */   // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
     /*   78753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78756 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78758 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78760 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78765 */   // GIR_Coverage, 27568,
     /*   78765 */   GIR_EraseRootFromParent_Done,
     /*   78766 */ // Label 781: @78766
     /*   78766 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(78795), // Rule ID 27569 //
     /*   78771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78778 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78782 */   // (bitconvert:{ *:[v2f16] } VGPR_32:{ *:[v2i16] }:$src0)  =>  VGPR_32:{ *:[v2f16] }:$src0
     /*   78782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78785 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78787 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78789 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   78794 */   // GIR_Coverage, 27569,
     /*   78794 */   GIR_EraseRootFromParent_Done,
     /*   78795 */ // Label 782: @78795
     /*   78795 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(78824), // Rule ID 27570 //
     /*   78800 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*   78803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78807 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78811 */   // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
     /*   78811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78814 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78816 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78818 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   78823 */   // GIR_Coverage, 27570,
     /*   78823 */   GIR_EraseRootFromParent_Done,
     /*   78824 */ // Label 783: @78824
     /*   78824 */ GIM_Reject,
     /*   78825 */ // Label 722: @78825
     /*   78825 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(78854), // Rule ID 27581 //
     /*   78830 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   78833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78837 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78841 */   // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
     /*   78841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78844 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78846 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78848 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78853 */   // GIR_Coverage, 27581,
     /*   78853 */   GIR_EraseRootFromParent_Done,
     /*   78854 */ // Label 784: @78854
     /*   78854 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(78883), // Rule ID 27582 //
     /*   78859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   78862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78866 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78870 */   // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
     /*   78870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78873 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78875 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78877 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78882 */   // GIR_Coverage, 27582,
     /*   78882 */   GIR_EraseRootFromParent_Done,
     /*   78883 */ // Label 785: @78883
     /*   78883 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(78912), // Rule ID 27583 //
     /*   78888 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   78891 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78895 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78899 */   // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
     /*   78899 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78902 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78904 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78906 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78911 */   // GIR_Coverage, 27583,
     /*   78911 */   GIR_EraseRootFromParent_Done,
     /*   78912 */ // Label 786: @78912
     /*   78912 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(78941), // Rule ID 27584 //
     /*   78917 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   78920 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78924 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78928 */   // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
     /*   78928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78931 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78933 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78935 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78940 */   // GIR_Coverage, 27584,
     /*   78940 */   GIR_EraseRootFromParent_Done,
     /*   78941 */ // Label 787: @78941
     /*   78941 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(78970), // Rule ID 27585 //
     /*   78946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   78949 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78953 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78957 */   // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
     /*   78957 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78960 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78962 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78964 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78969 */   // GIR_Coverage, 27585,
     /*   78969 */   GIR_EraseRootFromParent_Done,
     /*   78970 */ // Label 788: @78970
     /*   78970 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(78999), // Rule ID 27586 //
     /*   78975 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   78978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78982 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78986 */   // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
     /*   78986 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   78989 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   78991 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   78993 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   78998 */   // GIR_Coverage, 27586,
     /*   78998 */   GIR_EraseRootFromParent_Done,
     /*   78999 */ // Label 789: @78999
     /*   78999 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(79028), // Rule ID 27587 //
     /*   79004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   79007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79011 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79015 */   // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
     /*   79015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79018 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79020 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79022 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79027 */   // GIR_Coverage, 27587,
     /*   79027 */   GIR_EraseRootFromParent_Done,
     /*   79028 */ // Label 790: @79028
     /*   79028 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(79057), // Rule ID 27588 //
     /*   79033 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   79036 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79040 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79044 */   // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
     /*   79044 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79047 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79049 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79051 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79056 */   // GIR_Coverage, 27588,
     /*   79056 */   GIR_EraseRootFromParent_Done,
     /*   79057 */ // Label 791: @79057
     /*   79057 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(79086), // Rule ID 27589 //
     /*   79062 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   79065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79069 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79073 */   // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
     /*   79073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79076 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79078 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79080 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79085 */   // GIR_Coverage, 27589,
     /*   79085 */   GIR_EraseRootFromParent_Done,
     /*   79086 */ // Label 792: @79086
     /*   79086 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(79115), // Rule ID 27590 //
     /*   79091 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   79094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79098 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79102 */   // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
     /*   79102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79105 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79107 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79109 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   79114 */   // GIR_Coverage, 27590,
     /*   79114 */   GIR_EraseRootFromParent_Done,
     /*   79115 */ // Label 793: @79115
     /*   79115 */ GIM_Reject,
     /*   79116 */ // Label 723: @79116
     /*   79116 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(79145), // Rule ID 27623 //
     /*   79121 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79128 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79132 */   // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
     /*   79132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79135 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79137 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79139 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79144 */   // GIR_Coverage, 27623,
     /*   79144 */   GIR_EraseRootFromParent_Done,
     /*   79145 */ // Label 794: @79145
     /*   79145 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(79174), // Rule ID 27624 //
     /*   79150 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79153 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79157 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79161 */   // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
     /*   79161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79164 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79166 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79168 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79173 */   // GIR_Coverage, 27624,
     /*   79173 */   GIR_EraseRootFromParent_Done,
     /*   79174 */ // Label 795: @79174
     /*   79174 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(79203), // Rule ID 27625 //
     /*   79179 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79186 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79190 */   // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
     /*   79190 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79193 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79195 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79197 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79202 */   // GIR_Coverage, 27625,
     /*   79202 */   GIR_EraseRootFromParent_Done,
     /*   79203 */ // Label 796: @79203
     /*   79203 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(79232), // Rule ID 27626 //
     /*   79208 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79211 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79215 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79219 */   // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4f32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
     /*   79219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79222 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79224 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79226 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79231 */   // GIR_Coverage, 27626,
     /*   79231 */   GIR_EraseRootFromParent_Done,
     /*   79232 */ // Label 797: @79232
     /*   79232 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(79261), // Rule ID 27627 //
     /*   79237 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   79240 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79244 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79248 */   // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
     /*   79248 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79251 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79253 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79255 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79260 */   // GIR_Coverage, 27627,
     /*   79260 */   GIR_EraseRootFromParent_Done,
     /*   79261 */ // Label 798: @79261
     /*   79261 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(79290), // Rule ID 27628 //
     /*   79266 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   79269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79273 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79277 */   // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
     /*   79277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79280 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79282 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79284 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79289 */   // GIR_Coverage, 27628,
     /*   79289 */   GIR_EraseRootFromParent_Done,
     /*   79290 */ // Label 799: @79290
     /*   79290 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(79319), // Rule ID 27629 //
     /*   79295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79302 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79306 */   // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
     /*   79306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79309 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79311 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79313 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79318 */   // GIR_Coverage, 27629,
     /*   79318 */   GIR_EraseRootFromParent_Done,
     /*   79319 */ // Label 800: @79319
     /*   79319 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(79348), // Rule ID 27630 //
     /*   79324 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79331 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79335 */   // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
     /*   79335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79338 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79340 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79342 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79347 */   // GIR_Coverage, 27630,
     /*   79347 */   GIR_EraseRootFromParent_Done,
     /*   79348 */ // Label 801: @79348
     /*   79348 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(79377), // Rule ID 27631 //
     /*   79353 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79360 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79364 */   // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
     /*   79364 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79367 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79369 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79371 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79376 */   // GIR_Coverage, 27631,
     /*   79376 */   GIR_EraseRootFromParent_Done,
     /*   79377 */ // Label 802: @79377
     /*   79377 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(79406), // Rule ID 27632 //
     /*   79382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79393 */   // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
     /*   79393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79396 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79398 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79400 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79405 */   // GIR_Coverage, 27632,
     /*   79405 */   GIR_EraseRootFromParent_Done,
     /*   79406 */ // Label 803: @79406
     /*   79406 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(79435), // Rule ID 27633 //
     /*   79411 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79418 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79422 */   // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
     /*   79422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79425 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79427 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79429 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79434 */   // GIR_Coverage, 27633,
     /*   79434 */   GIR_EraseRootFromParent_Done,
     /*   79435 */ // Label 804: @79435
     /*   79435 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(79464), // Rule ID 27634 //
     /*   79440 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79443 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79447 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79451 */   // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
     /*   79451 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79454 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79456 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79458 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79463 */   // GIR_Coverage, 27634,
     /*   79463 */   GIR_EraseRootFromParent_Done,
     /*   79464 */ // Label 805: @79464
     /*   79464 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(79493), // Rule ID 27635 //
     /*   79469 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79476 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79480 */   // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
     /*   79480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79483 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79485 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79487 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79492 */   // GIR_Coverage, 27635,
     /*   79492 */   GIR_EraseRootFromParent_Done,
     /*   79493 */ // Label 806: @79493
     /*   79493 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(79522), // Rule ID 27636 //
     /*   79498 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   79501 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79505 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79509 */   // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v4f32] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
     /*   79509 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79512 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79514 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79516 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79521 */   // GIR_Coverage, 27636,
     /*   79521 */   GIR_EraseRootFromParent_Done,
     /*   79522 */ // Label 807: @79522
     /*   79522 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(79551), // Rule ID 27637 //
     /*   79527 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   79530 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79534 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79538 */   // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
     /*   79538 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79541 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79543 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79545 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79550 */   // GIR_Coverage, 27637,
     /*   79550 */   GIR_EraseRootFromParent_Done,
     /*   79551 */ // Label 808: @79551
     /*   79551 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(79580), // Rule ID 27638 //
     /*   79556 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   79559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79563 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79567 */   // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
     /*   79567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79570 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79572 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79574 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79579 */   // GIR_Coverage, 27638,
     /*   79579 */   GIR_EraseRootFromParent_Done,
     /*   79580 */ // Label 809: @79580
     /*   79580 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(79609), // Rule ID 27639 //
     /*   79585 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79592 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79596 */   // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
     /*   79596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79599 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79601 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79603 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79608 */   // GIR_Coverage, 27639,
     /*   79608 */   GIR_EraseRootFromParent_Done,
     /*   79609 */ // Label 810: @79609
     /*   79609 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(79638), // Rule ID 27640 //
     /*   79614 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79617 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79621 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79625 */   // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
     /*   79625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79628 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79630 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79632 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79637 */   // GIR_Coverage, 27640,
     /*   79637 */   GIR_EraseRootFromParent_Done,
     /*   79638 */ // Label 811: @79638
     /*   79638 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(79667), // Rule ID 27641 //
     /*   79643 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79650 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79654 */   // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
     /*   79654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79657 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79659 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79661 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   79666 */   // GIR_Coverage, 27641,
     /*   79666 */   GIR_EraseRootFromParent_Done,
     /*   79667 */ // Label 812: @79667
     /*   79667 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(79696), // Rule ID 27642 //
     /*   79672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   79675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79679 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79683 */   // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
     /*   79683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79686 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79688 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79690 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   79695 */   // GIR_Coverage, 27642,
     /*   79695 */   GIR_EraseRootFromParent_Done,
     /*   79696 */ // Label 813: @79696
     /*   79696 */ GIM_Reject,
     /*   79697 */ // Label 724: @79697
     /*   79697 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(79750),
     /*   79702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s32,
     /*   79705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
     /*   79709 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
     /*   79713 */   GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(79731), // Rule ID 27601 //
     /*   79718 */     // (bitconvert:{ *:[v3i32] } SGPR_96:{ *:[v3f32] }:$src0)  =>  SGPR_96:{ *:[v3i32] }:$src0
     /*   79718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79721 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79723 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79725 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
     /*   79730 */     // GIR_Coverage, 27601,
     /*   79730 */     GIR_EraseRootFromParent_Done,
     /*   79731 */   // Label 815: @79731
     /*   79731 */   GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(79749), // Rule ID 27602 //
     /*   79736 */     // (bitconvert:{ *:[v3f32] } SGPR_96:{ *:[v3i32] }:$src0)  =>  SGPR_96:{ *:[v3f32] }:$src0
     /*   79736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79739 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79741 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79743 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
     /*   79748 */     // GIR_Coverage, 27602,
     /*   79748 */     GIR_EraseRootFromParent_Done,
     /*   79749 */   // Label 816: @79749
     /*   79749 */   GIM_Reject,
     /*   79750 */ // Label 814: @79750
     /*   79750 */ GIM_Reject,
     /*   79751 */ // Label 725: @79751
     /*   79751 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(79780), // Rule ID 27679 //
     /*   79756 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79763 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79767 */   // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v6i32] }:$src0)  =>  VReg_192:{ *:[v3i64] }:$src0
     /*   79767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79770 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79772 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79774 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79779 */   // GIR_Coverage, 27679,
     /*   79779 */   GIR_EraseRootFromParent_Done,
     /*   79780 */ // Label 817: @79780
     /*   79780 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(79809), // Rule ID 27680 //
     /*   79785 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79792 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79796 */   // (bitconvert:{ *:[v3i64] } SReg_192:{ *:[v6i32] }:$src0)  =>  SReg_192:{ *:[v3i64] }:$src0
     /*   79796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79799 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79801 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79803 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79808 */   // GIR_Coverage, 27680,
     /*   79808 */   GIR_EraseRootFromParent_Done,
     /*   79809 */ // Label 818: @79809
     /*   79809 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(79838), // Rule ID 27681 //
     /*   79814 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79821 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79825 */   // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v6f32] }:$src0)  =>  VReg_192:{ *:[v3i64] }:$src0
     /*   79825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79828 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79830 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79832 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79837 */   // GIR_Coverage, 27681,
     /*   79837 */   GIR_EraseRootFromParent_Done,
     /*   79838 */ // Label 819: @79838
     /*   79838 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(79867), // Rule ID 27682 //
     /*   79843 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79850 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79854 */   // (bitconvert:{ *:[v3i64] } SReg_192:{ *:[v6f32] }:$src0)  =>  SReg_192:{ *:[v3i64] }:$src0
     /*   79854 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79857 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79859 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79861 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79866 */   // GIR_Coverage, 27682,
     /*   79866 */   GIR_EraseRootFromParent_Done,
     /*   79867 */ // Label 820: @79867
     /*   79867 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(79896), // Rule ID 27683 //
     /*   79872 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   79875 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79879 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79883 */   // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v3f64] }:$src0)  =>  VReg_192:{ *:[v3i64] }:$src0
     /*   79883 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79886 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79888 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79890 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79895 */   // GIR_Coverage, 27683,
     /*   79895 */   GIR_EraseRootFromParent_Done,
     /*   79896 */ // Label 821: @79896
     /*   79896 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(79925), // Rule ID 27684 //
     /*   79901 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   79904 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79908 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79912 */   // (bitconvert:{ *:[v3i64] } SReg_192:{ *:[v3f64] }:$src0)  =>  SReg_192:{ *:[v3i64] }:$src0
     /*   79912 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79915 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79917 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79919 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79924 */   // GIR_Coverage, 27684,
     /*   79924 */   GIR_EraseRootFromParent_Done,
     /*   79925 */ // Label 822: @79925
     /*   79925 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(79954), // Rule ID 27685 //
     /*   79930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79937 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79941 */   // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v6i32] }:$src0)  =>  VReg_192:{ *:[v3f64] }:$src0
     /*   79941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79944 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79946 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79948 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79953 */   // GIR_Coverage, 27685,
     /*   79953 */   GIR_EraseRootFromParent_Done,
     /*   79954 */ // Label 823: @79954
     /*   79954 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(79983), // Rule ID 27686 //
     /*   79959 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79966 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79970 */   // (bitconvert:{ *:[v3f64] } SReg_192:{ *:[v6i32] }:$src0)  =>  SReg_192:{ *:[v3f64] }:$src0
     /*   79970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   79973 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   79975 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   79977 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   79982 */   // GIR_Coverage, 27686,
     /*   79982 */   GIR_EraseRootFromParent_Done,
     /*   79983 */ // Label 824: @79983
     /*   79983 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(80012), // Rule ID 27687 //
     /*   79988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   79991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79995 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   79999 */   // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v6f32] }:$src0)  =>  VReg_192:{ *:[v3f64] }:$src0
     /*   79999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80002 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80004 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80006 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   80011 */   // GIR_Coverage, 27687,
     /*   80011 */   GIR_EraseRootFromParent_Done,
     /*   80012 */ // Label 825: @80012
     /*   80012 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(80041), // Rule ID 27688 //
     /*   80017 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   80020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   80024 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   80028 */   // (bitconvert:{ *:[v3f64] } SReg_192:{ *:[v6f32] }:$src0)  =>  SReg_192:{ *:[v3f64] }:$src0
     /*   80028 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80031 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80033 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80035 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   80040 */   // GIR_Coverage, 27688,
     /*   80040 */   GIR_EraseRootFromParent_Done,
     /*   80041 */ // Label 826: @80041
     /*   80041 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(80070), // Rule ID 27689 //
     /*   80046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   80049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   80053 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   80057 */   // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v3i64] }:$src0)  =>  VReg_192:{ *:[v3f64] }:$src0
     /*   80057 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80060 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80062 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80064 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   80069 */   // GIR_Coverage, 27689,
     /*   80069 */   GIR_EraseRootFromParent_Done,
     /*   80070 */ // Label 827: @80070
     /*   80070 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(80099), // Rule ID 27690 //
     /*   80075 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   80078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   80082 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   80086 */   // (bitconvert:{ *:[v3f64] } SReg_192:{ *:[v3i64] }:$src0)  =>  SReg_192:{ *:[v3f64] }:$src0
     /*   80086 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80089 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80091 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80093 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   80098 */   // GIR_Coverage, 27690,
     /*   80098 */   GIR_EraseRootFromParent_Done,
     /*   80099 */ // Label 828: @80099
     /*   80099 */ GIM_Reject,
     /*   80100 */ // Label 726: @80100
     /*   80100 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(80129), // Rule ID 27591 //
     /*   80105 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   80108 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80112 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80116 */   // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
     /*   80116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80119 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80121 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80123 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80128 */   // GIR_Coverage, 27591,
     /*   80128 */   GIR_EraseRootFromParent_Done,
     /*   80129 */ // Label 829: @80129
     /*   80129 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(80158), // Rule ID 27592 //
     /*   80134 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   80137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80141 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80145 */   // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
     /*   80145 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80148 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80150 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80152 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80157 */   // GIR_Coverage, 27592,
     /*   80157 */   GIR_EraseRootFromParent_Done,
     /*   80158 */ // Label 830: @80158
     /*   80158 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(80187), // Rule ID 27593 //
     /*   80163 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   80166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80170 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80174 */   // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
     /*   80174 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80177 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80179 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80181 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80186 */   // GIR_Coverage, 27593,
     /*   80186 */   GIR_EraseRootFromParent_Done,
     /*   80187 */ // Label 831: @80187
     /*   80187 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(80216), // Rule ID 27594 //
     /*   80192 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   80195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80199 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80203 */   // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
     /*   80203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80206 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80208 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80210 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80215 */   // GIR_Coverage, 27594,
     /*   80215 */   GIR_EraseRootFromParent_Done,
     /*   80216 */ // Label 832: @80216
     /*   80216 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(80245), // Rule ID 27595 //
     /*   80221 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   80224 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80228 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80232 */   // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
     /*   80232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80235 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80237 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80239 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80244 */   // GIR_Coverage, 27595,
     /*   80244 */   GIR_EraseRootFromParent_Done,
     /*   80245 */ // Label 833: @80245
     /*   80245 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(80274), // Rule ID 27596 //
     /*   80250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   80253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80257 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80261 */   // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
     /*   80261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80264 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80266 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80268 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80273 */   // GIR_Coverage, 27596,
     /*   80273 */   GIR_EraseRootFromParent_Done,
     /*   80274 */ // Label 834: @80274
     /*   80274 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(80303), // Rule ID 27597 //
     /*   80279 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   80282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80286 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80290 */   // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
     /*   80290 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80293 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80295 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80297 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80302 */   // GIR_Coverage, 27597,
     /*   80302 */   GIR_EraseRootFromParent_Done,
     /*   80303 */ // Label 835: @80303
     /*   80303 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(80332), // Rule ID 27598 //
     /*   80308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   80311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80315 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80319 */   // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
     /*   80319 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80322 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80324 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80326 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80331 */   // GIR_Coverage, 27598,
     /*   80331 */   GIR_EraseRootFromParent_Done,
     /*   80332 */ // Label 836: @80332
     /*   80332 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(80361), // Rule ID 27599 //
     /*   80337 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   80340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80344 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80348 */   // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
     /*   80348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80351 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80353 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80355 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80360 */   // GIR_Coverage, 27599,
     /*   80360 */   GIR_EraseRootFromParent_Done,
     /*   80361 */ // Label 837: @80361
     /*   80361 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(80390), // Rule ID 27600 //
     /*   80366 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*   80369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80373 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80377 */   // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
     /*   80377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80380 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80382 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80384 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   80389 */   // GIR_Coverage, 27600,
     /*   80389 */   GIR_EraseRootFromParent_Done,
     /*   80390 */ // Label 838: @80390
     /*   80390 */ GIM_Reject,
     /*   80391 */ // Label 727: @80391
     /*   80391 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(80420), // Rule ID 27603 //
     /*   80396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   80399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80403 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80407 */   // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
     /*   80407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80410 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80412 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80414 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80419 */   // GIR_Coverage, 27603,
     /*   80419 */   GIR_EraseRootFromParent_Done,
     /*   80420 */ // Label 839: @80420
     /*   80420 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(80449), // Rule ID 27604 //
     /*   80425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   80428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80432 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80436 */   // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v4f32] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
     /*   80436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80439 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80441 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80443 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80448 */   // GIR_Coverage, 27604,
     /*   80448 */   GIR_EraseRootFromParent_Done,
     /*   80449 */ // Label 840: @80449
     /*   80449 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(80478), // Rule ID 27605 //
     /*   80454 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80461 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80465 */   // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
     /*   80465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80468 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80470 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80472 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80477 */   // GIR_Coverage, 27605,
     /*   80477 */   GIR_EraseRootFromParent_Done,
     /*   80478 */ // Label 841: @80478
     /*   80478 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(80507), // Rule ID 27606 //
     /*   80483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80490 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80494 */   // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
     /*   80494 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80497 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80499 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80501 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80506 */   // GIR_Coverage, 27606,
     /*   80506 */   GIR_EraseRootFromParent_Done,
     /*   80507 */ // Label 842: @80507
     /*   80507 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(80536), // Rule ID 27607 //
     /*   80512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80519 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80523 */   // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
     /*   80523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80526 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80528 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80530 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80535 */   // GIR_Coverage, 27607,
     /*   80535 */   GIR_EraseRootFromParent_Done,
     /*   80536 */ // Label 843: @80536
     /*   80536 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(80565), // Rule ID 27608 //
     /*   80541 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80544 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80548 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80552 */   // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
     /*   80552 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80555 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80557 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80559 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80564 */   // GIR_Coverage, 27608,
     /*   80564 */   GIR_EraseRootFromParent_Done,
     /*   80565 */ // Label 844: @80565
     /*   80565 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(80594), // Rule ID 27609 //
     /*   80570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80577 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80581 */   // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
     /*   80581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80584 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80586 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80588 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80593 */   // GIR_Coverage, 27609,
     /*   80593 */   GIR_EraseRootFromParent_Done,
     /*   80594 */ // Label 845: @80594
     /*   80594 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(80623), // Rule ID 27610 //
     /*   80599 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80606 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80610 */   // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
     /*   80610 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80613 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80615 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80617 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80622 */   // GIR_Coverage, 27610,
     /*   80622 */   GIR_EraseRootFromParent_Done,
     /*   80623 */ // Label 846: @80623
     /*   80623 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(80652), // Rule ID 27611 //
     /*   80628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80639 */   // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
     /*   80639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80642 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80644 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80646 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80651 */   // GIR_Coverage, 27611,
     /*   80651 */   GIR_EraseRootFromParent_Done,
     /*   80652 */ // Label 847: @80652
     /*   80652 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(80681), // Rule ID 27612 //
     /*   80657 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80660 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80664 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80668 */   // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
     /*   80668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80671 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80673 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80675 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80680 */   // GIR_Coverage, 27612,
     /*   80680 */   GIR_EraseRootFromParent_Done,
     /*   80681 */ // Label 848: @80681
     /*   80681 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(80710), // Rule ID 27613 //
     /*   80686 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   80689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80693 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80697 */   // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
     /*   80697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80700 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80702 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80704 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80709 */   // GIR_Coverage, 27613,
     /*   80709 */   GIR_EraseRootFromParent_Done,
     /*   80710 */ // Label 849: @80710
     /*   80710 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(80739), // Rule ID 27614 //
     /*   80715 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   80718 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80722 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80726 */   // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v4f32] }:$src0
     /*   80726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80729 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80731 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80733 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80738 */   // GIR_Coverage, 27614,
     /*   80738 */   GIR_EraseRootFromParent_Done,
     /*   80739 */ // Label 850: @80739
     /*   80739 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(80768), // Rule ID 27615 //
     /*   80744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80751 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80755 */   // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
     /*   80755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80758 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80760 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80762 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80767 */   // GIR_Coverage, 27615,
     /*   80767 */   GIR_EraseRootFromParent_Done,
     /*   80768 */ // Label 851: @80768
     /*   80768 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(80797), // Rule ID 27616 //
     /*   80773 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80780 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80784 */   // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4f32] }:$src0
     /*   80784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80787 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80789 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80791 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80796 */   // GIR_Coverage, 27616,
     /*   80796 */   GIR_EraseRootFromParent_Done,
     /*   80797 */ // Label 852: @80797
     /*   80797 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(80826), // Rule ID 27617 //
     /*   80802 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80809 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80813 */   // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
     /*   80813 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80816 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80818 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80820 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80825 */   // GIR_Coverage, 27617,
     /*   80825 */   GIR_EraseRootFromParent_Done,
     /*   80826 */ // Label 853: @80826
     /*   80826 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(80855), // Rule ID 27618 //
     /*   80831 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   80834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80838 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80842 */   // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v4f32] }:$src0
     /*   80842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80845 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80847 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80849 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80854 */   // GIR_Coverage, 27618,
     /*   80854 */   GIR_EraseRootFromParent_Done,
     /*   80855 */ // Label 854: @80855
     /*   80855 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(80884), // Rule ID 27619 //
     /*   80860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80871 */   // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
     /*   80871 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80874 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80876 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80878 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80883 */   // GIR_Coverage, 27619,
     /*   80883 */   GIR_EraseRootFromParent_Done,
     /*   80884 */ // Label 855: @80884
     /*   80884 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(80913), // Rule ID 27620 //
     /*   80889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80896 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80900 */   // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v4f32] }:$src0
     /*   80900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80903 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80905 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80907 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80912 */   // GIR_Coverage, 27620,
     /*   80912 */   GIR_EraseRootFromParent_Done,
     /*   80913 */ // Label 856: @80913
     /*   80913 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(80942), // Rule ID 27621 //
     /*   80918 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80925 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80929 */   // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
     /*   80929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80932 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80934 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80936 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   80941 */   // GIR_Coverage, 27621,
     /*   80941 */   GIR_EraseRootFromParent_Done,
     /*   80942 */ // Label 857: @80942
     /*   80942 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(80971), // Rule ID 27622 //
     /*   80947 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   80950 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80954 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80958 */   // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v4f32] }:$src0
     /*   80958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80961 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80963 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80965 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   80970 */   // GIR_Coverage, 27622,
     /*   80970 */   GIR_EraseRootFromParent_Done,
     /*   80971 */ // Label 858: @80971
     /*   80971 */ GIM_Reject,
     /*   80972 */ // Label 728: @80972
     /*   80972 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(81001), // Rule ID 27715 //
     /*   80977 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   80980 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   80984 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   80988 */   // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
     /*   80988 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   80991 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   80993 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   80995 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81000 */   // GIR_Coverage, 27715,
     /*   81000 */   GIR_EraseRootFromParent_Done,
     /*   81001 */ // Label 859: @81001
     /*   81001 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(81030), // Rule ID 27716 //
     /*   81006 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81013 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81017 */   // (bitconvert:{ *:[v4i64] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v4i64] }:$src0
     /*   81017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81020 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81022 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81024 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81029 */   // GIR_Coverage, 27716,
     /*   81029 */   GIR_EraseRootFromParent_Done,
     /*   81030 */ // Label 860: @81030
     /*   81030 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(81059), // Rule ID 27717 //
     /*   81035 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81042 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81046 */   // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
     /*   81046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81049 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81051 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81053 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81058 */   // GIR_Coverage, 27717,
     /*   81058 */   GIR_EraseRootFromParent_Done,
     /*   81059 */ // Label 861: @81059
     /*   81059 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(81088), // Rule ID 27718 //
     /*   81064 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81071 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81075 */   // (bitconvert:{ *:[v4i64] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v4i64] }:$src0
     /*   81075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81078 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81080 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81082 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81087 */   // GIR_Coverage, 27718,
     /*   81087 */   GIR_EraseRootFromParent_Done,
     /*   81088 */ // Label 862: @81088
     /*   81088 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(81117), // Rule ID 27719 //
     /*   81093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   81096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81100 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81104 */   // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
     /*   81104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81107 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81109 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81111 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81116 */   // GIR_Coverage, 27719,
     /*   81116 */   GIR_EraseRootFromParent_Done,
     /*   81117 */ // Label 863: @81117
     /*   81117 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(81146), // Rule ID 27720 //
     /*   81122 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   81125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81129 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81133 */   // (bitconvert:{ *:[v4i64] } SReg_256:{ *:[v4f64] }:$src0)  =>  SReg_256:{ *:[v4i64] }:$src0
     /*   81133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81136 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81138 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81140 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81145 */   // GIR_Coverage, 27720,
     /*   81145 */   GIR_EraseRootFromParent_Done,
     /*   81146 */ // Label 864: @81146
     /*   81146 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(81175), // Rule ID 27721 //
     /*   81151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81162 */   // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
     /*   81162 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81165 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81167 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81169 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81174 */   // GIR_Coverage, 27721,
     /*   81174 */   GIR_EraseRootFromParent_Done,
     /*   81175 */ // Label 865: @81175
     /*   81175 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(81204), // Rule ID 27722 //
     /*   81180 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81187 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81191 */   // (bitconvert:{ *:[v4i64] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v4i64] }:$src0
     /*   81191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81194 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81196 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81198 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81203 */   // GIR_Coverage, 27722,
     /*   81203 */   GIR_EraseRootFromParent_Done,
     /*   81204 */ // Label 866: @81204
     /*   81204 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(81233), // Rule ID 27723 //
     /*   81209 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81216 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81220 */   // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
     /*   81220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81223 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81225 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81227 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81232 */   // GIR_Coverage, 27723,
     /*   81232 */   GIR_EraseRootFromParent_Done,
     /*   81233 */ // Label 867: @81233
     /*   81233 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(81262), // Rule ID 27724 //
     /*   81238 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81245 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81249 */   // (bitconvert:{ *:[v4i64] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v4i64] }:$src0
     /*   81249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81252 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81254 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81256 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81261 */   // GIR_Coverage, 27724,
     /*   81261 */   GIR_EraseRootFromParent_Done,
     /*   81262 */ // Label 868: @81262
     /*   81262 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(81291), // Rule ID 27725 //
     /*   81267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81274 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81278 */   // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
     /*   81278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81281 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81283 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81285 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81290 */   // GIR_Coverage, 27725,
     /*   81290 */   GIR_EraseRootFromParent_Done,
     /*   81291 */ // Label 869: @81291
     /*   81291 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(81320), // Rule ID 27726 //
     /*   81296 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81303 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81307 */   // (bitconvert:{ *:[v4f64] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v4f64] }:$src0
     /*   81307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81310 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81312 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81314 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81319 */   // GIR_Coverage, 27726,
     /*   81319 */   GIR_EraseRootFromParent_Done,
     /*   81320 */ // Label 870: @81320
     /*   81320 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(81349), // Rule ID 27727 //
     /*   81325 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81332 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81336 */   // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
     /*   81336 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81339 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81341 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81343 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81348 */   // GIR_Coverage, 27727,
     /*   81348 */   GIR_EraseRootFromParent_Done,
     /*   81349 */ // Label 871: @81349
     /*   81349 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(81378), // Rule ID 27728 //
     /*   81354 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   81357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81361 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81365 */   // (bitconvert:{ *:[v4f64] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v4f64] }:$src0
     /*   81365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81368 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81370 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81372 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81377 */   // GIR_Coverage, 27728,
     /*   81377 */   GIR_EraseRootFromParent_Done,
     /*   81378 */ // Label 872: @81378
     /*   81378 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(81407), // Rule ID 27729 //
     /*   81383 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   81386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81390 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81394 */   // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
     /*   81394 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81397 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81399 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81401 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81406 */   // GIR_Coverage, 27729,
     /*   81406 */   GIR_EraseRootFromParent_Done,
     /*   81407 */ // Label 873: @81407
     /*   81407 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(81436), // Rule ID 27730 //
     /*   81412 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   81415 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81419 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81423 */   // (bitconvert:{ *:[v4f64] } SReg_256:{ *:[v4i64] }:$src0)  =>  SReg_256:{ *:[v4f64] }:$src0
     /*   81423 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81426 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81428 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81430 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81435 */   // GIR_Coverage, 27730,
     /*   81435 */   GIR_EraseRootFromParent_Done,
     /*   81436 */ // Label 874: @81436
     /*   81436 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(81465), // Rule ID 27731 //
     /*   81441 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81448 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81452 */   // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
     /*   81452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81455 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81457 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81459 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81464 */   // GIR_Coverage, 27731,
     /*   81464 */   GIR_EraseRootFromParent_Done,
     /*   81465 */ // Label 875: @81465
     /*   81465 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(81494), // Rule ID 27732 //
     /*   81470 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81473 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81477 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81481 */   // (bitconvert:{ *:[v4f64] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v4f64] }:$src0
     /*   81481 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81484 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81486 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81488 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81493 */   // GIR_Coverage, 27732,
     /*   81493 */   GIR_EraseRootFromParent_Done,
     /*   81494 */ // Label 876: @81494
     /*   81494 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(81523), // Rule ID 27733 //
     /*   81499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81506 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81510 */   // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
     /*   81510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81513 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81515 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81517 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   81522 */   // GIR_Coverage, 27733,
     /*   81522 */   GIR_EraseRootFromParent_Done,
     /*   81523 */ // Label 877: @81523
     /*   81523 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(81552), // Rule ID 27734 //
     /*   81528 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   81531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81535 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81539 */   // (bitconvert:{ *:[v4f64] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v4f64] }:$src0
     /*   81539 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81542 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81544 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81546 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   81551 */   // GIR_Coverage, 27734,
     /*   81551 */   GIR_EraseRootFromParent_Done,
     /*   81552 */ // Label 878: @81552
     /*   81552 */ GIM_Reject,
     /*   81553 */ // Label 729: @81553
     /*   81553 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(81666),
     /*   81558 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v5s32,
     /*   81561 */   GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(81587), // Rule ID 27663 //
     /*   81566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
     /*   81570 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
     /*   81574 */     // (bitconvert:{ *:[v5i32] } VReg_160:{ *:[v5f32] }:$src0)  =>  VReg_160:{ *:[v5i32] }:$src0
     /*   81574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81577 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81579 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81581 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_160RegClassID),
     /*   81586 */     // GIR_Coverage, 27663,
     /*   81586 */     GIR_EraseRootFromParent_Done,
     /*   81587 */   // Label 880: @81587
     /*   81587 */   GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(81613), // Rule ID 27664 //
     /*   81592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
     /*   81596 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
     /*   81600 */     // (bitconvert:{ *:[v5i32] } SReg_160:{ *:[v5f32] }:$src0)  =>  SReg_160:{ *:[v5i32] }:$src0
     /*   81600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81603 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81605 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81607 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_160RegClassID),
     /*   81612 */     // GIR_Coverage, 27664,
     /*   81612 */     GIR_EraseRootFromParent_Done,
     /*   81613 */   // Label 881: @81613
     /*   81613 */   GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(81639), // Rule ID 27665 //
     /*   81618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
     /*   81622 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
     /*   81626 */     // (bitconvert:{ *:[v5f32] } VReg_160:{ *:[v5i32] }:$src0)  =>  VReg_160:{ *:[v5f32] }:$src0
     /*   81626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81629 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81631 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81633 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_160RegClassID),
     /*   81638 */     // GIR_Coverage, 27665,
     /*   81638 */     GIR_EraseRootFromParent_Done,
     /*   81639 */   // Label 882: @81639
     /*   81639 */   GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(81665), // Rule ID 27666 //
     /*   81644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
     /*   81648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
     /*   81652 */     // (bitconvert:{ *:[v5f32] } SReg_160:{ *:[v5i32] }:$src0)  =>  SReg_160:{ *:[v5f32] }:$src0
     /*   81652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81655 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81657 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81659 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_160RegClassID),
     /*   81664 */     // GIR_Coverage, 27666,
     /*   81664 */     GIR_EraseRootFromParent_Done,
     /*   81665 */   // Label 883: @81665
     /*   81665 */   GIM_Reject,
     /*   81666 */ // Label 879: @81666
     /*   81666 */ GIM_Reject,
     /*   81667 */ // Label 730: @81667
     /*   81667 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(81696), // Rule ID 27667 //
     /*   81672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   81675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81679 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81683 */   // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v6f32] }:$src0)  =>  VReg_192:{ *:[v6i32] }:$src0
     /*   81683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81686 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81688 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81690 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81695 */   // GIR_Coverage, 27667,
     /*   81695 */   GIR_EraseRootFromParent_Done,
     /*   81696 */ // Label 884: @81696
     /*   81696 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(81725), // Rule ID 27668 //
     /*   81701 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   81704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81708 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81712 */   // (bitconvert:{ *:[v6i32] } SReg_192:{ *:[v6f32] }:$src0)  =>  SReg_192:{ *:[v6i32] }:$src0
     /*   81712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81715 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81717 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81719 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81724 */   // GIR_Coverage, 27668,
     /*   81724 */   GIR_EraseRootFromParent_Done,
     /*   81725 */ // Label 885: @81725
     /*   81725 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(81754), // Rule ID 27669 //
     /*   81730 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81737 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81741 */   // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v3i64] }:$src0)  =>  VReg_192:{ *:[v6i32] }:$src0
     /*   81741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81744 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81746 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81748 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81753 */   // GIR_Coverage, 27669,
     /*   81753 */   GIR_EraseRootFromParent_Done,
     /*   81754 */ // Label 886: @81754
     /*   81754 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(81783), // Rule ID 27670 //
     /*   81759 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81762 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81766 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81770 */   // (bitconvert:{ *:[v6i32] } SReg_192:{ *:[v3i64] }:$src0)  =>  SReg_192:{ *:[v6i32] }:$src0
     /*   81770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81773 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81775 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81777 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81782 */   // GIR_Coverage, 27670,
     /*   81782 */   GIR_EraseRootFromParent_Done,
     /*   81783 */ // Label 887: @81783
     /*   81783 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(81812), // Rule ID 27671 //
     /*   81788 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81791 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81795 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81799 */   // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v3f64] }:$src0)  =>  VReg_192:{ *:[v6i32] }:$src0
     /*   81799 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81802 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81804 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81806 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81811 */   // GIR_Coverage, 27671,
     /*   81811 */   GIR_EraseRootFromParent_Done,
     /*   81812 */ // Label 888: @81812
     /*   81812 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(81841), // Rule ID 27672 //
     /*   81817 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81820 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81824 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81828 */   // (bitconvert:{ *:[v6i32] } SReg_192:{ *:[v3f64] }:$src0)  =>  SReg_192:{ *:[v6i32] }:$src0
     /*   81828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81831 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81833 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81835 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81840 */   // GIR_Coverage, 27672,
     /*   81840 */   GIR_EraseRootFromParent_Done,
     /*   81841 */ // Label 889: @81841
     /*   81841 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(81870), // Rule ID 27673 //
     /*   81846 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   81849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81853 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81857 */   // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v6i32] }:$src0)  =>  VReg_192:{ *:[v6f32] }:$src0
     /*   81857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81860 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81862 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81864 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81869 */   // GIR_Coverage, 27673,
     /*   81869 */   GIR_EraseRootFromParent_Done,
     /*   81870 */ // Label 890: @81870
     /*   81870 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(81899), // Rule ID 27674 //
     /*   81875 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32,
     /*   81878 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81882 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81886 */   // (bitconvert:{ *:[v6f32] } SReg_192:{ *:[v6i32] }:$src0)  =>  SReg_192:{ *:[v6f32] }:$src0
     /*   81886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81889 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81891 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81893 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81898 */   // GIR_Coverage, 27674,
     /*   81898 */   GIR_EraseRootFromParent_Done,
     /*   81899 */ // Label 891: @81899
     /*   81899 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(81928), // Rule ID 27675 //
     /*   81904 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81911 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81915 */   // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v3i64] }:$src0)  =>  VReg_192:{ *:[v6f32] }:$src0
     /*   81915 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81918 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81920 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81922 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81927 */   // GIR_Coverage, 27675,
     /*   81927 */   GIR_EraseRootFromParent_Done,
     /*   81928 */ // Label 892: @81928
     /*   81928 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(81957), // Rule ID 27676 //
     /*   81933 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81940 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81944 */   // (bitconvert:{ *:[v6f32] } SReg_192:{ *:[v3i64] }:$src0)  =>  SReg_192:{ *:[v6f32] }:$src0
     /*   81944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81947 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81949 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81951 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81956 */   // GIR_Coverage, 27676,
     /*   81956 */   GIR_EraseRootFromParent_Done,
     /*   81957 */ // Label 893: @81957
     /*   81957 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(81986), // Rule ID 27677 //
     /*   81962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81969 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81973 */   // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v3f64] }:$src0)  =>  VReg_192:{ *:[v6f32] }:$src0
     /*   81973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   81976 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   81978 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   81980 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*   81985 */   // GIR_Coverage, 27677,
     /*   81985 */   GIR_EraseRootFromParent_Done,
     /*   81986 */ // Label 894: @81986
     /*   81986 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(82015), // Rule ID 27678 //
     /*   81991 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64,
     /*   81994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   81998 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   82002 */   // (bitconvert:{ *:[v6f32] } SReg_192:{ *:[v3f64] }:$src0)  =>  SReg_192:{ *:[v6f32] }:$src0
     /*   82002 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82005 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82007 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82009 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
     /*   82014 */   // GIR_Coverage, 27678,
     /*   82014 */   GIR_EraseRootFromParent_Done,
     /*   82015 */ // Label 895: @82015
     /*   82015 */ GIM_Reject,
     /*   82016 */ // Label 731: @82016
     /*   82016 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(82129),
     /*   82021 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v7s32,
     /*   82024 */   GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(82050), // Rule ID 27691 //
     /*   82029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
     /*   82033 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
     /*   82037 */     // (bitconvert:{ *:[v7i32] } VReg_224:{ *:[v7f32] }:$src0)  =>  VReg_224:{ *:[v7i32] }:$src0
     /*   82037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82040 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82042 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82044 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_224RegClassID),
     /*   82049 */     // GIR_Coverage, 27691,
     /*   82049 */     GIR_EraseRootFromParent_Done,
     /*   82050 */   // Label 897: @82050
     /*   82050 */   GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(82076), // Rule ID 27692 //
     /*   82055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
     /*   82059 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
     /*   82063 */     // (bitconvert:{ *:[v7i32] } SReg_224:{ *:[v7f32] }:$src0)  =>  SReg_224:{ *:[v7i32] }:$src0
     /*   82063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82066 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82068 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82070 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_224RegClassID),
     /*   82075 */     // GIR_Coverage, 27692,
     /*   82075 */     GIR_EraseRootFromParent_Done,
     /*   82076 */   // Label 898: @82076
     /*   82076 */   GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(82102), // Rule ID 27693 //
     /*   82081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
     /*   82085 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
     /*   82089 */     // (bitconvert:{ *:[v7f32] } VReg_224:{ *:[v7i32] }:$src0)  =>  VReg_224:{ *:[v7f32] }:$src0
     /*   82089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82092 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82094 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82096 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_224RegClassID),
     /*   82101 */     // GIR_Coverage, 27693,
     /*   82101 */     GIR_EraseRootFromParent_Done,
     /*   82102 */   // Label 899: @82102
     /*   82102 */   GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(82128), // Rule ID 27694 //
     /*   82107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
     /*   82111 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
     /*   82115 */     // (bitconvert:{ *:[v7f32] } SReg_224:{ *:[v7i32] }:$src0)  =>  SReg_224:{ *:[v7f32] }:$src0
     /*   82115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82118 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82120 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82122 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_224RegClassID),
     /*   82127 */     // GIR_Coverage, 27694,
     /*   82127 */     GIR_EraseRootFromParent_Done,
     /*   82128 */   // Label 900: @82128
     /*   82128 */   GIM_Reject,
     /*   82129 */ // Label 896: @82129
     /*   82129 */ GIM_Reject,
     /*   82130 */ // Label 732: @82130
     /*   82130 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(82159), // Rule ID 27643 //
     /*   82135 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82142 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82146 */   // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
     /*   82146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82149 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82151 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82153 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82158 */   // GIR_Coverage, 27643,
     /*   82158 */   GIR_EraseRootFromParent_Done,
     /*   82159 */ // Label 901: @82159
     /*   82159 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(82188), // Rule ID 27644 //
     /*   82164 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82167 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82171 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82175 */   // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
     /*   82175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82178 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82180 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82182 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82187 */   // GIR_Coverage, 27644,
     /*   82187 */   GIR_EraseRootFromParent_Done,
     /*   82188 */ // Label 902: @82188
     /*   82188 */ GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(82217), // Rule ID 27645 //
     /*   82193 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82196 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82200 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82204 */   // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
     /*   82204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82207 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82209 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82211 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82216 */   // GIR_Coverage, 27645,
     /*   82216 */   GIR_EraseRootFromParent_Done,
     /*   82217 */ // Label 903: @82217
     /*   82217 */ GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(82246), // Rule ID 27646 //
     /*   82222 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82229 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82233 */   // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v4f32] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
     /*   82233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82236 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82238 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82240 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82245 */   // GIR_Coverage, 27646,
     /*   82245 */   GIR_EraseRootFromParent_Done,
     /*   82246 */ // Label 904: @82246
     /*   82246 */ GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(82275), // Rule ID 27647 //
     /*   82251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82258 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82262 */   // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
     /*   82262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82265 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82267 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82269 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82274 */   // GIR_Coverage, 27647,
     /*   82274 */   GIR_EraseRootFromParent_Done,
     /*   82275 */ // Label 905: @82275
     /*   82275 */ GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(82304), // Rule ID 27648 //
     /*   82280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82287 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82291 */   // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
     /*   82291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82294 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82296 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82298 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82303 */   // GIR_Coverage, 27648,
     /*   82303 */   GIR_EraseRootFromParent_Done,
     /*   82304 */ // Label 906: @82304
     /*   82304 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(82333), // Rule ID 27649 //
     /*   82309 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82316 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82320 */   // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
     /*   82320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82323 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82325 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82327 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82332 */   // GIR_Coverage, 27649,
     /*   82332 */   GIR_EraseRootFromParent_Done,
     /*   82333 */ // Label 907: @82333
     /*   82333 */ GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(82362), // Rule ID 27650 //
     /*   82338 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82345 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82349 */   // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
     /*   82349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82352 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82354 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82356 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82361 */   // GIR_Coverage, 27650,
     /*   82361 */   GIR_EraseRootFromParent_Done,
     /*   82362 */ // Label 908: @82362
     /*   82362 */ GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(82391), // Rule ID 27651 //
     /*   82367 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   82370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82374 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82378 */   // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
     /*   82378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82381 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82383 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82385 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82390 */   // GIR_Coverage, 27651,
     /*   82390 */   GIR_EraseRootFromParent_Done,
     /*   82391 */ // Label 909: @82391
     /*   82391 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(82420), // Rule ID 27652 //
     /*   82396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   82399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82403 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82407 */   // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
     /*   82407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82410 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82412 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82414 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82419 */   // GIR_Coverage, 27652,
     /*   82419 */   GIR_EraseRootFromParent_Done,
     /*   82420 */ // Label 910: @82420
     /*   82420 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(82449), // Rule ID 27653 //
     /*   82425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82432 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82436 */   // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
     /*   82436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82439 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82441 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82443 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82448 */   // GIR_Coverage, 27653,
     /*   82448 */   GIR_EraseRootFromParent_Done,
     /*   82449 */ // Label 911: @82449
     /*   82449 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(82478), // Rule ID 27654 //
     /*   82454 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82461 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82465 */   // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
     /*   82465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82468 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82470 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82472 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82477 */   // GIR_Coverage, 27654,
     /*   82477 */   GIR_EraseRootFromParent_Done,
     /*   82478 */ // Label 912: @82478
     /*   82478 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(82507), // Rule ID 27655 //
     /*   82483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82490 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82494 */   // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
     /*   82494 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82497 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82499 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82501 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82506 */   // GIR_Coverage, 27655,
     /*   82506 */   GIR_EraseRootFromParent_Done,
     /*   82507 */ // Label 913: @82507
     /*   82507 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(82536), // Rule ID 27656 //
     /*   82512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*   82515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82519 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82523 */   // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v4f32] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
     /*   82523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82526 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82528 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82530 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82535 */   // GIR_Coverage, 27656,
     /*   82535 */   GIR_EraseRootFromParent_Done,
     /*   82536 */ // Label 914: @82536
     /*   82536 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(82565), // Rule ID 27657 //
     /*   82541 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82544 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82548 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82552 */   // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
     /*   82552 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82555 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82557 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82559 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82564 */   // GIR_Coverage, 27657,
     /*   82564 */   GIR_EraseRootFromParent_Done,
     /*   82565 */ // Label 915: @82565
     /*   82565 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(82594), // Rule ID 27658 //
     /*   82570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82577 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82581 */   // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
     /*   82581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82584 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82586 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82588 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82593 */   // GIR_Coverage, 27658,
     /*   82593 */   GIR_EraseRootFromParent_Done,
     /*   82594 */ // Label 916: @82594
     /*   82594 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(82623), // Rule ID 27659 //
     /*   82599 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82606 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82610 */   // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
     /*   82610 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82613 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82615 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82617 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82622 */   // GIR_Coverage, 27659,
     /*   82622 */   GIR_EraseRootFromParent_Done,
     /*   82623 */ // Label 917: @82623
     /*   82623 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(82652), // Rule ID 27660 //
     /*   82628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   82631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82639 */   // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
     /*   82639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82642 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82644 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82646 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82651 */   // GIR_Coverage, 27660,
     /*   82651 */   GIR_EraseRootFromParent_Done,
     /*   82652 */ // Label 918: @82652
     /*   82652 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(82681), // Rule ID 27661 //
     /*   82657 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   82660 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82664 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82668 */   // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
     /*   82668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82671 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82673 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82675 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*   82680 */   // GIR_Coverage, 27661,
     /*   82680 */   GIR_EraseRootFromParent_Done,
     /*   82681 */ // Label 919: @82681
     /*   82681 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(82710), // Rule ID 27662 //
     /*   82686 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*   82689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82693 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82697 */   // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
     /*   82697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82700 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82702 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82704 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*   82709 */   // GIR_Coverage, 27662,
     /*   82709 */   GIR_EraseRootFromParent_Done,
     /*   82710 */ // Label 920: @82710
     /*   82710 */ GIM_Reject,
     /*   82711 */ // Label 733: @82711
     /*   82711 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(82740), // Rule ID 27695 //
     /*   82716 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   82719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82723 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82727 */   // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
     /*   82727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82730 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82732 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82734 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82739 */   // GIR_Coverage, 27695,
     /*   82739 */   GIR_EraseRootFromParent_Done,
     /*   82740 */ // Label 921: @82740
     /*   82740 */ GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(82769), // Rule ID 27696 //
     /*   82745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   82748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82752 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82756 */   // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
     /*   82756 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82759 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82761 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82763 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82768 */   // GIR_Coverage, 27696,
     /*   82768 */   GIR_EraseRootFromParent_Done,
     /*   82769 */ // Label 922: @82769
     /*   82769 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(82798), // Rule ID 27697 //
     /*   82774 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   82777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82781 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82785 */   // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
     /*   82785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82788 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82790 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82792 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82797 */   // GIR_Coverage, 27697,
     /*   82797 */   GIR_EraseRootFromParent_Done,
     /*   82798 */ // Label 923: @82798
     /*   82798 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(82827), // Rule ID 27698 //
     /*   82803 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   82806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82810 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82814 */   // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v4i64] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
     /*   82814 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82817 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82819 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82821 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82826 */   // GIR_Coverage, 27698,
     /*   82826 */   GIR_EraseRootFromParent_Done,
     /*   82827 */ // Label 924: @82827
     /*   82827 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(82856), // Rule ID 27699 //
     /*   82832 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   82835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82839 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82843 */   // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
     /*   82843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82846 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82848 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82850 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82855 */   // GIR_Coverage, 27699,
     /*   82855 */   GIR_EraseRootFromParent_Done,
     /*   82856 */ // Label 925: @82856
     /*   82856 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(82885), // Rule ID 27700 //
     /*   82861 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   82864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82868 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82872 */   // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v4f64] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
     /*   82872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82875 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82877 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82879 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82884 */   // GIR_Coverage, 27700,
     /*   82884 */   GIR_EraseRootFromParent_Done,
     /*   82885 */ // Label 926: @82885
     /*   82885 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(82914), // Rule ID 27701 //
     /*   82890 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   82893 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82897 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82901 */   // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
     /*   82901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82904 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82906 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82908 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82913 */   // GIR_Coverage, 27701,
     /*   82913 */   GIR_EraseRootFromParent_Done,
     /*   82914 */ // Label 927: @82914
     /*   82914 */ GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(82943), // Rule ID 27702 //
     /*   82919 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   82922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82926 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82930 */   // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
     /*   82930 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82933 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82935 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82937 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82942 */   // GIR_Coverage, 27702,
     /*   82942 */   GIR_EraseRootFromParent_Done,
     /*   82943 */ // Label 928: @82943
     /*   82943 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(82972), // Rule ID 27703 //
     /*   82948 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   82951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82955 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82959 */   // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
     /*   82959 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82962 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82964 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82966 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   82971 */   // GIR_Coverage, 27703,
     /*   82971 */   GIR_EraseRootFromParent_Done,
     /*   82972 */ // Label 929: @82972
     /*   82972 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(83001), // Rule ID 27704 //
     /*   82977 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   82980 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82984 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   82988 */   // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
     /*   82988 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   82991 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   82993 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   82995 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83000 */   // GIR_Coverage, 27704,
     /*   83000 */   GIR_EraseRootFromParent_Done,
     /*   83001 */ // Label 930: @83001
     /*   83001 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(83030), // Rule ID 27705 //
     /*   83006 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   83009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83013 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83017 */   // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
     /*   83017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83020 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83022 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83024 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83029 */   // GIR_Coverage, 27705,
     /*   83029 */   GIR_EraseRootFromParent_Done,
     /*   83030 */ // Label 931: @83030
     /*   83030 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(83059), // Rule ID 27706 //
     /*   83035 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   83038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83042 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83046 */   // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
     /*   83046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83049 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83051 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83053 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83058 */   // GIR_Coverage, 27706,
     /*   83058 */   GIR_EraseRootFromParent_Done,
     /*   83059 */ // Label 932: @83059
     /*   83059 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(83088), // Rule ID 27707 //
     /*   83064 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   83067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83071 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83075 */   // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
     /*   83075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83078 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83080 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83082 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83087 */   // GIR_Coverage, 27707,
     /*   83087 */   GIR_EraseRootFromParent_Done,
     /*   83088 */ // Label 933: @83088
     /*   83088 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(83117), // Rule ID 27708 //
     /*   83093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   83096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83100 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83104 */   // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v4i64] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
     /*   83104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83107 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83109 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83111 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83116 */   // GIR_Coverage, 27708,
     /*   83116 */   GIR_EraseRootFromParent_Done,
     /*   83117 */ // Label 934: @83117
     /*   83117 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(83146), // Rule ID 27709 //
     /*   83122 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   83125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83129 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83133 */   // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
     /*   83133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83136 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83138 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83140 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83145 */   // GIR_Coverage, 27709,
     /*   83145 */   GIR_EraseRootFromParent_Done,
     /*   83146 */ // Label 935: @83146
     /*   83146 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(83175), // Rule ID 27710 //
     /*   83151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   83154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83162 */   // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v4f64] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
     /*   83162 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83165 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83167 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83169 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83174 */   // GIR_Coverage, 27710,
     /*   83174 */   GIR_EraseRootFromParent_Done,
     /*   83175 */ // Label 936: @83175
     /*   83175 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(83204), // Rule ID 27711 //
     /*   83180 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   83183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83187 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83191 */   // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
     /*   83191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83194 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83196 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83198 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83203 */   // GIR_Coverage, 27711,
     /*   83203 */   GIR_EraseRootFromParent_Done,
     /*   83204 */ // Label 937: @83204
     /*   83204 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(83233), // Rule ID 27712 //
     /*   83209 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   83212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83216 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83220 */   // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
     /*   83220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83223 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83225 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83227 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83232 */   // GIR_Coverage, 27712,
     /*   83232 */   GIR_EraseRootFromParent_Done,
     /*   83233 */ // Label 938: @83233
     /*   83233 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(83262), // Rule ID 27713 //
     /*   83238 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   83241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83245 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83249 */   // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
     /*   83249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83252 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83254 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83256 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   83261 */   // GIR_Coverage, 27713,
     /*   83261 */   GIR_EraseRootFromParent_Done,
     /*   83262 */ // Label 939: @83262
     /*   83262 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(83291), // Rule ID 27714 //
     /*   83267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   83270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83274 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83278 */   // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
     /*   83278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83281 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83283 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83285 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   83290 */   // GIR_Coverage, 27714,
     /*   83290 */   GIR_EraseRootFromParent_Done,
     /*   83291 */ // Label 940: @83291
     /*   83291 */ GIM_Reject,
     /*   83292 */ // Label 734: @83292
     /*   83292 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(83321), // Rule ID 27791 //
     /*   83297 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83304 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83308 */   // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
     /*   83308 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83311 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83313 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83315 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83320 */   // GIR_Coverage, 27791,
     /*   83320 */   GIR_EraseRootFromParent_Done,
     /*   83321 */ // Label 941: @83321
     /*   83321 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(83350), // Rule ID 27792 //
     /*   83326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83333 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83337 */   // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v16i32] }:$src0)  =>  SReg_512:{ *:[v8i64] }:$src0
     /*   83337 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83340 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83342 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83344 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83349 */   // GIR_Coverage, 27792,
     /*   83349 */   GIR_EraseRootFromParent_Done,
     /*   83350 */ // Label 942: @83350
     /*   83350 */ GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(83379), // Rule ID 27793 //
     /*   83355 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83362 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83366 */   // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
     /*   83366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83369 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83371 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83373 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83378 */   // GIR_Coverage, 27793,
     /*   83378 */   GIR_EraseRootFromParent_Done,
     /*   83379 */ // Label 943: @83379
     /*   83379 */ GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(83408), // Rule ID 27794 //
     /*   83384 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83391 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83395 */   // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v16f32] }:$src0)  =>  SReg_512:{ *:[v8i64] }:$src0
     /*   83395 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83398 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83400 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83402 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83407 */   // GIR_Coverage, 27794,
     /*   83407 */   GIR_EraseRootFromParent_Done,
     /*   83408 */ // Label 944: @83408
     /*   83408 */ GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(83437), // Rule ID 27795 //
     /*   83413 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   83416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83420 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83424 */   // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
     /*   83424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83427 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83429 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83431 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83436 */   // GIR_Coverage, 27795,
     /*   83436 */   GIR_EraseRootFromParent_Done,
     /*   83437 */ // Label 945: @83437
     /*   83437 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(83466), // Rule ID 27796 //
     /*   83442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   83445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83449 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83453 */   // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v8f64] }:$src0)  =>  SReg_512:{ *:[v8i64] }:$src0
     /*   83453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83456 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83458 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83460 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83465 */   // GIR_Coverage, 27796,
     /*   83465 */   GIR_EraseRootFromParent_Done,
     /*   83466 */ // Label 946: @83466
     /*   83466 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(83495), // Rule ID 27797 //
     /*   83471 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83478 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83482 */   // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
     /*   83482 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83485 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83487 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83489 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83494 */   // GIR_Coverage, 27797,
     /*   83494 */   GIR_EraseRootFromParent_Done,
     /*   83495 */ // Label 947: @83495
     /*   83495 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(83524), // Rule ID 27798 //
     /*   83500 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83507 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83511 */   // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v32i16] }:$src0)  =>  SReg_512:{ *:[v8i64] }:$src0
     /*   83511 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83514 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83516 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83518 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83523 */   // GIR_Coverage, 27798,
     /*   83523 */   GIR_EraseRootFromParent_Done,
     /*   83524 */ // Label 948: @83524
     /*   83524 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(83553), // Rule ID 27799 //
     /*   83529 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83532 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83536 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83540 */   // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
     /*   83540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83543 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83545 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83547 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83552 */   // GIR_Coverage, 27799,
     /*   83552 */   GIR_EraseRootFromParent_Done,
     /*   83553 */ // Label 949: @83553
     /*   83553 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(83582), // Rule ID 27800 //
     /*   83558 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83565 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83569 */   // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v32f16] }:$src0)  =>  SReg_512:{ *:[v8i64] }:$src0
     /*   83569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83572 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83574 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83576 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83581 */   // GIR_Coverage, 27800,
     /*   83581 */   GIR_EraseRootFromParent_Done,
     /*   83582 */ // Label 950: @83582
     /*   83582 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(83611), // Rule ID 27801 //
     /*   83587 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83590 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83594 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83598 */   // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
     /*   83598 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83601 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83603 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83605 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83610 */   // GIR_Coverage, 27801,
     /*   83610 */   GIR_EraseRootFromParent_Done,
     /*   83611 */ // Label 951: @83611
     /*   83611 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(83640), // Rule ID 27802 //
     /*   83616 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83623 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83627 */   // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v16i32] }:$src0)  =>  SReg_512:{ *:[v8f64] }:$src0
     /*   83627 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83630 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83632 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83634 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83639 */   // GIR_Coverage, 27802,
     /*   83639 */   GIR_EraseRootFromParent_Done,
     /*   83640 */ // Label 952: @83640
     /*   83640 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(83669), // Rule ID 27803 //
     /*   83645 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83648 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83652 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83656 */   // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
     /*   83656 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83659 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83661 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83663 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83668 */   // GIR_Coverage, 27803,
     /*   83668 */   GIR_EraseRootFromParent_Done,
     /*   83669 */ // Label 953: @83669
     /*   83669 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(83698), // Rule ID 27804 //
     /*   83674 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   83677 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83681 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83685 */   // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v16f32] }:$src0)  =>  SReg_512:{ *:[v8f64] }:$src0
     /*   83685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83688 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83690 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83692 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83697 */   // GIR_Coverage, 27804,
     /*   83697 */   GIR_EraseRootFromParent_Done,
     /*   83698 */ // Label 954: @83698
     /*   83698 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(83727), // Rule ID 27805 //
     /*   83703 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   83706 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83710 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83714 */   // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
     /*   83714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83717 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83719 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83721 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83726 */   // GIR_Coverage, 27805,
     /*   83726 */   GIR_EraseRootFromParent_Done,
     /*   83727 */ // Label 955: @83727
     /*   83727 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(83756), // Rule ID 27806 //
     /*   83732 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   83735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83739 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83743 */   // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v8i64] }:$src0)  =>  SReg_512:{ *:[v8f64] }:$src0
     /*   83743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83746 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83748 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83750 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83755 */   // GIR_Coverage, 27806,
     /*   83755 */   GIR_EraseRootFromParent_Done,
     /*   83756 */ // Label 956: @83756
     /*   83756 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(83785), // Rule ID 27807 //
     /*   83761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83768 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83772 */   // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
     /*   83772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83775 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83777 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83779 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83784 */   // GIR_Coverage, 27807,
     /*   83784 */   GIR_EraseRootFromParent_Done,
     /*   83785 */ // Label 957: @83785
     /*   83785 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(83814), // Rule ID 27808 //
     /*   83790 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83797 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83801 */   // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v32i16] }:$src0)  =>  SReg_512:{ *:[v8f64] }:$src0
     /*   83801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83804 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83806 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83808 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83813 */   // GIR_Coverage, 27808,
     /*   83813 */   GIR_EraseRootFromParent_Done,
     /*   83814 */ // Label 958: @83814
     /*   83814 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(83843), // Rule ID 27809 //
     /*   83819 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83826 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83830 */   // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
     /*   83830 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83833 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83835 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83837 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   83842 */   // GIR_Coverage, 27809,
     /*   83842 */   GIR_EraseRootFromParent_Done,
     /*   83843 */ // Label 959: @83843
     /*   83843 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(83872), // Rule ID 27810 //
     /*   83848 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   83851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83855 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83859 */   // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v32f16] }:$src0)  =>  SReg_512:{ *:[v8f64] }:$src0
     /*   83859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83862 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83864 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83866 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   83871 */   // GIR_Coverage, 27810,
     /*   83871 */   GIR_EraseRootFromParent_Done,
     /*   83872 */ // Label 960: @83872
     /*   83872 */ GIM_Reject,
     /*   83873 */ // Label 735: @83873
     /*   83873 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(83986),
     /*   83878 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v9s32,
     /*   83881 */   GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(83907), // Rule ID 27755 //
     /*   83886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
     /*   83890 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
     /*   83894 */     // (bitconvert:{ *:[v9i32] } VReg_288:{ *:[v9f32] }:$src0)  =>  VReg_288:{ *:[v9i32] }:$src0
     /*   83894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83897 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83899 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83901 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_288RegClassID),
     /*   83906 */     // GIR_Coverage, 27755,
     /*   83906 */     GIR_EraseRootFromParent_Done,
     /*   83907 */   // Label 962: @83907
     /*   83907 */   GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(83933), // Rule ID 27756 //
     /*   83912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
     /*   83916 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
     /*   83920 */     // (bitconvert:{ *:[v9i32] } SReg_288:{ *:[v9f32] }:$src0)  =>  SReg_288:{ *:[v9i32] }:$src0
     /*   83920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83923 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83925 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83927 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_288RegClassID),
     /*   83932 */     // GIR_Coverage, 27756,
     /*   83932 */     GIR_EraseRootFromParent_Done,
     /*   83933 */   // Label 963: @83933
     /*   83933 */   GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(83959), // Rule ID 27757 //
     /*   83938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
     /*   83942 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
     /*   83946 */     // (bitconvert:{ *:[v9f32] } VReg_288:{ *:[v9i32] }:$src0)  =>  VReg_288:{ *:[v9f32] }:$src0
     /*   83946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83949 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83951 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83953 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_288RegClassID),
     /*   83958 */     // GIR_Coverage, 27757,
     /*   83958 */     GIR_EraseRootFromParent_Done,
     /*   83959 */   // Label 964: @83959
     /*   83959 */   GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(83985), // Rule ID 27758 //
     /*   83964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
     /*   83968 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
     /*   83972 */     // (bitconvert:{ *:[v9f32] } SReg_288:{ *:[v9i32] }:$src0)  =>  SReg_288:{ *:[v9f32] }:$src0
     /*   83972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   83975 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   83977 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   83979 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_288RegClassID),
     /*   83984 */     // GIR_Coverage, 27758,
     /*   83984 */     GIR_EraseRootFromParent_Done,
     /*   83985 */   // Label 965: @83985
     /*   83985 */   GIM_Reject,
     /*   83986 */ // Label 961: @83986
     /*   83986 */ GIM_Reject,
     /*   83987 */ // Label 736: @83987
     /*   83987 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(84100),
     /*   83992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v10s32,
     /*   83995 */   GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(84021), // Rule ID 27759 //
     /*   84000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
     /*   84004 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
     /*   84008 */     // (bitconvert:{ *:[v10i32] } VReg_320:{ *:[v10f32] }:$src0)  =>  VReg_320:{ *:[v10i32] }:$src0
     /*   84008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84011 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84013 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84015 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_320RegClassID),
     /*   84020 */     // GIR_Coverage, 27759,
     /*   84020 */     GIR_EraseRootFromParent_Done,
     /*   84021 */   // Label 967: @84021
     /*   84021 */   GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(84047), // Rule ID 27760 //
     /*   84026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
     /*   84030 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
     /*   84034 */     // (bitconvert:{ *:[v10i32] } SReg_320:{ *:[v10f32] }:$src0)  =>  SReg_320:{ *:[v10i32] }:$src0
     /*   84034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84037 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84039 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84041 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_320RegClassID),
     /*   84046 */     // GIR_Coverage, 27760,
     /*   84046 */     GIR_EraseRootFromParent_Done,
     /*   84047 */   // Label 968: @84047
     /*   84047 */   GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(84073), // Rule ID 27761 //
     /*   84052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
     /*   84056 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
     /*   84060 */     // (bitconvert:{ *:[v10f32] } VReg_320:{ *:[v10i32] }:$src0)  =>  VReg_320:{ *:[v10f32] }:$src0
     /*   84060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84063 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84065 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84067 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_320RegClassID),
     /*   84072 */     // GIR_Coverage, 27761,
     /*   84072 */     GIR_EraseRootFromParent_Done,
     /*   84073 */   // Label 969: @84073
     /*   84073 */   GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(84099), // Rule ID 27762 //
     /*   84078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
     /*   84082 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
     /*   84086 */     // (bitconvert:{ *:[v10f32] } SReg_320:{ *:[v10i32] }:$src0)  =>  SReg_320:{ *:[v10f32] }:$src0
     /*   84086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84089 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84091 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84093 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_320RegClassID),
     /*   84098 */     // GIR_Coverage, 27762,
     /*   84098 */     GIR_EraseRootFromParent_Done,
     /*   84099 */   // Label 970: @84099
     /*   84099 */   GIM_Reject,
     /*   84100 */ // Label 966: @84100
     /*   84100 */ GIM_Reject,
     /*   84101 */ // Label 737: @84101
     /*   84101 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(84214),
     /*   84106 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v11s32,
     /*   84109 */   GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(84135), // Rule ID 27763 //
     /*   84114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
     /*   84118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
     /*   84122 */     // (bitconvert:{ *:[v11i32] } VReg_352:{ *:[v11f32] }:$src0)  =>  VReg_352:{ *:[v11i32] }:$src0
     /*   84122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84125 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84127 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84129 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_352RegClassID),
     /*   84134 */     // GIR_Coverage, 27763,
     /*   84134 */     GIR_EraseRootFromParent_Done,
     /*   84135 */   // Label 972: @84135
     /*   84135 */   GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(84161), // Rule ID 27764 //
     /*   84140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
     /*   84144 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
     /*   84148 */     // (bitconvert:{ *:[v11i32] } SReg_352:{ *:[v11f32] }:$src0)  =>  SReg_352:{ *:[v11i32] }:$src0
     /*   84148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84151 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84153 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84155 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_352RegClassID),
     /*   84160 */     // GIR_Coverage, 27764,
     /*   84160 */     GIR_EraseRootFromParent_Done,
     /*   84161 */   // Label 973: @84161
     /*   84161 */   GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(84187), // Rule ID 27765 //
     /*   84166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
     /*   84170 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
     /*   84174 */     // (bitconvert:{ *:[v11f32] } VReg_352:{ *:[v11i32] }:$src0)  =>  VReg_352:{ *:[v11f32] }:$src0
     /*   84174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84177 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84179 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84181 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_352RegClassID),
     /*   84186 */     // GIR_Coverage, 27765,
     /*   84186 */     GIR_EraseRootFromParent_Done,
     /*   84187 */   // Label 974: @84187
     /*   84187 */   GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(84213), // Rule ID 27766 //
     /*   84192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
     /*   84196 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
     /*   84200 */     // (bitconvert:{ *:[v11f32] } SReg_352:{ *:[v11i32] }:$src0)  =>  SReg_352:{ *:[v11f32] }:$src0
     /*   84200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84203 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84205 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84207 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_352RegClassID),
     /*   84212 */     // GIR_Coverage, 27766,
     /*   84212 */     GIR_EraseRootFromParent_Done,
     /*   84213 */   // Label 975: @84213
     /*   84213 */   GIM_Reject,
     /*   84214 */ // Label 971: @84214
     /*   84214 */ GIM_Reject,
     /*   84215 */ // Label 738: @84215
     /*   84215 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(84328),
     /*   84220 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v12s32,
     /*   84223 */   GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(84249), // Rule ID 27767 //
     /*   84228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
     /*   84232 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
     /*   84236 */     // (bitconvert:{ *:[v12i32] } VReg_384:{ *:[v12f32] }:$src0)  =>  VReg_384:{ *:[v12i32] }:$src0
     /*   84236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84239 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84241 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84243 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_384RegClassID),
     /*   84248 */     // GIR_Coverage, 27767,
     /*   84248 */     GIR_EraseRootFromParent_Done,
     /*   84249 */   // Label 977: @84249
     /*   84249 */   GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(84275), // Rule ID 27768 //
     /*   84254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
     /*   84258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
     /*   84262 */     // (bitconvert:{ *:[v12i32] } SReg_384:{ *:[v12f32] }:$src0)  =>  SReg_384:{ *:[v12i32] }:$src0
     /*   84262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84265 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84267 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84269 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_384RegClassID),
     /*   84274 */     // GIR_Coverage, 27768,
     /*   84274 */     GIR_EraseRootFromParent_Done,
     /*   84275 */   // Label 978: @84275
     /*   84275 */   GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(84301), // Rule ID 27769 //
     /*   84280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
     /*   84284 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
     /*   84288 */     // (bitconvert:{ *:[v12f32] } VReg_384:{ *:[v12i32] }:$src0)  =>  VReg_384:{ *:[v12f32] }:$src0
     /*   84288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84291 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84293 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84295 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_384RegClassID),
     /*   84300 */     // GIR_Coverage, 27769,
     /*   84300 */     GIR_EraseRootFromParent_Done,
     /*   84301 */   // Label 979: @84301
     /*   84301 */   GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(84327), // Rule ID 27770 //
     /*   84306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
     /*   84310 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
     /*   84314 */     // (bitconvert:{ *:[v12f32] } SReg_384:{ *:[v12i32] }:$src0)  =>  SReg_384:{ *:[v12f32] }:$src0
     /*   84314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84317 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84319 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84321 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_384RegClassID),
     /*   84326 */     // GIR_Coverage, 27770,
     /*   84326 */     GIR_EraseRootFromParent_Done,
     /*   84327 */   // Label 980: @84327
     /*   84327 */   GIM_Reject,
     /*   84328 */ // Label 976: @84328
     /*   84328 */ GIM_Reject,
     /*   84329 */ // Label 739: @84329
     /*   84329 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(84358), // Rule ID 27735 //
     /*   84334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84341 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84345 */   // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
     /*   84345 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84348 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84350 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84352 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84357 */   // GIR_Coverage, 27735,
     /*   84357 */   GIR_EraseRootFromParent_Done,
     /*   84358 */ // Label 981: @84358
     /*   84358 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(84387), // Rule ID 27736 //
     /*   84363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84370 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84374 */   // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
     /*   84374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84377 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84379 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84381 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84386 */   // GIR_Coverage, 27736,
     /*   84386 */   GIR_EraseRootFromParent_Done,
     /*   84387 */ // Label 982: @84387
     /*   84387 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(84416), // Rule ID 27737 //
     /*   84392 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84399 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84403 */   // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
     /*   84403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84406 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84408 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84410 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84415 */   // GIR_Coverage, 27737,
     /*   84415 */   GIR_EraseRootFromParent_Done,
     /*   84416 */ // Label 983: @84416
     /*   84416 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(84445), // Rule ID 27738 //
     /*   84421 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84428 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84432 */   // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
     /*   84432 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84435 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84437 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84439 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84444 */   // GIR_Coverage, 27738,
     /*   84444 */   GIR_EraseRootFromParent_Done,
     /*   84445 */ // Label 984: @84445
     /*   84445 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(84474), // Rule ID 27739 //
     /*   84450 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84453 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84457 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84461 */   // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
     /*   84461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84464 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84466 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84468 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84473 */   // GIR_Coverage, 27739,
     /*   84473 */   GIR_EraseRootFromParent_Done,
     /*   84474 */ // Label 985: @84474
     /*   84474 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(84503), // Rule ID 27740 //
     /*   84479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84486 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84490 */   // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v4i64] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
     /*   84490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84493 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84495 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84497 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84502 */   // GIR_Coverage, 27740,
     /*   84502 */   GIR_EraseRootFromParent_Done,
     /*   84503 */ // Label 986: @84503
     /*   84503 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(84532), // Rule ID 27741 //
     /*   84508 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84511 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84515 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84519 */   // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
     /*   84519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84522 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84524 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84526 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84531 */   // GIR_Coverage, 27741,
     /*   84531 */   GIR_EraseRootFromParent_Done,
     /*   84532 */ // Label 987: @84532
     /*   84532 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(84561), // Rule ID 27742 //
     /*   84537 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84540 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84544 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84548 */   // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v4f64] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
     /*   84548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84551 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84553 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84555 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84560 */   // GIR_Coverage, 27742,
     /*   84560 */   GIR_EraseRootFromParent_Done,
     /*   84561 */ // Label 988: @84561
     /*   84561 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(84590), // Rule ID 27743 //
     /*   84566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   84569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84573 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84577 */   // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
     /*   84577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84580 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84582 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84584 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84589 */   // GIR_Coverage, 27743,
     /*   84589 */   GIR_EraseRootFromParent_Done,
     /*   84590 */ // Label 989: @84590
     /*   84590 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(84619), // Rule ID 27744 //
     /*   84595 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   84598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84602 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84606 */   // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
     /*   84606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84609 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84611 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84613 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84618 */   // GIR_Coverage, 27744,
     /*   84618 */   GIR_EraseRootFromParent_Done,
     /*   84619 */ // Label 990: @84619
     /*   84619 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(84648), // Rule ID 27745 //
     /*   84624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84631 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84635 */   // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
     /*   84635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84638 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84640 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84642 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84647 */   // GIR_Coverage, 27745,
     /*   84647 */   GIR_EraseRootFromParent_Done,
     /*   84648 */ // Label 991: @84648
     /*   84648 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(84677), // Rule ID 27746 //
     /*   84653 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84660 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84664 */   // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
     /*   84664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84667 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84669 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84671 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84676 */   // GIR_Coverage, 27746,
     /*   84676 */   GIR_EraseRootFromParent_Done,
     /*   84677 */ // Label 992: @84677
     /*   84677 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(84706), // Rule ID 27747 //
     /*   84682 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84689 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84693 */   // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
     /*   84693 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84696 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84698 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84700 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84705 */   // GIR_Coverage, 27747,
     /*   84705 */   GIR_EraseRootFromParent_Done,
     /*   84706 */ // Label 993: @84706
     /*   84706 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(84735), // Rule ID 27748 //
     /*   84711 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32,
     /*   84714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84718 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84722 */   // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
     /*   84722 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84725 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84727 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84729 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84734 */   // GIR_Coverage, 27748,
     /*   84734 */   GIR_EraseRootFromParent_Done,
     /*   84735 */ // Label 994: @84735
     /*   84735 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(84764), // Rule ID 27749 //
     /*   84740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84747 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84751 */   // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
     /*   84751 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84754 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84756 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84758 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84763 */   // GIR_Coverage, 27749,
     /*   84763 */   GIR_EraseRootFromParent_Done,
     /*   84764 */ // Label 995: @84764
     /*   84764 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(84793), // Rule ID 27750 //
     /*   84769 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84776 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84780 */   // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v4i64] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
     /*   84780 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84783 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84785 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84787 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84792 */   // GIR_Coverage, 27750,
     /*   84792 */   GIR_EraseRootFromParent_Done,
     /*   84793 */ // Label 996: @84793
     /*   84793 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(84822), // Rule ID 27751 //
     /*   84798 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84801 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84805 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84809 */   // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
     /*   84809 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84812 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84814 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84816 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84821 */   // GIR_Coverage, 27751,
     /*   84821 */   GIR_EraseRootFromParent_Done,
     /*   84822 */ // Label 997: @84822
     /*   84822 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(84851), // Rule ID 27752 //
     /*   84827 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64,
     /*   84830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84834 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84838 */   // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v4f64] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
     /*   84838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84841 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84843 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84845 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84850 */   // GIR_Coverage, 27752,
     /*   84850 */   GIR_EraseRootFromParent_Done,
     /*   84851 */ // Label 998: @84851
     /*   84851 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(84880), // Rule ID 27753 //
     /*   84856 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   84859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84863 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84867 */   // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
     /*   84867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84870 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84872 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84874 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*   84879 */   // GIR_Coverage, 27753,
     /*   84879 */   GIR_EraseRootFromParent_Done,
     /*   84880 */ // Label 999: @84880
     /*   84880 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(84909), // Rule ID 27754 //
     /*   84885 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16,
     /*   84888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84892 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84896 */   // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
     /*   84896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84899 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84901 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84903 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*   84908 */   // GIR_Coverage, 27754,
     /*   84908 */   GIR_EraseRootFromParent_Done,
     /*   84909 */ // Label 1000: @84909
     /*   84909 */ GIM_Reject,
     /*   84910 */ // Label 740: @84910
     /*   84910 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(84939), // Rule ID 27771 //
     /*   84915 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   84918 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   84922 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   84926 */   // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
     /*   84926 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84929 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84931 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84933 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   84938 */   // GIR_Coverage, 27771,
     /*   84938 */   GIR_EraseRootFromParent_Done,
     /*   84939 */ // Label 1001: @84939
     /*   84939 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(84968), // Rule ID 27772 //
     /*   84944 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   84947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   84951 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   84955 */   // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v16f32] }:$src0)  =>  SReg_512:{ *:[v16i32] }:$src0
     /*   84955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84958 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84960 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84962 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   84967 */   // GIR_Coverage, 27772,
     /*   84967 */   GIR_EraseRootFromParent_Done,
     /*   84968 */ // Label 1002: @84968
     /*   84968 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(84997), // Rule ID 27773 //
     /*   84973 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   84976 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   84980 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   84984 */   // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
     /*   84984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   84987 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   84989 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   84991 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   84996 */   // GIR_Coverage, 27773,
     /*   84996 */   GIR_EraseRootFromParent_Done,
     /*   84997 */ // Label 1003: @84997
     /*   84997 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(85026), // Rule ID 27774 //
     /*   85002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85005 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85009 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85013 */   // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v8i64] }:$src0)  =>  SReg_512:{ *:[v16i32] }:$src0
     /*   85013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85016 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85018 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85020 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85025 */   // GIR_Coverage, 27774,
     /*   85025 */   GIR_EraseRootFromParent_Done,
     /*   85026 */ // Label 1004: @85026
     /*   85026 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(85055), // Rule ID 27775 //
     /*   85031 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85034 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85038 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85042 */   // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
     /*   85042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85045 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85047 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85049 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85054 */   // GIR_Coverage, 27775,
     /*   85054 */   GIR_EraseRootFromParent_Done,
     /*   85055 */ // Label 1005: @85055
     /*   85055 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(85084), // Rule ID 27776 //
     /*   85060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85067 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85071 */   // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v8f64] }:$src0)  =>  SReg_512:{ *:[v16i32] }:$src0
     /*   85071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85074 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85076 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85078 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85083 */   // GIR_Coverage, 27776,
     /*   85083 */   GIR_EraseRootFromParent_Done,
     /*   85084 */ // Label 1006: @85084
     /*   85084 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(85113), // Rule ID 27777 //
     /*   85089 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85092 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85096 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85100 */   // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
     /*   85100 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85103 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85105 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85107 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85112 */   // GIR_Coverage, 27777,
     /*   85112 */   GIR_EraseRootFromParent_Done,
     /*   85113 */ // Label 1007: @85113
     /*   85113 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(85142), // Rule ID 27778 //
     /*   85118 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85125 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85129 */   // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v32i16] }:$src0)  =>  SReg_512:{ *:[v16i32] }:$src0
     /*   85129 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85132 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85134 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85136 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85141 */   // GIR_Coverage, 27778,
     /*   85141 */   GIR_EraseRootFromParent_Done,
     /*   85142 */ // Label 1008: @85142
     /*   85142 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(85171), // Rule ID 27779 //
     /*   85147 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85150 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85154 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85158 */   // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
     /*   85158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85161 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85163 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85165 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85170 */   // GIR_Coverage, 27779,
     /*   85170 */   GIR_EraseRootFromParent_Done,
     /*   85171 */ // Label 1009: @85171
     /*   85171 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(85200), // Rule ID 27780 //
     /*   85176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85183 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85187 */   // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v32f16] }:$src0)  =>  SReg_512:{ *:[v16i32] }:$src0
     /*   85187 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85190 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85192 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85194 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85199 */   // GIR_Coverage, 27780,
     /*   85199 */   GIR_EraseRootFromParent_Done,
     /*   85200 */ // Label 1010: @85200
     /*   85200 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(85229), // Rule ID 27781 //
     /*   85205 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   85208 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85212 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85216 */   // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
     /*   85216 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85219 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85221 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85223 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85228 */   // GIR_Coverage, 27781,
     /*   85228 */   GIR_EraseRootFromParent_Done,
     /*   85229 */ // Label 1011: @85229
     /*   85229 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(85258), // Rule ID 27782 //
     /*   85234 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   85237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85241 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85245 */   // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v16i32] }:$src0)  =>  SReg_512:{ *:[v16f32] }:$src0
     /*   85245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85248 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85250 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85252 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85257 */   // GIR_Coverage, 27782,
     /*   85257 */   GIR_EraseRootFromParent_Done,
     /*   85258 */ // Label 1012: @85258
     /*   85258 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(85287), // Rule ID 27783 //
     /*   85263 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85270 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85274 */   // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
     /*   85274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85277 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85279 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85281 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85286 */   // GIR_Coverage, 27783,
     /*   85286 */   GIR_EraseRootFromParent_Done,
     /*   85287 */ // Label 1013: @85287
     /*   85287 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(85316), // Rule ID 27784 //
     /*   85292 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85295 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85299 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85303 */   // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v8i64] }:$src0)  =>  SReg_512:{ *:[v16f32] }:$src0
     /*   85303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85306 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85308 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85310 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85315 */   // GIR_Coverage, 27784,
     /*   85315 */   GIR_EraseRootFromParent_Done,
     /*   85316 */ // Label 1014: @85316
     /*   85316 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(85345), // Rule ID 27785 //
     /*   85321 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85328 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85332 */   // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
     /*   85332 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85335 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85337 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85339 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85344 */   // GIR_Coverage, 27785,
     /*   85344 */   GIR_EraseRootFromParent_Done,
     /*   85345 */ // Label 1015: @85345
     /*   85345 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(85374), // Rule ID 27786 //
     /*   85350 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85353 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85357 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85361 */   // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v8f64] }:$src0)  =>  SReg_512:{ *:[v16f32] }:$src0
     /*   85361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85364 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85366 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85368 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85373 */   // GIR_Coverage, 27786,
     /*   85373 */   GIR_EraseRootFromParent_Done,
     /*   85374 */ // Label 1016: @85374
     /*   85374 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(85403), // Rule ID 27787 //
     /*   85379 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85382 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85386 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85390 */   // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
     /*   85390 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85393 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85395 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85397 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85402 */   // GIR_Coverage, 27787,
     /*   85402 */   GIR_EraseRootFromParent_Done,
     /*   85403 */ // Label 1017: @85403
     /*   85403 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(85432), // Rule ID 27788 //
     /*   85408 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85415 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85419 */   // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v32i16] }:$src0)  =>  SReg_512:{ *:[v16f32] }:$src0
     /*   85419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85422 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85424 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85426 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85431 */   // GIR_Coverage, 27788,
     /*   85431 */   GIR_EraseRootFromParent_Done,
     /*   85432 */ // Label 1018: @85432
     /*   85432 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(85461), // Rule ID 27789 //
     /*   85437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85444 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85448 */   // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
     /*   85448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85451 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85453 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85455 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85460 */   // GIR_Coverage, 27789,
     /*   85460 */   GIR_EraseRootFromParent_Done,
     /*   85461 */ // Label 1019: @85461
     /*   85461 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(85490), // Rule ID 27790 //
     /*   85466 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   85469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85477 */   // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v32f16] }:$src0)  =>  SReg_512:{ *:[v16f32] }:$src0
     /*   85477 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85480 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85482 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85484 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85489 */   // GIR_Coverage, 27790,
     /*   85489 */   GIR_EraseRootFromParent_Done,
     /*   85490 */ // Label 1020: @85490
     /*   85490 */ GIM_Reject,
     /*   85491 */ // Label 741: @85491
     /*   85491 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(85520), // Rule ID 27843 //
     /*   85496 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85503 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85507 */   // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v32i32] }:$src0)  =>  VReg_1024:{ *:[v16i64] }:$src0
     /*   85507 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85510 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85512 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85514 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85519 */   // GIR_Coverage, 27843,
     /*   85519 */   GIR_EraseRootFromParent_Done,
     /*   85520 */ // Label 1021: @85520
     /*   85520 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(85549), // Rule ID 27844 //
     /*   85525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85532 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85536 */   // (bitconvert:{ *:[v16i64] } SReg_1024:{ *:[v32i32] }:$src0)  =>  SReg_1024:{ *:[v16i64] }:$src0
     /*   85536 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85539 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85541 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85543 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85548 */   // GIR_Coverage, 27844,
     /*   85548 */   GIR_EraseRootFromParent_Done,
     /*   85549 */ // Label 1022: @85549
     /*   85549 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(85578), // Rule ID 27845 //
     /*   85554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85561 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85565 */   // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v32f32] }:$src0)  =>  VReg_1024:{ *:[v16i64] }:$src0
     /*   85565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85568 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85570 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85572 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85577 */   // GIR_Coverage, 27845,
     /*   85577 */   GIR_EraseRootFromParent_Done,
     /*   85578 */ // Label 1023: @85578
     /*   85578 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(85607), // Rule ID 27846 //
     /*   85583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85590 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85594 */   // (bitconvert:{ *:[v16i64] } SReg_1024:{ *:[v32f32] }:$src0)  =>  SReg_1024:{ *:[v16i64] }:$src0
     /*   85594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85597 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85599 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85601 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85606 */   // GIR_Coverage, 27846,
     /*   85606 */   GIR_EraseRootFromParent_Done,
     /*   85607 */ // Label 1024: @85607
     /*   85607 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(85636), // Rule ID 27847 //
     /*   85612 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   85615 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85619 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85623 */   // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v16f64] }:$src0)  =>  VReg_1024:{ *:[v16i64] }:$src0
     /*   85623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85626 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85628 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85630 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85635 */   // GIR_Coverage, 27847,
     /*   85635 */   GIR_EraseRootFromParent_Done,
     /*   85636 */ // Label 1025: @85636
     /*   85636 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(85665), // Rule ID 27848 //
     /*   85641 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   85644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85648 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85652 */   // (bitconvert:{ *:[v16i64] } SReg_1024:{ *:[v16f64] }:$src0)  =>  SReg_1024:{ *:[v16i64] }:$src0
     /*   85652 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85655 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85657 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85659 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85664 */   // GIR_Coverage, 27848,
     /*   85664 */   GIR_EraseRootFromParent_Done,
     /*   85665 */ // Label 1026: @85665
     /*   85665 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(85694), // Rule ID 27849 //
     /*   85670 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85677 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85681 */   // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v32i32] }:$src0)  =>  VReg_1024:{ *:[v16f64] }:$src0
     /*   85681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85684 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85686 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85688 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85693 */   // GIR_Coverage, 27849,
     /*   85693 */   GIR_EraseRootFromParent_Done,
     /*   85694 */ // Label 1027: @85694
     /*   85694 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(85723), // Rule ID 27850 //
     /*   85699 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85702 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85706 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85710 */   // (bitconvert:{ *:[v16f64] } SReg_1024:{ *:[v32i32] }:$src0)  =>  SReg_1024:{ *:[v16f64] }:$src0
     /*   85710 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85713 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85715 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85717 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85722 */   // GIR_Coverage, 27850,
     /*   85722 */   GIR_EraseRootFromParent_Done,
     /*   85723 */ // Label 1028: @85723
     /*   85723 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(85752), // Rule ID 27851 //
     /*   85728 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85731 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85735 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85739 */   // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v32f32] }:$src0)  =>  VReg_1024:{ *:[v16f64] }:$src0
     /*   85739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85742 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85744 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85746 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85751 */   // GIR_Coverage, 27851,
     /*   85751 */   GIR_EraseRootFromParent_Done,
     /*   85752 */ // Label 1029: @85752
     /*   85752 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(85781), // Rule ID 27852 //
     /*   85757 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   85760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85764 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85768 */   // (bitconvert:{ *:[v16f64] } SReg_1024:{ *:[v32f32] }:$src0)  =>  SReg_1024:{ *:[v16f64] }:$src0
     /*   85768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85771 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85773 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85775 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85780 */   // GIR_Coverage, 27852,
     /*   85780 */   GIR_EraseRootFromParent_Done,
     /*   85781 */ // Label 1030: @85781
     /*   85781 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(85810), // Rule ID 27853 //
     /*   85786 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   85789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85793 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85797 */   // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v16i64] }:$src0)  =>  VReg_1024:{ *:[v16f64] }:$src0
     /*   85797 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85800 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85802 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85804 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   85809 */   // GIR_Coverage, 27853,
     /*   85809 */   GIR_EraseRootFromParent_Done,
     /*   85810 */ // Label 1031: @85810
     /*   85810 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(85839), // Rule ID 27854 //
     /*   85815 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   85818 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85822 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85826 */   // (bitconvert:{ *:[v16f64] } SReg_1024:{ *:[v16i64] }:$src0)  =>  SReg_1024:{ *:[v16f64] }:$src0
     /*   85826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85829 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85831 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85833 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   85838 */   // GIR_Coverage, 27854,
     /*   85838 */   GIR_EraseRootFromParent_Done,
     /*   85839 */ // Label 1032: @85839
     /*   85839 */ GIM_Reject,
     /*   85840 */ // Label 742: @85840
     /*   85840 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(85869), // Rule ID 27811 //
     /*   85845 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   85848 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85852 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85856 */   // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
     /*   85856 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85859 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85861 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85863 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85868 */   // GIR_Coverage, 27811,
     /*   85868 */   GIR_EraseRootFromParent_Done,
     /*   85869 */ // Label 1033: @85869
     /*   85869 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(85898), // Rule ID 27812 //
     /*   85874 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   85877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85881 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85885 */   // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v16i32] }:$src0)  =>  SReg_512:{ *:[v32i16] }:$src0
     /*   85885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85888 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85890 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85892 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85897 */   // GIR_Coverage, 27812,
     /*   85897 */   GIR_EraseRootFromParent_Done,
     /*   85898 */ // Label 1034: @85898
     /*   85898 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(85927), // Rule ID 27813 //
     /*   85903 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   85906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85910 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85914 */   // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
     /*   85914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85917 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85919 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85921 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85926 */   // GIR_Coverage, 27813,
     /*   85926 */   GIR_EraseRootFromParent_Done,
     /*   85927 */ // Label 1035: @85927
     /*   85927 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(85956), // Rule ID 27814 //
     /*   85932 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   85935 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85939 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85943 */   // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v16f32] }:$src0)  =>  SReg_512:{ *:[v32i16] }:$src0
     /*   85943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85946 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85948 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85950 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85955 */   // GIR_Coverage, 27814,
     /*   85955 */   GIR_EraseRootFromParent_Done,
     /*   85956 */ // Label 1036: @85956
     /*   85956 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(85985), // Rule ID 27815 //
     /*   85961 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85964 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85968 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85972 */   // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
     /*   85972 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   85975 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   85977 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   85979 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   85984 */   // GIR_Coverage, 27815,
     /*   85984 */   GIR_EraseRootFromParent_Done,
     /*   85985 */ // Label 1037: @85985
     /*   85985 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(86014), // Rule ID 27816 //
     /*   85990 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   85993 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   85997 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86001 */   // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v8i64] }:$src0)  =>  SReg_512:{ *:[v32i16] }:$src0
     /*   86001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86004 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86006 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86008 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86013 */   // GIR_Coverage, 27816,
     /*   86013 */   GIR_EraseRootFromParent_Done,
     /*   86014 */ // Label 1038: @86014
     /*   86014 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(86043), // Rule ID 27817 //
     /*   86019 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   86022 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86026 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86030 */   // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
     /*   86030 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86033 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86035 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86037 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86042 */   // GIR_Coverage, 27817,
     /*   86042 */   GIR_EraseRootFromParent_Done,
     /*   86043 */ // Label 1039: @86043
     /*   86043 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(86072), // Rule ID 27818 //
     /*   86048 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   86051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86055 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86059 */   // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v8f64] }:$src0)  =>  SReg_512:{ *:[v32i16] }:$src0
     /*   86059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86062 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86064 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86066 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86071 */   // GIR_Coverage, 27818,
     /*   86071 */   GIR_EraseRootFromParent_Done,
     /*   86072 */ // Label 1040: @86072
     /*   86072 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(86101), // Rule ID 27819 //
     /*   86077 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   86080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86084 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86088 */   // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
     /*   86088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86091 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86093 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86095 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86100 */   // GIR_Coverage, 27819,
     /*   86100 */   GIR_EraseRootFromParent_Done,
     /*   86101 */ // Label 1041: @86101
     /*   86101 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(86130), // Rule ID 27820 //
     /*   86106 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   86109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86113 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86117 */   // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v32f16] }:$src0)  =>  SReg_512:{ *:[v32i16] }:$src0
     /*   86117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86120 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86122 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86124 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86129 */   // GIR_Coverage, 27820,
     /*   86129 */   GIR_EraseRootFromParent_Done,
     /*   86130 */ // Label 1042: @86130
     /*   86130 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(86159), // Rule ID 27821 //
     /*   86135 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   86138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86142 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86146 */   // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
     /*   86146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86149 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86151 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86153 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86158 */   // GIR_Coverage, 27821,
     /*   86158 */   GIR_EraseRootFromParent_Done,
     /*   86159 */ // Label 1043: @86159
     /*   86159 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(86188), // Rule ID 27822 //
     /*   86164 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   86167 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86171 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86175 */   // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v16i32] }:$src0)  =>  SReg_512:{ *:[v32f16] }:$src0
     /*   86175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86178 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86180 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86182 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86187 */   // GIR_Coverage, 27822,
     /*   86187 */   GIR_EraseRootFromParent_Done,
     /*   86188 */ // Label 1044: @86188
     /*   86188 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(86217), // Rule ID 27823 //
     /*   86193 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   86196 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86200 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86204 */   // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
     /*   86204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86207 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86209 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86211 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86216 */   // GIR_Coverage, 27823,
     /*   86216 */   GIR_EraseRootFromParent_Done,
     /*   86217 */ // Label 1045: @86217
     /*   86217 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(86246), // Rule ID 27824 //
     /*   86222 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32,
     /*   86225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86229 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86233 */   // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v16f32] }:$src0)  =>  SReg_512:{ *:[v32f16] }:$src0
     /*   86233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86236 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86238 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86240 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86245 */   // GIR_Coverage, 27824,
     /*   86245 */   GIR_EraseRootFromParent_Done,
     /*   86246 */ // Label 1046: @86246
     /*   86246 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(86275), // Rule ID 27825 //
     /*   86251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   86254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86258 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86262 */   // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
     /*   86262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86265 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86267 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86269 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86274 */   // GIR_Coverage, 27825,
     /*   86274 */   GIR_EraseRootFromParent_Done,
     /*   86275 */ // Label 1047: @86275
     /*   86275 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(86304), // Rule ID 27826 //
     /*   86280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   86283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86287 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86291 */   // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v8i64] }:$src0)  =>  SReg_512:{ *:[v32f16] }:$src0
     /*   86291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86294 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86296 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86298 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86303 */   // GIR_Coverage, 27826,
     /*   86303 */   GIR_EraseRootFromParent_Done,
     /*   86304 */ // Label 1048: @86304
     /*   86304 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(86333), // Rule ID 27827 //
     /*   86309 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   86312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86316 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86320 */   // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
     /*   86320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86323 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86325 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86327 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86332 */   // GIR_Coverage, 27827,
     /*   86332 */   GIR_EraseRootFromParent_Done,
     /*   86333 */ // Label 1049: @86333
     /*   86333 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(86362), // Rule ID 27828 //
     /*   86338 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64,
     /*   86341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86345 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86349 */   // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v8f64] }:$src0)  =>  SReg_512:{ *:[v32f16] }:$src0
     /*   86349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86352 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86354 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86356 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86361 */   // GIR_Coverage, 27828,
     /*   86361 */   GIR_EraseRootFromParent_Done,
     /*   86362 */ // Label 1050: @86362
     /*   86362 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(86391), // Rule ID 27829 //
     /*   86367 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   86370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86374 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86378 */   // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
     /*   86378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86381 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86383 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86385 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*   86390 */   // GIR_Coverage, 27829,
     /*   86390 */   GIR_EraseRootFromParent_Done,
     /*   86391 */ // Label 1051: @86391
     /*   86391 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(86420), // Rule ID 27830 //
     /*   86396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16,
     /*   86399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86403 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86407 */   // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v32i16] }:$src0)  =>  SReg_512:{ *:[v32f16] }:$src0
     /*   86407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86410 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86412 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86414 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*   86419 */   // GIR_Coverage, 27830,
     /*   86419 */   GIR_EraseRootFromParent_Done,
     /*   86420 */ // Label 1052: @86420
     /*   86420 */ GIM_Reject,
     /*   86421 */ // Label 743: @86421
     /*   86421 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(86450), // Rule ID 27831 //
     /*   86426 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   86429 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86433 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86437 */   // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v32f32] }:$src0)  =>  VReg_1024:{ *:[v32i32] }:$src0
     /*   86437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86440 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86442 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86444 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86449 */   // GIR_Coverage, 27831,
     /*   86449 */   GIR_EraseRootFromParent_Done,
     /*   86450 */ // Label 1053: @86450
     /*   86450 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(86479), // Rule ID 27832 //
     /*   86455 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   86458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86462 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86466 */   // (bitconvert:{ *:[v32i32] } SReg_1024:{ *:[v32f32] }:$src0)  =>  SReg_1024:{ *:[v32i32] }:$src0
     /*   86466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86469 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86471 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86473 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86478 */   // GIR_Coverage, 27832,
     /*   86478 */   GIR_EraseRootFromParent_Done,
     /*   86479 */ // Label 1054: @86479
     /*   86479 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(86508), // Rule ID 27833 //
     /*   86484 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86491 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86495 */   // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v16i64] }:$src0)  =>  VReg_1024:{ *:[v32i32] }:$src0
     /*   86495 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86498 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86500 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86502 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86507 */   // GIR_Coverage, 27833,
     /*   86507 */   GIR_EraseRootFromParent_Done,
     /*   86508 */ // Label 1055: @86508
     /*   86508 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(86537), // Rule ID 27834 //
     /*   86513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86520 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86524 */   // (bitconvert:{ *:[v32i32] } SReg_1024:{ *:[v16i64] }:$src0)  =>  SReg_1024:{ *:[v32i32] }:$src0
     /*   86524 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86527 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86529 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86531 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86536 */   // GIR_Coverage, 27834,
     /*   86536 */   GIR_EraseRootFromParent_Done,
     /*   86537 */ // Label 1056: @86537
     /*   86537 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(86566), // Rule ID 27835 //
     /*   86542 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86549 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86553 */   // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v16f64] }:$src0)  =>  VReg_1024:{ *:[v32i32] }:$src0
     /*   86553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86556 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86558 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86560 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86565 */   // GIR_Coverage, 27835,
     /*   86565 */   GIR_EraseRootFromParent_Done,
     /*   86566 */ // Label 1057: @86566
     /*   86566 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(86595), // Rule ID 27836 //
     /*   86571 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86578 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86582 */   // (bitconvert:{ *:[v32i32] } SReg_1024:{ *:[v16f64] }:$src0)  =>  SReg_1024:{ *:[v32i32] }:$src0
     /*   86582 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86585 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86587 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86589 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86594 */   // GIR_Coverage, 27836,
     /*   86594 */   GIR_EraseRootFromParent_Done,
     /*   86595 */ // Label 1058: @86595
     /*   86595 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(86624), // Rule ID 27837 //
     /*   86600 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   86603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86607 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86611 */   // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v32i32] }:$src0)  =>  VReg_1024:{ *:[v32f32] }:$src0
     /*   86611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86614 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86616 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86618 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86623 */   // GIR_Coverage, 27837,
     /*   86623 */   GIR_EraseRootFromParent_Done,
     /*   86624 */ // Label 1059: @86624
     /*   86624 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(86653), // Rule ID 27838 //
     /*   86629 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32,
     /*   86632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86636 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86640 */   // (bitconvert:{ *:[v32f32] } SReg_1024:{ *:[v32i32] }:$src0)  =>  SReg_1024:{ *:[v32f32] }:$src0
     /*   86640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86643 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86645 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86647 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86652 */   // GIR_Coverage, 27838,
     /*   86652 */   GIR_EraseRootFromParent_Done,
     /*   86653 */ // Label 1060: @86653
     /*   86653 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(86682), // Rule ID 27839 //
     /*   86658 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86661 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86665 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86669 */   // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v16i64] }:$src0)  =>  VReg_1024:{ *:[v32f32] }:$src0
     /*   86669 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86672 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86674 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86676 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86681 */   // GIR_Coverage, 27839,
     /*   86681 */   GIR_EraseRootFromParent_Done,
     /*   86682 */ // Label 1061: @86682
     /*   86682 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(86711), // Rule ID 27840 //
     /*   86687 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86694 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86698 */   // (bitconvert:{ *:[v32f32] } SReg_1024:{ *:[v16i64] }:$src0)  =>  SReg_1024:{ *:[v32f32] }:$src0
     /*   86698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86701 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86703 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86705 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86710 */   // GIR_Coverage, 27840,
     /*   86710 */   GIR_EraseRootFromParent_Done,
     /*   86711 */ // Label 1062: @86711
     /*   86711 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(86740), // Rule ID 27841 //
     /*   86716 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86723 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86727 */   // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v16f64] }:$src0)  =>  VReg_1024:{ *:[v32f32] }:$src0
     /*   86727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86730 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86732 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86734 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*   86739 */   // GIR_Coverage, 27841,
     /*   86739 */   GIR_EraseRootFromParent_Done,
     /*   86740 */ // Label 1063: @86740
     /*   86740 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(86769), // Rule ID 27842 //
     /*   86745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64,
     /*   86748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86752 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86756 */   // (bitconvert:{ *:[v32f32] } SReg_1024:{ *:[v16f64] }:$src0)  =>  SReg_1024:{ *:[v32f32] }:$src0
     /*   86756 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   86759 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /*   86761 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86763 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_1024RegClassID),
     /*   86768 */   // GIR_Coverage, 27842,
     /*   86768 */   GIR_EraseRootFromParent_Done,
     /*   86769 */ // Label 1064: @86769
     /*   86769 */ GIM_Reject,
     /*   86770 */ // Label 744: @86770
     /*   86770 */ GIM_Reject,
     /*   86771 */ // Label 9: @86771
     /*   86771 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 1067*/ GIMT_Encode4(86965),
     /*   86782 */ /*GILLT_s16*//*Label 1065*/ GIMT_Encode4(86790),
     /*   86786 */ /*GILLT_s32*//*Label 1066*/ GIMT_Encode4(86929),
     /*   86790 */ // Label 1065: @86790
     /*   86790 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(86928),
     /*   86795 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   86798 */   GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(86857), // Rule ID 27318 //
     /*   86803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   86806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   86810 */     // MIs[0] round
     /*   86810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*   86813 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SupportedRoundMode),
     /*   86818 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   86825 */     // (fptrunc_round:{ *:[f16] } (VOP3OpSelMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] })<<P:Predicate_SupportedRoundMode>>:$round)  =>  (FPTRUNC_ROUND_F16_F32_PSEUDO_t16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, (as_hw_round_mode:{ *:[i32] } ?:{ *:[i32] }:$round))
     /*   86825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO_t16_e64),
     /*   86828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   86830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   86835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   86840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   86843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   86846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   86849 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderRoundMode), // round
     /*   86855 */     GIR_RootConstrainSelectedInstOperands,
     /*   86856 */     // GIR_Coverage, 27318,
     /*   86856 */     GIR_EraseRootFromParent_Done,
     /*   86857 */   // Label 1069: @86857
     /*   86857 */   GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(86892), // Rule ID 27316 //
     /*   86862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
     /*   86865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   86869 */     // MIs[0] round
     /*   86869 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*   86872 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SupportedRoundMode),
     /*   86877 */     // (fptrunc_round:{ *:[f16] } f32:{ *:[f32] }:$src0, (timm:{ *:[i32] })<<P:Predicate_SupportedRoundMode>>:$round)  =>  (FPTRUNC_ROUND_F16_F32_PSEUDO:{ *:[f16] } ?:{ *:[f32] }:$src0, (as_hw_round_mode:{ *:[i32] } ?:{ *:[i32] }:$round))
     /*   86877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO),
     /*   86880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   86882 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86884 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderRoundMode), // round
     /*   86890 */     GIR_RootConstrainSelectedInstOperands,
     /*   86891 */     // GIR_Coverage, 27316,
     /*   86891 */     GIR_EraseRootFromParent_Done,
     /*   86892 */   // Label 1070: @86892
     /*   86892 */   GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(86927), // Rule ID 27317 //
     /*   86897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   86900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   86904 */     // MIs[0] round
     /*   86904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*   86907 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SupportedRoundMode),
     /*   86912 */     // (fptrunc_round:{ *:[f16] } f32:{ *:[f32] }:$src0, (timm:{ *:[i32] })<<P:Predicate_SupportedRoundMode>>:$round)  =>  (FPTRUNC_ROUND_F16_F32_PSEUDO_fake16_e32:{ *:[f16] } ?:{ *:[f32] }:$src0, (as_hw_round_mode:{ *:[i32] } ?:{ *:[i32] }:$round))
     /*   86912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO_fake16_e32),
     /*   86915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   86917 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86919 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderRoundMode), // round
     /*   86925 */     GIR_RootConstrainSelectedInstOperands,
     /*   86926 */     // GIR_Coverage, 27317,
     /*   86926 */     GIR_EraseRootFromParent_Done,
     /*   86927 */   // Label 1071: @86927
     /*   86927 */   GIM_Reject,
     /*   86928 */ // Label 1068: @86928
     /*   86928 */ GIM_Reject,
     /*   86929 */ // Label 1066: @86929
     /*   86929 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(86964), // Rule ID 27319 //
     /*   86934 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   86937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   86941 */   // MIs[0] round
     /*   86941 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*   86944 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SupportedRoundMode),
     /*   86949 */   // (fptrunc_round:{ *:[f32] } f64:{ *:[f64] }:$src0, (timm:{ *:[i32] })<<P:Predicate_SupportedRoundMode>>:$round)  =>  (FPTRUNC_ROUND_F32_F64_PSEUDO:{ *:[f32] } ?:{ *:[f64] }:$src0, (as_hw_round_mode:{ *:[i32] } ?:{ *:[i32] }:$round))
     /*   86949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_ROUND_F32_F64_PSEUDO),
     /*   86952 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   86954 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*   86956 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderRoundMode), // round
     /*   86962 */   GIR_RootConstrainSelectedInstOperands,
     /*   86963 */   // GIR_Coverage, 27319,
     /*   86963 */   GIR_EraseRootFromParent_Done,
     /*   86964 */ // Label 1072: @86964
     /*   86964 */ GIM_Reject,
     /*   86965 */ // Label 1067: @86965
     /*   86965 */ GIM_Reject,
     /*   86966 */ // Label 10: @86966
     /*   86966 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 1076*/ GIMT_Encode4(87467),
     /*   86977 */ /*GILLT_s16*//*Label 1073*/ GIMT_Encode4(86989),
     /*   86981 */ /*GILLT_s32*//*Label 1074*/ GIMT_Encode4(87163),
     /*   86985 */ /*GILLT_s64*//*Label 1075*/ GIMT_Encode4(87243),
     /*   86989 */ // Label 1073: @86989
     /*   86989 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(87162),
     /*   86994 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   86997 */   GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(87024), // Rule ID 39 //
     /*   87002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
     /*   87005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   87009 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20766),
     /*   87013 */     // (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_20766>>  =>  (S_TRUNC_F16:{ *:[f16] } f16:{ *:[f16] }:$src0)
     /*   87013 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TRUNC_F16),
     /*   87018 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
     /*   87022 */     GIR_RootConstrainSelectedInstOperands,
     /*   87023 */     // GIR_Coverage, 39,
     /*   87023 */     GIR_Done,
     /*   87024 */   // Label 1078: @87024
     /*   87024 */   GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(87070), // Rule ID 2567 //
     /*   87029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*   87032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   87036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87043 */     // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_e64),
     /*   87046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87068 */     GIR_RootConstrainSelectedInstOperands,
     /*   87069 */     // GIR_Coverage, 2567,
     /*   87069 */     GIR_EraseRootFromParent_Done,
     /*   87070 */   // Label 1079: @87070
     /*   87070 */   GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(87116), // Rule ID 2569 //
     /*   87075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   87078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   87082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87089 */     // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_fake16_e64),
     /*   87092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87114 */     GIR_RootConstrainSelectedInstOperands,
     /*   87115 */     // GIR_Coverage, 2569,
     /*   87115 */     GIR_EraseRootFromParent_Done,
     /*   87116 */   // Label 1080: @87116
     /*   87116 */   GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(87161), // Rule ID 2568 //
     /*   87121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   87124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   87128 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   87135 */     // (ftrunc:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_TRUNC_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*   87135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_t16_e64),
     /*   87138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87150 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   87153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   87156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   87159 */     GIR_RootConstrainSelectedInstOperands,
     /*   87160 */     // GIR_Coverage, 2568,
     /*   87160 */     GIR_EraseRootFromParent_Done,
     /*   87161 */   // Label 1081: @87161
     /*   87161 */   GIM_Reject,
     /*   87162 */ // Label 1077: @87162
     /*   87162 */ GIM_Reject,
     /*   87163 */ // Label 1074: @87163
     /*   87163 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(87242),
     /*   87168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   87171 */   GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(87198), // Rule ID 34 //
     /*   87176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
     /*   87179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   87183 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20766),
     /*   87187 */     // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_20766>>  =>  (S_TRUNC_F32:{ *:[f32] } f32:{ *:[f32] }:$src0)
     /*   87187 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TRUNC_F32),
     /*   87192 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
     /*   87196 */     GIR_RootConstrainSelectedInstOperands,
     /*   87197 */     // GIR_Coverage, 34,
     /*   87197 */     GIR_Done,
     /*   87198 */   // Label 1083: @87198
     /*   87198 */   GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(87241), // Rule ID 2389 //
     /*   87203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   87207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87214 */     // (ftrunc:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F32_e64),
     /*   87217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87239 */     GIR_RootConstrainSelectedInstOperands,
     /*   87240 */     // GIR_Coverage, 2389,
     /*   87240 */     GIR_EraseRootFromParent_Done,
     /*   87241 */   // Label 1084: @87241
     /*   87241 */   GIM_Reject,
     /*   87242 */ // Label 1082: @87242
     /*   87242 */ GIM_Reject,
     /*   87243 */ // Label 1075: @87243
     /*   87243 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(87466),
     /*   87248 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   87251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   87255 */   GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(87297), // Rule ID 2478 //
     /*   87260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode0),
     /*   87263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87270 */     // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64),
     /*   87273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87295 */     GIR_RootConstrainSelectedInstOperands,
     /*   87296 */     // GIR_Coverage, 2478,
     /*   87296 */     GIR_EraseRootFromParent_Done,
     /*   87297 */   // Label 1086: @87297
     /*   87297 */   GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(87339), // Rule ID 2479 //
     /*   87302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode1),
     /*   87305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87312 */     // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64),
     /*   87315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87337 */     GIR_RootConstrainSelectedInstOperands,
     /*   87338 */     // GIR_Coverage, 2479,
     /*   87338 */     GIR_EraseRootFromParent_Done,
     /*   87339 */   // Label 1087: @87339
     /*   87339 */   GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(87381), // Rule ID 2480 //
     /*   87344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode2),
     /*   87347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87354 */     // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64),
     /*   87357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87379 */     GIR_RootConstrainSelectedInstOperands,
     /*   87380 */     // GIR_Coverage, 2480,
     /*   87380 */     GIR_EraseRootFromParent_Done,
     /*   87381 */   // Label 1088: @87381
     /*   87381 */   GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(87423), // Rule ID 2481 //
     /*   87386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode3),
     /*   87389 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87396 */     // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64),
     /*   87399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87421 */     GIR_RootConstrainSelectedInstOperands,
     /*   87422 */     // GIR_Coverage, 2481,
     /*   87422 */     GIR_EraseRootFromParent_Done,
     /*   87423 */   // Label 1089: @87423
     /*   87423 */   GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(87465), // Rule ID 2482 //
     /*   87428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode4),
     /*   87431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87438 */     // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64),
     /*   87441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87463 */     GIR_RootConstrainSelectedInstOperands,
     /*   87464 */     // GIR_Coverage, 2482,
     /*   87464 */     GIR_EraseRootFromParent_Done,
     /*   87465 */   // Label 1090: @87465
     /*   87465 */   GIM_Reject,
     /*   87466 */ // Label 1085: @87466
     /*   87466 */ GIM_Reject,
     /*   87467 */ // Label 1076: @87467
     /*   87467 */ GIM_Reject,
     /*   87468 */ // Label 11: @87468
     /*   87468 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 1094*/ GIMT_Encode4(87969),
     /*   87479 */ /*GILLT_s16*//*Label 1091*/ GIMT_Encode4(87491),
     /*   87483 */ /*GILLT_s32*//*Label 1092*/ GIMT_Encode4(87665),
     /*   87487 */ /*GILLT_s64*//*Label 1093*/ GIMT_Encode4(87745),
     /*   87491 */ // Label 1091: @87491
     /*   87491 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(87664),
     /*   87496 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*   87499 */   GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(87526), // Rule ID 40 //
     /*   87504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
     /*   87507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   87511 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20767),
     /*   87515 */     // (froundeven:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_20767>>  =>  (S_RNDNE_F16:{ *:[f16] } f16:{ *:[f16] }:$src0)
     /*   87515 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_RNDNE_F16),
     /*   87520 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
     /*   87524 */     GIR_RootConstrainSelectedInstOperands,
     /*   87525 */     // GIR_Coverage, 40,
     /*   87525 */     GIR_Done,
     /*   87526 */   // Label 1096: @87526
     /*   87526 */   GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(87572), // Rule ID 2570 //
     /*   87531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*   87534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   87538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87545 */     // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_e64),
     /*   87548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87570 */     GIR_RootConstrainSelectedInstOperands,
     /*   87571 */     // GIR_Coverage, 2570,
     /*   87571 */     GIR_EraseRootFromParent_Done,
     /*   87572 */   // Label 1097: @87572
     /*   87572 */   GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(87618), // Rule ID 2572 //
     /*   87577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*   87580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   87584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87591 */     // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_fake16_e64),
     /*   87594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87616 */     GIR_RootConstrainSelectedInstOperands,
     /*   87617 */     // GIR_Coverage, 2572,
     /*   87617 */     GIR_EraseRootFromParent_Done,
     /*   87618 */   // Label 1098: @87618
     /*   87618 */   GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(87663), // Rule ID 2571 //
     /*   87623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*   87626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*   87630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*   87637 */     // (froundeven:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_RNDNE_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*   87637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_t16_e64),
     /*   87640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   87655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   87658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   87661 */     GIR_RootConstrainSelectedInstOperands,
     /*   87662 */     // GIR_Coverage, 2571,
     /*   87662 */     GIR_EraseRootFromParent_Done,
     /*   87663 */   // Label 1099: @87663
     /*   87663 */   GIM_Reject,
     /*   87664 */ // Label 1095: @87664
     /*   87664 */ GIM_Reject,
     /*   87665 */ // Label 1092: @87665
     /*   87665 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(87744),
     /*   87670 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   87673 */   GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(87700), // Rule ID 35 //
     /*   87678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
     /*   87681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*   87685 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20767),
     /*   87689 */     // (froundeven:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_20767>>  =>  (S_RNDNE_F32:{ *:[f32] } f32:{ *:[f32] }:$src0)
     /*   87689 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_RNDNE_F32),
     /*   87694 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
     /*   87698 */     GIR_RootConstrainSelectedInstOperands,
     /*   87699 */     // GIR_Coverage, 35,
     /*   87699 */     GIR_Done,
     /*   87700 */   // Label 1101: @87700
     /*   87700 */   GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(87743), // Rule ID 2391 //
     /*   87705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*   87709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87716 */     // (froundeven:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F32_e64),
     /*   87719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87741 */     GIR_RootConstrainSelectedInstOperands,
     /*   87742 */     // GIR_Coverage, 2391,
     /*   87742 */     GIR_EraseRootFromParent_Done,
     /*   87743 */   // Label 1102: @87743
     /*   87743 */   GIM_Reject,
     /*   87744 */ // Label 1100: @87744
     /*   87744 */ GIM_Reject,
     /*   87745 */ // Label 1093: @87745
     /*   87745 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(87968),
     /*   87750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   87753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   87757 */   GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(87799), // Rule ID 2488 //
     /*   87762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode0),
     /*   87765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87772 */     // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64),
     /*   87775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87797 */     GIR_RootConstrainSelectedInstOperands,
     /*   87798 */     // GIR_Coverage, 2488,
     /*   87798 */     GIR_EraseRootFromParent_Done,
     /*   87799 */   // Label 1104: @87799
     /*   87799 */   GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(87841), // Rule ID 2489 //
     /*   87804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode1),
     /*   87807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87814 */     // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64),
     /*   87817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87839 */     GIR_RootConstrainSelectedInstOperands,
     /*   87840 */     // GIR_Coverage, 2489,
     /*   87840 */     GIR_EraseRootFromParent_Done,
     /*   87841 */   // Label 1105: @87841
     /*   87841 */   GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(87883), // Rule ID 2490 //
     /*   87846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode2),
     /*   87849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87856 */     // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64),
     /*   87859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87881 */     GIR_RootConstrainSelectedInstOperands,
     /*   87882 */     // GIR_Coverage, 2490,
     /*   87882 */     GIR_EraseRootFromParent_Done,
     /*   87883 */   // Label 1106: @87883
     /*   87883 */   GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(87925), // Rule ID 2491 //
     /*   87888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode3),
     /*   87891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87898 */     // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64),
     /*   87901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87923 */     GIR_RootConstrainSelectedInstOperands,
     /*   87924 */     // GIR_Coverage, 2491,
     /*   87924 */     GIR_EraseRootFromParent_Done,
     /*   87925 */   // Label 1107: @87925
     /*   87925 */   GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(87967), // Rule ID 2492 //
     /*   87930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus_HwMode4),
     /*   87933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*   87940 */     // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*   87940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64),
     /*   87943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   87945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*   87950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*   87955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*   87960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*   87965 */     GIR_RootConstrainSelectedInstOperands,
     /*   87966 */     // GIR_Coverage, 2492,
     /*   87966 */     GIR_EraseRootFromParent_Done,
     /*   87967 */   // Label 1108: @87967
     /*   87967 */   GIM_Reject,
     /*   87968 */ // Label 1103: @87968
     /*   87968 */ GIM_Reject,
     /*   87969 */ // Label 1094: @87969
     /*   87969 */ GIM_Reject,
     /*   87970 */ // Label 12: @87970
     /*   87970 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(88130),
     /*   87975 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*   87978 */   GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(88024),
     /*   87983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   87987 */     GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(88002), // Rule ID 191 //
     /*   87992 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSGetShaderCyclesInst),
     /*   87995 */       // (readcyclecounter:{ *:[i64] })  =>  (S_GET_SHADER_CYCLES_U64:{ *:[i64] })
     /*   87995 */       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_GET_SHADER_CYCLES_U64),
     /*   88000 */       GIR_RootConstrainSelectedInstOperands,
     /*   88001 */       // GIR_Coverage, 191,
     /*   88001 */       GIR_Done,
     /*   88002 */     // Label 1111: @88002
     /*   88002 */     GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(88023), // Rule ID 4239 //
     /*   88007 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShaderCyclesHiLoRegisters),
     /*   88010 */       // (readcyclecounter:{ *:[i64] })  =>  (GET_SHADERCYCLESHILO:{ *:[i64] }:{ *:[i1] })
     /*   88010 */       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GET_SHADERCYCLESHILO),
     /*   88015 */       GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*   88021 */       GIR_RootConstrainSelectedInstOperands,
     /*   88022 */       // GIR_Coverage, 4239,
     /*   88022 */       GIR_Done,
     /*   88023 */     // Label 1112: @88023
     /*   88023 */     GIM_Reject,
     /*   88024 */   // Label 1110: @88024
     /*   88024 */   GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(88043), // Rule ID 9278 //
     /*   88029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemTimeInst),
     /*   88032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88036 */     // (readcyclecounter:{ *:[i64] })  =>  (S_MEMTIME:{ *:[i64] })
     /*   88036 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMTIME),
     /*   88041 */     GIR_RootConstrainSelectedInstOperands,
     /*   88042 */     // GIR_Coverage, 9278,
     /*   88042 */     GIR_Done,
     /*   88043 */   // Label 1113: @88043
     /*   88043 */   GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(88129), // Rule ID 9279 //
     /*   88048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShaderCyclesRegister),
     /*   88051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   88055 */     // (readcyclecounter:{ *:[i64] })  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 38941:{ *:[i32] }), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*   88055 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*   88058 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*   88062 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   88067 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*   88070 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   88072 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*   88075 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32),
     /*   88079 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   88084 */     GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(38941),
     /*   88094 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   88096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*   88099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   88101 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   88104 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*   88107 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   88110 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*   88113 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   88118 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*   88123 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*   88128 */     // GIR_Coverage, 9279,
     /*   88128 */     GIR_EraseRootFromParent_Done,
     /*   88129 */   // Label 1114: @88129
     /*   88129 */   GIM_Reject,
     /*   88130 */ // Label 1109: @88130
     /*   88130 */ GIM_Reject,
     /*   88131 */ // Label 13: @88131
     /*   88131 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(88188),
     /*   88136 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*   88139 */   GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(88158), // Rule ID 9280 //
     /*   88144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemRealTime),
     /*   88147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88151 */     // (readsteadycounter:{ *:[i64] })  =>  (S_MEMREALTIME:{ *:[i64] })
     /*   88151 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMREALTIME),
     /*   88156 */     GIR_RootConstrainSelectedInstOperands,
     /*   88157 */     // GIR_Coverage, 9280,
     /*   88157 */     GIR_Done,
     /*   88158 */   // Label 1116: @88158
     /*   88158 */   GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(88187), // Rule ID 9281 //
     /*   88163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*   88166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   88170 */     // (readsteadycounter:{ *:[i64] })  =>  (S_SENDMSG_RTN_B64:{ *:[i64] } 131:{ *:[i32] })
     /*   88170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B64),
     /*   88173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88175 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(131),
     /*   88185 */     GIR_RootConstrainSelectedInstOperands,
     /*   88186 */     // GIR_Coverage, 9281,
     /*   88186 */     GIR_EraseRootFromParent_Done,
     /*   88187 */   // Label 1117: @88187
     /*   88187 */   GIM_Reject,
     /*   88188 */ // Label 1115: @88188
     /*   88188 */ GIM_Reject,
     /*   88189 */ // Label 14: @88189
     /*   88189 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(33), /*)*//*default:*//*Label 1142*/ GIMT_Encode4(314855),
     /*   88200 */ /*GILLT_p0s64*//*Label 1118*/ GIMT_Encode4(88332),
     /*   88204 */ /*GILLT_p1s64*//*Label 1119*/ GIMT_Encode4(94372),
     /*   88208 */ /*GILLT_p2s32*//*Label 1120*/ GIMT_Encode4(100412),
     /*   88212 */ /*GILLT_p3s32*//*Label 1121*/ GIMT_Encode4(106163),
     /*   88216 */ /*GILLT_p4s64*//*Label 1122*/ GIMT_Encode4(111914),
     /*   88220 */ /*GILLT_p5s32*//*Label 1123*/ GIMT_Encode4(117954),
     /*   88224 */ /*GILLT_p6s32*//*Label 1124*/ GIMT_Encode4(123705),
     /*   88228 */ /*GILLT_s1*//*Label 1125*/ GIMT_Encode4(129456),
     /*   88232 */ /*GILLT_s16*//*Label 1126*/ GIMT_Encode4(130064),
     /*   88236 */ /*GILLT_s32*//*Label 1127*/ GIMT_Encode4(164612),
     /*   88240 */ /*GILLT_s64*//*Label 1128*/ GIMT_Encode4(200300),
     /*   88244 */ /*GILLT_v2s16*//*Label 1129*/ GIMT_Encode4(216494),
     /*   88248 */ /*GILLT_v2s32*//*Label 1130*/ GIMT_Encode4(227986),
     /*   88252 */ /*GILLT_v2s64*//*Label 1131*/ GIMT_Encode4(243409),
     /*   88256 */ /*GILLT_v3s32*//*Label 1132*/ GIMT_Encode4(255479), GIMT_Encode4(0),
     /*   88264 */ /*GILLT_v4s16*//*Label 1133*/ GIMT_Encode4(265236),
     /*   88268 */ /*GILLT_v4s32*//*Label 1134*/ GIMT_Encode4(277306),
     /*   88272 */ /*GILLT_v4s64*//*Label 1135*/ GIMT_Encode4(292729), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   88288 */ /*GILLT_v8s16*//*Label 1136*/ GIMT_Encode4(294405),
     /*   88292 */ /*GILLT_v8s32*//*Label 1137*/ GIMT_Encode4(306475),
     /*   88296 */ /*GILLT_v8s64*//*Label 1138*/ GIMT_Encode4(308151), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   88316 */ /*GILLT_v16s16*//*Label 1139*/ GIMT_Encode4(309827),
     /*   88320 */ /*GILLT_v16s32*//*Label 1140*/ GIMT_Encode4(311503), GIMT_Encode4(0),
     /*   88328 */ /*GILLT_v32s16*//*Label 1141*/ GIMT_Encode4(313179),
     /*   88332 */ // Label 1118: @88332
     /*   88332 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(94371),
     /*   88337 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*   88340 */   GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(88406), // Rule ID 31112 //
     /*   88345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   88348 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88360 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   88364 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   88368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*   88375 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   88375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   88378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   88385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   88390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   88395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   88400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88404 */     GIR_RootConstrainSelectedInstOperands,
     /*   88405 */     // GIR_Coverage, 31112,
     /*   88405 */     GIR_EraseRootFromParent_Done,
     /*   88406 */   // Label 1144: @88406
     /*   88406 */   GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(88468), // Rule ID 31117 //
     /*   88411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   88414 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88426 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   88430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*   88437 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   88437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*   88440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   88447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   88452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   88457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   88462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88466 */     GIR_RootConstrainSelectedInstOperands,
     /*   88467 */     // GIR_Coverage, 31117,
     /*   88467 */     GIR_EraseRootFromParent_Done,
     /*   88468 */   // Label 1145: @88468
     /*   88468 */   GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(88530), // Rule ID 31123 //
     /*   88473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   88476 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88488 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   88492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*   88499 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   88499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   88502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   88509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   88514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   88519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   88524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88528 */     GIR_RootConstrainSelectedInstOperands,
     /*   88529 */     // GIR_Coverage, 31123,
     /*   88529 */     GIR_EraseRootFromParent_Done,
     /*   88530 */   // Label 1146: @88530
     /*   88530 */   GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(88589), // Rule ID 31108 //
     /*   88535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   88538 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88550 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   88554 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   88558 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*   88565 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   88565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   88568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   88575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88583 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88587 */     GIR_RootConstrainSelectedInstOperands,
     /*   88588 */     // GIR_Coverage, 31108,
     /*   88588 */     GIR_EraseRootFromParent_Done,
     /*   88589 */   // Label 1147: @88589
     /*   88589 */   GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(88648), // Rule ID 31109 //
     /*   88594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*   88597 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88609 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   88613 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   88617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*   88624 */     // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   88624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*   88627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   88634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88646 */     GIR_RootConstrainSelectedInstOperands,
     /*   88647 */     // GIR_Coverage, 31109,
     /*   88647 */     GIR_EraseRootFromParent_Done,
     /*   88648 */   // Label 1148: @88648
     /*   88648 */   GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(88703), // Rule ID 31114 //
     /*   88653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   88656 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   88664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88668 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   88672 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*   88679 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   88679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*   88682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   88684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   88689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88701 */     GIR_RootConstrainSelectedInstOperands,
     /*   88702 */     // GIR_Coverage, 31114,
     /*   88702 */     GIR_EraseRootFromParent_Done,
     /*   88703 */   // Label 1149: @88703
     /*   88703 */   GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(88768), // Rule ID 30063 //
     /*   88708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*   88711 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   88729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88733 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   88737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   88744 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   88744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   88747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   88749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   88754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88766 */     GIR_RootConstrainSelectedInstOperands,
     /*   88767 */     // GIR_Coverage, 30063,
     /*   88767 */     GIR_EraseRootFromParent_Done,
     /*   88768 */   // Label 1150: @88768
     /*   88768 */   GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(88833), // Rule ID 30064 //
     /*   88773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*   88776 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88780 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88785 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   88794 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88798 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   88802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   88809 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   88809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   88812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   88814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   88819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88831 */     GIR_RootConstrainSelectedInstOperands,
     /*   88832 */     // GIR_Coverage, 30064,
     /*   88832 */     GIR_EraseRootFromParent_Done,
     /*   88833 */   // Label 1151: @88833
     /*   88833 */   GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(88898), // Rule ID 30065 //
     /*   88838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*   88841 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88845 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88850 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   88859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88863 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   88867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   88874 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   88874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   88877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   88879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   88884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88896 */     GIR_RootConstrainSelectedInstOperands,
     /*   88897 */     // GIR_Coverage, 30065,
     /*   88897 */     GIR_EraseRootFromParent_Done,
     /*   88898 */   // Label 1152: @88898
     /*   88898 */   GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(88963), // Rule ID 30066 //
     /*   88903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*   88906 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   88924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88928 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   88932 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   88939 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   88939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   88942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   88944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   88949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   88954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   88957 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   88961 */     GIR_RootConstrainSelectedInstOperands,
     /*   88962 */     // GIR_Coverage, 30066,
     /*   88962 */     GIR_EraseRootFromParent_Done,
     /*   88963 */   // Label 1153: @88963
     /*   88963 */   GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(89028), // Rule ID 30067 //
     /*   88968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*   88971 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   88975 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   88985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   88989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   88993 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   88997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89004 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   89007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89026 */     GIR_RootConstrainSelectedInstOperands,
     /*   89027 */     // GIR_Coverage, 30067,
     /*   89027 */     GIR_EraseRootFromParent_Done,
     /*   89028 */   // Label 1154: @89028
     /*   89028 */   GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(89088), // Rule ID 29723 //
     /*   89033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*   89036 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89045 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89064 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   89067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89086 */     GIR_RootConstrainSelectedInstOperands,
     /*   89087 */     // GIR_Coverage, 29723,
     /*   89087 */     GIR_EraseRootFromParent_Done,
     /*   89088 */   // Label 1155: @89088
     /*   89088 */   GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(89148), // Rule ID 29724 //
     /*   89093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*   89096 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89105 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89124 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   89127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89146 */     GIR_RootConstrainSelectedInstOperands,
     /*   89147 */     // GIR_Coverage, 29724,
     /*   89147 */     GIR_EraseRootFromParent_Done,
     /*   89148 */   // Label 1156: @89148
     /*   89148 */   GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(89208), // Rule ID 29725 //
     /*   89153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*   89156 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89165 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89184 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   89187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89206 */     GIR_RootConstrainSelectedInstOperands,
     /*   89207 */     // GIR_Coverage, 29725,
     /*   89207 */     GIR_EraseRootFromParent_Done,
     /*   89208 */   // Label 1157: @89208
     /*   89208 */   GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(89268), // Rule ID 29726 //
     /*   89213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*   89216 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89225 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89244 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   89247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89266 */     GIR_RootConstrainSelectedInstOperands,
     /*   89267 */     // GIR_Coverage, 29726,
     /*   89267 */     GIR_EraseRootFromParent_Done,
     /*   89268 */   // Label 1158: @89268
     /*   89268 */   GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(89328), // Rule ID 29727 //
     /*   89273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*   89276 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89285 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89304 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   89307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89326 */     GIR_RootConstrainSelectedInstOperands,
     /*   89327 */     // GIR_Coverage, 29727,
     /*   89327 */     GIR_EraseRootFromParent_Done,
     /*   89328 */   // Label 1159: @89328
     /*   89328 */   GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(89380), // Rule ID 31119 //
     /*   89333 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   89341 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89345 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   89349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*   89356 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   89356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   89359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   89361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   89366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89378 */     GIR_RootConstrainSelectedInstOperands,
     /*   89379 */     // GIR_Coverage, 31119,
     /*   89379 */     GIR_EraseRootFromParent_Done,
     /*   89380 */   // Label 1160: @89380
     /*   89380 */   GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(89435), // Rule ID 31120 //
     /*   89385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*   89388 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   89392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   89396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89400 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   89404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*   89411 */     // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   89411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*   89414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   89416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   89421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89433 */     GIR_RootConstrainSelectedInstOperands,
     /*   89434 */     // GIR_Coverage, 31120,
     /*   89434 */     GIR_EraseRootFromParent_Done,
     /*   89435 */   // Label 1161: @89435
     /*   89435 */   GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(89496), // Rule ID 30068 //
     /*   89440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*   89443 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89461 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   89465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89472 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89494 */     GIR_RootConstrainSelectedInstOperands,
     /*   89495 */     // GIR_Coverage, 30068,
     /*   89495 */     GIR_EraseRootFromParent_Done,
     /*   89496 */   // Label 1162: @89496
     /*   89496 */   GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(89557), // Rule ID 30069 //
     /*   89501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*   89504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89509 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89522 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   89526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89533 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89555 */     GIR_RootConstrainSelectedInstOperands,
     /*   89556 */     // GIR_Coverage, 30069,
     /*   89556 */     GIR_EraseRootFromParent_Done,
     /*   89557 */   // Label 1163: @89557
     /*   89557 */   GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(89618), // Rule ID 30070 //
     /*   89562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*   89565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89583 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   89587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89594 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89612 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89616 */     GIR_RootConstrainSelectedInstOperands,
     /*   89617 */     // GIR_Coverage, 30070,
     /*   89617 */     GIR_EraseRootFromParent_Done,
     /*   89618 */   // Label 1164: @89618
     /*   89618 */   GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(89679), // Rule ID 30071 //
     /*   89623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*   89626 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89640 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89644 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   89648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89655 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89677 */     GIR_RootConstrainSelectedInstOperands,
     /*   89678 */     // GIR_Coverage, 30071,
     /*   89678 */     GIR_EraseRootFromParent_Done,
     /*   89679 */   // Label 1165: @89679
     /*   89679 */   GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(89740), // Rule ID 30072 //
     /*   89684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*   89687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89705 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   89709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89716 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89738 */     GIR_RootConstrainSelectedInstOperands,
     /*   89739 */     // GIR_Coverage, 30072,
     /*   89739 */     GIR_EraseRootFromParent_Done,
     /*   89740 */   // Label 1166: @89740
     /*   89740 */   GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(89796), // Rule ID 29728 //
     /*   89745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*   89748 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89753 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89772 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89794 */     GIR_RootConstrainSelectedInstOperands,
     /*   89795 */     // GIR_Coverage, 29728,
     /*   89795 */     GIR_EraseRootFromParent_Done,
     /*   89796 */   // Label 1167: @89796
     /*   89796 */   GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(89852), // Rule ID 29729 //
     /*   89801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*   89804 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89809 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89828 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89850 */     GIR_RootConstrainSelectedInstOperands,
     /*   89851 */     // GIR_Coverage, 29729,
     /*   89851 */     GIR_EraseRootFromParent_Done,
     /*   89852 */   // Label 1168: @89852
     /*   89852 */   GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(89908), // Rule ID 29730 //
     /*   89857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*   89860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89865 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89884 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89906 */     GIR_RootConstrainSelectedInstOperands,
     /*   89907 */     // GIR_Coverage, 29730,
     /*   89907 */     GIR_EraseRootFromParent_Done,
     /*   89908 */   // Label 1169: @89908
     /*   89908 */   GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(89964), // Rule ID 29731 //
     /*   89913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*   89916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89921 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89940 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   89945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   89950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   89955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   89958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   89962 */     GIR_RootConstrainSelectedInstOperands,
     /*   89963 */     // GIR_Coverage, 29731,
     /*   89963 */     GIR_EraseRootFromParent_Done,
     /*   89964 */   // Label 1170: @89964
     /*   89964 */   GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(90020), // Rule ID 29732 //
     /*   89969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*   89972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   89977 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   89981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   89985 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   89989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   89996 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   89996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   89999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   90006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   90011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90018 */     GIR_RootConstrainSelectedInstOperands,
     /*   90019 */     // GIR_Coverage, 29732,
     /*   90019 */     GIR_EraseRootFromParent_Done,
     /*   90020 */   // Label 1171: @90020
     /*   90020 */   GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(90079), // Rule ID 31110 //
     /*   90025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*   90028 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90040 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90044 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   90048 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   90055 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*   90055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*   90058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   90065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   90070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90073 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90077 */     GIR_RootConstrainSelectedInstOperands,
     /*   90078 */     // GIR_Coverage, 31110,
     /*   90078 */     GIR_EraseRootFromParent_Done,
     /*   90079 */   // Label 1172: @90079
     /*   90079 */   GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(90143), // Rule ID 31111 //
     /*   90084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   90087 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90099 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90103 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   90107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   90114 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*   90114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   90117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   90124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   90129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*   90137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90141 */     GIR_RootConstrainSelectedInstOperands,
     /*   90142 */     // GIR_Coverage, 31111,
     /*   90142 */     GIR_EraseRootFromParent_Done,
     /*   90143 */   // Label 1173: @90143
     /*   90143 */   GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(90194), // Rule ID 31113 //
     /*   90148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   90151 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90159 */     // MIs[0] sbase
     /*   90159 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*   90163 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   90167 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90171 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   90175 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*   90175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   90178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90180 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*   90182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90192 */     GIR_RootConstrainSelectedInstOperands,
     /*   90193 */     // GIR_Coverage, 31113,
     /*   90193 */     GIR_EraseRootFromParent_Done,
     /*   90194 */   // Label 1174: @90194
     /*   90194 */   GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(90249), // Rule ID 31115 //
     /*   90199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*   90202 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90214 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   90225 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*   90225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*   90228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   90235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   90240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90247 */     GIR_RootConstrainSelectedInstOperands,
     /*   90248 */     // GIR_Coverage, 31115,
     /*   90248 */     GIR_EraseRootFromParent_Done,
     /*   90249 */   // Label 1175: @90249
     /*   90249 */   GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(90309), // Rule ID 31116 //
     /*   90254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   90257 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90269 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   90280 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*   90280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*   90283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   90290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   90295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*   90303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90307 */     GIR_RootConstrainSelectedInstOperands,
     /*   90308 */     // GIR_Coverage, 31116,
     /*   90308 */     GIR_EraseRootFromParent_Done,
     /*   90309 */   // Label 1176: @90309
     /*   90309 */   GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(90356), // Rule ID 31118 //
     /*   90314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   90317 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90325 */     // MIs[0] sbase
     /*   90325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*   90329 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   90333 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90337 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*   90337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*   90340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90342 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*   90344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90354 */     GIR_RootConstrainSelectedInstOperands,
     /*   90355 */     // GIR_Coverage, 31118,
     /*   90355 */     GIR_EraseRootFromParent_Done,
     /*   90356 */   // Label 1177: @90356
     /*   90356 */   GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(90411), // Rule ID 31121 //
     /*   90361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*   90364 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90376 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   90387 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*   90387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*   90390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   90397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   90402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90409 */     GIR_RootConstrainSelectedInstOperands,
     /*   90410 */     // GIR_Coverage, 31121,
     /*   90410 */     GIR_EraseRootFromParent_Done,
     /*   90411 */   // Label 1178: @90411
     /*   90411 */   GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(90471), // Rule ID 31122 //
     /*   90416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   90419 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90431 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   90442 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*   90442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   90445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   90452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   90457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*   90465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90469 */     GIR_RootConstrainSelectedInstOperands,
     /*   90470 */     // GIR_Coverage, 31122,
     /*   90470 */     GIR_EraseRootFromParent_Done,
     /*   90471 */   // Label 1179: @90471
     /*   90471 */   GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(90515), // Rule ID 31124 //
     /*   90476 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   90480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   90484 */     // MIs[0] sbase
     /*   90484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*   90488 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   90492 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   90496 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*   90496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   90499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   90501 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*   90503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90513 */     GIR_RootConstrainSelectedInstOperands,
     /*   90514 */     // GIR_Coverage, 31124,
     /*   90514 */     GIR_EraseRootFromParent_Done,
     /*   90515 */   // Label 1180: @90515
     /*   90515 */   GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(90574), // Rule ID 14482 //
     /*   90520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*   90523 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   90543 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   90543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   90546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   90553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   90558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   90563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   90568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90572 */     GIR_RootConstrainSelectedInstOperands,
     /*   90573 */     // GIR_Coverage, 14482,
     /*   90573 */     GIR_EraseRootFromParent_Done,
     /*   90574 */   // Label 1181: @90574
     /*   90574 */   GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(90633), // Rule ID 14483 //
     /*   90579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*   90582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   90602 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   90602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   90605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   90612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   90617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   90622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   90627 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90631 */     GIR_RootConstrainSelectedInstOperands,
     /*   90632 */     // GIR_Coverage, 14483,
     /*   90632 */     GIR_EraseRootFromParent_Done,
     /*   90633 */   // Label 1182: @90633
     /*   90633 */   GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(90692), // Rule ID 14484 //
     /*   90638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*   90641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   90661 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   90661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   90664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   90671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   90676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   90681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   90686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90690 */     GIR_RootConstrainSelectedInstOperands,
     /*   90691 */     // GIR_Coverage, 14484,
     /*   90691 */     GIR_EraseRootFromParent_Done,
     /*   90692 */   // Label 1183: @90692
     /*   90692 */   GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(90751), // Rule ID 14485 //
     /*   90697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*   90700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   90720 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   90720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   90723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   90730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   90735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   90740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   90745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90749 */     GIR_RootConstrainSelectedInstOperands,
     /*   90750 */     // GIR_Coverage, 14485,
     /*   90750 */     GIR_EraseRootFromParent_Done,
     /*   90751 */   // Label 1184: @90751
     /*   90751 */   GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(90810), // Rule ID 14486 //
     /*   90756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*   90759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90768 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   90779 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   90779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   90782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   90789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   90794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   90799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   90804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90808 */     GIR_RootConstrainSelectedInstOperands,
     /*   90809 */     // GIR_Coverage, 14486,
     /*   90809 */     GIR_EraseRootFromParent_Done,
     /*   90810 */   // Label 1185: @90810
     /*   90810 */   GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(90862), // Rule ID 14477 //
     /*   90815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*   90818 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   90838 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   90838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   90841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   90848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   90853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90860 */     GIR_RootConstrainSelectedInstOperands,
     /*   90861 */     // GIR_Coverage, 14477,
     /*   90861 */     GIR_EraseRootFromParent_Done,
     /*   90862 */   // Label 1186: @90862
     /*   90862 */   GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(90914), // Rule ID 14478 //
     /*   90867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*   90870 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90883 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   90890 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   90890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   90893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   90900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   90905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90912 */     GIR_RootConstrainSelectedInstOperands,
     /*   90913 */     // GIR_Coverage, 14478,
     /*   90913 */     GIR_EraseRootFromParent_Done,
     /*   90914 */   // Label 1187: @90914
     /*   90914 */   GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(90966), // Rule ID 14479 //
     /*   90919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*   90922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   90942 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   90942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   90945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   90952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   90957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   90960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   90964 */     GIR_RootConstrainSelectedInstOperands,
     /*   90965 */     // GIR_Coverage, 14479,
     /*   90965 */     GIR_EraseRootFromParent_Done,
     /*   90966 */   // Label 1188: @90966
     /*   90966 */   GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(91018), // Rule ID 14480 //
     /*   90971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*   90974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   90979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   90983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   90987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   90994 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   90994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   90997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   90999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   91004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91012 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91016 */     GIR_RootConstrainSelectedInstOperands,
     /*   91017 */     // GIR_Coverage, 14480,
     /*   91017 */     GIR_EraseRootFromParent_Done,
     /*   91018 */   // Label 1189: @91018
     /*   91018 */   GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(91070), // Rule ID 14481 //
     /*   91023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*   91026 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   91031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   91046 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   91046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   91049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   91051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   91056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91068 */     GIR_RootConstrainSelectedInstOperands,
     /*   91069 */     // GIR_Coverage, 14481,
     /*   91069 */     GIR_EraseRootFromParent_Done,
     /*   91070 */   // Label 1190: @91070
     /*   91070 */   GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(91122), // Rule ID 14472 //
     /*   91075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*   91078 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   91083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91087 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   91098 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   91098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   91101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   91103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   91108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91120 */     GIR_RootConstrainSelectedInstOperands,
     /*   91121 */     // GIR_Coverage, 14472,
     /*   91121 */     GIR_EraseRootFromParent_Done,
     /*   91122 */   // Label 1191: @91122
     /*   91122 */   GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(91174), // Rule ID 14473 //
     /*   91127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*   91130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   91135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   91150 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   91150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   91153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   91155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   91160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91172 */     GIR_RootConstrainSelectedInstOperands,
     /*   91173 */     // GIR_Coverage, 14473,
     /*   91173 */     GIR_EraseRootFromParent_Done,
     /*   91174 */   // Label 1192: @91174
     /*   91174 */   GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(91226), // Rule ID 14474 //
     /*   91179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*   91182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   91187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   91202 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   91202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   91205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   91207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   91212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91224 */     GIR_RootConstrainSelectedInstOperands,
     /*   91225 */     // GIR_Coverage, 14474,
     /*   91225 */     GIR_EraseRootFromParent_Done,
     /*   91226 */   // Label 1193: @91226
     /*   91226 */   GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(91278), // Rule ID 14475 //
     /*   91231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*   91234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   91239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   91254 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   91254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   91257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   91259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   91264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91276 */     GIR_RootConstrainSelectedInstOperands,
     /*   91277 */     // GIR_Coverage, 14475,
     /*   91277 */     GIR_EraseRootFromParent_Done,
     /*   91278 */   // Label 1194: @91278
     /*   91278 */   GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(91330), // Rule ID 14476 //
     /*   91283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*   91286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   91291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   91306 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   91306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   91309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   91311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   91316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   91321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91328 */     GIR_RootConstrainSelectedInstOperands,
     /*   91329 */     // GIR_Coverage, 14476,
     /*   91329 */     GIR_EraseRootFromParent_Done,
     /*   91330 */   // Label 1195: @91330
     /*   91330 */   GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(91397), // Rule ID 15648 //
     /*   91335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*   91338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91360 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   91363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91395 */     GIR_RootConstrainSelectedInstOperands,
     /*   91396 */     // GIR_Coverage, 15648,
     /*   91396 */     GIR_EraseRootFromParent_Done,
     /*   91397 */   // Label 1196: @91397
     /*   91397 */   GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(91464), // Rule ID 15649 //
     /*   91402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*   91405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91427 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   91430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91462 */     GIR_RootConstrainSelectedInstOperands,
     /*   91463 */     // GIR_Coverage, 15649,
     /*   91463 */     GIR_EraseRootFromParent_Done,
     /*   91464 */   // Label 1197: @91464
     /*   91464 */   GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(91531), // Rule ID 15650 //
     /*   91469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*   91472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91494 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   91497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91529 */     GIR_RootConstrainSelectedInstOperands,
     /*   91530 */     // GIR_Coverage, 15650,
     /*   91530 */     GIR_EraseRootFromParent_Done,
     /*   91531 */   // Label 1198: @91531
     /*   91531 */   GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(91598), // Rule ID 15651 //
     /*   91536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*   91539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91561 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   91564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91596 */     GIR_RootConstrainSelectedInstOperands,
     /*   91597 */     // GIR_Coverage, 15651,
     /*   91597 */     GIR_EraseRootFromParent_Done,
     /*   91598 */   // Label 1199: @91598
     /*   91598 */   GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(91665), // Rule ID 15652 //
     /*   91603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*   91606 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91628 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   91631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91663 */     GIR_RootConstrainSelectedInstOperands,
     /*   91664 */     // GIR_Coverage, 15652,
     /*   91664 */     GIR_EraseRootFromParent_Done,
     /*   91665 */   // Label 1200: @91665
     /*   91665 */   GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(91732), // Rule ID 15658 //
     /*   91670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   91673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91695 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   91698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91730 */     GIR_RootConstrainSelectedInstOperands,
     /*   91731 */     // GIR_Coverage, 15658,
     /*   91731 */     GIR_EraseRootFromParent_Done,
     /*   91732 */   // Label 1201: @91732
     /*   91732 */   GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(91799), // Rule ID 15659 //
     /*   91737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   91740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91762 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   91765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91790 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91793 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91797 */     GIR_RootConstrainSelectedInstOperands,
     /*   91798 */     // GIR_Coverage, 15659,
     /*   91798 */     GIR_EraseRootFromParent_Done,
     /*   91799 */   // Label 1202: @91799
     /*   91799 */   GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(91866), // Rule ID 15660 //
     /*   91804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   91807 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91829 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   91832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91864 */     GIR_RootConstrainSelectedInstOperands,
     /*   91865 */     // GIR_Coverage, 15660,
     /*   91865 */     GIR_EraseRootFromParent_Done,
     /*   91866 */   // Label 1203: @91866
     /*   91866 */   GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(91933), // Rule ID 15661 //
     /*   91871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   91874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91896 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   91899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91927 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91931 */     GIR_RootConstrainSelectedInstOperands,
     /*   91932 */     // GIR_Coverage, 15661,
     /*   91932 */     GIR_EraseRootFromParent_Done,
     /*   91933 */   // Label 1204: @91933
     /*   91933 */   GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(92000), // Rule ID 15662 //
     /*   91938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   91941 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   91948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   91952 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   91956 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   91963 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   91963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   91966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   91968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   91973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   91978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   91983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   91988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   91994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   91998 */     GIR_RootConstrainSelectedInstOperands,
     /*   91999 */     // GIR_Coverage, 15662,
     /*   91999 */     GIR_EraseRootFromParent_Done,
     /*   92000 */   // Label 1205: @92000
     /*   92000 */   GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(92061), // Rule ID 29467 //
     /*   92005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*   92008 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   92012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92021 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92025 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   92032 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   92032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   92035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   92037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   92042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   92047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   92052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92055 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92059 */     GIR_RootConstrainSelectedInstOperands,
     /*   92060 */     // GIR_Coverage, 29467,
     /*   92060 */     GIR_EraseRootFromParent_Done,
     /*   92061 */   // Label 1206: @92061
     /*   92061 */   GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(92122), // Rule ID 29468 //
     /*   92066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*   92069 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   92073 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   92093 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   92093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   92096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   92098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   92103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   92108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   92113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92120 */     GIR_RootConstrainSelectedInstOperands,
     /*   92121 */     // GIR_Coverage, 29468,
     /*   92121 */     GIR_EraseRootFromParent_Done,
     /*   92122 */   // Label 1207: @92122
     /*   92122 */   GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(92183), // Rule ID 29469 //
     /*   92127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*   92130 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   92134 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   92154 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   92154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   92157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   92159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   92164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   92169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   92174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92181 */     GIR_RootConstrainSelectedInstOperands,
     /*   92182 */     // GIR_Coverage, 29469,
     /*   92182 */     GIR_EraseRootFromParent_Done,
     /*   92183 */   // Label 1208: @92183
     /*   92183 */   GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(92244), // Rule ID 29470 //
     /*   92188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*   92191 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   92195 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92204 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92208 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   92215 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   92215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   92218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   92220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   92225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   92230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   92235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92242 */     GIR_RootConstrainSelectedInstOperands,
     /*   92243 */     // GIR_Coverage, 29470,
     /*   92243 */     GIR_EraseRootFromParent_Done,
     /*   92244 */   // Label 1209: @92244
     /*   92244 */   GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(92305), // Rule ID 29471 //
     /*   92249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*   92252 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   92256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   92276 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   92276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   92279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   92281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   92286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   92291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   92296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92303 */     GIR_RootConstrainSelectedInstOperands,
     /*   92304 */     // GIR_Coverage, 29471,
     /*   92304 */     GIR_EraseRootFromParent_Done,
     /*   92305 */   // Label 1210: @92305
     /*   92305 */   GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(92367), // Rule ID 15643 //
     /*   92310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*   92313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92335 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   92338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92365 */     GIR_RootConstrainSelectedInstOperands,
     /*   92366 */     // GIR_Coverage, 15643,
     /*   92366 */     GIR_EraseRootFromParent_Done,
     /*   92367 */   // Label 1211: @92367
     /*   92367 */   GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(92429), // Rule ID 15644 //
     /*   92372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*   92375 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92397 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   92400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92427 */     GIR_RootConstrainSelectedInstOperands,
     /*   92428 */     // GIR_Coverage, 15644,
     /*   92428 */     GIR_EraseRootFromParent_Done,
     /*   92429 */   // Label 1212: @92429
     /*   92429 */   GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(92491), // Rule ID 15645 //
     /*   92434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*   92437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92459 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   92462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92482 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92485 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92489 */     GIR_RootConstrainSelectedInstOperands,
     /*   92490 */     // GIR_Coverage, 15645,
     /*   92490 */     GIR_EraseRootFromParent_Done,
     /*   92491 */   // Label 1213: @92491
     /*   92491 */   GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(92553), // Rule ID 15646 //
     /*   92496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*   92499 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92510 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92521 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   92524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92551 */     GIR_RootConstrainSelectedInstOperands,
     /*   92552 */     // GIR_Coverage, 15646,
     /*   92552 */     GIR_EraseRootFromParent_Done,
     /*   92553 */   // Label 1214: @92553
     /*   92553 */   GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(92615), // Rule ID 15647 //
     /*   92558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*   92561 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92583 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   92586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92613 */     GIR_RootConstrainSelectedInstOperands,
     /*   92614 */     // GIR_Coverage, 15647,
     /*   92614 */     GIR_EraseRootFromParent_Done,
     /*   92615 */   // Label 1215: @92615
     /*   92615 */   GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(92677), // Rule ID 15653 //
     /*   92620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   92623 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92638 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92645 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   92648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92675 */     GIR_RootConstrainSelectedInstOperands,
     /*   92676 */     // GIR_Coverage, 15653,
     /*   92676 */     GIR_EraseRootFromParent_Done,
     /*   92677 */   // Label 1216: @92677
     /*   92677 */   GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(92739), // Rule ID 15654 //
     /*   92682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   92685 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92707 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   92710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92737 */     GIR_RootConstrainSelectedInstOperands,
     /*   92738 */     // GIR_Coverage, 15654,
     /*   92738 */     GIR_EraseRootFromParent_Done,
     /*   92739 */   // Label 1217: @92739
     /*   92739 */   GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(92801), // Rule ID 15655 //
     /*   92744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   92747 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92769 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   92772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92799 */     GIR_RootConstrainSelectedInstOperands,
     /*   92800 */     // GIR_Coverage, 15655,
     /*   92800 */     GIR_EraseRootFromParent_Done,
     /*   92801 */   // Label 1218: @92801
     /*   92801 */   GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(92863), // Rule ID 15656 //
     /*   92806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   92809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92820 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92824 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92831 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   92834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92861 */     GIR_RootConstrainSelectedInstOperands,
     /*   92862 */     // GIR_Coverage, 15656,
     /*   92862 */     GIR_EraseRootFromParent_Done,
     /*   92863 */   // Label 1219: @92863
     /*   92863 */   GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(92925), // Rule ID 15657 //
     /*   92868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   92871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   92878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92882 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92886 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   92893 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   92893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   92896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   92898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   92903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   92908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   92913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92923 */     GIR_RootConstrainSelectedInstOperands,
     /*   92924 */     // GIR_Coverage, 15657,
     /*   92924 */     GIR_EraseRootFromParent_Done,
     /*   92925 */   // Label 1220: @92925
     /*   92925 */   GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(92982), // Rule ID 29473 //
     /*   92930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*   92933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   92946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   92953 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   92953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   92956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   92958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   92963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   92968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   92973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   92976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   92980 */     GIR_RootConstrainSelectedInstOperands,
     /*   92981 */     // GIR_Coverage, 29473,
     /*   92981 */     GIR_EraseRootFromParent_Done,
     /*   92982 */   // Label 1221: @92982
     /*   92982 */   GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(93039), // Rule ID 29474 //
     /*   92987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*   92990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   92995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   92999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   93010 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   93010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   93013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   93020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   93025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   93030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93033 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93037 */     GIR_RootConstrainSelectedInstOperands,
     /*   93038 */     // GIR_Coverage, 29474,
     /*   93038 */     GIR_EraseRootFromParent_Done,
     /*   93039 */   // Label 1222: @93039
     /*   93039 */   GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(93096), // Rule ID 29475 //
     /*   93044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*   93047 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   93052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   93067 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   93067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   93070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   93077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   93082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   93087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93094 */     GIR_RootConstrainSelectedInstOperands,
     /*   93095 */     // GIR_Coverage, 29475,
     /*   93095 */     GIR_EraseRootFromParent_Done,
     /*   93096 */   // Label 1223: @93096
     /*   93096 */   GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(93153), // Rule ID 29476 //
     /*   93101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*   93104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   93109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   93124 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   93124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   93127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   93134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   93139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   93144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93151 */     GIR_RootConstrainSelectedInstOperands,
     /*   93152 */     // GIR_Coverage, 29476,
     /*   93152 */     GIR_EraseRootFromParent_Done,
     /*   93153 */   // Label 1224: @93153
     /*   93153 */   GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(93210), // Rule ID 29477 //
     /*   93158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*   93161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   93166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   93181 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   93181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   93184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   93191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   93196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   93201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93208 */     GIR_RootConstrainSelectedInstOperands,
     /*   93209 */     // GIR_Coverage, 29477,
     /*   93209 */     GIR_EraseRootFromParent_Done,
     /*   93210 */   // Label 1225: @93210
     /*   93210 */   GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(93271), // Rule ID 12383 //
     /*   93215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*   93218 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93240 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   93243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93269 */     GIR_RootConstrainSelectedInstOperands,
     /*   93270 */     // GIR_Coverage, 12383,
     /*   93270 */     GIR_EraseRootFromParent_Done,
     /*   93271 */   // Label 1226: @93271
     /*   93271 */   GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(93332), // Rule ID 12384 //
     /*   93276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*   93279 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93290 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93294 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93301 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   93304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93330 */     GIR_RootConstrainSelectedInstOperands,
     /*   93331 */     // GIR_Coverage, 12384,
     /*   93331 */     GIR_EraseRootFromParent_Done,
     /*   93332 */   // Label 1227: @93332
     /*   93332 */   GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(93393), // Rule ID 12385 //
     /*   93337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*   93340 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93351 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93362 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   93365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93391 */     GIR_RootConstrainSelectedInstOperands,
     /*   93392 */     // GIR_Coverage, 12385,
     /*   93392 */     GIR_EraseRootFromParent_Done,
     /*   93393 */   // Label 1228: @93393
     /*   93393 */   GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(93454), // Rule ID 12386 //
     /*   93398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*   93401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93423 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   93426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93452 */     GIR_RootConstrainSelectedInstOperands,
     /*   93453 */     // GIR_Coverage, 12386,
     /*   93453 */     GIR_EraseRootFromParent_Done,
     /*   93454 */   // Label 1229: @93454
     /*   93454 */   GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(93515), // Rule ID 12387 //
     /*   93459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*   93462 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93484 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   93487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93513 */     GIR_RootConstrainSelectedInstOperands,
     /*   93514 */     // GIR_Coverage, 12387,
     /*   93514 */     GIR_EraseRootFromParent_Done,
     /*   93515 */   // Label 1230: @93515
     /*   93515 */   GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(93569), // Rule ID 12378 //
     /*   93520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*   93523 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   93545 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   93545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   93548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   93555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   93560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93567 */     GIR_RootConstrainSelectedInstOperands,
     /*   93568 */     // GIR_Coverage, 12378,
     /*   93568 */     GIR_EraseRootFromParent_Done,
     /*   93569 */   // Label 1231: @93569
     /*   93569 */   GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(93623), // Rule ID 12379 //
     /*   93574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*   93577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   93599 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   93599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   93602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   93609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   93614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93621 */     GIR_RootConstrainSelectedInstOperands,
     /*   93622 */     // GIR_Coverage, 12379,
     /*   93622 */     GIR_EraseRootFromParent_Done,
     /*   93623 */   // Label 1232: @93623
     /*   93623 */   GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(93677), // Rule ID 12380 //
     /*   93628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*   93631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   93653 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   93653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   93656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   93663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   93668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93675 */     GIR_RootConstrainSelectedInstOperands,
     /*   93676 */     // GIR_Coverage, 12380,
     /*   93676 */     GIR_EraseRootFromParent_Done,
     /*   93677 */   // Label 1233: @93677
     /*   93677 */   GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(93731), // Rule ID 12381 //
     /*   93682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*   93685 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   93707 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   93707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   93710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   93717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   93722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93729 */     GIR_RootConstrainSelectedInstOperands,
     /*   93730 */     // GIR_Coverage, 12381,
     /*   93730 */     GIR_EraseRootFromParent_Done,
     /*   93731 */   // Label 1234: @93731
     /*   93731 */   GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(93785), // Rule ID 12382 //
     /*   93736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*   93739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93754 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   93761 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   93761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   93764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   93771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   93776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   93779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93783 */     GIR_RootConstrainSelectedInstOperands,
     /*   93784 */     // GIR_Coverage, 12382,
     /*   93784 */     GIR_EraseRootFromParent_Done,
     /*   93785 */   // Label 1235: @93785
     /*   93785 */   GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(93847), // Rule ID 10251 //
     /*   93790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*   93793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93816 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   93819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93845 */     GIR_RootConstrainSelectedInstOperands,
     /*   93846 */     // GIR_Coverage, 10251,
     /*   93846 */     GIR_EraseRootFromParent_Done,
     /*   93847 */   // Label 1236: @93847
     /*   93847 */   GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(93909), // Rule ID 10252 //
     /*   93852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*   93855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93878 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   93881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93903 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93907 */     GIR_RootConstrainSelectedInstOperands,
     /*   93908 */     // GIR_Coverage, 10252,
     /*   93908 */     GIR_EraseRootFromParent_Done,
     /*   93909 */   // Label 1237: @93909
     /*   93909 */   GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(93971), // Rule ID 10253 //
     /*   93914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*   93917 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   93940 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   93940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   93943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   93945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   93950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   93955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   93960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   93965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   93969 */     GIR_RootConstrainSelectedInstOperands,
     /*   93970 */     // GIR_Coverage, 10253,
     /*   93970 */     GIR_EraseRootFromParent_Done,
     /*   93971 */   // Label 1238: @93971
     /*   93971 */   GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(94033), // Rule ID 10254 //
     /*   93976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*   93979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   93987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   93991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   93995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   94002 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   94002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   94005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   94012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   94017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   94022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   94027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94031 */     GIR_RootConstrainSelectedInstOperands,
     /*   94032 */     // GIR_Coverage, 10254,
     /*   94032 */     GIR_EraseRootFromParent_Done,
     /*   94033 */   // Label 1239: @94033
     /*   94033 */   GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(94095), // Rule ID 10255 //
     /*   94038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*   94041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   94049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   94064 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   94064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   94067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   94074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   94079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   94084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   94089 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94093 */     GIR_RootConstrainSelectedInstOperands,
     /*   94094 */     // GIR_Coverage, 10255,
     /*   94094 */     GIR_EraseRootFromParent_Done,
     /*   94095 */   // Label 1240: @94095
     /*   94095 */   GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(94150), // Rule ID 10246 //
     /*   94100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*   94103 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   94111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*   94126 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   94126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*   94129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   94136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94148 */     GIR_RootConstrainSelectedInstOperands,
     /*   94149 */     // GIR_Coverage, 10246,
     /*   94149 */     GIR_EraseRootFromParent_Done,
     /*   94150 */   // Label 1241: @94150
     /*   94150 */   GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(94205), // Rule ID 10247 //
     /*   94155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*   94158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   94166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*   94181 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   94181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*   94184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   94191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94203 */     GIR_RootConstrainSelectedInstOperands,
     /*   94204 */     // GIR_Coverage, 10247,
     /*   94204 */     GIR_EraseRootFromParent_Done,
     /*   94205 */   // Label 1242: @94205
     /*   94205 */   GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(94260), // Rule ID 10248 //
     /*   94210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*   94213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   94221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*   94236 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   94236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*   94239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   94246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94258 */     GIR_RootConstrainSelectedInstOperands,
     /*   94259 */     // GIR_Coverage, 10248,
     /*   94259 */     GIR_EraseRootFromParent_Done,
     /*   94260 */   // Label 1243: @94260
     /*   94260 */   GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(94315), // Rule ID 10249 //
     /*   94265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*   94268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   94276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*   94291 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   94291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*   94294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   94301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94313 */     GIR_RootConstrainSelectedInstOperands,
     /*   94314 */     // GIR_Coverage, 10249,
     /*   94314 */     GIR_EraseRootFromParent_Done,
     /*   94315 */   // Label 1244: @94315
     /*   94315 */   GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(94370), // Rule ID 10250 //
     /*   94320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*   94323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   94331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*   94346 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   94346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*   94349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   94356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94368 */     GIR_RootConstrainSelectedInstOperands,
     /*   94369 */     // GIR_Coverage, 10250,
     /*   94369 */     GIR_EraseRootFromParent_Done,
     /*   94370 */   // Label 1245: @94370
     /*   94370 */   GIM_Reject,
     /*   94371 */ // Label 1143: @94371
     /*   94371 */ GIM_Reject,
     /*   94372 */ // Label 1119: @94372
     /*   94372 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(100411),
     /*   94377 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*   94380 */   GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(94446), // Rule ID 31129 //
     /*   94385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   94388 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   94396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94400 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   94404 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   94408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*   94415 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   94415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   94418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   94420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   94425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   94430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   94435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   94440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94444 */     GIR_RootConstrainSelectedInstOperands,
     /*   94445 */     // GIR_Coverage, 31129,
     /*   94445 */     GIR_EraseRootFromParent_Done,
     /*   94446 */   // Label 1247: @94446
     /*   94446 */   GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(94508), // Rule ID 31134 //
     /*   94451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   94454 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   94462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94466 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   94470 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*   94477 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   94477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*   94480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   94482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   94487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   94492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   94497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   94502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94506 */     GIR_RootConstrainSelectedInstOperands,
     /*   94507 */     // GIR_Coverage, 31134,
     /*   94507 */     GIR_EraseRootFromParent_Done,
     /*   94508 */   // Label 1248: @94508
     /*   94508 */   GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(94570), // Rule ID 31140 //
     /*   94513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   94516 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   94524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94528 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   94532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*   94539 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   94539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   94542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   94544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   94549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   94554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   94559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   94564 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94568 */     GIR_RootConstrainSelectedInstOperands,
     /*   94569 */     // GIR_Coverage, 31140,
     /*   94569 */     GIR_EraseRootFromParent_Done,
     /*   94570 */   // Label 1249: @94570
     /*   94570 */   GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(94629), // Rule ID 31125 //
     /*   94575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   94578 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   94586 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94590 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   94594 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   94598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*   94605 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   94605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   94608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   94610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   94615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94627 */     GIR_RootConstrainSelectedInstOperands,
     /*   94628 */     // GIR_Coverage, 31125,
     /*   94628 */     GIR_EraseRootFromParent_Done,
     /*   94629 */   // Label 1250: @94629
     /*   94629 */   GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(94688), // Rule ID 31126 //
     /*   94634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*   94637 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   94645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94649 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   94653 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   94657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*   94664 */     // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   94664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*   94667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   94669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   94674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94686 */     GIR_RootConstrainSelectedInstOperands,
     /*   94687 */     // GIR_Coverage, 31126,
     /*   94687 */     GIR_EraseRootFromParent_Done,
     /*   94688 */   // Label 1251: @94688
     /*   94688 */   GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(94743), // Rule ID 31131 //
     /*   94693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   94696 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   94704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94708 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   94712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*   94719 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   94719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*   94722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   94724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   94729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94741 */     GIR_RootConstrainSelectedInstOperands,
     /*   94742 */     // GIR_Coverage, 31131,
     /*   94742 */     GIR_EraseRootFromParent_Done,
     /*   94743 */   // Label 1252: @94743
     /*   94743 */   GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(94808), // Rule ID 30083 //
     /*   94748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*   94751 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94773 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   94777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   94784 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   94784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   94787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   94794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94806 */     GIR_RootConstrainSelectedInstOperands,
     /*   94807 */     // GIR_Coverage, 30083,
     /*   94807 */     GIR_EraseRootFromParent_Done,
     /*   94808 */   // Label 1253: @94808
     /*   94808 */   GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(94873), // Rule ID 30084 //
     /*   94813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*   94816 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94838 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   94842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   94849 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   94849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   94852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   94859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94867 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94871 */     GIR_RootConstrainSelectedInstOperands,
     /*   94872 */     // GIR_Coverage, 30084,
     /*   94872 */     GIR_EraseRootFromParent_Done,
     /*   94873 */   // Label 1254: @94873
     /*   94873 */   GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(94938), // Rule ID 30085 //
     /*   94878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*   94881 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94903 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   94907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   94914 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   94914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   94917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   94924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   94936 */     GIR_RootConstrainSelectedInstOperands,
     /*   94937 */     // GIR_Coverage, 30085,
     /*   94937 */     GIR_EraseRootFromParent_Done,
     /*   94938 */   // Label 1255: @94938
     /*   94938 */   GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(95003), // Rule ID 30086 //
     /*   94943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*   94946 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   94950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   94960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   94964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   94968 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   94972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   94979 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   94979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   94982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   94984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   94989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   94994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   94997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95001 */     GIR_RootConstrainSelectedInstOperands,
     /*   95002 */     // GIR_Coverage, 30086,
     /*   95002 */     GIR_EraseRootFromParent_Done,
     /*   95003 */   // Label 1256: @95003
     /*   95003 */   GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(95068), // Rule ID 30087 //
     /*   95008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*   95011 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95033 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*   95037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95044 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   95047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95066 */     GIR_RootConstrainSelectedInstOperands,
     /*   95067 */     // GIR_Coverage, 30087,
     /*   95067 */     GIR_EraseRootFromParent_Done,
     /*   95068 */   // Label 1257: @95068
     /*   95068 */   GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(95128), // Rule ID 29743 //
     /*   95073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*   95076 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95080 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95085 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95104 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   95107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95126 */     GIR_RootConstrainSelectedInstOperands,
     /*   95127 */     // GIR_Coverage, 29743,
     /*   95127 */     GIR_EraseRootFromParent_Done,
     /*   95128 */   // Label 1258: @95128
     /*   95128 */   GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(95188), // Rule ID 29744 //
     /*   95133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*   95136 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95145 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95164 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   95167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95186 */     GIR_RootConstrainSelectedInstOperands,
     /*   95187 */     // GIR_Coverage, 29744,
     /*   95187 */     GIR_EraseRootFromParent_Done,
     /*   95188 */   // Label 1259: @95188
     /*   95188 */   GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(95248), // Rule ID 29745 //
     /*   95193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*   95196 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95205 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95213 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95224 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   95227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95246 */     GIR_RootConstrainSelectedInstOperands,
     /*   95247 */     // GIR_Coverage, 29745,
     /*   95247 */     GIR_EraseRootFromParent_Done,
     /*   95248 */   // Label 1260: @95248
     /*   95248 */   GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(95308), // Rule ID 29746 //
     /*   95253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*   95256 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95265 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95284 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   95287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95306 */     GIR_RootConstrainSelectedInstOperands,
     /*   95307 */     // GIR_Coverage, 29746,
     /*   95307 */     GIR_EraseRootFromParent_Done,
     /*   95308 */   // Label 1261: @95308
     /*   95308 */   GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(95368), // Rule ID 29747 //
     /*   95313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*   95316 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95325 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95337 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95344 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*   95347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95362 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95366 */     GIR_RootConstrainSelectedInstOperands,
     /*   95367 */     // GIR_Coverage, 29747,
     /*   95367 */     GIR_EraseRootFromParent_Done,
     /*   95368 */   // Label 1262: @95368
     /*   95368 */   GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(95420), // Rule ID 31136 //
     /*   95373 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   95381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95385 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   95389 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*   95396 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   95396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   95399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   95401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   95406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95418 */     GIR_RootConstrainSelectedInstOperands,
     /*   95419 */     // GIR_Coverage, 31136,
     /*   95419 */     GIR_EraseRootFromParent_Done,
     /*   95420 */   // Label 1263: @95420
     /*   95420 */   GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(95475), // Rule ID 31137 //
     /*   95425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*   95428 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   95432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   95436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95440 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   95444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*   95451 */     // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*   95451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*   95454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   95456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   95461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95473 */     GIR_RootConstrainSelectedInstOperands,
     /*   95474 */     // GIR_Coverage, 31137,
     /*   95474 */     GIR_EraseRootFromParent_Done,
     /*   95475 */   // Label 1264: @95475
     /*   95475 */   GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(95536), // Rule ID 30088 //
     /*   95480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*   95483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95501 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   95505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95512 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95534 */     GIR_RootConstrainSelectedInstOperands,
     /*   95535 */     // GIR_Coverage, 30088,
     /*   95535 */     GIR_EraseRootFromParent_Done,
     /*   95536 */   // Label 1265: @95536
     /*   95536 */   GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(95597), // Rule ID 30089 //
     /*   95541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*   95544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95562 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   95566 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95573 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95591 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95595 */     GIR_RootConstrainSelectedInstOperands,
     /*   95596 */     // GIR_Coverage, 30089,
     /*   95596 */     GIR_EraseRootFromParent_Done,
     /*   95597 */   // Label 1266: @95597
     /*   95597 */   GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(95658), // Rule ID 30090 //
     /*   95602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*   95605 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95623 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   95627 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95634 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95656 */     GIR_RootConstrainSelectedInstOperands,
     /*   95657 */     // GIR_Coverage, 30090,
     /*   95657 */     GIR_EraseRootFromParent_Done,
     /*   95658 */   // Label 1267: @95658
     /*   95658 */   GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(95719), // Rule ID 30091 //
     /*   95663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*   95666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95684 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   95688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95695 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95717 */     GIR_RootConstrainSelectedInstOperands,
     /*   95718 */     // GIR_Coverage, 30091,
     /*   95718 */     GIR_EraseRootFromParent_Done,
     /*   95719 */   // Label 1268: @95719
     /*   95719 */   GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(95780), // Rule ID 30092 //
     /*   95724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*   95727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95745 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*   95749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95756 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95774 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95778 */     GIR_RootConstrainSelectedInstOperands,
     /*   95779 */     // GIR_Coverage, 30092,
     /*   95779 */     GIR_EraseRootFromParent_Done,
     /*   95780 */   // Label 1269: @95780
     /*   95780 */   GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(95836), // Rule ID 29748 //
     /*   95785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*   95788 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95793 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95812 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95834 */     GIR_RootConstrainSelectedInstOperands,
     /*   95835 */     // GIR_Coverage, 29748,
     /*   95835 */     GIR_EraseRootFromParent_Done,
     /*   95836 */   // Label 1270: @95836
     /*   95836 */   GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(95892), // Rule ID 29749 //
     /*   95841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*   95844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95849 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95857 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95861 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95868 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95886 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95890 */     GIR_RootConstrainSelectedInstOperands,
     /*   95891 */     // GIR_Coverage, 29749,
     /*   95891 */     GIR_EraseRootFromParent_Done,
     /*   95892 */   // Label 1271: @95892
     /*   95892 */   GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(95948), // Rule ID 29750 //
     /*   95897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*   95900 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95905 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95924 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   95946 */     GIR_RootConstrainSelectedInstOperands,
     /*   95947 */     // GIR_Coverage, 29750,
     /*   95947 */     GIR_EraseRootFromParent_Done,
     /*   95948 */   // Label 1272: @95948
     /*   95948 */   GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(96004), // Rule ID 29751 //
     /*   95953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*   95956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   95961 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   95965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   95969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   95973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   95980 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   95980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   95983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   95985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   95990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   95995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   95998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96002 */     GIR_RootConstrainSelectedInstOperands,
     /*   96003 */     // GIR_Coverage, 29751,
     /*   96003 */     GIR_EraseRootFromParent_Done,
     /*   96004 */   // Label 1273: @96004
     /*   96004 */   GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(96060), // Rule ID 29752 //
     /*   96009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*   96012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   96017 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*   96021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96025 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96029 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*   96036 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*   96036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*   96039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   96046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   96051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96058 */     GIR_RootConstrainSelectedInstOperands,
     /*   96059 */     // GIR_Coverage, 29752,
     /*   96059 */     GIR_EraseRootFromParent_Done,
     /*   96060 */   // Label 1274: @96060
     /*   96060 */   GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(96119), // Rule ID 31127 //
     /*   96065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*   96068 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96080 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96084 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   96088 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   96095 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*   96095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*   96098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   96105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   96110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96113 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96117 */     GIR_RootConstrainSelectedInstOperands,
     /*   96118 */     // GIR_Coverage, 31127,
     /*   96118 */     GIR_EraseRootFromParent_Done,
     /*   96119 */   // Label 1275: @96119
     /*   96119 */   GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(96183), // Rule ID 31128 //
     /*   96124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   96127 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96139 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96143 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   96147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   96154 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*   96154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   96157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   96164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   96169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*   96177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96181 */     GIR_RootConstrainSelectedInstOperands,
     /*   96182 */     // GIR_Coverage, 31128,
     /*   96182 */     GIR_EraseRootFromParent_Done,
     /*   96183 */   // Label 1276: @96183
     /*   96183 */   GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(96234), // Rule ID 31130 //
     /*   96188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   96191 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96199 */     // MIs[0] sbase
     /*   96199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*   96203 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   96207 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96211 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*   96215 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*   96215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   96218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96220 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*   96222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96232 */     GIR_RootConstrainSelectedInstOperands,
     /*   96233 */     // GIR_Coverage, 31130,
     /*   96233 */     GIR_EraseRootFromParent_Done,
     /*   96234 */   // Label 1277: @96234
     /*   96234 */   GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(96289), // Rule ID 31132 //
     /*   96239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*   96242 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96254 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   96265 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*   96265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*   96268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   96275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   96280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96287 */     GIR_RootConstrainSelectedInstOperands,
     /*   96288 */     // GIR_Coverage, 31132,
     /*   96288 */     GIR_EraseRootFromParent_Done,
     /*   96289 */   // Label 1278: @96289
     /*   96289 */   GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(96349), // Rule ID 31133 //
     /*   96294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*   96297 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96309 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   96320 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*   96320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*   96323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   96330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   96335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*   96343 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96347 */     GIR_RootConstrainSelectedInstOperands,
     /*   96348 */     // GIR_Coverage, 31133,
     /*   96348 */     GIR_EraseRootFromParent_Done,
     /*   96349 */   // Label 1279: @96349
     /*   96349 */   GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(96396), // Rule ID 31135 //
     /*   96354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*   96357 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96365 */     // MIs[0] sbase
     /*   96365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*   96369 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   96373 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96377 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*   96377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*   96380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96382 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*   96384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96394 */     GIR_RootConstrainSelectedInstOperands,
     /*   96395 */     // GIR_Coverage, 31135,
     /*   96395 */     GIR_EraseRootFromParent_Done,
     /*   96396 */   // Label 1280: @96396
     /*   96396 */   GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(96451), // Rule ID 31138 //
     /*   96401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*   96404 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96416 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   96427 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*   96427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*   96430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   96437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   96442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96449 */     GIR_RootConstrainSelectedInstOperands,
     /*   96450 */     // GIR_Coverage, 31138,
     /*   96450 */     GIR_EraseRootFromParent_Done,
     /*   96451 */   // Label 1281: @96451
     /*   96451 */   GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(96511), // Rule ID 31139 //
     /*   96456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*   96459 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96471 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*   96482 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*   96482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*   96485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*   96492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   96497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*   96505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96509 */     GIR_RootConstrainSelectedInstOperands,
     /*   96510 */     // GIR_Coverage, 31139,
     /*   96510 */     GIR_EraseRootFromParent_Done,
     /*   96511 */   // Label 1282: @96511
     /*   96511 */   GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(96555), // Rule ID 31141 //
     /*   96516 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   96520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*   96524 */     // MIs[0] sbase
     /*   96524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*   96528 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*   96532 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*   96536 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*   96536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*   96539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*   96541 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*   96543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96553 */     GIR_RootConstrainSelectedInstOperands,
     /*   96554 */     // GIR_Coverage, 31141,
     /*   96554 */     GIR_EraseRootFromParent_Done,
     /*   96555 */   // Label 1283: @96555
     /*   96555 */   GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(96614), // Rule ID 14512 //
     /*   96560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*   96563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   96583 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   96583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   96586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   96593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   96598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   96603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   96608 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96612 */     GIR_RootConstrainSelectedInstOperands,
     /*   96613 */     // GIR_Coverage, 14512,
     /*   96613 */     GIR_EraseRootFromParent_Done,
     /*   96614 */   // Label 1284: @96614
     /*   96614 */   GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(96673), // Rule ID 14513 //
     /*   96619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*   96622 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   96642 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   96642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   96645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   96652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   96657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   96662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   96667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96671 */     GIR_RootConstrainSelectedInstOperands,
     /*   96672 */     // GIR_Coverage, 14513,
     /*   96672 */     GIR_EraseRootFromParent_Done,
     /*   96673 */   // Label 1285: @96673
     /*   96673 */   GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(96732), // Rule ID 14514 //
     /*   96678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*   96681 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96690 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   96701 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   96701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   96704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   96711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   96716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   96721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   96726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96730 */     GIR_RootConstrainSelectedInstOperands,
     /*   96731 */     // GIR_Coverage, 14514,
     /*   96731 */     GIR_EraseRootFromParent_Done,
     /*   96732 */   // Label 1286: @96732
     /*   96732 */   GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(96791), // Rule ID 14515 //
     /*   96737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*   96740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96749 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   96760 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   96760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   96763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   96770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   96775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   96780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   96785 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96789 */     GIR_RootConstrainSelectedInstOperands,
     /*   96790 */     // GIR_Coverage, 14515,
     /*   96790 */     GIR_EraseRootFromParent_Done,
     /*   96791 */   // Label 1287: @96791
     /*   96791 */   GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(96850), // Rule ID 14516 //
     /*   96796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*   96799 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96808 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96812 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*   96819 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   96819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*   96822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   96829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*   96834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   96839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   96844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96848 */     GIR_RootConstrainSelectedInstOperands,
     /*   96849 */     // GIR_Coverage, 14516,
     /*   96849 */     GIR_EraseRootFromParent_Done,
     /*   96850 */   // Label 1288: @96850
     /*   96850 */   GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(96902), // Rule ID 14507 //
     /*   96855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*   96858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   96878 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   96878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   96881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   96888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   96893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96900 */     GIR_RootConstrainSelectedInstOperands,
     /*   96901 */     // GIR_Coverage, 14507,
     /*   96901 */     GIR_EraseRootFromParent_Done,
     /*   96902 */   // Label 1289: @96902
     /*   96902 */   GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(96954), // Rule ID 14508 //
     /*   96907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*   96910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   96930 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   96930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   96933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   96940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   96945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   96948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   96952 */     GIR_RootConstrainSelectedInstOperands,
     /*   96953 */     // GIR_Coverage, 14508,
     /*   96953 */     GIR_EraseRootFromParent_Done,
     /*   96954 */   // Label 1290: @96954
     /*   96954 */   GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(97006), // Rule ID 14509 //
     /*   96959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*   96962 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   96967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   96971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   96975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   96982 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   96982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   96985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   96987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   96992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   96997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97004 */     GIR_RootConstrainSelectedInstOperands,
     /*   97005 */     // GIR_Coverage, 14509,
     /*   97005 */     GIR_EraseRootFromParent_Done,
     /*   97006 */   // Label 1291: @97006
     /*   97006 */   GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(97058), // Rule ID 14510 //
     /*   97011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*   97014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   97034 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   97034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   97037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   97044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97056 */     GIR_RootConstrainSelectedInstOperands,
     /*   97057 */     // GIR_Coverage, 14510,
     /*   97057 */     GIR_EraseRootFromParent_Done,
     /*   97058 */   // Label 1292: @97058
     /*   97058 */   GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(97110), // Rule ID 14511 //
     /*   97063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*   97066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*   97086 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*   97086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*   97089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   97096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97104 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97108 */     GIR_RootConstrainSelectedInstOperands,
     /*   97109 */     // GIR_Coverage, 14511,
     /*   97109 */     GIR_EraseRootFromParent_Done,
     /*   97110 */   // Label 1293: @97110
     /*   97110 */   GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(97162), // Rule ID 14502 //
     /*   97115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*   97118 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   97138 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   97138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   97141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   97148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97160 */     GIR_RootConstrainSelectedInstOperands,
     /*   97161 */     // GIR_Coverage, 14502,
     /*   97161 */     GIR_EraseRootFromParent_Done,
     /*   97162 */   // Label 1294: @97162
     /*   97162 */   GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(97214), // Rule ID 14503 //
     /*   97167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*   97170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   97190 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   97190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   97193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   97200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97212 */     GIR_RootConstrainSelectedInstOperands,
     /*   97213 */     // GIR_Coverage, 14503,
     /*   97213 */     GIR_EraseRootFromParent_Done,
     /*   97214 */   // Label 1295: @97214
     /*   97214 */   GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(97266), // Rule ID 14504 //
     /*   97219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*   97222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   97242 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   97242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   97245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   97252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97264 */     GIR_RootConstrainSelectedInstOperands,
     /*   97265 */     // GIR_Coverage, 14504,
     /*   97265 */     GIR_EraseRootFromParent_Done,
     /*   97266 */   // Label 1296: @97266
     /*   97266 */   GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(97318), // Rule ID 14505 //
     /*   97271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*   97274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   97294 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   97294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   97297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   97304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97316 */     GIR_RootConstrainSelectedInstOperands,
     /*   97317 */     // GIR_Coverage, 14505,
     /*   97317 */     GIR_EraseRootFromParent_Done,
     /*   97318 */   // Label 1297: @97318
     /*   97318 */   GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(97370), // Rule ID 14506 //
     /*   97323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*   97326 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*   97331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*   97346 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   97346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*   97349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   97351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   97356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   97361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97368 */     GIR_RootConstrainSelectedInstOperands,
     /*   97369 */     // GIR_Coverage, 14506,
     /*   97369 */     GIR_EraseRootFromParent_Done,
     /*   97370 */   // Label 1298: @97370
     /*   97370 */   GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(97437), // Rule ID 15668 //
     /*   97375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*   97378 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97400 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   97403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97435 */     GIR_RootConstrainSelectedInstOperands,
     /*   97436 */     // GIR_Coverage, 15668,
     /*   97436 */     GIR_EraseRootFromParent_Done,
     /*   97437 */   // Label 1299: @97437
     /*   97437 */   GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(97504), // Rule ID 15669 //
     /*   97442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*   97445 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97467 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   97470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97502 */     GIR_RootConstrainSelectedInstOperands,
     /*   97503 */     // GIR_Coverage, 15669,
     /*   97503 */     GIR_EraseRootFromParent_Done,
     /*   97504 */   // Label 1300: @97504
     /*   97504 */   GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(97571), // Rule ID 15670 //
     /*   97509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*   97512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97534 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   97537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97569 */     GIR_RootConstrainSelectedInstOperands,
     /*   97570 */     // GIR_Coverage, 15670,
     /*   97570 */     GIR_EraseRootFromParent_Done,
     /*   97571 */   // Label 1301: @97571
     /*   97571 */   GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(97638), // Rule ID 15671 //
     /*   97576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*   97579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97601 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   97604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97632 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97636 */     GIR_RootConstrainSelectedInstOperands,
     /*   97637 */     // GIR_Coverage, 15671,
     /*   97637 */     GIR_EraseRootFromParent_Done,
     /*   97638 */   // Label 1302: @97638
     /*   97638 */   GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(97705), // Rule ID 15672 //
     /*   97643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*   97646 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97668 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*   97671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97699 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97703 */     GIR_RootConstrainSelectedInstOperands,
     /*   97704 */     // GIR_Coverage, 15672,
     /*   97704 */     GIR_EraseRootFromParent_Done,
     /*   97705 */   // Label 1303: @97705
     /*   97705 */   GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(97772), // Rule ID 15678 //
     /*   97710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   97713 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97724 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97735 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   97738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97763 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97770 */     GIR_RootConstrainSelectedInstOperands,
     /*   97771 */     // GIR_Coverage, 15678,
     /*   97771 */     GIR_EraseRootFromParent_Done,
     /*   97772 */   // Label 1304: @97772
     /*   97772 */   GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(97839), // Rule ID 15679 //
     /*   97777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   97780 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97802 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   97805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97837 */     GIR_RootConstrainSelectedInstOperands,
     /*   97838 */     // GIR_Coverage, 15679,
     /*   97838 */     GIR_EraseRootFromParent_Done,
     /*   97839 */   // Label 1305: @97839
     /*   97839 */   GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(97906), // Rule ID 15680 //
     /*   97844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   97847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97862 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97869 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   97872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97897 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97904 */     GIR_RootConstrainSelectedInstOperands,
     /*   97905 */     // GIR_Coverage, 15680,
     /*   97905 */     GIR_EraseRootFromParent_Done,
     /*   97906 */   // Label 1306: @97906
     /*   97906 */   GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(97973), // Rule ID 15681 //
     /*   97911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   97914 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   97936 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   97936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   97939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   97941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   97946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   97951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   97956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   97961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   97967 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   97971 */     GIR_RootConstrainSelectedInstOperands,
     /*   97972 */     // GIR_Coverage, 15681,
     /*   97972 */     GIR_EraseRootFromParent_Done,
     /*   97973 */   // Label 1307: @97973
     /*   97973 */   GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(98040), // Rule ID 15682 //
     /*   97978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   97981 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   97988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   97992 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   97996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*   98003 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*   98006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*   98013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*   98023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*   98028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98038 */     GIR_RootConstrainSelectedInstOperands,
     /*   98039 */     // GIR_Coverage, 15682,
     /*   98039 */     GIR_EraseRootFromParent_Done,
     /*   98040 */   // Label 1308: @98040
     /*   98040 */   GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(98101), // Rule ID 29479 //
     /*   98045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*   98048 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   98052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   98057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   98072 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   98072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   98075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   98077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   98082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   98087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   98092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98099 */     GIR_RootConstrainSelectedInstOperands,
     /*   98100 */     // GIR_Coverage, 29479,
     /*   98100 */     GIR_EraseRootFromParent_Done,
     /*   98101 */   // Label 1309: @98101
     /*   98101 */   GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(98162), // Rule ID 29480 //
     /*   98106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*   98109 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   98113 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   98118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   98133 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   98133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   98136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   98138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   98143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   98148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   98153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98160 */     GIR_RootConstrainSelectedInstOperands,
     /*   98161 */     // GIR_Coverage, 29480,
     /*   98161 */     GIR_EraseRootFromParent_Done,
     /*   98162 */   // Label 1310: @98162
     /*   98162 */   GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(98223), // Rule ID 29481 //
     /*   98167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*   98170 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   98174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   98179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   98194 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   98194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   98197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   98199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   98204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   98209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   98214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98217 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98221 */     GIR_RootConstrainSelectedInstOperands,
     /*   98222 */     // GIR_Coverage, 29481,
     /*   98222 */     GIR_EraseRootFromParent_Done,
     /*   98223 */   // Label 1311: @98223
     /*   98223 */   GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(98284), // Rule ID 29482 //
     /*   98228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*   98231 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   98235 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   98240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   98255 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   98255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   98258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   98260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   98265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   98270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   98275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98282 */     GIR_RootConstrainSelectedInstOperands,
     /*   98283 */     // GIR_Coverage, 29482,
     /*   98283 */     GIR_EraseRootFromParent_Done,
     /*   98284 */   // Label 1312: @98284
     /*   98284 */   GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(98345), // Rule ID 29483 //
     /*   98289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*   98292 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*   98296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   98301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   98316 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   98316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*   98319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   98321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   98326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   98331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   98336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98343 */     GIR_RootConstrainSelectedInstOperands,
     /*   98344 */     // GIR_Coverage, 29483,
     /*   98344 */     GIR_EraseRootFromParent_Done,
     /*   98345 */   // Label 1313: @98345
     /*   98345 */   GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(98407), // Rule ID 15663 //
     /*   98350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*   98353 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98375 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   98378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98405 */     GIR_RootConstrainSelectedInstOperands,
     /*   98406 */     // GIR_Coverage, 15663,
     /*   98406 */     GIR_EraseRootFromParent_Done,
     /*   98407 */   // Label 1314: @98407
     /*   98407 */   GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(98469), // Rule ID 15664 //
     /*   98412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*   98415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98437 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   98440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98467 */     GIR_RootConstrainSelectedInstOperands,
     /*   98468 */     // GIR_Coverage, 15664,
     /*   98468 */     GIR_EraseRootFromParent_Done,
     /*   98469 */   // Label 1315: @98469
     /*   98469 */   GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(98531), // Rule ID 15665 //
     /*   98474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*   98477 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98499 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   98502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98529 */     GIR_RootConstrainSelectedInstOperands,
     /*   98530 */     // GIR_Coverage, 15665,
     /*   98530 */     GIR_EraseRootFromParent_Done,
     /*   98531 */   // Label 1316: @98531
     /*   98531 */   GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(98593), // Rule ID 15666 //
     /*   98536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*   98539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98561 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   98564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98591 */     GIR_RootConstrainSelectedInstOperands,
     /*   98592 */     // GIR_Coverage, 15666,
     /*   98592 */     GIR_EraseRootFromParent_Done,
     /*   98593 */   // Label 1317: @98593
     /*   98593 */   GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(98655), // Rule ID 15667 //
     /*   98598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*   98601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98623 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*   98626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98653 */     GIR_RootConstrainSelectedInstOperands,
     /*   98654 */     // GIR_Coverage, 15667,
     /*   98654 */     GIR_EraseRootFromParent_Done,
     /*   98655 */   // Label 1318: @98655
     /*   98655 */   GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(98717), // Rule ID 15673 //
     /*   98660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*   98663 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98685 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   98688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98715 */     GIR_RootConstrainSelectedInstOperands,
     /*   98716 */     // GIR_Coverage, 15673,
     /*   98716 */     GIR_EraseRootFromParent_Done,
     /*   98717 */   // Label 1319: @98717
     /*   98717 */   GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(98779), // Rule ID 15674 //
     /*   98722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*   98725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98747 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   98750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98773 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98777 */     GIR_RootConstrainSelectedInstOperands,
     /*   98778 */     // GIR_Coverage, 15674,
     /*   98778 */     GIR_EraseRootFromParent_Done,
     /*   98779 */   // Label 1320: @98779
     /*   98779 */   GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(98841), // Rule ID 15675 //
     /*   98784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*   98787 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98809 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   98812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98839 */     GIR_RootConstrainSelectedInstOperands,
     /*   98840 */     // GIR_Coverage, 15675,
     /*   98840 */     GIR_EraseRootFromParent_Done,
     /*   98841 */   // Label 1321: @98841
     /*   98841 */   GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(98903), // Rule ID 15676 //
     /*   98846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*   98849 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98860 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98871 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   98874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98901 */     GIR_RootConstrainSelectedInstOperands,
     /*   98902 */     // GIR_Coverage, 15676,
     /*   98902 */     GIR_EraseRootFromParent_Done,
     /*   98903 */   // Label 1322: @98903
     /*   98903 */   GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(98965), // Rule ID 15677 //
     /*   98908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*   98911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   98918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*   98933 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*   98933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*   98936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*   98938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*   98943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*   98948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   98953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   98959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   98963 */     GIR_RootConstrainSelectedInstOperands,
     /*   98964 */     // GIR_Coverage, 15677,
     /*   98964 */     GIR_EraseRootFromParent_Done,
     /*   98965 */   // Label 1323: @98965
     /*   98965 */   GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(99022), // Rule ID 29485 //
     /*   98970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*   98973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   98978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   98982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   98986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   98993 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   98993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   98996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   98998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   99003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   99008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   99013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99020 */     GIR_RootConstrainSelectedInstOperands,
     /*   99021 */     // GIR_Coverage, 29485,
     /*   99021 */     GIR_EraseRootFromParent_Done,
     /*   99022 */   // Label 1324: @99022
     /*   99022 */   GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(99079), // Rule ID 29486 //
     /*   99027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*   99030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   99035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   99050 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   99050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   99053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   99060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   99065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   99070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99073 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99077 */     GIR_RootConstrainSelectedInstOperands,
     /*   99078 */     // GIR_Coverage, 29486,
     /*   99078 */     GIR_EraseRootFromParent_Done,
     /*   99079 */   // Label 1325: @99079
     /*   99079 */   GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(99136), // Rule ID 29487 //
     /*   99084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*   99087 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   99092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99096 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99100 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   99107 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   99107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   99110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   99117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   99122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   99127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99134 */     GIR_RootConstrainSelectedInstOperands,
     /*   99135 */     // GIR_Coverage, 29487,
     /*   99135 */     GIR_EraseRootFromParent_Done,
     /*   99136 */   // Label 1326: @99136
     /*   99136 */   GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(99193), // Rule ID 29488 //
     /*   99141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*   99144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   99149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   99164 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   99164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   99167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   99174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   99179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   99184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99191 */     GIR_RootConstrainSelectedInstOperands,
     /*   99192 */     // GIR_Coverage, 29488,
     /*   99192 */     GIR_EraseRootFromParent_Done,
     /*   99193 */   // Label 1327: @99193
     /*   99193 */   GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(99250), // Rule ID 29489 //
     /*   99198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*   99201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*   99206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*   99221 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*   99221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*   99224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*   99231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*   99236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*   99241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99248 */     GIR_RootConstrainSelectedInstOperands,
     /*   99249 */     // GIR_Coverage, 29489,
     /*   99249 */     GIR_EraseRootFromParent_Done,
     /*   99250 */   // Label 1328: @99250
     /*   99250 */   GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(99311), // Rule ID 12403 //
     /*   99255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*   99258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99280 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   99283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99309 */     GIR_RootConstrainSelectedInstOperands,
     /*   99310 */     // GIR_Coverage, 12403,
     /*   99310 */     GIR_EraseRootFromParent_Done,
     /*   99311 */   // Label 1329: @99311
     /*   99311 */   GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(99372), // Rule ID 12404 //
     /*   99316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*   99319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99341 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   99344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99370 */     GIR_RootConstrainSelectedInstOperands,
     /*   99371 */     // GIR_Coverage, 12404,
     /*   99371 */     GIR_EraseRootFromParent_Done,
     /*   99372 */   // Label 1330: @99372
     /*   99372 */   GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(99433), // Rule ID 12405 //
     /*   99377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*   99380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99402 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   99405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99431 */     GIR_RootConstrainSelectedInstOperands,
     /*   99432 */     // GIR_Coverage, 12405,
     /*   99432 */     GIR_EraseRootFromParent_Done,
     /*   99433 */   // Label 1331: @99433
     /*   99433 */   GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(99494), // Rule ID 12406 //
     /*   99438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*   99441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99452 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99463 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   99466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99492 */     GIR_RootConstrainSelectedInstOperands,
     /*   99493 */     // GIR_Coverage, 12406,
     /*   99493 */     GIR_EraseRootFromParent_Done,
     /*   99494 */   // Label 1332: @99494
     /*   99494 */   GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(99555), // Rule ID 12407 //
     /*   99499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*   99502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99524 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*   99527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99553 */     GIR_RootConstrainSelectedInstOperands,
     /*   99554 */     // GIR_Coverage, 12407,
     /*   99554 */     GIR_EraseRootFromParent_Done,
     /*   99555 */   // Label 1333: @99555
     /*   99555 */   GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(99609), // Rule ID 12398 //
     /*   99560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*   99563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99574 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99578 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   99585 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   99585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   99588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   99595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   99600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99607 */     GIR_RootConstrainSelectedInstOperands,
     /*   99608 */     // GIR_Coverage, 12398,
     /*   99608 */     GIR_EraseRootFromParent_Done,
     /*   99609 */   // Label 1334: @99609
     /*   99609 */   GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(99663), // Rule ID 12399 //
     /*   99614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*   99617 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   99639 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   99639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   99642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   99649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   99654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99661 */     GIR_RootConstrainSelectedInstOperands,
     /*   99662 */     // GIR_Coverage, 12399,
     /*   99662 */     GIR_EraseRootFromParent_Done,
     /*   99663 */   // Label 1335: @99663
     /*   99663 */   GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(99717), // Rule ID 12400 //
     /*   99668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*   99671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   99693 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   99693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   99696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   99703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   99708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99715 */     GIR_RootConstrainSelectedInstOperands,
     /*   99716 */     // GIR_Coverage, 12400,
     /*   99716 */     GIR_EraseRootFromParent_Done,
     /*   99717 */   // Label 1336: @99717
     /*   99717 */   GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(99771), // Rule ID 12401 //
     /*   99722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*   99725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   99747 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   99747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   99750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   99757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   99762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99769 */     GIR_RootConstrainSelectedInstOperands,
     /*   99770 */     // GIR_Coverage, 12401,
     /*   99770 */     GIR_EraseRootFromParent_Done,
     /*   99771 */   // Label 1337: @99771
     /*   99771 */   GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(99825), // Rule ID 12402 //
     /*   99776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*   99779 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*   99801 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*   99801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*   99804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*   99811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*   99816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*   99819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99823 */     GIR_RootConstrainSelectedInstOperands,
     /*   99824 */     // GIR_Coverage, 12402,
     /*   99824 */     GIR_EraseRootFromParent_Done,
     /*   99825 */   // Label 1338: @99825
     /*   99825 */   GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(99887), // Rule ID 10271 //
     /*   99830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*   99833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99856 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   99859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99885 */     GIR_RootConstrainSelectedInstOperands,
     /*   99886 */     // GIR_Coverage, 10271,
     /*   99886 */     GIR_EraseRootFromParent_Done,
     /*   99887 */   // Label 1339: @99887
     /*   99887 */   GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(99949), // Rule ID 10272 //
     /*   99892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*   99895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99918 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   99921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*   99938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*   99943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*   99947 */     GIR_RootConstrainSelectedInstOperands,
     /*   99948 */     // GIR_Coverage, 10272,
     /*   99948 */     GIR_EraseRootFromParent_Done,
     /*   99949 */   // Label 1340: @99949
     /*   99949 */   GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(100011), // Rule ID 10273 //
     /*   99954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*   99957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*   99965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*   99969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*   99973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*   99980 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*   99980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*   99983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*   99985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*   99990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*   99995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  100000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  100005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100009 */     GIR_RootConstrainSelectedInstOperands,
     /*  100010 */     // GIR_Coverage, 10273,
     /*  100010 */     GIR_EraseRootFromParent_Done,
     /*  100011 */   // Label 1341: @100011
     /*  100011 */   GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(100073), // Rule ID 10274 //
     /*  100016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  100019 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  100042 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  100042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  100045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  100052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  100057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  100062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  100067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100071 */     GIR_RootConstrainSelectedInstOperands,
     /*  100072 */     // GIR_Coverage, 10274,
     /*  100072 */     GIR_EraseRootFromParent_Done,
     /*  100073 */   // Label 1342: @100073
     /*  100073 */   GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(100135), // Rule ID 10275 //
     /*  100078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  100081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  100104 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  100104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  100107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  100114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  100119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  100124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  100129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100133 */     GIR_RootConstrainSelectedInstOperands,
     /*  100134 */     // GIR_Coverage, 10275,
     /*  100134 */     GIR_EraseRootFromParent_Done,
     /*  100135 */   // Label 1343: @100135
     /*  100135 */   GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(100190), // Rule ID 10266 //
     /*  100140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  100143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  100166 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  100166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  100169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  100176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100188 */     GIR_RootConstrainSelectedInstOperands,
     /*  100189 */     // GIR_Coverage, 10266,
     /*  100189 */     GIR_EraseRootFromParent_Done,
     /*  100190 */   // Label 1344: @100190
     /*  100190 */   GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(100245), // Rule ID 10267 //
     /*  100195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  100198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  100221 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  100221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  100224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  100231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100243 */     GIR_RootConstrainSelectedInstOperands,
     /*  100244 */     // GIR_Coverage, 10267,
     /*  100244 */     GIR_EraseRootFromParent_Done,
     /*  100245 */   // Label 1345: @100245
     /*  100245 */   GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(100300), // Rule ID 10268 //
     /*  100250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  100253 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  100276 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  100276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  100279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  100286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100298 */     GIR_RootConstrainSelectedInstOperands,
     /*  100299 */     // GIR_Coverage, 10268,
     /*  100299 */     GIR_EraseRootFromParent_Done,
     /*  100300 */   // Label 1346: @100300
     /*  100300 */   GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(100355), // Rule ID 10269 //
     /*  100305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  100308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100320 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100324 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  100331 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  100331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  100334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  100341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100353 */     GIR_RootConstrainSelectedInstOperands,
     /*  100354 */     // GIR_Coverage, 10269,
     /*  100354 */     GIR_EraseRootFromParent_Done,
     /*  100355 */   // Label 1347: @100355
     /*  100355 */   GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(100410), // Rule ID 10270 //
     /*  100360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  100363 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  100371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  100375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  100386 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  100386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  100389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  100391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  100396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100408 */     GIR_RootConstrainSelectedInstOperands,
     /*  100409 */     // GIR_Coverage, 10270,
     /*  100409 */     GIR_EraseRootFromParent_Done,
     /*  100410 */   // Label 1348: @100410
     /*  100410 */   GIM_Reject,
     /*  100411 */ // Label 1246: @100411
     /*  100411 */ GIM_Reject,
     /*  100412 */ // Label 1120: @100412
     /*  100412 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(106162),
     /*  100417 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  100420 */   GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(100486), // Rule ID 8731 //
     /*  100425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  100428 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100440 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100444 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  100448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  100455 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  100455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  100458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  100470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  100475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  100480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100484 */     GIR_RootConstrainSelectedInstOperands,
     /*  100485 */     // GIR_Coverage, 8731,
     /*  100485 */     GIR_EraseRootFromParent_Done,
     /*  100486 */   // Label 1350: @100486
     /*  100486 */   GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(100548), // Rule ID 8737 //
     /*  100491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  100494 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100502 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100506 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  100517 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  100517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  100520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  100532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  100537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  100542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100546 */     GIR_RootConstrainSelectedInstOperands,
     /*  100547 */     // GIR_Coverage, 8737,
     /*  100547 */     GIR_EraseRootFromParent_Done,
     /*  100548 */   // Label 1351: @100548
     /*  100548 */   GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(100607), // Rule ID 8727 //
     /*  100553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  100556 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100564 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100568 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100572 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  100576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  100583 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  100583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  100586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100605 */     GIR_RootConstrainSelectedInstOperands,
     /*  100606 */     // GIR_Coverage, 8727,
     /*  100606 */     GIR_EraseRootFromParent_Done,
     /*  100607 */   // Label 1352: @100607
     /*  100607 */   GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(100666), // Rule ID 8728 //
     /*  100612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  100615 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100623 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100627 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100631 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  100635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  100642 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  100642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  100645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100664 */     GIR_RootConstrainSelectedInstOperands,
     /*  100665 */     // GIR_Coverage, 8728,
     /*  100665 */     GIR_EraseRootFromParent_Done,
     /*  100666 */   // Label 1353: @100666
     /*  100666 */   GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(100718), // Rule ID 8733 //
     /*  100671 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100679 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100683 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  100694 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  100694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  100697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100716 */     GIR_RootConstrainSelectedInstOperands,
     /*  100717 */     // GIR_Coverage, 8733,
     /*  100717 */     GIR_EraseRootFromParent_Done,
     /*  100718 */   // Label 1354: @100718
     /*  100718 */   GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(100773), // Rule ID 8734 //
     /*  100723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  100726 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100738 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  100749 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  100749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  100752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  100764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100771 */     GIR_RootConstrainSelectedInstOperands,
     /*  100772 */     // GIR_Coverage, 8734,
     /*  100772 */     GIR_EraseRootFromParent_Done,
     /*  100773 */   // Label 1355: @100773
     /*  100773 */   GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(100832), // Rule ID 8729 //
     /*  100778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  100781 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100793 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100797 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  100801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  100808 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  100808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  100811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  100823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100830 */     GIR_RootConstrainSelectedInstOperands,
     /*  100831 */     // GIR_Coverage, 8729,
     /*  100831 */     GIR_EraseRootFromParent_Done,
     /*  100832 */   // Label 1356: @100832
     /*  100832 */   GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(100896), // Rule ID 8730 //
     /*  100837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  100840 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100852 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100856 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  100860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  100867 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  100867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  100870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  100882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  100890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100894 */     GIR_RootConstrainSelectedInstOperands,
     /*  100895 */     // GIR_Coverage, 8730,
     /*  100895 */     GIR_EraseRootFromParent_Done,
     /*  100896 */   // Label 1357: @100896
     /*  100896 */   GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(100947), // Rule ID 8732 //
     /*  100901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  100904 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100912 */     // MIs[0] sbase
     /*  100912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  100916 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  100920 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  100928 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  100928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  100931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100933 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  100935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100941 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  100945 */     GIR_RootConstrainSelectedInstOperands,
     /*  100946 */     // GIR_Coverage, 8732,
     /*  100946 */     GIR_EraseRootFromParent_Done,
     /*  100947 */   // Label 1358: @100947
     /*  100947 */   GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(101002), // Rule ID 8735 //
     /*  100952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  100955 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  100959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  100963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  100967 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  100971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  100978 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  100978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  100981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  100983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  100988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  100993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  100996 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101000 */     GIR_RootConstrainSelectedInstOperands,
     /*  101001 */     // GIR_Coverage, 8735,
     /*  101001 */     GIR_EraseRootFromParent_Done,
     /*  101002 */   // Label 1359: @101002
     /*  101002 */   GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(101062), // Rule ID 8736 //
     /*  101007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  101010 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  101014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  101018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101022 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  101026 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  101033 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  101033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  101036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  101038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  101043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  101056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101060 */     GIR_RootConstrainSelectedInstOperands,
     /*  101061 */     // GIR_Coverage, 8736,
     /*  101061 */     GIR_EraseRootFromParent_Done,
     /*  101062 */   // Label 1360: @101062
     /*  101062 */   GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(101106), // Rule ID 8738 //
     /*  101067 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  101071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  101075 */     // MIs[0] sbase
     /*  101075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  101079 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  101083 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  101087 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  101087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  101090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  101092 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  101094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101104 */     GIR_RootConstrainSelectedInstOperands,
     /*  101105 */     // GIR_Coverage, 8738,
     /*  101105 */     GIR_EraseRootFromParent_Done,
     /*  101106 */   // Label 1361: @101106
     /*  101106 */   GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(101166), // Rule ID 25256 //
     /*  101111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  101114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101127 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101134 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  101137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101164 */     GIR_RootConstrainSelectedInstOperands,
     /*  101165 */     // GIR_Coverage, 25256,
     /*  101165 */     GIR_EraseRootFromParent_Done,
     /*  101166 */   // Label 1362: @101166
     /*  101166 */   GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(101226), // Rule ID 25257 //
     /*  101171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  101174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101194 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  101197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101224 */     GIR_RootConstrainSelectedInstOperands,
     /*  101225 */     // GIR_Coverage, 25257,
     /*  101225 */     GIR_EraseRootFromParent_Done,
     /*  101226 */   // Label 1363: @101226
     /*  101226 */   GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(101286), // Rule ID 25258 //
     /*  101231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  101234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101254 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  101257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101284 */     GIR_RootConstrainSelectedInstOperands,
     /*  101285 */     // GIR_Coverage, 25258,
     /*  101285 */     GIR_EraseRootFromParent_Done,
     /*  101286 */   // Label 1364: @101286
     /*  101286 */   GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(101346), // Rule ID 25259 //
     /*  101291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  101294 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101314 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  101317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101344 */     GIR_RootConstrainSelectedInstOperands,
     /*  101345 */     // GIR_Coverage, 25259,
     /*  101345 */     GIR_EraseRootFromParent_Done,
     /*  101346 */   // Label 1365: @101346
     /*  101346 */   GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(101406), // Rule ID 25260 //
     /*  101351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  101354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101374 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  101377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101404 */     GIR_RootConstrainSelectedInstOperands,
     /*  101405 */     // GIR_Coverage, 25260,
     /*  101405 */     GIR_EraseRootFromParent_Done,
     /*  101406 */   // Label 1366: @101406
     /*  101406 */   GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(101466), // Rule ID 25266 //
     /*  101411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  101414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101427 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101434 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  101437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101454 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101464 */     GIR_RootConstrainSelectedInstOperands,
     /*  101465 */     // GIR_Coverage, 25266,
     /*  101465 */     GIR_EraseRootFromParent_Done,
     /*  101466 */   // Label 1367: @101466
     /*  101466 */   GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(101526), // Rule ID 25267 //
     /*  101471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  101474 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101494 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  101497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101524 */     GIR_RootConstrainSelectedInstOperands,
     /*  101525 */     // GIR_Coverage, 25267,
     /*  101525 */     GIR_EraseRootFromParent_Done,
     /*  101526 */   // Label 1368: @101526
     /*  101526 */   GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(101586), // Rule ID 25268 //
     /*  101531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  101534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101554 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  101557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101580 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101584 */     GIR_RootConstrainSelectedInstOperands,
     /*  101585 */     // GIR_Coverage, 25268,
     /*  101585 */     GIR_EraseRootFromParent_Done,
     /*  101586 */   // Label 1369: @101586
     /*  101586 */   GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(101646), // Rule ID 25269 //
     /*  101591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  101594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101603 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101614 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  101617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101640 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101644 */     GIR_RootConstrainSelectedInstOperands,
     /*  101645 */     // GIR_Coverage, 25269,
     /*  101645 */     GIR_EraseRootFromParent_Done,
     /*  101646 */   // Label 1370: @101646
     /*  101646 */   GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(101706), // Rule ID 25270 //
     /*  101651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  101654 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  101674 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  101674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  101677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  101679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  101684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  101689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  101700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101704 */     GIR_RootConstrainSelectedInstOperands,
     /*  101705 */     // GIR_Coverage, 25270,
     /*  101705 */     GIR_EraseRootFromParent_Done,
     /*  101706 */   // Label 1371: @101706
     /*  101706 */   GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(101765), // Rule ID 14182 //
     /*  101711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  101714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101723 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  101734 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  101734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  101737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  101739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  101744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  101749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  101759 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101763 */     GIR_RootConstrainSelectedInstOperands,
     /*  101764 */     // GIR_Coverage, 14182,
     /*  101764 */     GIR_EraseRootFromParent_Done,
     /*  101765 */   // Label 1372: @101765
     /*  101765 */   GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(101824), // Rule ID 14183 //
     /*  101770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  101773 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  101793 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  101793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  101796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  101798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  101803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  101808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  101818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101822 */     GIR_RootConstrainSelectedInstOperands,
     /*  101823 */     // GIR_Coverage, 14183,
     /*  101823 */     GIR_EraseRootFromParent_Done,
     /*  101824 */   // Label 1373: @101824
     /*  101824 */   GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(101883), // Rule ID 14184 //
     /*  101829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  101832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  101852 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  101852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  101855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  101857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  101862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  101867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  101877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101881 */     GIR_RootConstrainSelectedInstOperands,
     /*  101882 */     // GIR_Coverage, 14184,
     /*  101882 */     GIR_EraseRootFromParent_Done,
     /*  101883 */   // Label 1374: @101883
     /*  101883 */   GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(101942), // Rule ID 14185 //
     /*  101888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  101891 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  101911 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  101911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  101914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  101916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  101921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  101926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  101936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101940 */     GIR_RootConstrainSelectedInstOperands,
     /*  101941 */     // GIR_Coverage, 14185,
     /*  101941 */     GIR_EraseRootFromParent_Done,
     /*  101942 */   // Label 1375: @101942
     /*  101942 */   GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(102001), // Rule ID 14186 //
     /*  101947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  101950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  101955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  101959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  101963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  101970 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  101970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  101973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  101975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  101980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  101985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  101990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  101995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  101999 */     GIR_RootConstrainSelectedInstOperands,
     /*  102000 */     // GIR_Coverage, 14186,
     /*  102000 */     GIR_EraseRootFromParent_Done,
     /*  102001 */   // Label 1376: @102001
     /*  102001 */   GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(102053), // Rule ID 14177 //
     /*  102006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  102009 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  102029 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  102029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  102032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  102039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102051 */     GIR_RootConstrainSelectedInstOperands,
     /*  102052 */     // GIR_Coverage, 14177,
     /*  102052 */     GIR_EraseRootFromParent_Done,
     /*  102053 */   // Label 1377: @102053
     /*  102053 */   GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(102105), // Rule ID 14178 //
     /*  102058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  102061 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  102081 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  102081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  102084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  102091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102103 */     GIR_RootConstrainSelectedInstOperands,
     /*  102104 */     // GIR_Coverage, 14178,
     /*  102104 */     GIR_EraseRootFromParent_Done,
     /*  102105 */   // Label 1378: @102105
     /*  102105 */   GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(102157), // Rule ID 14179 //
     /*  102110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  102113 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  102133 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  102133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  102136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  102143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102155 */     GIR_RootConstrainSelectedInstOperands,
     /*  102156 */     // GIR_Coverage, 14179,
     /*  102156 */     GIR_EraseRootFromParent_Done,
     /*  102157 */   // Label 1379: @102157
     /*  102157 */   GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(102209), // Rule ID 14180 //
     /*  102162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  102165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  102185 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  102185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  102188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  102195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102203 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102207 */     GIR_RootConstrainSelectedInstOperands,
     /*  102208 */     // GIR_Coverage, 14180,
     /*  102208 */     GIR_EraseRootFromParent_Done,
     /*  102209 */   // Label 1380: @102209
     /*  102209 */   GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(102261), // Rule ID 14181 //
     /*  102214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  102217 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  102237 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  102237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  102240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  102247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102259 */     GIR_RootConstrainSelectedInstOperands,
     /*  102260 */     // GIR_Coverage, 14181,
     /*  102260 */     GIR_EraseRootFromParent_Done,
     /*  102261 */   // Label 1381: @102261
     /*  102261 */   GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(102313), // Rule ID 14172 //
     /*  102266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  102269 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  102289 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  102289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  102292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  102299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102311 */     GIR_RootConstrainSelectedInstOperands,
     /*  102312 */     // GIR_Coverage, 14172,
     /*  102312 */     GIR_EraseRootFromParent_Done,
     /*  102313 */   // Label 1382: @102313
     /*  102313 */   GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(102365), // Rule ID 14173 //
     /*  102318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  102321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  102341 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  102341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  102344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  102351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102363 */     GIR_RootConstrainSelectedInstOperands,
     /*  102364 */     // GIR_Coverage, 14173,
     /*  102364 */     GIR_EraseRootFromParent_Done,
     /*  102365 */   // Label 1383: @102365
     /*  102365 */   GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(102417), // Rule ID 14174 //
     /*  102370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  102373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102382 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  102393 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  102393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  102396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  102403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102415 */     GIR_RootConstrainSelectedInstOperands,
     /*  102416 */     // GIR_Coverage, 14174,
     /*  102416 */     GIR_EraseRootFromParent_Done,
     /*  102417 */   // Label 1384: @102417
     /*  102417 */   GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(102469), // Rule ID 14175 //
     /*  102422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  102425 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  102445 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  102445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  102448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  102455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102467 */     GIR_RootConstrainSelectedInstOperands,
     /*  102468 */     // GIR_Coverage, 14175,
     /*  102468 */     GIR_EraseRootFromParent_Done,
     /*  102469 */   // Label 1385: @102469
     /*  102469 */   GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(102521), // Rule ID 14176 //
     /*  102474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  102477 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  102482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102486 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  102497 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  102497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  102500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  102502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  102507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  102512 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102515 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102519 */     GIR_RootConstrainSelectedInstOperands,
     /*  102520 */     // GIR_Coverage, 14176,
     /*  102520 */     GIR_EraseRootFromParent_Done,
     /*  102521 */   // Label 1386: @102521
     /*  102521 */   GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(102588), // Rule ID 15448 //
     /*  102526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  102529 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102551 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  102554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102586 */     GIR_RootConstrainSelectedInstOperands,
     /*  102587 */     // GIR_Coverage, 15448,
     /*  102587 */     GIR_EraseRootFromParent_Done,
     /*  102588 */   // Label 1387: @102588
     /*  102588 */   GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(102655), // Rule ID 15449 //
     /*  102593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  102596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102603 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102618 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  102621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102653 */     GIR_RootConstrainSelectedInstOperands,
     /*  102654 */     // GIR_Coverage, 15449,
     /*  102654 */     GIR_EraseRootFromParent_Done,
     /*  102655 */   // Label 1388: @102655
     /*  102655 */   GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(102722), // Rule ID 15450 //
     /*  102660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  102663 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102685 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  102688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102716 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102720 */     GIR_RootConstrainSelectedInstOperands,
     /*  102721 */     // GIR_Coverage, 15450,
     /*  102721 */     GIR_EraseRootFromParent_Done,
     /*  102722 */   // Label 1389: @102722
     /*  102722 */   GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(102789), // Rule ID 15451 //
     /*  102727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  102730 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102752 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  102755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102787 */     GIR_RootConstrainSelectedInstOperands,
     /*  102788 */     // GIR_Coverage, 15451,
     /*  102788 */     GIR_EraseRootFromParent_Done,
     /*  102789 */   // Label 1390: @102789
     /*  102789 */   GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(102856), // Rule ID 15452 //
     /*  102794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  102797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102808 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102812 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102819 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  102822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102854 */     GIR_RootConstrainSelectedInstOperands,
     /*  102855 */     // GIR_Coverage, 15452,
     /*  102855 */     GIR_EraseRootFromParent_Done,
     /*  102856 */   // Label 1391: @102856
     /*  102856 */   GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(102923), // Rule ID 15458 //
     /*  102861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  102864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102886 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  102889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102917 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102921 */     GIR_RootConstrainSelectedInstOperands,
     /*  102922 */     // GIR_Coverage, 15458,
     /*  102922 */     GIR_EraseRootFromParent_Done,
     /*  102923 */   // Label 1392: @102923
     /*  102923 */   GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(102990), // Rule ID 15459 //
     /*  102928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  102931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  102938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  102942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  102946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  102953 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  102953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  102956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  102958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  102963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  102968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  102973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  102978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  102984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  102988 */     GIR_RootConstrainSelectedInstOperands,
     /*  102989 */     // GIR_Coverage, 15459,
     /*  102989 */     GIR_EraseRootFromParent_Done,
     /*  102990 */   // Label 1393: @102990
     /*  102990 */   GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(103057), // Rule ID 15460 //
     /*  102995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  102998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  103005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  103020 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  103020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  103023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103055 */     GIR_RootConstrainSelectedInstOperands,
     /*  103056 */     // GIR_Coverage, 15460,
     /*  103056 */     GIR_EraseRootFromParent_Done,
     /*  103057 */   // Label 1394: @103057
     /*  103057 */   GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(103124), // Rule ID 15461 //
     /*  103062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  103065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  103072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  103087 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  103087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  103090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103122 */     GIR_RootConstrainSelectedInstOperands,
     /*  103123 */     // GIR_Coverage, 15461,
     /*  103123 */     GIR_EraseRootFromParent_Done,
     /*  103124 */   // Label 1395: @103124
     /*  103124 */   GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(103191), // Rule ID 15462 //
     /*  103129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  103132 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  103139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  103154 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  103154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  103157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103185 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103189 */     GIR_RootConstrainSelectedInstOperands,
     /*  103190 */     // GIR_Coverage, 15462,
     /*  103190 */     GIR_EraseRootFromParent_Done,
     /*  103191 */   // Label 1396: @103191
     /*  103191 */   GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(103256), // Rule ID 25251 //
     /*  103196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  103199 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103208 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103219 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  103222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103254 */     GIR_RootConstrainSelectedInstOperands,
     /*  103255 */     // GIR_Coverage, 25251,
     /*  103255 */     GIR_EraseRootFromParent_Done,
     /*  103256 */   // Label 1397: @103256
     /*  103256 */   GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(103321), // Rule ID 25252 //
     /*  103261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  103264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103284 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  103287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103315 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103319 */     GIR_RootConstrainSelectedInstOperands,
     /*  103320 */     // GIR_Coverage, 25252,
     /*  103320 */     GIR_EraseRootFromParent_Done,
     /*  103321 */   // Label 1398: @103321
     /*  103321 */   GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(103386), // Rule ID 25253 //
     /*  103326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  103329 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103349 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  103352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103384 */     GIR_RootConstrainSelectedInstOperands,
     /*  103385 */     // GIR_Coverage, 25253,
     /*  103385 */     GIR_EraseRootFromParent_Done,
     /*  103386 */   // Label 1399: @103386
     /*  103386 */   GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(103451), // Rule ID 25254 //
     /*  103391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  103394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103414 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  103417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103449 */     GIR_RootConstrainSelectedInstOperands,
     /*  103450 */     // GIR_Coverage, 25254,
     /*  103450 */     GIR_EraseRootFromParent_Done,
     /*  103451 */   // Label 1400: @103451
     /*  103451 */   GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(103516), // Rule ID 25255 //
     /*  103456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  103459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103479 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  103482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103514 */     GIR_RootConstrainSelectedInstOperands,
     /*  103515 */     // GIR_Coverage, 25255,
     /*  103515 */     GIR_EraseRootFromParent_Done,
     /*  103516 */   // Label 1401: @103516
     /*  103516 */   GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(103581), // Rule ID 25261 //
     /*  103521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  103524 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103544 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  103547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103579 */     GIR_RootConstrainSelectedInstOperands,
     /*  103580 */     // GIR_Coverage, 25261,
     /*  103580 */     GIR_EraseRootFromParent_Done,
     /*  103581 */   // Label 1402: @103581
     /*  103581 */   GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(103646), // Rule ID 25262 //
     /*  103586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  103589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103609 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  103612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103640 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103644 */     GIR_RootConstrainSelectedInstOperands,
     /*  103645 */     // GIR_Coverage, 25262,
     /*  103645 */     GIR_EraseRootFromParent_Done,
     /*  103646 */   // Label 1403: @103646
     /*  103646 */   GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(103711), // Rule ID 25263 //
     /*  103651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  103654 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103674 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  103677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103705 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103709 */     GIR_RootConstrainSelectedInstOperands,
     /*  103710 */     // GIR_Coverage, 25263,
     /*  103710 */     GIR_EraseRootFromParent_Done,
     /*  103711 */   // Label 1404: @103711
     /*  103711 */   GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(103776), // Rule ID 25264 //
     /*  103716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  103719 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103728 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103732 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103739 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  103742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103774 */     GIR_RootConstrainSelectedInstOperands,
     /*  103775 */     // GIR_Coverage, 25264,
     /*  103775 */     GIR_EraseRootFromParent_Done,
     /*  103776 */   // Label 1405: @103776
     /*  103776 */   GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(103841), // Rule ID 25265 //
     /*  103781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  103784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  103789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  103804 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  103804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  103807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  103814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  103824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  103829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103839 */     GIR_RootConstrainSelectedInstOperands,
     /*  103840 */     // GIR_Coverage, 25265,
     /*  103840 */     GIR_EraseRootFromParent_Done,
     /*  103841 */   // Label 1406: @103841
     /*  103841 */   GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(103903), // Rule ID 15443 //
     /*  103846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  103849 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  103856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103860 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  103871 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  103871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  103874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  103886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  103891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103901 */     GIR_RootConstrainSelectedInstOperands,
     /*  103902 */     // GIR_Coverage, 15443,
     /*  103902 */     GIR_EraseRootFromParent_Done,
     /*  103903 */   // Label 1407: @103903
     /*  103903 */   GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(103965), // Rule ID 15444 //
     /*  103908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  103911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  103918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  103933 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  103933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  103936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  103938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  103943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  103948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  103953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  103959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  103963 */     GIR_RootConstrainSelectedInstOperands,
     /*  103964 */     // GIR_Coverage, 15444,
     /*  103964 */     GIR_EraseRootFromParent_Done,
     /*  103965 */   // Label 1408: @103965
     /*  103965 */   GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(104027), // Rule ID 15445 //
     /*  103970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  103973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  103980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  103984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  103988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  103995 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  103995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  103998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104025 */     GIR_RootConstrainSelectedInstOperands,
     /*  104026 */     // GIR_Coverage, 15445,
     /*  104026 */     GIR_EraseRootFromParent_Done,
     /*  104027 */   // Label 1409: @104027
     /*  104027 */   GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(104089), // Rule ID 15446 //
     /*  104032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  104035 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104050 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104057 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  104060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104080 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104083 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104087 */     GIR_RootConstrainSelectedInstOperands,
     /*  104088 */     // GIR_Coverage, 15446,
     /*  104088 */     GIR_EraseRootFromParent_Done,
     /*  104089 */   // Label 1410: @104089
     /*  104089 */   GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(104151), // Rule ID 15447 //
     /*  104094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  104097 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104119 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  104122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104149 */     GIR_RootConstrainSelectedInstOperands,
     /*  104150 */     // GIR_Coverage, 15447,
     /*  104150 */     GIR_EraseRootFromParent_Done,
     /*  104151 */   // Label 1411: @104151
     /*  104151 */   GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(104213), // Rule ID 15453 //
     /*  104156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  104159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104181 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  104184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104211 */     GIR_RootConstrainSelectedInstOperands,
     /*  104212 */     // GIR_Coverage, 15453,
     /*  104212 */     GIR_EraseRootFromParent_Done,
     /*  104213 */   // Label 1412: @104213
     /*  104213 */   GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(104275), // Rule ID 15454 //
     /*  104218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  104221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104243 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  104246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104269 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104273 */     GIR_RootConstrainSelectedInstOperands,
     /*  104274 */     // GIR_Coverage, 15454,
     /*  104274 */     GIR_EraseRootFromParent_Done,
     /*  104275 */   // Label 1413: @104275
     /*  104275 */   GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(104337), // Rule ID 15455 //
     /*  104280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  104283 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104305 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  104308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104335 */     GIR_RootConstrainSelectedInstOperands,
     /*  104336 */     // GIR_Coverage, 15455,
     /*  104336 */     GIR_EraseRootFromParent_Done,
     /*  104337 */   // Label 1414: @104337
     /*  104337 */   GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(104399), // Rule ID 15456 //
     /*  104342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  104345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104367 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  104370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104397 */     GIR_RootConstrainSelectedInstOperands,
     /*  104398 */     // GIR_Coverage, 15456,
     /*  104398 */     GIR_EraseRootFromParent_Done,
     /*  104399 */   // Label 1415: @104399
     /*  104399 */   GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(104461), // Rule ID 15457 //
     /*  104404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  104407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  104414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  104429 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  104429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  104432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  104434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  104439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  104444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  104449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104455 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104459 */     GIR_RootConstrainSelectedInstOperands,
     /*  104460 */     // GIR_Coverage, 15457,
     /*  104460 */     GIR_EraseRootFromParent_Done,
     /*  104461 */   // Label 1416: @104461
     /*  104461 */   GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(104517), // Rule ID 28937 //
     /*  104466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  104469 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  104473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104493 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  104496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104515 */     GIR_RootConstrainSelectedInstOperands,
     /*  104516 */     // GIR_Coverage, 28937,
     /*  104516 */     GIR_EraseRootFromParent_Done,
     /*  104517 */   // Label 1417: @104517
     /*  104517 */   GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(104573), // Rule ID 28938 //
     /*  104522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  104525 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  104529 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104542 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104549 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  104552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104567 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104571 */     GIR_RootConstrainSelectedInstOperands,
     /*  104572 */     // GIR_Coverage, 28938,
     /*  104572 */     GIR_EraseRootFromParent_Done,
     /*  104573 */   // Label 1418: @104573
     /*  104573 */   GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(104629), // Rule ID 28939 //
     /*  104578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  104581 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  104585 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104605 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  104608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104627 */     GIR_RootConstrainSelectedInstOperands,
     /*  104628 */     // GIR_Coverage, 28939,
     /*  104628 */     GIR_EraseRootFromParent_Done,
     /*  104629 */   // Label 1419: @104629
     /*  104629 */   GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(104685), // Rule ID 28940 //
     /*  104634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  104637 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  104641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104661 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  104664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104683 */     GIR_RootConstrainSelectedInstOperands,
     /*  104684 */     // GIR_Coverage, 28940,
     /*  104684 */     GIR_EraseRootFromParent_Done,
     /*  104685 */   // Label 1420: @104685
     /*  104685 */   GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(104741), // Rule ID 28941 //
     /*  104690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  104693 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  104697 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104717 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  104720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104739 */     GIR_RootConstrainSelectedInstOperands,
     /*  104740 */     // GIR_Coverage, 28941,
     /*  104740 */     GIR_EraseRootFromParent_Done,
     /*  104741 */   // Label 1421: @104741
     /*  104741 */   GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(104793), // Rule ID 28942 //
     /*  104746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  104749 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104769 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  104772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104787 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104791 */     GIR_RootConstrainSelectedInstOperands,
     /*  104792 */     // GIR_Coverage, 28942,
     /*  104792 */     GIR_EraseRootFromParent_Done,
     /*  104793 */   // Label 1422: @104793
     /*  104793 */   GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(104845), // Rule ID 28943 //
     /*  104798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  104801 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104821 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  104824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104843 */     GIR_RootConstrainSelectedInstOperands,
     /*  104844 */     // GIR_Coverage, 28943,
     /*  104844 */     GIR_EraseRootFromParent_Done,
     /*  104845 */   // Label 1423: @104845
     /*  104845 */   GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(104897), // Rule ID 28944 //
     /*  104850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  104853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104873 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  104876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104895 */     GIR_RootConstrainSelectedInstOperands,
     /*  104896 */     // GIR_Coverage, 28944,
     /*  104896 */     GIR_EraseRootFromParent_Done,
     /*  104897 */   // Label 1424: @104897
     /*  104897 */   GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(104949), // Rule ID 28945 //
     /*  104902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  104905 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104918 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104925 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  104928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104947 */     GIR_RootConstrainSelectedInstOperands,
     /*  104948 */     // GIR_Coverage, 28945,
     /*  104948 */     GIR_EraseRootFromParent_Done,
     /*  104949 */   // Label 1425: @104949
     /*  104949 */   GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(105001), // Rule ID 28946 //
     /*  104954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  104957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  104962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  104966 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  104970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  104977 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  104977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  104980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  104982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  104987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  104992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  104995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  104999 */     GIR_RootConstrainSelectedInstOperands,
     /*  105000 */     // GIR_Coverage, 28946,
     /*  105000 */     GIR_EraseRootFromParent_Done,
     /*  105001 */   // Label 1426: @105001
     /*  105001 */   GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(105062), // Rule ID 12183 //
     /*  105006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  105009 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105031 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  105034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105060 */     GIR_RootConstrainSelectedInstOperands,
     /*  105061 */     // GIR_Coverage, 12183,
     /*  105061 */     GIR_EraseRootFromParent_Done,
     /*  105062 */   // Label 1427: @105062
     /*  105062 */   GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(105123), // Rule ID 12184 //
     /*  105067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  105070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105081 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105085 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105092 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  105095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105121 */     GIR_RootConstrainSelectedInstOperands,
     /*  105122 */     // GIR_Coverage, 12184,
     /*  105122 */     GIR_EraseRootFromParent_Done,
     /*  105123 */   // Label 1428: @105123
     /*  105123 */   GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(105184), // Rule ID 12185 //
     /*  105128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  105131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105142 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105153 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  105156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105182 */     GIR_RootConstrainSelectedInstOperands,
     /*  105183 */     // GIR_Coverage, 12185,
     /*  105183 */     GIR_EraseRootFromParent_Done,
     /*  105184 */   // Label 1429: @105184
     /*  105184 */   GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(105245), // Rule ID 12186 //
     /*  105189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  105192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105214 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  105217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105243 */     GIR_RootConstrainSelectedInstOperands,
     /*  105244 */     // GIR_Coverage, 12186,
     /*  105244 */     GIR_EraseRootFromParent_Done,
     /*  105245 */   // Label 1430: @105245
     /*  105245 */   GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(105306), // Rule ID 12187 //
     /*  105250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  105253 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105264 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105275 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  105278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105304 */     GIR_RootConstrainSelectedInstOperands,
     /*  105305 */     // GIR_Coverage, 12187,
     /*  105305 */     GIR_EraseRootFromParent_Done,
     /*  105306 */   // Label 1431: @105306
     /*  105306 */   GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(105360), // Rule ID 12178 //
     /*  105311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  105314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  105336 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  105339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105358 */     GIR_RootConstrainSelectedInstOperands,
     /*  105359 */     // GIR_Coverage, 12178,
     /*  105359 */     GIR_EraseRootFromParent_Done,
     /*  105360 */   // Label 1432: @105360
     /*  105360 */   GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(105414), // Rule ID 12179 //
     /*  105365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  105368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  105390 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  105393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105412 */     GIR_RootConstrainSelectedInstOperands,
     /*  105413 */     // GIR_Coverage, 12179,
     /*  105413 */     GIR_EraseRootFromParent_Done,
     /*  105414 */   // Label 1433: @105414
     /*  105414 */   GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(105468), // Rule ID 12180 //
     /*  105419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  105422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  105444 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  105447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105466 */     GIR_RootConstrainSelectedInstOperands,
     /*  105467 */     // GIR_Coverage, 12180,
     /*  105467 */     GIR_EraseRootFromParent_Done,
     /*  105468 */   // Label 1434: @105468
     /*  105468 */   GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(105522), // Rule ID 12181 //
     /*  105473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  105476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  105498 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  105501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105516 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105520 */     GIR_RootConstrainSelectedInstOperands,
     /*  105521 */     // GIR_Coverage, 12181,
     /*  105521 */     GIR_EraseRootFromParent_Done,
     /*  105522 */   // Label 1435: @105522
     /*  105522 */   GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(105576), // Rule ID 12182 //
     /*  105527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  105530 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  105552 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  105555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105574 */     GIR_RootConstrainSelectedInstOperands,
     /*  105575 */     // GIR_Coverage, 12182,
     /*  105575 */     GIR_EraseRootFromParent_Done,
     /*  105576 */   // Label 1436: @105576
     /*  105576 */   GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(105638), // Rule ID 10041 //
     /*  105581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  105584 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105607 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  105610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105632 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105636 */     GIR_RootConstrainSelectedInstOperands,
     /*  105637 */     // GIR_Coverage, 10041,
     /*  105637 */     GIR_EraseRootFromParent_Done,
     /*  105638 */   // Label 1437: @105638
     /*  105638 */   GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(105700), // Rule ID 10042 //
     /*  105643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  105646 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105658 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105662 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105669 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  105672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105698 */     GIR_RootConstrainSelectedInstOperands,
     /*  105699 */     // GIR_Coverage, 10042,
     /*  105699 */     GIR_EraseRootFromParent_Done,
     /*  105700 */   // Label 1438: @105700
     /*  105700 */   GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(105762), // Rule ID 10043 //
     /*  105705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  105708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105731 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  105734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105760 */     GIR_RootConstrainSelectedInstOperands,
     /*  105761 */     // GIR_Coverage, 10043,
     /*  105761 */     GIR_EraseRootFromParent_Done,
     /*  105762 */   // Label 1439: @105762
     /*  105762 */   GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(105824), // Rule ID 10044 //
     /*  105767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  105770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105793 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  105796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105822 */     GIR_RootConstrainSelectedInstOperands,
     /*  105823 */     // GIR_Coverage, 10044,
     /*  105823 */     GIR_EraseRootFromParent_Done,
     /*  105824 */   // Label 1440: @105824
     /*  105824 */   GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(105886), // Rule ID 10045 //
     /*  105829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  105832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  105855 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  105855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  105858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  105865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  105870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  105875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  105880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105884 */     GIR_RootConstrainSelectedInstOperands,
     /*  105885 */     // GIR_Coverage, 10045,
     /*  105885 */     GIR_EraseRootFromParent_Done,
     /*  105886 */   // Label 1441: @105886
     /*  105886 */   GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(105941), // Rule ID 10036 //
     /*  105891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  105894 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105906 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105910 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  105917 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  105920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105932 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105935 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105939 */     GIR_RootConstrainSelectedInstOperands,
     /*  105940 */     // GIR_Coverage, 10036,
     /*  105940 */     GIR_EraseRootFromParent_Done,
     /*  105941 */   // Label 1442: @105941
     /*  105941 */   GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(105996), // Rule ID 10037 //
     /*  105946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  105949 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  105957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  105961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  105965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  105972 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  105972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  105975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  105977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  105982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  105987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  105990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  105994 */     GIR_RootConstrainSelectedInstOperands,
     /*  105995 */     // GIR_Coverage, 10037,
     /*  105995 */     GIR_EraseRootFromParent_Done,
     /*  105996 */   // Label 1443: @105996
     /*  105996 */   GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(106051), // Rule ID 10038 //
     /*  106001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  106004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  106012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  106016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  106027 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  106027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  106030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  106032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  106037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106049 */     GIR_RootConstrainSelectedInstOperands,
     /*  106050 */     // GIR_Coverage, 10038,
     /*  106050 */     GIR_EraseRootFromParent_Done,
     /*  106051 */   // Label 1444: @106051
     /*  106051 */   GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(106106), // Rule ID 10039 //
     /*  106056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  106059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  106067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  106071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  106082 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  106082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  106085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  106087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  106092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106104 */     GIR_RootConstrainSelectedInstOperands,
     /*  106105 */     // GIR_Coverage, 10039,
     /*  106105 */     GIR_EraseRootFromParent_Done,
     /*  106106 */   // Label 1445: @106106
     /*  106106 */   GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(106161), // Rule ID 10040 //
     /*  106111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  106114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  106122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  106126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  106137 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  106137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  106140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  106142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  106147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106152 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106155 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106159 */     GIR_RootConstrainSelectedInstOperands,
     /*  106160 */     // GIR_Coverage, 10040,
     /*  106160 */     GIR_EraseRootFromParent_Done,
     /*  106161 */   // Label 1446: @106161
     /*  106161 */   GIM_Reject,
     /*  106162 */ // Label 1349: @106162
     /*  106162 */ GIM_Reject,
     /*  106163 */ // Label 1121: @106163
     /*  106163 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(111913),
     /*  106168 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  106171 */   GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(106237), // Rule ID 8743 //
     /*  106176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  106179 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106191 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106195 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  106199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  106206 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  106206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  106209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  106226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  106231 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106235 */     GIR_RootConstrainSelectedInstOperands,
     /*  106236 */     // GIR_Coverage, 8743,
     /*  106236 */     GIR_EraseRootFromParent_Done,
     /*  106237 */   // Label 1448: @106237
     /*  106237 */   GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(106299), // Rule ID 8749 //
     /*  106242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  106245 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106257 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  106268 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  106268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  106271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  106288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  106293 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106297 */     GIR_RootConstrainSelectedInstOperands,
     /*  106298 */     // GIR_Coverage, 8749,
     /*  106298 */     GIR_EraseRootFromParent_Done,
     /*  106299 */   // Label 1449: @106299
     /*  106299 */   GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(106358), // Rule ID 8739 //
     /*  106304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  106307 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106319 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106323 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  106327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  106334 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  106334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  106337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106356 */     GIR_RootConstrainSelectedInstOperands,
     /*  106357 */     // GIR_Coverage, 8739,
     /*  106357 */     GIR_EraseRootFromParent_Done,
     /*  106358 */   // Label 1450: @106358
     /*  106358 */   GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(106417), // Rule ID 8740 //
     /*  106363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  106366 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106378 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106382 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  106386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  106393 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  106393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  106396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106415 */     GIR_RootConstrainSelectedInstOperands,
     /*  106416 */     // GIR_Coverage, 8740,
     /*  106416 */     GIR_EraseRootFromParent_Done,
     /*  106417 */   // Label 1451: @106417
     /*  106417 */   GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(106469), // Rule ID 8745 //
     /*  106422 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106434 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  106445 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  106445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  106448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106467 */     GIR_RootConstrainSelectedInstOperands,
     /*  106468 */     // GIR_Coverage, 8745,
     /*  106468 */     GIR_EraseRootFromParent_Done,
     /*  106469 */   // Label 1452: @106469
     /*  106469 */   GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(106524), // Rule ID 8746 //
     /*  106474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  106477 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106489 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  106500 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  106500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  106503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  106515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106522 */     GIR_RootConstrainSelectedInstOperands,
     /*  106523 */     // GIR_Coverage, 8746,
     /*  106523 */     GIR_EraseRootFromParent_Done,
     /*  106524 */   // Label 1453: @106524
     /*  106524 */   GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(106583), // Rule ID 8741 //
     /*  106529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  106532 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106544 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106548 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  106552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  106559 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  106559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  106562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106581 */     GIR_RootConstrainSelectedInstOperands,
     /*  106582 */     // GIR_Coverage, 8741,
     /*  106582 */     GIR_EraseRootFromParent_Done,
     /*  106583 */   // Label 1454: @106583
     /*  106583 */   GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(106647), // Rule ID 8742 //
     /*  106588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  106591 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106603 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106607 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  106611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  106618 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  106618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  106621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  106641 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106645 */     GIR_RootConstrainSelectedInstOperands,
     /*  106646 */     // GIR_Coverage, 8742,
     /*  106646 */     GIR_EraseRootFromParent_Done,
     /*  106647 */   // Label 1455: @106647
     /*  106647 */   GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(106698), // Rule ID 8744 //
     /*  106652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  106655 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106663 */     // MIs[0] sbase
     /*  106663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  106667 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  106671 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106675 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  106679 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  106679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  106682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106684 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  106686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106696 */     GIR_RootConstrainSelectedInstOperands,
     /*  106697 */     // GIR_Coverage, 8744,
     /*  106697 */     GIR_EraseRootFromParent_Done,
     /*  106698 */   // Label 1456: @106698
     /*  106698 */   GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(106753), // Rule ID 8747 //
     /*  106703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  106706 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106714 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106718 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106722 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  106729 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  106729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  106732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106744 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106751 */     GIR_RootConstrainSelectedInstOperands,
     /*  106752 */     // GIR_Coverage, 8747,
     /*  106752 */     GIR_EraseRootFromParent_Done,
     /*  106753 */   // Label 1457: @106753
     /*  106753 */   GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(106813), // Rule ID 8748 //
     /*  106758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  106761 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106773 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  106784 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  106784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  106787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  106794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  106807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106811 */     GIR_RootConstrainSelectedInstOperands,
     /*  106812 */     // GIR_Coverage, 8748,
     /*  106812 */     GIR_EraseRootFromParent_Done,
     /*  106813 */   // Label 1458: @106813
     /*  106813 */   GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(106857), // Rule ID 8750 //
     /*  106818 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  106822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  106826 */     // MIs[0] sbase
     /*  106826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  106830 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  106834 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  106838 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  106838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  106841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  106843 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  106845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106855 */     GIR_RootConstrainSelectedInstOperands,
     /*  106856 */     // GIR_Coverage, 8750,
     /*  106856 */     GIR_EraseRootFromParent_Done,
     /*  106857 */   // Label 1459: @106857
     /*  106857 */   GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(106917), // Rule ID 25276 //
     /*  106862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  106865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  106870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  106874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  106885 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  106885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  106888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  106890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  106895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  106905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106915 */     GIR_RootConstrainSelectedInstOperands,
     /*  106916 */     // GIR_Coverage, 25276,
     /*  106916 */     GIR_EraseRootFromParent_Done,
     /*  106917 */   // Label 1460: @106917
     /*  106917 */   GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(106977), // Rule ID 25277 //
     /*  106922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  106925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  106930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  106934 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106938 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  106945 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  106945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  106948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  106950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  106955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  106960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  106965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  106971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  106975 */     GIR_RootConstrainSelectedInstOperands,
     /*  106976 */     // GIR_Coverage, 25277,
     /*  106976 */     GIR_EraseRootFromParent_Done,
     /*  106977 */   // Label 1461: @106977
     /*  106977 */   GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(107037), // Rule ID 25278 //
     /*  106982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  106985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  106990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  106994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  106998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107005 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  107008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107031 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107035 */     GIR_RootConstrainSelectedInstOperands,
     /*  107036 */     // GIR_Coverage, 25278,
     /*  107036 */     GIR_EraseRootFromParent_Done,
     /*  107037 */   // Label 1462: @107037
     /*  107037 */   GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(107097), // Rule ID 25279 //
     /*  107042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  107045 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107065 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  107068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107095 */     GIR_RootConstrainSelectedInstOperands,
     /*  107096 */     // GIR_Coverage, 25279,
     /*  107096 */     GIR_EraseRootFromParent_Done,
     /*  107097 */   // Label 1463: @107097
     /*  107097 */   GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(107157), // Rule ID 25280 //
     /*  107102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  107105 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107125 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  107128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107155 */     GIR_RootConstrainSelectedInstOperands,
     /*  107156 */     // GIR_Coverage, 25280,
     /*  107156 */     GIR_EraseRootFromParent_Done,
     /*  107157 */   // Label 1464: @107157
     /*  107157 */   GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(107217), // Rule ID 25286 //
     /*  107162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  107165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107185 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  107188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107215 */     GIR_RootConstrainSelectedInstOperands,
     /*  107216 */     // GIR_Coverage, 25286,
     /*  107216 */     GIR_EraseRootFromParent_Done,
     /*  107217 */   // Label 1465: @107217
     /*  107217 */   GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(107277), // Rule ID 25287 //
     /*  107222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  107225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107245 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  107248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107275 */     GIR_RootConstrainSelectedInstOperands,
     /*  107276 */     // GIR_Coverage, 25287,
     /*  107276 */     GIR_EraseRootFromParent_Done,
     /*  107277 */   // Label 1466: @107277
     /*  107277 */   GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(107337), // Rule ID 25288 //
     /*  107282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  107285 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107305 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  107308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107335 */     GIR_RootConstrainSelectedInstOperands,
     /*  107336 */     // GIR_Coverage, 25288,
     /*  107336 */     GIR_EraseRootFromParent_Done,
     /*  107337 */   // Label 1467: @107337
     /*  107337 */   GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(107397), // Rule ID 25289 //
     /*  107342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  107345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107354 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107358 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107365 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  107368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107395 */     GIR_RootConstrainSelectedInstOperands,
     /*  107396 */     // GIR_Coverage, 25289,
     /*  107396 */     GIR_EraseRootFromParent_Done,
     /*  107397 */   // Label 1468: @107397
     /*  107397 */   GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(107457), // Rule ID 25290 //
     /*  107402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  107405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107418 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  107425 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  107425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  107428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  107430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  107435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  107440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107455 */     GIR_RootConstrainSelectedInstOperands,
     /*  107456 */     // GIR_Coverage, 25290,
     /*  107456 */     GIR_EraseRootFromParent_Done,
     /*  107457 */   // Label 1469: @107457
     /*  107457 */   GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(107516), // Rule ID 14212 //
     /*  107462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  107465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  107485 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  107485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  107488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  107495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  107500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  107510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107514 */     GIR_RootConstrainSelectedInstOperands,
     /*  107515 */     // GIR_Coverage, 14212,
     /*  107515 */     GIR_EraseRootFromParent_Done,
     /*  107516 */   // Label 1470: @107516
     /*  107516 */   GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(107575), // Rule ID 14213 //
     /*  107521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  107524 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  107544 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  107544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  107547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  107554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  107559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  107569 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107573 */     GIR_RootConstrainSelectedInstOperands,
     /*  107574 */     // GIR_Coverage, 14213,
     /*  107574 */     GIR_EraseRootFromParent_Done,
     /*  107575 */   // Label 1471: @107575
     /*  107575 */   GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(107634), // Rule ID 14214 //
     /*  107580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  107583 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107592 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107596 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  107603 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  107603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  107606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  107613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  107618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  107628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107632 */     GIR_RootConstrainSelectedInstOperands,
     /*  107633 */     // GIR_Coverage, 14214,
     /*  107633 */     GIR_EraseRootFromParent_Done,
     /*  107634 */   // Label 1472: @107634
     /*  107634 */   GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(107693), // Rule ID 14215 //
     /*  107639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  107642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  107662 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  107662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  107665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  107672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  107677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  107687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107691 */     GIR_RootConstrainSelectedInstOperands,
     /*  107692 */     // GIR_Coverage, 14215,
     /*  107692 */     GIR_EraseRootFromParent_Done,
     /*  107693 */   // Label 1473: @107693
     /*  107693 */   GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(107752), // Rule ID 14216 //
     /*  107698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  107701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  107721 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  107721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  107724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  107731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  107736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  107741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  107746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107750 */     GIR_RootConstrainSelectedInstOperands,
     /*  107751 */     // GIR_Coverage, 14216,
     /*  107751 */     GIR_EraseRootFromParent_Done,
     /*  107752 */   // Label 1474: @107752
     /*  107752 */   GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(107804), // Rule ID 14207 //
     /*  107757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  107760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  107780 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  107780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  107783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  107790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  107795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107802 */     GIR_RootConstrainSelectedInstOperands,
     /*  107803 */     // GIR_Coverage, 14207,
     /*  107803 */     GIR_EraseRootFromParent_Done,
     /*  107804 */   // Label 1475: @107804
     /*  107804 */   GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(107856), // Rule ID 14208 //
     /*  107809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  107812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  107832 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  107832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  107835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  107842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  107847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107854 */     GIR_RootConstrainSelectedInstOperands,
     /*  107855 */     // GIR_Coverage, 14208,
     /*  107855 */     GIR_EraseRootFromParent_Done,
     /*  107856 */   // Label 1476: @107856
     /*  107856 */   GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(107908), // Rule ID 14209 //
     /*  107861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  107864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  107884 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  107884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  107887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  107894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  107899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107906 */     GIR_RootConstrainSelectedInstOperands,
     /*  107907 */     // GIR_Coverage, 14209,
     /*  107907 */     GIR_EraseRootFromParent_Done,
     /*  107908 */   // Label 1477: @107908
     /*  107908 */   GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(107960), // Rule ID 14210 //
     /*  107913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  107916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  107936 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  107936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  107939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  107946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  107951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  107954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  107958 */     GIR_RootConstrainSelectedInstOperands,
     /*  107959 */     // GIR_Coverage, 14210,
     /*  107959 */     GIR_EraseRootFromParent_Done,
     /*  107960 */   // Label 1478: @107960
     /*  107960 */   GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(108012), // Rule ID 14211 //
     /*  107965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  107968 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  107973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  107977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  107981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  107988 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  107988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  107991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  107993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  107998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  108003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108010 */     GIR_RootConstrainSelectedInstOperands,
     /*  108011 */     // GIR_Coverage, 14211,
     /*  108011 */     GIR_EraseRootFromParent_Done,
     /*  108012 */   // Label 1479: @108012
     /*  108012 */   GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(108064), // Rule ID 14202 //
     /*  108017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  108020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  108025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  108040 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  108040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  108043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  108045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  108050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  108055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108062 */     GIR_RootConstrainSelectedInstOperands,
     /*  108063 */     // GIR_Coverage, 14202,
     /*  108063 */     GIR_EraseRootFromParent_Done,
     /*  108064 */   // Label 1480: @108064
     /*  108064 */   GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(108116), // Rule ID 14203 //
     /*  108069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  108072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  108077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108081 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108085 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  108092 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  108092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  108095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  108097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  108102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  108107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108114 */     GIR_RootConstrainSelectedInstOperands,
     /*  108115 */     // GIR_Coverage, 14203,
     /*  108115 */     GIR_EraseRootFromParent_Done,
     /*  108116 */   // Label 1481: @108116
     /*  108116 */   GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(108168), // Rule ID 14204 //
     /*  108121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  108124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  108129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  108144 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  108144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  108147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  108149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  108154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  108159 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108162 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108166 */     GIR_RootConstrainSelectedInstOperands,
     /*  108167 */     // GIR_Coverage, 14204,
     /*  108167 */     GIR_EraseRootFromParent_Done,
     /*  108168 */   // Label 1482: @108168
     /*  108168 */   GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(108220), // Rule ID 14205 //
     /*  108173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  108176 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  108181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  108196 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  108196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  108199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  108201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  108206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  108211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108218 */     GIR_RootConstrainSelectedInstOperands,
     /*  108219 */     // GIR_Coverage, 14205,
     /*  108219 */     GIR_EraseRootFromParent_Done,
     /*  108220 */   // Label 1483: @108220
     /*  108220 */   GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(108272), // Rule ID 14206 //
     /*  108225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  108228 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  108233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  108248 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  108248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  108251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  108253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  108258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  108263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108270 */     GIR_RootConstrainSelectedInstOperands,
     /*  108271 */     // GIR_Coverage, 14206,
     /*  108271 */     GIR_EraseRootFromParent_Done,
     /*  108272 */   // Label 1484: @108272
     /*  108272 */   GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(108339), // Rule ID 15468 //
     /*  108277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  108280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108302 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  108305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108337 */     GIR_RootConstrainSelectedInstOperands,
     /*  108338 */     // GIR_Coverage, 15468,
     /*  108338 */     GIR_EraseRootFromParent_Done,
     /*  108339 */   // Label 1485: @108339
     /*  108339 */   GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(108406), // Rule ID 15469 //
     /*  108344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  108347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108369 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  108372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108404 */     GIR_RootConstrainSelectedInstOperands,
     /*  108405 */     // GIR_Coverage, 15469,
     /*  108405 */     GIR_EraseRootFromParent_Done,
     /*  108406 */   // Label 1486: @108406
     /*  108406 */   GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(108473), // Rule ID 15470 //
     /*  108411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  108414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108436 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  108439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108461 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108471 */     GIR_RootConstrainSelectedInstOperands,
     /*  108472 */     // GIR_Coverage, 15470,
     /*  108472 */     GIR_EraseRootFromParent_Done,
     /*  108473 */   // Label 1487: @108473
     /*  108473 */   GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(108540), // Rule ID 15471 //
     /*  108478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  108481 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108492 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108503 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  108506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108528 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108538 */     GIR_RootConstrainSelectedInstOperands,
     /*  108539 */     // GIR_Coverage, 15471,
     /*  108539 */     GIR_EraseRootFromParent_Done,
     /*  108540 */   // Label 1488: @108540
     /*  108540 */   GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(108607), // Rule ID 15472 //
     /*  108545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  108548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108570 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  108573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108605 */     GIR_RootConstrainSelectedInstOperands,
     /*  108606 */     // GIR_Coverage, 15472,
     /*  108606 */     GIR_EraseRootFromParent_Done,
     /*  108607 */   // Label 1489: @108607
     /*  108607 */   GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(108674), // Rule ID 15478 //
     /*  108612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  108615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108626 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108637 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  108640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108662 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108668 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108672 */     GIR_RootConstrainSelectedInstOperands,
     /*  108673 */     // GIR_Coverage, 15478,
     /*  108673 */     GIR_EraseRootFromParent_Done,
     /*  108674 */   // Label 1490: @108674
     /*  108674 */   GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(108741), // Rule ID 15479 //
     /*  108679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  108682 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108704 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  108707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108739 */     GIR_RootConstrainSelectedInstOperands,
     /*  108740 */     // GIR_Coverage, 15479,
     /*  108740 */     GIR_EraseRootFromParent_Done,
     /*  108741 */   // Label 1491: @108741
     /*  108741 */   GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(108808), // Rule ID 15480 //
     /*  108746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  108749 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108771 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  108774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108806 */     GIR_RootConstrainSelectedInstOperands,
     /*  108807 */     // GIR_Coverage, 15480,
     /*  108807 */     GIR_EraseRootFromParent_Done,
     /*  108808 */   // Label 1492: @108808
     /*  108808 */   GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(108875), // Rule ID 15481 //
     /*  108813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  108816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108838 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  108841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108869 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108873 */     GIR_RootConstrainSelectedInstOperands,
     /*  108874 */     // GIR_Coverage, 15481,
     /*  108874 */     GIR_EraseRootFromParent_Done,
     /*  108875 */   // Label 1493: @108875
     /*  108875 */   GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(108942), // Rule ID 15482 //
     /*  108880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  108883 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  108890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  108905 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  108905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  108908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  108940 */     GIR_RootConstrainSelectedInstOperands,
     /*  108941 */     // GIR_Coverage, 15482,
     /*  108941 */     GIR_EraseRootFromParent_Done,
     /*  108942 */   // Label 1494: @108942
     /*  108942 */   GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(109007), // Rule ID 25271 //
     /*  108947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  108950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  108955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  108959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  108963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  108970 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  108970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  108973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  108975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  108980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  108985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  108990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  108995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  108998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109005 */     GIR_RootConstrainSelectedInstOperands,
     /*  109006 */     // GIR_Coverage, 25271,
     /*  109006 */     GIR_EraseRootFromParent_Done,
     /*  109007 */   // Label 1495: @109007
     /*  109007 */   GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(109072), // Rule ID 25272 //
     /*  109012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  109015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109035 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  109038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109066 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109070 */     GIR_RootConstrainSelectedInstOperands,
     /*  109071 */     // GIR_Coverage, 25272,
     /*  109071 */     GIR_EraseRootFromParent_Done,
     /*  109072 */   // Label 1496: @109072
     /*  109072 */   GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(109137), // Rule ID 25273 //
     /*  109077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  109080 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109089 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109093 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109100 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  109103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109135 */     GIR_RootConstrainSelectedInstOperands,
     /*  109136 */     // GIR_Coverage, 25273,
     /*  109136 */     GIR_EraseRootFromParent_Done,
     /*  109137 */   // Label 1497: @109137
     /*  109137 */   GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(109202), // Rule ID 25274 //
     /*  109142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  109145 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109165 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  109168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109196 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109200 */     GIR_RootConstrainSelectedInstOperands,
     /*  109201 */     // GIR_Coverage, 25274,
     /*  109201 */     GIR_EraseRootFromParent_Done,
     /*  109202 */   // Label 1498: @109202
     /*  109202 */   GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(109267), // Rule ID 25275 //
     /*  109207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  109210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109223 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109230 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  109233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109265 */     GIR_RootConstrainSelectedInstOperands,
     /*  109266 */     // GIR_Coverage, 25275,
     /*  109266 */     GIR_EraseRootFromParent_Done,
     /*  109267 */   // Label 1499: @109267
     /*  109267 */   GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(109332), // Rule ID 25281 //
     /*  109272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  109275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109284 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109288 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109295 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  109298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109330 */     GIR_RootConstrainSelectedInstOperands,
     /*  109331 */     // GIR_Coverage, 25281,
     /*  109331 */     GIR_EraseRootFromParent_Done,
     /*  109332 */   // Label 1500: @109332
     /*  109332 */   GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(109397), // Rule ID 25282 //
     /*  109337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  109340 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109360 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  109363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109395 */     GIR_RootConstrainSelectedInstOperands,
     /*  109396 */     // GIR_Coverage, 25282,
     /*  109396 */     GIR_EraseRootFromParent_Done,
     /*  109397 */   // Label 1501: @109397
     /*  109397 */   GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(109462), // Rule ID 25283 //
     /*  109402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  109405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109418 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109425 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  109428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109460 */     GIR_RootConstrainSelectedInstOperands,
     /*  109461 */     // GIR_Coverage, 25283,
     /*  109461 */     GIR_EraseRootFromParent_Done,
     /*  109462 */   // Label 1502: @109462
     /*  109462 */   GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(109527), // Rule ID 25284 //
     /*  109467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  109470 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109490 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  109493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109525 */     GIR_RootConstrainSelectedInstOperands,
     /*  109526 */     // GIR_Coverage, 25284,
     /*  109526 */     GIR_EraseRootFromParent_Done,
     /*  109527 */   // Label 1503: @109527
     /*  109527 */   GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(109592), // Rule ID 25285 //
     /*  109532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  109535 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  109540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109544 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109548 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  109555 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  109555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  109558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  109565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  109575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  109580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109590 */     GIR_RootConstrainSelectedInstOperands,
     /*  109591 */     // GIR_Coverage, 25285,
     /*  109591 */     GIR_EraseRootFromParent_Done,
     /*  109592 */   // Label 1504: @109592
     /*  109592 */   GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(109654), // Rule ID 15463 //
     /*  109597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  109600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109622 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  109625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  109637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  109642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109652 */     GIR_RootConstrainSelectedInstOperands,
     /*  109653 */     // GIR_Coverage, 15463,
     /*  109653 */     GIR_EraseRootFromParent_Done,
     /*  109654 */   // Label 1505: @109654
     /*  109654 */   GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(109716), // Rule ID 15464 //
     /*  109659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  109662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109684 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  109687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  109699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  109704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109714 */     GIR_RootConstrainSelectedInstOperands,
     /*  109715 */     // GIR_Coverage, 15464,
     /*  109715 */     GIR_EraseRootFromParent_Done,
     /*  109716 */   // Label 1506: @109716
     /*  109716 */   GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(109778), // Rule ID 15465 //
     /*  109721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  109724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109735 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109746 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  109749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  109761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  109766 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109776 */     GIR_RootConstrainSelectedInstOperands,
     /*  109777 */     // GIR_Coverage, 15465,
     /*  109777 */     GIR_EraseRootFromParent_Done,
     /*  109778 */   // Label 1507: @109778
     /*  109778 */   GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(109840), // Rule ID 15466 //
     /*  109783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  109786 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109797 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109808 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  109811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  109823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  109828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109838 */     GIR_RootConstrainSelectedInstOperands,
     /*  109839 */     // GIR_Coverage, 15466,
     /*  109839 */     GIR_EraseRootFromParent_Done,
     /*  109840 */   // Label 1508: @109840
     /*  109840 */   GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(109902), // Rule ID 15467 //
     /*  109845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  109848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109870 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  109873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  109885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  109890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109900 */     GIR_RootConstrainSelectedInstOperands,
     /*  109901 */     // GIR_Coverage, 15467,
     /*  109901 */     GIR_EraseRootFromParent_Done,
     /*  109902 */   // Label 1509: @109902
     /*  109902 */   GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(109964), // Rule ID 15473 //
     /*  109907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  109910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109932 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  109935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  109942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  109947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  109952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  109958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  109962 */     GIR_RootConstrainSelectedInstOperands,
     /*  109963 */     // GIR_Coverage, 15473,
     /*  109963 */     GIR_EraseRootFromParent_Done,
     /*  109964 */   // Label 1510: @109964
     /*  109964 */   GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(110026), // Rule ID 15474 //
     /*  109969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  109972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  109979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  109983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  109987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  109994 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  109994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  109997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  109999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  110004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  110009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110024 */     GIR_RootConstrainSelectedInstOperands,
     /*  110025 */     // GIR_Coverage, 15474,
     /*  110025 */     GIR_EraseRootFromParent_Done,
     /*  110026 */   // Label 1511: @110026
     /*  110026 */   GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(110088), // Rule ID 15475 //
     /*  110031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  110034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  110056 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  110056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  110059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  110061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  110066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  110071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110086 */     GIR_RootConstrainSelectedInstOperands,
     /*  110087 */     // GIR_Coverage, 15475,
     /*  110087 */     GIR_EraseRootFromParent_Done,
     /*  110088 */   // Label 1512: @110088
     /*  110088 */   GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(110150), // Rule ID 15476 //
     /*  110093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  110096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  110118 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  110118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  110121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  110123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  110128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  110133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110148 */     GIR_RootConstrainSelectedInstOperands,
     /*  110149 */     // GIR_Coverage, 15476,
     /*  110149 */     GIR_EraseRootFromParent_Done,
     /*  110150 */   // Label 1513: @110150
     /*  110150 */   GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(110212), // Rule ID 15477 //
     /*  110155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  110158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  110180 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  110180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  110183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  110185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  110190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  110195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110210 */     GIR_RootConstrainSelectedInstOperands,
     /*  110211 */     // GIR_Coverage, 15477,
     /*  110211 */     GIR_EraseRootFromParent_Done,
     /*  110212 */   // Label 1514: @110212
     /*  110212 */   GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(110268), // Rule ID 28947 //
     /*  110217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  110220 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  110224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110244 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  110247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110266 */     GIR_RootConstrainSelectedInstOperands,
     /*  110267 */     // GIR_Coverage, 28947,
     /*  110267 */     GIR_EraseRootFromParent_Done,
     /*  110268 */   // Label 1515: @110268
     /*  110268 */   GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(110324), // Rule ID 28948 //
     /*  110273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  110276 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  110280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110300 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  110303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110322 */     GIR_RootConstrainSelectedInstOperands,
     /*  110323 */     // GIR_Coverage, 28948,
     /*  110323 */     GIR_EraseRootFromParent_Done,
     /*  110324 */   // Label 1516: @110324
     /*  110324 */   GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(110380), // Rule ID 28949 //
     /*  110329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  110332 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  110336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110356 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  110359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110378 */     GIR_RootConstrainSelectedInstOperands,
     /*  110379 */     // GIR_Coverage, 28949,
     /*  110379 */     GIR_EraseRootFromParent_Done,
     /*  110380 */   // Label 1517: @110380
     /*  110380 */   GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(110436), // Rule ID 28950 //
     /*  110385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  110388 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  110392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110412 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  110415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110434 */     GIR_RootConstrainSelectedInstOperands,
     /*  110435 */     // GIR_Coverage, 28950,
     /*  110435 */     GIR_EraseRootFromParent_Done,
     /*  110436 */   // Label 1518: @110436
     /*  110436 */   GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(110492), // Rule ID 28951 //
     /*  110441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  110444 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  110448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110468 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  110471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110490 */     GIR_RootConstrainSelectedInstOperands,
     /*  110491 */     // GIR_Coverage, 28951,
     /*  110491 */     GIR_EraseRootFromParent_Done,
     /*  110492 */   // Label 1519: @110492
     /*  110492 */   GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(110544), // Rule ID 28952 //
     /*  110497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  110500 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110520 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  110523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110542 */     GIR_RootConstrainSelectedInstOperands,
     /*  110543 */     // GIR_Coverage, 28952,
     /*  110543 */     GIR_EraseRootFromParent_Done,
     /*  110544 */   // Label 1520: @110544
     /*  110544 */   GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(110596), // Rule ID 28953 //
     /*  110549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  110552 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110572 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  110575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110594 */     GIR_RootConstrainSelectedInstOperands,
     /*  110595 */     // GIR_Coverage, 28953,
     /*  110595 */     GIR_EraseRootFromParent_Done,
     /*  110596 */   // Label 1521: @110596
     /*  110596 */   GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(110648), // Rule ID 28954 //
     /*  110601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  110604 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110624 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  110627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110646 */     GIR_RootConstrainSelectedInstOperands,
     /*  110647 */     // GIR_Coverage, 28954,
     /*  110647 */     GIR_EraseRootFromParent_Done,
     /*  110648 */   // Label 1522: @110648
     /*  110648 */   GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(110700), // Rule ID 28955 //
     /*  110653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  110656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110676 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  110679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110698 */     GIR_RootConstrainSelectedInstOperands,
     /*  110699 */     // GIR_Coverage, 28955,
     /*  110699 */     GIR_EraseRootFromParent_Done,
     /*  110700 */   // Label 1523: @110700
     /*  110700 */   GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(110752), // Rule ID 28956 //
     /*  110705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  110708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  110713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  110728 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  110728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  110731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  110738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  110743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  110746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110750 */     GIR_RootConstrainSelectedInstOperands,
     /*  110751 */     // GIR_Coverage, 28956,
     /*  110751 */     GIR_EraseRootFromParent_Done,
     /*  110752 */   // Label 1524: @110752
     /*  110752 */   GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(110813), // Rule ID 12203 //
     /*  110757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  110760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110771 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  110782 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  110782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  110785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  110792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  110797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  110807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110811 */     GIR_RootConstrainSelectedInstOperands,
     /*  110812 */     // GIR_Coverage, 12203,
     /*  110812 */     GIR_EraseRootFromParent_Done,
     /*  110813 */   // Label 1525: @110813
     /*  110813 */   GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(110874), // Rule ID 12204 //
     /*  110818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  110821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  110843 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  110843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  110846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  110853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  110858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  110868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110872 */     GIR_RootConstrainSelectedInstOperands,
     /*  110873 */     // GIR_Coverage, 12204,
     /*  110873 */     GIR_EraseRootFromParent_Done,
     /*  110874 */   // Label 1526: @110874
     /*  110874 */   GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(110935), // Rule ID 12205 //
     /*  110879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  110882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110893 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110897 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  110904 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  110904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  110907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  110914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  110919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  110929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110933 */     GIR_RootConstrainSelectedInstOperands,
     /*  110934 */     // GIR_Coverage, 12205,
     /*  110934 */     GIR_EraseRootFromParent_Done,
     /*  110935 */   // Label 1527: @110935
     /*  110935 */   GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(110996), // Rule ID 12206 //
     /*  110940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  110943 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  110950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  110954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  110958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  110965 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  110965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  110968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  110970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  110975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  110980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  110985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  110990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  110994 */     GIR_RootConstrainSelectedInstOperands,
     /*  110995 */     // GIR_Coverage, 12206,
     /*  110995 */     GIR_EraseRootFromParent_Done,
     /*  110996 */   // Label 1528: @110996
     /*  110996 */   GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(111057), // Rule ID 12207 //
     /*  111001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  111004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  111026 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  111029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  111036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  111041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111055 */     GIR_RootConstrainSelectedInstOperands,
     /*  111056 */     // GIR_Coverage, 12207,
     /*  111056 */     GIR_EraseRootFromParent_Done,
     /*  111057 */   // Label 1529: @111057
     /*  111057 */   GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(111111), // Rule ID 12198 //
     /*  111062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  111065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  111087 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  111090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111105 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111109 */     GIR_RootConstrainSelectedInstOperands,
     /*  111110 */     // GIR_Coverage, 12198,
     /*  111110 */     GIR_EraseRootFromParent_Done,
     /*  111111 */   // Label 1530: @111111
     /*  111111 */   GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(111165), // Rule ID 12199 //
     /*  111116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  111119 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111130 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111134 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  111141 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  111144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111163 */     GIR_RootConstrainSelectedInstOperands,
     /*  111164 */     // GIR_Coverage, 12199,
     /*  111164 */     GIR_EraseRootFromParent_Done,
     /*  111165 */   // Label 1531: @111165
     /*  111165 */   GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(111219), // Rule ID 12200 //
     /*  111170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  111173 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  111195 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  111198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111213 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111217 */     GIR_RootConstrainSelectedInstOperands,
     /*  111218 */     // GIR_Coverage, 12200,
     /*  111218 */     GIR_EraseRootFromParent_Done,
     /*  111219 */   // Label 1532: @111219
     /*  111219 */   GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(111273), // Rule ID 12201 //
     /*  111224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  111227 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111238 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111242 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  111249 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  111252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111267 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111271 */     GIR_RootConstrainSelectedInstOperands,
     /*  111272 */     // GIR_Coverage, 12201,
     /*  111272 */     GIR_EraseRootFromParent_Done,
     /*  111273 */   // Label 1533: @111273
     /*  111273 */   GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(111327), // Rule ID 12202 //
     /*  111278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  111281 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  111303 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  111306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111325 */     GIR_RootConstrainSelectedInstOperands,
     /*  111326 */     // GIR_Coverage, 12202,
     /*  111326 */     GIR_EraseRootFromParent_Done,
     /*  111327 */   // Label 1534: @111327
     /*  111327 */   GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(111389), // Rule ID 10061 //
     /*  111332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  111335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  111358 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  111361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  111368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  111373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111383 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111387 */     GIR_RootConstrainSelectedInstOperands,
     /*  111388 */     // GIR_Coverage, 10061,
     /*  111388 */     GIR_EraseRootFromParent_Done,
     /*  111389 */   // Label 1535: @111389
     /*  111389 */   GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(111451), // Rule ID 10062 //
     /*  111394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  111397 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111409 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  111420 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  111423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  111430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  111435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111449 */     GIR_RootConstrainSelectedInstOperands,
     /*  111450 */     // GIR_Coverage, 10062,
     /*  111450 */     GIR_EraseRootFromParent_Done,
     /*  111451 */   // Label 1536: @111451
     /*  111451 */   GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(111513), // Rule ID 10063 //
     /*  111456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  111459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  111482 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  111485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  111492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  111497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111507 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111511 */     GIR_RootConstrainSelectedInstOperands,
     /*  111512 */     // GIR_Coverage, 10063,
     /*  111512 */     GIR_EraseRootFromParent_Done,
     /*  111513 */   // Label 1537: @111513
     /*  111513 */   GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(111575), // Rule ID 10064 //
     /*  111518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  111521 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  111544 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  111547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  111554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  111559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111569 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111573 */     GIR_RootConstrainSelectedInstOperands,
     /*  111574 */     // GIR_Coverage, 10064,
     /*  111574 */     GIR_EraseRootFromParent_Done,
     /*  111575 */   // Label 1538: @111575
     /*  111575 */   GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(111637), // Rule ID 10065 //
     /*  111580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  111583 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  111606 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  111609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  111616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  111621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111635 */     GIR_RootConstrainSelectedInstOperands,
     /*  111636 */     // GIR_Coverage, 10065,
     /*  111636 */     GIR_EraseRootFromParent_Done,
     /*  111637 */   // Label 1539: @111637
     /*  111637 */   GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(111692), // Rule ID 10056 //
     /*  111642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  111645 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  111668 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  111671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111690 */     GIR_RootConstrainSelectedInstOperands,
     /*  111691 */     // GIR_Coverage, 10056,
     /*  111691 */     GIR_EraseRootFromParent_Done,
     /*  111692 */   // Label 1540: @111692
     /*  111692 */   GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(111747), // Rule ID 10057 //
     /*  111697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  111700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  111723 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  111726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111745 */     GIR_RootConstrainSelectedInstOperands,
     /*  111746 */     // GIR_Coverage, 10057,
     /*  111746 */     GIR_EraseRootFromParent_Done,
     /*  111747 */   // Label 1541: @111747
     /*  111747 */   GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(111802), // Rule ID 10058 //
     /*  111752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  111755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  111778 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  111781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111800 */     GIR_RootConstrainSelectedInstOperands,
     /*  111801 */     // GIR_Coverage, 10058,
     /*  111801 */     GIR_EraseRootFromParent_Done,
     /*  111802 */   // Label 1542: @111802
     /*  111802 */   GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(111857), // Rule ID 10059 //
     /*  111807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  111810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  111833 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  111836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111855 */     GIR_RootConstrainSelectedInstOperands,
     /*  111856 */     // GIR_Coverage, 10059,
     /*  111856 */     GIR_EraseRootFromParent_Done,
     /*  111857 */   // Label 1543: @111857
     /*  111857 */   GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(111912), // Rule ID 10060 //
     /*  111862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  111865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  111873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  111877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  111888 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  111888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  111891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  111893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  111898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  111903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  111906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111910 */     GIR_RootConstrainSelectedInstOperands,
     /*  111911 */     // GIR_Coverage, 10060,
     /*  111911 */     GIR_EraseRootFromParent_Done,
     /*  111912 */   // Label 1544: @111912
     /*  111912 */   GIM_Reject,
     /*  111913 */ // Label 1447: @111913
     /*  111913 */ GIM_Reject,
     /*  111914 */ // Label 1122: @111914
     /*  111914 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(117953),
     /*  111919 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  111922 */   GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(111988), // Rule ID 31146 //
     /*  111927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  111930 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  111934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  111938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  111942 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  111946 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  111950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  111957 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  111957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  111960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  111962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  111967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  111972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  111977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  111982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  111986 */     GIR_RootConstrainSelectedInstOperands,
     /*  111987 */     // GIR_Coverage, 31146,
     /*  111987 */     GIR_EraseRootFromParent_Done,
     /*  111988 */   // Label 1546: @111988
     /*  111988 */   GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(112050), // Rule ID 31151 //
     /*  111993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  111996 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112004 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112008 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  112019 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  112019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  112022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  112029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  112034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  112039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  112044 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112048 */     GIR_RootConstrainSelectedInstOperands,
     /*  112049 */     // GIR_Coverage, 31151,
     /*  112049 */     GIR_EraseRootFromParent_Done,
     /*  112050 */   // Label 1547: @112050
     /*  112050 */   GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(112112), // Rule ID 31157 //
     /*  112055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  112058 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112066 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112070 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  112081 */     // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  112081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  112084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  112091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  112096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  112101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  112106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112110 */     GIR_RootConstrainSelectedInstOperands,
     /*  112111 */     // GIR_Coverage, 31157,
     /*  112111 */     GIR_EraseRootFromParent_Done,
     /*  112112 */   // Label 1548: @112112
     /*  112112 */   GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(112171), // Rule ID 31142 //
     /*  112117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  112120 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112132 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112136 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  112140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  112147 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  112147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  112150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  112157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112165 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112169 */     GIR_RootConstrainSelectedInstOperands,
     /*  112170 */     // GIR_Coverage, 31142,
     /*  112170 */     GIR_EraseRootFromParent_Done,
     /*  112171 */   // Label 1549: @112171
     /*  112171 */   GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(112230), // Rule ID 31143 //
     /*  112176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  112179 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112191 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112195 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  112199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  112206 */     // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  112206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  112209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  112216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112228 */     GIR_RootConstrainSelectedInstOperands,
     /*  112229 */     // GIR_Coverage, 31143,
     /*  112229 */     GIR_EraseRootFromParent_Done,
     /*  112230 */   // Label 1550: @112230
     /*  112230 */   GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(112285), // Rule ID 31148 //
     /*  112235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  112238 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112250 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  112261 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  112261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  112264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  112271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112283 */     GIR_RootConstrainSelectedInstOperands,
     /*  112284 */     // GIR_Coverage, 31148,
     /*  112284 */     GIR_EraseRootFromParent_Done,
     /*  112285 */   // Label 1551: @112285
     /*  112285 */   GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(112350), // Rule ID 30103 //
     /*  112290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  112293 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112297 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112315 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  112319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112326 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112348 */     GIR_RootConstrainSelectedInstOperands,
     /*  112349 */     // GIR_Coverage, 30103,
     /*  112349 */     GIR_EraseRootFromParent_Done,
     /*  112350 */   // Label 1552: @112350
     /*  112350 */   GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(112415), // Rule ID 30104 //
     /*  112355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  112358 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112362 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112367 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112380 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  112384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112391 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112413 */     GIR_RootConstrainSelectedInstOperands,
     /*  112414 */     // GIR_Coverage, 30104,
     /*  112414 */     GIR_EraseRootFromParent_Done,
     /*  112415 */   // Label 1553: @112415
     /*  112415 */   GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(112480), // Rule ID 30105 //
     /*  112420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  112423 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112427 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112445 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  112449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112456 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112478 */     GIR_RootConstrainSelectedInstOperands,
     /*  112479 */     // GIR_Coverage, 30105,
     /*  112479 */     GIR_EraseRootFromParent_Done,
     /*  112480 */   // Label 1554: @112480
     /*  112480 */   GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(112545), // Rule ID 30106 //
     /*  112485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  112488 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112510 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  112514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112521 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112543 */     GIR_RootConstrainSelectedInstOperands,
     /*  112544 */     // GIR_Coverage, 30106,
     /*  112544 */     GIR_EraseRootFromParent_Done,
     /*  112545 */   // Label 1555: @112545
     /*  112545 */   GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(112610), // Rule ID 30107 //
     /*  112550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  112553 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112557 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112575 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  112579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112586 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112608 */     GIR_RootConstrainSelectedInstOperands,
     /*  112609 */     // GIR_Coverage, 30107,
     /*  112609 */     GIR_EraseRootFromParent_Done,
     /*  112610 */   // Label 1556: @112610
     /*  112610 */   GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(112670), // Rule ID 29763 //
     /*  112615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  112618 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112622 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112627 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  112631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112646 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112664 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112668 */     GIR_RootConstrainSelectedInstOperands,
     /*  112669 */     // GIR_Coverage, 29763,
     /*  112669 */     GIR_EraseRootFromParent_Done,
     /*  112670 */   // Label 1557: @112670
     /*  112670 */   GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(112730), // Rule ID 29764 //
     /*  112675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  112678 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112682 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112687 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  112691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112706 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112728 */     GIR_RootConstrainSelectedInstOperands,
     /*  112729 */     // GIR_Coverage, 29764,
     /*  112729 */     GIR_EraseRootFromParent_Done,
     /*  112730 */   // Label 1558: @112730
     /*  112730 */   GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(112790), // Rule ID 29765 //
     /*  112735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  112738 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112742 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112747 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  112751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112755 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112766 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112788 */     GIR_RootConstrainSelectedInstOperands,
     /*  112789 */     // GIR_Coverage, 29765,
     /*  112789 */     GIR_EraseRootFromParent_Done,
     /*  112790 */   // Label 1559: @112790
     /*  112790 */   GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(112850), // Rule ID 29766 //
     /*  112795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  112798 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112807 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  112811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112826 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112848 */     GIR_RootConstrainSelectedInstOperands,
     /*  112849 */     // GIR_Coverage, 29766,
     /*  112849 */     GIR_EraseRootFromParent_Done,
     /*  112850 */   // Label 1560: @112850
     /*  112850 */   GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(112910), // Rule ID 29767 //
     /*  112855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  112858 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112862 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  112867 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  112871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  112875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  112886 */     // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  112886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  112889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  112891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  112896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112908 */     GIR_RootConstrainSelectedInstOperands,
     /*  112909 */     // GIR_Coverage, 29767,
     /*  112909 */     GIR_EraseRootFromParent_Done,
     /*  112910 */   // Label 1561: @112910
     /*  112910 */   GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(112962), // Rule ID 31153 //
     /*  112915 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112923 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112927 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  112938 */     // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  112938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  112941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  112948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  112953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  112956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  112960 */     GIR_RootConstrainSelectedInstOperands,
     /*  112961 */     // GIR_Coverage, 31153,
     /*  112961 */     GIR_EraseRootFromParent_Done,
     /*  112962 */   // Label 1562: @112962
     /*  112962 */   GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(113017), // Rule ID 31154 //
     /*  112967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  112970 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  112974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  112978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  112982 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  112986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  112993 */     // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  112993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  112996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  112998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  113003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113011 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113015 */     GIR_RootConstrainSelectedInstOperands,
     /*  113016 */     // GIR_Coverage, 31154,
     /*  113016 */     GIR_EraseRootFromParent_Done,
     /*  113017 */   // Label 1563: @113017
     /*  113017 */   GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(113078), // Rule ID 30108 //
     /*  113022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  113025 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113043 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  113047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113054 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113076 */     GIR_RootConstrainSelectedInstOperands,
     /*  113077 */     // GIR_Coverage, 30108,
     /*  113077 */     GIR_EraseRootFromParent_Done,
     /*  113078 */   // Label 1564: @113078
     /*  113078 */   GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(113139), // Rule ID 30109 //
     /*  113083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  113086 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113091 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113104 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  113108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113115 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113133 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113137 */     GIR_RootConstrainSelectedInstOperands,
     /*  113138 */     // GIR_Coverage, 30109,
     /*  113138 */     GIR_EraseRootFromParent_Done,
     /*  113139 */   // Label 1565: @113139
     /*  113139 */   GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(113200), // Rule ID 30110 //
     /*  113144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  113147 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113161 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113165 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  113169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113176 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113198 */     GIR_RootConstrainSelectedInstOperands,
     /*  113199 */     // GIR_Coverage, 30110,
     /*  113199 */     GIR_EraseRootFromParent_Done,
     /*  113200 */   // Label 1566: @113200
     /*  113200 */   GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(113261), // Rule ID 30111 //
     /*  113205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  113208 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113226 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  113230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113237 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113259 */     GIR_RootConstrainSelectedInstOperands,
     /*  113260 */     // GIR_Coverage, 30111,
     /*  113260 */     GIR_EraseRootFromParent_Done,
     /*  113261 */   // Label 1567: @113261
     /*  113261 */   GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(113322), // Rule ID 30112 //
     /*  113266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  113269 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113287 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  113291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113298 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113320 */     GIR_RootConstrainSelectedInstOperands,
     /*  113321 */     // GIR_Coverage, 30112,
     /*  113321 */     GIR_EraseRootFromParent_Done,
     /*  113322 */   // Label 1568: @113322
     /*  113322 */   GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(113378), // Rule ID 29768 //
     /*  113327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  113330 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113335 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  113339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113354 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113376 */     GIR_RootConstrainSelectedInstOperands,
     /*  113377 */     // GIR_Coverage, 29768,
     /*  113377 */     GIR_EraseRootFromParent_Done,
     /*  113378 */   // Label 1569: @113378
     /*  113378 */   GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(113434), // Rule ID 29769 //
     /*  113383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  113386 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113391 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  113395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113410 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113432 */     GIR_RootConstrainSelectedInstOperands,
     /*  113433 */     // GIR_Coverage, 29769,
     /*  113433 */     GIR_EraseRootFromParent_Done,
     /*  113434 */   // Label 1570: @113434
     /*  113434 */   GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(113490), // Rule ID 29770 //
     /*  113439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  113442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113447 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  113451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113466 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113488 */     GIR_RootConstrainSelectedInstOperands,
     /*  113489 */     // GIR_Coverage, 29770,
     /*  113489 */     GIR_EraseRootFromParent_Done,
     /*  113490 */   // Label 1571: @113490
     /*  113490 */   GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(113546), // Rule ID 29771 //
     /*  113495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  113498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113503 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  113507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113522 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113544 */     GIR_RootConstrainSelectedInstOperands,
     /*  113545 */     // GIR_Coverage, 29771,
     /*  113545 */     GIR_EraseRootFromParent_Done,
     /*  113546 */   // Label 1572: @113546
     /*  113546 */   GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(113602), // Rule ID 29772 //
     /*  113551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  113554 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  113559 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  113563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  113567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  113578 */     // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  113578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  113581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  113583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  113588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  113593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113600 */     GIR_RootConstrainSelectedInstOperands,
     /*  113601 */     // GIR_Coverage, 29772,
     /*  113601 */     GIR_EraseRootFromParent_Done,
     /*  113602 */   // Label 1573: @113602
     /*  113602 */   GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(113661), // Rule ID 31144 //
     /*  113607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  113610 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113622 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113626 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  113630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  113637 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  113637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  113640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  113647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  113652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113659 */     GIR_RootConstrainSelectedInstOperands,
     /*  113660 */     // GIR_Coverage, 31144,
     /*  113660 */     GIR_EraseRootFromParent_Done,
     /*  113661 */   // Label 1574: @113661
     /*  113661 */   GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(113725), // Rule ID 31145 //
     /*  113666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  113669 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113681 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113685 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  113689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  113696 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  113696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  113699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  113706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  113711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  113719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113723 */     GIR_RootConstrainSelectedInstOperands,
     /*  113724 */     // GIR_Coverage, 31145,
     /*  113724 */     GIR_EraseRootFromParent_Done,
     /*  113725 */   // Label 1575: @113725
     /*  113725 */   GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(113776), // Rule ID 31147 //
     /*  113730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  113733 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113741 */     // MIs[0] sbase
     /*  113741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  113745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  113749 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113753 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  113757 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  113757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  113760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113762 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  113764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113774 */     GIR_RootConstrainSelectedInstOperands,
     /*  113775 */     // GIR_Coverage, 31147,
     /*  113775 */     GIR_EraseRootFromParent_Done,
     /*  113776 */   // Label 1576: @113776
     /*  113776 */   GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(113831), // Rule ID 31149 //
     /*  113781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  113784 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113796 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  113807 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  113807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  113810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  113817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  113822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113829 */     GIR_RootConstrainSelectedInstOperands,
     /*  113830 */     // GIR_Coverage, 31149,
     /*  113830 */     GIR_EraseRootFromParent_Done,
     /*  113831 */   // Label 1577: @113831
     /*  113831 */   GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(113891), // Rule ID 31150 //
     /*  113836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  113839 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113851 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  113862 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  113862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  113865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  113872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  113877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  113885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113889 */     GIR_RootConstrainSelectedInstOperands,
     /*  113890 */     // GIR_Coverage, 31150,
     /*  113890 */     GIR_EraseRootFromParent_Done,
     /*  113891 */   // Label 1578: @113891
     /*  113891 */   GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(113938), // Rule ID 31152 //
     /*  113896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  113899 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113907 */     // MIs[0] sbase
     /*  113907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  113911 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  113915 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113919 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  113919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  113922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113924 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  113926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113936 */     GIR_RootConstrainSelectedInstOperands,
     /*  113937 */     // GIR_Coverage, 31152,
     /*  113937 */     GIR_EraseRootFromParent_Done,
     /*  113938 */   // Label 1579: @113938
     /*  113938 */   GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(113993), // Rule ID 31155 //
     /*  113943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  113946 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  113950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  113954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  113958 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  113962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  113969 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  113969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  113972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  113974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  113979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  113984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  113987 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  113991 */     GIR_RootConstrainSelectedInstOperands,
     /*  113992 */     // GIR_Coverage, 31155,
     /*  113992 */     GIR_EraseRootFromParent_Done,
     /*  113993 */   // Label 1580: @113993
     /*  113993 */   GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(114053), // Rule ID 31156 //
     /*  113998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  114001 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  114005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  114009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114013 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  114017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  114024 */     // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  114024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  114027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  114029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  114034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  114039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  114047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114051 */     GIR_RootConstrainSelectedInstOperands,
     /*  114052 */     // GIR_Coverage, 31156,
     /*  114052 */     GIR_EraseRootFromParent_Done,
     /*  114053 */   // Label 1581: @114053
     /*  114053 */   GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(114097), // Rule ID 31158 //
     /*  114058 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  114062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  114066 */     // MIs[0] sbase
     /*  114066 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  114070 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  114074 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  114078 */     // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  114078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  114081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  114083 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  114085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114095 */     GIR_RootConstrainSelectedInstOperands,
     /*  114096 */     // GIR_Coverage, 31158,
     /*  114096 */     GIR_EraseRootFromParent_Done,
     /*  114097 */   // Label 1582: @114097
     /*  114097 */   GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(114156), // Rule ID 14542 //
     /*  114102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  114105 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  114125 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  114125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  114128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  114140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  114145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  114150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114154 */     GIR_RootConstrainSelectedInstOperands,
     /*  114155 */     // GIR_Coverage, 14542,
     /*  114155 */     GIR_EraseRootFromParent_Done,
     /*  114156 */   // Label 1583: @114156
     /*  114156 */   GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(114215), // Rule ID 14543 //
     /*  114161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  114164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  114184 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  114184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  114187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  114199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  114204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  114209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114213 */     GIR_RootConstrainSelectedInstOperands,
     /*  114214 */     // GIR_Coverage, 14543,
     /*  114214 */     GIR_EraseRootFromParent_Done,
     /*  114215 */   // Label 1584: @114215
     /*  114215 */   GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(114274), // Rule ID 14544 //
     /*  114220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  114223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  114243 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  114243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  114246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  114258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  114263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  114268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114272 */     GIR_RootConstrainSelectedInstOperands,
     /*  114273 */     // GIR_Coverage, 14544,
     /*  114273 */     GIR_EraseRootFromParent_Done,
     /*  114274 */   // Label 1585: @114274
     /*  114274 */   GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(114333), // Rule ID 14545 //
     /*  114279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  114282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  114302 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  114302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  114305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  114317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  114322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  114327 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114331 */     GIR_RootConstrainSelectedInstOperands,
     /*  114332 */     // GIR_Coverage, 14545,
     /*  114332 */     GIR_EraseRootFromParent_Done,
     /*  114333 */   // Label 1586: @114333
     /*  114333 */   GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(114392), // Rule ID 14546 //
     /*  114338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  114341 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  114361 */     // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  114361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  114364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  114376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  114381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  114386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114390 */     GIR_RootConstrainSelectedInstOperands,
     /*  114391 */     // GIR_Coverage, 14546,
     /*  114391 */     GIR_EraseRootFromParent_Done,
     /*  114392 */   // Label 1587: @114392
     /*  114392 */   GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(114444), // Rule ID 14537 //
     /*  114397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  114400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114409 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  114420 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  114420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  114423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  114430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114442 */     GIR_RootConstrainSelectedInstOperands,
     /*  114443 */     // GIR_Coverage, 14537,
     /*  114443 */     GIR_EraseRootFromParent_Done,
     /*  114444 */   // Label 1588: @114444
     /*  114444 */   GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(114496), // Rule ID 14538 //
     /*  114449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  114452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  114472 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  114472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  114475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  114482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114494 */     GIR_RootConstrainSelectedInstOperands,
     /*  114495 */     // GIR_Coverage, 14538,
     /*  114495 */     GIR_EraseRootFromParent_Done,
     /*  114496 */   // Label 1589: @114496
     /*  114496 */   GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(114548), // Rule ID 14539 //
     /*  114501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  114504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  114524 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  114524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  114527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  114534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114546 */     GIR_RootConstrainSelectedInstOperands,
     /*  114547 */     // GIR_Coverage, 14539,
     /*  114547 */     GIR_EraseRootFromParent_Done,
     /*  114548 */   // Label 1590: @114548
     /*  114548 */   GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(114600), // Rule ID 14540 //
     /*  114553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  114556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  114576 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  114576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  114579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  114586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114598 */     GIR_RootConstrainSelectedInstOperands,
     /*  114599 */     // GIR_Coverage, 14540,
     /*  114599 */     GIR_EraseRootFromParent_Done,
     /*  114600 */   // Label 1591: @114600
     /*  114600 */   GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(114652), // Rule ID 14541 //
     /*  114605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  114608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  114628 */     // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  114628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  114631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  114638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114650 */     GIR_RootConstrainSelectedInstOperands,
     /*  114651 */     // GIR_Coverage, 14541,
     /*  114651 */     GIR_EraseRootFromParent_Done,
     /*  114652 */   // Label 1592: @114652
     /*  114652 */   GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(114704), // Rule ID 14532 //
     /*  114657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  114660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114673 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  114680 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  114680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  114683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114702 */     GIR_RootConstrainSelectedInstOperands,
     /*  114703 */     // GIR_Coverage, 14532,
     /*  114703 */     GIR_EraseRootFromParent_Done,
     /*  114704 */   // Label 1593: @114704
     /*  114704 */   GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(114756), // Rule ID 14533 //
     /*  114709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  114712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  114732 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  114732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  114735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114754 */     GIR_RootConstrainSelectedInstOperands,
     /*  114755 */     // GIR_Coverage, 14533,
     /*  114755 */     GIR_EraseRootFromParent_Done,
     /*  114756 */   // Label 1594: @114756
     /*  114756 */   GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(114808), // Rule ID 14534 //
     /*  114761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  114764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  114784 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  114784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  114787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114806 */     GIR_RootConstrainSelectedInstOperands,
     /*  114807 */     // GIR_Coverage, 14534,
     /*  114807 */     GIR_EraseRootFromParent_Done,
     /*  114808 */   // Label 1595: @114808
     /*  114808 */   GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(114860), // Rule ID 14535 //
     /*  114813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  114816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  114836 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  114836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  114839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114858 */     GIR_RootConstrainSelectedInstOperands,
     /*  114859 */     // GIR_Coverage, 14535,
     /*  114859 */     GIR_EraseRootFromParent_Done,
     /*  114860 */   // Label 1596: @114860
     /*  114860 */   GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(114912), // Rule ID 14536 //
     /*  114865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  114868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  114873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  114888 */     // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  114888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  114891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  114893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  114898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  114903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114910 */     GIR_RootConstrainSelectedInstOperands,
     /*  114911 */     // GIR_Coverage, 14536,
     /*  114911 */     GIR_EraseRootFromParent_Done,
     /*  114912 */   // Label 1597: @114912
     /*  114912 */   GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(114979), // Rule ID 15688 //
     /*  114917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  114920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  114927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  114935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  114942 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  114942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  114945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  114947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  114952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  114957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  114962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  114967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  114973 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  114977 */     GIR_RootConstrainSelectedInstOperands,
     /*  114978 */     // GIR_Coverage, 15688,
     /*  114978 */     GIR_EraseRootFromParent_Done,
     /*  114979 */   // Label 1598: @114979
     /*  114979 */   GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(115046), // Rule ID 15689 //
     /*  114984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  114987 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  114994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  114998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115009 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  115012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115044 */     GIR_RootConstrainSelectedInstOperands,
     /*  115045 */     // GIR_Coverage, 15689,
     /*  115045 */     GIR_EraseRootFromParent_Done,
     /*  115046 */   // Label 1599: @115046
     /*  115046 */   GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(115113), // Rule ID 15690 //
     /*  115051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  115054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115076 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  115079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115111 */     GIR_RootConstrainSelectedInstOperands,
     /*  115112 */     // GIR_Coverage, 15690,
     /*  115112 */     GIR_EraseRootFromParent_Done,
     /*  115113 */   // Label 1600: @115113
     /*  115113 */   GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(115180), // Rule ID 15691 //
     /*  115118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  115121 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115143 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  115146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115178 */     GIR_RootConstrainSelectedInstOperands,
     /*  115179 */     // GIR_Coverage, 15691,
     /*  115179 */     GIR_EraseRootFromParent_Done,
     /*  115180 */   // Label 1601: @115180
     /*  115180 */   GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(115247), // Rule ID 15692 //
     /*  115185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  115188 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115210 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  115213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115241 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115245 */     GIR_RootConstrainSelectedInstOperands,
     /*  115246 */     // GIR_Coverage, 15692,
     /*  115246 */     GIR_EraseRootFromParent_Done,
     /*  115247 */   // Label 1602: @115247
     /*  115247 */   GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(115314), // Rule ID 15698 //
     /*  115252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  115255 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115266 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115277 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  115280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115312 */     GIR_RootConstrainSelectedInstOperands,
     /*  115313 */     // GIR_Coverage, 15698,
     /*  115313 */     GIR_EraseRootFromParent_Done,
     /*  115314 */   // Label 1603: @115314
     /*  115314 */   GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(115381), // Rule ID 15699 //
     /*  115319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  115322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115337 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115344 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  115347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115375 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115379 */     GIR_RootConstrainSelectedInstOperands,
     /*  115380 */     // GIR_Coverage, 15699,
     /*  115380 */     GIR_EraseRootFromParent_Done,
     /*  115381 */   // Label 1604: @115381
     /*  115381 */   GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(115448), // Rule ID 15700 //
     /*  115386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  115389 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115411 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  115414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115446 */     GIR_RootConstrainSelectedInstOperands,
     /*  115447 */     // GIR_Coverage, 15700,
     /*  115447 */     GIR_EraseRootFromParent_Done,
     /*  115448 */   // Label 1605: @115448
     /*  115448 */   GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(115515), // Rule ID 15701 //
     /*  115453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  115456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115478 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  115481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115513 */     GIR_RootConstrainSelectedInstOperands,
     /*  115514 */     // GIR_Coverage, 15701,
     /*  115514 */     GIR_EraseRootFromParent_Done,
     /*  115515 */   // Label 1606: @115515
     /*  115515 */   GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(115582), // Rule ID 15702 //
     /*  115520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  115523 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  115545 */     // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  115548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  115555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  115565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  115570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115576 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115580 */     GIR_RootConstrainSelectedInstOperands,
     /*  115581 */     // GIR_Coverage, 15702,
     /*  115581 */     GIR_EraseRootFromParent_Done,
     /*  115582 */   // Label 1607: @115582
     /*  115582 */   GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(115643), // Rule ID 29491 //
     /*  115587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  115590 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  115594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  115599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115603 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  115614 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  115614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  115617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  115619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  115624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  115629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  115634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115637 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115641 */     GIR_RootConstrainSelectedInstOperands,
     /*  115642 */     // GIR_Coverage, 29491,
     /*  115642 */     GIR_EraseRootFromParent_Done,
     /*  115643 */   // Label 1608: @115643
     /*  115643 */   GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(115704), // Rule ID 29492 //
     /*  115648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  115651 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  115655 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  115660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  115675 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  115675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  115678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  115680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  115685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  115690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  115695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115702 */     GIR_RootConstrainSelectedInstOperands,
     /*  115703 */     // GIR_Coverage, 29492,
     /*  115703 */     GIR_EraseRootFromParent_Done,
     /*  115704 */   // Label 1609: @115704
     /*  115704 */   GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(115765), // Rule ID 29493 //
     /*  115709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  115712 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  115716 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  115721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  115736 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  115736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  115739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  115741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  115746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  115751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  115756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115759 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115763 */     GIR_RootConstrainSelectedInstOperands,
     /*  115764 */     // GIR_Coverage, 29493,
     /*  115764 */     GIR_EraseRootFromParent_Done,
     /*  115765 */   // Label 1610: @115765
     /*  115765 */   GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(115826), // Rule ID 29494 //
     /*  115770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  115773 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  115777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  115782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  115797 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  115797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  115800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  115802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  115807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  115812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  115817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115824 */     GIR_RootConstrainSelectedInstOperands,
     /*  115825 */     // GIR_Coverage, 29494,
     /*  115825 */     GIR_EraseRootFromParent_Done,
     /*  115826 */   // Label 1611: @115826
     /*  115826 */   GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(115887), // Rule ID 29495 //
     /*  115831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  115834 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  115838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  115843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  115858 */     // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  115858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  115861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  115863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  115868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  115873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  115878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115885 */     GIR_RootConstrainSelectedInstOperands,
     /*  115886 */     // GIR_Coverage, 29495,
     /*  115886 */     GIR_EraseRootFromParent_Done,
     /*  115887 */   // Label 1612: @115887
     /*  115887 */   GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(115949), // Rule ID 15683 //
     /*  115892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  115895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115906 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115910 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  115917 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  115920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  115932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  115937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  115943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  115947 */     GIR_RootConstrainSelectedInstOperands,
     /*  115948 */     // GIR_Coverage, 15683,
     /*  115948 */     GIR_EraseRootFromParent_Done,
     /*  115949 */   // Label 1613: @115949
     /*  115949 */   GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(116011), // Rule ID 15684 //
     /*  115954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  115957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  115964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  115968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  115972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  115979 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  115979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  115982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  115984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  115989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  115994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  115999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116009 */     GIR_RootConstrainSelectedInstOperands,
     /*  116010 */     // GIR_Coverage, 15684,
     /*  116010 */     GIR_EraseRootFromParent_Done,
     /*  116011 */   // Label 1614: @116011
     /*  116011 */   GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(116073), // Rule ID 15685 //
     /*  116016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  116019 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116030 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116034 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116041 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  116044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116071 */     GIR_RootConstrainSelectedInstOperands,
     /*  116072 */     // GIR_Coverage, 15685,
     /*  116072 */     GIR_EraseRootFromParent_Done,
     /*  116073 */   // Label 1615: @116073
     /*  116073 */   GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(116135), // Rule ID 15686 //
     /*  116078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  116081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116092 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116096 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116103 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  116106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116133 */     GIR_RootConstrainSelectedInstOperands,
     /*  116134 */     // GIR_Coverage, 15686,
     /*  116134 */     GIR_EraseRootFromParent_Done,
     /*  116135 */   // Label 1616: @116135
     /*  116135 */   GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(116197), // Rule ID 15687 //
     /*  116140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  116143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116165 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  116168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116195 */     GIR_RootConstrainSelectedInstOperands,
     /*  116196 */     // GIR_Coverage, 15687,
     /*  116196 */     GIR_EraseRootFromParent_Done,
     /*  116197 */   // Label 1617: @116197
     /*  116197 */   GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(116259), // Rule ID 15693 //
     /*  116202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  116205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116227 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  116230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116257 */     GIR_RootConstrainSelectedInstOperands,
     /*  116258 */     // GIR_Coverage, 15693,
     /*  116258 */     GIR_EraseRootFromParent_Done,
     /*  116259 */   // Label 1618: @116259
     /*  116259 */   GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(116321), // Rule ID 15694 //
     /*  116264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  116267 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116289 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  116292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116315 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116319 */     GIR_RootConstrainSelectedInstOperands,
     /*  116320 */     // GIR_Coverage, 15694,
     /*  116320 */     GIR_EraseRootFromParent_Done,
     /*  116321 */   // Label 1619: @116321
     /*  116321 */   GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(116383), // Rule ID 15695 //
     /*  116326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  116329 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116351 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  116354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116381 */     GIR_RootConstrainSelectedInstOperands,
     /*  116382 */     // GIR_Coverage, 15695,
     /*  116382 */     GIR_EraseRootFromParent_Done,
     /*  116383 */   // Label 1620: @116383
     /*  116383 */   GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(116445), // Rule ID 15696 //
     /*  116388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  116391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116413 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  116416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116443 */     GIR_RootConstrainSelectedInstOperands,
     /*  116444 */     // GIR_Coverage, 15696,
     /*  116444 */     GIR_EraseRootFromParent_Done,
     /*  116445 */   // Label 1621: @116445
     /*  116445 */   GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(116507), // Rule ID 15697 //
     /*  116450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  116453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  116475 */     // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  116475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  116478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  116480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  116485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  116490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116505 */     GIR_RootConstrainSelectedInstOperands,
     /*  116506 */     // GIR_Coverage, 15697,
     /*  116506 */     GIR_EraseRootFromParent_Done,
     /*  116507 */   // Label 1622: @116507
     /*  116507 */   GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(116564), // Rule ID 29497 //
     /*  116512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  116515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  116520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  116535 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  116535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  116538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  116545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  116550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  116555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116562 */     GIR_RootConstrainSelectedInstOperands,
     /*  116563 */     // GIR_Coverage, 29497,
     /*  116563 */     GIR_EraseRootFromParent_Done,
     /*  116564 */   // Label 1623: @116564
     /*  116564 */   GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(116621), // Rule ID 29498 //
     /*  116569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  116572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  116577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  116592 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  116592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  116595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  116602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  116607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  116612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116615 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116619 */     GIR_RootConstrainSelectedInstOperands,
     /*  116620 */     // GIR_Coverage, 29498,
     /*  116620 */     GIR_EraseRootFromParent_Done,
     /*  116621 */   // Label 1624: @116621
     /*  116621 */   GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(116678), // Rule ID 29499 //
     /*  116626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  116629 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  116634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116638 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116642 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  116649 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  116649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  116652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  116659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  116664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  116669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116676 */     GIR_RootConstrainSelectedInstOperands,
     /*  116677 */     // GIR_Coverage, 29499,
     /*  116677 */     GIR_EraseRootFromParent_Done,
     /*  116678 */   // Label 1625: @116678
     /*  116678 */   GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(116735), // Rule ID 29500 //
     /*  116683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  116686 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  116691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  116706 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  116706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  116709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  116716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  116721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  116726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116733 */     GIR_RootConstrainSelectedInstOperands,
     /*  116734 */     // GIR_Coverage, 29500,
     /*  116734 */     GIR_EraseRootFromParent_Done,
     /*  116735 */   // Label 1626: @116735
     /*  116735 */   GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(116792), // Rule ID 29501 //
     /*  116740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  116743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  116748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  116763 */     // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  116763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  116766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  116773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  116778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  116783 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  116786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116790 */     GIR_RootConstrainSelectedInstOperands,
     /*  116791 */     // GIR_Coverage, 29501,
     /*  116791 */     GIR_EraseRootFromParent_Done,
     /*  116792 */   // Label 1627: @116792
     /*  116792 */   GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(116853), // Rule ID 12423 //
     /*  116797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  116800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  116822 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  116822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  116825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  116832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  116837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  116847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116851 */     GIR_RootConstrainSelectedInstOperands,
     /*  116852 */     // GIR_Coverage, 12423,
     /*  116852 */     GIR_EraseRootFromParent_Done,
     /*  116853 */   // Label 1628: @116853
     /*  116853 */   GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(116914), // Rule ID 12424 //
     /*  116858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  116861 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  116883 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  116883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  116886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  116893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  116898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  116908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116912 */     GIR_RootConstrainSelectedInstOperands,
     /*  116913 */     // GIR_Coverage, 12424,
     /*  116913 */     GIR_EraseRootFromParent_Done,
     /*  116914 */   // Label 1629: @116914
     /*  116914 */   GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(116975), // Rule ID 12425 //
     /*  116919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  116922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  116944 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  116944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  116947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  116949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  116954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  116959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  116964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  116969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  116973 */     GIR_RootConstrainSelectedInstOperands,
     /*  116974 */     // GIR_Coverage, 12425,
     /*  116974 */     GIR_EraseRootFromParent_Done,
     /*  116975 */   // Label 1630: @116975
     /*  116975 */   GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(117036), // Rule ID 12426 //
     /*  116980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  116983 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  116990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  116994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  116998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117005 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  117008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117034 */     GIR_RootConstrainSelectedInstOperands,
     /*  117035 */     // GIR_Coverage, 12426,
     /*  117035 */     GIR_EraseRootFromParent_Done,
     /*  117036 */   // Label 1631: @117036
     /*  117036 */   GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(117097), // Rule ID 12427 //
     /*  117041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  117044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117066 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  117069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117095 */     GIR_RootConstrainSelectedInstOperands,
     /*  117096 */     // GIR_Coverage, 12427,
     /*  117096 */     GIR_EraseRootFromParent_Done,
     /*  117097 */   // Label 1632: @117097
     /*  117097 */   GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(117151), // Rule ID 12418 //
     /*  117102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  117105 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117120 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  117127 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  117130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117149 */     GIR_RootConstrainSelectedInstOperands,
     /*  117150 */     // GIR_Coverage, 12418,
     /*  117150 */     GIR_EraseRootFromParent_Done,
     /*  117151 */   // Label 1633: @117151
     /*  117151 */   GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(117205), // Rule ID 12419 //
     /*  117156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  117159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  117181 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  117184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117203 */     GIR_RootConstrainSelectedInstOperands,
     /*  117204 */     // GIR_Coverage, 12419,
     /*  117204 */     GIR_EraseRootFromParent_Done,
     /*  117205 */   // Label 1634: @117205
     /*  117205 */   GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(117259), // Rule ID 12420 //
     /*  117210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  117213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  117235 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  117238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117257 */     GIR_RootConstrainSelectedInstOperands,
     /*  117258 */     // GIR_Coverage, 12420,
     /*  117258 */     GIR_EraseRootFromParent_Done,
     /*  117259 */   // Label 1635: @117259
     /*  117259 */   GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(117313), // Rule ID 12421 //
     /*  117264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  117267 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  117289 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  117292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117311 */     GIR_RootConstrainSelectedInstOperands,
     /*  117312 */     // GIR_Coverage, 12421,
     /*  117312 */     GIR_EraseRootFromParent_Done,
     /*  117313 */   // Label 1636: @117313
     /*  117313 */   GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(117367), // Rule ID 12422 //
     /*  117318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  117321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117332 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  117343 */     // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  117346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117365 */     GIR_RootConstrainSelectedInstOperands,
     /*  117366 */     // GIR_Coverage, 12422,
     /*  117366 */     GIR_EraseRootFromParent_Done,
     /*  117367 */   // Label 1637: @117367
     /*  117367 */   GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(117429), // Rule ID 10291 //
     /*  117372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  117375 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117398 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  117401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117427 */     GIR_RootConstrainSelectedInstOperands,
     /*  117428 */     // GIR_Coverage, 10291,
     /*  117428 */     GIR_EraseRootFromParent_Done,
     /*  117429 */   // Label 1638: @117429
     /*  117429 */   GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(117491), // Rule ID 10292 //
     /*  117434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  117437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117460 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  117463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117485 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117489 */     GIR_RootConstrainSelectedInstOperands,
     /*  117490 */     // GIR_Coverage, 10292,
     /*  117490 */     GIR_EraseRootFromParent_Done,
     /*  117491 */   // Label 1639: @117491
     /*  117491 */   GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(117553), // Rule ID 10293 //
     /*  117496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  117499 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117522 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  117525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117551 */     GIR_RootConstrainSelectedInstOperands,
     /*  117552 */     // GIR_Coverage, 10293,
     /*  117552 */     GIR_EraseRootFromParent_Done,
     /*  117553 */   // Label 1640: @117553
     /*  117553 */   GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(117615), // Rule ID 10294 //
     /*  117558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  117561 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117584 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  117587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117613 */     GIR_RootConstrainSelectedInstOperands,
     /*  117614 */     // GIR_Coverage, 10294,
     /*  117614 */     GIR_EraseRootFromParent_Done,
     /*  117615 */   // Label 1641: @117615
     /*  117615 */   GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(117677), // Rule ID 10295 //
     /*  117620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  117623 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  117646 */     // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  117649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  117656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  117661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  117666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  117671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117675 */     GIR_RootConstrainSelectedInstOperands,
     /*  117676 */     // GIR_Coverage, 10295,
     /*  117676 */     GIR_EraseRootFromParent_Done,
     /*  117677 */   // Label 1642: @117677
     /*  117677 */   GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(117732), // Rule ID 10286 //
     /*  117682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  117685 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117697 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  117708 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  117711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117730 */     GIR_RootConstrainSelectedInstOperands,
     /*  117731 */     // GIR_Coverage, 10286,
     /*  117731 */     GIR_EraseRootFromParent_Done,
     /*  117732 */   // Label 1643: @117732
     /*  117732 */   GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(117787), // Rule ID 10287 //
     /*  117737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  117740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  117763 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  117766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117785 */     GIR_RootConstrainSelectedInstOperands,
     /*  117786 */     // GIR_Coverage, 10287,
     /*  117786 */     GIR_EraseRootFromParent_Done,
     /*  117787 */   // Label 1644: @117787
     /*  117787 */   GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(117842), // Rule ID 10288 //
     /*  117792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  117795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  117818 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  117821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117840 */     GIR_RootConstrainSelectedInstOperands,
     /*  117841 */     // GIR_Coverage, 10288,
     /*  117841 */     GIR_EraseRootFromParent_Done,
     /*  117842 */   // Label 1645: @117842
     /*  117842 */   GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(117897), // Rule ID 10289 //
     /*  117847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  117850 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  117873 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  117876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117895 */     GIR_RootConstrainSelectedInstOperands,
     /*  117896 */     // GIR_Coverage, 10289,
     /*  117896 */     GIR_EraseRootFromParent_Done,
     /*  117897 */   // Label 1646: @117897
     /*  117897 */   GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(117952), // Rule ID 10290 //
     /*  117902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  117905 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  117913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  117917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  117928 */     // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  117928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  117931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  117933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  117938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  117943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  117946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  117950 */     GIR_RootConstrainSelectedInstOperands,
     /*  117951 */     // GIR_Coverage, 10290,
     /*  117951 */     GIR_EraseRootFromParent_Done,
     /*  117952 */   // Label 1647: @117952
     /*  117952 */   GIM_Reject,
     /*  117953 */ // Label 1545: @117953
     /*  117953 */ GIM_Reject,
     /*  117954 */ // Label 1123: @117954
     /*  117954 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(123704),
     /*  117959 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  117962 */   GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(118028), // Rule ID 8755 //
     /*  117967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  117970 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  117974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  117978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  117982 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  117986 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  117990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  117997 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  117997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  118000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  118022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118026 */     GIR_RootConstrainSelectedInstOperands,
     /*  118027 */     // GIR_Coverage, 8755,
     /*  118027 */     GIR_EraseRootFromParent_Done,
     /*  118028 */   // Label 1649: @118028
     /*  118028 */   GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(118090), // Rule ID 8761 //
     /*  118033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  118036 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118044 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118048 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  118059 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  118059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  118062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  118084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118088 */     GIR_RootConstrainSelectedInstOperands,
     /*  118089 */     // GIR_Coverage, 8761,
     /*  118089 */     GIR_EraseRootFromParent_Done,
     /*  118090 */   // Label 1650: @118090
     /*  118090 */   GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(118149), // Rule ID 8751 //
     /*  118095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  118098 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118110 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118114 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  118118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  118125 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  118125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  118128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  118140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118147 */     GIR_RootConstrainSelectedInstOperands,
     /*  118148 */     // GIR_Coverage, 8751,
     /*  118148 */     GIR_EraseRootFromParent_Done,
     /*  118149 */   // Label 1651: @118149
     /*  118149 */   GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(118208), // Rule ID 8752 //
     /*  118154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  118157 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118169 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118173 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  118177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  118184 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  118184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  118187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  118199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118206 */     GIR_RootConstrainSelectedInstOperands,
     /*  118207 */     // GIR_Coverage, 8752,
     /*  118207 */     GIR_EraseRootFromParent_Done,
     /*  118208 */   // Label 1652: @118208
     /*  118208 */   GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(118260), // Rule ID 8757 //
     /*  118213 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118225 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  118236 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  118236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  118239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  118251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118258 */     GIR_RootConstrainSelectedInstOperands,
     /*  118259 */     // GIR_Coverage, 8757,
     /*  118259 */     GIR_EraseRootFromParent_Done,
     /*  118260 */   // Label 1653: @118260
     /*  118260 */   GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(118315), // Rule ID 8758 //
     /*  118265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  118268 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118280 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  118291 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  118291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  118294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  118306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118313 */     GIR_RootConstrainSelectedInstOperands,
     /*  118314 */     // GIR_Coverage, 8758,
     /*  118314 */     GIR_EraseRootFromParent_Done,
     /*  118315 */   // Label 1654: @118315
     /*  118315 */   GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(118374), // Rule ID 8753 //
     /*  118320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  118323 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118335 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118339 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  118343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  118350 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  118350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  118353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118372 */     GIR_RootConstrainSelectedInstOperands,
     /*  118373 */     // GIR_Coverage, 8753,
     /*  118373 */     GIR_EraseRootFromParent_Done,
     /*  118374 */   // Label 1655: @118374
     /*  118374 */   GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(118438), // Rule ID 8754 //
     /*  118379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  118382 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118394 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118398 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  118402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  118409 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  118409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  118412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  118432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118436 */     GIR_RootConstrainSelectedInstOperands,
     /*  118437 */     // GIR_Coverage, 8754,
     /*  118437 */     GIR_EraseRootFromParent_Done,
     /*  118438 */   // Label 1656: @118438
     /*  118438 */   GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(118489), // Rule ID 8756 //
     /*  118443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  118446 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118454 */     // MIs[0] sbase
     /*  118454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  118458 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  118462 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118466 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  118470 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  118470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  118473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118475 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  118477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118487 */     GIR_RootConstrainSelectedInstOperands,
     /*  118488 */     // GIR_Coverage, 8756,
     /*  118488 */     GIR_EraseRootFromParent_Done,
     /*  118489 */   // Label 1657: @118489
     /*  118489 */   GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(118544), // Rule ID 8759 //
     /*  118494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  118497 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118505 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118509 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  118520 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  118520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  118523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118542 */     GIR_RootConstrainSelectedInstOperands,
     /*  118543 */     // GIR_Coverage, 8759,
     /*  118543 */     GIR_EraseRootFromParent_Done,
     /*  118544 */   // Label 1658: @118544
     /*  118544 */   GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(118604), // Rule ID 8760 //
     /*  118549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  118552 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118564 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118568 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  118575 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  118575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  118578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  118585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  118598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118602 */     GIR_RootConstrainSelectedInstOperands,
     /*  118603 */     // GIR_Coverage, 8760,
     /*  118603 */     GIR_EraseRootFromParent_Done,
     /*  118604 */   // Label 1659: @118604
     /*  118604 */   GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(118648), // Rule ID 8762 //
     /*  118609 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  118613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  118617 */     // MIs[0] sbase
     /*  118617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  118621 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  118625 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  118629 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  118629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  118632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  118634 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  118636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118646 */     GIR_RootConstrainSelectedInstOperands,
     /*  118647 */     // GIR_Coverage, 8762,
     /*  118647 */     GIR_EraseRootFromParent_Done,
     /*  118648 */   // Label 1660: @118648
     /*  118648 */   GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(118708), // Rule ID 25296 //
     /*  118653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  118656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  118661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  118665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  118676 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  118676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  118679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  118681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  118686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118702 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118706 */     GIR_RootConstrainSelectedInstOperands,
     /*  118707 */     // GIR_Coverage, 25296,
     /*  118707 */     GIR_EraseRootFromParent_Done,
     /*  118708 */   // Label 1661: @118708
     /*  118708 */   GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(118768), // Rule ID 25297 //
     /*  118713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  118716 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  118721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  118725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  118736 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  118736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  118739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  118741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  118746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118766 */     GIR_RootConstrainSelectedInstOperands,
     /*  118767 */     // GIR_Coverage, 25297,
     /*  118767 */     GIR_EraseRootFromParent_Done,
     /*  118768 */   // Label 1662: @118768
     /*  118768 */   GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(118828), // Rule ID 25298 //
     /*  118773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  118776 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  118781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  118785 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118789 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  118796 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  118796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  118799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  118801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  118806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118822 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118826 */     GIR_RootConstrainSelectedInstOperands,
     /*  118827 */     // GIR_Coverage, 25298,
     /*  118827 */     GIR_EraseRootFromParent_Done,
     /*  118828 */   // Label 1663: @118828
     /*  118828 */   GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(118888), // Rule ID 25299 //
     /*  118833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  118836 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  118841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  118845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  118856 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  118856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  118859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  118861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  118866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118886 */     GIR_RootConstrainSelectedInstOperands,
     /*  118887 */     // GIR_Coverage, 25299,
     /*  118887 */     GIR_EraseRootFromParent_Done,
     /*  118888 */   // Label 1664: @118888
     /*  118888 */   GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(118948), // Rule ID 25300 //
     /*  118893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  118896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  118901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  118905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  118916 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  118916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  118919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  118921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  118926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  118946 */     GIR_RootConstrainSelectedInstOperands,
     /*  118947 */     // GIR_Coverage, 25300,
     /*  118947 */     GIR_EraseRootFromParent_Done,
     /*  118948 */   // Label 1665: @118948
     /*  118948 */   GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(119008), // Rule ID 25306 //
     /*  118953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  118956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  118961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  118965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  118969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  118976 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  118976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  118979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  118981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  118986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  118991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  118996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  118999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119006 */     GIR_RootConstrainSelectedInstOperands,
     /*  119007 */     // GIR_Coverage, 25306,
     /*  119007 */     GIR_EraseRootFromParent_Done,
     /*  119008 */   // Label 1666: @119008
     /*  119008 */   GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(119068), // Rule ID 25307 //
     /*  119013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  119016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119025 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119029 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  119036 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  119036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  119039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  119041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  119046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  119051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119066 */     GIR_RootConstrainSelectedInstOperands,
     /*  119067 */     // GIR_Coverage, 25307,
     /*  119067 */     GIR_EraseRootFromParent_Done,
     /*  119068 */   // Label 1667: @119068
     /*  119068 */   GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(119128), // Rule ID 25308 //
     /*  119073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  119076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119085 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  119096 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  119096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  119099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  119101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  119106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  119111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119126 */     GIR_RootConstrainSelectedInstOperands,
     /*  119127 */     // GIR_Coverage, 25308,
     /*  119127 */     GIR_EraseRootFromParent_Done,
     /*  119128 */   // Label 1668: @119128
     /*  119128 */   GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(119188), // Rule ID 25309 //
     /*  119133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  119136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119145 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119149 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  119156 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  119156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  119159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  119161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  119166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  119171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119186 */     GIR_RootConstrainSelectedInstOperands,
     /*  119187 */     // GIR_Coverage, 25309,
     /*  119187 */     GIR_EraseRootFromParent_Done,
     /*  119188 */   // Label 1669: @119188
     /*  119188 */   GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(119248), // Rule ID 25310 //
     /*  119193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  119196 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  119216 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  119216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  119219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  119221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  119226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  119231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119246 */     GIR_RootConstrainSelectedInstOperands,
     /*  119247 */     // GIR_Coverage, 25310,
     /*  119247 */     GIR_EraseRootFromParent_Done,
     /*  119248 */   // Label 1670: @119248
     /*  119248 */   GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(119307), // Rule ID 14242 //
     /*  119253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  119256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  119276 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  119276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  119279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  119291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  119301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119305 */     GIR_RootConstrainSelectedInstOperands,
     /*  119306 */     // GIR_Coverage, 14242,
     /*  119306 */     GIR_EraseRootFromParent_Done,
     /*  119307 */   // Label 1671: @119307
     /*  119307 */   GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(119366), // Rule ID 14243 //
     /*  119312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  119315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  119335 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  119335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  119338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  119350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  119360 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119364 */     GIR_RootConstrainSelectedInstOperands,
     /*  119365 */     // GIR_Coverage, 14243,
     /*  119365 */     GIR_EraseRootFromParent_Done,
     /*  119366 */   // Label 1672: @119366
     /*  119366 */   GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(119425), // Rule ID 14244 //
     /*  119371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  119374 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119383 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  119394 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  119394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  119397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  119409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  119419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119423 */     GIR_RootConstrainSelectedInstOperands,
     /*  119424 */     // GIR_Coverage, 14244,
     /*  119424 */     GIR_EraseRootFromParent_Done,
     /*  119425 */   // Label 1673: @119425
     /*  119425 */   GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(119484), // Rule ID 14245 //
     /*  119430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  119433 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119442 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119446 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  119453 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  119453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  119456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  119468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  119478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119482 */     GIR_RootConstrainSelectedInstOperands,
     /*  119483 */     // GIR_Coverage, 14245,
     /*  119483 */     GIR_EraseRootFromParent_Done,
     /*  119484 */   // Label 1674: @119484
     /*  119484 */   GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(119543), // Rule ID 14246 //
     /*  119489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  119492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  119512 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  119512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  119515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  119527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  119532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  119537 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119541 */     GIR_RootConstrainSelectedInstOperands,
     /*  119542 */     // GIR_Coverage, 14246,
     /*  119542 */     GIR_EraseRootFromParent_Done,
     /*  119543 */   // Label 1675: @119543
     /*  119543 */   GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(119595), // Rule ID 14237 //
     /*  119548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  119551 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  119571 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  119571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  119574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  119581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119593 */     GIR_RootConstrainSelectedInstOperands,
     /*  119594 */     // GIR_Coverage, 14237,
     /*  119594 */     GIR_EraseRootFromParent_Done,
     /*  119595 */   // Label 1676: @119595
     /*  119595 */   GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(119647), // Rule ID 14238 //
     /*  119600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  119603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  119623 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  119623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  119626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  119633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119641 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119645 */     GIR_RootConstrainSelectedInstOperands,
     /*  119646 */     // GIR_Coverage, 14238,
     /*  119646 */     GIR_EraseRootFromParent_Done,
     /*  119647 */   // Label 1677: @119647
     /*  119647 */   GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(119699), // Rule ID 14239 //
     /*  119652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  119655 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  119675 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  119675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  119678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  119685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119697 */     GIR_RootConstrainSelectedInstOperands,
     /*  119698 */     // GIR_Coverage, 14239,
     /*  119698 */     GIR_EraseRootFromParent_Done,
     /*  119699 */   // Label 1678: @119699
     /*  119699 */   GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(119751), // Rule ID 14240 //
     /*  119704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  119707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  119727 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  119727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  119730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  119737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119749 */     GIR_RootConstrainSelectedInstOperands,
     /*  119750 */     // GIR_Coverage, 14240,
     /*  119750 */     GIR_EraseRootFromParent_Done,
     /*  119751 */   // Label 1679: @119751
     /*  119751 */   GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(119803), // Rule ID 14241 //
     /*  119756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  119759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119768 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  119779 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  119779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  119782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  119789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119797 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119801 */     GIR_RootConstrainSelectedInstOperands,
     /*  119802 */     // GIR_Coverage, 14241,
     /*  119802 */     GIR_EraseRootFromParent_Done,
     /*  119803 */   // Label 1680: @119803
     /*  119803 */   GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(119855), // Rule ID 14232 //
     /*  119808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  119811 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119820 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119824 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  119831 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  119831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  119834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119853 */     GIR_RootConstrainSelectedInstOperands,
     /*  119854 */     // GIR_Coverage, 14232,
     /*  119854 */     GIR_EraseRootFromParent_Done,
     /*  119855 */   // Label 1681: @119855
     /*  119855 */   GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(119907), // Rule ID 14233 //
     /*  119860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  119863 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  119883 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  119883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  119886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119905 */     GIR_RootConstrainSelectedInstOperands,
     /*  119906 */     // GIR_Coverage, 14233,
     /*  119906 */     GIR_EraseRootFromParent_Done,
     /*  119907 */   // Label 1682: @119907
     /*  119907 */   GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(119959), // Rule ID 14234 //
     /*  119912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  119915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  119935 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  119935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  119938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  119950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  119953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  119957 */     GIR_RootConstrainSelectedInstOperands,
     /*  119958 */     // GIR_Coverage, 14234,
     /*  119958 */     GIR_EraseRootFromParent_Done,
     /*  119959 */   // Label 1683: @119959
     /*  119959 */   GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(120011), // Rule ID 14235 //
     /*  119964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  119967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  119972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  119976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  119980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  119987 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  119987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  119990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  119992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  119997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  120002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120009 */     GIR_RootConstrainSelectedInstOperands,
     /*  120010 */     // GIR_Coverage, 14235,
     /*  120010 */     GIR_EraseRootFromParent_Done,
     /*  120011 */   // Label 1684: @120011
     /*  120011 */   GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(120063), // Rule ID 14236 //
     /*  120016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  120019 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  120024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120028 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120032 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  120039 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  120039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  120042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  120044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  120049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  120054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120061 */     GIR_RootConstrainSelectedInstOperands,
     /*  120062 */     // GIR_Coverage, 14236,
     /*  120062 */     GIR_EraseRootFromParent_Done,
     /*  120063 */   // Label 1685: @120063
     /*  120063 */   GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(120130), // Rule ID 15488 //
     /*  120068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  120071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120093 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  120096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120128 */     GIR_RootConstrainSelectedInstOperands,
     /*  120129 */     // GIR_Coverage, 15488,
     /*  120129 */     GIR_EraseRootFromParent_Done,
     /*  120130 */   // Label 1686: @120130
     /*  120130 */   GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(120197), // Rule ID 15489 //
     /*  120135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  120138 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120160 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  120163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120195 */     GIR_RootConstrainSelectedInstOperands,
     /*  120196 */     // GIR_Coverage, 15489,
     /*  120196 */     GIR_EraseRootFromParent_Done,
     /*  120197 */   // Label 1687: @120197
     /*  120197 */   GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(120264), // Rule ID 15490 //
     /*  120202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  120205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120227 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  120230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120262 */     GIR_RootConstrainSelectedInstOperands,
     /*  120263 */     // GIR_Coverage, 15490,
     /*  120263 */     GIR_EraseRootFromParent_Done,
     /*  120264 */   // Label 1688: @120264
     /*  120264 */   GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(120331), // Rule ID 15491 //
     /*  120269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  120272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120294 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  120297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120329 */     GIR_RootConstrainSelectedInstOperands,
     /*  120330 */     // GIR_Coverage, 15491,
     /*  120330 */     GIR_EraseRootFromParent_Done,
     /*  120331 */   // Label 1689: @120331
     /*  120331 */   GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(120398), // Rule ID 15492 //
     /*  120336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  120339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120361 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  120364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120396 */     GIR_RootConstrainSelectedInstOperands,
     /*  120397 */     // GIR_Coverage, 15492,
     /*  120397 */     GIR_EraseRootFromParent_Done,
     /*  120398 */   // Label 1690: @120398
     /*  120398 */   GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(120465), // Rule ID 15498 //
     /*  120403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  120406 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120428 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  120431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120463 */     GIR_RootConstrainSelectedInstOperands,
     /*  120464 */     // GIR_Coverage, 15498,
     /*  120464 */     GIR_EraseRootFromParent_Done,
     /*  120465 */   // Label 1691: @120465
     /*  120465 */   GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(120532), // Rule ID 15499 //
     /*  120470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  120473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120495 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  120498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120530 */     GIR_RootConstrainSelectedInstOperands,
     /*  120531 */     // GIR_Coverage, 15499,
     /*  120531 */     GIR_EraseRootFromParent_Done,
     /*  120532 */   // Label 1692: @120532
     /*  120532 */   GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(120599), // Rule ID 15500 //
     /*  120537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  120540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120562 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  120565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120597 */     GIR_RootConstrainSelectedInstOperands,
     /*  120598 */     // GIR_Coverage, 15500,
     /*  120598 */     GIR_EraseRootFromParent_Done,
     /*  120599 */   // Label 1693: @120599
     /*  120599 */   GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(120666), // Rule ID 15501 //
     /*  120604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  120607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120629 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  120632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120664 */     GIR_RootConstrainSelectedInstOperands,
     /*  120665 */     // GIR_Coverage, 15501,
     /*  120665 */     GIR_EraseRootFromParent_Done,
     /*  120666 */   // Label 1694: @120666
     /*  120666 */   GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(120733), // Rule ID 15502 //
     /*  120671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  120674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  120681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  120696 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  120696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  120699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120731 */     GIR_RootConstrainSelectedInstOperands,
     /*  120732 */     // GIR_Coverage, 15502,
     /*  120732 */     GIR_EraseRootFromParent_Done,
     /*  120733 */   // Label 1695: @120733
     /*  120733 */   GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(120798), // Rule ID 25291 //
     /*  120738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  120741 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  120746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120754 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  120761 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  120761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  120764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120796 */     GIR_RootConstrainSelectedInstOperands,
     /*  120797 */     // GIR_Coverage, 25291,
     /*  120797 */     GIR_EraseRootFromParent_Done,
     /*  120798 */   // Label 1696: @120798
     /*  120798 */   GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(120863), // Rule ID 25292 //
     /*  120803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  120806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  120811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  120826 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  120826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  120829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120861 */     GIR_RootConstrainSelectedInstOperands,
     /*  120862 */     // GIR_Coverage, 25292,
     /*  120862 */     GIR_EraseRootFromParent_Done,
     /*  120863 */   // Label 1697: @120863
     /*  120863 */   GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(120928), // Rule ID 25293 //
     /*  120868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  120871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  120876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  120891 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  120891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  120894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120926 */     GIR_RootConstrainSelectedInstOperands,
     /*  120927 */     // GIR_Coverage, 25293,
     /*  120927 */     GIR_EraseRootFromParent_Done,
     /*  120928 */   // Label 1698: @120928
     /*  120928 */   GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(120993), // Rule ID 25294 //
     /*  120933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  120936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  120941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  120945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  120949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  120956 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  120956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  120959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  120961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  120966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  120971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  120976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  120981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  120987 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  120991 */     GIR_RootConstrainSelectedInstOperands,
     /*  120992 */     // GIR_Coverage, 25294,
     /*  120992 */     GIR_EraseRootFromParent_Done,
     /*  120993 */   // Label 1699: @120993
     /*  120993 */   GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(121058), // Rule ID 25295 //
     /*  120998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  121001 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  121006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121010 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121014 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  121021 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  121021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  121024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  121031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  121041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  121046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121056 */     GIR_RootConstrainSelectedInstOperands,
     /*  121057 */     // GIR_Coverage, 25295,
     /*  121057 */     GIR_EraseRootFromParent_Done,
     /*  121058 */   // Label 1700: @121058
     /*  121058 */   GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(121123), // Rule ID 25301 //
     /*  121063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  121066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  121071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  121086 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  121086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  121089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  121096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  121106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  121111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121121 */     GIR_RootConstrainSelectedInstOperands,
     /*  121122 */     // GIR_Coverage, 25301,
     /*  121122 */     GIR_EraseRootFromParent_Done,
     /*  121123 */   // Label 1701: @121123
     /*  121123 */   GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(121188), // Rule ID 25302 //
     /*  121128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  121131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  121136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  121151 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  121151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  121154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  121161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  121171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  121176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121186 */     GIR_RootConstrainSelectedInstOperands,
     /*  121187 */     // GIR_Coverage, 25302,
     /*  121187 */     GIR_EraseRootFromParent_Done,
     /*  121188 */   // Label 1702: @121188
     /*  121188 */   GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(121253), // Rule ID 25303 //
     /*  121193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  121196 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  121201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  121216 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  121216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  121219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  121226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  121236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  121241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121251 */     GIR_RootConstrainSelectedInstOperands,
     /*  121252 */     // GIR_Coverage, 25303,
     /*  121252 */     GIR_EraseRootFromParent_Done,
     /*  121253 */   // Label 1703: @121253
     /*  121253 */   GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(121318), // Rule ID 25304 //
     /*  121258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  121261 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  121266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121270 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121274 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  121281 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  121281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  121284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  121291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  121301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  121306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121316 */     GIR_RootConstrainSelectedInstOperands,
     /*  121317 */     // GIR_Coverage, 25304,
     /*  121317 */     GIR_EraseRootFromParent_Done,
     /*  121318 */   // Label 1704: @121318
     /*  121318 */   GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(121383), // Rule ID 25305 //
     /*  121323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  121326 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  121331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  121346 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  121346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  121349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  121356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  121366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  121371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121381 */     GIR_RootConstrainSelectedInstOperands,
     /*  121382 */     // GIR_Coverage, 25305,
     /*  121382 */     GIR_EraseRootFromParent_Done,
     /*  121383 */   // Label 1705: @121383
     /*  121383 */   GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(121445), // Rule ID 15483 //
     /*  121388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  121391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121413 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  121416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121443 */     GIR_RootConstrainSelectedInstOperands,
     /*  121444 */     // GIR_Coverage, 15483,
     /*  121444 */     GIR_EraseRootFromParent_Done,
     /*  121445 */   // Label 1706: @121445
     /*  121445 */   GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(121507), // Rule ID 15484 //
     /*  121450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  121453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121475 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  121478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121505 */     GIR_RootConstrainSelectedInstOperands,
     /*  121506 */     // GIR_Coverage, 15484,
     /*  121506 */     GIR_EraseRootFromParent_Done,
     /*  121507 */   // Label 1707: @121507
     /*  121507 */   GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(121569), // Rule ID 15485 //
     /*  121512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  121515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121537 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  121540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121567 */     GIR_RootConstrainSelectedInstOperands,
     /*  121568 */     // GIR_Coverage, 15485,
     /*  121568 */     GIR_EraseRootFromParent_Done,
     /*  121569 */   // Label 1708: @121569
     /*  121569 */   GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(121631), // Rule ID 15486 //
     /*  121574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  121577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121599 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  121602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121629 */     GIR_RootConstrainSelectedInstOperands,
     /*  121630 */     // GIR_Coverage, 15486,
     /*  121630 */     GIR_EraseRootFromParent_Done,
     /*  121631 */   // Label 1709: @121631
     /*  121631 */   GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(121693), // Rule ID 15487 //
     /*  121636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  121639 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121661 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  121664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121691 */     GIR_RootConstrainSelectedInstOperands,
     /*  121692 */     // GIR_Coverage, 15487,
     /*  121692 */     GIR_EraseRootFromParent_Done,
     /*  121693 */   // Label 1710: @121693
     /*  121693 */   GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(121755), // Rule ID 15493 //
     /*  121698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  121701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121723 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  121726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121749 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121753 */     GIR_RootConstrainSelectedInstOperands,
     /*  121754 */     // GIR_Coverage, 15493,
     /*  121754 */     GIR_EraseRootFromParent_Done,
     /*  121755 */   // Label 1711: @121755
     /*  121755 */   GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(121817), // Rule ID 15494 //
     /*  121760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  121763 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121785 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  121788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121815 */     GIR_RootConstrainSelectedInstOperands,
     /*  121816 */     // GIR_Coverage, 15494,
     /*  121816 */     GIR_EraseRootFromParent_Done,
     /*  121817 */   // Label 1712: @121817
     /*  121817 */   GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(121879), // Rule ID 15495 //
     /*  121822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  121825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121847 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  121850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121877 */     GIR_RootConstrainSelectedInstOperands,
     /*  121878 */     // GIR_Coverage, 15495,
     /*  121878 */     GIR_EraseRootFromParent_Done,
     /*  121879 */   // Label 1713: @121879
     /*  121879 */   GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(121941), // Rule ID 15496 //
     /*  121884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  121887 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121909 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  121912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121932 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121935 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  121939 */     GIR_RootConstrainSelectedInstOperands,
     /*  121940 */     // GIR_Coverage, 15496,
     /*  121940 */     GIR_EraseRootFromParent_Done,
     /*  121941 */   // Label 1714: @121941
     /*  121941 */   GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(122003), // Rule ID 15497 //
     /*  121946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  121949 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  121956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  121960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  121964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  121971 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  121971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  121974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  121976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  121981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  121986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  121991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  121997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122001 */     GIR_RootConstrainSelectedInstOperands,
     /*  122002 */     // GIR_Coverage, 15497,
     /*  122002 */     GIR_EraseRootFromParent_Done,
     /*  122003 */   // Label 1715: @122003
     /*  122003 */   GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(122059), // Rule ID 28957 //
     /*  122008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  122011 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  122015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122035 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  122038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122057 */     GIR_RootConstrainSelectedInstOperands,
     /*  122058 */     // GIR_Coverage, 28957,
     /*  122058 */     GIR_EraseRootFromParent_Done,
     /*  122059 */   // Label 1716: @122059
     /*  122059 */   GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(122115), // Rule ID 28958 //
     /*  122064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  122067 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  122071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122091 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  122094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122113 */     GIR_RootConstrainSelectedInstOperands,
     /*  122114 */     // GIR_Coverage, 28958,
     /*  122114 */     GIR_EraseRootFromParent_Done,
     /*  122115 */   // Label 1717: @122115
     /*  122115 */   GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(122171), // Rule ID 28959 //
     /*  122120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  122123 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  122127 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122147 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  122150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122165 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122169 */     GIR_RootConstrainSelectedInstOperands,
     /*  122170 */     // GIR_Coverage, 28959,
     /*  122170 */     GIR_EraseRootFromParent_Done,
     /*  122171 */   // Label 1718: @122171
     /*  122171 */   GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(122227), // Rule ID 28960 //
     /*  122176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  122179 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  122183 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122203 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  122206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122221 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122225 */     GIR_RootConstrainSelectedInstOperands,
     /*  122226 */     // GIR_Coverage, 28960,
     /*  122226 */     GIR_EraseRootFromParent_Done,
     /*  122227 */   // Label 1719: @122227
     /*  122227 */   GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(122283), // Rule ID 28961 //
     /*  122232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  122235 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  122239 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122259 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  122262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122281 */     GIR_RootConstrainSelectedInstOperands,
     /*  122282 */     // GIR_Coverage, 28961,
     /*  122282 */     GIR_EraseRootFromParent_Done,
     /*  122283 */   // Label 1720: @122283
     /*  122283 */   GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(122335), // Rule ID 28962 //
     /*  122288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  122291 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122311 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  122314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122333 */     GIR_RootConstrainSelectedInstOperands,
     /*  122334 */     // GIR_Coverage, 28962,
     /*  122334 */     GIR_EraseRootFromParent_Done,
     /*  122335 */   // Label 1721: @122335
     /*  122335 */   GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(122387), // Rule ID 28963 //
     /*  122340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  122343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122352 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122363 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  122366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122381 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122385 */     GIR_RootConstrainSelectedInstOperands,
     /*  122386 */     // GIR_Coverage, 28963,
     /*  122386 */     GIR_EraseRootFromParent_Done,
     /*  122387 */   // Label 1722: @122387
     /*  122387 */   GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(122439), // Rule ID 28964 //
     /*  122392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  122395 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122415 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  122418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122437 */     GIR_RootConstrainSelectedInstOperands,
     /*  122438 */     // GIR_Coverage, 28964,
     /*  122438 */     GIR_EraseRootFromParent_Done,
     /*  122439 */   // Label 1723: @122439
     /*  122439 */   GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(122491), // Rule ID 28965 //
     /*  122444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  122447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122467 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  122470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122482 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122485 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122489 */     GIR_RootConstrainSelectedInstOperands,
     /*  122490 */     // GIR_Coverage, 28965,
     /*  122490 */     GIR_EraseRootFromParent_Done,
     /*  122491 */   // Label 1724: @122491
     /*  122491 */   GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(122543), // Rule ID 28966 //
     /*  122496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  122499 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  122504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122512 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  122519 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  122519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  122522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  122529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122537 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122541 */     GIR_RootConstrainSelectedInstOperands,
     /*  122542 */     // GIR_Coverage, 28966,
     /*  122542 */     GIR_EraseRootFromParent_Done,
     /*  122543 */   // Label 1725: @122543
     /*  122543 */   GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(122604), // Rule ID 12223 //
     /*  122548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  122551 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122562 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122566 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  122573 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  122573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  122576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  122583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  122588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  122593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  122598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122602 */     GIR_RootConstrainSelectedInstOperands,
     /*  122603 */     // GIR_Coverage, 12223,
     /*  122603 */     GIR_EraseRootFromParent_Done,
     /*  122604 */   // Label 1726: @122604
     /*  122604 */   GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(122665), // Rule ID 12224 //
     /*  122609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  122612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122623 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122627 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  122634 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  122634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  122637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  122644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  122649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  122654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  122659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122663 */     GIR_RootConstrainSelectedInstOperands,
     /*  122664 */     // GIR_Coverage, 12224,
     /*  122664 */     GIR_EraseRootFromParent_Done,
     /*  122665 */   // Label 1727: @122665
     /*  122665 */   GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(122726), // Rule ID 12225 //
     /*  122670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  122673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  122695 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  122695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  122698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  122705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  122710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  122715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  122720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122724 */     GIR_RootConstrainSelectedInstOperands,
     /*  122725 */     // GIR_Coverage, 12225,
     /*  122725 */     GIR_EraseRootFromParent_Done,
     /*  122726 */   // Label 1728: @122726
     /*  122726 */   GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(122787), // Rule ID 12226 //
     /*  122731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  122734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  122756 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  122756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  122759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  122766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  122771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  122776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  122781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122785 */     GIR_RootConstrainSelectedInstOperands,
     /*  122786 */     // GIR_Coverage, 12226,
     /*  122786 */     GIR_EraseRootFromParent_Done,
     /*  122787 */   // Label 1729: @122787
     /*  122787 */   GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(122848), // Rule ID 12227 //
     /*  122792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  122795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122806 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  122817 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  122817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  122820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  122827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  122832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  122837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  122842 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122846 */     GIR_RootConstrainSelectedInstOperands,
     /*  122847 */     // GIR_Coverage, 12227,
     /*  122847 */     GIR_EraseRootFromParent_Done,
     /*  122848 */   // Label 1730: @122848
     /*  122848 */   GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(122902), // Rule ID 12218 //
     /*  122853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  122856 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  122878 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  122878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  122881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  122888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122900 */     GIR_RootConstrainSelectedInstOperands,
     /*  122901 */     // GIR_Coverage, 12218,
     /*  122901 */     GIR_EraseRootFromParent_Done,
     /*  122902 */   // Label 1731: @122902
     /*  122902 */   GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(122956), // Rule ID 12219 //
     /*  122907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  122910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  122932 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  122932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  122935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  122942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  122947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  122950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  122954 */     GIR_RootConstrainSelectedInstOperands,
     /*  122955 */     // GIR_Coverage, 12219,
     /*  122955 */     GIR_EraseRootFromParent_Done,
     /*  122956 */   // Label 1732: @122956
     /*  122956 */   GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(123010), // Rule ID 12220 //
     /*  122961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  122964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  122971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  122975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  122979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  122986 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  122986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  122989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  122991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  122996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123004 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123008 */     GIR_RootConstrainSelectedInstOperands,
     /*  123009 */     // GIR_Coverage, 12220,
     /*  123009 */     GIR_EraseRootFromParent_Done,
     /*  123010 */   // Label 1733: @123010
     /*  123010 */   GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(123064), // Rule ID 12221 //
     /*  123015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  123018 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  123040 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  123043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123062 */     GIR_RootConstrainSelectedInstOperands,
     /*  123063 */     // GIR_Coverage, 12221,
     /*  123063 */     GIR_EraseRootFromParent_Done,
     /*  123064 */   // Label 1734: @123064
     /*  123064 */   GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(123118), // Rule ID 12222 //
     /*  123069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  123072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  123094 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  123097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123112 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123116 */     GIR_RootConstrainSelectedInstOperands,
     /*  123117 */     // GIR_Coverage, 12222,
     /*  123117 */     GIR_EraseRootFromParent_Done,
     /*  123118 */   // Label 1735: @123118
     /*  123118 */   GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(123180), // Rule ID 10081 //
     /*  123123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  123126 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123138 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  123149 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  123152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  123159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  123164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123178 */     GIR_RootConstrainSelectedInstOperands,
     /*  123179 */     // GIR_Coverage, 10081,
     /*  123179 */     GIR_EraseRootFromParent_Done,
     /*  123180 */   // Label 1736: @123180
     /*  123180 */   GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(123242), // Rule ID 10082 //
     /*  123185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  123188 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123200 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  123211 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  123214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  123221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  123226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123240 */     GIR_RootConstrainSelectedInstOperands,
     /*  123241 */     // GIR_Coverage, 10082,
     /*  123241 */     GIR_EraseRootFromParent_Done,
     /*  123242 */   // Label 1737: @123242
     /*  123242 */   GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(123304), // Rule ID 10083 //
     /*  123247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  123250 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123266 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  123273 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  123276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  123283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  123288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123302 */     GIR_RootConstrainSelectedInstOperands,
     /*  123303 */     // GIR_Coverage, 10083,
     /*  123303 */     GIR_EraseRootFromParent_Done,
     /*  123304 */   // Label 1738: @123304
     /*  123304 */   GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(123366), // Rule ID 10084 //
     /*  123309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  123312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  123335 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  123338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  123345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  123350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123360 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123364 */     GIR_RootConstrainSelectedInstOperands,
     /*  123365 */     // GIR_Coverage, 10084,
     /*  123365 */     GIR_EraseRootFromParent_Done,
     /*  123366 */   // Label 1739: @123366
     /*  123366 */   GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(123428), // Rule ID 10085 //
     /*  123371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  123374 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  123397 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  123400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  123407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  123412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123426 */     GIR_RootConstrainSelectedInstOperands,
     /*  123427 */     // GIR_Coverage, 10085,
     /*  123427 */     GIR_EraseRootFromParent_Done,
     /*  123428 */   // Label 1740: @123428
     /*  123428 */   GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(123483), // Rule ID 10076 //
     /*  123433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  123436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  123459 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  123462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123481 */     GIR_RootConstrainSelectedInstOperands,
     /*  123482 */     // GIR_Coverage, 10076,
     /*  123482 */     GIR_EraseRootFromParent_Done,
     /*  123483 */   // Label 1741: @123483
     /*  123483 */   GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(123538), // Rule ID 10077 //
     /*  123488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  123491 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  123514 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  123517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123536 */     GIR_RootConstrainSelectedInstOperands,
     /*  123537 */     // GIR_Coverage, 10077,
     /*  123537 */     GIR_EraseRootFromParent_Done,
     /*  123538 */   // Label 1742: @123538
     /*  123538 */   GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(123593), // Rule ID 10078 //
     /*  123543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  123546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  123569 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  123572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123591 */     GIR_RootConstrainSelectedInstOperands,
     /*  123592 */     // GIR_Coverage, 10078,
     /*  123592 */     GIR_EraseRootFromParent_Done,
     /*  123593 */   // Label 1743: @123593
     /*  123593 */   GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(123648), // Rule ID 10079 //
     /*  123598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  123601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  123624 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  123627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123646 */     GIR_RootConstrainSelectedInstOperands,
     /*  123647 */     // GIR_Coverage, 10079,
     /*  123647 */     GIR_EraseRootFromParent_Done,
     /*  123648 */   // Label 1744: @123648
     /*  123648 */   GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(123703), // Rule ID 10080 //
     /*  123653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  123656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  123664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  123668 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123672 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  123679 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  123679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  123682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  123684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  123689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123701 */     GIR_RootConstrainSelectedInstOperands,
     /*  123702 */     // GIR_Coverage, 10080,
     /*  123702 */     GIR_EraseRootFromParent_Done,
     /*  123703 */   // Label 1745: @123703
     /*  123703 */   GIM_Reject,
     /*  123704 */ // Label 1648: @123704
     /*  123704 */ GIM_Reject,
     /*  123705 */ // Label 1124: @123705
     /*  123705 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(129455),
     /*  123710 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  123713 */   GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(123779), // Rule ID 8767 //
     /*  123718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  123721 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  123725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  123729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123733 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  123737 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  123741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  123748 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  123751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  123753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  123758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  123763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123773 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123777 */     GIR_RootConstrainSelectedInstOperands,
     /*  123778 */     // GIR_Coverage, 8767,
     /*  123778 */     GIR_EraseRootFromParent_Done,
     /*  123779 */   // Label 1747: @123779
     /*  123779 */   GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(123841), // Rule ID 8773 //
     /*  123784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  123787 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  123791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  123795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123799 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  123803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  123810 */     // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  123810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  123813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  123815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  123820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  123825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  123830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  123835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123839 */     GIR_RootConstrainSelectedInstOperands,
     /*  123840 */     // GIR_Coverage, 8773,
     /*  123840 */     GIR_EraseRootFromParent_Done,
     /*  123841 */   // Label 1748: @123841
     /*  123841 */   GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(123900), // Rule ID 8763 //
     /*  123846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  123849 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  123853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  123857 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123861 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  123865 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  123869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  123876 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  123876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  123879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  123881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  123886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123898 */     GIR_RootConstrainSelectedInstOperands,
     /*  123899 */     // GIR_Coverage, 8763,
     /*  123899 */     GIR_EraseRootFromParent_Done,
     /*  123900 */   // Label 1749: @123900
     /*  123900 */   GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(123959), // Rule ID 8764 //
     /*  123905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  123908 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  123912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  123916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123920 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  123924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  123928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  123935 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  123935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  123938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  123940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  123945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  123950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  123953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  123957 */     GIR_RootConstrainSelectedInstOperands,
     /*  123958 */     // GIR_Coverage, 8764,
     /*  123958 */     GIR_EraseRootFromParent_Done,
     /*  123959 */   // Label 1750: @123959
     /*  123959 */   GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(124011), // Rule ID 8769 //
     /*  123964 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  123968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  123972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  123976 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  123980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  123987 */     // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  123987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  123990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  123992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  123997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  124002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124009 */     GIR_RootConstrainSelectedInstOperands,
     /*  124010 */     // GIR_Coverage, 8769,
     /*  124010 */     GIR_EraseRootFromParent_Done,
     /*  124011 */   // Label 1751: @124011
     /*  124011 */   GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(124066), // Rule ID 8770 //
     /*  124016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  124019 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124031 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  124042 */     // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  124042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  124045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  124052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  124057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124060 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124064 */     GIR_RootConstrainSelectedInstOperands,
     /*  124065 */     // GIR_Coverage, 8770,
     /*  124065 */     GIR_EraseRootFromParent_Done,
     /*  124066 */   // Label 1752: @124066
     /*  124066 */   GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(124125), // Rule ID 8765 //
     /*  124071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  124074 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124086 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124090 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  124094 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  124101 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  124101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  124104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  124111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124123 */     GIR_RootConstrainSelectedInstOperands,
     /*  124124 */     // GIR_Coverage, 8765,
     /*  124124 */     GIR_EraseRootFromParent_Done,
     /*  124125 */   // Label 1753: @124125
     /*  124125 */   GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(124189), // Rule ID 8766 //
     /*  124130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  124133 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124145 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124149 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  124153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  124160 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  124160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  124163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  124170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  124183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124187 */     GIR_RootConstrainSelectedInstOperands,
     /*  124188 */     // GIR_Coverage, 8766,
     /*  124188 */     GIR_EraseRootFromParent_Done,
     /*  124189 */   // Label 1754: @124189
     /*  124189 */   GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(124240), // Rule ID 8768 //
     /*  124194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  124197 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124205 */     // MIs[0] sbase
     /*  124205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  124209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  124213 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124217 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  124221 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  124221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  124224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124226 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  124228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124238 */     GIR_RootConstrainSelectedInstOperands,
     /*  124239 */     // GIR_Coverage, 8768,
     /*  124239 */     GIR_EraseRootFromParent_Done,
     /*  124240 */   // Label 1755: @124240
     /*  124240 */   GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(124295), // Rule ID 8771 //
     /*  124245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  124248 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124260 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  124271 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  124271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  124274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  124281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124293 */     GIR_RootConstrainSelectedInstOperands,
     /*  124294 */     // GIR_Coverage, 8771,
     /*  124294 */     GIR_EraseRootFromParent_Done,
     /*  124295 */   // Label 1756: @124295
     /*  124295 */   GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(124355), // Rule ID 8772 //
     /*  124300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  124303 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124315 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  124326 */     // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  124326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  124329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  124336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  124349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124353 */     GIR_RootConstrainSelectedInstOperands,
     /*  124354 */     // GIR_Coverage, 8772,
     /*  124354 */     GIR_EraseRootFromParent_Done,
     /*  124355 */   // Label 1757: @124355
     /*  124355 */   GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(124399), // Rule ID 8774 //
     /*  124360 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  124364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  124368 */     // MIs[0] sbase
     /*  124368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  124372 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  124376 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  124380 */     // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  124380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  124383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  124385 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  124387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124397 */     GIR_RootConstrainSelectedInstOperands,
     /*  124398 */     // GIR_Coverage, 8774,
     /*  124398 */     GIR_EraseRootFromParent_Done,
     /*  124399 */   // Label 1758: @124399
     /*  124399 */   GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(124459), // Rule ID 25316 //
     /*  124404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  124407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124427 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  124430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124457 */     GIR_RootConstrainSelectedInstOperands,
     /*  124458 */     // GIR_Coverage, 25316,
     /*  124458 */     GIR_EraseRootFromParent_Done,
     /*  124459 */   // Label 1759: @124459
     /*  124459 */   GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(124519), // Rule ID 25317 //
     /*  124464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  124467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124476 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124480 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124487 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  124490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124517 */     GIR_RootConstrainSelectedInstOperands,
     /*  124518 */     // GIR_Coverage, 25317,
     /*  124518 */     GIR_EraseRootFromParent_Done,
     /*  124519 */   // Label 1760: @124519
     /*  124519 */   GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(124579), // Rule ID 25318 //
     /*  124524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  124527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124547 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  124550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124573 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124577 */     GIR_RootConstrainSelectedInstOperands,
     /*  124578 */     // GIR_Coverage, 25318,
     /*  124578 */     GIR_EraseRootFromParent_Done,
     /*  124579 */   // Label 1761: @124579
     /*  124579 */   GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(124639), // Rule ID 25319 //
     /*  124584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  124587 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124607 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  124610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124637 */     GIR_RootConstrainSelectedInstOperands,
     /*  124638 */     // GIR_Coverage, 25319,
     /*  124638 */     GIR_EraseRootFromParent_Done,
     /*  124639 */   // Label 1762: @124639
     /*  124639 */   GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(124699), // Rule ID 25320 //
     /*  124644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  124647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124667 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  124670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124697 */     GIR_RootConstrainSelectedInstOperands,
     /*  124698 */     // GIR_Coverage, 25320,
     /*  124698 */     GIR_EraseRootFromParent_Done,
     /*  124699 */   // Label 1763: @124699
     /*  124699 */   GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(124759), // Rule ID 25326 //
     /*  124704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  124707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124727 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  124730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124757 */     GIR_RootConstrainSelectedInstOperands,
     /*  124758 */     // GIR_Coverage, 25326,
     /*  124758 */     GIR_EraseRootFromParent_Done,
     /*  124759 */   // Label 1764: @124759
     /*  124759 */   GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(124819), // Rule ID 25327 //
     /*  124764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  124767 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124787 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  124790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124817 */     GIR_RootConstrainSelectedInstOperands,
     /*  124818 */     // GIR_Coverage, 25327,
     /*  124818 */     GIR_EraseRootFromParent_Done,
     /*  124819 */   // Label 1765: @124819
     /*  124819 */   GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(124879), // Rule ID 25328 //
     /*  124824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  124827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124847 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  124850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124877 */     GIR_RootConstrainSelectedInstOperands,
     /*  124878 */     // GIR_Coverage, 25328,
     /*  124878 */     GIR_EraseRootFromParent_Done,
     /*  124879 */   // Label 1766: @124879
     /*  124879 */   GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(124939), // Rule ID 25329 //
     /*  124884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  124887 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124907 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  124910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124937 */     GIR_RootConstrainSelectedInstOperands,
     /*  124938 */     // GIR_Coverage, 25329,
     /*  124938 */     GIR_EraseRootFromParent_Done,
     /*  124939 */   // Label 1767: @124939
     /*  124939 */   GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(124999), // Rule ID 25330 //
     /*  124944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  124947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  124952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  124956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  124960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  124967 */     // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  124967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  124970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  124972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  124977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  124982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  124987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  124993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  124997 */     GIR_RootConstrainSelectedInstOperands,
     /*  124998 */     // GIR_Coverage, 25330,
     /*  124998 */     GIR_EraseRootFromParent_Done,
     /*  124999 */   // Label 1768: @124999
     /*  124999 */   GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(125058), // Rule ID 14272 //
     /*  125004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  125007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  125027 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  125027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  125030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  125042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  125047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  125052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125056 */     GIR_RootConstrainSelectedInstOperands,
     /*  125057 */     // GIR_Coverage, 14272,
     /*  125057 */     GIR_EraseRootFromParent_Done,
     /*  125058 */   // Label 1769: @125058
     /*  125058 */   GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(125117), // Rule ID 14273 //
     /*  125063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  125066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  125086 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  125086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  125089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  125101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  125106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  125111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125115 */     GIR_RootConstrainSelectedInstOperands,
     /*  125116 */     // GIR_Coverage, 14273,
     /*  125116 */     GIR_EraseRootFromParent_Done,
     /*  125117 */   // Label 1770: @125117
     /*  125117 */   GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(125176), // Rule ID 14274 //
     /*  125122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  125125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  125145 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  125145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  125148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  125160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  125165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  125170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125174 */     GIR_RootConstrainSelectedInstOperands,
     /*  125175 */     // GIR_Coverage, 14274,
     /*  125175 */     GIR_EraseRootFromParent_Done,
     /*  125176 */   // Label 1771: @125176
     /*  125176 */   GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(125235), // Rule ID 14275 //
     /*  125181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  125184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  125204 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  125204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  125207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  125219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  125224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  125229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125233 */     GIR_RootConstrainSelectedInstOperands,
     /*  125234 */     // GIR_Coverage, 14275,
     /*  125234 */     GIR_EraseRootFromParent_Done,
     /*  125235 */   // Label 1772: @125235
     /*  125235 */   GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(125294), // Rule ID 14276 //
     /*  125240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  125243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  125263 */     // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  125263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  125266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  125278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  125283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  125288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125292 */     GIR_RootConstrainSelectedInstOperands,
     /*  125293 */     // GIR_Coverage, 14276,
     /*  125293 */     GIR_EraseRootFromParent_Done,
     /*  125294 */   // Label 1773: @125294
     /*  125294 */   GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(125346), // Rule ID 14267 //
     /*  125299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  125302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  125322 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  125322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  125325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  125332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125344 */     GIR_RootConstrainSelectedInstOperands,
     /*  125345 */     // GIR_Coverage, 14267,
     /*  125345 */     GIR_EraseRootFromParent_Done,
     /*  125346 */   // Label 1774: @125346
     /*  125346 */   GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(125398), // Rule ID 14268 //
     /*  125351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  125354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  125374 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  125374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  125377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  125384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125396 */     GIR_RootConstrainSelectedInstOperands,
     /*  125397 */     // GIR_Coverage, 14268,
     /*  125397 */     GIR_EraseRootFromParent_Done,
     /*  125398 */   // Label 1775: @125398
     /*  125398 */   GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(125450), // Rule ID 14269 //
     /*  125403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  125406 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  125426 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  125426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  125429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  125436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125448 */     GIR_RootConstrainSelectedInstOperands,
     /*  125449 */     // GIR_Coverage, 14269,
     /*  125449 */     GIR_EraseRootFromParent_Done,
     /*  125450 */   // Label 1776: @125450
     /*  125450 */   GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(125502), // Rule ID 14270 //
     /*  125455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  125458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  125478 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  125478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  125481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  125488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125500 */     GIR_RootConstrainSelectedInstOperands,
     /*  125501 */     // GIR_Coverage, 14270,
     /*  125501 */     GIR_EraseRootFromParent_Done,
     /*  125502 */   // Label 1777: @125502
     /*  125502 */   GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(125554), // Rule ID 14271 //
     /*  125507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  125510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  125530 */     // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  125530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  125533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  125540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125552 */     GIR_RootConstrainSelectedInstOperands,
     /*  125553 */     // GIR_Coverage, 14271,
     /*  125553 */     GIR_EraseRootFromParent_Done,
     /*  125554 */   // Label 1778: @125554
     /*  125554 */   GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(125606), // Rule ID 14262 //
     /*  125559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  125562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  125582 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  125582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  125585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125604 */     GIR_RootConstrainSelectedInstOperands,
     /*  125605 */     // GIR_Coverage, 14262,
     /*  125605 */     GIR_EraseRootFromParent_Done,
     /*  125606 */   // Label 1779: @125606
     /*  125606 */   GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(125658), // Rule ID 14263 //
     /*  125611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  125614 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125623 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125627 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  125634 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  125634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  125637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125656 */     GIR_RootConstrainSelectedInstOperands,
     /*  125657 */     // GIR_Coverage, 14263,
     /*  125657 */     GIR_EraseRootFromParent_Done,
     /*  125658 */   // Label 1780: @125658
     /*  125658 */   GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(125710), // Rule ID 14264 //
     /*  125663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  125666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  125686 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  125686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  125689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125708 */     GIR_RootConstrainSelectedInstOperands,
     /*  125709 */     // GIR_Coverage, 14264,
     /*  125709 */     GIR_EraseRootFromParent_Done,
     /*  125710 */   // Label 1781: @125710
     /*  125710 */   GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(125762), // Rule ID 14265 //
     /*  125715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  125718 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  125738 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  125738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  125741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125760 */     GIR_RootConstrainSelectedInstOperands,
     /*  125761 */     // GIR_Coverage, 14265,
     /*  125761 */     GIR_EraseRootFromParent_Done,
     /*  125762 */   // Label 1782: @125762
     /*  125762 */   GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(125814), // Rule ID 14266 //
     /*  125767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  125770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  125775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125783 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  125790 */     // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  125790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  125793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  125795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  125800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  125805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125808 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125812 */     GIR_RootConstrainSelectedInstOperands,
     /*  125813 */     // GIR_Coverage, 14266,
     /*  125813 */     GIR_EraseRootFromParent_Done,
     /*  125814 */   // Label 1783: @125814
     /*  125814 */   GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(125881), // Rule ID 15508 //
     /*  125819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  125822 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  125829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125833 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125837 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  125844 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  125844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  125847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  125849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  125854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  125859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  125864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  125869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125879 */     GIR_RootConstrainSelectedInstOperands,
     /*  125880 */     // GIR_Coverage, 15508,
     /*  125880 */     GIR_EraseRootFromParent_Done,
     /*  125881 */   // Label 1784: @125881
     /*  125881 */   GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(125948), // Rule ID 15509 //
     /*  125886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  125889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  125896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  125911 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  125911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  125914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  125916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  125921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  125926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  125931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  125936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  125942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  125946 */     GIR_RootConstrainSelectedInstOperands,
     /*  125947 */     // GIR_Coverage, 15509,
     /*  125947 */     GIR_EraseRootFromParent_Done,
     /*  125948 */   // Label 1785: @125948
     /*  125948 */   GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(126015), // Rule ID 15510 //
     /*  125953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  125956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  125963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  125967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  125971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  125978 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  125978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  125981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  125983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  125988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  125993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  125998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126013 */     GIR_RootConstrainSelectedInstOperands,
     /*  126014 */     // GIR_Coverage, 15510,
     /*  126014 */     GIR_EraseRootFromParent_Done,
     /*  126015 */   // Label 1786: @126015
     /*  126015 */   GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(126082), // Rule ID 15511 //
     /*  126020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  126023 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126034 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126038 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126045 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  126048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126080 */     GIR_RootConstrainSelectedInstOperands,
     /*  126081 */     // GIR_Coverage, 15511,
     /*  126081 */     GIR_EraseRootFromParent_Done,
     /*  126082 */   // Label 1787: @126082
     /*  126082 */   GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(126149), // Rule ID 15512 //
     /*  126087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  126090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126112 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  126115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126147 */     GIR_RootConstrainSelectedInstOperands,
     /*  126148 */     // GIR_Coverage, 15512,
     /*  126148 */     GIR_EraseRootFromParent_Done,
     /*  126149 */   // Label 1788: @126149
     /*  126149 */   GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(126216), // Rule ID 15518 //
     /*  126154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  126157 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126179 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  126182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126214 */     GIR_RootConstrainSelectedInstOperands,
     /*  126215 */     // GIR_Coverage, 15518,
     /*  126215 */     GIR_EraseRootFromParent_Done,
     /*  126216 */   // Label 1789: @126216
     /*  126216 */   GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(126283), // Rule ID 15519 //
     /*  126221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  126224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126235 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126239 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126246 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  126249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126281 */     GIR_RootConstrainSelectedInstOperands,
     /*  126282 */     // GIR_Coverage, 15519,
     /*  126282 */     GIR_EraseRootFromParent_Done,
     /*  126283 */   // Label 1790: @126283
     /*  126283 */   GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(126350), // Rule ID 15520 //
     /*  126288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  126291 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126313 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  126316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126348 */     GIR_RootConstrainSelectedInstOperands,
     /*  126349 */     // GIR_Coverage, 15520,
     /*  126349 */     GIR_EraseRootFromParent_Done,
     /*  126350 */   // Label 1791: @126350
     /*  126350 */   GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(126417), // Rule ID 15521 //
     /*  126355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  126358 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126369 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126380 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  126383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126415 */     GIR_RootConstrainSelectedInstOperands,
     /*  126416 */     // GIR_Coverage, 15521,
     /*  126416 */     GIR_EraseRootFromParent_Done,
     /*  126417 */   // Label 1792: @126417
     /*  126417 */   GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(126484), // Rule ID 15522 //
     /*  126422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  126425 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  126432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  126447 */     // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  126447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  126450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126482 */     GIR_RootConstrainSelectedInstOperands,
     /*  126483 */     // GIR_Coverage, 15522,
     /*  126483 */     GIR_EraseRootFromParent_Done,
     /*  126484 */   // Label 1793: @126484
     /*  126484 */   GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(126549), // Rule ID 25311 //
     /*  126489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  126492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126512 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  126515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126540 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126547 */     GIR_RootConstrainSelectedInstOperands,
     /*  126548 */     // GIR_Coverage, 25311,
     /*  126548 */     GIR_EraseRootFromParent_Done,
     /*  126549 */   // Label 1794: @126549
     /*  126549 */   GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(126614), // Rule ID 25312 //
     /*  126554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  126557 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126577 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  126580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126605 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126608 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126612 */     GIR_RootConstrainSelectedInstOperands,
     /*  126613 */     // GIR_Coverage, 25312,
     /*  126613 */     GIR_EraseRootFromParent_Done,
     /*  126614 */   // Label 1795: @126614
     /*  126614 */   GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(126679), // Rule ID 25313 //
     /*  126619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  126622 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126642 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  126645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126677 */     GIR_RootConstrainSelectedInstOperands,
     /*  126678 */     // GIR_Coverage, 25313,
     /*  126678 */     GIR_EraseRootFromParent_Done,
     /*  126679 */   // Label 1796: @126679
     /*  126679 */   GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(126744), // Rule ID 25314 //
     /*  126684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  126687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126707 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  126710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126742 */     GIR_RootConstrainSelectedInstOperands,
     /*  126743 */     // GIR_Coverage, 25314,
     /*  126743 */     GIR_EraseRootFromParent_Done,
     /*  126744 */   // Label 1797: @126744
     /*  126744 */   GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(126809), // Rule ID 25315 //
     /*  126749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  126752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126772 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  126775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126807 */     GIR_RootConstrainSelectedInstOperands,
     /*  126808 */     // GIR_Coverage, 25315,
     /*  126808 */     GIR_EraseRootFromParent_Done,
     /*  126809 */   // Label 1798: @126809
     /*  126809 */   GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(126874), // Rule ID 25321 //
     /*  126814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  126817 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126837 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  126840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126872 */     GIR_RootConstrainSelectedInstOperands,
     /*  126873 */     // GIR_Coverage, 25321,
     /*  126873 */     GIR_EraseRootFromParent_Done,
     /*  126874 */   // Label 1799: @126874
     /*  126874 */   GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(126939), // Rule ID 25322 //
     /*  126879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  126882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126902 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  126905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  126937 */     GIR_RootConstrainSelectedInstOperands,
     /*  126938 */     // GIR_Coverage, 25322,
     /*  126938 */     GIR_EraseRootFromParent_Done,
     /*  126939 */   // Label 1800: @126939
     /*  126939 */   GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(127004), // Rule ID 25323 //
     /*  126944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  126947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  126952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  126956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  126960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  126967 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  126967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  126970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  126972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  126977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  126982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  126987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  126992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  126998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127002 */     GIR_RootConstrainSelectedInstOperands,
     /*  127003 */     // GIR_Coverage, 25323,
     /*  127003 */     GIR_EraseRootFromParent_Done,
     /*  127004 */   // Label 1801: @127004
     /*  127004 */   GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(127069), // Rule ID 25324 //
     /*  127009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  127012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  127017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127021 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127025 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  127032 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  127032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  127035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  127042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  127052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  127057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127067 */     GIR_RootConstrainSelectedInstOperands,
     /*  127068 */     // GIR_Coverage, 25324,
     /*  127068 */     GIR_EraseRootFromParent_Done,
     /*  127069 */   // Label 1802: @127069
     /*  127069 */   GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(127134), // Rule ID 25325 //
     /*  127074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  127077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  127082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  127097 */     // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  127097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  127100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  127107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  127117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  127122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127128 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127132 */     GIR_RootConstrainSelectedInstOperands,
     /*  127133 */     // GIR_Coverage, 25325,
     /*  127133 */     GIR_EraseRootFromParent_Done,
     /*  127134 */   // Label 1803: @127134
     /*  127134 */   GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(127196), // Rule ID 15503 //
     /*  127139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  127142 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127164 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  127167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127194 */     GIR_RootConstrainSelectedInstOperands,
     /*  127195 */     // GIR_Coverage, 15503,
     /*  127195 */     GIR_EraseRootFromParent_Done,
     /*  127196 */   // Label 1804: @127196
     /*  127196 */   GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(127258), // Rule ID 15504 //
     /*  127201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  127204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127215 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127226 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  127229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127249 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127252 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127256 */     GIR_RootConstrainSelectedInstOperands,
     /*  127257 */     // GIR_Coverage, 15504,
     /*  127257 */     GIR_EraseRootFromParent_Done,
     /*  127258 */   // Label 1805: @127258
     /*  127258 */   GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(127320), // Rule ID 15505 //
     /*  127263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  127266 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127288 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  127291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127318 */     GIR_RootConstrainSelectedInstOperands,
     /*  127319 */     // GIR_Coverage, 15505,
     /*  127319 */     GIR_EraseRootFromParent_Done,
     /*  127320 */   // Label 1806: @127320
     /*  127320 */   GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(127382), // Rule ID 15506 //
     /*  127325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  127328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127339 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127350 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  127353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127380 */     GIR_RootConstrainSelectedInstOperands,
     /*  127381 */     // GIR_Coverage, 15506,
     /*  127381 */     GIR_EraseRootFromParent_Done,
     /*  127382 */   // Label 1807: @127382
     /*  127382 */   GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(127444), // Rule ID 15507 //
     /*  127387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  127390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127412 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  127415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127442 */     GIR_RootConstrainSelectedInstOperands,
     /*  127443 */     // GIR_Coverage, 15507,
     /*  127443 */     GIR_EraseRootFromParent_Done,
     /*  127444 */   // Label 1808: @127444
     /*  127444 */   GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(127506), // Rule ID 15513 //
     /*  127449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  127452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127474 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  127477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127504 */     GIR_RootConstrainSelectedInstOperands,
     /*  127505 */     // GIR_Coverage, 15513,
     /*  127505 */     GIR_EraseRootFromParent_Done,
     /*  127506 */   // Label 1809: @127506
     /*  127506 */   GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(127568), // Rule ID 15514 //
     /*  127511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  127514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127525 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127529 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127536 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  127539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127566 */     GIR_RootConstrainSelectedInstOperands,
     /*  127567 */     // GIR_Coverage, 15514,
     /*  127567 */     GIR_EraseRootFromParent_Done,
     /*  127568 */   // Label 1810: @127568
     /*  127568 */   GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(127630), // Rule ID 15515 //
     /*  127573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  127576 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127598 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  127601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127624 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127628 */     GIR_RootConstrainSelectedInstOperands,
     /*  127629 */     // GIR_Coverage, 15515,
     /*  127629 */     GIR_EraseRootFromParent_Done,
     /*  127630 */   // Label 1811: @127630
     /*  127630 */   GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(127692), // Rule ID 15516 //
     /*  127635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  127638 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127649 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127653 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127660 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  127663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127690 */     GIR_RootConstrainSelectedInstOperands,
     /*  127691 */     // GIR_Coverage, 15516,
     /*  127691 */     GIR_EraseRootFromParent_Done,
     /*  127692 */   // Label 1812: @127692
     /*  127692 */   GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(127754), // Rule ID 15517 //
     /*  127697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  127700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  127707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  127722 */     // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  127722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  127725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  127727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  127732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  127737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  127742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127752 */     GIR_RootConstrainSelectedInstOperands,
     /*  127753 */     // GIR_Coverage, 15517,
     /*  127753 */     GIR_EraseRootFromParent_Done,
     /*  127754 */   // Label 1813: @127754
     /*  127754 */   GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(127810), // Rule ID 28967 //
     /*  127759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  127762 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  127766 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  127771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  127786 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  127786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  127789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  127791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  127796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  127801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127808 */     GIR_RootConstrainSelectedInstOperands,
     /*  127809 */     // GIR_Coverage, 28967,
     /*  127809 */     GIR_EraseRootFromParent_Done,
     /*  127810 */   // Label 1814: @127810
     /*  127810 */   GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(127866), // Rule ID 28968 //
     /*  127815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  127818 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  127822 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  127827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127831 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127835 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  127842 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  127842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  127845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  127847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  127852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  127857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127864 */     GIR_RootConstrainSelectedInstOperands,
     /*  127865 */     // GIR_Coverage, 28968,
     /*  127865 */     GIR_EraseRootFromParent_Done,
     /*  127866 */   // Label 1815: @127866
     /*  127866 */   GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(127922), // Rule ID 28969 //
     /*  127871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  127874 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  127878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  127883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  127898 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  127898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  127901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  127903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  127908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  127913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127920 */     GIR_RootConstrainSelectedInstOperands,
     /*  127921 */     // GIR_Coverage, 28969,
     /*  127921 */     GIR_EraseRootFromParent_Done,
     /*  127922 */   // Label 1816: @127922
     /*  127922 */   GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(127978), // Rule ID 28970 //
     /*  127927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  127930 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  127934 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  127939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  127947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  127954 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  127954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  127957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  127959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  127964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  127969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  127972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  127976 */     GIR_RootConstrainSelectedInstOperands,
     /*  127977 */     // GIR_Coverage, 28970,
     /*  127977 */     GIR_EraseRootFromParent_Done,
     /*  127978 */   // Label 1817: @127978
     /*  127978 */   GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(128034), // Rule ID 28971 //
     /*  127983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  127986 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  127990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  127995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  127999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  128010 */     // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  128010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  128013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  128020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128032 */     GIR_RootConstrainSelectedInstOperands,
     /*  128033 */     // GIR_Coverage, 28971,
     /*  128033 */     GIR_EraseRootFromParent_Done,
     /*  128034 */   // Label 1818: @128034
     /*  128034 */   GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(128086), // Rule ID 28972 //
     /*  128039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  128042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  128047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  128062 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  128062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  128065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  128072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128084 */     GIR_RootConstrainSelectedInstOperands,
     /*  128085 */     // GIR_Coverage, 28972,
     /*  128085 */     GIR_EraseRootFromParent_Done,
     /*  128086 */   // Label 1819: @128086
     /*  128086 */   GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(128138), // Rule ID 28973 //
     /*  128091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  128094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  128099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  128114 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  128114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  128117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  128124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128136 */     GIR_RootConstrainSelectedInstOperands,
     /*  128137 */     // GIR_Coverage, 28973,
     /*  128137 */     GIR_EraseRootFromParent_Done,
     /*  128138 */   // Label 1820: @128138
     /*  128138 */   GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(128190), // Rule ID 28974 //
     /*  128143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  128146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  128151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  128166 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  128166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  128169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  128176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128188 */     GIR_RootConstrainSelectedInstOperands,
     /*  128189 */     // GIR_Coverage, 28974,
     /*  128189 */     GIR_EraseRootFromParent_Done,
     /*  128190 */   // Label 1821: @128190
     /*  128190 */   GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(128242), // Rule ID 28975 //
     /*  128195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  128198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  128203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  128218 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  128218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  128221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  128228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128240 */     GIR_RootConstrainSelectedInstOperands,
     /*  128241 */     // GIR_Coverage, 28975,
     /*  128241 */     GIR_EraseRootFromParent_Done,
     /*  128242 */   // Label 1822: @128242
     /*  128242 */   GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(128294), // Rule ID 28976 //
     /*  128247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  128250 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  128255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  128270 */     // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  128270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  128273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  128280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128292 */     GIR_RootConstrainSelectedInstOperands,
     /*  128293 */     // GIR_Coverage, 28976,
     /*  128293 */     GIR_EraseRootFromParent_Done,
     /*  128294 */   // Label 1823: @128294
     /*  128294 */   GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(128355), // Rule ID 12243 //
     /*  128299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  128302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128313 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128317 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128324 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  128327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128353 */     GIR_RootConstrainSelectedInstOperands,
     /*  128354 */     // GIR_Coverage, 12243,
     /*  128354 */     GIR_EraseRootFromParent_Done,
     /*  128355 */   // Label 1824: @128355
     /*  128355 */   GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(128416), // Rule ID 12244 //
     /*  128360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  128363 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128385 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  128388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128414 */     GIR_RootConstrainSelectedInstOperands,
     /*  128415 */     // GIR_Coverage, 12244,
     /*  128415 */     GIR_EraseRootFromParent_Done,
     /*  128416 */   // Label 1825: @128416
     /*  128416 */   GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(128477), // Rule ID 12245 //
     /*  128421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  128424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128446 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  128449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128471 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128475 */     GIR_RootConstrainSelectedInstOperands,
     /*  128476 */     // GIR_Coverage, 12245,
     /*  128476 */     GIR_EraseRootFromParent_Done,
     /*  128477 */   // Label 1826: @128477
     /*  128477 */   GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(128538), // Rule ID 12246 //
     /*  128482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  128485 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128492 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128507 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  128510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128536 */     GIR_RootConstrainSelectedInstOperands,
     /*  128537 */     // GIR_Coverage, 12246,
     /*  128537 */     GIR_EraseRootFromParent_Done,
     /*  128538 */   // Label 1827: @128538
     /*  128538 */   GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(128599), // Rule ID 12247 //
     /*  128543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  128546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128568 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  128571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128597 */     GIR_RootConstrainSelectedInstOperands,
     /*  128598 */     // GIR_Coverage, 12247,
     /*  128598 */     GIR_EraseRootFromParent_Done,
     /*  128599 */   // Label 1828: @128599
     /*  128599 */   GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(128653), // Rule ID 12238 //
     /*  128604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  128607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  128629 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  128629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  128632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  128639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128651 */     GIR_RootConstrainSelectedInstOperands,
     /*  128652 */     // GIR_Coverage, 12238,
     /*  128652 */     GIR_EraseRootFromParent_Done,
     /*  128653 */   // Label 1829: @128653
     /*  128653 */   GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(128707), // Rule ID 12239 //
     /*  128658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  128661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  128683 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  128683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  128686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  128693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128705 */     GIR_RootConstrainSelectedInstOperands,
     /*  128706 */     // GIR_Coverage, 12239,
     /*  128706 */     GIR_EraseRootFromParent_Done,
     /*  128707 */   // Label 1830: @128707
     /*  128707 */   GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(128761), // Rule ID 12240 //
     /*  128712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  128715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128726 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128730 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  128737 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  128737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  128740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  128747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128759 */     GIR_RootConstrainSelectedInstOperands,
     /*  128760 */     // GIR_Coverage, 12240,
     /*  128760 */     GIR_EraseRootFromParent_Done,
     /*  128761 */   // Label 1831: @128761
     /*  128761 */   GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(128815), // Rule ID 12241 //
     /*  128766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  128769 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128784 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  128791 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  128791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  128794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  128801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128813 */     GIR_RootConstrainSelectedInstOperands,
     /*  128814 */     // GIR_Coverage, 12241,
     /*  128814 */     GIR_EraseRootFromParent_Done,
     /*  128815 */   // Label 1832: @128815
     /*  128815 */   GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(128869), // Rule ID 12242 //
     /*  128820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  128823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  128845 */     // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  128845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  128848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  128855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  128860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  128863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128867 */     GIR_RootConstrainSelectedInstOperands,
     /*  128868 */     // GIR_Coverage, 12242,
     /*  128868 */     GIR_EraseRootFromParent_Done,
     /*  128869 */   // Label 1833: @128869
     /*  128869 */   GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(128931), // Rule ID 10101 //
     /*  128874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  128877 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128900 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  128903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128929 */     GIR_RootConstrainSelectedInstOperands,
     /*  128930 */     // GIR_Coverage, 10101,
     /*  128930 */     GIR_EraseRootFromParent_Done,
     /*  128931 */   // Label 1834: @128931
     /*  128931 */   GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(128993), // Rule ID 10102 //
     /*  128936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  128939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  128947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  128951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  128955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  128962 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  128962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  128965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  128967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  128972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  128977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  128982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  128987 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  128991 */     GIR_RootConstrainSelectedInstOperands,
     /*  128992 */     // GIR_Coverage, 10102,
     /*  128992 */     GIR_EraseRootFromParent_Done,
     /*  128993 */   // Label 1835: @128993
     /*  128993 */   GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(129055), // Rule ID 10103 //
     /*  128998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  129001 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  129024 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  129024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  129027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  129034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  129039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  129044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  129049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129053 */     GIR_RootConstrainSelectedInstOperands,
     /*  129054 */     // GIR_Coverage, 10103,
     /*  129054 */     GIR_EraseRootFromParent_Done,
     /*  129055 */   // Label 1836: @129055
     /*  129055 */   GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(129117), // Rule ID 10104 //
     /*  129060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  129063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  129086 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  129086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  129089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  129096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  129101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  129106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  129111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129115 */     GIR_RootConstrainSelectedInstOperands,
     /*  129116 */     // GIR_Coverage, 10104,
     /*  129116 */     GIR_EraseRootFromParent_Done,
     /*  129117 */   // Label 1837: @129117
     /*  129117 */   GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(129179), // Rule ID 10105 //
     /*  129122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  129125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  129148 */     // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  129148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  129151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  129158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  129163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  129168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  129173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129177 */     GIR_RootConstrainSelectedInstOperands,
     /*  129178 */     // GIR_Coverage, 10105,
     /*  129178 */     GIR_EraseRootFromParent_Done,
     /*  129179 */   // Label 1838: @129179
     /*  129179 */   GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(129234), // Rule ID 10096 //
     /*  129184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  129187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  129210 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  129210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  129213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  129220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129232 */     GIR_RootConstrainSelectedInstOperands,
     /*  129233 */     // GIR_Coverage, 10096,
     /*  129233 */     GIR_EraseRootFromParent_Done,
     /*  129234 */   // Label 1839: @129234
     /*  129234 */   GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(129289), // Rule ID 10097 //
     /*  129239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  129242 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129254 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  129265 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  129265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  129268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  129275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129287 */     GIR_RootConstrainSelectedInstOperands,
     /*  129288 */     // GIR_Coverage, 10097,
     /*  129288 */     GIR_EraseRootFromParent_Done,
     /*  129289 */   // Label 1840: @129289
     /*  129289 */   GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(129344), // Rule ID 10098 //
     /*  129294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  129297 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129309 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  129320 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  129320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  129323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  129330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129342 */     GIR_RootConstrainSelectedInstOperands,
     /*  129343 */     // GIR_Coverage, 10098,
     /*  129343 */     GIR_EraseRootFromParent_Done,
     /*  129344 */   // Label 1841: @129344
     /*  129344 */   GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(129399), // Rule ID 10099 //
     /*  129349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  129352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  129375 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  129375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  129378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  129385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129397 */     GIR_RootConstrainSelectedInstOperands,
     /*  129398 */     // GIR_Coverage, 10099,
     /*  129398 */     GIR_EraseRootFromParent_Done,
     /*  129399 */   // Label 1842: @129399
     /*  129399 */   GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(129454), // Rule ID 10100 //
     /*  129404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  129407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  129415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  129419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  129430 */     // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  129430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  129433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  129435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  129440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129452 */     GIR_RootConstrainSelectedInstOperands,
     /*  129453 */     // GIR_Coverage, 10100,
     /*  129453 */     GIR_EraseRootFromParent_Done,
     /*  129454 */   // Label 1843: @129454
     /*  129454 */   GIM_Reject,
     /*  129455 */ // Label 1746: @129455
     /*  129455 */ GIM_Reject,
     /*  129456 */ // Label 1125: @129456
     /*  129456 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(130063),
     /*  129461 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  129464 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  129468 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  129472 */   GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(129530), // Rule ID 8847 //
     /*  129477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  129480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129488 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  129492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  129499 */     // (ld:{ *:[i1] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  129499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  129502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  129514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  129519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  129524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129528 */     GIR_RootConstrainSelectedInstOperands,
     /*  129529 */     // GIR_Coverage, 8847,
     /*  129529 */     GIR_EraseRootFromParent_Done,
     /*  129530 */   // Label 1845: @129530
     /*  129530 */   GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(129584), // Rule ID 8853 //
     /*  129535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  129538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  129553 */     // (ld:{ *:[i1] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  129553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  129556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  129568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  129573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  129578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129582 */     GIR_RootConstrainSelectedInstOperands,
     /*  129583 */     // GIR_Coverage, 8853,
     /*  129583 */     GIR_EraseRootFromParent_Done,
     /*  129584 */   // Label 1846: @129584
     /*  129584 */   GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(129635), // Rule ID 8843 //
     /*  129589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  129592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129600 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  129604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  129611 */     // (ld:{ *:[i1] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  129611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  129614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129633 */     GIR_RootConstrainSelectedInstOperands,
     /*  129634 */     // GIR_Coverage, 8843,
     /*  129634 */     GIR_EraseRootFromParent_Done,
     /*  129635 */   // Label 1847: @129635
     /*  129635 */   GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(129686), // Rule ID 8844 //
     /*  129640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  129643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129651 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  129655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  129662 */     // (ld:{ *:[i1] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  129662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  129665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129677 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129680 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129684 */     GIR_RootConstrainSelectedInstOperands,
     /*  129685 */     // GIR_Coverage, 8844,
     /*  129685 */     GIR_EraseRootFromParent_Done,
     /*  129686 */   // Label 1848: @129686
     /*  129686 */   GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(129730), // Rule ID 8849 //
     /*  129691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  129706 */     // (ld:{ *:[i1] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  129706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  129709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129728 */     GIR_RootConstrainSelectedInstOperands,
     /*  129729 */     // GIR_Coverage, 8849,
     /*  129729 */     GIR_EraseRootFromParent_Done,
     /*  129730 */   // Label 1849: @129730
     /*  129730 */   GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(129777), // Rule ID 8850 //
     /*  129735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  129738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  129753 */     // (ld:{ *:[i1] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  129753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  129756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  129768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129775 */     GIR_RootConstrainSelectedInstOperands,
     /*  129776 */     // GIR_Coverage, 8850,
     /*  129776 */     GIR_EraseRootFromParent_Done,
     /*  129777 */   // Label 1850: @129777
     /*  129777 */   GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(129828), // Rule ID 8845 //
     /*  129782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  129785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129793 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  129797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  129804 */     // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  129804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  129807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  129819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129822 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129826 */     GIR_RootConstrainSelectedInstOperands,
     /*  129827 */     // GIR_Coverage, 8845,
     /*  129827 */     GIR_EraseRootFromParent_Done,
     /*  129828 */   // Label 1851: @129828
     /*  129828 */   GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(129884), // Rule ID 8846 //
     /*  129833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  129836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129844 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  129848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  129855 */     // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  129855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  129858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  129870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  129878 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129882 */     GIR_RootConstrainSelectedInstOperands,
     /*  129883 */     // GIR_Coverage, 8846,
     /*  129883 */     GIR_EraseRootFromParent_Done,
     /*  129884 */   // Label 1852: @129884
     /*  129884 */   GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(129927), // Rule ID 8848 //
     /*  129889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  129892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129896 */     // MIs[0] sbase
     /*  129896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  129900 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  129904 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  129908 */     // (ld:{ *:[i1] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i1] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  129908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  129911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129913 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  129915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129925 */     GIR_RootConstrainSelectedInstOperands,
     /*  129926 */     // GIR_Coverage, 8848,
     /*  129926 */     GIR_EraseRootFromParent_Done,
     /*  129927 */   // Label 1853: @129927
     /*  129927 */   GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(129974), // Rule ID 8851 //
     /*  129932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  129935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  129950 */     // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  129950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  129953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  129955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  129960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  129965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  129968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  129972 */     GIR_RootConstrainSelectedInstOperands,
     /*  129973 */     // GIR_Coverage, 8851,
     /*  129973 */     GIR_EraseRootFromParent_Done,
     /*  129974 */   // Label 1854: @129974
     /*  129974 */   GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(130026), // Rule ID 8852 //
     /*  129979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  129982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  129986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  129990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  129997 */     // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  129997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  130000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  130002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  130007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  130020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130024 */     GIR_RootConstrainSelectedInstOperands,
     /*  130025 */     // GIR_Coverage, 8852,
     /*  130025 */     GIR_EraseRootFromParent_Done,
     /*  130026 */   // Label 1855: @130026
     /*  130026 */   GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(130062), // Rule ID 8854 //
     /*  130031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  130035 */     // MIs[0] sbase
     /*  130035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  130039 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  130043 */     // (ld:{ *:[i1] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i1] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  130043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  130046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  130048 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  130050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130060 */     GIR_RootConstrainSelectedInstOperands,
     /*  130061 */     // GIR_Coverage, 8854,
     /*  130061 */     GIR_EraseRootFromParent_Done,
     /*  130062 */   // Label 1856: @130062
     /*  130062 */   GIM_Reject,
     /*  130063 */ // Label 1844: @130063
     /*  130063 */ GIM_Reject,
     /*  130064 */ // Label 1126: @130064
     /*  130064 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(130138), // Rule ID 25056 //
     /*  130069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  130072 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130075 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130079 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130086 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130095 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130099 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130106 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130106 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  130109 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130126 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130132 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130136 */   GIR_RootConstrainSelectedInstOperands,
     /*  130137 */   // GIR_Coverage, 25056,
     /*  130137 */   GIR_EraseRootFromParent_Done,
     /*  130138 */ // Label 1857: @130138
     /*  130138 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(130212), // Rule ID 25057 //
     /*  130143 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  130146 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130149 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130153 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130160 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130180 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130180 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  130183 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130203 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130206 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130210 */   GIR_RootConstrainSelectedInstOperands,
     /*  130211 */   // GIR_Coverage, 25057,
     /*  130211 */   GIR_EraseRootFromParent_Done,
     /*  130212 */ // Label 1858: @130212
     /*  130212 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(130286), // Rule ID 25058 //
     /*  130217 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  130220 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130223 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130227 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130254 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  130257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130274 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130277 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130280 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130284 */   GIR_RootConstrainSelectedInstOperands,
     /*  130285 */   // GIR_Coverage, 25058,
     /*  130285 */   GIR_EraseRootFromParent_Done,
     /*  130286 */ // Label 1859: @130286
     /*  130286 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(130360), // Rule ID 25059 //
     /*  130291 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  130294 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130297 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130301 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130308 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130313 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130317 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130321 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130328 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130328 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  130331 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130348 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130351 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130354 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130358 */   GIR_RootConstrainSelectedInstOperands,
     /*  130359 */   // GIR_Coverage, 25059,
     /*  130359 */   GIR_EraseRootFromParent_Done,
     /*  130360 */ // Label 1860: @130360
     /*  130360 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(130434), // Rule ID 25060 //
     /*  130365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  130368 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130371 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130375 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130382 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130391 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130395 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130402 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  130405 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130425 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130428 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130432 */   GIR_RootConstrainSelectedInstOperands,
     /*  130433 */   // GIR_Coverage, 25060,
     /*  130433 */   GIR_EraseRootFromParent_Done,
     /*  130434 */ // Label 1861: @130434
     /*  130434 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(130508), // Rule ID 25066 //
     /*  130439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  130442 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130445 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130449 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130456 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130476 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  130479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130506 */   GIR_RootConstrainSelectedInstOperands,
     /*  130507 */   // GIR_Coverage, 25066,
     /*  130507 */   GIR_EraseRootFromParent_Done,
     /*  130508 */ // Label 1862: @130508
     /*  130508 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(130582), // Rule ID 25067 //
     /*  130513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  130516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130519 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130523 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130530 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130539 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130543 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130550 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  130553 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130570 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130573 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130576 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130580 */   GIR_RootConstrainSelectedInstOperands,
     /*  130581 */   // GIR_Coverage, 25067,
     /*  130581 */   GIR_EraseRootFromParent_Done,
     /*  130582 */ // Label 1863: @130582
     /*  130582 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(130656), // Rule ID 25068 //
     /*  130587 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  130590 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130593 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130597 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130604 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130624 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  130627 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130644 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130647 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130650 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130654 */   GIR_RootConstrainSelectedInstOperands,
     /*  130655 */   // GIR_Coverage, 25068,
     /*  130655 */   GIR_EraseRootFromParent_Done,
     /*  130656 */ // Label 1864: @130656
     /*  130656 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(130730), // Rule ID 25069 //
     /*  130661 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  130664 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130667 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130671 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130678 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130687 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130691 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130698 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  130701 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130718 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130724 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130728 */   GIR_RootConstrainSelectedInstOperands,
     /*  130729 */   // GIR_Coverage, 25069,
     /*  130729 */   GIR_EraseRootFromParent_Done,
     /*  130730 */ // Label 1865: @130730
     /*  130730 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(130804), // Rule ID 25070 //
     /*  130735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  130738 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130741 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  130745 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  130752 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130772 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  130775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130792 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130795 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130798 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130802 */   GIR_RootConstrainSelectedInstOperands,
     /*  130803 */   // GIR_Coverage, 25070,
     /*  130803 */   GIR_EraseRootFromParent_Done,
     /*  130804 */ // Label 1866: @130804
     /*  130804 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(130867), // Rule ID 25156 //
     /*  130809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  130812 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130815 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130820 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130824 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130828 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130835 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130835 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  130838 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130855 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130858 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130861 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130865 */   GIR_RootConstrainSelectedInstOperands,
     /*  130866 */   // GIR_Coverage, 25156,
     /*  130866 */   GIR_EraseRootFromParent_Done,
     /*  130867 */ // Label 1867: @130867
     /*  130867 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(130930), // Rule ID 25157 //
     /*  130872 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  130875 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130878 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130898 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  130901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130918 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130921 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130924 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130928 */   GIR_RootConstrainSelectedInstOperands,
     /*  130929 */   // GIR_Coverage, 25157,
     /*  130929 */   GIR_EraseRootFromParent_Done,
     /*  130930 */ // Label 1868: @130930
     /*  130930 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(130993), // Rule ID 25158 //
     /*  130935 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  130938 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  130941 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  130946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  130950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  130954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  130961 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  130961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  130964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  130966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  130971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  130976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  130981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  130987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  130991 */   GIR_RootConstrainSelectedInstOperands,
     /*  130992 */   // GIR_Coverage, 25158,
     /*  130992 */   GIR_EraseRootFromParent_Done,
     /*  130993 */ // Label 1869: @130993
     /*  130993 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(131056), // Rule ID 25159 //
     /*  130998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  131001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131024 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  131027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131047 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131050 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131054 */   GIR_RootConstrainSelectedInstOperands,
     /*  131055 */   // GIR_Coverage, 25159,
     /*  131055 */   GIR_EraseRootFromParent_Done,
     /*  131056 */ // Label 1870: @131056
     /*  131056 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(131119), // Rule ID 25160 //
     /*  131061 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  131064 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131067 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131076 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131080 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131087 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  131090 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131107 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131110 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131117 */   GIR_RootConstrainSelectedInstOperands,
     /*  131118 */   // GIR_Coverage, 25160,
     /*  131118 */   GIR_EraseRootFromParent_Done,
     /*  131119 */ // Label 1871: @131119
     /*  131119 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(131182), // Rule ID 25166 //
     /*  131124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  131127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131130 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131139 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131143 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131150 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  131153 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131173 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131176 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131180 */   GIR_RootConstrainSelectedInstOperands,
     /*  131181 */   // GIR_Coverage, 25166,
     /*  131181 */   GIR_EraseRootFromParent_Done,
     /*  131182 */ // Label 1872: @131182
     /*  131182 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(131245), // Rule ID 25167 //
     /*  131187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  131190 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131193 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131213 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  131216 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131236 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131239 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131243 */   GIR_RootConstrainSelectedInstOperands,
     /*  131244 */   // GIR_Coverage, 25167,
     /*  131244 */   GIR_EraseRootFromParent_Done,
     /*  131245 */ // Label 1873: @131245
     /*  131245 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(131308), // Rule ID 25168 //
     /*  131250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  131253 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131256 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131261 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131265 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131269 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131276 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131276 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  131279 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131306 */   GIR_RootConstrainSelectedInstOperands,
     /*  131307 */   // GIR_Coverage, 25168,
     /*  131307 */   GIR_EraseRootFromParent_Done,
     /*  131308 */ // Label 1874: @131308
     /*  131308 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(131371), // Rule ID 25169 //
     /*  131313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  131316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131328 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131332 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131339 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131339 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  131342 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131359 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131362 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131365 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131369 */   GIR_RootConstrainSelectedInstOperands,
     /*  131370 */   // GIR_Coverage, 25169,
     /*  131370 */   GIR_EraseRootFromParent_Done,
     /*  131371 */ // Label 1875: @131371
     /*  131371 */ GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(131434), // Rule ID 25170 //
     /*  131376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  131379 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131382 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131391 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131395 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  131402 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  131402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  131405 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  131407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  131412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  131417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131425 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  131428 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131432 */   GIR_RootConstrainSelectedInstOperands,
     /*  131433 */   // GIR_Coverage, 25170,
     /*  131433 */   GIR_EraseRootFromParent_Done,
     /*  131434 */ // Label 1876: @131434
     /*  131434 */ GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(131507), // Rule ID 9458 //
     /*  131439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatScratchSVSMode_UseRealTrue16Insts),
     /*  131442 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131445 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  131449 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  131456 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  131476 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_D16_SVS_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  131476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_t16),
     /*  131479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  131481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  131486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  131491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  131501 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131505 */   GIR_RootConstrainSelectedInstOperands,
     /*  131506 */   // GIR_Coverage, 9458,
     /*  131506 */   GIR_EraseRootFromParent_Done,
     /*  131507 */ // Label 1877: @131507
     /*  131507 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(131610), // Rule ID 9469 //
     /*  131512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode0),
     /*  131515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131518 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  131522 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  131529 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131538 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131542 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  131549 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  131549 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  131552 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  131556 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  131561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  131566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  131571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  131581 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131585 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  131587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  131590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  131592 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  131599 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131604 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131609 */   // GIR_Coverage, 9469,
     /*  131609 */   GIR_EraseRootFromParent_Done,
     /*  131610 */ // Label 1878: @131610
     /*  131610 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(131713), // Rule ID 9470 //
     /*  131615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode1),
     /*  131618 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131621 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  131625 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  131632 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131645 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  131652 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  131652 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  131655 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  131659 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  131664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  131669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  131674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  131684 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131688 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  131690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  131693 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  131695 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  131702 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131707 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131712 */   // GIR_Coverage, 9470,
     /*  131712 */   GIR_EraseRootFromParent_Done,
     /*  131713 */ // Label 1879: @131713
     /*  131713 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(131816), // Rule ID 9471 //
     /*  131718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode2),
     /*  131721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131724 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  131728 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  131735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  131755 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  131755 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  131758 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  131762 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  131767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  131772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  131777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  131787 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131791 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  131793 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  131796 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  131798 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  131805 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131810 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131815 */   // GIR_Coverage, 9471,
     /*  131815 */   GIR_EraseRootFromParent_Done,
     /*  131816 */ // Label 1880: @131816
     /*  131816 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(131919), // Rule ID 9472 //
     /*  131821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode3),
     /*  131824 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131827 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  131831 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  131838 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131847 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131851 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  131858 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  131858 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  131861 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  131865 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  131870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  131875 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  131880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  131890 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131894 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  131896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  131899 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  131901 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  131908 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131913 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  131918 */   // GIR_Coverage, 9472,
     /*  131918 */   GIR_EraseRootFromParent_Done,
     /*  131919 */ // Label 1881: @131919
     /*  131919 */ GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(132022), // Rule ID 9473 //
     /*  131924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode4),
     /*  131927 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  131930 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  131934 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  131941 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  131946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  131950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  131954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  131961 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  131961 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  131964 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  131968 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  131973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  131978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  131983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  131988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  131993 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  131997 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  131999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  132002 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  132004 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  132011 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132016 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132021 */   // GIR_Coverage, 9473,
     /*  132021 */   GIR_EraseRootFromParent_Done,
     /*  132022 */ // Label 1882: @132022
     /*  132022 */ GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(132095), // Rule ID 13930 //
     /*  132027 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  132030 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132033 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  132037 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  132044 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132053 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132057 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132064 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  132067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132093 */   GIR_RootConstrainSelectedInstOperands,
     /*  132094 */   // GIR_Coverage, 13930,
     /*  132094 */   GIR_EraseRootFromParent_Done,
     /*  132095 */ // Label 1883: @132095
     /*  132095 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(132168), // Rule ID 13931 //
     /*  132100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  132103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132106 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  132110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  132117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132122 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132126 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132130 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132137 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132137 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  132140 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132162 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132166 */   GIR_RootConstrainSelectedInstOperands,
     /*  132167 */   // GIR_Coverage, 13931,
     /*  132167 */   GIR_EraseRootFromParent_Done,
     /*  132168 */ // Label 1884: @132168
     /*  132168 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(132241), // Rule ID 13932 //
     /*  132173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  132176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132179 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  132183 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  132190 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132199 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132203 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132210 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  132213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132239 */   GIR_RootConstrainSelectedInstOperands,
     /*  132240 */   // GIR_Coverage, 13932,
     /*  132240 */   GIR_EraseRootFromParent_Done,
     /*  132241 */ // Label 1885: @132241
     /*  132241 */ GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(132314), // Rule ID 13933 //
     /*  132246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  132249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132252 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  132256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  132263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132268 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132272 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132276 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132283 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132283 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  132286 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132308 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132312 */   GIR_RootConstrainSelectedInstOperands,
     /*  132313 */   // GIR_Coverage, 13933,
     /*  132313 */   GIR_EraseRootFromParent_Done,
     /*  132314 */ // Label 1886: @132314
     /*  132314 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(132387), // Rule ID 13934 //
     /*  132319 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  132322 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132325 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  132329 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  132336 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132345 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132349 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132356 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132356 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  132359 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132381 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132385 */   GIR_RootConstrainSelectedInstOperands,
     /*  132386 */   // GIR_Coverage, 13934,
     /*  132386 */   GIR_EraseRootFromParent_Done,
     /*  132387 */ // Label 1887: @132387
     /*  132387 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(132449), // Rule ID 13975 //
     /*  132392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  132395 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132398 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132403 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132407 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132411 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132418 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132418 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132421 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132447 */   GIR_RootConstrainSelectedInstOperands,
     /*  132448 */   // GIR_Coverage, 13975,
     /*  132448 */   GIR_EraseRootFromParent_Done,
     /*  132449 */ // Label 1888: @132449
     /*  132449 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(132511), // Rule ID 13976 //
     /*  132454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  132457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132460 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132465 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132469 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132473 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132480 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132483 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132505 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132509 */   GIR_RootConstrainSelectedInstOperands,
     /*  132510 */   // GIR_Coverage, 13976,
     /*  132510 */   GIR_EraseRootFromParent_Done,
     /*  132511 */ // Label 1889: @132511
     /*  132511 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(132573), // Rule ID 13977 //
     /*  132516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  132519 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132522 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132535 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132542 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132542 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132545 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132571 */   GIR_RootConstrainSelectedInstOperands,
     /*  132572 */   // GIR_Coverage, 13977,
     /*  132572 */   GIR_EraseRootFromParent_Done,
     /*  132573 */ // Label 1890: @132573
     /*  132573 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(132635), // Rule ID 13978 //
     /*  132578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  132581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132593 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132597 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132604 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132604 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132607 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132633 */   GIR_RootConstrainSelectedInstOperands,
     /*  132634 */   // GIR_Coverage, 13978,
     /*  132634 */   GIR_EraseRootFromParent_Done,
     /*  132635 */ // Label 1891: @132635
     /*  132635 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(132697), // Rule ID 13979 //
     /*  132640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  132643 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132646 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132655 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132666 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  132666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  132671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132691 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132695 */   GIR_RootConstrainSelectedInstOperands,
     /*  132696 */   // GIR_Coverage, 13979,
     /*  132696 */   GIR_EraseRootFromParent_Done,
     /*  132697 */ // Label 1892: @132697
     /*  132697 */ GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(132789), // Rule ID 14035 //
     /*  132702 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode0),
     /*  132705 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132708 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132717 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132721 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132728 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  132728 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  132731 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132735 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  132740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132760 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132764 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  132766 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  132769 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  132771 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  132778 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132783 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132788 */   // GIR_Coverage, 14035,
     /*  132788 */   GIR_EraseRootFromParent_Done,
     /*  132789 */ // Label 1893: @132789
     /*  132789 */ GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(132881), // Rule ID 14036 //
     /*  132794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode1),
     /*  132797 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132800 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132820 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  132820 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  132823 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132827 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  132832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132852 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132856 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  132858 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  132861 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  132863 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  132870 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132875 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132880 */   // GIR_Coverage, 14036,
     /*  132880 */   GIR_EraseRootFromParent_Done,
     /*  132881 */ // Label 1894: @132881
     /*  132881 */ GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(132973), // Rule ID 14037 //
     /*  132886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode2),
     /*  132889 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132892 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132901 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132905 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  132912 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  132912 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  132915 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  132919 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  132924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  132929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  132934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  132939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  132944 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  132948 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  132950 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  132953 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  132955 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  132962 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132967 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  132972 */   // GIR_Coverage, 14037,
     /*  132972 */   GIR_EraseRootFromParent_Done,
     /*  132973 */ // Label 1895: @132973
     /*  132973 */ GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(133065), // Rule ID 14038 //
     /*  132978 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode3),
     /*  132981 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  132984 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  132989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  132993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  132997 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  133004 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  133004 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133007 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  133011 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  133021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  133026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  133031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  133036 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133040 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133045 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133047 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133054 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133059 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133064 */   // GIR_Coverage, 14038,
     /*  133064 */   GIR_EraseRootFromParent_Done,
     /*  133065 */ // Label 1896: @133065
     /*  133065 */ GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(133157), // Rule ID 14039 //
     /*  133070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode4),
     /*  133073 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133076 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133085 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133089 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  133096 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  133096 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133099 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  133103 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  133113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  133118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  133123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  133128 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133132 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133137 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133139 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133146 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133151 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133156 */   // GIR_Coverage, 14039,
     /*  133156 */   GIR_EraseRootFromParent_Done,
     /*  133157 */ // Label 1897: @133157
     /*  133157 */ GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(133219), // Rule ID 14048 //
     /*  133162 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatScratchSVSMode_UseRealTrue16Insts),
     /*  133165 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133168 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133173 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133177 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133181 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  133188 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_SHORT_D16_SVS_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  133188 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SHORT_D16_SVS_t16),
     /*  133191 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  133193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  133198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  133203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  133208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  133213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133217 */   GIR_RootConstrainSelectedInstOperands,
     /*  133218 */   // GIR_Coverage, 14048,
     /*  133218 */   GIR_EraseRootFromParent_Done,
     /*  133219 */ // Label 1898: @133219
     /*  133219 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(133285), // Rule ID 9457 //
     /*  133224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  133227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133230 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133261 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  133261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_t16),
     /*  133264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  133266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  133279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133283 */   GIR_RootConstrainSelectedInstOperands,
     /*  133284 */   // GIR_Coverage, 9457,
     /*  133284 */   GIR_EraseRootFromParent_Done,
     /*  133285 */ // Label 1899: @133285
     /*  133285 */ GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(133381), // Rule ID 9464 //
     /*  133290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  133293 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133296 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133300 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133307 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133316 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133320 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133327 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  133327 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133330 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133334 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133349 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  133352 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133356 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133358 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133361 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133363 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133370 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133375 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133380 */   // GIR_Coverage, 9464,
     /*  133380 */   GIR_EraseRootFromParent_Done,
     /*  133381 */ // Label 1900: @133381
     /*  133381 */ GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(133477), // Rule ID 9465 //
     /*  133386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  133389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133392 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133412 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133416 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133423 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  133423 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133426 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133430 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133445 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  133448 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133452 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133454 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133457 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133459 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133466 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133471 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133476 */   // GIR_Coverage, 9465,
     /*  133476 */   GIR_EraseRootFromParent_Done,
     /*  133477 */ // Label 1901: @133477
     /*  133477 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(133573), // Rule ID 9466 //
     /*  133482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  133485 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133488 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133519 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  133519 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133522 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133526 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133541 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  133544 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133548 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133553 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133555 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133562 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133567 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133572 */   // GIR_Coverage, 9466,
     /*  133572 */   GIR_EraseRootFromParent_Done,
     /*  133573 */ // Label 1902: @133573
     /*  133573 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(133669), // Rule ID 9467 //
     /*  133578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  133581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133584 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133588 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133595 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133604 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133608 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133615 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  133615 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133618 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133622 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133637 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  133640 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133644 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133651 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133658 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133663 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133668 */   // GIR_Coverage, 9467,
     /*  133668 */   GIR_EraseRootFromParent_Done,
     /*  133669 */ // Label 1903: @133669
     /*  133669 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(133765), // Rule ID 9468 //
     /*  133674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  133677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133680 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133684 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133691 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133700 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133704 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133711 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  133711 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  133714 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133718 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  133723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133733 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  133736 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133740 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  133742 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  133745 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  133747 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  133754 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  133759 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133764 */   // GIR_Coverage, 9468,
     /*  133764 */   GIR_EraseRootFromParent_Done,
     /*  133765 */ // Label 1904: @133765
     /*  133765 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(133831), // Rule ID 13925 //
     /*  133770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  133773 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133776 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133780 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133787 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133796 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133800 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133807 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  133807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133810 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  133812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133822 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  133825 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133829 */   GIR_RootConstrainSelectedInstOperands,
     /*  133830 */   // GIR_Coverage, 13925,
     /*  133830 */   GIR_EraseRootFromParent_Done,
     /*  133831 */ // Label 1905: @133831
     /*  133831 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(133897), // Rule ID 13926 //
     /*  133836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  133839 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133842 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133846 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133853 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133862 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133866 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133873 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  133873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  133878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133888 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  133891 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133895 */   GIR_RootConstrainSelectedInstOperands,
     /*  133896 */   // GIR_Coverage, 13926,
     /*  133896 */   GIR_EraseRootFromParent_Done,
     /*  133897 */ // Label 1906: @133897
     /*  133897 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(133963), // Rule ID 13927 //
     /*  133902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  133905 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133908 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133912 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133919 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133924 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133928 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133932 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  133939 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  133939 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  133942 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  133944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  133949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  133954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  133957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  133961 */   GIR_RootConstrainSelectedInstOperands,
     /*  133962 */   // GIR_Coverage, 13927,
     /*  133962 */   GIR_EraseRootFromParent_Done,
     /*  133963 */ // Label 1907: @133963
     /*  133963 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(134029), // Rule ID 13928 //
     /*  133968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  133971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  133974 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  133978 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  133985 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  133990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  133994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  133998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134005 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  134008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134027 */   GIR_RootConstrainSelectedInstOperands,
     /*  134028 */   // GIR_Coverage, 13928,
     /*  134028 */   GIR_EraseRootFromParent_Done,
     /*  134029 */ // Label 1908: @134029
     /*  134029 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(134095), // Rule ID 13929 //
     /*  134034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  134037 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134040 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  134044 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  134051 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134056 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134060 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134064 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134071 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  134074 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134093 */   GIR_RootConstrainSelectedInstOperands,
     /*  134094 */   // GIR_Coverage, 13929,
     /*  134094 */   GIR_EraseRootFromParent_Done,
     /*  134095 */ // Label 1909: @134095
     /*  134095 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(134150), // Rule ID 13970 //
     /*  134100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  134103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134111 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134115 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134119 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134126 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134126 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134129 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134141 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134144 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134148 */   GIR_RootConstrainSelectedInstOperands,
     /*  134149 */   // GIR_Coverage, 13970,
     /*  134149 */   GIR_EraseRootFromParent_Done,
     /*  134150 */ // Label 1910: @134150
     /*  134150 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(134205), // Rule ID 13971 //
     /*  134155 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  134158 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134161 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134170 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134174 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134181 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134196 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134199 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134203 */   GIR_RootConstrainSelectedInstOperands,
     /*  134204 */   // GIR_Coverage, 13971,
     /*  134204 */   GIR_EraseRootFromParent_Done,
     /*  134205 */ // Label 1911: @134205
     /*  134205 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(134260), // Rule ID 13972 //
     /*  134210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  134213 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134236 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134251 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134254 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134258 */   GIR_RootConstrainSelectedInstOperands,
     /*  134259 */   // GIR_Coverage, 13972,
     /*  134259 */   GIR_EraseRootFromParent_Done,
     /*  134260 */ // Label 1912: @134260
     /*  134260 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(134315), // Rule ID 13973 //
     /*  134265 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  134268 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134271 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134291 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134306 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134309 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134313 */   GIR_RootConstrainSelectedInstOperands,
     /*  134314 */   // GIR_Coverage, 13973,
     /*  134314 */   GIR_EraseRootFromParent_Done,
     /*  134315 */ // Label 1913: @134315
     /*  134315 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(134370), // Rule ID 13974 //
     /*  134320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  134323 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134326 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134335 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134339 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134346 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  134346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134349 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134361 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134364 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134368 */   GIR_RootConstrainSelectedInstOperands,
     /*  134369 */   // GIR_Coverage, 13974,
     /*  134369 */   GIR_EraseRootFromParent_Done,
     /*  134370 */ // Label 1914: @134370
     /*  134370 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(134455), // Rule ID 14030 //
     /*  134375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  134378 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134381 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134390 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134394 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134401 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  134401 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  134404 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134408 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  134413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134423 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  134426 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134430 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  134432 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  134435 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  134437 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  134444 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134449 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134454 */   // GIR_Coverage, 14030,
     /*  134454 */   GIR_EraseRootFromParent_Done,
     /*  134455 */ // Label 1915: @134455
     /*  134455 */ GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(134540), // Rule ID 14031 //
     /*  134460 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  134463 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134466 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134475 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134479 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134486 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  134486 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  134489 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134493 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  134498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134508 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  134511 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134515 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  134517 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  134520 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  134522 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  134529 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134534 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134539 */   // GIR_Coverage, 14031,
     /*  134539 */   GIR_EraseRootFromParent_Done,
     /*  134540 */ // Label 1916: @134540
     /*  134540 */ GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(134625), // Rule ID 14032 //
     /*  134545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  134548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134560 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134564 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134571 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  134571 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  134574 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134578 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  134583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134593 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  134596 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134600 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  134602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  134605 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  134607 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  134614 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134619 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134624 */   // GIR_Coverage, 14032,
     /*  134624 */   GIR_EraseRootFromParent_Done,
     /*  134625 */ // Label 1917: @134625
     /*  134625 */ GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(134710), // Rule ID 14033 //
     /*  134630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  134633 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134636 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134645 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134649 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134656 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  134656 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  134659 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134663 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  134668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134678 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  134681 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134685 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  134687 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  134690 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  134692 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  134699 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134704 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134709 */   // GIR_Coverage, 14033,
     /*  134709 */   GIR_EraseRootFromParent_Done,
     /*  134710 */ // Label 1918: @134710
     /*  134710 */ GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(134795), // Rule ID 14034 //
     /*  134715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  134718 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134721 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134726 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134730 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134734 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134741 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  134741 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  134744 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  134748 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  134753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134763 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  134766 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134770 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  134772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  134775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  134777 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  134784 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134789 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  134794 */   // GIR_Coverage, 14034,
     /*  134794 */   GIR_EraseRootFromParent_Done,
     /*  134795 */ // Label 1919: @134795
     /*  134795 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(134850), // Rule ID 14047 //
     /*  134800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  134803 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134806 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134815 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134819 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  134826 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_SHORT_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  134826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_t16),
     /*  134829 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  134836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134841 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134844 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134848 */   GIR_RootConstrainSelectedInstOperands,
     /*  134849 */   // GIR_Coverage, 14047,
     /*  134849 */   GIR_EraseRootFromParent_Done,
     /*  134850 */ // Label 1920: @134850
     /*  134850 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(134916), // Rule ID 9456 //
     /*  134855 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  134858 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134861 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  134865 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  134872 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134881 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134885 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  134892 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  134892 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_D16_t16),
     /*  134895 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  134897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  134902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134907 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  134910 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134914 */   GIR_RootConstrainSelectedInstOperands,
     /*  134915 */   // GIR_Coverage, 9456,
     /*  134915 */   GIR_EraseRootFromParent_Done,
     /*  134916 */ // Label 1921: @134916
     /*  134916 */ GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(135012), // Rule ID 9459 //
     /*  134921 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  134924 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  134927 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  134931 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  134938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  134943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  134947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  134951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  134958 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  134958 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  134961 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  134965 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  134970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  134975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  134980 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  134983 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  134987 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  134989 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  134992 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  134994 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  135001 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135006 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135011 */   // GIR_Coverage, 9459,
     /*  135011 */   GIR_EraseRootFromParent_Done,
     /*  135012 */ // Label 1922: @135012
     /*  135012 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(135108), // Rule ID 9460 //
     /*  135017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  135020 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135023 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135027 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135034 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135039 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135043 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135047 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135054 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  135054 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  135057 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135061 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  135066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135076 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  135079 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135083 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  135085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  135088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  135090 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  135097 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135102 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135107 */   // GIR_Coverage, 9460,
     /*  135107 */   GIR_EraseRootFromParent_Done,
     /*  135108 */ // Label 1923: @135108
     /*  135108 */ GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(135204), // Rule ID 9461 //
     /*  135113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  135116 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135119 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135123 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135130 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135139 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135143 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135150 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  135150 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  135153 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135157 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  135162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135172 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  135175 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135179 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  135181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  135184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  135186 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  135193 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135198 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135203 */   // GIR_Coverage, 9461,
     /*  135203 */   GIR_EraseRootFromParent_Done,
     /*  135204 */ // Label 1924: @135204
     /*  135204 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(135300), // Rule ID 9462 //
     /*  135209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  135212 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135215 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135219 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135235 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135239 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135246 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  135246 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  135249 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135253 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  135258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135268 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  135271 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135275 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  135277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  135280 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  135282 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  135289 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135294 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135299 */   // GIR_Coverage, 9462,
     /*  135299 */   GIR_EraseRootFromParent_Done,
     /*  135300 */ // Label 1925: @135300
     /*  135300 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(135396), // Rule ID 9463 //
     /*  135305 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  135308 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135311 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135315 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135322 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135331 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135335 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135342 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  135342 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  135345 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135349 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  135354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135364 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  135367 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135371 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  135373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  135376 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  135378 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  135385 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  135390 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135395 */   // GIR_Coverage, 9463,
     /*  135395 */   GIR_EraseRootFromParent_Done,
     /*  135396 */ // Label 1926: @135396
     /*  135396 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(135462), // Rule ID 13920 //
     /*  135401 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  135404 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135407 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135411 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135418 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135427 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135431 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135438 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135441 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135453 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135456 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135460 */   GIR_RootConstrainSelectedInstOperands,
     /*  135461 */   // GIR_Coverage, 13920,
     /*  135461 */   GIR_EraseRootFromParent_Done,
     /*  135462 */ // Label 1927: @135462
     /*  135462 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(135528), // Rule ID 13921 //
     /*  135467 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  135470 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135473 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135477 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135484 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135493 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135497 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135504 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135507 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135519 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135522 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135526 */   GIR_RootConstrainSelectedInstOperands,
     /*  135527 */   // GIR_Coverage, 13921,
     /*  135527 */   GIR_EraseRootFromParent_Done,
     /*  135528 */ // Label 1928: @135528
     /*  135528 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(135594), // Rule ID 13922 //
     /*  135533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  135536 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135539 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135543 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135559 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135563 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135570 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135570 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135573 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135585 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135588 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135592 */   GIR_RootConstrainSelectedInstOperands,
     /*  135593 */   // GIR_Coverage, 13922,
     /*  135593 */   GIR_EraseRootFromParent_Done,
     /*  135594 */ // Label 1929: @135594
     /*  135594 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(135660), // Rule ID 13923 //
     /*  135599 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  135602 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135605 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135609 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135616 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135625 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135629 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135636 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135639 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135651 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135654 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135658 */   GIR_RootConstrainSelectedInstOperands,
     /*  135659 */   // GIR_Coverage, 13923,
     /*  135659 */   GIR_EraseRootFromParent_Done,
     /*  135660 */ // Label 1930: @135660
     /*  135660 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(135726), // Rule ID 13924 //
     /*  135665 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  135668 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135671 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  135675 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  135682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135691 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135695 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135702 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135702 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  135705 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135717 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135720 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135724 */   GIR_RootConstrainSelectedInstOperands,
     /*  135725 */   // GIR_Coverage, 13924,
     /*  135725 */   GIR_EraseRootFromParent_Done,
     /*  135726 */ // Label 1931: @135726
     /*  135726 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(135781), // Rule ID 13965 //
     /*  135731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  135734 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135737 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135746 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135750 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135757 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135757 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  135760 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135772 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135775 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135779 */   GIR_RootConstrainSelectedInstOperands,
     /*  135780 */   // GIR_Coverage, 13965,
     /*  135780 */   GIR_EraseRootFromParent_Done,
     /*  135781 */ // Label 1932: @135781
     /*  135781 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(135836), // Rule ID 13966 //
     /*  135786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  135789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135792 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135801 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135812 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135812 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  135815 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135827 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135830 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135834 */   GIR_RootConstrainSelectedInstOperands,
     /*  135835 */   // GIR_Coverage, 13966,
     /*  135835 */   GIR_EraseRootFromParent_Done,
     /*  135836 */ // Label 1933: @135836
     /*  135836 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(135891), // Rule ID 13967 //
     /*  135841 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  135844 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135847 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135867 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  135870 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135889 */   GIR_RootConstrainSelectedInstOperands,
     /*  135890 */   // GIR_Coverage, 13967,
     /*  135890 */   GIR_EraseRootFromParent_Done,
     /*  135891 */ // Label 1934: @135891
     /*  135891 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(135946), // Rule ID 13968 //
     /*  135896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  135899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135902 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135911 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135915 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135922 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  135925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135937 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135940 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135944 */   GIR_RootConstrainSelectedInstOperands,
     /*  135945 */   // GIR_Coverage, 13968,
     /*  135945 */   GIR_EraseRootFromParent_Done,
     /*  135946 */ // Label 1935: @135946
     /*  135946 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(136001), // Rule ID 13969 //
     /*  135951 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  135954 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  135957 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  135962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  135966 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  135970 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  135977 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  135977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  135980 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  135982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  135987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  135992 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  135995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  135999 */   GIR_RootConstrainSelectedInstOperands,
     /*  136000 */   // GIR_Coverage, 13969,
     /*  136000 */   GIR_EraseRootFromParent_Done,
     /*  136001 */ // Label 1936: @136001
     /*  136001 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(136086), // Rule ID 14025 //
     /*  136006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  136009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  136012 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  136017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136021 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136025 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  136032 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  136032 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  136035 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  136039 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  136044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  136049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  136054 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  136057 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136061 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  136063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  136066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  136068 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  136075 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136080 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136085 */   // GIR_Coverage, 14025,
     /*  136085 */   GIR_EraseRootFromParent_Done,
     /*  136086 */ // Label 1937: @136086
     /*  136086 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(136171), // Rule ID 14026 //
     /*  136091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  136094 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  136097 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  136102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136106 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136110 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  136117 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  136117 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  136120 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  136124 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  136129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  136134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  136139 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  136142 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136146 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  136148 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  136151 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  136153 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  136160 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136165 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136170 */   // GIR_Coverage, 14026,
     /*  136170 */   GIR_EraseRootFromParent_Done,
     /*  136171 */ // Label 1938: @136171
     /*  136171 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(136256), // Rule ID 14027 //
     /*  136176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  136179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  136182 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  136187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136191 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136195 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  136202 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  136202 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  136205 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  136209 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  136214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  136219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  136224 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  136227 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136231 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  136233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  136236 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  136238 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  136245 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136250 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136255 */   // GIR_Coverage, 14027,
     /*  136255 */   GIR_EraseRootFromParent_Done,
     /*  136256 */ // Label 1939: @136256
     /*  136256 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(136341), // Rule ID 14028 //
     /*  136261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  136264 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  136267 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  136272 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136276 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136280 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  136287 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  136287 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  136290 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  136294 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  136299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  136304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  136309 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  136312 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136316 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  136318 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  136321 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  136323 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  136330 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136335 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136340 */   // GIR_Coverage, 14028,
     /*  136340 */   GIR_EraseRootFromParent_Done,
     /*  136341 */ // Label 1940: @136341
     /*  136341 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(136426), // Rule ID 14029 //
     /*  136346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  136349 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  136352 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  136357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136361 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136365 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  136372 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  136372 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  136375 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  136379 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  136384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  136389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  136394 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  136397 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136401 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  136403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  136406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  136408 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  136415 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136420 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136425 */   // GIR_Coverage, 14029,
     /*  136425 */   GIR_EraseRootFromParent_Done,
     /*  136426 */ // Label 1941: @136426
     /*  136426 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(136481), // Rule ID 14046 //
     /*  136431 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  136434 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  136437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  136442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  136446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  136457 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  136457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SHORT_D16_t16),
     /*  136460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  136462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  136467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  136472 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136479 */   GIR_RootConstrainSelectedInstOperands,
     /*  136480 */   // GIR_Coverage, 14046,
     /*  136480 */   GIR_EraseRootFromParent_Done,
     /*  136481 */ // Label 1942: @136481
     /*  136481 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(136562), // Rule ID 15128 //
     /*  136486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  136489 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136492 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  136525 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  136525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  136528 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  136530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  136535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  136540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  136545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  136550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136553 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136556 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136560 */   GIR_RootConstrainSelectedInstOperands,
     /*  136561 */   // GIR_Coverage, 15128,
     /*  136561 */   GIR_EraseRootFromParent_Done,
     /*  136562 */ // Label 1943: @136562
     /*  136562 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(136643), // Rule ID 15129 //
     /*  136567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  136570 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136573 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136577 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  136606 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  136606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  136609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  136611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  136616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  136621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  136626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  136631 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136634 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136637 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136641 */   GIR_RootConstrainSelectedInstOperands,
     /*  136642 */   // GIR_Coverage, 15129,
     /*  136642 */   GIR_EraseRootFromParent_Done,
     /*  136643 */ // Label 1944: @136643
     /*  136643 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(136724), // Rule ID 15130 //
     /*  136648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  136651 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136654 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136658 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136665 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136676 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136680 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  136687 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  136687 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  136690 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  136692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  136697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  136702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  136707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  136712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136715 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136718 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136722 */   GIR_RootConstrainSelectedInstOperands,
     /*  136723 */   // GIR_Coverage, 15130,
     /*  136723 */   GIR_EraseRootFromParent_Done,
     /*  136724 */ // Label 1945: @136724
     /*  136724 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(136805), // Rule ID 15131 //
     /*  136729 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  136732 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136735 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136746 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136757 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136761 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  136768 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  136768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  136771 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  136773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  136778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  136783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  136788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  136793 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136796 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136799 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136803 */   GIR_RootConstrainSelectedInstOperands,
     /*  136804 */   // GIR_Coverage, 15131,
     /*  136804 */   GIR_EraseRootFromParent_Done,
     /*  136805 */ // Label 1946: @136805
     /*  136805 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(136886), // Rule ID 15132 //
     /*  136810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  136813 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136816 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136820 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136827 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136842 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  136849 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  136849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  136852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  136854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  136859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  136864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  136869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  136874 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136884 */   GIR_RootConstrainSelectedInstOperands,
     /*  136885 */   // GIR_Coverage, 15132,
     /*  136885 */   GIR_EraseRootFromParent_Done,
     /*  136886 */ // Label 1947: @136886
     /*  136886 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(136967), // Rule ID 15138 //
     /*  136891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  136894 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136897 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136901 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136908 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  136919 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  136923 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  136930 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  136930 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  136933 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  136935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  136940 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  136945 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  136950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  136955 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136958 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  136961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  136965 */   GIR_RootConstrainSelectedInstOperands,
     /*  136966 */   // GIR_Coverage, 15138,
     /*  136966 */   GIR_EraseRootFromParent_Done,
     /*  136967 */ // Label 1948: @136967
     /*  136967 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(137048), // Rule ID 15139 //
     /*  136972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  136975 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  136978 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  136982 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  136989 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  136996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137000 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137004 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137011 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  137014 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137036 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137046 */   GIR_RootConstrainSelectedInstOperands,
     /*  137047 */   // GIR_Coverage, 15139,
     /*  137047 */   GIR_EraseRootFromParent_Done,
     /*  137048 */ // Label 1949: @137048
     /*  137048 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(137129), // Rule ID 15140 //
     /*  137053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  137056 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137059 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137063 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  137070 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137077 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137081 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137085 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137092 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137092 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  137095 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137120 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137123 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137127 */   GIR_RootConstrainSelectedInstOperands,
     /*  137128 */   // GIR_Coverage, 15140,
     /*  137128 */   GIR_EraseRootFromParent_Done,
     /*  137129 */ // Label 1950: @137129
     /*  137129 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(137210), // Rule ID 15141 //
     /*  137134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  137137 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137140 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137144 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  137151 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137158 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137166 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137173 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  137176 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137198 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137201 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137204 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137208 */   GIR_RootConstrainSelectedInstOperands,
     /*  137209 */   // GIR_Coverage, 15141,
     /*  137209 */   GIR_EraseRootFromParent_Done,
     /*  137210 */ // Label 1951: @137210
     /*  137210 */ GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(137291), // Rule ID 15142 //
     /*  137215 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  137218 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137221 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137225 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  137232 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137254 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  137257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137279 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137282 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137285 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137289 */   GIR_RootConstrainSelectedInstOperands,
     /*  137290 */   // GIR_Coverage, 15142,
     /*  137290 */   GIR_EraseRootFromParent_Done,
     /*  137291 */ // Label 1952: @137291
     /*  137291 */ GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(137372), // Rule ID 15168 //
     /*  137296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  137299 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137302 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137335 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  137338 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137360 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137370 */   GIR_RootConstrainSelectedInstOperands,
     /*  137371 */   // GIR_Coverage, 15168,
     /*  137371 */   GIR_EraseRootFromParent_Done,
     /*  137372 */ // Label 1953: @137372
     /*  137372 */ GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(137453), // Rule ID 15169 //
     /*  137377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  137380 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137383 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137387 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137394 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137405 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137409 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137416 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  137419 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137441 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137444 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137447 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137451 */   GIR_RootConstrainSelectedInstOperands,
     /*  137452 */   // GIR_Coverage, 15169,
     /*  137452 */   GIR_EraseRootFromParent_Done,
     /*  137453 */ // Label 1954: @137453
     /*  137453 */ GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(137534), // Rule ID 15170 //
     /*  137458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  137461 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137464 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137468 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137475 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137486 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137490 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137497 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  137500 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137502 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137522 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137532 */   GIR_RootConstrainSelectedInstOperands,
     /*  137533 */   // GIR_Coverage, 15170,
     /*  137533 */   GIR_EraseRootFromParent_Done,
     /*  137534 */ // Label 1955: @137534
     /*  137534 */ GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(137615), // Rule ID 15171 //
     /*  137539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  137542 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137545 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137549 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137578 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  137581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137613 */   GIR_RootConstrainSelectedInstOperands,
     /*  137614 */   // GIR_Coverage, 15171,
     /*  137614 */   GIR_EraseRootFromParent_Done,
     /*  137615 */ // Label 1956: @137615
     /*  137615 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(137696), // Rule ID 15172 //
     /*  137620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  137623 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137626 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137637 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137659 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  137662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137684 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137687 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137690 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137694 */   GIR_RootConstrainSelectedInstOperands,
     /*  137695 */   // GIR_Coverage, 15172,
     /*  137695 */   GIR_EraseRootFromParent_Done,
     /*  137696 */ // Label 1957: @137696
     /*  137696 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(137777), // Rule ID 15178 //
     /*  137701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  137704 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137707 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137711 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137740 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  137743 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137765 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137771 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137775 */   GIR_RootConstrainSelectedInstOperands,
     /*  137776 */   // GIR_Coverage, 15178,
     /*  137776 */   GIR_EraseRootFromParent_Done,
     /*  137777 */ // Label 1958: @137777
     /*  137777 */ GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(137858), // Rule ID 15179 //
     /*  137782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  137785 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137788 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137792 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137821 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  137824 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137846 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137856 */   GIR_RootConstrainSelectedInstOperands,
     /*  137857 */   // GIR_Coverage, 15179,
     /*  137857 */   GIR_EraseRootFromParent_Done,
     /*  137858 */ // Label 1959: @137858
     /*  137858 */ GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(137939), // Rule ID 15180 //
     /*  137863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  137866 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137869 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137873 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137880 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137891 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137895 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137902 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137902 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  137905 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  137922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  137927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137930 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  137933 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  137937 */   GIR_RootConstrainSelectedInstOperands,
     /*  137938 */   // GIR_Coverage, 15180,
     /*  137938 */   GIR_EraseRootFromParent_Done,
     /*  137939 */ // Label 1960: @137939
     /*  137939 */ GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(138020), // Rule ID 15181 //
     /*  137944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  137947 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  137950 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  137954 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  137961 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  137968 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  137972 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  137976 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  137983 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  137983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  137986 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  137988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  137993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  137998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138008 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138011 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138014 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138018 */   GIR_RootConstrainSelectedInstOperands,
     /*  138019 */   // GIR_Coverage, 15181,
     /*  138019 */   GIR_EraseRootFromParent_Done,
     /*  138020 */ // Label 1961: @138020
     /*  138020 */ GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(138101), // Rule ID 15182 //
     /*  138025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  138028 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  138031 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138035 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  138042 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  138049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138053 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138057 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  138064 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  138064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  138067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138095 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138099 */   GIR_RootConstrainSelectedInstOperands,
     /*  138100 */   // GIR_Coverage, 15182,
     /*  138100 */   GIR_EraseRootFromParent_Done,
     /*  138101 */ // Label 1962: @138101
     /*  138101 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(138180), // Rule ID 25051 //
     /*  138106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  138109 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138112 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138116 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138123 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138136 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138143 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  138146 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138168 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138178 */   GIR_RootConstrainSelectedInstOperands,
     /*  138179 */   // GIR_Coverage, 25051,
     /*  138179 */   GIR_EraseRootFromParent_Done,
     /*  138180 */ // Label 1963: @138180
     /*  138180 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(138259), // Rule ID 25052 //
     /*  138185 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  138188 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138191 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138195 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138202 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138211 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138215 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138222 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  138225 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138247 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138250 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138253 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138257 */   GIR_RootConstrainSelectedInstOperands,
     /*  138258 */   // GIR_Coverage, 25052,
     /*  138258 */   GIR_EraseRootFromParent_Done,
     /*  138259 */ // Label 1964: @138259
     /*  138259 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(138338), // Rule ID 25053 //
     /*  138264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  138267 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138270 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138274 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138281 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138290 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138294 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138301 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138301 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  138304 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138329 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138332 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138336 */   GIR_RootConstrainSelectedInstOperands,
     /*  138337 */   // GIR_Coverage, 25053,
     /*  138337 */   GIR_EraseRootFromParent_Done,
     /*  138338 */ // Label 1965: @138338
     /*  138338 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(138417), // Rule ID 25054 //
     /*  138343 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  138346 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138349 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138353 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138360 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138369 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138373 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138380 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138380 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  138383 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138405 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138415 */   GIR_RootConstrainSelectedInstOperands,
     /*  138416 */   // GIR_Coverage, 25054,
     /*  138416 */   GIR_EraseRootFromParent_Done,
     /*  138417 */ // Label 1966: @138417
     /*  138417 */ GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(138496), // Rule ID 25055 //
     /*  138422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  138425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138428 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138432 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138439 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138459 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  138462 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138487 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138490 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138494 */   GIR_RootConstrainSelectedInstOperands,
     /*  138495 */   // GIR_Coverage, 25055,
     /*  138495 */   GIR_EraseRootFromParent_Done,
     /*  138496 */ // Label 1967: @138496
     /*  138496 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(138575), // Rule ID 25061 //
     /*  138501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  138504 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138507 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138511 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138518 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138527 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138531 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138538 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138538 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  138541 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138563 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138569 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138573 */   GIR_RootConstrainSelectedInstOperands,
     /*  138574 */   // GIR_Coverage, 25061,
     /*  138574 */   GIR_EraseRootFromParent_Done,
     /*  138575 */ // Label 1968: @138575
     /*  138575 */ GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(138654), // Rule ID 25062 //
     /*  138580 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  138583 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138586 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138590 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138597 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138617 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  138620 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138642 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138645 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138648 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138652 */   GIR_RootConstrainSelectedInstOperands,
     /*  138653 */   // GIR_Coverage, 25062,
     /*  138653 */   GIR_EraseRootFromParent_Done,
     /*  138654 */ // Label 1969: @138654
     /*  138654 */ GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(138733), // Rule ID 25063 //
     /*  138659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  138662 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138665 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138669 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138676 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138696 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  138699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138731 */   GIR_RootConstrainSelectedInstOperands,
     /*  138732 */   // GIR_Coverage, 25063,
     /*  138732 */   GIR_EraseRootFromParent_Done,
     /*  138733 */ // Label 1970: @138733
     /*  138733 */ GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(138812), // Rule ID 25064 //
     /*  138738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  138741 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138744 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138748 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138755 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138775 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  138778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138803 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138806 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138810 */   GIR_RootConstrainSelectedInstOperands,
     /*  138811 */   // GIR_Coverage, 25064,
     /*  138811 */   GIR_EraseRootFromParent_Done,
     /*  138812 */ // Label 1971: @138812
     /*  138812 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(138891), // Rule ID 25065 //
     /*  138817 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  138820 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138823 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  138827 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  138834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138847 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138854 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138854 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  138857 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138889 */   GIR_RootConstrainSelectedInstOperands,
     /*  138890 */   // GIR_Coverage, 25065,
     /*  138890 */   GIR_EraseRootFromParent_Done,
     /*  138891 */ // Label 1972: @138891
     /*  138891 */ GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(138959), // Rule ID 25151 //
     /*  138896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  138899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138902 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138911 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138915 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138922 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  138925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  138932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  138937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  138942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  138947 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138950 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  138953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  138957 */   GIR_RootConstrainSelectedInstOperands,
     /*  138958 */   // GIR_Coverage, 25151,
     /*  138958 */   GIR_EraseRootFromParent_Done,
     /*  138959 */ // Label 1973: @138959
     /*  138959 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(139027), // Rule ID 25152 //
     /*  138964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  138967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  138970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  138975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  138979 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  138983 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  138990 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  138990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  138993 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  138995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139015 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139021 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139025 */   GIR_RootConstrainSelectedInstOperands,
     /*  139026 */   // GIR_Coverage, 25152,
     /*  139026 */   GIR_EraseRootFromParent_Done,
     /*  139027 */ // Label 1974: @139027
     /*  139027 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(139095), // Rule ID 25153 //
     /*  139032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  139035 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139038 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139058 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  139061 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139093 */   GIR_RootConstrainSelectedInstOperands,
     /*  139094 */   // GIR_Coverage, 25153,
     /*  139094 */   GIR_EraseRootFromParent_Done,
     /*  139095 */ // Label 1975: @139095
     /*  139095 */ GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(139163), // Rule ID 25154 //
     /*  139100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  139103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139111 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139115 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139119 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139126 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139126 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  139129 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139146 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139151 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139154 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139161 */   GIR_RootConstrainSelectedInstOperands,
     /*  139162 */   // GIR_Coverage, 25154,
     /*  139162 */   GIR_EraseRootFromParent_Done,
     /*  139163 */ // Label 1976: @139163
     /*  139163 */ GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(139231), // Rule ID 25155 //
     /*  139168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  139171 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139174 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139183 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139187 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139194 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  139197 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139222 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139225 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139229 */   GIR_RootConstrainSelectedInstOperands,
     /*  139230 */   // GIR_Coverage, 25155,
     /*  139230 */   GIR_EraseRootFromParent_Done,
     /*  139231 */ // Label 1977: @139231
     /*  139231 */ GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(139299), // Rule ID 25161 //
     /*  139236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  139239 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139242 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139251 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139255 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139262 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  139265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139287 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139290 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139293 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139297 */   GIR_RootConstrainSelectedInstOperands,
     /*  139298 */   // GIR_Coverage, 25161,
     /*  139298 */   GIR_EraseRootFromParent_Done,
     /*  139299 */ // Label 1978: @139299
     /*  139299 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(139367), // Rule ID 25162 //
     /*  139304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  139307 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139310 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139319 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139323 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139330 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139330 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  139333 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139355 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139358 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139361 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139365 */   GIR_RootConstrainSelectedInstOperands,
     /*  139366 */   // GIR_Coverage, 25162,
     /*  139366 */   GIR_EraseRootFromParent_Done,
     /*  139367 */ // Label 1979: @139367
     /*  139367 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(139435), // Rule ID 25163 //
     /*  139372 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  139375 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139378 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139383 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139387 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139391 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139398 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139398 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  139401 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139423 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139426 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139429 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139433 */   GIR_RootConstrainSelectedInstOperands,
     /*  139434 */   // GIR_Coverage, 25163,
     /*  139434 */   GIR_EraseRootFromParent_Done,
     /*  139435 */ // Label 1980: @139435
     /*  139435 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(139503), // Rule ID 25164 //
     /*  139440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  139443 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139446 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139466 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  139469 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139501 */   GIR_RootConstrainSelectedInstOperands,
     /*  139502 */   // GIR_Coverage, 25164,
     /*  139502 */   GIR_EraseRootFromParent_Done,
     /*  139503 */ // Label 1981: @139503
     /*  139503 */ GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(139571), // Rule ID 25165 //
     /*  139508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  139511 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  139514 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  139519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139523 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139527 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  139534 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  139534 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  139537 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  139544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  139554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  139559 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139562 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139565 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139569 */   GIR_RootConstrainSelectedInstOperands,
     /*  139570 */   // GIR_Coverage, 25165,
     /*  139570 */   GIR_EraseRootFromParent_Done,
     /*  139571 */ // Label 1982: @139571
     /*  139571 */ GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(139647), // Rule ID 15123 //
     /*  139576 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  139579 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  139582 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  139586 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  139593 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  139600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139604 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139608 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  139615 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  139615 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  139618 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  139630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  139635 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139641 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139645 */   GIR_RootConstrainSelectedInstOperands,
     /*  139646 */   // GIR_Coverage, 15123,
     /*  139646 */   GIR_EraseRootFromParent_Done,
     /*  139647 */ // Label 1983: @139647
     /*  139647 */ GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(139723), // Rule ID 15124 //
     /*  139652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  139655 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  139658 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  139662 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  139669 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  139676 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139680 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139684 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  139691 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  139691 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  139694 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  139706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  139711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139714 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139717 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139721 */   GIR_RootConstrainSelectedInstOperands,
     /*  139722 */   // GIR_Coverage, 15124,
     /*  139722 */   GIR_EraseRootFromParent_Done,
     /*  139723 */ // Label 1984: @139723
     /*  139723 */ GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(139799), // Rule ID 15125 //
     /*  139728 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  139731 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  139734 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  139738 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  139745 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  139752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  139767 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  139767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  139770 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  139782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  139787 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139790 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139797 */   GIR_RootConstrainSelectedInstOperands,
     /*  139798 */   // GIR_Coverage, 15125,
     /*  139798 */   GIR_EraseRootFromParent_Done,
     /*  139799 */ // Label 1985: @139799
     /*  139799 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(139875), // Rule ID 15126 //
     /*  139804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  139807 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  139810 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  139814 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  139821 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  139828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139832 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139836 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  139843 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  139843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  139846 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  139858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  139863 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139866 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139869 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139873 */   GIR_RootConstrainSelectedInstOperands,
     /*  139874 */   // GIR_Coverage, 15126,
     /*  139874 */   GIR_EraseRootFromParent_Done,
     /*  139875 */ // Label 1986: @139875
     /*  139875 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(139951), // Rule ID 15127 //
     /*  139880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  139883 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  139886 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  139890 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  139897 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  139904 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139908 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139912 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  139919 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  139919 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  139922 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  139924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  139929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  139934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  139939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139942 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  139945 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  139949 */   GIR_RootConstrainSelectedInstOperands,
     /*  139950 */   // GIR_Coverage, 15127,
     /*  139950 */   GIR_EraseRootFromParent_Done,
     /*  139951 */ // Label 1987: @139951
     /*  139951 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(140027), // Rule ID 15133 //
     /*  139956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  139959 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  139962 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  139966 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  139973 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  139980 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  139984 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  139988 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  139995 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  139995 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  139998 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140015 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140021 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140025 */   GIR_RootConstrainSelectedInstOperands,
     /*  140026 */   // GIR_Coverage, 15133,
     /*  140026 */   GIR_EraseRootFromParent_Done,
     /*  140027 */ // Label 1988: @140027
     /*  140027 */ GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(140103), // Rule ID 15134 //
     /*  140032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  140035 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140038 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140042 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  140049 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140056 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140060 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140064 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140071 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  140074 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140091 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140094 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140097 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140101 */   GIR_RootConstrainSelectedInstOperands,
     /*  140102 */   // GIR_Coverage, 15134,
     /*  140102 */   GIR_EraseRootFromParent_Done,
     /*  140103 */ // Label 1989: @140103
     /*  140103 */ GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(140179), // Rule ID 15135 //
     /*  140108 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  140111 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140114 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140118 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  140125 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140147 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  140150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140173 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140177 */   GIR_RootConstrainSelectedInstOperands,
     /*  140178 */   // GIR_Coverage, 15135,
     /*  140178 */   GIR_EraseRootFromParent_Done,
     /*  140179 */ // Label 1990: @140179
     /*  140179 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(140255), // Rule ID 15136 //
     /*  140184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  140187 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140190 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140194 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  140201 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140208 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140212 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140216 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140223 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  140226 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140243 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140249 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140253 */   GIR_RootConstrainSelectedInstOperands,
     /*  140254 */   // GIR_Coverage, 15136,
     /*  140254 */   GIR_EraseRootFromParent_Done,
     /*  140255 */ // Label 1991: @140255
     /*  140255 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(140331), // Rule ID 15137 //
     /*  140260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  140263 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140266 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140270 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  140277 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140288 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140292 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140299 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140299 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  140302 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140309 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140319 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140325 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140329 */   GIR_RootConstrainSelectedInstOperands,
     /*  140330 */   // GIR_Coverage, 15137,
     /*  140330 */   GIR_EraseRootFromParent_Done,
     /*  140331 */ // Label 1992: @140331
     /*  140331 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(140407), // Rule ID 15163 //
     /*  140336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  140339 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140342 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140346 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140353 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140360 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140364 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140368 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140375 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140375 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  140378 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140395 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140398 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140401 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140405 */   GIR_RootConstrainSelectedInstOperands,
     /*  140406 */   // GIR_Coverage, 15163,
     /*  140406 */   GIR_EraseRootFromParent_Done,
     /*  140407 */ // Label 1993: @140407
     /*  140407 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(140483), // Rule ID 15164 //
     /*  140412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  140415 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140418 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140422 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140429 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140440 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140444 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140451 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140451 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  140454 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140456 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140474 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140477 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140481 */   GIR_RootConstrainSelectedInstOperands,
     /*  140482 */   // GIR_Coverage, 15164,
     /*  140482 */   GIR_EraseRootFromParent_Done,
     /*  140483 */ // Label 1994: @140483
     /*  140483 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(140559), // Rule ID 15165 //
     /*  140488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  140491 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140494 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140498 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140505 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140516 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140520 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140527 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140527 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  140530 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140547 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140557 */   GIR_RootConstrainSelectedInstOperands,
     /*  140558 */   // GIR_Coverage, 15165,
     /*  140558 */   GIR_EraseRootFromParent_Done,
     /*  140559 */ // Label 1995: @140559
     /*  140559 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(140635), // Rule ID 15166 //
     /*  140564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  140567 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140570 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140574 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140581 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140592 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140596 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140603 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  140606 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140623 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140633 */   GIR_RootConstrainSelectedInstOperands,
     /*  140634 */   // GIR_Coverage, 15166,
     /*  140634 */   GIR_EraseRootFromParent_Done,
     /*  140635 */ // Label 1996: @140635
     /*  140635 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(140711), // Rule ID 15167 //
     /*  140640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  140643 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140646 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140650 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140657 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140664 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140668 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140672 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140679 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  140682 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140699 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140702 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140705 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140709 */   GIR_RootConstrainSelectedInstOperands,
     /*  140710 */   // GIR_Coverage, 15167,
     /*  140710 */   GIR_EraseRootFromParent_Done,
     /*  140711 */ // Label 1997: @140711
     /*  140711 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(140787), // Rule ID 15173 //
     /*  140716 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  140719 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140722 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140726 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140733 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140755 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  140758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140775 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140778 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140781 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140785 */   GIR_RootConstrainSelectedInstOperands,
     /*  140786 */   // GIR_Coverage, 15173,
     /*  140786 */   GIR_EraseRootFromParent_Done,
     /*  140787 */ // Label 1998: @140787
     /*  140787 */ GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(140863), // Rule ID 15174 //
     /*  140792 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  140795 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140798 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140802 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140820 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140824 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140831 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  140834 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140851 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140854 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140861 */   GIR_RootConstrainSelectedInstOperands,
     /*  140862 */   // GIR_Coverage, 15174,
     /*  140862 */   GIR_EraseRootFromParent_Done,
     /*  140863 */ // Label 1999: @140863
     /*  140863 */ GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(140939), // Rule ID 15175 //
     /*  140868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  140871 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140874 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140878 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140885 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140907 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  140910 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  140927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140930 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  140933 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  140937 */   GIR_RootConstrainSelectedInstOperands,
     /*  140938 */   // GIR_Coverage, 15175,
     /*  140938 */   GIR_EraseRootFromParent_Done,
     /*  140939 */ // Label 2000: @140939
     /*  140939 */ GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(141015), // Rule ID 15176 //
     /*  140944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  140947 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  140950 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  140954 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  140961 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  140968 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  140972 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  140976 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  140983 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  140983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  140986 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  140988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  140993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  140998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141009 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141013 */   GIR_RootConstrainSelectedInstOperands,
     /*  141014 */   // GIR_Coverage, 15176,
     /*  141014 */   GIR_EraseRootFromParent_Done,
     /*  141015 */ // Label 2001: @141015
     /*  141015 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(141091), // Rule ID 15177 //
     /*  141020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  141023 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  141026 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141030 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  141037 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141052 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141059 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  141059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  141062 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141079 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141082 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141085 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141089 */   GIR_RootConstrainSelectedInstOperands,
     /*  141090 */   // GIR_Coverage, 15177,
     /*  141090 */   GIR_EraseRootFromParent_Done,
     /*  141091 */ // Label 2002: @141091
     /*  141091 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(141166), // Rule ID 24901 //
     /*  141096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  141099 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141102 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141106 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141113 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141119 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141123 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141127 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141134 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141137 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141139 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141154 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141157 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141160 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141164 */   GIR_RootConstrainSelectedInstOperands,
     /*  141165 */   // GIR_Coverage, 24901,
     /*  141165 */   GIR_EraseRootFromParent_Done,
     /*  141166 */ // Label 2003: @141166
     /*  141166 */ GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(141241), // Rule ID 24902 //
     /*  141171 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  141174 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141177 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141181 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141188 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141209 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141229 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141239 */   GIR_RootConstrainSelectedInstOperands,
     /*  141240 */   // GIR_Coverage, 24902,
     /*  141240 */   GIR_EraseRootFromParent_Done,
     /*  141241 */ // Label 2004: @141241
     /*  141241 */ GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(141316), // Rule ID 24903 //
     /*  141246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  141249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141252 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141277 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141284 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141304 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141310 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141314 */   GIR_RootConstrainSelectedInstOperands,
     /*  141315 */   // GIR_Coverage, 24903,
     /*  141315 */   GIR_EraseRootFromParent_Done,
     /*  141316 */ // Label 2005: @141316
     /*  141316 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(141391), // Rule ID 24904 //
     /*  141321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  141324 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141327 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141331 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141338 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141359 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141362 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141379 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141382 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141385 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141389 */   GIR_RootConstrainSelectedInstOperands,
     /*  141390 */   // GIR_Coverage, 24904,
     /*  141390 */   GIR_EraseRootFromParent_Done,
     /*  141391 */ // Label 2006: @141391
     /*  141391 */ GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(141466), // Rule ID 24905 //
     /*  141396 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  141399 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141402 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141406 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141413 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141434 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141457 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141460 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141464 */   GIR_RootConstrainSelectedInstOperands,
     /*  141465 */   // GIR_Coverage, 24905,
     /*  141465 */   GIR_EraseRootFromParent_Done,
     /*  141466 */ // Label 2007: @141466
     /*  141466 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(141541), // Rule ID 24906 //
     /*  141471 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  141474 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141477 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141481 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141488 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141494 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141498 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141502 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141509 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141509 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  141512 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141532 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141535 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141539 */   GIR_RootConstrainSelectedInstOperands,
     /*  141540 */   // GIR_Coverage, 24906,
     /*  141540 */   GIR_EraseRootFromParent_Done,
     /*  141541 */ // Label 2008: @141541
     /*  141541 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(141616), // Rule ID 24907 //
     /*  141546 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  141549 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141552 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141556 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141563 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141577 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141584 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  141587 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141604 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141607 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141610 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141614 */   GIR_RootConstrainSelectedInstOperands,
     /*  141615 */   // GIR_Coverage, 24907,
     /*  141615 */   GIR_EraseRootFromParent_Done,
     /*  141616 */ // Label 2009: @141616
     /*  141616 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(141691), // Rule ID 24908 //
     /*  141621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  141624 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141627 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141631 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141638 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141659 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  141662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141679 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141682 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141689 */   GIR_RootConstrainSelectedInstOperands,
     /*  141690 */   // GIR_Coverage, 24908,
     /*  141690 */   GIR_EraseRootFromParent_Done,
     /*  141691 */ // Label 2010: @141691
     /*  141691 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(141766), // Rule ID 24909 //
     /*  141696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  141699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141702 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141706 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141723 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141727 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141734 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  141737 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141754 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141757 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141760 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141764 */   GIR_RootConstrainSelectedInstOperands,
     /*  141765 */   // GIR_Coverage, 24909,
     /*  141765 */   GIR_EraseRootFromParent_Done,
     /*  141766 */ // Label 2011: @141766
     /*  141766 */ GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(141841), // Rule ID 24910 //
     /*  141771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  141774 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141777 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141781 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141798 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141802 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141809 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141809 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  141812 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141839 */   GIR_RootConstrainSelectedInstOperands,
     /*  141840 */   // GIR_Coverage, 24910,
     /*  141840 */   GIR_EraseRootFromParent_Done,
     /*  141841 */ // Label 2012: @141841
     /*  141841 */ GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(141917), // Rule ID 24931 //
     /*  141846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  141849 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141852 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141856 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141885 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141888 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141905 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141908 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141911 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141915 */   GIR_RootConstrainSelectedInstOperands,
     /*  141916 */   // GIR_Coverage, 24931,
     /*  141916 */   GIR_EraseRootFromParent_Done,
     /*  141917 */ // Label 2013: @141917
     /*  141917 */ GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(141993), // Rule ID 24932 //
     /*  141922 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  141925 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  141928 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  141932 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  141939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  141946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  141950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  141954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  141961 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  141961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  141964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  141966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  141971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  141976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  141981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  141987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  141991 */   GIR_RootConstrainSelectedInstOperands,
     /*  141992 */   // GIR_Coverage, 24932,
     /*  141992 */   GIR_EraseRootFromParent_Done,
     /*  141993 */ // Label 2014: @141993
     /*  141993 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(142069), // Rule ID 24933 //
     /*  141998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  142001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142004 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142008 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142022 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142026 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142030 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142037 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142037 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  142040 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142057 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142063 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142067 */   GIR_RootConstrainSelectedInstOperands,
     /*  142068 */   // GIR_Coverage, 24933,
     /*  142068 */   GIR_EraseRootFromParent_Done,
     /*  142069 */ // Label 2015: @142069
     /*  142069 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(142145), // Rule ID 24934 //
     /*  142074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  142077 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142080 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142084 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142091 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142098 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142102 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142106 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142113 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  142116 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142133 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142139 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142143 */   GIR_RootConstrainSelectedInstOperands,
     /*  142144 */   // GIR_Coverage, 24934,
     /*  142144 */   GIR_EraseRootFromParent_Done,
     /*  142145 */ // Label 2016: @142145
     /*  142145 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(142221), // Rule ID 24935 //
     /*  142150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  142153 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142156 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142160 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142178 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142182 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142189 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142189 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  142192 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142215 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142219 */   GIR_RootConstrainSelectedInstOperands,
     /*  142220 */   // GIR_Coverage, 24935,
     /*  142220 */   GIR_EraseRootFromParent_Done,
     /*  142221 */ // Label 2017: @142221
     /*  142221 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(142297), // Rule ID 24936 //
     /*  142226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  142229 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142232 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142236 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142243 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142250 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142254 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142258 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142265 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142265 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  142268 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142285 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142288 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142291 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142295 */   GIR_RootConstrainSelectedInstOperands,
     /*  142296 */   // GIR_Coverage, 24936,
     /*  142296 */   GIR_EraseRootFromParent_Done,
     /*  142297 */ // Label 2018: @142297
     /*  142297 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(142373), // Rule ID 24937 //
     /*  142302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  142305 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142308 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142312 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142341 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  142344 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142361 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142364 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142367 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142371 */   GIR_RootConstrainSelectedInstOperands,
     /*  142372 */   // GIR_Coverage, 24937,
     /*  142372 */   GIR_EraseRootFromParent_Done,
     /*  142373 */ // Label 2019: @142373
     /*  142373 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(142449), // Rule ID 24938 //
     /*  142378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  142381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142384 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142388 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142406 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142410 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142417 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142417 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  142420 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142447 */   GIR_RootConstrainSelectedInstOperands,
     /*  142448 */   // GIR_Coverage, 24938,
     /*  142448 */   GIR_EraseRootFromParent_Done,
     /*  142449 */ // Label 2020: @142449
     /*  142449 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(142525), // Rule ID 24939 //
     /*  142454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  142457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142460 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142464 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142471 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142478 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142482 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142486 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142493 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142493 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  142496 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142513 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142516 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142519 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142523 */   GIR_RootConstrainSelectedInstOperands,
     /*  142524 */   // GIR_Coverage, 24939,
     /*  142524 */   GIR_EraseRootFromParent_Done,
     /*  142525 */ // Label 2021: @142525
     /*  142525 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(142601), // Rule ID 24940 //
     /*  142530 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  142533 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142536 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  142540 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  142547 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142554 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142558 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142562 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142569 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  142572 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142589 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142592 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142595 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142599 */   GIR_RootConstrainSelectedInstOperands,
     /*  142600 */   // GIR_Coverage, 24940,
     /*  142600 */   GIR_EraseRootFromParent_Done,
     /*  142601 */ // Label 2022: @142601
     /*  142601 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(142666), // Rule ID 24951 //
     /*  142606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  142609 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142612 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142634 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  142637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142654 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142657 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142660 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142664 */   GIR_RootConstrainSelectedInstOperands,
     /*  142665 */   // GIR_Coverage, 24951,
     /*  142665 */   GIR_EraseRootFromParent_Done,
     /*  142666 */ // Label 2023: @142666
     /*  142666 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(142731), // Rule ID 24952 //
     /*  142671 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  142674 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142677 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142684 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142688 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142692 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142699 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  142702 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142722 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142729 */   GIR_RootConstrainSelectedInstOperands,
     /*  142730 */   // GIR_Coverage, 24952,
     /*  142730 */   GIR_EraseRootFromParent_Done,
     /*  142731 */ // Label 2024: @142731
     /*  142731 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(142796), // Rule ID 24953 //
     /*  142736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  142739 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142742 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142749 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142753 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142757 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142764 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  142767 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142784 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142787 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142790 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142794 */   GIR_RootConstrainSelectedInstOperands,
     /*  142795 */   // GIR_Coverage, 24953,
     /*  142795 */   GIR_EraseRootFromParent_Done,
     /*  142796 */ // Label 2025: @142796
     /*  142796 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(142861), // Rule ID 24954 //
     /*  142801 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  142804 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142818 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142822 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142829 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  142832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142859 */   GIR_RootConstrainSelectedInstOperands,
     /*  142860 */   // GIR_Coverage, 24954,
     /*  142860 */   GIR_EraseRootFromParent_Done,
     /*  142861 */ // Label 2026: @142861
     /*  142861 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(142926), // Rule ID 24955 //
     /*  142866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  142869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142872 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142883 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142887 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142894 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142894 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  142897 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142917 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142920 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142924 */   GIR_RootConstrainSelectedInstOperands,
     /*  142925 */   // GIR_Coverage, 24955,
     /*  142925 */   GIR_EraseRootFromParent_Done,
     /*  142926 */ // Label 2027: @142926
     /*  142926 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(142991), // Rule ID 24956 //
     /*  142931 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  142934 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  142937 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  142944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  142948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  142952 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  142959 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  142959 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  142962 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  142964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  142969 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  142974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  142979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  142985 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  142989 */   GIR_RootConstrainSelectedInstOperands,
     /*  142990 */   // GIR_Coverage, 24956,
     /*  142990 */   GIR_EraseRootFromParent_Done,
     /*  142991 */ // Label 2028: @142991
     /*  142991 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(143056), // Rule ID 24957 //
     /*  142996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  142999 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143002 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  143009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  143024 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  143024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  143027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  143029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  143034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  143039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  143044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143047 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143050 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143054 */   GIR_RootConstrainSelectedInstOperands,
     /*  143055 */   // GIR_Coverage, 24957,
     /*  143055 */   GIR_EraseRootFromParent_Done,
     /*  143056 */ // Label 2029: @143056
     /*  143056 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(143121), // Rule ID 24958 //
     /*  143061 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  143064 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143067 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  143074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143082 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  143089 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  143089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  143092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  143094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  143099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  143104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  143109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143112 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143115 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143119 */   GIR_RootConstrainSelectedInstOperands,
     /*  143120 */   // GIR_Coverage, 24958,
     /*  143120 */   GIR_EraseRootFromParent_Done,
     /*  143121 */ // Label 2030: @143121
     /*  143121 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(143186), // Rule ID 24959 //
     /*  143126 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  143129 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143132 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  143139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143147 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  143154 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  143154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  143157 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  143159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  143164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  143169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  143174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143177 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143180 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143184 */   GIR_RootConstrainSelectedInstOperands,
     /*  143185 */   // GIR_Coverage, 24959,
     /*  143185 */   GIR_EraseRootFromParent_Done,
     /*  143186 */ // Label 2031: @143186
     /*  143186 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(143251), // Rule ID 24960 //
     /*  143191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  143194 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143197 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  143204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  143219 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  143219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  143222 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  143224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  143229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  143234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  143239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143242 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143245 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143249 */   GIR_RootConstrainSelectedInstOperands,
     /*  143250 */   // GIR_Coverage, 24960,
     /*  143250 */   GIR_EraseRootFromParent_Done,
     /*  143251 */ // Label 2032: @143251
     /*  143251 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(143317), // Rule ID 28849 //
     /*  143256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  143259 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143262 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143266 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143273 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143278 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143282 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143286 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143293 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  143296 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143308 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143311 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143315 */   GIR_RootConstrainSelectedInstOperands,
     /*  143316 */   // GIR_Coverage, 28849,
     /*  143316 */   GIR_EraseRootFromParent_Done,
     /*  143317 */ // Label 2033: @143317
     /*  143317 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(143383), // Rule ID 28850 //
     /*  143322 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  143325 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143328 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143332 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143339 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143359 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  143362 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143374 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143377 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143381 */   GIR_RootConstrainSelectedInstOperands,
     /*  143382 */   // GIR_Coverage, 28850,
     /*  143382 */   GIR_EraseRootFromParent_Done,
     /*  143383 */ // Label 2034: @143383
     /*  143383 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(143449), // Rule ID 28851 //
     /*  143388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  143391 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143394 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143398 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143405 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143410 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143414 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143418 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143425 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143425 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  143428 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143447 */   GIR_RootConstrainSelectedInstOperands,
     /*  143448 */   // GIR_Coverage, 28851,
     /*  143448 */   GIR_EraseRootFromParent_Done,
     /*  143449 */ // Label 2035: @143449
     /*  143449 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(143515), // Rule ID 28852 //
     /*  143454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  143457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143460 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143464 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143471 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143480 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143484 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143491 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  143494 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143506 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143509 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143513 */   GIR_RootConstrainSelectedInstOperands,
     /*  143514 */   // GIR_Coverage, 28852,
     /*  143514 */   GIR_EraseRootFromParent_Done,
     /*  143515 */ // Label 2036: @143515
     /*  143515 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(143581), // Rule ID 28853 //
     /*  143520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  143523 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143526 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143530 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143537 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143546 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143550 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143557 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143557 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  143560 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143572 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143575 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143579 */   GIR_RootConstrainSelectedInstOperands,
     /*  143580 */   // GIR_Coverage, 28853,
     /*  143580 */   GIR_EraseRootFromParent_Done,
     /*  143581 */ // Label 2037: @143581
     /*  143581 */ GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(143647), // Rule ID 28854 //
     /*  143586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  143589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143592 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143608 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143616 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143623 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  143626 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143641 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143645 */   GIR_RootConstrainSelectedInstOperands,
     /*  143646 */   // GIR_Coverage, 28854,
     /*  143646 */   GIR_EraseRootFromParent_Done,
     /*  143647 */ // Label 2038: @143647
     /*  143647 */ GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(143713), // Rule ID 28855 //
     /*  143652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  143655 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143658 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143662 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143669 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143674 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143678 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143682 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143689 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143689 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  143692 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143704 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143707 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143711 */   GIR_RootConstrainSelectedInstOperands,
     /*  143712 */   // GIR_Coverage, 28855,
     /*  143712 */   GIR_EraseRootFromParent_Done,
     /*  143713 */ // Label 2039: @143713
     /*  143713 */ GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(143779), // Rule ID 28856 //
     /*  143718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  143721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143724 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143728 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143755 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  143758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143770 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143773 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143777 */   GIR_RootConstrainSelectedInstOperands,
     /*  143778 */   // GIR_Coverage, 28856,
     /*  143778 */   GIR_EraseRootFromParent_Done,
     /*  143779 */ // Label 2040: @143779
     /*  143779 */ GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(143845), // Rule ID 28857 //
     /*  143784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  143787 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143790 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143794 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143801 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143821 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  143824 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143843 */   GIR_RootConstrainSelectedInstOperands,
     /*  143844 */   // GIR_Coverage, 28857,
     /*  143844 */   GIR_EraseRootFromParent_Done,
     /*  143845 */ // Label 2041: @143845
     /*  143845 */ GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(143911), // Rule ID 28858 //
     /*  143850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  143853 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143856 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143860 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143867 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  143876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143887 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  143890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143902 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143905 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143909 */   GIR_RootConstrainSelectedInstOperands,
     /*  143910 */   // GIR_Coverage, 28858,
     /*  143910 */   GIR_EraseRootFromParent_Done,
     /*  143911 */ // Label 2042: @143911
     /*  143911 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(143977), // Rule ID 28859 //
     /*  143916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  143919 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143922 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143926 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  143938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  143942 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  143946 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  143953 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  143953 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_t16),
     /*  143956 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  143958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  143963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  143968 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  143971 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  143975 */   GIR_RootConstrainSelectedInstOperands,
     /*  143976 */   // GIR_Coverage, 28859,
     /*  143976 */   GIR_EraseRootFromParent_Done,
     /*  143977 */ // Label 2043: @143977
     /*  143977 */ GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(144073), // Rule ID 28860 //
     /*  143982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  143985 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  143988 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  143992 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  143999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144004 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144008 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144012 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144019 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  144019 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  144022 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144026 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  144031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144041 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  144044 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144048 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  144050 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  144053 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  144055 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  144062 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144067 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144072 */   // GIR_Coverage, 28860,
     /*  144072 */   GIR_EraseRootFromParent_Done,
     /*  144073 */ // Label 2044: @144073
     /*  144073 */ GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(144169), // Rule ID 28861 //
     /*  144078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  144081 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  144084 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144088 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144095 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144100 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144104 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144108 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144115 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  144115 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  144118 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144122 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  144127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144137 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  144140 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144144 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  144146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  144149 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  144151 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  144158 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144163 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144168 */   // GIR_Coverage, 28861,
     /*  144168 */   GIR_EraseRootFromParent_Done,
     /*  144169 */ // Label 2045: @144169
     /*  144169 */ GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(144265), // Rule ID 28862 //
     /*  144174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  144177 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  144180 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144184 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144191 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144196 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144200 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144204 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144211 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  144211 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  144214 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144218 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  144223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144233 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  144236 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144240 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  144242 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  144245 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  144247 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  144254 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144259 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144264 */   // GIR_Coverage, 28862,
     /*  144264 */   GIR_EraseRootFromParent_Done,
     /*  144265 */ // Label 2046: @144265
     /*  144265 */ GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(144361), // Rule ID 28863 //
     /*  144270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  144273 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  144276 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144280 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144287 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144292 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144296 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144300 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144307 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  144307 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  144310 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144314 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  144319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144329 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  144332 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144336 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  144338 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  144341 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  144343 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  144350 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144355 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144360 */   // GIR_Coverage, 28863,
     /*  144360 */   GIR_EraseRootFromParent_Done,
     /*  144361 */ // Label 2047: @144361
     /*  144361 */ GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(144457), // Rule ID 28864 //
     /*  144366 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  144369 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  144372 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144403 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  144403 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  144406 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144410 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  144415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144425 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  144428 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144432 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  144434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  144437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  144439 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  144446 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  144451 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144456 */   // GIR_Coverage, 28864,
     /*  144456 */   GIR_EraseRootFromParent_Done,
     /*  144457 */ // Label 2048: @144457
     /*  144457 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(144523), // Rule ID 28977 //
     /*  144462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  144465 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144468 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144472 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144488 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144492 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144499 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  144502 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144514 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144517 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144521 */   GIR_RootConstrainSelectedInstOperands,
     /*  144522 */   // GIR_Coverage, 28977,
     /*  144522 */   GIR_EraseRootFromParent_Done,
     /*  144523 */ // Label 2049: @144523
     /*  144523 */ GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(144589), // Rule ID 28978 //
     /*  144528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  144531 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144534 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144538 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144545 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144550 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144554 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144558 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144565 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  144568 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144580 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144583 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144587 */   GIR_RootConstrainSelectedInstOperands,
     /*  144588 */   // GIR_Coverage, 28978,
     /*  144588 */   GIR_EraseRootFromParent_Done,
     /*  144589 */ // Label 2050: @144589
     /*  144589 */ GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(144655), // Rule ID 28979 //
     /*  144594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  144597 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144600 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144604 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144611 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144620 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144624 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144631 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  144634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144653 */   GIR_RootConstrainSelectedInstOperands,
     /*  144654 */   // GIR_Coverage, 28979,
     /*  144654 */   GIR_EraseRootFromParent_Done,
     /*  144655 */ // Label 2051: @144655
     /*  144655 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(144721), // Rule ID 28980 //
     /*  144660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  144663 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144666 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144670 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144677 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144686 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144697 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  144700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144715 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144719 */   GIR_RootConstrainSelectedInstOperands,
     /*  144720 */   // GIR_Coverage, 28980,
     /*  144720 */   GIR_EraseRootFromParent_Done,
     /*  144721 */ // Label 2052: @144721
     /*  144721 */ GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(144787), // Rule ID 28981 //
     /*  144726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  144729 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144732 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144736 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144752 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144756 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144763 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  144766 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144778 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144781 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144785 */   GIR_RootConstrainSelectedInstOperands,
     /*  144786 */   // GIR_Coverage, 28981,
     /*  144786 */   GIR_EraseRootFromParent_Done,
     /*  144787 */ // Label 2053: @144787
     /*  144787 */ GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(144853), // Rule ID 28982 //
     /*  144792 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  144795 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144798 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144802 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144818 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144822 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144829 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144844 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144851 */   GIR_RootConstrainSelectedInstOperands,
     /*  144852 */   // GIR_Coverage, 28982,
     /*  144852 */   GIR_EraseRootFromParent_Done,
     /*  144853 */ // Label 2054: @144853
     /*  144853 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(144919), // Rule ID 28983 //
     /*  144858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  144861 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144864 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144868 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144875 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144880 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144884 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144888 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144895 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144895 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144898 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144910 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144913 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144917 */   GIR_RootConstrainSelectedInstOperands,
     /*  144918 */   // GIR_Coverage, 28983,
     /*  144918 */   GIR_EraseRootFromParent_Done,
     /*  144919 */ // Label 2055: @144919
     /*  144919 */ GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(144985), // Rule ID 28984 //
     /*  144924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  144927 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144930 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  144934 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  144941 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  144946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  144950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  144954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  144961 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  144961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  144964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  144966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  144971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  144976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  144979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  144983 */   GIR_RootConstrainSelectedInstOperands,
     /*  144984 */   // GIR_Coverage, 28984,
     /*  144984 */   GIR_EraseRootFromParent_Done,
     /*  144985 */ // Label 2056: @144985
     /*  144985 */ GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(145051), // Rule ID 28985 //
     /*  144990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  144993 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  144996 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145000 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145012 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145020 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145027 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145030 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145042 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145045 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145049 */   GIR_RootConstrainSelectedInstOperands,
     /*  145050 */   // GIR_Coverage, 28985,
     /*  145050 */   GIR_EraseRootFromParent_Done,
     /*  145051 */ // Label 2057: @145051
     /*  145051 */ GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(145117), // Rule ID 28986 //
     /*  145056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  145059 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145062 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145066 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145082 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145093 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145111 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145115 */   GIR_RootConstrainSelectedInstOperands,
     /*  145116 */   // GIR_Coverage, 28986,
     /*  145116 */   GIR_EraseRootFromParent_Done,
     /*  145117 */ // Label 2058: @145117
     /*  145117 */ GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(145183), // Rule ID 28987 //
     /*  145122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  145125 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145128 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145132 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145139 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145159 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_t16),
     /*  145162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145181 */   GIR_RootConstrainSelectedInstOperands,
     /*  145182 */   // GIR_Coverage, 28987,
     /*  145182 */   GIR_EraseRootFromParent_Done,
     /*  145183 */ // Label 2059: @145183
     /*  145183 */ GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(145279), // Rule ID 28988 //
     /*  145188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  145191 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145194 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145198 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145205 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145214 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145218 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145225 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  145225 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  145228 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145232 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  145237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145247 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  145250 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145254 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  145256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  145259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  145261 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  145268 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145273 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145278 */   // GIR_Coverage, 28988,
     /*  145278 */   GIR_EraseRootFromParent_Done,
     /*  145279 */ // Label 2060: @145279
     /*  145279 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(145375), // Rule ID 28989 //
     /*  145284 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  145287 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145290 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145294 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145301 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145321 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  145321 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  145324 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145328 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  145333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145343 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  145346 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145350 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  145352 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  145355 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  145357 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  145364 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145369 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145374 */   // GIR_Coverage, 28989,
     /*  145374 */   GIR_EraseRootFromParent_Done,
     /*  145375 */ // Label 2061: @145375
     /*  145375 */ GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(145471), // Rule ID 28990 //
     /*  145380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  145383 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145386 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145390 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145397 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145406 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145410 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145417 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  145417 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  145420 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145424 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  145429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145439 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  145442 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145446 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  145448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  145451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  145453 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  145460 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145465 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145470 */   // GIR_Coverage, 28990,
     /*  145470 */   GIR_EraseRootFromParent_Done,
     /*  145471 */ // Label 2062: @145471
     /*  145471 */ GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(145567), // Rule ID 28991 //
     /*  145476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  145479 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145482 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145486 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145493 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145502 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145506 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145513 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  145513 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  145516 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145520 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  145525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145535 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  145538 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145542 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  145544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  145547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  145549 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  145556 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145561 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145566 */   // GIR_Coverage, 28991,
     /*  145566 */   GIR_EraseRootFromParent_Done,
     /*  145567 */ // Label 2063: @145567
     /*  145567 */ GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(145663), // Rule ID 28992 //
     /*  145572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  145575 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145578 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145582 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  145589 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145609 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  145609 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  145612 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  145616 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  145621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145631 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  145634 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145638 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  145640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  145643 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  145645 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  145652 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  145657 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145662 */   // GIR_Coverage, 28992,
     /*  145662 */   GIR_EraseRootFromParent_Done,
     /*  145663 */ // Label 2064: @145663
     /*  145663 */ GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(145729), // Rule ID 29055 //
     /*  145668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  145671 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145674 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145678 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  145685 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145705 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_16_glue>><<P:Predicate_atomic_load_nonext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  145708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145723 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145727 */   GIR_RootConstrainSelectedInstOperands,
     /*  145728 */   // GIR_Coverage, 29055,
     /*  145728 */   GIR_EraseRootFromParent_Done,
     /*  145729 */ // Label 2065: @145729
     /*  145729 */ GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(145795), // Rule ID 29056 //
     /*  145734 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  145737 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145740 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145744 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  145751 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145756 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145760 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145764 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145771 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_16_glue>><<P:Predicate_atomic_load_nonext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145771 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  145774 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145786 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145789 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145793 */   GIR_RootConstrainSelectedInstOperands,
     /*  145794 */   // GIR_Coverage, 29056,
     /*  145794 */   GIR_EraseRootFromParent_Done,
     /*  145795 */ // Label 2066: @145795
     /*  145795 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(145861), // Rule ID 29057 //
     /*  145800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  145803 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145806 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145810 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  145817 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145826 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145830 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145837 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_16_glue>><<P:Predicate_atomic_load_nonext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  145840 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145859 */   GIR_RootConstrainSelectedInstOperands,
     /*  145860 */   // GIR_Coverage, 29057,
     /*  145860 */   GIR_EraseRootFromParent_Done,
     /*  145861 */ // Label 2067: @145861
     /*  145861 */ GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(145927), // Rule ID 29058 //
     /*  145866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  145869 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145872 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145876 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  145883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145892 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145896 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145903 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_16_glue>><<P:Predicate_atomic_load_nonext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  145906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145918 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145925 */   GIR_RootConstrainSelectedInstOperands,
     /*  145926 */   // GIR_Coverage, 29058,
     /*  145926 */   GIR_EraseRootFromParent_Done,
     /*  145927 */ // Label 2068: @145927
     /*  145927 */ GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(145993), // Rule ID 29059 //
     /*  145932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  145935 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  145938 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  145942 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  145949 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  145954 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  145958 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  145962 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  145969 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_16_glue>><<P:Predicate_atomic_load_nonext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  145969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  145972 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  145974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  145979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  145984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  145987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  145991 */   GIR_RootConstrainSelectedInstOperands,
     /*  145992 */   // GIR_Coverage, 29059,
     /*  145992 */   GIR_EraseRootFromParent_Done,
     /*  145993 */ // Label 2069: @145993
     /*  145993 */ GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(146059), // Rule ID 29060 //
     /*  145998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  146001 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146004 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146008 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146024 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146028 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146035 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146035 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146038 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146050 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146053 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146057 */   GIR_RootConstrainSelectedInstOperands,
     /*  146058 */   // GIR_Coverage, 29060,
     /*  146058 */   GIR_EraseRootFromParent_Done,
     /*  146059 */ // Label 2070: @146059
     /*  146059 */ GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(146125), // Rule ID 29061 //
     /*  146064 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  146067 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146070 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146074 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146081 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146101 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146123 */   GIR_RootConstrainSelectedInstOperands,
     /*  146124 */   // GIR_Coverage, 29061,
     /*  146124 */   GIR_EraseRootFromParent_Done,
     /*  146125 */ // Label 2071: @146125
     /*  146125 */ GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(146191), // Rule ID 29062 //
     /*  146130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  146133 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146136 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146140 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146152 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146167 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146170 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146182 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146185 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146189 */   GIR_RootConstrainSelectedInstOperands,
     /*  146190 */   // GIR_Coverage, 29062,
     /*  146190 */   GIR_EraseRootFromParent_Done,
     /*  146191 */ // Label 2072: @146191
     /*  146191 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(146257), // Rule ID 29063 //
     /*  146196 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  146199 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146202 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146218 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146222 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146226 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146233 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146236 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146248 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146251 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146255 */   GIR_RootConstrainSelectedInstOperands,
     /*  146256 */   // GIR_Coverage, 29063,
     /*  146256 */   GIR_EraseRootFromParent_Done,
     /*  146257 */ // Label 2073: @146257
     /*  146257 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(146323), // Rule ID 29064 //
     /*  146262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  146265 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146268 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146272 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146288 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146292 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146299 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146299 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146302 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146309 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146314 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146317 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146321 */   GIR_RootConstrainSelectedInstOperands,
     /*  146322 */   // GIR_Coverage, 29064,
     /*  146322 */   GIR_EraseRootFromParent_Done,
     /*  146323 */ // Label 2074: @146323
     /*  146323 */ GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(146389), // Rule ID 29065 //
     /*  146328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  146331 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146334 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146338 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146345 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146350 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146354 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146358 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146365 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (DS_READ_U16_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_t16),
     /*  146368 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146380 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146383 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146387 */   GIR_RootConstrainSelectedInstOperands,
     /*  146388 */   // GIR_Coverage, 29065,
     /*  146388 */   GIR_EraseRootFromParent_Done,
     /*  146389 */ // Label 2075: @146389
     /*  146389 */ GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(146485), // Rule ID 29066 //
     /*  146394 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  146397 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146400 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146404 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146411 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146420 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146424 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146431 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  146431 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  146434 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146438 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  146443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146453 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  146456 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146460 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  146462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  146465 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  146467 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  146474 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146479 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146484 */   // GIR_Coverage, 29066,
     /*  146484 */   GIR_EraseRootFromParent_Done,
     /*  146485 */ // Label 2076: @146485
     /*  146485 */ GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(146581), // Rule ID 29067 //
     /*  146490 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  146493 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146496 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146500 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146516 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146520 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146527 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  146527 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  146530 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146534 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  146539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146549 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  146552 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146556 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  146558 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  146561 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  146563 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  146570 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146575 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146580 */   // GIR_Coverage, 29067,
     /*  146580 */   GIR_EraseRootFromParent_Done,
     /*  146581 */ // Label 2077: @146581
     /*  146581 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(146677), // Rule ID 29068 //
     /*  146586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  146589 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146592 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146608 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146616 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146623 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  146623 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  146626 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146630 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  146635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146645 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  146648 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146652 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  146654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  146657 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  146659 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  146666 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146671 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146676 */   // GIR_Coverage, 29068,
     /*  146676 */   GIR_EraseRootFromParent_Done,
     /*  146677 */ // Label 2078: @146677
     /*  146677 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(146773), // Rule ID 29069 //
     /*  146682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  146685 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146688 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146692 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146699 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146719 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  146719 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  146722 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146726 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  146731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146741 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  146744 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146748 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  146750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  146753 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  146755 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  146762 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146767 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146772 */   // GIR_Coverage, 29069,
     /*  146772 */   GIR_EraseRootFromParent_Done,
     /*  146773 */ // Label 2079: @146773
     /*  146773 */ GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(146869), // Rule ID 29070 //
     /*  146778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  146781 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  146784 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146788 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  146795 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146808 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146815 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  146815 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  146818 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  146822 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  146827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146837 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  146840 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146844 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  146846 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  146849 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  146851 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  146858 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  146863 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146868 */   // GIR_Coverage, 29070,
     /*  146868 */   GIR_EraseRootFromParent_Done,
     /*  146869 */ // Label 2080: @146869
     /*  146869 */ GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(146928), // Rule ID 28881 //
     /*  146874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  146877 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  146880 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146884 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146897 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146904 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  146907 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146922 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146926 */   GIR_RootConstrainSelectedInstOperands,
     /*  146927 */   // GIR_Coverage, 28881,
     /*  146927 */   GIR_EraseRootFromParent_Done,
     /*  146928 */ // Label 2081: @146928
     /*  146928 */ GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(146987), // Rule ID 28882 //
     /*  146933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  146936 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  146939 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  146943 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  146948 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  146952 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  146956 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  146963 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  146963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  146966 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  146968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  146973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  146978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  146981 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  146985 */   GIR_RootConstrainSelectedInstOperands,
     /*  146986 */   // GIR_Coverage, 28882,
     /*  146986 */   GIR_EraseRootFromParent_Done,
     /*  146987 */ // Label 2082: @146987
     /*  146987 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(147046), // Rule ID 28883 //
     /*  146992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  146995 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  146998 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  147002 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147011 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147015 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147022 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147022 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  147025 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147040 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147044 */   GIR_RootConstrainSelectedInstOperands,
     /*  147045 */   // GIR_Coverage, 28883,
     /*  147045 */   GIR_EraseRootFromParent_Done,
     /*  147046 */ // Label 2083: @147046
     /*  147046 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(147105), // Rule ID 28884 //
     /*  147051 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  147054 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147057 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  147061 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147081 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  147084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147096 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147099 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147103 */   GIR_RootConstrainSelectedInstOperands,
     /*  147104 */   // GIR_Coverage, 28884,
     /*  147104 */   GIR_EraseRootFromParent_Done,
     /*  147105 */ // Label 2084: @147105
     /*  147105 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(147164), // Rule ID 28885 //
     /*  147110 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  147113 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147116 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  147120 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147140 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  147143 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147155 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147162 */   GIR_RootConstrainSelectedInstOperands,
     /*  147163 */   // GIR_Coverage, 28885,
     /*  147163 */   GIR_EraseRootFromParent_Done,
     /*  147164 */ // Label 2085: @147164
     /*  147164 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(147219), // Rule ID 28886 //
     /*  147169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  147172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147175 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147184 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147188 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147195 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147205 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147217 */   GIR_RootConstrainSelectedInstOperands,
     /*  147218 */   // GIR_Coverage, 28886,
     /*  147218 */   GIR_EraseRootFromParent_Done,
     /*  147219 */ // Label 2086: @147219
     /*  147219 */ GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(147274), // Rule ID 28887 //
     /*  147224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  147227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147230 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147235 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147239 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147243 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147250 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147250 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147253 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147265 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147268 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147272 */   GIR_RootConstrainSelectedInstOperands,
     /*  147273 */   // GIR_Coverage, 28887,
     /*  147273 */   GIR_EraseRootFromParent_Done,
     /*  147274 */ // Label 2087: @147274
     /*  147274 */ GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(147329), // Rule ID 28888 //
     /*  147279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  147282 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147285 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147305 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147323 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147327 */   GIR_RootConstrainSelectedInstOperands,
     /*  147328 */   // GIR_Coverage, 28888,
     /*  147328 */   GIR_EraseRootFromParent_Done,
     /*  147329 */ // Label 2088: @147329
     /*  147329 */ GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(147384), // Rule ID 28889 //
     /*  147334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  147337 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147340 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147349 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147353 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147360 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147382 */   GIR_RootConstrainSelectedInstOperands,
     /*  147383 */   // GIR_Coverage, 28889,
     /*  147383 */   GIR_EraseRootFromParent_Done,
     /*  147384 */ // Label 2089: @147384
     /*  147384 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(147439), // Rule ID 28890 //
     /*  147389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  147392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147415 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147418 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147430 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147433 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147437 */   GIR_RootConstrainSelectedInstOperands,
     /*  147438 */   // GIR_Coverage, 28890,
     /*  147438 */   GIR_EraseRootFromParent_Done,
     /*  147439 */ // Label 2090: @147439
     /*  147439 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(147494), // Rule ID 28891 //
     /*  147444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  147447 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147455 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147459 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147463 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147470 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  147470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_t16),
     /*  147473 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147485 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  147488 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147492 */   GIR_RootConstrainSelectedInstOperands,
     /*  147493 */   // GIR_Coverage, 28891,
     /*  147493 */   GIR_EraseRootFromParent_Done,
     /*  147494 */ // Label 2091: @147494
     /*  147494 */ GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(147579), // Rule ID 28892 //
     /*  147499 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  147502 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147505 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147525 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  147525 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  147528 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147532 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  147537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147547 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  147550 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147554 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  147556 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  147559 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  147561 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  147568 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147573 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147578 */   // GIR_Coverage, 28892,
     /*  147578 */   GIR_EraseRootFromParent_Done,
     /*  147579 */ // Label 2092: @147579
     /*  147579 */ GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(147664), // Rule ID 28893 //
     /*  147584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  147587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147590 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147595 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147599 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147603 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147610 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  147610 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  147613 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147617 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  147622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147632 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  147635 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147639 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  147641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  147644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  147646 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  147653 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147658 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147663 */   // GIR_Coverage, 28893,
     /*  147663 */   GIR_EraseRootFromParent_Done,
     /*  147664 */ // Label 2093: @147664
     /*  147664 */ GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(147749), // Rule ID 28894 //
     /*  147669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  147672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147675 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147695 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  147695 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  147698 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147702 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  147707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147717 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  147720 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147724 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  147726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  147729 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  147731 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  147738 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147743 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147748 */   // GIR_Coverage, 28894,
     /*  147748 */   GIR_EraseRootFromParent_Done,
     /*  147749 */ // Label 2094: @147749
     /*  147749 */ GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(147834), // Rule ID 28895 //
     /*  147754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  147757 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147760 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147769 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147773 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147780 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  147780 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  147783 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147787 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  147792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147802 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  147805 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147809 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  147811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  147814 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  147816 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  147823 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147828 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147833 */   // GIR_Coverage, 28895,
     /*  147833 */   GIR_EraseRootFromParent_Done,
     /*  147834 */ // Label 2095: @147834
     /*  147834 */ GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(147919), // Rule ID 28896 //
     /*  147839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  147842 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147845 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  147850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147854 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147858 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  147865 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  147865 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  147868 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  147872 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  147877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  147882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  147887 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  147890 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147894 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  147896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  147899 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  147901 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  147908 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147913 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  147918 */   // GIR_Coverage, 28896,
     /*  147918 */   GIR_EraseRootFromParent_Done,
     /*  147919 */ // Label 2096: @147919
     /*  147919 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(147994), // Rule ID 9365 //
     /*  147924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  147927 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  147930 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  147934 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  147941 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  147948 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  147952 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  147956 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  147963 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  147963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_t16),
     /*  147966 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  147968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  147973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  147978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  147983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  147988 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  147992 */   GIR_RootConstrainSelectedInstOperands,
     /*  147993 */   // GIR_Coverage, 9365,
     /*  147993 */   GIR_EraseRootFromParent_Done,
     /*  147994 */ // Label 2097: @147994
     /*  147994 */ GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(148099), // Rule ID 9371 //
     /*  147999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  148002 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148005 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148009 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148016 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148027 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148031 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148038 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  148038 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  148041 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148045 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  148050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148070 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148074 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  148076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  148079 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  148081 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  148088 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148093 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148098 */   // GIR_Coverage, 9371,
     /*  148098 */   GIR_EraseRootFromParent_Done,
     /*  148099 */ // Label 2098: @148099
     /*  148099 */ GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(148204), // Rule ID 9372 //
     /*  148104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  148107 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148110 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148114 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148121 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148136 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148143 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  148143 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  148146 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148150 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  148155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148175 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148179 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  148181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  148184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  148186 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  148193 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148198 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148203 */   // GIR_Coverage, 9372,
     /*  148203 */   GIR_EraseRootFromParent_Done,
     /*  148204 */ // Label 2099: @148204
     /*  148204 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(148309), // Rule ID 9373 //
     /*  148209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  148212 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148215 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148219 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148237 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148241 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148248 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  148248 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  148251 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148255 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  148260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148280 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148284 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  148286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  148289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  148291 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  148298 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148303 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148308 */   // GIR_Coverage, 9373,
     /*  148308 */   GIR_EraseRootFromParent_Done,
     /*  148309 */ // Label 2100: @148309
     /*  148309 */ GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(148414), // Rule ID 9374 //
     /*  148314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  148317 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148320 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148324 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148331 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148353 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  148353 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  148356 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148360 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  148365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148385 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148389 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  148391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  148394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  148396 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  148403 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148408 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148413 */   // GIR_Coverage, 9374,
     /*  148413 */   GIR_EraseRootFromParent_Done,
     /*  148414 */ // Label 2101: @148414
     /*  148414 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(148519), // Rule ID 9375 //
     /*  148419 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  148422 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148425 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148429 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148436 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148443 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148447 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148451 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148458 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  148458 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  148461 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148465 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  148470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148490 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148494 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  148496 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  148499 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  148501 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  148508 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  148513 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148518 */   // GIR_Coverage, 9375,
     /*  148518 */   GIR_EraseRootFromParent_Done,
     /*  148519 */ // Label 2102: @148519
     /*  148519 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(148594), // Rule ID 11837 //
     /*  148524 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  148527 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148530 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148534 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148541 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148548 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148552 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148556 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148563 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  148563 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148566 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  148568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148588 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148592 */   GIR_RootConstrainSelectedInstOperands,
     /*  148593 */   // GIR_Coverage, 11837,
     /*  148593 */   GIR_EraseRootFromParent_Done,
     /*  148594 */ // Label 2103: @148594
     /*  148594 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(148669), // Rule ID 11838 //
     /*  148599 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  148602 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148605 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148609 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148616 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148627 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148631 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148638 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  148638 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148641 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  148643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148667 */   GIR_RootConstrainSelectedInstOperands,
     /*  148668 */   // GIR_Coverage, 11838,
     /*  148668 */   GIR_EraseRootFromParent_Done,
     /*  148669 */ // Label 2104: @148669
     /*  148669 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(148744), // Rule ID 11839 //
     /*  148674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  148677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148680 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148684 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148691 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148713 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  148713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  148718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148738 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148742 */   GIR_RootConstrainSelectedInstOperands,
     /*  148743 */   // GIR_Coverage, 11839,
     /*  148743 */   GIR_EraseRootFromParent_Done,
     /*  148744 */ // Label 2105: @148744
     /*  148744 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(148819), // Rule ID 11840 //
     /*  148749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  148752 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148755 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148759 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148766 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148777 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148781 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148788 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  148788 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148791 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  148793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148813 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148817 */   GIR_RootConstrainSelectedInstOperands,
     /*  148818 */   // GIR_Coverage, 11840,
     /*  148818 */   GIR_EraseRootFromParent_Done,
     /*  148819 */ // Label 2106: @148819
     /*  148819 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(148894), // Rule ID 11841 //
     /*  148824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  148827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  148830 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148834 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148841 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148848 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148852 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148856 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148863 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  148863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148866 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  148868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148888 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148892 */   GIR_RootConstrainSelectedInstOperands,
     /*  148893 */   // GIR_Coverage, 11841,
     /*  148893 */   GIR_EraseRootFromParent_Done,
     /*  148894 */ // Label 2107: @148894
     /*  148894 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(148969), // Rule ID 11897 //
     /*  148899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  148902 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  148905 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148909 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148916 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148923 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  148927 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  148931 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  148938 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  148938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  148941 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  148943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  148948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  148953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  148958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  148963 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  148967 */   GIR_RootConstrainSelectedInstOperands,
     /*  148968 */   // GIR_Coverage, 11897,
     /*  148968 */   GIR_EraseRootFromParent_Done,
     /*  148969 */ // Label 2108: @148969
     /*  148969 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(149044), // Rule ID 11898 //
     /*  148974 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  148977 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  148980 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  148984 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  148991 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  148998 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149002 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149006 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149013 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149016 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149038 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149042 */   GIR_RootConstrainSelectedInstOperands,
     /*  149043 */   // GIR_Coverage, 11898,
     /*  149043 */   GIR_EraseRootFromParent_Done,
     /*  149044 */ // Label 2109: @149044
     /*  149044 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(149119), // Rule ID 11899 //
     /*  149049 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  149052 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149055 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149059 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149066 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149077 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149088 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149091 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149117 */   GIR_RootConstrainSelectedInstOperands,
     /*  149118 */   // GIR_Coverage, 11899,
     /*  149118 */   GIR_EraseRootFromParent_Done,
     /*  149119 */ // Label 2110: @149119
     /*  149119 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(149194), // Rule ID 11900 //
     /*  149124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  149127 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149130 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149134 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149141 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149152 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149156 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149163 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149166 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149192 */   GIR_RootConstrainSelectedInstOperands,
     /*  149193 */   // GIR_Coverage, 11900,
     /*  149193 */   GIR_EraseRootFromParent_Done,
     /*  149194 */ // Label 2111: @149194
     /*  149194 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(149269), // Rule ID 11901 //
     /*  149199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  149202 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149205 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149223 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149227 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149231 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149238 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149241 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149263 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149267 */   GIR_RootConstrainSelectedInstOperands,
     /*  149268 */   // GIR_Coverage, 11901,
     /*  149268 */   GIR_EraseRootFromParent_Done,
     /*  149269 */ // Label 2112: @149269
     /*  149269 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(149344), // Rule ID 11927 //
     /*  149274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  149277 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149280 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149284 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  149291 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149313 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  149316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149338 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149342 */   GIR_RootConstrainSelectedInstOperands,
     /*  149343 */   // GIR_Coverage, 11927,
     /*  149343 */   GIR_EraseRootFromParent_Done,
     /*  149344 */ // Label 2113: @149344
     /*  149344 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(149419), // Rule ID 11928 //
     /*  149349 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  149352 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149355 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149359 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  149366 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149377 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149388 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  149391 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149413 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149417 */   GIR_RootConstrainSelectedInstOperands,
     /*  149418 */   // GIR_Coverage, 11928,
     /*  149418 */   GIR_EraseRootFromParent_Done,
     /*  149419 */ // Label 2114: @149419
     /*  149419 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(149494), // Rule ID 11929 //
     /*  149424 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  149427 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149430 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149434 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  149441 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149448 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149452 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149456 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149463 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  149466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149488 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149492 */   GIR_RootConstrainSelectedInstOperands,
     /*  149493 */   // GIR_Coverage, 11929,
     /*  149493 */   GIR_EraseRootFromParent_Done,
     /*  149494 */ // Label 2115: @149494
     /*  149494 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(149569), // Rule ID 11930 //
     /*  149499 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  149502 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149505 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149509 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  149516 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149527 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149531 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149538 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149538 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  149541 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149563 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149567 */   GIR_RootConstrainSelectedInstOperands,
     /*  149568 */   // GIR_Coverage, 11930,
     /*  149568 */   GIR_EraseRootFromParent_Done,
     /*  149569 */ // Label 2116: @149569
     /*  149569 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(149644), // Rule ID 11931 //
     /*  149574 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  149577 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149580 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149584 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  149591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149613 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  149613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  149616 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  149618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149638 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149642 */   GIR_RootConstrainSelectedInstOperands,
     /*  149643 */   // GIR_Coverage, 11931,
     /*  149643 */   GIR_EraseRootFromParent_Done,
     /*  149644 */ // Label 2117: @149644
     /*  149644 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(149749), // Rule ID 11997 //
     /*  149649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  149652 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149655 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149659 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149666 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149677 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149681 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149688 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  149688 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  149691 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149695 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  149700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149720 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149724 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  149726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  149729 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  149731 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  149738 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149743 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149748 */   // GIR_Coverage, 11997,
     /*  149748 */   GIR_EraseRootFromParent_Done,
     /*  149749 */ // Label 2118: @149749
     /*  149749 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(149854), // Rule ID 11998 //
     /*  149754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  149757 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149760 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149764 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149771 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149782 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149786 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149793 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  149793 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  149796 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149800 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  149805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149825 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149829 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  149831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  149834 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  149836 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  149843 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149848 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149853 */   // GIR_Coverage, 11998,
     /*  149853 */   GIR_EraseRootFromParent_Done,
     /*  149854 */ // Label 2119: @149854
     /*  149854 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(149959), // Rule ID 11999 //
     /*  149859 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  149862 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149865 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149869 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  149898 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  149898 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  149901 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  149905 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  149910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  149915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  149920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  149925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  149930 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  149934 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  149936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  149939 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  149941 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  149948 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149953 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  149958 */   // GIR_Coverage, 11999,
     /*  149958 */   GIR_EraseRootFromParent_Done,
     /*  149959 */ // Label 2120: @149959
     /*  149959 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(150064), // Rule ID 12000 //
     /*  149964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  149967 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  149970 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  149974 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  149981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  149988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  149992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  149996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150003 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150003 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150006 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  150010 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150035 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150039 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150044 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150046 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150053 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150058 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150063 */   // GIR_Coverage, 12000,
     /*  150063 */   GIR_EraseRootFromParent_Done,
     /*  150064 */ // Label 2121: @150064
     /*  150064 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(150169), // Rule ID 12001 //
     /*  150069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  150072 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150075 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150079 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  150086 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150108 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150108 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150111 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  150115 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150140 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150144 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150149 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150151 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150158 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150163 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150168 */   // GIR_Coverage, 12001,
     /*  150168 */   GIR_EraseRootFromParent_Done,
     /*  150169 */ // Label 2122: @150169
     /*  150169 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(150274), // Rule ID 12027 //
     /*  150174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  150177 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150180 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150184 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  150191 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150213 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150213 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150216 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150220 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150245 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150249 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150251 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150254 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150256 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150263 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150268 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150273 */   // GIR_Coverage, 12027,
     /*  150273 */   GIR_EraseRootFromParent_Done,
     /*  150274 */ // Label 2123: @150274
     /*  150274 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(150379), // Rule ID 12028 //
     /*  150279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  150282 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150285 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150289 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  150296 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150307 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150311 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150318 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150318 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150321 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150325 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150350 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150354 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150356 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150359 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150361 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150368 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150373 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150378 */   // GIR_Coverage, 12028,
     /*  150378 */   GIR_EraseRootFromParent_Done,
     /*  150379 */ // Label 2124: @150379
     /*  150379 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(150484), // Rule ID 12029 //
     /*  150384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  150387 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150390 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150394 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  150401 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150412 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150416 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150423 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150423 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150426 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150430 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150455 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150459 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150464 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150466 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150473 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150478 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150483 */   // GIR_Coverage, 12029,
     /*  150483 */   GIR_EraseRootFromParent_Done,
     /*  150484 */ // Label 2125: @150484
     /*  150484 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(150589), // Rule ID 12030 //
     /*  150489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  150492 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150495 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150499 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  150506 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150521 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150528 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150528 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150531 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150535 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150560 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150564 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150569 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150571 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150578 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150583 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150588 */   // GIR_Coverage, 12030,
     /*  150588 */   GIR_EraseRootFromParent_Done,
     /*  150589 */ // Label 2126: @150589
     /*  150589 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(150694), // Rule ID 12031 //
     /*  150594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  150597 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150600 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150604 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  150611 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150622 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150626 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150633 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  150633 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  150636 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150640 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  150645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150665 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150669 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  150671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  150674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  150676 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  150683 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150688 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150693 */   // GIR_Coverage, 12031,
     /*  150693 */   GIR_EraseRootFromParent_Done,
     /*  150694 */ // Label 2127: @150694
     /*  150694 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(150769), // Rule ID 12065 //
     /*  150699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  150702 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150705 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150709 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  150716 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150727 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150731 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150738 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  150738 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_t16),
     /*  150741 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  150743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150763 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150767 */   GIR_RootConstrainSelectedInstOperands,
     /*  150768 */   // GIR_Coverage, 12065,
     /*  150768 */   GIR_EraseRootFromParent_Done,
     /*  150769 */ // Label 2128: @150769
     /*  150769 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(150844), // Rule ID 12083 //
     /*  150774 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  150777 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  150780 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  150784 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  150791 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150798 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  150802 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150806 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150813 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  150813 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_t16),
     /*  150816 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  150818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150838 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150842 */   GIR_RootConstrainSelectedInstOperands,
     /*  150843 */   // GIR_Coverage, 12083,
     /*  150843 */   GIR_EraseRootFromParent_Done,
     /*  150844 */ // Label 2129: @150844
     /*  150844 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(150908), // Rule ID 11887 //
     /*  150849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  150852 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  150855 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150866 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150870 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150877 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  150877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  150882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150902 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150906 */   GIR_RootConstrainSelectedInstOperands,
     /*  150907 */   // GIR_Coverage, 11887,
     /*  150907 */   GIR_EraseRootFromParent_Done,
     /*  150908 */ // Label 2130: @150908
     /*  150908 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(150972), // Rule ID 11888 //
     /*  150913 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  150916 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  150919 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150930 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  150941 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  150941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  150944 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  150946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  150951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  150956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  150961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  150966 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  150970 */   GIR_RootConstrainSelectedInstOperands,
     /*  150971 */   // GIR_Coverage, 11888,
     /*  150971 */   GIR_EraseRootFromParent_Done,
     /*  150972 */ // Label 2131: @150972
     /*  150972 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(151036), // Rule ID 11889 //
     /*  150977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  150980 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  150983 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  150990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  150994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  150998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151005 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  151005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151030 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151034 */   GIR_RootConstrainSelectedInstOperands,
     /*  151035 */   // GIR_Coverage, 11889,
     /*  151035 */   GIR_EraseRootFromParent_Done,
     /*  151036 */ // Label 2132: @151036
     /*  151036 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(151100), // Rule ID 11890 //
     /*  151041 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  151044 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151047 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151054 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151062 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151069 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  151069 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151072 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151094 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151098 */   GIR_RootConstrainSelectedInstOperands,
     /*  151099 */   // GIR_Coverage, 11890,
     /*  151099 */   GIR_EraseRootFromParent_Done,
     /*  151100 */ // Label 2133: @151100
     /*  151100 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(151164), // Rule ID 11891 //
     /*  151105 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  151108 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151111 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151122 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151126 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151133 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  151133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151136 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151162 */   GIR_RootConstrainSelectedInstOperands,
     /*  151163 */   // GIR_Coverage, 11891,
     /*  151163 */   GIR_EraseRootFromParent_Done,
     /*  151164 */ // Label 2134: @151164
     /*  151164 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(151258), // Rule ID 11987 //
     /*  151169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  151172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151175 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151186 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151190 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151197 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  151197 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  151200 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151204 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  151209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151229 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151233 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  151235 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  151238 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  151240 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  151247 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151252 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151257 */   // GIR_Coverage, 11987,
     /*  151257 */   GIR_EraseRootFromParent_Done,
     /*  151258 */ // Label 2135: @151258
     /*  151258 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(151352), // Rule ID 11988 //
     /*  151263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  151266 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151291 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  151291 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  151294 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151298 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  151303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151323 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151327 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  151329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  151332 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  151334 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  151341 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151346 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151351 */   // GIR_Coverage, 11988,
     /*  151351 */   GIR_EraseRootFromParent_Done,
     /*  151352 */ // Label 2136: @151352
     /*  151352 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(151446), // Rule ID 11989 //
     /*  151357 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  151360 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151374 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151378 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151385 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  151385 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  151388 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151392 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  151397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151417 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151421 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  151423 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  151426 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  151428 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  151435 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151440 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151445 */   // GIR_Coverage, 11989,
     /*  151445 */   GIR_EraseRootFromParent_Done,
     /*  151446 */ // Label 2137: @151446
     /*  151446 */ GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(151540), // Rule ID 11990 //
     /*  151451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  151454 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151457 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151464 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151468 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151472 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151479 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  151479 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  151482 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151486 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  151491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151511 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151515 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  151517 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  151520 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  151522 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  151529 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151534 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151539 */   // GIR_Coverage, 11990,
     /*  151539 */   GIR_EraseRootFromParent_Done,
     /*  151540 */ // Label 2138: @151540
     /*  151540 */ GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(151634), // Rule ID 11991 //
     /*  151545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  151548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151562 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151566 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151573 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  151573 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  151576 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  151580 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  151585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151605 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151609 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  151611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  151614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  151616 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  151623 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151628 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  151633 */   // GIR_Coverage, 11991,
     /*  151633 */   GIR_EraseRootFromParent_Done,
     /*  151634 */ // Label 2139: @151634
     /*  151634 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(151698), // Rule ID 12059 //
     /*  151639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  151642 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151645 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151652 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151656 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151660 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  151667 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_SHORT_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  151667 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_t16),
     /*  151670 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  151677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  151682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  151687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  151692 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151696 */   GIR_RootConstrainSelectedInstOperands,
     /*  151697 */   // GIR_Coverage, 12059,
     /*  151697 */   GIR_EraseRootFromParent_Done,
     /*  151698 */ // Label 2140: @151698
     /*  151698 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(151766), // Rule ID 9360 //
     /*  151703 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  151706 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151709 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  151713 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  151720 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151727 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151731 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151735 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  151742 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  151742 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  151745 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  151752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  151757 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  151760 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151764 */   GIR_RootConstrainSelectedInstOperands,
     /*  151765 */   // GIR_Coverage, 9360,
     /*  151765 */   GIR_EraseRootFromParent_Done,
     /*  151766 */ // Label 2141: @151766
     /*  151766 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(151834), // Rule ID 9361 //
     /*  151771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  151774 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151777 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  151781 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  151788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  151810 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  151810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  151813 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  151820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  151825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  151828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151832 */   GIR_RootConstrainSelectedInstOperands,
     /*  151833 */   // GIR_Coverage, 9361,
     /*  151833 */   GIR_EraseRootFromParent_Done,
     /*  151834 */ // Label 2142: @151834
     /*  151834 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(151902), // Rule ID 9362 //
     /*  151839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  151842 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151845 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  151849 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  151856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151867 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151871 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  151878 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  151878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  151881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  151888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  151893 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  151896 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151900 */   GIR_RootConstrainSelectedInstOperands,
     /*  151901 */   // GIR_Coverage, 9362,
     /*  151901 */   GIR_EraseRootFromParent_Done,
     /*  151902 */ // Label 2143: @151902
     /*  151902 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(151970), // Rule ID 9363 //
     /*  151907 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  151910 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151913 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  151917 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  151924 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  151935 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  151939 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  151946 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  151946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  151949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  151951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  151956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  151961 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  151964 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  151968 */   GIR_RootConstrainSelectedInstOperands,
     /*  151969 */   // GIR_Coverage, 9363,
     /*  151969 */   GIR_EraseRootFromParent_Done,
     /*  151970 */ // Label 2144: @151970
     /*  151970 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(152038), // Rule ID 9364 //
     /*  151975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  151978 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  151981 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  151985 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  151992 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  151999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152003 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152007 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152014 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  152014 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  152017 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152029 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152032 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152036 */   GIR_RootConstrainSelectedInstOperands,
     /*  152037 */   // GIR_Coverage, 9364,
     /*  152037 */   GIR_EraseRootFromParent_Done,
     /*  152038 */ // Label 2145: @152038
     /*  152038 */ GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(152136), // Rule ID 9366 //
     /*  152043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  152046 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152049 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152053 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152082 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  152082 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  152085 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152089 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  152094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152104 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  152107 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152111 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  152113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  152116 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  152118 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  152125 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152130 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152135 */   // GIR_Coverage, 9366,
     /*  152135 */   GIR_EraseRootFromParent_Done,
     /*  152136 */ // Label 2146: @152136
     /*  152136 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(152234), // Rule ID 9367 //
     /*  152141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  152144 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152147 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152151 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152158 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152180 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  152180 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  152183 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152187 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  152192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152202 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  152205 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152209 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  152211 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  152214 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  152216 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  152223 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152228 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152233 */   // GIR_Coverage, 9367,
     /*  152233 */   GIR_EraseRootFromParent_Done,
     /*  152234 */ // Label 2147: @152234
     /*  152234 */ GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(152332), // Rule ID 9368 //
     /*  152239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  152242 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152245 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152249 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152256 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152278 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  152278 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  152281 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152285 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  152290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152300 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  152303 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  152309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  152312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  152314 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  152321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152326 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152331 */   // GIR_Coverage, 9368,
     /*  152331 */   GIR_EraseRootFromParent_Done,
     /*  152332 */ // Label 2148: @152332
     /*  152332 */ GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(152430), // Rule ID 9369 //
     /*  152337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  152340 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152343 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152347 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152354 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152376 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  152376 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  152379 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152383 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  152388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152398 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  152401 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152405 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  152407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  152410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  152412 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  152419 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152424 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152429 */   // GIR_Coverage, 9369,
     /*  152429 */   GIR_EraseRootFromParent_Done,
     /*  152430 */ // Label 2149: @152430
     /*  152430 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(152528), // Rule ID 9370 //
     /*  152435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  152438 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152441 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152445 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152452 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152463 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152467 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152474 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  152474 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  152477 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152481 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  152486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152496 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  152499 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152503 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  152505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  152508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  152510 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  152517 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  152522 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152527 */   // GIR_Coverage, 9370,
     /*  152527 */   GIR_EraseRootFromParent_Done,
     /*  152528 */ // Label 2150: @152528
     /*  152528 */ GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(152596), // Rule ID 11832 //
     /*  152533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  152536 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152539 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152543 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152572 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152587 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152594 */   GIR_RootConstrainSelectedInstOperands,
     /*  152595 */   // GIR_Coverage, 11832,
     /*  152595 */   GIR_EraseRootFromParent_Done,
     /*  152596 */ // Label 2151: @152596
     /*  152596 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(152664), // Rule ID 11833 //
     /*  152601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  152604 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152607 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152611 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152640 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152643 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152655 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152662 */   GIR_RootConstrainSelectedInstOperands,
     /*  152663 */   // GIR_Coverage, 11833,
     /*  152663 */   GIR_EraseRootFromParent_Done,
     /*  152664 */ // Label 2152: @152664
     /*  152664 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(152732), // Rule ID 11834 //
     /*  152669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  152672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152675 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152679 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152686 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152693 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152697 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152708 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152730 */   GIR_RootConstrainSelectedInstOperands,
     /*  152731 */   // GIR_Coverage, 11834,
     /*  152731 */   GIR_EraseRootFromParent_Done,
     /*  152732 */ // Label 2153: @152732
     /*  152732 */ GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(152800), // Rule ID 11835 //
     /*  152737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  152740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152743 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152765 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152776 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152779 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152791 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152794 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152798 */   GIR_RootConstrainSelectedInstOperands,
     /*  152799 */   // GIR_Coverage, 11835,
     /*  152799 */   GIR_EraseRootFromParent_Done,
     /*  152800 */ // Label 2154: @152800
     /*  152800 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(152868), // Rule ID 11836 //
     /*  152805 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  152808 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  152811 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152815 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152822 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152833 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152837 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152844 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152844 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152847 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152859 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152862 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152866 */   GIR_RootConstrainSelectedInstOperands,
     /*  152867 */   // GIR_Coverage, 11836,
     /*  152867 */   GIR_EraseRootFromParent_Done,
     /*  152868 */ // Label 2155: @152868
     /*  152868 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(152936), // Rule ID 11892 //
     /*  152873 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  152876 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  152879 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152883 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152890 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152901 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152905 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152912 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152912 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152915 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  152934 */   GIR_RootConstrainSelectedInstOperands,
     /*  152935 */   // GIR_Coverage, 11892,
     /*  152935 */   GIR_EraseRootFromParent_Done,
     /*  152936 */ // Label 2156: @152936
     /*  152936 */ GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(153004), // Rule ID 11893 //
     /*  152941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  152944 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  152947 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  152951 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  152958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  152965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  152969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  152973 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  152980 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  152980 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  152983 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  152985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  152990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  152995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  152998 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153002 */   GIR_RootConstrainSelectedInstOperands,
     /*  153003 */   // GIR_Coverage, 11893,
     /*  153003 */   GIR_EraseRootFromParent_Done,
     /*  153004 */ // Label 2157: @153004
     /*  153004 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(153072), // Rule ID 11894 //
     /*  153009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  153012 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153015 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153019 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153037 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153041 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153048 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153051 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153063 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153066 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153070 */   GIR_RootConstrainSelectedInstOperands,
     /*  153071 */   // GIR_Coverage, 11894,
     /*  153071 */   GIR_EraseRootFromParent_Done,
     /*  153072 */ // Label 2158: @153072
     /*  153072 */ GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(153140), // Rule ID 11895 //
     /*  153077 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  153080 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153083 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153087 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153116 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153134 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153138 */   GIR_RootConstrainSelectedInstOperands,
     /*  153139 */   // GIR_Coverage, 11895,
     /*  153139 */   GIR_EraseRootFromParent_Done,
     /*  153140 */ // Label 2159: @153140
     /*  153140 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(153208), // Rule ID 11896 //
     /*  153145 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  153148 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153151 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153155 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153173 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153177 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153184 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153184 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153187 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153199 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153202 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153206 */   GIR_RootConstrainSelectedInstOperands,
     /*  153207 */   // GIR_Coverage, 11896,
     /*  153207 */   GIR_EraseRootFromParent_Done,
     /*  153208 */ // Label 2160: @153208
     /*  153208 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(153276), // Rule ID 11922 //
     /*  153213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  153216 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153219 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153223 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  153230 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153245 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153252 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  153255 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153267 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153270 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153274 */   GIR_RootConstrainSelectedInstOperands,
     /*  153275 */   // GIR_Coverage, 11922,
     /*  153275 */   GIR_EraseRootFromParent_Done,
     /*  153276 */ // Label 2161: @153276
     /*  153276 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(153344), // Rule ID 11923 //
     /*  153281 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  153284 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153287 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153291 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  153298 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153320 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  153323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153335 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153338 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153342 */   GIR_RootConstrainSelectedInstOperands,
     /*  153343 */   // GIR_Coverage, 11923,
     /*  153343 */   GIR_EraseRootFromParent_Done,
     /*  153344 */ // Label 2162: @153344
     /*  153344 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(153412), // Rule ID 11924 //
     /*  153349 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  153352 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153355 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153359 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  153366 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153377 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153388 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  153391 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153406 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153410 */   GIR_RootConstrainSelectedInstOperands,
     /*  153411 */   // GIR_Coverage, 11924,
     /*  153411 */   GIR_EraseRootFromParent_Done,
     /*  153412 */ // Label 2163: @153412
     /*  153412 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(153480), // Rule ID 11925 //
     /*  153417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  153420 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153423 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153427 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  153434 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153445 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153449 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153456 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153456 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  153459 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153478 */   GIR_RootConstrainSelectedInstOperands,
     /*  153479 */   // GIR_Coverage, 11925,
     /*  153479 */   GIR_EraseRootFromParent_Done,
     /*  153480 */ // Label 2164: @153480
     /*  153480 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(153548), // Rule ID 11926 //
     /*  153485 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  153488 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153491 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153495 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  153502 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153513 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153517 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153524 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  153524 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  153527 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  153529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153539 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  153542 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153546 */   GIR_RootConstrainSelectedInstOperands,
     /*  153547 */   // GIR_Coverage, 11926,
     /*  153547 */   GIR_EraseRootFromParent_Done,
     /*  153548 */ // Label 2165: @153548
     /*  153548 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(153646), // Rule ID 11992 //
     /*  153553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  153556 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153559 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153563 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153570 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153577 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153581 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153585 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153592 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  153592 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  153595 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153599 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  153604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153614 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  153617 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153621 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  153623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  153626 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  153628 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  153635 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153640 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153645 */   // GIR_Coverage, 11992,
     /*  153645 */   GIR_EraseRootFromParent_Done,
     /*  153646 */ // Label 2166: @153646
     /*  153646 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(153744), // Rule ID 11993 //
     /*  153651 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  153654 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153657 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153661 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153668 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153679 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153683 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153690 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  153690 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  153693 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153697 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  153702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153712 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  153715 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153719 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  153721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  153724 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  153726 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  153733 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153738 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153743 */   // GIR_Coverage, 11993,
     /*  153743 */   GIR_EraseRootFromParent_Done,
     /*  153744 */ // Label 2167: @153744
     /*  153744 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(153842), // Rule ID 11994 //
     /*  153749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  153752 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153755 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153759 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153766 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153777 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153781 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153788 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  153788 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  153791 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153795 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  153800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153810 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  153813 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153817 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  153819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  153822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  153824 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  153831 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153836 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153841 */   // GIR_Coverage, 11994,
     /*  153841 */   GIR_EraseRootFromParent_Done,
     /*  153842 */ // Label 2168: @153842
     /*  153842 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(153940), // Rule ID 11995 //
     /*  153847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  153850 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153853 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153857 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153871 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153875 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153879 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153886 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  153886 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  153889 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153893 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  153898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  153903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  153908 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  153911 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  153915 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  153917 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  153920 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  153922 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  153929 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153934 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  153939 */   // GIR_Coverage, 11995,
     /*  153939 */   GIR_EraseRootFromParent_Done,
     /*  153940 */ // Label 2169: @153940
     /*  153940 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(154038), // Rule ID 11996 //
     /*  153945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  153948 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  153951 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  153955 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  153962 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  153969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  153973 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  153977 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  153984 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  153984 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  153987 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  153991 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  153996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154006 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  154009 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154013 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  154015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  154018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  154020 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  154027 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154032 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  154037 */   // GIR_Coverage, 11996,
     /*  154037 */   GIR_EraseRootFromParent_Done,
     /*  154038 */ // Label 2170: @154038
     /*  154038 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(154136), // Rule ID 12022 //
     /*  154043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  154046 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154049 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154053 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154082 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  154082 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  154085 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  154089 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  154094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154104 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  154107 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154111 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  154113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  154116 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  154118 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  154125 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154130 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  154135 */   // GIR_Coverage, 12022,
     /*  154135 */   GIR_EraseRootFromParent_Done,
     /*  154136 */ // Label 2171: @154136
     /*  154136 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(154234), // Rule ID 12023 //
     /*  154141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  154144 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154147 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154151 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154158 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154180 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  154180 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  154183 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  154187 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  154192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154202 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  154205 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154209 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  154211 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  154214 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  154216 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  154223 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154228 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  154233 */   // GIR_Coverage, 12023,
     /*  154233 */   GIR_EraseRootFromParent_Done,
     /*  154234 */ // Label 2172: @154234
     /*  154234 */ GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(154332), // Rule ID 12024 //
     /*  154239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  154242 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154245 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154249 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154256 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154278 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  154278 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  154281 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  154285 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  154290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154300 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  154303 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  154309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  154312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  154314 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  154321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154326 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  154331 */   // GIR_Coverage, 12024,
     /*  154331 */   GIR_EraseRootFromParent_Done,
     /*  154332 */ // Label 2173: @154332
     /*  154332 */ GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(154430), // Rule ID 12025 //
     /*  154337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  154340 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154343 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154347 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154354 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154376 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  154376 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  154379 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  154383 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  154388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154398 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  154401 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154405 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  154407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  154410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  154412 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  154419 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154424 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  154429 */   // GIR_Coverage, 12025,
     /*  154429 */   GIR_EraseRootFromParent_Done,
     /*  154430 */ // Label 2174: @154430
     /*  154430 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(154528), // Rule ID 12026 //
     /*  154435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  154438 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154441 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154445 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154452 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154463 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154467 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154474 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  154474 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  154477 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  154481 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  154486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154496 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  154499 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154503 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  154505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  154508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  154510 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  154517 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154522 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  154527 */   // GIR_Coverage, 12026,
     /*  154527 */   GIR_EraseRootFromParent_Done,
     /*  154528 */ // Label 2175: @154528
     /*  154528 */ GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(154596), // Rule ID 12060 //
     /*  154533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  154536 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154539 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154543 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  154550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154572 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  154575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154587 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154594 */   GIR_RootConstrainSelectedInstOperands,
     /*  154595 */   // GIR_Coverage, 12060,
     /*  154595 */   GIR_EraseRootFromParent_Done,
     /*  154596 */ // Label 2176: @154596
     /*  154596 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(154664), // Rule ID 12061 //
     /*  154601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  154604 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154607 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154611 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  154618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154640 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  154643 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154655 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154662 */   GIR_RootConstrainSelectedInstOperands,
     /*  154663 */   // GIR_Coverage, 12061,
     /*  154663 */   GIR_EraseRootFromParent_Done,
     /*  154664 */ // Label 2177: @154664
     /*  154664 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(154732), // Rule ID 12062 //
     /*  154669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  154672 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154675 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154679 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  154686 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154693 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154697 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154708 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  154711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154730 */   GIR_RootConstrainSelectedInstOperands,
     /*  154731 */   // GIR_Coverage, 12062,
     /*  154731 */   GIR_EraseRootFromParent_Done,
     /*  154732 */ // Label 2178: @154732
     /*  154732 */ GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(154800), // Rule ID 12063 //
     /*  154737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  154740 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154743 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  154754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154765 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154776 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  154779 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154791 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154794 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154798 */   GIR_RootConstrainSelectedInstOperands,
     /*  154799 */   // GIR_Coverage, 12063,
     /*  154799 */   GIR_EraseRootFromParent_Done,
     /*  154800 */ // Label 2179: @154800
     /*  154800 */ GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(154868), // Rule ID 12064 //
     /*  154805 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  154808 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154811 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154815 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  154822 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154833 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154837 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154844 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154844 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  154847 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154859 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154862 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154866 */   GIR_RootConstrainSelectedInstOperands,
     /*  154867 */   // GIR_Coverage, 12064,
     /*  154867 */   GIR_EraseRootFromParent_Done,
     /*  154868 */ // Label 2180: @154868
     /*  154868 */ GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(154936), // Rule ID 12078 //
     /*  154873 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  154876 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154879 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154883 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154890 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154901 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154905 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154912 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154912 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  154915 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  154934 */   GIR_RootConstrainSelectedInstOperands,
     /*  154935 */   // GIR_Coverage, 12078,
     /*  154935 */   GIR_EraseRootFromParent_Done,
     /*  154936 */ // Label 2181: @154936
     /*  154936 */ GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(155004), // Rule ID 12079 //
     /*  154941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  154944 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  154947 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  154951 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  154958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  154965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  154969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  154973 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  154980 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  154980 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  154983 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  154985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  154990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  154995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  154998 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155002 */   GIR_RootConstrainSelectedInstOperands,
     /*  155003 */   // GIR_Coverage, 12079,
     /*  155003 */   GIR_EraseRootFromParent_Done,
     /*  155004 */ // Label 2182: @155004
     /*  155004 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(155072), // Rule ID 12080 //
     /*  155009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  155012 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  155015 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  155019 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  155026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155037 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155041 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155048 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  155048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  155051 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155063 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155066 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155070 */   GIR_RootConstrainSelectedInstOperands,
     /*  155071 */   // GIR_Coverage, 12080,
     /*  155071 */   GIR_EraseRootFromParent_Done,
     /*  155072 */ // Label 2183: @155072
     /*  155072 */ GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(155140), // Rule ID 12081 //
     /*  155077 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  155080 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  155083 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  155087 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  155094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155116 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  155116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  155119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155134 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155138 */   GIR_RootConstrainSelectedInstOperands,
     /*  155139 */   // GIR_Coverage, 12081,
     /*  155139 */   GIR_EraseRootFromParent_Done,
     /*  155140 */ // Label 2184: @155140
     /*  155140 */ GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(155208), // Rule ID 12082 //
     /*  155145 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  155148 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  155151 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  155155 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  155162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155173 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155177 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155184 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  155184 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  155187 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155199 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155202 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155206 */   GIR_RootConstrainSelectedInstOperands,
     /*  155207 */   // GIR_Coverage, 12082,
     /*  155207 */   GIR_EraseRootFromParent_Done,
     /*  155208 */ // Label 2185: @155208
     /*  155208 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(155265), // Rule ID 11882 //
     /*  155213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  155216 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155219 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155241 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  155241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155259 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155263 */   GIR_RootConstrainSelectedInstOperands,
     /*  155264 */   // GIR_Coverage, 11882,
     /*  155264 */   GIR_EraseRootFromParent_Done,
     /*  155265 */ // Label 2186: @155265
     /*  155265 */ GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(155322), // Rule ID 11883 //
     /*  155270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  155273 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155276 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155287 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155298 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  155298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155313 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155320 */   GIR_RootConstrainSelectedInstOperands,
     /*  155321 */   // GIR_Coverage, 11883,
     /*  155321 */   GIR_EraseRootFromParent_Done,
     /*  155322 */ // Label 2187: @155322
     /*  155322 */ GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(155379), // Rule ID 11884 //
     /*  155327 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  155330 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155344 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155355 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  155355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155377 */   GIR_RootConstrainSelectedInstOperands,
     /*  155378 */   // GIR_Coverage, 11884,
     /*  155378 */   GIR_EraseRootFromParent_Done,
     /*  155379 */ // Label 2188: @155379
     /*  155379 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(155436), // Rule ID 11885 //
     /*  155384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  155387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155397 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155412 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  155412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155415 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155434 */   GIR_RootConstrainSelectedInstOperands,
     /*  155435 */   // GIR_Coverage, 11885,
     /*  155435 */   GIR_EraseRootFromParent_Done,
     /*  155436 */ // Label 2189: @155436
     /*  155436 */ GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(155493), // Rule ID 11886 //
     /*  155441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  155444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155469 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  155469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155487 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155491 */   GIR_RootConstrainSelectedInstOperands,
     /*  155492 */   // GIR_Coverage, 11886,
     /*  155492 */   GIR_EraseRootFromParent_Done,
     /*  155493 */ // Label 2190: @155493
     /*  155493 */ GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(155580), // Rule ID 11982 //
     /*  155498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  155501 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155504 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155511 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155515 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155519 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155526 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  155526 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  155529 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155533 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  155538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155548 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  155551 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155555 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  155557 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  155560 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  155562 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  155569 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155574 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155579 */   // GIR_Coverage, 11982,
     /*  155579 */   GIR_EraseRootFromParent_Done,
     /*  155580 */ // Label 2191: @155580
     /*  155580 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(155667), // Rule ID 11983 //
     /*  155585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  155588 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155613 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  155613 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  155616 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155620 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  155625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155635 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  155638 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155642 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  155644 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  155647 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  155649 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  155656 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155661 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155666 */   // GIR_Coverage, 11983,
     /*  155666 */   GIR_EraseRootFromParent_Done,
     /*  155667 */ // Label 2192: @155667
     /*  155667 */ GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(155754), // Rule ID 11984 //
     /*  155672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  155675 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155678 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155689 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155693 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155700 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  155700 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  155703 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155707 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  155712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155722 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  155725 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155729 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  155731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  155734 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  155736 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  155743 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155748 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155753 */   // GIR_Coverage, 11984,
     /*  155753 */   GIR_EraseRootFromParent_Done,
     /*  155754 */ // Label 2193: @155754
     /*  155754 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(155841), // Rule ID 11985 //
     /*  155759 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  155762 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155765 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155780 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155787 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  155787 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  155790 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155794 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  155799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155809 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  155812 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155816 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  155818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  155821 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  155823 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  155830 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155835 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155840 */   // GIR_Coverage, 11985,
     /*  155840 */   GIR_EraseRootFromParent_Done,
     /*  155841 */ // Label 2194: @155841
     /*  155841 */ GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(155928), // Rule ID 11986 //
     /*  155846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  155849 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155852 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155863 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155867 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155874 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  155874 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  155877 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  155881 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  155886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155896 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  155899 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155903 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  155905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  155908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  155910 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  155917 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155922 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  155927 */   // GIR_Coverage, 11986,
     /*  155927 */   GIR_EraseRootFromParent_Done,
     /*  155928 */ // Label 2195: @155928
     /*  155928 */ GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(155985), // Rule ID 12054 //
     /*  155933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  155936 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  155946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  155950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  155954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  155961 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  155961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  155964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  155966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  155971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  155976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  155979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  155983 */   GIR_RootConstrainSelectedInstOperands,
     /*  155984 */   // GIR_Coverage, 12054,
     /*  155984 */   GIR_EraseRootFromParent_Done,
     /*  155985 */ // Label 2196: @155985
     /*  155985 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(156042), // Rule ID 12055 //
     /*  155990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  155993 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  155996 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156007 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156011 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  156018 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  156018 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  156021 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  156028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  156033 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  156036 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156040 */   GIR_RootConstrainSelectedInstOperands,
     /*  156041 */   // GIR_Coverage, 12055,
     /*  156041 */   GIR_EraseRootFromParent_Done,
     /*  156042 */ // Label 2197: @156042
     /*  156042 */ GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(156099), // Rule ID 12056 //
     /*  156047 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  156050 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156060 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156064 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156068 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  156075 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  156075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  156078 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  156085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  156090 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  156093 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156097 */   GIR_RootConstrainSelectedInstOperands,
     /*  156098 */   // GIR_Coverage, 12056,
     /*  156098 */   GIR_EraseRootFromParent_Done,
     /*  156099 */ // Label 2198: @156099
     /*  156099 */ GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(156156), // Rule ID 12057 //
     /*  156104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  156107 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156110 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156117 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156121 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  156132 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  156132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  156135 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  156142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  156147 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  156150 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156154 */   GIR_RootConstrainSelectedInstOperands,
     /*  156155 */   // GIR_Coverage, 12057,
     /*  156155 */   GIR_EraseRootFromParent_Done,
     /*  156156 */ // Label 2199: @156156
     /*  156156 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(156213), // Rule ID 12058 //
     /*  156161 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  156164 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156178 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156182 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  156189 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  156189 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  156192 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  156199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  156204 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  156207 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156211 */   GIR_RootConstrainSelectedInstOperands,
     /*  156212 */   // GIR_Coverage, 12058,
     /*  156212 */   GIR_EraseRootFromParent_Done,
     /*  156213 */ // Label 2200: @156213
     /*  156213 */ GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(156289), // Rule ID 9499 //
     /*  156218 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  156221 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156224 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156228 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156235 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156258 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  156258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16_SADDR),
     /*  156261 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156283 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156287 */   GIR_RootConstrainSelectedInstOperands,
     /*  156288 */   // GIR_Coverage, 9499,
     /*  156288 */   GIR_EraseRootFromParent_Done,
     /*  156289 */ // Label 2201: @156289
     /*  156289 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(156395), // Rule ID 9505 //
     /*  156294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  156297 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156300 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156304 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156311 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156323 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156327 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156334 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  156334 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  156337 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156341 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  156346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156366 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156370 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  156372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  156375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  156377 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  156384 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156389 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156394 */   // GIR_Coverage, 9505,
     /*  156394 */   GIR_EraseRootFromParent_Done,
     /*  156395 */ // Label 2202: @156395
     /*  156395 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(156501), // Rule ID 9506 //
     /*  156400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  156403 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156406 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156410 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156425 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156429 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156433 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156440 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  156440 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  156443 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156447 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  156452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156472 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156476 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  156478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  156481 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  156483 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  156490 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156495 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156500 */   // GIR_Coverage, 9506,
     /*  156500 */   GIR_EraseRootFromParent_Done,
     /*  156501 */ // Label 2203: @156501
     /*  156501 */ GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(156607), // Rule ID 9507 //
     /*  156506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  156509 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156512 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156516 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156523 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156535 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156539 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156546 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  156546 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  156549 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156553 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  156558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156578 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156582 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  156584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  156587 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  156589 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  156596 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156601 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156606 */   // GIR_Coverage, 9507,
     /*  156606 */   GIR_EraseRootFromParent_Done,
     /*  156607 */ // Label 2204: @156607
     /*  156607 */ GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(156713), // Rule ID 9508 //
     /*  156612 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  156615 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156618 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156622 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156629 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156645 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156652 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  156652 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  156655 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156659 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  156664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156684 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156688 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  156690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  156693 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  156695 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  156702 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156707 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156712 */   // GIR_Coverage, 9508,
     /*  156712 */   GIR_EraseRootFromParent_Done,
     /*  156713 */ // Label 2205: @156713
     /*  156713 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(156819), // Rule ID 9509 //
     /*  156718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  156721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156724 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156728 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156747 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156751 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156758 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  156758 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  156761 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156765 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  156770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156790 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156794 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  156796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  156799 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  156801 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  156808 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  156813 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156818 */   // GIR_Coverage, 9509,
     /*  156818 */   GIR_EraseRootFromParent_Done,
     /*  156819 */ // Label 2206: @156819
     /*  156819 */ GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(156895), // Rule ID 9661 //
     /*  156824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  156827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156830 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156834 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156841 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156853 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156857 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156864 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  156864 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156867 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156889 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156893 */   GIR_RootConstrainSelectedInstOperands,
     /*  156894 */   // GIR_Coverage, 9661,
     /*  156894 */   GIR_EraseRootFromParent_Done,
     /*  156895 */ // Label 2207: @156895
     /*  156895 */ GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(156971), // Rule ID 9662 //
     /*  156900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  156903 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156906 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156910 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156917 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  156925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  156929 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  156933 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  156940 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  156940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  156943 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  156945 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  156950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  156955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  156960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  156965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  156969 */   GIR_RootConstrainSelectedInstOperands,
     /*  156970 */   // GIR_Coverage, 9662,
     /*  156970 */   GIR_EraseRootFromParent_Done,
     /*  156971 */ // Label 2208: @156971
     /*  156971 */ GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(157047), // Rule ID 9663 //
     /*  156976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  156979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  156982 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  156986 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  156993 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157005 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157009 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157016 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157016 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157019 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157041 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157045 */   GIR_RootConstrainSelectedInstOperands,
     /*  157046 */   // GIR_Coverage, 9663,
     /*  157046 */   GIR_EraseRootFromParent_Done,
     /*  157047 */ // Label 2209: @157047
     /*  157047 */ GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(157123), // Rule ID 9664 //
     /*  157052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  157055 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  157058 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157062 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157069 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157077 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157081 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157085 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157092 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157092 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157095 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157117 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157121 */   GIR_RootConstrainSelectedInstOperands,
     /*  157122 */   // GIR_Coverage, 9664,
     /*  157122 */   GIR_EraseRootFromParent_Done,
     /*  157123 */ // Label 2210: @157123
     /*  157123 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(157199), // Rule ID 9665 //
     /*  157128 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  157131 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  157134 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157138 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157145 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157153 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157157 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157161 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157168 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157168 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157171 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157193 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157197 */   GIR_RootConstrainSelectedInstOperands,
     /*  157198 */   // GIR_Coverage, 9665,
     /*  157198 */   GIR_EraseRootFromParent_Done,
     /*  157199 */ // Label 2211: @157199
     /*  157199 */ GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(157275), // Rule ID 9701 //
     /*  157204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  157207 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157210 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157214 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157221 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157244 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157247 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157269 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157273 */   GIR_RootConstrainSelectedInstOperands,
     /*  157274 */   // GIR_Coverage, 9701,
     /*  157274 */   GIR_EraseRootFromParent_Done,
     /*  157275 */ // Label 2212: @157275
     /*  157275 */ GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(157351), // Rule ID 9702 //
     /*  157280 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  157283 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157286 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157290 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157297 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157320 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157349 */   GIR_RootConstrainSelectedInstOperands,
     /*  157350 */   // GIR_Coverage, 9702,
     /*  157350 */   GIR_EraseRootFromParent_Done,
     /*  157351 */ // Label 2213: @157351
     /*  157351 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(157427), // Rule ID 9703 //
     /*  157356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  157359 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157362 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157366 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157373 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157396 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157399 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157425 */   GIR_RootConstrainSelectedInstOperands,
     /*  157426 */   // GIR_Coverage, 9703,
     /*  157426 */   GIR_EraseRootFromParent_Done,
     /*  157427 */ // Label 2214: @157427
     /*  157427 */ GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(157503), // Rule ID 9704 //
     /*  157432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  157435 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157438 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157442 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157472 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157501 */   GIR_RootConstrainSelectedInstOperands,
     /*  157502 */   // GIR_Coverage, 9704,
     /*  157502 */   GIR_EraseRootFromParent_Done,
     /*  157503 */ // Label 2215: @157503
     /*  157503 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(157579), // Rule ID 9705 //
     /*  157508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  157511 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157514 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157518 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157525 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157537 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157541 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157548 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  157551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157573 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157577 */   GIR_RootConstrainSelectedInstOperands,
     /*  157578 */   // GIR_Coverage, 9705,
     /*  157578 */   GIR_EraseRootFromParent_Done,
     /*  157579 */ // Label 2216: @157579
     /*  157579 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(157655), // Rule ID 9721 //
     /*  157584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  157587 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157590 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157594 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  157601 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157624 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  157627 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157653 */   GIR_RootConstrainSelectedInstOperands,
     /*  157654 */   // GIR_Coverage, 9721,
     /*  157654 */   GIR_EraseRootFromParent_Done,
     /*  157655 */ // Label 2217: @157655
     /*  157655 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(157731), // Rule ID 9722 //
     /*  157660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  157663 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157666 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157670 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  157677 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157689 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157693 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157700 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  157703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157729 */   GIR_RootConstrainSelectedInstOperands,
     /*  157730 */   // GIR_Coverage, 9722,
     /*  157730 */   GIR_EraseRootFromParent_Done,
     /*  157731 */ // Label 2218: @157731
     /*  157731 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(157807), // Rule ID 9723 //
     /*  157736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  157739 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157742 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157746 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  157753 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157765 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157776 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  157779 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157805 */   GIR_RootConstrainSelectedInstOperands,
     /*  157806 */   // GIR_Coverage, 9723,
     /*  157806 */   GIR_EraseRootFromParent_Done,
     /*  157807 */ // Label 2219: @157807
     /*  157807 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(157883), // Rule ID 9724 //
     /*  157812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  157815 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157818 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  157829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157841 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157845 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157852 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157852 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  157855 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157877 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157881 */   GIR_RootConstrainSelectedInstOperands,
     /*  157882 */   // GIR_Coverage, 9724,
     /*  157882 */   GIR_EraseRootFromParent_Done,
     /*  157883 */ // Label 2220: @157883
     /*  157883 */ GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(157959), // Rule ID 9725 //
     /*  157888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  157891 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157894 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157898 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  157905 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  157917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  157928 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  157928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  157931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  157933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  157938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  157943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  157948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  157953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  157957 */   GIR_RootConstrainSelectedInstOperands,
     /*  157958 */   // GIR_Coverage, 9725,
     /*  157958 */   GIR_EraseRootFromParent_Done,
     /*  157959 */ // Label 2221: @157959
     /*  157959 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(158065), // Rule ID 9801 //
     /*  157964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  157967 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  157970 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  157974 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  157981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  157989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  157993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  157997 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158004 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158004 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158007 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  158011 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158036 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158040 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158045 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158047 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158054 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158059 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158064 */   // GIR_Coverage, 9801,
     /*  158064 */   GIR_EraseRootFromParent_Done,
     /*  158065 */ // Label 2222: @158065
     /*  158065 */ GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(158171), // Rule ID 9802 //
     /*  158070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  158073 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158076 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158080 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  158087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158095 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158099 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158103 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158110 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158110 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158113 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  158117 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158142 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158146 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158148 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158151 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158153 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158160 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158165 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158170 */   // GIR_Coverage, 9802,
     /*  158170 */   GIR_EraseRootFromParent_Done,
     /*  158171 */ // Label 2223: @158171
     /*  158171 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(158277), // Rule ID 9803 //
     /*  158176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  158179 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158182 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158186 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  158193 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158205 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158209 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158216 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158216 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158219 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  158223 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158248 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158252 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158259 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158266 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158271 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158276 */   // GIR_Coverage, 9803,
     /*  158276 */   GIR_EraseRootFromParent_Done,
     /*  158277 */ // Label 2224: @158277
     /*  158277 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(158383), // Rule ID 9804 //
     /*  158282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  158285 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158288 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  158299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158311 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158315 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158322 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158322 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158325 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  158329 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158354 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158358 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158365 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158372 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158377 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158382 */   // GIR_Coverage, 9804,
     /*  158382 */   GIR_EraseRootFromParent_Done,
     /*  158383 */ // Label 2225: @158383
     /*  158383 */ GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(158489), // Rule ID 9805 //
     /*  158388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  158391 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158394 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158398 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  158405 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158413 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158428 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158428 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158431 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  158435 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158460 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158464 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158469 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158471 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158478 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158483 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158488 */   // GIR_Coverage, 9805,
     /*  158488 */   GIR_EraseRootFromParent_Done,
     /*  158489 */ // Label 2226: @158489
     /*  158489 */ GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(158595), // Rule ID 9821 //
     /*  158494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  158497 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158500 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158504 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  158511 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158523 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158527 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158534 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158534 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158537 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  158541 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158566 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158570 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158577 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158584 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158589 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158594 */   // GIR_Coverage, 9821,
     /*  158594 */   GIR_EraseRootFromParent_Done,
     /*  158595 */ // Label 2227: @158595
     /*  158595 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(158701), // Rule ID 9822 //
     /*  158600 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  158603 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158606 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158610 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  158617 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158640 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158640 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158643 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  158647 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158672 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158676 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158678 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158681 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158683 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158690 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158695 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158700 */   // GIR_Coverage, 9822,
     /*  158700 */   GIR_EraseRootFromParent_Done,
     /*  158701 */ // Label 2228: @158701
     /*  158701 */ GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(158807), // Rule ID 9823 //
     /*  158706 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  158709 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158712 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158716 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  158723 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158731 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158735 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158746 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158746 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158749 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  158753 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158778 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158782 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158787 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158789 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158796 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158801 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158806 */   // GIR_Coverage, 9823,
     /*  158806 */   GIR_EraseRootFromParent_Done,
     /*  158807 */ // Label 2229: @158807
     /*  158807 */ GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(158913), // Rule ID 9824 //
     /*  158812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  158815 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158818 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  158829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158841 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158845 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158852 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158852 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158855 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  158859 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158884 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158888 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158890 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158893 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  158895 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  158902 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158907 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  158912 */   // GIR_Coverage, 9824,
     /*  158912 */   GIR_EraseRootFromParent_Done,
     /*  158913 */ // Label 2230: @158913
     /*  158913 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(159019), // Rule ID 9825 //
     /*  158918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  158921 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  158924 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  158928 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  158935 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  158943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  158947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  158951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  158958 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  158958 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  158961 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  158965 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  158970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  158975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  158980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  158985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  158990 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  158994 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  158996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  158999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  159001 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  159008 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159013 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159018 */   // GIR_Coverage, 9825,
     /*  159018 */   GIR_EraseRootFromParent_Done,
     /*  159019 */ // Label 2231: @159019
     /*  159019 */ GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(159095), // Rule ID 9859 //
     /*  159024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  159027 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  159030 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  159034 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  159041 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159053 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159057 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159064 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16_SADDR),
     /*  159067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159093 */   GIR_RootConstrainSelectedInstOperands,
     /*  159094 */   // GIR_Coverage, 9859,
     /*  159094 */   GIR_EraseRootFromParent_Done,
     /*  159095 */ // Label 2232: @159095
     /*  159095 */ GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(159171), // Rule ID 9871 //
     /*  159100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  159103 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  159106 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  159110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  159117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159140 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16_SADDR),
     /*  159143 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159169 */   GIR_RootConstrainSelectedInstOperands,
     /*  159170 */   // GIR_Coverage, 9871,
     /*  159170 */   GIR_EraseRootFromParent_Done,
     /*  159171 */ // Label 2233: @159171
     /*  159171 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(159236), // Rule ID 9691 //
     /*  159176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  159179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159182 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159194 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159198 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159205 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159208 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159230 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159234 */   GIR_RootConstrainSelectedInstOperands,
     /*  159235 */   // GIR_Coverage, 9691,
     /*  159235 */   GIR_EraseRootFromParent_Done,
     /*  159236 */ // Label 2234: @159236
     /*  159236 */ GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(159301), // Rule ID 9692 //
     /*  159241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  159244 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159247 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159255 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159259 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159263 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159270 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159273 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159295 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159299 */   GIR_RootConstrainSelectedInstOperands,
     /*  159300 */   // GIR_Coverage, 9692,
     /*  159300 */   GIR_EraseRootFromParent_Done,
     /*  159301 */ // Label 2235: @159301
     /*  159301 */ GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(159366), // Rule ID 9693 //
     /*  159306 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  159309 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159312 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159335 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159338 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159360 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159364 */   GIR_RootConstrainSelectedInstOperands,
     /*  159365 */   // GIR_Coverage, 9693,
     /*  159365 */   GIR_EraseRootFromParent_Done,
     /*  159366 */ // Label 2236: @159366
     /*  159366 */ GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(159431), // Rule ID 9694 //
     /*  159371 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  159374 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159377 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159389 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159393 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159400 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159403 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159429 */   GIR_RootConstrainSelectedInstOperands,
     /*  159430 */   // GIR_Coverage, 9694,
     /*  159430 */   GIR_EraseRootFromParent_Done,
     /*  159431 */ // Label 2237: @159431
     /*  159431 */ GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(159496), // Rule ID 9695 //
     /*  159436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  159439 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159442 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159454 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159458 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159465 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  159465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159468 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  159470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159490 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159494 */   GIR_RootConstrainSelectedInstOperands,
     /*  159495 */   // GIR_Coverage, 9695,
     /*  159495 */   GIR_EraseRootFromParent_Done,
     /*  159496 */ // Label 2238: @159496
     /*  159496 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(159591), // Rule ID 9791 //
     /*  159501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  159504 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159530 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  159530 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  159533 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159537 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  159542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159562 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159566 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  159568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  159571 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  159573 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  159580 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159585 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159590 */   // GIR_Coverage, 9791,
     /*  159590 */   GIR_EraseRootFromParent_Done,
     /*  159591 */ // Label 2239: @159591
     /*  159591 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(159686), // Rule ID 9792 //
     /*  159596 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  159599 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159602 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159610 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159614 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159618 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159625 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  159625 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  159628 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159632 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  159637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159657 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159661 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  159663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  159666 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  159668 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  159675 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159680 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159685 */   // GIR_Coverage, 9792,
     /*  159685 */   GIR_EraseRootFromParent_Done,
     /*  159686 */ // Label 2240: @159686
     /*  159686 */ GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(159781), // Rule ID 9793 //
     /*  159691 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  159694 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159697 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159709 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159713 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159720 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  159720 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  159723 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159727 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  159732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159752 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159756 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  159758 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  159761 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  159763 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  159770 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159775 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159780 */   // GIR_Coverage, 9793,
     /*  159780 */   GIR_EraseRootFromParent_Done,
     /*  159781 */ // Label 2241: @159781
     /*  159781 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(159876), // Rule ID 9794 //
     /*  159786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  159789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159792 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159808 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159815 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  159815 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  159818 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159822 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  159827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159847 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159851 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  159853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  159856 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  159858 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  159865 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159870 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159875 */   // GIR_Coverage, 9794,
     /*  159875 */   GIR_EraseRootFromParent_Done,
     /*  159876 */ // Label 2242: @159876
     /*  159876 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(159971), // Rule ID 9795 //
     /*  159881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  159884 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159887 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159899 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159903 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  159910 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  159910 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  159913 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  159917 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  159922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  159927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  159932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  159937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  159942 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  159946 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  159948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  159951 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  159953 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  159960 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159965 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  159970 */   // GIR_Coverage, 9795,
     /*  159970 */   GIR_EraseRootFromParent_Done,
     /*  159971 */ // Label 2243: @159971
     /*  159971 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(160036), // Rule ID 9853 //
     /*  159976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  159979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  159982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  159990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  159994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  159998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  160005 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  160005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16_SADDR),
     /*  160008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  160015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  160020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  160025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  160030 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160034 */   GIR_RootConstrainSelectedInstOperands,
     /*  160035 */   // GIR_Coverage, 9853,
     /*  160035 */   GIR_EraseRootFromParent_Done,
     /*  160036 */ // Label 2244: @160036
     /*  160036 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(160105), // Rule ID 9494 //
     /*  160041 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  160044 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160047 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160051 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160058 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160081 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  160081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  160084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160096 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  160099 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160103 */   GIR_RootConstrainSelectedInstOperands,
     /*  160104 */   // GIR_Coverage, 9494,
     /*  160104 */   GIR_EraseRootFromParent_Done,
     /*  160105 */ // Label 2245: @160105
     /*  160105 */ GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(160174), // Rule ID 9495 //
     /*  160110 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  160113 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160116 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160120 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160139 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160143 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160150 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  160150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  160153 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160165 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  160168 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160172 */   GIR_RootConstrainSelectedInstOperands,
     /*  160173 */   // GIR_Coverage, 9495,
     /*  160173 */   GIR_EraseRootFromParent_Done,
     /*  160174 */ // Label 2246: @160174
     /*  160174 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(160243), // Rule ID 9496 //
     /*  160179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  160182 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160185 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160189 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160196 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160219 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  160219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  160222 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160234 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  160237 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160241 */   GIR_RootConstrainSelectedInstOperands,
     /*  160242 */   // GIR_Coverage, 9496,
     /*  160242 */   GIR_EraseRootFromParent_Done,
     /*  160243 */ // Label 2247: @160243
     /*  160243 */ GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(160312), // Rule ID 9497 //
     /*  160248 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  160251 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160254 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160258 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160265 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160277 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160281 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160288 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  160288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  160291 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160303 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  160306 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160310 */   GIR_RootConstrainSelectedInstOperands,
     /*  160311 */   // GIR_Coverage, 9497,
     /*  160311 */   GIR_EraseRootFromParent_Done,
     /*  160312 */ // Label 2248: @160312
     /*  160312 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(160381), // Rule ID 9498 //
     /*  160317 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  160320 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160323 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160327 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160334 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160346 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160350 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160357 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  160357 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  160360 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160372 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  160375 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160379 */   GIR_RootConstrainSelectedInstOperands,
     /*  160380 */   // GIR_Coverage, 9498,
     /*  160380 */   GIR_EraseRootFromParent_Done,
     /*  160381 */ // Label 2249: @160381
     /*  160381 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(160480), // Rule ID 9500 //
     /*  160386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  160389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160392 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160415 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160419 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160426 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  160426 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  160429 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160433 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  160438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160448 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  160451 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160455 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  160457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  160460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  160462 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  160469 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160474 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160479 */   // GIR_Coverage, 9500,
     /*  160479 */   GIR_EraseRootFromParent_Done,
     /*  160480 */ // Label 2250: @160480
     /*  160480 */ GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(160579), // Rule ID 9501 //
     /*  160485 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  160488 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160491 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160495 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160502 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160525 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  160525 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  160528 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160532 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  160537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160547 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  160550 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160554 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  160556 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  160559 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  160561 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  160568 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160573 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160578 */   // GIR_Coverage, 9501,
     /*  160578 */   GIR_EraseRootFromParent_Done,
     /*  160579 */ // Label 2251: @160579
     /*  160579 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(160678), // Rule ID 9502 //
     /*  160584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  160587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160590 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160594 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160601 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160624 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  160624 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  160627 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160631 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  160636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160646 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  160649 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160653 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  160655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  160658 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  160660 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  160667 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160672 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160677 */   // GIR_Coverage, 9502,
     /*  160677 */   GIR_EraseRootFromParent_Done,
     /*  160678 */ // Label 2252: @160678
     /*  160678 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(160777), // Rule ID 9503 //
     /*  160683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  160686 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160689 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160693 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160700 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160712 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160716 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160723 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  160723 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  160726 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160730 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  160735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160745 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  160748 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160752 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  160754 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  160757 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  160759 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  160766 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160771 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160776 */   // GIR_Coverage, 9503,
     /*  160776 */   GIR_EraseRootFromParent_Done,
     /*  160777 */ // Label 2253: @160777
     /*  160777 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(160876), // Rule ID 9504 //
     /*  160782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  160785 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160788 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160792 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160811 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160815 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160822 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  160822 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  160825 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160829 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  160834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160844 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  160847 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160851 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  160853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  160856 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  160858 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  160865 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  160870 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160875 */   // GIR_Coverage, 9504,
     /*  160875 */   GIR_EraseRootFromParent_Done,
     /*  160876 */ // Label 2254: @160876
     /*  160876 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(160945), // Rule ID 9656 //
     /*  160881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  160884 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160887 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160891 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160910 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160914 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160921 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  160921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  160931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  160936 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  160939 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  160943 */   GIR_RootConstrainSelectedInstOperands,
     /*  160944 */   // GIR_Coverage, 9656,
     /*  160944 */   GIR_EraseRootFromParent_Done,
     /*  160945 */ // Label 2255: @160945
     /*  160945 */ GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(161014), // Rule ID 9657 //
     /*  160950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  160953 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  160956 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  160960 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  160967 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  160975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  160979 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  160983 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  160990 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  160990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  160993 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  160995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161005 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161008 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161012 */   GIR_RootConstrainSelectedInstOperands,
     /*  161013 */   // GIR_Coverage, 9657,
     /*  161013 */   GIR_EraseRootFromParent_Done,
     /*  161014 */ // Label 2256: @161014
     /*  161014 */ GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(161083), // Rule ID 9658 //
     /*  161019 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  161022 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  161025 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161029 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161036 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161052 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161059 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161062 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161081 */   GIR_RootConstrainSelectedInstOperands,
     /*  161082 */   // GIR_Coverage, 9658,
     /*  161082 */   GIR_EraseRootFromParent_Done,
     /*  161083 */ // Label 2257: @161083
     /*  161083 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(161152), // Rule ID 9659 //
     /*  161088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  161091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  161094 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161098 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161105 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161128 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161143 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161146 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161150 */   GIR_RootConstrainSelectedInstOperands,
     /*  161151 */   // GIR_Coverage, 9659,
     /*  161151 */   GIR_EraseRootFromParent_Done,
     /*  161152 */ // Label 2258: @161152
     /*  161152 */ GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(161221), // Rule ID 9660 //
     /*  161157 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  161160 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  161163 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161167 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161174 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161186 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161190 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161197 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161197 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161200 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161215 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161219 */   GIR_RootConstrainSelectedInstOperands,
     /*  161220 */   // GIR_Coverage, 9660,
     /*  161220 */   GIR_EraseRootFromParent_Done,
     /*  161221 */ // Label 2259: @161221
     /*  161221 */ GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(161290), // Rule ID 9696 //
     /*  161226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  161229 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161232 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161236 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161243 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161255 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161259 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161266 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161266 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161269 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161284 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161288 */   GIR_RootConstrainSelectedInstOperands,
     /*  161289 */   // GIR_Coverage, 9696,
     /*  161289 */   GIR_EraseRootFromParent_Done,
     /*  161290 */ // Label 2260: @161290
     /*  161290 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(161359), // Rule ID 9697 //
     /*  161295 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  161298 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161301 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161305 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161312 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161335 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161338 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161350 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161353 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161357 */   GIR_RootConstrainSelectedInstOperands,
     /*  161358 */   // GIR_Coverage, 9697,
     /*  161358 */   GIR_EraseRootFromParent_Done,
     /*  161359 */ // Label 2261: @161359
     /*  161359 */ GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(161428), // Rule ID 9698 //
     /*  161364 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  161367 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161370 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161374 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161381 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161393 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161397 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161404 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161407 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161426 */   GIR_RootConstrainSelectedInstOperands,
     /*  161427 */   // GIR_Coverage, 9698,
     /*  161427 */   GIR_EraseRootFromParent_Done,
     /*  161428 */ // Label 2262: @161428
     /*  161428 */ GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(161497), // Rule ID 9699 //
     /*  161433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  161436 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161439 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161443 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161462 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161466 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161473 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161476 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161488 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161491 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161495 */   GIR_RootConstrainSelectedInstOperands,
     /*  161496 */   // GIR_Coverage, 9699,
     /*  161496 */   GIR_EraseRootFromParent_Done,
     /*  161497 */ // Label 2263: @161497
     /*  161497 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(161566), // Rule ID 9700 //
     /*  161502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  161505 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161508 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161512 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161535 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161542 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161542 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161545 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161557 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161560 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161564 */   GIR_RootConstrainSelectedInstOperands,
     /*  161565 */   // GIR_Coverage, 9700,
     /*  161565 */   GIR_EraseRootFromParent_Done,
     /*  161566 */ // Label 2264: @161566
     /*  161566 */ GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(161635), // Rule ID 9716 //
     /*  161571 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  161574 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161577 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161581 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  161588 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161600 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161604 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161611 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  161614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161633 */   GIR_RootConstrainSelectedInstOperands,
     /*  161634 */   // GIR_Coverage, 9716,
     /*  161634 */   GIR_EraseRootFromParent_Done,
     /*  161635 */ // Label 2265: @161635
     /*  161635 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(161704), // Rule ID 9717 //
     /*  161640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  161643 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161646 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161650 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  161657 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161669 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161680 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  161683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161695 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161698 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161702 */   GIR_RootConstrainSelectedInstOperands,
     /*  161703 */   // GIR_Coverage, 9717,
     /*  161703 */   GIR_EraseRootFromParent_Done,
     /*  161704 */ // Label 2266: @161704
     /*  161704 */ GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(161773), // Rule ID 9718 //
     /*  161709 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  161712 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161715 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161719 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  161726 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161734 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161738 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161742 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161749 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  161752 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161767 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161771 */   GIR_RootConstrainSelectedInstOperands,
     /*  161772 */   // GIR_Coverage, 9718,
     /*  161772 */   GIR_EraseRootFromParent_Done,
     /*  161773 */ // Label 2267: @161773
     /*  161773 */ GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(161842), // Rule ID 9719 //
     /*  161778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  161781 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161784 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161788 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  161795 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161811 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161818 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  161821 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161840 */   GIR_RootConstrainSelectedInstOperands,
     /*  161841 */   // GIR_Coverage, 9719,
     /*  161841 */   GIR_EraseRootFromParent_Done,
     /*  161842 */ // Label 2268: @161842
     /*  161842 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(161911), // Rule ID 9720 //
     /*  161847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  161850 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161853 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161857 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  161864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  161876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161887 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  161887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  161890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  161892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161902 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  161905 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161909 */   GIR_RootConstrainSelectedInstOperands,
     /*  161910 */   // GIR_Coverage, 9720,
     /*  161910 */   GIR_EraseRootFromParent_Done,
     /*  161911 */ // Label 2269: @161911
     /*  161911 */ GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(162010), // Rule ID 9796 //
     /*  161916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  161919 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  161922 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  161926 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  161933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  161941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  161945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  161949 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  161956 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  161956 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  161959 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  161963 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  161968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  161973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  161978 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  161981 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  161985 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  161987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  161990 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  161992 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  161999 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162004 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162009 */   // GIR_Coverage, 9796,
     /*  162009 */   GIR_EraseRootFromParent_Done,
     /*  162010 */ // Label 2270: @162010
     /*  162010 */ GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(162109), // Rule ID 9797 //
     /*  162015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  162018 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162021 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162025 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  162032 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162048 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162055 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162055 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162058 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  162062 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162077 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162080 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162084 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162086 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162089 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162091 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162098 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162103 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162108 */   // GIR_Coverage, 9797,
     /*  162108 */   GIR_EraseRootFromParent_Done,
     /*  162109 */ // Label 2271: @162109
     /*  162109 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(162208), // Rule ID 9798 //
     /*  162114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  162117 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162120 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162124 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  162131 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162147 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162154 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162154 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162157 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  162161 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162176 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162179 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162183 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162185 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162188 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162190 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162197 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162202 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162207 */   // GIR_Coverage, 9798,
     /*  162207 */   GIR_EraseRootFromParent_Done,
     /*  162208 */ // Label 2272: @162208
     /*  162208 */ GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(162307), // Rule ID 9799 //
     /*  162213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  162216 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162219 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162223 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  162230 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162242 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162246 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162253 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162253 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162256 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  162260 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162275 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162278 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162282 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162289 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162296 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162301 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162306 */   // GIR_Coverage, 9799,
     /*  162306 */   GIR_EraseRootFromParent_Done,
     /*  162307 */ // Label 2273: @162307
     /*  162307 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(162406), // Rule ID 9800 //
     /*  162312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  162315 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162318 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162322 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  162329 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162341 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162345 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162352 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162352 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162355 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  162359 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162374 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162377 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162381 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162383 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162386 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162388 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162395 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162400 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162405 */   // GIR_Coverage, 9800,
     /*  162405 */   GIR_EraseRootFromParent_Done,
     /*  162406 */ // Label 2274: @162406
     /*  162406 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(162505), // Rule ID 9816 //
     /*  162411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  162414 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162417 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162421 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  162428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162440 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162444 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162451 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162451 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162454 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  162458 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162473 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162476 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162480 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162482 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162485 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162487 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162494 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162499 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162504 */   // GIR_Coverage, 9816,
     /*  162504 */   GIR_EraseRootFromParent_Done,
     /*  162505 */ // Label 2275: @162505
     /*  162505 */ GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(162604), // Rule ID 9817 //
     /*  162510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  162513 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162516 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162520 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  162527 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162539 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162543 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162550 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162550 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162553 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  162557 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162572 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162575 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162579 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162586 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162593 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162598 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162603 */   // GIR_Coverage, 9817,
     /*  162603 */   GIR_EraseRootFromParent_Done,
     /*  162604 */ // Label 2276: @162604
     /*  162604 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(162703), // Rule ID 9818 //
     /*  162609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  162612 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162615 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162619 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  162626 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162638 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162642 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162649 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162649 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162652 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  162656 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162671 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162674 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162678 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162685 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162692 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162697 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162702 */   // GIR_Coverage, 9818,
     /*  162702 */   GIR_EraseRootFromParent_Done,
     /*  162703 */ // Label 2277: @162703
     /*  162703 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(162802), // Rule ID 9819 //
     /*  162708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  162711 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162714 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162718 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  162725 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162737 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162741 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162748 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162748 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162751 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  162755 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162770 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162773 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162777 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162782 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162784 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162791 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162796 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162801 */   // GIR_Coverage, 9819,
     /*  162801 */   GIR_EraseRootFromParent_Done,
     /*  162802 */ // Label 2278: @162802
     /*  162802 */ GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(162901), // Rule ID 9820 //
     /*  162807 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  162810 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162813 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162817 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  162824 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162832 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162836 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162840 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162847 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  162847 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  162850 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  162854 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  162859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162869 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  162872 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162876 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  162878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  162881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  162883 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  162890 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162895 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  162900 */   // GIR_Coverage, 9820,
     /*  162900 */   GIR_EraseRootFromParent_Done,
     /*  162901 */ // Label 2279: @162901
     /*  162901 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(162970), // Rule ID 9854 //
     /*  162906 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  162909 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162912 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  162923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  162931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  162935 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  162939 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  162946 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  162946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  162949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  162951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  162956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  162961 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  162964 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  162968 */   GIR_RootConstrainSelectedInstOperands,
     /*  162969 */   // GIR_Coverage, 9854,
     /*  162969 */   GIR_EraseRootFromParent_Done,
     /*  162970 */ // Label 2280: @162970
     /*  162970 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(163039), // Rule ID 9855 //
     /*  162975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  162978 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  162981 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  162985 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  162992 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163004 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163008 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163015 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  163018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163030 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163033 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163037 */   GIR_RootConstrainSelectedInstOperands,
     /*  163038 */   // GIR_Coverage, 9855,
     /*  163038 */   GIR_EraseRootFromParent_Done,
     /*  163039 */ // Label 2281: @163039
     /*  163039 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(163108), // Rule ID 9856 //
     /*  163044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  163047 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163050 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163054 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  163061 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163069 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163073 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163077 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163084 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163084 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  163087 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163099 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163102 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163106 */   GIR_RootConstrainSelectedInstOperands,
     /*  163107 */   // GIR_Coverage, 9856,
     /*  163107 */   GIR_EraseRootFromParent_Done,
     /*  163108 */ // Label 2282: @163108
     /*  163108 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(163177), // Rule ID 9857 //
     /*  163113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  163116 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163119 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163123 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  163130 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163142 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163146 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163153 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  163156 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163168 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163171 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163175 */   GIR_RootConstrainSelectedInstOperands,
     /*  163176 */   // GIR_Coverage, 9857,
     /*  163176 */   GIR_EraseRootFromParent_Done,
     /*  163177 */ // Label 2283: @163177
     /*  163177 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(163246), // Rule ID 9858 //
     /*  163182 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  163185 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163188 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163192 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  163199 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163211 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163215 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163222 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  163225 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163237 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163240 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163244 */   GIR_RootConstrainSelectedInstOperands,
     /*  163245 */   // GIR_Coverage, 9858,
     /*  163245 */   GIR_EraseRootFromParent_Done,
     /*  163246 */ // Label 2284: @163246
     /*  163246 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(163315), // Rule ID 9866 //
     /*  163251 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  163254 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163257 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163261 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  163268 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163291 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  163294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163306 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163309 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163313 */   GIR_RootConstrainSelectedInstOperands,
     /*  163314 */   // GIR_Coverage, 9866,
     /*  163314 */   GIR_EraseRootFromParent_Done,
     /*  163315 */ // Label 2285: @163315
     /*  163315 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(163384), // Rule ID 9867 //
     /*  163320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  163323 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163326 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163330 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  163337 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163349 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163353 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163360 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  163363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163382 */   GIR_RootConstrainSelectedInstOperands,
     /*  163383 */   // GIR_Coverage, 9867,
     /*  163383 */   GIR_EraseRootFromParent_Done,
     /*  163384 */ // Label 2286: @163384
     /*  163384 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(163453), // Rule ID 9868 //
     /*  163389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  163392 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163395 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163399 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  163406 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163418 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163422 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163429 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163429 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  163432 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163444 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163447 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163451 */   GIR_RootConstrainSelectedInstOperands,
     /*  163452 */   // GIR_Coverage, 9868,
     /*  163452 */   GIR_EraseRootFromParent_Done,
     /*  163453 */ // Label 2287: @163453
     /*  163453 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(163522), // Rule ID 9869 //
     /*  163458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  163461 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163464 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163468 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  163475 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163483 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163487 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163491 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163498 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163498 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  163501 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163513 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163516 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163520 */   GIR_RootConstrainSelectedInstOperands,
     /*  163521 */   // GIR_Coverage, 9869,
     /*  163521 */   GIR_EraseRootFromParent_Done,
     /*  163522 */ // Label 2288: @163522
     /*  163522 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(163591), // Rule ID 9870 //
     /*  163527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  163530 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  163533 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  163537 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  163544 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163556 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163560 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163567 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_16>><<P:Predicate_atomic_load_nonext_16_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  163567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  163570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163572 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163582 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163585 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163589 */   GIR_RootConstrainSelectedInstOperands,
     /*  163590 */   // GIR_Coverage, 9870,
     /*  163590 */   GIR_EraseRootFromParent_Done,
     /*  163591 */ // Label 2289: @163591
     /*  163591 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(163649), // Rule ID 9686 //
     /*  163596 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  163599 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163602 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163610 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  163614 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163618 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163625 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  163625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  163628 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163640 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163643 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163647 */   GIR_RootConstrainSelectedInstOperands,
     /*  163648 */   // GIR_Coverage, 9686,
     /*  163648 */   GIR_EraseRootFromParent_Done,
     /*  163649 */ // Label 2290: @163649
     /*  163649 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(163707), // Rule ID 9687 //
     /*  163654 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  163657 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163660 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163668 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  163672 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163676 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163683 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  163683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  163686 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163698 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163701 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163705 */   GIR_RootConstrainSelectedInstOperands,
     /*  163706 */   // GIR_Coverage, 9687,
     /*  163706 */   GIR_EraseRootFromParent_Done,
     /*  163707 */ // Label 2291: @163707
     /*  163707 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(163765), // Rule ID 9688 //
     /*  163712 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  163715 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163726 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  163730 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163734 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163741 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  163741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  163744 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163756 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163759 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163763 */   GIR_RootConstrainSelectedInstOperands,
     /*  163764 */   // GIR_Coverage, 9688,
     /*  163764 */   GIR_EraseRootFromParent_Done,
     /*  163765 */ // Label 2292: @163765
     /*  163765 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(163823), // Rule ID 9689 //
     /*  163770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  163773 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163776 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163784 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  163788 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163792 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163799 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  163799 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  163802 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163817 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163821 */   GIR_RootConstrainSelectedInstOperands,
     /*  163822 */   // GIR_Coverage, 9689,
     /*  163822 */   GIR_EraseRootFromParent_Done,
     /*  163823 */ // Label 2293: @163823
     /*  163823 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(163881), // Rule ID 9690 //
     /*  163828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  163831 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  163846 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163850 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163857 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  163857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  163860 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  163862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163872 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  163875 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163879 */   GIR_RootConstrainSelectedInstOperands,
     /*  163880 */   // GIR_Coverage, 9690,
     /*  163880 */   GIR_EraseRootFromParent_Done,
     /*  163881 */ // Label 2294: @163881
     /*  163881 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(163969), // Rule ID 9786 //
     /*  163886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  163889 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163892 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163904 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163908 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  163915 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  163915 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  163918 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  163922 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  163927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  163932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  163937 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  163940 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  163944 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  163946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  163949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  163951 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  163958 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163963 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  163968 */   // GIR_Coverage, 9786,
     /*  163968 */   GIR_EraseRootFromParent_Done,
     /*  163969 */ // Label 2295: @163969
     /*  163969 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(164057), // Rule ID 9787 //
     /*  163974 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  163977 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  163980 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  163988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  163992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  163996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164003 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  164003 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  164006 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  164010 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  164015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164025 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  164028 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164032 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  164034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  164037 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  164039 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  164046 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164051 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  164056 */   // GIR_Coverage, 9787,
     /*  164056 */   GIR_EraseRootFromParent_Done,
     /*  164057 */ // Label 2296: @164057
     /*  164057 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(164145), // Rule ID 9788 //
     /*  164062 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  164065 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164080 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164084 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164091 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  164091 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  164094 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  164098 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  164103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164113 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  164116 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164120 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  164122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  164125 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  164127 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  164134 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164139 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  164144 */   // GIR_Coverage, 9788,
     /*  164144 */   GIR_EraseRootFromParent_Done,
     /*  164145 */ // Label 2297: @164145
     /*  164145 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(164233), // Rule ID 9789 //
     /*  164150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  164153 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164156 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164168 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164172 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164179 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  164179 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  164182 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  164186 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  164191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164201 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  164204 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164208 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  164210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  164213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  164215 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  164222 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164227 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  164232 */   // GIR_Coverage, 9789,
     /*  164232 */   GIR_EraseRootFromParent_Done,
     /*  164233 */ // Label 2298: @164233
     /*  164233 */ GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(164321), // Rule ID 9790 //
     /*  164238 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  164241 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164244 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164252 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164256 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164260 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164267 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  164267 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  164270 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  164274 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  164279 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164289 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  164292 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164296 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  164298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  164301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  164303 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  164310 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164315 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  164320 */   // GIR_Coverage, 9790,
     /*  164320 */   GIR_EraseRootFromParent_Done,
     /*  164321 */ // Label 2299: @164321
     /*  164321 */ GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(164379), // Rule ID 9848 //
     /*  164326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  164329 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164332 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164344 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164355 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  164355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  164358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  164360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  164373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164377 */   GIR_RootConstrainSelectedInstOperands,
     /*  164378 */   // GIR_Coverage, 9848,
     /*  164378 */   GIR_EraseRootFromParent_Done,
     /*  164379 */ // Label 2300: @164379
     /*  164379 */ GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(164437), // Rule ID 9849 //
     /*  164384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  164387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164402 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164413 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  164413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  164416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  164418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164428 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  164431 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164435 */   GIR_RootConstrainSelectedInstOperands,
     /*  164436 */   // GIR_Coverage, 9849,
     /*  164436 */   GIR_EraseRootFromParent_Done,
     /*  164437 */ // Label 2301: @164437
     /*  164437 */ GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(164495), // Rule ID 9850 //
     /*  164442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  164445 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164448 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164471 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  164471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  164474 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  164476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164486 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  164489 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164493 */   GIR_RootConstrainSelectedInstOperands,
     /*  164494 */   // GIR_Coverage, 9850,
     /*  164494 */   GIR_EraseRootFromParent_Done,
     /*  164495 */ // Label 2302: @164495
     /*  164495 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(164553), // Rule ID 9851 //
     /*  164500 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  164503 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164506 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164522 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164529 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  164529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  164532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  164534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164544 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  164547 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164551 */   GIR_RootConstrainSelectedInstOperands,
     /*  164552 */   // GIR_Coverage, 9851,
     /*  164552 */   GIR_EraseRootFromParent_Done,
     /*  164553 */ // Label 2303: @164553
     /*  164553 */ GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(164611), // Rule ID 9852 //
     /*  164558 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  164561 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164564 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  164572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  164576 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164580 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  164587 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  164587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SHORT_D16_t16),
     /*  164590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  164592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  164597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  164602 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  164605 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164609 */   GIR_RootConstrainSelectedInstOperands,
     /*  164610 */   // GIR_Coverage, 9852,
     /*  164610 */   GIR_EraseRootFromParent_Done,
     /*  164611 */ // Label 2304: @164611
     /*  164611 */ GIM_Reject,
     /*  164612 */ // Label 1127: @164612
     /*  164612 */ GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(164681), // Rule ID 8642 //
     /*  164617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  164620 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164623 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  164627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  164631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164635 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  164639 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  164643 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  164650 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  164650 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  164653 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  164655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  164660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  164665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  164670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  164675 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164679 */   GIR_RootConstrainSelectedInstOperands,
     /*  164680 */   // GIR_Coverage, 8642,
     /*  164680 */   GIR_EraseRootFromParent_Done,
     /*  164681 */ // Label 2305: @164681
     /*  164681 */ GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(164750), // Rule ID 8695 //
     /*  164686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  164689 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164692 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  164696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  164700 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164704 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  164708 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  164712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  164719 */   // (ld:{ *:[f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  164719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  164722 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  164724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  164729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  164734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  164739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  164744 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164748 */   GIR_RootConstrainSelectedInstOperands,
     /*  164749 */   // GIR_Coverage, 8695,
     /*  164749 */   GIR_EraseRootFromParent_Done,
     /*  164750 */ // Label 2306: @164750
     /*  164750 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(164822), // Rule ID 8651 //
     /*  164755 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  164758 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164761 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  164765 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  164772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  164776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164780 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
     /*  164784 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  164791 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  164791 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
     /*  164794 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  164796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  164801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  164806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  164811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  164816 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164820 */   GIR_RootConstrainSelectedInstOperands,
     /*  164821 */   // GIR_Coverage, 8651,
     /*  164821 */   GIR_EraseRootFromParent_Done,
     /*  164822 */ // Label 2307: @164822
     /*  164822 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(164894), // Rule ID 8666 //
     /*  164827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  164830 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164833 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  164837 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  164844 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  164848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164852 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
     /*  164856 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  164863 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  164863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
     /*  164866 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  164868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  164873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  164878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  164883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  164888 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164892 */   GIR_RootConstrainSelectedInstOperands,
     /*  164893 */   // GIR_Coverage, 8666,
     /*  164893 */   GIR_EraseRootFromParent_Done,
     /*  164894 */ // Label 2308: @164894
     /*  164894 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(164959), // Rule ID 8689 //
     /*  164899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  164902 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164905 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  164909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  164913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164917 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  164921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  164928 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  164928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  164931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  164933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  164938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  164943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  164948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  164953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  164957 */   GIR_RootConstrainSelectedInstOperands,
     /*  164958 */   // GIR_Coverage, 8689,
     /*  164958 */   GIR_EraseRootFromParent_Done,
     /*  164959 */ // Label 2309: @164959
     /*  164959 */ GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(165024), // Rule ID 8701 //
     /*  164964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  164967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  164970 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  164974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  164978 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  164982 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  164986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  164993 */   // (ld:{ *:[f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  164993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  164996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  164998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  165008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  165013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  165018 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165022 */   GIR_RootConstrainSelectedInstOperands,
     /*  165023 */   // GIR_Coverage, 8701,
     /*  165023 */   GIR_EraseRootFromParent_Done,
     /*  165024 */ // Label 2310: @165024
     /*  165024 */ GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(165086), // Rule ID 8638 //
     /*  165029 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  165032 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165035 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165039 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165043 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165047 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165051 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  165062 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  165065 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165077 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165080 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165084 */   GIR_RootConstrainSelectedInstOperands,
     /*  165085 */   // GIR_Coverage, 8638,
     /*  165085 */   GIR_EraseRootFromParent_Done,
     /*  165086 */ // Label 2311: @165086
     /*  165086 */ GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(165148), // Rule ID 8639 //
     /*  165091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  165094 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165097 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165109 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165113 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165117 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  165124 */   // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  165127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165146 */   GIR_RootConstrainSelectedInstOperands,
     /*  165147 */   // GIR_Coverage, 8639,
     /*  165147 */   GIR_EraseRootFromParent_Done,
     /*  165148 */ // Label 2312: @165148
     /*  165148 */ GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(165210), // Rule ID 8691 //
     /*  165153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  165156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165159 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165167 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165171 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165175 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165179 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  165186 */   // (ld:{ *:[f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165186 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  165189 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165201 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165204 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165208 */   GIR_RootConstrainSelectedInstOperands,
     /*  165209 */   // GIR_Coverage, 8691,
     /*  165209 */   GIR_EraseRootFromParent_Done,
     /*  165210 */ // Label 2313: @165210
     /*  165210 */ GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(165272), // Rule ID 8692 //
     /*  165215 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  165218 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165221 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165229 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165233 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165237 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165241 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  165248 */   // (ld:{ *:[f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165248 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  165251 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165263 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165266 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165270 */   GIR_RootConstrainSelectedInstOperands,
     /*  165271 */   // GIR_Coverage, 8692,
     /*  165271 */   GIR_EraseRootFromParent_Done,
     /*  165272 */ // Label 2314: @165272
     /*  165272 */ GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(165337), // Rule ID 8649 //
     /*  165277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  165280 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165283 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165287 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  165294 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165298 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165302 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
     /*  165306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  165313 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
     /*  165316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165328 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165331 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165335 */   GIR_RootConstrainSelectedInstOperands,
     /*  165336 */   // GIR_Coverage, 8649,
     /*  165336 */   GIR_EraseRootFromParent_Done,
     /*  165337 */ // Label 2315: @165337
     /*  165337 */ GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(165402), // Rule ID 8664 //
     /*  165342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  165345 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165348 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165352 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  165359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165367 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
     /*  165371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  165378 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
     /*  165381 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165393 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165396 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165400 */   GIR_RootConstrainSelectedInstOperands,
     /*  165401 */   // GIR_Coverage, 8664,
     /*  165401 */   GIR_EraseRootFromParent_Done,
     /*  165402 */ // Label 2316: @165402
     /*  165402 */ GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(165457), // Rule ID 8685 //
     /*  165407 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165410 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165418 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165422 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165426 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  165433 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  165436 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165448 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165451 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165455 */   GIR_RootConstrainSelectedInstOperands,
     /*  165456 */   // GIR_Coverage, 8685,
     /*  165456 */   GIR_EraseRootFromParent_Done,
     /*  165457 */ // Label 2317: @165457
     /*  165457 */ GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(165515), // Rule ID 8686 //
     /*  165462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  165465 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165468 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165476 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165480 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165484 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  165491 */   // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  165494 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165506 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165509 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165513 */   GIR_RootConstrainSelectedInstOperands,
     /*  165514 */   // GIR_Coverage, 8686,
     /*  165514 */   GIR_EraseRootFromParent_Done,
     /*  165515 */ // Label 2318: @165515
     /*  165515 */ GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(165570), // Rule ID 8697 //
     /*  165520 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165523 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165535 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165539 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  165546 */   // (ld:{ *:[f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  165549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165561 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165564 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165568 */   GIR_RootConstrainSelectedInstOperands,
     /*  165569 */   // GIR_Coverage, 8697,
     /*  165569 */   GIR_EraseRootFromParent_Done,
     /*  165570 */ // Label 2319: @165570
     /*  165570 */ GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(165628), // Rule ID 8698 //
     /*  165575 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  165578 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165581 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165585 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165589 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165593 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165597 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  165604 */   // (ld:{ *:[f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  165604 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  165607 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  165619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165622 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165626 */   GIR_RootConstrainSelectedInstOperands,
     /*  165627 */   // GIR_Coverage, 8698,
     /*  165627 */   GIR_EraseRootFromParent_Done,
     /*  165628 */ // Label 2320: @165628
     /*  165628 */ GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(165690), // Rule ID 8640 //
     /*  165633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  165636 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165639 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165643 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165647 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165651 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165655 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  165666 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  165666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  165669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  165681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165688 */   GIR_RootConstrainSelectedInstOperands,
     /*  165689 */   // GIR_Coverage, 8640,
     /*  165689 */   GIR_EraseRootFromParent_Done,
     /*  165690 */ // Label 2321: @165690
     /*  165690 */ GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(165757), // Rule ID 8641 //
     /*  165695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  165698 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165701 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165709 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165713 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165717 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165721 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  165728 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  165728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  165731 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  165743 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  165751 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165755 */   GIR_RootConstrainSelectedInstOperands,
     /*  165756 */   // GIR_Coverage, 8641,
     /*  165756 */   GIR_EraseRootFromParent_Done,
     /*  165757 */ // Label 2322: @165757
     /*  165757 */ GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(165819), // Rule ID 8693 //
     /*  165762 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  165765 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165768 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165780 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165784 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165788 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  165795 */   // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  165795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  165798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  165810 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165813 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165817 */   GIR_RootConstrainSelectedInstOperands,
     /*  165818 */   // GIR_Coverage, 8693,
     /*  165818 */   GIR_EraseRootFromParent_Done,
     /*  165819 */ // Label 2323: @165819
     /*  165819 */ GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(165886), // Rule ID 8694 //
     /*  165824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  165827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165830 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  165842 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165846 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165850 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  165857 */   // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  165857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  165860 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  165867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  165872 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165875 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  165880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165884 */   GIR_RootConstrainSelectedInstOperands,
     /*  165885 */   // GIR_Coverage, 8694,
     /*  165885 */   GIR_EraseRootFromParent_Done,
     /*  165886 */ // Label 2324: @165886
     /*  165886 */ GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(165940), // Rule ID 8643 //
     /*  165891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  165894 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165897 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165905 */   // MIs[0] sbase
     /*  165905 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  165909 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  165913 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165917 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165921 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  165921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  165924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165926 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  165928 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165931 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165934 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165938 */   GIR_RootConstrainSelectedInstOperands,
     /*  165939 */   // GIR_Coverage, 8643,
     /*  165939 */   GIR_EraseRootFromParent_Done,
     /*  165940 */ // Label 2325: @165940
     /*  165940 */ GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(165994), // Rule ID 8696 //
     /*  165945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  165948 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  165951 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  165955 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  165959 */   // MIs[0] sbase
     /*  165959 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  165963 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  165967 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  165971 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  165975 */   // (ld:{ *:[f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  165975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  165978 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  165980 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  165982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165985 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  165988 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  165992 */   GIR_RootConstrainSelectedInstOperands,
     /*  165993 */   // GIR_Coverage, 8696,
     /*  165993 */   GIR_EraseRootFromParent_Done,
     /*  165994 */ // Label 2326: @165994
     /*  165994 */ GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(166064), // Rule ID 8650 //
     /*  165999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  166002 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166005 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166009 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166020 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166024 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
     /*  166028 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  166035 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  166035 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
     /*  166038 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  166045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166050 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  166058 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166062 */   GIR_RootConstrainSelectedInstOperands,
     /*  166063 */   // GIR_Coverage, 8650,
     /*  166063 */   GIR_EraseRootFromParent_Done,
     /*  166064 */ // Label 2327: @166064
     /*  166064 */ GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(166134), // Rule ID 8665 //
     /*  166069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  166072 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166075 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166079 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  166086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166094 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
     /*  166098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  166105 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  166105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
     /*  166108 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  166115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166120 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  166128 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166132 */   GIR_RootConstrainSelectedInstOperands,
     /*  166133 */   // GIR_Coverage, 8665,
     /*  166133 */   GIR_EraseRootFromParent_Done,
     /*  166134 */ // Label 2328: @166134
     /*  166134 */ GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(166191), // Rule ID 8652 //
     /*  166139 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  166142 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166145 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166149 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166160 */   // MIs[0] sbase
     /*  166160 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  166164 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  166168 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
     /*  166172 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  166172 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
     /*  166175 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166177 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  166179 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166182 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166185 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166189 */   GIR_RootConstrainSelectedInstOperands,
     /*  166190 */   // GIR_Coverage, 8652,
     /*  166190 */   GIR_EraseRootFromParent_Done,
     /*  166191 */ // Label 2329: @166191
     /*  166191 */ GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(166248), // Rule ID 8667 //
     /*  166196 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  166199 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166202 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  166213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166217 */   // MIs[0] sbase
     /*  166217 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  166221 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  166225 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
     /*  166229 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  166229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
     /*  166232 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166234 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  166236 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166246 */   GIR_RootConstrainSelectedInstOperands,
     /*  166247 */   // GIR_Coverage, 8667,
     /*  166247 */   GIR_EraseRootFromParent_Done,
     /*  166248 */ // Label 2330: @166248
     /*  166248 */ GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(166306), // Rule ID 8687 //
     /*  166253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  166256 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166259 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166271 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  166275 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  166282 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  166282 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  166285 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  166292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166300 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166304 */   GIR_RootConstrainSelectedInstOperands,
     /*  166305 */   // GIR_Coverage, 8687,
     /*  166305 */   GIR_EraseRootFromParent_Done,
     /*  166306 */ // Label 2331: @166306
     /*  166306 */ GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(166369), // Rule ID 8688 //
     /*  166311 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  166314 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166317 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166325 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166329 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  166333 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  166340 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  166340 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  166343 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  166350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166355 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  166363 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166367 */   GIR_RootConstrainSelectedInstOperands,
     /*  166368 */   // GIR_Coverage, 8688,
     /*  166368 */   GIR_EraseRootFromParent_Done,
     /*  166369 */ // Label 2332: @166369
     /*  166369 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(166427), // Rule ID 8699 //
     /*  166374 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  166377 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166380 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166384 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166388 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166392 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  166396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  166403 */   // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  166403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  166406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  166413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166425 */   GIR_RootConstrainSelectedInstOperands,
     /*  166426 */   // GIR_Coverage, 8699,
     /*  166426 */   GIR_EraseRootFromParent_Done,
     /*  166427 */ // Label 2333: @166427
     /*  166427 */ GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(166490), // Rule ID 8700 //
     /*  166432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  166435 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166438 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166450 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  166454 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  166461 */   // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  166461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  166464 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  166471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166476 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  166484 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166488 */   GIR_RootConstrainSelectedInstOperands,
     /*  166489 */   // GIR_Coverage, 8700,
     /*  166489 */   GIR_EraseRootFromParent_Done,
     /*  166490 */ // Label 2334: @166490
     /*  166490 */ GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(166537), // Rule ID 8690 //
     /*  166495 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166498 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166506 */   // MIs[0] sbase
     /*  166506 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  166510 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  166514 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  166518 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  166518 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  166521 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166523 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  166525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166531 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166535 */   GIR_RootConstrainSelectedInstOperands,
     /*  166536 */   // GIR_Coverage, 8690,
     /*  166536 */   GIR_EraseRootFromParent_Done,
     /*  166537 */ // Label 2335: @166537
     /*  166537 */ GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(166584), // Rule ID 8702 //
     /*  166542 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166545 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  166553 */   // MIs[0] sbase
     /*  166553 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  166557 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  166561 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  166565 */   // (ld:{ *:[f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  166565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  166568 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  166570 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  166572 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166575 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166578 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166582 */   GIR_RootConstrainSelectedInstOperands,
     /*  166583 */   // GIR_Coverage, 8702,
     /*  166583 */   GIR_EraseRootFromParent_Done,
     /*  166584 */ // Label 2336: @166584
     /*  166584 */ GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(166658), // Rule ID 24996 //
     /*  166589 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  166592 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166595 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166599 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166606 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  166611 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  166615 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166619 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  166626 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  166626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  166629 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  166631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  166636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  166646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166656 */   GIR_RootConstrainSelectedInstOperands,
     /*  166657 */   // GIR_Coverage, 24996,
     /*  166657 */   GIR_EraseRootFromParent_Done,
     /*  166658 */ // Label 2337: @166658
     /*  166658 */ GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(166732), // Rule ID 24997 //
     /*  166663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  166666 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166669 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166673 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  166685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  166689 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166693 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  166700 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  166700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  166703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  166705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  166710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  166720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166730 */   GIR_RootConstrainSelectedInstOperands,
     /*  166731 */   // GIR_Coverage, 24997,
     /*  166731 */   GIR_EraseRootFromParent_Done,
     /*  166732 */ // Label 2338: @166732
     /*  166732 */ GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(166806), // Rule ID 24998 //
     /*  166737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  166740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166743 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  166759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  166763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  166774 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  166774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  166777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  166779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  166784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  166794 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166800 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166804 */   GIR_RootConstrainSelectedInstOperands,
     /*  166805 */   // GIR_Coverage, 24998,
     /*  166805 */   GIR_EraseRootFromParent_Done,
     /*  166806 */ // Label 2339: @166806
     /*  166806 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(166880), // Rule ID 24999 //
     /*  166811 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  166814 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166817 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166821 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166828 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  166833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  166837 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166841 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  166848 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  166848 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  166851 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  166853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  166858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  166868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166878 */   GIR_RootConstrainSelectedInstOperands,
     /*  166879 */   // GIR_Coverage, 24999,
     /*  166879 */   GIR_EraseRootFromParent_Done,
     /*  166880 */ // Label 2340: @166880
     /*  166880 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(166954), // Rule ID 25000 //
     /*  166885 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  166888 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166891 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166895 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166902 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  166907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  166911 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166915 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  166922 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  166922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  166925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  166927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  166932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  166937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  166942 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166945 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  166948 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  166952 */   GIR_RootConstrainSelectedInstOperands,
     /*  166953 */   // GIR_Coverage, 25000,
     /*  166953 */   GIR_EraseRootFromParent_Done,
     /*  166954 */ // Label 2341: @166954
     /*  166954 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(167028), // Rule ID 25006 //
     /*  166959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  166962 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  166965 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  166969 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  166976 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  166981 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  166985 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  166989 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  166996 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  166996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  166999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167026 */   GIR_RootConstrainSelectedInstOperands,
     /*  167027 */   // GIR_Coverage, 25006,
     /*  167027 */   GIR_EraseRootFromParent_Done,
     /*  167028 */ // Label 2342: @167028
     /*  167028 */ GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(167102), // Rule ID 25007 //
     /*  167033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  167036 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167039 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167043 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  167050 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167059 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167063 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167070 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167070 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  167073 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167090 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167093 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167096 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167100 */   GIR_RootConstrainSelectedInstOperands,
     /*  167101 */   // GIR_Coverage, 25007,
     /*  167101 */   GIR_EraseRootFromParent_Done,
     /*  167102 */ // Label 2343: @167102
     /*  167102 */ GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(167176), // Rule ID 25008 //
     /*  167107 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  167110 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167113 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167117 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  167124 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167133 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167137 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167144 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  167147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167164 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167170 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167174 */   GIR_RootConstrainSelectedInstOperands,
     /*  167175 */   // GIR_Coverage, 25008,
     /*  167175 */   GIR_EraseRootFromParent_Done,
     /*  167176 */ // Label 2344: @167176
     /*  167176 */ GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(167250), // Rule ID 25009 //
     /*  167181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  167184 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167187 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167191 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  167198 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167207 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167211 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167218 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167218 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  167221 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167241 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167244 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167248 */   GIR_RootConstrainSelectedInstOperands,
     /*  167249 */   // GIR_Coverage, 25009,
     /*  167249 */   GIR_EraseRootFromParent_Done,
     /*  167250 */ // Label 2345: @167250
     /*  167250 */ GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(167324), // Rule ID 25010 //
     /*  167255 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  167258 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167261 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167265 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  167272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167292 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  167295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167322 */   GIR_RootConstrainSelectedInstOperands,
     /*  167323 */   // GIR_Coverage, 25010,
     /*  167323 */   GIR_EraseRootFromParent_Done,
     /*  167324 */ // Label 2346: @167324
     /*  167324 */ GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(167398), // Rule ID 25116 //
     /*  167329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  167332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167335 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167339 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167355 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167359 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167366 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  167369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167386 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167389 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167392 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167396 */   GIR_RootConstrainSelectedInstOperands,
     /*  167397 */   // GIR_Coverage, 25116,
     /*  167397 */   GIR_EraseRootFromParent_Done,
     /*  167398 */ // Label 2347: @167398
     /*  167398 */ GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(167472), // Rule ID 25117 //
     /*  167403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  167406 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167409 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167413 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167420 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167425 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167429 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167433 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167440 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167440 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  167443 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167460 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167463 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167466 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167470 */   GIR_RootConstrainSelectedInstOperands,
     /*  167471 */   // GIR_Coverage, 25117,
     /*  167471 */   GIR_EraseRootFromParent_Done,
     /*  167472 */ // Label 2348: @167472
     /*  167472 */ GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(167546), // Rule ID 25118 //
     /*  167477 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  167480 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167483 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167487 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167494 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167514 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  167517 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167534 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167537 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167540 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167544 */   GIR_RootConstrainSelectedInstOperands,
     /*  167545 */   // GIR_Coverage, 25118,
     /*  167545 */   GIR_EraseRootFromParent_Done,
     /*  167546 */ // Label 2349: @167546
     /*  167546 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(167620), // Rule ID 25119 //
     /*  167551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  167554 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167557 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167561 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167568 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167577 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167581 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167588 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167588 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  167591 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167608 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167611 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167614 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167618 */   GIR_RootConstrainSelectedInstOperands,
     /*  167619 */   // GIR_Coverage, 25119,
     /*  167619 */   GIR_EraseRootFromParent_Done,
     /*  167620 */ // Label 2350: @167620
     /*  167620 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(167694), // Rule ID 25120 //
     /*  167625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  167628 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167631 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167635 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167642 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167651 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167655 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167662 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167662 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  167665 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167682 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167685 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167688 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167692 */   GIR_RootConstrainSelectedInstOperands,
     /*  167693 */   // GIR_Coverage, 25120,
     /*  167693 */   GIR_EraseRootFromParent_Done,
     /*  167694 */ // Label 2351: @167694
     /*  167694 */ GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(167768), // Rule ID 25126 //
     /*  167699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  167702 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167705 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167709 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167716 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167721 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167725 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167729 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167736 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167736 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  167739 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167756 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167759 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167762 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167766 */   GIR_RootConstrainSelectedInstOperands,
     /*  167767 */   // GIR_Coverage, 25126,
     /*  167767 */   GIR_EraseRootFromParent_Done,
     /*  167768 */ // Label 2352: @167768
     /*  167768 */ GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(167842), // Rule ID 25127 //
     /*  167773 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  167776 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167779 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167783 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167790 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167810 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  167813 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167830 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167840 */   GIR_RootConstrainSelectedInstOperands,
     /*  167841 */   // GIR_Coverage, 25127,
     /*  167841 */   GIR_EraseRootFromParent_Done,
     /*  167842 */ // Label 2353: @167842
     /*  167842 */ GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(167916), // Rule ID 25128 //
     /*  167847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  167850 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167853 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167857 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167877 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167884 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  167887 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167904 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167907 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167910 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167914 */   GIR_RootConstrainSelectedInstOperands,
     /*  167915 */   // GIR_Coverage, 25128,
     /*  167915 */   GIR_EraseRootFromParent_Done,
     /*  167916 */ // Label 2354: @167916
     /*  167916 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(167990), // Rule ID 25129 //
     /*  167921 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  167924 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  167927 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  167931 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  167938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  167943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  167947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  167951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  167958 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  167958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  167961 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  167963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  167968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  167973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  167978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  167984 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  167988 */   GIR_RootConstrainSelectedInstOperands,
     /*  167989 */   // GIR_Coverage, 25129,
     /*  167989 */   GIR_EraseRootFromParent_Done,
     /*  167990 */ // Label 2355: @167990
     /*  167990 */ GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(168064), // Rule ID 25130 //
     /*  167995 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  167998 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168001 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  168005 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  168012 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168021 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168025 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168032 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168032 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  168035 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168052 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168055 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168058 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168062 */   GIR_RootConstrainSelectedInstOperands,
     /*  168063 */   // GIR_Coverage, 25130,
     /*  168063 */   GIR_EraseRootFromParent_Done,
     /*  168064 */ // Label 2356: @168064
     /*  168064 */ GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(168127), // Rule ID 25176 //
     /*  168069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  168072 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168075 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168088 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168095 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168098 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168115 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168118 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168121 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168125 */   GIR_RootConstrainSelectedInstOperands,
     /*  168126 */   // GIR_Coverage, 25176,
     /*  168126 */   GIR_EraseRootFromParent_Done,
     /*  168127 */ // Label 2357: @168127
     /*  168127 */ GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(168190), // Rule ID 25177 //
     /*  168132 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  168135 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168138 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168147 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168151 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168158 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168161 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168178 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168181 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168184 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168188 */   GIR_RootConstrainSelectedInstOperands,
     /*  168189 */   // GIR_Coverage, 25177,
     /*  168189 */   GIR_EraseRootFromParent_Done,
     /*  168190 */ // Label 2358: @168190
     /*  168190 */ GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(168253), // Rule ID 25178 //
     /*  168195 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  168198 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168201 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168210 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168214 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168221 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168241 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168251 */   GIR_RootConstrainSelectedInstOperands,
     /*  168252 */   // GIR_Coverage, 25178,
     /*  168252 */   GIR_EraseRootFromParent_Done,
     /*  168253 */ // Label 2359: @168253
     /*  168253 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(168316), // Rule ID 25179 //
     /*  168258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  168261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168277 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168284 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168304 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168310 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168314 */   GIR_RootConstrainSelectedInstOperands,
     /*  168315 */   // GIR_Coverage, 25179,
     /*  168315 */   GIR_EraseRootFromParent_Done,
     /*  168316 */ // Label 2360: @168316
     /*  168316 */ GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(168379), // Rule ID 25180 //
     /*  168321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  168324 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168327 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168332 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168336 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168340 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168347 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168350 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168367 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168377 */   GIR_RootConstrainSelectedInstOperands,
     /*  168378 */   // GIR_Coverage, 25180,
     /*  168378 */   GIR_EraseRootFromParent_Done,
     /*  168379 */ // Label 2361: @168379
     /*  168379 */ GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(168442), // Rule ID 25186 //
     /*  168384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  168387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168399 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168403 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168410 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168410 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  168413 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168430 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168433 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168436 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168440 */   GIR_RootConstrainSelectedInstOperands,
     /*  168441 */   // GIR_Coverage, 25186,
     /*  168441 */   GIR_EraseRootFromParent_Done,
     /*  168442 */ // Label 2362: @168442
     /*  168442 */ GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(168505), // Rule ID 25187 //
     /*  168447 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  168450 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168453 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168462 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168466 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168473 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  168476 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168499 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168503 */   GIR_RootConstrainSelectedInstOperands,
     /*  168504 */   // GIR_Coverage, 25187,
     /*  168504 */   GIR_EraseRootFromParent_Done,
     /*  168505 */ // Label 2363: @168505
     /*  168505 */ GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(168568), // Rule ID 25188 //
     /*  168510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  168513 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168516 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168521 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168525 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168529 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168536 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168536 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  168539 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168541 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168556 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168559 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168562 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168566 */   GIR_RootConstrainSelectedInstOperands,
     /*  168567 */   // GIR_Coverage, 25188,
     /*  168567 */   GIR_EraseRootFromParent_Done,
     /*  168568 */ // Label 2364: @168568
     /*  168568 */ GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(168631), // Rule ID 25189 //
     /*  168573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  168576 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168588 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168592 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168599 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  168602 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168625 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168629 */   GIR_RootConstrainSelectedInstOperands,
     /*  168630 */   // GIR_Coverage, 25189,
     /*  168630 */   GIR_EraseRootFromParent_Done,
     /*  168631 */ // Label 2365: @168631
     /*  168631 */ GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(168694), // Rule ID 25190 //
     /*  168636 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  168639 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168642 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168651 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168655 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168662 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168662 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  168665 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168682 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168685 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168688 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168692 */   GIR_RootConstrainSelectedInstOperands,
     /*  168693 */   // GIR_Coverage, 25190,
     /*  168693 */   GIR_EraseRootFromParent_Done,
     /*  168694 */ // Label 2366: @168694
     /*  168694 */ GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(168757), // Rule ID 25196 //
     /*  168699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  168702 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168705 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168714 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168718 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168725 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168725 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168728 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168745 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168748 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168751 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168755 */   GIR_RootConstrainSelectedInstOperands,
     /*  168756 */   // GIR_Coverage, 25196,
     /*  168756 */   GIR_EraseRootFromParent_Done,
     /*  168757 */ // Label 2367: @168757
     /*  168757 */ GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(168820), // Rule ID 25197 //
     /*  168762 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  168765 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168768 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168777 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168781 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168788 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168788 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168791 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168808 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168814 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168818 */   GIR_RootConstrainSelectedInstOperands,
     /*  168819 */   // GIR_Coverage, 25197,
     /*  168819 */   GIR_EraseRootFromParent_Done,
     /*  168820 */ // Label 2368: @168820
     /*  168820 */ GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(168883), // Rule ID 25198 //
     /*  168825 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  168828 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168851 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168854 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168874 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168877 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168881 */   GIR_RootConstrainSelectedInstOperands,
     /*  168882 */   // GIR_Coverage, 25198,
     /*  168882 */   GIR_EraseRootFromParent_Done,
     /*  168883 */ // Label 2369: @168883
     /*  168883 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(168946), // Rule ID 25199 //
     /*  168888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  168891 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168894 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168899 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168903 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168907 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168914 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168917 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168934 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168937 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  168940 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  168944 */   GIR_RootConstrainSelectedInstOperands,
     /*  168945 */   // GIR_Coverage, 25199,
     /*  168945 */   GIR_EraseRootFromParent_Done,
     /*  168946 */ // Label 2370: @168946
     /*  168946 */ GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(169009), // Rule ID 25200 //
     /*  168951 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  168954 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  168957 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  168962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  168966 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  168970 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  168977 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  168977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  168980 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  168982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  168987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  168992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  168997 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169000 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169007 */   GIR_RootConstrainSelectedInstOperands,
     /*  169008 */   // GIR_Coverage, 25200,
     /*  169008 */   GIR_EraseRootFromParent_Done,
     /*  169009 */ // Label 2371: @169009
     /*  169009 */ GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(169072), // Rule ID 25206 //
     /*  169014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  169017 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169020 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169025 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169029 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169033 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  169040 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  169040 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  169043 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  169045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  169050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  169055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169063 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169066 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169070 */   GIR_RootConstrainSelectedInstOperands,
     /*  169071 */   // GIR_Coverage, 25206,
     /*  169071 */   GIR_EraseRootFromParent_Done,
     /*  169072 */ // Label 2372: @169072
     /*  169072 */ GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(169135), // Rule ID 25207 //
     /*  169077 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  169080 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169083 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169088 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169092 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169096 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  169103 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  169103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  169106 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  169108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  169113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  169118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169123 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169126 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169129 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169133 */   GIR_RootConstrainSelectedInstOperands,
     /*  169134 */   // GIR_Coverage, 25207,
     /*  169134 */   GIR_EraseRootFromParent_Done,
     /*  169135 */ // Label 2373: @169135
     /*  169135 */ GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(169198), // Rule ID 25208 //
     /*  169140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  169143 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169146 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169151 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169155 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169159 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  169166 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  169166 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  169169 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  169171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  169176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  169181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169186 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169189 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169192 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169196 */   GIR_RootConstrainSelectedInstOperands,
     /*  169197 */   // GIR_Coverage, 25208,
     /*  169197 */   GIR_EraseRootFromParent_Done,
     /*  169198 */ // Label 2374: @169198
     /*  169198 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(169261), // Rule ID 25209 //
     /*  169203 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  169206 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169209 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169214 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  169229 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  169229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  169232 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  169234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  169239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  169244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169252 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169255 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169259 */   GIR_RootConstrainSelectedInstOperands,
     /*  169260 */   // GIR_Coverage, 25209,
     /*  169260 */   GIR_EraseRootFromParent_Done,
     /*  169261 */ // Label 2375: @169261
     /*  169261 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(169324), // Rule ID 25210 //
     /*  169266 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  169269 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  169292 */   // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  169292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  169295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  169297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  169302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  169307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  169318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169322 */   GIR_RootConstrainSelectedInstOperands,
     /*  169323 */   // GIR_Coverage, 25210,
     /*  169323 */   GIR_EraseRootFromParent_Done,
     /*  169324 */ // Label 2376: @169324
     /*  169324 */ GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(169397), // Rule ID 9418 //
     /*  169329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  169332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169335 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169339 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  169346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169355 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169359 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169366 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  169369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169391 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169395 */   GIR_RootConstrainSelectedInstOperands,
     /*  169396 */   // GIR_Coverage, 9418,
     /*  169396 */   GIR_EraseRootFromParent_Done,
     /*  169397 */ // Label 2377: @169397
     /*  169397 */ GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(169470), // Rule ID 9419 //
     /*  169402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  169405 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169408 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169412 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  169419 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169428 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169432 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169439 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169439 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  169442 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169464 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169468 */   GIR_RootConstrainSelectedInstOperands,
     /*  169469 */   // GIR_Coverage, 9419,
     /*  169469 */   GIR_EraseRootFromParent_Done,
     /*  169470 */ // Label 2378: @169470
     /*  169470 */ GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(169543), // Rule ID 9420 //
     /*  169475 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  169478 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169481 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169485 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  169492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169512 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  169515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169541 */   GIR_RootConstrainSelectedInstOperands,
     /*  169542 */   // GIR_Coverage, 9420,
     /*  169542 */   GIR_EraseRootFromParent_Done,
     /*  169543 */ // Label 2379: @169543
     /*  169543 */ GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(169616), // Rule ID 9421 //
     /*  169548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  169551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169554 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169558 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  169565 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169574 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169578 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169585 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169585 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  169588 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169610 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169614 */   GIR_RootConstrainSelectedInstOperands,
     /*  169615 */   // GIR_Coverage, 9421,
     /*  169615 */   GIR_EraseRootFromParent_Done,
     /*  169616 */ // Label 2380: @169616
     /*  169616 */ GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(169689), // Rule ID 9422 //
     /*  169621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  169624 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169627 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169631 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  169638 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169643 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169647 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169651 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169658 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169658 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  169661 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169683 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169687 */   GIR_RootConstrainSelectedInstOperands,
     /*  169688 */   // GIR_Coverage, 9422,
     /*  169688 */   GIR_EraseRootFromParent_Done,
     /*  169689 */ // Label 2381: @169689
     /*  169689 */ GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(169762), // Rule ID 13885 //
     /*  169694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  169697 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169700 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169704 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  169711 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169720 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169724 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169731 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  169734 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169756 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169760 */   GIR_RootConstrainSelectedInstOperands,
     /*  169761 */   // GIR_Coverage, 13885,
     /*  169761 */   GIR_EraseRootFromParent_Done,
     /*  169762 */ // Label 2382: @169762
     /*  169762 */ GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(169835), // Rule ID 13886 //
     /*  169767 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  169770 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169773 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169777 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  169784 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169804 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  169807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169829 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169833 */   GIR_RootConstrainSelectedInstOperands,
     /*  169834 */   // GIR_Coverage, 13886,
     /*  169834 */   GIR_EraseRootFromParent_Done,
     /*  169835 */ // Label 2383: @169835
     /*  169835 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(169908), // Rule ID 13887 //
     /*  169840 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  169843 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169846 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169850 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  169857 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169866 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169870 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169877 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  169880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169902 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169906 */   GIR_RootConstrainSelectedInstOperands,
     /*  169907 */   // GIR_Coverage, 13887,
     /*  169907 */   GIR_EraseRootFromParent_Done,
     /*  169908 */ // Label 2384: @169908
     /*  169908 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(169981), // Rule ID 13888 //
     /*  169913 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  169916 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169919 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169923 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  169930 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  169935 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  169939 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  169943 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  169950 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  169950 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  169953 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  169955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  169960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  169965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  169970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  169975 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  169979 */   GIR_RootConstrainSelectedInstOperands,
     /*  169980 */   // GIR_Coverage, 13888,
     /*  169980 */   GIR_EraseRootFromParent_Done,
     /*  169981 */ // Label 2385: @169981
     /*  169981 */ GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(170054), // Rule ID 13889 //
     /*  169986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  169989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  169992 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  169996 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  170003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170023 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  170026 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170048 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170052 */   GIR_RootConstrainSelectedInstOperands,
     /*  170053 */   // GIR_Coverage, 13889,
     /*  170053 */   GIR_EraseRootFromParent_Done,
     /*  170054 */ // Label 2386: @170054
     /*  170054 */ GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(170116), // Rule ID 14062 //
     /*  170059 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  170062 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170085 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170110 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170114 */   GIR_RootConstrainSelectedInstOperands,
     /*  170115 */   // GIR_Coverage, 14062,
     /*  170115 */   GIR_EraseRootFromParent_Done,
     /*  170116 */ // Label 2387: @170116
     /*  170116 */ GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(170178), // Rule ID 14063 //
     /*  170121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  170124 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170147 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170172 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170176 */   GIR_RootConstrainSelectedInstOperands,
     /*  170177 */   // GIR_Coverage, 14063,
     /*  170177 */   GIR_EraseRootFromParent_Done,
     /*  170178 */ // Label 2388: @170178
     /*  170178 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(170240), // Rule ID 14064 //
     /*  170183 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  170186 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170189 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170209 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170234 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170238 */   GIR_RootConstrainSelectedInstOperands,
     /*  170239 */   // GIR_Coverage, 14064,
     /*  170239 */   GIR_EraseRootFromParent_Done,
     /*  170240 */ // Label 2389: @170240
     /*  170240 */ GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(170302), // Rule ID 14065 //
     /*  170245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  170248 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170271 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170274 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170296 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170300 */   GIR_RootConstrainSelectedInstOperands,
     /*  170301 */   // GIR_Coverage, 14065,
     /*  170301 */   GIR_EraseRootFromParent_Done,
     /*  170302 */ // Label 2390: @170302
     /*  170302 */ GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(170364), // Rule ID 14066 //
     /*  170307 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  170310 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170333 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170336 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170358 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170362 */   GIR_RootConstrainSelectedInstOperands,
     /*  170363 */   // GIR_Coverage, 14066,
     /*  170363 */   GIR_EraseRootFromParent_Done,
     /*  170364 */ // Label 2391: @170364
     /*  170364 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(170426), // Rule ID 14092 //
     /*  170369 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  170372 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170384 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170388 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170395 */   // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170395 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170398 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170420 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170424 */   GIR_RootConstrainSelectedInstOperands,
     /*  170425 */   // GIR_Coverage, 14092,
     /*  170425 */   GIR_EraseRootFromParent_Done,
     /*  170426 */ // Label 2392: @170426
     /*  170426 */ GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(170488), // Rule ID 14093 //
     /*  170431 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  170434 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170457 */   // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170482 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170486 */   GIR_RootConstrainSelectedInstOperands,
     /*  170487 */   // GIR_Coverage, 14093,
     /*  170487 */   GIR_EraseRootFromParent_Done,
     /*  170488 */ // Label 2393: @170488
     /*  170488 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(170550), // Rule ID 14094 //
     /*  170493 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  170496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170519 */   // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170544 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170548 */   GIR_RootConstrainSelectedInstOperands,
     /*  170549 */   // GIR_Coverage, 14094,
     /*  170549 */   GIR_EraseRootFromParent_Done,
     /*  170550 */ // Label 2394: @170550
     /*  170550 */ GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(170612), // Rule ID 14095 //
     /*  170555 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  170558 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170570 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170581 */   // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170606 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170610 */   GIR_RootConstrainSelectedInstOperands,
     /*  170611 */   // GIR_Coverage, 14095,
     /*  170611 */   GIR_EraseRootFromParent_Done,
     /*  170612 */ // Label 2395: @170612
     /*  170612 */ GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(170674), // Rule ID 14096 //
     /*  170617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  170620 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170623 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  170643 */   // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  170643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  170646 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  170653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  170658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  170663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  170668 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170672 */   GIR_RootConstrainSelectedInstOperands,
     /*  170673 */   // GIR_Coverage, 14096,
     /*  170673 */   GIR_EraseRootFromParent_Done,
     /*  170674 */ // Label 2396: @170674
     /*  170674 */ GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(170740), // Rule ID 9413 //
     /*  170679 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  170682 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170685 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  170689 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  170696 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170701 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170705 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170709 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  170716 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  170716 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  170719 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  170726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  170731 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  170734 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170738 */   GIR_RootConstrainSelectedInstOperands,
     /*  170739 */   // GIR_Coverage, 9413,
     /*  170739 */   GIR_EraseRootFromParent_Done,
     /*  170740 */ // Label 2397: @170740
     /*  170740 */ GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(170806), // Rule ID 9414 //
     /*  170745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  170748 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170751 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  170755 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  170762 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170775 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  170782 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  170782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  170785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  170792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  170797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  170800 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170804 */   GIR_RootConstrainSelectedInstOperands,
     /*  170805 */   // GIR_Coverage, 9414,
     /*  170805 */   GIR_EraseRootFromParent_Done,
     /*  170806 */ // Label 2398: @170806
     /*  170806 */ GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(170872), // Rule ID 9415 //
     /*  170811 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  170814 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170817 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  170821 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  170828 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170837 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170841 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  170848 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  170848 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  170851 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  170858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  170863 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  170866 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170870 */   GIR_RootConstrainSelectedInstOperands,
     /*  170871 */   // GIR_Coverage, 9415,
     /*  170871 */   GIR_EraseRootFromParent_Done,
     /*  170872 */ // Label 2399: @170872
     /*  170872 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(170938), // Rule ID 9416 //
     /*  170877 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  170880 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170883 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  170887 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  170894 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170899 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170903 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170907 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  170914 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  170914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  170917 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  170924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  170929 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  170932 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  170936 */   GIR_RootConstrainSelectedInstOperands,
     /*  170937 */   // GIR_Coverage, 9416,
     /*  170937 */   GIR_EraseRootFromParent_Done,
     /*  170938 */ // Label 2400: @170938
     /*  170938 */ GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(171004), // Rule ID 9417 //
     /*  170943 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  170946 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  170949 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  170953 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  170960 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  170965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  170969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  170973 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  170980 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  170980 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  170983 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  170985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  170990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  170995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  170998 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171002 */   GIR_RootConstrainSelectedInstOperands,
     /*  171003 */   // GIR_Coverage, 9417,
     /*  171003 */   GIR_EraseRootFromParent_Done,
     /*  171004 */ // Label 2401: @171004
     /*  171004 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(171070), // Rule ID 13880 //
     /*  171009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  171012 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171015 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171019 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  171026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171046 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  171049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171061 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171064 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171068 */   GIR_RootConstrainSelectedInstOperands,
     /*  171069 */   // GIR_Coverage, 13880,
     /*  171069 */   GIR_EraseRootFromParent_Done,
     /*  171070 */ // Label 2402: @171070
     /*  171070 */ GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(171136), // Rule ID 13881 //
     /*  171075 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  171078 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171081 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171085 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  171092 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171097 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171101 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171105 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171112 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  171115 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171127 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171130 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171134 */   GIR_RootConstrainSelectedInstOperands,
     /*  171135 */   // GIR_Coverage, 13881,
     /*  171135 */   GIR_EraseRootFromParent_Done,
     /*  171136 */ // Label 2403: @171136
     /*  171136 */ GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(171202), // Rule ID 13882 //
     /*  171141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  171144 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171147 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171151 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  171158 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171167 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171171 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171178 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171178 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  171181 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171196 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171200 */   GIR_RootConstrainSelectedInstOperands,
     /*  171201 */   // GIR_Coverage, 13882,
     /*  171201 */   GIR_EraseRootFromParent_Done,
     /*  171202 */ // Label 2404: @171202
     /*  171202 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(171268), // Rule ID 13883 //
     /*  171207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  171210 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171213 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171217 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  171224 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171244 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  171247 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171266 */   GIR_RootConstrainSelectedInstOperands,
     /*  171267 */   // GIR_Coverage, 13883,
     /*  171267 */   GIR_EraseRootFromParent_Done,
     /*  171268 */ // Label 2405: @171268
     /*  171268 */ GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(171334), // Rule ID 13884 //
     /*  171273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  171276 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171279 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171283 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  171290 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171295 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171299 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171303 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171310 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171310 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  171313 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171325 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171328 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171332 */   GIR_RootConstrainSelectedInstOperands,
     /*  171333 */   // GIR_Coverage, 13884,
     /*  171333 */   GIR_EraseRootFromParent_Done,
     /*  171334 */ // Label 2406: @171334
     /*  171334 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(171389), // Rule ID 14057 //
     /*  171339 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  171342 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171345 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171350 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171354 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171358 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171365 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171368 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171380 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171383 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171387 */   GIR_RootConstrainSelectedInstOperands,
     /*  171388 */   // GIR_Coverage, 14057,
     /*  171388 */   GIR_EraseRootFromParent_Done,
     /*  171389 */ // Label 2407: @171389
     /*  171389 */ GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(171444), // Rule ID 14058 //
     /*  171394 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  171397 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171400 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171405 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171409 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171413 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171420 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171420 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171423 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171435 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171438 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171442 */   GIR_RootConstrainSelectedInstOperands,
     /*  171443 */   // GIR_Coverage, 14058,
     /*  171443 */   GIR_EraseRootFromParent_Done,
     /*  171444 */ // Label 2408: @171444
     /*  171444 */ GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(171499), // Rule ID 14059 //
     /*  171449 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  171452 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171455 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171464 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171468 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171475 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171475 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171478 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171490 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171493 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171497 */   GIR_RootConstrainSelectedInstOperands,
     /*  171498 */   // GIR_Coverage, 14059,
     /*  171498 */   GIR_EraseRootFromParent_Done,
     /*  171499 */ // Label 2409: @171499
     /*  171499 */ GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(171554), // Rule ID 14060 //
     /*  171504 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  171507 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171510 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171530 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171530 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171533 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171545 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171548 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171552 */   GIR_RootConstrainSelectedInstOperands,
     /*  171553 */   // GIR_Coverage, 14060,
     /*  171553 */   GIR_EraseRootFromParent_Done,
     /*  171554 */ // Label 2410: @171554
     /*  171554 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(171609), // Rule ID 14061 //
     /*  171559 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  171562 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171565 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171574 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171578 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171585 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171585 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171588 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171600 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171603 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171607 */   GIR_RootConstrainSelectedInstOperands,
     /*  171608 */   // GIR_Coverage, 14061,
     /*  171608 */   GIR_EraseRootFromParent_Done,
     /*  171609 */ // Label 2411: @171609
     /*  171609 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(171664), // Rule ID 14087 //
     /*  171614 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  171617 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171640 */   // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171643 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171655 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171662 */   GIR_RootConstrainSelectedInstOperands,
     /*  171663 */   // GIR_Coverage, 14087,
     /*  171663 */   GIR_EraseRootFromParent_Done,
     /*  171664 */ // Label 2412: @171664
     /*  171664 */ GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(171719), // Rule ID 14088 //
     /*  171669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  171672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171675 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171695 */   // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171710 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171713 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171717 */   GIR_RootConstrainSelectedInstOperands,
     /*  171718 */   // GIR_Coverage, 14088,
     /*  171718 */   GIR_EraseRootFromParent_Done,
     /*  171719 */ // Label 2413: @171719
     /*  171719 */ GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(171774), // Rule ID 14089 //
     /*  171724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  171727 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171730 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171739 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171743 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171750 */   // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171753 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171765 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171768 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171772 */   GIR_RootConstrainSelectedInstOperands,
     /*  171773 */   // GIR_Coverage, 14089,
     /*  171773 */   GIR_EraseRootFromParent_Done,
     /*  171774 */ // Label 2414: @171774
     /*  171774 */ GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(171829), // Rule ID 14090 //
     /*  171779 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  171782 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171785 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171794 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171798 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171805 */   // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171808 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171820 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171823 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171827 */   GIR_RootConstrainSelectedInstOperands,
     /*  171828 */   // GIR_Coverage, 14090,
     /*  171828 */   GIR_EraseRootFromParent_Done,
     /*  171829 */ // Label 2415: @171829
     /*  171829 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(171884), // Rule ID 14091 //
     /*  171834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  171837 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171840 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171849 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171853 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  171860 */   // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  171860 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  171863 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  171870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171882 */   GIR_RootConstrainSelectedInstOperands,
     /*  171883 */   // GIR_Coverage, 14091,
     /*  171883 */   GIR_EraseRootFromParent_Done,
     /*  171884 */ // Label 2416: @171884
     /*  171884 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(171950), // Rule ID 9408 //
     /*  171889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  171892 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171895 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171899 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  171906 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171911 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171915 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171919 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  171926 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  171926 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  171929 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  171936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  171941 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  171944 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  171948 */   GIR_RootConstrainSelectedInstOperands,
     /*  171949 */   // GIR_Coverage, 9408,
     /*  171949 */   GIR_EraseRootFromParent_Done,
     /*  171950 */ // Label 2417: @171950
     /*  171950 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(172016), // Rule ID 9409 //
     /*  171955 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  171958 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  171961 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  171965 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  171972 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  171977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  171981 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  171985 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  171992 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  171992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  171995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  171997 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172007 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172010 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172014 */   GIR_RootConstrainSelectedInstOperands,
     /*  172015 */   // GIR_Coverage, 9409,
     /*  172015 */   GIR_EraseRootFromParent_Done,
     /*  172016 */ // Label 2418: @172016
     /*  172016 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(172082), // Rule ID 9410 //
     /*  172021 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  172024 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172027 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172031 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  172038 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172058 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  172061 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172073 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172076 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172080 */   GIR_RootConstrainSelectedInstOperands,
     /*  172081 */   // GIR_Coverage, 9410,
     /*  172081 */   GIR_EraseRootFromParent_Done,
     /*  172082 */ // Label 2419: @172082
     /*  172082 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(172148), // Rule ID 9411 //
     /*  172087 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  172090 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172093 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172097 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  172104 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172113 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172117 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172124 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  172127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172146 */   GIR_RootConstrainSelectedInstOperands,
     /*  172147 */   // GIR_Coverage, 9411,
     /*  172147 */   GIR_EraseRootFromParent_Done,
     /*  172148 */ // Label 2420: @172148
     /*  172148 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(172214), // Rule ID 9412 //
     /*  172153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  172156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172159 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172163 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  172170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172175 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172179 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172183 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172190 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172190 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  172193 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172205 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172208 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172212 */   GIR_RootConstrainSelectedInstOperands,
     /*  172213 */   // GIR_Coverage, 9412,
     /*  172213 */   GIR_EraseRootFromParent_Done,
     /*  172214 */ // Label 2421: @172214
     /*  172214 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(172280), // Rule ID 13875 //
     /*  172219 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  172222 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172225 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172229 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  172236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172256 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  172259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172271 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172278 */   GIR_RootConstrainSelectedInstOperands,
     /*  172279 */   // GIR_Coverage, 13875,
     /*  172279 */   GIR_EraseRootFromParent_Done,
     /*  172280 */ // Label 2422: @172280
     /*  172280 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(172346), // Rule ID 13876 //
     /*  172285 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  172288 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172291 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172295 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  172302 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172311 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172315 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172322 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172322 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  172325 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172340 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172344 */   GIR_RootConstrainSelectedInstOperands,
     /*  172345 */   // GIR_Coverage, 13876,
     /*  172345 */   GIR_EraseRootFromParent_Done,
     /*  172346 */ // Label 2423: @172346
     /*  172346 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(172412), // Rule ID 13877 //
     /*  172351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  172354 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172357 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172361 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  172368 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172377 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172388 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  172391 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172406 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172410 */   GIR_RootConstrainSelectedInstOperands,
     /*  172411 */   // GIR_Coverage, 13877,
     /*  172411 */   GIR_EraseRootFromParent_Done,
     /*  172412 */ // Label 2424: @172412
     /*  172412 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(172478), // Rule ID 13878 //
     /*  172417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  172420 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172423 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172427 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  172434 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172443 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172447 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172454 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172454 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  172457 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172469 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172472 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172476 */   GIR_RootConstrainSelectedInstOperands,
     /*  172477 */   // GIR_Coverage, 13878,
     /*  172477 */   GIR_EraseRootFromParent_Done,
     /*  172478 */ // Label 2425: @172478
     /*  172478 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(172544), // Rule ID 13879 //
     /*  172483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  172486 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172489 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  172493 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  172500 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172505 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172509 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172513 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172520 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  172523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172535 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172538 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172542 */   GIR_RootConstrainSelectedInstOperands,
     /*  172543 */   // GIR_Coverage, 13879,
     /*  172543 */   GIR_EraseRootFromParent_Done,
     /*  172544 */ // Label 2426: @172544
     /*  172544 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(172599), // Rule ID 14052 //
     /*  172549 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  172552 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172555 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172560 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172564 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172568 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172575 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172575 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172578 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172590 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172593 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172597 */   GIR_RootConstrainSelectedInstOperands,
     /*  172598 */   // GIR_Coverage, 14052,
     /*  172598 */   GIR_EraseRootFromParent_Done,
     /*  172599 */ // Label 2427: @172599
     /*  172599 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(172654), // Rule ID 14053 //
     /*  172604 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  172607 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172610 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172615 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172619 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172623 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172630 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172630 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172633 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172645 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172648 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172652 */   GIR_RootConstrainSelectedInstOperands,
     /*  172653 */   // GIR_Coverage, 14053,
     /*  172653 */   GIR_EraseRootFromParent_Done,
     /*  172654 */ // Label 2428: @172654
     /*  172654 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(172709), // Rule ID 14054 //
     /*  172659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  172662 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172665 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172670 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172674 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172678 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172685 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172700 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172703 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172707 */   GIR_RootConstrainSelectedInstOperands,
     /*  172708 */   // GIR_Coverage, 14054,
     /*  172708 */   GIR_EraseRootFromParent_Done,
     /*  172709 */ // Label 2429: @172709
     /*  172709 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(172764), // Rule ID 14055 //
     /*  172714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  172717 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172720 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172740 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172743 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172758 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172762 */   GIR_RootConstrainSelectedInstOperands,
     /*  172763 */   // GIR_Coverage, 14055,
     /*  172763 */   GIR_EraseRootFromParent_Done,
     /*  172764 */ // Label 2430: @172764
     /*  172764 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(172819), // Rule ID 14056 //
     /*  172769 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  172772 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172784 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172788 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172795 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172810 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172813 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172817 */   GIR_RootConstrainSelectedInstOperands,
     /*  172818 */   // GIR_Coverage, 14056,
     /*  172818 */   GIR_EraseRootFromParent_Done,
     /*  172819 */ // Label 2431: @172819
     /*  172819 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(172874), // Rule ID 14082 //
     /*  172824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  172827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172830 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172839 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172843 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172850 */   // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172865 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172868 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172872 */   GIR_RootConstrainSelectedInstOperands,
     /*  172873 */   // GIR_Coverage, 14082,
     /*  172873 */   GIR_EraseRootFromParent_Done,
     /*  172874 */ // Label 2432: @172874
     /*  172874 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(172929), // Rule ID 14083 //
     /*  172879 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  172882 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172885 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172898 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172905 */   // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172920 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172923 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172927 */   GIR_RootConstrainSelectedInstOperands,
     /*  172928 */   // GIR_Coverage, 14083,
     /*  172928 */   GIR_EraseRootFromParent_Done,
     /*  172929 */ // Label 2433: @172929
     /*  172929 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(172984), // Rule ID 14084 //
     /*  172934 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  172937 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  172945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  172949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  172953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  172960 */   // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  172960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  172963 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  172965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  172970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  172975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  172978 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  172982 */   GIR_RootConstrainSelectedInstOperands,
     /*  172983 */   // GIR_Coverage, 14084,
     /*  172983 */   GIR_EraseRootFromParent_Done,
     /*  172984 */ // Label 2434: @172984
     /*  172984 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(173039), // Rule ID 14085 //
     /*  172989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  172992 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  172995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  173000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173004 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173008 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  173015 */   // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  173015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  173018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  173020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  173025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  173030 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173033 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173037 */   GIR_RootConstrainSelectedInstOperands,
     /*  173038 */   // GIR_Coverage, 14085,
     /*  173038 */   GIR_EraseRootFromParent_Done,
     /*  173039 */ // Label 2435: @173039
     /*  173039 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(173094), // Rule ID 14086 //
     /*  173044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  173047 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  173050 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  173055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173059 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173063 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  173070 */   // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  173070 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  173073 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  173075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  173080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  173085 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173088 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173092 */   GIR_RootConstrainSelectedInstOperands,
     /*  173093 */   // GIR_Coverage, 14086,
     /*  173093 */   GIR_EraseRootFromParent_Done,
     /*  173094 */ // Label 2436: @173094
     /*  173094 */ GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(173175), // Rule ID 15038 //
     /*  173099 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  173102 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173105 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173109 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173116 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173123 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173127 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173131 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173138 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173138 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  173141 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173166 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173169 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173173 */   GIR_RootConstrainSelectedInstOperands,
     /*  173174 */   // GIR_Coverage, 15038,
     /*  173174 */   GIR_EraseRootFromParent_Done,
     /*  173175 */ // Label 2437: @173175
     /*  173175 */ GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(173256), // Rule ID 15039 //
     /*  173180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  173183 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173186 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173190 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173197 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173219 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  173222 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173247 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173250 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173254 */   GIR_RootConstrainSelectedInstOperands,
     /*  173255 */   // GIR_Coverage, 15039,
     /*  173255 */   GIR_EraseRootFromParent_Done,
     /*  173256 */ // Label 2438: @173256
     /*  173256 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(173337), // Rule ID 15040 //
     /*  173261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  173264 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173267 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173271 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173278 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173285 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173289 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173293 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173300 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173300 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  173303 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173325 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173328 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173331 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173335 */   GIR_RootConstrainSelectedInstOperands,
     /*  173336 */   // GIR_Coverage, 15040,
     /*  173336 */   GIR_EraseRootFromParent_Done,
     /*  173337 */ // Label 2439: @173337
     /*  173337 */ GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(173418), // Rule ID 15041 //
     /*  173342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  173345 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173348 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173352 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173370 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173374 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173381 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  173384 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173409 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173412 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173416 */   GIR_RootConstrainSelectedInstOperands,
     /*  173417 */   // GIR_Coverage, 15041,
     /*  173417 */   GIR_EraseRootFromParent_Done,
     /*  173418 */ // Label 2440: @173418
     /*  173418 */ GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(173499), // Rule ID 15042 //
     /*  173423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  173426 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173429 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173433 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173440 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173447 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173451 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173455 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173462 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  173465 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173487 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173490 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173493 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173497 */   GIR_RootConstrainSelectedInstOperands,
     /*  173498 */   // GIR_Coverage, 15042,
     /*  173498 */   GIR_EraseRootFromParent_Done,
     /*  173499 */ // Label 2441: @173499
     /*  173499 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(173580), // Rule ID 15058 //
     /*  173504 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  173507 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173510 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173514 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173521 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173543 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  173546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173578 */   GIR_RootConstrainSelectedInstOperands,
     /*  173579 */   // GIR_Coverage, 15058,
     /*  173579 */   GIR_EraseRootFromParent_Done,
     /*  173580 */ // Label 2442: @173580
     /*  173580 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(173661), // Rule ID 15059 //
     /*  173585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  173588 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173591 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173595 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173602 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173624 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  173627 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173652 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173655 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173659 */   GIR_RootConstrainSelectedInstOperands,
     /*  173660 */   // GIR_Coverage, 15059,
     /*  173660 */   GIR_EraseRootFromParent_Done,
     /*  173661 */ // Label 2443: @173661
     /*  173661 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(173742), // Rule ID 15060 //
     /*  173666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  173669 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173672 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173676 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173683 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173705 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  173708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173730 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173733 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173736 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173740 */   GIR_RootConstrainSelectedInstOperands,
     /*  173741 */   // GIR_Coverage, 15060,
     /*  173741 */   GIR_EraseRootFromParent_Done,
     /*  173742 */ // Label 2444: @173742
     /*  173742 */ GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(173823), // Rule ID 15061 //
     /*  173747 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  173750 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173753 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173757 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173764 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173771 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173775 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173779 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173786 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  173789 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173817 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173821 */   GIR_RootConstrainSelectedInstOperands,
     /*  173822 */   // GIR_Coverage, 15061,
     /*  173822 */   GIR_EraseRootFromParent_Done,
     /*  173823 */ // Label 2445: @173823
     /*  173823 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(173904), // Rule ID 15062 //
     /*  173828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  173831 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173834 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173838 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  173845 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173867 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  173870 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173892 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173895 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173898 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173902 */   GIR_RootConstrainSelectedInstOperands,
     /*  173903 */   // GIR_Coverage, 15062,
     /*  173903 */   GIR_EraseRootFromParent_Done,
     /*  173904 */ // Label 2446: @173904
     /*  173904 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(173985), // Rule ID 15088 //
     /*  173909 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  173912 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173915 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  173919 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  173926 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  173933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  173937 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  173941 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  173948 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  173948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  173951 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  173953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  173958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  173963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  173968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  173973 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  173979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  173983 */   GIR_RootConstrainSelectedInstOperands,
     /*  173984 */   // GIR_Coverage, 15088,
     /*  173984 */   GIR_EraseRootFromParent_Done,
     /*  173985 */ // Label 2447: @173985
     /*  173985 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(174066), // Rule ID 15089 //
     /*  173990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  173993 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  173996 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174000 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174018 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174022 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174029 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  174032 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174054 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174057 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174060 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174064 */   GIR_RootConstrainSelectedInstOperands,
     /*  174065 */   // GIR_Coverage, 15089,
     /*  174065 */   GIR_EraseRootFromParent_Done,
     /*  174066 */ // Label 2448: @174066
     /*  174066 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(174147), // Rule ID 15090 //
     /*  174071 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  174074 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174077 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174081 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174095 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174099 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174103 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174110 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174110 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  174113 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174135 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174138 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174141 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174145 */   GIR_RootConstrainSelectedInstOperands,
     /*  174146 */   // GIR_Coverage, 15090,
     /*  174146 */   GIR_EraseRootFromParent_Done,
     /*  174147 */ // Label 2449: @174147
     /*  174147 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(174228), // Rule ID 15091 //
     /*  174152 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  174155 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174158 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174162 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174169 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174176 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174191 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  174194 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174216 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174222 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174226 */   GIR_RootConstrainSelectedInstOperands,
     /*  174227 */   // GIR_Coverage, 15091,
     /*  174227 */   GIR_EraseRootFromParent_Done,
     /*  174228 */ // Label 2450: @174228
     /*  174228 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(174309), // Rule ID 15092 //
     /*  174233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  174236 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174239 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174243 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174250 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174261 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174265 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174272 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174272 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  174275 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174300 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174307 */   GIR_RootConstrainSelectedInstOperands,
     /*  174308 */   // GIR_Coverage, 15092,
     /*  174308 */   GIR_EraseRootFromParent_Done,
     /*  174309 */ // Label 2451: @174309
     /*  174309 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(174390), // Rule ID 15098 //
     /*  174314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  174317 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174320 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174324 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174331 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174353 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  174356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174381 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174384 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174388 */   GIR_RootConstrainSelectedInstOperands,
     /*  174389 */   // GIR_Coverage, 15098,
     /*  174389 */   GIR_EraseRootFromParent_Done,
     /*  174390 */ // Label 2452: @174390
     /*  174390 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(174471), // Rule ID 15099 //
     /*  174395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  174398 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174401 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174405 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174412 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174434 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  174437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174459 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174462 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174465 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174469 */   GIR_RootConstrainSelectedInstOperands,
     /*  174470 */   // GIR_Coverage, 15099,
     /*  174470 */   GIR_EraseRootFromParent_Done,
     /*  174471 */ // Label 2453: @174471
     /*  174471 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(174552), // Rule ID 15100 //
     /*  174476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  174479 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174482 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174486 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174493 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174515 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  174518 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174543 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174546 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174550 */   GIR_RootConstrainSelectedInstOperands,
     /*  174551 */   // GIR_Coverage, 15100,
     /*  174551 */   GIR_EraseRootFromParent_Done,
     /*  174552 */ // Label 2454: @174552
     /*  174552 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(174633), // Rule ID 15101 //
     /*  174557 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  174560 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174563 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174567 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174574 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174581 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174585 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174589 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174596 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  174599 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174621 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174624 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174627 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174631 */   GIR_RootConstrainSelectedInstOperands,
     /*  174632 */   // GIR_Coverage, 15101,
     /*  174632 */   GIR_EraseRootFromParent_Done,
     /*  174633 */ // Label 2455: @174633
     /*  174633 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(174714), // Rule ID 15102 //
     /*  174638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  174641 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  174644 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174648 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  174655 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174666 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174670 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174677 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174677 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  174680 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174702 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174705 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174708 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174712 */   GIR_RootConstrainSelectedInstOperands,
     /*  174713 */   // GIR_Coverage, 15102,
     /*  174713 */   GIR_EraseRootFromParent_Done,
     /*  174714 */ // Label 2456: @174714
     /*  174714 */ GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(174795), // Rule ID 15188 //
     /*  174719 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  174722 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  174725 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174729 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  174736 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174747 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174751 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174758 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174758 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  174761 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174783 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174786 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174789 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174793 */   GIR_RootConstrainSelectedInstOperands,
     /*  174794 */   // GIR_Coverage, 15188,
     /*  174794 */   GIR_EraseRootFromParent_Done,
     /*  174795 */ // Label 2457: @174795
     /*  174795 */ GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(174876), // Rule ID 15189 //
     /*  174800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  174803 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  174806 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174810 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  174817 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174832 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174839 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174839 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  174842 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174864 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174867 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174870 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174874 */   GIR_RootConstrainSelectedInstOperands,
     /*  174875 */   // GIR_Coverage, 15189,
     /*  174875 */   GIR_EraseRootFromParent_Done,
     /*  174876 */ // Label 2458: @174876
     /*  174876 */ GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(174957), // Rule ID 15190 //
     /*  174881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  174884 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  174887 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174891 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  174898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174909 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174913 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  174920 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  174920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  174923 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  174925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  174930 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  174935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  174940 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  174945 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174948 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  174951 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  174955 */   GIR_RootConstrainSelectedInstOperands,
     /*  174956 */   // GIR_Coverage, 15190,
     /*  174956 */   GIR_EraseRootFromParent_Done,
     /*  174957 */ // Label 2459: @174957
     /*  174957 */ GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(175038), // Rule ID 15191 //
     /*  174962 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  174965 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  174968 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  174972 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  174979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  174986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  174990 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  174994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175001 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  175004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175026 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175029 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175032 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175036 */   GIR_RootConstrainSelectedInstOperands,
     /*  175037 */   // GIR_Coverage, 15191,
     /*  175037 */   GIR_EraseRootFromParent_Done,
     /*  175038 */ // Label 2460: @175038
     /*  175038 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(175119), // Rule ID 15192 //
     /*  175043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  175046 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175049 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175053 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  175060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175082 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  175085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175107 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175110 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175117 */   GIR_RootConstrainSelectedInstOperands,
     /*  175118 */   // GIR_Coverage, 15192,
     /*  175118 */   GIR_EraseRootFromParent_Done,
     /*  175119 */ // Label 2461: @175119
     /*  175119 */ GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(175200), // Rule ID 15198 //
     /*  175124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  175127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175130 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175134 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  175141 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175152 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175156 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175163 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  175166 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175194 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175198 */   GIR_RootConstrainSelectedInstOperands,
     /*  175199 */   // GIR_Coverage, 15198,
     /*  175199 */   GIR_EraseRootFromParent_Done,
     /*  175200 */ // Label 2462: @175200
     /*  175200 */ GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(175281), // Rule ID 15199 //
     /*  175205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  175208 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175211 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175215 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  175222 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175244 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  175247 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175279 */   GIR_RootConstrainSelectedInstOperands,
     /*  175280 */   // GIR_Coverage, 15199,
     /*  175280 */   GIR_EraseRootFromParent_Done,
     /*  175281 */ // Label 2463: @175281
     /*  175281 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(175362), // Rule ID 15200 //
     /*  175286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  175289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175292 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  175303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175314 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175318 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175325 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175325 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  175328 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175350 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175356 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175360 */   GIR_RootConstrainSelectedInstOperands,
     /*  175361 */   // GIR_Coverage, 15200,
     /*  175361 */   GIR_EraseRootFromParent_Done,
     /*  175362 */ // Label 2464: @175362
     /*  175362 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(175443), // Rule ID 15201 //
     /*  175367 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  175370 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175373 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175377 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  175384 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175391 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175395 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175399 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175406 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175406 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  175409 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175431 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175441 */   GIR_RootConstrainSelectedInstOperands,
     /*  175442 */   // GIR_Coverage, 15201,
     /*  175442 */   GIR_EraseRootFromParent_Done,
     /*  175443 */ // Label 2465: @175443
     /*  175443 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(175524), // Rule ID 15202 //
     /*  175448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  175451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175454 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175458 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  175465 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175476 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175480 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175487 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175487 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  175490 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175497 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175502 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175512 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175515 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175518 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175522 */   GIR_RootConstrainSelectedInstOperands,
     /*  175523 */   // GIR_Coverage, 15202,
     /*  175523 */   GIR_EraseRootFromParent_Done,
     /*  175524 */ // Label 2466: @175524
     /*  175524 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(175605), // Rule ID 15288 //
     /*  175529 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  175532 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175535 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175539 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  175546 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175557 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175561 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175568 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  175571 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175603 */   GIR_RootConstrainSelectedInstOperands,
     /*  175604 */   // GIR_Coverage, 15288,
     /*  175604 */   GIR_EraseRootFromParent_Done,
     /*  175605 */ // Label 2467: @175605
     /*  175605 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(175686), // Rule ID 15289 //
     /*  175610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  175613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175616 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  175627 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175638 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175642 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175649 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175649 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  175652 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175674 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175677 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175680 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175684 */   GIR_RootConstrainSelectedInstOperands,
     /*  175685 */   // GIR_Coverage, 15289,
     /*  175685 */   GIR_EraseRootFromParent_Done,
     /*  175686 */ // Label 2468: @175686
     /*  175686 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(175767), // Rule ID 15290 //
     /*  175691 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  175694 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175697 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175701 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  175708 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175719 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175723 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175730 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175730 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  175733 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175765 */   GIR_RootConstrainSelectedInstOperands,
     /*  175766 */   // GIR_Coverage, 15290,
     /*  175766 */   GIR_EraseRootFromParent_Done,
     /*  175767 */ // Label 2469: @175767
     /*  175767 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(175848), // Rule ID 15291 //
     /*  175772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  175775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175778 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175782 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  175789 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175804 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175811 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  175814 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175839 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175842 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175846 */   GIR_RootConstrainSelectedInstOperands,
     /*  175847 */   // GIR_Coverage, 15291,
     /*  175847 */   GIR_EraseRootFromParent_Done,
     /*  175848 */ // Label 2470: @175848
     /*  175848 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(175929), // Rule ID 15292 //
     /*  175853 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  175856 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175859 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175863 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  175870 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175881 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175885 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175892 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175892 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  175895 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175917 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175920 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  175923 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  175927 */   GIR_RootConstrainSelectedInstOperands,
     /*  175928 */   // GIR_Coverage, 15292,
     /*  175928 */   GIR_EraseRootFromParent_Done,
     /*  175929 */ // Label 2471: @175929
     /*  175929 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(176010), // Rule ID 15298 //
     /*  175934 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  175937 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  175940 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  175944 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  175951 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  175958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  175962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  175966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  175973 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  175973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  175976 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  175978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  175983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  175988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  175993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  175998 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176004 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176008 */   GIR_RootConstrainSelectedInstOperands,
     /*  176009 */   // GIR_Coverage, 15298,
     /*  176009 */   GIR_EraseRootFromParent_Done,
     /*  176010 */ // Label 2472: @176010
     /*  176010 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(176091), // Rule ID 15299 //
     /*  176015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  176018 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176021 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176025 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  176032 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176039 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176043 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176047 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176054 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  176054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  176057 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176079 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176082 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176085 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176089 */   GIR_RootConstrainSelectedInstOperands,
     /*  176090 */   // GIR_Coverage, 15299,
     /*  176090 */   GIR_EraseRootFromParent_Done,
     /*  176091 */ // Label 2473: @176091
     /*  176091 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(176172), // Rule ID 15300 //
     /*  176096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  176099 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176102 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176106 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  176113 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176135 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  176135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  176138 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176170 */   GIR_RootConstrainSelectedInstOperands,
     /*  176171 */   // GIR_Coverage, 15300,
     /*  176171 */   GIR_EraseRootFromParent_Done,
     /*  176172 */ // Label 2474: @176172
     /*  176172 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(176253), // Rule ID 15301 //
     /*  176177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  176180 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176183 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176187 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  176194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176205 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176209 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176216 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  176216 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  176219 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176241 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176251 */   GIR_RootConstrainSelectedInstOperands,
     /*  176252 */   // GIR_Coverage, 15301,
     /*  176252 */   GIR_EraseRootFromParent_Done,
     /*  176253 */ // Label 2475: @176253
     /*  176253 */ GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(176334), // Rule ID 15302 //
     /*  176258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  176261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176264 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176268 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  176275 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176286 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176290 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176297 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  176297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  176300 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176325 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176328 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176332 */   GIR_RootConstrainSelectedInstOperands,
     /*  176333 */   // GIR_Coverage, 15302,
     /*  176333 */   GIR_EraseRootFromParent_Done,
     /*  176334 */ // Label 2476: @176334
     /*  176334 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(176415), // Rule ID 24841 //
     /*  176339 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  176342 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  176345 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176349 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  176356 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176367 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176378 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  176381 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176413 */   GIR_RootConstrainSelectedInstOperands,
     /*  176414 */   // GIR_Coverage, 24841,
     /*  176414 */   GIR_EraseRootFromParent_Done,
     /*  176415 */ // Label 2477: @176415
     /*  176415 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(176496), // Rule ID 24842 //
     /*  176420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  176423 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  176426 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176430 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  176437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176459 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  176462 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176487 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176490 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176494 */   GIR_RootConstrainSelectedInstOperands,
     /*  176495 */   // GIR_Coverage, 24842,
     /*  176495 */   GIR_EraseRootFromParent_Done,
     /*  176496 */ // Label 2478: @176496
     /*  176496 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(176577), // Rule ID 24843 //
     /*  176501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  176504 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  176507 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176511 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  176518 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176525 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176540 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  176543 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176565 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176571 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176575 */   GIR_RootConstrainSelectedInstOperands,
     /*  176576 */   // GIR_Coverage, 24843,
     /*  176576 */   GIR_EraseRootFromParent_Done,
     /*  176577 */ // Label 2479: @176577
     /*  176577 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(176658), // Rule ID 24844 //
     /*  176582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  176585 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  176588 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176592 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  176599 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176606 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176610 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176614 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176621 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176621 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  176624 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176656 */   GIR_RootConstrainSelectedInstOperands,
     /*  176657 */   // GIR_Coverage, 24844,
     /*  176657 */   GIR_EraseRootFromParent_Done,
     /*  176658 */ // Label 2480: @176658
     /*  176658 */ GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(176739), // Rule ID 24845 //
     /*  176663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  176666 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  176669 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176673 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  176680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176691 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176695 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176702 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176702 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  176705 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176727 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176730 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176733 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176737 */   GIR_RootConstrainSelectedInstOperands,
     /*  176738 */   // GIR_Coverage, 24845,
     /*  176738 */   GIR_EraseRootFromParent_Done,
     /*  176739 */ // Label 2481: @176739
     /*  176739 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(176819), // Rule ID 24856 //
     /*  176744 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  176747 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176750 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176754 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  176761 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176775 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176782 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  176785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176807 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176810 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176813 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176817 */   GIR_RootConstrainSelectedInstOperands,
     /*  176818 */   // GIR_Coverage, 24856,
     /*  176818 */   GIR_EraseRootFromParent_Done,
     /*  176819 */ // Label 2482: @176819
     /*  176819 */ GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(176899), // Rule ID 24857 //
     /*  176824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  176827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176830 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176834 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  176841 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176855 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176862 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  176865 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176890 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176893 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176897 */   GIR_RootConstrainSelectedInstOperands,
     /*  176898 */   // GIR_Coverage, 24857,
     /*  176898 */   GIR_EraseRootFromParent_Done,
     /*  176899 */ // Label 2483: @176899
     /*  176899 */ GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(176979), // Rule ID 24858 //
     /*  176904 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  176907 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176910 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176914 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  176921 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  176927 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  176931 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  176935 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  176942 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  176942 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  176945 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  176947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  176952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  176957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  176962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  176967 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176970 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  176973 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  176977 */   GIR_RootConstrainSelectedInstOperands,
     /*  176978 */   // GIR_Coverage, 24858,
     /*  176978 */   GIR_EraseRootFromParent_Done,
     /*  176979 */ // Label 2484: @176979
     /*  176979 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(177059), // Rule ID 24859 //
     /*  176984 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  176987 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  176990 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  176994 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177001 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177011 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177015 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177022 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177022 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  177025 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177047 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177050 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177053 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177057 */   GIR_RootConstrainSelectedInstOperands,
     /*  177058 */   // GIR_Coverage, 24859,
     /*  177058 */   GIR_EraseRootFromParent_Done,
     /*  177059 */ // Label 2485: @177059
     /*  177059 */ GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(177139), // Rule ID 24860 //
     /*  177064 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  177067 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177070 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177074 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177081 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177091 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177095 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177102 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  177105 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177127 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177133 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177137 */   GIR_RootConstrainSelectedInstOperands,
     /*  177138 */   // GIR_Coverage, 24860,
     /*  177138 */   GIR_EraseRootFromParent_Done,
     /*  177139 */ // Label 2486: @177139
     /*  177139 */ GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(177219), // Rule ID 24871 //
     /*  177144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  177147 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177150 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177154 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  177161 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177167 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177171 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177175 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177182 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177182 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  177185 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177217 */   GIR_RootConstrainSelectedInstOperands,
     /*  177218 */   // GIR_Coverage, 24871,
     /*  177218 */   GIR_EraseRootFromParent_Done,
     /*  177219 */ // Label 2487: @177219
     /*  177219 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(177299), // Rule ID 24872 //
     /*  177224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  177227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177230 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  177241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177251 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177255 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177262 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  177265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177287 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177290 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177293 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177297 */   GIR_RootConstrainSelectedInstOperands,
     /*  177298 */   // GIR_Coverage, 24872,
     /*  177298 */   GIR_EraseRootFromParent_Done,
     /*  177299 */ // Label 2488: @177299
     /*  177299 */ GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(177379), // Rule ID 24873 //
     /*  177304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  177307 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177310 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177314 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  177321 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177331 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177335 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177342 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177342 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  177345 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177367 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177377 */   GIR_RootConstrainSelectedInstOperands,
     /*  177378 */   // GIR_Coverage, 24873,
     /*  177378 */   GIR_EraseRootFromParent_Done,
     /*  177379 */ // Label 2489: @177379
     /*  177379 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(177459), // Rule ID 24874 //
     /*  177384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  177387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177390 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177394 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  177401 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177422 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  177425 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177437 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177442 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177447 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177450 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177453 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177457 */   GIR_RootConstrainSelectedInstOperands,
     /*  177458 */   // GIR_Coverage, 24874,
     /*  177458 */   GIR_EraseRootFromParent_Done,
     /*  177459 */ // Label 2490: @177459
     /*  177459 */ GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(177539), // Rule ID 24875 //
     /*  177464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  177467 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177470 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177474 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  177481 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  177487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177491 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177495 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  177502 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  177502 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  177505 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177527 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177537 */   GIR_RootConstrainSelectedInstOperands,
     /*  177538 */   // GIR_Coverage, 24875,
     /*  177538 */   GIR_EraseRootFromParent_Done,
     /*  177539 */ // Label 2491: @177539
     /*  177539 */ GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(177618), // Rule ID 24991 //
     /*  177544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  177547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177550 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  177566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177570 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  177581 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  177581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  177584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177609 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177612 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177616 */   GIR_RootConstrainSelectedInstOperands,
     /*  177617 */   // GIR_Coverage, 24991,
     /*  177617 */   GIR_EraseRootFromParent_Done,
     /*  177618 */ // Label 2492: @177618
     /*  177618 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(177697), // Rule ID 24992 //
     /*  177623 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  177626 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177629 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177633 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177640 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  177645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  177660 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  177660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  177663 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177685 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177688 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177691 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177695 */   GIR_RootConstrainSelectedInstOperands,
     /*  177696 */   // GIR_Coverage, 24992,
     /*  177696 */   GIR_EraseRootFromParent_Done,
     /*  177697 */ // Label 2493: @177697
     /*  177697 */ GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(177776), // Rule ID 24993 //
     /*  177702 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  177705 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177708 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177712 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177719 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  177724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177732 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  177739 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  177739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  177742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177767 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177770 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177774 */   GIR_RootConstrainSelectedInstOperands,
     /*  177775 */   // GIR_Coverage, 24993,
     /*  177775 */   GIR_EraseRootFromParent_Done,
     /*  177776 */ // Label 2494: @177776
     /*  177776 */ GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(177855), // Rule ID 24994 //
     /*  177781 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  177784 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177787 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177791 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177798 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  177803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177811 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  177818 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  177818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  177821 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177843 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177846 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177849 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177853 */   GIR_RootConstrainSelectedInstOperands,
     /*  177854 */   // GIR_Coverage, 24994,
     /*  177854 */   GIR_EraseRootFromParent_Done,
     /*  177855 */ // Label 2495: @177855
     /*  177855 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(177934), // Rule ID 24995 //
     /*  177860 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  177863 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177866 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177870 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177877 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  177882 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177886 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177890 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  177897 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  177897 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  177900 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  177922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177925 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  177928 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  177932 */   GIR_RootConstrainSelectedInstOperands,
     /*  177933 */   // GIR_Coverage, 24995,
     /*  177933 */   GIR_EraseRootFromParent_Done,
     /*  177934 */ // Label 2496: @177934
     /*  177934 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(178013), // Rule ID 25001 //
     /*  177939 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  177942 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  177945 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  177949 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  177956 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  177961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  177965 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  177969 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  177976 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  177976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  177979 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  177981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  177986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  177991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  177996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178004 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178007 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178011 */   GIR_RootConstrainSelectedInstOperands,
     /*  178012 */   // GIR_Coverage, 25001,
     /*  178012 */   GIR_EraseRootFromParent_Done,
     /*  178013 */ // Label 2497: @178013
     /*  178013 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(178092), // Rule ID 25002 //
     /*  178018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  178021 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178024 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178028 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  178035 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178048 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178055 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  178058 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178086 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178090 */   GIR_RootConstrainSelectedInstOperands,
     /*  178091 */   // GIR_Coverage, 25002,
     /*  178091 */   GIR_EraseRootFromParent_Done,
     /*  178092 */ // Label 2498: @178092
     /*  178092 */ GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(178171), // Rule ID 25003 //
     /*  178097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  178100 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178103 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178107 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  178114 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178119 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178123 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178127 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178134 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  178137 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178139 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178169 */   GIR_RootConstrainSelectedInstOperands,
     /*  178170 */   // GIR_Coverage, 25003,
     /*  178170 */   GIR_EraseRootFromParent_Done,
     /*  178171 */ // Label 2499: @178171
     /*  178171 */ GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(178250), // Rule ID 25004 //
     /*  178176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  178179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178182 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178186 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  178193 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178213 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  178216 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178241 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178244 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178248 */   GIR_RootConstrainSelectedInstOperands,
     /*  178249 */   // GIR_Coverage, 25004,
     /*  178249 */   GIR_EraseRootFromParent_Done,
     /*  178250 */ // Label 2500: @178250
     /*  178250 */ GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(178329), // Rule ID 25005 //
     /*  178255 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  178258 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178261 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178265 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  178272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178292 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  178295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178317 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178323 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178327 */   GIR_RootConstrainSelectedInstOperands,
     /*  178328 */   // GIR_Coverage, 25005,
     /*  178328 */   GIR_EraseRootFromParent_Done,
     /*  178329 */ // Label 2501: @178329
     /*  178329 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(178408), // Rule ID 25111 //
     /*  178334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  178337 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178340 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178344 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178351 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178360 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178364 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178371 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  178374 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178396 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178406 */   GIR_RootConstrainSelectedInstOperands,
     /*  178407 */   // GIR_Coverage, 25111,
     /*  178407 */   GIR_EraseRootFromParent_Done,
     /*  178408 */ // Label 2502: @178408
     /*  178408 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(178487), // Rule ID 25112 //
     /*  178413 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  178416 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178419 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178423 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178430 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178435 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178439 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178443 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178450 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178450 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  178453 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178475 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178478 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178481 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178485 */   GIR_RootConstrainSelectedInstOperands,
     /*  178486 */   // GIR_Coverage, 25112,
     /*  178486 */   GIR_EraseRootFromParent_Done,
     /*  178487 */ // Label 2503: @178487
     /*  178487 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(178566), // Rule ID 25113 //
     /*  178492 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  178495 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178498 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178502 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178522 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178529 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  178532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178554 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178557 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178560 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178564 */   GIR_RootConstrainSelectedInstOperands,
     /*  178565 */   // GIR_Coverage, 25113,
     /*  178565 */   GIR_EraseRootFromParent_Done,
     /*  178566 */ // Label 2504: @178566
     /*  178566 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(178645), // Rule ID 25114 //
     /*  178571 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  178574 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178577 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178581 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178588 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178593 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178597 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178601 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178608 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  178611 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178633 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178636 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178639 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178643 */   GIR_RootConstrainSelectedInstOperands,
     /*  178644 */   // GIR_Coverage, 25114,
     /*  178644 */   GIR_EraseRootFromParent_Done,
     /*  178645 */ // Label 2505: @178645
     /*  178645 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(178724), // Rule ID 25115 //
     /*  178650 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  178653 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178656 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178660 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178667 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178676 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178680 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178687 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178687 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  178690 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178715 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178718 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178722 */   GIR_RootConstrainSelectedInstOperands,
     /*  178723 */   // GIR_Coverage, 25115,
     /*  178723 */   GIR_EraseRootFromParent_Done,
     /*  178724 */ // Label 2506: @178724
     /*  178724 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(178803), // Rule ID 25121 //
     /*  178729 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  178732 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178735 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178746 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178751 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178755 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178759 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178766 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178766 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  178769 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178791 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178794 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178797 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178801 */   GIR_RootConstrainSelectedInstOperands,
     /*  178802 */   // GIR_Coverage, 25121,
     /*  178802 */   GIR_EraseRootFromParent_Done,
     /*  178803 */ // Label 2507: @178803
     /*  178803 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(178882), // Rule ID 25122 //
     /*  178808 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  178811 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178814 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178818 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178825 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178845 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  178848 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178870 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178873 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178876 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178880 */   GIR_RootConstrainSelectedInstOperands,
     /*  178881 */   // GIR_Coverage, 25122,
     /*  178881 */   GIR_EraseRootFromParent_Done,
     /*  178882 */ // Label 2508: @178882
     /*  178882 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(178961), // Rule ID 25123 //
     /*  178887 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  178890 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178893 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178897 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  178924 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  178924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  178927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  178929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  178934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  178939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  178944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  178949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178952 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  178955 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  178959 */   GIR_RootConstrainSelectedInstOperands,
     /*  178960 */   // GIR_Coverage, 25123,
     /*  178960 */   GIR_EraseRootFromParent_Done,
     /*  178961 */ // Label 2509: @178961
     /*  178961 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(179040), // Rule ID 25124 //
     /*  178966 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  178969 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  178972 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  178976 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  178983 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  178988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  178992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  178996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  179003 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  179003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  179006 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179038 */   GIR_RootConstrainSelectedInstOperands,
     /*  179039 */   // GIR_Coverage, 25124,
     /*  179039 */   GIR_EraseRootFromParent_Done,
     /*  179040 */ // Label 2510: @179040
     /*  179040 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(179119), // Rule ID 25125 //
     /*  179045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  179048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179051 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  179055 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  179062 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  179067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  179082 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  179082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  179085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179107 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179110 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179117 */   GIR_RootConstrainSelectedInstOperands,
     /*  179118 */   // GIR_Coverage, 25125,
     /*  179118 */   GIR_EraseRootFromParent_Done,
     /*  179119 */ // Label 2511: @179119
     /*  179119 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(179189), // Rule ID 15368 //
     /*  179124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  179127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179130 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179145 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179152 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179152 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179155 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179177 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179187 */   GIR_RootConstrainSelectedInstOperands,
     /*  179188 */   // GIR_Coverage, 15368,
     /*  179188 */   GIR_EraseRootFromParent_Done,
     /*  179189 */ // Label 2512: @179189
     /*  179189 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(179259), // Rule ID 15369 //
     /*  179194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  179197 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179211 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179215 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179222 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179225 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179247 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179250 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179253 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179257 */   GIR_RootConstrainSelectedInstOperands,
     /*  179258 */   // GIR_Coverage, 15369,
     /*  179258 */   GIR_EraseRootFromParent_Done,
     /*  179259 */ // Label 2513: @179259
     /*  179259 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(179329), // Rule ID 15370 //
     /*  179264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  179267 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179270 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179292 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179317 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179323 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179327 */   GIR_RootConstrainSelectedInstOperands,
     /*  179328 */   // GIR_Coverage, 15370,
     /*  179328 */   GIR_EraseRootFromParent_Done,
     /*  179329 */ // Label 2514: @179329
     /*  179329 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(179399), // Rule ID 15371 //
     /*  179334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  179337 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179340 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179362 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179365 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179390 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179397 */   GIR_RootConstrainSelectedInstOperands,
     /*  179398 */   // GIR_Coverage, 15371,
     /*  179398 */   GIR_EraseRootFromParent_Done,
     /*  179399 */ // Label 2515: @179399
     /*  179399 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(179469), // Rule ID 15372 //
     /*  179404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  179407 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179410 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179417 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179421 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179425 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179432 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179432 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179435 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179437 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179442 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179457 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179460 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179463 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179467 */   GIR_RootConstrainSelectedInstOperands,
     /*  179468 */   // GIR_Coverage, 15372,
     /*  179468 */   GIR_EraseRootFromParent_Done,
     /*  179469 */ // Label 2516: @179469
     /*  179469 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(179539), // Rule ID 15378 //
     /*  179474 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  179477 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179480 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179491 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179495 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179502 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179502 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  179505 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179527 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179537 */   GIR_RootConstrainSelectedInstOperands,
     /*  179538 */   // GIR_Coverage, 15378,
     /*  179538 */   GIR_EraseRootFromParent_Done,
     /*  179539 */ // Label 2517: @179539
     /*  179539 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(179609), // Rule ID 15379 //
     /*  179544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  179547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179572 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  179575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179597 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179600 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179603 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179607 */   GIR_RootConstrainSelectedInstOperands,
     /*  179608 */   // GIR_Coverage, 15379,
     /*  179608 */   GIR_EraseRootFromParent_Done,
     /*  179609 */ // Label 2518: @179609
     /*  179609 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(179679), // Rule ID 15380 //
     /*  179614 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  179617 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179642 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  179645 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179667 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179670 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179673 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179677 */   GIR_RootConstrainSelectedInstOperands,
     /*  179678 */   // GIR_Coverage, 15380,
     /*  179678 */   GIR_EraseRootFromParent_Done,
     /*  179679 */ // Label 2519: @179679
     /*  179679 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(179749), // Rule ID 15381 //
     /*  179684 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  179687 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179690 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179697 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179705 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179712 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  179715 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179737 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179740 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179743 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179747 */   GIR_RootConstrainSelectedInstOperands,
     /*  179748 */   // GIR_Coverage, 15381,
     /*  179748 */   GIR_EraseRootFromParent_Done,
     /*  179749 */ // Label 2520: @179749
     /*  179749 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(179819), // Rule ID 15382 //
     /*  179754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  179757 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179760 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179775 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179782 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  179785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179807 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179810 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179813 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179817 */   GIR_RootConstrainSelectedInstOperands,
     /*  179818 */   // GIR_Coverage, 15382,
     /*  179818 */   GIR_EraseRootFromParent_Done,
     /*  179819 */ // Label 2521: @179819
     /*  179819 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(179889), // Rule ID 15388 //
     /*  179824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  179827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179830 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179841 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179845 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179852 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179852 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179855 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179880 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179883 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179887 */   GIR_RootConstrainSelectedInstOperands,
     /*  179888 */   // GIR_Coverage, 15388,
     /*  179888 */   GIR_EraseRootFromParent_Done,
     /*  179889 */ // Label 2522: @179889
     /*  179889 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(179959), // Rule ID 15389 //
     /*  179894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  179897 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179900 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179911 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179915 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179922 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  179932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  179937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  179942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  179947 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179950 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  179953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  179957 */   GIR_RootConstrainSelectedInstOperands,
     /*  179958 */   // GIR_Coverage, 15389,
     /*  179958 */   GIR_EraseRootFromParent_Done,
     /*  179959 */ // Label 2523: @179959
     /*  179959 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(180029), // Rule ID 15390 //
     /*  179964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  179967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  179970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  179977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  179981 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  179985 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  179992 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  179992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  179995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  179997 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180017 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180027 */   GIR_RootConstrainSelectedInstOperands,
     /*  180028 */   // GIR_Coverage, 15390,
     /*  180028 */   GIR_EraseRootFromParent_Done,
     /*  180029 */ // Label 2524: @180029
     /*  180029 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(180099), // Rule ID 15391 //
     /*  180034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  180037 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180040 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180047 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180051 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180062 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  180065 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180077 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180087 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180090 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180093 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180097 */   GIR_RootConstrainSelectedInstOperands,
     /*  180098 */   // GIR_Coverage, 15391,
     /*  180098 */   GIR_EraseRootFromParent_Done,
     /*  180099 */ // Label 2525: @180099
     /*  180099 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(180169), // Rule ID 15392 //
     /*  180104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  180107 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180110 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180117 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180121 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180132 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  180135 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180157 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180163 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180167 */   GIR_RootConstrainSelectedInstOperands,
     /*  180168 */   // GIR_Coverage, 15392,
     /*  180168 */   GIR_EraseRootFromParent_Done,
     /*  180169 */ // Label 2526: @180169
     /*  180169 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(180239), // Rule ID 15398 //
     /*  180174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  180177 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180180 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180191 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180195 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180202 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180202 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  180205 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180227 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180230 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180233 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180237 */   GIR_RootConstrainSelectedInstOperands,
     /*  180238 */   // GIR_Coverage, 15398,
     /*  180238 */   GIR_EraseRootFromParent_Done,
     /*  180239 */ // Label 2527: @180239
     /*  180239 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(180309), // Rule ID 15399 //
     /*  180244 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  180247 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180250 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180261 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180265 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180272 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180272 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  180275 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180300 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180307 */   GIR_RootConstrainSelectedInstOperands,
     /*  180308 */   // GIR_Coverage, 15399,
     /*  180308 */   GIR_EraseRootFromParent_Done,
     /*  180309 */ // Label 2528: @180309
     /*  180309 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(180379), // Rule ID 15400 //
     /*  180314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  180317 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180320 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180331 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180335 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180342 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180342 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  180345 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180367 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180377 */   GIR_RootConstrainSelectedInstOperands,
     /*  180378 */   // GIR_Coverage, 15400,
     /*  180378 */   GIR_EraseRootFromParent_Done,
     /*  180379 */ // Label 2529: @180379
     /*  180379 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(180449), // Rule ID 15401 //
     /*  180384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  180387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180397 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180412 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  180415 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180447 */   GIR_RootConstrainSelectedInstOperands,
     /*  180448 */   // GIR_Coverage, 15401,
     /*  180448 */   GIR_EraseRootFromParent_Done,
     /*  180449 */ // Label 2530: @180449
     /*  180449 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(180519), // Rule ID 15402 //
     /*  180454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  180457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180460 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  180467 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180471 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180475 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  180482 */   // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  180482 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  180485 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180497 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180502 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180507 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180510 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180513 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180517 */   GIR_RootConstrainSelectedInstOperands,
     /*  180518 */   // GIR_Coverage, 15402,
     /*  180518 */   GIR_EraseRootFromParent_Done,
     /*  180519 */ // Label 2531: @180519
     /*  180519 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(180587), // Rule ID 25171 //
     /*  180524 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  180527 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180530 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180539 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180543 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180550 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  180553 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180575 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180578 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180581 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180585 */   GIR_RootConstrainSelectedInstOperands,
     /*  180586 */   // GIR_Coverage, 25171,
     /*  180586 */   GIR_EraseRootFromParent_Done,
     /*  180587 */ // Label 2532: @180587
     /*  180587 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(180655), // Rule ID 25172 //
     /*  180592 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  180595 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180598 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180607 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180611 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180618 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  180621 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180643 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180653 */   GIR_RootConstrainSelectedInstOperands,
     /*  180654 */   // GIR_Coverage, 25172,
     /*  180654 */   GIR_EraseRootFromParent_Done,
     /*  180655 */ // Label 2533: @180655
     /*  180655 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(180723), // Rule ID 25173 //
     /*  180660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  180663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180666 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180671 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180675 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180679 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180686 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180686 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  180689 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180714 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180717 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180721 */   GIR_RootConstrainSelectedInstOperands,
     /*  180722 */   // GIR_Coverage, 25173,
     /*  180722 */   GIR_EraseRootFromParent_Done,
     /*  180723 */ // Label 2534: @180723
     /*  180723 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(180791), // Rule ID 25174 //
     /*  180728 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  180731 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180734 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180739 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180743 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180747 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180754 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180754 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  180757 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180789 */   GIR_RootConstrainSelectedInstOperands,
     /*  180790 */   // GIR_Coverage, 25174,
     /*  180790 */   GIR_EraseRootFromParent_Done,
     /*  180791 */ // Label 2535: @180791
     /*  180791 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(180859), // Rule ID 25175 //
     /*  180796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  180799 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180811 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180815 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180822 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  180825 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180847 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180850 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180853 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180857 */   GIR_RootConstrainSelectedInstOperands,
     /*  180858 */   // GIR_Coverage, 25175,
     /*  180858 */   GIR_EraseRootFromParent_Done,
     /*  180859 */ // Label 2536: @180859
     /*  180859 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(180927), // Rule ID 25181 //
     /*  180864 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  180867 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180870 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180875 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180879 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180883 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180890 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180890 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  180893 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180915 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180918 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180925 */   GIR_RootConstrainSelectedInstOperands,
     /*  180926 */   // GIR_Coverage, 25181,
     /*  180926 */   GIR_EraseRootFromParent_Done,
     /*  180927 */ // Label 2537: @180927
     /*  180927 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(180995), // Rule ID 25182 //
     /*  180932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  180935 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  180938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  180943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  180947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  180951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  180958 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  180958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  180961 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  180963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  180968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  180973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  180978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  180983 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180986 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  180989 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  180993 */   GIR_RootConstrainSelectedInstOperands,
     /*  180994 */   // GIR_Coverage, 25182,
     /*  180994 */   GIR_EraseRootFromParent_Done,
     /*  180995 */ // Label 2538: @180995
     /*  180995 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(181063), // Rule ID 25183 //
     /*  181000 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  181003 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181006 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181026 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181051 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181054 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181057 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181061 */   GIR_RootConstrainSelectedInstOperands,
     /*  181062 */   // GIR_Coverage, 25183,
     /*  181062 */   GIR_EraseRootFromParent_Done,
     /*  181063 */ // Label 2539: @181063
     /*  181063 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(181131), // Rule ID 25184 //
     /*  181068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  181071 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181074 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181094 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181094 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181097 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181119 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181122 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181125 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181129 */   GIR_RootConstrainSelectedInstOperands,
     /*  181130 */   // GIR_Coverage, 25184,
     /*  181130 */   GIR_EraseRootFromParent_Done,
     /*  181131 */ // Label 2540: @181131
     /*  181131 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(181199), // Rule ID 25185 //
     /*  181136 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  181139 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181142 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181151 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181155 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181162 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181162 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181165 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181190 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181193 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181197 */   GIR_RootConstrainSelectedInstOperands,
     /*  181198 */   // GIR_Coverage, 25185,
     /*  181198 */   GIR_EraseRootFromParent_Done,
     /*  181199 */ // Label 2541: @181199
     /*  181199 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(181267), // Rule ID 25191 //
     /*  181204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  181207 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181210 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181223 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181230 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181230 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  181233 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181255 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181258 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181261 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181265 */   GIR_RootConstrainSelectedInstOperands,
     /*  181266 */   // GIR_Coverage, 25191,
     /*  181266 */   GIR_EraseRootFromParent_Done,
     /*  181267 */ // Label 2542: @181267
     /*  181267 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(181335), // Rule ID 25192 //
     /*  181272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  181275 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181278 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181287 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181298 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  181301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181333 */   GIR_RootConstrainSelectedInstOperands,
     /*  181334 */   // GIR_Coverage, 25192,
     /*  181334 */   GIR_EraseRootFromParent_Done,
     /*  181335 */ // Label 2543: @181335
     /*  181335 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(181403), // Rule ID 25193 //
     /*  181340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  181343 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181355 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181359 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181366 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  181369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181391 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181394 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181397 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181401 */   GIR_RootConstrainSelectedInstOperands,
     /*  181402 */   // GIR_Coverage, 25193,
     /*  181402 */   GIR_EraseRootFromParent_Done,
     /*  181403 */ // Label 2544: @181403
     /*  181403 */ GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(181471), // Rule ID 25194 //
     /*  181408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  181411 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181414 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181434 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  181437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181459 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181462 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181465 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181469 */   GIR_RootConstrainSelectedInstOperands,
     /*  181470 */   // GIR_Coverage, 25194,
     /*  181470 */   GIR_EraseRootFromParent_Done,
     /*  181471 */ // Label 2545: @181471
     /*  181471 */ GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(181539), // Rule ID 25195 //
     /*  181476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  181479 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181482 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181491 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181495 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181502 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181502 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  181505 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181527 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181537 */   GIR_RootConstrainSelectedInstOperands,
     /*  181538 */   // GIR_Coverage, 25195,
     /*  181538 */   GIR_EraseRootFromParent_Done,
     /*  181539 */ // Label 2546: @181539
     /*  181539 */ GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(181607), // Rule ID 25201 //
     /*  181544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  181547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181559 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181563 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181570 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181570 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181573 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181595 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181598 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181601 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181605 */   GIR_RootConstrainSelectedInstOperands,
     /*  181606 */   // GIR_Coverage, 25201,
     /*  181606 */   GIR_EraseRootFromParent_Done,
     /*  181607 */ // Label 2547: @181607
     /*  181607 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(181675), // Rule ID 25202 //
     /*  181612 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  181615 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181627 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181631 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181638 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181638 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181641 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181663 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181666 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181669 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181673 */   GIR_RootConstrainSelectedInstOperands,
     /*  181674 */   // GIR_Coverage, 25202,
     /*  181674 */   GIR_EraseRootFromParent_Done,
     /*  181675 */ // Label 2548: @181675
     /*  181675 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(181743), // Rule ID 25203 //
     /*  181680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  181683 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181686 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181691 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181695 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181699 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181706 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181706 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181709 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181731 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181741 */   GIR_RootConstrainSelectedInstOperands,
     /*  181742 */   // GIR_Coverage, 25203,
     /*  181742 */   GIR_EraseRootFromParent_Done,
     /*  181743 */ // Label 2549: @181743
     /*  181743 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(181811), // Rule ID 25204 //
     /*  181748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  181751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181774 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181799 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181802 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181805 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181809 */   GIR_RootConstrainSelectedInstOperands,
     /*  181810 */   // GIR_Coverage, 25204,
     /*  181810 */   GIR_EraseRootFromParent_Done,
     /*  181811 */ // Label 2550: @181811
     /*  181811 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(181879), // Rule ID 25205 //
     /*  181816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  181819 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  181822 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  181827 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181831 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181835 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  181842 */   // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  181842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  181845 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  181852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  181862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  181867 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181870 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181873 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181877 */   GIR_RootConstrainSelectedInstOperands,
     /*  181878 */   // GIR_Coverage, 25205,
     /*  181878 */   GIR_EraseRootFromParent_Done,
     /*  181879 */ // Label 2551: @181879
     /*  181879 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(181955), // Rule ID 15033 //
     /*  181884 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  181887 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  181890 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  181894 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  181901 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  181908 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181912 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181916 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  181923 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  181923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  181926 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  181928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  181933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  181938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  181943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181946 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  181949 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  181953 */   GIR_RootConstrainSelectedInstOperands,
     /*  181954 */   // GIR_Coverage, 15033,
     /*  181954 */   GIR_EraseRootFromParent_Done,
     /*  181955 */ // Label 2552: @181955
     /*  181955 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(182031), // Rule ID 15034 //
     /*  181960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  181963 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  181966 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  181970 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  181977 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  181984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  181988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  181992 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  181999 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  181999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  182002 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182022 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182029 */   GIR_RootConstrainSelectedInstOperands,
     /*  182030 */   // GIR_Coverage, 15034,
     /*  182030 */   GIR_EraseRootFromParent_Done,
     /*  182031 */ // Label 2553: @182031
     /*  182031 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(182107), // Rule ID 15035 //
     /*  182036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  182039 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182042 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182046 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182060 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182064 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182068 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182075 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  182078 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182095 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182098 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182101 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182105 */   GIR_RootConstrainSelectedInstOperands,
     /*  182106 */   // GIR_Coverage, 15035,
     /*  182106 */   GIR_EraseRootFromParent_Done,
     /*  182107 */ // Label 2554: @182107
     /*  182107 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(182183), // Rule ID 15036 //
     /*  182112 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  182115 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182118 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182122 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182151 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  182154 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182181 */   GIR_RootConstrainSelectedInstOperands,
     /*  182182 */   // GIR_Coverage, 15036,
     /*  182182 */   GIR_EraseRootFromParent_Done,
     /*  182183 */ // Label 2555: @182183
     /*  182183 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(182259), // Rule ID 15037 //
     /*  182188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  182191 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182194 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182198 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182205 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182216 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182220 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182227 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182227 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  182230 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182247 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182250 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182253 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182257 */   GIR_RootConstrainSelectedInstOperands,
     /*  182258 */   // GIR_Coverage, 15037,
     /*  182258 */   GIR_EraseRootFromParent_Done,
     /*  182259 */ // Label 2556: @182259
     /*  182259 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(182335), // Rule ID 15053 //
     /*  182264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  182267 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182270 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182274 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182281 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182288 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182292 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182296 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182303 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  182306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182333 */   GIR_RootConstrainSelectedInstOperands,
     /*  182334 */   // GIR_Coverage, 15053,
     /*  182334 */   GIR_EraseRootFromParent_Done,
     /*  182335 */ // Label 2557: @182335
     /*  182335 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(182411), // Rule ID 15054 //
     /*  182340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  182343 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182346 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182350 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182357 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182368 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182372 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182379 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182379 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  182382 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182402 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182405 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182409 */   GIR_RootConstrainSelectedInstOperands,
     /*  182410 */   // GIR_Coverage, 15054,
     /*  182410 */   GIR_EraseRootFromParent_Done,
     /*  182411 */ // Label 2558: @182411
     /*  182411 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(182487), // Rule ID 15055 //
     /*  182416 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  182419 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182422 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182426 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182433 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182444 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182448 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182455 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182455 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  182458 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182475 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182478 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182481 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182485 */   GIR_RootConstrainSelectedInstOperands,
     /*  182486 */   // GIR_Coverage, 15055,
     /*  182486 */   GIR_EraseRootFromParent_Done,
     /*  182487 */ // Label 2559: @182487
     /*  182487 */ GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(182563), // Rule ID 15056 //
     /*  182492 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  182495 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182498 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182502 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182520 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182524 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182531 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182531 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  182534 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182541 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182551 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182554 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182557 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182561 */   GIR_RootConstrainSelectedInstOperands,
     /*  182562 */   // GIR_Coverage, 15056,
     /*  182562 */   GIR_EraseRootFromParent_Done,
     /*  182563 */ // Label 2560: @182563
     /*  182563 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(182639), // Rule ID 15057 //
     /*  182568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  182571 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182574 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182578 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  182585 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182600 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182607 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182607 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  182610 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182627 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182630 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182633 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182637 */   GIR_RootConstrainSelectedInstOperands,
     /*  182638 */   // GIR_Coverage, 15057,
     /*  182638 */   GIR_EraseRootFromParent_Done,
     /*  182639 */ // Label 2561: @182639
     /*  182639 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(182715), // Rule ID 15083 //
     /*  182644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  182647 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182650 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182654 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  182661 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182668 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182672 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182676 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182683 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  182686 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182703 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182706 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182709 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182713 */   GIR_RootConstrainSelectedInstOperands,
     /*  182714 */   // GIR_Coverage, 15083,
     /*  182714 */   GIR_EraseRootFromParent_Done,
     /*  182715 */ // Label 2562: @182715
     /*  182715 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(182791), // Rule ID 15084 //
     /*  182720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  182723 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182726 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182730 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  182737 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182759 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  182762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182789 */   GIR_RootConstrainSelectedInstOperands,
     /*  182790 */   // GIR_Coverage, 15084,
     /*  182790 */   GIR_EraseRootFromParent_Done,
     /*  182791 */ // Label 2563: @182791
     /*  182791 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(182867), // Rule ID 15085 //
     /*  182796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  182799 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182802 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182806 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  182813 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182820 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182824 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182828 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182835 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182835 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  182838 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182855 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182858 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182861 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182865 */   GIR_RootConstrainSelectedInstOperands,
     /*  182866 */   // GIR_Coverage, 15085,
     /*  182866 */   GIR_EraseRootFromParent_Done,
     /*  182867 */ // Label 2564: @182867
     /*  182867 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(182943), // Rule ID 15086 //
     /*  182872 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  182875 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182878 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182882 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  182889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182904 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182911 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  182914 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  182926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  182931 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182934 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  182937 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  182941 */   GIR_RootConstrainSelectedInstOperands,
     /*  182942 */   // GIR_Coverage, 15086,
     /*  182942 */   GIR_EraseRootFromParent_Done,
     /*  182943 */ // Label 2565: @182943
     /*  182943 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(183019), // Rule ID 15087 //
     /*  182948 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  182951 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  182954 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  182958 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  182965 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  182972 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  182976 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  182980 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  182987 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  182987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  182990 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  182992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  182997 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183007 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183010 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183013 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183017 */   GIR_RootConstrainSelectedInstOperands,
     /*  183018 */   // GIR_Coverage, 15087,
     /*  183018 */   GIR_EraseRootFromParent_Done,
     /*  183019 */ // Label 2566: @183019
     /*  183019 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(183095), // Rule ID 15093 //
     /*  183024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  183027 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  183030 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183034 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  183041 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183052 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183056 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183063 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  183066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183093 */   GIR_RootConstrainSelectedInstOperands,
     /*  183094 */   // GIR_Coverage, 15093,
     /*  183094 */   GIR_EraseRootFromParent_Done,
     /*  183095 */ // Label 2567: @183095
     /*  183095 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(183171), // Rule ID 15094 //
     /*  183100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  183103 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  183106 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  183117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183139 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  183142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183169 */   GIR_RootConstrainSelectedInstOperands,
     /*  183170 */   // GIR_Coverage, 15094,
     /*  183170 */   GIR_EraseRootFromParent_Done,
     /*  183171 */ // Label 2568: @183171
     /*  183171 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(183247), // Rule ID 15095 //
     /*  183176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  183179 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  183182 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183186 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  183193 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183204 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183208 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183215 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183215 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  183218 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183241 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183245 */   GIR_RootConstrainSelectedInstOperands,
     /*  183246 */   // GIR_Coverage, 15095,
     /*  183246 */   GIR_EraseRootFromParent_Done,
     /*  183247 */ // Label 2569: @183247
     /*  183247 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(183323), // Rule ID 15096 //
     /*  183252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  183255 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  183258 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183262 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  183269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183291 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  183294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183314 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183317 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183321 */   GIR_RootConstrainSelectedInstOperands,
     /*  183322 */   // GIR_Coverage, 15096,
     /*  183322 */   GIR_EraseRootFromParent_Done,
     /*  183323 */ // Label 2570: @183323
     /*  183323 */ GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(183399), // Rule ID 15097 //
     /*  183328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  183331 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  183334 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183338 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  183345 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183352 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183356 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183360 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183367 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183367 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  183370 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183390 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183397 */   GIR_RootConstrainSelectedInstOperands,
     /*  183398 */   // GIR_Coverage, 15097,
     /*  183398 */   GIR_EraseRootFromParent_Done,
     /*  183399 */ // Label 2571: @183399
     /*  183399 */ GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(183475), // Rule ID 15183 //
     /*  183404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  183407 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183410 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183414 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183421 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183432 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183436 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183443 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183443 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  183446 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183463 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183466 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183469 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183473 */   GIR_RootConstrainSelectedInstOperands,
     /*  183474 */   // GIR_Coverage, 15183,
     /*  183474 */   GIR_EraseRootFromParent_Done,
     /*  183475 */ // Label 2572: @183475
     /*  183475 */ GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(183551), // Rule ID 15184 //
     /*  183480 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  183483 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183486 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183490 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183497 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183519 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  183522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183539 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183542 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183549 */   GIR_RootConstrainSelectedInstOperands,
     /*  183550 */   // GIR_Coverage, 15184,
     /*  183550 */   GIR_EraseRootFromParent_Done,
     /*  183551 */ // Label 2573: @183551
     /*  183551 */ GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(183627), // Rule ID 15185 //
     /*  183556 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  183559 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183562 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183566 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183573 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183580 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183584 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183588 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183595 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183595 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  183598 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183615 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183618 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183621 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183625 */   GIR_RootConstrainSelectedInstOperands,
     /*  183626 */   // GIR_Coverage, 15185,
     /*  183626 */   GIR_EraseRootFromParent_Done,
     /*  183627 */ // Label 2574: @183627
     /*  183627 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(183703), // Rule ID 15186 //
     /*  183632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  183635 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183638 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183642 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183660 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183664 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183671 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  183674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183691 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183694 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183697 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183701 */   GIR_RootConstrainSelectedInstOperands,
     /*  183702 */   // GIR_Coverage, 15186,
     /*  183702 */   GIR_EraseRootFromParent_Done,
     /*  183703 */ // Label 2575: @183703
     /*  183703 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(183779), // Rule ID 15187 //
     /*  183708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  183711 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183714 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183718 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183725 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183736 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183740 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183747 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183747 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  183750 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183757 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183767 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183770 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183773 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183777 */   GIR_RootConstrainSelectedInstOperands,
     /*  183778 */   // GIR_Coverage, 15187,
     /*  183778 */   GIR_EraseRootFromParent_Done,
     /*  183779 */ // Label 2576: @183779
     /*  183779 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(183855), // Rule ID 15193 //
     /*  183784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  183787 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183790 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183794 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183801 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183808 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183812 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183816 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183823 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183823 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  183826 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183843 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183846 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183849 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183853 */   GIR_RootConstrainSelectedInstOperands,
     /*  183854 */   // GIR_Coverage, 15193,
     /*  183854 */   GIR_EraseRootFromParent_Done,
     /*  183855 */ // Label 2577: @183855
     /*  183855 */ GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(183931), // Rule ID 15194 //
     /*  183860 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  183863 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183866 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183870 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183877 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183884 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183888 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183892 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183899 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183899 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  183902 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  183929 */   GIR_RootConstrainSelectedInstOperands,
     /*  183930 */   // GIR_Coverage, 15194,
     /*  183930 */   GIR_EraseRootFromParent_Done,
     /*  183931 */ // Label 2578: @183931
     /*  183931 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(184007), // Rule ID 15195 //
     /*  183936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  183939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  183942 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  183946 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  183953 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  183960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  183964 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  183968 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  183975 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  183975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  183978 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  183980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  183985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  183990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  183995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  183998 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184001 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184005 */   GIR_RootConstrainSelectedInstOperands,
     /*  184006 */   // GIR_Coverage, 15195,
     /*  184006 */   GIR_EraseRootFromParent_Done,
     /*  184007 */ // Label 2579: @184007
     /*  184007 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(184083), // Rule ID 15196 //
     /*  184012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  184015 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184018 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184022 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  184029 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184036 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184040 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184044 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184051 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  184054 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184081 */   GIR_RootConstrainSelectedInstOperands,
     /*  184082 */   // GIR_Coverage, 15196,
     /*  184082 */   GIR_EraseRootFromParent_Done,
     /*  184083 */ // Label 2580: @184083
     /*  184083 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(184159), // Rule ID 15197 //
     /*  184088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  184091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184094 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184098 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  184105 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184112 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184116 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184120 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184127 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  184130 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184147 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184150 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184153 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184157 */   GIR_RootConstrainSelectedInstOperands,
     /*  184158 */   // GIR_Coverage, 15197,
     /*  184158 */   GIR_EraseRootFromParent_Done,
     /*  184159 */ // Label 2581: @184159
     /*  184159 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(184235), // Rule ID 15283 //
     /*  184164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  184167 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184170 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184174 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184181 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184192 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184196 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184203 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  184206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184223 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184226 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184229 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184233 */   GIR_RootConstrainSelectedInstOperands,
     /*  184234 */   // GIR_Coverage, 15283,
     /*  184234 */   GIR_EraseRootFromParent_Done,
     /*  184235 */ // Label 2582: @184235
     /*  184235 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(184311), // Rule ID 15284 //
     /*  184240 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  184243 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184246 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184250 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184257 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184279 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  184282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184302 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184309 */   GIR_RootConstrainSelectedInstOperands,
     /*  184310 */   // GIR_Coverage, 15284,
     /*  184310 */   GIR_EraseRootFromParent_Done,
     /*  184311 */ // Label 2583: @184311
     /*  184311 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(184387), // Rule ID 15285 //
     /*  184316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  184319 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184322 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184326 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184344 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184355 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  184358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184381 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184385 */   GIR_RootConstrainSelectedInstOperands,
     /*  184386 */   // GIR_Coverage, 15285,
     /*  184386 */   GIR_EraseRootFromParent_Done,
     /*  184387 */ // Label 2584: @184387
     /*  184387 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(184463), // Rule ID 15286 //
     /*  184392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  184395 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184398 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184402 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184409 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184420 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184424 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184431 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184431 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  184434 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184451 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184457 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184461 */   GIR_RootConstrainSelectedInstOperands,
     /*  184462 */   // GIR_Coverage, 15286,
     /*  184462 */   GIR_EraseRootFromParent_Done,
     /*  184463 */ // Label 2585: @184463
     /*  184463 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(184539), // Rule ID 15287 //
     /*  184468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  184471 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184474 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184485 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184496 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184500 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184507 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184507 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  184510 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184527 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184537 */   GIR_RootConstrainSelectedInstOperands,
     /*  184538 */   // GIR_Coverage, 15287,
     /*  184538 */   GIR_EraseRootFromParent_Done,
     /*  184539 */ // Label 2586: @184539
     /*  184539 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(184615), // Rule ID 15293 //
     /*  184544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  184547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184550 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184568 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184572 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184576 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184583 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184583 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  184586 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184613 */   GIR_RootConstrainSelectedInstOperands,
     /*  184614 */   // GIR_Coverage, 15293,
     /*  184614 */   GIR_EraseRootFromParent_Done,
     /*  184615 */ // Label 2587: @184615
     /*  184615 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(184691), // Rule ID 15294 //
     /*  184620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  184623 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184626 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184637 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184659 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  184662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184679 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184682 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184689 */   GIR_RootConstrainSelectedInstOperands,
     /*  184690 */   // GIR_Coverage, 15294,
     /*  184690 */   GIR_EraseRootFromParent_Done,
     /*  184691 */ // Label 2588: @184691
     /*  184691 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(184767), // Rule ID 15295 //
     /*  184696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  184699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184702 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184706 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184724 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184728 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184735 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184735 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  184738 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184765 */   GIR_RootConstrainSelectedInstOperands,
     /*  184766 */   // GIR_Coverage, 15295,
     /*  184766 */   GIR_EraseRootFromParent_Done,
     /*  184767 */ // Label 2589: @184767
     /*  184767 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(184843), // Rule ID 15296 //
     /*  184772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  184775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184778 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184782 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184789 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184804 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184811 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  184814 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184831 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184834 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184837 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184841 */   GIR_RootConstrainSelectedInstOperands,
     /*  184842 */   // GIR_Coverage, 15296,
     /*  184842 */   GIR_EraseRootFromParent_Done,
     /*  184843 */ // Label 2590: @184843
     /*  184843 */ GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(184919), // Rule ID 15297 //
     /*  184848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  184851 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184854 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  184858 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  184865 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184887 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  184890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184907 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184910 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184913 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184917 */   GIR_RootConstrainSelectedInstOperands,
     /*  184918 */   // GIR_Coverage, 15297,
     /*  184918 */   GIR_EraseRootFromParent_Done,
     /*  184919 */ // Label 2591: @184919
     /*  184919 */ GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(184984), // Rule ID 15363 //
     /*  184924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  184927 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184930 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  184937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  184941 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  184945 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  184952 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  184952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  184955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  184957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  184962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  184967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  184972 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  184978 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  184982 */   GIR_RootConstrainSelectedInstOperands,
     /*  184983 */   // GIR_Coverage, 15363,
     /*  184983 */   GIR_EraseRootFromParent_Done,
     /*  184984 */ // Label 2592: @184984
     /*  184984 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(185049), // Rule ID 15364 //
     /*  184989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  184992 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  184995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185010 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185017 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185040 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185047 */   GIR_RootConstrainSelectedInstOperands,
     /*  185048 */   // GIR_Coverage, 15364,
     /*  185048 */   GIR_EraseRootFromParent_Done,
     /*  185049 */ // Label 2593: @185049
     /*  185049 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(185114), // Rule ID 15365 //
     /*  185054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  185057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185082 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185102 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185105 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185108 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185112 */   GIR_RootConstrainSelectedInstOperands,
     /*  185113 */   // GIR_Coverage, 15365,
     /*  185113 */   GIR_EraseRootFromParent_Done,
     /*  185114 */ // Label 2594: @185114
     /*  185114 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(185179), // Rule ID 15366 //
     /*  185119 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  185122 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185125 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185147 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185173 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185177 */   GIR_RootConstrainSelectedInstOperands,
     /*  185178 */   // GIR_Coverage, 15366,
     /*  185178 */   GIR_EraseRootFromParent_Done,
     /*  185179 */ // Label 2595: @185179
     /*  185179 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(185244), // Rule ID 15367 //
     /*  185184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  185187 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185190 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185201 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185205 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185212 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185212 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185215 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185242 */   GIR_RootConstrainSelectedInstOperands,
     /*  185243 */   // GIR_Coverage, 15367,
     /*  185243 */   GIR_EraseRootFromParent_Done,
     /*  185244 */ // Label 2596: @185244
     /*  185244 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(185309), // Rule ID 15373 //
     /*  185249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  185252 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185255 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185266 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185270 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185277 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185280 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185300 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185307 */   GIR_RootConstrainSelectedInstOperands,
     /*  185308 */   // GIR_Coverage, 15373,
     /*  185308 */   GIR_EraseRootFromParent_Done,
     /*  185309 */ // Label 2597: @185309
     /*  185309 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(185374), // Rule ID 15374 //
     /*  185314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  185317 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185320 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185331 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185335 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185342 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185342 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185345 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185362 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185365 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185372 */   GIR_RootConstrainSelectedInstOperands,
     /*  185373 */   // GIR_Coverage, 15374,
     /*  185373 */   GIR_EraseRootFromParent_Done,
     /*  185374 */ // Label 2598: @185374
     /*  185374 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(185439), // Rule ID 15375 //
     /*  185379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  185382 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185385 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185407 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185430 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185433 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185437 */   GIR_RootConstrainSelectedInstOperands,
     /*  185438 */   // GIR_Coverage, 15375,
     /*  185438 */   GIR_EraseRootFromParent_Done,
     /*  185439 */ // Label 2599: @185439
     /*  185439 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(185504), // Rule ID 15376 //
     /*  185444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  185447 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185472 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185495 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185498 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185502 */   GIR_RootConstrainSelectedInstOperands,
     /*  185503 */   // GIR_Coverage, 15376,
     /*  185503 */   GIR_EraseRootFromParent_Done,
     /*  185504 */ // Label 2600: @185504
     /*  185504 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(185569), // Rule ID 15377 //
     /*  185509 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  185512 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185515 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185526 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185530 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185537 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185540 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185557 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185560 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185563 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185567 */   GIR_RootConstrainSelectedInstOperands,
     /*  185568 */   // GIR_Coverage, 15377,
     /*  185568 */   GIR_EraseRootFromParent_Done,
     /*  185569 */ // Label 2601: @185569
     /*  185569 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(185634), // Rule ID 15383 //
     /*  185574 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  185577 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185580 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185587 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185591 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185595 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185602 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185605 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185625 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185628 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185632 */   GIR_RootConstrainSelectedInstOperands,
     /*  185633 */   // GIR_Coverage, 15383,
     /*  185633 */   GIR_EraseRootFromParent_Done,
     /*  185634 */ // Label 2602: @185634
     /*  185634 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(185699), // Rule ID 15384 //
     /*  185639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  185642 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185645 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185652 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185656 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185660 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185667 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185667 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185670 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185687 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185690 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185693 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185697 */   GIR_RootConstrainSelectedInstOperands,
     /*  185698 */   // GIR_Coverage, 15384,
     /*  185698 */   GIR_EraseRootFromParent_Done,
     /*  185699 */ // Label 2603: @185699
     /*  185699 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(185764), // Rule ID 15385 //
     /*  185704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  185707 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185710 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185721 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185725 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185732 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185732 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185735 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185752 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185758 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185762 */   GIR_RootConstrainSelectedInstOperands,
     /*  185763 */   // GIR_Coverage, 15385,
     /*  185763 */   GIR_EraseRootFromParent_Done,
     /*  185764 */ // Label 2604: @185764
     /*  185764 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(185829), // Rule ID 15386 //
     /*  185769 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  185772 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185782 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185786 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185790 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185797 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185797 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185800 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185807 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185817 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185820 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185823 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185827 */   GIR_RootConstrainSelectedInstOperands,
     /*  185828 */   // GIR_Coverage, 15386,
     /*  185828 */   GIR_EraseRootFromParent_Done,
     /*  185829 */ // Label 2605: @185829
     /*  185829 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(185894), // Rule ID 15387 //
     /*  185834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  185837 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185840 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185855 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185862 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  185865 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185885 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185888 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185892 */   GIR_RootConstrainSelectedInstOperands,
     /*  185893 */   // GIR_Coverage, 15387,
     /*  185893 */   GIR_EraseRootFromParent_Done,
     /*  185894 */ // Label 2606: @185894
     /*  185894 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(185959), // Rule ID 15393 //
     /*  185899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  185902 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185905 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185916 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185920 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185927 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185927 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185930 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  185937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  185942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  185947 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185950 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  185953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  185957 */   GIR_RootConstrainSelectedInstOperands,
     /*  185958 */   // GIR_Coverage, 15393,
     /*  185958 */   GIR_EraseRootFromParent_Done,
     /*  185959 */ // Label 2607: @185959
     /*  185959 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(186024), // Rule ID 15394 //
     /*  185964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  185967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  185970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  185977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  185981 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  185985 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  185992 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  185992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  185995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  185997 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  186002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  186007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  186012 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186015 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186018 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186022 */   GIR_RootConstrainSelectedInstOperands,
     /*  186023 */   // GIR_Coverage, 15394,
     /*  186023 */   GIR_EraseRootFromParent_Done,
     /*  186024 */ // Label 2608: @186024
     /*  186024 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(186089), // Rule ID 15395 //
     /*  186029 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  186032 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186035 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  186042 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186046 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186050 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  186057 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  186057 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  186060 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  186062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  186067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  186072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  186077 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186087 */   GIR_RootConstrainSelectedInstOperands,
     /*  186088 */   // GIR_Coverage, 15395,
     /*  186088 */   GIR_EraseRootFromParent_Done,
     /*  186089 */ // Label 2609: @186089
     /*  186089 */ GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(186154), // Rule ID 15396 //
     /*  186094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  186097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186100 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  186107 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186111 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186115 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  186122 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  186122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  186125 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  186127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  186132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  186137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  186142 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186145 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186148 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186152 */   GIR_RootConstrainSelectedInstOperands,
     /*  186153 */   // GIR_Coverage, 15396,
     /*  186153 */   GIR_EraseRootFromParent_Done,
     /*  186154 */ // Label 2610: @186154
     /*  186154 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(186219), // Rule ID 15397 //
     /*  186159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  186162 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186165 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  186172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186176 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186180 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  186187 */   // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  186187 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  186190 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  186192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  186197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  186202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  186207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186217 */   GIR_RootConstrainSelectedInstOperands,
     /*  186218 */   // GIR_Coverage, 15397,
     /*  186218 */   GIR_EraseRootFromParent_Done,
     /*  186219 */ // Label 2611: @186219
     /*  186219 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(186285), // Rule ID 28799 //
     /*  186224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  186227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186230 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186261 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  186264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186283 */   GIR_RootConstrainSelectedInstOperands,
     /*  186284 */   // GIR_Coverage, 28799,
     /*  186284 */   GIR_EraseRootFromParent_Done,
     /*  186285 */ // Label 2612: @186285
     /*  186285 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(186351), // Rule ID 28800 //
     /*  186290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  186293 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186296 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186300 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186307 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186316 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186320 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186327 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186327 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  186330 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186342 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186349 */   GIR_RootConstrainSelectedInstOperands,
     /*  186350 */   // GIR_Coverage, 28800,
     /*  186350 */   GIR_EraseRootFromParent_Done,
     /*  186351 */ // Label 2613: @186351
     /*  186351 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(186417), // Rule ID 28801 //
     /*  186356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  186359 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186362 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186366 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186373 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186382 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186393 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  186396 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186415 */   GIR_RootConstrainSelectedInstOperands,
     /*  186416 */   // GIR_Coverage, 28801,
     /*  186416 */   GIR_EraseRootFromParent_Done,
     /*  186417 */ // Label 2614: @186417
     /*  186417 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(186483), // Rule ID 28802 //
     /*  186422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  186425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186428 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186432 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186439 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186459 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  186462 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186474 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186477 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186481 */   GIR_RootConstrainSelectedInstOperands,
     /*  186482 */   // GIR_Coverage, 28802,
     /*  186482 */   GIR_EraseRootFromParent_Done,
     /*  186483 */ // Label 2615: @186483
     /*  186483 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(186549), // Rule ID 28803 //
     /*  186488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  186491 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186494 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186498 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186505 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186525 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  186528 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186547 */   GIR_RootConstrainSelectedInstOperands,
     /*  186548 */   // GIR_Coverage, 28803,
     /*  186548 */   GIR_EraseRootFromParent_Done,
     /*  186549 */ // Label 2616: @186549
     /*  186549 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(186615), // Rule ID 28804 //
     /*  186554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  186557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186560 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186564 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186571 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186591 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  186594 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186613 */   GIR_RootConstrainSelectedInstOperands,
     /*  186614 */   // GIR_Coverage, 28804,
     /*  186614 */   GIR_EraseRootFromParent_Done,
     /*  186615 */ // Label 2617: @186615
     /*  186615 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(186681), // Rule ID 28805 //
     /*  186620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  186623 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186626 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186637 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186642 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186646 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186650 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186657 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  186660 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186672 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186675 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186679 */   GIR_RootConstrainSelectedInstOperands,
     /*  186680 */   // GIR_Coverage, 28805,
     /*  186680 */   GIR_EraseRootFromParent_Done,
     /*  186681 */ // Label 2618: @186681
     /*  186681 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(186747), // Rule ID 28806 //
     /*  186686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  186689 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186692 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186696 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186712 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186716 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186723 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186723 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  186726 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186738 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186745 */   GIR_RootConstrainSelectedInstOperands,
     /*  186746 */   // GIR_Coverage, 28806,
     /*  186746 */   GIR_EraseRootFromParent_Done,
     /*  186747 */ // Label 2619: @186747
     /*  186747 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(186813), // Rule ID 28807 //
     /*  186752 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  186755 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186758 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186762 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186769 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186778 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186782 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186789 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186789 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  186792 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186804 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186811 */   GIR_RootConstrainSelectedInstOperands,
     /*  186812 */   // GIR_Coverage, 28807,
     /*  186812 */   GIR_EraseRootFromParent_Done,
     /*  186813 */ // Label 2620: @186813
     /*  186813 */ GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(186879), // Rule ID 28808 //
     /*  186818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  186821 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186824 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186828 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  186835 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186844 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186848 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186855 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186855 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  186858 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186870 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186873 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186877 */   GIR_RootConstrainSelectedInstOperands,
     /*  186878 */   // GIR_Coverage, 28808,
     /*  186878 */   GIR_EraseRootFromParent_Done,
     /*  186879 */ // Label 2621: @186879
     /*  186879 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(186945), // Rule ID 28829 //
     /*  186884 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  186887 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186890 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186894 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  186901 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186910 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186914 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186921 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  186924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  186936 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  186939 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  186943 */   GIR_RootConstrainSelectedInstOperands,
     /*  186944 */   // GIR_Coverage, 28829,
     /*  186944 */   GIR_EraseRootFromParent_Done,
     /*  186945 */ // Label 2622: @186945
     /*  186945 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(187011), // Rule ID 28830 //
     /*  186950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  186953 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  186956 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  186960 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  186967 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  186972 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  186976 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  186980 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  186987 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  186987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  186990 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  186992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  186997 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187002 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187005 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187009 */   GIR_RootConstrainSelectedInstOperands,
     /*  187010 */   // GIR_Coverage, 28830,
     /*  187010 */   GIR_EraseRootFromParent_Done,
     /*  187011 */ // Label 2623: @187011
     /*  187011 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(187077), // Rule ID 28831 //
     /*  187016 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  187019 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187022 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187026 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187033 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187042 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187046 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187053 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  187056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187068 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187071 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187075 */   GIR_RootConstrainSelectedInstOperands,
     /*  187076 */   // GIR_Coverage, 28831,
     /*  187076 */   GIR_EraseRootFromParent_Done,
     /*  187077 */ // Label 2624: @187077
     /*  187077 */ GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(187143), // Rule ID 28832 //
     /*  187082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  187085 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187088 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187092 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187099 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187108 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187112 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187119 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187119 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  187122 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187137 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187141 */   GIR_RootConstrainSelectedInstOperands,
     /*  187142 */   // GIR_Coverage, 28832,
     /*  187142 */   GIR_EraseRootFromParent_Done,
     /*  187143 */ // Label 2625: @187143
     /*  187143 */ GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(187209), // Rule ID 28833 //
     /*  187148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  187151 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187154 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187158 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187165 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187170 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187174 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187178 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187185 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187185 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  187188 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187203 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187207 */   GIR_RootConstrainSelectedInstOperands,
     /*  187208 */   // GIR_Coverage, 28833,
     /*  187208 */   GIR_EraseRootFromParent_Done,
     /*  187209 */ // Label 2626: @187209
     /*  187209 */ GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(187275), // Rule ID 28834 //
     /*  187214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  187217 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187220 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187224 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187231 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187236 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187240 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187244 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187251 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187251 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  187254 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187266 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187269 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187273 */   GIR_RootConstrainSelectedInstOperands,
     /*  187274 */   // GIR_Coverage, 28834,
     /*  187274 */   GIR_EraseRootFromParent_Done,
     /*  187275 */ // Label 2627: @187275
     /*  187275 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(187341), // Rule ID 28835 //
     /*  187280 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  187283 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187286 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187290 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187297 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187306 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187310 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187317 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  187320 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187332 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187335 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187339 */   GIR_RootConstrainSelectedInstOperands,
     /*  187340 */   // GIR_Coverage, 28835,
     /*  187340 */   GIR_EraseRootFromParent_Done,
     /*  187341 */ // Label 2628: @187341
     /*  187341 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(187407), // Rule ID 28836 //
     /*  187346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  187349 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187352 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187356 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187368 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187372 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187376 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187383 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187383 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  187386 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187398 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187401 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187405 */   GIR_RootConstrainSelectedInstOperands,
     /*  187406 */   // GIR_Coverage, 28836,
     /*  187406 */   GIR_EraseRootFromParent_Done,
     /*  187407 */ // Label 2629: @187407
     /*  187407 */ GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(187473), // Rule ID 28837 //
     /*  187412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  187415 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187418 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187422 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187429 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187434 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187438 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187442 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187449 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187449 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  187452 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187464 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187471 */   GIR_RootConstrainSelectedInstOperands,
     /*  187472 */   // GIR_Coverage, 28837,
     /*  187472 */   GIR_EraseRootFromParent_Done,
     /*  187473 */ // Label 2630: @187473
     /*  187473 */ GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(187539), // Rule ID 28838 //
     /*  187478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  187481 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  187484 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187488 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  187495 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187515 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  187518 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187537 */   GIR_RootConstrainSelectedInstOperands,
     /*  187538 */   // GIR_Coverage, 28838,
     /*  187538 */   GIR_EraseRootFromParent_Done,
     /*  187539 */ // Label 2631: @187539
     /*  187539 */ GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(187605), // Rule ID 28993 //
     /*  187544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  187547 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187550 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187570 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187581 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  187584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187603 */   GIR_RootConstrainSelectedInstOperands,
     /*  187604 */   // GIR_Coverage, 28993,
     /*  187604 */   GIR_EraseRootFromParent_Done,
     /*  187605 */ // Label 2632: @187605
     /*  187605 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(187671), // Rule ID 28994 //
     /*  187610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  187613 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187616 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187627 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187636 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187640 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187647 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187647 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  187650 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187662 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187665 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187669 */   GIR_RootConstrainSelectedInstOperands,
     /*  187670 */   // GIR_Coverage, 28994,
     /*  187670 */   GIR_EraseRootFromParent_Done,
     /*  187671 */ // Label 2633: @187671
     /*  187671 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(187737), // Rule ID 28995 //
     /*  187676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  187679 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187682 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187713 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  187716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187728 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187731 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187735 */   GIR_RootConstrainSelectedInstOperands,
     /*  187736 */   // GIR_Coverage, 28995,
     /*  187736 */   GIR_EraseRootFromParent_Done,
     /*  187737 */ // Label 2634: @187737
     /*  187737 */ GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(187803), // Rule ID 28996 //
     /*  187742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  187745 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187748 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187752 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187759 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187768 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187772 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187779 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  187782 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187794 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187797 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187801 */   GIR_RootConstrainSelectedInstOperands,
     /*  187802 */   // GIR_Coverage, 28996,
     /*  187802 */   GIR_EraseRootFromParent_Done,
     /*  187803 */ // Label 2635: @187803
     /*  187803 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(187869), // Rule ID 28997 //
     /*  187808 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  187811 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187814 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187818 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187825 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187845 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_8_glue>><<P:Predicate_atomic_load_aext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  187848 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187867 */   GIR_RootConstrainSelectedInstOperands,
     /*  187868 */   // GIR_Coverage, 28997,
     /*  187868 */   GIR_EraseRootFromParent_Done,
     /*  187869 */ // Label 2636: @187869
     /*  187869 */ GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(187935), // Rule ID 28998 //
     /*  187874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  187877 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187880 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187884 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187891 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187904 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187911 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  187914 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187926 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187929 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187933 */   GIR_RootConstrainSelectedInstOperands,
     /*  187934 */   // GIR_Coverage, 28998,
     /*  187934 */   GIR_EraseRootFromParent_Done,
     /*  187935 */ // Label 2637: @187935
     /*  187935 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(188001), // Rule ID 28999 //
     /*  187940 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  187943 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  187946 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  187950 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  187957 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  187962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  187966 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  187970 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  187977 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  187977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  187980 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  187982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  187987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  187992 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  187995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  187999 */   GIR_RootConstrainSelectedInstOperands,
     /*  188000 */   // GIR_Coverage, 28999,
     /*  188000 */   GIR_EraseRootFromParent_Done,
     /*  188001 */ // Label 2638: @188001
     /*  188001 */ GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(188067), // Rule ID 29000 //
     /*  188006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  188009 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188012 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  188023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188032 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188043 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  188046 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188065 */   GIR_RootConstrainSelectedInstOperands,
     /*  188066 */   // GIR_Coverage, 29000,
     /*  188066 */   GIR_EraseRootFromParent_Done,
     /*  188067 */ // Label 2639: @188067
     /*  188067 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(188133), // Rule ID 29001 //
     /*  188072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  188075 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188078 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188082 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  188089 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188098 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188102 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188109 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188109 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  188112 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188124 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188127 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188131 */   GIR_RootConstrainSelectedInstOperands,
     /*  188132 */   // GIR_Coverage, 29001,
     /*  188132 */   GIR_EraseRootFromParent_Done,
     /*  188133 */ // Label 2640: @188133
     /*  188133 */ GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(188199), // Rule ID 29002 //
     /*  188138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  188141 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188144 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188148 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  188155 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188160 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188164 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188168 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188175 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  188178 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188190 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188193 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188197 */   GIR_RootConstrainSelectedInstOperands,
     /*  188198 */   // GIR_Coverage, 29002,
     /*  188198 */   GIR_EraseRootFromParent_Done,
     /*  188199 */ // Label 2641: @188199
     /*  188199 */ GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(188265), // Rule ID 29071 //
     /*  188204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  188207 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188210 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188214 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188221 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188241 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_16_glue>><<P:Predicate_atomic_load_aext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  188244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188259 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188263 */   GIR_RootConstrainSelectedInstOperands,
     /*  188264 */   // GIR_Coverage, 29071,
     /*  188264 */   GIR_EraseRootFromParent_Done,
     /*  188265 */ // Label 2642: @188265
     /*  188265 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(188331), // Rule ID 29072 //
     /*  188270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  188273 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188276 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188280 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188287 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188292 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188296 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188300 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188307 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_16_glue>><<P:Predicate_atomic_load_aext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  188310 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188325 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188329 */   GIR_RootConstrainSelectedInstOperands,
     /*  188330 */   // GIR_Coverage, 29072,
     /*  188330 */   GIR_EraseRootFromParent_Done,
     /*  188331 */ // Label 2643: @188331
     /*  188331 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(188397), // Rule ID 29073 //
     /*  188336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  188339 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188342 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188346 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188353 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188362 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188366 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188373 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_16_glue>><<P:Predicate_atomic_load_aext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  188376 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188388 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188391 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188395 */   GIR_RootConstrainSelectedInstOperands,
     /*  188396 */   // GIR_Coverage, 29073,
     /*  188396 */   GIR_EraseRootFromParent_Done,
     /*  188397 */ // Label 2644: @188397
     /*  188397 */ GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(188463), // Rule ID 29074 //
     /*  188402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  188405 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188408 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188412 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188419 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188428 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188432 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188439 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_16_glue>><<P:Predicate_atomic_load_aext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188439 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  188442 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188457 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188461 */   GIR_RootConstrainSelectedInstOperands,
     /*  188462 */   // GIR_Coverage, 29074,
     /*  188462 */   GIR_EraseRootFromParent_Done,
     /*  188463 */ // Label 2645: @188463
     /*  188463 */ GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(188529), // Rule ID 29075 //
     /*  188468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  188471 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188474 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188485 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188490 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188494 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188498 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188505 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext_glue>><<P:Predicate_atomic_load_aext_16_glue>><<P:Predicate_atomic_load_aext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  188508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188520 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188523 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188527 */   GIR_RootConstrainSelectedInstOperands,
     /*  188528 */   // GIR_Coverage, 29075,
     /*  188528 */   GIR_EraseRootFromParent_Done,
     /*  188529 */ // Label 2646: @188529
     /*  188529 */ GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(188595), // Rule ID 29076 //
     /*  188534 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  188537 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188540 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188544 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188560 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188564 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188571 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  188574 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188586 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188589 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188593 */   GIR_RootConstrainSelectedInstOperands,
     /*  188594 */   // GIR_Coverage, 29076,
     /*  188594 */   GIR_EraseRootFromParent_Done,
     /*  188595 */ // Label 2647: @188595
     /*  188595 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(188661), // Rule ID 29077 //
     /*  188600 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  188603 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188606 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188610 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188617 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188622 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188626 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188630 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188637 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  188640 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188652 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188655 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188659 */   GIR_RootConstrainSelectedInstOperands,
     /*  188660 */   // GIR_Coverage, 29077,
     /*  188660 */   GIR_EraseRootFromParent_Done,
     /*  188661 */ // Label 2648: @188661
     /*  188661 */ GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(188727), // Rule ID 29078 //
     /*  188666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  188669 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188672 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188676 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188683 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188692 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188696 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188703 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188703 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  188706 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188718 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188721 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188725 */   GIR_RootConstrainSelectedInstOperands,
     /*  188726 */   // GIR_Coverage, 29078,
     /*  188726 */   GIR_EraseRootFromParent_Done,
     /*  188727 */ // Label 2649: @188727
     /*  188727 */ GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(188793), // Rule ID 29079 //
     /*  188732 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  188735 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188738 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188742 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188758 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188762 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188769 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  188772 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188784 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188787 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188791 */   GIR_RootConstrainSelectedInstOperands,
     /*  188792 */   // GIR_Coverage, 29079,
     /*  188792 */   GIR_EraseRootFromParent_Done,
     /*  188793 */ // Label 2650: @188793
     /*  188793 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(188859), // Rule ID 29080 //
     /*  188798 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  188801 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188804 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188808 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  188815 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188820 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188824 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188828 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188835 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188835 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  188838 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188850 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188853 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188857 */   GIR_RootConstrainSelectedInstOperands,
     /*  188858 */   // GIR_Coverage, 29080,
     /*  188858 */   GIR_EraseRootFromParent_Done,
     /*  188859 */ // Label 2651: @188859
     /*  188859 */ GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(188925), // Rule ID 29101 //
     /*  188864 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  188867 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188870 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188874 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  188881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188890 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188894 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188901 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_32_glue>><<P:Predicate_atomic_load_nonext_32_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  188904 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188919 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188923 */   GIR_RootConstrainSelectedInstOperands,
     /*  188924 */   // GIR_Coverage, 29101,
     /*  188924 */   GIR_EraseRootFromParent_Done,
     /*  188925 */ // Label 2652: @188925
     /*  188925 */ GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(188991), // Rule ID 29102 //
     /*  188930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  188933 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  188936 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  188940 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  188947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  188952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  188956 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  188960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  188967 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_32_glue>><<P:Predicate_atomic_load_nonext_32_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  188967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  188970 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  188972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  188977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  188982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  188985 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  188989 */   GIR_RootConstrainSelectedInstOperands,
     /*  188990 */   // GIR_Coverage, 29102,
     /*  188990 */   GIR_EraseRootFromParent_Done,
     /*  188991 */ // Label 2653: @188991
     /*  188991 */ GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(189057), // Rule ID 29103 //
     /*  188996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  188999 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189002 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189006 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189013 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189022 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189026 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189033 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_32_glue>><<P:Predicate_atomic_load_nonext_32_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189033 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189036 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189048 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189051 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189055 */   GIR_RootConstrainSelectedInstOperands,
     /*  189056 */   // GIR_Coverage, 29103,
     /*  189056 */   GIR_EraseRootFromParent_Done,
     /*  189057 */ // Label 2654: @189057
     /*  189057 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(189123), // Rule ID 29104 //
     /*  189062 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  189065 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189068 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189072 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189079 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189088 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189092 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189099 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_32_glue>><<P:Predicate_atomic_load_nonext_32_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189099 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189102 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189114 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189117 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189121 */   GIR_RootConstrainSelectedInstOperands,
     /*  189122 */   // GIR_Coverage, 29104,
     /*  189122 */   GIR_EraseRootFromParent_Done,
     /*  189123 */ // Label 2655: @189123
     /*  189123 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(189189), // Rule ID 29105 //
     /*  189128 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  189131 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189134 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189138 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189145 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189150 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189158 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189165 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_32_glue>><<P:Predicate_atomic_load_nonext_32_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189165 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189168 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189187 */   GIR_RootConstrainSelectedInstOperands,
     /*  189188 */   // GIR_Coverage, 29105,
     /*  189188 */   GIR_EraseRootFromParent_Done,
     /*  189189 */ // Label 2656: @189189
     /*  189189 */ GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(189255), // Rule ID 29106 //
     /*  189194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  189197 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189200 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189204 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189211 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189216 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189220 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189224 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189231 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189231 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  189234 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189249 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189253 */   GIR_RootConstrainSelectedInstOperands,
     /*  189254 */   // GIR_Coverage, 29106,
     /*  189254 */   GIR_EraseRootFromParent_Done,
     /*  189255 */ // Label 2657: @189255
     /*  189255 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(189321), // Rule ID 29107 //
     /*  189260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  189263 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189266 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189270 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189277 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189286 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189290 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189297 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  189300 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189315 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189319 */   GIR_RootConstrainSelectedInstOperands,
     /*  189320 */   // GIR_Coverage, 29107,
     /*  189320 */   GIR_EraseRootFromParent_Done,
     /*  189321 */ // Label 2658: @189321
     /*  189321 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(189387), // Rule ID 29108 //
     /*  189326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  189329 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189332 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189336 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189343 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189363 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  189366 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189381 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189385 */   GIR_RootConstrainSelectedInstOperands,
     /*  189386 */   // GIR_Coverage, 29108,
     /*  189386 */   GIR_EraseRootFromParent_Done,
     /*  189387 */ // Label 2659: @189387
     /*  189387 */ GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(189453), // Rule ID 29109 //
     /*  189392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  189395 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189398 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189402 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189409 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189418 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189422 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189429 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189429 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  189432 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189444 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189447 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189451 */   GIR_RootConstrainSelectedInstOperands,
     /*  189452 */   // GIR_Coverage, 29109,
     /*  189452 */   GIR_EraseRootFromParent_Done,
     /*  189453 */ // Label 2660: @189453
     /*  189453 */ GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(189519), // Rule ID 29110 //
     /*  189458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  189461 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  189464 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189468 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  189475 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189480 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189484 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189488 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189495 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189495 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  189498 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189505 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189510 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189513 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189517 */   GIR_RootConstrainSelectedInstOperands,
     /*  189518 */   // GIR_Coverage, 29110,
     /*  189518 */   GIR_EraseRootFromParent_Done,
     /*  189519 */ // Label 2661: @189519
     /*  189519 */ GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(189578), // Rule ID 28897 //
     /*  189524 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  189527 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189530 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189534 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189543 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189547 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189554 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189554 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189557 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189576 */   GIR_RootConstrainSelectedInstOperands,
     /*  189577 */   // GIR_Coverage, 28897,
     /*  189577 */   GIR_EraseRootFromParent_Done,
     /*  189578 */ // Label 2662: @189578
     /*  189578 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(189637), // Rule ID 28898 //
     /*  189583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  189586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189589 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189593 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189613 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189616 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189628 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189631 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189635 */   GIR_RootConstrainSelectedInstOperands,
     /*  189636 */   // GIR_Coverage, 28898,
     /*  189636 */   GIR_EraseRootFromParent_Done,
     /*  189637 */ // Label 2663: @189637
     /*  189637 */ GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(189696), // Rule ID 28899 //
     /*  189642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  189645 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189648 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189652 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189661 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189665 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189672 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189672 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189675 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189687 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189690 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189694 */   GIR_RootConstrainSelectedInstOperands,
     /*  189695 */   // GIR_Coverage, 28899,
     /*  189695 */   GIR_EraseRootFromParent_Done,
     /*  189696 */ // Label 2664: @189696
     /*  189696 */ GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(189755), // Rule ID 28900 //
     /*  189701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  189704 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189707 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189711 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189720 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189724 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189731 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189734 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189746 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189749 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189753 */   GIR_RootConstrainSelectedInstOperands,
     /*  189754 */   // GIR_Coverage, 28900,
     /*  189754 */   GIR_EraseRootFromParent_Done,
     /*  189755 */ // Label 2665: @189755
     /*  189755 */ GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(189814), // Rule ID 28901 //
     /*  189760 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  189763 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189766 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189770 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189775 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189779 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189783 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189790 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189793 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189805 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189808 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189812 */   GIR_RootConstrainSelectedInstOperands,
     /*  189813 */   // GIR_Coverage, 28901,
     /*  189813 */   GIR_EraseRootFromParent_Done,
     /*  189814 */ // Label 2666: @189814
     /*  189814 */ GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(189873), // Rule ID 28907 //
     /*  189819 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  189822 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189825 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189842 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189849 */   // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189864 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189867 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189871 */   GIR_RootConstrainSelectedInstOperands,
     /*  189872 */   // GIR_Coverage, 28907,
     /*  189872 */   GIR_EraseRootFromParent_Done,
     /*  189873 */ // Label 2667: @189873
     /*  189873 */ GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(189932), // Rule ID 28908 //
     /*  189878 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  189881 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189884 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189888 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189893 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189897 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189901 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189908 */   // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189908 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189911 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189923 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189926 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189930 */   GIR_RootConstrainSelectedInstOperands,
     /*  189931 */   // GIR_Coverage, 28908,
     /*  189931 */   GIR_EraseRootFromParent_Done,
     /*  189932 */ // Label 2668: @189932
     /*  189932 */ GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(189991), // Rule ID 28909 //
     /*  189937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  189940 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  189943 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  189947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  189952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  189956 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  189960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  189967 */   // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  189967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  189970 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  189972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  189977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  189982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  189985 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  189989 */   GIR_RootConstrainSelectedInstOperands,
     /*  189990 */   // GIR_Coverage, 28909,
     /*  189990 */   GIR_EraseRootFromParent_Done,
     /*  189991 */ // Label 2669: @189991
     /*  189991 */ GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(190050), // Rule ID 28910 //
     /*  189996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  189999 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190002 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190006 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190026 */   // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  190029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190048 */   GIR_RootConstrainSelectedInstOperands,
     /*  190049 */   // GIR_Coverage, 28910,
     /*  190049 */   GIR_EraseRootFromParent_Done,
     /*  190050 */ // Label 2670: @190050
     /*  190050 */ GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(190109), // Rule ID 28911 //
     /*  190055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  190058 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190061 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190085 */   // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  190088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190100 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190107 */   GIR_RootConstrainSelectedInstOperands,
     /*  190108 */   // GIR_Coverage, 28911,
     /*  190108 */   GIR_EraseRootFromParent_Done,
     /*  190109 */ // Label 2671: @190109
     /*  190109 */ GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(190164), // Rule ID 28902 //
     /*  190114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  190117 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190120 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190140 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190143 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190155 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190162 */   GIR_RootConstrainSelectedInstOperands,
     /*  190163 */   // GIR_Coverage, 28902,
     /*  190163 */   GIR_EraseRootFromParent_Done,
     /*  190164 */ // Label 2672: @190164
     /*  190164 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(190219), // Rule ID 28903 //
     /*  190169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  190172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190175 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190184 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190188 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190195 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190205 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190217 */   GIR_RootConstrainSelectedInstOperands,
     /*  190218 */   // GIR_Coverage, 28903,
     /*  190218 */   GIR_EraseRootFromParent_Done,
     /*  190219 */ // Label 2673: @190219
     /*  190219 */ GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(190274), // Rule ID 28904 //
     /*  190224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  190227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190230 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190235 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190239 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190243 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190250 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190250 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190253 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190265 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190268 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190272 */   GIR_RootConstrainSelectedInstOperands,
     /*  190273 */   // GIR_Coverage, 28904,
     /*  190273 */   GIR_EraseRootFromParent_Done,
     /*  190274 */ // Label 2674: @190274
     /*  190274 */ GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(190329), // Rule ID 28905 //
     /*  190279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  190282 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190285 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190305 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190323 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190327 */   GIR_RootConstrainSelectedInstOperands,
     /*  190328 */   // GIR_Coverage, 28905,
     /*  190328 */   GIR_EraseRootFromParent_Done,
     /*  190329 */ // Label 2675: @190329
     /*  190329 */ GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(190384), // Rule ID 28906 //
     /*  190334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  190337 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190340 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190349 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190353 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190360 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190382 */   GIR_RootConstrainSelectedInstOperands,
     /*  190383 */   // GIR_Coverage, 28906,
     /*  190383 */   GIR_EraseRootFromParent_Done,
     /*  190384 */ // Label 2676: @190384
     /*  190384 */ GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(190439), // Rule ID 28912 //
     /*  190389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  190392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190415 */   // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190418 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190430 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190433 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190437 */   GIR_RootConstrainSelectedInstOperands,
     /*  190438 */   // GIR_Coverage, 28912,
     /*  190438 */   GIR_EraseRootFromParent_Done,
     /*  190439 */ // Label 2677: @190439
     /*  190439 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(190494), // Rule ID 28913 //
     /*  190444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  190447 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190455 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190459 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190463 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190470 */   // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190473 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190485 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190488 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190492 */   GIR_RootConstrainSelectedInstOperands,
     /*  190493 */   // GIR_Coverage, 28913,
     /*  190493 */   GIR_EraseRootFromParent_Done,
     /*  190494 */ // Label 2678: @190494
     /*  190494 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(190549), // Rule ID 28914 //
     /*  190499 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  190502 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190505 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190525 */   // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190528 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190547 */   GIR_RootConstrainSelectedInstOperands,
     /*  190548 */   // GIR_Coverage, 28914,
     /*  190548 */   GIR_EraseRootFromParent_Done,
     /*  190549 */ // Label 2679: @190549
     /*  190549 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(190604), // Rule ID 28915 //
     /*  190554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  190557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190560 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190565 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190569 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190580 */   // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190583 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190595 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190602 */   GIR_RootConstrainSelectedInstOperands,
     /*  190603 */   // GIR_Coverage, 28915,
     /*  190603 */   GIR_EraseRootFromParent_Done,
     /*  190604 */ // Label 2680: @190604
     /*  190604 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(190659), // Rule ID 28916 //
     /*  190609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  190612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  190615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  190620 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190624 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190628 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  190635 */   // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  190635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  190638 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  190645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  190650 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  190653 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190657 */   GIR_RootConstrainSelectedInstOperands,
     /*  190658 */   // GIR_Coverage, 28916,
     /*  190658 */   GIR_EraseRootFromParent_Done,
     /*  190659 */ // Label 2681: @190659
     /*  190659 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(190734), // Rule ID 9333 //
     /*  190664 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  190667 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  190670 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190674 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  190681 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  190688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190692 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190696 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  190703 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  190703 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  190706 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  190713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  190718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  190723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  190728 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190732 */   GIR_RootConstrainSelectedInstOperands,
     /*  190733 */   // GIR_Coverage, 9333,
     /*  190733 */   GIR_EraseRootFromParent_Done,
     /*  190734 */ // Label 2682: @190734
     /*  190734 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(190809), // Rule ID 9334 //
     /*  190739 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  190742 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  190745 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190749 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  190756 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  190763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  190778 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  190778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  190781 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  190788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  190793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  190798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  190803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190807 */   GIR_RootConstrainSelectedInstOperands,
     /*  190808 */   // GIR_Coverage, 9334,
     /*  190808 */   GIR_EraseRootFromParent_Done,
     /*  190809 */ // Label 2683: @190809
     /*  190809 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(190884), // Rule ID 9335 //
     /*  190814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  190817 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  190820 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190824 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  190831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  190838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190842 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190846 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  190853 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  190853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  190856 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  190863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  190868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  190873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  190878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190882 */   GIR_RootConstrainSelectedInstOperands,
     /*  190883 */   // GIR_Coverage, 9335,
     /*  190883 */   GIR_EraseRootFromParent_Done,
     /*  190884 */ // Label 2684: @190884
     /*  190884 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(190959), // Rule ID 9336 //
     /*  190889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  190892 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  190895 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190899 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  190906 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  190913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  190928 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  190928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  190931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  190933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  190938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  190943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  190948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  190953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  190957 */   GIR_RootConstrainSelectedInstOperands,
     /*  190958 */   // GIR_Coverage, 9336,
     /*  190958 */   GIR_EraseRootFromParent_Done,
     /*  190959 */ // Label 2685: @190959
     /*  190959 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(191034), // Rule ID 9337 //
     /*  190964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  190967 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  190970 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  190974 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  190981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  190988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  190992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  190996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191003 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  191006 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191028 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191032 */   GIR_RootConstrainSelectedInstOperands,
     /*  191033 */   // GIR_Coverage, 9337,
     /*  191033 */   GIR_EraseRootFromParent_Done,
     /*  191034 */ // Label 2686: @191034
     /*  191034 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(191109), // Rule ID 11747 //
     /*  191039 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  191042 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  191045 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191049 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191056 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191067 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191071 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191078 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191078 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191081 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191107 */   GIR_RootConstrainSelectedInstOperands,
     /*  191108 */   // GIR_Coverage, 11747,
     /*  191108 */   GIR_EraseRootFromParent_Done,
     /*  191109 */ // Label 2687: @191109
     /*  191109 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(191184), // Rule ID 11748 //
     /*  191114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  191117 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  191120 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191124 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191131 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191142 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191146 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191153 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191156 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191178 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191182 */   GIR_RootConstrainSelectedInstOperands,
     /*  191183 */   // GIR_Coverage, 11748,
     /*  191183 */   GIR_EraseRootFromParent_Done,
     /*  191184 */ // Label 2688: @191184
     /*  191184 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(191259), // Rule ID 11749 //
     /*  191189 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  191192 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  191195 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191199 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191206 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191217 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191221 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191228 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191228 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191231 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191253 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191257 */   GIR_RootConstrainSelectedInstOperands,
     /*  191258 */   // GIR_Coverage, 11749,
     /*  191258 */   GIR_EraseRootFromParent_Done,
     /*  191259 */ // Label 2689: @191259
     /*  191259 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(191334), // Rule ID 11750 //
     /*  191264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  191267 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  191270 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191274 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191281 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191288 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191292 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191296 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191303 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191328 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191332 */   GIR_RootConstrainSelectedInstOperands,
     /*  191333 */   // GIR_Coverage, 11750,
     /*  191333 */   GIR_EraseRootFromParent_Done,
     /*  191334 */ // Label 2690: @191334
     /*  191334 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(191409), // Rule ID 11751 //
     /*  191339 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  191342 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  191345 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191349 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191356 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191367 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191378 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191381 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191403 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191407 */   GIR_RootConstrainSelectedInstOperands,
     /*  191408 */   // GIR_Coverage, 11751,
     /*  191408 */   GIR_EraseRootFromParent_Done,
     /*  191409 */ // Label 2691: @191409
     /*  191409 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(191484), // Rule ID 11777 //
     /*  191414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  191417 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191420 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191424 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  191431 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191453 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  191456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191478 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191482 */   GIR_RootConstrainSelectedInstOperands,
     /*  191483 */   // GIR_Coverage, 11777,
     /*  191483 */   GIR_EraseRootFromParent_Done,
     /*  191484 */ // Label 2692: @191484
     /*  191484 */ GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(191559), // Rule ID 11778 //
     /*  191489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  191492 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191495 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191499 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  191506 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191521 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191528 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  191531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191557 */   GIR_RootConstrainSelectedInstOperands,
     /*  191558 */   // GIR_Coverage, 11778,
     /*  191558 */   GIR_EraseRootFromParent_Done,
     /*  191559 */ // Label 2693: @191559
     /*  191559 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(191634), // Rule ID 11779 //
     /*  191564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  191567 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191570 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191574 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  191581 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191592 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191596 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191603 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  191606 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191628 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191632 */   GIR_RootConstrainSelectedInstOperands,
     /*  191633 */   // GIR_Coverage, 11779,
     /*  191633 */   GIR_EraseRootFromParent_Done,
     /*  191634 */ // Label 2694: @191634
     /*  191634 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(191709), // Rule ID 11780 //
     /*  191639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  191642 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191645 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191649 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  191656 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191663 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191667 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191671 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191678 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191678 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  191681 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191703 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191707 */   GIR_RootConstrainSelectedInstOperands,
     /*  191708 */   // GIR_Coverage, 11780,
     /*  191708 */   GIR_EraseRootFromParent_Done,
     /*  191709 */ // Label 2695: @191709
     /*  191709 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(191784), // Rule ID 11781 //
     /*  191714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  191717 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191720 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191724 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  191731 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191738 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191742 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191746 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191753 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  191756 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191778 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191782 */   GIR_RootConstrainSelectedInstOperands,
     /*  191783 */   // GIR_Coverage, 11781,
     /*  191783 */   GIR_EraseRootFromParent_Done,
     /*  191784 */ // Label 2696: @191784
     /*  191784 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(191859), // Rule ID 11807 //
     /*  191789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  191792 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191795 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191799 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191806 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191813 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191817 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191821 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191828 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191831 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191853 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191857 */   GIR_RootConstrainSelectedInstOperands,
     /*  191858 */   // GIR_Coverage, 11807,
     /*  191858 */   GIR_EraseRootFromParent_Done,
     /*  191859 */ // Label 2697: @191859
     /*  191859 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(191934), // Rule ID 11808 //
     /*  191864 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  191867 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191870 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191874 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191892 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191896 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191903 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  191928 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  191932 */   GIR_RootConstrainSelectedInstOperands,
     /*  191933 */   // GIR_Coverage, 11808,
     /*  191933 */   GIR_EraseRootFromParent_Done,
     /*  191934 */ // Label 2698: @191934
     /*  191934 */ GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(192009), // Rule ID 11809 //
     /*  191939 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  191942 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  191945 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  191949 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  191956 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  191963 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  191967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  191971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  191978 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  191978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  191981 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  191983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  191988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  191993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  191998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192007 */   GIR_RootConstrainSelectedInstOperands,
     /*  192008 */   // GIR_Coverage, 11809,
     /*  192008 */   GIR_EraseRootFromParent_Done,
     /*  192009 */ // Label 2699: @192009
     /*  192009 */ GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(192084), // Rule ID 11810 //
     /*  192014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  192017 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192020 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192024 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  192031 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192042 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192046 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192053 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  192056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192078 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192082 */   GIR_RootConstrainSelectedInstOperands,
     /*  192083 */   // GIR_Coverage, 11810,
     /*  192083 */   GIR_EraseRootFromParent_Done,
     /*  192084 */ // Label 2700: @192084
     /*  192084 */ GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(192159), // Rule ID 11811 //
     /*  192089 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  192092 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192095 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192099 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  192106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192128 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  192131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192153 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192157 */   GIR_RootConstrainSelectedInstOperands,
     /*  192158 */   // GIR_Coverage, 11811,
     /*  192158 */   GIR_EraseRootFromParent_Done,
     /*  192159 */ // Label 2701: @192159
     /*  192159 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(192234), // Rule ID 12573 //
     /*  192164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  192167 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  192170 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192174 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  192181 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192192 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192196 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192203 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192228 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192232 */   GIR_RootConstrainSelectedInstOperands,
     /*  192233 */   // GIR_Coverage, 12573,
     /*  192233 */   GIR_EraseRootFromParent_Done,
     /*  192234 */ // Label 2702: @192234
     /*  192234 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(192309), // Rule ID 12574 //
     /*  192239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  192242 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  192245 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192249 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  192256 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192278 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192281 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192307 */   GIR_RootConstrainSelectedInstOperands,
     /*  192308 */   // GIR_Coverage, 12574,
     /*  192308 */   GIR_EraseRootFromParent_Done,
     /*  192309 */ // Label 2703: @192309
     /*  192309 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(192384), // Rule ID 12575 //
     /*  192314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  192317 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  192320 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192324 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  192331 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192353 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192382 */   GIR_RootConstrainSelectedInstOperands,
     /*  192383 */   // GIR_Coverage, 12575,
     /*  192383 */   GIR_EraseRootFromParent_Done,
     /*  192384 */ // Label 2704: @192384
     /*  192384 */ GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(192459), // Rule ID 12576 //
     /*  192389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  192392 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  192395 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192399 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  192406 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192413 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192428 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192431 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192453 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192457 */   GIR_RootConstrainSelectedInstOperands,
     /*  192458 */   // GIR_Coverage, 12576,
     /*  192458 */   GIR_EraseRootFromParent_Done,
     /*  192459 */ // Label 2705: @192459
     /*  192459 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(192534), // Rule ID 12577 //
     /*  192464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  192467 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  192470 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  192474 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  192481 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192492 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192496 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192503 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192506 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192532 */   GIR_RootConstrainSelectedInstOperands,
     /*  192533 */   // GIR_Coverage, 12577,
     /*  192533 */   GIR_EraseRootFromParent_Done,
     /*  192534 */ // Label 2706: @192534
     /*  192534 */ GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(192598), // Rule ID 12113 //
     /*  192539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  192542 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192545 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192556 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192560 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192567 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192572 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192592 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192596 */   GIR_RootConstrainSelectedInstOperands,
     /*  192597 */   // GIR_Coverage, 12113,
     /*  192597 */   GIR_EraseRootFromParent_Done,
     /*  192598 */ // Label 2707: @192598
     /*  192598 */ GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(192662), // Rule ID 12114 //
     /*  192603 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  192606 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192609 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192620 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192624 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192631 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192656 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192660 */   GIR_RootConstrainSelectedInstOperands,
     /*  192661 */   // GIR_Coverage, 12114,
     /*  192661 */   GIR_EraseRootFromParent_Done,
     /*  192662 */ // Label 2708: @192662
     /*  192662 */ GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(192726), // Rule ID 12115 //
     /*  192667 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  192670 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192673 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192695 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192720 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192724 */   GIR_RootConstrainSelectedInstOperands,
     /*  192725 */   // GIR_Coverage, 12115,
     /*  192725 */   GIR_EraseRootFromParent_Done,
     /*  192726 */ // Label 2709: @192726
     /*  192726 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(192790), // Rule ID 12116 //
     /*  192731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  192734 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192737 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192759 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192784 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192788 */   GIR_RootConstrainSelectedInstOperands,
     /*  192789 */   // GIR_Coverage, 12116,
     /*  192789 */   GIR_EraseRootFromParent_Done,
     /*  192790 */ // Label 2710: @192790
     /*  192790 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(192854), // Rule ID 12117 //
     /*  192795 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  192798 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192801 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192808 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192812 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192816 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192823 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192823 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192826 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192848 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192852 */   GIR_RootConstrainSelectedInstOperands,
     /*  192853 */   // GIR_Coverage, 12117,
     /*  192853 */   GIR_EraseRootFromParent_Done,
     /*  192854 */ // Label 2711: @192854
     /*  192854 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(192918), // Rule ID 12123 //
     /*  192859 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  192862 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192865 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192887 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192912 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192916 */   GIR_RootConstrainSelectedInstOperands,
     /*  192917 */   // GIR_Coverage, 12123,
     /*  192917 */   GIR_EraseRootFromParent_Done,
     /*  192918 */ // Label 2712: @192918
     /*  192918 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(192982), // Rule ID 12124 //
     /*  192923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  192926 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  192936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  192940 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  192944 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  192951 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  192951 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  192954 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  192956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  192961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  192966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  192971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  192976 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  192980 */   GIR_RootConstrainSelectedInstOperands,
     /*  192981 */   // GIR_Coverage, 12124,
     /*  192981 */   GIR_EraseRootFromParent_Done,
     /*  192982 */ // Label 2713: @192982
     /*  192982 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(193046), // Rule ID 12125 //
     /*  192987 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  192990 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  192993 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193004 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193008 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  193015 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  193015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  193018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  193025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  193030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  193035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  193040 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193044 */   GIR_RootConstrainSelectedInstOperands,
     /*  193045 */   // GIR_Coverage, 12125,
     /*  193045 */   GIR_EraseRootFromParent_Done,
     /*  193046 */ // Label 2714: @193046
     /*  193046 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(193110), // Rule ID 12126 //
     /*  193051 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  193054 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  193057 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  193079 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  193079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  193082 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  193089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  193094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  193099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  193104 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193108 */   GIR_RootConstrainSelectedInstOperands,
     /*  193109 */   // GIR_Coverage, 12126,
     /*  193109 */   GIR_EraseRootFromParent_Done,
     /*  193110 */ // Label 2715: @193110
     /*  193110 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(193174), // Rule ID 12127 //
     /*  193115 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  193118 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  193121 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193136 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  193143 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  193143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  193146 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  193153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  193158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  193163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  193168 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193172 */   GIR_RootConstrainSelectedInstOperands,
     /*  193173 */   // GIR_Coverage, 12127,
     /*  193173 */   GIR_EraseRootFromParent_Done,
     /*  193174 */ // Label 2716: @193174
     /*  193174 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(193242), // Rule ID 9328 //
     /*  193179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  193182 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193185 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193189 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193196 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193207 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193211 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193218 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193218 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193221 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193236 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193240 */   GIR_RootConstrainSelectedInstOperands,
     /*  193241 */   // GIR_Coverage, 9328,
     /*  193241 */   GIR_EraseRootFromParent_Done,
     /*  193242 */ // Label 2717: @193242
     /*  193242 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(193310), // Rule ID 9329 //
     /*  193247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  193250 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193253 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193257 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193275 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193279 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193286 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193301 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193304 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193308 */   GIR_RootConstrainSelectedInstOperands,
     /*  193309 */   // GIR_Coverage, 9329,
     /*  193309 */   GIR_EraseRootFromParent_Done,
     /*  193310 */ // Label 2718: @193310
     /*  193310 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(193378), // Rule ID 9330 //
     /*  193315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  193318 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193321 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193325 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193332 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193354 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193357 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193376 */   GIR_RootConstrainSelectedInstOperands,
     /*  193377 */   // GIR_Coverage, 9330,
     /*  193377 */   GIR_EraseRootFromParent_Done,
     /*  193378 */ // Label 2719: @193378
     /*  193378 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(193446), // Rule ID 9331 //
     /*  193383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  193386 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193389 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193393 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193400 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193422 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193425 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193444 */   GIR_RootConstrainSelectedInstOperands,
     /*  193445 */   // GIR_Coverage, 9331,
     /*  193445 */   GIR_EraseRootFromParent_Done,
     /*  193446 */ // Label 2720: @193446
     /*  193446 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(193514), // Rule ID 9332 //
     /*  193451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  193454 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193457 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193461 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193468 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193475 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193479 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193483 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193490 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193505 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193508 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193512 */   GIR_RootConstrainSelectedInstOperands,
     /*  193513 */   // GIR_Coverage, 9332,
     /*  193513 */   GIR_EraseRootFromParent_Done,
     /*  193514 */ // Label 2721: @193514
     /*  193514 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(193582), // Rule ID 11742 //
     /*  193519 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  193522 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193525 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193529 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  193536 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193547 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193551 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193558 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193558 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  193561 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193573 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193576 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193580 */   GIR_RootConstrainSelectedInstOperands,
     /*  193581 */   // GIR_Coverage, 11742,
     /*  193581 */   GIR_EraseRootFromParent_Done,
     /*  193582 */ // Label 2722: @193582
     /*  193582 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(193650), // Rule ID 11743 //
     /*  193587 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  193590 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193593 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193597 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  193604 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193611 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193615 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193619 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193626 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  193629 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193641 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193648 */   GIR_RootConstrainSelectedInstOperands,
     /*  193649 */   // GIR_Coverage, 11743,
     /*  193649 */   GIR_EraseRootFromParent_Done,
     /*  193650 */ // Label 2723: @193650
     /*  193650 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(193718), // Rule ID 11744 //
     /*  193655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  193658 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193661 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193665 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  193672 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193679 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193683 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193687 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193694 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  193697 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193709 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193712 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193716 */   GIR_RootConstrainSelectedInstOperands,
     /*  193717 */   // GIR_Coverage, 11744,
     /*  193717 */   GIR_EraseRootFromParent_Done,
     /*  193718 */ // Label 2724: @193718
     /*  193718 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(193786), // Rule ID 11745 //
     /*  193723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  193726 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193729 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193733 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  193740 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193751 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193755 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193762 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193762 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  193765 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193777 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193780 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193784 */   GIR_RootConstrainSelectedInstOperands,
     /*  193785 */   // GIR_Coverage, 11745,
     /*  193785 */   GIR_EraseRootFromParent_Done,
     /*  193786 */ // Label 2725: @193786
     /*  193786 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(193854), // Rule ID 11746 //
     /*  193791 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  193794 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  193797 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193801 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  193808 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193819 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193823 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193830 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193830 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  193833 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193845 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193848 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193852 */   GIR_RootConstrainSelectedInstOperands,
     /*  193853 */   // GIR_Coverage, 11746,
     /*  193853 */   GIR_EraseRootFromParent_Done,
     /*  193854 */ // Label 2726: @193854
     /*  193854 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(193922), // Rule ID 11772 //
     /*  193859 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  193862 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  193865 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193869 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193898 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193913 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193916 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193920 */   GIR_RootConstrainSelectedInstOperands,
     /*  193921 */   // GIR_Coverage, 11772,
     /*  193921 */   GIR_EraseRootFromParent_Done,
     /*  193922 */ // Label 2727: @193922
     /*  193922 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(193990), // Rule ID 11773 //
     /*  193927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  193930 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  193933 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  193937 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  193944 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  193951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  193955 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  193959 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  193966 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  193966 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  193969 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  193971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  193976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  193981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  193984 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  193988 */   GIR_RootConstrainSelectedInstOperands,
     /*  193989 */   // GIR_Coverage, 11773,
     /*  193989 */   GIR_EraseRootFromParent_Done,
     /*  193990 */ // Label 2728: @193990
     /*  193990 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(194058), // Rule ID 11774 //
     /*  193995 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  193998 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194001 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194005 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  194012 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194023 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194027 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194034 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  194037 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194049 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194052 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194056 */   GIR_RootConstrainSelectedInstOperands,
     /*  194057 */   // GIR_Coverage, 11774,
     /*  194057 */   GIR_EraseRootFromParent_Done,
     /*  194058 */ // Label 2729: @194058
     /*  194058 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(194126), // Rule ID 11775 //
     /*  194063 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  194066 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194069 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194073 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  194080 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194091 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194095 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194102 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  194105 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194124 */   GIR_RootConstrainSelectedInstOperands,
     /*  194125 */   // GIR_Coverage, 11775,
     /*  194125 */   GIR_EraseRootFromParent_Done,
     /*  194126 */ // Label 2730: @194126
     /*  194126 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(194194), // Rule ID 11776 //
     /*  194131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  194134 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194137 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194141 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  194148 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194155 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194170 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  194173 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194192 */   GIR_RootConstrainSelectedInstOperands,
     /*  194193 */   // GIR_Coverage, 11776,
     /*  194193 */   GIR_EraseRootFromParent_Done,
     /*  194194 */ // Label 2731: @194194
     /*  194194 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(194262), // Rule ID 11802 //
     /*  194199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  194202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194205 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  194216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194223 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194227 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194231 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194238 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  194241 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194253 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194256 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194260 */   GIR_RootConstrainSelectedInstOperands,
     /*  194261 */   // GIR_Coverage, 11802,
     /*  194261 */   GIR_EraseRootFromParent_Done,
     /*  194262 */ // Label 2732: @194262
     /*  194262 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(194330), // Rule ID 11803 //
     /*  194267 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  194270 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194273 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194277 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  194284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194295 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194306 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  194309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194321 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194324 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194328 */   GIR_RootConstrainSelectedInstOperands,
     /*  194329 */   // GIR_Coverage, 11803,
     /*  194329 */   GIR_EraseRootFromParent_Done,
     /*  194330 */ // Label 2733: @194330
     /*  194330 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(194398), // Rule ID 11804 //
     /*  194335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  194338 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194341 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194345 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  194352 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194367 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194374 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  194377 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194389 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194392 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194396 */   GIR_RootConstrainSelectedInstOperands,
     /*  194397 */   // GIR_Coverage, 11804,
     /*  194397 */   GIR_EraseRootFromParent_Done,
     /*  194398 */ // Label 2734: @194398
     /*  194398 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(194466), // Rule ID 11805 //
     /*  194403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  194406 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194409 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194413 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  194420 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194431 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194435 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194442 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194442 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  194445 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194457 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194460 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194464 */   GIR_RootConstrainSelectedInstOperands,
     /*  194465 */   // GIR_Coverage, 11805,
     /*  194465 */   GIR_EraseRootFromParent_Done,
     /*  194466 */ // Label 2735: @194466
     /*  194466 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(194534), // Rule ID 11806 //
     /*  194471 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  194474 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194477 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194481 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  194488 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194499 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194503 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194510 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  194513 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194532 */   GIR_RootConstrainSelectedInstOperands,
     /*  194533 */   // GIR_Coverage, 11806,
     /*  194533 */   GIR_EraseRootFromParent_Done,
     /*  194534 */ // Label 2736: @194534
     /*  194534 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(194602), // Rule ID 12568 //
     /*  194539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  194542 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  194545 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194549 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  194556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194578 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194596 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194600 */   GIR_RootConstrainSelectedInstOperands,
     /*  194601 */   // GIR_Coverage, 12568,
     /*  194601 */   GIR_EraseRootFromParent_Done,
     /*  194602 */ // Label 2737: @194602
     /*  194602 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(194670), // Rule ID 12569 //
     /*  194607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  194610 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  194613 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194617 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  194624 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194635 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194639 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194646 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194661 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194664 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194668 */   GIR_RootConstrainSelectedInstOperands,
     /*  194669 */   // GIR_Coverage, 12569,
     /*  194669 */   GIR_EraseRootFromParent_Done,
     /*  194670 */ // Label 2738: @194670
     /*  194670 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(194738), // Rule ID 12570 //
     /*  194675 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  194678 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  194681 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194685 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  194692 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194707 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194714 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194717 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194729 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194736 */   GIR_RootConstrainSelectedInstOperands,
     /*  194737 */   // GIR_Coverage, 12570,
     /*  194737 */   GIR_EraseRootFromParent_Done,
     /*  194738 */ // Label 2739: @194738
     /*  194738 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(194806), // Rule ID 12571 //
     /*  194743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  194746 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  194749 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194753 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  194760 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194775 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194782 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194800 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194804 */   GIR_RootConstrainSelectedInstOperands,
     /*  194805 */   // GIR_Coverage, 12571,
     /*  194805 */   GIR_EraseRootFromParent_Done,
     /*  194806 */ // Label 2740: @194806
     /*  194806 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(194874), // Rule ID 12572 //
     /*  194811 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  194814 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  194817 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  194821 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  194828 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194839 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194843 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194850 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194865 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194868 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194872 */   GIR_RootConstrainSelectedInstOperands,
     /*  194873 */   // GIR_Coverage, 12572,
     /*  194873 */   GIR_EraseRootFromParent_Done,
     /*  194874 */ // Label 2741: @194874
     /*  194874 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(194931), // Rule ID 12108 //
     /*  194879 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  194882 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194885 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194907 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194910 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194929 */   GIR_RootConstrainSelectedInstOperands,
     /*  194930 */   // GIR_Coverage, 12108,
     /*  194930 */   GIR_EraseRootFromParent_Done,
     /*  194931 */ // Label 2742: @194931
     /*  194931 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(194988), // Rule ID 12109 //
     /*  194936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  194939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  194949 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  194953 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  194957 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  194964 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  194964 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  194967 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  194969 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  194974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  194979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  194982 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  194986 */   GIR_RootConstrainSelectedInstOperands,
     /*  194987 */   // GIR_Coverage, 12109,
     /*  194987 */   GIR_EraseRootFromParent_Done,
     /*  194988 */ // Label 2743: @194988
     /*  194988 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(195045), // Rule ID 12110 //
     /*  194993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  194996 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  194999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195021 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195036 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195039 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195043 */   GIR_RootConstrainSelectedInstOperands,
     /*  195044 */   // GIR_Coverage, 12110,
     /*  195044 */   GIR_EraseRootFromParent_Done,
     /*  195045 */ // Label 2744: @195045
     /*  195045 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(195102), // Rule ID 12111 //
     /*  195050 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  195053 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195056 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195067 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195071 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195078 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195078 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195081 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195093 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195096 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195100 */   GIR_RootConstrainSelectedInstOperands,
     /*  195101 */   // GIR_Coverage, 12111,
     /*  195101 */   GIR_EraseRootFromParent_Done,
     /*  195102 */ // Label 2745: @195102
     /*  195102 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(195159), // Rule ID 12112 //
     /*  195107 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  195110 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195113 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195135 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195138 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195150 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195153 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195157 */   GIR_RootConstrainSelectedInstOperands,
     /*  195158 */   // GIR_Coverage, 12112,
     /*  195158 */   GIR_EraseRootFromParent_Done,
     /*  195159 */ // Label 2746: @195159
     /*  195159 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(195216), // Rule ID 12118 //
     /*  195164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  195167 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195192 */   // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195195 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195210 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195214 */   GIR_RootConstrainSelectedInstOperands,
     /*  195215 */   // GIR_Coverage, 12118,
     /*  195215 */   GIR_EraseRootFromParent_Done,
     /*  195216 */ // Label 2747: @195216
     /*  195216 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(195273), // Rule ID 12119 //
     /*  195221 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  195224 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195227 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195234 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195238 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195249 */   // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195252 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195271 */   GIR_RootConstrainSelectedInstOperands,
     /*  195272 */   // GIR_Coverage, 12119,
     /*  195272 */   GIR_EraseRootFromParent_Done,
     /*  195273 */ // Label 2748: @195273
     /*  195273 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(195330), // Rule ID 12120 //
     /*  195278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  195281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195295 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195306 */   // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195321 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195324 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195328 */   GIR_RootConstrainSelectedInstOperands,
     /*  195329 */   // GIR_Coverage, 12120,
     /*  195329 */   GIR_EraseRootFromParent_Done,
     /*  195330 */ // Label 2749: @195330
     /*  195330 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(195387), // Rule ID 12121 //
     /*  195335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  195338 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195341 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195363 */   // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195366 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195381 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195385 */   GIR_RootConstrainSelectedInstOperands,
     /*  195386 */   // GIR_Coverage, 12121,
     /*  195386 */   GIR_EraseRootFromParent_Done,
     /*  195387 */ // Label 2750: @195387
     /*  195387 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(195444), // Rule ID 12122 //
     /*  195392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  195395 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  195398 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195405 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195409 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195413 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  195420 */   // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  195420 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  195423 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  195430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  195435 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  195438 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195442 */   GIR_RootConstrainSelectedInstOperands,
     /*  195443 */   // GIR_Coverage, 12122,
     /*  195443 */   GIR_EraseRootFromParent_Done,
     /*  195444 */ // Label 2751: @195444
     /*  195444 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(195520), // Rule ID 9479 //
     /*  195449 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  195452 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195455 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195459 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  195466 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195489 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  195492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195514 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195518 */   GIR_RootConstrainSelectedInstOperands,
     /*  195519 */   // GIR_Coverage, 9479,
     /*  195519 */   GIR_EraseRootFromParent_Done,
     /*  195520 */ // Label 2752: @195520
     /*  195520 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(195596), // Rule ID 9480 //
     /*  195525 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  195528 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195531 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195535 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  195542 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195550 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195554 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195558 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195565 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  195568 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195594 */   GIR_RootConstrainSelectedInstOperands,
     /*  195595 */   // GIR_Coverage, 9480,
     /*  195595 */   GIR_EraseRootFromParent_Done,
     /*  195596 */ // Label 2753: @195596
     /*  195596 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(195672), // Rule ID 9481 //
     /*  195601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  195604 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195607 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195611 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  195618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195626 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195630 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195641 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  195644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195666 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195670 */   GIR_RootConstrainSelectedInstOperands,
     /*  195671 */   // GIR_Coverage, 9481,
     /*  195671 */   GIR_EraseRootFromParent_Done,
     /*  195672 */ // Label 2754: @195672
     /*  195672 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(195748), // Rule ID 9482 //
     /*  195677 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  195680 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195683 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195687 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  195694 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195702 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195706 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195710 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195717 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195717 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  195720 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195742 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195746 */   GIR_RootConstrainSelectedInstOperands,
     /*  195747 */   // GIR_Coverage, 9482,
     /*  195747 */   GIR_EraseRootFromParent_Done,
     /*  195748 */ // Label 2755: @195748
     /*  195748 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(195824), // Rule ID 9483 //
     /*  195753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  195756 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195759 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195763 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  195770 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195782 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195786 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195793 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195793 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  195796 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195818 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195822 */   GIR_RootConstrainSelectedInstOperands,
     /*  195823 */   // GIR_Coverage, 9483,
     /*  195823 */   GIR_EraseRootFromParent_Done,
     /*  195824 */ // Label 2756: @195824
     /*  195824 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(195900), // Rule ID 9541 //
     /*  195829 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  195832 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195835 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195839 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  195846 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195854 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195869 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  195872 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195894 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195898 */   GIR_RootConstrainSelectedInstOperands,
     /*  195899 */   // GIR_Coverage, 9541,
     /*  195899 */   GIR_EraseRootFromParent_Done,
     /*  195900 */ // Label 2757: @195900
     /*  195900 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(195976), // Rule ID 9542 //
     /*  195905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  195908 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195911 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195915 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  195922 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  195930 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  195934 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  195938 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  195945 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  195945 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  195948 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  195950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  195955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  195960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  195965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  195970 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  195974 */   GIR_RootConstrainSelectedInstOperands,
     /*  195975 */   // GIR_Coverage, 9542,
     /*  195975 */   GIR_EraseRootFromParent_Done,
     /*  195976 */ // Label 2758: @195976
     /*  195976 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(196052), // Rule ID 9543 //
     /*  195981 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  195984 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  195987 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  195991 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  195998 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196021 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196050 */   GIR_RootConstrainSelectedInstOperands,
     /*  196051 */   // GIR_Coverage, 9543,
     /*  196051 */   GIR_EraseRootFromParent_Done,
     /*  196052 */ // Label 2759: @196052
     /*  196052 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(196128), // Rule ID 9544 //
     /*  196057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  196060 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  196063 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196067 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196074 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196086 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196090 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196097 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196097 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196100 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196122 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196126 */   GIR_RootConstrainSelectedInstOperands,
     /*  196127 */   // GIR_Coverage, 9544,
     /*  196127 */   GIR_EraseRootFromParent_Done,
     /*  196128 */ // Label 2760: @196128
     /*  196128 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(196204), // Rule ID 9545 //
     /*  196133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  196136 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  196139 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196143 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196150 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196158 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196166 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196173 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196176 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196198 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196202 */   GIR_RootConstrainSelectedInstOperands,
     /*  196203 */   // GIR_Coverage, 9545,
     /*  196203 */   GIR_EraseRootFromParent_Done,
     /*  196204 */ // Label 2761: @196204
     /*  196204 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(196280), // Rule ID 9571 //
     /*  196209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  196212 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196215 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196219 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  196226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196234 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196238 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196249 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  196252 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196278 */   GIR_RootConstrainSelectedInstOperands,
     /*  196279 */   // GIR_Coverage, 9571,
     /*  196279 */   GIR_EraseRootFromParent_Done,
     /*  196280 */ // Label 2762: @196280
     /*  196280 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(196356), // Rule ID 9572 //
     /*  196285 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  196288 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196291 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196295 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  196302 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196314 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196318 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196325 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196325 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  196328 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196350 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196354 */   GIR_RootConstrainSelectedInstOperands,
     /*  196355 */   // GIR_Coverage, 9572,
     /*  196355 */   GIR_EraseRootFromParent_Done,
     /*  196356 */ // Label 2763: @196356
     /*  196356 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(196432), // Rule ID 9573 //
     /*  196361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  196364 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196367 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196371 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  196378 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196390 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196394 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196401 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196401 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  196404 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196426 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196430 */   GIR_RootConstrainSelectedInstOperands,
     /*  196431 */   // GIR_Coverage, 9573,
     /*  196431 */   GIR_EraseRootFromParent_Done,
     /*  196432 */ // Label 2764: @196432
     /*  196432 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(196508), // Rule ID 9574 //
     /*  196437 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  196440 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196443 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196447 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  196454 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196466 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196470 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196477 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196477 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  196480 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196497 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196506 */   GIR_RootConstrainSelectedInstOperands,
     /*  196507 */   // GIR_Coverage, 9574,
     /*  196507 */   GIR_EraseRootFromParent_Done,
     /*  196508 */ // Label 2765: @196508
     /*  196508 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(196584), // Rule ID 9575 //
     /*  196513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  196516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196519 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196523 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  196530 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196538 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196542 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196546 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196553 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  196556 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196578 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196582 */   GIR_RootConstrainSelectedInstOperands,
     /*  196583 */   // GIR_Coverage, 9575,
     /*  196583 */   GIR_EraseRootFromParent_Done,
     /*  196584 */ // Label 2766: @196584
     /*  196584 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(196660), // Rule ID 9611 //
     /*  196589 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  196592 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196595 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196599 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196606 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196614 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196618 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196622 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196629 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196629 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196632 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196654 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196658 */   GIR_RootConstrainSelectedInstOperands,
     /*  196659 */   // GIR_Coverage, 9611,
     /*  196659 */   GIR_EraseRootFromParent_Done,
     /*  196660 */ // Label 2767: @196660
     /*  196660 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(196736), // Rule ID 9612 //
     /*  196665 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  196668 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196671 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196675 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196705 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196730 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196734 */   GIR_RootConstrainSelectedInstOperands,
     /*  196735 */   // GIR_Coverage, 9612,
     /*  196735 */   GIR_EraseRootFromParent_Done,
     /*  196736 */ // Label 2768: @196736
     /*  196736 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(196812), // Rule ID 9613 //
     /*  196741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  196744 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196747 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196751 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196758 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196781 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196784 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196806 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196810 */   GIR_RootConstrainSelectedInstOperands,
     /*  196811 */   // GIR_Coverage, 9613,
     /*  196811 */   GIR_EraseRootFromParent_Done,
     /*  196812 */ // Label 2769: @196812
     /*  196812 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(196888), // Rule ID 9614 //
     /*  196817 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  196820 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196823 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196827 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196846 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196850 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196857 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196860 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196886 */   GIR_RootConstrainSelectedInstOperands,
     /*  196887 */   // GIR_Coverage, 9614,
     /*  196887 */   GIR_EraseRootFromParent_Done,
     /*  196888 */ // Label 2770: @196888
     /*  196888 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(196964), // Rule ID 9615 //
     /*  196893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  196896 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  196899 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196903 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  196910 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196918 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196922 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  196926 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  196933 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  196933 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  196936 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  196938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  196943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  196948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  196953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  196958 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  196962 */   GIR_RootConstrainSelectedInstOperands,
     /*  196963 */   // GIR_Coverage, 9615,
     /*  196963 */   GIR_EraseRootFromParent_Done,
     /*  196964 */ // Label 2771: @196964
     /*  196964 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(197040), // Rule ID 9901 //
     /*  196969 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  196972 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  196975 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  196979 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  196986 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  196994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  196998 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197002 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197009 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197009 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197012 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197038 */   GIR_RootConstrainSelectedInstOperands,
     /*  197039 */   // GIR_Coverage, 9901,
     /*  197039 */   GIR_EraseRootFromParent_Done,
     /*  197040 */ // Label 2772: @197040
     /*  197040 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(197116), // Rule ID 9902 //
     /*  197045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  197048 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  197051 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  197055 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  197062 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197085 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197110 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197114 */   GIR_RootConstrainSelectedInstOperands,
     /*  197115 */   // GIR_Coverage, 9902,
     /*  197115 */   GIR_EraseRootFromParent_Done,
     /*  197116 */ // Label 2773: @197116
     /*  197116 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(197192), // Rule ID 9903 //
     /*  197121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  197124 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  197127 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  197131 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  197138 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197150 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197154 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197161 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197164 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197186 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197190 */   GIR_RootConstrainSelectedInstOperands,
     /*  197191 */   // GIR_Coverage, 9903,
     /*  197191 */   GIR_EraseRootFromParent_Done,
     /*  197192 */ // Label 2774: @197192
     /*  197192 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(197268), // Rule ID 9904 //
     /*  197197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  197200 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  197203 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  197207 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  197214 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197230 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197237 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197240 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197266 */   GIR_RootConstrainSelectedInstOperands,
     /*  197267 */   // GIR_Coverage, 9904,
     /*  197267 */   GIR_EraseRootFromParent_Done,
     /*  197268 */ // Label 2775: @197268
     /*  197268 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(197344), // Rule ID 9905 //
     /*  197273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  197276 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  197279 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  197283 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  197290 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197313 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197338 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197342 */   GIR_RootConstrainSelectedInstOperands,
     /*  197343 */   // GIR_Coverage, 9905,
     /*  197343 */   GIR_EraseRootFromParent_Done,
     /*  197344 */ // Label 2776: @197344
     /*  197344 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(197409), // Rule ID 9961 //
     /*  197349 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  197352 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197355 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197367 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197378 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197381 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197403 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197407 */   GIR_RootConstrainSelectedInstOperands,
     /*  197408 */   // GIR_Coverage, 9961,
     /*  197408 */   GIR_EraseRootFromParent_Done,
     /*  197409 */ // Label 2777: @197409
     /*  197409 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(197474), // Rule ID 9962 //
     /*  197414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  197417 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197420 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197432 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197436 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197443 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197443 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197446 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197468 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197472 */   GIR_RootConstrainSelectedInstOperands,
     /*  197473 */   // GIR_Coverage, 9962,
     /*  197473 */   GIR_EraseRootFromParent_Done,
     /*  197474 */ // Label 2778: @197474
     /*  197474 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(197539), // Rule ID 9963 //
     /*  197479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  197482 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197485 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197497 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197501 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197508 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197511 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197537 */   GIR_RootConstrainSelectedInstOperands,
     /*  197538 */   // GIR_Coverage, 9963,
     /*  197538 */   GIR_EraseRootFromParent_Done,
     /*  197539 */ // Label 2779: @197539
     /*  197539 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(197604), // Rule ID 9964 //
     /*  197544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  197547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197562 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197566 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197573 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197576 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197602 */   GIR_RootConstrainSelectedInstOperands,
     /*  197603 */   // GIR_Coverage, 9964,
     /*  197603 */   GIR_EraseRootFromParent_Done,
     /*  197604 */ // Label 2780: @197604
     /*  197604 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(197669), // Rule ID 9965 //
     /*  197609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  197612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197627 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197631 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197638 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197638 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197641 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197667 */   GIR_RootConstrainSelectedInstOperands,
     /*  197668 */   // GIR_Coverage, 9965,
     /*  197668 */   GIR_EraseRootFromParent_Done,
     /*  197669 */ // Label 2781: @197669
     /*  197669 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(197734), // Rule ID 9981 //
     /*  197674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  197677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197692 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197696 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197703 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197703 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197706 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197728 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197732 */   GIR_RootConstrainSelectedInstOperands,
     /*  197733 */   // GIR_Coverage, 9981,
     /*  197733 */   GIR_EraseRootFromParent_Done,
     /*  197734 */ // Label 2782: @197734
     /*  197734 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(197799), // Rule ID 9982 //
     /*  197739 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  197742 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197745 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197757 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197761 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197768 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197771 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197797 */   GIR_RootConstrainSelectedInstOperands,
     /*  197798 */   // GIR_Coverage, 9982,
     /*  197798 */   GIR_EraseRootFromParent_Done,
     /*  197799 */ // Label 2783: @197799
     /*  197799 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(197864), // Rule ID 9983 //
     /*  197804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  197807 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197810 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197818 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197826 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197833 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197836 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197858 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197862 */   GIR_RootConstrainSelectedInstOperands,
     /*  197863 */   // GIR_Coverage, 9983,
     /*  197863 */   GIR_EraseRootFromParent_Done,
     /*  197864 */ // Label 2784: @197864
     /*  197864 */ GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(197929), // Rule ID 9984 //
     /*  197869 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  197872 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197875 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197898 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197923 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197927 */   GIR_RootConstrainSelectedInstOperands,
     /*  197928 */   // GIR_Coverage, 9984,
     /*  197928 */   GIR_EraseRootFromParent_Done,
     /*  197929 */ // Label 2785: @197929
     /*  197929 */ GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(197994), // Rule ID 9985 //
     /*  197934 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  197937 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  197940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  197948 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  197952 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  197956 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  197963 */   // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  197963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  197966 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  197968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  197973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  197978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  197983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  197988 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  197992 */   GIR_RootConstrainSelectedInstOperands,
     /*  197993 */   // GIR_Coverage, 9985,
     /*  197993 */   GIR_EraseRootFromParent_Done,
     /*  197994 */ // Label 2786: @197994
     /*  197994 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(198063), // Rule ID 9474 //
     /*  197999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  198002 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198005 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198009 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198016 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198032 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198039 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198042 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198054 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198057 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198061 */   GIR_RootConstrainSelectedInstOperands,
     /*  198062 */   // GIR_Coverage, 9474,
     /*  198062 */   GIR_EraseRootFromParent_Done,
     /*  198063 */ // Label 2787: @198063
     /*  198063 */ GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(198132), // Rule ID 9475 //
     /*  198068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  198071 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198074 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198078 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198085 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198108 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198108 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198111 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198123 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198126 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198130 */   GIR_RootConstrainSelectedInstOperands,
     /*  198131 */   // GIR_Coverage, 9475,
     /*  198131 */   GIR_EraseRootFromParent_Done,
     /*  198132 */ // Label 2788: @198132
     /*  198132 */ GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(198201), // Rule ID 9476 //
     /*  198137 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  198140 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198143 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198147 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198154 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198166 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198170 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198177 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198177 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198180 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198192 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198195 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198199 */   GIR_RootConstrainSelectedInstOperands,
     /*  198200 */   // GIR_Coverage, 9476,
     /*  198200 */   GIR_EraseRootFromParent_Done,
     /*  198201 */ // Label 2789: @198201
     /*  198201 */ GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(198270), // Rule ID 9477 //
     /*  198206 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  198209 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198212 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198216 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198223 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198235 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198239 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198246 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198246 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198249 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198264 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198268 */   GIR_RootConstrainSelectedInstOperands,
     /*  198269 */   // GIR_Coverage, 9477,
     /*  198269 */   GIR_EraseRootFromParent_Done,
     /*  198270 */ // Label 2790: @198270
     /*  198270 */ GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(198339), // Rule ID 9478 //
     /*  198275 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  198278 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198281 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198285 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198292 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198304 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198308 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198315 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_atomic_load_aext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198318 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198330 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198333 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198337 */   GIR_RootConstrainSelectedInstOperands,
     /*  198338 */   // GIR_Coverage, 9478,
     /*  198338 */   GIR_EraseRootFromParent_Done,
     /*  198339 */ // Label 2791: @198339
     /*  198339 */ GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(198408), // Rule ID 9536 //
     /*  198344 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  198347 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198350 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198354 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  198361 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198384 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  198387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198406 */   GIR_RootConstrainSelectedInstOperands,
     /*  198407 */   // GIR_Coverage, 9536,
     /*  198407 */   GIR_EraseRootFromParent_Done,
     /*  198408 */ // Label 2792: @198408
     /*  198408 */ GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(198477), // Rule ID 9537 //
     /*  198413 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  198416 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198419 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198423 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  198430 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198453 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  198456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198471 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198475 */   GIR_RootConstrainSelectedInstOperands,
     /*  198476 */   // GIR_Coverage, 9537,
     /*  198476 */   GIR_EraseRootFromParent_Done,
     /*  198477 */ // Label 2793: @198477
     /*  198477 */ GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(198546), // Rule ID 9538 //
     /*  198482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  198485 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198488 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  198499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198511 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198515 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198522 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  198525 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198537 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198540 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198544 */   GIR_RootConstrainSelectedInstOperands,
     /*  198545 */   // GIR_Coverage, 9538,
     /*  198545 */   GIR_EraseRootFromParent_Done,
     /*  198546 */ // Label 2794: @198546
     /*  198546 */ GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(198615), // Rule ID 9539 //
     /*  198551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  198554 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198557 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198561 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  198568 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198591 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  198594 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198613 */   GIR_RootConstrainSelectedInstOperands,
     /*  198614 */   // GIR_Coverage, 9539,
     /*  198614 */   GIR_EraseRootFromParent_Done,
     /*  198615 */ // Label 2795: @198615
     /*  198615 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(198684), // Rule ID 9540 //
     /*  198620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  198623 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  198626 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  198637 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198660 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_atomic_load_aext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  198663 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198678 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198682 */   GIR_RootConstrainSelectedInstOperands,
     /*  198683 */   // GIR_Coverage, 9540,
     /*  198683 */   GIR_EraseRootFromParent_Done,
     /*  198684 */ // Label 2796: @198684
     /*  198684 */ GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(198753), // Rule ID 9566 //
     /*  198689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  198692 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  198695 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198699 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198706 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198718 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198722 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198729 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198732 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198744 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198747 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198751 */   GIR_RootConstrainSelectedInstOperands,
     /*  198752 */   // GIR_Coverage, 9566,
     /*  198752 */   GIR_EraseRootFromParent_Done,
     /*  198753 */ // Label 2797: @198753
     /*  198753 */ GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(198822), // Rule ID 9567 //
     /*  198758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  198761 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  198764 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198768 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198783 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198787 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198791 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198798 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198798 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198801 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198813 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198816 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198820 */   GIR_RootConstrainSelectedInstOperands,
     /*  198821 */   // GIR_Coverage, 9567,
     /*  198821 */   GIR_EraseRootFromParent_Done,
     /*  198822 */ // Label 2798: @198822
     /*  198822 */ GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(198891), // Rule ID 9568 //
     /*  198827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  198830 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  198833 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198837 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198867 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198870 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198889 */   GIR_RootConstrainSelectedInstOperands,
     /*  198890 */   // GIR_Coverage, 9568,
     /*  198890 */   GIR_EraseRootFromParent_Done,
     /*  198891 */ // Label 2799: @198891
     /*  198891 */ GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(198960), // Rule ID 9569 //
     /*  198896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  198899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  198902 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198906 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198913 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198929 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  198936 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  198936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  198939 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  198941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  198946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  198951 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  198954 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  198958 */   GIR_RootConstrainSelectedInstOperands,
     /*  198959 */   // GIR_Coverage, 9569,
     /*  198959 */   GIR_EraseRootFromParent_Done,
     /*  198960 */ // Label 2800: @198960
     /*  198960 */ GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(199029), // Rule ID 9570 //
     /*  198965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  198968 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  198971 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  198975 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  198982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  198990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  198994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  198998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199005 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  199008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199027 */   GIR_RootConstrainSelectedInstOperands,
     /*  199028 */   // GIR_Coverage, 9570,
     /*  199028 */   GIR_EraseRootFromParent_Done,
     /*  199029 */ // Label 2801: @199029
     /*  199029 */ GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(199098), // Rule ID 9606 //
     /*  199034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  199037 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199040 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199044 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  199051 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199059 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199063 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199067 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199074 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199074 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  199077 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199092 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199096 */   GIR_RootConstrainSelectedInstOperands,
     /*  199097 */   // GIR_Coverage, 9606,
     /*  199097 */   GIR_EraseRootFromParent_Done,
     /*  199098 */ // Label 2802: @199098
     /*  199098 */ GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(199167), // Rule ID 9607 //
     /*  199103 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  199106 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199109 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199113 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  199120 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199136 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199143 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  199146 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199158 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199161 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199165 */   GIR_RootConstrainSelectedInstOperands,
     /*  199166 */   // GIR_Coverage, 9607,
     /*  199166 */   GIR_EraseRootFromParent_Done,
     /*  199167 */ // Label 2803: @199167
     /*  199167 */ GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(199236), // Rule ID 9608 //
     /*  199172 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  199175 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199178 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199182 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  199189 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199201 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199205 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199212 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199212 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  199215 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199227 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199230 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199234 */   GIR_RootConstrainSelectedInstOperands,
     /*  199235 */   // GIR_Coverage, 9608,
     /*  199235 */   GIR_EraseRootFromParent_Done,
     /*  199236 */ // Label 2804: @199236
     /*  199236 */ GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(199305), // Rule ID 9609 //
     /*  199241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  199244 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199247 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199251 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  199258 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199274 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199281 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199281 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  199284 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199299 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199303 */   GIR_RootConstrainSelectedInstOperands,
     /*  199304 */   // GIR_Coverage, 9609,
     /*  199304 */   GIR_EraseRootFromParent_Done,
     /*  199305 */ // Label 2805: @199305
     /*  199305 */ GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(199374), // Rule ID 9610 //
     /*  199310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  199313 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199316 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199320 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  199327 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199339 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199343 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199350 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  199353 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199365 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199372 */   GIR_RootConstrainSelectedInstOperands,
     /*  199373 */   // GIR_Coverage, 9610,
     /*  199373 */   GIR_EraseRootFromParent_Done,
     /*  199374 */ // Label 2806: @199374
     /*  199374 */ GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(199443), // Rule ID 9896 //
     /*  199379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  199382 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  199385 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199389 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  199396 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199408 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199419 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199422 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199441 */   GIR_RootConstrainSelectedInstOperands,
     /*  199442 */   // GIR_Coverage, 9896,
     /*  199442 */   GIR_EraseRootFromParent_Done,
     /*  199443 */ // Label 2807: @199443
     /*  199443 */ GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(199512), // Rule ID 9897 //
     /*  199448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  199451 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  199454 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199458 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  199465 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199473 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199477 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199481 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199488 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199488 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199491 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199503 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199506 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199510 */   GIR_RootConstrainSelectedInstOperands,
     /*  199511 */   // GIR_Coverage, 9897,
     /*  199511 */   GIR_EraseRootFromParent_Done,
     /*  199512 */ // Label 2808: @199512
     /*  199512 */ GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(199581), // Rule ID 9898 //
     /*  199517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  199520 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  199523 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199527 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  199534 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199546 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199550 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199557 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199557 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199560 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199572 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199575 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199579 */   GIR_RootConstrainSelectedInstOperands,
     /*  199580 */   // GIR_Coverage, 9898,
     /*  199580 */   GIR_EraseRootFromParent_Done,
     /*  199581 */ // Label 2809: @199581
     /*  199581 */ GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(199650), // Rule ID 9899 //
     /*  199586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  199589 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  199592 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  199603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199611 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199615 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199619 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199626 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199629 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199641 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199648 */   GIR_RootConstrainSelectedInstOperands,
     /*  199649 */   // GIR_Coverage, 9899,
     /*  199649 */   GIR_EraseRootFromParent_Done,
     /*  199650 */ // Label 2810: @199650
     /*  199650 */ GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(199719), // Rule ID 9900 //
     /*  199655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  199658 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  199661 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  199665 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  199672 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199695 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_atomic_load_nonext_32_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199710 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199713 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199717 */   GIR_RootConstrainSelectedInstOperands,
     /*  199718 */   // GIR_Coverage, 9900,
     /*  199718 */   GIR_EraseRootFromParent_Done,
     /*  199719 */ // Label 2811: @199719
     /*  199719 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(199777), // Rule ID 9956 //
     /*  199724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  199727 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199730 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199738 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199742 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199746 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199753 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199756 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199771 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199775 */   GIR_RootConstrainSelectedInstOperands,
     /*  199776 */   // GIR_Coverage, 9956,
     /*  199776 */   GIR_EraseRootFromParent_Done,
     /*  199777 */ // Label 2812: @199777
     /*  199777 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(199835), // Rule ID 9957 //
     /*  199782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  199785 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199804 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199811 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199814 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199826 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199829 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199833 */   GIR_RootConstrainSelectedInstOperands,
     /*  199834 */   // GIR_Coverage, 9957,
     /*  199834 */   GIR_EraseRootFromParent_Done,
     /*  199835 */ // Label 2813: @199835
     /*  199835 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(199893), // Rule ID 9958 //
     /*  199840 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  199843 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199846 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199854 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199869 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199872 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199891 */   GIR_RootConstrainSelectedInstOperands,
     /*  199892 */   // GIR_Coverage, 9958,
     /*  199892 */   GIR_EraseRootFromParent_Done,
     /*  199893 */ // Label 2814: @199893
     /*  199893 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(199951), // Rule ID 9959 //
     /*  199898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  199901 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199916 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199920 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199927 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199927 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199930 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  199942 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  199945 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  199949 */   GIR_RootConstrainSelectedInstOperands,
     /*  199950 */   // GIR_Coverage, 9959,
     /*  199950 */   GIR_EraseRootFromParent_Done,
     /*  199951 */ // Label 2815: @199951
     /*  199951 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(200009), // Rule ID 9960 //
     /*  199956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  199959 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  199962 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  199970 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  199974 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  199978 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  199985 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  199985 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  199988 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  199990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  199995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200000 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200007 */   GIR_RootConstrainSelectedInstOperands,
     /*  200008 */   // GIR_Coverage, 9960,
     /*  200008 */   GIR_EraseRootFromParent_Done,
     /*  200009 */ // Label 2816: @200009
     /*  200009 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(200067), // Rule ID 9976 //
     /*  200014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  200017 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200020 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  200028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  200032 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  200043 */   // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  200043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  200046 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  200048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  200053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200065 */   GIR_RootConstrainSelectedInstOperands,
     /*  200066 */   // GIR_Coverage, 9976,
     /*  200066 */   GIR_EraseRootFromParent_Done,
     /*  200067 */ // Label 2817: @200067
     /*  200067 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(200125), // Rule ID 9977 //
     /*  200072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  200075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  200086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  200090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  200101 */   // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  200101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  200104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  200106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  200111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200123 */   GIR_RootConstrainSelectedInstOperands,
     /*  200124 */   // GIR_Coverage, 9977,
     /*  200124 */   GIR_EraseRootFromParent_Done,
     /*  200125 */ // Label 2818: @200125
     /*  200125 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(200183), // Rule ID 9978 //
     /*  200130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  200133 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  200144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  200148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  200159 */   // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  200159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  200162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  200164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  200169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200181 */   GIR_RootConstrainSelectedInstOperands,
     /*  200182 */   // GIR_Coverage, 9978,
     /*  200182 */   GIR_EraseRootFromParent_Done,
     /*  200183 */ // Label 2819: @200183
     /*  200183 */ GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(200241), // Rule ID 9979 //
     /*  200188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  200191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  200202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  200206 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200210 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  200217 */   // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  200217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  200220 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  200222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  200227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200239 */   GIR_RootConstrainSelectedInstOperands,
     /*  200240 */   // GIR_Coverage, 9979,
     /*  200240 */   GIR_EraseRootFromParent_Done,
     /*  200241 */ // Label 2820: @200241
     /*  200241 */ GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(200299), // Rule ID 9980 //
     /*  200246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  200249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200252 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  200260 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  200264 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200268 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  200275 */   // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  200275 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  200278 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  200280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  200285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200290 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200293 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200297 */   GIR_RootConstrainSelectedInstOperands,
     /*  200298 */   // GIR_Coverage, 9980,
     /*  200298 */   GIR_EraseRootFromParent_Done,
     /*  200299 */ // Label 2821: @200299
     /*  200299 */ GIM_Reject,
     /*  200300 */ // Label 1128: @200300
     /*  200300 */ GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(200369), // Rule ID 8796 //
     /*  200305 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  200308 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200311 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200319 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200323 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200327 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  200331 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200338 */   // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200338 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  200341 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200363 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200367 */   GIR_RootConstrainSelectedInstOperands,
     /*  200368 */   // GIR_Coverage, 8796,
     /*  200368 */   GIR_EraseRootFromParent_Done,
     /*  200369 */ // Label 2822: @200369
     /*  200369 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(200438), // Rule ID 8830 //
     /*  200374 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  200377 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200380 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200384 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200388 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200392 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200396 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  200400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200407 */   // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  200410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200436 */   GIR_RootConstrainSelectedInstOperands,
     /*  200437 */   // GIR_Coverage, 8830,
     /*  200437 */   GIR_EraseRootFromParent_Done,
     /*  200438 */ // Label 2823: @200438
     /*  200438 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(200507), // Rule ID 31095 //
     /*  200443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  200446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200449 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200453 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200457 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200461 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200465 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  200469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200476 */   // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  200479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200501 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200505 */   GIR_RootConstrainSelectedInstOperands,
     /*  200506 */   // GIR_Coverage, 31095,
     /*  200506 */   GIR_EraseRootFromParent_Done,
     /*  200507 */ // Label 2824: @200507
     /*  200507 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(200572), // Rule ID 8801 //
     /*  200512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  200515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200518 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200526 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200530 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200541 */   // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  200544 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200566 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200570 */   GIR_RootConstrainSelectedInstOperands,
     /*  200571 */   // GIR_Coverage, 8801,
     /*  200571 */   GIR_EraseRootFromParent_Done,
     /*  200572 */ // Label 2825: @200572
     /*  200572 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(200637), // Rule ID 8835 //
     /*  200577 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  200580 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200583 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200587 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200591 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200595 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200606 */   // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  200609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200631 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200635 */   GIR_RootConstrainSelectedInstOperands,
     /*  200636 */   // GIR_Coverage, 8835,
     /*  200636 */   GIR_EraseRootFromParent_Done,
     /*  200637 */ // Label 2826: @200637
     /*  200637 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(200702), // Rule ID 31100 //
     /*  200642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  200645 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200648 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200652 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200656 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200660 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200664 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200671 */   // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  200674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200696 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200700 */   GIR_RootConstrainSelectedInstOperands,
     /*  200701 */   // GIR_Coverage, 31100,
     /*  200701 */   GIR_EraseRootFromParent_Done,
     /*  200702 */ // Label 2827: @200702
     /*  200702 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(200767), // Rule ID 8807 //
     /*  200707 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  200710 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200713 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200721 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200725 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200729 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200736 */   // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200736 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  200739 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200765 */   GIR_RootConstrainSelectedInstOperands,
     /*  200766 */   // GIR_Coverage, 8807,
     /*  200766 */   GIR_EraseRootFromParent_Done,
     /*  200767 */ // Label 2828: @200767
     /*  200767 */ GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(200832), // Rule ID 8841 //
     /*  200772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  200775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200778 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200782 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200786 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200790 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200801 */   // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  200804 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200826 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200830 */   GIR_RootConstrainSelectedInstOperands,
     /*  200831 */   // GIR_Coverage, 8841,
     /*  200831 */   GIR_EraseRootFromParent_Done,
     /*  200832 */ // Label 2829: @200832
     /*  200832 */ GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(200897), // Rule ID 31106 //
     /*  200837 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  200840 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200843 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200855 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200859 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  200866 */   // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  200866 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  200869 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  200881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  200886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  200891 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200895 */   GIR_RootConstrainSelectedInstOperands,
     /*  200896 */   // GIR_Coverage, 31106,
     /*  200896 */   GIR_EraseRootFromParent_Done,
     /*  200897 */ // Label 2830: @200897
     /*  200897 */ GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(200959), // Rule ID 8792 //
     /*  200902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  200905 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200908 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200916 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200920 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200924 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  200928 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  200935 */   // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  200935 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  200938 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  200940 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  200945 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  200950 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  200953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  200957 */   GIR_RootConstrainSelectedInstOperands,
     /*  200958 */   // GIR_Coverage, 8792,
     /*  200958 */   GIR_EraseRootFromParent_Done,
     /*  200959 */ // Label 2831: @200959
     /*  200959 */ GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(201021), // Rule ID 8793 //
     /*  200964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  200967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  200970 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  200974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  200978 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  200982 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  200986 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  200990 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  200997 */   // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  200997 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  201000 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201012 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201015 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201019 */   GIR_RootConstrainSelectedInstOperands,
     /*  201020 */   // GIR_Coverage, 8793,
     /*  201020 */   GIR_EraseRootFromParent_Done,
     /*  201021 */ // Label 2832: @201021
     /*  201021 */ GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(201083), // Rule ID 8826 //
     /*  201026 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  201029 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201032 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201036 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201040 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201044 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201048 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  201052 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  201059 */   // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  201062 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201081 */   GIR_RootConstrainSelectedInstOperands,
     /*  201082 */   // GIR_Coverage, 8826,
     /*  201082 */   GIR_EraseRootFromParent_Done,
     /*  201083 */ // Label 2833: @201083
     /*  201083 */ GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(201145), // Rule ID 8827 //
     /*  201088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  201091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201094 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201098 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201102 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201106 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201110 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  201114 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  201121 */   // (ld:{ *:[f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  201124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201139 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201143 */   GIR_RootConstrainSelectedInstOperands,
     /*  201144 */   // GIR_Coverage, 8827,
     /*  201144 */   GIR_EraseRootFromParent_Done,
     /*  201145 */ // Label 2834: @201145
     /*  201145 */ GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(201207), // Rule ID 31091 //
     /*  201150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  201153 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201156 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201160 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201164 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201168 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201172 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  201176 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  201183 */   // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201183 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  201186 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201198 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201201 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201205 */   GIR_RootConstrainSelectedInstOperands,
     /*  201206 */   // GIR_Coverage, 31091,
     /*  201206 */   GIR_EraseRootFromParent_Done,
     /*  201207 */ // Label 2835: @201207
     /*  201207 */ GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(201269), // Rule ID 31092 //
     /*  201212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  201215 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201218 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201230 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201234 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  201238 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  201245 */   // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  201248 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201260 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201263 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201267 */   GIR_RootConstrainSelectedInstOperands,
     /*  201268 */   // GIR_Coverage, 31092,
     /*  201268 */   GIR_EraseRootFromParent_Done,
     /*  201269 */ // Label 2836: @201269
     /*  201269 */ GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(201327), // Rule ID 8798 //
     /*  201274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  201277 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201280 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201288 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201292 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201296 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  201303 */   // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  201306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201318 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201321 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201325 */   GIR_RootConstrainSelectedInstOperands,
     /*  201326 */   // GIR_Coverage, 8798,
     /*  201326 */   GIR_EraseRootFromParent_Done,
     /*  201327 */ // Label 2837: @201327
     /*  201327 */ GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(201385), // Rule ID 8832 //
     /*  201332 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  201335 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201338 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201346 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201350 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201354 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  201361 */   // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  201364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201376 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201383 */   GIR_RootConstrainSelectedInstOperands,
     /*  201384 */   // GIR_Coverage, 8832,
     /*  201384 */   GIR_EraseRootFromParent_Done,
     /*  201385 */ // Label 2838: @201385
     /*  201385 */ GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(201443), // Rule ID 31097 //
     /*  201390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  201393 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201396 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  201404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201408 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  201412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  201419 */   // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  201419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  201422 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  201424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  201429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201441 */   GIR_RootConstrainSelectedInstOperands,
     /*  201442 */   // GIR_Coverage, 31097,
     /*  201442 */   GIR_EraseRootFromParent_Done,
     /*  201443 */ // Label 2839: @201443
     /*  201443 */ GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(201511), // Rule ID 29943 //
     /*  201448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  201451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201454 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201458 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201463 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201472 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201476 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201480 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201487 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201487 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201490 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201497 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201502 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201505 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201509 */   GIR_RootConstrainSelectedInstOperands,
     /*  201510 */   // GIR_Coverage, 29943,
     /*  201510 */   GIR_EraseRootFromParent_Done,
     /*  201511 */ // Label 2840: @201511
     /*  201511 */ GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(201579), // Rule ID 29944 //
     /*  201516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  201519 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201522 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201526 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201531 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201536 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201540 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201544 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201548 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201555 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201558 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201570 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201573 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201577 */   GIR_RootConstrainSelectedInstOperands,
     /*  201578 */   // GIR_Coverage, 29944,
     /*  201578 */   GIR_EraseRootFromParent_Done,
     /*  201579 */ // Label 2841: @201579
     /*  201579 */ GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(201647), // Rule ID 29945 //
     /*  201584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  201587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201590 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201594 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201599 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201608 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201612 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201616 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201623 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201626 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201641 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201645 */   GIR_RootConstrainSelectedInstOperands,
     /*  201646 */   // GIR_Coverage, 29945,
     /*  201646 */   GIR_EraseRootFromParent_Done,
     /*  201647 */ // Label 2842: @201647
     /*  201647 */ GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(201715), // Rule ID 29946 //
     /*  201652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  201655 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201658 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201662 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201667 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201676 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201680 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201684 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201691 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201691 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201694 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201706 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201709 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201713 */   GIR_RootConstrainSelectedInstOperands,
     /*  201714 */   // GIR_Coverage, 29946,
     /*  201714 */   GIR_EraseRootFromParent_Done,
     /*  201715 */ // Label 2843: @201715
     /*  201715 */ GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(201783), // Rule ID 29947 //
     /*  201720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  201723 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201726 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201730 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201748 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201759 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201777 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201781 */   GIR_RootConstrainSelectedInstOperands,
     /*  201782 */   // GIR_Coverage, 29947,
     /*  201782 */   GIR_EraseRootFromParent_Done,
     /*  201783 */ // Label 2844: @201783
     /*  201783 */ GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(201851), // Rule ID 29963 //
     /*  201788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  201791 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201794 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201798 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201808 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201812 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201816 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201820 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201827 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201827 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201830 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201842 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201845 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201849 */   GIR_RootConstrainSelectedInstOperands,
     /*  201850 */   // GIR_Coverage, 29963,
     /*  201850 */   GIR_EraseRootFromParent_Done,
     /*  201851 */ // Label 2845: @201851
     /*  201851 */ GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(201919), // Rule ID 29964 //
     /*  201856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  201859 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201862 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201866 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201884 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201888 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201895 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201895 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201898 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201910 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201913 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201917 */   GIR_RootConstrainSelectedInstOperands,
     /*  201918 */   // GIR_Coverage, 29964,
     /*  201918 */   GIR_EraseRootFromParent_Done,
     /*  201919 */ // Label 2846: @201919
     /*  201919 */ GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(201987), // Rule ID 29965 //
     /*  201924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  201927 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201930 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  201934 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  201944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  201948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  201952 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  201956 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  201963 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  201963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  201966 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  201968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  201973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  201978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  201981 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  201985 */   GIR_RootConstrainSelectedInstOperands,
     /*  201986 */   // GIR_Coverage, 29965,
     /*  201986 */   GIR_EraseRootFromParent_Done,
     /*  201987 */ // Label 2847: @201987
     /*  201987 */ GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(202055), // Rule ID 29966 //
     /*  201992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  201995 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  201998 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202002 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202012 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202020 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  202024 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202031 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202031 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202034 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202046 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202053 */   GIR_RootConstrainSelectedInstOperands,
     /*  202054 */   // GIR_Coverage, 29966,
     /*  202054 */   GIR_EraseRootFromParent_Done,
     /*  202055 */ // Label 2848: @202055
     /*  202055 */ GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(202123), // Rule ID 29967 //
     /*  202060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  202063 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202066 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202070 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202075 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202088 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  202092 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202099 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202099 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202102 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202114 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202117 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202121 */   GIR_RootConstrainSelectedInstOperands,
     /*  202122 */   // GIR_Coverage, 29967,
     /*  202122 */   GIR_EraseRootFromParent_Done,
     /*  202123 */ // Label 2849: @202123
     /*  202123 */ GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(202186), // Rule ID 29603 //
     /*  202128 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  202131 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202134 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202138 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202143 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202151 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202155 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202162 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202162 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202165 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202177 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202180 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202184 */   GIR_RootConstrainSelectedInstOperands,
     /*  202185 */   // GIR_Coverage, 29603,
     /*  202185 */   GIR_EraseRootFromParent_Done,
     /*  202186 */ // Label 2850: @202186
     /*  202186 */ GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(202249), // Rule ID 29604 //
     /*  202191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  202194 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202197 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202201 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202206 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202214 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202218 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202225 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202225 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202228 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202240 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202243 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202247 */   GIR_RootConstrainSelectedInstOperands,
     /*  202248 */   // GIR_Coverage, 29604,
     /*  202248 */   GIR_EraseRootFromParent_Done,
     /*  202249 */ // Label 2851: @202249
     /*  202249 */ GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(202312), // Rule ID 29605 //
     /*  202254 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  202257 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202260 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202269 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202277 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202281 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202288 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202291 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202303 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202306 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202310 */   GIR_RootConstrainSelectedInstOperands,
     /*  202311 */   // GIR_Coverage, 29605,
     /*  202311 */   GIR_EraseRootFromParent_Done,
     /*  202312 */ // Label 2852: @202312
     /*  202312 */ GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(202375), // Rule ID 29606 //
     /*  202317 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  202320 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202323 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202327 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202332 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202336 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202340 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202344 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202351 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202354 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202373 */   GIR_RootConstrainSelectedInstOperands,
     /*  202374 */   // GIR_Coverage, 29606,
     /*  202374 */   GIR_EraseRootFromParent_Done,
     /*  202375 */ // Label 2853: @202375
     /*  202375 */ GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(202438), // Rule ID 29607 //
     /*  202380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  202383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202386 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202395 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202414 */   // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202417 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202436 */   GIR_RootConstrainSelectedInstOperands,
     /*  202437 */   // GIR_Coverage, 29607,
     /*  202437 */   GIR_EraseRootFromParent_Done,
     /*  202438 */ // Label 2854: @202438
     /*  202438 */ GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(202501), // Rule ID 29623 //
     /*  202443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  202446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202449 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202453 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202458 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202466 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202470 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202477 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202477 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202480 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202495 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202499 */   GIR_RootConstrainSelectedInstOperands,
     /*  202500 */   // GIR_Coverage, 29623,
     /*  202500 */   GIR_EraseRootFromParent_Done,
     /*  202501 */ // Label 2855: @202501
     /*  202501 */ GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(202564), // Rule ID 29624 //
     /*  202506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  202509 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202512 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202516 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202521 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202525 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202540 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202543 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202562 */   GIR_RootConstrainSelectedInstOperands,
     /*  202563 */   // GIR_Coverage, 29624,
     /*  202563 */   GIR_EraseRootFromParent_Done,
     /*  202564 */ // Label 2856: @202564
     /*  202564 */ GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(202627), // Rule ID 29625 //
     /*  202569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  202572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202575 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202584 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202592 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202596 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202603 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202606 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202618 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202621 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202625 */   GIR_RootConstrainSelectedInstOperands,
     /*  202626 */   // GIR_Coverage, 29625,
     /*  202626 */   GIR_EraseRootFromParent_Done,
     /*  202627 */ // Label 2857: @202627
     /*  202627 */ GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(202690), // Rule ID 29626 //
     /*  202632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  202635 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202638 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202642 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202647 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202655 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202666 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202688 */   GIR_RootConstrainSelectedInstOperands,
     /*  202689 */   // GIR_Coverage, 29626,
     /*  202689 */   GIR_EraseRootFromParent_Done,
     /*  202690 */ // Label 2858: @202690
     /*  202690 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(202753), // Rule ID 29627 //
     /*  202695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  202698 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202701 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202705 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  202710 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  202714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  202718 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202722 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  202729 */   // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  202729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  202732 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  202734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  202739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202744 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202747 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202751 */   GIR_RootConstrainSelectedInstOperands,
     /*  202752 */   // GIR_Coverage, 29627,
     /*  202752 */   GIR_EraseRootFromParent_Done,
     /*  202753 */ // Label 2859: @202753
     /*  202753 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(202808), // Rule ID 8803 //
     /*  202758 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202761 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  202769 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202773 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  202777 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  202784 */   // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  202784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  202787 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  202789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  202794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202799 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202802 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202806 */   GIR_RootConstrainSelectedInstOperands,
     /*  202807 */   // GIR_Coverage, 8803,
     /*  202807 */   GIR_EraseRootFromParent_Done,
     /*  202808 */ // Label 2860: @202808
     /*  202808 */ GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(202866), // Rule ID 8804 //
     /*  202813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  202816 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202819 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202823 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  202827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202831 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  202835 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  202842 */   // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  202842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  202845 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  202847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  202852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202857 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202860 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202864 */   GIR_RootConstrainSelectedInstOperands,
     /*  202865 */   // GIR_Coverage, 8804,
     /*  202865 */   GIR_EraseRootFromParent_Done,
     /*  202866 */ // Label 2861: @202866
     /*  202866 */ GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(202921), // Rule ID 8837 //
     /*  202871 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202874 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202878 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  202882 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202886 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  202890 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  202897 */   // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  202897 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  202900 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  202902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  202907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202912 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202915 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202919 */   GIR_RootConstrainSelectedInstOperands,
     /*  202920 */   // GIR_Coverage, 8837,
     /*  202920 */   GIR_EraseRootFromParent_Done,
     /*  202921 */ // Label 2862: @202921
     /*  202921 */ GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(202979), // Rule ID 8838 //
     /*  202926 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  202929 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202932 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  202940 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202944 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  202948 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  202955 */   // (ld:{ *:[f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  202955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  202958 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  202960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  202965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  202970 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  202973 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  202977 */   GIR_RootConstrainSelectedInstOperands,
     /*  202978 */   // GIR_Coverage, 8838,
     /*  202978 */   GIR_EraseRootFromParent_Done,
     /*  202979 */ // Label 2863: @202979
     /*  202979 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(203034), // Rule ID 31102 //
     /*  202984 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  202987 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  202991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  202995 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  202999 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  203003 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  203010 */   // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  203010 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  203013 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  203015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  203020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203025 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203028 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203032 */   GIR_RootConstrainSelectedInstOperands,
     /*  203033 */   // GIR_Coverage, 31102,
     /*  203033 */   GIR_EraseRootFromParent_Done,
     /*  203034 */ // Label 2864: @203034
     /*  203034 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(203092), // Rule ID 31103 //
     /*  203039 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  203042 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203045 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  203049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  203053 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203057 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  203061 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  203068 */   // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  203068 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  203071 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  203073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  203078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203086 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203090 */   GIR_RootConstrainSelectedInstOperands,
     /*  203091 */   // GIR_Coverage, 31103,
     /*  203091 */   GIR_EraseRootFromParent_Done,
     /*  203092 */ // Label 2865: @203092
     /*  203092 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(203156), // Rule ID 29948 //
     /*  203097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  203100 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203103 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203121 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203132 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203135 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203147 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203150 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203154 */   GIR_RootConstrainSelectedInstOperands,
     /*  203155 */   // GIR_Coverage, 29948,
     /*  203155 */   GIR_EraseRootFromParent_Done,
     /*  203156 */ // Label 2866: @203156
     /*  203156 */ GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(203220), // Rule ID 29949 //
     /*  203161 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  203164 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203172 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203185 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203189 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203196 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203196 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203199 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203214 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203218 */   GIR_RootConstrainSelectedInstOperands,
     /*  203219 */   // GIR_Coverage, 29949,
     /*  203219 */   GIR_EraseRootFromParent_Done,
     /*  203220 */ // Label 2867: @203220
     /*  203220 */ GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(203284), // Rule ID 29950 //
     /*  203225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  203228 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203231 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203249 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203253 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203260 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203260 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203263 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203278 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203282 */   GIR_RootConstrainSelectedInstOperands,
     /*  203283 */   // GIR_Coverage, 29950,
     /*  203283 */   GIR_EraseRootFromParent_Done,
     /*  203284 */ // Label 2868: @203284
     /*  203284 */ GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(203348), // Rule ID 29951 //
     /*  203289 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  203292 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203300 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203313 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203324 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203327 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203346 */   GIR_RootConstrainSelectedInstOperands,
     /*  203347 */   // GIR_Coverage, 29951,
     /*  203347 */   GIR_EraseRootFromParent_Done,
     /*  203348 */ // Label 2869: @203348
     /*  203348 */ GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(203412), // Rule ID 29952 //
     /*  203353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  203356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203364 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203377 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203388 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203391 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203406 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203410 */   GIR_RootConstrainSelectedInstOperands,
     /*  203411 */   // GIR_Coverage, 29952,
     /*  203411 */   GIR_EraseRootFromParent_Done,
     /*  203412 */ // Label 2870: @203412
     /*  203412 */ GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(203476), // Rule ID 29968 //
     /*  203417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  203420 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203423 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203441 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203452 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203455 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203467 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203470 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203474 */   GIR_RootConstrainSelectedInstOperands,
     /*  203475 */   // GIR_Coverage, 29968,
     /*  203475 */   GIR_EraseRootFromParent_Done,
     /*  203476 */ // Label 2871: @203476
     /*  203476 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(203540), // Rule ID 29969 //
     /*  203481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  203484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203487 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203505 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203509 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203516 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203516 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203519 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203531 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203534 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203538 */   GIR_RootConstrainSelectedInstOperands,
     /*  203539 */   // GIR_Coverage, 29969,
     /*  203539 */   GIR_EraseRootFromParent_Done,
     /*  203540 */ // Label 2872: @203540
     /*  203540 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(203604), // Rule ID 29970 //
     /*  203545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  203548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203569 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203580 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203583 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203595 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203602 */   GIR_RootConstrainSelectedInstOperands,
     /*  203603 */   // GIR_Coverage, 29970,
     /*  203603 */   GIR_EraseRootFromParent_Done,
     /*  203604 */ // Label 2873: @203604
     /*  203604 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(203668), // Rule ID 29971 //
     /*  203609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  203612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203633 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203637 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203644 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203644 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203647 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203662 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203666 */   GIR_RootConstrainSelectedInstOperands,
     /*  203667 */   // GIR_Coverage, 29971,
     /*  203667 */   GIR_EraseRootFromParent_Done,
     /*  203668 */ // Label 2874: @203668
     /*  203668 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(203732), // Rule ID 29972 //
     /*  203673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  203676 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203679 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203697 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  203701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203708 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203730 */   GIR_RootConstrainSelectedInstOperands,
     /*  203731 */   // GIR_Coverage, 29972,
     /*  203731 */   GIR_EraseRootFromParent_Done,
     /*  203732 */ // Label 2875: @203732
     /*  203732 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(203791), // Rule ID 29608 //
     /*  203737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  203740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203748 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  203752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203767 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203770 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203789 */   GIR_RootConstrainSelectedInstOperands,
     /*  203790 */   // GIR_Coverage, 29608,
     /*  203790 */   GIR_EraseRootFromParent_Done,
     /*  203791 */ // Label 2876: @203791
     /*  203791 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(203850), // Rule ID 29609 //
     /*  203796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  203799 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203807 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  203811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203815 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203819 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203826 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203829 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203841 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203844 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203848 */   GIR_RootConstrainSelectedInstOperands,
     /*  203849 */   // GIR_Coverage, 29609,
     /*  203849 */   GIR_EraseRootFromParent_Done,
     /*  203850 */ // Label 2877: @203850
     /*  203850 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(203909), // Rule ID 29610 //
     /*  203855 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  203858 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203861 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203866 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  203870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203885 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203888 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203900 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203907 */   GIR_RootConstrainSelectedInstOperands,
     /*  203908 */   // GIR_Coverage, 29610,
     /*  203908 */   GIR_EraseRootFromParent_Done,
     /*  203909 */ // Label 2878: @203909
     /*  203909 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(203968), // Rule ID 29611 //
     /*  203914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  203917 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203920 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203925 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  203929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  203944 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  203944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  203947 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  203949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  203954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  203959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  203962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  203966 */   GIR_RootConstrainSelectedInstOperands,
     /*  203967 */   // GIR_Coverage, 29611,
     /*  203967 */   GIR_EraseRootFromParent_Done,
     /*  203968 */ // Label 2879: @203968
     /*  203968 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(204027), // Rule ID 29612 //
     /*  203973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  203976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  203979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  203984 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  203988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  203992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  203996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  204003 */   // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  204003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  204006 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  204008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  204013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  204018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204021 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204025 */   GIR_RootConstrainSelectedInstOperands,
     /*  204026 */   // GIR_Coverage, 29612,
     /*  204026 */   GIR_EraseRootFromParent_Done,
     /*  204027 */ // Label 2880: @204027
     /*  204027 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(204086), // Rule ID 29628 //
     /*  204032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  204035 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204038 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  204043 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  204047 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  204051 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  204062 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  204062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  204065 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  204067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  204072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  204077 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204080 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204084 */   GIR_RootConstrainSelectedInstOperands,
     /*  204085 */   // GIR_Coverage, 29628,
     /*  204085 */   GIR_EraseRootFromParent_Done,
     /*  204086 */ // Label 2881: @204086
     /*  204086 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(204145), // Rule ID 29629 //
     /*  204091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  204094 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204097 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  204102 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  204106 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  204110 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204114 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  204121 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  204121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  204124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  204126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  204131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  204136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204139 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204143 */   GIR_RootConstrainSelectedInstOperands,
     /*  204144 */   // GIR_Coverage, 29629,
     /*  204144 */   GIR_EraseRootFromParent_Done,
     /*  204145 */ // Label 2882: @204145
     /*  204145 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(204204), // Rule ID 29630 //
     /*  204150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  204153 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204156 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  204161 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  204165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  204169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  204180 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  204180 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  204183 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  204185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  204190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  204195 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204198 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204202 */   GIR_RootConstrainSelectedInstOperands,
     /*  204203 */   // GIR_Coverage, 29630,
     /*  204203 */   GIR_EraseRootFromParent_Done,
     /*  204204 */ // Label 2883: @204204
     /*  204204 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(204263), // Rule ID 29631 //
     /*  204209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  204212 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204215 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  204220 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  204224 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  204228 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204232 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  204239 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  204239 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  204242 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  204244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  204249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  204254 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204257 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204261 */   GIR_RootConstrainSelectedInstOperands,
     /*  204262 */   // GIR_Coverage, 29631,
     /*  204262 */   GIR_EraseRootFromParent_Done,
     /*  204263 */ // Label 2884: @204263
     /*  204263 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(204322), // Rule ID 29632 //
     /*  204268 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  204271 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204274 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  204279 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  204283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  204287 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  204298 */   // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  204298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  204301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  204303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  204308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  204313 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204320 */   GIR_RootConstrainSelectedInstOperands,
     /*  204321 */   // GIR_Coverage, 29632,
     /*  204321 */   GIR_EraseRootFromParent_Done,
     /*  204322 */ // Label 2885: @204322
     /*  204322 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(204384), // Rule ID 8794 //
     /*  204327 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  204330 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204333 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204341 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204345 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204349 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204353 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204360 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  204360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  204363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204382 */   GIR_RootConstrainSelectedInstOperands,
     /*  204383 */   // GIR_Coverage, 8794,
     /*  204383 */   GIR_EraseRootFromParent_Done,
     /*  204384 */ // Label 2886: @204384
     /*  204384 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(204451), // Rule ID 8795 //
     /*  204389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  204392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204395 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204407 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204411 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204422 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  204422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  204425 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  204445 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204449 */   GIR_RootConstrainSelectedInstOperands,
     /*  204450 */   // GIR_Coverage, 8795,
     /*  204450 */   GIR_EraseRootFromParent_Done,
     /*  204451 */ // Label 2887: @204451
     /*  204451 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(204513), // Rule ID 8828 //
     /*  204456 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  204459 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204462 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204466 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204470 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204474 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204478 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204489 */   // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  204489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  204492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204504 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204507 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204511 */   GIR_RootConstrainSelectedInstOperands,
     /*  204512 */   // GIR_Coverage, 8828,
     /*  204512 */   GIR_EraseRootFromParent_Done,
     /*  204513 */ // Label 2888: @204513
     /*  204513 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(204580), // Rule ID 8829 //
     /*  204518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  204521 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204524 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204536 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204540 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204544 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204551 */   // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  204551 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  204554 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  204574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204578 */   GIR_RootConstrainSelectedInstOperands,
     /*  204579 */   // GIR_Coverage, 8829,
     /*  204579 */   GIR_EraseRootFromParent_Done,
     /*  204580 */ // Label 2889: @204580
     /*  204580 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(204642), // Rule ID 31093 //
     /*  204585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  204588 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204591 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204595 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204599 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204603 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204607 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204611 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204618 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  204618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  204621 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204633 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204636 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204640 */   GIR_RootConstrainSelectedInstOperands,
     /*  204641 */   // GIR_Coverage, 31093,
     /*  204641 */   GIR_EraseRootFromParent_Done,
     /*  204642 */ // Label 2890: @204642
     /*  204642 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(204709), // Rule ID 31094 //
     /*  204647 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  204650 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204653 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204661 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204665 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204669 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204680 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  204680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  204683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204695 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  204703 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204707 */   GIR_RootConstrainSelectedInstOperands,
     /*  204708 */   // GIR_Coverage, 31094,
     /*  204708 */   GIR_EraseRootFromParent_Done,
     /*  204709 */ // Label 2891: @204709
     /*  204709 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(204763), // Rule ID 8797 //
     /*  204714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  204717 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204720 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204728 */   // MIs[0] sbase
     /*  204728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  204732 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  204736 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204740 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204744 */   // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  204744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  204747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204749 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  204751 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204754 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204757 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204761 */   GIR_RootConstrainSelectedInstOperands,
     /*  204762 */   // GIR_Coverage, 8797,
     /*  204762 */   GIR_EraseRootFromParent_Done,
     /*  204763 */ // Label 2892: @204763
     /*  204763 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(204817), // Rule ID 8831 //
     /*  204768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  204771 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204774 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204782 */   // MIs[0] sbase
     /*  204782 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  204786 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  204790 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204794 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204798 */   // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  204798 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  204801 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204803 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  204805 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204808 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204811 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204815 */   GIR_RootConstrainSelectedInstOperands,
     /*  204816 */   // GIR_Coverage, 8831,
     /*  204816 */   GIR_EraseRootFromParent_Done,
     /*  204817 */ // Label 2893: @204817
     /*  204817 */ GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(204871), // Rule ID 31096 //
     /*  204822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  204825 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204828 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204832 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204836 */   // MIs[0] sbase
     /*  204836 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  204840 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  204844 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204848 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  204852 */   // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  204852 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  204855 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204857 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  204859 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204862 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204865 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204869 */   GIR_RootConstrainSelectedInstOperands,
     /*  204870 */   // GIR_Coverage, 31096,
     /*  204870 */   GIR_EraseRootFromParent_Done,
     /*  204871 */ // Label 2894: @204871
     /*  204871 */ GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(204929), // Rule ID 8799 //
     /*  204876 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  204879 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204882 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204890 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204894 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204898 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204905 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  204905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  204908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204920 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204923 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204927 */   GIR_RootConstrainSelectedInstOperands,
     /*  204928 */   // GIR_Coverage, 8799,
     /*  204928 */   GIR_EraseRootFromParent_Done,
     /*  204929 */ // Label 2895: @204929
     /*  204929 */ GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(204992), // Rule ID 8800 //
     /*  204934 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  204937 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  204940 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  204944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  204948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  204952 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  204956 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  204963 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  204963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  204966 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  204968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  204973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  204978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  204981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  204986 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  204990 */   GIR_RootConstrainSelectedInstOperands,
     /*  204991 */   // GIR_Coverage, 8800,
     /*  204991 */   GIR_EraseRootFromParent_Done,
     /*  204992 */ // Label 2896: @204992
     /*  204992 */ GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(205050), // Rule ID 8833 //
     /*  204997 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  205000 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205003 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205011 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205015 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205026 */   // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  205026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  205029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205048 */   GIR_RootConstrainSelectedInstOperands,
     /*  205049 */   // GIR_Coverage, 8833,
     /*  205049 */   GIR_EraseRootFromParent_Done,
     /*  205050 */ // Label 2897: @205050
     /*  205050 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(205113), // Rule ID 8834 //
     /*  205055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  205058 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205061 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205069 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205073 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205077 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205084 */   // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  205084 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  205087 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205099 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  205107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205111 */   GIR_RootConstrainSelectedInstOperands,
     /*  205112 */   // GIR_Coverage, 8834,
     /*  205112 */   GIR_EraseRootFromParent_Done,
     /*  205113 */ // Label 2898: @205113
     /*  205113 */ GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(205171), // Rule ID 31098 //
     /*  205118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  205121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205124 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205136 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205147 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  205147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  205150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205169 */   GIR_RootConstrainSelectedInstOperands,
     /*  205170 */   // GIR_Coverage, 31098,
     /*  205170 */   GIR_EraseRootFromParent_Done,
     /*  205171 */ // Label 2899: @205171
     /*  205171 */ GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(205234), // Rule ID 31099 //
     /*  205176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  205179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205182 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205190 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205194 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205198 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205205 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  205205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  205208 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205220 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  205228 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205232 */   GIR_RootConstrainSelectedInstOperands,
     /*  205233 */   // GIR_Coverage, 31099,
     /*  205233 */   GIR_EraseRootFromParent_Done,
     /*  205234 */ // Label 2900: @205234
     /*  205234 */ GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(205284), // Rule ID 8802 //
     /*  205239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  205242 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205245 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205249 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205253 */   // MIs[0] sbase
     /*  205253 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  205257 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  205261 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205265 */   // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  205265 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  205268 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205270 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  205272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205278 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205282 */   GIR_RootConstrainSelectedInstOperands,
     /*  205283 */   // GIR_Coverage, 8802,
     /*  205283 */   GIR_EraseRootFromParent_Done,
     /*  205284 */ // Label 2901: @205284
     /*  205284 */ GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(205334), // Rule ID 8836 //
     /*  205289 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  205292 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205295 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205303 */   // MIs[0] sbase
     /*  205303 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  205307 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  205311 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205315 */   // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  205315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  205318 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205320 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  205322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205325 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205328 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205332 */   GIR_RootConstrainSelectedInstOperands,
     /*  205333 */   // GIR_Coverage, 8836,
     /*  205333 */   GIR_EraseRootFromParent_Done,
     /*  205334 */ // Label 2902: @205334
     /*  205334 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(205384), // Rule ID 31101 //
     /*  205339 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  205342 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205345 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205353 */   // MIs[0] sbase
     /*  205353 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  205357 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  205361 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205365 */   // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  205365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  205368 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205370 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  205372 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205382 */   GIR_RootConstrainSelectedInstOperands,
     /*  205383 */   // GIR_Coverage, 31101,
     /*  205383 */   GIR_EraseRootFromParent_Done,
     /*  205384 */ // Label 2903: @205384
     /*  205384 */ GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(205442), // Rule ID 8805 //
     /*  205389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  205392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205395 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205407 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205411 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205418 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  205418 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  205421 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205433 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205436 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205440 */   GIR_RootConstrainSelectedInstOperands,
     /*  205441 */   // GIR_Coverage, 8805,
     /*  205441 */   GIR_EraseRootFromParent_Done,
     /*  205442 */ // Label 2904: @205442
     /*  205442 */ GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(205505), // Rule ID 8806 //
     /*  205447 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  205450 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205453 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205465 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205476 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  205476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  205479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  205499 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205503 */   GIR_RootConstrainSelectedInstOperands,
     /*  205504 */   // GIR_Coverage, 8806,
     /*  205504 */   GIR_EraseRootFromParent_Done,
     /*  205505 */ // Label 2905: @205505
     /*  205505 */ GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(205563), // Rule ID 8839 //
     /*  205510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  205513 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205516 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205528 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205532 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205539 */   // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  205539 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  205542 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205554 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205557 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205561 */   GIR_RootConstrainSelectedInstOperands,
     /*  205562 */   // GIR_Coverage, 8839,
     /*  205562 */   GIR_EraseRootFromParent_Done,
     /*  205563 */ // Label 2906: @205563
     /*  205563 */ GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(205626), // Rule ID 8840 //
     /*  205568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  205571 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205574 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205582 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205586 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205597 */   // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  205597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  205600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205615 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  205620 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205624 */   GIR_RootConstrainSelectedInstOperands,
     /*  205625 */   // GIR_Coverage, 8840,
     /*  205625 */   GIR_EraseRootFromParent_Done,
     /*  205626 */ // Label 2907: @205626
     /*  205626 */ GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(205684), // Rule ID 31104 //
     /*  205631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  205634 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205637 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205645 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205649 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205660 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  205660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  205663 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205678 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205682 */   GIR_RootConstrainSelectedInstOperands,
     /*  205683 */   // GIR_Coverage, 31104,
     /*  205683 */   GIR_EraseRootFromParent_Done,
     /*  205684 */ // Label 2908: @205684
     /*  205684 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(205747), // Rule ID 31105 //
     /*  205689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  205692 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205695 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205707 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205711 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  205718 */   // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  205718 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  205721 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  205728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  205733 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  205741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205745 */   GIR_RootConstrainSelectedInstOperands,
     /*  205746 */   // GIR_Coverage, 31105,
     /*  205746 */   GIR_EraseRootFromParent_Done,
     /*  205747 */ // Label 2909: @205747
     /*  205747 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(205794), // Rule ID 8808 //
     /*  205752 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205755 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205763 */   // MIs[0] sbase
     /*  205763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  205767 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  205771 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205775 */   // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  205775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  205778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205780 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  205782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205792 */   GIR_RootConstrainSelectedInstOperands,
     /*  205793 */   // GIR_Coverage, 8808,
     /*  205793 */   GIR_EraseRootFromParent_Done,
     /*  205794 */ // Label 2910: @205794
     /*  205794 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(205841), // Rule ID 8842 //
     /*  205799 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205802 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205810 */   // MIs[0] sbase
     /*  205810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  205814 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  205818 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205822 */   // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  205822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  205825 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205827 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  205829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205839 */   GIR_RootConstrainSelectedInstOperands,
     /*  205840 */   // GIR_Coverage, 8842,
     /*  205840 */   GIR_EraseRootFromParent_Done,
     /*  205841 */ // Label 2911: @205841
     /*  205841 */ GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(205888), // Rule ID 31107 //
     /*  205846 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205849 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  205853 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  205857 */   // MIs[0] sbase
     /*  205857 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  205861 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  205865 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  205869 */   // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  205869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  205872 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  205874 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  205876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  205882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205886 */   GIR_RootConstrainSelectedInstOperands,
     /*  205887 */   // GIR_Coverage, 31107,
     /*  205887 */   GIR_EraseRootFromParent_Done,
     /*  205888 */ // Label 2912: @205888
     /*  205888 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(205950), // Rule ID 14302 //
     /*  205893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  205896 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205899 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  205904 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  205908 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205912 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  205919 */   // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  205919 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  205922 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  205924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  205929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  205934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  205939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  205944 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  205948 */   GIR_RootConstrainSelectedInstOperands,
     /*  205949 */   // GIR_Coverage, 14302,
     /*  205949 */   GIR_EraseRootFromParent_Done,
     /*  205950 */ // Label 2913: @205950
     /*  205950 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(206012), // Rule ID 14303 //
     /*  205955 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  205958 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  205961 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  205966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  205970 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  205974 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  205981 */   // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  205981 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  205984 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  205986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  205991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  205996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206006 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206010 */   GIR_RootConstrainSelectedInstOperands,
     /*  206011 */   // GIR_Coverage, 14303,
     /*  206011 */   GIR_EraseRootFromParent_Done,
     /*  206012 */ // Label 2914: @206012
     /*  206012 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(206074), // Rule ID 14304 //
     /*  206017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  206020 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206032 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206043 */   // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206046 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206068 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206072 */   GIR_RootConstrainSelectedInstOperands,
     /*  206073 */   // GIR_Coverage, 14304,
     /*  206073 */   GIR_EraseRootFromParent_Done,
     /*  206074 */ // Label 2915: @206074
     /*  206074 */ GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(206136), // Rule ID 14305 //
     /*  206079 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  206082 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206085 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206105 */   // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206108 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206130 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206134 */   GIR_RootConstrainSelectedInstOperands,
     /*  206135 */   // GIR_Coverage, 14305,
     /*  206135 */   GIR_EraseRootFromParent_Done,
     /*  206136 */ // Label 2916: @206136
     /*  206136 */ GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(206198), // Rule ID 14306 //
     /*  206141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  206144 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206152 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206167 */   // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206170 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206192 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206196 */   GIR_RootConstrainSelectedInstOperands,
     /*  206197 */   // GIR_Coverage, 14306,
     /*  206197 */   GIR_EraseRootFromParent_Done,
     /*  206198 */ // Label 2917: @206198
     /*  206198 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(206260), // Rule ID 14332 //
     /*  206203 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  206206 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206209 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206214 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206229 */   // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206232 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206254 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206258 */   GIR_RootConstrainSelectedInstOperands,
     /*  206259 */   // GIR_Coverage, 14332,
     /*  206259 */   GIR_EraseRootFromParent_Done,
     /*  206260 */ // Label 2918: @206260
     /*  206260 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(206322), // Rule ID 14333 //
     /*  206265 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  206268 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206271 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206291 */   // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206320 */   GIR_RootConstrainSelectedInstOperands,
     /*  206321 */   // GIR_Coverage, 14333,
     /*  206321 */   GIR_EraseRootFromParent_Done,
     /*  206322 */ // Label 2919: @206322
     /*  206322 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(206384), // Rule ID 14334 //
     /*  206327 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  206330 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206353 */   // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206382 */   GIR_RootConstrainSelectedInstOperands,
     /*  206383 */   // GIR_Coverage, 14334,
     /*  206383 */   GIR_EraseRootFromParent_Done,
     /*  206384 */ // Label 2920: @206384
     /*  206384 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(206446), // Rule ID 14335 //
     /*  206389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  206392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206415 */   // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206418 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206444 */   GIR_RootConstrainSelectedInstOperands,
     /*  206445 */   // GIR_Coverage, 14335,
     /*  206445 */   GIR_EraseRootFromParent_Done,
     /*  206446 */ // Label 2921: @206446
     /*  206446 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(206508), // Rule ID 14336 //
     /*  206451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  206454 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206457 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206466 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206470 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  206477 */   // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  206477 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  206480 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  206487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  206492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  206497 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  206502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206506 */   GIR_RootConstrainSelectedInstOperands,
     /*  206507 */   // GIR_Coverage, 14336,
     /*  206507 */   GIR_EraseRootFromParent_Done,
     /*  206508 */ // Label 2922: @206508
     /*  206508 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(206563), // Rule ID 14297 //
     /*  206513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  206516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206532 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206539 */   // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206539 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206542 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206554 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206557 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206561 */   GIR_RootConstrainSelectedInstOperands,
     /*  206562 */   // GIR_Coverage, 14297,
     /*  206562 */   GIR_EraseRootFromParent_Done,
     /*  206563 */ // Label 2923: @206563
     /*  206563 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(206618), // Rule ID 14298 //
     /*  206568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  206571 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206574 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206583 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206587 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206594 */   // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206597 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206609 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206612 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206616 */   GIR_RootConstrainSelectedInstOperands,
     /*  206617 */   // GIR_Coverage, 14298,
     /*  206617 */   GIR_EraseRootFromParent_Done,
     /*  206618 */ // Label 2924: @206618
     /*  206618 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(206673), // Rule ID 14299 //
     /*  206623 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  206626 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206629 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206638 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206642 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206649 */   // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206649 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206652 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206664 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206667 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206671 */   GIR_RootConstrainSelectedInstOperands,
     /*  206672 */   // GIR_Coverage, 14299,
     /*  206672 */   GIR_EraseRootFromParent_Done,
     /*  206673 */ // Label 2925: @206673
     /*  206673 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(206728), // Rule ID 14300 //
     /*  206678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  206681 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206697 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206704 */   // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206704 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206707 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206722 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206726 */   GIR_RootConstrainSelectedInstOperands,
     /*  206727 */   // GIR_Coverage, 14300,
     /*  206727 */   GIR_EraseRootFromParent_Done,
     /*  206728 */ // Label 2926: @206728
     /*  206728 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(206783), // Rule ID 14301 //
     /*  206733 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  206736 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206739 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206759 */   // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206777 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206781 */   GIR_RootConstrainSelectedInstOperands,
     /*  206782 */   // GIR_Coverage, 14301,
     /*  206782 */   GIR_EraseRootFromParent_Done,
     /*  206783 */ // Label 2927: @206783
     /*  206783 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(206838), // Rule ID 14327 //
     /*  206788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  206791 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206794 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206799 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206803 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206807 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206814 */   // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206814 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206817 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206832 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206836 */   GIR_RootConstrainSelectedInstOperands,
     /*  206837 */   // GIR_Coverage, 14327,
     /*  206837 */   GIR_EraseRootFromParent_Done,
     /*  206838 */ // Label 2928: @206838
     /*  206838 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(206893), // Rule ID 14328 //
     /*  206843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  206846 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206849 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206854 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206869 */   // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206872 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206891 */   GIR_RootConstrainSelectedInstOperands,
     /*  206892 */   // GIR_Coverage, 14328,
     /*  206892 */   GIR_EraseRootFromParent_Done,
     /*  206893 */ // Label 2929: @206893
     /*  206893 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(206948), // Rule ID 14329 //
     /*  206898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  206901 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206924 */   // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206942 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  206946 */   GIR_RootConstrainSelectedInstOperands,
     /*  206947 */   // GIR_Coverage, 14329,
     /*  206947 */   GIR_EraseRootFromParent_Done,
     /*  206948 */ // Label 2930: @206948
     /*  206948 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(207003), // Rule ID 14330 //
     /*  206953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  206956 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  206959 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  206964 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  206968 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  206972 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  206979 */   // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  206979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  206982 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  206984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  206989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  206994 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  206997 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207001 */   GIR_RootConstrainSelectedInstOperands,
     /*  207002 */   // GIR_Coverage, 14330,
     /*  207002 */   GIR_EraseRootFromParent_Done,
     /*  207003 */ // Label 2931: @207003
     /*  207003 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(207058), // Rule ID 14331 //
     /*  207008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  207011 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207014 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207023 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207027 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  207034 */   // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  207034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  207037 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  207044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207049 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207052 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207056 */   GIR_RootConstrainSelectedInstOperands,
     /*  207057 */   // GIR_Coverage, 14331,
     /*  207057 */   GIR_EraseRootFromParent_Done,
     /*  207058 */ // Label 2932: @207058
     /*  207058 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(207113), // Rule ID 14292 //
     /*  207063 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  207066 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207069 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207082 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207089 */   // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207104 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207111 */   GIR_RootConstrainSelectedInstOperands,
     /*  207112 */   // GIR_Coverage, 14292,
     /*  207112 */   GIR_EraseRootFromParent_Done,
     /*  207113 */ // Label 2933: @207113
     /*  207113 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(207168), // Rule ID 14293 //
     /*  207118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  207121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207124 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207133 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207137 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207144 */   // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207162 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207166 */   GIR_RootConstrainSelectedInstOperands,
     /*  207167 */   // GIR_Coverage, 14293,
     /*  207167 */   GIR_EraseRootFromParent_Done,
     /*  207168 */ // Label 2934: @207168
     /*  207168 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(207223), // Rule ID 14294 //
     /*  207173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  207176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207179 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207188 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207192 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207199 */   // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207202 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207221 */   GIR_RootConstrainSelectedInstOperands,
     /*  207222 */   // GIR_Coverage, 14294,
     /*  207222 */   GIR_EraseRootFromParent_Done,
     /*  207223 */ // Label 2935: @207223
     /*  207223 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(207278), // Rule ID 14295 //
     /*  207228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  207231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207254 */   // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207276 */   GIR_RootConstrainSelectedInstOperands,
     /*  207277 */   // GIR_Coverage, 14295,
     /*  207277 */   GIR_EraseRootFromParent_Done,
     /*  207278 */ // Label 2936: @207278
     /*  207278 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(207333), // Rule ID 14296 //
     /*  207283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  207286 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207294 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207298 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207302 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207309 */   // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207324 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207327 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207331 */   GIR_RootConstrainSelectedInstOperands,
     /*  207332 */   // GIR_Coverage, 14296,
     /*  207332 */   GIR_EraseRootFromParent_Done,
     /*  207333 */ // Label 2937: @207333
     /*  207333 */ GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(207388), // Rule ID 14322 //
     /*  207338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  207341 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207344 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207353 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207357 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207364 */   // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207364 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207367 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207379 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207382 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207386 */   GIR_RootConstrainSelectedInstOperands,
     /*  207387 */   // GIR_Coverage, 14322,
     /*  207387 */   GIR_EraseRootFromParent_Done,
     /*  207388 */ // Label 2938: @207388
     /*  207388 */ GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(207443), // Rule ID 14323 //
     /*  207393 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  207396 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207399 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207408 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207419 */   // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207422 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207441 */   GIR_RootConstrainSelectedInstOperands,
     /*  207442 */   // GIR_Coverage, 14323,
     /*  207442 */   GIR_EraseRootFromParent_Done,
     /*  207443 */ // Label 2939: @207443
     /*  207443 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(207498), // Rule ID 14324 //
     /*  207448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  207451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207454 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207463 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207467 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207474 */   // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207474 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207477 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207489 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207492 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207496 */   GIR_RootConstrainSelectedInstOperands,
     /*  207497 */   // GIR_Coverage, 14324,
     /*  207497 */   GIR_EraseRootFromParent_Done,
     /*  207498 */ // Label 2940: @207498
     /*  207498 */ GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(207553), // Rule ID 14325 //
     /*  207503 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  207506 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207522 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207529 */   // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207544 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207547 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207551 */   GIR_RootConstrainSelectedInstOperands,
     /*  207552 */   // GIR_Coverage, 14325,
     /*  207552 */   GIR_EraseRootFromParent_Done,
     /*  207553 */ // Label 2941: @207553
     /*  207553 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(207608), // Rule ID 14326 //
     /*  207558 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  207561 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  207564 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  207569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207577 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  207584 */   // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  207584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  207587 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  207589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  207594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  207599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207606 */   GIR_RootConstrainSelectedInstOperands,
     /*  207607 */   // GIR_Coverage, 14326,
     /*  207607 */   GIR_EraseRootFromParent_Done,
     /*  207608 */ // Label 2942: @207608
     /*  207608 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(207689), // Rule ID 24881 //
     /*  207613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  207616 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  207619 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  207623 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  207630 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  207637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207645 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  207652 */   // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  207652 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  207655 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  207657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  207662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  207667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  207672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  207677 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207680 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207683 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207687 */   GIR_RootConstrainSelectedInstOperands,
     /*  207688 */   // GIR_Coverage, 24881,
     /*  207688 */   GIR_EraseRootFromParent_Done,
     /*  207689 */ // Label 2943: @207689
     /*  207689 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(207770), // Rule ID 24882 //
     /*  207694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  207697 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  207700 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  207704 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  207711 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  207718 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207722 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207726 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  207733 */   // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  207733 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  207736 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  207738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  207743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  207748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  207753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  207758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207761 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207764 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207768 */   GIR_RootConstrainSelectedInstOperands,
     /*  207769 */   // GIR_Coverage, 24882,
     /*  207769 */   GIR_EraseRootFromParent_Done,
     /*  207770 */ // Label 2944: @207770
     /*  207770 */ GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(207851), // Rule ID 24883 //
     /*  207775 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  207778 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  207781 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  207785 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  207792 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  207799 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207803 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207807 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  207814 */   // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  207814 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  207817 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  207819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  207824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  207829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  207834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  207839 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207842 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207845 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207849 */   GIR_RootConstrainSelectedInstOperands,
     /*  207850 */   // GIR_Coverage, 24883,
     /*  207850 */   GIR_EraseRootFromParent_Done,
     /*  207851 */ // Label 2945: @207851
     /*  207851 */ GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(207932), // Rule ID 24884 //
     /*  207856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  207859 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  207862 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  207866 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  207873 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  207880 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207884 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207888 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  207895 */   // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  207895 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  207898 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  207900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  207905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  207910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  207915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  207920 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207923 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  207926 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  207930 */   GIR_RootConstrainSelectedInstOperands,
     /*  207931 */   // GIR_Coverage, 24884,
     /*  207931 */   GIR_EraseRootFromParent_Done,
     /*  207932 */ // Label 2946: @207932
     /*  207932 */ GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(208013), // Rule ID 24885 //
     /*  207937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  207940 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  207943 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  207947 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  207954 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  207961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  207965 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  207969 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  207976 */   // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  207976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  207979 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  207981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  207986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  207991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  207996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208004 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208007 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208011 */   GIR_RootConstrainSelectedInstOperands,
     /*  208012 */   // GIR_Coverage, 24885,
     /*  208012 */   GIR_EraseRootFromParent_Done,
     /*  208013 */ // Label 2947: @208013
     /*  208013 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(208083), // Rule ID 15528 //
     /*  208018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  208021 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208024 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208046 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208081 */   GIR_RootConstrainSelectedInstOperands,
     /*  208082 */   // GIR_Coverage, 15528,
     /*  208082 */   GIR_EraseRootFromParent_Done,
     /*  208083 */ // Label 2948: @208083
     /*  208083 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(208153), // Rule ID 15529 //
     /*  208088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  208091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208116 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208141 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208144 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208147 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208151 */   GIR_RootConstrainSelectedInstOperands,
     /*  208152 */   // GIR_Coverage, 15529,
     /*  208152 */   GIR_EraseRootFromParent_Done,
     /*  208153 */ // Label 2949: @208153
     /*  208153 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(208223), // Rule ID 15530 //
     /*  208158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  208161 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208164 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208175 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208179 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208186 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208186 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208189 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208221 */   GIR_RootConstrainSelectedInstOperands,
     /*  208222 */   // GIR_Coverage, 15530,
     /*  208222 */   GIR_EraseRootFromParent_Done,
     /*  208223 */ // Label 2950: @208223
     /*  208223 */ GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(208293), // Rule ID 15531 //
     /*  208228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  208231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208256 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208287 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208291 */   GIR_RootConstrainSelectedInstOperands,
     /*  208292 */   // GIR_Coverage, 15531,
     /*  208292 */   GIR_EraseRootFromParent_Done,
     /*  208293 */ // Label 2951: @208293
     /*  208293 */ GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(208363), // Rule ID 15532 //
     /*  208298 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  208301 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208304 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208326 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208329 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208351 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208354 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208357 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208361 */   GIR_RootConstrainSelectedInstOperands,
     /*  208362 */   // GIR_Coverage, 15532,
     /*  208362 */   GIR_EraseRootFromParent_Done,
     /*  208363 */ // Label 2952: @208363
     /*  208363 */ GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(208433), // Rule ID 15538 //
     /*  208368 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  208371 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208374 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208396 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  208399 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208421 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208427 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208431 */   GIR_RootConstrainSelectedInstOperands,
     /*  208432 */   // GIR_Coverage, 15538,
     /*  208432 */   GIR_EraseRootFromParent_Done,
     /*  208433 */ // Label 2953: @208433
     /*  208433 */ GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(208503), // Rule ID 15539 //
     /*  208438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  208441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208444 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208466 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  208469 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208501 */   GIR_RootConstrainSelectedInstOperands,
     /*  208502 */   // GIR_Coverage, 15539,
     /*  208502 */   GIR_EraseRootFromParent_Done,
     /*  208503 */ // Label 2954: @208503
     /*  208503 */ GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(208573), // Rule ID 15540 //
     /*  208508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  208511 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208514 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208521 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208525 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208529 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208536 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208536 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  208539 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208541 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208561 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208564 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208571 */   GIR_RootConstrainSelectedInstOperands,
     /*  208572 */   // GIR_Coverage, 15540,
     /*  208572 */   GIR_EraseRootFromParent_Done,
     /*  208573 */ // Label 2955: @208573
     /*  208573 */ GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(208643), // Rule ID 15541 //
     /*  208578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  208581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208606 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  208609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208631 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208634 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208637 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208641 */   GIR_RootConstrainSelectedInstOperands,
     /*  208642 */   // GIR_Coverage, 15541,
     /*  208642 */   GIR_EraseRootFromParent_Done,
     /*  208643 */ // Label 2956: @208643
     /*  208643 */ GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(208713), // Rule ID 15542 //
     /*  208648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  208651 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208654 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208661 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208665 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208669 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208676 */   // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208676 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  208679 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208701 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208704 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208707 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208711 */   GIR_RootConstrainSelectedInstOperands,
     /*  208712 */   // GIR_Coverage, 15542,
     /*  208712 */   GIR_EraseRootFromParent_Done,
     /*  208713 */ // Label 2957: @208713
     /*  208713 */ GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(208783), // Rule ID 15548 //
     /*  208718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  208721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208724 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208731 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208735 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208746 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208746 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208749 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208771 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208777 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208781 */   GIR_RootConstrainSelectedInstOperands,
     /*  208782 */   // GIR_Coverage, 15548,
     /*  208782 */   GIR_EraseRootFromParent_Done,
     /*  208783 */ // Label 2958: @208783
     /*  208783 */ GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(208853), // Rule ID 15549 //
     /*  208788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  208791 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208794 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208801 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208805 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208809 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208816 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208819 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208841 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208844 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208851 */   GIR_RootConstrainSelectedInstOperands,
     /*  208852 */   // GIR_Coverage, 15549,
     /*  208852 */   GIR_EraseRootFromParent_Done,
     /*  208853 */ // Label 2959: @208853
     /*  208853 */ GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(208923), // Rule ID 15550 //
     /*  208858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  208861 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208871 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208875 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208879 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208886 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208889 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208911 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208917 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208921 */   GIR_RootConstrainSelectedInstOperands,
     /*  208922 */   // GIR_Coverage, 15550,
     /*  208922 */   GIR_EraseRootFromParent_Done,
     /*  208923 */ // Label 2960: @208923
     /*  208923 */ GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(208993), // Rule ID 15551 //
     /*  208928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  208931 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  208934 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  208941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  208945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  208949 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  208956 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  208956 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  208959 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  208961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  208966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  208971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  208976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  208981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  208987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  208991 */   GIR_RootConstrainSelectedInstOperands,
     /*  208992 */   // GIR_Coverage, 15551,
     /*  208992 */   GIR_EraseRootFromParent_Done,
     /*  208993 */ // Label 2961: @208993
     /*  208993 */ GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(209063), // Rule ID 15552 //
     /*  208998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  209001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  209011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  209026 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  209026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  209029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  209031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  209036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  209041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  209046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  209051 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209054 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209057 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209061 */   GIR_RootConstrainSelectedInstOperands,
     /*  209062 */   // GIR_Coverage, 15552,
     /*  209062 */   GIR_EraseRootFromParent_Done,
     /*  209063 */ // Label 2962: @209063
     /*  209063 */ GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(209133), // Rule ID 15558 //
     /*  209068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  209071 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209074 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  209081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209085 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209089 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  209096 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  209096 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  209099 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  209101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  209106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  209111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  209116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  209121 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209124 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209127 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209131 */   GIR_RootConstrainSelectedInstOperands,
     /*  209132 */   // GIR_Coverage, 15558,
     /*  209132 */   GIR_EraseRootFromParent_Done,
     /*  209133 */ // Label 2963: @209133
     /*  209133 */ GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(209203), // Rule ID 15559 //
     /*  209138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  209141 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209144 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  209151 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209155 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209159 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  209166 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  209166 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  209169 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  209171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  209176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  209181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  209186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  209191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209194 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209197 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209201 */   GIR_RootConstrainSelectedInstOperands,
     /*  209202 */   // GIR_Coverage, 15559,
     /*  209202 */   GIR_EraseRootFromParent_Done,
     /*  209203 */ // Label 2964: @209203
     /*  209203 */ GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(209273), // Rule ID 15560 //
     /*  209208 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  209211 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209214 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  209221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  209236 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  209236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  209239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  209241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  209246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  209251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  209256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  209261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209271 */   GIR_RootConstrainSelectedInstOperands,
     /*  209272 */   // GIR_Coverage, 15560,
     /*  209272 */   GIR_EraseRootFromParent_Done,
     /*  209273 */ // Label 2965: @209273
     /*  209273 */ GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(209343), // Rule ID 15561 //
     /*  209278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  209281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  209291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209295 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  209306 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  209306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  209309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  209311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  209316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  209321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  209326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  209331 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209334 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209337 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209341 */   GIR_RootConstrainSelectedInstOperands,
     /*  209342 */   // GIR_Coverage, 15561,
     /*  209342 */   GIR_EraseRootFromParent_Done,
     /*  209343 */ // Label 2966: @209343
     /*  209343 */ GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(209413), // Rule ID 15562 //
     /*  209348 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  209351 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209354 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  209361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  209376 */   // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  209376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  209379 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  209381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  209386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  209391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  209396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  209401 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209404 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209411 */   GIR_RootConstrainSelectedInstOperands,
     /*  209412 */   // GIR_Coverage, 15562,
     /*  209412 */   GIR_EraseRootFromParent_Done,
     /*  209413 */ // Label 2967: @209413
     /*  209413 */ GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(209477), // Rule ID 29375 //
     /*  209418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  209421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209424 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209448 */   // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209471 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209475 */   GIR_RootConstrainSelectedInstOperands,
     /*  209476 */   // GIR_Coverage, 29375,
     /*  209476 */   GIR_EraseRootFromParent_Done,
     /*  209477 */ // Label 2968: @209477
     /*  209477 */ GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(209541), // Rule ID 29376 //
     /*  209482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  209485 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209488 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209512 */   // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209532 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209535 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209539 */   GIR_RootConstrainSelectedInstOperands,
     /*  209540 */   // GIR_Coverage, 29376,
     /*  209540 */   GIR_EraseRootFromParent_Done,
     /*  209541 */ // Label 2969: @209541
     /*  209541 */ GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(209605), // Rule ID 29377 //
     /*  209546 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  209549 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209552 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209569 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209576 */   // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209576 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209579 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209603 */   GIR_RootConstrainSelectedInstOperands,
     /*  209604 */   // GIR_Coverage, 29377,
     /*  209604 */   GIR_EraseRootFromParent_Done,
     /*  209605 */ // Label 2970: @209605
     /*  209605 */ GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(209669), // Rule ID 29378 //
     /*  209610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  209613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209616 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209640 */   // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209643 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209660 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209667 */   GIR_RootConstrainSelectedInstOperands,
     /*  209668 */   // GIR_Coverage, 29378,
     /*  209668 */   GIR_EraseRootFromParent_Done,
     /*  209669 */ // Label 2971: @209669
     /*  209669 */ GIM_Try, /*On fail goto*//*Label 2972*/ GIMT_Encode4(209733), // Rule ID 29379 //
     /*  209674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  209677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209680 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209697 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209704 */   // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209704 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209707 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209731 */   GIR_RootConstrainSelectedInstOperands,
     /*  209732 */   // GIR_Coverage, 29379,
     /*  209732 */   GIR_EraseRootFromParent_Done,
     /*  209733 */ // Label 2972: @209733
     /*  209733 */ GIM_Try, /*On fail goto*//*Label 2973*/ GIMT_Encode4(209797), // Rule ID 29407 //
     /*  209738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  209741 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209744 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209748 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209757 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209761 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209768 */   // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209771 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209788 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209791 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209795 */   GIR_RootConstrainSelectedInstOperands,
     /*  209796 */   // GIR_Coverage, 29407,
     /*  209796 */   GIR_EraseRootFromParent_Done,
     /*  209797 */ // Label 2973: @209797
     /*  209797 */ GIM_Try, /*On fail goto*//*Label 2974*/ GIMT_Encode4(209861), // Rule ID 29408 //
     /*  209802 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  209805 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209808 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209832 */   // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209835 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209859 */   GIR_RootConstrainSelectedInstOperands,
     /*  209860 */   // GIR_Coverage, 29408,
     /*  209860 */   GIR_EraseRootFromParent_Done,
     /*  209861 */ // Label 2974: @209861
     /*  209861 */ GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(209925), // Rule ID 29409 //
     /*  209866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  209869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209872 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209881 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209885 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209889 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209896 */   // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209899 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209919 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209923 */   GIR_RootConstrainSelectedInstOperands,
     /*  209924 */   // GIR_Coverage, 29409,
     /*  209924 */   GIR_EraseRootFromParent_Done,
     /*  209925 */ // Label 2975: @209925
     /*  209925 */ GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(209989), // Rule ID 29410 //
     /*  209930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  209933 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  209936 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  209940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  209945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  209949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  209953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  209960 */   // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  209960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  209963 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  209965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  209970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  209975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  209980 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  209983 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  209987 */   GIR_RootConstrainSelectedInstOperands,
     /*  209988 */   // GIR_Coverage, 29410,
     /*  209988 */   GIR_EraseRootFromParent_Done,
     /*  209989 */ // Label 2976: @209989
     /*  209989 */ GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(210053), // Rule ID 29411 //
     /*  209994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  209997 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210000 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  210004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  210009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  210024 */   // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  210024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  210027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  210029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  210034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  210039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  210044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210047 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210051 */   GIR_RootConstrainSelectedInstOperands,
     /*  210052 */   // GIR_Coverage, 29411,
     /*  210052 */   GIR_EraseRootFromParent_Done,
     /*  210053 */ // Label 2977: @210053
     /*  210053 */ GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(210118), // Rule ID 15523 //
     /*  210058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  210061 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210064 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210071 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210075 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210079 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210086 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210086 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210089 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210106 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210116 */   GIR_RootConstrainSelectedInstOperands,
     /*  210117 */   // GIR_Coverage, 15523,
     /*  210117 */   GIR_EraseRootFromParent_Done,
     /*  210118 */ // Label 2978: @210118
     /*  210118 */ GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(210183), // Rule ID 15524 //
     /*  210123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  210126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210151 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210154 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210181 */   GIR_RootConstrainSelectedInstOperands,
     /*  210182 */   // GIR_Coverage, 15524,
     /*  210182 */   GIR_EraseRootFromParent_Done,
     /*  210183 */ // Label 2979: @210183
     /*  210183 */ GIM_Try, /*On fail goto*//*Label 2980*/ GIMT_Encode4(210248), // Rule ID 15525 //
     /*  210188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  210191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210205 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210209 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210216 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210216 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210219 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210236 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210246 */   GIR_RootConstrainSelectedInstOperands,
     /*  210247 */   // GIR_Coverage, 15525,
     /*  210247 */   GIR_EraseRootFromParent_Done,
     /*  210248 */ // Label 2980: @210248
     /*  210248 */ GIM_Try, /*On fail goto*//*Label 2981*/ GIMT_Encode4(210313), // Rule ID 15526 //
     /*  210253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  210256 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210259 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210274 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210281 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210281 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210284 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210301 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210304 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210307 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210311 */   GIR_RootConstrainSelectedInstOperands,
     /*  210312 */   // GIR_Coverage, 15526,
     /*  210312 */   GIR_EraseRootFromParent_Done,
     /*  210313 */ // Label 2981: @210313
     /*  210313 */ GIM_Try, /*On fail goto*//*Label 2982*/ GIMT_Encode4(210378), // Rule ID 15527 //
     /*  210318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  210321 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210324 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210335 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210339 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210346 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210349 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210376 */   GIR_RootConstrainSelectedInstOperands,
     /*  210377 */   // GIR_Coverage, 15527,
     /*  210377 */   GIR_EraseRootFromParent_Done,
     /*  210378 */ // Label 2982: @210378
     /*  210378 */ GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(210443), // Rule ID 15533 //
     /*  210383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  210386 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210389 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210400 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210404 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210411 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  210414 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210431 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210441 */   GIR_RootConstrainSelectedInstOperands,
     /*  210442 */   // GIR_Coverage, 15533,
     /*  210442 */   GIR_EraseRootFromParent_Done,
     /*  210443 */ // Label 2983: @210443
     /*  210443 */ GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(210508), // Rule ID 15534 //
     /*  210448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  210451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210454 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210476 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  210479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210506 */   GIR_RootConstrainSelectedInstOperands,
     /*  210507 */   // GIR_Coverage, 15534,
     /*  210507 */   GIR_EraseRootFromParent_Done,
     /*  210508 */ // Label 2984: @210508
     /*  210508 */ GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(210573), // Rule ID 15535 //
     /*  210513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  210516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210530 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210541 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  210544 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210561 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210564 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210571 */   GIR_RootConstrainSelectedInstOperands,
     /*  210572 */   // GIR_Coverage, 15535,
     /*  210572 */   GIR_EraseRootFromParent_Done,
     /*  210573 */ // Label 2985: @210573
     /*  210573 */ GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(210638), // Rule ID 15536 //
     /*  210578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  210581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210606 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  210609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210629 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210632 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210636 */   GIR_RootConstrainSelectedInstOperands,
     /*  210637 */   // GIR_Coverage, 15536,
     /*  210637 */   GIR_EraseRootFromParent_Done,
     /*  210638 */ // Label 2986: @210638
     /*  210638 */ GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(210703), // Rule ID 15537 //
     /*  210643 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  210646 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210660 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210664 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210671 */   // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  210674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210691 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210694 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210697 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210701 */   GIR_RootConstrainSelectedInstOperands,
     /*  210702 */   // GIR_Coverage, 15537,
     /*  210702 */   GIR_EraseRootFromParent_Done,
     /*  210703 */ // Label 2987: @210703
     /*  210703 */ GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(210768), // Rule ID 15543 //
     /*  210708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  210711 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210714 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210721 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210725 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210729 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210736 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210736 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210739 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210756 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210759 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210762 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210766 */   GIR_RootConstrainSelectedInstOperands,
     /*  210767 */   // GIR_Coverage, 15543,
     /*  210767 */   GIR_EraseRootFromParent_Done,
     /*  210768 */ // Label 2988: @210768
     /*  210768 */ GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(210833), // Rule ID 15544 //
     /*  210773 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  210776 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210779 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210786 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210790 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210801 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210804 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210821 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210831 */   GIR_RootConstrainSelectedInstOperands,
     /*  210832 */   // GIR_Coverage, 15544,
     /*  210832 */   GIR_EraseRootFromParent_Done,
     /*  210833 */ // Label 2989: @210833
     /*  210833 */ GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(210898), // Rule ID 15545 //
     /*  210838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  210841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210855 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210859 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210866 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210866 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210869 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210886 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210889 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210892 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210896 */   GIR_RootConstrainSelectedInstOperands,
     /*  210897 */   // GIR_Coverage, 15545,
     /*  210897 */   GIR_EraseRootFromParent_Done,
     /*  210898 */ // Label 2990: @210898
     /*  210898 */ GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(210963), // Rule ID 15546 //
     /*  210903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  210906 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210909 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210920 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210924 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210931 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210931 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210934 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  210936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  210941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  210946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  210951 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  210957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  210961 */   GIR_RootConstrainSelectedInstOperands,
     /*  210962 */   // GIR_Coverage, 15546,
     /*  210962 */   GIR_EraseRootFromParent_Done,
     /*  210963 */ // Label 2991: @210963
     /*  210963 */ GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(211028), // Rule ID 15547 //
     /*  210968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  210971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  210974 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  210981 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  210985 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  210989 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  210996 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  210996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  210999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  211001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  211006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  211011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  211016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211026 */   GIR_RootConstrainSelectedInstOperands,
     /*  211027 */   // GIR_Coverage, 15547,
     /*  211027 */   GIR_EraseRootFromParent_Done,
     /*  211028 */ // Label 2992: @211028
     /*  211028 */ GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(211093), // Rule ID 15553 //
     /*  211033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  211036 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211039 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  211046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211050 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211054 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  211061 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  211061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  211064 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  211066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  211071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  211076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  211081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211084 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211087 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211091 */   GIR_RootConstrainSelectedInstOperands,
     /*  211092 */   // GIR_Coverage, 15553,
     /*  211092 */   GIR_EraseRootFromParent_Done,
     /*  211093 */ // Label 2993: @211093
     /*  211093 */ GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(211158), // Rule ID 15554 //
     /*  211098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  211101 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211104 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  211111 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211115 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211119 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  211126 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  211126 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  211129 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  211131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  211136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  211141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  211146 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211149 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211152 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211156 */   GIR_RootConstrainSelectedInstOperands,
     /*  211157 */   // GIR_Coverage, 15554,
     /*  211157 */   GIR_EraseRootFromParent_Done,
     /*  211158 */ // Label 2994: @211158
     /*  211158 */ GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(211223), // Rule ID 15555 //
     /*  211163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  211166 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211169 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  211176 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  211191 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  211191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  211194 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  211196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  211201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  211206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  211211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211221 */   GIR_RootConstrainSelectedInstOperands,
     /*  211222 */   // GIR_Coverage, 15555,
     /*  211222 */   GIR_EraseRootFromParent_Done,
     /*  211223 */ // Label 2995: @211223
     /*  211223 */ GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(211288), // Rule ID 15556 //
     /*  211228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  211231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  211241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  211256 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  211256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  211259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  211261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  211266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  211271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  211276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211279 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211282 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211286 */   GIR_RootConstrainSelectedInstOperands,
     /*  211287 */   // GIR_Coverage, 15556,
     /*  211287 */   GIR_EraseRootFromParent_Done,
     /*  211288 */ // Label 2996: @211288
     /*  211288 */ GIM_Try, /*On fail goto*//*Label 2997*/ GIMT_Encode4(211353), // Rule ID 15557 //
     /*  211293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  211296 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  211306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  211321 */   // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  211321 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  211324 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  211326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  211331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  211336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  211341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211344 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211351 */   GIR_RootConstrainSelectedInstOperands,
     /*  211352 */   // GIR_Coverage, 15557,
     /*  211352 */   GIR_EraseRootFromParent_Done,
     /*  211353 */ // Label 2997: @211353
     /*  211353 */ GIM_Try, /*On fail goto*//*Label 2998*/ GIMT_Encode4(211413), // Rule ID 29381 //
     /*  211358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  211361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211364 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211384 */   // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211404 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211411 */   GIR_RootConstrainSelectedInstOperands,
     /*  211412 */   // GIR_Coverage, 29381,
     /*  211412 */   GIR_EraseRootFromParent_Done,
     /*  211413 */ // Label 2998: @211413
     /*  211413 */ GIM_Try, /*On fail goto*//*Label 2999*/ GIMT_Encode4(211473), // Rule ID 29382 //
     /*  211418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  211421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211424 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211429 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211433 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211437 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211444 */   // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211444 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211447 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211464 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211471 */   GIR_RootConstrainSelectedInstOperands,
     /*  211472 */   // GIR_Coverage, 29382,
     /*  211472 */   GIR_EraseRootFromParent_Done,
     /*  211473 */ // Label 2999: @211473
     /*  211473 */ GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(211533), // Rule ID 29383 //
     /*  211478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  211481 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211484 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211493 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211497 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211504 */   // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211507 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211524 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211527 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211531 */   GIR_RootConstrainSelectedInstOperands,
     /*  211532 */   // GIR_Coverage, 29383,
     /*  211532 */   GIR_EraseRootFromParent_Done,
     /*  211533 */ // Label 3000: @211533
     /*  211533 */ GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(211593), // Rule ID 29384 //
     /*  211538 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  211541 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211544 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211553 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211557 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211564 */   // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211564 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211567 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211584 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211587 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211591 */   GIR_RootConstrainSelectedInstOperands,
     /*  211592 */   // GIR_Coverage, 29384,
     /*  211592 */   GIR_EraseRootFromParent_Done,
     /*  211593 */ // Label 3001: @211593
     /*  211593 */ GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(211653), // Rule ID 29385 //
     /*  211598 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  211601 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211604 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211624 */   // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211627 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211644 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211647 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211651 */   GIR_RootConstrainSelectedInstOperands,
     /*  211652 */   // GIR_Coverage, 29385,
     /*  211652 */   GIR_EraseRootFromParent_Done,
     /*  211653 */ // Label 3002: @211653
     /*  211653 */ GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(211713), // Rule ID 29413 //
     /*  211658 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  211661 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211664 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211669 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211673 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211677 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211684 */   // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211687 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211704 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211707 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211711 */   GIR_RootConstrainSelectedInstOperands,
     /*  211712 */   // GIR_Coverage, 29413,
     /*  211712 */   GIR_EraseRootFromParent_Done,
     /*  211713 */ // Label 3003: @211713
     /*  211713 */ GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(211773), // Rule ID 29414 //
     /*  211718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  211721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211724 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211737 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211744 */   // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211767 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211771 */   GIR_RootConstrainSelectedInstOperands,
     /*  211772 */   // GIR_Coverage, 29414,
     /*  211772 */   GIR_EraseRootFromParent_Done,
     /*  211773 */ // Label 3004: @211773
     /*  211773 */ GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(211833), // Rule ID 29415 //
     /*  211778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  211781 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211784 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211804 */   // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211831 */   GIR_RootConstrainSelectedInstOperands,
     /*  211832 */   // GIR_Coverage, 29415,
     /*  211832 */   GIR_EraseRootFromParent_Done,
     /*  211833 */ // Label 3005: @211833
     /*  211833 */ GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(211893), // Rule ID 29416 //
     /*  211838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  211841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211853 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211857 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211864 */   // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211864 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211867 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211891 */   GIR_RootConstrainSelectedInstOperands,
     /*  211892 */   // GIR_Coverage, 29416,
     /*  211892 */   GIR_EraseRootFromParent_Done,
     /*  211893 */ // Label 3006: @211893
     /*  211893 */ GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(211953), // Rule ID 29417 //
     /*  211898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  211901 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  211904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  211924 */   // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  211924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  211927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  211929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  211934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  211939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  211944 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  211947 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  211951 */   GIR_RootConstrainSelectedInstOperands,
     /*  211952 */   // GIR_Coverage, 29417,
     /*  211952 */   GIR_EraseRootFromParent_Done,
     /*  211953 */ // Label 3007: @211953
     /*  211953 */ GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(212019), // Rule ID 29111 //
     /*  211958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  211961 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  211964 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  211968 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  211975 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  211980 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  211984 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  211988 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  211995 */   // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_64_glue>><<P:Predicate_atomic_load_nonext_64_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  211995 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  211998 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212010 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212013 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212017 */   GIR_RootConstrainSelectedInstOperands,
     /*  212018 */   // GIR_Coverage, 29111,
     /*  212018 */   GIR_EraseRootFromParent_Done,
     /*  212019 */ // Label 3008: @212019
     /*  212019 */ GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(212085), // Rule ID 29112 //
     /*  212024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  212027 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212030 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212034 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212041 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212050 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212054 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212061 */   // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_64_glue>><<P:Predicate_atomic_load_nonext_64_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  212064 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212076 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212079 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212083 */   GIR_RootConstrainSelectedInstOperands,
     /*  212084 */   // GIR_Coverage, 29112,
     /*  212084 */   GIR_EraseRootFromParent_Done,
     /*  212085 */ // Label 3009: @212085
     /*  212085 */ GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(212151), // Rule ID 29113 //
     /*  212090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  212093 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212096 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212100 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212107 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212112 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212116 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212120 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212127 */   // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_64_glue>><<P:Predicate_atomic_load_nonext_64_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  212130 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212142 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212145 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212149 */   GIR_RootConstrainSelectedInstOperands,
     /*  212150 */   // GIR_Coverage, 29113,
     /*  212150 */   GIR_EraseRootFromParent_Done,
     /*  212151 */ // Label 3010: @212151
     /*  212151 */ GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(212217), // Rule ID 29114 //
     /*  212156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  212159 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212162 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212166 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212173 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212178 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212182 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212186 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212193 */   // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_64_glue>><<P:Predicate_atomic_load_nonext_64_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212193 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  212196 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212208 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212211 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212215 */   GIR_RootConstrainSelectedInstOperands,
     /*  212216 */   // GIR_Coverage, 29114,
     /*  212216 */   GIR_EraseRootFromParent_Done,
     /*  212217 */ // Label 3011: @212217
     /*  212217 */ GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(212283), // Rule ID 29115 //
     /*  212222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  212225 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212228 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212252 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212259 */   // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext_glue>><<P:Predicate_atomic_load_nonext_64_glue>><<P:Predicate_atomic_load_nonext_64_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  212262 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212274 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212277 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212281 */   GIR_RootConstrainSelectedInstOperands,
     /*  212282 */   // GIR_Coverage, 29115,
     /*  212282 */   GIR_EraseRootFromParent_Done,
     /*  212283 */ // Label 3012: @212283
     /*  212283 */ GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(212349), // Rule ID 29116 //
     /*  212288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  212291 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212294 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212298 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212305 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212314 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212318 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212325 */   // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212325 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  212328 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212340 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212343 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212347 */   GIR_RootConstrainSelectedInstOperands,
     /*  212348 */   // GIR_Coverage, 29116,
     /*  212348 */   GIR_EraseRootFromParent_Done,
     /*  212349 */ // Label 3013: @212349
     /*  212349 */ GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(212415), // Rule ID 29117 //
     /*  212354 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  212357 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212360 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212364 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212371 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212376 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212380 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212384 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212391 */   // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  212394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212413 */   GIR_RootConstrainSelectedInstOperands,
     /*  212414 */   // GIR_Coverage, 29117,
     /*  212414 */   GIR_EraseRootFromParent_Done,
     /*  212415 */ // Label 3014: @212415
     /*  212415 */ GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(212481), // Rule ID 29118 //
     /*  212420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  212423 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212426 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212430 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212457 */   // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  212460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212472 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212479 */   GIR_RootConstrainSelectedInstOperands,
     /*  212480 */   // GIR_Coverage, 29118,
     /*  212480 */   GIR_EraseRootFromParent_Done,
     /*  212481 */ // Label 3015: @212481
     /*  212481 */ GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(212547), // Rule ID 29119 //
     /*  212486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  212489 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212492 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212512 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212516 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212523 */   // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  212526 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212538 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212541 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212545 */   GIR_RootConstrainSelectedInstOperands,
     /*  212546 */   // GIR_Coverage, 29119,
     /*  212546 */   GIR_EraseRootFromParent_Done,
     /*  212547 */ // Label 3016: @212547
     /*  212547 */ GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(212613), // Rule ID 29120 //
     /*  212552 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  212555 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212558 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212562 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  212574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212578 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  212589 */   // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  212589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  212592 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  212599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  212604 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  212607 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212611 */   GIR_RootConstrainSelectedInstOperands,
     /*  212612 */   // GIR_Coverage, 29120,
     /*  212612 */   GIR_EraseRootFromParent_Done,
     /*  212613 */ // Label 3017: @212613
     /*  212613 */ GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(212688), // Rule ID 12583 //
     /*  212618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  212621 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212624 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212628 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212635 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  212642 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212646 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212650 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  212657 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  212657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  212660 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  212667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  212672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  212677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  212682 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212686 */   GIR_RootConstrainSelectedInstOperands,
     /*  212687 */   // GIR_Coverage, 12583,
     /*  212687 */   GIR_EraseRootFromParent_Done,
     /*  212688 */ // Label 3018: @212688
     /*  212688 */ GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(212763), // Rule ID 12584 //
     /*  212693 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  212696 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212699 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212703 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212710 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  212717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212721 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212725 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  212732 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  212732 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  212735 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  212742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  212747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  212752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  212757 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212761 */   GIR_RootConstrainSelectedInstOperands,
     /*  212762 */   // GIR_Coverage, 12584,
     /*  212762 */   GIR_EraseRootFromParent_Done,
     /*  212763 */ // Label 3019: @212763
     /*  212763 */ GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(212838), // Rule ID 12585 //
     /*  212768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  212771 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212774 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212778 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212785 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  212792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212796 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212800 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  212807 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  212807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  212810 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  212817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  212822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  212827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  212832 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212836 */   GIR_RootConstrainSelectedInstOperands,
     /*  212837 */   // GIR_Coverage, 12585,
     /*  212837 */   GIR_EraseRootFromParent_Done,
     /*  212838 */ // Label 3020: @212838
     /*  212838 */ GIM_Try, /*On fail goto*//*Label 3021*/ GIMT_Encode4(212913), // Rule ID 12586 //
     /*  212843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  212846 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212849 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212853 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212860 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  212867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212871 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212875 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  212882 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  212882 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  212885 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  212892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  212897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  212902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  212907 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212911 */   GIR_RootConstrainSelectedInstOperands,
     /*  212912 */   // GIR_Coverage, 12586,
     /*  212912 */   GIR_EraseRootFromParent_Done,
     /*  212913 */ // Label 3021: @212913
     /*  212913 */ GIM_Try, /*On fail goto*//*Label 3022*/ GIMT_Encode4(212988), // Rule ID 12587 //
     /*  212918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  212921 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  212924 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  212928 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  212935 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  212942 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  212946 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  212950 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  212957 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  212957 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  212960 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  212962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  212967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  212972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  212977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  212982 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  212986 */   GIR_RootConstrainSelectedInstOperands,
     /*  212987 */   // GIR_Coverage, 12587,
     /*  212987 */   GIR_EraseRootFromParent_Done,
     /*  212988 */ // Label 3022: @212988
     /*  212988 */ GIM_Try, /*On fail goto*//*Label 3023*/ GIMT_Encode4(213052), // Rule ID 12263 //
     /*  212993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  212996 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  212999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213021 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213050 */   GIR_RootConstrainSelectedInstOperands,
     /*  213051 */   // GIR_Coverage, 12263,
     /*  213051 */   GIR_EraseRootFromParent_Done,
     /*  213052 */ // Label 3023: @213052
     /*  213052 */ GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(213116), // Rule ID 12264 //
     /*  213057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  213060 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213063 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213085 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213110 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213114 */   GIR_RootConstrainSelectedInstOperands,
     /*  213115 */   // GIR_Coverage, 12264,
     /*  213115 */   GIR_EraseRootFromParent_Done,
     /*  213116 */ // Label 3024: @213116
     /*  213116 */ GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(213180), // Rule ID 12265 //
     /*  213121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  213124 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213138 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213142 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213149 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213149 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213152 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213178 */   GIR_RootConstrainSelectedInstOperands,
     /*  213179 */   // GIR_Coverage, 12265,
     /*  213179 */   GIR_EraseRootFromParent_Done,
     /*  213180 */ // Label 3025: @213180
     /*  213180 */ GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(213244), // Rule ID 12266 //
     /*  213185 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  213188 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213191 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213213 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213216 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213242 */   GIR_RootConstrainSelectedInstOperands,
     /*  213243 */   // GIR_Coverage, 12266,
     /*  213243 */   GIR_EraseRootFromParent_Done,
     /*  213244 */ // Label 3026: @213244
     /*  213244 */ GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(213308), // Rule ID 12267 //
     /*  213249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  213252 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213255 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213266 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213270 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213277 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213280 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213306 */   GIR_RootConstrainSelectedInstOperands,
     /*  213307 */   // GIR_Coverage, 12267,
     /*  213307 */   GIR_EraseRootFromParent_Done,
     /*  213308 */ // Label 3027: @213308
     /*  213308 */ GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(213372), // Rule ID 12283 //
     /*  213313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  213316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213341 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213344 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213370 */   GIR_RootConstrainSelectedInstOperands,
     /*  213371 */   // GIR_Coverage, 12283,
     /*  213371 */   GIR_EraseRootFromParent_Done,
     /*  213372 */ // Label 3028: @213372
     /*  213372 */ GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(213436), // Rule ID 12284 //
     /*  213377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  213380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213394 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213398 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213405 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213434 */   GIR_RootConstrainSelectedInstOperands,
     /*  213435 */   // GIR_Coverage, 12284,
     /*  213435 */   GIR_EraseRootFromParent_Done,
     /*  213436 */ // Label 3029: @213436
     /*  213436 */ GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(213500), // Rule ID 12285 //
     /*  213441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  213444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213469 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213498 */   GIR_RootConstrainSelectedInstOperands,
     /*  213499 */   // GIR_Coverage, 12285,
     /*  213499 */   GIR_EraseRootFromParent_Done,
     /*  213500 */ // Label 3030: @213500
     /*  213500 */ GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(213564), // Rule ID 12286 //
     /*  213505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  213508 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213511 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213522 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213526 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213533 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213533 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213536 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213562 */   GIR_RootConstrainSelectedInstOperands,
     /*  213563 */   // GIR_Coverage, 12286,
     /*  213563 */   GIR_EraseRootFromParent_Done,
     /*  213564 */ // Label 3031: @213564
     /*  213564 */ GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(213628), // Rule ID 12287 //
     /*  213569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  213572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213575 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  213597 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  213597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  213600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  213607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  213612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  213617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  213622 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213626 */   GIR_RootConstrainSelectedInstOperands,
     /*  213627 */   // GIR_Coverage, 12287,
     /*  213627 */   GIR_EraseRootFromParent_Done,
     /*  213628 */ // Label 3032: @213628
     /*  213628 */ GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(213696), // Rule ID 12578 //
     /*  213633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  213636 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  213639 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  213643 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  213650 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213661 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213665 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  213672 */   // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  213672 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  213675 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  213682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  213687 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  213690 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213694 */   GIR_RootConstrainSelectedInstOperands,
     /*  213695 */   // GIR_Coverage, 12578,
     /*  213695 */   GIR_EraseRootFromParent_Done,
     /*  213696 */ // Label 3033: @213696
     /*  213696 */ GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(213764), // Rule ID 12579 //
     /*  213701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  213704 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  213707 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  213711 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  213718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  213740 */   // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  213740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  213743 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  213750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  213755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  213758 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213762 */   GIR_RootConstrainSelectedInstOperands,
     /*  213763 */   // GIR_Coverage, 12579,
     /*  213763 */   GIR_EraseRootFromParent_Done,
     /*  213764 */ // Label 3034: @213764
     /*  213764 */ GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(213832), // Rule ID 12580 //
     /*  213769 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  213772 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  213775 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  213779 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  213786 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213797 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213801 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  213808 */   // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  213808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  213811 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  213818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  213823 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  213826 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213830 */   GIR_RootConstrainSelectedInstOperands,
     /*  213831 */   // GIR_Coverage, 12580,
     /*  213831 */   GIR_EraseRootFromParent_Done,
     /*  213832 */ // Label 3035: @213832
     /*  213832 */ GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(213900), // Rule ID 12581 //
     /*  213837 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  213840 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  213843 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  213847 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  213854 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213865 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213869 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  213876 */   // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  213876 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  213879 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  213886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  213891 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  213894 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213898 */   GIR_RootConstrainSelectedInstOperands,
     /*  213899 */   // GIR_Coverage, 12581,
     /*  213899 */   GIR_EraseRootFromParent_Done,
     /*  213900 */ // Label 3036: @213900
     /*  213900 */ GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(213968), // Rule ID 12582 //
     /*  213905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  213908 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  213911 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  213915 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  213922 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  213944 */   // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  213944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  213947 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  213949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  213954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  213959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  213962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  213966 */   GIR_RootConstrainSelectedInstOperands,
     /*  213967 */   // GIR_Coverage, 12582,
     /*  213967 */   GIR_EraseRootFromParent_Done,
     /*  213968 */ // Label 3037: @213968
     /*  213968 */ GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(214025), // Rule ID 12258 //
     /*  213973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  213976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  213979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  213986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  213990 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  213994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214001 */   // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214023 */   GIR_RootConstrainSelectedInstOperands,
     /*  214024 */   // GIR_Coverage, 12258,
     /*  214024 */   GIR_EraseRootFromParent_Done,
     /*  214025 */ // Label 3038: @214025
     /*  214025 */ GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(214082), // Rule ID 12259 //
     /*  214030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  214033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214036 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214058 */   // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214061 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214073 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214076 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214080 */   GIR_RootConstrainSelectedInstOperands,
     /*  214081 */   // GIR_Coverage, 12259,
     /*  214081 */   GIR_EraseRootFromParent_Done,
     /*  214082 */ // Label 3039: @214082
     /*  214082 */ GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(214139), // Rule ID 12260 //
     /*  214087 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  214090 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214093 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214100 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214104 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214108 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214115 */   // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214115 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214118 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214133 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214137 */   GIR_RootConstrainSelectedInstOperands,
     /*  214138 */   // GIR_Coverage, 12260,
     /*  214138 */   GIR_EraseRootFromParent_Done,
     /*  214139 */ // Label 3040: @214139
     /*  214139 */ GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(214196), // Rule ID 12261 //
     /*  214144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  214147 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214150 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214157 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214161 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214165 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214172 */   // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214172 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214175 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214190 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214194 */   GIR_RootConstrainSelectedInstOperands,
     /*  214195 */   // GIR_Coverage, 12261,
     /*  214195 */   GIR_EraseRootFromParent_Done,
     /*  214196 */ // Label 3041: @214196
     /*  214196 */ GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(214253), // Rule ID 12262 //
     /*  214201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  214204 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214207 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214214 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214229 */   // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214232 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214251 */   GIR_RootConstrainSelectedInstOperands,
     /*  214252 */   // GIR_Coverage, 12262,
     /*  214252 */   GIR_EraseRootFromParent_Done,
     /*  214253 */ // Label 3042: @214253
     /*  214253 */ GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(214310), // Rule ID 12278 //
     /*  214258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  214261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214275 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214279 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214286 */   // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214301 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214304 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214308 */   GIR_RootConstrainSelectedInstOperands,
     /*  214309 */   // GIR_Coverage, 12278,
     /*  214309 */   GIR_EraseRootFromParent_Done,
     /*  214310 */ // Label 3043: @214310
     /*  214310 */ GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(214367), // Rule ID 12279 //
     /*  214315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  214318 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214321 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214343 */   // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214358 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214361 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214365 */   GIR_RootConstrainSelectedInstOperands,
     /*  214366 */   // GIR_Coverage, 12279,
     /*  214366 */   GIR_EraseRootFromParent_Done,
     /*  214367 */ // Label 3044: @214367
     /*  214367 */ GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(214424), // Rule ID 12280 //
     /*  214372 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  214375 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214378 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214389 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214393 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214400 */   // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214403 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214415 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214418 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214422 */   GIR_RootConstrainSelectedInstOperands,
     /*  214423 */   // GIR_Coverage, 12280,
     /*  214423 */   GIR_EraseRootFromParent_Done,
     /*  214424 */ // Label 3045: @214424
     /*  214424 */ GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(214481), // Rule ID 12281 //
     /*  214429 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  214432 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214435 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214457 */   // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214472 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214479 */   GIR_RootConstrainSelectedInstOperands,
     /*  214480 */   // GIR_Coverage, 12281,
     /*  214480 */   GIR_EraseRootFromParent_Done,
     /*  214481 */ // Label 3046: @214481
     /*  214481 */ GIM_Try, /*On fail goto*//*Label 3047*/ GIMT_Encode4(214538), // Rule ID 12282 //
     /*  214486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  214489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  214514 */   // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  214514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  214517 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  214524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  214529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  214532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214536 */   GIR_RootConstrainSelectedInstOperands,
     /*  214537 */   // GIR_Coverage, 12282,
     /*  214537 */   GIR_EraseRootFromParent_Done,
     /*  214538 */ // Label 3047: @214538
     /*  214538 */ GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(214614), // Rule ID 9911 //
     /*  214543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  214546 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  214549 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  214553 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  214560 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214568 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214572 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214576 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  214583 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  214583 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  214586 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  214593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  214598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  214603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  214608 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214612 */   GIR_RootConstrainSelectedInstOperands,
     /*  214613 */   // GIR_Coverage, 9911,
     /*  214613 */   GIR_EraseRootFromParent_Done,
     /*  214614 */ // Label 3048: @214614
     /*  214614 */ GIM_Try, /*On fail goto*//*Label 3049*/ GIMT_Encode4(214690), // Rule ID 9912 //
     /*  214619 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  214622 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  214625 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  214629 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  214636 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  214659 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  214659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  214662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  214669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  214674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  214679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  214684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214688 */   GIR_RootConstrainSelectedInstOperands,
     /*  214689 */   // GIR_Coverage, 9912,
     /*  214689 */   GIR_EraseRootFromParent_Done,
     /*  214690 */ // Label 3049: @214690
     /*  214690 */ GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(214766), // Rule ID 9913 //
     /*  214695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  214698 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  214701 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  214705 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  214712 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214724 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214728 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  214735 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  214735 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  214738 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  214745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  214750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  214755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  214760 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214764 */   GIR_RootConstrainSelectedInstOperands,
     /*  214765 */   // GIR_Coverage, 9913,
     /*  214765 */   GIR_EraseRootFromParent_Done,
     /*  214766 */ // Label 3050: @214766
     /*  214766 */ GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(214842), // Rule ID 9914 //
     /*  214771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  214774 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  214777 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  214781 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  214788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214804 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  214811 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  214811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  214814 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  214821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  214826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  214831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  214836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214840 */   GIR_RootConstrainSelectedInstOperands,
     /*  214841 */   // GIR_Coverage, 9914,
     /*  214841 */   GIR_EraseRootFromParent_Done,
     /*  214842 */ // Label 3051: @214842
     /*  214842 */ GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(214918), // Rule ID 9915 //
     /*  214847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  214850 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  214853 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  214857 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  214864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  214887 */   // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  214887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  214890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  214897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  214902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  214907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  214912 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214916 */   GIR_RootConstrainSelectedInstOperands,
     /*  214917 */   // GIR_Coverage, 9915,
     /*  214917 */   GIR_EraseRootFromParent_Done,
     /*  214918 */ // Label 3052: @214918
     /*  214918 */ GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(214983), // Rule ID 10131 //
     /*  214923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  214926 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  214937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  214941 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  214945 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  214952 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  214952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  214955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  214957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  214962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  214967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  214972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  214977 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  214981 */   GIR_RootConstrainSelectedInstOperands,
     /*  214982 */   // GIR_Coverage, 10131,
     /*  214982 */   GIR_EraseRootFromParent_Done,
     /*  214983 */ // Label 3053: @214983
     /*  214983 */ GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(215048), // Rule ID 10132 //
     /*  214988 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  214991 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  214994 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215010 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215017 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215046 */   GIR_RootConstrainSelectedInstOperands,
     /*  215047 */   // GIR_Coverage, 10132,
     /*  215047 */   GIR_EraseRootFromParent_Done,
     /*  215048 */ // Label 3054: @215048
     /*  215048 */ GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(215113), // Rule ID 10133 //
     /*  215053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  215056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215059 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215082 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215111 */   GIR_RootConstrainSelectedInstOperands,
     /*  215112 */   // GIR_Coverage, 10133,
     /*  215112 */   GIR_EraseRootFromParent_Done,
     /*  215113 */ // Label 3055: @215113
     /*  215113 */ GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(215178), // Rule ID 10134 //
     /*  215118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  215121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215124 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215147 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215172 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215176 */   GIR_RootConstrainSelectedInstOperands,
     /*  215177 */   // GIR_Coverage, 10134,
     /*  215177 */   GIR_EraseRootFromParent_Done,
     /*  215178 */ // Label 3056: @215178
     /*  215178 */ GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(215243), // Rule ID 10135 //
     /*  215183 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  215186 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215189 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215201 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215205 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215212 */   // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215212 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215215 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215237 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215241 */   GIR_RootConstrainSelectedInstOperands,
     /*  215242 */   // GIR_Coverage, 10135,
     /*  215242 */   GIR_EraseRootFromParent_Done,
     /*  215243 */ // Label 3057: @215243
     /*  215243 */ GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(215308), // Rule ID 10151 //
     /*  215248 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  215251 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215254 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215266 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215270 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215277 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215280 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215306 */   GIR_RootConstrainSelectedInstOperands,
     /*  215307 */   // GIR_Coverage, 10151,
     /*  215307 */   GIR_EraseRootFromParent_Done,
     /*  215308 */ // Label 3058: @215308
     /*  215308 */ GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(215373), // Rule ID 10152 //
     /*  215313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  215316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215331 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215335 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215342 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215342 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215345 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215367 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215371 */   GIR_RootConstrainSelectedInstOperands,
     /*  215372 */   // GIR_Coverage, 10152,
     /*  215372 */   GIR_EraseRootFromParent_Done,
     /*  215373 */ // Label 3059: @215373
     /*  215373 */ GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(215438), // Rule ID 10153 //
     /*  215378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  215381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215384 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215407 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215436 */   GIR_RootConstrainSelectedInstOperands,
     /*  215437 */   // GIR_Coverage, 10153,
     /*  215437 */   GIR_EraseRootFromParent_Done,
     /*  215438 */ // Label 3060: @215438
     /*  215438 */ GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(215503), // Rule ID 10154 //
     /*  215443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  215446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215472 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215501 */   GIR_RootConstrainSelectedInstOperands,
     /*  215502 */   // GIR_Coverage, 10154,
     /*  215502 */   GIR_EraseRootFromParent_Done,
     /*  215503 */ // Label 3061: @215503
     /*  215503 */ GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(215568), // Rule ID 10155 //
     /*  215508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  215511 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215514 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215526 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215530 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  215537 */   // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  215537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  215540 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  215547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  215552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  215557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  215562 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215566 */   GIR_RootConstrainSelectedInstOperands,
     /*  215567 */   // GIR_Coverage, 10155,
     /*  215567 */   GIR_EraseRootFromParent_Done,
     /*  215568 */ // Label 3062: @215568
     /*  215568 */ GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(215637), // Rule ID 9906 //
     /*  215573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  215576 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  215579 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  215583 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  215590 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  215613 */   // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  215613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  215616 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  215623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  215628 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  215631 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215635 */   GIR_RootConstrainSelectedInstOperands,
     /*  215636 */   // GIR_Coverage, 9906,
     /*  215636 */   GIR_EraseRootFromParent_Done,
     /*  215637 */ // Label 3063: @215637
     /*  215637 */ GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(215706), // Rule ID 9907 //
     /*  215642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  215645 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  215648 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  215652 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  215659 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215671 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215675 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  215682 */   // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  215682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  215685 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  215692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  215697 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  215700 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215704 */   GIR_RootConstrainSelectedInstOperands,
     /*  215705 */   // GIR_Coverage, 9907,
     /*  215705 */   GIR_EraseRootFromParent_Done,
     /*  215706 */ // Label 3064: @215706
     /*  215706 */ GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(215775), // Rule ID 9908 //
     /*  215711 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  215714 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  215717 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  215721 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  215728 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215740 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215744 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  215751 */   // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  215751 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  215754 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  215761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  215766 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  215769 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215773 */   GIR_RootConstrainSelectedInstOperands,
     /*  215774 */   // GIR_Coverage, 9908,
     /*  215774 */   GIR_EraseRootFromParent_Done,
     /*  215775 */ // Label 3065: @215775
     /*  215775 */ GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(215844), // Rule ID 9909 //
     /*  215780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  215783 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  215786 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  215790 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  215797 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  215820 */   // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  215820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  215823 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  215830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  215835 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  215838 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215842 */   GIR_RootConstrainSelectedInstOperands,
     /*  215843 */   // GIR_Coverage, 9909,
     /*  215843 */   GIR_EraseRootFromParent_Done,
     /*  215844 */ // Label 3066: @215844
     /*  215844 */ GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(215913), // Rule ID 9910 //
     /*  215849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  215852 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  215855 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  215859 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  215866 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215874 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215878 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215882 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  215889 */   // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  215889 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  215892 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  215899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  215904 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  215907 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215911 */   GIR_RootConstrainSelectedInstOperands,
     /*  215912 */   // GIR_Coverage, 9910,
     /*  215912 */   GIR_EraseRootFromParent_Done,
     /*  215913 */ // Label 3067: @215913
     /*  215913 */ GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(215971), // Rule ID 10126 //
     /*  215918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  215921 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215924 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215936 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  215947 */   // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  215947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  215950 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  215952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  215957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  215962 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  215965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  215969 */   GIR_RootConstrainSelectedInstOperands,
     /*  215970 */   // GIR_Coverage, 10126,
     /*  215970 */   GIR_EraseRootFromParent_Done,
     /*  215971 */ // Label 3068: @215971
     /*  215971 */ GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(216029), // Rule ID 10127 //
     /*  215976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  215979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  215982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  215990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  215994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  215998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216005 */   // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216027 */   GIR_RootConstrainSelectedInstOperands,
     /*  216028 */   // GIR_Coverage, 10127,
     /*  216028 */   GIR_EraseRootFromParent_Done,
     /*  216029 */ // Label 3069: @216029
     /*  216029 */ GIM_Try, /*On fail goto*//*Label 3070*/ GIMT_Encode4(216087), // Rule ID 10128 //
     /*  216034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  216037 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216040 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216052 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216056 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216063 */   // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216078 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216081 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216085 */   GIR_RootConstrainSelectedInstOperands,
     /*  216086 */   // GIR_Coverage, 10128,
     /*  216086 */   GIR_EraseRootFromParent_Done,
     /*  216087 */ // Label 3070: @216087
     /*  216087 */ GIM_Try, /*On fail goto*//*Label 3071*/ GIMT_Encode4(216145), // Rule ID 10129 //
     /*  216092 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  216095 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216098 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216106 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216110 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216114 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216121 */   // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216139 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216143 */   GIR_RootConstrainSelectedInstOperands,
     /*  216144 */   // GIR_Coverage, 10129,
     /*  216144 */   GIR_EraseRootFromParent_Done,
     /*  216145 */ // Label 3071: @216145
     /*  216145 */ GIM_Try, /*On fail goto*//*Label 3072*/ GIMT_Encode4(216203), // Rule ID 10130 //
     /*  216150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  216153 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216156 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216168 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216172 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216179 */   // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216179 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216182 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216194 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216197 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216201 */   GIR_RootConstrainSelectedInstOperands,
     /*  216202 */   // GIR_Coverage, 10130,
     /*  216202 */   GIR_EraseRootFromParent_Done,
     /*  216203 */ // Label 3072: @216203
     /*  216203 */ GIM_Try, /*On fail goto*//*Label 3073*/ GIMT_Encode4(216261), // Rule ID 10146 //
     /*  216208 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  216211 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216214 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216230 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216237 */   // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216240 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216252 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216255 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216259 */   GIR_RootConstrainSelectedInstOperands,
     /*  216260 */   // GIR_Coverage, 10146,
     /*  216260 */   GIR_EraseRootFromParent_Done,
     /*  216261 */ // Label 3073: @216261
     /*  216261 */ GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(216319), // Rule ID 10147 //
     /*  216266 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  216269 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216284 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216288 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216295 */   // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216298 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216310 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216313 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216317 */   GIR_RootConstrainSelectedInstOperands,
     /*  216318 */   // GIR_Coverage, 10147,
     /*  216318 */   GIR_EraseRootFromParent_Done,
     /*  216319 */ // Label 3074: @216319
     /*  216319 */ GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(216377), // Rule ID 10148 //
     /*  216324 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  216327 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216330 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216353 */   // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216368 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216371 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216375 */   GIR_RootConstrainSelectedInstOperands,
     /*  216376 */   // GIR_Coverage, 10148,
     /*  216376 */   GIR_EraseRootFromParent_Done,
     /*  216377 */ // Label 3075: @216377
     /*  216377 */ GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(216435), // Rule ID 10149 //
     /*  216382 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  216385 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216388 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216400 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216404 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216411 */   // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216414 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216426 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216429 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216433 */   GIR_RootConstrainSelectedInstOperands,
     /*  216434 */   // GIR_Coverage, 10149,
     /*  216434 */   GIR_EraseRootFromParent_Done,
     /*  216435 */ // Label 3076: @216435
     /*  216435 */ GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(216493), // Rule ID 10150 //
     /*  216440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  216443 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216446 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  216454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  216458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  216469 */   // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  216469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  216472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  216474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  216479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216487 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216491 */   GIR_RootConstrainSelectedInstOperands,
     /*  216492 */   // GIR_Coverage, 10150,
     /*  216492 */   GIR_EraseRootFromParent_Done,
     /*  216493 */ // Label 3077: @216493
     /*  216493 */ GIM_Reject,
     /*  216494 */ // Label 1129: @216494
     /*  216494 */ GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(227985),
     /*  216499 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  216502 */   GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(216568), // Rule ID 8707 //
     /*  216507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  216510 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216522 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216526 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  216530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  216537 */     // (ld:{ *:[v2i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  216537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  216540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  216552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  216557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  216562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216566 */     GIR_RootConstrainSelectedInstOperands,
     /*  216567 */     // GIR_Coverage, 8707,
     /*  216567 */     GIR_EraseRootFromParent_Done,
     /*  216568 */   // Label 3079: @216568
     /*  216568 */   GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(216634), // Rule ID 8719 //
     /*  216573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  216576 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216588 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216592 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  216596 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  216603 */     // (ld:{ *:[v2f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  216603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  216606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  216618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  216623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  216628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216632 */     GIR_RootConstrainSelectedInstOperands,
     /*  216633 */     // GIR_Coverage, 8719,
     /*  216633 */     GIR_EraseRootFromParent_Done,
     /*  216634 */   // Label 3080: @216634
     /*  216634 */   GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(216696), // Rule ID 8713 //
     /*  216639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  216642 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216654 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  216665 */     // (ld:{ *:[v2i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  216665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  216668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  216680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  216685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  216690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216694 */     GIR_RootConstrainSelectedInstOperands,
     /*  216695 */     // GIR_Coverage, 8713,
     /*  216695 */     GIR_EraseRootFromParent_Done,
     /*  216696 */   // Label 3081: @216696
     /*  216696 */   GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(216758), // Rule ID 8725 //
     /*  216701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  216704 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216716 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  216727 */     // (ld:{ *:[v2f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  216727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  216730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  216742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  216747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  216752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216756 */     GIR_RootConstrainSelectedInstOperands,
     /*  216757 */     // GIR_Coverage, 8725,
     /*  216757 */     GIR_EraseRootFromParent_Done,
     /*  216758 */   // Label 3082: @216758
     /*  216758 */   GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(216817), // Rule ID 8703 //
     /*  216763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  216766 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216778 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216782 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  216786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  216793 */     // (ld:{ *:[v2i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  216793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  216796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216815 */     GIR_RootConstrainSelectedInstOperands,
     /*  216816 */     // GIR_Coverage, 8703,
     /*  216816 */     GIR_EraseRootFromParent_Done,
     /*  216817 */   // Label 3083: @216817
     /*  216817 */   GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(216876), // Rule ID 8704 //
     /*  216822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  216825 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216833 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216837 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216841 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  216845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  216852 */     // (ld:{ *:[v2i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  216852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  216855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216874 */     GIR_RootConstrainSelectedInstOperands,
     /*  216875 */     // GIR_Coverage, 8704,
     /*  216875 */     GIR_EraseRootFromParent_Done,
     /*  216876 */   // Label 3084: @216876
     /*  216876 */   GIM_Try, /*On fail goto*//*Label 3085*/ GIMT_Encode4(216935), // Rule ID 8715 //
     /*  216881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  216884 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216892 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216896 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216900 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  216904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  216911 */     // (ld:{ *:[v2f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  216911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  216914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216933 */     GIR_RootConstrainSelectedInstOperands,
     /*  216934 */     // GIR_Coverage, 8715,
     /*  216934 */     GIR_EraseRootFromParent_Done,
     /*  216935 */   // Label 3085: @216935
     /*  216935 */   GIM_Try, /*On fail goto*//*Label 3086*/ GIMT_Encode4(216994), // Rule ID 8716 //
     /*  216940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  216943 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  216947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  216951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  216955 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  216959 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  216963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  216970 */     // (ld:{ *:[v2f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  216970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  216973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  216975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  216980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  216985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  216988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  216992 */     GIR_RootConstrainSelectedInstOperands,
     /*  216993 */     // GIR_Coverage, 8716,
     /*  216993 */     GIR_EraseRootFromParent_Done,
     /*  216994 */   // Label 3086: @216994
     /*  216994 */   GIM_Try, /*On fail goto*//*Label 3087*/ GIMT_Encode4(217046), // Rule ID 8709 //
     /*  216999 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217011 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  217022 */     // (ld:{ *:[v2i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  217022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  217025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  217037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217044 */     GIR_RootConstrainSelectedInstOperands,
     /*  217045 */     // GIR_Coverage, 8709,
     /*  217045 */     GIR_EraseRootFromParent_Done,
     /*  217046 */   // Label 3087: @217046
     /*  217046 */   GIM_Try, /*On fail goto*//*Label 3088*/ GIMT_Encode4(217101), // Rule ID 8710 //
     /*  217051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  217054 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217066 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217070 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  217077 */     // (ld:{ *:[v2i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  217077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  217080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  217092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217099 */     GIR_RootConstrainSelectedInstOperands,
     /*  217100 */     // GIR_Coverage, 8710,
     /*  217100 */     GIR_EraseRootFromParent_Done,
     /*  217101 */   // Label 3088: @217101
     /*  217101 */   GIM_Try, /*On fail goto*//*Label 3089*/ GIMT_Encode4(217153), // Rule ID 8721 //
     /*  217106 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217118 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217122 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  217129 */     // (ld:{ *:[v2f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  217129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  217132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  217144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217151 */     GIR_RootConstrainSelectedInstOperands,
     /*  217152 */     // GIR_Coverage, 8721,
     /*  217152 */     GIR_EraseRootFromParent_Done,
     /*  217153 */   // Label 3089: @217153
     /*  217153 */   GIM_Try, /*On fail goto*//*Label 3090*/ GIMT_Encode4(217208), // Rule ID 8722 //
     /*  217158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  217161 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217173 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  217184 */     // (ld:{ *:[v2f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  217184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
     /*  217187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  217199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217206 */     GIR_RootConstrainSelectedInstOperands,
     /*  217207 */     // GIR_Coverage, 8722,
     /*  217207 */     GIR_EraseRootFromParent_Done,
     /*  217208 */   // Label 3090: @217208
     /*  217208 */   GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(217267), // Rule ID 8705 //
     /*  217213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  217216 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217228 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217232 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  217236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217243 */     // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  217243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  217246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217265 */     GIR_RootConstrainSelectedInstOperands,
     /*  217266 */     // GIR_Coverage, 8705,
     /*  217266 */     GIR_EraseRootFromParent_Done,
     /*  217267 */   // Label 3091: @217267
     /*  217267 */   GIM_Try, /*On fail goto*//*Label 3092*/ GIMT_Encode4(217331), // Rule ID 8706 //
     /*  217272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  217275 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217287 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217291 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  217295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217302 */     // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  217302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  217305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  217325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217329 */     GIR_RootConstrainSelectedInstOperands,
     /*  217330 */     // GIR_Coverage, 8706,
     /*  217330 */     GIR_EraseRootFromParent_Done,
     /*  217331 */   // Label 3092: @217331
     /*  217331 */   GIM_Try, /*On fail goto*//*Label 3093*/ GIMT_Encode4(217390), // Rule ID 8717 //
     /*  217336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  217339 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217351 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217355 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  217359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217366 */     // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  217366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  217369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217384 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217388 */     GIR_RootConstrainSelectedInstOperands,
     /*  217389 */     // GIR_Coverage, 8717,
     /*  217389 */     GIR_EraseRootFromParent_Done,
     /*  217390 */   // Label 3093: @217390
     /*  217390 */   GIM_Try, /*On fail goto*//*Label 3094*/ GIMT_Encode4(217454), // Rule ID 8718 //
     /*  217395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  217398 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217410 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217414 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  217418 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217425 */     // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  217425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  217428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  217448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217452 */     GIR_RootConstrainSelectedInstOperands,
     /*  217453 */     // GIR_Coverage, 8718,
     /*  217453 */     GIR_EraseRootFromParent_Done,
     /*  217454 */   // Label 3094: @217454
     /*  217454 */   GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(217505), // Rule ID 8708 //
     /*  217459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  217462 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217470 */     // MIs[0] sbase
     /*  217470 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  217474 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  217478 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217482 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  217486 */     // (ld:{ *:[v2i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  217486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  217489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217491 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  217493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217503 */     GIR_RootConstrainSelectedInstOperands,
     /*  217504 */     // GIR_Coverage, 8708,
     /*  217504 */     GIR_EraseRootFromParent_Done,
     /*  217505 */   // Label 3095: @217505
     /*  217505 */   GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(217556), // Rule ID 8720 //
     /*  217510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  217513 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217521 */     // MIs[0] sbase
     /*  217521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  217525 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  217529 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217533 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  217537 */     // (ld:{ *:[v2f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  217537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  217540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217542 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  217544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217550 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217554 */     GIR_RootConstrainSelectedInstOperands,
     /*  217555 */     // GIR_Coverage, 8720,
     /*  217555 */     GIR_EraseRootFromParent_Done,
     /*  217556 */   // Label 3096: @217556
     /*  217556 */   GIM_Try, /*On fail goto*//*Label 3097*/ GIMT_Encode4(217611), // Rule ID 8711 //
     /*  217561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  217564 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217576 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217580 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217587 */     // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  217587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  217590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217605 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217609 */     GIR_RootConstrainSelectedInstOperands,
     /*  217610 */     // GIR_Coverage, 8711,
     /*  217610 */     GIR_EraseRootFromParent_Done,
     /*  217611 */   // Label 3097: @217611
     /*  217611 */   GIM_Try, /*On fail goto*//*Label 3098*/ GIMT_Encode4(217671), // Rule ID 8712 //
     /*  217616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  217619 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217631 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217642 */     // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  217642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  217645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  217665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217669 */     GIR_RootConstrainSelectedInstOperands,
     /*  217670 */     // GIR_Coverage, 8712,
     /*  217670 */     GIR_EraseRootFromParent_Done,
     /*  217671 */   // Label 3098: @217671
     /*  217671 */   GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(217726), // Rule ID 8723 //
     /*  217676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  217679 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217687 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217691 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217702 */     // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  217702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
     /*  217705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217724 */     GIR_RootConstrainSelectedInstOperands,
     /*  217725 */     // GIR_Coverage, 8723,
     /*  217725 */     GIR_EraseRootFromParent_Done,
     /*  217726 */   // Label 3099: @217726
     /*  217726 */   GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(217786), // Rule ID 8724 //
     /*  217731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  217734 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217746 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  217757 */     // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  217757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
     /*  217760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  217767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  217780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217784 */     GIR_RootConstrainSelectedInstOperands,
     /*  217785 */     // GIR_Coverage, 8724,
     /*  217785 */     GIR_EraseRootFromParent_Done,
     /*  217786 */   // Label 3100: @217786
     /*  217786 */   GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(217830), // Rule ID 8714 //
     /*  217791 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217799 */     // MIs[0] sbase
     /*  217799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  217803 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  217807 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217811 */     // (ld:{ *:[v2i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  217811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  217814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217816 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  217818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217828 */     GIR_RootConstrainSelectedInstOperands,
     /*  217829 */     // GIR_Coverage, 8714,
     /*  217829 */     GIR_EraseRootFromParent_Done,
     /*  217830 */   // Label 3101: @217830
     /*  217830 */   GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(217874), // Rule ID 8726 //
     /*  217835 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  217839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  217843 */     // MIs[0] sbase
     /*  217843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  217847 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  217851 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  217855 */     // (ld:{ *:[v2f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  217855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
     /*  217858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  217860 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  217862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217872 */     GIR_RootConstrainSelectedInstOperands,
     /*  217873 */     // GIR_Coverage, 8726,
     /*  217873 */     GIR_EraseRootFromParent_Done,
     /*  217874 */   // Label 3102: @217874
     /*  217874 */   GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(217934), // Rule ID 25216 //
     /*  217879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  217882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  217887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  217891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  217902 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  217902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  217905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  217907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  217912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  217922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217932 */     GIR_RootConstrainSelectedInstOperands,
     /*  217933 */     // GIR_Coverage, 25216,
     /*  217933 */     GIR_EraseRootFromParent_Done,
     /*  217934 */   // Label 3103: @217934
     /*  217934 */   GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(217994), // Rule ID 25217 //
     /*  217939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  217942 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  217947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  217951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  217955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  217962 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  217962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  217965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  217967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  217972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  217977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  217982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  217988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  217992 */     GIR_RootConstrainSelectedInstOperands,
     /*  217993 */     // GIR_Coverage, 25217,
     /*  217993 */     GIR_EraseRootFromParent_Done,
     /*  217994 */   // Label 3104: @217994
     /*  217994 */   GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(218054), // Rule ID 25218 //
     /*  217999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  218002 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218022 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218052 */     GIR_RootConstrainSelectedInstOperands,
     /*  218053 */     // GIR_Coverage, 25218,
     /*  218053 */     GIR_EraseRootFromParent_Done,
     /*  218054 */   // Label 3105: @218054
     /*  218054 */   GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(218114), // Rule ID 25219 //
     /*  218059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  218062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218082 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218112 */     GIR_RootConstrainSelectedInstOperands,
     /*  218113 */     // GIR_Coverage, 25219,
     /*  218113 */     GIR_EraseRootFromParent_Done,
     /*  218114 */   // Label 3106: @218114
     /*  218114 */   GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(218174), // Rule ID 25220 //
     /*  218119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  218122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218142 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218172 */     GIR_RootConstrainSelectedInstOperands,
     /*  218173 */     // GIR_Coverage, 25220,
     /*  218173 */     GIR_EraseRootFromParent_Done,
     /*  218174 */   // Label 3107: @218174
     /*  218174 */   GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(218234), // Rule ID 25226 //
     /*  218179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  218182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218202 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218232 */     GIR_RootConstrainSelectedInstOperands,
     /*  218233 */     // GIR_Coverage, 25226,
     /*  218233 */     GIR_EraseRootFromParent_Done,
     /*  218234 */   // Label 3108: @218234
     /*  218234 */   GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(218294), // Rule ID 25227 //
     /*  218239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  218242 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218262 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218282 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218292 */     GIR_RootConstrainSelectedInstOperands,
     /*  218293 */     // GIR_Coverage, 25227,
     /*  218293 */     GIR_EraseRootFromParent_Done,
     /*  218294 */   // Label 3109: @218294
     /*  218294 */   GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(218354), // Rule ID 25228 //
     /*  218299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  218302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218322 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218352 */     GIR_RootConstrainSelectedInstOperands,
     /*  218353 */     // GIR_Coverage, 25228,
     /*  218353 */     GIR_EraseRootFromParent_Done,
     /*  218354 */   // Label 3110: @218354
     /*  218354 */   GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(218414), // Rule ID 25229 //
     /*  218359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  218362 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218382 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218412 */     GIR_RootConstrainSelectedInstOperands,
     /*  218413 */     // GIR_Coverage, 25229,
     /*  218413 */     GIR_EraseRootFromParent_Done,
     /*  218414 */   // Label 3111: @218414
     /*  218414 */   GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(218474), // Rule ID 25230 //
     /*  218419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  218422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218442 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218472 */     GIR_RootConstrainSelectedInstOperands,
     /*  218473 */     // GIR_Coverage, 25230,
     /*  218473 */     GIR_EraseRootFromParent_Done,
     /*  218474 */   // Label 3112: @218474
     /*  218474 */   GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(218534), // Rule ID 25236 //
     /*  218479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  218482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218502 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218532 */     GIR_RootConstrainSelectedInstOperands,
     /*  218533 */     // GIR_Coverage, 25236,
     /*  218533 */     GIR_EraseRootFromParent_Done,
     /*  218534 */   // Label 3113: @218534
     /*  218534 */   GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(218594), // Rule ID 25237 //
     /*  218539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  218542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218562 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218592 */     GIR_RootConstrainSelectedInstOperands,
     /*  218593 */     // GIR_Coverage, 25237,
     /*  218593 */     GIR_EraseRootFromParent_Done,
     /*  218594 */   // Label 3114: @218594
     /*  218594 */   GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(218654), // Rule ID 25238 //
     /*  218599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  218602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218622 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218652 */     GIR_RootConstrainSelectedInstOperands,
     /*  218653 */     // GIR_Coverage, 25238,
     /*  218653 */     GIR_EraseRootFromParent_Done,
     /*  218654 */   // Label 3115: @218654
     /*  218654 */   GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(218714), // Rule ID 25239 //
     /*  218659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  218662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218682 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218708 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218712 */     GIR_RootConstrainSelectedInstOperands,
     /*  218713 */     // GIR_Coverage, 25239,
     /*  218713 */     GIR_EraseRootFromParent_Done,
     /*  218714 */   // Label 3116: @218714
     /*  218714 */   GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(218774), // Rule ID 25240 //
     /*  218719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  218722 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218731 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218735 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218742 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  218745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218772 */     GIR_RootConstrainSelectedInstOperands,
     /*  218773 */     // GIR_Coverage, 25240,
     /*  218773 */     GIR_EraseRootFromParent_Done,
     /*  218774 */   // Label 3117: @218774
     /*  218774 */   GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(218834), // Rule ID 25246 //
     /*  218779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  218782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218802 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218832 */     GIR_RootConstrainSelectedInstOperands,
     /*  218833 */     // GIR_Coverage, 25246,
     /*  218833 */     GIR_EraseRootFromParent_Done,
     /*  218834 */   // Label 3118: @218834
     /*  218834 */   GIM_Try, /*On fail goto*//*Label 3119*/ GIMT_Encode4(218894), // Rule ID 25247 //
     /*  218839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  218842 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218862 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218892 */     GIR_RootConstrainSelectedInstOperands,
     /*  218893 */     // GIR_Coverage, 25247,
     /*  218893 */     GIR_EraseRootFromParent_Done,
     /*  218894 */   // Label 3119: @218894
     /*  218894 */   GIM_Try, /*On fail goto*//*Label 3120*/ GIMT_Encode4(218954), // Rule ID 25248 //
     /*  218899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  218902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218922 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  218942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  218948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  218952 */     GIR_RootConstrainSelectedInstOperands,
     /*  218953 */     // GIR_Coverage, 25248,
     /*  218953 */     GIR_EraseRootFromParent_Done,
     /*  218954 */   // Label 3120: @218954
     /*  218954 */   GIM_Try, /*On fail goto*//*Label 3121*/ GIMT_Encode4(219014), // Rule ID 25249 //
     /*  218959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  218962 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  218967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  218971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  218975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  218982 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  218982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  218985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  218987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  218992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  218997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219012 */     GIR_RootConstrainSelectedInstOperands,
     /*  219013 */     // GIR_Coverage, 25249,
     /*  219013 */     GIR_EraseRootFromParent_Done,
     /*  219014 */   // Label 3121: @219014
     /*  219014 */   GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(219074), // Rule ID 25250 //
     /*  219019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  219022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  219042 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  219042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  219045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  219047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  219052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  219057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219072 */     GIR_RootConstrainSelectedInstOperands,
     /*  219073 */     // GIR_Coverage, 25250,
     /*  219073 */     GIR_EraseRootFromParent_Done,
     /*  219074 */   // Label 3122: @219074
     /*  219074 */   GIM_Try, /*On fail goto*//*Label 3123*/ GIMT_Encode4(219133), // Rule ID 14122 //
     /*  219079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  219082 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219091 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219102 */     // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219131 */     GIR_RootConstrainSelectedInstOperands,
     /*  219132 */     // GIR_Coverage, 14122,
     /*  219132 */     GIR_EraseRootFromParent_Done,
     /*  219133 */   // Label 3123: @219133
     /*  219133 */   GIM_Try, /*On fail goto*//*Label 3124*/ GIMT_Encode4(219192), // Rule ID 14123 //
     /*  219138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  219141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219161 */     // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219190 */     GIR_RootConstrainSelectedInstOperands,
     /*  219191 */     // GIR_Coverage, 14123,
     /*  219191 */     GIR_EraseRootFromParent_Done,
     /*  219192 */   // Label 3124: @219192
     /*  219192 */   GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(219251), // Rule ID 14124 //
     /*  219197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  219200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219209 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219220 */     // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219245 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219249 */     GIR_RootConstrainSelectedInstOperands,
     /*  219250 */     // GIR_Coverage, 14124,
     /*  219250 */     GIR_EraseRootFromParent_Done,
     /*  219251 */   // Label 3125: @219251
     /*  219251 */   GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(219310), // Rule ID 14125 //
     /*  219256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  219259 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219279 */     // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219308 */     GIR_RootConstrainSelectedInstOperands,
     /*  219309 */     // GIR_Coverage, 14125,
     /*  219309 */     GIR_EraseRootFromParent_Done,
     /*  219310 */   // Label 3126: @219310
     /*  219310 */   GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(219369), // Rule ID 14126 //
     /*  219315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  219318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219338 */     // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219367 */     GIR_RootConstrainSelectedInstOperands,
     /*  219368 */     // GIR_Coverage, 14126,
     /*  219368 */     GIR_EraseRootFromParent_Done,
     /*  219369 */   // Label 3127: @219369
     /*  219369 */   GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(219428), // Rule ID 14152 //
     /*  219374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  219377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219397 */     // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219426 */     GIR_RootConstrainSelectedInstOperands,
     /*  219427 */     // GIR_Coverage, 14152,
     /*  219427 */     GIR_EraseRootFromParent_Done,
     /*  219428 */   // Label 3128: @219428
     /*  219428 */   GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(219487), // Rule ID 14153 //
     /*  219433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  219436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219445 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219456 */     // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219485 */     GIR_RootConstrainSelectedInstOperands,
     /*  219486 */     // GIR_Coverage, 14153,
     /*  219486 */     GIR_EraseRootFromParent_Done,
     /*  219487 */   // Label 3129: @219487
     /*  219487 */   GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(219546), // Rule ID 14154 //
     /*  219492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  219495 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219515 */     // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219544 */     GIR_RootConstrainSelectedInstOperands,
     /*  219545 */     // GIR_Coverage, 14154,
     /*  219545 */     GIR_EraseRootFromParent_Done,
     /*  219546 */   // Label 3130: @219546
     /*  219546 */   GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(219605), // Rule ID 14155 //
     /*  219551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  219554 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219574 */     // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219599 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219603 */     GIR_RootConstrainSelectedInstOperands,
     /*  219604 */     // GIR_Coverage, 14155,
     /*  219604 */     GIR_EraseRootFromParent_Done,
     /*  219605 */   // Label 3131: @219605
     /*  219605 */   GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(219664), // Rule ID 14156 //
     /*  219610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  219613 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219626 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  219633 */     // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  219633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
     /*  219636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  219643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  219648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  219653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  219658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219662 */     GIR_RootConstrainSelectedInstOperands,
     /*  219663 */     // GIR_Coverage, 14156,
     /*  219663 */     GIR_EraseRootFromParent_Done,
     /*  219664 */   // Label 3132: @219664
     /*  219664 */   GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(219716), // Rule ID 14117 //
     /*  219669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  219672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  219692 */     // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  219692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  219695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  219702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  219707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219714 */     GIR_RootConstrainSelectedInstOperands,
     /*  219715 */     // GIR_Coverage, 14117,
     /*  219715 */     GIR_EraseRootFromParent_Done,
     /*  219716 */   // Label 3133: @219716
     /*  219716 */   GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(219768), // Rule ID 14118 //
     /*  219721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  219724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  219744 */     // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  219744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  219747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  219754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  219759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219766 */     GIR_RootConstrainSelectedInstOperands,
     /*  219767 */     // GIR_Coverage, 14118,
     /*  219767 */     GIR_EraseRootFromParent_Done,
     /*  219768 */   // Label 3134: @219768
     /*  219768 */   GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(219820), // Rule ID 14119 //
     /*  219773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  219776 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219785 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219789 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  219796 */     // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  219796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  219799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  219806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  219811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219818 */     GIR_RootConstrainSelectedInstOperands,
     /*  219819 */     // GIR_Coverage, 14119,
     /*  219819 */     GIR_EraseRootFromParent_Done,
     /*  219820 */   // Label 3135: @219820
     /*  219820 */   GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(219872), // Rule ID 14120 //
     /*  219825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  219828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  219848 */     // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  219848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  219851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  219858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  219863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219870 */     GIR_RootConstrainSelectedInstOperands,
     /*  219871 */     // GIR_Coverage, 14120,
     /*  219871 */     GIR_EraseRootFromParent_Done,
     /*  219872 */   // Label 3136: @219872
     /*  219872 */   GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(219924), // Rule ID 14121 //
     /*  219877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  219880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  219900 */     // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  219900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  219903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  219910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  219915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219918 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219922 */     GIR_RootConstrainSelectedInstOperands,
     /*  219923 */     // GIR_Coverage, 14121,
     /*  219923 */     GIR_EraseRootFromParent_Done,
     /*  219924 */   // Label 3137: @219924
     /*  219924 */   GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(219976), // Rule ID 14147 //
     /*  219929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  219932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  219952 */     // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  219952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  219955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  219957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  219962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  219967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  219970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  219974 */     GIR_RootConstrainSelectedInstOperands,
     /*  219975 */     // GIR_Coverage, 14147,
     /*  219975 */     GIR_EraseRootFromParent_Done,
     /*  219976 */   // Label 3138: @219976
     /*  219976 */   GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(220028), // Rule ID 14148 //
     /*  219981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  219984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  219989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  219993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  219997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  220004 */     // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  220004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  220007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  220014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220026 */     GIR_RootConstrainSelectedInstOperands,
     /*  220027 */     // GIR_Coverage, 14148,
     /*  220027 */     GIR_EraseRootFromParent_Done,
     /*  220028 */   // Label 3139: @220028
     /*  220028 */   GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(220080), // Rule ID 14149 //
     /*  220033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  220036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  220056 */     // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  220056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  220059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  220066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220078 */     GIR_RootConstrainSelectedInstOperands,
     /*  220079 */     // GIR_Coverage, 14149,
     /*  220079 */     GIR_EraseRootFromParent_Done,
     /*  220080 */   // Label 3140: @220080
     /*  220080 */   GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(220132), // Rule ID 14150 //
     /*  220085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  220088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220101 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  220108 */     // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  220108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  220111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  220118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220130 */     GIR_RootConstrainSelectedInstOperands,
     /*  220131 */     // GIR_Coverage, 14150,
     /*  220131 */     GIR_EraseRootFromParent_Done,
     /*  220132 */   // Label 3141: @220132
     /*  220132 */   GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(220184), // Rule ID 14151 //
     /*  220137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  220140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  220160 */     // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  220160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
     /*  220163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  220170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220182 */     GIR_RootConstrainSelectedInstOperands,
     /*  220183 */     // GIR_Coverage, 14151,
     /*  220183 */     GIR_EraseRootFromParent_Done,
     /*  220184 */   // Label 3142: @220184
     /*  220184 */   GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(220236), // Rule ID 14112 //
     /*  220189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  220192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220212 */     // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220234 */     GIR_RootConstrainSelectedInstOperands,
     /*  220235 */     // GIR_Coverage, 14112,
     /*  220235 */     GIR_EraseRootFromParent_Done,
     /*  220236 */   // Label 3143: @220236
     /*  220236 */   GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(220288), // Rule ID 14113 //
     /*  220241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  220244 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220264 */     // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220286 */     GIR_RootConstrainSelectedInstOperands,
     /*  220287 */     // GIR_Coverage, 14113,
     /*  220287 */     GIR_EraseRootFromParent_Done,
     /*  220288 */   // Label 3144: @220288
     /*  220288 */   GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(220340), // Rule ID 14114 //
     /*  220293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  220296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220316 */     // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220338 */     GIR_RootConstrainSelectedInstOperands,
     /*  220339 */     // GIR_Coverage, 14114,
     /*  220339 */     GIR_EraseRootFromParent_Done,
     /*  220340 */   // Label 3145: @220340
     /*  220340 */   GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(220392), // Rule ID 14115 //
     /*  220345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  220348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220368 */     // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220390 */     GIR_RootConstrainSelectedInstOperands,
     /*  220391 */     // GIR_Coverage, 14115,
     /*  220391 */     GIR_EraseRootFromParent_Done,
     /*  220392 */   // Label 3146: @220392
     /*  220392 */   GIM_Try, /*On fail goto*//*Label 3147*/ GIMT_Encode4(220444), // Rule ID 14116 //
     /*  220397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  220400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220409 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220420 */     // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220442 */     GIR_RootConstrainSelectedInstOperands,
     /*  220443 */     // GIR_Coverage, 14116,
     /*  220443 */     GIR_EraseRootFromParent_Done,
     /*  220444 */   // Label 3147: @220444
     /*  220444 */   GIM_Try, /*On fail goto*//*Label 3148*/ GIMT_Encode4(220496), // Rule ID 14142 //
     /*  220449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  220452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220472 */     // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220494 */     GIR_RootConstrainSelectedInstOperands,
     /*  220495 */     // GIR_Coverage, 14142,
     /*  220495 */     GIR_EraseRootFromParent_Done,
     /*  220496 */   // Label 3148: @220496
     /*  220496 */   GIM_Try, /*On fail goto*//*Label 3149*/ GIMT_Encode4(220548), // Rule ID 14143 //
     /*  220501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  220504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220524 */     // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220546 */     GIR_RootConstrainSelectedInstOperands,
     /*  220547 */     // GIR_Coverage, 14143,
     /*  220547 */     GIR_EraseRootFromParent_Done,
     /*  220548 */   // Label 3149: @220548
     /*  220548 */   GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(220600), // Rule ID 14144 //
     /*  220553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  220556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220576 */     // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220598 */     GIR_RootConstrainSelectedInstOperands,
     /*  220599 */     // GIR_Coverage, 14144,
     /*  220599 */     GIR_EraseRootFromParent_Done,
     /*  220600 */   // Label 3150: @220600
     /*  220600 */   GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(220652), // Rule ID 14145 //
     /*  220605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  220608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220628 */     // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220650 */     GIR_RootConstrainSelectedInstOperands,
     /*  220651 */     // GIR_Coverage, 14145,
     /*  220651 */     GIR_EraseRootFromParent_Done,
     /*  220652 */   // Label 3151: @220652
     /*  220652 */   GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(220704), // Rule ID 14146 //
     /*  220657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  220660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  220665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220673 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  220680 */     // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  220680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
     /*  220683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  220685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  220690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  220695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220702 */     GIR_RootConstrainSelectedInstOperands,
     /*  220703 */     // GIR_Coverage, 14146,
     /*  220703 */     GIR_EraseRootFromParent_Done,
     /*  220704 */   // Label 3152: @220704
     /*  220704 */   GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(220771), // Rule ID 15408 //
     /*  220709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  220712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  220719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220723 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  220734 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  220734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  220737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  220739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  220744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  220749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  220754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  220759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220769 */     GIR_RootConstrainSelectedInstOperands,
     /*  220770 */     // GIR_Coverage, 15408,
     /*  220770 */     GIR_EraseRootFromParent_Done,
     /*  220771 */   // Label 3153: @220771
     /*  220771 */   GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(220838), // Rule ID 15409 //
     /*  220776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  220779 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  220786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  220801 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  220801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  220804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  220806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  220811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  220816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  220821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  220826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220836 */     GIR_RootConstrainSelectedInstOperands,
     /*  220837 */     // GIR_Coverage, 15409,
     /*  220837 */     GIR_EraseRootFromParent_Done,
     /*  220838 */   // Label 3154: @220838
     /*  220838 */   GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(220905), // Rule ID 15410 //
     /*  220843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  220846 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  220853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220857 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220861 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  220868 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  220868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  220871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  220873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  220878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  220883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  220888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  220893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220903 */     GIR_RootConstrainSelectedInstOperands,
     /*  220904 */     // GIR_Coverage, 15410,
     /*  220904 */     GIR_EraseRootFromParent_Done,
     /*  220905 */   // Label 3155: @220905
     /*  220905 */   GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(220972), // Rule ID 15411 //
     /*  220910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  220913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  220920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  220935 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  220935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  220938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  220940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  220945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  220950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  220955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  220960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  220966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  220970 */     GIR_RootConstrainSelectedInstOperands,
     /*  220971 */     // GIR_Coverage, 15411,
     /*  220971 */     GIR_EraseRootFromParent_Done,
     /*  220972 */   // Label 3156: @220972
     /*  220972 */   GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(221039), // Rule ID 15412 //
     /*  220977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  220980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  220987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  220991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  220995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221002 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  221005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221033 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221037 */     GIR_RootConstrainSelectedInstOperands,
     /*  221038 */     // GIR_Coverage, 15412,
     /*  221038 */     GIR_EraseRootFromParent_Done,
     /*  221039 */   // Label 3157: @221039
     /*  221039 */   GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(221106), // Rule ID 15418 //
     /*  221044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  221047 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221058 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221062 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221069 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221104 */     GIR_RootConstrainSelectedInstOperands,
     /*  221105 */     // GIR_Coverage, 15418,
     /*  221105 */     GIR_EraseRootFromParent_Done,
     /*  221106 */   // Label 3158: @221106
     /*  221106 */   GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(221173), // Rule ID 15419 //
     /*  221111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  221114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221136 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221171 */     GIR_RootConstrainSelectedInstOperands,
     /*  221172 */     // GIR_Coverage, 15419,
     /*  221172 */     GIR_EraseRootFromParent_Done,
     /*  221173 */   // Label 3159: @221173
     /*  221173 */   GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(221240), // Rule ID 15420 //
     /*  221178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  221181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221203 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221238 */     GIR_RootConstrainSelectedInstOperands,
     /*  221239 */     // GIR_Coverage, 15420,
     /*  221239 */     GIR_EraseRootFromParent_Done,
     /*  221240 */   // Label 3160: @221240
     /*  221240 */   GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(221307), // Rule ID 15421 //
     /*  221245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  221248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221270 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221305 */     GIR_RootConstrainSelectedInstOperands,
     /*  221306 */     // GIR_Coverage, 15421,
     /*  221306 */     GIR_EraseRootFromParent_Done,
     /*  221307 */   // Label 3161: @221307
     /*  221307 */   GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(221374), // Rule ID 15422 //
     /*  221312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  221315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221326 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221337 */     // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221372 */     GIR_RootConstrainSelectedInstOperands,
     /*  221373 */     // GIR_Coverage, 15422,
     /*  221373 */     GIR_EraseRootFromParent_Done,
     /*  221374 */   // Label 3162: @221374
     /*  221374 */   GIM_Try, /*On fail goto*//*Label 3163*/ GIMT_Encode4(221441), // Rule ID 15428 //
     /*  221379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  221382 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221404 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  221407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221439 */     GIR_RootConstrainSelectedInstOperands,
     /*  221440 */     // GIR_Coverage, 15428,
     /*  221440 */     GIR_EraseRootFromParent_Done,
     /*  221441 */   // Label 3163: @221441
     /*  221441 */   GIM_Try, /*On fail goto*//*Label 3164*/ GIMT_Encode4(221508), // Rule ID 15429 //
     /*  221446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  221449 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221460 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221471 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  221474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221506 */     GIR_RootConstrainSelectedInstOperands,
     /*  221507 */     // GIR_Coverage, 15429,
     /*  221507 */     GIR_EraseRootFromParent_Done,
     /*  221508 */   // Label 3164: @221508
     /*  221508 */   GIM_Try, /*On fail goto*//*Label 3165*/ GIMT_Encode4(221575), // Rule ID 15430 //
     /*  221513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  221516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221538 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  221541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221569 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221573 */     GIR_RootConstrainSelectedInstOperands,
     /*  221574 */     // GIR_Coverage, 15430,
     /*  221574 */     GIR_EraseRootFromParent_Done,
     /*  221575 */   // Label 3165: @221575
     /*  221575 */   GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(221642), // Rule ID 15431 //
     /*  221580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  221583 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221605 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  221608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221640 */     GIR_RootConstrainSelectedInstOperands,
     /*  221641 */     // GIR_Coverage, 15431,
     /*  221641 */     GIR_EraseRootFromParent_Done,
     /*  221642 */   // Label 3166: @221642
     /*  221642 */   GIM_Try, /*On fail goto*//*Label 3167*/ GIMT_Encode4(221709), // Rule ID 15432 //
     /*  221647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  221650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221672 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
     /*  221675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221703 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221707 */     GIR_RootConstrainSelectedInstOperands,
     /*  221708 */     // GIR_Coverage, 15432,
     /*  221708 */     GIR_EraseRootFromParent_Done,
     /*  221709 */   // Label 3167: @221709
     /*  221709 */   GIM_Try, /*On fail goto*//*Label 3168*/ GIMT_Encode4(221776), // Rule ID 15438 //
     /*  221714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  221717 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221728 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221732 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221739 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221774 */     GIR_RootConstrainSelectedInstOperands,
     /*  221775 */     // GIR_Coverage, 15438,
     /*  221775 */     GIR_EraseRootFromParent_Done,
     /*  221776 */   // Label 3168: @221776
     /*  221776 */   GIM_Try, /*On fail goto*//*Label 3169*/ GIMT_Encode4(221843), // Rule ID 15439 //
     /*  221781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  221784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221799 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221806 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221837 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221841 */     GIR_RootConstrainSelectedInstOperands,
     /*  221842 */     // GIR_Coverage, 15439,
     /*  221842 */     GIR_EraseRootFromParent_Done,
     /*  221843 */   // Label 3169: @221843
     /*  221843 */   GIM_Try, /*On fail goto*//*Label 3170*/ GIMT_Encode4(221910), // Rule ID 15440 //
     /*  221848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  221851 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221873 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221908 */     GIR_RootConstrainSelectedInstOperands,
     /*  221909 */     // GIR_Coverage, 15440,
     /*  221909 */     GIR_EraseRootFromParent_Done,
     /*  221910 */   // Label 3170: @221910
     /*  221910 */   GIM_Try, /*On fail goto*//*Label 3171*/ GIMT_Encode4(221977), // Rule ID 15441 //
     /*  221915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  221918 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  221933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  221940 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  221940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  221943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  221945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  221950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  221955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  221960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  221965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  221971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  221975 */     GIR_RootConstrainSelectedInstOperands,
     /*  221976 */     // GIR_Coverage, 15441,
     /*  221976 */     GIR_EraseRootFromParent_Done,
     /*  221977 */   // Label 3171: @221977
     /*  221977 */   GIM_Try, /*On fail goto*//*Label 3172*/ GIMT_Encode4(222044), // Rule ID 15442 //
     /*  221982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  221985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  221992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  221996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222000 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  222007 */     // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  222007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
     /*  222010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222042 */     GIR_RootConstrainSelectedInstOperands,
     /*  222043 */     // GIR_Coverage, 15442,
     /*  222043 */     GIR_EraseRootFromParent_Done,
     /*  222044 */   // Label 3172: @222044
     /*  222044 */   GIM_Try, /*On fail goto*//*Label 3173*/ GIMT_Encode4(222109), // Rule ID 25211 //
     /*  222049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  222052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222072 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222107 */     GIR_RootConstrainSelectedInstOperands,
     /*  222108 */     // GIR_Coverage, 25211,
     /*  222108 */     GIR_EraseRootFromParent_Done,
     /*  222109 */   // Label 3173: @222109
     /*  222109 */   GIM_Try, /*On fail goto*//*Label 3174*/ GIMT_Encode4(222174), // Rule ID 25212 //
     /*  222114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  222117 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222137 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222172 */     GIR_RootConstrainSelectedInstOperands,
     /*  222173 */     // GIR_Coverage, 25212,
     /*  222173 */     GIR_EraseRootFromParent_Done,
     /*  222174 */   // Label 3174: @222174
     /*  222174 */   GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(222239), // Rule ID 25213 //
     /*  222179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  222182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222202 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222237 */     GIR_RootConstrainSelectedInstOperands,
     /*  222238 */     // GIR_Coverage, 25213,
     /*  222238 */     GIR_EraseRootFromParent_Done,
     /*  222239 */   // Label 3175: @222239
     /*  222239 */   GIM_Try, /*On fail goto*//*Label 3176*/ GIMT_Encode4(222304), // Rule ID 25214 //
     /*  222244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  222247 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222267 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222302 */     GIR_RootConstrainSelectedInstOperands,
     /*  222303 */     // GIR_Coverage, 25214,
     /*  222303 */     GIR_EraseRootFromParent_Done,
     /*  222304 */   // Label 3176: @222304
     /*  222304 */   GIM_Try, /*On fail goto*//*Label 3177*/ GIMT_Encode4(222369), // Rule ID 25215 //
     /*  222309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  222312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222332 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222367 */     GIR_RootConstrainSelectedInstOperands,
     /*  222368 */     // GIR_Coverage, 25215,
     /*  222368 */     GIR_EraseRootFromParent_Done,
     /*  222369 */   // Label 3177: @222369
     /*  222369 */   GIM_Try, /*On fail goto*//*Label 3178*/ GIMT_Encode4(222434), // Rule ID 25221 //
     /*  222374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  222377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222397 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  222400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222432 */     GIR_RootConstrainSelectedInstOperands,
     /*  222433 */     // GIR_Coverage, 25221,
     /*  222433 */     GIR_EraseRootFromParent_Done,
     /*  222434 */   // Label 3178: @222434
     /*  222434 */   GIM_Try, /*On fail goto*//*Label 3179*/ GIMT_Encode4(222499), // Rule ID 25222 //
     /*  222439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  222442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222462 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  222465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222497 */     GIR_RootConstrainSelectedInstOperands,
     /*  222498 */     // GIR_Coverage, 25222,
     /*  222498 */     GIR_EraseRootFromParent_Done,
     /*  222499 */   // Label 3179: @222499
     /*  222499 */   GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(222564), // Rule ID 25223 //
     /*  222504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  222507 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222527 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  222530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222562 */     GIR_RootConstrainSelectedInstOperands,
     /*  222563 */     // GIR_Coverage, 25223,
     /*  222563 */     GIR_EraseRootFromParent_Done,
     /*  222564 */   // Label 3180: @222564
     /*  222564 */   GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(222629), // Rule ID 25224 //
     /*  222569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  222572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222592 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  222595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222627 */     GIR_RootConstrainSelectedInstOperands,
     /*  222628 */     // GIR_Coverage, 25224,
     /*  222628 */     GIR_EraseRootFromParent_Done,
     /*  222629 */   // Label 3181: @222629
     /*  222629 */   GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(222694), // Rule ID 25225 //
     /*  222634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  222637 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222657 */     // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  222660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222685 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222692 */     GIR_RootConstrainSelectedInstOperands,
     /*  222693 */     // GIR_Coverage, 25225,
     /*  222693 */     GIR_EraseRootFromParent_Done,
     /*  222694 */   // Label 3182: @222694
     /*  222694 */   GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(222759), // Rule ID 25231 //
     /*  222699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  222702 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222722 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222757 */     GIR_RootConstrainSelectedInstOperands,
     /*  222758 */     // GIR_Coverage, 25231,
     /*  222758 */     GIR_EraseRootFromParent_Done,
     /*  222759 */   // Label 3183: @222759
     /*  222759 */   GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(222824), // Rule ID 25232 //
     /*  222764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  222767 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222787 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222822 */     GIR_RootConstrainSelectedInstOperands,
     /*  222823 */     // GIR_Coverage, 25232,
     /*  222823 */     GIR_EraseRootFromParent_Done,
     /*  222824 */   // Label 3184: @222824
     /*  222824 */   GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(222889), // Rule ID 25233 //
     /*  222829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  222832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222852 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222887 */     GIR_RootConstrainSelectedInstOperands,
     /*  222888 */     // GIR_Coverage, 25233,
     /*  222888 */     GIR_EraseRootFromParent_Done,
     /*  222889 */   // Label 3185: @222889
     /*  222889 */   GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(222954), // Rule ID 25234 //
     /*  222894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  222897 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222906 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222910 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222917 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  222937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  222942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  222948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  222952 */     GIR_RootConstrainSelectedInstOperands,
     /*  222953 */     // GIR_Coverage, 25234,
     /*  222953 */     GIR_EraseRootFromParent_Done,
     /*  222954 */   // Label 3186: @222954
     /*  222954 */   GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(223019), // Rule ID 25235 //
     /*  222959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  222962 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  222967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  222971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  222975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  222982 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  222982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
     /*  222985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  222987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  222992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  222997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  223002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  223007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223017 */     GIR_RootConstrainSelectedInstOperands,
     /*  223018 */     // GIR_Coverage, 25235,
     /*  223018 */     GIR_EraseRootFromParent_Done,
     /*  223019 */   // Label 3187: @223019
     /*  223019 */   GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(223084), // Rule ID 25241 //
     /*  223024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  223027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  223032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  223047 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  223047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  223050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  223057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  223067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  223072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223082 */     GIR_RootConstrainSelectedInstOperands,
     /*  223083 */     // GIR_Coverage, 25241,
     /*  223083 */     GIR_EraseRootFromParent_Done,
     /*  223084 */   // Label 3188: @223084
     /*  223084 */   GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(223149), // Rule ID 25242 //
     /*  223089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  223092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  223097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  223112 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  223112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  223115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  223122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  223132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  223137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223147 */     GIR_RootConstrainSelectedInstOperands,
     /*  223148 */     // GIR_Coverage, 25242,
     /*  223148 */     GIR_EraseRootFromParent_Done,
     /*  223149 */   // Label 3189: @223149
     /*  223149 */   GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(223214), // Rule ID 25243 //
     /*  223154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  223157 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  223162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  223177 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  223177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  223180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  223187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  223197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  223202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223212 */     GIR_RootConstrainSelectedInstOperands,
     /*  223213 */     // GIR_Coverage, 25243,
     /*  223213 */     GIR_EraseRootFromParent_Done,
     /*  223214 */   // Label 3190: @223214
     /*  223214 */   GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(223279), // Rule ID 25244 //
     /*  223219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  223222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  223227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  223242 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  223242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  223245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  223252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  223262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  223267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223277 */     GIR_RootConstrainSelectedInstOperands,
     /*  223278 */     // GIR_Coverage, 25244,
     /*  223278 */     GIR_EraseRootFromParent_Done,
     /*  223279 */   // Label 3191: @223279
     /*  223279 */   GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(223344), // Rule ID 25245 //
     /*  223284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  223287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  223292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  223307 */     // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  223307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
     /*  223310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  223317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  223327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  223332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223342 */     GIR_RootConstrainSelectedInstOperands,
     /*  223343 */     // GIR_Coverage, 25245,
     /*  223343 */     GIR_EraseRootFromParent_Done,
     /*  223344 */   // Label 3192: @223344
     /*  223344 */   GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(223406), // Rule ID 15403 //
     /*  223349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  223352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223374 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  223377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223404 */     GIR_RootConstrainSelectedInstOperands,
     /*  223405 */     // GIR_Coverage, 15403,
     /*  223405 */     GIR_EraseRootFromParent_Done,
     /*  223406 */   // Label 3193: @223406
     /*  223406 */   GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(223468), // Rule ID 15404 //
     /*  223411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  223414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223436 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  223439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223466 */     GIR_RootConstrainSelectedInstOperands,
     /*  223467 */     // GIR_Coverage, 15404,
     /*  223467 */     GIR_EraseRootFromParent_Done,
     /*  223468 */   // Label 3194: @223468
     /*  223468 */   GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(223530), // Rule ID 15405 //
     /*  223473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  223476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223498 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  223501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223528 */     GIR_RootConstrainSelectedInstOperands,
     /*  223529 */     // GIR_Coverage, 15405,
     /*  223529 */     GIR_EraseRootFromParent_Done,
     /*  223530 */   // Label 3195: @223530
     /*  223530 */   GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(223592), // Rule ID 15406 //
     /*  223535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  223538 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223560 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  223563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223590 */     GIR_RootConstrainSelectedInstOperands,
     /*  223591 */     // GIR_Coverage, 15406,
     /*  223591 */     GIR_EraseRootFromParent_Done,
     /*  223592 */   // Label 3196: @223592
     /*  223592 */   GIM_Try, /*On fail goto*//*Label 3197*/ GIMT_Encode4(223654), // Rule ID 15407 //
     /*  223597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  223600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223622 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  223625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223652 */     GIR_RootConstrainSelectedInstOperands,
     /*  223653 */     // GIR_Coverage, 15407,
     /*  223653 */     GIR_EraseRootFromParent_Done,
     /*  223654 */   // Label 3197: @223654
     /*  223654 */   GIM_Try, /*On fail goto*//*Label 3198*/ GIMT_Encode4(223716), // Rule ID 15413 //
     /*  223659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  223662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223684 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  223687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223714 */     GIR_RootConstrainSelectedInstOperands,
     /*  223715 */     // GIR_Coverage, 15413,
     /*  223715 */     GIR_EraseRootFromParent_Done,
     /*  223716 */   // Label 3198: @223716
     /*  223716 */   GIM_Try, /*On fail goto*//*Label 3199*/ GIMT_Encode4(223778), // Rule ID 15414 //
     /*  223721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  223724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223735 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223746 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  223749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223766 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223776 */     GIR_RootConstrainSelectedInstOperands,
     /*  223777 */     // GIR_Coverage, 15414,
     /*  223777 */     GIR_EraseRootFromParent_Done,
     /*  223778 */   // Label 3199: @223778
     /*  223778 */   GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(223840), // Rule ID 15415 //
     /*  223783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  223786 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223797 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223808 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  223811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223838 */     GIR_RootConstrainSelectedInstOperands,
     /*  223839 */     // GIR_Coverage, 15415,
     /*  223839 */     GIR_EraseRootFromParent_Done,
     /*  223840 */   // Label 3200: @223840
     /*  223840 */   GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(223902), // Rule ID 15416 //
     /*  223845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  223848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223870 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  223873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223900 */     GIR_RootConstrainSelectedInstOperands,
     /*  223901 */     // GIR_Coverage, 15416,
     /*  223901 */     GIR_EraseRootFromParent_Done,
     /*  223902 */   // Label 3201: @223902
     /*  223902 */   GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(223964), // Rule ID 15417 //
     /*  223907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  223910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223932 */     // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  223935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  223942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  223947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  223952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  223958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  223962 */     GIR_RootConstrainSelectedInstOperands,
     /*  223963 */     // GIR_Coverage, 15417,
     /*  223963 */     GIR_EraseRootFromParent_Done,
     /*  223964 */   // Label 3202: @223964
     /*  223964 */   GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(224026), // Rule ID 15423 //
     /*  223969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  223972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  223979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  223983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  223987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  223994 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  223994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  223997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  223999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224024 */     GIR_RootConstrainSelectedInstOperands,
     /*  224025 */     // GIR_Coverage, 15423,
     /*  224025 */     GIR_EraseRootFromParent_Done,
     /*  224026 */   // Label 3203: @224026
     /*  224026 */   GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(224088), // Rule ID 15424 //
     /*  224031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  224034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224056 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  224059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224086 */     GIR_RootConstrainSelectedInstOperands,
     /*  224087 */     // GIR_Coverage, 15424,
     /*  224087 */     GIR_EraseRootFromParent_Done,
     /*  224088 */   // Label 3204: @224088
     /*  224088 */   GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(224150), // Rule ID 15425 //
     /*  224093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  224096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224118 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  224121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224148 */     GIR_RootConstrainSelectedInstOperands,
     /*  224149 */     // GIR_Coverage, 15425,
     /*  224149 */     GIR_EraseRootFromParent_Done,
     /*  224150 */   // Label 3205: @224150
     /*  224150 */   GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(224212), // Rule ID 15426 //
     /*  224155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  224158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224180 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  224183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224210 */     GIR_RootConstrainSelectedInstOperands,
     /*  224211 */     // GIR_Coverage, 15426,
     /*  224211 */     GIR_EraseRootFromParent_Done,
     /*  224212 */   // Label 3206: @224212
     /*  224212 */   GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(224274), // Rule ID 15427 //
     /*  224217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  224220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224242 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
     /*  224245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224272 */     GIR_RootConstrainSelectedInstOperands,
     /*  224273 */     // GIR_Coverage, 15427,
     /*  224273 */     GIR_EraseRootFromParent_Done,
     /*  224274 */   // Label 3207: @224274
     /*  224274 */   GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(224336), // Rule ID 15433 //
     /*  224279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  224282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224304 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  224307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224324 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224334 */     GIR_RootConstrainSelectedInstOperands,
     /*  224335 */     // GIR_Coverage, 15433,
     /*  224335 */     GIR_EraseRootFromParent_Done,
     /*  224336 */   // Label 3208: @224336
     /*  224336 */   GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(224398), // Rule ID 15434 //
     /*  224341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  224344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224366 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  224369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224396 */     GIR_RootConstrainSelectedInstOperands,
     /*  224397 */     // GIR_Coverage, 15434,
     /*  224397 */     GIR_EraseRootFromParent_Done,
     /*  224398 */   // Label 3209: @224398
     /*  224398 */   GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(224460), // Rule ID 15435 //
     /*  224403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  224406 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224428 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  224431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224458 */     GIR_RootConstrainSelectedInstOperands,
     /*  224459 */     // GIR_Coverage, 15435,
     /*  224459 */     GIR_EraseRootFromParent_Done,
     /*  224460 */   // Label 3210: @224460
     /*  224460 */   GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(224522), // Rule ID 15436 //
     /*  224465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  224468 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224490 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  224493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224516 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224520 */     GIR_RootConstrainSelectedInstOperands,
     /*  224521 */     // GIR_Coverage, 15436,
     /*  224521 */     GIR_EraseRootFromParent_Done,
     /*  224522 */   // Label 3211: @224522
     /*  224522 */   GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(224584), // Rule ID 15437 //
     /*  224527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  224530 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  224537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  224552 */     // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  224552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
     /*  224555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  224557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  224562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  224567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  224572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224582 */     GIR_RootConstrainSelectedInstOperands,
     /*  224583 */     // GIR_Coverage, 15437,
     /*  224583 */     GIR_EraseRootFromParent_Done,
     /*  224584 */   // Label 3212: @224584
     /*  224584 */   GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(224640), // Rule ID 28917 //
     /*  224589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  224592 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224616 */     // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224638 */     GIR_RootConstrainSelectedInstOperands,
     /*  224639 */     // GIR_Coverage, 28917,
     /*  224639 */     GIR_EraseRootFromParent_Done,
     /*  224640 */   // Label 3213: @224640
     /*  224640 */   GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(224696), // Rule ID 28918 //
     /*  224645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  224648 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224652 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224672 */     // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224694 */     GIR_RootConstrainSelectedInstOperands,
     /*  224695 */     // GIR_Coverage, 28918,
     /*  224695 */     GIR_EraseRootFromParent_Done,
     /*  224696 */   // Label 3214: @224696
     /*  224696 */   GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(224752), // Rule ID 28919 //
     /*  224701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  224704 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224728 */     // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224750 */     GIR_RootConstrainSelectedInstOperands,
     /*  224751 */     // GIR_Coverage, 28919,
     /*  224751 */     GIR_EraseRootFromParent_Done,
     /*  224752 */   // Label 3215: @224752
     /*  224752 */   GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(224808), // Rule ID 28920 //
     /*  224757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  224760 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224784 */     // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224806 */     GIR_RootConstrainSelectedInstOperands,
     /*  224807 */     // GIR_Coverage, 28920,
     /*  224807 */     GIR_EraseRootFromParent_Done,
     /*  224808 */   // Label 3216: @224808
     /*  224808 */   GIM_Try, /*On fail goto*//*Label 3217*/ GIMT_Encode4(224864), // Rule ID 28921 //
     /*  224813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  224816 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224840 */     // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224862 */     GIR_RootConstrainSelectedInstOperands,
     /*  224863 */     // GIR_Coverage, 28921,
     /*  224863 */     GIR_EraseRootFromParent_Done,
     /*  224864 */   // Label 3217: @224864
     /*  224864 */   GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(224920), // Rule ID 28927 //
     /*  224869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  224872 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224896 */     // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224918 */     GIR_RootConstrainSelectedInstOperands,
     /*  224919 */     // GIR_Coverage, 28927,
     /*  224919 */     GIR_EraseRootFromParent_Done,
     /*  224920 */   // Label 3218: @224920
     /*  224920 */   GIM_Try, /*On fail goto*//*Label 3219*/ GIMT_Encode4(224976), // Rule ID 28928 //
     /*  224925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  224928 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  224945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  224952 */     // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  224952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  224955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  224957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  224962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  224967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  224970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  224974 */     GIR_RootConstrainSelectedInstOperands,
     /*  224975 */     // GIR_Coverage, 28928,
     /*  224975 */     GIR_EraseRootFromParent_Done,
     /*  224976 */   // Label 3219: @224976
     /*  224976 */   GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(225032), // Rule ID 28929 //
     /*  224981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  224984 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  224988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  224993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  224997 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225008 */     // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  225011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225030 */     GIR_RootConstrainSelectedInstOperands,
     /*  225031 */     // GIR_Coverage, 28929,
     /*  225031 */     GIR_EraseRootFromParent_Done,
     /*  225032 */   // Label 3220: @225032
     /*  225032 */   GIM_Try, /*On fail goto*//*Label 3221*/ GIMT_Encode4(225088), // Rule ID 28930 //
     /*  225037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  225040 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  225044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225064 */     // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  225067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225086 */     GIR_RootConstrainSelectedInstOperands,
     /*  225087 */     // GIR_Coverage, 28930,
     /*  225087 */     GIR_EraseRootFromParent_Done,
     /*  225088 */   // Label 3221: @225088
     /*  225088 */   GIM_Try, /*On fail goto*//*Label 3222*/ GIMT_Encode4(225144), // Rule ID 28931 //
     /*  225093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  225096 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  225100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225109 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225120 */     // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
     /*  225123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225142 */     GIR_RootConstrainSelectedInstOperands,
     /*  225143 */     // GIR_Coverage, 28931,
     /*  225143 */     GIR_EraseRootFromParent_Done,
     /*  225144 */   // Label 3222: @225144
     /*  225144 */   GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(225196), // Rule ID 28922 //
     /*  225149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  225152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225161 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225172 */     // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225194 */     GIR_RootConstrainSelectedInstOperands,
     /*  225195 */     // GIR_Coverage, 28922,
     /*  225195 */     GIR_EraseRootFromParent_Done,
     /*  225196 */   // Label 3223: @225196
     /*  225196 */   GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(225248), // Rule ID 28923 //
     /*  225201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  225204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225213 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225224 */     // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225246 */     GIR_RootConstrainSelectedInstOperands,
     /*  225247 */     // GIR_Coverage, 28923,
     /*  225247 */     GIR_EraseRootFromParent_Done,
     /*  225248 */   // Label 3224: @225248
     /*  225248 */   GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(225300), // Rule ID 28924 //
     /*  225253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  225256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225276 */     // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225298 */     GIR_RootConstrainSelectedInstOperands,
     /*  225299 */     // GIR_Coverage, 28924,
     /*  225299 */     GIR_EraseRootFromParent_Done,
     /*  225300 */   // Label 3225: @225300
     /*  225300 */   GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(225352), // Rule ID 28925 //
     /*  225305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  225308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225328 */     // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225350 */     GIR_RootConstrainSelectedInstOperands,
     /*  225351 */     // GIR_Coverage, 28925,
     /*  225351 */     GIR_EraseRootFromParent_Done,
     /*  225352 */   // Label 3226: @225352
     /*  225352 */   GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(225404), // Rule ID 28926 //
     /*  225357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  225360 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225369 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225380 */     // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225402 */     GIR_RootConstrainSelectedInstOperands,
     /*  225403 */     // GIR_Coverage, 28926,
     /*  225403 */     GIR_EraseRootFromParent_Done,
     /*  225404 */   // Label 3227: @225404
     /*  225404 */   GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(225456), // Rule ID 28932 //
     /*  225409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  225412 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225432 */     // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225454 */     GIR_RootConstrainSelectedInstOperands,
     /*  225455 */     // GIR_Coverage, 28932,
     /*  225455 */     GIR_EraseRootFromParent_Done,
     /*  225456 */   // Label 3228: @225456
     /*  225456 */   GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(225508), // Rule ID 28933 //
     /*  225461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  225464 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225484 */     // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225506 */     GIR_RootConstrainSelectedInstOperands,
     /*  225507 */     // GIR_Coverage, 28933,
     /*  225507 */     GIR_EraseRootFromParent_Done,
     /*  225508 */   // Label 3229: @225508
     /*  225508 */   GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(225560), // Rule ID 28934 //
     /*  225513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  225516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225525 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225529 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225536 */     // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225558 */     GIR_RootConstrainSelectedInstOperands,
     /*  225559 */     // GIR_Coverage, 28934,
     /*  225559 */     GIR_EraseRootFromParent_Done,
     /*  225560 */   // Label 3230: @225560
     /*  225560 */   GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(225612), // Rule ID 28935 //
     /*  225565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  225568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225588 */     // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225610 */     GIR_RootConstrainSelectedInstOperands,
     /*  225611 */     // GIR_Coverage, 28935,
     /*  225611 */     GIR_EraseRootFromParent_Done,
     /*  225612 */   // Label 3231: @225612
     /*  225612 */   GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(225664), // Rule ID 28936 //
     /*  225617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  225620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  225625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  225640 */     // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  225640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
     /*  225643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  225650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  225655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  225658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225662 */     GIR_RootConstrainSelectedInstOperands,
     /*  225663 */     // GIR_Coverage, 28936,
     /*  225663 */     GIR_EraseRootFromParent_Done,
     /*  225664 */   // Label 3232: @225664
     /*  225664 */   GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(225725), // Rule ID 12143 //
     /*  225669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  225672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  225679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  225694 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  225694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  225697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  225704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  225709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  225714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  225719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225723 */     GIR_RootConstrainSelectedInstOperands,
     /*  225724 */     // GIR_Coverage, 12143,
     /*  225724 */     GIR_EraseRootFromParent_Done,
     /*  225725 */   // Label 3233: @225725
     /*  225725 */   GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(225786), // Rule ID 12144 //
     /*  225730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  225733 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  225740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  225755 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  225755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  225758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  225765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  225770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  225775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  225780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225784 */     GIR_RootConstrainSelectedInstOperands,
     /*  225785 */     // GIR_Coverage, 12144,
     /*  225785 */     GIR_EraseRootFromParent_Done,
     /*  225786 */   // Label 3234: @225786
     /*  225786 */   GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(225847), // Rule ID 12145 //
     /*  225791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  225794 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  225801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  225816 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  225816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  225819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  225826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  225831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  225836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  225841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225845 */     GIR_RootConstrainSelectedInstOperands,
     /*  225846 */     // GIR_Coverage, 12145,
     /*  225846 */     GIR_EraseRootFromParent_Done,
     /*  225847 */   // Label 3235: @225847
     /*  225847 */   GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(225908), // Rule ID 12146 //
     /*  225852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  225855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  225862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  225877 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  225877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  225880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  225887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  225892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  225897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  225902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225906 */     GIR_RootConstrainSelectedInstOperands,
     /*  225907 */     // GIR_Coverage, 12146,
     /*  225907 */     GIR_EraseRootFromParent_Done,
     /*  225908 */   // Label 3236: @225908
     /*  225908 */   GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(225969), // Rule ID 12147 //
     /*  225913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  225916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  225923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  225938 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  225938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  225941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  225943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  225948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  225953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  225958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  225963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  225967 */     GIR_RootConstrainSelectedInstOperands,
     /*  225968 */     // GIR_Coverage, 12147,
     /*  225968 */     GIR_EraseRootFromParent_Done,
     /*  225969 */   // Label 3237: @225969
     /*  225969 */   GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(226030), // Rule ID 12163 //
     /*  225974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  225977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  225984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  225988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  225992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  225999 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  225999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  226002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226028 */     GIR_RootConstrainSelectedInstOperands,
     /*  226029 */     // GIR_Coverage, 12163,
     /*  226029 */     GIR_EraseRootFromParent_Done,
     /*  226030 */   // Label 3238: @226030
     /*  226030 */   GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(226091), // Rule ID 12164 //
     /*  226035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  226038 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226060 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  226063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226089 */     GIR_RootConstrainSelectedInstOperands,
     /*  226090 */     // GIR_Coverage, 12164,
     /*  226090 */     GIR_EraseRootFromParent_Done,
     /*  226091 */   // Label 3239: @226091
     /*  226091 */   GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(226152), // Rule ID 12165 //
     /*  226096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  226099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226121 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  226124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226150 */     GIR_RootConstrainSelectedInstOperands,
     /*  226151 */     // GIR_Coverage, 12165,
     /*  226151 */     GIR_EraseRootFromParent_Done,
     /*  226152 */   // Label 3240: @226152
     /*  226152 */   GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(226213), // Rule ID 12166 //
     /*  226157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  226160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226182 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  226185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226211 */     GIR_RootConstrainSelectedInstOperands,
     /*  226212 */     // GIR_Coverage, 12166,
     /*  226212 */     GIR_EraseRootFromParent_Done,
     /*  226213 */   // Label 3241: @226213
     /*  226213 */   GIM_Try, /*On fail goto*//*Label 3242*/ GIMT_Encode4(226274), // Rule ID 12167 //
     /*  226218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  226221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226243 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
     /*  226246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226272 */     GIR_RootConstrainSelectedInstOperands,
     /*  226273 */     // GIR_Coverage, 12167,
     /*  226273 */     GIR_EraseRootFromParent_Done,
     /*  226274 */   // Label 3242: @226274
     /*  226274 */   GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(226328), // Rule ID 12138 //
     /*  226279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  226282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226304 */     // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226326 */     GIR_RootConstrainSelectedInstOperands,
     /*  226327 */     // GIR_Coverage, 12138,
     /*  226327 */     GIR_EraseRootFromParent_Done,
     /*  226328 */   // Label 3243: @226328
     /*  226328 */   GIM_Try, /*On fail goto*//*Label 3244*/ GIMT_Encode4(226382), // Rule ID 12139 //
     /*  226333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  226336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226358 */     // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226380 */     GIR_RootConstrainSelectedInstOperands,
     /*  226381 */     // GIR_Coverage, 12139,
     /*  226381 */     GIR_EraseRootFromParent_Done,
     /*  226382 */   // Label 3244: @226382
     /*  226382 */   GIM_Try, /*On fail goto*//*Label 3245*/ GIMT_Encode4(226436), // Rule ID 12140 //
     /*  226387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  226390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226412 */     // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226434 */     GIR_RootConstrainSelectedInstOperands,
     /*  226435 */     // GIR_Coverage, 12140,
     /*  226435 */     GIR_EraseRootFromParent_Done,
     /*  226436 */   // Label 3245: @226436
     /*  226436 */   GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(226490), // Rule ID 12141 //
     /*  226441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  226444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226466 */     // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226488 */     GIR_RootConstrainSelectedInstOperands,
     /*  226489 */     // GIR_Coverage, 12141,
     /*  226489 */     GIR_EraseRootFromParent_Done,
     /*  226490 */   // Label 3246: @226490
     /*  226490 */   GIM_Try, /*On fail goto*//*Label 3247*/ GIMT_Encode4(226544), // Rule ID 12142 //
     /*  226495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  226498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226520 */     // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226542 */     GIR_RootConstrainSelectedInstOperands,
     /*  226543 */     // GIR_Coverage, 12142,
     /*  226543 */     GIR_EraseRootFromParent_Done,
     /*  226544 */   // Label 3247: @226544
     /*  226544 */   GIM_Try, /*On fail goto*//*Label 3248*/ GIMT_Encode4(226598), // Rule ID 12158 //
     /*  226549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  226552 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226574 */     // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226596 */     GIR_RootConstrainSelectedInstOperands,
     /*  226597 */     // GIR_Coverage, 12158,
     /*  226597 */     GIR_EraseRootFromParent_Done,
     /*  226598 */   // Label 3248: @226598
     /*  226598 */   GIM_Try, /*On fail goto*//*Label 3249*/ GIMT_Encode4(226652), // Rule ID 12159 //
     /*  226603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  226606 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226628 */     // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226650 */     GIR_RootConstrainSelectedInstOperands,
     /*  226651 */     // GIR_Coverage, 12159,
     /*  226651 */     GIR_EraseRootFromParent_Done,
     /*  226652 */   // Label 3249: @226652
     /*  226652 */   GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(226706), // Rule ID 12160 //
     /*  226657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  226660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226682 */     // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226704 */     GIR_RootConstrainSelectedInstOperands,
     /*  226705 */     // GIR_Coverage, 12160,
     /*  226705 */     GIR_EraseRootFromParent_Done,
     /*  226706 */   // Label 3250: @226706
     /*  226706 */   GIM_Try, /*On fail goto*//*Label 3251*/ GIMT_Encode4(226760), // Rule ID 12161 //
     /*  226711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  226714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226736 */     // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226758 */     GIR_RootConstrainSelectedInstOperands,
     /*  226759 */     // GIR_Coverage, 12161,
     /*  226759 */     GIR_EraseRootFromParent_Done,
     /*  226760 */   // Label 3251: @226760
     /*  226760 */   GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(226814), // Rule ID 12162 //
     /*  226765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  226768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226783 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  226790 */     // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  226790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
     /*  226793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  226800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  226805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  226808 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226812 */     GIR_RootConstrainSelectedInstOperands,
     /*  226813 */     // GIR_Coverage, 12162,
     /*  226813 */     GIR_EraseRootFromParent_Done,
     /*  226814 */   // Label 3252: @226814
     /*  226814 */   GIM_Try, /*On fail goto*//*Label 3253*/ GIMT_Encode4(226876), // Rule ID 10001 //
     /*  226819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  226822 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226845 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  226848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226874 */     GIR_RootConstrainSelectedInstOperands,
     /*  226875 */     // GIR_Coverage, 10001,
     /*  226875 */     GIR_EraseRootFromParent_Done,
     /*  226876 */   // Label 3253: @226876
     /*  226876 */   GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(226938), // Rule ID 10002 //
     /*  226881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  226884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226907 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  226910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226936 */     GIR_RootConstrainSelectedInstOperands,
     /*  226937 */     // GIR_Coverage, 10002,
     /*  226937 */     GIR_EraseRootFromParent_Done,
     /*  226938 */   // Label 3254: @226938
     /*  226938 */   GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(227000), // Rule ID 10003 //
     /*  226943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  226946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  226954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  226958 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  226962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  226969 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  226969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  226972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  226974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  226979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  226984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  226989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  226994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  226998 */     GIR_RootConstrainSelectedInstOperands,
     /*  226999 */     // GIR_Coverage, 10003,
     /*  226999 */     GIR_EraseRootFromParent_Done,
     /*  227000 */   // Label 3255: @227000
     /*  227000 */   GIM_Try, /*On fail goto*//*Label 3256*/ GIMT_Encode4(227062), // Rule ID 10004 //
     /*  227005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  227008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227031 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227060 */     GIR_RootConstrainSelectedInstOperands,
     /*  227061 */     // GIR_Coverage, 10004,
     /*  227061 */     GIR_EraseRootFromParent_Done,
     /*  227062 */   // Label 3256: @227062
     /*  227062 */   GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(227124), // Rule ID 10005 //
     /*  227067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  227070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227093 */     // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227122 */     GIR_RootConstrainSelectedInstOperands,
     /*  227123 */     // GIR_Coverage, 10005,
     /*  227123 */     GIR_EraseRootFromParent_Done,
     /*  227124 */   // Label 3257: @227124
     /*  227124 */   GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(227186), // Rule ID 10021 //
     /*  227129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  227132 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227144 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227155 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227184 */     GIR_RootConstrainSelectedInstOperands,
     /*  227185 */     // GIR_Coverage, 10021,
     /*  227185 */     GIR_EraseRootFromParent_Done,
     /*  227186 */   // Label 3258: @227186
     /*  227186 */   GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(227248), // Rule ID 10022 //
     /*  227191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  227194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227217 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227246 */     GIR_RootConstrainSelectedInstOperands,
     /*  227247 */     // GIR_Coverage, 10022,
     /*  227247 */     GIR_EraseRootFromParent_Done,
     /*  227248 */   // Label 3259: @227248
     /*  227248 */   GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(227310), // Rule ID 10023 //
     /*  227253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  227256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227279 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227308 */     GIR_RootConstrainSelectedInstOperands,
     /*  227309 */     // GIR_Coverage, 10023,
     /*  227309 */     GIR_EraseRootFromParent_Done,
     /*  227310 */   // Label 3260: @227310
     /*  227310 */   GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(227372), // Rule ID 10024 //
     /*  227315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  227318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227341 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227370 */     GIR_RootConstrainSelectedInstOperands,
     /*  227371 */     // GIR_Coverage, 10024,
     /*  227371 */     GIR_EraseRootFromParent_Done,
     /*  227372 */   // Label 3261: @227372
     /*  227372 */   GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(227434), // Rule ID 10025 //
     /*  227377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  227380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227396 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  227403 */     // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  227403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD_SADDR),
     /*  227406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  227413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  227418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  227423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  227428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227432 */     GIR_RootConstrainSelectedInstOperands,
     /*  227433 */     // GIR_Coverage, 10025,
     /*  227433 */     GIR_EraseRootFromParent_Done,
     /*  227434 */   // Label 3262: @227434
     /*  227434 */   GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(227489), // Rule ID 9996 //
     /*  227439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  227442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227465 */     // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227487 */     GIR_RootConstrainSelectedInstOperands,
     /*  227488 */     // GIR_Coverage, 9996,
     /*  227488 */     GIR_EraseRootFromParent_Done,
     /*  227489 */   // Label 3263: @227489
     /*  227489 */   GIM_Try, /*On fail goto*//*Label 3264*/ GIMT_Encode4(227544), // Rule ID 9997 //
     /*  227494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  227497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227520 */     // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227542 */     GIR_RootConstrainSelectedInstOperands,
     /*  227543 */     // GIR_Coverage, 9997,
     /*  227543 */     GIR_EraseRootFromParent_Done,
     /*  227544 */   // Label 3264: @227544
     /*  227544 */   GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(227599), // Rule ID 9998 //
     /*  227549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  227552 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227564 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227568 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227575 */     // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227597 */     GIR_RootConstrainSelectedInstOperands,
     /*  227598 */     // GIR_Coverage, 9998,
     /*  227598 */     GIR_EraseRootFromParent_Done,
     /*  227599 */   // Label 3265: @227599
     /*  227599 */   GIM_Try, /*On fail goto*//*Label 3266*/ GIMT_Encode4(227654), // Rule ID 9999 //
     /*  227604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  227607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227630 */     // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227652 */     GIR_RootConstrainSelectedInstOperands,
     /*  227653 */     // GIR_Coverage, 9999,
     /*  227653 */     GIR_EraseRootFromParent_Done,
     /*  227654 */   // Label 3266: @227654
     /*  227654 */   GIM_Try, /*On fail goto*//*Label 3267*/ GIMT_Encode4(227709), // Rule ID 10000 //
     /*  227659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  227662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227685 */     // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227703 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227707 */     GIR_RootConstrainSelectedInstOperands,
     /*  227708 */     // GIR_Coverage, 10000,
     /*  227708 */     GIR_EraseRootFromParent_Done,
     /*  227709 */   // Label 3267: @227709
     /*  227709 */   GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(227764), // Rule ID 10016 //
     /*  227714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  227717 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227740 */     // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227762 */     GIR_RootConstrainSelectedInstOperands,
     /*  227763 */     // GIR_Coverage, 10016,
     /*  227763 */     GIR_EraseRootFromParent_Done,
     /*  227764 */   // Label 3268: @227764
     /*  227764 */   GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(227819), // Rule ID 10017 //
     /*  227769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  227772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227795 */     // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227817 */     GIR_RootConstrainSelectedInstOperands,
     /*  227818 */     // GIR_Coverage, 10017,
     /*  227818 */     GIR_EraseRootFromParent_Done,
     /*  227819 */   // Label 3269: @227819
     /*  227819 */   GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(227874), // Rule ID 10018 //
     /*  227824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  227827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227839 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227850 */     // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227872 */     GIR_RootConstrainSelectedInstOperands,
     /*  227873 */     // GIR_Coverage, 10018,
     /*  227873 */     GIR_EraseRootFromParent_Done,
     /*  227874 */   // Label 3270: @227874
     /*  227874 */   GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(227929), // Rule ID 10019 //
     /*  227879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  227882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227905 */     // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227927 */     GIR_RootConstrainSelectedInstOperands,
     /*  227928 */     // GIR_Coverage, 10019,
     /*  227928 */     GIR_EraseRootFromParent_Done,
     /*  227929 */   // Label 3271: @227929
     /*  227929 */   GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(227984), // Rule ID 10020 //
     /*  227934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  227937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  227945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  227949 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  227953 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  227960 */     // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  227960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
     /*  227963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  227965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  227970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  227975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  227978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  227982 */     GIR_RootConstrainSelectedInstOperands,
     /*  227983 */     // GIR_Coverage, 10020,
     /*  227983 */     GIR_EraseRootFromParent_Done,
     /*  227984 */   // Label 3272: @227984
     /*  227984 */   GIM_Reject,
     /*  227985 */ // Label 3078: @227985
     /*  227985 */ GIM_Reject,
     /*  227986 */ // Label 1130: @227986
     /*  227986 */ GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(228055), // Rule ID 8779 //
     /*  227991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  227994 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  227997 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228005 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228009 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228013 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  228017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  228024 */   // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  228024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  228027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  228039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  228044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  228049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228053 */   GIR_RootConstrainSelectedInstOperands,
     /*  228054 */   // GIR_Coverage, 8779,
     /*  228054 */   GIR_EraseRootFromParent_Done,
     /*  228055 */ // Label 3273: @228055
     /*  228055 */ GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(228124), // Rule ID 8813 //
     /*  228060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  228063 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228066 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228078 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228082 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  228086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  228093 */   // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  228093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  228096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  228108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  228113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  228118 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228122 */   GIR_RootConstrainSelectedInstOperands,
     /*  228123 */   // GIR_Coverage, 8813,
     /*  228123 */   GIR_EraseRootFromParent_Done,
     /*  228124 */ // Label 3274: @228124
     /*  228124 */ GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(228189), // Rule ID 8784 //
     /*  228129 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  228132 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228135 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228147 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228151 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  228158 */   // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  228158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  228161 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  228173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  228178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  228183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228187 */   GIR_RootConstrainSelectedInstOperands,
     /*  228188 */   // GIR_Coverage, 8784,
     /*  228188 */   GIR_EraseRootFromParent_Done,
     /*  228189 */ // Label 3275: @228189
     /*  228189 */ GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(228254), // Rule ID 8818 //
     /*  228194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  228197 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228200 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228212 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228216 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  228223 */   // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  228223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  228226 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  228238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  228243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  228248 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228252 */   GIR_RootConstrainSelectedInstOperands,
     /*  228253 */   // GIR_Coverage, 8818,
     /*  228253 */   GIR_EraseRootFromParent_Done,
     /*  228254 */ // Label 3276: @228254
     /*  228254 */ GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(228319), // Rule ID 8790 //
     /*  228259 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  228262 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228265 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228277 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228281 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  228288 */   // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  228288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  228291 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  228303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  228308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  228313 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228317 */   GIR_RootConstrainSelectedInstOperands,
     /*  228318 */   // GIR_Coverage, 8790,
     /*  228318 */   GIR_EraseRootFromParent_Done,
     /*  228319 */ // Label 3277: @228319
     /*  228319 */ GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(228384), // Rule ID 8824 //
     /*  228324 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  228327 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228330 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228338 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228342 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  228353 */   // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  228353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  228356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  228368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  228373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  228378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228382 */   GIR_RootConstrainSelectedInstOperands,
     /*  228383 */   // GIR_Coverage, 8824,
     /*  228383 */   GIR_EraseRootFromParent_Done,
     /*  228384 */ // Label 3278: @228384
     /*  228384 */ GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(228446), // Rule ID 8775 //
     /*  228389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  228392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228395 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228407 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228411 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  228415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  228422 */   // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  228422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  228425 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228444 */   GIR_RootConstrainSelectedInstOperands,
     /*  228445 */   // GIR_Coverage, 8775,
     /*  228445 */   GIR_EraseRootFromParent_Done,
     /*  228446 */ // Label 3279: @228446
     /*  228446 */ GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(228508), // Rule ID 8776 //
     /*  228451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  228454 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228457 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228469 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228473 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  228477 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  228484 */   // (ld:{ *:[v2i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  228484 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  228487 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228506 */   GIR_RootConstrainSelectedInstOperands,
     /*  228507 */   // GIR_Coverage, 8776,
     /*  228507 */   GIR_EraseRootFromParent_Done,
     /*  228508 */ // Label 3280: @228508
     /*  228508 */ GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(228570), // Rule ID 8809 //
     /*  228513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  228516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228519 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228527 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228531 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228535 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  228539 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  228546 */   // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  228546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  228549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228561 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228564 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228568 */   GIR_RootConstrainSelectedInstOperands,
     /*  228569 */   // GIR_Coverage, 8809,
     /*  228569 */   GIR_EraseRootFromParent_Done,
     /*  228570 */ // Label 3281: @228570
     /*  228570 */ GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(228632), // Rule ID 8810 //
     /*  228575 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  228578 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228581 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228585 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228589 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228593 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228597 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  228601 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  228608 */   // (ld:{ *:[v2f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  228608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  228611 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228623 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228626 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228630 */   GIR_RootConstrainSelectedInstOperands,
     /*  228631 */   // GIR_Coverage, 8810,
     /*  228631 */   GIR_EraseRootFromParent_Done,
     /*  228632 */ // Label 3282: @228632
     /*  228632 */ GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(228690), // Rule ID 8781 //
     /*  228637 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  228640 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228643 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228651 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228655 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  228666 */   // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  228666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  228669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228688 */   GIR_RootConstrainSelectedInstOperands,
     /*  228689 */   // GIR_Coverage, 8781,
     /*  228689 */   GIR_EraseRootFromParent_Done,
     /*  228690 */ // Label 3283: @228690
     /*  228690 */ GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(228748), // Rule ID 8815 //
     /*  228695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  228698 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228701 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  228709 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228713 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  228717 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  228724 */   // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  228724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  228727 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  228729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  228734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228739 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228742 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228746 */   GIR_RootConstrainSelectedInstOperands,
     /*  228747 */   // GIR_Coverage, 8815,
     /*  228747 */   GIR_EraseRootFromParent_Done,
     /*  228748 */ // Label 3284: @228748
     /*  228748 */ GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(228816), // Rule ID 29983 //
     /*  228753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  228756 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228759 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228763 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228768 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  228777 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228781 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  228785 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  228792 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  228792 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  228795 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  228797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  228802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228807 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228810 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228814 */   GIR_RootConstrainSelectedInstOperands,
     /*  228815 */   // GIR_Coverage, 29983,
     /*  228815 */   GIR_EraseRootFromParent_Done,
     /*  228816 */ // Label 3285: @228816
     /*  228816 */ GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(228884), // Rule ID 29984 //
     /*  228821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  228824 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228827 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228836 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  228845 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228849 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  228853 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  228860 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  228860 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  228863 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  228865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  228870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228882 */   GIR_RootConstrainSelectedInstOperands,
     /*  228883 */   // GIR_Coverage, 29984,
     /*  228883 */   GIR_EraseRootFromParent_Done,
     /*  228884 */ // Label 3286: @228884
     /*  228884 */ GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(228952), // Rule ID 29985 //
     /*  228889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  228892 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228895 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228899 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  228913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228917 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  228921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  228928 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  228928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  228931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  228933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  228938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  228943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  228946 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  228950 */   GIR_RootConstrainSelectedInstOperands,
     /*  228951 */   // GIR_Coverage, 29985,
     /*  228951 */   GIR_EraseRootFromParent_Done,
     /*  228952 */ // Label 3287: @228952
     /*  228952 */ GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(229020), // Rule ID 29986 //
     /*  228957 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  228960 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  228963 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  228967 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228972 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  228977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  228981 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  228985 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  228989 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  228996 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  228996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  228999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229011 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229014 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229018 */   GIR_RootConstrainSelectedInstOperands,
     /*  229019 */   // GIR_Coverage, 29986,
     /*  229019 */   GIR_EraseRootFromParent_Done,
     /*  229020 */ // Label 3288: @229020
     /*  229020 */ GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(229088), // Rule ID 29987 //
     /*  229025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  229028 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229031 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229035 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229040 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229045 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229049 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229053 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  229057 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229064 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229079 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229082 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229086 */   GIR_RootConstrainSelectedInstOperands,
     /*  229087 */   // GIR_Coverage, 29987,
     /*  229087 */   GIR_EraseRootFromParent_Done,
     /*  229088 */ // Label 3289: @229088
     /*  229088 */ GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(229156), // Rule ID 30003 //
     /*  229093 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  229096 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229099 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229103 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229121 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  229125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229132 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229135 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229147 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229150 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229154 */   GIR_RootConstrainSelectedInstOperands,
     /*  229155 */   // GIR_Coverage, 30003,
     /*  229155 */   GIR_EraseRootFromParent_Done,
     /*  229156 */ // Label 3290: @229156
     /*  229156 */ GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(229224), // Rule ID 30004 //
     /*  229161 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  229164 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229167 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229171 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229176 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229185 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229189 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  229193 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229200 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229200 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229203 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229205 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229215 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229218 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229222 */   GIR_RootConstrainSelectedInstOperands,
     /*  229223 */   // GIR_Coverage, 30004,
     /*  229223 */   GIR_EraseRootFromParent_Done,
     /*  229224 */ // Label 3291: @229224
     /*  229224 */ GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(229292), // Rule ID 30005 //
     /*  229229 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  229232 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229235 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229244 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229249 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229253 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229257 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  229261 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229268 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229268 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229271 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229283 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229286 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229290 */   GIR_RootConstrainSelectedInstOperands,
     /*  229291 */   // GIR_Coverage, 30005,
     /*  229291 */   GIR_EraseRootFromParent_Done,
     /*  229292 */ // Label 3292: @229292
     /*  229292 */ GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(229360), // Rule ID 30006 //
     /*  229297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  229300 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229303 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229307 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229312 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229317 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229321 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229325 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  229329 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229336 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229336 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229339 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229351 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229354 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229358 */   GIR_RootConstrainSelectedInstOperands,
     /*  229359 */   // GIR_Coverage, 30006,
     /*  229359 */   GIR_EraseRootFromParent_Done,
     /*  229360 */ // Label 3293: @229360
     /*  229360 */ GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(229428), // Rule ID 30007 //
     /*  229365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  229368 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229371 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229380 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229389 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229393 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  229397 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229404 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229407 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229426 */   GIR_RootConstrainSelectedInstOperands,
     /*  229427 */   // GIR_Coverage, 30007,
     /*  229427 */   GIR_EraseRootFromParent_Done,
     /*  229428 */ // Label 3294: @229428
     /*  229428 */ GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(229491), // Rule ID 29643 //
     /*  229433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  229436 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229439 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229448 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229456 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229460 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229467 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229482 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229485 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229489 */   GIR_RootConstrainSelectedInstOperands,
     /*  229490 */   // GIR_Coverage, 29643,
     /*  229490 */   GIR_EraseRootFromParent_Done,
     /*  229491 */ // Label 3295: @229491
     /*  229491 */ GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(229554), // Rule ID 29644 //
     /*  229496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  229499 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229502 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229506 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229511 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229530 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229530 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229533 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229545 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229548 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229552 */   GIR_RootConstrainSelectedInstOperands,
     /*  229553 */   // GIR_Coverage, 29644,
     /*  229553 */   GIR_EraseRootFromParent_Done,
     /*  229554 */ // Label 3296: @229554
     /*  229554 */ GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(229617), // Rule ID 29645 //
     /*  229559 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  229562 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229565 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229574 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229582 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229586 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229593 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229593 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229596 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229608 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229611 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229615 */   GIR_RootConstrainSelectedInstOperands,
     /*  229616 */   // GIR_Coverage, 29645,
     /*  229616 */   GIR_EraseRootFromParent_Done,
     /*  229617 */ // Label 3297: @229617
     /*  229617 */ GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(229680), // Rule ID 29646 //
     /*  229622 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  229625 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229628 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229632 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229637 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229645 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229649 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229656 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229656 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229659 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229678 */   GIR_RootConstrainSelectedInstOperands,
     /*  229679 */   // GIR_Coverage, 29646,
     /*  229679 */   GIR_EraseRootFromParent_Done,
     /*  229680 */ // Label 3298: @229680
     /*  229680 */ GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(229743), // Rule ID 29647 //
     /*  229685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  229688 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229691 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229700 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229719 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229722 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229741 */   GIR_RootConstrainSelectedInstOperands,
     /*  229742 */   // GIR_Coverage, 29647,
     /*  229742 */   GIR_EraseRootFromParent_Done,
     /*  229743 */ // Label 3299: @229743
     /*  229743 */ GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(229806), // Rule ID 29663 //
     /*  229748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  229751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229754 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229758 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229763 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229775 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229782 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229785 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229800 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229804 */   GIR_RootConstrainSelectedInstOperands,
     /*  229805 */   // GIR_Coverage, 29663,
     /*  229805 */   GIR_EraseRootFromParent_Done,
     /*  229806 */ // Label 3300: @229806
     /*  229806 */ GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(229869), // Rule ID 29664 //
     /*  229811 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  229814 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229817 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229821 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229826 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229845 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229848 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229867 */   GIR_RootConstrainSelectedInstOperands,
     /*  229868 */   // GIR_Coverage, 29664,
     /*  229868 */   GIR_EraseRootFromParent_Done,
     /*  229869 */ // Label 3301: @229869
     /*  229869 */ GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(229932), // Rule ID 29665 //
     /*  229874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  229877 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229880 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229884 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229889 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229893 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229897 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229901 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229908 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229908 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229911 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229923 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229926 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229930 */   GIR_RootConstrainSelectedInstOperands,
     /*  229931 */   // GIR_Coverage, 29665,
     /*  229931 */   GIR_EraseRootFromParent_Done,
     /*  229932 */ // Label 3302: @229932
     /*  229932 */ GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(229995), // Rule ID 29666 //
     /*  229937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  229940 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  229943 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  229947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  229952 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  229956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  229960 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  229964 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  229971 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  229971 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  229974 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  229976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  229981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  229986 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  229989 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  229993 */   GIR_RootConstrainSelectedInstOperands,
     /*  229994 */   // GIR_Coverage, 29666,
     /*  229994 */   GIR_EraseRootFromParent_Done,
     /*  229995 */ // Label 3303: @229995
     /*  229995 */ GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(230058), // Rule ID 29667 //
     /*  230000 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  230003 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230006 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  230010 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230015 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  230019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230023 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230027 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230034 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  230037 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230049 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230052 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230056 */   GIR_RootConstrainSelectedInstOperands,
     /*  230057 */   // GIR_Coverage, 29667,
     /*  230057 */   GIR_EraseRootFromParent_Done,
     /*  230058 */ // Label 3304: @230058
     /*  230058 */ GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(230113), // Rule ID 8786 //
     /*  230063 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230066 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  230070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  230074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230078 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  230082 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  230089 */   // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  230089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  230092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  230094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  230099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230104 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230111 */   GIR_RootConstrainSelectedInstOperands,
     /*  230112 */   // GIR_Coverage, 8786,
     /*  230112 */   GIR_EraseRootFromParent_Done,
     /*  230113 */ // Label 3305: @230113
     /*  230113 */ GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(230171), // Rule ID 8787 //
     /*  230118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  230121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230124 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  230128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  230132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230136 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  230140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  230147 */   // (ld:{ *:[v2i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  230147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  230150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  230152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  230157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230169 */   GIR_RootConstrainSelectedInstOperands,
     /*  230170 */   // GIR_Coverage, 8787,
     /*  230170 */   GIR_EraseRootFromParent_Done,
     /*  230171 */ // Label 3306: @230171
     /*  230171 */ GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(230226), // Rule ID 8820 //
     /*  230176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230179 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  230183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  230187 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230191 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  230195 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  230202 */   // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  230202 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  230205 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  230207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  230212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230217 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230220 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230224 */   GIR_RootConstrainSelectedInstOperands,
     /*  230225 */   // GIR_Coverage, 8820,
     /*  230225 */   GIR_EraseRootFromParent_Done,
     /*  230226 */ // Label 3307: @230226
     /*  230226 */ GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(230284), // Rule ID 8821 //
     /*  230231 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  230234 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230237 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  230241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  230245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230249 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  230253 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  230260 */   // (ld:{ *:[v2f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  230260 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  230263 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  230265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  230270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230278 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230282 */   GIR_RootConstrainSelectedInstOperands,
     /*  230283 */   // GIR_Coverage, 8821,
     /*  230283 */   GIR_EraseRootFromParent_Done,
     /*  230284 */ // Label 3308: @230284
     /*  230284 */ GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(230348), // Rule ID 29988 //
     /*  230289 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  230292 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230300 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230313 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230324 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230327 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230346 */   GIR_RootConstrainSelectedInstOperands,
     /*  230347 */   // GIR_Coverage, 29988,
     /*  230347 */   GIR_EraseRootFromParent_Done,
     /*  230348 */ // Label 3309: @230348
     /*  230348 */ GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(230412), // Rule ID 29989 //
     /*  230353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  230356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230364 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230377 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230388 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230391 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230406 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230410 */   GIR_RootConstrainSelectedInstOperands,
     /*  230411 */   // GIR_Coverage, 29989,
     /*  230411 */   GIR_EraseRootFromParent_Done,
     /*  230412 */ // Label 3310: @230412
     /*  230412 */ GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(230476), // Rule ID 29990 //
     /*  230417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  230420 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230423 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230441 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230452 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230455 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230467 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230470 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230474 */   GIR_RootConstrainSelectedInstOperands,
     /*  230475 */   // GIR_Coverage, 29990,
     /*  230475 */   GIR_EraseRootFromParent_Done,
     /*  230476 */ // Label 3311: @230476
     /*  230476 */ GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(230540), // Rule ID 29991 //
     /*  230481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  230484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230487 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230505 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230509 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230516 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230516 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230519 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230531 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230534 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230538 */   GIR_RootConstrainSelectedInstOperands,
     /*  230539 */   // GIR_Coverage, 29991,
     /*  230539 */   GIR_EraseRootFromParent_Done,
     /*  230540 */ // Label 3312: @230540
     /*  230540 */ GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(230604), // Rule ID 29992 //
     /*  230545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  230548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230569 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230580 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230583 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230595 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230602 */   GIR_RootConstrainSelectedInstOperands,
     /*  230603 */   // GIR_Coverage, 29992,
     /*  230603 */   GIR_EraseRootFromParent_Done,
     /*  230604 */ // Label 3313: @230604
     /*  230604 */ GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(230668), // Rule ID 30008 //
     /*  230609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  230612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230633 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230637 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230644 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230644 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230647 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230662 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230666 */   GIR_RootConstrainSelectedInstOperands,
     /*  230667 */   // GIR_Coverage, 30008,
     /*  230667 */   GIR_EraseRootFromParent_Done,
     /*  230668 */ // Label 3314: @230668
     /*  230668 */ GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(230732), // Rule ID 30009 //
     /*  230673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  230676 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230679 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230697 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230708 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230730 */   GIR_RootConstrainSelectedInstOperands,
     /*  230731 */   // GIR_Coverage, 30009,
     /*  230731 */   GIR_EraseRootFromParent_Done,
     /*  230732 */ // Label 3315: @230732
     /*  230732 */ GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(230796), // Rule ID 30010 //
     /*  230737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  230740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230748 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230757 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230761 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230772 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230787 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230790 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230794 */   GIR_RootConstrainSelectedInstOperands,
     /*  230795 */   // GIR_Coverage, 30010,
     /*  230795 */   GIR_EraseRootFromParent_Done,
     /*  230796 */ // Label 3316: @230796
     /*  230796 */ GIM_Try, /*On fail goto*//*Label 3317*/ GIMT_Encode4(230860), // Rule ID 30011 //
     /*  230801 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  230804 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230825 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230829 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230836 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230839 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230851 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230854 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230858 */   GIR_RootConstrainSelectedInstOperands,
     /*  230859 */   // GIR_Coverage, 30011,
     /*  230859 */   GIR_EraseRootFromParent_Done,
     /*  230860 */ // Label 3317: @230860
     /*  230860 */ GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(230924), // Rule ID 30012 //
     /*  230865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  230868 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230881 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230885 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230889 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  230893 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230900 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230903 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230915 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230918 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230922 */   GIR_RootConstrainSelectedInstOperands,
     /*  230923 */   // GIR_Coverage, 30012,
     /*  230923 */   GIR_EraseRootFromParent_Done,
     /*  230924 */ // Label 3318: @230924
     /*  230924 */ GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(230983), // Rule ID 29648 //
     /*  230929 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  230932 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230935 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230940 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  230944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  230948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  230952 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  230959 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  230959 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  230962 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  230964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  230969 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  230974 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  230977 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  230981 */   GIR_RootConstrainSelectedInstOperands,
     /*  230982 */   // GIR_Coverage, 29648,
     /*  230982 */   GIR_EraseRootFromParent_Done,
     /*  230983 */ // Label 3319: @230983
     /*  230983 */ GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(231042), // Rule ID 29649 //
     /*  230988 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  230991 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  230994 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  230999 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231007 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231011 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231018 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231018 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231021 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231033 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231036 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231040 */   GIR_RootConstrainSelectedInstOperands,
     /*  231041 */   // GIR_Coverage, 29649,
     /*  231041 */   GIR_EraseRootFromParent_Done,
     /*  231042 */ // Label 3320: @231042
     /*  231042 */ GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(231101), // Rule ID 29650 //
     /*  231047 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  231050 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231058 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231066 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231070 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231077 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231077 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231080 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231095 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231099 */   GIR_RootConstrainSelectedInstOperands,
     /*  231100 */   // GIR_Coverage, 29650,
     /*  231100 */   GIR_EraseRootFromParent_Done,
     /*  231101 */ // Label 3321: @231101
     /*  231101 */ GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(231160), // Rule ID 29651 //
     /*  231106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  231109 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231112 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231117 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231125 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231129 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231136 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231136 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231139 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231146 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231151 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231154 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231158 */   GIR_RootConstrainSelectedInstOperands,
     /*  231159 */   // GIR_Coverage, 29651,
     /*  231159 */   GIR_EraseRootFromParent_Done,
     /*  231160 */ // Label 3322: @231160
     /*  231160 */ GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(231219), // Rule ID 29652 //
     /*  231165 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  231168 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231171 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231176 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231184 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231188 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231195 */   // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231205 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231217 */   GIR_RootConstrainSelectedInstOperands,
     /*  231218 */   // GIR_Coverage, 29652,
     /*  231218 */   GIR_EraseRootFromParent_Done,
     /*  231219 */ // Label 3323: @231219
     /*  231219 */ GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(231278), // Rule ID 29668 //
     /*  231224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  231227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231230 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231235 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231254 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231276 */   GIR_RootConstrainSelectedInstOperands,
     /*  231277 */   // GIR_Coverage, 29668,
     /*  231277 */   GIR_EraseRootFromParent_Done,
     /*  231278 */ // Label 3324: @231278
     /*  231278 */ GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(231337), // Rule ID 29669 //
     /*  231283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  231286 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231294 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231313 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231328 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231331 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231335 */   GIR_RootConstrainSelectedInstOperands,
     /*  231336 */   // GIR_Coverage, 29669,
     /*  231336 */   GIR_EraseRootFromParent_Done,
     /*  231337 */ // Label 3325: @231337
     /*  231337 */ GIM_Try, /*On fail goto*//*Label 3326*/ GIMT_Encode4(231396), // Rule ID 29670 //
     /*  231342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  231345 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231348 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231353 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231361 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231365 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231372 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231390 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231394 */   GIR_RootConstrainSelectedInstOperands,
     /*  231395 */   // GIR_Coverage, 29670,
     /*  231395 */   GIR_EraseRootFromParent_Done,
     /*  231396 */ // Label 3326: @231396
     /*  231396 */ GIM_Try, /*On fail goto*//*Label 3327*/ GIMT_Encode4(231455), // Rule ID 29671 //
     /*  231401 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  231404 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231407 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231412 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231420 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231424 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231431 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231431 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231434 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231446 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231449 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231453 */   GIR_RootConstrainSelectedInstOperands,
     /*  231454 */   // GIR_Coverage, 29671,
     /*  231454 */   GIR_EraseRootFromParent_Done,
     /*  231455 */ // Label 3327: @231455
     /*  231455 */ GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(231514), // Rule ID 29672 //
     /*  231460 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  231463 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231466 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  231471 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  231475 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  231479 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231483 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  231490 */   // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  231490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  231493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  231495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  231500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  231505 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231508 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231512 */   GIR_RootConstrainSelectedInstOperands,
     /*  231513 */   // GIR_Coverage, 29672,
     /*  231513 */   GIR_EraseRootFromParent_Done,
     /*  231514 */ // Label 3328: @231514
     /*  231514 */ GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(231576), // Rule ID 8777 //
     /*  231519 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  231522 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231525 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231537 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231541 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  231545 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  231552 */   // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  231552 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  231555 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  231562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  231567 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231570 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231574 */   GIR_RootConstrainSelectedInstOperands,
     /*  231575 */   // GIR_Coverage, 8777,
     /*  231575 */   GIR_EraseRootFromParent_Done,
     /*  231576 */ // Label 3329: @231576
     /*  231576 */ GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(231643), // Rule ID 8778 //
     /*  231581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  231584 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231587 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231599 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231603 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  231607 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  231614 */   // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  231614 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  231617 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  231624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  231629 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  231637 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231641 */   GIR_RootConstrainSelectedInstOperands,
     /*  231642 */   // GIR_Coverage, 8778,
     /*  231642 */   GIR_EraseRootFromParent_Done,
     /*  231643 */ // Label 3330: @231643
     /*  231643 */ GIM_Try, /*On fail goto*//*Label 3331*/ GIMT_Encode4(231705), // Rule ID 8811 //
     /*  231648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  231651 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231654 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231662 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231666 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231670 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  231674 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  231681 */   // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  231681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  231684 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  231691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  231696 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231699 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231703 */   GIR_RootConstrainSelectedInstOperands,
     /*  231704 */   // GIR_Coverage, 8811,
     /*  231704 */   GIR_EraseRootFromParent_Done,
     /*  231705 */ // Label 3331: @231705
     /*  231705 */ GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(231772), // Rule ID 8812 //
     /*  231710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  231713 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231716 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231724 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231728 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231732 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  231736 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  231743 */   // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  231743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  231746 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  231753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  231758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  231766 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231770 */   GIR_RootConstrainSelectedInstOperands,
     /*  231771 */   // GIR_Coverage, 8812,
     /*  231771 */   GIR_EraseRootFromParent_Done,
     /*  231772 */ // Label 3332: @231772
     /*  231772 */ GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(231826), // Rule ID 8780 //
     /*  231777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  231780 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231783 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231791 */   // MIs[0] sbase
     /*  231791 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  231795 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  231799 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231803 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  231807 */   // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  231807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  231810 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231812 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  231814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231817 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231820 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231824 */   GIR_RootConstrainSelectedInstOperands,
     /*  231825 */   // GIR_Coverage, 8780,
     /*  231825 */   GIR_EraseRootFromParent_Done,
     /*  231826 */ // Label 3333: @231826
     /*  231826 */ GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(231880), // Rule ID 8814 //
     /*  231831 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  231834 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231837 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231845 */   // MIs[0] sbase
     /*  231845 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  231849 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  231853 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231857 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  231861 */   // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  231861 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  231864 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231866 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  231868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231878 */   GIR_RootConstrainSelectedInstOperands,
     /*  231879 */   // GIR_Coverage, 8814,
     /*  231879 */   GIR_EraseRootFromParent_Done,
     /*  231880 */ // Label 3334: @231880
     /*  231880 */ GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(231938), // Rule ID 8782 //
     /*  231885 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  231888 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231891 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231899 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231903 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231907 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  231914 */   // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  231914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  231917 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  231924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  231929 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231932 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231936 */   GIR_RootConstrainSelectedInstOperands,
     /*  231937 */   // GIR_Coverage, 8782,
     /*  231937 */   GIR_EraseRootFromParent_Done,
     /*  231938 */ // Label 3335: @231938
     /*  231938 */ GIM_Try, /*On fail goto*//*Label 3336*/ GIMT_Encode4(232001), // Rule ID 8783 //
     /*  231943 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  231946 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  231949 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  231953 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  231957 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  231961 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  231965 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  231972 */   // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  231972 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  231975 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  231977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  231982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  231987 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  231990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  231995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  231999 */   GIR_RootConstrainSelectedInstOperands,
     /*  232000 */   // GIR_Coverage, 8783,
     /*  232000 */   GIR_EraseRootFromParent_Done,
     /*  232001 */ // Label 3336: @232001
     /*  232001 */ GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(232059), // Rule ID 8816 //
     /*  232006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  232009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232012 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232020 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232024 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232028 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  232035 */   // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  232035 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  232038 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  232045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232050 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232053 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232057 */   GIR_RootConstrainSelectedInstOperands,
     /*  232058 */   // GIR_Coverage, 8816,
     /*  232058 */   GIR_EraseRootFromParent_Done,
     /*  232059 */ // Label 3337: @232059
     /*  232059 */ GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(232122), // Rule ID 8817 //
     /*  232064 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  232067 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232070 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232082 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  232093 */   // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  232093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  232096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  232103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  232116 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232120 */   GIR_RootConstrainSelectedInstOperands,
     /*  232121 */   // GIR_Coverage, 8817,
     /*  232121 */   GIR_EraseRootFromParent_Done,
     /*  232122 */ // Label 3338: @232122
     /*  232122 */ GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(232172), // Rule ID 8785 //
     /*  232127 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  232130 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232133 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232141 */   // MIs[0] sbase
     /*  232141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  232145 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  232149 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232153 */   // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  232153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  232156 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232158 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  232160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232170 */   GIR_RootConstrainSelectedInstOperands,
     /*  232171 */   // GIR_Coverage, 8785,
     /*  232171 */   GIR_EraseRootFromParent_Done,
     /*  232172 */ // Label 3339: @232172
     /*  232172 */ GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(232222), // Rule ID 8819 //
     /*  232177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  232180 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232183 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232191 */   // MIs[0] sbase
     /*  232191 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  232195 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  232199 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232203 */   // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  232203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  232206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232208 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  232210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232213 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232216 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232220 */   GIR_RootConstrainSelectedInstOperands,
     /*  232221 */   // GIR_Coverage, 8819,
     /*  232221 */   GIR_EraseRootFromParent_Done,
     /*  232222 */ // Label 3340: @232222
     /*  232222 */ GIM_Try, /*On fail goto*//*Label 3341*/ GIMT_Encode4(232280), // Rule ID 8788 //
     /*  232227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  232230 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232233 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232245 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  232256 */   // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  232256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  232259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  232266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232271 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232278 */   GIR_RootConstrainSelectedInstOperands,
     /*  232279 */   // GIR_Coverage, 8788,
     /*  232279 */   GIR_EraseRootFromParent_Done,
     /*  232280 */ // Label 3341: @232280
     /*  232280 */ GIM_Try, /*On fail goto*//*Label 3342*/ GIMT_Encode4(232343), // Rule ID 8789 //
     /*  232285 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  232288 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232291 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232295 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232299 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232303 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232307 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  232314 */   // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  232314 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  232317 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  232324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232329 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  232337 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232341 */   GIR_RootConstrainSelectedInstOperands,
     /*  232342 */   // GIR_Coverage, 8789,
     /*  232342 */   GIR_EraseRootFromParent_Done,
     /*  232343 */ // Label 3342: @232343
     /*  232343 */ GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(232401), // Rule ID 8822 //
     /*  232348 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  232351 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232354 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232362 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232366 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232370 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  232377 */   // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  232377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  232380 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  232387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232392 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232395 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232399 */   GIR_RootConstrainSelectedInstOperands,
     /*  232400 */   // GIR_Coverage, 8822,
     /*  232400 */   GIR_EraseRootFromParent_Done,
     /*  232401 */ // Label 3343: @232401
     /*  232401 */ GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(232464), // Rule ID 8823 //
     /*  232406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  232409 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232412 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232420 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232424 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232428 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  232435 */   // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  232435 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  232438 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  232445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232450 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  232458 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232462 */   GIR_RootConstrainSelectedInstOperands,
     /*  232463 */   // GIR_Coverage, 8823,
     /*  232463 */   GIR_EraseRootFromParent_Done,
     /*  232464 */ // Label 3344: @232464
     /*  232464 */ GIM_Try, /*On fail goto*//*Label 3345*/ GIMT_Encode4(232511), // Rule ID 8791 //
     /*  232469 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232472 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232480 */   // MIs[0] sbase
     /*  232480 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  232484 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  232488 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232492 */   // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  232492 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  232495 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232497 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  232499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232502 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232505 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232509 */   GIR_RootConstrainSelectedInstOperands,
     /*  232510 */   // GIR_Coverage, 8791,
     /*  232510 */   GIR_EraseRootFromParent_Done,
     /*  232511 */ // Label 3345: @232511
     /*  232511 */ GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(232558), // Rule ID 8825 //
     /*  232516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232519 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  232523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  232527 */   // MIs[0] sbase
     /*  232527 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  232531 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  232535 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  232539 */   // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  232539 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  232542 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  232544 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  232546 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232549 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232552 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232556 */   GIR_RootConstrainSelectedInstOperands,
     /*  232557 */   // GIR_Coverage, 8825,
     /*  232557 */   GIR_EraseRootFromParent_Done,
     /*  232558 */ // Label 3346: @232558
     /*  232558 */ GIM_Try, /*On fail goto*//*Label 3347*/ GIMT_Encode4(232621), // Rule ID 25336 //
     /*  232563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  232566 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232578 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232589 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  232592 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232609 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232619 */   GIR_RootConstrainSelectedInstOperands,
     /*  232620 */   // GIR_Coverage, 25336,
     /*  232620 */   GIR_EraseRootFromParent_Done,
     /*  232621 */ // Label 3347: @232621
     /*  232621 */ GIM_Try, /*On fail goto*//*Label 3348*/ GIMT_Encode4(232684), // Rule ID 25337 //
     /*  232626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  232629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232632 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232645 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232652 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232652 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  232655 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232672 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232678 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232682 */   GIR_RootConstrainSelectedInstOperands,
     /*  232683 */   // GIR_Coverage, 25337,
     /*  232683 */   GIR_EraseRootFromParent_Done,
     /*  232684 */ // Label 3348: @232684
     /*  232684 */ GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(232747), // Rule ID 25338 //
     /*  232689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  232692 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232700 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232704 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232708 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232715 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232715 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  232718 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232735 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232738 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232745 */   GIR_RootConstrainSelectedInstOperands,
     /*  232746 */   // GIR_Coverage, 25338,
     /*  232746 */   GIR_EraseRootFromParent_Done,
     /*  232747 */ // Label 3349: @232747
     /*  232747 */ GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(232810), // Rule ID 25339 //
     /*  232752 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  232755 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232758 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232778 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  232781 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232804 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232808 */   GIR_RootConstrainSelectedInstOperands,
     /*  232809 */   // GIR_Coverage, 25339,
     /*  232809 */   GIR_EraseRootFromParent_Done,
     /*  232810 */ // Label 3350: @232810
     /*  232810 */ GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(232873), // Rule ID 25340 //
     /*  232815 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  232818 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232821 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232826 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232830 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232834 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232841 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  232844 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232861 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232864 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232867 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232871 */   GIR_RootConstrainSelectedInstOperands,
     /*  232872 */   // GIR_Coverage, 25340,
     /*  232872 */   GIR_EraseRootFromParent_Done,
     /*  232873 */ // Label 3351: @232873
     /*  232873 */ GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(232936), // Rule ID 25346 //
     /*  232878 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  232881 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232884 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232897 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232904 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  232907 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232934 */   GIR_RootConstrainSelectedInstOperands,
     /*  232935 */   // GIR_Coverage, 25346,
     /*  232935 */   GIR_EraseRootFromParent_Done,
     /*  232936 */ // Label 3352: @232936
     /*  232936 */ GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(232999), // Rule ID 25347 //
     /*  232941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  232944 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  232947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  232952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  232956 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  232960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  232967 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  232967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  232970 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  232972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  232977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  232982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  232987 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232990 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  232993 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  232997 */   GIR_RootConstrainSelectedInstOperands,
     /*  232998 */   // GIR_Coverage, 25347,
     /*  232998 */   GIR_EraseRootFromParent_Done,
     /*  232999 */ // Label 3353: @232999
     /*  232999 */ GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(233062), // Rule ID 25348 //
     /*  233004 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  233007 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233010 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233015 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233019 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233023 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  233030 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  233030 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  233033 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  233035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  233040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  233045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233050 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233053 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233056 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233060 */   GIR_RootConstrainSelectedInstOperands,
     /*  233061 */   // GIR_Coverage, 25348,
     /*  233061 */   GIR_EraseRootFromParent_Done,
     /*  233062 */ // Label 3354: @233062
     /*  233062 */ GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(233125), // Rule ID 25349 //
     /*  233067 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  233070 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233082 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  233093 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  233093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  233096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  233098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  233103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  233108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233113 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233123 */   GIR_RootConstrainSelectedInstOperands,
     /*  233124 */   // GIR_Coverage, 25349,
     /*  233124 */   GIR_EraseRootFromParent_Done,
     /*  233125 */ // Label 3355: @233125
     /*  233125 */ GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(233188), // Rule ID 25350 //
     /*  233130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  233133 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233141 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233145 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233149 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  233156 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  233156 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  233159 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  233161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  233166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  233171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233176 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233179 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233182 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233186 */   GIR_RootConstrainSelectedInstOperands,
     /*  233187 */   // GIR_Coverage, 25350,
     /*  233187 */   GIR_EraseRootFromParent_Done,
     /*  233188 */ // Label 3356: @233188
     /*  233188 */ GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(233250), // Rule ID 14362 //
     /*  233193 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  233196 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233199 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233219 */   // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233222 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233244 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233248 */   GIR_RootConstrainSelectedInstOperands,
     /*  233249 */   // GIR_Coverage, 14362,
     /*  233249 */   GIR_EraseRootFromParent_Done,
     /*  233250 */ // Label 3357: @233250
     /*  233250 */ GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(233312), // Rule ID 14363 //
     /*  233255 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  233258 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233261 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233274 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233281 */   // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233281 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233284 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233306 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233310 */   GIR_RootConstrainSelectedInstOperands,
     /*  233311 */   // GIR_Coverage, 14363,
     /*  233311 */   GIR_EraseRootFromParent_Done,
     /*  233312 */ // Label 3358: @233312
     /*  233312 */ GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(233374), // Rule ID 14364 //
     /*  233317 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  233320 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233323 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233343 */   // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233372 */   GIR_RootConstrainSelectedInstOperands,
     /*  233373 */   // GIR_Coverage, 14364,
     /*  233373 */   GIR_EraseRootFromParent_Done,
     /*  233374 */ // Label 3359: @233374
     /*  233374 */ GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(233436), // Rule ID 14365 //
     /*  233379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  233382 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233385 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233394 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233398 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233405 */   // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233434 */   GIR_RootConstrainSelectedInstOperands,
     /*  233435 */   // GIR_Coverage, 14365,
     /*  233435 */   GIR_EraseRootFromParent_Done,
     /*  233436 */ // Label 3360: @233436
     /*  233436 */ GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(233498), // Rule ID 14366 //
     /*  233441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  233444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233456 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233460 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233467 */   // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233492 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233496 */   GIR_RootConstrainSelectedInstOperands,
     /*  233497 */   // GIR_Coverage, 14366,
     /*  233497 */   GIR_EraseRootFromParent_Done,
     /*  233498 */ // Label 3361: @233498
     /*  233498 */ GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(233560), // Rule ID 14392 //
     /*  233503 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  233506 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233522 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233529 */   // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233554 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233558 */   GIR_RootConstrainSelectedInstOperands,
     /*  233559 */   // GIR_Coverage, 14392,
     /*  233559 */   GIR_EraseRootFromParent_Done,
     /*  233560 */ // Label 3362: @233560
     /*  233560 */ GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(233622), // Rule ID 14393 //
     /*  233565 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  233568 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233571 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233591 */   // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233594 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233616 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233620 */   GIR_RootConstrainSelectedInstOperands,
     /*  233621 */   // GIR_Coverage, 14393,
     /*  233621 */   GIR_EraseRootFromParent_Done,
     /*  233622 */ // Label 3363: @233622
     /*  233622 */ GIM_Try, /*On fail goto*//*Label 3364*/ GIMT_Encode4(233684), // Rule ID 14394 //
     /*  233627 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  233630 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233633 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233653 */   // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233656 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233678 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233682 */   GIR_RootConstrainSelectedInstOperands,
     /*  233683 */   // GIR_Coverage, 14394,
     /*  233683 */   GIR_EraseRootFromParent_Done,
     /*  233684 */ // Label 3364: @233684
     /*  233684 */ GIM_Try, /*On fail goto*//*Label 3365*/ GIMT_Encode4(233746), // Rule ID 14395 //
     /*  233689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  233692 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233700 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233704 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233708 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233715 */   // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233715 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233718 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233740 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233744 */   GIR_RootConstrainSelectedInstOperands,
     /*  233745 */   // GIR_Coverage, 14395,
     /*  233745 */   GIR_EraseRootFromParent_Done,
     /*  233746 */ // Label 3365: @233746
     /*  233746 */ GIM_Try, /*On fail goto*//*Label 3366*/ GIMT_Encode4(233808), // Rule ID 14396 //
     /*  233751 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  233754 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233757 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233762 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233766 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233770 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  233777 */   // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  233777 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  233780 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  233787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  233792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  233797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  233802 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233806 */   GIR_RootConstrainSelectedInstOperands,
     /*  233807 */   // GIR_Coverage, 14396,
     /*  233807 */   GIR_EraseRootFromParent_Done,
     /*  233808 */ // Label 3366: @233808
     /*  233808 */ GIM_Try, /*On fail goto*//*Label 3367*/ GIMT_Encode4(233863), // Rule ID 14357 //
     /*  233813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  233816 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233819 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233832 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  233839 */   // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  233839 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  233842 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  233849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  233854 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233861 */   GIR_RootConstrainSelectedInstOperands,
     /*  233862 */   // GIR_Coverage, 14357,
     /*  233862 */   GIR_EraseRootFromParent_Done,
     /*  233863 */ // Label 3367: @233863
     /*  233863 */ GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(233918), // Rule ID 14358 //
     /*  233868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  233871 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233874 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233883 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233887 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  233894 */   // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  233894 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  233897 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  233904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  233909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233912 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233916 */   GIR_RootConstrainSelectedInstOperands,
     /*  233917 */   // GIR_Coverage, 14358,
     /*  233917 */   GIR_EraseRootFromParent_Done,
     /*  233918 */ // Label 3368: @233918
     /*  233918 */ GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(233973), // Rule ID 14359 //
     /*  233923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  233926 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233938 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233942 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  233949 */   // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  233949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  233952 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  233954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  233959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  233964 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  233967 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  233971 */   GIR_RootConstrainSelectedInstOperands,
     /*  233972 */   // GIR_Coverage, 14359,
     /*  233972 */   GIR_EraseRootFromParent_Done,
     /*  233973 */ // Label 3369: @233973
     /*  233973 */ GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(234028), // Rule ID 14360 //
     /*  233978 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  233981 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  233984 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  233989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  233993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  233997 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234004 */   // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234004 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234007 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234026 */   GIR_RootConstrainSelectedInstOperands,
     /*  234027 */   // GIR_Coverage, 14360,
     /*  234027 */   GIR_EraseRootFromParent_Done,
     /*  234028 */ // Label 3370: @234028
     /*  234028 */ GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(234083), // Rule ID 14361 //
     /*  234033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  234036 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234039 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234052 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234059 */   // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234062 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234081 */   GIR_RootConstrainSelectedInstOperands,
     /*  234082 */   // GIR_Coverage, 14361,
     /*  234082 */   GIR_EraseRootFromParent_Done,
     /*  234083 */ // Label 3371: @234083
     /*  234083 */ GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(234138), // Rule ID 14387 //
     /*  234088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  234091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234103 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234107 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234114 */   // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234114 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234117 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234132 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234136 */   GIR_RootConstrainSelectedInstOperands,
     /*  234137 */   // GIR_Coverage, 14387,
     /*  234137 */   GIR_EraseRootFromParent_Done,
     /*  234138 */ // Label 3372: @234138
     /*  234138 */ GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(234193), // Rule ID 14388 //
     /*  234143 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  234146 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234149 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234158 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234162 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234169 */   // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234191 */   GIR_RootConstrainSelectedInstOperands,
     /*  234192 */   // GIR_Coverage, 14388,
     /*  234192 */   GIR_EraseRootFromParent_Done,
     /*  234193 */ // Label 3373: @234193
     /*  234193 */ GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(234248), // Rule ID 14389 //
     /*  234198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  234201 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234204 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234209 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234217 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234224 */   // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234227 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234246 */   GIR_RootConstrainSelectedInstOperands,
     /*  234247 */   // GIR_Coverage, 14389,
     /*  234247 */   GIR_EraseRootFromParent_Done,
     /*  234248 */ // Label 3374: @234248
     /*  234248 */ GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(234303), // Rule ID 14390 //
     /*  234253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  234256 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234259 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234279 */   // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234294 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234297 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234301 */   GIR_RootConstrainSelectedInstOperands,
     /*  234302 */   // GIR_Coverage, 14390,
     /*  234302 */   GIR_EraseRootFromParent_Done,
     /*  234303 */ // Label 3375: @234303
     /*  234303 */ GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(234358), // Rule ID 14391 //
     /*  234308 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  234311 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234314 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234323 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234327 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  234334 */   // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  234334 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  234337 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  234344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234349 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234352 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234356 */   GIR_RootConstrainSelectedInstOperands,
     /*  234357 */   // GIR_Coverage, 14391,
     /*  234357 */   GIR_EraseRootFromParent_Done,
     /*  234358 */ // Label 3376: @234358
     /*  234358 */ GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(234413), // Rule ID 14352 //
     /*  234363 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  234366 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234369 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234378 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234389 */   // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234392 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234404 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234411 */   GIR_RootConstrainSelectedInstOperands,
     /*  234412 */   // GIR_Coverage, 14352,
     /*  234412 */   GIR_EraseRootFromParent_Done,
     /*  234413 */ // Label 3377: @234413
     /*  234413 */ GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(234468), // Rule ID 14353 //
     /*  234418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  234421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234424 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234429 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234433 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234437 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234444 */   // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234444 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234447 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234459 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234466 */   GIR_RootConstrainSelectedInstOperands,
     /*  234467 */   // GIR_Coverage, 14353,
     /*  234467 */   GIR_EraseRootFromParent_Done,
     /*  234468 */ // Label 3378: @234468
     /*  234468 */ GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(234523), // Rule ID 14354 //
     /*  234473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  234476 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234488 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234492 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234499 */   // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234502 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234514 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234517 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234521 */   GIR_RootConstrainSelectedInstOperands,
     /*  234522 */   // GIR_Coverage, 14354,
     /*  234522 */   GIR_EraseRootFromParent_Done,
     /*  234523 */ // Label 3379: @234523
     /*  234523 */ GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(234578), // Rule ID 14355 //
     /*  234528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  234531 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234534 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234543 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234547 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234554 */   // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234554 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234557 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234576 */   GIR_RootConstrainSelectedInstOperands,
     /*  234577 */   // GIR_Coverage, 14355,
     /*  234577 */   GIR_EraseRootFromParent_Done,
     /*  234578 */ // Label 3380: @234578
     /*  234578 */ GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(234633), // Rule ID 14356 //
     /*  234583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  234586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234589 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234609 */   // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234612 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234624 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234627 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234631 */   GIR_RootConstrainSelectedInstOperands,
     /*  234632 */   // GIR_Coverage, 14356,
     /*  234632 */   GIR_EraseRootFromParent_Done,
     /*  234633 */ // Label 3381: @234633
     /*  234633 */ GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(234688), // Rule ID 14382 //
     /*  234638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  234641 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234644 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234653 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234657 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234664 */   // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234667 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234679 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234682 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234686 */   GIR_RootConstrainSelectedInstOperands,
     /*  234687 */   // GIR_Coverage, 14382,
     /*  234687 */   GIR_EraseRootFromParent_Done,
     /*  234688 */ // Label 3382: @234688
     /*  234688 */ GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(234743), // Rule ID 14383 //
     /*  234693 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  234696 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234699 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234719 */   // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234722 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234741 */   GIR_RootConstrainSelectedInstOperands,
     /*  234742 */   // GIR_Coverage, 14383,
     /*  234742 */   GIR_EraseRootFromParent_Done,
     /*  234743 */ // Label 3383: @234743
     /*  234743 */ GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(234798), // Rule ID 14384 //
     /*  234748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  234751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234774 */   // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234789 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234792 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234796 */   GIR_RootConstrainSelectedInstOperands,
     /*  234797 */   // GIR_Coverage, 14384,
     /*  234797 */   GIR_EraseRootFromParent_Done,
     /*  234798 */ // Label 3384: @234798
     /*  234798 */ GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(234853), // Rule ID 14385 //
     /*  234803 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  234806 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234818 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234822 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234829 */   // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234844 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234851 */   GIR_RootConstrainSelectedInstOperands,
     /*  234852 */   // GIR_Coverage, 14385,
     /*  234852 */   GIR_EraseRootFromParent_Done,
     /*  234853 */ // Label 3385: @234853
     /*  234853 */ GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(234908), // Rule ID 14386 //
     /*  234858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  234861 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  234869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234877 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  234884 */   // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  234884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  234887 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  234889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  234894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  234899 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234902 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234906 */   GIR_RootConstrainSelectedInstOperands,
     /*  234907 */   // GIR_Coverage, 14386,
     /*  234907 */   GIR_EraseRootFromParent_Done,
     /*  234908 */ // Label 3386: @234908
     /*  234908 */ GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(234978), // Rule ID 15568 //
     /*  234913 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  234916 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234919 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  234926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  234930 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  234934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  234941 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  234941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  234944 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  234946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  234951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  234956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  234961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  234966 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234969 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  234972 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  234976 */   GIR_RootConstrainSelectedInstOperands,
     /*  234977 */   // GIR_Coverage, 15568,
     /*  234977 */   GIR_EraseRootFromParent_Done,
     /*  234978 */ // Label 3387: @234978
     /*  234978 */ GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(235048), // Rule ID 15569 //
     /*  234983 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  234986 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  234989 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  234996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235000 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235004 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235011 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235014 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235036 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235046 */   GIR_RootConstrainSelectedInstOperands,
     /*  235047 */   // GIR_Coverage, 15569,
     /*  235047 */   GIR_EraseRootFromParent_Done,
     /*  235048 */ // Label 3388: @235048
     /*  235048 */ GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(235118), // Rule ID 15570 //
     /*  235053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  235056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235059 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235081 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235106 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235116 */   GIR_RootConstrainSelectedInstOperands,
     /*  235117 */   // GIR_Coverage, 15570,
     /*  235117 */   GIR_EraseRootFromParent_Done,
     /*  235118 */ // Label 3389: @235118
     /*  235118 */ GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(235188), // Rule ID 15571 //
     /*  235123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  235126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235151 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235154 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235176 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235179 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235182 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235186 */   GIR_RootConstrainSelectedInstOperands,
     /*  235187 */   // GIR_Coverage, 15571,
     /*  235187 */   GIR_EraseRootFromParent_Done,
     /*  235188 */ // Label 3390: @235188
     /*  235188 */ GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(235258), // Rule ID 15572 //
     /*  235193 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  235196 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235199 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235210 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235214 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235221 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235252 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235256 */   GIR_RootConstrainSelectedInstOperands,
     /*  235257 */   // GIR_Coverage, 15572,
     /*  235257 */   GIR_EraseRootFromParent_Done,
     /*  235258 */ // Label 3391: @235258
     /*  235258 */ GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(235328), // Rule ID 15578 //
     /*  235263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  235266 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235291 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  235294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235316 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235319 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235322 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235326 */   GIR_RootConstrainSelectedInstOperands,
     /*  235327 */   // GIR_Coverage, 15578,
     /*  235327 */   GIR_EraseRootFromParent_Done,
     /*  235328 */ // Label 3392: @235328
     /*  235328 */ GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(235398), // Rule ID 15579 //
     /*  235333 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  235336 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235339 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235350 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235354 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235361 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  235364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235386 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235389 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235392 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235396 */   GIR_RootConstrainSelectedInstOperands,
     /*  235397 */   // GIR_Coverage, 15579,
     /*  235397 */   GIR_EraseRootFromParent_Done,
     /*  235398 */ // Label 3393: @235398
     /*  235398 */ GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(235468), // Rule ID 15580 //
     /*  235403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  235406 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235409 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235420 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235424 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235431 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235431 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  235434 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235456 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235459 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235466 */   GIR_RootConstrainSelectedInstOperands,
     /*  235467 */   // GIR_Coverage, 15580,
     /*  235467 */   GIR_EraseRootFromParent_Done,
     /*  235468 */ // Label 3394: @235468
     /*  235468 */ GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(235538), // Rule ID 15581 //
     /*  235473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  235476 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235490 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235494 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235501 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  235504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235526 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235536 */   GIR_RootConstrainSelectedInstOperands,
     /*  235537 */   // GIR_Coverage, 15581,
     /*  235537 */   GIR_EraseRootFromParent_Done,
     /*  235538 */ // Label 3395: @235538
     /*  235538 */ GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(235608), // Rule ID 15582 //
     /*  235543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  235546 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235549 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235560 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235564 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235571 */   // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  235574 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235606 */   GIR_RootConstrainSelectedInstOperands,
     /*  235607 */   // GIR_Coverage, 15582,
     /*  235607 */   GIR_EraseRootFromParent_Done,
     /*  235608 */ // Label 3396: @235608
     /*  235608 */ GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(235678), // Rule ID 15588 //
     /*  235613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  235616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235626 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235630 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235641 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235666 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235669 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235672 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235676 */   GIR_RootConstrainSelectedInstOperands,
     /*  235677 */   // GIR_Coverage, 15588,
     /*  235677 */   GIR_EraseRootFromParent_Done,
     /*  235678 */ // Label 3397: @235678
     /*  235678 */ GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(235748), // Rule ID 15589 //
     /*  235683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  235686 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235700 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235704 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235711 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235711 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235714 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235736 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235739 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235742 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235746 */   GIR_RootConstrainSelectedInstOperands,
     /*  235747 */   // GIR_Coverage, 15589,
     /*  235747 */   GIR_EraseRootFromParent_Done,
     /*  235748 */ // Label 3398: @235748
     /*  235748 */ GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(235818), // Rule ID 15590 //
     /*  235753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  235756 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235759 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235781 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235784 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235806 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235809 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235812 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235816 */   GIR_RootConstrainSelectedInstOperands,
     /*  235817 */   // GIR_Coverage, 15590,
     /*  235817 */   GIR_EraseRootFromParent_Done,
     /*  235818 */ // Label 3399: @235818
     /*  235818 */ GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(235888), // Rule ID 15591 //
     /*  235823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  235826 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235851 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235854 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235886 */   GIR_RootConstrainSelectedInstOperands,
     /*  235887 */   // GIR_Coverage, 15591,
     /*  235887 */   GIR_EraseRootFromParent_Done,
     /*  235888 */ // Label 3400: @235888
     /*  235888 */ GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(235958), // Rule ID 15592 //
     /*  235893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  235896 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235899 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235910 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235914 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235921 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  235924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  235931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  235936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  235941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  235946 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  235952 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  235956 */   GIR_RootConstrainSelectedInstOperands,
     /*  235957 */   // GIR_Coverage, 15592,
     /*  235957 */   GIR_EraseRootFromParent_Done,
     /*  235958 */ // Label 3401: @235958
     /*  235958 */ GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(236028), // Rule ID 15598 //
     /*  235963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  235966 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  235969 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  235976 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  235980 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  235984 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  235991 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  235991 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  235994 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  235996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236026 */   GIR_RootConstrainSelectedInstOperands,
     /*  236027 */   // GIR_Coverage, 15598,
     /*  236027 */   GIR_EraseRootFromParent_Done,
     /*  236028 */ // Label 3402: @236028
     /*  236028 */ GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(236098), // Rule ID 15599 //
     /*  236033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  236036 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236039 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  236046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236050 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236054 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  236061 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  236061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  236064 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236092 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236096 */   GIR_RootConstrainSelectedInstOperands,
     /*  236097 */   // GIR_Coverage, 15599,
     /*  236097 */   GIR_EraseRootFromParent_Done,
     /*  236098 */ // Label 3403: @236098
     /*  236098 */ GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(236168), // Rule ID 15600 //
     /*  236103 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  236106 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236109 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  236116 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236120 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236124 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  236131 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  236131 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  236134 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236146 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236151 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236156 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236162 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236166 */   GIR_RootConstrainSelectedInstOperands,
     /*  236167 */   // GIR_Coverage, 15600,
     /*  236167 */   GIR_EraseRootFromParent_Done,
     /*  236168 */ // Label 3404: @236168
     /*  236168 */ GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(236238), // Rule ID 15601 //
     /*  236173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  236176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236179 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  236186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236190 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236194 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  236201 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  236201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  236204 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236216 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236226 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236229 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236232 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236236 */   GIR_RootConstrainSelectedInstOperands,
     /*  236237 */   // GIR_Coverage, 15601,
     /*  236237 */   GIR_EraseRootFromParent_Done,
     /*  236238 */ // Label 3405: @236238
     /*  236238 */ GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(236308), // Rule ID 15602 //
     /*  236243 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  236246 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236249 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  236256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  236271 */   // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  236271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  236274 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236306 */   GIR_RootConstrainSelectedInstOperands,
     /*  236307 */   // GIR_Coverage, 15602,
     /*  236307 */   GIR_EraseRootFromParent_Done,
     /*  236308 */ // Label 3406: @236308
     /*  236308 */ GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(236376), // Rule ID 25331 //
     /*  236313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  236316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236328 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236332 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236339 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236339 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
     /*  236342 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236364 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236367 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236370 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236374 */   GIR_RootConstrainSelectedInstOperands,
     /*  236375 */   // GIR_Coverage, 25331,
     /*  236375 */   GIR_EraseRootFromParent_Done,
     /*  236376 */ // Label 3407: @236376
     /*  236376 */ GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(236444), // Rule ID 25332 //
     /*  236381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  236384 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236387 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236407 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
     /*  236410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236432 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236435 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236438 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236442 */   GIR_RootConstrainSelectedInstOperands,
     /*  236443 */   // GIR_Coverage, 25332,
     /*  236443 */   GIR_EraseRootFromParent_Done,
     /*  236444 */ // Label 3408: @236444
     /*  236444 */ GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(236512), // Rule ID 25333 //
     /*  236449 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  236452 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236455 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236464 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236468 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236475 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236475 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
     /*  236478 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236500 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236503 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236506 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236510 */   GIR_RootConstrainSelectedInstOperands,
     /*  236511 */   // GIR_Coverage, 25333,
     /*  236511 */   GIR_EraseRootFromParent_Done,
     /*  236512 */ // Label 3409: @236512
     /*  236512 */ GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(236580), // Rule ID 25334 //
     /*  236517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  236520 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236523 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236543 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
     /*  236546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236578 */   GIR_RootConstrainSelectedInstOperands,
     /*  236579 */   // GIR_Coverage, 25334,
     /*  236579 */   GIR_EraseRootFromParent_Done,
     /*  236580 */ // Label 3410: @236580
     /*  236580 */ GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(236648), // Rule ID 25335 //
     /*  236585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  236588 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236600 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236604 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236611 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
     /*  236614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236636 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236639 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236642 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236646 */   GIR_RootConstrainSelectedInstOperands,
     /*  236647 */   // GIR_Coverage, 25335,
     /*  236647 */   GIR_EraseRootFromParent_Done,
     /*  236648 */ // Label 3411: @236648
     /*  236648 */ GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(236716), // Rule ID 25341 //
     /*  236653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  236656 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236659 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236664 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236668 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236672 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236679 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
     /*  236682 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236704 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236707 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236710 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236714 */   GIR_RootConstrainSelectedInstOperands,
     /*  236715 */   // GIR_Coverage, 25341,
     /*  236715 */   GIR_EraseRootFromParent_Done,
     /*  236716 */ // Label 3412: @236716
     /*  236716 */ GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(236784), // Rule ID 25342 //
     /*  236721 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  236724 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236727 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236736 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236740 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236747 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236747 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
     /*  236750 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236757 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236772 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236775 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236778 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236782 */   GIR_RootConstrainSelectedInstOperands,
     /*  236783 */   // GIR_Coverage, 25342,
     /*  236783 */   GIR_EraseRootFromParent_Done,
     /*  236784 */ // Label 3413: @236784
     /*  236784 */ GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(236852), // Rule ID 25343 //
     /*  236789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  236792 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236795 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236808 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236815 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236815 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
     /*  236818 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236843 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236846 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236850 */   GIR_RootConstrainSelectedInstOperands,
     /*  236851 */   // GIR_Coverage, 25343,
     /*  236851 */   GIR_EraseRootFromParent_Done,
     /*  236852 */ // Label 3414: @236852
     /*  236852 */ GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(236920), // Rule ID 25344 //
     /*  236857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  236860 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236872 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236876 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236883 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236883 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
     /*  236886 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236908 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236911 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236914 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236918 */   GIR_RootConstrainSelectedInstOperands,
     /*  236919 */   // GIR_Coverage, 25344,
     /*  236919 */   GIR_EraseRootFromParent_Done,
     /*  236920 */ // Label 3415: @236920
     /*  236920 */ GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(236988), // Rule ID 25345 //
     /*  236925 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  236928 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236931 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  236936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  236940 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  236944 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  236951 */   // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  236951 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
     /*  236954 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  236956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  236961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  236966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  236971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  236976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  236982 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  236986 */   GIR_RootConstrainSelectedInstOperands,
     /*  236987 */   // GIR_Coverage, 25345,
     /*  236987 */   GIR_EraseRootFromParent_Done,
     /*  236988 */ // Label 3416: @236988
     /*  236988 */ GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(237052), // Rule ID 29419 //
     /*  236993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  236996 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  236999 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237023 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237026 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237043 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237050 */   GIR_RootConstrainSelectedInstOperands,
     /*  237051 */   // GIR_Coverage, 29419,
     /*  237051 */   GIR_EraseRootFromParent_Done,
     /*  237052 */ // Label 3417: @237052
     /*  237052 */ GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(237116), // Rule ID 29420 //
     /*  237057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  237060 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237063 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237067 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237076 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237080 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237087 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237090 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237107 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237110 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237114 */   GIR_RootConstrainSelectedInstOperands,
     /*  237115 */   // GIR_Coverage, 29420,
     /*  237115 */   GIR_EraseRootFromParent_Done,
     /*  237116 */ // Label 3418: @237116
     /*  237116 */ GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(237180), // Rule ID 29421 //
     /*  237121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  237124 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237127 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237131 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237151 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237154 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237178 */   GIR_RootConstrainSelectedInstOperands,
     /*  237179 */   // GIR_Coverage, 29421,
     /*  237179 */   GIR_EraseRootFromParent_Done,
     /*  237180 */ // Label 3419: @237180
     /*  237180 */ GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(237244), // Rule ID 29422 //
     /*  237185 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  237188 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237191 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237195 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237204 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237208 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237215 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237215 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237218 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237242 */   GIR_RootConstrainSelectedInstOperands,
     /*  237243 */   // GIR_Coverage, 29422,
     /*  237243 */   GIR_EraseRootFromParent_Done,
     /*  237244 */ // Label 3420: @237244
     /*  237244 */ GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(237308), // Rule ID 29423 //
     /*  237249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  237252 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237255 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237259 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237279 */   // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237306 */   GIR_RootConstrainSelectedInstOperands,
     /*  237307 */   // GIR_Coverage, 29423,
     /*  237307 */   GIR_EraseRootFromParent_Done,
     /*  237308 */ // Label 3421: @237308
     /*  237308 */ GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(237372), // Rule ID 29431 //
     /*  237313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  237316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237319 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237323 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237343 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237370 */   GIR_RootConstrainSelectedInstOperands,
     /*  237371 */   // GIR_Coverage, 29431,
     /*  237371 */   GIR_EraseRootFromParent_Done,
     /*  237372 */ // Label 3422: @237372
     /*  237372 */ GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(237436), // Rule ID 29432 //
     /*  237377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  237380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237383 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237387 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237407 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237434 */   GIR_RootConstrainSelectedInstOperands,
     /*  237435 */   // GIR_Coverage, 29432,
     /*  237435 */   GIR_EraseRootFromParent_Done,
     /*  237436 */ // Label 3423: @237436
     /*  237436 */ GIM_Try, /*On fail goto*//*Label 3424*/ GIMT_Encode4(237500), // Rule ID 29433 //
     /*  237441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  237444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237447 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237451 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237471 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237474 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237498 */   GIR_RootConstrainSelectedInstOperands,
     /*  237499 */   // GIR_Coverage, 29433,
     /*  237499 */   GIR_EraseRootFromParent_Done,
     /*  237500 */ // Label 3424: @237500
     /*  237500 */ GIM_Try, /*On fail goto*//*Label 3425*/ GIMT_Encode4(237564), // Rule ID 29434 //
     /*  237505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  237508 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237511 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237515 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237535 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237538 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237562 */   GIR_RootConstrainSelectedInstOperands,
     /*  237563 */   // GIR_Coverage, 29434,
     /*  237563 */   GIR_EraseRootFromParent_Done,
     /*  237564 */ // Label 3425: @237564
     /*  237564 */ GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(237628), // Rule ID 29435 //
     /*  237569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  237572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237575 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  237579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  237584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237588 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237592 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  237599 */   // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  237599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  237602 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  237604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  237609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  237614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  237619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237622 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237626 */   GIR_RootConstrainSelectedInstOperands,
     /*  237627 */   // GIR_Coverage, 29435,
     /*  237627 */   GIR_EraseRootFromParent_Done,
     /*  237628 */ // Label 3426: @237628
     /*  237628 */ GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(237693), // Rule ID 15563 //
     /*  237633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  237636 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237639 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  237646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237650 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237654 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  237661 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  237661 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  237664 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  237666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  237671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  237676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  237681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237684 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237687 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237691 */   GIR_RootConstrainSelectedInstOperands,
     /*  237692 */   // GIR_Coverage, 15563,
     /*  237692 */   GIR_EraseRootFromParent_Done,
     /*  237693 */ // Label 3427: @237693
     /*  237693 */ GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(237758), // Rule ID 15564 //
     /*  237698 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  237701 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237704 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  237711 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237715 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237719 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  237726 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  237726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  237729 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  237731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  237736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  237741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  237746 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237749 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237752 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237756 */   GIR_RootConstrainSelectedInstOperands,
     /*  237757 */   // GIR_Coverage, 15564,
     /*  237757 */   GIR_EraseRootFromParent_Done,
     /*  237758 */ // Label 3428: @237758
     /*  237758 */ GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(237823), // Rule ID 15565 //
     /*  237763 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  237766 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237769 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  237776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237780 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237784 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  237791 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  237791 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  237794 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  237796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  237801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  237806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  237811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237817 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237821 */   GIR_RootConstrainSelectedInstOperands,
     /*  237822 */   // GIR_Coverage, 15565,
     /*  237822 */   GIR_EraseRootFromParent_Done,
     /*  237823 */ // Label 3429: @237823
     /*  237823 */ GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(237888), // Rule ID 15566 //
     /*  237828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  237831 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  237841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237845 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237849 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  237856 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  237856 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  237859 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  237861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  237866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  237871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  237876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237886 */   GIR_RootConstrainSelectedInstOperands,
     /*  237887 */   // GIR_Coverage, 15566,
     /*  237887 */   GIR_EraseRootFromParent_Done,
     /*  237888 */ // Label 3430: @237888
     /*  237888 */ GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(237953), // Rule ID 15567 //
     /*  237893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  237896 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237899 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  237906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237910 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237914 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  237921 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  237921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  237924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  237926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  237931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  237936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  237941 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237944 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  237947 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  237951 */   GIR_RootConstrainSelectedInstOperands,
     /*  237952 */   // GIR_Coverage, 15567,
     /*  237952 */   GIR_EraseRootFromParent_Done,
     /*  237953 */ // Label 3431: @237953
     /*  237953 */ GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(238018), // Rule ID 15573 //
     /*  237958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  237961 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  237964 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  237971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  237975 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  237979 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  237986 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  237986 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  237989 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  237991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  237996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238009 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238012 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238016 */   GIR_RootConstrainSelectedInstOperands,
     /*  238017 */   // GIR_Coverage, 15573,
     /*  238017 */   GIR_EraseRootFromParent_Done,
     /*  238018 */ // Label 3432: @238018
     /*  238018 */ GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(238083), // Rule ID 15574 //
     /*  238023 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  238026 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238029 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238036 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238040 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238044 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238051 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238054 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238081 */   GIR_RootConstrainSelectedInstOperands,
     /*  238082 */   // GIR_Coverage, 15574,
     /*  238082 */   GIR_EraseRootFromParent_Done,
     /*  238083 */ // Label 3433: @238083
     /*  238083 */ GIM_Try, /*On fail goto*//*Label 3434*/ GIMT_Encode4(238148), // Rule ID 15575 //
     /*  238088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  238091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238116 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238146 */   GIR_RootConstrainSelectedInstOperands,
     /*  238147 */   // GIR_Coverage, 15575,
     /*  238147 */   GIR_EraseRootFromParent_Done,
     /*  238148 */ // Label 3434: @238148
     /*  238148 */ GIM_Try, /*On fail goto*//*Label 3435*/ GIMT_Encode4(238213), // Rule ID 15576 //
     /*  238153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  238156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238159 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238170 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238174 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238181 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238201 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238204 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238207 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238211 */   GIR_RootConstrainSelectedInstOperands,
     /*  238212 */   // GIR_Coverage, 15576,
     /*  238212 */   GIR_EraseRootFromParent_Done,
     /*  238213 */ // Label 3435: @238213
     /*  238213 */ GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(238278), // Rule ID 15577 //
     /*  238218 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  238221 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238224 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238235 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238239 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238246 */   // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238246 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238249 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238266 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238276 */   GIR_RootConstrainSelectedInstOperands,
     /*  238277 */   // GIR_Coverage, 15577,
     /*  238277 */   GIR_EraseRootFromParent_Done,
     /*  238278 */ // Label 3436: @238278
     /*  238278 */ GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(238343), // Rule ID 15583 //
     /*  238283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  238286 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238311 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  238314 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238331 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238334 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238337 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238341 */   GIR_RootConstrainSelectedInstOperands,
     /*  238342 */   // GIR_Coverage, 15583,
     /*  238342 */   GIR_EraseRootFromParent_Done,
     /*  238343 */ // Label 3437: @238343
     /*  238343 */ GIM_Try, /*On fail goto*//*Label 3438*/ GIMT_Encode4(238408), // Rule ID 15584 //
     /*  238348 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  238351 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238354 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238376 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  238379 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238396 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238406 */   GIR_RootConstrainSelectedInstOperands,
     /*  238407 */   // GIR_Coverage, 15584,
     /*  238407 */   GIR_EraseRootFromParent_Done,
     /*  238408 */ // Label 3438: @238408
     /*  238408 */ GIM_Try, /*On fail goto*//*Label 3439*/ GIMT_Encode4(238473), // Rule ID 15585 //
     /*  238413 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  238416 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238419 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238426 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238430 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238434 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238441 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238441 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  238444 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238456 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238461 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238464 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238471 */   GIR_RootConstrainSelectedInstOperands,
     /*  238472 */   // GIR_Coverage, 15585,
     /*  238472 */   GIR_EraseRootFromParent_Done,
     /*  238473 */ // Label 3439: @238473
     /*  238473 */ GIM_Try, /*On fail goto*//*Label 3440*/ GIMT_Encode4(238538), // Rule ID 15586 //
     /*  238478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  238481 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238484 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238491 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238495 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238499 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238506 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238506 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  238509 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238526 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238536 */   GIR_RootConstrainSelectedInstOperands,
     /*  238537 */   // GIR_Coverage, 15586,
     /*  238537 */   GIR_EraseRootFromParent_Done,
     /*  238538 */ // Label 3440: @238538
     /*  238538 */ GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(238603), // Rule ID 15587 //
     /*  238543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  238546 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238549 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238560 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238564 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238571 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  238574 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238591 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238594 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238597 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238601 */   GIR_RootConstrainSelectedInstOperands,
     /*  238602 */   // GIR_Coverage, 15587,
     /*  238602 */   GIR_EraseRootFromParent_Done,
     /*  238603 */ // Label 3441: @238603
     /*  238603 */ GIM_Try, /*On fail goto*//*Label 3442*/ GIMT_Encode4(238668), // Rule ID 15593 //
     /*  238608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  238611 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238614 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238625 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238629 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238636 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238639 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238656 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238662 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238666 */   GIR_RootConstrainSelectedInstOperands,
     /*  238667 */   // GIR_Coverage, 15593,
     /*  238667 */   GIR_EraseRootFromParent_Done,
     /*  238668 */ // Label 3442: @238668
     /*  238668 */ GIM_Try, /*On fail goto*//*Label 3443*/ GIMT_Encode4(238733), // Rule ID 15594 //
     /*  238673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  238676 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238679 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238686 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238690 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238694 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238701 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238704 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238731 */   GIR_RootConstrainSelectedInstOperands,
     /*  238732 */   // GIR_Coverage, 15594,
     /*  238732 */   GIR_EraseRootFromParent_Done,
     /*  238733 */ // Label 3443: @238733
     /*  238733 */ GIM_Try, /*On fail goto*//*Label 3444*/ GIMT_Encode4(238798), // Rule ID 15595 //
     /*  238738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  238741 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238744 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238751 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238755 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238759 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238766 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238766 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238769 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238786 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238789 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238792 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238796 */   GIR_RootConstrainSelectedInstOperands,
     /*  238797 */   // GIR_Coverage, 15595,
     /*  238797 */   GIR_EraseRootFromParent_Done,
     /*  238798 */ // Label 3444: @238798
     /*  238798 */ GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(238863), // Rule ID 15596 //
     /*  238803 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  238806 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238820 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238824 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238831 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238834 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238851 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238854 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238861 */   GIR_RootConstrainSelectedInstOperands,
     /*  238862 */   // GIR_Coverage, 15596,
     /*  238862 */   GIR_EraseRootFromParent_Done,
     /*  238863 */ // Label 3445: @238863
     /*  238863 */ GIM_Try, /*On fail goto*//*Label 3446*/ GIMT_Encode4(238928), // Rule ID 15597 //
     /*  238868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  238871 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238874 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  238881 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238885 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238889 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  238896 */   // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  238896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  238899 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  238901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  238906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  238911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  238916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238922 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238926 */   GIR_RootConstrainSelectedInstOperands,
     /*  238927 */   // GIR_Coverage, 15597,
     /*  238927 */   GIR_EraseRootFromParent_Done,
     /*  238928 */ // Label 3446: @238928
     /*  238928 */ GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(238988), // Rule ID 29425 //
     /*  238933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  238936 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  238944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  238948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  238952 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  238959 */   // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  238959 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  238962 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  238964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  238969 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  238974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  238979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  238982 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  238986 */   GIR_RootConstrainSelectedInstOperands,
     /*  238987 */   // GIR_Coverage, 29425,
     /*  238987 */   GIR_EraseRootFromParent_Done,
     /*  238988 */ // Label 3447: @238988
     /*  238988 */ GIM_Try, /*On fail goto*//*Label 3448*/ GIMT_Encode4(239048), // Rule ID 29426 //
     /*  238993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  238996 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  238999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239004 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239008 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239012 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239019 */   // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239019 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239022 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239046 */   GIR_RootConstrainSelectedInstOperands,
     /*  239047 */   // GIR_Coverage, 29426,
     /*  239047 */   GIR_EraseRootFromParent_Done,
     /*  239048 */ // Label 3448: @239048
     /*  239048 */ GIM_Try, /*On fail goto*//*Label 3449*/ GIMT_Encode4(239108), // Rule ID 29427 //
     /*  239053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  239056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239059 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239079 */   // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239082 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239099 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239102 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239106 */   GIR_RootConstrainSelectedInstOperands,
     /*  239107 */   // GIR_Coverage, 29427,
     /*  239107 */   GIR_EraseRootFromParent_Done,
     /*  239108 */ // Label 3449: @239108
     /*  239108 */ GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(239168), // Rule ID 29428 //
     /*  239113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  239116 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239119 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239139 */   // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239162 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239166 */   GIR_RootConstrainSelectedInstOperands,
     /*  239167 */   // GIR_Coverage, 29428,
     /*  239167 */   GIR_EraseRootFromParent_Done,
     /*  239168 */ // Label 3450: @239168
     /*  239168 */ GIM_Try, /*On fail goto*//*Label 3451*/ GIMT_Encode4(239228), // Rule ID 29429 //
     /*  239173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  239176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239179 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239188 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239192 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239199 */   // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239202 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239222 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239226 */   GIR_RootConstrainSelectedInstOperands,
     /*  239227 */   // GIR_Coverage, 29429,
     /*  239227 */   GIR_EraseRootFromParent_Done,
     /*  239228 */ // Label 3451: @239228
     /*  239228 */ GIM_Try, /*On fail goto*//*Label 3452*/ GIMT_Encode4(239288), // Rule ID 29437 //
     /*  239233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  239236 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239252 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239259 */   // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239262 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239279 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239282 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239286 */   GIR_RootConstrainSelectedInstOperands,
     /*  239287 */   // GIR_Coverage, 29437,
     /*  239287 */   GIR_EraseRootFromParent_Done,
     /*  239288 */ // Label 3452: @239288
     /*  239288 */ GIM_Try, /*On fail goto*//*Label 3453*/ GIMT_Encode4(239348), // Rule ID 29438 //
     /*  239293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  239296 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239308 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239312 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239319 */   // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239319 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239322 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239346 */   GIR_RootConstrainSelectedInstOperands,
     /*  239347 */   // GIR_Coverage, 29438,
     /*  239347 */   GIR_EraseRootFromParent_Done,
     /*  239348 */ // Label 3453: @239348
     /*  239348 */ GIM_Try, /*On fail goto*//*Label 3454*/ GIMT_Encode4(239408), // Rule ID 29439 //
     /*  239353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  239356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239368 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239372 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239379 */   // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239379 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239382 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239406 */   GIR_RootConstrainSelectedInstOperands,
     /*  239407 */   // GIR_Coverage, 29439,
     /*  239407 */   GIR_EraseRootFromParent_Done,
     /*  239408 */ // Label 3454: @239408
     /*  239408 */ GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(239468), // Rule ID 29440 //
     /*  239413 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  239416 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239419 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239428 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239432 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239439 */   // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239439 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239442 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239459 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239466 */   GIR_RootConstrainSelectedInstOperands,
     /*  239467 */   // GIR_Coverage, 29440,
     /*  239467 */   GIR_EraseRootFromParent_Done,
     /*  239468 */ // Label 3455: @239468
     /*  239468 */ GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(239528), // Rule ID 29441 //
     /*  239473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  239476 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  239484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239488 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239492 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  239499 */   // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  239499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  239502 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  239509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  239514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  239519 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  239522 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239526 */   GIR_RootConstrainSelectedInstOperands,
     /*  239527 */   // GIR_Coverage, 29441,
     /*  239527 */   GIR_EraseRootFromParent_Done,
     /*  239528 */ // Label 3456: @239528
     /*  239528 */ GIM_Try, /*On fail goto*//*Label 3457*/ GIMT_Encode4(239603), // Rule ID 12593 //
     /*  239533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  239536 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  239539 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  239543 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  239550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  239572 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  239572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  239575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  239582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  239587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  239592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  239597 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239601 */   GIR_RootConstrainSelectedInstOperands,
     /*  239602 */   // GIR_Coverage, 12593,
     /*  239602 */   GIR_EraseRootFromParent_Done,
     /*  239603 */ // Label 3457: @239603
     /*  239603 */ GIM_Try, /*On fail goto*//*Label 3458*/ GIMT_Encode4(239678), // Rule ID 12594 //
     /*  239608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  239611 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  239614 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  239618 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  239625 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239636 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239640 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  239647 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  239647 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  239650 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  239657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  239662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  239667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  239672 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239676 */   GIR_RootConstrainSelectedInstOperands,
     /*  239677 */   // GIR_Coverage, 12594,
     /*  239677 */   GIR_EraseRootFromParent_Done,
     /*  239678 */ // Label 3458: @239678
     /*  239678 */ GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(239753), // Rule ID 12595 //
     /*  239683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  239686 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  239689 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  239693 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  239700 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239707 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239711 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239715 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  239722 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  239722 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  239725 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  239732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  239737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  239742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  239747 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239751 */   GIR_RootConstrainSelectedInstOperands,
     /*  239752 */   // GIR_Coverage, 12595,
     /*  239752 */   GIR_EraseRootFromParent_Done,
     /*  239753 */ // Label 3459: @239753
     /*  239753 */ GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(239828), // Rule ID 12596 //
     /*  239758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  239761 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  239764 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  239768 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  239775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239782 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239786 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239790 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  239797 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  239797 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  239800 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  239807 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  239812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  239817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  239822 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239826 */   GIR_RootConstrainSelectedInstOperands,
     /*  239827 */   // GIR_Coverage, 12596,
     /*  239827 */   GIR_EraseRootFromParent_Done,
     /*  239828 */ // Label 3460: @239828
     /*  239828 */ GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(239903), // Rule ID 12597 //
     /*  239833 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  239836 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  239839 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  239843 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  239850 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239861 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239865 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  239872 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  239872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  239875 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  239882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  239887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  239892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  239897 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239901 */   GIR_RootConstrainSelectedInstOperands,
     /*  239902 */   // GIR_Coverage, 12597,
     /*  239902 */   GIR_EraseRootFromParent_Done,
     /*  239903 */ // Label 3461: @239903
     /*  239903 */ GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(239967), // Rule ID 12303 //
     /*  239908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  239911 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239914 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239929 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  239936 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  239936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  239939 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  239941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  239946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  239951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  239956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  239961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  239965 */   GIR_RootConstrainSelectedInstOperands,
     /*  239966 */   // GIR_Coverage, 12303,
     /*  239966 */   GIR_EraseRootFromParent_Done,
     /*  239967 */ // Label 3462: @239967
     /*  239967 */ GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(240031), // Rule ID 12304 //
     /*  239972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  239975 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  239978 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  239985 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  239989 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  239993 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240000 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240003 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240029 */   GIR_RootConstrainSelectedInstOperands,
     /*  240030 */   // GIR_Coverage, 12304,
     /*  240030 */   GIR_EraseRootFromParent_Done,
     /*  240031 */ // Label 3463: @240031
     /*  240031 */ GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(240095), // Rule ID 12305 //
     /*  240036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  240039 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240042 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240053 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240057 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240064 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240093 */   GIR_RootConstrainSelectedInstOperands,
     /*  240094 */   // GIR_Coverage, 12305,
     /*  240094 */   GIR_EraseRootFromParent_Done,
     /*  240095 */ // Label 3464: @240095
     /*  240095 */ GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(240159), // Rule ID 12306 //
     /*  240100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  240103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240128 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240153 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240157 */   GIR_RootConstrainSelectedInstOperands,
     /*  240158 */   // GIR_Coverage, 12306,
     /*  240158 */   GIR_EraseRootFromParent_Done,
     /*  240159 */ // Label 3465: @240159
     /*  240159 */ GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(240223), // Rule ID 12307 //
     /*  240164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  240167 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240192 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240195 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240221 */   GIR_RootConstrainSelectedInstOperands,
     /*  240222 */   // GIR_Coverage, 12307,
     /*  240222 */   GIR_EraseRootFromParent_Done,
     /*  240223 */ // Label 3466: @240223
     /*  240223 */ GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(240287), // Rule ID 12323 //
     /*  240228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  240231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240256 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240281 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240285 */   GIR_RootConstrainSelectedInstOperands,
     /*  240286 */   // GIR_Coverage, 12323,
     /*  240286 */   GIR_EraseRootFromParent_Done,
     /*  240287 */ // Label 3467: @240287
     /*  240287 */ GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(240351), // Rule ID 12324 //
     /*  240292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  240295 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240298 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240320 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240349 */   GIR_RootConstrainSelectedInstOperands,
     /*  240350 */   // GIR_Coverage, 12324,
     /*  240350 */   GIR_EraseRootFromParent_Done,
     /*  240351 */ // Label 3468: @240351
     /*  240351 */ GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(240415), // Rule ID 12325 //
     /*  240356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  240359 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240362 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240384 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240413 */   GIR_RootConstrainSelectedInstOperands,
     /*  240414 */   // GIR_Coverage, 12325,
     /*  240414 */   GIR_EraseRootFromParent_Done,
     /*  240415 */ // Label 3469: @240415
     /*  240415 */ GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(240479), // Rule ID 12326 //
     /*  240420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  240423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240426 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240448 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240477 */   GIR_RootConstrainSelectedInstOperands,
     /*  240478 */   // GIR_Coverage, 12326,
     /*  240478 */   GIR_EraseRootFromParent_Done,
     /*  240479 */ // Label 3470: @240479
     /*  240479 */ GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(240543), // Rule ID 12327 //
     /*  240484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  240487 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240490 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  240512 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  240512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  240515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  240522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  240527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  240532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  240537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240541 */   GIR_RootConstrainSelectedInstOperands,
     /*  240542 */   // GIR_Coverage, 12327,
     /*  240542 */   GIR_EraseRootFromParent_Done,
     /*  240543 */ // Label 3471: @240543
     /*  240543 */ GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(240611), // Rule ID 12588 //
     /*  240548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  240551 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  240554 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  240558 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  240565 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240576 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240580 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240587 */   // (atomic_load:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240602 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240605 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240609 */   GIR_RootConstrainSelectedInstOperands,
     /*  240610 */   // GIR_Coverage, 12588,
     /*  240610 */   GIR_EraseRootFromParent_Done,
     /*  240611 */ // Label 3472: @240611
     /*  240611 */ GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(240679), // Rule ID 12589 //
     /*  240616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  240619 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  240622 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  240626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  240633 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240640 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240644 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240648 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240655 */   // (atomic_load:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240658 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240670 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240673 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240677 */   GIR_RootConstrainSelectedInstOperands,
     /*  240678 */   // GIR_Coverage, 12589,
     /*  240678 */   GIR_EraseRootFromParent_Done,
     /*  240679 */ // Label 3473: @240679
     /*  240679 */ GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(240747), // Rule ID 12590 //
     /*  240684 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  240687 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  240690 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  240694 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  240701 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240712 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240716 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240723 */   // (atomic_load:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240723 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240726 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240738 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240745 */   GIR_RootConstrainSelectedInstOperands,
     /*  240746 */   // GIR_Coverage, 12590,
     /*  240746 */   GIR_EraseRootFromParent_Done,
     /*  240747 */ // Label 3474: @240747
     /*  240747 */ GIM_Try, /*On fail goto*//*Label 3475*/ GIMT_Encode4(240815), // Rule ID 12591 //
     /*  240752 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  240755 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  240758 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  240762 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  240769 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240780 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240784 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240791 */   // (atomic_load:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240791 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240794 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240806 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240809 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240813 */   GIR_RootConstrainSelectedInstOperands,
     /*  240814 */   // GIR_Coverage, 12591,
     /*  240814 */   GIR_EraseRootFromParent_Done,
     /*  240815 */ // Label 3475: @240815
     /*  240815 */ GIM_Try, /*On fail goto*//*Label 3476*/ GIMT_Encode4(240883), // Rule ID 12592 //
     /*  240820 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  240823 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  240826 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  240830 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  240837 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240844 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240852 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240859 */   // (atomic_load:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240862 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240874 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240877 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240881 */   GIR_RootConstrainSelectedInstOperands,
     /*  240882 */   // GIR_Coverage, 12592,
     /*  240882 */   GIR_EraseRootFromParent_Done,
     /*  240883 */ // Label 3476: @240883
     /*  240883 */ GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(240940), // Rule ID 12298 //
     /*  240888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  240891 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240894 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240905 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240909 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240916 */   // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240916 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240919 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240931 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240934 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240938 */   GIR_RootConstrainSelectedInstOperands,
     /*  240939 */   // GIR_Coverage, 12298,
     /*  240939 */   GIR_EraseRootFromParent_Done,
     /*  240940 */ // Label 3477: @240940
     /*  240940 */ GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(240997), // Rule ID 12299 //
     /*  240945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  240948 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  240951 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  240958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  240962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  240966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  240973 */   // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  240973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  240976 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  240978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  240983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  240988 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  240991 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  240995 */   GIR_RootConstrainSelectedInstOperands,
     /*  240996 */   // GIR_Coverage, 12299,
     /*  240996 */   GIR_EraseRootFromParent_Done,
     /*  240997 */ // Label 3478: @240997
     /*  240997 */ GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(241054), // Rule ID 12300 //
     /*  241002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  241005 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241008 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241015 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241019 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241023 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241030 */   // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241030 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241033 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241045 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241048 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241052 */   GIR_RootConstrainSelectedInstOperands,
     /*  241053 */   // GIR_Coverage, 12300,
     /*  241053 */   GIR_EraseRootFromParent_Done,
     /*  241054 */ // Label 3479: @241054
     /*  241054 */ GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(241111), // Rule ID 12301 //
     /*  241059 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  241062 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241076 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241080 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241087 */   // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241090 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241102 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241105 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241109 */   GIR_RootConstrainSelectedInstOperands,
     /*  241110 */   // GIR_Coverage, 12301,
     /*  241110 */   GIR_EraseRootFromParent_Done,
     /*  241111 */ // Label 3480: @241111
     /*  241111 */ GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(241168), // Rule ID 12302 //
     /*  241116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  241119 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241122 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241133 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241137 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241144 */   // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241162 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241166 */   GIR_RootConstrainSelectedInstOperands,
     /*  241167 */   // GIR_Coverage, 12302,
     /*  241167 */   GIR_EraseRootFromParent_Done,
     /*  241168 */ // Label 3481: @241168
     /*  241168 */ GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(241225), // Rule ID 12318 //
     /*  241173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  241176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241179 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241190 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241194 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241201 */   // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241204 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241216 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241219 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241223 */   GIR_RootConstrainSelectedInstOperands,
     /*  241224 */   // GIR_Coverage, 12318,
     /*  241224 */   GIR_EraseRootFromParent_Done,
     /*  241225 */ // Label 3482: @241225
     /*  241225 */ GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(241282), // Rule ID 12319 //
     /*  241230 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  241233 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241258 */   // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241261 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241273 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241276 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241280 */   GIR_RootConstrainSelectedInstOperands,
     /*  241281 */   // GIR_Coverage, 12319,
     /*  241281 */   GIR_EraseRootFromParent_Done,
     /*  241282 */ // Label 3483: @241282
     /*  241282 */ GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(241339), // Rule ID 12320 //
     /*  241287 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  241290 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241293 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241304 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241308 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241315 */   // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241318 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241330 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241333 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241337 */   GIR_RootConstrainSelectedInstOperands,
     /*  241338 */   // GIR_Coverage, 12320,
     /*  241338 */   GIR_EraseRootFromParent_Done,
     /*  241339 */ // Label 3484: @241339
     /*  241339 */ GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(241396), // Rule ID 12321 //
     /*  241344 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  241347 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241350 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241361 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241365 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241372 */   // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241390 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241394 */   GIR_RootConstrainSelectedInstOperands,
     /*  241395 */   // GIR_Coverage, 12321,
     /*  241395 */   GIR_EraseRootFromParent_Done,
     /*  241396 */ // Label 3485: @241396
     /*  241396 */ GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(241453), // Rule ID 12322 //
     /*  241401 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  241404 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241407 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241418 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241422 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  241429 */   // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  241429 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  241432 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  241439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  241444 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  241447 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241451 */   GIR_RootConstrainSelectedInstOperands,
     /*  241452 */   // GIR_Coverage, 12322,
     /*  241452 */   GIR_EraseRootFromParent_Done,
     /*  241453 */ // Label 3486: @241453
     /*  241453 */ GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(241529), // Rule ID 9921 //
     /*  241458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  241461 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  241464 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  241468 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  241475 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241483 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241487 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241491 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241498 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241498 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241501 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241523 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241527 */   GIR_RootConstrainSelectedInstOperands,
     /*  241528 */   // GIR_Coverage, 9921,
     /*  241528 */   GIR_EraseRootFromParent_Done,
     /*  241529 */ // Label 3487: @241529
     /*  241529 */ GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(241605), // Rule ID 9922 //
     /*  241534 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  241537 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  241540 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  241544 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  241551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241563 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241567 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241574 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241574 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241577 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241603 */   GIR_RootConstrainSelectedInstOperands,
     /*  241604 */   // GIR_Coverage, 9922,
     /*  241604 */   GIR_EraseRootFromParent_Done,
     /*  241605 */ // Label 3488: @241605
     /*  241605 */ GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(241681), // Rule ID 9923 //
     /*  241610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  241613 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  241616 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  241620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  241627 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241635 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241639 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241643 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241650 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241650 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241653 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241675 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241679 */   GIR_RootConstrainSelectedInstOperands,
     /*  241680 */   // GIR_Coverage, 9923,
     /*  241680 */   GIR_EraseRootFromParent_Done,
     /*  241681 */ // Label 3489: @241681
     /*  241681 */ GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(241757), // Rule ID 9924 //
     /*  241686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  241689 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  241692 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  241696 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  241703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241711 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241715 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241719 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241726 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241729 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241751 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241755 */   GIR_RootConstrainSelectedInstOperands,
     /*  241756 */   // GIR_Coverage, 9924,
     /*  241756 */   GIR_EraseRootFromParent_Done,
     /*  241757 */ // Label 3490: @241757
     /*  241757 */ GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(241833), // Rule ID 9925 //
     /*  241762 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  241765 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  241768 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  241772 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  241779 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241791 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241795 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241802 */   // (atomic_load:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241802 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241805 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241807 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241831 */   GIR_RootConstrainSelectedInstOperands,
     /*  241832 */   // GIR_Coverage, 9925,
     /*  241832 */   GIR_EraseRootFromParent_Done,
     /*  241833 */ // Label 3491: @241833
     /*  241833 */ GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(241898), // Rule ID 10171 //
     /*  241838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  241841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241867 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241870 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241892 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241896 */   GIR_RootConstrainSelectedInstOperands,
     /*  241897 */   // GIR_Coverage, 10171,
     /*  241897 */   GIR_EraseRootFromParent_Done,
     /*  241898 */ // Label 3492: @241898
     /*  241898 */ GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(241963), // Rule ID 10172 //
     /*  241903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  241906 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241909 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241917 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241921 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241925 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241932 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241932 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  241935 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  241937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  241942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  241947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  241952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  241957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  241961 */   GIR_RootConstrainSelectedInstOperands,
     /*  241962 */   // GIR_Coverage, 10172,
     /*  241962 */   GIR_EraseRootFromParent_Done,
     /*  241963 */ // Label 3493: @241963
     /*  241963 */ GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(242028), // Rule ID 10173 //
     /*  241968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  241971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  241974 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  241982 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  241986 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  241990 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  241997 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  241997 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242000 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242026 */   GIR_RootConstrainSelectedInstOperands,
     /*  242027 */   // GIR_Coverage, 10173,
     /*  242027 */   GIR_EraseRootFromParent_Done,
     /*  242028 */ // Label 3494: @242028
     /*  242028 */ GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(242093), // Rule ID 10174 //
     /*  242033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  242036 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242039 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242047 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242051 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242062 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242065 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242077 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242087 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242091 */   GIR_RootConstrainSelectedInstOperands,
     /*  242092 */   // GIR_Coverage, 10174,
     /*  242092 */   GIR_EraseRootFromParent_Done,
     /*  242093 */ // Label 3495: @242093
     /*  242093 */ GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(242158), // Rule ID 10175 //
     /*  242098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  242101 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242104 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242112 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242116 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242120 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242127 */   // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242130 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242152 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242156 */   GIR_RootConstrainSelectedInstOperands,
     /*  242157 */   // GIR_Coverage, 10175,
     /*  242157 */   GIR_EraseRootFromParent_Done,
     /*  242158 */ // Label 3496: @242158
     /*  242158 */ GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(242223), // Rule ID 10191 //
     /*  242163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  242166 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242169 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242192 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242195 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242221 */   GIR_RootConstrainSelectedInstOperands,
     /*  242222 */   // GIR_Coverage, 10191,
     /*  242222 */   GIR_EraseRootFromParent_Done,
     /*  242223 */ // Label 3497: @242223
     /*  242223 */ GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(242288), // Rule ID 10192 //
     /*  242228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  242231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242242 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242246 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242250 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242257 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242282 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242286 */   GIR_RootConstrainSelectedInstOperands,
     /*  242287 */   // GIR_Coverage, 10192,
     /*  242287 */   GIR_EraseRootFromParent_Done,
     /*  242288 */ // Label 3498: @242288
     /*  242288 */ GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(242353), // Rule ID 10193 //
     /*  242293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  242296 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242311 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242315 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242322 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242322 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242325 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242342 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242351 */   GIR_RootConstrainSelectedInstOperands,
     /*  242352 */   // GIR_Coverage, 10193,
     /*  242352 */   GIR_EraseRootFromParent_Done,
     /*  242353 */ // Label 3499: @242353
     /*  242353 */ GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(242418), // Rule ID 10194 //
     /*  242358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  242361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242364 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242372 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242376 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242380 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242387 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242387 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242390 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242412 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242416 */   GIR_RootConstrainSelectedInstOperands,
     /*  242417 */   // GIR_Coverage, 10194,
     /*  242417 */   GIR_EraseRootFromParent_Done,
     /*  242418 */ // Label 3500: @242418
     /*  242418 */ GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(242483), // Rule ID 10195 //
     /*  242423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  242426 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242429 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242437 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242441 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  242452 */   // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  242452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  242455 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  242462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  242467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  242472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  242477 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242481 */   GIR_RootConstrainSelectedInstOperands,
     /*  242482 */   // GIR_Coverage, 10195,
     /*  242482 */   GIR_EraseRootFromParent_Done,
     /*  242483 */ // Label 3501: @242483
     /*  242483 */ GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(242552), // Rule ID 9916 //
     /*  242488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  242491 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  242494 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  242498 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  242505 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242521 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242528 */   // (atomic_load:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242543 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242546 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242550 */   GIR_RootConstrainSelectedInstOperands,
     /*  242551 */   // GIR_Coverage, 9916,
     /*  242551 */   GIR_EraseRootFromParent_Done,
     /*  242552 */ // Label 3502: @242552
     /*  242552 */ GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(242621), // Rule ID 9917 //
     /*  242557 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  242560 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  242563 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  242567 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  242574 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242597 */   // (atomic_load:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242619 */   GIR_RootConstrainSelectedInstOperands,
     /*  242620 */   // GIR_Coverage, 9917,
     /*  242620 */   GIR_EraseRootFromParent_Done,
     /*  242621 */ // Label 3503: @242621
     /*  242621 */ GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(242690), // Rule ID 9918 //
     /*  242626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  242629 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  242632 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  242636 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  242643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242655 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242666 */   // (atomic_load:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242688 */   GIR_RootConstrainSelectedInstOperands,
     /*  242689 */   // GIR_Coverage, 9918,
     /*  242689 */   GIR_EraseRootFromParent_Done,
     /*  242690 */ // Label 3504: @242690
     /*  242690 */ GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(242759), // Rule ID 9919 //
     /*  242695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  242698 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  242701 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  242705 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  242712 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242724 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242728 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242735 */   // (atomic_load:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242735 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242738 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242750 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242753 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242757 */   GIR_RootConstrainSelectedInstOperands,
     /*  242758 */   // GIR_Coverage, 9919,
     /*  242758 */   GIR_EraseRootFromParent_Done,
     /*  242759 */ // Label 3505: @242759
     /*  242759 */ GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(242828), // Rule ID 9920 //
     /*  242764 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  242767 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  242770 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  242774 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  242781 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242804 */   // (atomic_load:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_atomic_load_nonext_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242819 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242822 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242826 */   GIR_RootConstrainSelectedInstOperands,
     /*  242827 */   // GIR_Coverage, 9920,
     /*  242827 */   GIR_EraseRootFromParent_Done,
     /*  242828 */ // Label 3506: @242828
     /*  242828 */ GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(242886), // Rule ID 10166 //
     /*  242833 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  242836 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242839 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242855 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242862 */   // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242865 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242884 */   GIR_RootConstrainSelectedInstOperands,
     /*  242885 */   // GIR_Coverage, 10166,
     /*  242885 */   GIR_EraseRootFromParent_Done,
     /*  242886 */ // Label 3507: @242886
     /*  242886 */ GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(242944), // Rule ID 10167 //
     /*  242891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  242894 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242897 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242909 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242913 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242920 */   // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242923 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242930 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242935 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242938 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  242942 */   GIR_RootConstrainSelectedInstOperands,
     /*  242943 */   // GIR_Coverage, 10167,
     /*  242943 */   GIR_EraseRootFromParent_Done,
     /*  242944 */ // Label 3508: @242944
     /*  242944 */ GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(243002), // Rule ID 10168 //
     /*  242949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  242952 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  242955 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  242963 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  242967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  242971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  242978 */   // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  242978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  242981 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  242983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  242988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  242993 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  242996 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243000 */   GIR_RootConstrainSelectedInstOperands,
     /*  243001 */   // GIR_Coverage, 10168,
     /*  243001 */   GIR_EraseRootFromParent_Done,
     /*  243002 */ // Label 3509: @243002
     /*  243002 */ GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(243060), // Rule ID 10169 //
     /*  243007 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  243010 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243013 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243025 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243029 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243036 */   // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243036 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243039 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243051 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243054 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243058 */   GIR_RootConstrainSelectedInstOperands,
     /*  243059 */   // GIR_Coverage, 10169,
     /*  243059 */   GIR_EraseRootFromParent_Done,
     /*  243060 */ // Label 3510: @243060
     /*  243060 */ GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(243118), // Rule ID 10170 //
     /*  243065 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  243068 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243071 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243094 */   // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243094 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243097 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243116 */   GIR_RootConstrainSelectedInstOperands,
     /*  243117 */   // GIR_Coverage, 10170,
     /*  243117 */   GIR_EraseRootFromParent_Done,
     /*  243118 */ // Label 3511: @243118
     /*  243118 */ GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(243176), // Rule ID 10186 //
     /*  243123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  243126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243145 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243152 */   // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243152 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243155 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243170 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243174 */   GIR_RootConstrainSelectedInstOperands,
     /*  243175 */   // GIR_Coverage, 10186,
     /*  243175 */   GIR_EraseRootFromParent_Done,
     /*  243176 */ // Label 3512: @243176
     /*  243176 */ GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(243234), // Rule ID 10187 //
     /*  243181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  243184 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243187 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243199 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243203 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243210 */   // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243225 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243228 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243232 */   GIR_RootConstrainSelectedInstOperands,
     /*  243233 */   // GIR_Coverage, 10187,
     /*  243233 */   GIR_EraseRootFromParent_Done,
     /*  243234 */ // Label 3513: @243234
     /*  243234 */ GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(243292), // Rule ID 10188 //
     /*  243239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  243242 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243245 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243257 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243261 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243268 */   // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243268 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243271 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243283 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243286 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243290 */   GIR_RootConstrainSelectedInstOperands,
     /*  243291 */   // GIR_Coverage, 10188,
     /*  243291 */   GIR_EraseRootFromParent_Done,
     /*  243292 */ // Label 3514: @243292
     /*  243292 */ GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(243350), // Rule ID 10189 //
     /*  243297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  243300 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243326 */   // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243329 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243344 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243348 */   GIR_RootConstrainSelectedInstOperands,
     /*  243349 */   // GIR_Coverage, 10189,
     /*  243349 */   GIR_EraseRootFromParent_Done,
     /*  243350 */ // Label 3515: @243350
     /*  243350 */ GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(243408), // Rule ID 10190 //
     /*  243355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  243358 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243361 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  243369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  243373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  243384 */   // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  243384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  243387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  243389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  243394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243406 */   GIR_RootConstrainSelectedInstOperands,
     /*  243407 */   // GIR_Coverage, 10190,
     /*  243407 */   GIR_EraseRootFromParent_Done,
     /*  243408 */ // Label 3516: @243408
     /*  243408 */ GIM_Reject,
     /*  243409 */ // Label 1131: @243409
     /*  243409 */ GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(255478),
     /*  243414 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  243417 */   GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(243483), // Rule ID 8957 //
     /*  243422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  243425 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243437 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243441 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  243445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  243452 */     // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  243452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  243455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  243467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  243472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  243477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243481 */     GIR_RootConstrainSelectedInstOperands,
     /*  243482 */     // GIR_Coverage, 8957,
     /*  243482 */     GIR_EraseRootFromParent_Done,
     /*  243483 */   // Label 3518: @243483
     /*  243483 */   GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(243549), // Rule ID 8974 //
     /*  243488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  243491 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243503 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243507 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  243511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  243518 */     // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  243518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  243521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  243533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  243538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  243543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243547 */     GIR_RootConstrainSelectedInstOperands,
     /*  243548 */     // GIR_Coverage, 8974,
     /*  243548 */     GIR_EraseRootFromParent_Done,
     /*  243549 */   // Label 3519: @243549
     /*  243549 */   GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(243611), // Rule ID 8962 //
     /*  243554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  243557 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243569 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243573 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  243580 */     // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  243580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  243583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  243595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  243600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  243605 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243609 */     GIR_RootConstrainSelectedInstOperands,
     /*  243610 */     // GIR_Coverage, 8962,
     /*  243610 */     GIR_EraseRootFromParent_Done,
     /*  243611 */   // Label 3520: @243611
     /*  243611 */   GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(243673), // Rule ID 8979 //
     /*  243616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  243619 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243631 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  243642 */     // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  243642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  243645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  243657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  243662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  243667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243671 */     GIR_RootConstrainSelectedInstOperands,
     /*  243672 */     // GIR_Coverage, 8979,
     /*  243672 */     GIR_EraseRootFromParent_Done,
     /*  243673 */   // Label 3521: @243673
     /*  243673 */   GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(243735), // Rule ID 8968 //
     /*  243678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  243681 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243693 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  243704 */     // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  243704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  243707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  243719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  243724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  243729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243733 */     GIR_RootConstrainSelectedInstOperands,
     /*  243734 */     // GIR_Coverage, 8968,
     /*  243734 */     GIR_EraseRootFromParent_Done,
     /*  243735 */   // Label 3522: @243735
     /*  243735 */   GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(243797), // Rule ID 8985 //
     /*  243740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  243743 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243755 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  243766 */     // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  243766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  243769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  243781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  243786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  243791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243795 */     GIR_RootConstrainSelectedInstOperands,
     /*  243796 */     // GIR_Coverage, 8985,
     /*  243796 */     GIR_EraseRootFromParent_Done,
     /*  243797 */   // Label 3523: @243797
     /*  243797 */   GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(243856), // Rule ID 8953 //
     /*  243802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  243805 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243817 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243821 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  243825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  243832 */     // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  243832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  243835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243854 */     GIR_RootConstrainSelectedInstOperands,
     /*  243855 */     // GIR_Coverage, 8953,
     /*  243855 */     GIR_EraseRootFromParent_Done,
     /*  243856 */   // Label 3524: @243856
     /*  243856 */   GIM_Try, /*On fail goto*//*Label 3525*/ GIMT_Encode4(243915), // Rule ID 8954 //
     /*  243861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  243864 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243876 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243880 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  243884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  243891 */     // (ld:{ *:[v2i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  243891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  243894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243913 */     GIR_RootConstrainSelectedInstOperands,
     /*  243914 */     // GIR_Coverage, 8954,
     /*  243914 */     GIR_EraseRootFromParent_Done,
     /*  243915 */   // Label 3525: @243915
     /*  243915 */   GIM_Try, /*On fail goto*//*Label 3526*/ GIMT_Encode4(243974), // Rule ID 8970 //
     /*  243920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  243923 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243935 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243939 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  243943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  243950 */     // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  243950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  243953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  243955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  243960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  243965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  243968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  243972 */     GIR_RootConstrainSelectedInstOperands,
     /*  243973 */     // GIR_Coverage, 8970,
     /*  243973 */     GIR_EraseRootFromParent_Done,
     /*  243974 */   // Label 3526: @243974
     /*  243974 */   GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(244033), // Rule ID 8971 //
     /*  243979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  243982 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  243986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  243990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  243994 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  243998 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  244002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  244009 */     // (ld:{ *:[v2f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  244009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  244012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  244014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  244019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244031 */     GIR_RootConstrainSelectedInstOperands,
     /*  244032 */     // GIR_Coverage, 8971,
     /*  244032 */     GIR_EraseRootFromParent_Done,
     /*  244033 */   // Label 3527: @244033
     /*  244033 */   GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(244088), // Rule ID 8959 //
     /*  244038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  244041 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  244049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244053 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  244057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  244064 */     // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  244064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  244067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  244069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  244074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244086 */     GIR_RootConstrainSelectedInstOperands,
     /*  244087 */     // GIR_Coverage, 8959,
     /*  244087 */     GIR_EraseRootFromParent_Done,
     /*  244088 */   // Label 3528: @244088
     /*  244088 */   GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(244143), // Rule ID 8976 //
     /*  244093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  244096 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  244104 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244108 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  244112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  244119 */     // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  244119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  244122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  244124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  244129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244141 */     GIR_RootConstrainSelectedInstOperands,
     /*  244142 */     // GIR_Coverage, 8976,
     /*  244142 */     GIR_EraseRootFromParent_Done,
     /*  244143 */   // Label 3529: @244143
     /*  244143 */   GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(244203), // Rule ID 29863 //
     /*  244148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  244151 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244160 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244179 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244197 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244201 */     GIR_RootConstrainSelectedInstOperands,
     /*  244202 */     // GIR_Coverage, 29863,
     /*  244202 */     GIR_EraseRootFromParent_Done,
     /*  244203 */   // Label 3530: @244203
     /*  244203 */   GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(244263), // Rule ID 29864 //
     /*  244208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  244211 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244220 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244239 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244261 */     GIR_RootConstrainSelectedInstOperands,
     /*  244262 */     // GIR_Coverage, 29864,
     /*  244262 */     GIR_EraseRootFromParent_Done,
     /*  244263 */   // Label 3531: @244263
     /*  244263 */   GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(244323), // Rule ID 29865 //
     /*  244268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  244271 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244280 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244299 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244321 */     GIR_RootConstrainSelectedInstOperands,
     /*  244322 */     // GIR_Coverage, 29865,
     /*  244322 */     GIR_EraseRootFromParent_Done,
     /*  244323 */   // Label 3532: @244323
     /*  244323 */   GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(244383), // Rule ID 29866 //
     /*  244328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  244331 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244340 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244359 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244381 */     GIR_RootConstrainSelectedInstOperands,
     /*  244382 */     // GIR_Coverage, 29866,
     /*  244382 */     GIR_EraseRootFromParent_Done,
     /*  244383 */   // Label 3533: @244383
     /*  244383 */   GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(244443), // Rule ID 29867 //
     /*  244388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  244391 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244395 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244400 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244419 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244441 */     GIR_RootConstrainSelectedInstOperands,
     /*  244442 */     // GIR_Coverage, 29867,
     /*  244442 */     GIR_EraseRootFromParent_Done,
     /*  244443 */   // Label 3534: @244443
     /*  244443 */   GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(244503), // Rule ID 29883 //
     /*  244448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  244451 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244460 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244479 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244501 */     GIR_RootConstrainSelectedInstOperands,
     /*  244502 */     // GIR_Coverage, 29883,
     /*  244502 */     GIR_EraseRootFromParent_Done,
     /*  244503 */   // Label 3535: @244503
     /*  244503 */   GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(244563), // Rule ID 29884 //
     /*  244508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  244511 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244520 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244539 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244554 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244557 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244561 */     GIR_RootConstrainSelectedInstOperands,
     /*  244562 */     // GIR_Coverage, 29884,
     /*  244562 */     GIR_EraseRootFromParent_Done,
     /*  244563 */   // Label 3536: @244563
     /*  244563 */   GIM_Try, /*On fail goto*//*Label 3537*/ GIMT_Encode4(244623), // Rule ID 29885 //
     /*  244568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  244571 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244575 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244580 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244599 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244621 */     GIR_RootConstrainSelectedInstOperands,
     /*  244622 */     // GIR_Coverage, 29885,
     /*  244622 */     GIR_EraseRootFromParent_Done,
     /*  244623 */   // Label 3537: @244623
     /*  244623 */   GIM_Try, /*On fail goto*//*Label 3538*/ GIMT_Encode4(244683), // Rule ID 29886 //
     /*  244628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  244631 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244635 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244640 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244648 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244659 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244681 */     GIR_RootConstrainSelectedInstOperands,
     /*  244682 */     // GIR_Coverage, 29886,
     /*  244682 */     GIR_EraseRootFromParent_Done,
     /*  244683 */   // Label 3538: @244683
     /*  244683 */   GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(244743), // Rule ID 29887 //
     /*  244688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  244691 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244695 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244700 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  244704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244708 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244719 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244741 */     GIR_RootConstrainSelectedInstOperands,
     /*  244742 */     // GIR_Coverage, 29887,
     /*  244742 */     GIR_EraseRootFromParent_Done,
     /*  244743 */   // Label 3539: @244743
     /*  244743 */   GIM_Try, /*On fail goto*//*Label 3540*/ GIMT_Encode4(244808), // Rule ID 30203 //
     /*  244748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  244751 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244773 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  244777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244784 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244806 */     GIR_RootConstrainSelectedInstOperands,
     /*  244807 */     // GIR_Coverage, 30203,
     /*  244807 */     GIR_EraseRootFromParent_Done,
     /*  244808 */   // Label 3540: @244808
     /*  244808 */   GIM_Try, /*On fail goto*//*Label 3541*/ GIMT_Encode4(244873), // Rule ID 30204 //
     /*  244813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  244816 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244838 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  244842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244849 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244867 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244871 */     GIR_RootConstrainSelectedInstOperands,
     /*  244872 */     // GIR_Coverage, 30204,
     /*  244872 */     GIR_EraseRootFromParent_Done,
     /*  244873 */   // Label 3541: @244873
     /*  244873 */   GIM_Try, /*On fail goto*//*Label 3542*/ GIMT_Encode4(244938), // Rule ID 30205 //
     /*  244878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  244881 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244903 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  244907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244914 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  244936 */     GIR_RootConstrainSelectedInstOperands,
     /*  244937 */     // GIR_Coverage, 30205,
     /*  244937 */     GIR_EraseRootFromParent_Done,
     /*  244938 */   // Label 3542: @244938
     /*  244938 */   GIM_Try, /*On fail goto*//*Label 3543*/ GIMT_Encode4(245003), // Rule ID 30206 //
     /*  244943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  244946 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  244950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  244960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  244964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  244968 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  244972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  244979 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  244979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  244982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  244984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  244989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  244994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  244997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245001 */     GIR_RootConstrainSelectedInstOperands,
     /*  245002 */     // GIR_Coverage, 30206,
     /*  245002 */     GIR_EraseRootFromParent_Done,
     /*  245003 */   // Label 3543: @245003
     /*  245003 */   GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(245068), // Rule ID 30207 //
     /*  245008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  245011 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245033 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  245037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245044 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  245047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245066 */     GIR_RootConstrainSelectedInstOperands,
     /*  245067 */     // GIR_Coverage, 30207,
     /*  245067 */     GIR_EraseRootFromParent_Done,
     /*  245068 */   // Label 3544: @245068
     /*  245068 */   GIM_Try, /*On fail goto*//*Label 3545*/ GIMT_Encode4(245133), // Rule ID 30223 //
     /*  245073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  245076 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245080 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245085 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245094 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245098 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  245102 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245109 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  245112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245131 */     GIR_RootConstrainSelectedInstOperands,
     /*  245132 */     // GIR_Coverage, 30223,
     /*  245132 */     GIR_EraseRootFromParent_Done,
     /*  245133 */   // Label 3545: @245133
     /*  245133 */   GIM_Try, /*On fail goto*//*Label 3546*/ GIMT_Encode4(245198), // Rule ID 30224 //
     /*  245138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  245141 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245145 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245159 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245163 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  245167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245174 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  245177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245196 */     GIR_RootConstrainSelectedInstOperands,
     /*  245197 */     // GIR_Coverage, 30224,
     /*  245197 */     GIR_EraseRootFromParent_Done,
     /*  245198 */   // Label 3546: @245198
     /*  245198 */   GIM_Try, /*On fail goto*//*Label 3547*/ GIMT_Encode4(245263), // Rule ID 30225 //
     /*  245203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  245206 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245228 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  245232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245239 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  245242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245261 */     GIR_RootConstrainSelectedInstOperands,
     /*  245262 */     // GIR_Coverage, 30225,
     /*  245262 */     GIR_EraseRootFromParent_Done,
     /*  245263 */   // Label 3547: @245263
     /*  245263 */   GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(245328), // Rule ID 30226 //
     /*  245268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  245271 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245293 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  245297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245304 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  245307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245326 */     GIR_RootConstrainSelectedInstOperands,
     /*  245327 */     // GIR_Coverage, 30226,
     /*  245327 */     GIR_EraseRootFromParent_Done,
     /*  245328 */   // Label 3548: @245328
     /*  245328 */   GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(245393), // Rule ID 30227 //
     /*  245333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  245336 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245340 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245354 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245358 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  245362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245369 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  245372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245391 */     GIR_RootConstrainSelectedInstOperands,
     /*  245392 */     // GIR_Coverage, 30227,
     /*  245392 */     GIR_EraseRootFromParent_Done,
     /*  245393 */   // Label 3549: @245393
     /*  245393 */   GIM_Try, /*On fail goto*//*Label 3550*/ GIMT_Encode4(245445), // Rule ID 8964 //
     /*  245398 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  245406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245410 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  245414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  245421 */     // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  245421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  245424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  245426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  245431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245443 */     GIR_RootConstrainSelectedInstOperands,
     /*  245444 */     // GIR_Coverage, 8964,
     /*  245444 */     GIR_EraseRootFromParent_Done,
     /*  245445 */   // Label 3550: @245445
     /*  245445 */   GIM_Try, /*On fail goto*//*Label 3551*/ GIMT_Encode4(245500), // Rule ID 8965 //
     /*  245450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  245453 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  245461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245465 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  245469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  245476 */     // (ld:{ *:[v2i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  245476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  245479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  245481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  245486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245498 */     GIR_RootConstrainSelectedInstOperands,
     /*  245499 */     // GIR_Coverage, 8965,
     /*  245499 */     GIR_EraseRootFromParent_Done,
     /*  245500 */   // Label 3551: @245500
     /*  245500 */   GIM_Try, /*On fail goto*//*Label 3552*/ GIMT_Encode4(245552), // Rule ID 8981 //
     /*  245505 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  245513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245517 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  245521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  245528 */     // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  245528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  245531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  245533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  245538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245550 */     GIR_RootConstrainSelectedInstOperands,
     /*  245551 */     // GIR_Coverage, 8981,
     /*  245551 */     GIR_EraseRootFromParent_Done,
     /*  245552 */   // Label 3552: @245552
     /*  245552 */   GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(245607), // Rule ID 8982 //
     /*  245557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  245560 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  245564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  245568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245572 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  245576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  245583 */     // (ld:{ *:[v2f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  245583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  245586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  245588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  245593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245605 */     GIR_RootConstrainSelectedInstOperands,
     /*  245606 */     // GIR_Coverage, 8982,
     /*  245606 */     GIR_EraseRootFromParent_Done,
     /*  245607 */   // Label 3553: @245607
     /*  245607 */   GIM_Try, /*On fail goto*//*Label 3554*/ GIMT_Encode4(245663), // Rule ID 29868 //
     /*  245612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  245615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245620 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245639 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245661 */     GIR_RootConstrainSelectedInstOperands,
     /*  245662 */     // GIR_Coverage, 29868,
     /*  245662 */     GIR_EraseRootFromParent_Done,
     /*  245663 */   // Label 3554: @245663
     /*  245663 */   GIM_Try, /*On fail goto*//*Label 3555*/ GIMT_Encode4(245719), // Rule ID 29869 //
     /*  245668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  245671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245676 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245695 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245717 */     GIR_RootConstrainSelectedInstOperands,
     /*  245718 */     // GIR_Coverage, 29869,
     /*  245718 */     GIR_EraseRootFromParent_Done,
     /*  245719 */   // Label 3555: @245719
     /*  245719 */   GIM_Try, /*On fail goto*//*Label 3556*/ GIMT_Encode4(245775), // Rule ID 29870 //
     /*  245724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  245727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245732 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245740 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245744 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245751 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245766 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245773 */     GIR_RootConstrainSelectedInstOperands,
     /*  245774 */     // GIR_Coverage, 29870,
     /*  245774 */     GIR_EraseRootFromParent_Done,
     /*  245775 */   // Label 3556: @245775
     /*  245775 */   GIM_Try, /*On fail goto*//*Label 3557*/ GIMT_Encode4(245831), // Rule ID 29871 //
     /*  245780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  245783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245788 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245807 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245829 */     GIR_RootConstrainSelectedInstOperands,
     /*  245830 */     // GIR_Coverage, 29871,
     /*  245830 */     GIR_EraseRootFromParent_Done,
     /*  245831 */   // Label 3557: @245831
     /*  245831 */   GIM_Try, /*On fail goto*//*Label 3558*/ GIMT_Encode4(245887), // Rule ID 29872 //
     /*  245836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  245839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245844 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245863 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245885 */     GIR_RootConstrainSelectedInstOperands,
     /*  245886 */     // GIR_Coverage, 29872,
     /*  245886 */     GIR_EraseRootFromParent_Done,
     /*  245887 */   // Label 3558: @245887
     /*  245887 */   GIM_Try, /*On fail goto*//*Label 3559*/ GIMT_Encode4(245943), // Rule ID 29888 //
     /*  245892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  245895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245900 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245919 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245941 */     GIR_RootConstrainSelectedInstOperands,
     /*  245942 */     // GIR_Coverage, 29888,
     /*  245942 */     GIR_EraseRootFromParent_Done,
     /*  245943 */   // Label 3559: @245943
     /*  245943 */   GIM_Try, /*On fail goto*//*Label 3560*/ GIMT_Encode4(245999), // Rule ID 29889 //
     /*  245948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  245951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  245956 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  245960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  245964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  245968 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  245975 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  245975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  245978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  245980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  245985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  245990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  245993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  245997 */     GIR_RootConstrainSelectedInstOperands,
     /*  245998 */     // GIR_Coverage, 29889,
     /*  245998 */     GIR_EraseRootFromParent_Done,
     /*  245999 */   // Label 3560: @245999
     /*  245999 */   GIM_Try, /*On fail goto*//*Label 3561*/ GIMT_Encode4(246055), // Rule ID 29890 //
     /*  246004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  246007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246012 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  246016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246031 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246053 */     GIR_RootConstrainSelectedInstOperands,
     /*  246054 */     // GIR_Coverage, 29890,
     /*  246054 */     GIR_EraseRootFromParent_Done,
     /*  246055 */   // Label 3561: @246055
     /*  246055 */   GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(246111), // Rule ID 29891 //
     /*  246060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  246063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246068 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  246072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246087 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246105 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246109 */     GIR_RootConstrainSelectedInstOperands,
     /*  246110 */     // GIR_Coverage, 29891,
     /*  246110 */     GIR_EraseRootFromParent_Done,
     /*  246111 */   // Label 3562: @246111
     /*  246111 */   GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(246167), // Rule ID 29892 //
     /*  246116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  246119 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246124 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  246128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246143 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246165 */     GIR_RootConstrainSelectedInstOperands,
     /*  246166 */     // GIR_Coverage, 29892,
     /*  246166 */     GIR_EraseRootFromParent_Done,
     /*  246167 */   // Label 3563: @246167
     /*  246167 */   GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(246228), // Rule ID 30208 //
     /*  246172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  246175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246189 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246193 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246204 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246226 */     GIR_RootConstrainSelectedInstOperands,
     /*  246227 */     // GIR_Coverage, 30208,
     /*  246227 */     GIR_EraseRootFromParent_Done,
     /*  246228 */   // Label 3564: @246228
     /*  246228 */   GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(246289), // Rule ID 30209 //
     /*  246233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  246236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246254 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246265 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246287 */     GIR_RootConstrainSelectedInstOperands,
     /*  246288 */     // GIR_Coverage, 30209,
     /*  246288 */     GIR_EraseRootFromParent_Done,
     /*  246289 */   // Label 3565: @246289
     /*  246289 */   GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(246350), // Rule ID 30210 //
     /*  246294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  246297 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246315 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246326 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246348 */     GIR_RootConstrainSelectedInstOperands,
     /*  246349 */     // GIR_Coverage, 30210,
     /*  246349 */     GIR_EraseRootFromParent_Done,
     /*  246350 */   // Label 3566: @246350
     /*  246350 */   GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(246411), // Rule ID 30211 //
     /*  246355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  246358 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246363 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246376 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246387 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246409 */     GIR_RootConstrainSelectedInstOperands,
     /*  246410 */     // GIR_Coverage, 30211,
     /*  246410 */     GIR_EraseRootFromParent_Done,
     /*  246411 */   // Label 3567: @246411
     /*  246411 */   GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(246472), // Rule ID 30212 //
     /*  246416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  246419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246437 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246448 */     // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246470 */     GIR_RootConstrainSelectedInstOperands,
     /*  246471 */     // GIR_Coverage, 30212,
     /*  246471 */     GIR_EraseRootFromParent_Done,
     /*  246472 */   // Label 3568: @246472
     /*  246472 */   GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(246533), // Rule ID 30228 //
     /*  246477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  246480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246485 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246494 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246498 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246509 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246531 */     GIR_RootConstrainSelectedInstOperands,
     /*  246532 */     // GIR_Coverage, 30228,
     /*  246532 */     GIR_EraseRootFromParent_Done,
     /*  246533 */   // Label 3569: @246533
     /*  246533 */   GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(246594), // Rule ID 30229 //
     /*  246538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  246541 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246555 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246559 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246570 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246592 */     GIR_RootConstrainSelectedInstOperands,
     /*  246593 */     // GIR_Coverage, 30229,
     /*  246593 */     GIR_EraseRootFromParent_Done,
     /*  246594 */   // Label 3570: @246594
     /*  246594 */   GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(246655), // Rule ID 30230 //
     /*  246599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  246602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246620 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246631 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246653 */     GIR_RootConstrainSelectedInstOperands,
     /*  246654 */     // GIR_Coverage, 30230,
     /*  246654 */     GIR_EraseRootFromParent_Done,
     /*  246655 */   // Label 3571: @246655
     /*  246655 */   GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(246716), // Rule ID 30231 //
     /*  246660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  246663 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246668 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246681 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246692 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246714 */     GIR_RootConstrainSelectedInstOperands,
     /*  246715 */     // GIR_Coverage, 30231,
     /*  246715 */     GIR_EraseRootFromParent_Done,
     /*  246716 */   // Label 3572: @246716
     /*  246716 */   GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(246777), // Rule ID 30232 //
     /*  246721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  246724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246729 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  246734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  246738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246742 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  246746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  246753 */     // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  246753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  246756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  246758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  246763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  246768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246775 */     GIR_RootConstrainSelectedInstOperands,
     /*  246776 */     // GIR_Coverage, 30232,
     /*  246776 */     GIR_EraseRootFromParent_Done,
     /*  246777 */   // Label 3573: @246777
     /*  246777 */   GIM_Try, /*On fail goto*//*Label 3574*/ GIMT_Encode4(246836), // Rule ID 8955 //
     /*  246782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  246785 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  246789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  246793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246797 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  246801 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  246805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  246812 */     // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  246812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  246815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  246817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  246822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  246827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246834 */     GIR_RootConstrainSelectedInstOperands,
     /*  246835 */     // GIR_Coverage, 8955,
     /*  246835 */     GIR_EraseRootFromParent_Done,
     /*  246836 */   // Label 3574: @246836
     /*  246836 */   GIM_Try, /*On fail goto*//*Label 3575*/ GIMT_Encode4(246900), // Rule ID 8956 //
     /*  246841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  246844 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  246848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  246852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246856 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  246860 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  246864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  246871 */     // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  246871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  246874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  246876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  246881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  246886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  246894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246898 */     GIR_RootConstrainSelectedInstOperands,
     /*  246899 */     // GIR_Coverage, 8956,
     /*  246899 */     GIR_EraseRootFromParent_Done,
     /*  246900 */   // Label 3575: @246900
     /*  246900 */   GIM_Try, /*On fail goto*//*Label 3576*/ GIMT_Encode4(246959), // Rule ID 8972 //
     /*  246905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  246908 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  246912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  246916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246920 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  246924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  246928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  246935 */     // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  246935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  246938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  246940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  246945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  246950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  246953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  246957 */     GIR_RootConstrainSelectedInstOperands,
     /*  246958 */     // GIR_Coverage, 8972,
     /*  246958 */     GIR_EraseRootFromParent_Done,
     /*  246959 */   // Label 3576: @246959
     /*  246959 */   GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(247023), // Rule ID 8973 //
     /*  246964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  246967 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  246971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  246975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  246979 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  246983 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  246987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  246994 */     // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  246994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  246997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  246999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  247017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247021 */     GIR_RootConstrainSelectedInstOperands,
     /*  247022 */     // GIR_Coverage, 8973,
     /*  247022 */     GIR_EraseRootFromParent_Done,
     /*  247023 */   // Label 3577: @247023
     /*  247023 */   GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(247074), // Rule ID 8958 //
     /*  247028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  247031 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247039 */     // MIs[0] sbase
     /*  247039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  247043 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  247047 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247051 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  247055 */     // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  247055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  247058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247060 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  247062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247072 */     GIR_RootConstrainSelectedInstOperands,
     /*  247073 */     // GIR_Coverage, 8958,
     /*  247073 */     GIR_EraseRootFromParent_Done,
     /*  247074 */   // Label 3578: @247074
     /*  247074 */   GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(247125), // Rule ID 8975 //
     /*  247079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  247082 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247090 */     // MIs[0] sbase
     /*  247090 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  247094 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  247098 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247102 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  247106 */     // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  247106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  247109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247111 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  247113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247123 */     GIR_RootConstrainSelectedInstOperands,
     /*  247124 */     // GIR_Coverage, 8975,
     /*  247124 */     GIR_EraseRootFromParent_Done,
     /*  247125 */   // Label 3579: @247125
     /*  247125 */   GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(247180), // Rule ID 8960 //
     /*  247130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  247133 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247145 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247149 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247156 */     // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  247156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec),
     /*  247159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247178 */     GIR_RootConstrainSelectedInstOperands,
     /*  247179 */     // GIR_Coverage, 8960,
     /*  247179 */     GIR_EraseRootFromParent_Done,
     /*  247180 */   // Label 3580: @247180
     /*  247180 */   GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(247240), // Rule ID 8961 //
     /*  247185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  247188 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247200 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247211 */     // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  247211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  247214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  247234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247238 */     GIR_RootConstrainSelectedInstOperands,
     /*  247239 */     // GIR_Coverage, 8961,
     /*  247239 */     GIR_EraseRootFromParent_Done,
     /*  247240 */   // Label 3581: @247240
     /*  247240 */   GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(247295), // Rule ID 8977 //
     /*  247245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  247248 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247260 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247271 */     // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  247271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec),
     /*  247274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247293 */     GIR_RootConstrainSelectedInstOperands,
     /*  247294 */     // GIR_Coverage, 8977,
     /*  247294 */     GIR_EraseRootFromParent_Done,
     /*  247295 */   // Label 3582: @247295
     /*  247295 */   GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(247355), // Rule ID 8978 //
     /*  247300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  247303 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247315 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247326 */     // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  247326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  247329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  247349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247353 */     GIR_RootConstrainSelectedInstOperands,
     /*  247354 */     // GIR_Coverage, 8978,
     /*  247354 */     GIR_EraseRootFromParent_Done,
     /*  247355 */   // Label 3583: @247355
     /*  247355 */   GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(247402), // Rule ID 8963 //
     /*  247360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  247363 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247371 */     // MIs[0] sbase
     /*  247371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  247375 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  247379 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247383 */     // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  247383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  247386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247388 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  247390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247400 */     GIR_RootConstrainSelectedInstOperands,
     /*  247401 */     // GIR_Coverage, 8963,
     /*  247401 */     GIR_EraseRootFromParent_Done,
     /*  247402 */   // Label 3584: @247402
     /*  247402 */   GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(247449), // Rule ID 8980 //
     /*  247407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  247410 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247418 */     // MIs[0] sbase
     /*  247418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  247422 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  247426 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247430 */     // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  247430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  247433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247435 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  247437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247447 */     GIR_RootConstrainSelectedInstOperands,
     /*  247448 */     // GIR_Coverage, 8980,
     /*  247448 */     GIR_EraseRootFromParent_Done,
     /*  247449 */   // Label 3585: @247449
     /*  247449 */   GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(247504), // Rule ID 8966 //
     /*  247454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  247457 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247469 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247480 */     // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  247480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  247483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247502 */     GIR_RootConstrainSelectedInstOperands,
     /*  247503 */     // GIR_Coverage, 8966,
     /*  247503 */     GIR_EraseRootFromParent_Done,
     /*  247504 */   // Label 3586: @247504
     /*  247504 */   GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(247564), // Rule ID 8967 //
     /*  247509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  247512 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247524 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247535 */     // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  247535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  247538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  247558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247562 */     GIR_RootConstrainSelectedInstOperands,
     /*  247563 */     // GIR_Coverage, 8967,
     /*  247563 */     GIR_EraseRootFromParent_Done,
     /*  247564 */   // Label 3587: @247564
     /*  247564 */   GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(247619), // Rule ID 8983 //
     /*  247569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  247572 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247584 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247595 */     // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  247595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  247598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247617 */     GIR_RootConstrainSelectedInstOperands,
     /*  247618 */     // GIR_Coverage, 8983,
     /*  247618 */     GIR_EraseRootFromParent_Done,
     /*  247619 */   // Label 3588: @247619
     /*  247619 */   GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(247679), // Rule ID 8984 //
     /*  247624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  247627 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247639 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  247650 */     // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  247650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  247653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  247660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  247665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  247673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247677 */     GIR_RootConstrainSelectedInstOperands,
     /*  247678 */     // GIR_Coverage, 8984,
     /*  247678 */     GIR_EraseRootFromParent_Done,
     /*  247679 */   // Label 3589: @247679
     /*  247679 */   GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(247723), // Rule ID 8969 //
     /*  247684 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247692 */     // MIs[0] sbase
     /*  247692 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  247696 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  247700 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247704 */     // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  247704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  247707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247709 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  247711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247717 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247721 */     GIR_RootConstrainSelectedInstOperands,
     /*  247722 */     // GIR_Coverage, 8969,
     /*  247722 */     GIR_EraseRootFromParent_Done,
     /*  247723 */   // Label 3590: @247723
     /*  247723 */   GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(247767), // Rule ID 8986 //
     /*  247728 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  247732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  247736 */     // MIs[0] sbase
     /*  247736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  247740 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  247744 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  247748 */     // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  247748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  247751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  247753 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  247755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247758 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  247761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247765 */     GIR_RootConstrainSelectedInstOperands,
     /*  247766 */     // GIR_Coverage, 8986,
     /*  247766 */     GIR_EraseRootFromParent_Done,
     /*  247767 */   // Label 3591: @247767
     /*  247767 */   GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(247826), // Rule ID 14647 //
     /*  247772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  247775 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  247780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  247784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  247795 */     // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  247795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  247798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  247800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  247805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  247810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  247815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  247820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247824 */     GIR_RootConstrainSelectedInstOperands,
     /*  247825 */     // GIR_Coverage, 14647,
     /*  247825 */     GIR_EraseRootFromParent_Done,
     /*  247826 */   // Label 3592: @247826
     /*  247826 */   GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(247885), // Rule ID 14648 //
     /*  247831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  247834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  247839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  247843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  247854 */     // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  247854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  247857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  247859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  247864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  247869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  247874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  247879 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247883 */     GIR_RootConstrainSelectedInstOperands,
     /*  247884 */     // GIR_Coverage, 14648,
     /*  247884 */     GIR_EraseRootFromParent_Done,
     /*  247885 */   // Label 3593: @247885
     /*  247885 */   GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(247944), // Rule ID 14649 //
     /*  247890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  247893 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  247898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  247902 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247906 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  247913 */     // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  247913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  247916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  247918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  247923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  247928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  247933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  247938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  247942 */     GIR_RootConstrainSelectedInstOperands,
     /*  247943 */     // GIR_Coverage, 14649,
     /*  247943 */     GIR_EraseRootFromParent_Done,
     /*  247944 */   // Label 3594: @247944
     /*  247944 */   GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(248003), // Rule ID 14650 //
     /*  247949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  247952 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  247957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  247961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  247965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  247972 */     // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  247972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  247975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  247977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  247982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  247987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  247992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  247997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248001 */     GIR_RootConstrainSelectedInstOperands,
     /*  248002 */     // GIR_Coverage, 14650,
     /*  248002 */     GIR_EraseRootFromParent_Done,
     /*  248003 */   // Label 3595: @248003
     /*  248003 */   GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(248062), // Rule ID 14651 //
     /*  248008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  248011 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  248031 */     // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  248031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  248034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  248046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  248051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  248056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248060 */     GIR_RootConstrainSelectedInstOperands,
     /*  248061 */     // GIR_Coverage, 14651,
     /*  248061 */     GIR_EraseRootFromParent_Done,
     /*  248062 */   // Label 3596: @248062
     /*  248062 */   GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(248121), // Rule ID 14677 //
     /*  248067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  248070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  248090 */     // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  248090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  248093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  248105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  248110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  248115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248119 */     GIR_RootConstrainSelectedInstOperands,
     /*  248120 */     // GIR_Coverage, 14677,
     /*  248120 */     GIR_EraseRootFromParent_Done,
     /*  248121 */   // Label 3597: @248121
     /*  248121 */   GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(248180), // Rule ID 14678 //
     /*  248126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  248129 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248138 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  248149 */     // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  248149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  248152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  248164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  248169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  248174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248178 */     GIR_RootConstrainSelectedInstOperands,
     /*  248179 */     // GIR_Coverage, 14678,
     /*  248179 */     GIR_EraseRootFromParent_Done,
     /*  248180 */   // Label 3598: @248180
     /*  248180 */   GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(248239), // Rule ID 14679 //
     /*  248185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  248188 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248197 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  248208 */     // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  248208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  248211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  248223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  248228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  248233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248237 */     GIR_RootConstrainSelectedInstOperands,
     /*  248238 */     // GIR_Coverage, 14679,
     /*  248238 */     GIR_EraseRootFromParent_Done,
     /*  248239 */   // Label 3599: @248239
     /*  248239 */   GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(248298), // Rule ID 14680 //
     /*  248244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  248247 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  248267 */     // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  248267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  248270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  248282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  248287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  248292 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248296 */     GIR_RootConstrainSelectedInstOperands,
     /*  248297 */     // GIR_Coverage, 14680,
     /*  248297 */     GIR_EraseRootFromParent_Done,
     /*  248298 */   // Label 3600: @248298
     /*  248298 */   GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(248357), // Rule ID 14681 //
     /*  248303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  248306 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  248326 */     // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  248326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  248329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  248341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  248346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  248351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248355 */     GIR_RootConstrainSelectedInstOperands,
     /*  248356 */     // GIR_Coverage, 14681,
     /*  248356 */     GIR_EraseRootFromParent_Done,
     /*  248357 */   // Label 3601: @248357
     /*  248357 */   GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(248409), // Rule ID 14642 //
     /*  248362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  248365 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248385 */     // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248403 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248407 */     GIR_RootConstrainSelectedInstOperands,
     /*  248408 */     // GIR_Coverage, 14642,
     /*  248408 */     GIR_EraseRootFromParent_Done,
     /*  248409 */   // Label 3602: @248409
     /*  248409 */   GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(248461), // Rule ID 14643 //
     /*  248414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  248417 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248437 */     // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248455 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248459 */     GIR_RootConstrainSelectedInstOperands,
     /*  248460 */     // GIR_Coverage, 14643,
     /*  248460 */     GIR_EraseRootFromParent_Done,
     /*  248461 */   // Label 3603: @248461
     /*  248461 */   GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(248513), // Rule ID 14644 //
     /*  248466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  248469 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248478 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248482 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248489 */     // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248507 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248511 */     GIR_RootConstrainSelectedInstOperands,
     /*  248512 */     // GIR_Coverage, 14644,
     /*  248512 */     GIR_EraseRootFromParent_Done,
     /*  248513 */   // Label 3604: @248513
     /*  248513 */   GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(248565), // Rule ID 14645 //
     /*  248518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  248521 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248541 */     // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248563 */     GIR_RootConstrainSelectedInstOperands,
     /*  248564 */     // GIR_Coverage, 14645,
     /*  248564 */     GIR_EraseRootFromParent_Done,
     /*  248565 */   // Label 3605: @248565
     /*  248565 */   GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(248617), // Rule ID 14646 //
     /*  248570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  248573 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248582 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248593 */     // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248615 */     GIR_RootConstrainSelectedInstOperands,
     /*  248616 */     // GIR_Coverage, 14646,
     /*  248616 */     GIR_EraseRootFromParent_Done,
     /*  248617 */   // Label 3606: @248617
     /*  248617 */   GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(248669), // Rule ID 14672 //
     /*  248622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  248625 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248638 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248645 */     // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248667 */     GIR_RootConstrainSelectedInstOperands,
     /*  248668 */     // GIR_Coverage, 14672,
     /*  248668 */     GIR_EraseRootFromParent_Done,
     /*  248669 */   // Label 3607: @248669
     /*  248669 */   GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(248721), // Rule ID 14673 //
     /*  248674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  248677 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248697 */     // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248719 */     GIR_RootConstrainSelectedInstOperands,
     /*  248720 */     // GIR_Coverage, 14673,
     /*  248720 */     GIR_EraseRootFromParent_Done,
     /*  248721 */   // Label 3608: @248721
     /*  248721 */   GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(248773), // Rule ID 14674 //
     /*  248726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  248729 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248749 */     // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248771 */     GIR_RootConstrainSelectedInstOperands,
     /*  248772 */     // GIR_Coverage, 14674,
     /*  248772 */     GIR_EraseRootFromParent_Done,
     /*  248773 */   // Label 3609: @248773
     /*  248773 */   GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(248825), // Rule ID 14675 //
     /*  248778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  248781 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248801 */     // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248823 */     GIR_RootConstrainSelectedInstOperands,
     /*  248824 */     // GIR_Coverage, 14675,
     /*  248824 */     GIR_EraseRootFromParent_Done,
     /*  248825 */   // Label 3610: @248825
     /*  248825 */   GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(248877), // Rule ID 14676 //
     /*  248830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  248833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248842 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  248853 */     // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  248853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  248856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  248863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248871 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248875 */     GIR_RootConstrainSelectedInstOperands,
     /*  248876 */     // GIR_Coverage, 14676,
     /*  248876 */     GIR_EraseRootFromParent_Done,
     /*  248877 */   // Label 3611: @248877
     /*  248877 */   GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(248929), // Rule ID 14637 //
     /*  248882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  248885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  248905 */     // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  248905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  248908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248927 */     GIR_RootConstrainSelectedInstOperands,
     /*  248928 */     // GIR_Coverage, 14637,
     /*  248928 */     GIR_EraseRootFromParent_Done,
     /*  248929 */   // Label 3612: @248929
     /*  248929 */   GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(248981), // Rule ID 14638 //
     /*  248934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  248937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  248950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  248957 */     // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  248957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  248960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  248962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  248967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  248972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  248975 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  248979 */     GIR_RootConstrainSelectedInstOperands,
     /*  248980 */     // GIR_Coverage, 14638,
     /*  248980 */     GIR_EraseRootFromParent_Done,
     /*  248981 */   // Label 3613: @248981
     /*  248981 */   GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(249033), // Rule ID 14639 //
     /*  248986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  248989 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  248994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  248998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249009 */     // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249031 */     GIR_RootConstrainSelectedInstOperands,
     /*  249032 */     // GIR_Coverage, 14639,
     /*  249032 */     GIR_EraseRootFromParent_Done,
     /*  249033 */   // Label 3614: @249033
     /*  249033 */   GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(249085), // Rule ID 14640 //
     /*  249038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  249041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249061 */     // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249079 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249083 */     GIR_RootConstrainSelectedInstOperands,
     /*  249084 */     // GIR_Coverage, 14640,
     /*  249084 */     GIR_EraseRootFromParent_Done,
     /*  249085 */   // Label 3615: @249085
     /*  249085 */   GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(249137), // Rule ID 14641 //
     /*  249090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  249093 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249102 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249113 */     // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249135 */     GIR_RootConstrainSelectedInstOperands,
     /*  249136 */     // GIR_Coverage, 14641,
     /*  249136 */     GIR_EraseRootFromParent_Done,
     /*  249137 */   // Label 3616: @249137
     /*  249137 */   GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(249189), // Rule ID 14667 //
     /*  249142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  249145 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249165 */     // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249187 */     GIR_RootConstrainSelectedInstOperands,
     /*  249188 */     // GIR_Coverage, 14667,
     /*  249188 */     GIR_EraseRootFromParent_Done,
     /*  249189 */   // Label 3617: @249189
     /*  249189 */   GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(249241), // Rule ID 14668 //
     /*  249194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  249197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249217 */     // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249235 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249239 */     GIR_RootConstrainSelectedInstOperands,
     /*  249240 */     // GIR_Coverage, 14668,
     /*  249240 */     GIR_EraseRootFromParent_Done,
     /*  249241 */   // Label 3618: @249241
     /*  249241 */   GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(249293), // Rule ID 14669 //
     /*  249246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  249249 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249269 */     // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249287 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249291 */     GIR_RootConstrainSelectedInstOperands,
     /*  249292 */     // GIR_Coverage, 14669,
     /*  249292 */     GIR_EraseRootFromParent_Done,
     /*  249293 */   // Label 3619: @249293
     /*  249293 */   GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(249345), // Rule ID 14670 //
     /*  249298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  249301 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249321 */     // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249343 */     GIR_RootConstrainSelectedInstOperands,
     /*  249344 */     // GIR_Coverage, 14670,
     /*  249344 */     GIR_EraseRootFromParent_Done,
     /*  249345 */   // Label 3620: @249345
     /*  249345 */   GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(249397), // Rule ID 14671 //
     /*  249350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  249353 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  249358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249362 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249366 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  249373 */     // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  249373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  249376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  249378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  249383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  249388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249395 */     GIR_RootConstrainSelectedInstOperands,
     /*  249396 */     // GIR_Coverage, 14671,
     /*  249396 */     GIR_EraseRootFromParent_Done,
     /*  249397 */   // Label 3621: @249397
     /*  249397 */   GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(249464), // Rule ID 15788 //
     /*  249402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  249405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249427 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  249430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249462 */     GIR_RootConstrainSelectedInstOperands,
     /*  249463 */     // GIR_Coverage, 15788,
     /*  249463 */     GIR_EraseRootFromParent_Done,
     /*  249464 */   // Label 3622: @249464
     /*  249464 */   GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(249531), // Rule ID 15789 //
     /*  249469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  249472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249494 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  249497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249529 */     GIR_RootConstrainSelectedInstOperands,
     /*  249530 */     // GIR_Coverage, 15789,
     /*  249530 */     GIR_EraseRootFromParent_Done,
     /*  249531 */   // Label 3623: @249531
     /*  249531 */   GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(249598), // Rule ID 15790 //
     /*  249536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  249539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249561 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  249564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249596 */     GIR_RootConstrainSelectedInstOperands,
     /*  249597 */     // GIR_Coverage, 15790,
     /*  249597 */     GIR_EraseRootFromParent_Done,
     /*  249598 */   // Label 3624: @249598
     /*  249598 */   GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(249665), // Rule ID 15791 //
     /*  249603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  249606 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249628 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  249631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249663 */     GIR_RootConstrainSelectedInstOperands,
     /*  249664 */     // GIR_Coverage, 15791,
     /*  249664 */     GIR_EraseRootFromParent_Done,
     /*  249665 */   // Label 3625: @249665
     /*  249665 */   GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(249732), // Rule ID 15792 //
     /*  249670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  249673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249695 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  249698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249730 */     GIR_RootConstrainSelectedInstOperands,
     /*  249731 */     // GIR_Coverage, 15792,
     /*  249731 */     GIR_EraseRootFromParent_Done,
     /*  249732 */   // Label 3626: @249732
     /*  249732 */   GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(249799), // Rule ID 15798 //
     /*  249737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  249740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249762 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  249765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249790 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249793 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249797 */     GIR_RootConstrainSelectedInstOperands,
     /*  249798 */     // GIR_Coverage, 15798,
     /*  249798 */     GIR_EraseRootFromParent_Done,
     /*  249799 */   // Label 3627: @249799
     /*  249799 */   GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(249866), // Rule ID 15799 //
     /*  249804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  249807 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249829 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  249832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249864 */     GIR_RootConstrainSelectedInstOperands,
     /*  249865 */     // GIR_Coverage, 15799,
     /*  249865 */     GIR_EraseRootFromParent_Done,
     /*  249866 */   // Label 3628: @249866
     /*  249866 */   GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(249933), // Rule ID 15800 //
     /*  249871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  249874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249896 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  249899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249927 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249931 */     GIR_RootConstrainSelectedInstOperands,
     /*  249932 */     // GIR_Coverage, 15800,
     /*  249932 */     GIR_EraseRootFromParent_Done,
     /*  249933 */   // Label 3629: @249933
     /*  249933 */   GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(250000), // Rule ID 15801 //
     /*  249938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  249941 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  249948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  249952 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  249956 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  249963 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  249963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  249966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  249968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  249973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  249978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  249983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  249988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  249994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  249998 */     GIR_RootConstrainSelectedInstOperands,
     /*  249999 */     // GIR_Coverage, 15801,
     /*  249999 */     GIR_EraseRootFromParent_Done,
     /*  250000 */   // Label 3630: @250000
     /*  250000 */   GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(250067), // Rule ID 15802 //
     /*  250005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  250008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250019 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250023 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250030 */     // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  250033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250065 */     GIR_RootConstrainSelectedInstOperands,
     /*  250066 */     // GIR_Coverage, 15802,
     /*  250066 */     GIR_EraseRootFromParent_Done,
     /*  250067 */   // Label 3631: @250067
     /*  250067 */   GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(250134), // Rule ID 15808 //
     /*  250072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  250075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250097 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  250100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250128 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250132 */     GIR_RootConstrainSelectedInstOperands,
     /*  250133 */     // GIR_Coverage, 15808,
     /*  250133 */     GIR_EraseRootFromParent_Done,
     /*  250134 */   // Label 3632: @250134
     /*  250134 */   GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(250201), // Rule ID 15809 //
     /*  250139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  250142 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250164 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  250167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250195 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250199 */     GIR_RootConstrainSelectedInstOperands,
     /*  250200 */     // GIR_Coverage, 15809,
     /*  250200 */     GIR_EraseRootFromParent_Done,
     /*  250201 */   // Label 3633: @250201
     /*  250201 */   GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(250268), // Rule ID 15810 //
     /*  250206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  250209 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250231 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  250234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250266 */     GIR_RootConstrainSelectedInstOperands,
     /*  250267 */     // GIR_Coverage, 15810,
     /*  250267 */     GIR_EraseRootFromParent_Done,
     /*  250268 */   // Label 3634: @250268
     /*  250268 */   GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(250335), // Rule ID 15811 //
     /*  250273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  250276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250298 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  250301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250333 */     GIR_RootConstrainSelectedInstOperands,
     /*  250334 */     // GIR_Coverage, 15811,
     /*  250334 */     GIR_EraseRootFromParent_Done,
     /*  250335 */   // Label 3635: @250335
     /*  250335 */   GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(250402), // Rule ID 15812 //
     /*  250340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  250343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250354 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250358 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250365 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  250368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250400 */     GIR_RootConstrainSelectedInstOperands,
     /*  250401 */     // GIR_Coverage, 15812,
     /*  250401 */     GIR_EraseRootFromParent_Done,
     /*  250402 */   // Label 3636: @250402
     /*  250402 */   GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(250469), // Rule ID 15818 //
     /*  250407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  250410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250432 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  250435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250467 */     GIR_RootConstrainSelectedInstOperands,
     /*  250468 */     // GIR_Coverage, 15818,
     /*  250468 */     GIR_EraseRootFromParent_Done,
     /*  250469 */   // Label 3637: @250469
     /*  250469 */   GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(250536), // Rule ID 15819 //
     /*  250474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  250477 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250499 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  250502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250534 */     GIR_RootConstrainSelectedInstOperands,
     /*  250535 */     // GIR_Coverage, 15819,
     /*  250535 */     GIR_EraseRootFromParent_Done,
     /*  250536 */   // Label 3638: @250536
     /*  250536 */   GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(250603), // Rule ID 15820 //
     /*  250541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  250544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250555 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250559 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250566 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  250569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250601 */     GIR_RootConstrainSelectedInstOperands,
     /*  250602 */     // GIR_Coverage, 15820,
     /*  250602 */     GIR_EraseRootFromParent_Done,
     /*  250603 */   // Label 3639: @250603
     /*  250603 */   GIM_Try, /*On fail goto*//*Label 3640*/ GIMT_Encode4(250670), // Rule ID 15821 //
     /*  250608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  250611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250626 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250633 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  250636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250664 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250668 */     GIR_RootConstrainSelectedInstOperands,
     /*  250669 */     // GIR_Coverage, 15821,
     /*  250669 */     GIR_EraseRootFromParent_Done,
     /*  250670 */   // Label 3640: @250670
     /*  250670 */   GIM_Try, /*On fail goto*//*Label 3641*/ GIMT_Encode4(250737), // Rule ID 15822 //
     /*  250675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  250678 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  250685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  250700 */     // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  250700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  250703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  250705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  250710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  250715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  250720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  250725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250735 */     GIR_RootConstrainSelectedInstOperands,
     /*  250736 */     // GIR_Coverage, 15822,
     /*  250736 */     GIR_EraseRootFromParent_Done,
     /*  250737 */   // Label 3641: @250737
     /*  250737 */   GIM_Try, /*On fail goto*//*Label 3642*/ GIMT_Encode4(250798), // Rule ID 29523 //
     /*  250742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  250745 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  250749 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  250754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  250769 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  250769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  250772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  250774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  250779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  250784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  250789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250796 */     GIR_RootConstrainSelectedInstOperands,
     /*  250797 */     // GIR_Coverage, 29523,
     /*  250797 */     GIR_EraseRootFromParent_Done,
     /*  250798 */   // Label 3642: @250798
     /*  250798 */   GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(250859), // Rule ID 29524 //
     /*  250803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  250806 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  250810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  250815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  250830 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  250830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  250833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  250835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  250840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  250845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  250850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250853 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250857 */     GIR_RootConstrainSelectedInstOperands,
     /*  250858 */     // GIR_Coverage, 29524,
     /*  250858 */     GIR_EraseRootFromParent_Done,
     /*  250859 */   // Label 3643: @250859
     /*  250859 */   GIM_Try, /*On fail goto*//*Label 3644*/ GIMT_Encode4(250920), // Rule ID 29525 //
     /*  250864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  250867 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  250871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  250876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  250891 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  250891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  250894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  250896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  250901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  250906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  250911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250918 */     GIR_RootConstrainSelectedInstOperands,
     /*  250919 */     // GIR_Coverage, 29525,
     /*  250919 */     GIR_EraseRootFromParent_Done,
     /*  250920 */   // Label 3644: @250920
     /*  250920 */   GIM_Try, /*On fail goto*//*Label 3645*/ GIMT_Encode4(250981), // Rule ID 29526 //
     /*  250925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  250928 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  250932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  250937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  250941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  250945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  250952 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  250952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  250955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  250957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  250962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  250967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  250972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  250975 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  250979 */     GIR_RootConstrainSelectedInstOperands,
     /*  250980 */     // GIR_Coverage, 29526,
     /*  250980 */     GIR_EraseRootFromParent_Done,
     /*  250981 */   // Label 3645: @250981
     /*  250981 */   GIM_Try, /*On fail goto*//*Label 3646*/ GIMT_Encode4(251042), // Rule ID 29527 //
     /*  250986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  250989 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  250993 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  250998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  251013 */     // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  251013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  251016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  251018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  251023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  251028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  251033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251040 */     GIR_RootConstrainSelectedInstOperands,
     /*  251041 */     // GIR_Coverage, 29527,
     /*  251041 */     GIR_EraseRootFromParent_Done,
     /*  251042 */   // Label 3646: @251042
     /*  251042 */   GIM_Try, /*On fail goto*//*Label 3647*/ GIMT_Encode4(251103), // Rule ID 29543 //
     /*  251047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  251050 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  251054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  251059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  251074 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  251074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  251077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  251079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  251084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  251089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  251094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251097 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251101 */     GIR_RootConstrainSelectedInstOperands,
     /*  251102 */     // GIR_Coverage, 29543,
     /*  251102 */     GIR_EraseRootFromParent_Done,
     /*  251103 */   // Label 3647: @251103
     /*  251103 */   GIM_Try, /*On fail goto*//*Label 3648*/ GIMT_Encode4(251164), // Rule ID 29544 //
     /*  251108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  251111 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  251115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  251120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251124 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251128 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  251135 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  251135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  251138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  251140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  251145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  251150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  251155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251162 */     GIR_RootConstrainSelectedInstOperands,
     /*  251163 */     // GIR_Coverage, 29544,
     /*  251163 */     GIR_EraseRootFromParent_Done,
     /*  251164 */   // Label 3648: @251164
     /*  251164 */   GIM_Try, /*On fail goto*//*Label 3649*/ GIMT_Encode4(251225), // Rule ID 29545 //
     /*  251169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  251172 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  251176 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  251181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  251196 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  251196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  251199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  251201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  251206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  251211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  251216 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251219 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251223 */     GIR_RootConstrainSelectedInstOperands,
     /*  251224 */     // GIR_Coverage, 29545,
     /*  251224 */     GIR_EraseRootFromParent_Done,
     /*  251225 */   // Label 3649: @251225
     /*  251225 */   GIM_Try, /*On fail goto*//*Label 3650*/ GIMT_Encode4(251286), // Rule ID 29546 //
     /*  251230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  251233 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  251237 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  251242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  251257 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  251257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  251260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  251262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  251267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  251272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  251277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251284 */     GIR_RootConstrainSelectedInstOperands,
     /*  251285 */     // GIR_Coverage, 29546,
     /*  251285 */     GIR_EraseRootFromParent_Done,
     /*  251286 */   // Label 3650: @251286
     /*  251286 */   GIM_Try, /*On fail goto*//*Label 3651*/ GIMT_Encode4(251347), // Rule ID 29547 //
     /*  251291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  251294 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  251298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  251303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  251318 */     // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  251318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  251321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  251323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  251328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  251333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  251338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251345 */     GIR_RootConstrainSelectedInstOperands,
     /*  251346 */     // GIR_Coverage, 29547,
     /*  251346 */     GIR_EraseRootFromParent_Done,
     /*  251347 */   // Label 3651: @251347
     /*  251347 */   GIM_Try, /*On fail goto*//*Label 3652*/ GIMT_Encode4(251409), // Rule ID 15783 //
     /*  251352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  251355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251377 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  251380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251403 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251407 */     GIR_RootConstrainSelectedInstOperands,
     /*  251408 */     // GIR_Coverage, 15783,
     /*  251408 */     GIR_EraseRootFromParent_Done,
     /*  251409 */   // Label 3652: @251409
     /*  251409 */   GIM_Try, /*On fail goto*//*Label 3653*/ GIMT_Encode4(251471), // Rule ID 15784 //
     /*  251414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  251417 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251428 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251432 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251439 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  251442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251469 */     GIR_RootConstrainSelectedInstOperands,
     /*  251470 */     // GIR_Coverage, 15784,
     /*  251470 */     GIR_EraseRootFromParent_Done,
     /*  251471 */   // Label 3653: @251471
     /*  251471 */   GIM_Try, /*On fail goto*//*Label 3654*/ GIMT_Encode4(251533), // Rule ID 15785 //
     /*  251476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  251479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251501 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  251504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251531 */     GIR_RootConstrainSelectedInstOperands,
     /*  251532 */     // GIR_Coverage, 15785,
     /*  251532 */     GIR_EraseRootFromParent_Done,
     /*  251533 */   // Label 3654: @251533
     /*  251533 */   GIM_Try, /*On fail goto*//*Label 3655*/ GIMT_Encode4(251595), // Rule ID 15786 //
     /*  251538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  251541 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251563 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  251566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251593 */     GIR_RootConstrainSelectedInstOperands,
     /*  251594 */     // GIR_Coverage, 15786,
     /*  251594 */     GIR_EraseRootFromParent_Done,
     /*  251595 */   // Label 3655: @251595
     /*  251595 */   GIM_Try, /*On fail goto*//*Label 3656*/ GIMT_Encode4(251657), // Rule ID 15787 //
     /*  251600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  251603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251625 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  251628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251655 */     GIR_RootConstrainSelectedInstOperands,
     /*  251656 */     // GIR_Coverage, 15787,
     /*  251656 */     GIR_EraseRootFromParent_Done,
     /*  251657 */   // Label 3656: @251657
     /*  251657 */   GIM_Try, /*On fail goto*//*Label 3657*/ GIMT_Encode4(251719), // Rule ID 15793 //
     /*  251662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  251665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251687 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  251690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251717 */     GIR_RootConstrainSelectedInstOperands,
     /*  251718 */     // GIR_Coverage, 15793,
     /*  251718 */     GIR_EraseRootFromParent_Done,
     /*  251719 */   // Label 3657: @251719
     /*  251719 */   GIM_Try, /*On fail goto*//*Label 3658*/ GIMT_Encode4(251781), // Rule ID 15794 //
     /*  251724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  251727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251749 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  251752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251779 */     GIR_RootConstrainSelectedInstOperands,
     /*  251780 */     // GIR_Coverage, 15794,
     /*  251780 */     GIR_EraseRootFromParent_Done,
     /*  251781 */   // Label 3658: @251781
     /*  251781 */   GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(251843), // Rule ID 15795 //
     /*  251786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  251789 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251804 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251811 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  251814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251837 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251841 */     GIR_RootConstrainSelectedInstOperands,
     /*  251842 */     // GIR_Coverage, 15795,
     /*  251842 */     GIR_EraseRootFromParent_Done,
     /*  251843 */   // Label 3659: @251843
     /*  251843 */   GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(251905), // Rule ID 15796 //
     /*  251848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  251851 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251873 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  251876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251903 */     GIR_RootConstrainSelectedInstOperands,
     /*  251904 */     // GIR_Coverage, 15796,
     /*  251904 */     GIR_EraseRootFromParent_Done,
     /*  251905 */   // Label 3660: @251905
     /*  251905 */   GIM_Try, /*On fail goto*//*Label 3661*/ GIMT_Encode4(251967), // Rule ID 15797 //
     /*  251910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  251913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251935 */     // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  251938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  251940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  251945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  251950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  251955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  251961 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  251965 */     GIR_RootConstrainSelectedInstOperands,
     /*  251966 */     // GIR_Coverage, 15797,
     /*  251966 */     GIR_EraseRootFromParent_Done,
     /*  251967 */   // Label 3661: @251967
     /*  251967 */   GIM_Try, /*On fail goto*//*Label 3662*/ GIMT_Encode4(252029), // Rule ID 15803 //
     /*  251972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  251975 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  251982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  251986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  251990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  251997 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  251997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  252000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252027 */     GIR_RootConstrainSelectedInstOperands,
     /*  252028 */     // GIR_Coverage, 15803,
     /*  252028 */     GIR_EraseRootFromParent_Done,
     /*  252029 */   // Label 3662: @252029
     /*  252029 */   GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(252091), // Rule ID 15804 //
     /*  252034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  252037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252059 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  252062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252089 */     GIR_RootConstrainSelectedInstOperands,
     /*  252090 */     // GIR_Coverage, 15804,
     /*  252090 */     GIR_EraseRootFromParent_Done,
     /*  252091 */   // Label 3663: @252091
     /*  252091 */   GIM_Try, /*On fail goto*//*Label 3664*/ GIMT_Encode4(252153), // Rule ID 15805 //
     /*  252096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  252099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252121 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  252124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252151 */     GIR_RootConstrainSelectedInstOperands,
     /*  252152 */     // GIR_Coverage, 15805,
     /*  252152 */     GIR_EraseRootFromParent_Done,
     /*  252153 */   // Label 3664: @252153
     /*  252153 */   GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(252215), // Rule ID 15806 //
     /*  252158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  252161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252183 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  252186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252213 */     GIR_RootConstrainSelectedInstOperands,
     /*  252214 */     // GIR_Coverage, 15806,
     /*  252214 */     GIR_EraseRootFromParent_Done,
     /*  252215 */   // Label 3665: @252215
     /*  252215 */   GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(252277), // Rule ID 15807 //
     /*  252220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  252223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252245 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  252248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252275 */     GIR_RootConstrainSelectedInstOperands,
     /*  252276 */     // GIR_Coverage, 15807,
     /*  252276 */     GIR_EraseRootFromParent_Done,
     /*  252277 */   // Label 3666: @252277
     /*  252277 */   GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(252339), // Rule ID 15813 //
     /*  252282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  252285 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252307 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  252310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252337 */     GIR_RootConstrainSelectedInstOperands,
     /*  252338 */     // GIR_Coverage, 15813,
     /*  252338 */     GIR_EraseRootFromParent_Done,
     /*  252339 */   // Label 3667: @252339
     /*  252339 */   GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(252401), // Rule ID 15814 //
     /*  252344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  252347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252369 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  252372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252399 */     GIR_RootConstrainSelectedInstOperands,
     /*  252400 */     // GIR_Coverage, 15814,
     /*  252400 */     GIR_EraseRootFromParent_Done,
     /*  252401 */   // Label 3668: @252401
     /*  252401 */   GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(252463), // Rule ID 15815 //
     /*  252406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  252409 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252431 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  252434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252454 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252457 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252461 */     GIR_RootConstrainSelectedInstOperands,
     /*  252462 */     // GIR_Coverage, 15815,
     /*  252462 */     GIR_EraseRootFromParent_Done,
     /*  252463 */   // Label 3669: @252463
     /*  252463 */   GIM_Try, /*On fail goto*//*Label 3670*/ GIMT_Encode4(252525), // Rule ID 15816 //
     /*  252468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  252471 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252493 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  252496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252523 */     GIR_RootConstrainSelectedInstOperands,
     /*  252524 */     // GIR_Coverage, 15816,
     /*  252524 */     GIR_EraseRootFromParent_Done,
     /*  252525 */   // Label 3670: @252525
     /*  252525 */   GIM_Try, /*On fail goto*//*Label 3671*/ GIMT_Encode4(252587), // Rule ID 15817 //
     /*  252530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  252533 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  252540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252544 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252548 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  252555 */     // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  252555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  252558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  252560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  252565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  252570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  252575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252581 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252585 */     GIR_RootConstrainSelectedInstOperands,
     /*  252586 */     // GIR_Coverage, 15817,
     /*  252586 */     GIR_EraseRootFromParent_Done,
     /*  252587 */   // Label 3671: @252587
     /*  252587 */   GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(252644), // Rule ID 29533 //
     /*  252592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  252595 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252604 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252608 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252615 */     // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252642 */     GIR_RootConstrainSelectedInstOperands,
     /*  252643 */     // GIR_Coverage, 29533,
     /*  252643 */     GIR_EraseRootFromParent_Done,
     /*  252644 */   // Label 3672: @252644
     /*  252644 */   GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(252701), // Rule ID 29534 //
     /*  252649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  252652 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252672 */     // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252695 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252699 */     GIR_RootConstrainSelectedInstOperands,
     /*  252700 */     // GIR_Coverage, 29534,
     /*  252700 */     GIR_EraseRootFromParent_Done,
     /*  252701 */   // Label 3673: @252701
     /*  252701 */   GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(252758), // Rule ID 29535 //
     /*  252706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  252709 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252718 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252722 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252729 */     // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252756 */     GIR_RootConstrainSelectedInstOperands,
     /*  252757 */     // GIR_Coverage, 29535,
     /*  252757 */     GIR_EraseRootFromParent_Done,
     /*  252758 */   // Label 3674: @252758
     /*  252758 */   GIM_Try, /*On fail goto*//*Label 3675*/ GIMT_Encode4(252815), // Rule ID 29536 //
     /*  252763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  252766 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252786 */     // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252813 */     GIR_RootConstrainSelectedInstOperands,
     /*  252814 */     // GIR_Coverage, 29536,
     /*  252814 */     GIR_EraseRootFromParent_Done,
     /*  252815 */   // Label 3675: @252815
     /*  252815 */   GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(252872), // Rule ID 29537 //
     /*  252820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  252823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252843 */     // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252870 */     GIR_RootConstrainSelectedInstOperands,
     /*  252871 */     // GIR_Coverage, 29537,
     /*  252871 */     GIR_EraseRootFromParent_Done,
     /*  252872 */   // Label 3676: @252872
     /*  252872 */   GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(252929), // Rule ID 29553 //
     /*  252877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  252880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252900 */     // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252927 */     GIR_RootConstrainSelectedInstOperands,
     /*  252928 */     // GIR_Coverage, 29553,
     /*  252928 */     GIR_EraseRootFromParent_Done,
     /*  252929 */   // Label 3677: @252929
     /*  252929 */   GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(252986), // Rule ID 29554 //
     /*  252934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  252937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  252946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  252950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  252957 */     // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  252957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  252960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  252962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  252967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  252972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  252977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  252980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  252984 */     GIR_RootConstrainSelectedInstOperands,
     /*  252985 */     // GIR_Coverage, 29554,
     /*  252985 */     GIR_EraseRootFromParent_Done,
     /*  252986 */   // Label 3678: @252986
     /*  252986 */   GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(253043), // Rule ID 29555 //
     /*  252991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  252994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  252999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  253014 */     // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  253014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  253017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  253024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  253029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  253034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253041 */     GIR_RootConstrainSelectedInstOperands,
     /*  253042 */     // GIR_Coverage, 29555,
     /*  253042 */     GIR_EraseRootFromParent_Done,
     /*  253043 */   // Label 3679: @253043
     /*  253043 */   GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(253100), // Rule ID 29556 //
     /*  253048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  253051 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  253056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  253071 */     // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  253071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  253074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  253081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  253086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  253091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253098 */     GIR_RootConstrainSelectedInstOperands,
     /*  253099 */     // GIR_Coverage, 29556,
     /*  253099 */     GIR_EraseRootFromParent_Done,
     /*  253100 */   // Label 3680: @253100
     /*  253100 */   GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(253157), // Rule ID 29557 //
     /*  253105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  253108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  253113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  253128 */     // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  253128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  253131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  253138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  253143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  253148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253155 */     GIR_RootConstrainSelectedInstOperands,
     /*  253156 */     // GIR_Coverage, 29557,
     /*  253156 */     GIR_EraseRootFromParent_Done,
     /*  253157 */   // Label 3681: @253157
     /*  253157 */   GIM_Try, /*On fail goto*//*Label 3682*/ GIMT_Encode4(253218), // Rule ID 12493 //
     /*  253162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  253165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253180 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253187 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253216 */     GIR_RootConstrainSelectedInstOperands,
     /*  253217 */     // GIR_Coverage, 12493,
     /*  253217 */     GIR_EraseRootFromParent_Done,
     /*  253218 */   // Label 3682: @253218
     /*  253218 */   GIM_Try, /*On fail goto*//*Label 3683*/ GIMT_Encode4(253279), // Rule ID 12494 //
     /*  253223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  253226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253248 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253277 */     GIR_RootConstrainSelectedInstOperands,
     /*  253278 */     // GIR_Coverage, 12494,
     /*  253278 */     GIR_EraseRootFromParent_Done,
     /*  253279 */   // Label 3683: @253279
     /*  253279 */   GIM_Try, /*On fail goto*//*Label 3684*/ GIMT_Encode4(253340), // Rule ID 12495 //
     /*  253284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  253287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253298 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253302 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253309 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253338 */     GIR_RootConstrainSelectedInstOperands,
     /*  253339 */     // GIR_Coverage, 12495,
     /*  253339 */     GIR_EraseRootFromParent_Done,
     /*  253340 */   // Label 3684: @253340
     /*  253340 */   GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(253401), // Rule ID 12496 //
     /*  253345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  253348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253363 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253370 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253399 */     GIR_RootConstrainSelectedInstOperands,
     /*  253400 */     // GIR_Coverage, 12496,
     /*  253400 */     GIR_EraseRootFromParent_Done,
     /*  253401 */   // Label 3685: @253401
     /*  253401 */   GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(253462), // Rule ID 12497 //
     /*  253406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  253409 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253431 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253460 */     GIR_RootConstrainSelectedInstOperands,
     /*  253461 */     // GIR_Coverage, 12497,
     /*  253461 */     GIR_EraseRootFromParent_Done,
     /*  253462 */   // Label 3686: @253462
     /*  253462 */   GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(253523), // Rule ID 12513 //
     /*  253467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  253470 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253481 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253492 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253521 */     GIR_RootConstrainSelectedInstOperands,
     /*  253522 */     // GIR_Coverage, 12513,
     /*  253522 */     GIR_EraseRootFromParent_Done,
     /*  253523 */   // Label 3687: @253523
     /*  253523 */   GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(253584), // Rule ID 12514 //
     /*  253528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  253531 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253553 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253582 */     GIR_RootConstrainSelectedInstOperands,
     /*  253583 */     // GIR_Coverage, 12514,
     /*  253583 */     GIR_EraseRootFromParent_Done,
     /*  253584 */   // Label 3688: @253584
     /*  253584 */   GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(253645), // Rule ID 12515 //
     /*  253589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  253592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253603 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253614 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253639 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253643 */     GIR_RootConstrainSelectedInstOperands,
     /*  253644 */     // GIR_Coverage, 12515,
     /*  253644 */     GIR_EraseRootFromParent_Done,
     /*  253645 */   // Label 3689: @253645
     /*  253645 */   GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(253706), // Rule ID 12516 //
     /*  253650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  253653 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253675 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253704 */     GIR_RootConstrainSelectedInstOperands,
     /*  253705 */     // GIR_Coverage, 12516,
     /*  253705 */     GIR_EraseRootFromParent_Done,
     /*  253706 */   // Label 3690: @253706
     /*  253706 */   GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(253767), // Rule ID 12517 //
     /*  253711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  253714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  253736 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  253736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  253739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  253746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  253751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  253756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  253761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253765 */     GIR_RootConstrainSelectedInstOperands,
     /*  253766 */     // GIR_Coverage, 12517,
     /*  253766 */     GIR_EraseRootFromParent_Done,
     /*  253767 */   // Label 3691: @253767
     /*  253767 */   GIM_Try, /*On fail goto*//*Label 3692*/ GIMT_Encode4(253821), // Rule ID 12488 //
     /*  253772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  253775 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  253797 */     // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  253797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  253800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  253807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  253812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253819 */     GIR_RootConstrainSelectedInstOperands,
     /*  253820 */     // GIR_Coverage, 12488,
     /*  253820 */     GIR_EraseRootFromParent_Done,
     /*  253821 */   // Label 3692: @253821
     /*  253821 */   GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(253875), // Rule ID 12489 //
     /*  253826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  253829 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  253851 */     // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  253851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  253854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  253861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  253866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253869 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253873 */     GIR_RootConstrainSelectedInstOperands,
     /*  253874 */     // GIR_Coverage, 12489,
     /*  253874 */     GIR_EraseRootFromParent_Done,
     /*  253875 */   // Label 3693: @253875
     /*  253875 */   GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(253929), // Rule ID 12490 //
     /*  253880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  253883 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  253905 */     // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  253905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  253908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  253915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  253920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253927 */     GIR_RootConstrainSelectedInstOperands,
     /*  253928 */     // GIR_Coverage, 12490,
     /*  253928 */     GIR_EraseRootFromParent_Done,
     /*  253929 */   // Label 3694: @253929
     /*  253929 */   GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(253983), // Rule ID 12491 //
     /*  253934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  253937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  253948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  253952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  253959 */     // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  253959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  253962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  253964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  253969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  253974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  253977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  253981 */     GIR_RootConstrainSelectedInstOperands,
     /*  253982 */     // GIR_Coverage, 12491,
     /*  253982 */     GIR_EraseRootFromParent_Done,
     /*  253983 */   // Label 3695: @253983
     /*  253983 */   GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(254037), // Rule ID 12492 //
     /*  253988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  253991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  253998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  254013 */     // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  254016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254031 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254035 */     GIR_RootConstrainSelectedInstOperands,
     /*  254036 */     // GIR_Coverage, 12492,
     /*  254036 */     GIR_EraseRootFromParent_Done,
     /*  254037 */   // Label 3696: @254037
     /*  254037 */   GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(254091), // Rule ID 12508 //
     /*  254042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  254045 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  254067 */     // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  254070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254089 */     GIR_RootConstrainSelectedInstOperands,
     /*  254090 */     // GIR_Coverage, 12508,
     /*  254090 */     GIR_EraseRootFromParent_Done,
     /*  254091 */   // Label 3697: @254091
     /*  254091 */   GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(254145), // Rule ID 12509 //
     /*  254096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  254099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  254121 */     // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  254124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254143 */     GIR_RootConstrainSelectedInstOperands,
     /*  254144 */     // GIR_Coverage, 12509,
     /*  254144 */     GIR_EraseRootFromParent_Done,
     /*  254145 */   // Label 3698: @254145
     /*  254145 */   GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(254199), // Rule ID 12510 //
     /*  254150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  254153 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  254175 */     // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  254178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254197 */     GIR_RootConstrainSelectedInstOperands,
     /*  254198 */     // GIR_Coverage, 12510,
     /*  254198 */     GIR_EraseRootFromParent_Done,
     /*  254199 */   // Label 3699: @254199
     /*  254199 */   GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(254253), // Rule ID 12511 //
     /*  254204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  254207 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  254229 */     // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  254232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254251 */     GIR_RootConstrainSelectedInstOperands,
     /*  254252 */     // GIR_Coverage, 12511,
     /*  254252 */     GIR_EraseRootFromParent_Done,
     /*  254253 */   // Label 3700: @254253
     /*  254253 */   GIM_Try, /*On fail goto*//*Label 3701*/ GIMT_Encode4(254307), // Rule ID 12512 //
     /*  254258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  254261 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  254283 */     // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  254286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254305 */     GIR_RootConstrainSelectedInstOperands,
     /*  254306 */     // GIR_Coverage, 12512,
     /*  254306 */     GIR_EraseRootFromParent_Done,
     /*  254307 */   // Label 3701: @254307
     /*  254307 */   GIM_Try, /*On fail goto*//*Label 3702*/ GIMT_Encode4(254369), // Rule ID 10351 //
     /*  254312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  254315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254338 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254367 */     GIR_RootConstrainSelectedInstOperands,
     /*  254368 */     // GIR_Coverage, 10351,
     /*  254368 */     GIR_EraseRootFromParent_Done,
     /*  254369 */   // Label 3702: @254369
     /*  254369 */   GIM_Try, /*On fail goto*//*Label 3703*/ GIMT_Encode4(254431), // Rule ID 10352 //
     /*  254374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  254377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254400 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254429 */     GIR_RootConstrainSelectedInstOperands,
     /*  254430 */     // GIR_Coverage, 10352,
     /*  254430 */     GIR_EraseRootFromParent_Done,
     /*  254431 */   // Label 3703: @254431
     /*  254431 */   GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(254493), // Rule ID 10353 //
     /*  254436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  254439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254462 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254487 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254491 */     GIR_RootConstrainSelectedInstOperands,
     /*  254492 */     // GIR_Coverage, 10353,
     /*  254492 */     GIR_EraseRootFromParent_Done,
     /*  254493 */   // Label 3704: @254493
     /*  254493 */   GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(254555), // Rule ID 10354 //
     /*  254498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  254501 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254524 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254553 */     GIR_RootConstrainSelectedInstOperands,
     /*  254554 */     // GIR_Coverage, 10354,
     /*  254554 */     GIR_EraseRootFromParent_Done,
     /*  254555 */   // Label 3705: @254555
     /*  254555 */   GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(254617), // Rule ID 10355 //
     /*  254560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  254563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254575 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254586 */     // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254615 */     GIR_RootConstrainSelectedInstOperands,
     /*  254616 */     // GIR_Coverage, 10355,
     /*  254616 */     GIR_EraseRootFromParent_Done,
     /*  254617 */   // Label 3706: @254617
     /*  254617 */   GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(254679), // Rule ID 10371 //
     /*  254622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  254625 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254648 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254677 */     GIR_RootConstrainSelectedInstOperands,
     /*  254678 */     // GIR_Coverage, 10371,
     /*  254678 */     GIR_EraseRootFromParent_Done,
     /*  254679 */   // Label 3707: @254679
     /*  254679 */   GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(254741), // Rule ID 10372 //
     /*  254684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  254687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254710 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254739 */     GIR_RootConstrainSelectedInstOperands,
     /*  254740 */     // GIR_Coverage, 10372,
     /*  254740 */     GIR_EraseRootFromParent_Done,
     /*  254741 */   // Label 3708: @254741
     /*  254741 */   GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(254803), // Rule ID 10373 //
     /*  254746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  254749 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254772 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254797 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254801 */     GIR_RootConstrainSelectedInstOperands,
     /*  254802 */     // GIR_Coverage, 10373,
     /*  254802 */     GIR_EraseRootFromParent_Done,
     /*  254803 */   // Label 3709: @254803
     /*  254803 */   GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(254865), // Rule ID 10374 //
     /*  254808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  254811 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254834 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254859 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254863 */     GIR_RootConstrainSelectedInstOperands,
     /*  254864 */     // GIR_Coverage, 10374,
     /*  254864 */     GIR_EraseRootFromParent_Done,
     /*  254865 */   // Label 3710: @254865
     /*  254865 */   GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(254927), // Rule ID 10375 //
     /*  254870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  254873 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  254896 */     // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  254896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  254899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  254906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  254911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  254916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  254921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254925 */     GIR_RootConstrainSelectedInstOperands,
     /*  254926 */     // GIR_Coverage, 10375,
     /*  254926 */     GIR_EraseRootFromParent_Done,
     /*  254927 */   // Label 3711: @254927
     /*  254927 */   GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(254982), // Rule ID 10346 //
     /*  254932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  254935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  254947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  254951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  254958 */     // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  254958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  254961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  254963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  254968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  254973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  254976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  254980 */     GIR_RootConstrainSelectedInstOperands,
     /*  254981 */     // GIR_Coverage, 10346,
     /*  254981 */     GIR_EraseRootFromParent_Done,
     /*  254982 */   // Label 3712: @254982
     /*  254982 */   GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(255037), // Rule ID 10347 //
     /*  254987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  254990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  254998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255013 */     // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255031 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255035 */     GIR_RootConstrainSelectedInstOperands,
     /*  255036 */     // GIR_Coverage, 10347,
     /*  255036 */     GIR_EraseRootFromParent_Done,
     /*  255037 */   // Label 3713: @255037
     /*  255037 */   GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(255092), // Rule ID 10348 //
     /*  255042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  255045 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255057 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255068 */     // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255083 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255090 */     GIR_RootConstrainSelectedInstOperands,
     /*  255091 */     // GIR_Coverage, 10348,
     /*  255091 */     GIR_EraseRootFromParent_Done,
     /*  255092 */   // Label 3714: @255092
     /*  255092 */   GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(255147), // Rule ID 10349 //
     /*  255097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  255100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255112 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255116 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255123 */     // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255145 */     GIR_RootConstrainSelectedInstOperands,
     /*  255146 */     // GIR_Coverage, 10349,
     /*  255146 */     GIR_EraseRootFromParent_Done,
     /*  255147 */   // Label 3715: @255147
     /*  255147 */   GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(255202), // Rule ID 10350 //
     /*  255152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  255155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255167 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255171 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255178 */     // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255196 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255200 */     GIR_RootConstrainSelectedInstOperands,
     /*  255201 */     // GIR_Coverage, 10350,
     /*  255201 */     GIR_EraseRootFromParent_Done,
     /*  255202 */   // Label 3716: @255202
     /*  255202 */   GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(255257), // Rule ID 10366 //
     /*  255207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  255210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255233 */     // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255255 */     GIR_RootConstrainSelectedInstOperands,
     /*  255256 */     // GIR_Coverage, 10366,
     /*  255256 */     GIR_EraseRootFromParent_Done,
     /*  255257 */   // Label 3717: @255257
     /*  255257 */   GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(255312), // Rule ID 10367 //
     /*  255262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  255265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255288 */     // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255306 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255310 */     GIR_RootConstrainSelectedInstOperands,
     /*  255311 */     // GIR_Coverage, 10367,
     /*  255311 */     GIR_EraseRootFromParent_Done,
     /*  255312 */   // Label 3718: @255312
     /*  255312 */   GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(255367), // Rule ID 10368 //
     /*  255317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  255320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255332 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255343 */     // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255365 */     GIR_RootConstrainSelectedInstOperands,
     /*  255366 */     // GIR_Coverage, 10368,
     /*  255366 */     GIR_EraseRootFromParent_Done,
     /*  255367 */   // Label 3719: @255367
     /*  255367 */   GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(255422), // Rule ID 10369 //
     /*  255372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  255375 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255398 */     // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255416 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255420 */     GIR_RootConstrainSelectedInstOperands,
     /*  255421 */     // GIR_Coverage, 10369,
     /*  255421 */     GIR_EraseRootFromParent_Done,
     /*  255422 */   // Label 3720: @255422
     /*  255422 */   GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(255477), // Rule ID 10370 //
     /*  255427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  255430 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  255438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  255442 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255446 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  255453 */     // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  255453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  255456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  255458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  255463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255471 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255475 */     GIR_RootConstrainSelectedInstOperands,
     /*  255476 */     // GIR_Coverage, 10370,
     /*  255476 */     GIR_EraseRootFromParent_Done,
     /*  255477 */   // Label 3721: @255477
     /*  255477 */   GIM_Reject,
     /*  255478 */ // Label 3517: @255478
     /*  255478 */ GIM_Reject,
     /*  255479 */ // Label 1132: @255479
     /*  255479 */ GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(265235),
     /*  255484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  255487 */   GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(255553), // Rule ID 8892 //
     /*  255492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  255495 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255507 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255511 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  255515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  255522 */     // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  255522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  255525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  255537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  255542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  255547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255551 */     GIR_RootConstrainSelectedInstOperands,
     /*  255552 */     // GIR_Coverage, 8892,
     /*  255552 */     GIR_EraseRootFromParent_Done,
     /*  255553 */   // Label 3723: @255553
     /*  255553 */   GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(255619), // Rule ID 8907 //
     /*  255558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  255561 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255573 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255577 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  255581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  255588 */     // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  255588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  255591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  255603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  255608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  255613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255617 */     GIR_RootConstrainSelectedInstOperands,
     /*  255618 */     // GIR_Coverage, 8907,
     /*  255618 */     GIR_EraseRootFromParent_Done,
     /*  255619 */   // Label 3724: @255619
     /*  255619 */   GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(255681), // Rule ID 8897 //
     /*  255624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  255627 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255639 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  255650 */     // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  255650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec),
     /*  255653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  255665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  255670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  255675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255679 */     GIR_RootConstrainSelectedInstOperands,
     /*  255680 */     // GIR_Coverage, 8897,
     /*  255680 */     GIR_EraseRootFromParent_Done,
     /*  255681 */   // Label 3725: @255681
     /*  255681 */   GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(255743), // Rule ID 8912 //
     /*  255686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  255689 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255697 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255701 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255705 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  255712 */     // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  255712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec),
     /*  255715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  255727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  255732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  255737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255741 */     GIR_RootConstrainSelectedInstOperands,
     /*  255742 */     // GIR_Coverage, 8912,
     /*  255742 */     GIR_EraseRootFromParent_Done,
     /*  255743 */   // Label 3726: @255743
     /*  255743 */   GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(255805), // Rule ID 8902 //
     /*  255748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  255751 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255763 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  255774 */     // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  255774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  255777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  255789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  255794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  255799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255803 */     GIR_RootConstrainSelectedInstOperands,
     /*  255804 */     // GIR_Coverage, 8902,
     /*  255804 */     GIR_EraseRootFromParent_Done,
     /*  255805 */   // Label 3727: @255805
     /*  255805 */   GIM_Try, /*On fail goto*//*Label 3728*/ GIMT_Encode4(255867), // Rule ID 8917 //
     /*  255810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  255813 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255825 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  255836 */     // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  255836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  255839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  255851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  255856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  255861 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255865 */     GIR_RootConstrainSelectedInstOperands,
     /*  255866 */     // GIR_Coverage, 8917,
     /*  255866 */     GIR_EraseRootFromParent_Done,
     /*  255867 */   // Label 3728: @255867
     /*  255867 */   GIM_Try, /*On fail goto*//*Label 3729*/ GIMT_Encode4(255926), // Rule ID 8889 //
     /*  255872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  255875 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255887 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255891 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  255895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  255902 */     // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  255902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  255905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255920 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255924 */     GIR_RootConstrainSelectedInstOperands,
     /*  255925 */     // GIR_Coverage, 8889,
     /*  255925 */     GIR_EraseRootFromParent_Done,
     /*  255926 */   // Label 3729: @255926
     /*  255926 */   GIM_Try, /*On fail goto*//*Label 3730*/ GIMT_Encode4(255985), // Rule ID 8904 //
     /*  255931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  255934 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  255942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  255946 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  255950 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  255954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  255961 */     // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  255961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  255964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  255966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  255971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  255976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  255979 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  255983 */     GIR_RootConstrainSelectedInstOperands,
     /*  255984 */     // GIR_Coverage, 8904,
     /*  255984 */     GIR_EraseRootFromParent_Done,
     /*  255985 */   // Label 3730: @255985
     /*  255985 */   GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(256040), // Rule ID 8894 //
     /*  255990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  255993 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  255997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  256001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256005 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  256009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  256016 */     // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  256016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec),
     /*  256019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  256021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  256026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256038 */     GIR_RootConstrainSelectedInstOperands,
     /*  256039 */     // GIR_Coverage, 8894,
     /*  256039 */     GIR_EraseRootFromParent_Done,
     /*  256040 */   // Label 3731: @256040
     /*  256040 */   GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(256095), // Rule ID 8909 //
     /*  256045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  256048 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  256056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256060 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  256064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  256071 */     // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  256071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec),
     /*  256074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  256076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  256081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256086 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256089 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256093 */     GIR_RootConstrainSelectedInstOperands,
     /*  256094 */     // GIR_Coverage, 8909,
     /*  256094 */     GIR_EraseRootFromParent_Done,
     /*  256095 */   // Label 3732: @256095
     /*  256095 */   GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(256155), // Rule ID 29783 //
     /*  256100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  256103 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256107 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256112 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256131 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256153 */     GIR_RootConstrainSelectedInstOperands,
     /*  256154 */     // GIR_Coverage, 29783,
     /*  256154 */     GIR_EraseRootFromParent_Done,
     /*  256155 */   // Label 3733: @256155
     /*  256155 */   GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(256215), // Rule ID 29784 //
     /*  256160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  256163 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256167 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256172 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256191 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256213 */     GIR_RootConstrainSelectedInstOperands,
     /*  256214 */     // GIR_Coverage, 29784,
     /*  256214 */     GIR_EraseRootFromParent_Done,
     /*  256215 */   // Label 3734: @256215
     /*  256215 */   GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(256275), // Rule ID 29785 //
     /*  256220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  256223 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256227 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256232 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256244 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256251 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256269 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256273 */     GIR_RootConstrainSelectedInstOperands,
     /*  256274 */     // GIR_Coverage, 29785,
     /*  256274 */     GIR_EraseRootFromParent_Done,
     /*  256275 */   // Label 3735: @256275
     /*  256275 */   GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(256335), // Rule ID 29786 //
     /*  256280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  256283 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256292 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256311 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256333 */     GIR_RootConstrainSelectedInstOperands,
     /*  256334 */     // GIR_Coverage, 29786,
     /*  256334 */     GIR_EraseRootFromParent_Done,
     /*  256335 */   // Label 3736: @256335
     /*  256335 */   GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(256395), // Rule ID 29787 //
     /*  256340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  256343 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256352 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256371 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256389 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256393 */     GIR_RootConstrainSelectedInstOperands,
     /*  256394 */     // GIR_Coverage, 29787,
     /*  256394 */     GIR_EraseRootFromParent_Done,
     /*  256395 */   // Label 3737: @256395
     /*  256395 */   GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(256455), // Rule ID 29803 //
     /*  256400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  256403 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256412 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256431 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256446 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256449 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256453 */     GIR_RootConstrainSelectedInstOperands,
     /*  256454 */     // GIR_Coverage, 29803,
     /*  256454 */     GIR_EraseRootFromParent_Done,
     /*  256455 */   // Label 3738: @256455
     /*  256455 */   GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(256515), // Rule ID 29804 //
     /*  256460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  256463 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256472 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256480 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256484 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256491 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256513 */     GIR_RootConstrainSelectedInstOperands,
     /*  256514 */     // GIR_Coverage, 29804,
     /*  256514 */     GIR_EraseRootFromParent_Done,
     /*  256515 */   // Label 3739: @256515
     /*  256515 */   GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(256575), // Rule ID 29805 //
     /*  256520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  256523 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256532 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256551 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256569 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256573 */     GIR_RootConstrainSelectedInstOperands,
     /*  256574 */     // GIR_Coverage, 29805,
     /*  256574 */     GIR_EraseRootFromParent_Done,
     /*  256575 */   // Label 3740: @256575
     /*  256575 */   GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(256635), // Rule ID 29806 //
     /*  256580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  256583 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256587 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256592 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256611 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256633 */     GIR_RootConstrainSelectedInstOperands,
     /*  256634 */     // GIR_Coverage, 29806,
     /*  256634 */     GIR_EraseRootFromParent_Done,
     /*  256635 */   // Label 3741: @256635
     /*  256635 */   GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(256695), // Rule ID 29807 //
     /*  256640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  256643 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256652 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  256656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256671 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256693 */     GIR_RootConstrainSelectedInstOperands,
     /*  256694 */     // GIR_Coverage, 29807,
     /*  256694 */     GIR_EraseRootFromParent_Done,
     /*  256695 */   // Label 3742: @256695
     /*  256695 */   GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(256751), // Rule ID 30123 //
     /*  256700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  256703 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256727 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256749 */     GIR_RootConstrainSelectedInstOperands,
     /*  256750 */     // GIR_Coverage, 30123,
     /*  256750 */     GIR_EraseRootFromParent_Done,
     /*  256751 */   // Label 3743: @256751
     /*  256751 */   GIM_Try, /*On fail goto*//*Label 3744*/ GIMT_Encode4(256807), // Rule ID 30124 //
     /*  256756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  256759 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256763 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256772 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256783 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256805 */     GIR_RootConstrainSelectedInstOperands,
     /*  256806 */     // GIR_Coverage, 30124,
     /*  256806 */     GIR_EraseRootFromParent_Done,
     /*  256807 */   // Label 3744: @256807
     /*  256807 */   GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(256863), // Rule ID 30125 //
     /*  256812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  256815 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256839 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256861 */     GIR_RootConstrainSelectedInstOperands,
     /*  256862 */     // GIR_Coverage, 30125,
     /*  256862 */     GIR_EraseRootFromParent_Done,
     /*  256863 */   // Label 3745: @256863
     /*  256863 */   GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(256919), // Rule ID 30126 //
     /*  256868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  256871 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256875 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256884 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256895 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256913 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256917 */     GIR_RootConstrainSelectedInstOperands,
     /*  256918 */     // GIR_Coverage, 30126,
     /*  256918 */     GIR_EraseRootFromParent_Done,
     /*  256919 */   // Label 3746: @256919
     /*  256919 */   GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(256975), // Rule ID 30127 //
     /*  256924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  256927 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256940 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  256944 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  256951 */     // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  256951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  256954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  256956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  256961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  256966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  256969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  256973 */     GIR_RootConstrainSelectedInstOperands,
     /*  256974 */     // GIR_Coverage, 30127,
     /*  256974 */     GIR_EraseRootFromParent_Done,
     /*  256975 */   // Label 3747: @256975
     /*  256975 */   GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(257031), // Rule ID 30143 //
     /*  256980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  256983 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  256987 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  256992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  256996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257000 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257007 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  257010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257022 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257025 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257029 */     GIR_RootConstrainSelectedInstOperands,
     /*  257030 */     // GIR_Coverage, 30143,
     /*  257030 */     GIR_EraseRootFromParent_Done,
     /*  257031 */   // Label 3748: @257031
     /*  257031 */   GIM_Try, /*On fail goto*//*Label 3749*/ GIMT_Encode4(257087), // Rule ID 30144 //
     /*  257036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  257039 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  257043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257052 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257056 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257063 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  257066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257085 */     GIR_RootConstrainSelectedInstOperands,
     /*  257086 */     // GIR_Coverage, 30144,
     /*  257086 */     GIR_EraseRootFromParent_Done,
     /*  257087 */   // Label 3749: @257087
     /*  257087 */   GIM_Try, /*On fail goto*//*Label 3750*/ GIMT_Encode4(257143), // Rule ID 30145 //
     /*  257092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  257095 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  257099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257119 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  257122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257141 */     GIR_RootConstrainSelectedInstOperands,
     /*  257142 */     // GIR_Coverage, 30145,
     /*  257142 */     GIR_EraseRootFromParent_Done,
     /*  257143 */   // Label 3750: @257143
     /*  257143 */   GIM_Try, /*On fail goto*//*Label 3751*/ GIMT_Encode4(257199), // Rule ID 30146 //
     /*  257148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  257151 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  257155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257175 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  257178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257197 */     GIR_RootConstrainSelectedInstOperands,
     /*  257198 */     // GIR_Coverage, 30146,
     /*  257198 */     GIR_EraseRootFromParent_Done,
     /*  257199 */   // Label 3751: @257199
     /*  257199 */   GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(257255), // Rule ID 30147 //
     /*  257204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  257207 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  257211 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257231 */     // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
     /*  257234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257249 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257253 */     GIR_RootConstrainSelectedInstOperands,
     /*  257254 */     // GIR_Coverage, 30147,
     /*  257254 */     GIR_EraseRootFromParent_Done,
     /*  257255 */   // Label 3752: @257255
     /*  257255 */   GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(257307), // Rule ID 8899 //
     /*  257260 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  257264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  257268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257272 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  257276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  257283 */     // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  257283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  257286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  257288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  257293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257305 */     GIR_RootConstrainSelectedInstOperands,
     /*  257306 */     // GIR_Coverage, 8899,
     /*  257306 */     GIR_EraseRootFromParent_Done,
     /*  257307 */   // Label 3753: @257307
     /*  257307 */   GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(257359), // Rule ID 8914 //
     /*  257312 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  257316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  257320 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257324 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  257328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  257335 */     // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  257335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  257338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  257340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  257345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257353 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257357 */     GIR_RootConstrainSelectedInstOperands,
     /*  257358 */     // GIR_Coverage, 8914,
     /*  257358 */     GIR_EraseRootFromParent_Done,
     /*  257359 */   // Label 3754: @257359
     /*  257359 */   GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(257415), // Rule ID 29788 //
     /*  257364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  257367 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257372 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257380 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257391 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257413 */     GIR_RootConstrainSelectedInstOperands,
     /*  257414 */     // GIR_Coverage, 29788,
     /*  257414 */     GIR_EraseRootFromParent_Done,
     /*  257415 */   // Label 3755: @257415
     /*  257415 */   GIM_Try, /*On fail goto*//*Label 3756*/ GIMT_Encode4(257471), // Rule ID 29789 //
     /*  257420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  257423 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257428 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257447 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257469 */     GIR_RootConstrainSelectedInstOperands,
     /*  257470 */     // GIR_Coverage, 29789,
     /*  257470 */     GIR_EraseRootFromParent_Done,
     /*  257471 */   // Label 3756: @257471
     /*  257471 */   GIM_Try, /*On fail goto*//*Label 3757*/ GIMT_Encode4(257527), // Rule ID 29790 //
     /*  257476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  257479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257484 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257492 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257503 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257525 */     GIR_RootConstrainSelectedInstOperands,
     /*  257526 */     // GIR_Coverage, 29790,
     /*  257526 */     GIR_EraseRootFromParent_Done,
     /*  257527 */   // Label 3757: @257527
     /*  257527 */   GIM_Try, /*On fail goto*//*Label 3758*/ GIMT_Encode4(257583), // Rule ID 29791 //
     /*  257532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  257535 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257540 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257559 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257581 */     GIR_RootConstrainSelectedInstOperands,
     /*  257582 */     // GIR_Coverage, 29791,
     /*  257582 */     GIR_EraseRootFromParent_Done,
     /*  257583 */   // Label 3758: @257583
     /*  257583 */   GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(257639), // Rule ID 29792 //
     /*  257588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  257591 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257596 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257604 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257608 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257615 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257637 */     GIR_RootConstrainSelectedInstOperands,
     /*  257638 */     // GIR_Coverage, 29792,
     /*  257638 */     GIR_EraseRootFromParent_Done,
     /*  257639 */   // Label 3759: @257639
     /*  257639 */   GIM_Try, /*On fail goto*//*Label 3760*/ GIMT_Encode4(257695), // Rule ID 29808 //
     /*  257644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  257647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257652 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257671 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257693 */     GIR_RootConstrainSelectedInstOperands,
     /*  257694 */     // GIR_Coverage, 29808,
     /*  257694 */     GIR_EraseRootFromParent_Done,
     /*  257695 */   // Label 3760: @257695
     /*  257695 */   GIM_Try, /*On fail goto*//*Label 3761*/ GIMT_Encode4(257751), // Rule ID 29809 //
     /*  257700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  257703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257708 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257727 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257749 */     GIR_RootConstrainSelectedInstOperands,
     /*  257750 */     // GIR_Coverage, 29809,
     /*  257750 */     GIR_EraseRootFromParent_Done,
     /*  257751 */   // Label 3761: @257751
     /*  257751 */   GIM_Try, /*On fail goto*//*Label 3762*/ GIMT_Encode4(257807), // Rule ID 29810 //
     /*  257756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  257759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257764 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257772 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257783 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257805 */     GIR_RootConstrainSelectedInstOperands,
     /*  257806 */     // GIR_Coverage, 29810,
     /*  257806 */     GIR_EraseRootFromParent_Done,
     /*  257807 */   // Label 3762: @257807
     /*  257807 */   GIM_Try, /*On fail goto*//*Label 3763*/ GIMT_Encode4(257863), // Rule ID 29811 //
     /*  257812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  257815 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257820 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257839 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257861 */     GIR_RootConstrainSelectedInstOperands,
     /*  257862 */     // GIR_Coverage, 29811,
     /*  257862 */     GIR_EraseRootFromParent_Done,
     /*  257863 */   // Label 3763: @257863
     /*  257863 */   GIM_Try, /*On fail goto*//*Label 3764*/ GIMT_Encode4(257919), // Rule ID 29812 //
     /*  257868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  257871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257876 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  257880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257884 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257895 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257913 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257917 */     GIR_RootConstrainSelectedInstOperands,
     /*  257918 */     // GIR_Coverage, 29812,
     /*  257918 */     GIR_EraseRootFromParent_Done,
     /*  257919 */   // Label 3764: @257919
     /*  257919 */   GIM_Try, /*On fail goto*//*Label 3765*/ GIMT_Encode4(257971), // Rule ID 30128 //
     /*  257924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  257927 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257947 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  257950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  257952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  257957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  257962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  257965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  257969 */     GIR_RootConstrainSelectedInstOperands,
     /*  257970 */     // GIR_Coverage, 30128,
     /*  257970 */     GIR_EraseRootFromParent_Done,
     /*  257971 */   // Label 3765: @257971
     /*  257971 */   GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(258023), // Rule ID 30129 //
     /*  257976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  257979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  257984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  257988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  257992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  257999 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  257999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258021 */     GIR_RootConstrainSelectedInstOperands,
     /*  258022 */     // GIR_Coverage, 30129,
     /*  258022 */     GIR_EraseRootFromParent_Done,
     /*  258023 */   // Label 3766: @258023
     /*  258023 */   GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(258075), // Rule ID 30130 //
     /*  258028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  258031 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258040 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258044 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258051 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258069 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258073 */     GIR_RootConstrainSelectedInstOperands,
     /*  258074 */     // GIR_Coverage, 30130,
     /*  258074 */     GIR_EraseRootFromParent_Done,
     /*  258075 */   // Label 3767: @258075
     /*  258075 */   GIM_Try, /*On fail goto*//*Label 3768*/ GIMT_Encode4(258127), // Rule ID 30131 //
     /*  258080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  258083 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258092 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258096 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258103 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258121 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258125 */     GIR_RootConstrainSelectedInstOperands,
     /*  258126 */     // GIR_Coverage, 30131,
     /*  258126 */     GIR_EraseRootFromParent_Done,
     /*  258127 */   // Label 3768: @258127
     /*  258127 */   GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(258179), // Rule ID 30132 //
     /*  258132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  258135 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258144 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258155 */     // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258177 */     GIR_RootConstrainSelectedInstOperands,
     /*  258178 */     // GIR_Coverage, 30132,
     /*  258178 */     GIR_EraseRootFromParent_Done,
     /*  258179 */   // Label 3769: @258179
     /*  258179 */   GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(258231), // Rule ID 30148 //
     /*  258184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  258187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258200 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258207 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258225 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258229 */     GIR_RootConstrainSelectedInstOperands,
     /*  258230 */     // GIR_Coverage, 30148,
     /*  258230 */     GIR_EraseRootFromParent_Done,
     /*  258231 */   // Label 3770: @258231
     /*  258231 */   GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(258283), // Rule ID 30149 //
     /*  258236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  258239 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258259 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258281 */     GIR_RootConstrainSelectedInstOperands,
     /*  258282 */     // GIR_Coverage, 30149,
     /*  258282 */     GIR_EraseRootFromParent_Done,
     /*  258283 */   // Label 3771: @258283
     /*  258283 */   GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(258335), // Rule ID 30150 //
     /*  258288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  258291 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258311 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258333 */     GIR_RootConstrainSelectedInstOperands,
     /*  258334 */     // GIR_Coverage, 30150,
     /*  258334 */     GIR_EraseRootFromParent_Done,
     /*  258335 */   // Label 3772: @258335
     /*  258335 */   GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(258387), // Rule ID 30151 //
     /*  258340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  258343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258352 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258363 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258381 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258385 */     GIR_RootConstrainSelectedInstOperands,
     /*  258386 */     // GIR_Coverage, 30151,
     /*  258386 */     GIR_EraseRootFromParent_Done,
     /*  258387 */   // Label 3773: @258387
     /*  258387 */   GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(258439), // Rule ID 30152 //
     /*  258392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  258395 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  258400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  258404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  258415 */     // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  258415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
     /*  258418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  258420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  258425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  258430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258437 */     GIR_RootConstrainSelectedInstOperands,
     /*  258438 */     // GIR_Coverage, 30152,
     /*  258438 */     GIR_EraseRootFromParent_Done,
     /*  258439 */   // Label 3774: @258439
     /*  258439 */   GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(258498), // Rule ID 8890 //
     /*  258444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  258447 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258459 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258463 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  258467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258474 */     // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  258474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR),
     /*  258477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258492 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258496 */     GIR_RootConstrainSelectedInstOperands,
     /*  258497 */     // GIR_Coverage, 8890,
     /*  258497 */     GIR_EraseRootFromParent_Done,
     /*  258498 */   // Label 3775: @258498
     /*  258498 */   GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(258562), // Rule ID 8891 //
     /*  258503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  258506 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258518 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258522 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  258526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258533 */     // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  258533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  258536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  258556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258560 */     GIR_RootConstrainSelectedInstOperands,
     /*  258561 */     // GIR_Coverage, 8891,
     /*  258561 */     GIR_EraseRootFromParent_Done,
     /*  258562 */   // Label 3776: @258562
     /*  258562 */   GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(258621), // Rule ID 8905 //
     /*  258567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  258570 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258582 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258586 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  258590 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258597 */     // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  258597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR),
     /*  258600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258615 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258619 */     GIR_RootConstrainSelectedInstOperands,
     /*  258620 */     // GIR_Coverage, 8905,
     /*  258620 */     GIR_EraseRootFromParent_Done,
     /*  258621 */   // Label 3777: @258621
     /*  258621 */   GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(258685), // Rule ID 8906 //
     /*  258626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  258629 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258641 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258645 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  258649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258656 */     // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  258656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  258659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  258679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258683 */     GIR_RootConstrainSelectedInstOperands,
     /*  258684 */     // GIR_Coverage, 8906,
     /*  258684 */     GIR_EraseRootFromParent_Done,
     /*  258685 */   // Label 3778: @258685
     /*  258685 */   GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(258736), // Rule ID 8893 //
     /*  258690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  258693 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258701 */     // MIs[0] sbase
     /*  258701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  258705 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  258709 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258713 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  258717 */     // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  258717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  258720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258722 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  258724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258734 */     GIR_RootConstrainSelectedInstOperands,
     /*  258735 */     // GIR_Coverage, 8893,
     /*  258735 */     GIR_EraseRootFromParent_Done,
     /*  258736 */   // Label 3779: @258736
     /*  258736 */   GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(258787), // Rule ID 8908 //
     /*  258741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  258744 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258752 */     // MIs[0] sbase
     /*  258752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  258756 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  258760 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258764 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  258768 */     // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  258768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  258771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258773 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  258775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258785 */     GIR_RootConstrainSelectedInstOperands,
     /*  258786 */     // GIR_Coverage, 8908,
     /*  258786 */     GIR_EraseRootFromParent_Done,
     /*  258787 */   // Label 3780: @258787
     /*  258787 */   GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(258842), // Rule ID 8895 //
     /*  258792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  258795 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258807 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258818 */     // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  258818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_ec),
     /*  258821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258840 */     GIR_RootConstrainSelectedInstOperands,
     /*  258841 */     // GIR_Coverage, 8895,
     /*  258841 */     GIR_EraseRootFromParent_Done,
     /*  258842 */   // Label 3781: @258842
     /*  258842 */   GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(258902), // Rule ID 8896 //
     /*  258847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  258850 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258862 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258873 */     // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  258873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec),
     /*  258876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  258896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258900 */     GIR_RootConstrainSelectedInstOperands,
     /*  258901 */     // GIR_Coverage, 8896,
     /*  258901 */     GIR_EraseRootFromParent_Done,
     /*  258902 */   // Label 3782: @258902
     /*  258902 */   GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(258957), // Rule ID 8910 //
     /*  258907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  258910 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258922 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258933 */     // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  258933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_ec),
     /*  258936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  258948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  258951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  258955 */     GIR_RootConstrainSelectedInstOperands,
     /*  258956 */     // GIR_Coverage, 8910,
     /*  258956 */     GIR_EraseRootFromParent_Done,
     /*  258957 */   // Label 3783: @258957
     /*  258957 */   GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(259017), // Rule ID 8911 //
     /*  258962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  258965 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  258969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  258973 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  258977 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  258981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  258988 */     // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  258988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec),
     /*  258991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  258993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  258998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  259011 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259015 */     GIR_RootConstrainSelectedInstOperands,
     /*  259016 */     // GIR_Coverage, 8911,
     /*  259016 */     GIR_EraseRootFromParent_Done,
     /*  259017 */   // Label 3784: @259017
     /*  259017 */   GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(259064), // Rule ID 8898 //
     /*  259022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  259025 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259033 */     // MIs[0] sbase
     /*  259033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  259037 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  259041 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259045 */     // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM_ec:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  259045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec),
     /*  259048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259050 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  259052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259062 */     GIR_RootConstrainSelectedInstOperands,
     /*  259063 */     // GIR_Coverage, 8898,
     /*  259063 */     GIR_EraseRootFromParent_Done,
     /*  259064 */   // Label 3785: @259064
     /*  259064 */   GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(259111), // Rule ID 8913 //
     /*  259069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  259072 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259080 */     // MIs[0] sbase
     /*  259080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  259084 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  259088 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259092 */     // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM_ec:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  259092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec),
     /*  259095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259097 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  259099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259105 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259109 */     GIR_RootConstrainSelectedInstOperands,
     /*  259110 */     // GIR_Coverage, 8913,
     /*  259110 */     GIR_EraseRootFromParent_Done,
     /*  259111 */   // Label 3786: @259111
     /*  259111 */   GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(259166), // Rule ID 8900 //
     /*  259116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  259119 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259131 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  259142 */     // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  259142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR),
     /*  259145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  259152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259164 */     GIR_RootConstrainSelectedInstOperands,
     /*  259165 */     // GIR_Coverage, 8900,
     /*  259165 */     GIR_EraseRootFromParent_Done,
     /*  259166 */   // Label 3787: @259166
     /*  259166 */   GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(259226), // Rule ID 8901 //
     /*  259171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  259174 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259186 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259190 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  259197 */     // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  259197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  259200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  259207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259212 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  259220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259224 */     GIR_RootConstrainSelectedInstOperands,
     /*  259225 */     // GIR_Coverage, 8901,
     /*  259225 */     GIR_EraseRootFromParent_Done,
     /*  259226 */   // Label 3788: @259226
     /*  259226 */   GIM_Try, /*On fail goto*//*Label 3789*/ GIMT_Encode4(259281), // Rule ID 8915 //
     /*  259231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  259234 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259246 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  259257 */     // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  259257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR),
     /*  259260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  259267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259279 */     GIR_RootConstrainSelectedInstOperands,
     /*  259280 */     // GIR_Coverage, 8915,
     /*  259280 */     GIR_EraseRootFromParent_Done,
     /*  259281 */   // Label 3789: @259281
     /*  259281 */   GIM_Try, /*On fail goto*//*Label 3790*/ GIMT_Encode4(259341), // Rule ID 8916 //
     /*  259286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  259289 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259301 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  259312 */     // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  259312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
     /*  259315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  259322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  259335 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259339 */     GIR_RootConstrainSelectedInstOperands,
     /*  259340 */     // GIR_Coverage, 8916,
     /*  259340 */     GIR_EraseRootFromParent_Done,
     /*  259341 */   // Label 3790: @259341
     /*  259341 */   GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(259385), // Rule ID 8903 //
     /*  259346 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259354 */     // MIs[0] sbase
     /*  259354 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  259358 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  259362 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259366 */     // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  259366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  259369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259371 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  259373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259383 */     GIR_RootConstrainSelectedInstOperands,
     /*  259384 */     // GIR_Coverage, 8903,
     /*  259384 */     GIR_EraseRootFromParent_Done,
     /*  259385 */   // Label 3791: @259385
     /*  259385 */   GIM_Try, /*On fail goto*//*Label 3792*/ GIMT_Encode4(259429), // Rule ID 8918 //
     /*  259390 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  259394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
     /*  259398 */     // MIs[0] sbase
     /*  259398 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  259402 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  259406 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  259410 */     // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  259410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
     /*  259413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  259415 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  259417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259427 */     GIR_RootConstrainSelectedInstOperands,
     /*  259428 */     // GIR_Coverage, 8918,
     /*  259428 */     GIR_EraseRootFromParent_Done,
     /*  259429 */   // Label 3792: @259429
     /*  259429 */   GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(259489), // Rule ID 25356 //
     /*  259434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  259437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259446 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259450 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259457 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  259460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259487 */     GIR_RootConstrainSelectedInstOperands,
     /*  259488 */     // GIR_Coverage, 25356,
     /*  259488 */     GIR_EraseRootFromParent_Done,
     /*  259489 */   // Label 3793: @259489
     /*  259489 */   GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(259549), // Rule ID 25357 //
     /*  259494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  259497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259517 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  259520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259540 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259547 */     GIR_RootConstrainSelectedInstOperands,
     /*  259548 */     // GIR_Coverage, 25357,
     /*  259548 */     GIR_EraseRootFromParent_Done,
     /*  259549 */   // Label 3794: @259549
     /*  259549 */   GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(259609), // Rule ID 25358 //
     /*  259554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  259557 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259577 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  259580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259607 */     GIR_RootConstrainSelectedInstOperands,
     /*  259608 */     // GIR_Coverage, 25358,
     /*  259608 */     GIR_EraseRootFromParent_Done,
     /*  259609 */   // Label 3795: @259609
     /*  259609 */   GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(259669), // Rule ID 25359 //
     /*  259614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  259617 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259626 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259637 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  259640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259667 */     GIR_RootConstrainSelectedInstOperands,
     /*  259668 */     // GIR_Coverage, 25359,
     /*  259668 */     GIR_EraseRootFromParent_Done,
     /*  259669 */   // Label 3796: @259669
     /*  259669 */   GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(259729), // Rule ID 25360 //
     /*  259674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  259677 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259697 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  259700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259727 */     GIR_RootConstrainSelectedInstOperands,
     /*  259728 */     // GIR_Coverage, 25360,
     /*  259728 */     GIR_EraseRootFromParent_Done,
     /*  259729 */   // Label 3797: @259729
     /*  259729 */   GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(259789), // Rule ID 25366 //
     /*  259734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  259737 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259757 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  259760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259787 */     GIR_RootConstrainSelectedInstOperands,
     /*  259788 */     // GIR_Coverage, 25366,
     /*  259788 */     GIR_EraseRootFromParent_Done,
     /*  259789 */   // Label 3798: @259789
     /*  259789 */   GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(259849), // Rule ID 25367 //
     /*  259794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  259797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259806 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259817 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  259820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259843 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259847 */     GIR_RootConstrainSelectedInstOperands,
     /*  259848 */     // GIR_Coverage, 25367,
     /*  259848 */     GIR_EraseRootFromParent_Done,
     /*  259849 */   // Label 3799: @259849
     /*  259849 */   GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(259909), // Rule ID 25368 //
     /*  259854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  259857 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259877 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  259880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259897 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259900 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259903 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259907 */     GIR_RootConstrainSelectedInstOperands,
     /*  259908 */     // GIR_Coverage, 25368,
     /*  259908 */     GIR_EraseRootFromParent_Done,
     /*  259909 */   // Label 3800: @259909
     /*  259909 */   GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(259969), // Rule ID 25369 //
     /*  259914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  259917 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259937 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  259940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  259942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  259947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  259952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  259957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  259963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  259967 */     GIR_RootConstrainSelectedInstOperands,
     /*  259968 */     // GIR_Coverage, 25369,
     /*  259968 */     GIR_EraseRootFromParent_Done,
     /*  259969 */   // Label 3801: @259969
     /*  259969 */   GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(260029), // Rule ID 25370 //
     /*  259974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  259977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  259982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  259986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  259990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  259997 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  259997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  260000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  260002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  260007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  260012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  260017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260027 */     GIR_RootConstrainSelectedInstOperands,
     /*  260028 */     // GIR_Coverage, 25370,
     /*  260028 */     GIR_EraseRootFromParent_Done,
     /*  260029 */   // Label 3802: @260029
     /*  260029 */   GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(260088), // Rule ID 14572 //
     /*  260034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  260037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260050 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  260057 */     // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  260057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS),
     /*  260060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  260072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  260077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  260082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260086 */     GIR_RootConstrainSelectedInstOperands,
     /*  260087 */     // GIR_Coverage, 14572,
     /*  260087 */     GIR_EraseRootFromParent_Done,
     /*  260088 */   // Label 3803: @260088
     /*  260088 */   GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(260147), // Rule ID 14573 //
     /*  260093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  260096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  260116 */     // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  260116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS),
     /*  260119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  260131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  260136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  260141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260145 */     GIR_RootConstrainSelectedInstOperands,
     /*  260146 */     // GIR_Coverage, 14573,
     /*  260146 */     GIR_EraseRootFromParent_Done,
     /*  260147 */   // Label 3804: @260147
     /*  260147 */   GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(260206), // Rule ID 14574 //
     /*  260152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  260155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  260175 */     // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  260175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS),
     /*  260178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  260190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  260195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  260200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260204 */     GIR_RootConstrainSelectedInstOperands,
     /*  260205 */     // GIR_Coverage, 14574,
     /*  260205 */     GIR_EraseRootFromParent_Done,
     /*  260206 */   // Label 3805: @260206
     /*  260206 */   GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(260265), // Rule ID 14575 //
     /*  260211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  260214 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  260234 */     // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  260234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS),
     /*  260237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  260249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  260254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  260259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260263 */     GIR_RootConstrainSelectedInstOperands,
     /*  260264 */     // GIR_Coverage, 14575,
     /*  260264 */     GIR_EraseRootFromParent_Done,
     /*  260265 */   // Label 3806: @260265
     /*  260265 */   GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(260324), // Rule ID 14576 //
     /*  260270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  260273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  260293 */     // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  260293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS),
     /*  260296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  260308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  260313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  260318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260322 */     GIR_RootConstrainSelectedInstOperands,
     /*  260323 */     // GIR_Coverage, 14576,
     /*  260323 */     GIR_EraseRootFromParent_Done,
     /*  260324 */   // Label 3807: @260324
     /*  260324 */   GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(260376), // Rule ID 14567 //
     /*  260329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  260332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260341 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  260352 */     // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  260352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR),
     /*  260355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  260362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260374 */     GIR_RootConstrainSelectedInstOperands,
     /*  260375 */     // GIR_Coverage, 14567,
     /*  260375 */     GIR_EraseRootFromParent_Done,
     /*  260376 */   // Label 3808: @260376
     /*  260376 */   GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(260428), // Rule ID 14568 //
     /*  260381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  260384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  260404 */     // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  260404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR),
     /*  260407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  260414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260426 */     GIR_RootConstrainSelectedInstOperands,
     /*  260427 */     // GIR_Coverage, 14568,
     /*  260427 */     GIR_EraseRootFromParent_Done,
     /*  260428 */   // Label 3809: @260428
     /*  260428 */   GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(260480), // Rule ID 14569 //
     /*  260433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  260436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260445 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  260456 */     // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  260456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR),
     /*  260459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  260466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260478 */     GIR_RootConstrainSelectedInstOperands,
     /*  260479 */     // GIR_Coverage, 14569,
     /*  260479 */     GIR_EraseRootFromParent_Done,
     /*  260480 */   // Label 3810: @260480
     /*  260480 */   GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(260532), // Rule ID 14570 //
     /*  260485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  260488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  260508 */     // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  260508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR),
     /*  260511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  260518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260530 */     GIR_RootConstrainSelectedInstOperands,
     /*  260531 */     // GIR_Coverage, 14570,
     /*  260531 */     GIR_EraseRootFromParent_Done,
     /*  260532 */   // Label 3811: @260532
     /*  260532 */   GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(260584), // Rule ID 14571 //
     /*  260537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  260540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  260560 */     // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  260560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR),
     /*  260563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  260570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260582 */     GIR_RootConstrainSelectedInstOperands,
     /*  260583 */     // GIR_Coverage, 14571,
     /*  260583 */     GIR_EraseRootFromParent_Done,
     /*  260584 */   // Label 3812: @260584
     /*  260584 */   GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(260636), // Rule ID 14562 //
     /*  260589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  260592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260601 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  260612 */     // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  260612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3),
     /*  260615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260634 */     GIR_RootConstrainSelectedInstOperands,
     /*  260635 */     // GIR_Coverage, 14562,
     /*  260635 */     GIR_EraseRootFromParent_Done,
     /*  260636 */   // Label 3813: @260636
     /*  260636 */   GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(260688), // Rule ID 14563 //
     /*  260641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  260644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  260664 */     // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  260664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3),
     /*  260667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260686 */     GIR_RootConstrainSelectedInstOperands,
     /*  260687 */     // GIR_Coverage, 14563,
     /*  260687 */     GIR_EraseRootFromParent_Done,
     /*  260688 */   // Label 3814: @260688
     /*  260688 */   GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(260740), // Rule ID 14564 //
     /*  260693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  260696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260705 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  260716 */     // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  260716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3),
     /*  260719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260738 */     GIR_RootConstrainSelectedInstOperands,
     /*  260739 */     // GIR_Coverage, 14564,
     /*  260739 */     GIR_EraseRootFromParent_Done,
     /*  260740 */   // Label 3815: @260740
     /*  260740 */   GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(260792), // Rule ID 14565 //
     /*  260745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  260748 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260757 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  260768 */     // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  260768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3),
     /*  260771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260783 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260790 */     GIR_RootConstrainSelectedInstOperands,
     /*  260791 */     // GIR_Coverage, 14565,
     /*  260791 */     GIR_EraseRootFromParent_Done,
     /*  260792 */   // Label 3816: @260792
     /*  260792 */   GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(260844), // Rule ID 14566 //
     /*  260797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  260800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  260805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  260820 */     // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  260820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3),
     /*  260823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  260825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  260830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  260835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260842 */     GIR_RootConstrainSelectedInstOperands,
     /*  260843 */     // GIR_Coverage, 14566,
     /*  260843 */     GIR_EraseRootFromParent_Done,
     /*  260844 */   // Label 3817: @260844
     /*  260844 */   GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(260911), // Rule ID 15708 //
     /*  260849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  260852 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  260859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  260874 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  260874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  260877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  260879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  260884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  260889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  260894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  260899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260909 */     GIR_RootConstrainSelectedInstOperands,
     /*  260910 */     // GIR_Coverage, 15708,
     /*  260910 */     GIR_EraseRootFromParent_Done,
     /*  260911 */   // Label 3818: @260911
     /*  260911 */   GIM_Try, /*On fail goto*//*Label 3819*/ GIMT_Encode4(260978), // Rule ID 15709 //
     /*  260916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  260919 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  260926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  260934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  260941 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  260941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  260944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  260946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  260951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  260956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  260961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  260966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  260972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  260976 */     GIR_RootConstrainSelectedInstOperands,
     /*  260977 */     // GIR_Coverage, 15709,
     /*  260977 */     GIR_EraseRootFromParent_Done,
     /*  260978 */   // Label 3819: @260978
     /*  260978 */   GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(261045), // Rule ID 15710 //
     /*  260983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  260986 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  260993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  260997 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261008 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261043 */     GIR_RootConstrainSelectedInstOperands,
     /*  261044 */     // GIR_Coverage, 15710,
     /*  261044 */     GIR_EraseRootFromParent_Done,
     /*  261045 */   // Label 3820: @261045
     /*  261045 */   GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(261112), // Rule ID 15711 //
     /*  261050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  261053 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261075 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261110 */     GIR_RootConstrainSelectedInstOperands,
     /*  261111 */     // GIR_Coverage, 15711,
     /*  261111 */     GIR_EraseRootFromParent_Done,
     /*  261112 */   // Label 3821: @261112
     /*  261112 */   GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(261179), // Rule ID 15712 //
     /*  261117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  261120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261142 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261177 */     GIR_RootConstrainSelectedInstOperands,
     /*  261178 */     // GIR_Coverage, 15712,
     /*  261178 */     GIR_EraseRootFromParent_Done,
     /*  261179 */   // Label 3822: @261179
     /*  261179 */   GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(261246), // Rule ID 15718 //
     /*  261184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  261187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261202 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261209 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261244 */     GIR_RootConstrainSelectedInstOperands,
     /*  261245 */     // GIR_Coverage, 15718,
     /*  261245 */     GIR_EraseRootFromParent_Done,
     /*  261246 */   // Label 3823: @261246
     /*  261246 */   GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(261313), // Rule ID 15719 //
     /*  261251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  261254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261276 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261311 */     GIR_RootConstrainSelectedInstOperands,
     /*  261312 */     // GIR_Coverage, 15719,
     /*  261312 */     GIR_EraseRootFromParent_Done,
     /*  261313 */   // Label 3824: @261313
     /*  261313 */   GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(261380), // Rule ID 15720 //
     /*  261318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  261321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261332 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261343 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261378 */     GIR_RootConstrainSelectedInstOperands,
     /*  261379 */     // GIR_Coverage, 15720,
     /*  261379 */     GIR_EraseRootFromParent_Done,
     /*  261380 */   // Label 3825: @261380
     /*  261380 */   GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(261447), // Rule ID 15721 //
     /*  261385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  261388 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261410 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261445 */     GIR_RootConstrainSelectedInstOperands,
     /*  261446 */     // GIR_Coverage, 15721,
     /*  261446 */     GIR_EraseRootFromParent_Done,
     /*  261447 */   // Label 3826: @261447
     /*  261447 */   GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(261514), // Rule ID 15722 //
     /*  261452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  261455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261466 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261470 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261477 */     // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261512 */     GIR_RootConstrainSelectedInstOperands,
     /*  261513 */     // GIR_Coverage, 15722,
     /*  261513 */     GIR_EraseRootFromParent_Done,
     /*  261514 */   // Label 3827: @261514
     /*  261514 */   GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(261581), // Rule ID 15728 //
     /*  261519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  261522 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261544 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261579 */     GIR_RootConstrainSelectedInstOperands,
     /*  261580 */     // GIR_Coverage, 15728,
     /*  261580 */     GIR_EraseRootFromParent_Done,
     /*  261581 */   // Label 3828: @261581
     /*  261581 */   GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(261648), // Rule ID 15729 //
     /*  261586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  261589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261611 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261646 */     GIR_RootConstrainSelectedInstOperands,
     /*  261647 */     // GIR_Coverage, 15729,
     /*  261647 */     GIR_EraseRootFromParent_Done,
     /*  261648 */   // Label 3829: @261648
     /*  261648 */   GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(261715), // Rule ID 15730 //
     /*  261653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  261656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261678 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261713 */     GIR_RootConstrainSelectedInstOperands,
     /*  261714 */     // GIR_Coverage, 15730,
     /*  261714 */     GIR_EraseRootFromParent_Done,
     /*  261715 */   // Label 3830: @261715
     /*  261715 */   GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(261782), // Rule ID 15731 //
     /*  261720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  261723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261745 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261780 */     GIR_RootConstrainSelectedInstOperands,
     /*  261781 */     // GIR_Coverage, 15731,
     /*  261781 */     GIR_EraseRootFromParent_Done,
     /*  261782 */   // Label 3831: @261782
     /*  261782 */   GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(261849), // Rule ID 15732 //
     /*  261787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  261790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261812 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
     /*  261815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261843 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261847 */     GIR_RootConstrainSelectedInstOperands,
     /*  261848 */     // GIR_Coverage, 15732,
     /*  261848 */     GIR_EraseRootFromParent_Done,
     /*  261849 */   // Label 3832: @261849
     /*  261849 */   GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(261916), // Rule ID 15738 //
     /*  261854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  261857 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261879 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261914 */     GIR_RootConstrainSelectedInstOperands,
     /*  261915 */     // GIR_Coverage, 15738,
     /*  261915 */     GIR_EraseRootFromParent_Done,
     /*  261916 */   // Label 3833: @261916
     /*  261916 */   GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(261983), // Rule ID 15739 //
     /*  261921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  261924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  261935 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  261939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  261946 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  261946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  261949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  261951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  261956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  261961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  261966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  261971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  261977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  261981 */     GIR_RootConstrainSelectedInstOperands,
     /*  261982 */     // GIR_Coverage, 15739,
     /*  261982 */     GIR_EraseRootFromParent_Done,
     /*  261983 */   // Label 3834: @261983
     /*  261983 */   GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(262050), // Rule ID 15740 //
     /*  261988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  261991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  261998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  262013 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  262013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  262016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262044 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262048 */     GIR_RootConstrainSelectedInstOperands,
     /*  262049 */     // GIR_Coverage, 15740,
     /*  262049 */     GIR_EraseRootFromParent_Done,
     /*  262050 */   // Label 3835: @262050
     /*  262050 */   GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(262117), // Rule ID 15741 //
     /*  262055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  262058 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  262065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  262080 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  262080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  262083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262115 */     GIR_RootConstrainSelectedInstOperands,
     /*  262116 */     // GIR_Coverage, 15741,
     /*  262116 */     GIR_EraseRootFromParent_Done,
     /*  262117 */   // Label 3836: @262117
     /*  262117 */   GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(262184), // Rule ID 15742 //
     /*  262122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  262125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  262132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  262147 */     // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  262147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
     /*  262150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262172 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262182 */     GIR_RootConstrainSelectedInstOperands,
     /*  262183 */     // GIR_Coverage, 15742,
     /*  262183 */     GIR_EraseRootFromParent_Done,
     /*  262184 */   // Label 3837: @262184
     /*  262184 */   GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(262249), // Rule ID 25351 //
     /*  262189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  262192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262212 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
     /*  262215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262247 */     GIR_RootConstrainSelectedInstOperands,
     /*  262248 */     // GIR_Coverage, 25351,
     /*  262248 */     GIR_EraseRootFromParent_Done,
     /*  262249 */   // Label 3838: @262249
     /*  262249 */   GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(262314), // Rule ID 25352 //
     /*  262254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  262257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262266 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262277 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
     /*  262280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262312 */     GIR_RootConstrainSelectedInstOperands,
     /*  262313 */     // GIR_Coverage, 25352,
     /*  262313 */     GIR_EraseRootFromParent_Done,
     /*  262314 */   // Label 3839: @262314
     /*  262314 */   GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(262379), // Rule ID 25353 //
     /*  262319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  262322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262342 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
     /*  262345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262377 */     GIR_RootConstrainSelectedInstOperands,
     /*  262378 */     // GIR_Coverage, 25353,
     /*  262378 */     GIR_EraseRootFromParent_Done,
     /*  262379 */   // Label 3840: @262379
     /*  262379 */   GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(262444), // Rule ID 25354 //
     /*  262384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  262387 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262407 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
     /*  262410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262442 */     GIR_RootConstrainSelectedInstOperands,
     /*  262443 */     // GIR_Coverage, 25354,
     /*  262443 */     GIR_EraseRootFromParent_Done,
     /*  262444 */   // Label 3841: @262444
     /*  262444 */   GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(262509), // Rule ID 25355 //
     /*  262449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  262452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262472 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
     /*  262475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262507 */     GIR_RootConstrainSelectedInstOperands,
     /*  262508 */     // GIR_Coverage, 25355,
     /*  262508 */     GIR_EraseRootFromParent_Done,
     /*  262509 */   // Label 3842: @262509
     /*  262509 */   GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(262574), // Rule ID 25361 //
     /*  262514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  262517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262537 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
     /*  262540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262572 */     GIR_RootConstrainSelectedInstOperands,
     /*  262573 */     // GIR_Coverage, 25361,
     /*  262573 */     GIR_EraseRootFromParent_Done,
     /*  262574 */   // Label 3843: @262574
     /*  262574 */   GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(262639), // Rule ID 25362 //
     /*  262579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  262582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262602 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
     /*  262605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262637 */     GIR_RootConstrainSelectedInstOperands,
     /*  262638 */     // GIR_Coverage, 25362,
     /*  262638 */     GIR_EraseRootFromParent_Done,
     /*  262639 */   // Label 3844: @262639
     /*  262639 */   GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(262704), // Rule ID 25363 //
     /*  262644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  262647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262667 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
     /*  262670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262702 */     GIR_RootConstrainSelectedInstOperands,
     /*  262703 */     // GIR_Coverage, 25363,
     /*  262703 */     GIR_EraseRootFromParent_Done,
     /*  262704 */   // Label 3845: @262704
     /*  262704 */   GIM_Try, /*On fail goto*//*Label 3846*/ GIMT_Encode4(262769), // Rule ID 25364 //
     /*  262709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  262712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262732 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
     /*  262735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262767 */     GIR_RootConstrainSelectedInstOperands,
     /*  262768 */     // GIR_Coverage, 25364,
     /*  262768 */     GIR_EraseRootFromParent_Done,
     /*  262769 */   // Label 3846: @262769
     /*  262769 */   GIM_Try, /*On fail goto*//*Label 3847*/ GIMT_Encode4(262834), // Rule ID 25365 //
     /*  262774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  262777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  262782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  262797 */     // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  262797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
     /*  262800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  262807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  262817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  262822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262832 */     GIR_RootConstrainSelectedInstOperands,
     /*  262833 */     // GIR_Coverage, 25365,
     /*  262833 */     GIR_EraseRootFromParent_Done,
     /*  262834 */   // Label 3847: @262834
     /*  262834 */   GIM_Try, /*On fail goto*//*Label 3848*/ GIMT_Encode4(262896), // Rule ID 15703 //
     /*  262839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  262842 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  262849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  262864 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  262864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  262867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  262879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  262884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262894 */     GIR_RootConstrainSelectedInstOperands,
     /*  262895 */     // GIR_Coverage, 15703,
     /*  262895 */     GIR_EraseRootFromParent_Done,
     /*  262896 */   // Label 3848: @262896
     /*  262896 */   GIM_Try, /*On fail goto*//*Label 3849*/ GIMT_Encode4(262958), // Rule ID 15704 //
     /*  262901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  262904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  262911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  262926 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  262926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  262929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  262941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  262946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  262952 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  262956 */     GIR_RootConstrainSelectedInstOperands,
     /*  262957 */     // GIR_Coverage, 15704,
     /*  262957 */     GIR_EraseRootFromParent_Done,
     /*  262958 */   // Label 3849: @262958
     /*  262958 */   GIM_Try, /*On fail goto*//*Label 3850*/ GIMT_Encode4(263020), // Rule ID 15705 //
     /*  262963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  262966 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  262973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  262977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  262981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  262988 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  262988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  262991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  262993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  262998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263018 */     GIR_RootConstrainSelectedInstOperands,
     /*  263019 */     // GIR_Coverage, 15705,
     /*  263019 */     GIR_EraseRootFromParent_Done,
     /*  263020 */   // Label 3850: @263020
     /*  263020 */   GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(263082), // Rule ID 15706 //
     /*  263025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  263028 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263050 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263080 */     GIR_RootConstrainSelectedInstOperands,
     /*  263081 */     // GIR_Coverage, 15706,
     /*  263081 */     GIR_EraseRootFromParent_Done,
     /*  263082 */   // Label 3851: @263082
     /*  263082 */   GIM_Try, /*On fail goto*//*Label 3852*/ GIMT_Encode4(263144), // Rule ID 15707 //
     /*  263087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  263090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263112 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263142 */     GIR_RootConstrainSelectedInstOperands,
     /*  263143 */     // GIR_Coverage, 15707,
     /*  263143 */     GIR_EraseRootFromParent_Done,
     /*  263144 */   // Label 3852: @263144
     /*  263144 */   GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(263206), // Rule ID 15713 //
     /*  263149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  263152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263174 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263204 */     GIR_RootConstrainSelectedInstOperands,
     /*  263205 */     // GIR_Coverage, 15713,
     /*  263205 */     GIR_EraseRootFromParent_Done,
     /*  263206 */   // Label 3853: @263206
     /*  263206 */   GIM_Try, /*On fail goto*//*Label 3854*/ GIMT_Encode4(263268), // Rule ID 15714 //
     /*  263211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  263214 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263236 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263266 */     GIR_RootConstrainSelectedInstOperands,
     /*  263267 */     // GIR_Coverage, 15714,
     /*  263267 */     GIR_EraseRootFromParent_Done,
     /*  263268 */   // Label 3854: @263268
     /*  263268 */   GIM_Try, /*On fail goto*//*Label 3855*/ GIMT_Encode4(263330), // Rule ID 15715 //
     /*  263273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  263276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263298 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263328 */     GIR_RootConstrainSelectedInstOperands,
     /*  263329 */     // GIR_Coverage, 15715,
     /*  263329 */     GIR_EraseRootFromParent_Done,
     /*  263330 */   // Label 3855: @263330
     /*  263330 */   GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(263392), // Rule ID 15716 //
     /*  263335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  263338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263360 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263390 */     GIR_RootConstrainSelectedInstOperands,
     /*  263391 */     // GIR_Coverage, 15716,
     /*  263391 */     GIR_EraseRootFromParent_Done,
     /*  263392 */   // Label 3856: @263392
     /*  263392 */   GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(263454), // Rule ID 15717 //
     /*  263397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  263400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263422 */     // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263452 */     GIR_RootConstrainSelectedInstOperands,
     /*  263453 */     // GIR_Coverage, 15717,
     /*  263453 */     GIR_EraseRootFromParent_Done,
     /*  263454 */   // Label 3857: @263454
     /*  263454 */   GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(263516), // Rule ID 15723 //
     /*  263459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  263462 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263484 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263514 */     GIR_RootConstrainSelectedInstOperands,
     /*  263515 */     // GIR_Coverage, 15723,
     /*  263515 */     GIR_EraseRootFromParent_Done,
     /*  263516 */   // Label 3858: @263516
     /*  263516 */   GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(263578), // Rule ID 15724 //
     /*  263521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  263524 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263546 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263576 */     GIR_RootConstrainSelectedInstOperands,
     /*  263577 */     // GIR_Coverage, 15724,
     /*  263577 */     GIR_EraseRootFromParent_Done,
     /*  263578 */   // Label 3859: @263578
     /*  263578 */   GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(263640), // Rule ID 15725 //
     /*  263583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  263586 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263608 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263638 */     GIR_RootConstrainSelectedInstOperands,
     /*  263639 */     // GIR_Coverage, 15725,
     /*  263639 */     GIR_EraseRootFromParent_Done,
     /*  263640 */   // Label 3860: @263640
     /*  263640 */   GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(263702), // Rule ID 15726 //
     /*  263645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  263648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263670 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263700 */     GIR_RootConstrainSelectedInstOperands,
     /*  263701 */     // GIR_Coverage, 15726,
     /*  263701 */     GIR_EraseRootFromParent_Done,
     /*  263702 */   // Label 3861: @263702
     /*  263702 */   GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(263764), // Rule ID 15727 //
     /*  263707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  263710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263732 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
     /*  263735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263762 */     GIR_RootConstrainSelectedInstOperands,
     /*  263763 */     // GIR_Coverage, 15727,
     /*  263763 */     GIR_EraseRootFromParent_Done,
     /*  263764 */   // Label 3862: @263764
     /*  263764 */   GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(263826), // Rule ID 15733 //
     /*  263769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  263772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263794 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263824 */     GIR_RootConstrainSelectedInstOperands,
     /*  263825 */     // GIR_Coverage, 15733,
     /*  263825 */     GIR_EraseRootFromParent_Done,
     /*  263826 */   // Label 3863: @263826
     /*  263826 */   GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(263888), // Rule ID 15734 //
     /*  263831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  263834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263856 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263886 */     GIR_RootConstrainSelectedInstOperands,
     /*  263887 */     // GIR_Coverage, 15734,
     /*  263887 */     GIR_EraseRootFromParent_Done,
     /*  263888 */   // Label 3864: @263888
     /*  263888 */   GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(263950), // Rule ID 15735 //
     /*  263893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  263896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263918 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  263938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  263944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  263948 */     GIR_RootConstrainSelectedInstOperands,
     /*  263949 */     // GIR_Coverage, 15735,
     /*  263949 */     GIR_EraseRootFromParent_Done,
     /*  263950 */   // Label 3865: @263950
     /*  263950 */   GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(264012), // Rule ID 15736 //
     /*  263955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  263958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  263965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  263969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  263973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  263980 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  263980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  263983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  263985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  263990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  263995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264010 */     GIR_RootConstrainSelectedInstOperands,
     /*  264011 */     // GIR_Coverage, 15736,
     /*  264011 */     GIR_EraseRootFromParent_Done,
     /*  264012 */   // Label 3866: @264012
     /*  264012 */   GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(264074), // Rule ID 15737 //
     /*  264017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  264020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  264042 */     // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  264042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
     /*  264045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  264047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  264052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  264057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264072 */     GIR_RootConstrainSelectedInstOperands,
     /*  264073 */     // GIR_Coverage, 15737,
     /*  264073 */     GIR_EraseRootFromParent_Done,
     /*  264074 */   // Label 3867: @264074
     /*  264074 */   GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(264135), // Rule ID 12443 //
     /*  264079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  264082 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264104 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR),
     /*  264107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264133 */     GIR_RootConstrainSelectedInstOperands,
     /*  264134 */     // GIR_Coverage, 12443,
     /*  264134 */     GIR_EraseRootFromParent_Done,
     /*  264135 */   // Label 3868: @264135
     /*  264135 */   GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(264196), // Rule ID 12444 //
     /*  264140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  264143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264165 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR),
     /*  264168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264194 */     GIR_RootConstrainSelectedInstOperands,
     /*  264195 */     // GIR_Coverage, 12444,
     /*  264195 */     GIR_EraseRootFromParent_Done,
     /*  264196 */   // Label 3869: @264196
     /*  264196 */   GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(264257), // Rule ID 12445 //
     /*  264201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  264204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264215 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264226 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR),
     /*  264229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264255 */     GIR_RootConstrainSelectedInstOperands,
     /*  264256 */     // GIR_Coverage, 12445,
     /*  264256 */     GIR_EraseRootFromParent_Done,
     /*  264257 */   // Label 3870: @264257
     /*  264257 */   GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(264318), // Rule ID 12446 //
     /*  264262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  264265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264280 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264287 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR),
     /*  264290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264316 */     GIR_RootConstrainSelectedInstOperands,
     /*  264317 */     // GIR_Coverage, 12446,
     /*  264317 */     GIR_EraseRootFromParent_Done,
     /*  264318 */   // Label 3871: @264318
     /*  264318 */   GIM_Try, /*On fail goto*//*Label 3872*/ GIMT_Encode4(264379), // Rule ID 12447 //
     /*  264323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  264326 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264348 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR),
     /*  264351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264377 */     GIR_RootConstrainSelectedInstOperands,
     /*  264378 */     // GIR_Coverage, 12447,
     /*  264378 */     GIR_EraseRootFromParent_Done,
     /*  264379 */   // Label 3872: @264379
     /*  264379 */   GIM_Try, /*On fail goto*//*Label 3873*/ GIMT_Encode4(264433), // Rule ID 12438 //
     /*  264384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  264387 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264398 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  264409 */     // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  264409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3),
     /*  264412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  264419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  264424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264431 */     GIR_RootConstrainSelectedInstOperands,
     /*  264432 */     // GIR_Coverage, 12438,
     /*  264432 */     GIR_EraseRootFromParent_Done,
     /*  264433 */   // Label 3873: @264433
     /*  264433 */   GIM_Try, /*On fail goto*//*Label 3874*/ GIMT_Encode4(264487), // Rule ID 12439 //
     /*  264438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  264441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264452 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  264463 */     // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  264463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3),
     /*  264466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  264473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  264478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264485 */     GIR_RootConstrainSelectedInstOperands,
     /*  264486 */     // GIR_Coverage, 12439,
     /*  264486 */     GIR_EraseRootFromParent_Done,
     /*  264487 */   // Label 3874: @264487
     /*  264487 */   GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(264541), // Rule ID 12440 //
     /*  264492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  264495 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  264517 */     // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  264517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3),
     /*  264520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  264527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  264532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264539 */     GIR_RootConstrainSelectedInstOperands,
     /*  264540 */     // GIR_Coverage, 12440,
     /*  264540 */     GIR_EraseRootFromParent_Done,
     /*  264541 */   // Label 3875: @264541
     /*  264541 */   GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(264595), // Rule ID 12441 //
     /*  264546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  264549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  264571 */     // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  264571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3),
     /*  264574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  264581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  264586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264593 */     GIR_RootConstrainSelectedInstOperands,
     /*  264594 */     // GIR_Coverage, 12441,
     /*  264594 */     GIR_EraseRootFromParent_Done,
     /*  264595 */   // Label 3876: @264595
     /*  264595 */   GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(264649), // Rule ID 12442 //
     /*  264600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  264603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  264625 */     // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  264625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3),
     /*  264628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  264635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  264640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  264643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264647 */     GIR_RootConstrainSelectedInstOperands,
     /*  264648 */     // GIR_Coverage, 12442,
     /*  264648 */     GIR_EraseRootFromParent_Done,
     /*  264649 */   // Label 3877: @264649
     /*  264649 */   GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(264711), // Rule ID 9651 //
     /*  264654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  264657 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264673 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264680 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3_SADDR),
     /*  264683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264705 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264709 */     GIR_RootConstrainSelectedInstOperands,
     /*  264710 */     // GIR_Coverage, 9651,
     /*  264710 */     GIR_EraseRootFromParent_Done,
     /*  264711 */   // Label 3878: @264711
     /*  264711 */   GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(264773), // Rule ID 9652 //
     /*  264716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  264719 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264731 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264735 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264742 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3_SADDR),
     /*  264745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264771 */     GIR_RootConstrainSelectedInstOperands,
     /*  264772 */     // GIR_Coverage, 9652,
     /*  264772 */     GIR_EraseRootFromParent_Done,
     /*  264773 */   // Label 3879: @264773
     /*  264773 */   GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(264835), // Rule ID 9653 //
     /*  264778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  264781 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264804 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3_SADDR),
     /*  264807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264833 */     GIR_RootConstrainSelectedInstOperands,
     /*  264834 */     // GIR_Coverage, 9653,
     /*  264834 */     GIR_EraseRootFromParent_Done,
     /*  264835 */   // Label 3880: @264835
     /*  264835 */   GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(264897), // Rule ID 9654 //
     /*  264840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  264843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264866 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3_SADDR),
     /*  264869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264895 */     GIR_RootConstrainSelectedInstOperands,
     /*  264896 */     // GIR_Coverage, 9654,
     /*  264896 */     GIR_EraseRootFromParent_Done,
     /*  264897 */   // Label 3881: @264897
     /*  264897 */   GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(264959), // Rule ID 9655 //
     /*  264902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  264905 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  264928 */     // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  264928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3_SADDR),
     /*  264931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  264938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  264943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  264948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  264953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  264957 */     GIR_RootConstrainSelectedInstOperands,
     /*  264958 */     // GIR_Coverage, 9655,
     /*  264958 */     GIR_EraseRootFromParent_Done,
     /*  264959 */   // Label 3882: @264959
     /*  264959 */   GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(265014), // Rule ID 9646 //
     /*  264964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  264967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  264975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  264979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  264983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  264990 */     // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  264990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3),
     /*  264993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  264995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  265000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265012 */     GIR_RootConstrainSelectedInstOperands,
     /*  265013 */     // GIR_Coverage, 9646,
     /*  265013 */     GIR_EraseRootFromParent_Done,
     /*  265014 */   // Label 3883: @265014
     /*  265014 */   GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(265069), // Rule ID 9647 //
     /*  265019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  265022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  265030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  265034 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265038 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  265045 */     // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  265045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3),
     /*  265048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  265050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  265055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265067 */     GIR_RootConstrainSelectedInstOperands,
     /*  265068 */     // GIR_Coverage, 9647,
     /*  265068 */     GIR_EraseRootFromParent_Done,
     /*  265069 */   // Label 3884: @265069
     /*  265069 */   GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(265124), // Rule ID 9648 //
     /*  265074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  265077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  265085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  265089 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265093 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  265100 */     // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  265100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3),
     /*  265103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  265105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  265110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265122 */     GIR_RootConstrainSelectedInstOperands,
     /*  265123 */     // GIR_Coverage, 9648,
     /*  265123 */     GIR_EraseRootFromParent_Done,
     /*  265124 */   // Label 3885: @265124
     /*  265124 */   GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(265179), // Rule ID 9649 //
     /*  265129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  265132 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  265140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  265144 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  265155 */     // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  265155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3),
     /*  265158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  265160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  265165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265177 */     GIR_RootConstrainSelectedInstOperands,
     /*  265178 */     // GIR_Coverage, 9649,
     /*  265178 */     GIR_EraseRootFromParent_Done,
     /*  265179 */   // Label 3886: @265179
     /*  265179 */   GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(265234), // Rule ID 9650 //
     /*  265184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  265187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  265195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  265199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  265210 */     // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  265210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3),
     /*  265213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  265215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  265220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265232 */     GIR_RootConstrainSelectedInstOperands,
     /*  265233 */     // GIR_Coverage, 9650,
     /*  265233 */     GIR_EraseRootFromParent_Done,
     /*  265234 */   // Label 3887: @265234
     /*  265234 */   GIM_Reject,
     /*  265235 */ // Label 3722: @265235
     /*  265235 */ GIM_Reject,
     /*  265236 */ // Label 1133: @265236
     /*  265236 */ GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(277305),
     /*  265241 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  265244 */   GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(265310), // Rule ID 8859 //
     /*  265249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  265252 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265264 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265268 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  265272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  265279 */     // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  265279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  265282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  265294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  265299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  265304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265308 */     GIR_RootConstrainSelectedInstOperands,
     /*  265309 */     // GIR_Coverage, 8859,
     /*  265309 */     GIR_EraseRootFromParent_Done,
     /*  265310 */   // Label 3889: @265310
     /*  265310 */   GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(265376), // Rule ID 8876 //
     /*  265315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  265318 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265326 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265330 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265334 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  265338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  265345 */     // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  265345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  265348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  265360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  265365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  265370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265374 */     GIR_RootConstrainSelectedInstOperands,
     /*  265375 */     // GIR_Coverage, 8876,
     /*  265375 */     GIR_EraseRootFromParent_Done,
     /*  265376 */   // Label 3890: @265376
     /*  265376 */   GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(265438), // Rule ID 8864 //
     /*  265381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  265384 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265396 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  265407 */     // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  265407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  265410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  265422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  265427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  265432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265436 */     GIR_RootConstrainSelectedInstOperands,
     /*  265437 */     // GIR_Coverage, 8864,
     /*  265437 */     GIR_EraseRootFromParent_Done,
     /*  265438 */   // Label 3891: @265438
     /*  265438 */   GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(265500), // Rule ID 8881 //
     /*  265443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  265446 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265458 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  265469 */     // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  265469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  265472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  265484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  265489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  265494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265498 */     GIR_RootConstrainSelectedInstOperands,
     /*  265499 */     // GIR_Coverage, 8881,
     /*  265499 */     GIR_EraseRootFromParent_Done,
     /*  265500 */   // Label 3892: @265500
     /*  265500 */   GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(265562), // Rule ID 8870 //
     /*  265505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  265508 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265520 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  265531 */     // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  265531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  265534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  265546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  265551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  265556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265560 */     GIR_RootConstrainSelectedInstOperands,
     /*  265561 */     // GIR_Coverage, 8870,
     /*  265561 */     GIR_EraseRootFromParent_Done,
     /*  265562 */   // Label 3893: @265562
     /*  265562 */   GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(265624), // Rule ID 8887 //
     /*  265567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  265570 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265582 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  265593 */     // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  265593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  265596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  265608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  265613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  265618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265622 */     GIR_RootConstrainSelectedInstOperands,
     /*  265623 */     // GIR_Coverage, 8887,
     /*  265623 */     GIR_EraseRootFromParent_Done,
     /*  265624 */   // Label 3894: @265624
     /*  265624 */   GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(265683), // Rule ID 8855 //
     /*  265629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  265632 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265640 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265644 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265648 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  265652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  265659 */     // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  265659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  265662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265681 */     GIR_RootConstrainSelectedInstOperands,
     /*  265682 */     // GIR_Coverage, 8855,
     /*  265682 */     GIR_EraseRootFromParent_Done,
     /*  265683 */   // Label 3895: @265683
     /*  265683 */   GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(265742), // Rule ID 8856 //
     /*  265688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  265691 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265703 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265707 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  265711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  265718 */     // (ld:{ *:[v4i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  265718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  265721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265740 */     GIR_RootConstrainSelectedInstOperands,
     /*  265741 */     // GIR_Coverage, 8856,
     /*  265741 */     GIR_EraseRootFromParent_Done,
     /*  265742 */   // Label 3896: @265742
     /*  265742 */   GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(265801), // Rule ID 8872 //
     /*  265747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  265750 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265762 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265766 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  265770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  265777 */     // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  265777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  265780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265799 */     GIR_RootConstrainSelectedInstOperands,
     /*  265800 */     // GIR_Coverage, 8872,
     /*  265800 */     GIR_EraseRootFromParent_Done,
     /*  265801 */   // Label 3897: @265801
     /*  265801 */   GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(265860), // Rule ID 8873 //
     /*  265806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  265809 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265821 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265825 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  265829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  265836 */     // (ld:{ *:[v4f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  265836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  265839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265858 */     GIR_RootConstrainSelectedInstOperands,
     /*  265859 */     // GIR_Coverage, 8873,
     /*  265859 */     GIR_EraseRootFromParent_Done,
     /*  265860 */   // Label 3898: @265860
     /*  265860 */   GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(265915), // Rule ID 8861 //
     /*  265865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  265868 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265880 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  265891 */     // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  265891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  265894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265913 */     GIR_RootConstrainSelectedInstOperands,
     /*  265914 */     // GIR_Coverage, 8861,
     /*  265914 */     GIR_EraseRootFromParent_Done,
     /*  265915 */   // Label 3899: @265915
     /*  265915 */   GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(265970), // Rule ID 8878 //
     /*  265920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  265923 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  265931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  265935 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  265939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  265946 */     // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  265946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  265949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  265951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  265956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  265961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  265964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  265968 */     GIR_RootConstrainSelectedInstOperands,
     /*  265969 */     // GIR_Coverage, 8878,
     /*  265969 */     GIR_EraseRootFromParent_Done,
     /*  265970 */   // Label 3900: @265970
     /*  265970 */   GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(266035), // Rule ID 30023 //
     /*  265975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  265978 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  265982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  265987 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  265992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  265996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266000 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266004 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266011 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266033 */     GIR_RootConstrainSelectedInstOperands,
     /*  266034 */     // GIR_Coverage, 30023,
     /*  266034 */     GIR_EraseRootFromParent_Done,
     /*  266035 */   // Label 3901: @266035
     /*  266035 */   GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(266100), // Rule ID 30024 //
     /*  266040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  266043 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266047 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266065 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266076 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266098 */     GIR_RootConstrainSelectedInstOperands,
     /*  266099 */     // GIR_Coverage, 30024,
     /*  266099 */     GIR_EraseRootFromParent_Done,
     /*  266100 */   // Label 3902: @266100
     /*  266100 */   GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(266165), // Rule ID 30025 //
     /*  266105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  266108 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266117 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266130 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266134 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266141 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266163 */     GIR_RootConstrainSelectedInstOperands,
     /*  266164 */     // GIR_Coverage, 30025,
     /*  266164 */     GIR_EraseRootFromParent_Done,
     /*  266165 */   // Label 3903: @266165
     /*  266165 */   GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(266230), // Rule ID 30026 //
     /*  266170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  266173 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266195 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266206 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266228 */     GIR_RootConstrainSelectedInstOperands,
     /*  266229 */     // GIR_Coverage, 30026,
     /*  266229 */     GIR_EraseRootFromParent_Done,
     /*  266230 */   // Label 3904: @266230
     /*  266230 */   GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(266295), // Rule ID 30027 //
     /*  266235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  266238 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266242 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266247 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266260 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266271 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266293 */     GIR_RootConstrainSelectedInstOperands,
     /*  266294 */     // GIR_Coverage, 30027,
     /*  266294 */     GIR_EraseRootFromParent_Done,
     /*  266295 */   // Label 3905: @266295
     /*  266295 */   GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(266360), // Rule ID 30043 //
     /*  266300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  266303 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266325 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266336 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266358 */     GIR_RootConstrainSelectedInstOperands,
     /*  266359 */     // GIR_Coverage, 30043,
     /*  266359 */     GIR_EraseRootFromParent_Done,
     /*  266360 */   // Label 3906: @266360
     /*  266360 */   GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(266425), // Rule ID 30044 //
     /*  266365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  266368 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266390 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266394 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266401 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266423 */     GIR_RootConstrainSelectedInstOperands,
     /*  266424 */     // GIR_Coverage, 30044,
     /*  266424 */     GIR_EraseRootFromParent_Done,
     /*  266425 */   // Label 3907: @266425
     /*  266425 */   GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(266490), // Rule ID 30045 //
     /*  266430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  266433 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266455 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266466 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266488 */     GIR_RootConstrainSelectedInstOperands,
     /*  266489 */     // GIR_Coverage, 30045,
     /*  266489 */     GIR_EraseRootFromParent_Done,
     /*  266490 */   // Label 3908: @266490
     /*  266490 */   GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(266555), // Rule ID 30046 //
     /*  266495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  266498 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266507 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266520 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266531 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266553 */     GIR_RootConstrainSelectedInstOperands,
     /*  266554 */     // GIR_Coverage, 30046,
     /*  266554 */     GIR_EraseRootFromParent_Done,
     /*  266555 */   // Label 3909: @266555
     /*  266555 */   GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(266620), // Rule ID 30047 //
     /*  266560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  266563 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266567 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266585 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  266589 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266596 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266618 */     GIR_RootConstrainSelectedInstOperands,
     /*  266619 */     // GIR_Coverage, 30047,
     /*  266619 */     GIR_EraseRootFromParent_Done,
     /*  266620 */   // Label 3910: @266620
     /*  266620 */   GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(266680), // Rule ID 29683 //
     /*  266625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  266628 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266632 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266637 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  266641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266656 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266678 */     GIR_RootConstrainSelectedInstOperands,
     /*  266679 */     // GIR_Coverage, 29683,
     /*  266679 */     GIR_EraseRootFromParent_Done,
     /*  266680 */   // Label 3911: @266680
     /*  266680 */   GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(266740), // Rule ID 29684 //
     /*  266685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  266688 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266697 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  266701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266705 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266716 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266738 */     GIR_RootConstrainSelectedInstOperands,
     /*  266739 */     // GIR_Coverage, 29684,
     /*  266739 */     GIR_EraseRootFromParent_Done,
     /*  266740 */   // Label 3912: @266740
     /*  266740 */   GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(266800), // Rule ID 29685 //
     /*  266745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  266748 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266757 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  266761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266776 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266798 */     GIR_RootConstrainSelectedInstOperands,
     /*  266799 */     // GIR_Coverage, 29685,
     /*  266799 */     GIR_EraseRootFromParent_Done,
     /*  266800 */   // Label 3913: @266800
     /*  266800 */   GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(266860), // Rule ID 29686 //
     /*  266805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  266808 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266817 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  266821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266836 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266858 */     GIR_RootConstrainSelectedInstOperands,
     /*  266859 */     // GIR_Coverage, 29686,
     /*  266859 */     GIR_EraseRootFromParent_Done,
     /*  266860 */   // Label 3914: @266860
     /*  266860 */   GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(266920), // Rule ID 29687 //
     /*  266865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  266868 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266877 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  266881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266896 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266918 */     GIR_RootConstrainSelectedInstOperands,
     /*  266919 */     // GIR_Coverage, 29687,
     /*  266919 */     GIR_EraseRootFromParent_Done,
     /*  266920 */   // Label 3915: @266920
     /*  266920 */   GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(266980), // Rule ID 29703 //
     /*  266925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  266928 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266937 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  266941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  266945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  266949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  266956 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  266956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  266959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  266961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  266966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  266971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  266974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  266978 */     GIR_RootConstrainSelectedInstOperands,
     /*  266979 */     // GIR_Coverage, 29703,
     /*  266979 */     GIR_EraseRootFromParent_Done,
     /*  266980 */   // Label 3916: @266980
     /*  266980 */   GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(267040), // Rule ID 29704 //
     /*  266985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  266988 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  266992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  266997 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  267001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267016 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  267019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267038 */     GIR_RootConstrainSelectedInstOperands,
     /*  267039 */     // GIR_Coverage, 29704,
     /*  267039 */     GIR_EraseRootFromParent_Done,
     /*  267040 */   // Label 3917: @267040
     /*  267040 */   GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(267100), // Rule ID 29705 //
     /*  267045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  267048 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267057 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  267061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267076 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  267079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267098 */     GIR_RootConstrainSelectedInstOperands,
     /*  267099 */     // GIR_Coverage, 29705,
     /*  267099 */     GIR_EraseRootFromParent_Done,
     /*  267100 */   // Label 3918: @267100
     /*  267100 */   GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(267160), // Rule ID 29706 //
     /*  267105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  267108 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267117 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  267121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267136 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  267139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267158 */     GIR_RootConstrainSelectedInstOperands,
     /*  267159 */     // GIR_Coverage, 29706,
     /*  267159 */     GIR_EraseRootFromParent_Done,
     /*  267160 */   // Label 3919: @267160
     /*  267160 */   GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(267220), // Rule ID 29707 //
     /*  267165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  267168 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267177 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  267181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267196 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
     /*  267199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267218 */     GIR_RootConstrainSelectedInstOperands,
     /*  267219 */     // GIR_Coverage, 29707,
     /*  267219 */     GIR_EraseRootFromParent_Done,
     /*  267220 */   // Label 3920: @267220
     /*  267220 */   GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(267272), // Rule ID 8866 //
     /*  267225 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  267233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267237 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  267241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  267248 */     // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  267248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  267251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  267253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  267258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267270 */     GIR_RootConstrainSelectedInstOperands,
     /*  267271 */     // GIR_Coverage, 8866,
     /*  267271 */     GIR_EraseRootFromParent_Done,
     /*  267272 */   // Label 3921: @267272
     /*  267272 */   GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(267327), // Rule ID 8867 //
     /*  267277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  267280 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  267288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267292 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  267296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  267303 */     // (ld:{ *:[v4i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  267303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  267306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  267308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  267313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267325 */     GIR_RootConstrainSelectedInstOperands,
     /*  267326 */     // GIR_Coverage, 8867,
     /*  267326 */     GIR_EraseRootFromParent_Done,
     /*  267327 */   // Label 3922: @267327
     /*  267327 */   GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(267379), // Rule ID 8883 //
     /*  267332 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  267340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267344 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  267348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  267355 */     // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  267355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  267358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  267360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  267365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267377 */     GIR_RootConstrainSelectedInstOperands,
     /*  267378 */     // GIR_Coverage, 8883,
     /*  267378 */     GIR_EraseRootFromParent_Done,
     /*  267379 */   // Label 3923: @267379
     /*  267379 */   GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(267434), // Rule ID 8884 //
     /*  267384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  267387 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  267391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  267395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267399 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  267403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  267410 */     // (ld:{ *:[v4f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  267410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
     /*  267413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  267415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  267420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267432 */     GIR_RootConstrainSelectedInstOperands,
     /*  267433 */     // GIR_Coverage, 8884,
     /*  267433 */     GIR_EraseRootFromParent_Done,
     /*  267434 */   // Label 3924: @267434
     /*  267434 */   GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(267495), // Rule ID 30028 //
     /*  267439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  267442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267460 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267471 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267489 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267493 */     GIR_RootConstrainSelectedInstOperands,
     /*  267494 */     // GIR_Coverage, 30028,
     /*  267494 */     GIR_EraseRootFromParent_Done,
     /*  267495 */   // Label 3925: @267495
     /*  267495 */   GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(267556), // Rule ID 30029 //
     /*  267500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  267503 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267521 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267532 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267550 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267554 */     GIR_RootConstrainSelectedInstOperands,
     /*  267555 */     // GIR_Coverage, 30029,
     /*  267555 */     GIR_EraseRootFromParent_Done,
     /*  267556 */   // Label 3926: @267556
     /*  267556 */   GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(267617), // Rule ID 30030 //
     /*  267561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  267564 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267582 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267593 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267615 */     GIR_RootConstrainSelectedInstOperands,
     /*  267616 */     // GIR_Coverage, 30030,
     /*  267616 */     GIR_EraseRootFromParent_Done,
     /*  267617 */   // Label 3927: @267617
     /*  267617 */   GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(267678), // Rule ID 30031 //
     /*  267622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  267625 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267630 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267643 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267654 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267676 */     GIR_RootConstrainSelectedInstOperands,
     /*  267677 */     // GIR_Coverage, 30031,
     /*  267677 */     GIR_EraseRootFromParent_Done,
     /*  267678 */   // Label 3928: @267678
     /*  267678 */   GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(267739), // Rule ID 30032 //
     /*  267683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  267686 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267691 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267704 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267715 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267737 */     GIR_RootConstrainSelectedInstOperands,
     /*  267738 */     // GIR_Coverage, 30032,
     /*  267738 */     GIR_EraseRootFromParent_Done,
     /*  267739 */   // Label 3929: @267739
     /*  267739 */   GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(267800), // Rule ID 30048 //
     /*  267744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  267747 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267765 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267776 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267798 */     GIR_RootConstrainSelectedInstOperands,
     /*  267799 */     // GIR_Coverage, 30048,
     /*  267799 */     GIR_EraseRootFromParent_Done,
     /*  267800 */   // Label 3930: @267800
     /*  267800 */   GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(267861), // Rule ID 30049 //
     /*  267805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  267808 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267826 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267837 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267852 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267859 */     GIR_RootConstrainSelectedInstOperands,
     /*  267860 */     // GIR_Coverage, 30049,
     /*  267860 */     GIR_EraseRootFromParent_Done,
     /*  267861 */   // Label 3931: @267861
     /*  267861 */   GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(267922), // Rule ID 30050 //
     /*  267866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  267869 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267887 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267898 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267920 */     GIR_RootConstrainSelectedInstOperands,
     /*  267921 */     // GIR_Coverage, 30050,
     /*  267921 */     GIR_EraseRootFromParent_Done,
     /*  267922 */   // Label 3932: @267922
     /*  267922 */   GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(267983), // Rule ID 30051 //
     /*  267927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  267930 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  267944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  267948 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  267952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  267959 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  267959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  267962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  267964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  267969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  267974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  267977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  267981 */     GIR_RootConstrainSelectedInstOperands,
     /*  267982 */     // GIR_Coverage, 30051,
     /*  267982 */     GIR_EraseRootFromParent_Done,
     /*  267983 */   // Label 3933: @267983
     /*  267983 */   GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(268044), // Rule ID 30052 //
     /*  267988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  267991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  267996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268009 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  268013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268020 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268042 */     GIR_RootConstrainSelectedInstOperands,
     /*  268043 */     // GIR_Coverage, 30052,
     /*  268043 */     GIR_EraseRootFromParent_Done,
     /*  268044 */   // Label 3934: @268044
     /*  268044 */   GIM_Try, /*On fail goto*//*Label 3935*/ GIMT_Encode4(268100), // Rule ID 29688 //
     /*  268049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  268052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268057 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268076 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268098 */     GIR_RootConstrainSelectedInstOperands,
     /*  268099 */     // GIR_Coverage, 29688,
     /*  268099 */     GIR_EraseRootFromParent_Done,
     /*  268100 */   // Label 3935: @268100
     /*  268100 */   GIM_Try, /*On fail goto*//*Label 3936*/ GIMT_Encode4(268156), // Rule ID 29689 //
     /*  268105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  268108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268113 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268132 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268154 */     GIR_RootConstrainSelectedInstOperands,
     /*  268155 */     // GIR_Coverage, 29689,
     /*  268155 */     GIR_EraseRootFromParent_Done,
     /*  268156 */   // Label 3936: @268156
     /*  268156 */   GIM_Try, /*On fail goto*//*Label 3937*/ GIMT_Encode4(268212), // Rule ID 29690 //
     /*  268161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  268164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268169 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268188 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268210 */     GIR_RootConstrainSelectedInstOperands,
     /*  268211 */     // GIR_Coverage, 29690,
     /*  268211 */     GIR_EraseRootFromParent_Done,
     /*  268212 */   // Label 3937: @268212
     /*  268212 */   GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(268268), // Rule ID 29691 //
     /*  268217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  268220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268225 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268244 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268266 */     GIR_RootConstrainSelectedInstOperands,
     /*  268267 */     // GIR_Coverage, 29691,
     /*  268267 */     GIR_EraseRootFromParent_Done,
     /*  268268 */   // Label 3938: @268268
     /*  268268 */   GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(268324), // Rule ID 29692 //
     /*  268273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  268276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268281 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268300 */     // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268322 */     GIR_RootConstrainSelectedInstOperands,
     /*  268323 */     // GIR_Coverage, 29692,
     /*  268323 */     GIR_EraseRootFromParent_Done,
     /*  268324 */   // Label 3939: @268324
     /*  268324 */   GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(268380), // Rule ID 29708 //
     /*  268329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  268332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268337 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268356 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268378 */     GIR_RootConstrainSelectedInstOperands,
     /*  268379 */     // GIR_Coverage, 29708,
     /*  268379 */     GIR_EraseRootFromParent_Done,
     /*  268380 */   // Label 3940: @268380
     /*  268380 */   GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(268436), // Rule ID 29709 //
     /*  268385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  268388 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268393 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268412 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268434 */     GIR_RootConstrainSelectedInstOperands,
     /*  268435 */     // GIR_Coverage, 29709,
     /*  268435 */     GIR_EraseRootFromParent_Done,
     /*  268436 */   // Label 3941: @268436
     /*  268436 */   GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(268492), // Rule ID 29710 //
     /*  268441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  268444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268449 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268468 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268490 */     GIR_RootConstrainSelectedInstOperands,
     /*  268491 */     // GIR_Coverage, 29710,
     /*  268491 */     GIR_EraseRootFromParent_Done,
     /*  268492 */   // Label 3942: @268492
     /*  268492 */   GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(268548), // Rule ID 29711 //
     /*  268497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  268500 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268505 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268524 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268546 */     GIR_RootConstrainSelectedInstOperands,
     /*  268547 */     // GIR_Coverage, 29711,
     /*  268547 */     GIR_EraseRootFromParent_Done,
     /*  268548 */   // Label 3943: @268548
     /*  268548 */   GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(268604), // Rule ID 29712 //
     /*  268553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  268556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  268561 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  268565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  268569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268573 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  268580 */     // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  268580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
     /*  268583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  268585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  268590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  268595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268602 */     GIR_RootConstrainSelectedInstOperands,
     /*  268603 */     // GIR_Coverage, 29712,
     /*  268603 */     GIR_EraseRootFromParent_Done,
     /*  268604 */   // Label 3944: @268604
     /*  268604 */   GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(268663), // Rule ID 8857 //
     /*  268609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  268612 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268624 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268628 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  268632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  268639 */     // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  268639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  268642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  268649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  268654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268661 */     GIR_RootConstrainSelectedInstOperands,
     /*  268662 */     // GIR_Coverage, 8857,
     /*  268662 */     GIR_EraseRootFromParent_Done,
     /*  268663 */   // Label 3945: @268663
     /*  268663 */   GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(268727), // Rule ID 8858 //
     /*  268668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  268671 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268679 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268683 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268687 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  268691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  268698 */     // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  268698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  268701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  268708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  268713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  268721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268725 */     GIR_RootConstrainSelectedInstOperands,
     /*  268726 */     // GIR_Coverage, 8858,
     /*  268726 */     GIR_EraseRootFromParent_Done,
     /*  268727 */   // Label 3946: @268727
     /*  268727 */   GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(268786), // Rule ID 8874 //
     /*  268732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  268735 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268747 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268751 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  268755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  268762 */     // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  268762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  268765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  268772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  268777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268784 */     GIR_RootConstrainSelectedInstOperands,
     /*  268785 */     // GIR_Coverage, 8874,
     /*  268785 */     GIR_EraseRootFromParent_Done,
     /*  268786 */   // Label 3947: @268786
     /*  268786 */   GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(268850), // Rule ID 8875 //
     /*  268791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  268794 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268806 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268810 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  268814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  268821 */     // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  268821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  268824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  268831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  268836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  268844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268848 */     GIR_RootConstrainSelectedInstOperands,
     /*  268849 */     // GIR_Coverage, 8875,
     /*  268849 */     GIR_EraseRootFromParent_Done,
     /*  268850 */   // Label 3948: @268850
     /*  268850 */   GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(268901), // Rule ID 8860 //
     /*  268855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  268858 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268866 */     // MIs[0] sbase
     /*  268866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  268870 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  268874 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268878 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  268882 */     // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  268882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  268885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268887 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  268889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268899 */     GIR_RootConstrainSelectedInstOperands,
     /*  268900 */     // GIR_Coverage, 8860,
     /*  268900 */     GIR_EraseRootFromParent_Done,
     /*  268901 */   // Label 3949: @268901
     /*  268901 */   GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(268952), // Rule ID 8877 //
     /*  268906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  268909 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268917 */     // MIs[0] sbase
     /*  268917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  268921 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  268925 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268929 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  268933 */     // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  268933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  268936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268938 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  268940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  268946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  268950 */     GIR_RootConstrainSelectedInstOperands,
     /*  268951 */     // GIR_Coverage, 8877,
     /*  268951 */     GIR_EraseRootFromParent_Done,
     /*  268952 */   // Label 3950: @268952
     /*  268952 */   GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(269007), // Rule ID 8862 //
     /*  268957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  268960 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  268964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  268968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  268972 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  268976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  268983 */     // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  268983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  268986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  268988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  268993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  268998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269005 */     GIR_RootConstrainSelectedInstOperands,
     /*  269006 */     // GIR_Coverage, 8862,
     /*  269006 */     GIR_EraseRootFromParent_Done,
     /*  269007 */   // Label 3951: @269007
     /*  269007 */   GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(269067), // Rule ID 8863 //
     /*  269012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  269015 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269027 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269038 */     // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  269038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  269041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  269061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269065 */     GIR_RootConstrainSelectedInstOperands,
     /*  269066 */     // GIR_Coverage, 8863,
     /*  269066 */     GIR_EraseRootFromParent_Done,
     /*  269067 */   // Label 3952: @269067
     /*  269067 */   GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(269122), // Rule ID 8879 //
     /*  269072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  269075 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269087 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269098 */     // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  269098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec),
     /*  269101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269120 */     GIR_RootConstrainSelectedInstOperands,
     /*  269121 */     // GIR_Coverage, 8879,
     /*  269121 */     GIR_EraseRootFromParent_Done,
     /*  269122 */   // Label 3953: @269122
     /*  269122 */   GIM_Try, /*On fail goto*//*Label 3954*/ GIMT_Encode4(269182), // Rule ID 8880 //
     /*  269127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  269130 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269138 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269142 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269153 */     // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  269153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec),
     /*  269156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  269176 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269180 */     GIR_RootConstrainSelectedInstOperands,
     /*  269181 */     // GIR_Coverage, 8880,
     /*  269181 */     GIR_EraseRootFromParent_Done,
     /*  269182 */   // Label 3954: @269182
     /*  269182 */   GIM_Try, /*On fail goto*//*Label 3955*/ GIMT_Encode4(269229), // Rule ID 8865 //
     /*  269187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  269190 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269198 */     // MIs[0] sbase
     /*  269198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  269202 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  269206 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269210 */     // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  269210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  269213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269215 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  269217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269227 */     GIR_RootConstrainSelectedInstOperands,
     /*  269228 */     // GIR_Coverage, 8865,
     /*  269228 */     GIR_EraseRootFromParent_Done,
     /*  269229 */   // Label 3955: @269229
     /*  269229 */   GIM_Try, /*On fail goto*//*Label 3956*/ GIMT_Encode4(269276), // Rule ID 8882 //
     /*  269234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  269237 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269245 */     // MIs[0] sbase
     /*  269245 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  269249 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  269253 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269257 */     // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ec:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  269257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec),
     /*  269260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269262 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  269264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269274 */     GIR_RootConstrainSelectedInstOperands,
     /*  269275 */     // GIR_Coverage, 8882,
     /*  269275 */     GIR_EraseRootFromParent_Done,
     /*  269276 */   // Label 3956: @269276
     /*  269276 */   GIM_Try, /*On fail goto*//*Label 3957*/ GIMT_Encode4(269331), // Rule ID 8868 //
     /*  269281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  269284 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269296 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269307 */     // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  269307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  269310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269329 */     GIR_RootConstrainSelectedInstOperands,
     /*  269330 */     // GIR_Coverage, 8868,
     /*  269330 */     GIR_EraseRootFromParent_Done,
     /*  269331 */   // Label 3957: @269331
     /*  269331 */   GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(269391), // Rule ID 8869 //
     /*  269336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  269339 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269351 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269362 */     // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  269362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  269365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  269385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269389 */     GIR_RootConstrainSelectedInstOperands,
     /*  269390 */     // GIR_Coverage, 8869,
     /*  269390 */     GIR_EraseRootFromParent_Done,
     /*  269391 */   // Label 3958: @269391
     /*  269391 */   GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(269446), // Rule ID 8885 //
     /*  269396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  269399 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269407 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269411 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269422 */     // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  269422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
     /*  269425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269444 */     GIR_RootConstrainSelectedInstOperands,
     /*  269445 */     // GIR_Coverage, 8885,
     /*  269445 */     GIR_EraseRootFromParent_Done,
     /*  269446 */   // Label 3959: @269446
     /*  269446 */   GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(269506), // Rule ID 8886 //
     /*  269451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  269454 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269466 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269470 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  269477 */     // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  269477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
     /*  269480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  269487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  269492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  269500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269504 */     GIR_RootConstrainSelectedInstOperands,
     /*  269505 */     // GIR_Coverage, 8886,
     /*  269505 */     GIR_EraseRootFromParent_Done,
     /*  269506 */   // Label 3960: @269506
     /*  269506 */   GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(269550), // Rule ID 8871 //
     /*  269511 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269519 */     // MIs[0] sbase
     /*  269519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  269523 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  269527 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269531 */     // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  269531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  269534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269536 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  269538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269548 */     GIR_RootConstrainSelectedInstOperands,
     /*  269549 */     // GIR_Coverage, 8871,
     /*  269549 */     GIR_EraseRootFromParent_Done,
     /*  269550 */   // Label 3961: @269550
     /*  269550 */   GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(269594), // Rule ID 8888 //
     /*  269555 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  269559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  269563 */     // MIs[0] sbase
     /*  269563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  269567 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  269571 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  269575 */     // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  269575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
     /*  269578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  269580 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  269582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  269588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269592 */     GIR_RootConstrainSelectedInstOperands,
     /*  269593 */     // GIR_Coverage, 8888,
     /*  269593 */     GIR_EraseRootFromParent_Done,
     /*  269594 */   // Label 3962: @269594
     /*  269594 */   GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(269653), // Rule ID 14422 //
     /*  269599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  269602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269622 */     // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  269647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269651 */     GIR_RootConstrainSelectedInstOperands,
     /*  269652 */     // GIR_Coverage, 14422,
     /*  269652 */     GIR_EraseRootFromParent_Done,
     /*  269653 */   // Label 3963: @269653
     /*  269653 */   GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(269712), // Rule ID 14423 //
     /*  269658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  269661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269674 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269681 */     // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  269706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269710 */     GIR_RootConstrainSelectedInstOperands,
     /*  269711 */     // GIR_Coverage, 14423,
     /*  269711 */     GIR_EraseRootFromParent_Done,
     /*  269712 */   // Label 3964: @269712
     /*  269712 */   GIM_Try, /*On fail goto*//*Label 3965*/ GIMT_Encode4(269771), // Rule ID 14424 //
     /*  269717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  269720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269740 */     // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  269765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269769 */     GIR_RootConstrainSelectedInstOperands,
     /*  269770 */     // GIR_Coverage, 14424,
     /*  269770 */     GIR_EraseRootFromParent_Done,
     /*  269771 */   // Label 3965: @269771
     /*  269771 */   GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(269830), // Rule ID 14425 //
     /*  269776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  269779 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269799 */     // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  269824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269828 */     GIR_RootConstrainSelectedInstOperands,
     /*  269829 */     // GIR_Coverage, 14425,
     /*  269829 */     GIR_EraseRootFromParent_Done,
     /*  269830 */   // Label 3966: @269830
     /*  269830 */   GIM_Try, /*On fail goto*//*Label 3967*/ GIMT_Encode4(269889), // Rule ID 14426 //
     /*  269835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  269838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269858 */     // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  269883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269887 */     GIR_RootConstrainSelectedInstOperands,
     /*  269888 */     // GIR_Coverage, 14426,
     /*  269888 */     GIR_EraseRootFromParent_Done,
     /*  269889 */   // Label 3967: @269889
     /*  269889 */   GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(269948), // Rule ID 14452 //
     /*  269894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  269897 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269906 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269910 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269917 */     // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  269942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  269946 */     GIR_RootConstrainSelectedInstOperands,
     /*  269947 */     // GIR_Coverage, 14452,
     /*  269947 */     GIR_EraseRootFromParent_Done,
     /*  269948 */   // Label 3968: @269948
     /*  269948 */   GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(270007), // Rule ID 14453 //
     /*  269953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  269956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  269961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  269965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  269969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  269976 */     // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  269976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  269979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  269981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  269986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  269991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  269996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  270001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270005 */     GIR_RootConstrainSelectedInstOperands,
     /*  270006 */     // GIR_Coverage, 14453,
     /*  270006 */     GIR_EraseRootFromParent_Done,
     /*  270007 */   // Label 3969: @270007
     /*  270007 */   GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(270066), // Rule ID 14454 //
     /*  270012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  270015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  270035 */     // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  270035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  270038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  270050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  270055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  270060 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270064 */     GIR_RootConstrainSelectedInstOperands,
     /*  270065 */     // GIR_Coverage, 14454,
     /*  270065 */     GIR_EraseRootFromParent_Done,
     /*  270066 */   // Label 3970: @270066
     /*  270066 */   GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(270125), // Rule ID 14455 //
     /*  270071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  270074 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  270094 */     // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  270094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  270097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  270109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  270114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  270119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270123 */     GIR_RootConstrainSelectedInstOperands,
     /*  270124 */     // GIR_Coverage, 14455,
     /*  270124 */     GIR_EraseRootFromParent_Done,
     /*  270125 */   // Label 3971: @270125
     /*  270125 */   GIM_Try, /*On fail goto*//*Label 3972*/ GIMT_Encode4(270184), // Rule ID 14456 //
     /*  270130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  270133 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270142 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  270153 */     // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  270153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
     /*  270156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  270168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  270173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  270178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270182 */     GIR_RootConstrainSelectedInstOperands,
     /*  270183 */     // GIR_Coverage, 14456,
     /*  270183 */     GIR_EraseRootFromParent_Done,
     /*  270184 */   // Label 3972: @270184
     /*  270184 */   GIM_Try, /*On fail goto*//*Label 3973*/ GIMT_Encode4(270236), // Rule ID 14417 //
     /*  270189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  270192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270212 */     // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270234 */     GIR_RootConstrainSelectedInstOperands,
     /*  270235 */     // GIR_Coverage, 14417,
     /*  270235 */     GIR_EraseRootFromParent_Done,
     /*  270236 */   // Label 3973: @270236
     /*  270236 */   GIM_Try, /*On fail goto*//*Label 3974*/ GIMT_Encode4(270288), // Rule ID 14418 //
     /*  270241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  270244 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270264 */     // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270286 */     GIR_RootConstrainSelectedInstOperands,
     /*  270287 */     // GIR_Coverage, 14418,
     /*  270287 */     GIR_EraseRootFromParent_Done,
     /*  270288 */   // Label 3974: @270288
     /*  270288 */   GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(270340), // Rule ID 14419 //
     /*  270293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  270296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270316 */     // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270338 */     GIR_RootConstrainSelectedInstOperands,
     /*  270339 */     // GIR_Coverage, 14419,
     /*  270339 */     GIR_EraseRootFromParent_Done,
     /*  270340 */   // Label 3975: @270340
     /*  270340 */   GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(270392), // Rule ID 14420 //
     /*  270345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  270348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270368 */     // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270390 */     GIR_RootConstrainSelectedInstOperands,
     /*  270391 */     // GIR_Coverage, 14420,
     /*  270391 */     GIR_EraseRootFromParent_Done,
     /*  270392 */   // Label 3976: @270392
     /*  270392 */   GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(270444), // Rule ID 14421 //
     /*  270397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  270400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270409 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270420 */     // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270442 */     GIR_RootConstrainSelectedInstOperands,
     /*  270443 */     // GIR_Coverage, 14421,
     /*  270443 */     GIR_EraseRootFromParent_Done,
     /*  270444 */   // Label 3977: @270444
     /*  270444 */   GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(270496), // Rule ID 14447 //
     /*  270449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  270452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270472 */     // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270494 */     GIR_RootConstrainSelectedInstOperands,
     /*  270495 */     // GIR_Coverage, 14447,
     /*  270495 */     GIR_EraseRootFromParent_Done,
     /*  270496 */   // Label 3978: @270496
     /*  270496 */   GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(270548), // Rule ID 14448 //
     /*  270501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  270504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270524 */     // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270546 */     GIR_RootConstrainSelectedInstOperands,
     /*  270547 */     // GIR_Coverage, 14448,
     /*  270547 */     GIR_EraseRootFromParent_Done,
     /*  270548 */   // Label 3979: @270548
     /*  270548 */   GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(270600), // Rule ID 14449 //
     /*  270553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  270556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270576 */     // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270598 */     GIR_RootConstrainSelectedInstOperands,
     /*  270599 */     // GIR_Coverage, 14449,
     /*  270599 */     GIR_EraseRootFromParent_Done,
     /*  270600 */   // Label 3980: @270600
     /*  270600 */   GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(270652), // Rule ID 14450 //
     /*  270605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  270608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270628 */     // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270650 */     GIR_RootConstrainSelectedInstOperands,
     /*  270651 */     // GIR_Coverage, 14450,
     /*  270651 */     GIR_EraseRootFromParent_Done,
     /*  270652 */   // Label 3981: @270652
     /*  270652 */   GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(270704), // Rule ID 14451 //
     /*  270657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  270660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270673 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  270680 */     // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  270680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
     /*  270683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  270690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270702 */     GIR_RootConstrainSelectedInstOperands,
     /*  270703 */     // GIR_Coverage, 14451,
     /*  270703 */     GIR_EraseRootFromParent_Done,
     /*  270704 */   // Label 3982: @270704
     /*  270704 */   GIM_Try, /*On fail goto*//*Label 3983*/ GIMT_Encode4(270756), // Rule ID 14412 //
     /*  270709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  270712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  270732 */     // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  270732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  270735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270754 */     GIR_RootConstrainSelectedInstOperands,
     /*  270755 */     // GIR_Coverage, 14412,
     /*  270755 */     GIR_EraseRootFromParent_Done,
     /*  270756 */   // Label 3983: @270756
     /*  270756 */   GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(270808), // Rule ID 14413 //
     /*  270761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  270764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  270784 */     // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  270784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  270787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270806 */     GIR_RootConstrainSelectedInstOperands,
     /*  270807 */     // GIR_Coverage, 14413,
     /*  270807 */     GIR_EraseRootFromParent_Done,
     /*  270808 */   // Label 3984: @270808
     /*  270808 */   GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(270860), // Rule ID 14414 //
     /*  270813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  270816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  270836 */     // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  270836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  270839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270858 */     GIR_RootConstrainSelectedInstOperands,
     /*  270859 */     // GIR_Coverage, 14414,
     /*  270859 */     GIR_EraseRootFromParent_Done,
     /*  270860 */   // Label 3985: @270860
     /*  270860 */   GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(270912), // Rule ID 14415 //
     /*  270865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  270868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  270888 */     // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  270888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  270891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270910 */     GIR_RootConstrainSelectedInstOperands,
     /*  270911 */     // GIR_Coverage, 14415,
     /*  270911 */     GIR_EraseRootFromParent_Done,
     /*  270912 */   // Label 3986: @270912
     /*  270912 */   GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(270964), // Rule ID 14416 //
     /*  270917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  270920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  270940 */     // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  270940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  270943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  270950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  270955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  270958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  270962 */     GIR_RootConstrainSelectedInstOperands,
     /*  270963 */     // GIR_Coverage, 14416,
     /*  270963 */     GIR_EraseRootFromParent_Done,
     /*  270964 */   // Label 3987: @270964
     /*  270964 */   GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(271016), // Rule ID 14442 //
     /*  270969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  270972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  270977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  270981 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  270985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  270992 */     // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  270992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  270995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  270997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  271002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  271007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271014 */     GIR_RootConstrainSelectedInstOperands,
     /*  271015 */     // GIR_Coverage, 14442,
     /*  271015 */     GIR_EraseRootFromParent_Done,
     /*  271016 */   // Label 3988: @271016
     /*  271016 */   GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(271068), // Rule ID 14443 //
     /*  271021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  271024 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  271029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  271044 */     // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  271044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  271047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  271049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  271054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  271059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271066 */     GIR_RootConstrainSelectedInstOperands,
     /*  271067 */     // GIR_Coverage, 14443,
     /*  271067 */     GIR_EraseRootFromParent_Done,
     /*  271068 */   // Label 3989: @271068
     /*  271068 */   GIM_Try, /*On fail goto*//*Label 3990*/ GIMT_Encode4(271120), // Rule ID 14444 //
     /*  271073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  271076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  271081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271085 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  271096 */     // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  271096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  271099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  271101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  271106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  271111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271118 */     GIR_RootConstrainSelectedInstOperands,
     /*  271119 */     // GIR_Coverage, 14444,
     /*  271119 */     GIR_EraseRootFromParent_Done,
     /*  271120 */   // Label 3990: @271120
     /*  271120 */   GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(271172), // Rule ID 14445 //
     /*  271125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  271128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  271133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  271148 */     // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  271148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  271151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  271153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  271158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  271163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271170 */     GIR_RootConstrainSelectedInstOperands,
     /*  271171 */     // GIR_Coverage, 14445,
     /*  271171 */     GIR_EraseRootFromParent_Done,
     /*  271172 */   // Label 3991: @271172
     /*  271172 */   GIM_Try, /*On fail goto*//*Label 3992*/ GIMT_Encode4(271224), // Rule ID 14446 //
     /*  271177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  271180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  271185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271189 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  271200 */     // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  271200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
     /*  271203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  271205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  271210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  271215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271222 */     GIR_RootConstrainSelectedInstOperands,
     /*  271223 */     // GIR_Coverage, 14446,
     /*  271223 */     GIR_EraseRootFromParent_Done,
     /*  271224 */   // Label 3992: @271224
     /*  271224 */   GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(271291), // Rule ID 15608 //
     /*  271229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  271232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271254 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271282 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271285 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271289 */     GIR_RootConstrainSelectedInstOperands,
     /*  271290 */     // GIR_Coverage, 15608,
     /*  271290 */     GIR_EraseRootFromParent_Done,
     /*  271291 */   // Label 3993: @271291
     /*  271291 */   GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(271358), // Rule ID 15609 //
     /*  271296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  271299 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271321 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271356 */     GIR_RootConstrainSelectedInstOperands,
     /*  271357 */     // GIR_Coverage, 15609,
     /*  271357 */     GIR_EraseRootFromParent_Done,
     /*  271358 */   // Label 3994: @271358
     /*  271358 */   GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(271425), // Rule ID 15610 //
     /*  271363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  271366 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271388 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271423 */     GIR_RootConstrainSelectedInstOperands,
     /*  271424 */     // GIR_Coverage, 15610,
     /*  271424 */     GIR_EraseRootFromParent_Done,
     /*  271425 */   // Label 3995: @271425
     /*  271425 */   GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(271492), // Rule ID 15611 //
     /*  271430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  271433 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271444 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271455 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271490 */     GIR_RootConstrainSelectedInstOperands,
     /*  271491 */     // GIR_Coverage, 15611,
     /*  271491 */     GIR_EraseRootFromParent_Done,
     /*  271492 */   // Label 3996: @271492
     /*  271492 */   GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(271559), // Rule ID 15612 //
     /*  271497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  271500 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271522 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271553 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271557 */     GIR_RootConstrainSelectedInstOperands,
     /*  271558 */     // GIR_Coverage, 15612,
     /*  271558 */     GIR_EraseRootFromParent_Done,
     /*  271559 */   // Label 3997: @271559
     /*  271559 */   GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(271626), // Rule ID 15618 //
     /*  271564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  271567 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271589 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  271592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271624 */     GIR_RootConstrainSelectedInstOperands,
     /*  271625 */     // GIR_Coverage, 15618,
     /*  271625 */     GIR_EraseRootFromParent_Done,
     /*  271626 */   // Label 3998: @271626
     /*  271626 */   GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(271693), // Rule ID 15619 //
     /*  271631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  271634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271656 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  271659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271691 */     GIR_RootConstrainSelectedInstOperands,
     /*  271692 */     // GIR_Coverage, 15619,
     /*  271692 */     GIR_EraseRootFromParent_Done,
     /*  271693 */   // Label 3999: @271693
     /*  271693 */   GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(271760), // Rule ID 15620 //
     /*  271698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  271701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271723 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  271726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271758 */     GIR_RootConstrainSelectedInstOperands,
     /*  271759 */     // GIR_Coverage, 15620,
     /*  271759 */     GIR_EraseRootFromParent_Done,
     /*  271760 */   // Label 4000: @271760
     /*  271760 */   GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(271827), // Rule ID 15621 //
     /*  271765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  271768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271783 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271790 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  271793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271825 */     GIR_RootConstrainSelectedInstOperands,
     /*  271826 */     // GIR_Coverage, 15621,
     /*  271826 */     GIR_EraseRootFromParent_Done,
     /*  271827 */   // Label 4001: @271827
     /*  271827 */   GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(271894), // Rule ID 15622 //
     /*  271832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  271835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271857 */     // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  271860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271892 */     GIR_RootConstrainSelectedInstOperands,
     /*  271893 */     // GIR_Coverage, 15622,
     /*  271893 */     GIR_EraseRootFromParent_Done,
     /*  271894 */   // Label 4002: @271894
     /*  271894 */   GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(271961), // Rule ID 15628 //
     /*  271899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  271902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271924 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  271934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  271939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  271944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  271949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  271955 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  271959 */     GIR_RootConstrainSelectedInstOperands,
     /*  271960 */     // GIR_Coverage, 15628,
     /*  271960 */     GIR_EraseRootFromParent_Done,
     /*  271961 */   // Label 4003: @271961
     /*  271961 */   GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(272028), // Rule ID 15629 //
     /*  271966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  271969 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  271976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  271980 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  271984 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  271991 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  271991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  271994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  271996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272026 */     GIR_RootConstrainSelectedInstOperands,
     /*  272027 */     // GIR_Coverage, 15629,
     /*  272027 */     GIR_EraseRootFromParent_Done,
     /*  272028 */   // Label 4004: @272028
     /*  272028 */   GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(272095), // Rule ID 15630 //
     /*  272033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  272036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272058 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  272061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272083 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272086 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272089 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272093 */     GIR_RootConstrainSelectedInstOperands,
     /*  272094 */     // GIR_Coverage, 15630,
     /*  272094 */     GIR_EraseRootFromParent_Done,
     /*  272095 */   // Label 4005: @272095
     /*  272095 */   GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(272162), // Rule ID 15631 //
     /*  272100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  272103 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272125 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  272128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272150 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272160 */     GIR_RootConstrainSelectedInstOperands,
     /*  272161 */     // GIR_Coverage, 15631,
     /*  272161 */     GIR_EraseRootFromParent_Done,
     /*  272162 */   // Label 4006: @272162
     /*  272162 */   GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(272229), // Rule ID 15632 //
     /*  272167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  272170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272181 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272185 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272192 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
     /*  272195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272227 */     GIR_RootConstrainSelectedInstOperands,
     /*  272228 */     // GIR_Coverage, 15632,
     /*  272228 */     GIR_EraseRootFromParent_Done,
     /*  272229 */   // Label 4007: @272229
     /*  272229 */   GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(272296), // Rule ID 15638 //
     /*  272234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  272237 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272259 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  272262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272294 */     GIR_RootConstrainSelectedInstOperands,
     /*  272295 */     // GIR_Coverage, 15638,
     /*  272295 */     GIR_EraseRootFromParent_Done,
     /*  272296 */   // Label 4008: @272296
     /*  272296 */   GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(272363), // Rule ID 15639 //
     /*  272301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  272304 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272326 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  272329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272361 */     GIR_RootConstrainSelectedInstOperands,
     /*  272362 */     // GIR_Coverage, 15639,
     /*  272362 */     GIR_EraseRootFromParent_Done,
     /*  272363 */   // Label 4009: @272363
     /*  272363 */   GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(272430), // Rule ID 15640 //
     /*  272368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  272371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272382 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272393 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  272396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272424 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272428 */     GIR_RootConstrainSelectedInstOperands,
     /*  272429 */     // GIR_Coverage, 15640,
     /*  272429 */     GIR_EraseRootFromParent_Done,
     /*  272430 */   // Label 4010: @272430
     /*  272430 */   GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(272497), // Rule ID 15641 //
     /*  272435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  272438 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272460 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  272463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272495 */     GIR_RootConstrainSelectedInstOperands,
     /*  272496 */     // GIR_Coverage, 15641,
     /*  272496 */     GIR_EraseRootFromParent_Done,
     /*  272497 */   // Label 4011: @272497
     /*  272497 */   GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(272564), // Rule ID 15642 //
     /*  272502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  272505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  272512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  272527 */     // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  272527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
     /*  272530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  272532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  272537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  272542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  272547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  272552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272562 */     GIR_RootConstrainSelectedInstOperands,
     /*  272563 */     // GIR_Coverage, 15642,
     /*  272563 */     GIR_EraseRootFromParent_Done,
     /*  272564 */   // Label 4012: @272564
     /*  272564 */   GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(272625), // Rule ID 29443 //
     /*  272569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  272572 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272576 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272589 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272596 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272619 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272623 */     GIR_RootConstrainSelectedInstOperands,
     /*  272624 */     // GIR_Coverage, 29443,
     /*  272624 */     GIR_EraseRootFromParent_Done,
     /*  272625 */   // Label 4013: @272625
     /*  272625 */   GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(272686), // Rule ID 29444 //
     /*  272630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  272633 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272637 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272657 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272677 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272680 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272684 */     GIR_RootConstrainSelectedInstOperands,
     /*  272685 */     // GIR_Coverage, 29444,
     /*  272685 */     GIR_EraseRootFromParent_Done,
     /*  272686 */   // Label 4014: @272686
     /*  272686 */   GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(272747), // Rule ID 29445 //
     /*  272691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  272694 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272698 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272718 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272745 */     GIR_RootConstrainSelectedInstOperands,
     /*  272746 */     // GIR_Coverage, 29445,
     /*  272746 */     GIR_EraseRootFromParent_Done,
     /*  272747 */   // Label 4015: @272747
     /*  272747 */   GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(272808), // Rule ID 29446 //
     /*  272752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  272755 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272768 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272779 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272806 */     GIR_RootConstrainSelectedInstOperands,
     /*  272807 */     // GIR_Coverage, 29446,
     /*  272807 */     GIR_EraseRootFromParent_Done,
     /*  272808 */   // Label 4016: @272808
     /*  272808 */   GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(272869), // Rule ID 29447 //
     /*  272813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  272816 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272840 */     // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272867 */     GIR_RootConstrainSelectedInstOperands,
     /*  272868 */     // GIR_Coverage, 29447,
     /*  272868 */     GIR_EraseRootFromParent_Done,
     /*  272869 */   // Label 4017: @272869
     /*  272869 */   GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(272930), // Rule ID 29455 //
     /*  272874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  272877 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272881 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272890 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272901 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272924 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272928 */     GIR_RootConstrainSelectedInstOperands,
     /*  272929 */     // GIR_Coverage, 29455,
     /*  272929 */     GIR_EraseRootFromParent_Done,
     /*  272930 */   // Label 4018: @272930
     /*  272930 */   GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(272991), // Rule ID 29456 //
     /*  272935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  272938 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  272942 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  272947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  272951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  272955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  272962 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  272962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  272965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  272967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  272972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  272977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  272982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  272985 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  272989 */     GIR_RootConstrainSelectedInstOperands,
     /*  272990 */     // GIR_Coverage, 29456,
     /*  272990 */     GIR_EraseRootFromParent_Done,
     /*  272991 */   // Label 4019: @272991
     /*  272991 */   GIM_Try, /*On fail goto*//*Label 4020*/ GIMT_Encode4(273052), // Rule ID 29457 //
     /*  272996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  272999 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  273003 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  273008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273012 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273016 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  273023 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  273023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  273026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  273028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  273033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  273038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  273043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273050 */     GIR_RootConstrainSelectedInstOperands,
     /*  273051 */     // GIR_Coverage, 29457,
     /*  273051 */     GIR_EraseRootFromParent_Done,
     /*  273052 */   // Label 4020: @273052
     /*  273052 */   GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(273113), // Rule ID 29458 //
     /*  273057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  273060 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  273064 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  273069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  273084 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  273084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  273087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  273089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  273094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  273099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  273104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273111 */     GIR_RootConstrainSelectedInstOperands,
     /*  273112 */     // GIR_Coverage, 29458,
     /*  273112 */     GIR_EraseRootFromParent_Done,
     /*  273113 */   // Label 4021: @273113
     /*  273113 */   GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(273174), // Rule ID 29459 //
     /*  273118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  273121 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  273125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  273130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  273145 */     // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  273145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
     /*  273148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  273150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  273155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  273160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  273165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273172 */     GIR_RootConstrainSelectedInstOperands,
     /*  273173 */     // GIR_Coverage, 29459,
     /*  273173 */     GIR_EraseRootFromParent_Done,
     /*  273174 */   // Label 4022: @273174
     /*  273174 */   GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(273236), // Rule ID 15603 //
     /*  273179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  273182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273204 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273234 */     GIR_RootConstrainSelectedInstOperands,
     /*  273235 */     // GIR_Coverage, 15603,
     /*  273235 */     GIR_EraseRootFromParent_Done,
     /*  273236 */   // Label 4023: @273236
     /*  273236 */   GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(273298), // Rule ID 15604 //
     /*  273241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  273244 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273255 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273259 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273266 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273289 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273292 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273296 */     GIR_RootConstrainSelectedInstOperands,
     /*  273297 */     // GIR_Coverage, 15604,
     /*  273297 */     GIR_EraseRootFromParent_Done,
     /*  273298 */   // Label 4024: @273298
     /*  273298 */   GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(273360), // Rule ID 15605 //
     /*  273303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  273306 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273328 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273358 */     GIR_RootConstrainSelectedInstOperands,
     /*  273359 */     // GIR_Coverage, 15605,
     /*  273359 */     GIR_EraseRootFromParent_Done,
     /*  273360 */   // Label 4025: @273360
     /*  273360 */   GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(273422), // Rule ID 15606 //
     /*  273365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  273368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273390 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273416 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273420 */     GIR_RootConstrainSelectedInstOperands,
     /*  273421 */     // GIR_Coverage, 15606,
     /*  273421 */     GIR_EraseRootFromParent_Done,
     /*  273422 */   // Label 4026: @273422
     /*  273422 */   GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(273484), // Rule ID 15607 //
     /*  273427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  273430 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273452 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273482 */     GIR_RootConstrainSelectedInstOperands,
     /*  273483 */     // GIR_Coverage, 15607,
     /*  273483 */     GIR_EraseRootFromParent_Done,
     /*  273484 */   // Label 4027: @273484
     /*  273484 */   GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(273546), // Rule ID 15613 //
     /*  273489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  273492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273514 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  273517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273544 */     GIR_RootConstrainSelectedInstOperands,
     /*  273545 */     // GIR_Coverage, 15613,
     /*  273545 */     GIR_EraseRootFromParent_Done,
     /*  273546 */   // Label 4028: @273546
     /*  273546 */   GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(273608), // Rule ID 15614 //
     /*  273551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  273554 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273576 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  273579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273606 */     GIR_RootConstrainSelectedInstOperands,
     /*  273607 */     // GIR_Coverage, 15614,
     /*  273607 */     GIR_EraseRootFromParent_Done,
     /*  273608 */   // Label 4029: @273608
     /*  273608 */   GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(273670), // Rule ID 15615 //
     /*  273613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  273616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273638 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  273641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273664 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273668 */     GIR_RootConstrainSelectedInstOperands,
     /*  273669 */     // GIR_Coverage, 15615,
     /*  273669 */     GIR_EraseRootFromParent_Done,
     /*  273670 */   // Label 4030: @273670
     /*  273670 */   GIM_Try, /*On fail goto*//*Label 4031*/ GIMT_Encode4(273732), // Rule ID 15616 //
     /*  273675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  273678 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273700 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  273703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273730 */     GIR_RootConstrainSelectedInstOperands,
     /*  273731 */     // GIR_Coverage, 15616,
     /*  273731 */     GIR_EraseRootFromParent_Done,
     /*  273732 */   // Label 4031: @273732
     /*  273732 */   GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(273794), // Rule ID 15617 //
     /*  273737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  273740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273762 */     // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  273765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273792 */     GIR_RootConstrainSelectedInstOperands,
     /*  273793 */     // GIR_Coverage, 15617,
     /*  273793 */     GIR_EraseRootFromParent_Done,
     /*  273794 */   // Label 4032: @273794
     /*  273794 */   GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(273856), // Rule ID 15623 //
     /*  273799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  273802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273817 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273824 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273854 */     GIR_RootConstrainSelectedInstOperands,
     /*  273855 */     // GIR_Coverage, 15623,
     /*  273855 */     GIR_EraseRootFromParent_Done,
     /*  273856 */   // Label 4033: @273856
     /*  273856 */   GIM_Try, /*On fail goto*//*Label 4034*/ GIMT_Encode4(273918), // Rule ID 15624 //
     /*  273861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  273864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273886 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273912 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273916 */     GIR_RootConstrainSelectedInstOperands,
     /*  273917 */     // GIR_Coverage, 15624,
     /*  273917 */     GIR_EraseRootFromParent_Done,
     /*  273918 */   // Label 4034: @273918
     /*  273918 */   GIM_Try, /*On fail goto*//*Label 4035*/ GIMT_Encode4(273980), // Rule ID 15625 //
     /*  273923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  273926 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  273941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  273948 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  273948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  273951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  273953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  273958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  273963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  273968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  273974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  273978 */     GIR_RootConstrainSelectedInstOperands,
     /*  273979 */     // GIR_Coverage, 15625,
     /*  273979 */     GIR_EraseRootFromParent_Done,
     /*  273980 */   // Label 4035: @273980
     /*  273980 */   GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(274042), // Rule ID 15626 //
     /*  273985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  273988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  273995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  273999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274010 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  274013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274040 */     GIR_RootConstrainSelectedInstOperands,
     /*  274041 */     // GIR_Coverage, 15626,
     /*  274041 */     GIR_EraseRootFromParent_Done,
     /*  274042 */   // Label 4036: @274042
     /*  274042 */   GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(274104), // Rule ID 15627 //
     /*  274047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  274050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274072 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
     /*  274075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274102 */     GIR_RootConstrainSelectedInstOperands,
     /*  274103 */     // GIR_Coverage, 15627,
     /*  274103 */     GIR_EraseRootFromParent_Done,
     /*  274104 */   // Label 4037: @274104
     /*  274104 */   GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(274166), // Rule ID 15633 //
     /*  274109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  274112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274127 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274134 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  274137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274164 */     GIR_RootConstrainSelectedInstOperands,
     /*  274165 */     // GIR_Coverage, 15633,
     /*  274165 */     GIR_EraseRootFromParent_Done,
     /*  274166 */   // Label 4038: @274166
     /*  274166 */   GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(274228), // Rule ID 15634 //
     /*  274171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  274174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274196 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  274199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274216 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274226 */     GIR_RootConstrainSelectedInstOperands,
     /*  274227 */     // GIR_Coverage, 15634,
     /*  274227 */     GIR_EraseRootFromParent_Done,
     /*  274228 */   // Label 4039: @274228
     /*  274228 */   GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(274290), // Rule ID 15635 //
     /*  274233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  274236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274258 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  274261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274281 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274288 */     GIR_RootConstrainSelectedInstOperands,
     /*  274289 */     // GIR_Coverage, 15635,
     /*  274289 */     GIR_EraseRootFromParent_Done,
     /*  274290 */   // Label 4040: @274290
     /*  274290 */   GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(274352), // Rule ID 15636 //
     /*  274295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  274298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274309 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274320 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  274323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274340 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274350 */     GIR_RootConstrainSelectedInstOperands,
     /*  274351 */     // GIR_Coverage, 15636,
     /*  274351 */     GIR_EraseRootFromParent_Done,
     /*  274352 */   // Label 4041: @274352
     /*  274352 */   GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(274414), // Rule ID 15637 //
     /*  274357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  274360 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  274382 */     // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  274382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
     /*  274385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  274387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  274392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  274397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  274402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274412 */     GIR_RootConstrainSelectedInstOperands,
     /*  274413 */     // GIR_Coverage, 15637,
     /*  274413 */     GIR_EraseRootFromParent_Done,
     /*  274414 */   // Label 4042: @274414
     /*  274414 */   GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(274471), // Rule ID 29449 //
     /*  274419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  274422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274442 */     // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274469 */     GIR_RootConstrainSelectedInstOperands,
     /*  274470 */     // GIR_Coverage, 29449,
     /*  274470 */     GIR_EraseRootFromParent_Done,
     /*  274471 */   // Label 4043: @274471
     /*  274471 */   GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(274528), // Rule ID 29450 //
     /*  274476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  274479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274499 */     // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274526 */     GIR_RootConstrainSelectedInstOperands,
     /*  274527 */     // GIR_Coverage, 29450,
     /*  274527 */     GIR_EraseRootFromParent_Done,
     /*  274528 */   // Label 4044: @274528
     /*  274528 */   GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(274585), // Rule ID 29451 //
     /*  274533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  274536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274556 */     // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274583 */     GIR_RootConstrainSelectedInstOperands,
     /*  274584 */     // GIR_Coverage, 29451,
     /*  274584 */     GIR_EraseRootFromParent_Done,
     /*  274585 */   // Label 4045: @274585
     /*  274585 */   GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(274642), // Rule ID 29452 //
     /*  274590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  274593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274613 */     // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274640 */     GIR_RootConstrainSelectedInstOperands,
     /*  274641 */     // GIR_Coverage, 29452,
     /*  274641 */     GIR_EraseRootFromParent_Done,
     /*  274642 */   // Label 4046: @274642
     /*  274642 */   GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(274699), // Rule ID 29453 //
     /*  274647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  274650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274670 */     // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274697 */     GIR_RootConstrainSelectedInstOperands,
     /*  274698 */     // GIR_Coverage, 29453,
     /*  274698 */     GIR_EraseRootFromParent_Done,
     /*  274699 */   // Label 4047: @274699
     /*  274699 */   GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(274756), // Rule ID 29461 //
     /*  274704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  274707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274727 */     // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274754 */     GIR_RootConstrainSelectedInstOperands,
     /*  274755 */     // GIR_Coverage, 29461,
     /*  274755 */     GIR_EraseRootFromParent_Done,
     /*  274756 */   // Label 4048: @274756
     /*  274756 */   GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(274813), // Rule ID 29462 //
     /*  274761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  274764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274784 */     // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274811 */     GIR_RootConstrainSelectedInstOperands,
     /*  274812 */     // GIR_Coverage, 29462,
     /*  274812 */     GIR_EraseRootFromParent_Done,
     /*  274813 */   // Label 4049: @274813
     /*  274813 */   GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(274870), // Rule ID 29463 //
     /*  274818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  274821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274830 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274841 */     // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274868 */     GIR_RootConstrainSelectedInstOperands,
     /*  274869 */     // GIR_Coverage, 29463,
     /*  274869 */     GIR_EraseRootFromParent_Done,
     /*  274870 */   // Label 4050: @274870
     /*  274870 */   GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(274927), // Rule ID 29464 //
     /*  274875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  274878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274898 */     // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274925 */     GIR_RootConstrainSelectedInstOperands,
     /*  274926 */     // GIR_Coverage, 29464,
     /*  274926 */     GIR_EraseRootFromParent_Done,
     /*  274927 */   // Label 4051: @274927
     /*  274927 */   GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(274984), // Rule ID 29465 //
     /*  274932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  274935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  274940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  274944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  274948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  274955 */     // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  274955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
     /*  274958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  274960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  274965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  274970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  274975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  274978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  274982 */     GIR_RootConstrainSelectedInstOperands,
     /*  274983 */     // GIR_Coverage, 29465,
     /*  274983 */     GIR_EraseRootFromParent_Done,
     /*  274984 */   // Label 4052: @274984
     /*  274984 */   GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(275045), // Rule ID 12343 //
     /*  274989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  274992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  274999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275014 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275043 */     GIR_RootConstrainSelectedInstOperands,
     /*  275044 */     // GIR_Coverage, 12343,
     /*  275044 */     GIR_EraseRootFromParent_Done,
     /*  275045 */   // Label 4053: @275045
     /*  275045 */   GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(275106), // Rule ID 12344 //
     /*  275050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  275053 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275075 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275104 */     GIR_RootConstrainSelectedInstOperands,
     /*  275105 */     // GIR_Coverage, 12344,
     /*  275105 */     GIR_EraseRootFromParent_Done,
     /*  275106 */   // Label 4054: @275106
     /*  275106 */   GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(275167), // Rule ID 12345 //
     /*  275111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  275114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275136 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275165 */     GIR_RootConstrainSelectedInstOperands,
     /*  275166 */     // GIR_Coverage, 12345,
     /*  275166 */     GIR_EraseRootFromParent_Done,
     /*  275167 */   // Label 4055: @275167
     /*  275167 */   GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(275228), // Rule ID 12346 //
     /*  275172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  275175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275186 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275190 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275197 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275226 */     GIR_RootConstrainSelectedInstOperands,
     /*  275227 */     // GIR_Coverage, 12346,
     /*  275227 */     GIR_EraseRootFromParent_Done,
     /*  275228 */   // Label 4056: @275228
     /*  275228 */   GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(275289), // Rule ID 12347 //
     /*  275233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  275236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275258 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275287 */     GIR_RootConstrainSelectedInstOperands,
     /*  275288 */     // GIR_Coverage, 12347,
     /*  275288 */     GIR_EraseRootFromParent_Done,
     /*  275289 */   // Label 4057: @275289
     /*  275289 */   GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(275350), // Rule ID 12363 //
     /*  275294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  275297 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275304 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275308 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275312 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275319 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275348 */     GIR_RootConstrainSelectedInstOperands,
     /*  275349 */     // GIR_Coverage, 12363,
     /*  275349 */     GIR_EraseRootFromParent_Done,
     /*  275350 */   // Label 4058: @275350
     /*  275350 */   GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(275411), // Rule ID 12364 //
     /*  275355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  275358 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275369 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275380 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275409 */     GIR_RootConstrainSelectedInstOperands,
     /*  275410 */     // GIR_Coverage, 12364,
     /*  275410 */     GIR_EraseRootFromParent_Done,
     /*  275411 */   // Label 4059: @275411
     /*  275411 */   GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(275472), // Rule ID 12365 //
     /*  275416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  275419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275434 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275441 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275470 */     GIR_RootConstrainSelectedInstOperands,
     /*  275471 */     // GIR_Coverage, 12365,
     /*  275471 */     GIR_EraseRootFromParent_Done,
     /*  275472 */   // Label 4060: @275472
     /*  275472 */   GIM_Try, /*On fail goto*//*Label 4061*/ GIMT_Encode4(275533), // Rule ID 12366 //
     /*  275477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  275480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275502 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275531 */     GIR_RootConstrainSelectedInstOperands,
     /*  275532 */     // GIR_Coverage, 12366,
     /*  275532 */     GIR_EraseRootFromParent_Done,
     /*  275533 */   // Label 4061: @275533
     /*  275533 */   GIM_Try, /*On fail goto*//*Label 4062*/ GIMT_Encode4(275594), // Rule ID 12367 //
     /*  275538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  275541 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  275563 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  275563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
     /*  275566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  275573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  275578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  275583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  275588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275592 */     GIR_RootConstrainSelectedInstOperands,
     /*  275593 */     // GIR_Coverage, 12367,
     /*  275593 */     GIR_EraseRootFromParent_Done,
     /*  275594 */   // Label 4062: @275594
     /*  275594 */   GIM_Try, /*On fail goto*//*Label 4063*/ GIMT_Encode4(275648), // Rule ID 12338 //
     /*  275599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  275602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275624 */     // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275646 */     GIR_RootConstrainSelectedInstOperands,
     /*  275647 */     // GIR_Coverage, 12338,
     /*  275647 */     GIR_EraseRootFromParent_Done,
     /*  275648 */   // Label 4063: @275648
     /*  275648 */   GIM_Try, /*On fail goto*//*Label 4064*/ GIMT_Encode4(275702), // Rule ID 12339 //
     /*  275653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  275656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275678 */     // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275700 */     GIR_RootConstrainSelectedInstOperands,
     /*  275701 */     // GIR_Coverage, 12339,
     /*  275701 */     GIR_EraseRootFromParent_Done,
     /*  275702 */   // Label 4064: @275702
     /*  275702 */   GIM_Try, /*On fail goto*//*Label 4065*/ GIMT_Encode4(275756), // Rule ID 12340 //
     /*  275707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  275710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275732 */     // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275754 */     GIR_RootConstrainSelectedInstOperands,
     /*  275755 */     // GIR_Coverage, 12340,
     /*  275755 */     GIR_EraseRootFromParent_Done,
     /*  275756 */   // Label 4065: @275756
     /*  275756 */   GIM_Try, /*On fail goto*//*Label 4066*/ GIMT_Encode4(275810), // Rule ID 12341 //
     /*  275761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  275764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275786 */     // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275808 */     GIR_RootConstrainSelectedInstOperands,
     /*  275809 */     // GIR_Coverage, 12341,
     /*  275809 */     GIR_EraseRootFromParent_Done,
     /*  275810 */   // Label 4066: @275810
     /*  275810 */   GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(275864), // Rule ID 12342 //
     /*  275815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  275818 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275840 */     // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275862 */     GIR_RootConstrainSelectedInstOperands,
     /*  275863 */     // GIR_Coverage, 12342,
     /*  275863 */     GIR_EraseRootFromParent_Done,
     /*  275864 */   // Label 4067: @275864
     /*  275864 */   GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(275918), // Rule ID 12358 //
     /*  275869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  275872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275894 */     // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275912 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275916 */     GIR_RootConstrainSelectedInstOperands,
     /*  275917 */     // GIR_Coverage, 12358,
     /*  275917 */     GIR_EraseRootFromParent_Done,
     /*  275918 */   // Label 4068: @275918
     /*  275918 */   GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(275972), // Rule ID 12359 //
     /*  275923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  275926 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  275948 */     // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  275948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  275951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  275953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  275958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  275963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  275966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  275970 */     GIR_RootConstrainSelectedInstOperands,
     /*  275971 */     // GIR_Coverage, 12359,
     /*  275971 */     GIR_EraseRootFromParent_Done,
     /*  275972 */   // Label 4069: @275972
     /*  275972 */   GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(276026), // Rule ID 12360 //
     /*  275977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  275980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  275987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  275991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  275995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  276002 */     // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  276005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276024 */     GIR_RootConstrainSelectedInstOperands,
     /*  276025 */     // GIR_Coverage, 12360,
     /*  276025 */     GIR_EraseRootFromParent_Done,
     /*  276026 */   // Label 4070: @276026
     /*  276026 */   GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(276080), // Rule ID 12361 //
     /*  276031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  276034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  276056 */     // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  276059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276078 */     GIR_RootConstrainSelectedInstOperands,
     /*  276079 */     // GIR_Coverage, 12361,
     /*  276079 */     GIR_EraseRootFromParent_Done,
     /*  276080 */   // Label 4071: @276080
     /*  276080 */   GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(276134), // Rule ID 12362 //
     /*  276085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  276088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  276110 */     // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
     /*  276113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276128 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276132 */     GIR_RootConstrainSelectedInstOperands,
     /*  276133 */     // GIR_Coverage, 12362,
     /*  276133 */     GIR_EraseRootFromParent_Done,
     /*  276134 */   // Label 4072: @276134
     /*  276134 */   GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(276196), // Rule ID 10211 //
     /*  276139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  276142 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276165 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276194 */     GIR_RootConstrainSelectedInstOperands,
     /*  276195 */     // GIR_Coverage, 10211,
     /*  276195 */     GIR_EraseRootFromParent_Done,
     /*  276196 */   // Label 4073: @276196
     /*  276196 */   GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(276258), // Rule ID 10212 //
     /*  276201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  276204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276227 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276252 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276256 */     GIR_RootConstrainSelectedInstOperands,
     /*  276257 */     // GIR_Coverage, 10212,
     /*  276257 */     GIR_EraseRootFromParent_Done,
     /*  276258 */   // Label 4074: @276258
     /*  276258 */   GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(276320), // Rule ID 10213 //
     /*  276263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  276266 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276289 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276318 */     GIR_RootConstrainSelectedInstOperands,
     /*  276319 */     // GIR_Coverage, 10213,
     /*  276319 */     GIR_EraseRootFromParent_Done,
     /*  276320 */   // Label 4075: @276320
     /*  276320 */   GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(276382), // Rule ID 10214 //
     /*  276325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  276328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276351 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276380 */     GIR_RootConstrainSelectedInstOperands,
     /*  276381 */     // GIR_Coverage, 10214,
     /*  276381 */     GIR_EraseRootFromParent_Done,
     /*  276382 */   // Label 4076: @276382
     /*  276382 */   GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(276444), // Rule ID 10215 //
     /*  276387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  276390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276413 */     // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276442 */     GIR_RootConstrainSelectedInstOperands,
     /*  276443 */     // GIR_Coverage, 10215,
     /*  276443 */     GIR_EraseRootFromParent_Done,
     /*  276444 */   // Label 4077: @276444
     /*  276444 */   GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(276506), // Rule ID 10231 //
     /*  276449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  276452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276475 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276504 */     GIR_RootConstrainSelectedInstOperands,
     /*  276505 */     // GIR_Coverage, 10231,
     /*  276505 */     GIR_EraseRootFromParent_Done,
     /*  276506 */   // Label 4078: @276506
     /*  276506 */   GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(276568), // Rule ID 10232 //
     /*  276511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  276514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276537 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276566 */     GIR_RootConstrainSelectedInstOperands,
     /*  276567 */     // GIR_Coverage, 10232,
     /*  276567 */     GIR_EraseRootFromParent_Done,
     /*  276568 */   // Label 4079: @276568
     /*  276568 */   GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(276630), // Rule ID 10233 //
     /*  276573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  276576 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276599 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276624 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276628 */     GIR_RootConstrainSelectedInstOperands,
     /*  276629 */     // GIR_Coverage, 10233,
     /*  276629 */     GIR_EraseRootFromParent_Done,
     /*  276630 */   // Label 4080: @276630
     /*  276630 */   GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(276692), // Rule ID 10234 //
     /*  276635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  276638 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276661 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276690 */     GIR_RootConstrainSelectedInstOperands,
     /*  276691 */     // GIR_Coverage, 10234,
     /*  276691 */     GIR_EraseRootFromParent_Done,
     /*  276692 */   // Label 4081: @276692
     /*  276692 */   GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(276754), // Rule ID 10235 //
     /*  276697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  276700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  276723 */     // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  276723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2_SADDR),
     /*  276726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  276733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  276738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  276743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  276748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276752 */     GIR_RootConstrainSelectedInstOperands,
     /*  276753 */     // GIR_Coverage, 10235,
     /*  276753 */     GIR_EraseRootFromParent_Done,
     /*  276754 */   // Label 4082: @276754
     /*  276754 */   GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(276809), // Rule ID 10206 //
     /*  276759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  276762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  276785 */     // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  276788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276807 */     GIR_RootConstrainSelectedInstOperands,
     /*  276808 */     // GIR_Coverage, 10206,
     /*  276808 */     GIR_EraseRootFromParent_Done,
     /*  276809 */   // Label 4083: @276809
     /*  276809 */   GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(276864), // Rule ID 10207 //
     /*  276814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  276817 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  276840 */     // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  276843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276862 */     GIR_RootConstrainSelectedInstOperands,
     /*  276863 */     // GIR_Coverage, 10207,
     /*  276863 */     GIR_EraseRootFromParent_Done,
     /*  276864 */   // Label 4084: @276864
     /*  276864 */   GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(276919), // Rule ID 10208 //
     /*  276869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  276872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276884 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  276895 */     // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  276898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276913 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276917 */     GIR_RootConstrainSelectedInstOperands,
     /*  276918 */     // GIR_Coverage, 10208,
     /*  276918 */     GIR_EraseRootFromParent_Done,
     /*  276919 */   // Label 4085: @276919
     /*  276919 */   GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(276974), // Rule ID 10209 //
     /*  276924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  276927 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  276950 */     // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  276950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  276953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  276955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  276960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  276965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  276968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  276972 */     GIR_RootConstrainSelectedInstOperands,
     /*  276973 */     // GIR_Coverage, 10209,
     /*  276973 */     GIR_EraseRootFromParent_Done,
     /*  276974 */   // Label 4086: @276974
     /*  276974 */   GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(277029), // Rule ID 10210 //
     /*  276979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  276982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  276990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  276994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  276998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  277005 */     // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  277005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  277008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  277010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  277015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277027 */     GIR_RootConstrainSelectedInstOperands,
     /*  277028 */     // GIR_Coverage, 10210,
     /*  277028 */     GIR_EraseRootFromParent_Done,
     /*  277029 */   // Label 4087: @277029
     /*  277029 */   GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(277084), // Rule ID 10226 //
     /*  277034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  277037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  277045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  277049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  277060 */     // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  277060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  277063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  277065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  277070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277082 */     GIR_RootConstrainSelectedInstOperands,
     /*  277083 */     // GIR_Coverage, 10226,
     /*  277083 */     GIR_EraseRootFromParent_Done,
     /*  277084 */   // Label 4088: @277084
     /*  277084 */   GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(277139), // Rule ID 10227 //
     /*  277089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  277092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  277100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  277104 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  277115 */     // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  277115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  277118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  277120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  277125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277133 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277137 */     GIR_RootConstrainSelectedInstOperands,
     /*  277138 */     // GIR_Coverage, 10227,
     /*  277138 */     GIR_EraseRootFromParent_Done,
     /*  277139 */   // Label 4089: @277139
     /*  277139 */   GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(277194), // Rule ID 10228 //
     /*  277144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  277147 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  277155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  277159 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277163 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  277170 */     // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  277170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  277173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  277175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  277180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277192 */     GIR_RootConstrainSelectedInstOperands,
     /*  277193 */     // GIR_Coverage, 10228,
     /*  277193 */     GIR_EraseRootFromParent_Done,
     /*  277194 */   // Label 4090: @277194
     /*  277194 */   GIM_Try, /*On fail goto*//*Label 4091*/ GIMT_Encode4(277249), // Rule ID 10229 //
     /*  277199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  277202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  277210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  277214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  277225 */     // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  277225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  277228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  277230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  277235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277247 */     GIR_RootConstrainSelectedInstOperands,
     /*  277248 */     // GIR_Coverage, 10229,
     /*  277248 */     GIR_EraseRootFromParent_Done,
     /*  277249 */   // Label 4091: @277249
     /*  277249 */   GIM_Try, /*On fail goto*//*Label 4092*/ GIMT_Encode4(277304), // Rule ID 10230 //
     /*  277254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  277257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  277265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  277269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  277280 */     // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  277280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
     /*  277283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  277285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  277290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277302 */     GIR_RootConstrainSelectedInstOperands,
     /*  277303 */     // GIR_Coverage, 10230,
     /*  277303 */     GIR_EraseRootFromParent_Done,
     /*  277304 */   // Label 4092: @277304
     /*  277304 */   GIM_Reject,
     /*  277305 */ // Label 3888: @277305
     /*  277305 */ GIM_Reject,
     /*  277306 */ // Label 1134: @277306
     /*  277306 */ GIM_Try, /*On fail goto*//*Label 4093*/ GIMT_Encode4(277375), // Rule ID 8923 //
     /*  277311 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  277314 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277317 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277325 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277329 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277333 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  277337 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  277344 */   // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  277344 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  277347 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  277359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  277364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  277369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277373 */   GIR_RootConstrainSelectedInstOperands,
     /*  277374 */   // GIR_Coverage, 8923,
     /*  277374 */   GIR_EraseRootFromParent_Done,
     /*  277375 */ // Label 4093: @277375
     /*  277375 */ GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(277444), // Rule ID 8940 //
     /*  277380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  277383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277386 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277394 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277398 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277402 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  277406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  277413 */   // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  277413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  277416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  277428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  277433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  277438 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277442 */   GIR_RootConstrainSelectedInstOperands,
     /*  277443 */   // GIR_Coverage, 8940,
     /*  277443 */   GIR_EraseRootFromParent_Done,
     /*  277444 */ // Label 4094: @277444
     /*  277444 */ GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(277509), // Rule ID 8928 //
     /*  277449 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  277452 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277455 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277463 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277467 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277471 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  277478 */   // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  277478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  277481 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  277493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  277498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  277503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277507 */   GIR_RootConstrainSelectedInstOperands,
     /*  277508 */   // GIR_Coverage, 8928,
     /*  277508 */   GIR_EraseRootFromParent_Done,
     /*  277509 */ // Label 4095: @277509
     /*  277509 */ GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(277574), // Rule ID 8945 //
     /*  277514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  277517 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277520 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277532 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  277543 */   // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  277543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  277546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  277558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  277563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  277568 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277572 */   GIR_RootConstrainSelectedInstOperands,
     /*  277573 */   // GIR_Coverage, 8945,
     /*  277573 */   GIR_EraseRootFromParent_Done,
     /*  277574 */ // Label 4096: @277574
     /*  277574 */ GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(277639), // Rule ID 8934 //
     /*  277579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  277582 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277585 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277593 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277597 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277601 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  277608 */   // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  277608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  277611 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  277623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  277628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  277633 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277637 */   GIR_RootConstrainSelectedInstOperands,
     /*  277638 */   // GIR_Coverage, 8934,
     /*  277638 */   GIR_EraseRootFromParent_Done,
     /*  277639 */ // Label 4097: @277639
     /*  277639 */ GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(277704), // Rule ID 8951 //
     /*  277644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  277647 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277650 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277658 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277662 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277666 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  277673 */   // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  277673 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  277676 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  277688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  277693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  277698 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277702 */   GIR_RootConstrainSelectedInstOperands,
     /*  277703 */   // GIR_Coverage, 8951,
     /*  277703 */   GIR_EraseRootFromParent_Done,
     /*  277704 */ // Label 4098: @277704
     /*  277704 */ GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(277766), // Rule ID 8919 //
     /*  277709 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  277712 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277715 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277723 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277727 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277731 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  277735 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  277742 */   // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  277742 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  277745 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277757 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277760 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277764 */   GIR_RootConstrainSelectedInstOperands,
     /*  277765 */   // GIR_Coverage, 8919,
     /*  277765 */   GIR_EraseRootFromParent_Done,
     /*  277766 */ // Label 4099: @277766
     /*  277766 */ GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(277828), // Rule ID 8920 //
     /*  277771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  277774 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277777 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277781 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277789 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277793 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  277797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  277804 */   // (ld:{ *:[v4i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  277804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  277807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277819 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277822 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277826 */   GIR_RootConstrainSelectedInstOperands,
     /*  277827 */   // GIR_Coverage, 8920,
     /*  277827 */   GIR_EraseRootFromParent_Done,
     /*  277828 */ // Label 4100: @277828
     /*  277828 */ GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(277890), // Rule ID 8936 //
     /*  277833 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  277836 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277839 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277847 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277851 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277855 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  277859 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  277866 */   // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  277866 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  277869 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277881 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277884 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277888 */   GIR_RootConstrainSelectedInstOperands,
     /*  277889 */   // GIR_Coverage, 8936,
     /*  277889 */   GIR_EraseRootFromParent_Done,
     /*  277890 */ // Label 4101: @277890
     /*  277890 */ GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(277952), // Rule ID 8937 //
     /*  277895 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  277898 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277901 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277909 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277913 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277917 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  277921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  277928 */   // (ld:{ *:[v4f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  277928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  277931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  277943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  277946 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  277950 */   GIR_RootConstrainSelectedInstOperands,
     /*  277951 */   // GIR_Coverage, 8937,
     /*  277951 */   GIR_EraseRootFromParent_Done,
     /*  277952 */ // Label 4102: @277952
     /*  277952 */ GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(278010), // Rule ID 8925 //
     /*  277957 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  277960 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  277963 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  277967 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  277971 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  277975 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  277979 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  277986 */   // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  277986 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  277989 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  277991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  277996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278004 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278008 */   GIR_RootConstrainSelectedInstOperands,
     /*  278009 */   // GIR_Coverage, 8925,
     /*  278009 */   GIR_EraseRootFromParent_Done,
     /*  278010 */ // Label 4103: @278010
     /*  278010 */ GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(278068), // Rule ID 8942 //
     /*  278015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  278018 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278021 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278025 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  278029 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278033 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  278037 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  278044 */   // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  278044 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  278047 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  278049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  278054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278059 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278062 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278066 */   GIR_RootConstrainSelectedInstOperands,
     /*  278067 */   // GIR_Coverage, 8942,
     /*  278067 */   GIR_EraseRootFromParent_Done,
     /*  278068 */ // Label 4104: @278068
     /*  278068 */ GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(278131), // Rule ID 29823 //
     /*  278073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  278076 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278079 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278083 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278088 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278092 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278096 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278100 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278107 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278110 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278122 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278125 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278129 */   GIR_RootConstrainSelectedInstOperands,
     /*  278130 */   // GIR_Coverage, 29823,
     /*  278130 */   GIR_EraseRootFromParent_Done,
     /*  278131 */ // Label 4105: @278131
     /*  278131 */ GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(278194), // Rule ID 29824 //
     /*  278136 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  278139 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278142 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278146 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278151 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278155 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278170 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278173 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278192 */   GIR_RootConstrainSelectedInstOperands,
     /*  278193 */   // GIR_Coverage, 29824,
     /*  278193 */   GIR_EraseRootFromParent_Done,
     /*  278194 */ // Label 4106: @278194
     /*  278194 */ GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(278257), // Rule ID 29825 //
     /*  278199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  278202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278205 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278209 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278214 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278218 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278222 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278226 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278233 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278236 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278248 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278251 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278255 */   GIR_RootConstrainSelectedInstOperands,
     /*  278256 */   // GIR_Coverage, 29825,
     /*  278256 */   GIR_EraseRootFromParent_Done,
     /*  278257 */ // Label 4107: @278257
     /*  278257 */ GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(278320), // Rule ID 29826 //
     /*  278262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  278265 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278268 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278277 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278296 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278299 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278314 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278318 */   GIR_RootConstrainSelectedInstOperands,
     /*  278319 */   // GIR_Coverage, 29826,
     /*  278319 */   GIR_EraseRootFromParent_Done,
     /*  278320 */ // Label 4108: @278320
     /*  278320 */ GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(278383), // Rule ID 29827 //
     /*  278325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  278328 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278331 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278335 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278340 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278359 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278362 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278374 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278377 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278381 */   GIR_RootConstrainSelectedInstOperands,
     /*  278382 */   // GIR_Coverage, 29827,
     /*  278382 */   GIR_EraseRootFromParent_Done,
     /*  278383 */ // Label 4109: @278383
     /*  278383 */ GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(278446), // Rule ID 29843 //
     /*  278388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  278391 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278394 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278398 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278403 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278422 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278425 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278444 */   GIR_RootConstrainSelectedInstOperands,
     /*  278445 */   // GIR_Coverage, 29843,
     /*  278445 */   GIR_EraseRootFromParent_Done,
     /*  278446 */ // Label 4110: @278446
     /*  278446 */ GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(278509), // Rule ID 29844 //
     /*  278451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  278454 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278457 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278461 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278466 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278470 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278474 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278478 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278485 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278488 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278500 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278507 */   GIR_RootConstrainSelectedInstOperands,
     /*  278508 */   // GIR_Coverage, 29844,
     /*  278508 */   GIR_EraseRootFromParent_Done,
     /*  278509 */ // Label 4111: @278509
     /*  278509 */ GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(278572), // Rule ID 29845 //
     /*  278514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  278517 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278520 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278524 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278529 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278537 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278541 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278548 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278563 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278566 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278570 */   GIR_RootConstrainSelectedInstOperands,
     /*  278571 */   // GIR_Coverage, 29845,
     /*  278571 */   GIR_EraseRootFromParent_Done,
     /*  278572 */ // Label 4112: @278572
     /*  278572 */ GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(278635), // Rule ID 29846 //
     /*  278577 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  278580 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278583 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278587 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278592 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278600 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278604 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278611 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278633 */   GIR_RootConstrainSelectedInstOperands,
     /*  278634 */   // GIR_Coverage, 29846,
     /*  278634 */   GIR_EraseRootFromParent_Done,
     /*  278635 */ // Label 4113: @278635
     /*  278635 */ GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(278698), // Rule ID 29847 //
     /*  278640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  278643 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278646 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278650 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278655 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  278659 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278663 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278667 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278674 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278674 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278677 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278689 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278692 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278696 */   GIR_RootConstrainSelectedInstOperands,
     /*  278697 */   // GIR_Coverage, 29847,
     /*  278697 */   GIR_EraseRootFromParent_Done,
     /*  278698 */ // Label 4114: @278698
     /*  278698 */ GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(278766), // Rule ID 30163 //
     /*  278703 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  278706 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278709 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278727 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278731 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  278735 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278742 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278742 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278745 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278757 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278760 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278764 */   GIR_RootConstrainSelectedInstOperands,
     /*  278765 */   // GIR_Coverage, 30163,
     /*  278765 */   GIR_EraseRootFromParent_Done,
     /*  278766 */ // Label 4115: @278766
     /*  278766 */ GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(278834), // Rule ID 30164 //
     /*  278771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  278774 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278777 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278781 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278786 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278791 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278795 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278799 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  278803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278810 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278813 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278832 */   GIR_RootConstrainSelectedInstOperands,
     /*  278833 */   // GIR_Coverage, 30164,
     /*  278833 */   GIR_EraseRootFromParent_Done,
     /*  278834 */ // Label 4116: @278834
     /*  278834 */ GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(278902), // Rule ID 30165 //
     /*  278839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  278842 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278845 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278849 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278854 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278863 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278867 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  278871 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278878 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278893 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278896 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278900 */   GIR_RootConstrainSelectedInstOperands,
     /*  278901 */   // GIR_Coverage, 30165,
     /*  278901 */   GIR_EraseRootFromParent_Done,
     /*  278902 */ // Label 4117: @278902
     /*  278902 */ GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(278970), // Rule ID 30166 //
     /*  278907 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  278910 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278913 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278917 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278922 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278927 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278931 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  278935 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  278939 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  278946 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  278946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  278949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  278951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  278956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  278961 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  278964 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  278968 */   GIR_RootConstrainSelectedInstOperands,
     /*  278969 */   // GIR_Coverage, 30166,
     /*  278969 */   GIR_EraseRootFromParent_Done,
     /*  278970 */ // Label 4118: @278970
     /*  278970 */ GIM_Try, /*On fail goto*//*Label 4119*/ GIMT_Encode4(279038), // Rule ID 30167 //
     /*  278975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  278978 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  278981 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  278985 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278990 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  278995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  278999 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279003 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  279007 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279014 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279014 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  279017 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279029 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279032 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279036 */   GIR_RootConstrainSelectedInstOperands,
     /*  279037 */   // GIR_Coverage, 30167,
     /*  279037 */   GIR_EraseRootFromParent_Done,
     /*  279038 */ // Label 4119: @279038
     /*  279038 */ GIM_Try, /*On fail goto*//*Label 4120*/ GIMT_Encode4(279106), // Rule ID 30183 //
     /*  279043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  279046 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279049 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279058 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279067 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279071 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  279075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279082 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  279085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279097 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279100 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279104 */   GIR_RootConstrainSelectedInstOperands,
     /*  279105 */   // GIR_Coverage, 30183,
     /*  279105 */   GIR_EraseRootFromParent_Done,
     /*  279106 */ // Label 4120: @279106
     /*  279106 */ GIM_Try, /*On fail goto*//*Label 4121*/ GIMT_Encode4(279174), // Rule ID 30184 //
     /*  279111 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  279114 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279117 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279121 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279126 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279135 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279139 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  279143 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279150 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  279153 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279165 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279168 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279172 */   GIR_RootConstrainSelectedInstOperands,
     /*  279173 */   // GIR_Coverage, 30184,
     /*  279173 */   GIR_EraseRootFromParent_Done,
     /*  279174 */ // Label 4121: @279174
     /*  279174 */ GIM_Try, /*On fail goto*//*Label 4122*/ GIMT_Encode4(279242), // Rule ID 30185 //
     /*  279179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  279182 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279185 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279189 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279199 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279203 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279207 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  279211 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279218 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279218 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  279221 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279236 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279240 */   GIR_RootConstrainSelectedInstOperands,
     /*  279241 */   // GIR_Coverage, 30185,
     /*  279241 */   GIR_EraseRootFromParent_Done,
     /*  279242 */ // Label 4122: @279242
     /*  279242 */ GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(279310), // Rule ID 30186 //
     /*  279247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  279250 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279253 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279257 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279262 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279267 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279271 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279275 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  279279 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279286 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  279289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279301 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279304 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279308 */   GIR_RootConstrainSelectedInstOperands,
     /*  279309 */   // GIR_Coverage, 30186,
     /*  279309 */   GIR_EraseRootFromParent_Done,
     /*  279310 */ // Label 4123: @279310
     /*  279310 */ GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(279378), // Rule ID 30187 //
     /*  279315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  279318 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279321 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279325 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279330 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279339 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279343 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  279347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279354 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  279357 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279376 */   GIR_RootConstrainSelectedInstOperands,
     /*  279377 */   // GIR_Coverage, 30187,
     /*  279377 */   GIR_EraseRootFromParent_Done,
     /*  279378 */ // Label 4124: @279378
     /*  279378 */ GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(279433), // Rule ID 8930 //
     /*  279383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279386 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  279394 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279398 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  279402 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  279409 */   // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  279409 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  279412 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  279414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  279419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279427 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279431 */   GIR_RootConstrainSelectedInstOperands,
     /*  279432 */   // GIR_Coverage, 8930,
     /*  279432 */   GIR_EraseRootFromParent_Done,
     /*  279433 */ // Label 4125: @279433
     /*  279433 */ GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(279491), // Rule ID 8931 //
     /*  279438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  279441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279444 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279448 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  279452 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279456 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  279460 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  279467 */   // (ld:{ *:[v4i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  279467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  279470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  279472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  279477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279482 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279485 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279489 */   GIR_RootConstrainSelectedInstOperands,
     /*  279490 */   // GIR_Coverage, 8931,
     /*  279490 */   GIR_EraseRootFromParent_Done,
     /*  279491 */ // Label 4126: @279491
     /*  279491 */ GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(279546), // Rule ID 8947 //
     /*  279496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279499 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  279507 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279511 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  279515 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  279522 */   // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  279522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  279525 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  279527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  279532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279537 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279540 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279544 */   GIR_RootConstrainSelectedInstOperands,
     /*  279545 */   // GIR_Coverage, 8947,
     /*  279545 */   GIR_EraseRootFromParent_Done,
     /*  279546 */ // Label 4127: @279546
     /*  279546 */ GIM_Try, /*On fail goto*//*Label 4128*/ GIMT_Encode4(279604), // Rule ID 8948 //
     /*  279551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  279554 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279557 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  279561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  279565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279569 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  279573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  279580 */   // (ld:{ *:[v4f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  279580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  279583 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  279585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  279590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279595 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279602 */   GIR_RootConstrainSelectedInstOperands,
     /*  279603 */   // GIR_Coverage, 8948,
     /*  279603 */   GIR_EraseRootFromParent_Done,
     /*  279604 */ // Label 4128: @279604
     /*  279604 */ GIM_Try, /*On fail goto*//*Label 4129*/ GIMT_Encode4(279663), // Rule ID 29828 //
     /*  279609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  279612 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279620 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279632 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279639 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279642 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279654 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279661 */   GIR_RootConstrainSelectedInstOperands,
     /*  279662 */   // GIR_Coverage, 29828,
     /*  279662 */   GIR_EraseRootFromParent_Done,
     /*  279663 */ // Label 4129: @279663
     /*  279663 */ GIM_Try, /*On fail goto*//*Label 4130*/ GIMT_Encode4(279722), // Rule ID 29829 //
     /*  279668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  279671 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279674 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279679 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279687 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279691 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279698 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279701 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279713 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279716 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279720 */   GIR_RootConstrainSelectedInstOperands,
     /*  279721 */   // GIR_Coverage, 29829,
     /*  279721 */   GIR_EraseRootFromParent_Done,
     /*  279722 */ // Label 4130: @279722
     /*  279722 */ GIM_Try, /*On fail goto*//*Label 4131*/ GIMT_Encode4(279781), // Rule ID 29830 //
     /*  279727 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  279730 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279733 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279738 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279746 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279750 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279757 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279757 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279760 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279772 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279775 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279779 */   GIR_RootConstrainSelectedInstOperands,
     /*  279780 */   // GIR_Coverage, 29830,
     /*  279780 */   GIR_EraseRootFromParent_Done,
     /*  279781 */ // Label 4131: @279781
     /*  279781 */ GIM_Try, /*On fail goto*//*Label 4132*/ GIMT_Encode4(279840), // Rule ID 29831 //
     /*  279786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  279789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279792 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279797 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279801 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279805 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279809 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279816 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279819 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279831 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279834 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279838 */   GIR_RootConstrainSelectedInstOperands,
     /*  279839 */   // GIR_Coverage, 29831,
     /*  279839 */   GIR_EraseRootFromParent_Done,
     /*  279840 */ // Label 4132: @279840
     /*  279840 */ GIM_Try, /*On fail goto*//*Label 4133*/ GIMT_Encode4(279899), // Rule ID 29832 //
     /*  279845 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  279848 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279851 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279856 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279860 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279864 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279868 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279875 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279875 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279878 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279890 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279893 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279897 */   GIR_RootConstrainSelectedInstOperands,
     /*  279898 */   // GIR_Coverage, 29832,
     /*  279898 */   GIR_EraseRootFromParent_Done,
     /*  279899 */ // Label 4133: @279899
     /*  279899 */ GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(279958), // Rule ID 29848 //
     /*  279904 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  279907 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279910 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279915 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279919 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279923 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279934 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279937 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  279944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  279949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  279952 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  279956 */   GIR_RootConstrainSelectedInstOperands,
     /*  279957 */   // GIR_Coverage, 29848,
     /*  279957 */   GIR_EraseRootFromParent_Done,
     /*  279958 */ // Label 4134: @279958
     /*  279958 */ GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(280017), // Rule ID 29849 //
     /*  279963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  279966 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  279969 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  279974 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  279978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  279982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  279986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  279993 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  279993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  279996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  279998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280008 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280011 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280015 */   GIR_RootConstrainSelectedInstOperands,
     /*  280016 */   // GIR_Coverage, 29849,
     /*  280016 */   GIR_EraseRootFromParent_Done,
     /*  280017 */ // Label 4135: @280017
     /*  280017 */ GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(280076), // Rule ID 29850 //
     /*  280022 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  280025 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280028 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280033 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  280037 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280041 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280045 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280052 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280052 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280055 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280070 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280074 */   GIR_RootConstrainSelectedInstOperands,
     /*  280075 */   // GIR_Coverage, 29850,
     /*  280075 */   GIR_EraseRootFromParent_Done,
     /*  280076 */ // Label 4136: @280076
     /*  280076 */ GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(280135), // Rule ID 29851 //
     /*  280081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  280084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280092 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  280096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280100 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280104 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280111 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280111 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280114 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280126 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280129 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280133 */   GIR_RootConstrainSelectedInstOperands,
     /*  280134 */   // GIR_Coverage, 29851,
     /*  280134 */   GIR_EraseRootFromParent_Done,
     /*  280135 */ // Label 4137: @280135
     /*  280135 */ GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(280194), // Rule ID 29852 //
     /*  280140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  280143 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280146 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280151 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  280155 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280170 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280173 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280192 */   GIR_RootConstrainSelectedInstOperands,
     /*  280193 */   // GIR_Coverage, 29852,
     /*  280193 */   GIR_EraseRootFromParent_Done,
     /*  280194 */ // Label 4138: @280194
     /*  280194 */ GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(280258), // Rule ID 30168 //
     /*  280199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  280202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280205 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280210 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280223 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280227 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280234 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280252 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280256 */   GIR_RootConstrainSelectedInstOperands,
     /*  280257 */   // GIR_Coverage, 30168,
     /*  280257 */   GIR_EraseRootFromParent_Done,
     /*  280258 */ // Label 4139: @280258
     /*  280258 */ GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(280322), // Rule ID 30169 //
     /*  280263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  280266 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280274 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280279 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280283 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280287 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280298 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280313 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280320 */   GIR_RootConstrainSelectedInstOperands,
     /*  280321 */   // GIR_Coverage, 30169,
     /*  280321 */   GIR_EraseRootFromParent_Done,
     /*  280322 */ // Label 4140: @280322
     /*  280322 */ GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(280386), // Rule ID 30170 //
     /*  280327 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  280330 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280338 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280343 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280347 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280351 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280362 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280365 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280377 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280380 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280384 */   GIR_RootConstrainSelectedInstOperands,
     /*  280385 */   // GIR_Coverage, 30170,
     /*  280385 */   GIR_EraseRootFromParent_Done,
     /*  280386 */ // Label 4141: @280386
     /*  280386 */ GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(280450), // Rule ID 30171 //
     /*  280391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  280394 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280397 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280402 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280415 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280419 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280426 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280429 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280441 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280444 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280448 */   GIR_RootConstrainSelectedInstOperands,
     /*  280449 */   // GIR_Coverage, 30171,
     /*  280449 */   GIR_EraseRootFromParent_Done,
     /*  280450 */ // Label 4142: @280450
     /*  280450 */ GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(280514), // Rule ID 30172 //
     /*  280455 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  280458 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280461 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280466 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280475 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280479 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280483 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280490 */   // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280505 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280508 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280512 */   GIR_RootConstrainSelectedInstOperands,
     /*  280513 */   // GIR_Coverage, 30172,
     /*  280513 */   GIR_EraseRootFromParent_Done,
     /*  280514 */ // Label 4143: @280514
     /*  280514 */ GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(280578), // Rule ID 30188 //
     /*  280519 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  280522 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280525 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280530 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280539 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280543 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280547 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280554 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280554 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280557 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280576 */   GIR_RootConstrainSelectedInstOperands,
     /*  280577 */   // GIR_Coverage, 30188,
     /*  280577 */   GIR_EraseRootFromParent_Done,
     /*  280578 */ // Label 4144: @280578
     /*  280578 */ GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(280642), // Rule ID 30189 //
     /*  280583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  280586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280589 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280594 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280599 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280603 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280607 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280611 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280618 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280621 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280633 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280636 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280640 */   GIR_RootConstrainSelectedInstOperands,
     /*  280641 */   // GIR_Coverage, 30189,
     /*  280641 */   GIR_EraseRootFromParent_Done,
     /*  280642 */ // Label 4145: @280642
     /*  280642 */ GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(280706), // Rule ID 30190 //
     /*  280647 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  280650 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280653 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280658 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280663 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280667 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280671 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280675 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280682 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280685 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280697 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280700 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280704 */   GIR_RootConstrainSelectedInstOperands,
     /*  280705 */   // GIR_Coverage, 30190,
     /*  280705 */   GIR_EraseRootFromParent_Done,
     /*  280706 */ // Label 4146: @280706
     /*  280706 */ GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(280770), // Rule ID 30191 //
     /*  280711 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  280714 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280717 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280722 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280727 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280731 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280735 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280746 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280746 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280749 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280761 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280764 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280768 */   GIR_RootConstrainSelectedInstOperands,
     /*  280769 */   // GIR_Coverage, 30191,
     /*  280769 */   GIR_EraseRootFromParent_Done,
     /*  280770 */ // Label 4147: @280770
     /*  280770 */ GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(280834), // Rule ID 30192 //
     /*  280775 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  280778 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280781 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280786 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  280791 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  280795 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280799 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  280803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  280810 */   // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  280810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  280813 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  280815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  280820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  280825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280832 */   GIR_RootConstrainSelectedInstOperands,
     /*  280833 */   // GIR_Coverage, 30192,
     /*  280833 */   GIR_EraseRootFromParent_Done,
     /*  280834 */ // Label 4148: @280834
     /*  280834 */ GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(280896), // Rule ID 8921 //
     /*  280839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  280842 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280845 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  280849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  280853 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280857 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  280861 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  280865 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  280872 */   // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  280872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  280875 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  280877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  280882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  280887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280890 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280894 */   GIR_RootConstrainSelectedInstOperands,
     /*  280895 */   // GIR_Coverage, 8921,
     /*  280895 */   GIR_EraseRootFromParent_Done,
     /*  280896 */ // Label 4149: @280896
     /*  280896 */ GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(280963), // Rule ID 8922 //
     /*  280901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  280904 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280907 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  280911 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  280915 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280919 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  280923 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  280927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  280934 */   // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  280934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  280937 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  280939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  280944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  280949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  280952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  280957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  280961 */   GIR_RootConstrainSelectedInstOperands,
     /*  280962 */   // GIR_Coverage, 8922,
     /*  280962 */   GIR_EraseRootFromParent_Done,
     /*  280963 */ // Label 4150: @280963
     /*  280963 */ GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(281025), // Rule ID 8938 //
     /*  280968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  280971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  280974 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  280978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  280982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  280986 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  280990 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  280994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281001 */   // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  281001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  281004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281023 */   GIR_RootConstrainSelectedInstOperands,
     /*  281024 */   // GIR_Coverage, 8938,
     /*  281024 */   GIR_EraseRootFromParent_Done,
     /*  281025 */ // Label 4151: @281025
     /*  281025 */ GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(281092), // Rule ID 8939 //
     /*  281030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  281033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281036 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281048 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281052 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  281056 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281063 */   // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  281063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  281066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281078 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  281086 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281090 */   GIR_RootConstrainSelectedInstOperands,
     /*  281091 */   // GIR_Coverage, 8939,
     /*  281091 */   GIR_EraseRootFromParent_Done,
     /*  281092 */ // Label 4152: @281092
     /*  281092 */ GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(281146), // Rule ID 8924 //
     /*  281097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  281100 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281103 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281107 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281111 */   // MIs[0] sbase
     /*  281111 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  281115 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  281119 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281123 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  281127 */   // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  281127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  281130 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281132 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  281134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281140 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281144 */   GIR_RootConstrainSelectedInstOperands,
     /*  281145 */   // GIR_Coverage, 8924,
     /*  281145 */   GIR_EraseRootFromParent_Done,
     /*  281146 */ // Label 4153: @281146
     /*  281146 */ GIM_Try, /*On fail goto*//*Label 4154*/ GIMT_Encode4(281200), // Rule ID 8941 //
     /*  281151 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  281154 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281157 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281165 */   // MIs[0] sbase
     /*  281165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  281169 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  281173 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281177 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  281181 */   // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  281181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  281184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281186 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  281188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281194 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281198 */   GIR_RootConstrainSelectedInstOperands,
     /*  281199 */   // GIR_Coverage, 8941,
     /*  281199 */   GIR_EraseRootFromParent_Done,
     /*  281200 */ // Label 4154: @281200
     /*  281200 */ GIM_Try, /*On fail goto*//*Label 4155*/ GIMT_Encode4(281258), // Rule ID 8926 //
     /*  281205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  281208 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281211 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281223 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281227 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281234 */   // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  281234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec),
     /*  281237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281252 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281256 */   GIR_RootConstrainSelectedInstOperands,
     /*  281257 */   // GIR_Coverage, 8926,
     /*  281257 */   GIR_EraseRootFromParent_Done,
     /*  281258 */ // Label 4155: @281258
     /*  281258 */ GIM_Try, /*On fail goto*//*Label 4156*/ GIMT_Encode4(281321), // Rule ID 8927 //
     /*  281263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  281266 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281269 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281277 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281281 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281292 */   // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  281292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  281295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  281315 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281319 */   GIR_RootConstrainSelectedInstOperands,
     /*  281320 */   // GIR_Coverage, 8927,
     /*  281320 */   GIR_EraseRootFromParent_Done,
     /*  281321 */ // Label 4156: @281321
     /*  281321 */ GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(281379), // Rule ID 8943 //
     /*  281326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  281329 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281332 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281336 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281340 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281344 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281355 */   // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  281355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec),
     /*  281358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281377 */   GIR_RootConstrainSelectedInstOperands,
     /*  281378 */   // GIR_Coverage, 8943,
     /*  281378 */   GIR_EraseRootFromParent_Done,
     /*  281379 */ // Label 4157: @281379
     /*  281379 */ GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(281442), // Rule ID 8944 //
     /*  281384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  281387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281390 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281394 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281398 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281402 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281413 */   // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  281413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  281416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281428 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  281436 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281440 */   GIR_RootConstrainSelectedInstOperands,
     /*  281441 */   // GIR_Coverage, 8944,
     /*  281441 */   GIR_EraseRootFromParent_Done,
     /*  281442 */ // Label 4158: @281442
     /*  281442 */ GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(281492), // Rule ID 8929 //
     /*  281447 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  281450 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281453 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281461 */   // MIs[0] sbase
     /*  281461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  281465 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  281469 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281473 */   // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  281473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  281476 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281478 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  281480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281483 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281486 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281490 */   GIR_RootConstrainSelectedInstOperands,
     /*  281491 */   // GIR_Coverage, 8929,
     /*  281491 */   GIR_EraseRootFromParent_Done,
     /*  281492 */ // Label 4159: @281492
     /*  281492 */ GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(281542), // Rule ID 8946 //
     /*  281497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  281500 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281503 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281511 */   // MIs[0] sbase
     /*  281511 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  281515 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  281519 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281523 */   // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  281523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  281526 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281528 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  281530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281533 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281536 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281540 */   GIR_RootConstrainSelectedInstOperands,
     /*  281541 */   // GIR_Coverage, 8946,
     /*  281541 */   GIR_EraseRootFromParent_Done,
     /*  281542 */ // Label 4160: @281542
     /*  281542 */ GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(281600), // Rule ID 8932 //
     /*  281547 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  281550 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281553 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281565 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281569 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281576 */   // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  281576 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  281579 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281591 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281594 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281598 */   GIR_RootConstrainSelectedInstOperands,
     /*  281599 */   // GIR_Coverage, 8932,
     /*  281599 */   GIR_EraseRootFromParent_Done,
     /*  281600 */ // Label 4161: @281600
     /*  281600 */ GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(281663), // Rule ID 8933 //
     /*  281605 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  281608 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281611 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281615 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281619 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281623 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281634 */   // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  281634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  281637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  281657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281661 */   GIR_RootConstrainSelectedInstOperands,
     /*  281662 */   // GIR_Coverage, 8933,
     /*  281662 */   GIR_EraseRootFromParent_Done,
     /*  281663 */ // Label 4162: @281663
     /*  281663 */ GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(281721), // Rule ID 8949 //
     /*  281668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  281671 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281674 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281682 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281686 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281697 */   // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  281697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  281700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281715 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281719 */   GIR_RootConstrainSelectedInstOperands,
     /*  281720 */   // GIR_Coverage, 8949,
     /*  281720 */   GIR_EraseRootFromParent_Done,
     /*  281721 */ // Label 4163: @281721
     /*  281721 */ GIM_Try, /*On fail goto*//*Label 4164*/ GIMT_Encode4(281784), // Rule ID 8950 //
     /*  281726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  281729 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281732 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281740 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281744 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  281755 */   // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  281755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  281758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  281765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281770 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  281778 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281782 */   GIR_RootConstrainSelectedInstOperands,
     /*  281783 */   // GIR_Coverage, 8950,
     /*  281783 */   GIR_EraseRootFromParent_Done,
     /*  281784 */ // Label 4164: @281784
     /*  281784 */ GIM_Try, /*On fail goto*//*Label 4165*/ GIMT_Encode4(281831), // Rule ID 8935 //
     /*  281789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281792 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281796 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281800 */   // MIs[0] sbase
     /*  281800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  281804 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  281808 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281812 */   // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  281812 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  281815 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281817 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  281819 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281822 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281825 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281829 */   GIR_RootConstrainSelectedInstOperands,
     /*  281830 */   // GIR_Coverage, 8935,
     /*  281830 */   GIR_EraseRootFromParent_Done,
     /*  281831 */ // Label 4165: @281831
     /*  281831 */ GIM_Try, /*On fail goto*//*Label 4166*/ GIMT_Encode4(281878), // Rule ID 8952 //
     /*  281836 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281839 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  281843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  281847 */   // MIs[0] sbase
     /*  281847 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  281851 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  281855 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  281859 */   // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  281859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  281862 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  281864 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  281866 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281869 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281872 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281876 */   GIR_RootConstrainSelectedInstOperands,
     /*  281877 */   // GIR_Coverage, 8952,
     /*  281877 */   GIR_EraseRootFromParent_Done,
     /*  281878 */ // Label 4166: @281878
     /*  281878 */ GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(281941), // Rule ID 25376 //
     /*  281883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  281886 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  281894 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  281898 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281902 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  281909 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  281909 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  281912 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  281914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  281919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  281929 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281935 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  281939 */   GIR_RootConstrainSelectedInstOperands,
     /*  281940 */   // GIR_Coverage, 25376,
     /*  281940 */   GIR_EraseRootFromParent_Done,
     /*  281941 */ // Label 4167: @281941
     /*  281941 */ GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(282004), // Rule ID 25377 //
     /*  281946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  281949 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  281952 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  281957 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  281961 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  281965 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  281972 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  281972 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  281975 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  281977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  281982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  281987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  281992 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  281998 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282002 */   GIR_RootConstrainSelectedInstOperands,
     /*  282003 */   // GIR_Coverage, 25377,
     /*  282003 */   GIR_EraseRootFromParent_Done,
     /*  282004 */ // Label 4168: @282004
     /*  282004 */ GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(282067), // Rule ID 25378 //
     /*  282009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  282012 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282024 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282028 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282035 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282035 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  282038 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282055 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282065 */   GIR_RootConstrainSelectedInstOperands,
     /*  282066 */   // GIR_Coverage, 25378,
     /*  282066 */   GIR_EraseRootFromParent_Done,
     /*  282067 */ // Label 4169: @282067
     /*  282067 */ GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(282130), // Rule ID 25379 //
     /*  282072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  282075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282083 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282087 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282091 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282098 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  282101 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282118 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282121 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282124 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282128 */   GIR_RootConstrainSelectedInstOperands,
     /*  282129 */   // GIR_Coverage, 25379,
     /*  282129 */   GIR_EraseRootFromParent_Done,
     /*  282130 */ // Label 4170: @282130
     /*  282130 */ GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(282193), // Rule ID 25380 //
     /*  282135 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  282138 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282141 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282150 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282154 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282161 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  282164 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282181 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282191 */   GIR_RootConstrainSelectedInstOperands,
     /*  282192 */   // GIR_Coverage, 25380,
     /*  282192 */   GIR_EraseRootFromParent_Done,
     /*  282193 */ // Label 4171: @282193
     /*  282193 */ GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(282256), // Rule ID 25386 //
     /*  282198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  282201 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282204 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282209 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282217 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282224 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  282227 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282247 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282250 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282254 */   GIR_RootConstrainSelectedInstOperands,
     /*  282255 */   // GIR_Coverage, 25386,
     /*  282255 */   GIR_EraseRootFromParent_Done,
     /*  282256 */ // Label 4172: @282256
     /*  282256 */ GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(282319), // Rule ID 25387 //
     /*  282261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  282264 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282267 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282272 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282276 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282280 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282287 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282287 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  282290 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282310 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282313 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282317 */   GIR_RootConstrainSelectedInstOperands,
     /*  282318 */   // GIR_Coverage, 25387,
     /*  282318 */   GIR_EraseRootFromParent_Done,
     /*  282319 */ // Label 4173: @282319
     /*  282319 */ GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(282382), // Rule ID 25388 //
     /*  282324 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  282327 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282330 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282339 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282343 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282350 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  282353 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282373 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282376 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282380 */   GIR_RootConstrainSelectedInstOperands,
     /*  282381 */   // GIR_Coverage, 25388,
     /*  282381 */   GIR_EraseRootFromParent_Done,
     /*  282382 */ // Label 4174: @282382
     /*  282382 */ GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(282445), // Rule ID 25389 //
     /*  282387 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  282390 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282393 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282402 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282413 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  282416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282433 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282436 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282439 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282443 */   GIR_RootConstrainSelectedInstOperands,
     /*  282444 */   // GIR_Coverage, 25389,
     /*  282444 */   GIR_EraseRootFromParent_Done,
     /*  282445 */ // Label 4175: @282445
     /*  282445 */ GIM_Try, /*On fail goto*//*Label 4176*/ GIMT_Encode4(282508), // Rule ID 25390 //
     /*  282450 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  282453 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282456 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  282476 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  282476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  282479 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  282481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  282486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  282491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  282502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282506 */   GIR_RootConstrainSelectedInstOperands,
     /*  282507 */   // GIR_Coverage, 25390,
     /*  282507 */   GIR_EraseRootFromParent_Done,
     /*  282508 */ // Label 4176: @282508
     /*  282508 */ GIM_Try, /*On fail goto*//*Label 4177*/ GIMT_Encode4(282570), // Rule ID 14587 //
     /*  282513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  282516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282532 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282539 */   // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282539 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282542 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282564 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282568 */   GIR_RootConstrainSelectedInstOperands,
     /*  282569 */   // GIR_Coverage, 14587,
     /*  282569 */   GIR_EraseRootFromParent_Done,
     /*  282570 */ // Label 4177: @282570
     /*  282570 */ GIM_Try, /*On fail goto*//*Label 4178*/ GIMT_Encode4(282632), // Rule ID 14588 //
     /*  282575 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  282578 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282581 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282590 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282594 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282601 */   // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282604 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282626 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282630 */   GIR_RootConstrainSelectedInstOperands,
     /*  282631 */   // GIR_Coverage, 14588,
     /*  282631 */   GIR_EraseRootFromParent_Done,
     /*  282632 */ // Label 4178: @282632
     /*  282632 */ GIM_Try, /*On fail goto*//*Label 4179*/ GIMT_Encode4(282694), // Rule ID 14589 //
     /*  282637 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  282640 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282648 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282652 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282656 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282663 */   // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282666 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282688 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282692 */   GIR_RootConstrainSelectedInstOperands,
     /*  282693 */   // GIR_Coverage, 14589,
     /*  282693 */   GIR_EraseRootFromParent_Done,
     /*  282694 */ // Label 4179: @282694
     /*  282694 */ GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(282756), // Rule ID 14590 //
     /*  282699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  282702 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282705 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282714 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282718 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282725 */   // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282725 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282728 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282750 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282754 */   GIR_RootConstrainSelectedInstOperands,
     /*  282755 */   // GIR_Coverage, 14590,
     /*  282755 */   GIR_EraseRootFromParent_Done,
     /*  282756 */ // Label 4180: @282756
     /*  282756 */ GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(282818), // Rule ID 14591 //
     /*  282761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  282764 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282780 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282787 */   // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282787 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282790 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282807 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282812 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282816 */   GIR_RootConstrainSelectedInstOperands,
     /*  282817 */   // GIR_Coverage, 14591,
     /*  282817 */   GIR_EraseRootFromParent_Done,
     /*  282818 */ // Label 4181: @282818
     /*  282818 */ GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(282880), // Rule ID 14617 //
     /*  282823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  282826 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282842 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282849 */   // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282878 */   GIR_RootConstrainSelectedInstOperands,
     /*  282879 */   // GIR_Coverage, 14617,
     /*  282879 */   GIR_EraseRootFromParent_Done,
     /*  282880 */ // Label 4182: @282880
     /*  282880 */ GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(282942), // Rule ID 14618 //
     /*  282885 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  282888 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282891 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282904 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282911 */   // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282914 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282936 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  282940 */   GIR_RootConstrainSelectedInstOperands,
     /*  282941 */   // GIR_Coverage, 14618,
     /*  282941 */   GIR_EraseRootFromParent_Done,
     /*  282942 */ // Label 4183: @282942
     /*  282942 */ GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(283004), // Rule ID 14619 //
     /*  282947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  282950 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  282953 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  282958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  282962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  282966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  282973 */   // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  282973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  282976 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  282978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  282983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  282988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  282993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  282998 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283002 */   GIR_RootConstrainSelectedInstOperands,
     /*  283003 */   // GIR_Coverage, 14619,
     /*  283003 */   GIR_EraseRootFromParent_Done,
     /*  283004 */ // Label 4184: @283004
     /*  283004 */ GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(283066), // Rule ID 14620 //
     /*  283009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  283012 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283024 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283028 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  283035 */   // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  283035 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  283038 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  283050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  283055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  283060 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283064 */   GIR_RootConstrainSelectedInstOperands,
     /*  283065 */   // GIR_Coverage, 14620,
     /*  283065 */   GIR_EraseRootFromParent_Done,
     /*  283066 */ // Label 4185: @283066
     /*  283066 */ GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(283128), // Rule ID 14621 //
     /*  283071 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  283074 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283077 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283086 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283090 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  283097 */   // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  283097 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  283100 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  283112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  283117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  283122 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283126 */   GIR_RootConstrainSelectedInstOperands,
     /*  283127 */   // GIR_Coverage, 14621,
     /*  283127 */   GIR_EraseRootFromParent_Done,
     /*  283128 */ // Label 4186: @283128
     /*  283128 */ GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(283183), // Rule ID 14582 //
     /*  283133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  283136 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283139 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283159 */   // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283181 */   GIR_RootConstrainSelectedInstOperands,
     /*  283182 */   // GIR_Coverage, 14582,
     /*  283182 */   GIR_EraseRootFromParent_Done,
     /*  283183 */ // Label 4187: @283183
     /*  283183 */ GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(283238), // Rule ID 14583 //
     /*  283188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  283191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283199 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283203 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283207 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283214 */   // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283214 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283217 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283229 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283232 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283236 */   GIR_RootConstrainSelectedInstOperands,
     /*  283237 */   // GIR_Coverage, 14583,
     /*  283237 */   GIR_EraseRootFromParent_Done,
     /*  283238 */ // Label 4188: @283238
     /*  283238 */ GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(283293), // Rule ID 14584 //
     /*  283243 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  283246 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283249 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283258 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283262 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283269 */   // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283269 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283272 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283279 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283287 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283291 */   GIR_RootConstrainSelectedInstOperands,
     /*  283292 */   // GIR_Coverage, 14584,
     /*  283292 */   GIR_EraseRootFromParent_Done,
     /*  283293 */ // Label 4189: @283293
     /*  283293 */ GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(283348), // Rule ID 14585 //
     /*  283298 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  283301 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283304 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283324 */   // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283327 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283346 */   GIR_RootConstrainSelectedInstOperands,
     /*  283347 */   // GIR_Coverage, 14585,
     /*  283347 */   GIR_EraseRootFromParent_Done,
     /*  283348 */ // Label 4190: @283348
     /*  283348 */ GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(283403), // Rule ID 14586 //
     /*  283353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  283356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283368 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283372 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283379 */   // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283379 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283382 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283394 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283397 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283401 */   GIR_RootConstrainSelectedInstOperands,
     /*  283402 */   // GIR_Coverage, 14586,
     /*  283402 */   GIR_EraseRootFromParent_Done,
     /*  283403 */ // Label 4191: @283403
     /*  283403 */ GIM_Try, /*On fail goto*//*Label 4192*/ GIMT_Encode4(283458), // Rule ID 14612 //
     /*  283408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  283411 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283414 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283434 */   // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283449 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283452 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283456 */   GIR_RootConstrainSelectedInstOperands,
     /*  283457 */   // GIR_Coverage, 14612,
     /*  283457 */   GIR_EraseRootFromParent_Done,
     /*  283458 */ // Label 4192: @283458
     /*  283458 */ GIM_Try, /*On fail goto*//*Label 4193*/ GIMT_Encode4(283513), // Rule ID 14613 //
     /*  283463 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  283466 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283469 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283489 */   // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283504 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283507 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283511 */   GIR_RootConstrainSelectedInstOperands,
     /*  283512 */   // GIR_Coverage, 14613,
     /*  283512 */   GIR_EraseRootFromParent_Done,
     /*  283513 */ // Label 4193: @283513
     /*  283513 */ GIM_Try, /*On fail goto*//*Label 4194*/ GIMT_Encode4(283568), // Rule ID 14614 //
     /*  283518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  283521 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283524 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283537 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283544 */   // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283559 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283562 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283566 */   GIR_RootConstrainSelectedInstOperands,
     /*  283567 */   // GIR_Coverage, 14614,
     /*  283567 */   GIR_EraseRootFromParent_Done,
     /*  283568 */ // Label 4194: @283568
     /*  283568 */ GIM_Try, /*On fail goto*//*Label 4195*/ GIMT_Encode4(283623), // Rule ID 14615 //
     /*  283573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  283576 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283588 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283592 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283599 */   // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283602 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283614 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283617 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283621 */   GIR_RootConstrainSelectedInstOperands,
     /*  283622 */   // GIR_Coverage, 14615,
     /*  283622 */   GIR_EraseRootFromParent_Done,
     /*  283623 */ // Label 4195: @283623
     /*  283623 */ GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(283678), // Rule ID 14616 //
     /*  283628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  283631 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283634 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283643 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283647 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  283654 */   // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  283654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  283657 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  283664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283669 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283672 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283676 */   GIR_RootConstrainSelectedInstOperands,
     /*  283677 */   // GIR_Coverage, 14616,
     /*  283677 */   GIR_EraseRootFromParent_Done,
     /*  283678 */ // Label 4196: @283678
     /*  283678 */ GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(283733), // Rule ID 14577 //
     /*  283683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  283686 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283694 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283698 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283702 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  283709 */   // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  283709 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  283712 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283731 */   GIR_RootConstrainSelectedInstOperands,
     /*  283732 */   // GIR_Coverage, 14577,
     /*  283732 */   GIR_EraseRootFromParent_Done,
     /*  283733 */ // Label 4197: @283733
     /*  283733 */ GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(283788), // Rule ID 14578 //
     /*  283738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  283741 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283744 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283749 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283753 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283757 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  283764 */   // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  283764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  283767 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283782 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283786 */   GIR_RootConstrainSelectedInstOperands,
     /*  283787 */   // GIR_Coverage, 14578,
     /*  283787 */   GIR_EraseRootFromParent_Done,
     /*  283788 */ // Label 4198: @283788
     /*  283788 */ GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(283843), // Rule ID 14579 //
     /*  283793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  283796 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283804 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283808 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283812 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  283819 */   // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  283819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  283822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283834 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283837 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283841 */   GIR_RootConstrainSelectedInstOperands,
     /*  283842 */   // GIR_Coverage, 14579,
     /*  283842 */   GIR_EraseRootFromParent_Done,
     /*  283843 */ // Label 4199: @283843
     /*  283843 */ GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(283898), // Rule ID 14580 //
     /*  283848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  283851 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283854 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283863 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283867 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  283874 */   // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  283874 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  283877 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283889 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283892 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283896 */   GIR_RootConstrainSelectedInstOperands,
     /*  283897 */   // GIR_Coverage, 14580,
     /*  283897 */   GIR_EraseRootFromParent_Done,
     /*  283898 */ // Label 4200: @283898
     /*  283898 */ GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(283953), // Rule ID 14581 //
     /*  283903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  283906 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283909 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283918 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283922 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  283929 */   // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  283929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  283932 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283944 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  283947 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  283951 */   GIR_RootConstrainSelectedInstOperands,
     /*  283952 */   // GIR_Coverage, 14581,
     /*  283952 */   GIR_EraseRootFromParent_Done,
     /*  283953 */ // Label 4201: @283953
     /*  283953 */ GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(284008), // Rule ID 14607 //
     /*  283958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  283961 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  283964 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  283969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  283973 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  283977 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  283984 */   // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  283984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  283987 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  283989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  283994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  283999 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284002 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284006 */   GIR_RootConstrainSelectedInstOperands,
     /*  284007 */   // GIR_Coverage, 14607,
     /*  284007 */   GIR_EraseRootFromParent_Done,
     /*  284008 */ // Label 4202: @284008
     /*  284008 */ GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(284063), // Rule ID 14608 //
     /*  284013 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  284016 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284019 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  284024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284032 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  284039 */   // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  284039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  284042 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  284044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  284049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  284054 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284057 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284061 */   GIR_RootConstrainSelectedInstOperands,
     /*  284062 */   // GIR_Coverage, 14608,
     /*  284062 */   GIR_EraseRootFromParent_Done,
     /*  284063 */ // Label 4203: @284063
     /*  284063 */ GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(284118), // Rule ID 14609 //
     /*  284068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  284071 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284074 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  284079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  284094 */   // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  284094 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  284097 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  284099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  284104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  284109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284116 */   GIR_RootConstrainSelectedInstOperands,
     /*  284117 */   // GIR_Coverage, 14609,
     /*  284117 */   GIR_EraseRootFromParent_Done,
     /*  284118 */ // Label 4204: @284118
     /*  284118 */ GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(284173), // Rule ID 14610 //
     /*  284123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  284126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  284134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284138 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284142 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  284149 */   // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  284149 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  284152 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  284154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  284159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  284164 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284167 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284171 */   GIR_RootConstrainSelectedInstOperands,
     /*  284172 */   // GIR_Coverage, 14610,
     /*  284172 */   GIR_EraseRootFromParent_Done,
     /*  284173 */ // Label 4205: @284173
     /*  284173 */ GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(284228), // Rule ID 14611 //
     /*  284178 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  284181 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284184 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  284189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284197 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  284204 */   // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  284204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  284207 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  284209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  284214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  284219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284222 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284226 */   GIR_RootConstrainSelectedInstOperands,
     /*  284227 */   // GIR_Coverage, 14611,
     /*  284227 */   GIR_EraseRootFromParent_Done,
     /*  284228 */ // Label 4206: @284228
     /*  284228 */ GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(284298), // Rule ID 15748 //
     /*  284233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  284236 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284261 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  284264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284289 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284292 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284296 */   GIR_RootConstrainSelectedInstOperands,
     /*  284297 */   // GIR_Coverage, 15748,
     /*  284297 */   GIR_EraseRootFromParent_Done,
     /*  284298 */ // Label 4207: @284298
     /*  284298 */ GIM_Try, /*On fail goto*//*Label 4208*/ GIMT_Encode4(284368), // Rule ID 15749 //
     /*  284303 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  284306 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284309 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284316 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284320 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284324 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284331 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284331 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  284334 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284359 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284362 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284366 */   GIR_RootConstrainSelectedInstOperands,
     /*  284367 */   // GIR_Coverage, 15749,
     /*  284367 */   GIR_EraseRootFromParent_Done,
     /*  284368 */ // Label 4208: @284368
     /*  284368 */ GIM_Try, /*On fail goto*//*Label 4209*/ GIMT_Encode4(284438), // Rule ID 15750 //
     /*  284373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  284376 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284379 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284390 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284394 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284401 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284401 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  284404 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284426 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284436 */   GIR_RootConstrainSelectedInstOperands,
     /*  284437 */   // GIR_Coverage, 15750,
     /*  284437 */   GIR_EraseRootFromParent_Done,
     /*  284438 */ // Label 4209: @284438
     /*  284438 */ GIM_Try, /*On fail goto*//*Label 4210*/ GIMT_Encode4(284508), // Rule ID 15751 //
     /*  284443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  284446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284471 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  284474 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284506 */   GIR_RootConstrainSelectedInstOperands,
     /*  284507 */   // GIR_Coverage, 15751,
     /*  284507 */   GIR_EraseRootFromParent_Done,
     /*  284508 */ // Label 4210: @284508
     /*  284508 */ GIM_Try, /*On fail goto*//*Label 4211*/ GIMT_Encode4(284578), // Rule ID 15752 //
     /*  284513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  284516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284530 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284541 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  284544 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284576 */   GIR_RootConstrainSelectedInstOperands,
     /*  284577 */   // GIR_Coverage, 15752,
     /*  284577 */   GIR_EraseRootFromParent_Done,
     /*  284578 */ // Label 4211: @284578
     /*  284578 */ GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(284648), // Rule ID 15758 //
     /*  284583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  284586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284589 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284600 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284604 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284611 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  284614 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284636 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284639 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284642 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284646 */   GIR_RootConstrainSelectedInstOperands,
     /*  284647 */   // GIR_Coverage, 15758,
     /*  284647 */   GIR_EraseRootFromParent_Done,
     /*  284648 */ // Label 4212: @284648
     /*  284648 */ GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(284718), // Rule ID 15759 //
     /*  284653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  284656 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284659 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284670 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284674 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284681 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  284684 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284706 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284709 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284712 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284716 */   GIR_RootConstrainSelectedInstOperands,
     /*  284717 */   // GIR_Coverage, 15759,
     /*  284717 */   GIR_EraseRootFromParent_Done,
     /*  284718 */ // Label 4213: @284718
     /*  284718 */ GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(284788), // Rule ID 15760 //
     /*  284723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  284726 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284729 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284740 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284744 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284751 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284751 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  284754 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284782 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284786 */   GIR_RootConstrainSelectedInstOperands,
     /*  284787 */   // GIR_Coverage, 15760,
     /*  284787 */   GIR_EraseRootFromParent_Done,
     /*  284788 */ // Label 4214: @284788
     /*  284788 */ GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(284858), // Rule ID 15761 //
     /*  284793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  284796 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284821 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  284824 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284846 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284856 */   GIR_RootConstrainSelectedInstOperands,
     /*  284857 */   // GIR_Coverage, 15761,
     /*  284857 */   GIR_EraseRootFromParent_Done,
     /*  284858 */ // Label 4215: @284858
     /*  284858 */ GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(284928), // Rule ID 15762 //
     /*  284863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  284866 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284869 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284891 */   // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  284894 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284922 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284926 */   GIR_RootConstrainSelectedInstOperands,
     /*  284927 */   // GIR_Coverage, 15762,
     /*  284927 */   GIR_EraseRootFromParent_Done,
     /*  284928 */ // Label 4216: @284928
     /*  284928 */ GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(284998), // Rule ID 15768 //
     /*  284933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  284936 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  284939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  284946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  284950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  284954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  284961 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  284961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  284964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  284966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  284971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  284976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  284981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  284986 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284989 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  284992 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  284996 */   GIR_RootConstrainSelectedInstOperands,
     /*  284997 */   // GIR_Coverage, 15768,
     /*  284997 */   GIR_EraseRootFromParent_Done,
     /*  284998 */ // Label 4217: @284998
     /*  284998 */ GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(285068), // Rule ID 15769 //
     /*  285003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  285006 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285020 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285024 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285031 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285031 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  285034 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285059 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285062 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285066 */   GIR_RootConstrainSelectedInstOperands,
     /*  285067 */   // GIR_Coverage, 15769,
     /*  285067 */   GIR_EraseRootFromParent_Done,
     /*  285068 */ // Label 4218: @285068
     /*  285068 */ GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(285138), // Rule ID 15770 //
     /*  285073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  285076 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285079 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285101 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  285104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285126 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285132 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285136 */   GIR_RootConstrainSelectedInstOperands,
     /*  285137 */   // GIR_Coverage, 15770,
     /*  285137 */   GIR_EraseRootFromParent_Done,
     /*  285138 */ // Label 4219: @285138
     /*  285138 */ GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(285208), // Rule ID 15771 //
     /*  285143 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  285146 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285149 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285160 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285164 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285171 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  285174 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285196 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285199 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285202 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285206 */   GIR_RootConstrainSelectedInstOperands,
     /*  285207 */   // GIR_Coverage, 15771,
     /*  285207 */   GIR_EraseRootFromParent_Done,
     /*  285208 */ // Label 4220: @285208
     /*  285208 */ GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(285278), // Rule ID 15772 //
     /*  285213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  285216 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285219 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285241 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  285244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285266 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285276 */   GIR_RootConstrainSelectedInstOperands,
     /*  285277 */   // GIR_Coverage, 15772,
     /*  285277 */   GIR_EraseRootFromParent_Done,
     /*  285278 */ // Label 4221: @285278
     /*  285278 */ GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(285348), // Rule ID 15778 //
     /*  285283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  285286 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285311 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  285314 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285346 */   GIR_RootConstrainSelectedInstOperands,
     /*  285347 */   // GIR_Coverage, 15778,
     /*  285347 */   GIR_EraseRootFromParent_Done,
     /*  285348 */ // Label 4222: @285348
     /*  285348 */ GIM_Try, /*On fail goto*//*Label 4223*/ GIMT_Encode4(285418), // Rule ID 15779 //
     /*  285353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  285356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285370 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285374 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285381 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  285384 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285409 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285412 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285416 */   GIR_RootConstrainSelectedInstOperands,
     /*  285417 */   // GIR_Coverage, 15779,
     /*  285417 */   GIR_EraseRootFromParent_Done,
     /*  285418 */ // Label 4223: @285418
     /*  285418 */ GIM_Try, /*On fail goto*//*Label 4224*/ GIMT_Encode4(285488), // Rule ID 15780 //
     /*  285423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  285426 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285429 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285440 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285444 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285451 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285451 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  285454 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285456 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285476 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285479 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285482 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285486 */   GIR_RootConstrainSelectedInstOperands,
     /*  285487 */   // GIR_Coverage, 15780,
     /*  285487 */   GIR_EraseRootFromParent_Done,
     /*  285488 */ // Label 4224: @285488
     /*  285488 */ GIM_Try, /*On fail goto*//*Label 4225*/ GIMT_Encode4(285558), // Rule ID 15781 //
     /*  285493 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  285496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285514 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285521 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  285524 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285541 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285546 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285549 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285552 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285556 */   GIR_RootConstrainSelectedInstOperands,
     /*  285557 */   // GIR_Coverage, 15781,
     /*  285557 */   GIR_EraseRootFromParent_Done,
     /*  285558 */ // Label 4225: @285558
     /*  285558 */ GIM_Try, /*On fail goto*//*Label 4226*/ GIMT_Encode4(285628), // Rule ID 15782 //
     /*  285563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  285566 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  285576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  285591 */   // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  285591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  285594 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285616 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285622 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285626 */   GIR_RootConstrainSelectedInstOperands,
     /*  285627 */   // GIR_Coverage, 15782,
     /*  285627 */   GIR_EraseRootFromParent_Done,
     /*  285628 */ // Label 4226: @285628
     /*  285628 */ GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(285696), // Rule ID 25371 //
     /*  285633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  285636 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285639 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  285644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  285659 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  285659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
     /*  285662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285684 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285687 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285690 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285694 */   GIR_RootConstrainSelectedInstOperands,
     /*  285695 */   // GIR_Coverage, 25371,
     /*  285695 */   GIR_EraseRootFromParent_Done,
     /*  285696 */ // Label 4227: @285696
     /*  285696 */ GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(285764), // Rule ID 25372 //
     /*  285701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  285704 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285707 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  285712 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285716 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285720 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  285727 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  285727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
     /*  285730 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285752 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285758 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285762 */   GIR_RootConstrainSelectedInstOperands,
     /*  285763 */   // GIR_Coverage, 25372,
     /*  285763 */   GIR_EraseRootFromParent_Done,
     /*  285764 */ // Label 4228: @285764
     /*  285764 */ GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(285832), // Rule ID 25373 //
     /*  285769 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  285772 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  285780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285784 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285788 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  285795 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  285795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
     /*  285798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285820 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285823 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285826 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285830 */   GIR_RootConstrainSelectedInstOperands,
     /*  285831 */   // GIR_Coverage, 25373,
     /*  285831 */   GIR_EraseRootFromParent_Done,
     /*  285832 */ // Label 4229: @285832
     /*  285832 */ GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(285900), // Rule ID 25374 //
     /*  285837 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  285840 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285843 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  285848 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285852 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285856 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  285863 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  285863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
     /*  285866 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285888 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285891 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285894 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285898 */   GIR_RootConstrainSelectedInstOperands,
     /*  285899 */   // GIR_Coverage, 25374,
     /*  285899 */   GIR_EraseRootFromParent_Done,
     /*  285900 */ // Label 4230: @285900
     /*  285900 */ GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(285968), // Rule ID 25375 //
     /*  285905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  285908 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285911 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  285916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285920 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285924 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  285931 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  285931 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
     /*  285934 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  285936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  285941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  285946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  285951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  285956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  285962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  285966 */   GIR_RootConstrainSelectedInstOperands,
     /*  285967 */   // GIR_Coverage, 25375,
     /*  285967 */   GIR_EraseRootFromParent_Done,
     /*  285968 */ // Label 4231: @285968
     /*  285968 */ GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(286036), // Rule ID 25381 //
     /*  285973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  285976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  285979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  285984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  285988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  285992 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  285999 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  285999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
     /*  286002 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  286004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  286009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  286014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  286019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  286024 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286027 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286030 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286034 */   GIR_RootConstrainSelectedInstOperands,
     /*  286035 */   // GIR_Coverage, 25381,
     /*  286035 */   GIR_EraseRootFromParent_Done,
     /*  286036 */ // Label 4232: @286036
     /*  286036 */ GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(286104), // Rule ID 25382 //
     /*  286041 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  286044 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286047 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  286052 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286056 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286060 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  286067 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  286067 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
     /*  286070 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  286072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  286077 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  286082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  286087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  286092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286095 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286098 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286102 */   GIR_RootConstrainSelectedInstOperands,
     /*  286103 */   // GIR_Coverage, 25382,
     /*  286103 */   GIR_EraseRootFromParent_Done,
     /*  286104 */ // Label 4233: @286104
     /*  286104 */ GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(286172), // Rule ID 25383 //
     /*  286109 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  286112 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286115 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  286120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  286135 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  286135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
     /*  286138 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  286140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  286145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  286150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  286155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  286160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286170 */   GIR_RootConstrainSelectedInstOperands,
     /*  286171 */   // GIR_Coverage, 25383,
     /*  286171 */   GIR_EraseRootFromParent_Done,
     /*  286172 */ // Label 4234: @286172
     /*  286172 */ GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(286240), // Rule ID 25384 //
     /*  286177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  286180 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286183 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  286188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286192 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286196 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  286203 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  286203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
     /*  286206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  286208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  286213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  286218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  286223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  286228 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286231 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286234 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286238 */   GIR_RootConstrainSelectedInstOperands,
     /*  286239 */   // GIR_Coverage, 25384,
     /*  286239 */   GIR_EraseRootFromParent_Done,
     /*  286240 */ // Label 4235: @286240
     /*  286240 */ GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(286308), // Rule ID 25385 //
     /*  286245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  286248 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  286256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  286271 */   // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  286271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
     /*  286274 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  286276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  286281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  286286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  286291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  286296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286306 */   GIR_RootConstrainSelectedInstOperands,
     /*  286307 */   // GIR_Coverage, 25385,
     /*  286307 */   GIR_EraseRootFromParent_Done,
     /*  286308 */ // Label 4236: @286308
     /*  286308 */ GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(286372), // Rule ID 29387 //
     /*  286313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  286316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286319 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286323 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286343 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286370 */   GIR_RootConstrainSelectedInstOperands,
     /*  286371 */   // GIR_Coverage, 29387,
     /*  286371 */   GIR_EraseRootFromParent_Done,
     /*  286372 */ // Label 4237: @286372
     /*  286372 */ GIM_Try, /*On fail goto*//*Label 4238*/ GIMT_Encode4(286436), // Rule ID 29388 //
     /*  286377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  286380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286383 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286387 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286407 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286434 */   GIR_RootConstrainSelectedInstOperands,
     /*  286435 */   // GIR_Coverage, 29388,
     /*  286435 */   GIR_EraseRootFromParent_Done,
     /*  286436 */ // Label 4238: @286436
     /*  286436 */ GIM_Try, /*On fail goto*//*Label 4239*/ GIMT_Encode4(286500), // Rule ID 29389 //
     /*  286441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  286444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286447 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286451 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286471 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286474 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286498 */   GIR_RootConstrainSelectedInstOperands,
     /*  286499 */   // GIR_Coverage, 29389,
     /*  286499 */   GIR_EraseRootFromParent_Done,
     /*  286500 */ // Label 4239: @286500
     /*  286500 */ GIM_Try, /*On fail goto*//*Label 4240*/ GIMT_Encode4(286564), // Rule ID 29390 //
     /*  286505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  286508 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286511 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286515 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286535 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286538 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286562 */   GIR_RootConstrainSelectedInstOperands,
     /*  286563 */   // GIR_Coverage, 29390,
     /*  286563 */   GIR_EraseRootFromParent_Done,
     /*  286564 */ // Label 4240: @286564
     /*  286564 */ GIM_Try, /*On fail goto*//*Label 4241*/ GIMT_Encode4(286628), // Rule ID 29391 //
     /*  286569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  286572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286575 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286588 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286592 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286599 */   // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286602 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286622 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286626 */   GIR_RootConstrainSelectedInstOperands,
     /*  286627 */   // GIR_Coverage, 29391,
     /*  286627 */   GIR_EraseRootFromParent_Done,
     /*  286628 */ // Label 4241: @286628
     /*  286628 */ GIM_Try, /*On fail goto*//*Label 4242*/ GIMT_Encode4(286692), // Rule ID 29503 //
     /*  286633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  286636 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286639 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286648 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286652 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286656 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286663 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286666 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286683 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286690 */   GIR_RootConstrainSelectedInstOperands,
     /*  286691 */   // GIR_Coverage, 29503,
     /*  286691 */   GIR_EraseRootFromParent_Done,
     /*  286692 */ // Label 4242: @286692
     /*  286692 */ GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(286756), // Rule ID 29504 //
     /*  286697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  286700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286703 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286707 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286712 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286716 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286720 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286727 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286730 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286747 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286750 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286754 */   GIR_RootConstrainSelectedInstOperands,
     /*  286755 */   // GIR_Coverage, 29504,
     /*  286755 */   GIR_EraseRootFromParent_Done,
     /*  286756 */ // Label 4243: @286756
     /*  286756 */ GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(286820), // Rule ID 29505 //
     /*  286761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  286764 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286767 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286771 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286780 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286784 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286791 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286791 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286794 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286814 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286818 */   GIR_RootConstrainSelectedInstOperands,
     /*  286819 */   // GIR_Coverage, 29505,
     /*  286819 */   GIR_EraseRootFromParent_Done,
     /*  286820 */ // Label 4244: @286820
     /*  286820 */ GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(286884), // Rule ID 29506 //
     /*  286825 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  286828 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286831 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286835 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286844 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286848 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286855 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286855 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286858 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286882 */   GIR_RootConstrainSelectedInstOperands,
     /*  286883 */   // GIR_Coverage, 29506,
     /*  286883 */   GIR_EraseRootFromParent_Done,
     /*  286884 */ // Label 4245: @286884
     /*  286884 */ GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(286948), // Rule ID 29507 //
     /*  286889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  286892 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286895 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  286899 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  286904 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286908 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286912 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  286919 */   // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  286919 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  286922 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  286924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  286929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  286934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  286939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  286942 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  286946 */   GIR_RootConstrainSelectedInstOperands,
     /*  286947 */   // GIR_Coverage, 29507,
     /*  286947 */   GIR_EraseRootFromParent_Done,
     /*  286948 */ // Label 4246: @286948
     /*  286948 */ GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(287013), // Rule ID 15743 //
     /*  286953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  286956 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  286959 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  286966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  286970 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  286974 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  286981 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  286981 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  286984 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  286986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  286991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  286996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287004 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287007 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287011 */   GIR_RootConstrainSelectedInstOperands,
     /*  287012 */   // GIR_Coverage, 15743,
     /*  287012 */   GIR_EraseRootFromParent_Done,
     /*  287013 */ // Label 4247: @287013
     /*  287013 */ GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(287078), // Rule ID 15744 //
     /*  287018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  287021 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287024 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287046 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287066 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287069 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287072 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287076 */   GIR_RootConstrainSelectedInstOperands,
     /*  287077 */   // GIR_Coverage, 15744,
     /*  287077 */   GIR_EraseRootFromParent_Done,
     /*  287078 */ // Label 4248: @287078
     /*  287078 */ GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(287143), // Rule ID 15745 //
     /*  287083 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  287086 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287089 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287100 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287104 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287111 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287111 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287114 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287137 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287141 */   GIR_RootConstrainSelectedInstOperands,
     /*  287142 */   // GIR_Coverage, 15745,
     /*  287142 */   GIR_EraseRootFromParent_Done,
     /*  287143 */ // Label 4249: @287143
     /*  287143 */ GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(287208), // Rule ID 15746 //
     /*  287148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  287151 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287154 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287176 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287179 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287196 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287199 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287202 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287206 */   GIR_RootConstrainSelectedInstOperands,
     /*  287207 */   // GIR_Coverage, 15746,
     /*  287207 */   GIR_EraseRootFromParent_Done,
     /*  287208 */ // Label 4250: @287208
     /*  287208 */ GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(287273), // Rule ID 15747 //
     /*  287213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  287216 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287219 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287241 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287271 */   GIR_RootConstrainSelectedInstOperands,
     /*  287272 */   // GIR_Coverage, 15747,
     /*  287272 */   GIR_EraseRootFromParent_Done,
     /*  287273 */ // Label 4251: @287273
     /*  287273 */ GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(287338), // Rule ID 15753 //
     /*  287278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  287281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287295 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287306 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  287309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287329 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287332 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287336 */   GIR_RootConstrainSelectedInstOperands,
     /*  287337 */   // GIR_Coverage, 15753,
     /*  287337 */   GIR_EraseRootFromParent_Done,
     /*  287338 */ // Label 4252: @287338
     /*  287338 */ GIM_Try, /*On fail goto*//*Label 4253*/ GIMT_Encode4(287403), // Rule ID 15754 //
     /*  287343 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  287346 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287349 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287360 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287364 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287371 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  287374 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287391 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287394 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287397 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287401 */   GIR_RootConstrainSelectedInstOperands,
     /*  287402 */   // GIR_Coverage, 15754,
     /*  287402 */   GIR_EraseRootFromParent_Done,
     /*  287403 */ // Label 4253: @287403
     /*  287403 */ GIM_Try, /*On fail goto*//*Label 4254*/ GIMT_Encode4(287468), // Rule ID 15755 //
     /*  287408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  287411 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287414 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287421 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287425 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287429 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287436 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  287439 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287456 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287459 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287466 */   GIR_RootConstrainSelectedInstOperands,
     /*  287467 */   // GIR_Coverage, 15755,
     /*  287467 */   GIR_EraseRootFromParent_Done,
     /*  287468 */ // Label 4254: @287468
     /*  287468 */ GIM_Try, /*On fail goto*//*Label 4255*/ GIMT_Encode4(287533), // Rule ID 15756 //
     /*  287473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  287476 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287490 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287494 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287501 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  287504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287521 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287524 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287527 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287531 */   GIR_RootConstrainSelectedInstOperands,
     /*  287532 */   // GIR_Coverage, 15756,
     /*  287532 */   GIR_EraseRootFromParent_Done,
     /*  287533 */ // Label 4255: @287533
     /*  287533 */ GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(287598), // Rule ID 15757 //
     /*  287538 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  287541 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287544 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287551 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287566 */   // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  287569 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287586 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287589 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287592 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287596 */   GIR_RootConstrainSelectedInstOperands,
     /*  287597 */   // GIR_Coverage, 15757,
     /*  287597 */   GIR_EraseRootFromParent_Done,
     /*  287598 */ // Label 4256: @287598
     /*  287598 */ GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(287663), // Rule ID 15763 //
     /*  287603 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  287606 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287609 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287620 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287624 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287631 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287651 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287654 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287661 */   GIR_RootConstrainSelectedInstOperands,
     /*  287662 */   // GIR_Coverage, 15763,
     /*  287662 */   GIR_EraseRootFromParent_Done,
     /*  287663 */ // Label 4257: @287663
     /*  287663 */ GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(287728), // Rule ID 15764 //
     /*  287668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  287671 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287674 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287696 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287716 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287722 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287726 */   GIR_RootConstrainSelectedInstOperands,
     /*  287727 */   // GIR_Coverage, 15764,
     /*  287727 */   GIR_EraseRootFromParent_Done,
     /*  287728 */ // Label 4258: @287728
     /*  287728 */ GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(287793), // Rule ID 15765 //
     /*  287733 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  287736 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287739 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287761 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287764 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287781 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287784 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287787 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287791 */   GIR_RootConstrainSelectedInstOperands,
     /*  287792 */   // GIR_Coverage, 15765,
     /*  287792 */   GIR_EraseRootFromParent_Done,
     /*  287793 */ // Label 4259: @287793
     /*  287793 */ GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(287858), // Rule ID 15766 //
     /*  287798 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  287801 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287804 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287815 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287819 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287826 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287829 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287846 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287856 */   GIR_RootConstrainSelectedInstOperands,
     /*  287857 */   // GIR_Coverage, 15766,
     /*  287857 */   GIR_EraseRootFromParent_Done,
     /*  287858 */ // Label 4260: @287858
     /*  287858 */ GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(287923), // Rule ID 15767 //
     /*  287863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  287866 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287869 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287891 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  287894 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287911 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287917 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287921 */   GIR_RootConstrainSelectedInstOperands,
     /*  287922 */   // GIR_Coverage, 15767,
     /*  287922 */   GIR_EraseRootFromParent_Done,
     /*  287923 */ // Label 4261: @287923
     /*  287923 */ GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(287988), // Rule ID 15773 //
     /*  287928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  287931 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287934 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  287941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  287945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  287949 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  287956 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  287956 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  287959 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  287961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  287966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  287971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  287976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  287982 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  287986 */   GIR_RootConstrainSelectedInstOperands,
     /*  287987 */   // GIR_Coverage, 15773,
     /*  287987 */   GIR_EraseRootFromParent_Done,
     /*  287988 */ // Label 4262: @287988
     /*  287988 */ GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(288053), // Rule ID 15774 //
     /*  287993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  287996 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  287999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  288006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  288021 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  288021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  288024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  288026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  288031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  288036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  288041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288047 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288051 */   GIR_RootConstrainSelectedInstOperands,
     /*  288052 */   // GIR_Coverage, 15774,
     /*  288052 */   GIR_EraseRootFromParent_Done,
     /*  288053 */ // Label 4263: @288053
     /*  288053 */ GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(288118), // Rule ID 15775 //
     /*  288058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  288061 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288064 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  288071 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288075 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288079 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  288086 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  288086 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  288089 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  288091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  288096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  288101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  288106 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288116 */   GIR_RootConstrainSelectedInstOperands,
     /*  288117 */   // GIR_Coverage, 15775,
     /*  288117 */   GIR_EraseRootFromParent_Done,
     /*  288118 */ // Label 4264: @288118
     /*  288118 */ GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(288183), // Rule ID 15776 //
     /*  288123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  288126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  288136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  288151 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  288151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  288154 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  288156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  288161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  288166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  288171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288181 */   GIR_RootConstrainSelectedInstOperands,
     /*  288182 */   // GIR_Coverage, 15776,
     /*  288182 */   GIR_EraseRootFromParent_Done,
     /*  288183 */ // Label 4265: @288183
     /*  288183 */ GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(288248), // Rule ID 15777 //
     /*  288188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  288191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  288201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288205 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288209 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  288216 */   // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  288216 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  288219 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  288221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  288226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  288231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  288236 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288246 */   GIR_RootConstrainSelectedInstOperands,
     /*  288247 */   // GIR_Coverage, 15777,
     /*  288247 */   GIR_EraseRootFromParent_Done,
     /*  288248 */ // Label 4266: @288248
     /*  288248 */ GIM_Try, /*On fail goto*//*Label 4267*/ GIMT_Encode4(288308), // Rule ID 29397 //
     /*  288253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  288256 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288259 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288279 */   // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288306 */   GIR_RootConstrainSelectedInstOperands,
     /*  288307 */   // GIR_Coverage, 29397,
     /*  288307 */   GIR_EraseRootFromParent_Done,
     /*  288308 */ // Label 4267: @288308
     /*  288308 */ GIM_Try, /*On fail goto*//*Label 4268*/ GIMT_Encode4(288368), // Rule ID 29398 //
     /*  288313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  288316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288328 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288332 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288339 */   // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288339 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288342 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288359 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288362 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288366 */   GIR_RootConstrainSelectedInstOperands,
     /*  288367 */   // GIR_Coverage, 29398,
     /*  288367 */   GIR_EraseRootFromParent_Done,
     /*  288368 */ // Label 4268: @288368
     /*  288368 */ GIM_Try, /*On fail goto*//*Label 4269*/ GIMT_Encode4(288428), // Rule ID 29399 //
     /*  288373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  288376 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288379 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288384 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288388 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288392 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288399 */   // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288399 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288402 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288426 */   GIR_RootConstrainSelectedInstOperands,
     /*  288427 */   // GIR_Coverage, 29399,
     /*  288427 */   GIR_EraseRootFromParent_Done,
     /*  288428 */ // Label 4269: @288428
     /*  288428 */ GIM_Try, /*On fail goto*//*Label 4270*/ GIMT_Encode4(288488), // Rule ID 29400 //
     /*  288433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  288436 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288439 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288459 */   // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288462 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288479 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288482 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288486 */   GIR_RootConstrainSelectedInstOperands,
     /*  288487 */   // GIR_Coverage, 29400,
     /*  288487 */   GIR_EraseRootFromParent_Done,
     /*  288488 */ // Label 4270: @288488
     /*  288488 */ GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(288548), // Rule ID 29401 //
     /*  288493 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  288496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288519 */   // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288539 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288542 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288546 */   GIR_RootConstrainSelectedInstOperands,
     /*  288547 */   // GIR_Coverage, 29401,
     /*  288547 */   GIR_EraseRootFromParent_Done,
     /*  288548 */ // Label 4271: @288548
     /*  288548 */ GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(288608), // Rule ID 29513 //
     /*  288553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  288556 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288559 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288564 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288568 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288572 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288579 */   // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288582 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288606 */   GIR_RootConstrainSelectedInstOperands,
     /*  288607 */   // GIR_Coverage, 29513,
     /*  288607 */   GIR_EraseRootFromParent_Done,
     /*  288608 */ // Label 4272: @288608
     /*  288608 */ GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(288668), // Rule ID 29514 //
     /*  288613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  288616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288632 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288639 */   // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288642 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288662 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288666 */   GIR_RootConstrainSelectedInstOperands,
     /*  288667 */   // GIR_Coverage, 29514,
     /*  288667 */   GIR_EraseRootFromParent_Done,
     /*  288668 */ // Label 4273: @288668
     /*  288668 */ GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(288728), // Rule ID 29515 //
     /*  288673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  288676 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288679 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288684 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288688 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288692 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288699 */   // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288702 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288722 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288726 */   GIR_RootConstrainSelectedInstOperands,
     /*  288727 */   // GIR_Coverage, 29515,
     /*  288727 */   GIR_EraseRootFromParent_Done,
     /*  288728 */ // Label 4274: @288728
     /*  288728 */ GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(288788), // Rule ID 29516 //
     /*  288733 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  288736 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288739 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288759 */   // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288782 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288786 */   GIR_RootConstrainSelectedInstOperands,
     /*  288787 */   // GIR_Coverage, 29516,
     /*  288787 */   GIR_EraseRootFromParent_Done,
     /*  288788 */ // Label 4275: @288788
     /*  288788 */ GIM_Try, /*On fail goto*//*Label 4276*/ GIMT_Encode4(288848), // Rule ID 29517 //
     /*  288793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  288796 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  288799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  288804 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288808 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288812 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  288819 */   // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  288819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  288822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  288829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  288834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  288839 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  288842 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288846 */   GIR_RootConstrainSelectedInstOperands,
     /*  288847 */   // GIR_Coverage, 29517,
     /*  288847 */   GIR_EraseRootFromParent_Done,
     /*  288848 */ // Label 4276: @288848
     /*  288848 */ GIM_Try, /*On fail goto*//*Label 4277*/ GIMT_Encode4(288923), // Rule ID 12603 //
     /*  288853 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  288856 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  288859 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  288863 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  288870 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  288877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288881 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288885 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  288892 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  288892 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  288895 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  288902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  288907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  288912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  288917 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288921 */   GIR_RootConstrainSelectedInstOperands,
     /*  288922 */   // GIR_Coverage, 12603,
     /*  288922 */   GIR_EraseRootFromParent_Done,
     /*  288923 */ // Label 4277: @288923
     /*  288923 */ GIM_Try, /*On fail goto*//*Label 4278*/ GIMT_Encode4(288998), // Rule ID 12604 //
     /*  288928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  288931 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  288934 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  288938 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  288945 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  288952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  288956 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  288960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  288967 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  288967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  288970 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  288972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  288977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  288982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  288987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  288992 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  288996 */   GIR_RootConstrainSelectedInstOperands,
     /*  288997 */   // GIR_Coverage, 12604,
     /*  288997 */   GIR_EraseRootFromParent_Done,
     /*  288998 */ // Label 4278: @288998
     /*  288998 */ GIM_Try, /*On fail goto*//*Label 4279*/ GIMT_Encode4(289073), // Rule ID 12605 //
     /*  289003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  289006 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  289009 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  289013 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  289020 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289027 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289031 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289035 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289042 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289045 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289067 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289071 */   GIR_RootConstrainSelectedInstOperands,
     /*  289072 */   // GIR_Coverage, 12605,
     /*  289072 */   GIR_EraseRootFromParent_Done,
     /*  289073 */ // Label 4279: @289073
     /*  289073 */ GIM_Try, /*On fail goto*//*Label 4280*/ GIMT_Encode4(289148), // Rule ID 12606 //
     /*  289078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  289081 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  289084 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  289088 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  289095 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289106 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289110 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289117 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289146 */   GIR_RootConstrainSelectedInstOperands,
     /*  289147 */   // GIR_Coverage, 12606,
     /*  289147 */   GIR_EraseRootFromParent_Done,
     /*  289148 */ // Label 4280: @289148
     /*  289148 */ GIM_Try, /*On fail goto*//*Label 4281*/ GIMT_Encode4(289223), // Rule ID 12607 //
     /*  289153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  289156 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  289159 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  289163 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  289170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289192 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289195 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289221 */   GIR_RootConstrainSelectedInstOperands,
     /*  289222 */   // GIR_Coverage, 12607,
     /*  289222 */   GIR_EraseRootFromParent_Done,
     /*  289223 */ // Label 4281: @289223
     /*  289223 */ GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(289287), // Rule ID 12453 //
     /*  289228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  289231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289245 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289256 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289281 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289285 */   GIR_RootConstrainSelectedInstOperands,
     /*  289286 */   // GIR_Coverage, 12453,
     /*  289286 */   GIR_EraseRootFromParent_Done,
     /*  289287 */ // Label 4282: @289287
     /*  289287 */ GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(289351), // Rule ID 12454 //
     /*  289292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  289295 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289298 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289320 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289349 */   GIR_RootConstrainSelectedInstOperands,
     /*  289350 */   // GIR_Coverage, 12454,
     /*  289350 */   GIR_EraseRootFromParent_Done,
     /*  289351 */ // Label 4283: @289351
     /*  289351 */ GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(289415), // Rule ID 12455 //
     /*  289356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  289359 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289362 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289384 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289413 */   GIR_RootConstrainSelectedInstOperands,
     /*  289414 */   // GIR_Coverage, 12455,
     /*  289414 */   GIR_EraseRootFromParent_Done,
     /*  289415 */ // Label 4284: @289415
     /*  289415 */ GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(289479), // Rule ID 12456 //
     /*  289420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  289423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289426 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289448 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289477 */   GIR_RootConstrainSelectedInstOperands,
     /*  289478 */   // GIR_Coverage, 12456,
     /*  289478 */   GIR_EraseRootFromParent_Done,
     /*  289479 */ // Label 4285: @289479
     /*  289479 */ GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(289543), // Rule ID 12457 //
     /*  289484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  289487 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289490 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289512 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289541 */   GIR_RootConstrainSelectedInstOperands,
     /*  289542 */   // GIR_Coverage, 12457,
     /*  289542 */   GIR_EraseRootFromParent_Done,
     /*  289543 */ // Label 4286: @289543
     /*  289543 */ GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(289607), // Rule ID 12473 //
     /*  289548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  289551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289554 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289569 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289576 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289576 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289579 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289601 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289605 */   GIR_RootConstrainSelectedInstOperands,
     /*  289606 */   // GIR_Coverage, 12473,
     /*  289606 */   GIR_EraseRootFromParent_Done,
     /*  289607 */ // Label 4287: @289607
     /*  289607 */ GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(289671), // Rule ID 12474 //
     /*  289612 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  289615 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289640 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289643 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289665 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289669 */   GIR_RootConstrainSelectedInstOperands,
     /*  289670 */   // GIR_Coverage, 12474,
     /*  289670 */   GIR_EraseRootFromParent_Done,
     /*  289671 */ // Label 4288: @289671
     /*  289671 */ GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(289735), // Rule ID 12475 //
     /*  289676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  289679 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289697 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289704 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289704 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289707 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289729 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289733 */   GIR_RootConstrainSelectedInstOperands,
     /*  289734 */   // GIR_Coverage, 12475,
     /*  289734 */   GIR_EraseRootFromParent_Done,
     /*  289735 */ // Label 4289: @289735
     /*  289735 */ GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(289799), // Rule ID 12476 //
     /*  289740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  289743 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289746 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289757 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289761 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289768 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289768 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289771 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289797 */   GIR_RootConstrainSelectedInstOperands,
     /*  289798 */   // GIR_Coverage, 12476,
     /*  289798 */   GIR_EraseRootFromParent_Done,
     /*  289799 */ // Label 4290: @289799
     /*  289799 */ GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(289863), // Rule ID 12477 //
     /*  289804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  289807 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  289810 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  289832 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  289832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  289835 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  289842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  289847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  289852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  289857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289861 */   GIR_RootConstrainSelectedInstOperands,
     /*  289862 */   // GIR_Coverage, 12477,
     /*  289862 */   GIR_EraseRootFromParent_Done,
     /*  289863 */ // Label 4291: @289863
     /*  289863 */ GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(289931), // Rule ID 12598 //
     /*  289868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  289871 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  289874 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  289878 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  289885 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  289907 */   // (atomic_load:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  289907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  289910 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  289917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  289922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  289925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289929 */   GIR_RootConstrainSelectedInstOperands,
     /*  289930 */   // GIR_Coverage, 12598,
     /*  289930 */   GIR_EraseRootFromParent_Done,
     /*  289931 */ // Label 4292: @289931
     /*  289931 */ GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(289999), // Rule ID 12599 //
     /*  289936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  289939 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  289942 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  289946 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  289953 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  289960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  289964 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  289968 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  289975 */   // (atomic_load:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  289975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  289978 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  289980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  289985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  289990 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  289993 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  289997 */   GIR_RootConstrainSelectedInstOperands,
     /*  289998 */   // GIR_Coverage, 12599,
     /*  289998 */   GIR_EraseRootFromParent_Done,
     /*  289999 */ // Label 4293: @289999
     /*  289999 */ GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(290067), // Rule ID 12600 //
     /*  290004 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  290007 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  290010 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  290014 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  290021 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290032 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290043 */   // (atomic_load:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290046 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290065 */   GIR_RootConstrainSelectedInstOperands,
     /*  290066 */   // GIR_Coverage, 12600,
     /*  290066 */   GIR_EraseRootFromParent_Done,
     /*  290067 */ // Label 4294: @290067
     /*  290067 */ GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(290135), // Rule ID 12601 //
     /*  290072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  290075 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  290078 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  290082 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  290089 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290100 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290104 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290111 */   // (atomic_load:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290111 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290114 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290126 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290129 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290133 */   GIR_RootConstrainSelectedInstOperands,
     /*  290134 */   // GIR_Coverage, 12601,
     /*  290134 */   GIR_EraseRootFromParent_Done,
     /*  290135 */ // Label 4295: @290135
     /*  290135 */ GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(290203), // Rule ID 12602 //
     /*  290140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  290143 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  290146 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  290150 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  290157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290168 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290172 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290179 */   // (atomic_load:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290179 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290182 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290194 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290197 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290201 */   GIR_RootConstrainSelectedInstOperands,
     /*  290202 */   // GIR_Coverage, 12602,
     /*  290202 */   GIR_EraseRootFromParent_Done,
     /*  290203 */ // Label 4296: @290203
     /*  290203 */ GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(290260), // Rule ID 12448 //
     /*  290208 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  290211 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290214 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290236 */   // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290251 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290254 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290258 */   GIR_RootConstrainSelectedInstOperands,
     /*  290259 */   // GIR_Coverage, 12448,
     /*  290259 */   GIR_EraseRootFromParent_Done,
     /*  290260 */ // Label 4297: @290260
     /*  290260 */ GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(290317), // Rule ID 12449 //
     /*  290265 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  290268 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290271 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290278 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290282 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290286 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290293 */   // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290296 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290308 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290311 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290315 */   GIR_RootConstrainSelectedInstOperands,
     /*  290316 */   // GIR_Coverage, 12449,
     /*  290316 */   GIR_EraseRootFromParent_Done,
     /*  290317 */ // Label 4298: @290317
     /*  290317 */ GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(290374), // Rule ID 12450 //
     /*  290322 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  290325 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290328 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290339 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290343 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290350 */   // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290353 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290365 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290372 */   GIR_RootConstrainSelectedInstOperands,
     /*  290373 */   // GIR_Coverage, 12450,
     /*  290373 */   GIR_EraseRootFromParent_Done,
     /*  290374 */ // Label 4299: @290374
     /*  290374 */ GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(290431), // Rule ID 12451 //
     /*  290379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  290382 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290385 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290407 */   // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290429 */   GIR_RootConstrainSelectedInstOperands,
     /*  290430 */   // GIR_Coverage, 12451,
     /*  290430 */   GIR_EraseRootFromParent_Done,
     /*  290431 */ // Label 4300: @290431
     /*  290431 */ GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(290488), // Rule ID 12452 //
     /*  290436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  290439 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290442 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290449 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290453 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290457 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290464 */   // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290467 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290479 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290482 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290486 */   GIR_RootConstrainSelectedInstOperands,
     /*  290487 */   // GIR_Coverage, 12452,
     /*  290487 */   GIR_EraseRootFromParent_Done,
     /*  290488 */ // Label 4301: @290488
     /*  290488 */ GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(290545), // Rule ID 12468 //
     /*  290493 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  290496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290514 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290521 */   // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290524 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290536 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290543 */   GIR_RootConstrainSelectedInstOperands,
     /*  290544 */   // GIR_Coverage, 12468,
     /*  290544 */   GIR_EraseRootFromParent_Done,
     /*  290545 */ // Label 4302: @290545
     /*  290545 */ GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(290602), // Rule ID 12469 //
     /*  290550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  290553 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290578 */   // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290596 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290600 */   GIR_RootConstrainSelectedInstOperands,
     /*  290601 */   // GIR_Coverage, 12469,
     /*  290601 */   GIR_EraseRootFromParent_Done,
     /*  290602 */ // Label 4303: @290602
     /*  290602 */ GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(290659), // Rule ID 12470 //
     /*  290607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  290610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290613 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290620 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290624 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290628 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290635 */   // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290638 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290650 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290653 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290657 */   GIR_RootConstrainSelectedInstOperands,
     /*  290658 */   // GIR_Coverage, 12470,
     /*  290658 */   GIR_EraseRootFromParent_Done,
     /*  290659 */ // Label 4304: @290659
     /*  290659 */ GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(290716), // Rule ID 12471 //
     /*  290664 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  290667 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290670 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290677 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290681 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290685 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290692 */   // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290692 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290695 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290707 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290710 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290714 */   GIR_RootConstrainSelectedInstOperands,
     /*  290715 */   // GIR_Coverage, 12471,
     /*  290715 */   GIR_EraseRootFromParent_Done,
     /*  290716 */ // Label 4305: @290716
     /*  290716 */ GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(290773), // Rule ID 12472 //
     /*  290721 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  290724 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  290727 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290734 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290738 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290742 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  290749 */   // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  290749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  290752 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  290759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  290764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  290767 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290771 */   GIR_RootConstrainSelectedInstOperands,
     /*  290772 */   // GIR_Coverage, 12472,
     /*  290772 */   GIR_EraseRootFromParent_Done,
     /*  290773 */ // Label 4306: @290773
     /*  290773 */ GIM_Try, /*On fail goto*//*Label 4307*/ GIMT_Encode4(290849), // Rule ID 9931 //
     /*  290778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  290781 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  290784 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  290788 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  290795 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290811 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  290818 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  290818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  290821 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  290828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  290833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  290838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  290843 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290847 */   GIR_RootConstrainSelectedInstOperands,
     /*  290848 */   // GIR_Coverage, 9931,
     /*  290848 */   GIR_EraseRootFromParent_Done,
     /*  290849 */ // Label 4307: @290849
     /*  290849 */ GIM_Try, /*On fail goto*//*Label 4308*/ GIMT_Encode4(290925), // Rule ID 9932 //
     /*  290854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  290857 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  290860 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  290864 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  290871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290883 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290887 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  290894 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  290894 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  290897 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  290904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  290909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  290914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  290919 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290923 */   GIR_RootConstrainSelectedInstOperands,
     /*  290924 */   // GIR_Coverage, 9932,
     /*  290924 */   GIR_EraseRootFromParent_Done,
     /*  290925 */ // Label 4308: @290925
     /*  290925 */ GIM_Try, /*On fail goto*//*Label 4309*/ GIMT_Encode4(291001), // Rule ID 9933 //
     /*  290930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  290933 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  290936 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  290940 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  290947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  290955 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  290959 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  290963 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  290970 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  290970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  290973 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  290975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  290980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  290985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  290990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  290995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  290999 */   GIR_RootConstrainSelectedInstOperands,
     /*  291000 */   // GIR_Coverage, 9933,
     /*  291000 */   GIR_EraseRootFromParent_Done,
     /*  291001 */ // Label 4309: @291001
     /*  291001 */ GIM_Try, /*On fail goto*//*Label 4310*/ GIMT_Encode4(291077), // Rule ID 9934 //
     /*  291006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  291009 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  291012 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  291016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  291023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291046 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291071 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291075 */   GIR_RootConstrainSelectedInstOperands,
     /*  291076 */   // GIR_Coverage, 9934,
     /*  291076 */   GIR_EraseRootFromParent_Done,
     /*  291077 */ // Label 4310: @291077
     /*  291077 */ GIM_Try, /*On fail goto*//*Label 4311*/ GIMT_Encode4(291153), // Rule ID 9935 //
     /*  291082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  291085 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  291088 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  291092 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  291099 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291107 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291111 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291115 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291122 */   // (atomic_load:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291125 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291147 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291151 */   GIR_RootConstrainSelectedInstOperands,
     /*  291152 */   // GIR_Coverage, 9935,
     /*  291152 */   GIR_EraseRootFromParent_Done,
     /*  291153 */ // Label 4311: @291153
     /*  291153 */ GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(291218), // Rule ID 10311 //
     /*  291158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  291161 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291164 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291176 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291180 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291187 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291187 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291190 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291216 */   GIR_RootConstrainSelectedInstOperands,
     /*  291217 */   // GIR_Coverage, 10311,
     /*  291217 */   GIR_EraseRootFromParent_Done,
     /*  291218 */ // Label 4312: @291218
     /*  291218 */ GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(291283), // Rule ID 10312 //
     /*  291223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  291226 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291229 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291245 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291252 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291255 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291277 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291281 */   GIR_RootConstrainSelectedInstOperands,
     /*  291282 */   // GIR_Coverage, 10312,
     /*  291282 */   GIR_EraseRootFromParent_Done,
     /*  291283 */ // Label 4313: @291283
     /*  291283 */ GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(291348), // Rule ID 10313 //
     /*  291288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  291291 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291294 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291306 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291310 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291317 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291320 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291346 */   GIR_RootConstrainSelectedInstOperands,
     /*  291347 */   // GIR_Coverage, 10313,
     /*  291347 */   GIR_EraseRootFromParent_Done,
     /*  291348 */ // Label 4314: @291348
     /*  291348 */ GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(291413), // Rule ID 10314 //
     /*  291353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  291356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291371 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291375 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291382 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291385 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291411 */   GIR_RootConstrainSelectedInstOperands,
     /*  291412 */   // GIR_Coverage, 10314,
     /*  291412 */   GIR_EraseRootFromParent_Done,
     /*  291413 */ // Label 4315: @291413
     /*  291413 */ GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(291478), // Rule ID 10315 //
     /*  291418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  291421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291424 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291432 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291436 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291440 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291447 */   // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291450 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291472 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291476 */   GIR_RootConstrainSelectedInstOperands,
     /*  291477 */   // GIR_Coverage, 10315,
     /*  291477 */   GIR_EraseRootFromParent_Done,
     /*  291478 */ // Label 4316: @291478
     /*  291478 */ GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(291543), // Rule ID 10331 //
     /*  291483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  291486 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291489 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291512 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291541 */   GIR_RootConstrainSelectedInstOperands,
     /*  291542 */   // GIR_Coverage, 10331,
     /*  291542 */   GIR_EraseRootFromParent_Done,
     /*  291543 */ // Label 4317: @291543
     /*  291543 */ GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(291608), // Rule ID 10332 //
     /*  291548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  291551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291554 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291562 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291570 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291577 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291580 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291606 */   GIR_RootConstrainSelectedInstOperands,
     /*  291607 */   // GIR_Coverage, 10332,
     /*  291607 */   GIR_EraseRootFromParent_Done,
     /*  291608 */ // Label 4318: @291608
     /*  291608 */ GIM_Try, /*On fail goto*//*Label 4319*/ GIMT_Encode4(291673), // Rule ID 10333 //
     /*  291613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  291616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291642 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291645 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291667 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291671 */   GIR_RootConstrainSelectedInstOperands,
     /*  291672 */   // GIR_Coverage, 10333,
     /*  291672 */   GIR_EraseRootFromParent_Done,
     /*  291673 */ // Label 4319: @291673
     /*  291673 */ GIM_Try, /*On fail goto*//*Label 4320*/ GIMT_Encode4(291738), // Rule ID 10334 //
     /*  291678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  291681 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291692 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291696 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291700 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291707 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291707 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291710 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291736 */   GIR_RootConstrainSelectedInstOperands,
     /*  291737 */   // GIR_Coverage, 10334,
     /*  291737 */   GIR_EraseRootFromParent_Done,
     /*  291738 */ // Label 4320: @291738
     /*  291738 */ GIM_Try, /*On fail goto*//*Label 4321*/ GIMT_Encode4(291803), // Rule ID 10335 //
     /*  291743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  291746 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  291749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  291772 */   // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  291772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  291775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  291782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  291787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  291792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  291797 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291801 */   GIR_RootConstrainSelectedInstOperands,
     /*  291802 */   // GIR_Coverage, 10335,
     /*  291802 */   GIR_EraseRootFromParent_Done,
     /*  291803 */ // Label 4321: @291803
     /*  291803 */ GIM_Try, /*On fail goto*//*Label 4322*/ GIMT_Encode4(291872), // Rule ID 9926 //
     /*  291808 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  291811 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  291814 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  291818 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  291825 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291837 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291841 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  291848 */   // (atomic_load:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  291848 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  291851 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  291858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  291863 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  291866 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291870 */   GIR_RootConstrainSelectedInstOperands,
     /*  291871 */   // GIR_Coverage, 9926,
     /*  291871 */   GIR_EraseRootFromParent_Done,
     /*  291872 */ // Label 4322: @291872
     /*  291872 */ GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(291941), // Rule ID 9927 //
     /*  291877 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  291880 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  291883 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  291887 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  291894 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291902 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291906 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291910 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  291917 */   // (atomic_load:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  291917 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  291920 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  291927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  291932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  291935 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  291939 */   GIR_RootConstrainSelectedInstOperands,
     /*  291940 */   // GIR_Coverage, 9927,
     /*  291940 */   GIR_EraseRootFromParent_Done,
     /*  291941 */ // Label 4323: @291941
     /*  291941 */ GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(292010), // Rule ID 9928 //
     /*  291946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  291949 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  291952 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  291956 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  291963 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  291971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  291975 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  291979 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  291986 */   // (atomic_load:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  291986 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  291989 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  291991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  291996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292004 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292008 */   GIR_RootConstrainSelectedInstOperands,
     /*  292009 */   // GIR_Coverage, 9928,
     /*  292009 */   GIR_EraseRootFromParent_Done,
     /*  292010 */ // Label 4324: @292010
     /*  292010 */ GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(292079), // Rule ID 9929 //
     /*  292015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  292018 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  292021 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  292025 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  292032 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292048 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292055 */   // (atomic_load:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292058 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292070 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292073 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292077 */   GIR_RootConstrainSelectedInstOperands,
     /*  292078 */   // GIR_Coverage, 9929,
     /*  292078 */   GIR_EraseRootFromParent_Done,
     /*  292079 */ // Label 4325: @292079
     /*  292079 */ GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(292148), // Rule ID 9930 //
     /*  292084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  292087 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  292090 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  292094 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  292101 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292113 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292117 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292124 */   // (atomic_load:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_128>><<P:Predicate_atomic_load_nonext_128_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292146 */   GIR_RootConstrainSelectedInstOperands,
     /*  292147 */   // GIR_Coverage, 9930,
     /*  292147 */   GIR_EraseRootFromParent_Done,
     /*  292148 */ // Label 4326: @292148
     /*  292148 */ GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(292206), // Rule ID 10306 //
     /*  292153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  292156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292159 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292167 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292171 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292175 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292182 */   // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292182 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292185 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292197 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292200 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292204 */   GIR_RootConstrainSelectedInstOperands,
     /*  292205 */   // GIR_Coverage, 10306,
     /*  292205 */   GIR_EraseRootFromParent_Done,
     /*  292206 */ // Label 4327: @292206
     /*  292206 */ GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(292264), // Rule ID 10307 //
     /*  292211 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  292214 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292217 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292229 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292233 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292240 */   // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292240 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292243 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292255 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292258 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292262 */   GIR_RootConstrainSelectedInstOperands,
     /*  292263 */   // GIR_Coverage, 10307,
     /*  292263 */   GIR_EraseRootFromParent_Done,
     /*  292264 */ // Label 4328: @292264
     /*  292264 */ GIM_Try, /*On fail goto*//*Label 4329*/ GIMT_Encode4(292322), // Rule ID 10308 //
     /*  292269 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  292272 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292275 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292287 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292298 */   // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292313 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292320 */   GIR_RootConstrainSelectedInstOperands,
     /*  292321 */   // GIR_Coverage, 10308,
     /*  292321 */   GIR_EraseRootFromParent_Done,
     /*  292322 */ // Label 4329: @292322
     /*  292322 */ GIM_Try, /*On fail goto*//*Label 4330*/ GIMT_Encode4(292380), // Rule ID 10309 //
     /*  292327 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  292330 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292345 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292349 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292356 */   // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292356 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292359 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292371 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292374 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292378 */   GIR_RootConstrainSelectedInstOperands,
     /*  292379 */   // GIR_Coverage, 10309,
     /*  292379 */   GIR_EraseRootFromParent_Done,
     /*  292380 */ // Label 4330: @292380
     /*  292380 */ GIM_Try, /*On fail goto*//*Label 4331*/ GIMT_Encode4(292438), // Rule ID 10310 //
     /*  292385 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  292388 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292391 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292414 */   // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292417 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292436 */   GIR_RootConstrainSelectedInstOperands,
     /*  292437 */   // GIR_Coverage, 10310,
     /*  292437 */   GIR_EraseRootFromParent_Done,
     /*  292438 */ // Label 4331: @292438
     /*  292438 */ GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(292496), // Rule ID 10326 //
     /*  292443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  292446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292472 */   // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292487 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292490 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292494 */   GIR_RootConstrainSelectedInstOperands,
     /*  292495 */   // GIR_Coverage, 10326,
     /*  292495 */   GIR_EraseRootFromParent_Done,
     /*  292496 */ // Label 4332: @292496
     /*  292496 */ GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(292554), // Rule ID 10327 //
     /*  292501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  292504 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292530 */   // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292530 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292533 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292545 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292548 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292552 */   GIR_RootConstrainSelectedInstOperands,
     /*  292553 */   // GIR_Coverage, 10327,
     /*  292553 */   GIR_EraseRootFromParent_Done,
     /*  292554 */ // Label 4333: @292554
     /*  292554 */ GIM_Try, /*On fail goto*//*Label 4334*/ GIMT_Encode4(292612), // Rule ID 10328 //
     /*  292559 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  292562 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292565 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292577 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292581 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292588 */   // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292588 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292591 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292606 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292610 */   GIR_RootConstrainSelectedInstOperands,
     /*  292611 */   // GIR_Coverage, 10328,
     /*  292611 */   GIR_EraseRootFromParent_Done,
     /*  292612 */ // Label 4334: @292612
     /*  292612 */ GIM_Try, /*On fail goto*//*Label 4335*/ GIMT_Encode4(292670), // Rule ID 10329 //
     /*  292617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  292620 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292623 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292635 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292639 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292646 */   // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292661 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292664 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292668 */   GIR_RootConstrainSelectedInstOperands,
     /*  292669 */   // GIR_Coverage, 10329,
     /*  292669 */   GIR_EraseRootFromParent_Done,
     /*  292670 */ // Label 4335: @292670
     /*  292670 */ GIM_Try, /*On fail goto*//*Label 4336*/ GIMT_Encode4(292728), // Rule ID 10330 //
     /*  292675 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  292678 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292681 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  292689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  292693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292697 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  292704 */   // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  292704 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  292707 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  292709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  292714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  292719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  292722 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292726 */   GIR_RootConstrainSelectedInstOperands,
     /*  292727 */   // GIR_Coverage, 10330,
     /*  292727 */   GIR_EraseRootFromParent_Done,
     /*  292728 */ // Label 4336: @292728
     /*  292728 */ GIM_Reject,
     /*  292729 */ // Label 1135: @292729
     /*  292729 */ GIM_Try, /*On fail goto*//*Label 4337*/ GIMT_Encode4(294404),
     /*  292734 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  292737 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  292741 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  292745 */   GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(292803), // Rule ID 9059 //
     /*  292750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  292753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  292757 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292761 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  292765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  292772 */     // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  292772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  292775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  292777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  292782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  292787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  292792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  292797 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292801 */     GIR_RootConstrainSelectedInstOperands,
     /*  292802 */     // GIR_Coverage, 9059,
     /*  292802 */     GIR_EraseRootFromParent_Done,
     /*  292803 */   // Label 4338: @292803
     /*  292803 */   GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(292861), // Rule ID 9076 //
     /*  292808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  292811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  292815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292819 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  292823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  292830 */     // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  292830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  292833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  292835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  292840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  292845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  292850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  292855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292859 */     GIR_RootConstrainSelectedInstOperands,
     /*  292860 */     // GIR_Coverage, 9076,
     /*  292860 */     GIR_EraseRootFromParent_Done,
     /*  292861 */   // Label 4339: @292861
     /*  292861 */   GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(292915), // Rule ID 9064 //
     /*  292866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  292869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  292873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  292884 */     // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  292884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  292887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  292889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  292894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  292899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  292904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  292909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292913 */     GIR_RootConstrainSelectedInstOperands,
     /*  292914 */     // GIR_Coverage, 9064,
     /*  292914 */     GIR_EraseRootFromParent_Done,
     /*  292915 */   // Label 4340: @292915
     /*  292915 */   GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(292969), // Rule ID 9081 //
     /*  292920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  292923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  292927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  292938 */     // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  292938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  292941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  292943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  292948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  292953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  292958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  292963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  292967 */     GIR_RootConstrainSelectedInstOperands,
     /*  292968 */     // GIR_Coverage, 9081,
     /*  292968 */     GIR_EraseRootFromParent_Done,
     /*  292969 */   // Label 4341: @292969
     /*  292969 */   GIM_Try, /*On fail goto*//*Label 4342*/ GIMT_Encode4(293023), // Rule ID 9070 //
     /*  292974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  292977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  292981 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  292985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  292992 */     // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  292992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  292995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  292997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  293012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  293017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293021 */     GIR_RootConstrainSelectedInstOperands,
     /*  293022 */     // GIR_Coverage, 9070,
     /*  293022 */     GIR_EraseRootFromParent_Done,
     /*  293023 */   // Label 4342: @293023
     /*  293023 */   GIM_Try, /*On fail goto*//*Label 4343*/ GIMT_Encode4(293077), // Rule ID 9087 //
     /*  293028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  293031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  293046 */     // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  293046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  293049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  293066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  293071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293075 */     GIR_RootConstrainSelectedInstOperands,
     /*  293076 */     // GIR_Coverage, 9087,
     /*  293076 */     GIR_EraseRootFromParent_Done,
     /*  293077 */   // Label 4343: @293077
     /*  293077 */   GIM_Try, /*On fail goto*//*Label 4344*/ GIMT_Encode4(293128), // Rule ID 9055 //
     /*  293082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  293085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293089 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293093 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  293104 */     // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  293107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293126 */     GIR_RootConstrainSelectedInstOperands,
     /*  293127 */     // GIR_Coverage, 9055,
     /*  293127 */     GIR_EraseRootFromParent_Done,
     /*  293128 */   // Label 4344: @293128
     /*  293128 */   GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(293179), // Rule ID 9056 //
     /*  293133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  293136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293144 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  293155 */     // (ld:{ *:[v4i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  293158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293177 */     GIR_RootConstrainSelectedInstOperands,
     /*  293178 */     // GIR_Coverage, 9056,
     /*  293178 */     GIR_EraseRootFromParent_Done,
     /*  293179 */   // Label 4345: @293179
     /*  293179 */   GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(293230), // Rule ID 9072 //
     /*  293184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  293187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293195 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  293206 */     // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  293209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293228 */     GIR_RootConstrainSelectedInstOperands,
     /*  293229 */     // GIR_Coverage, 9072,
     /*  293229 */     GIR_EraseRootFromParent_Done,
     /*  293230 */   // Label 4346: @293230
     /*  293230 */   GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(293281), // Rule ID 9073 //
     /*  293235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  293238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293246 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  293257 */     // (ld:{ *:[v4f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  293260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293279 */     GIR_RootConstrainSelectedInstOperands,
     /*  293280 */     // GIR_Coverage, 9073,
     /*  293280 */     GIR_EraseRootFromParent_Done,
     /*  293281 */   // Label 4347: @293281
     /*  293281 */   GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(293328), // Rule ID 9061 //
     /*  293286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  293289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  293304 */     // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  293307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293326 */     GIR_RootConstrainSelectedInstOperands,
     /*  293327 */     // GIR_Coverage, 9061,
     /*  293327 */     GIR_EraseRootFromParent_Done,
     /*  293328 */   // Label 4348: @293328
     /*  293328 */   GIM_Try, /*On fail goto*//*Label 4349*/ GIMT_Encode4(293375), // Rule ID 9078 //
     /*  293333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  293336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  293351 */     // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  293354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293369 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293373 */     GIR_RootConstrainSelectedInstOperands,
     /*  293374 */     // GIR_Coverage, 9078,
     /*  293374 */     GIR_EraseRootFromParent_Done,
     /*  293375 */   // Label 4349: @293375
     /*  293375 */   GIM_Try, /*On fail goto*//*Label 4350*/ GIMT_Encode4(293419), // Rule ID 9066 //
     /*  293380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293384 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  293395 */     // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  293398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293413 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293417 */     GIR_RootConstrainSelectedInstOperands,
     /*  293418 */     // GIR_Coverage, 9066,
     /*  293418 */     GIR_EraseRootFromParent_Done,
     /*  293419 */   // Label 4350: @293419
     /*  293419 */   GIM_Try, /*On fail goto*//*Label 4351*/ GIMT_Encode4(293466), // Rule ID 9067 //
     /*  293424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  293427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  293442 */     // (ld:{ *:[v4i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  293445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293464 */     GIR_RootConstrainSelectedInstOperands,
     /*  293465 */     // GIR_Coverage, 9067,
     /*  293465 */     GIR_EraseRootFromParent_Done,
     /*  293466 */   // Label 4351: @293466
     /*  293466 */   GIM_Try, /*On fail goto*//*Label 4352*/ GIMT_Encode4(293510), // Rule ID 9083 //
     /*  293471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  293486 */     // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  293489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293508 */     GIR_RootConstrainSelectedInstOperands,
     /*  293509 */     // GIR_Coverage, 9083,
     /*  293509 */     GIR_EraseRootFromParent_Done,
     /*  293510 */   // Label 4352: @293510
     /*  293510 */   GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(293557), // Rule ID 9084 //
     /*  293515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  293518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  293533 */     // (ld:{ *:[v4f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  293533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  293536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  293548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293555 */     GIR_RootConstrainSelectedInstOperands,
     /*  293556 */     // GIR_Coverage, 9084,
     /*  293556 */     GIR_EraseRootFromParent_Done,
     /*  293557 */   // Label 4353: @293557
     /*  293557 */   GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(293608), // Rule ID 9057 //
     /*  293562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  293565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293573 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293584 */     // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  293584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  293587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293606 */     GIR_RootConstrainSelectedInstOperands,
     /*  293607 */     // GIR_Coverage, 9057,
     /*  293607 */     GIR_EraseRootFromParent_Done,
     /*  293608 */   // Label 4354: @293608
     /*  293608 */   GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(293664), // Rule ID 9058 //
     /*  293613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  293616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293624 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293635 */     // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  293635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  293638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  293658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293662 */     GIR_RootConstrainSelectedInstOperands,
     /*  293663 */     // GIR_Coverage, 9058,
     /*  293663 */     GIR_EraseRootFromParent_Done,
     /*  293664 */   // Label 4355: @293664
     /*  293664 */   GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(293715), // Rule ID 9074 //
     /*  293669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  293672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293680 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293691 */     // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  293691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  293694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293713 */     GIR_RootConstrainSelectedInstOperands,
     /*  293714 */     // GIR_Coverage, 9074,
     /*  293714 */     GIR_EraseRootFromParent_Done,
     /*  293715 */   // Label 4356: @293715
     /*  293715 */   GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(293771), // Rule ID 9075 //
     /*  293720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  293723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293731 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293735 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293742 */     // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  293742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  293745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  293765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293769 */     GIR_RootConstrainSelectedInstOperands,
     /*  293770 */     // GIR_Coverage, 9075,
     /*  293770 */     GIR_EraseRootFromParent_Done,
     /*  293771 */   // Label 4357: @293771
     /*  293771 */   GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(293814), // Rule ID 9060 //
     /*  293776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  293779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293783 */     // MIs[0] sbase
     /*  293783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  293787 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  293791 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293795 */     // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  293795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  293798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293800 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  293802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293808 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293812 */     GIR_RootConstrainSelectedInstOperands,
     /*  293813 */     // GIR_Coverage, 9060,
     /*  293813 */     GIR_EraseRootFromParent_Done,
     /*  293814 */   // Label 4358: @293814
     /*  293814 */   GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(293857), // Rule ID 9077 //
     /*  293819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  293822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293826 */     // MIs[0] sbase
     /*  293826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  293830 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  293834 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  293838 */     // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  293838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  293841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293843 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  293845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293855 */     GIR_RootConstrainSelectedInstOperands,
     /*  293856 */     // GIR_Coverage, 9077,
     /*  293856 */     GIR_EraseRootFromParent_Done,
     /*  293857 */   // Label 4359: @293857
     /*  293857 */   GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(293904), // Rule ID 9062 //
     /*  293862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  293865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293880 */     // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  293880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec),
     /*  293883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293902 */     GIR_RootConstrainSelectedInstOperands,
     /*  293903 */     // GIR_Coverage, 9062,
     /*  293903 */     GIR_EraseRootFromParent_Done,
     /*  293904 */   // Label 4360: @293904
     /*  293904 */   GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(293956), // Rule ID 9063 //
     /*  293909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  293912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293927 */     // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  293927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  293930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  293950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  293954 */     GIR_RootConstrainSelectedInstOperands,
     /*  293955 */     // GIR_Coverage, 9063,
     /*  293955 */     GIR_EraseRootFromParent_Done,
     /*  293956 */   // Label 4361: @293956
     /*  293956 */   GIM_Try, /*On fail goto*//*Label 4362*/ GIMT_Encode4(294003), // Rule ID 9079 //
     /*  293961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  293964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  293968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  293972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  293979 */     // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  293979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec),
     /*  293982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  293984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  293989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  293994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  293997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294001 */     GIR_RootConstrainSelectedInstOperands,
     /*  294002 */     // GIR_Coverage, 9079,
     /*  294002 */     GIR_EraseRootFromParent_Done,
     /*  294003 */   // Label 4362: @294003
     /*  294003 */   GIM_Try, /*On fail goto*//*Label 4363*/ GIMT_Encode4(294055), // Rule ID 9080 //
     /*  294008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  294011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  294026 */     // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  294026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  294029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  294049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294053 */     GIR_RootConstrainSelectedInstOperands,
     /*  294054 */     // GIR_Coverage, 9080,
     /*  294054 */     GIR_EraseRootFromParent_Done,
     /*  294055 */   // Label 4363: @294055
     /*  294055 */   GIM_Try, /*On fail goto*//*Label 4364*/ GIMT_Encode4(294094), // Rule ID 9065 //
     /*  294060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  294063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294067 */     // MIs[0] sbase
     /*  294067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  294071 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  294075 */     // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  294075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  294078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294080 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  294082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294088 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294092 */     GIR_RootConstrainSelectedInstOperands,
     /*  294093 */     // GIR_Coverage, 9065,
     /*  294093 */     GIR_EraseRootFromParent_Done,
     /*  294094 */   // Label 4364: @294094
     /*  294094 */   GIM_Try, /*On fail goto*//*Label 4365*/ GIMT_Encode4(294133), // Rule ID 9082 //
     /*  294099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  294102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294106 */     // MIs[0] sbase
     /*  294106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  294110 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  294114 */     // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  294114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  294117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294119 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  294121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294131 */     GIR_RootConstrainSelectedInstOperands,
     /*  294132 */     // GIR_Coverage, 9082,
     /*  294132 */     GIR_EraseRootFromParent_Done,
     /*  294133 */   // Label 4365: @294133
     /*  294133 */   GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(294180), // Rule ID 9068 //
     /*  294138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  294141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294145 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294149 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  294156 */     // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  294156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  294159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294178 */     GIR_RootConstrainSelectedInstOperands,
     /*  294179 */     // GIR_Coverage, 9068,
     /*  294179 */     GIR_EraseRootFromParent_Done,
     /*  294180 */   // Label 4366: @294180
     /*  294180 */   GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(294232), // Rule ID 9069 //
     /*  294185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  294188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  294203 */     // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  294203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  294206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  294226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294230 */     GIR_RootConstrainSelectedInstOperands,
     /*  294231 */     // GIR_Coverage, 9069,
     /*  294231 */     GIR_EraseRootFromParent_Done,
     /*  294232 */   // Label 4367: @294232
     /*  294232 */   GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(294279), // Rule ID 9085 //
     /*  294237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  294240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  294255 */     // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  294255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  294258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294277 */     GIR_RootConstrainSelectedInstOperands,
     /*  294278 */     // GIR_Coverage, 9085,
     /*  294278 */     GIR_EraseRootFromParent_Done,
     /*  294279 */   // Label 4368: @294279
     /*  294279 */   GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(294331), // Rule ID 9086 //
     /*  294284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  294287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  294302 */     // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  294302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  294305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  294325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294329 */     GIR_RootConstrainSelectedInstOperands,
     /*  294330 */     // GIR_Coverage, 9086,
     /*  294330 */     GIR_EraseRootFromParent_Done,
     /*  294331 */   // Label 4369: @294331
     /*  294331 */   GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(294367), // Rule ID 9071 //
     /*  294336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294340 */     // MIs[0] sbase
     /*  294340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  294344 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  294348 */     // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  294348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  294351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294353 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  294355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294365 */     GIR_RootConstrainSelectedInstOperands,
     /*  294366 */     // GIR_Coverage, 9071,
     /*  294366 */     GIR_EraseRootFromParent_Done,
     /*  294367 */   // Label 4370: @294367
     /*  294367 */   GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(294403), // Rule ID 9088 //
     /*  294372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  294376 */     // MIs[0] sbase
     /*  294376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  294380 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  294384 */     // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  294384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  294387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294389 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  294391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294401 */     GIR_RootConstrainSelectedInstOperands,
     /*  294402 */     // GIR_Coverage, 9088,
     /*  294402 */     GIR_EraseRootFromParent_Done,
     /*  294403 */   // Label 4371: @294403
     /*  294403 */   GIM_Reject,
     /*  294404 */ // Label 4337: @294404
     /*  294404 */ GIM_Reject,
     /*  294405 */ // Label 1136: @294405
     /*  294405 */ GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(306474),
     /*  294410 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  294413 */   GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(294479), // Rule ID 8991 //
     /*  294418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  294421 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294433 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294437 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  294441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  294448 */     // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  294448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  294451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  294468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  294473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294477 */     GIR_RootConstrainSelectedInstOperands,
     /*  294478 */     // GIR_Coverage, 8991,
     /*  294478 */     GIR_EraseRootFromParent_Done,
     /*  294479 */   // Label 4373: @294479
     /*  294479 */   GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(294545), // Rule ID 9008 //
     /*  294484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  294487 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294499 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294503 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  294507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  294514 */     // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  294514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  294517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  294534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  294539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294543 */     GIR_RootConstrainSelectedInstOperands,
     /*  294544 */     // GIR_Coverage, 9008,
     /*  294544 */     GIR_EraseRootFromParent_Done,
     /*  294545 */   // Label 4374: @294545
     /*  294545 */   GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(294607), // Rule ID 8996 //
     /*  294550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  294553 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294565 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  294576 */     // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  294576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  294579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  294596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  294601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294605 */     GIR_RootConstrainSelectedInstOperands,
     /*  294606 */     // GIR_Coverage, 8996,
     /*  294606 */     GIR_EraseRootFromParent_Done,
     /*  294607 */   // Label 4375: @294607
     /*  294607 */   GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(294669), // Rule ID 9013 //
     /*  294612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  294615 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294623 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294627 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  294638 */     // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  294638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  294641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  294658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  294663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294667 */     GIR_RootConstrainSelectedInstOperands,
     /*  294668 */     // GIR_Coverage, 9013,
     /*  294668 */     GIR_EraseRootFromParent_Done,
     /*  294669 */   // Label 4376: @294669
     /*  294669 */   GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(294731), // Rule ID 9002 //
     /*  294674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  294677 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294689 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  294700 */     // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  294700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  294703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  294720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  294725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294729 */     GIR_RootConstrainSelectedInstOperands,
     /*  294730 */     // GIR_Coverage, 9002,
     /*  294730 */     GIR_EraseRootFromParent_Done,
     /*  294731 */   // Label 4377: @294731
     /*  294731 */   GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(294793), // Rule ID 9019 //
     /*  294736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  294739 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294751 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  294762 */     // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  294762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  294765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  294777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  294782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  294787 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294791 */     GIR_RootConstrainSelectedInstOperands,
     /*  294792 */     // GIR_Coverage, 9019,
     /*  294792 */     GIR_EraseRootFromParent_Done,
     /*  294793 */   // Label 4378: @294793
     /*  294793 */   GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(294852), // Rule ID 8987 //
     /*  294798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  294801 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294813 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294817 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  294821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  294828 */     // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  294828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  294831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  294843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294850 */     GIR_RootConstrainSelectedInstOperands,
     /*  294851 */     // GIR_Coverage, 8987,
     /*  294851 */     GIR_EraseRootFromParent_Done,
     /*  294852 */   // Label 4379: @294852
     /*  294852 */   GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(294911), // Rule ID 8988 //
     /*  294857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  294860 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294872 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294876 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  294880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  294887 */     // (ld:{ *:[v8i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  294887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  294890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  294902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294909 */     GIR_RootConstrainSelectedInstOperands,
     /*  294910 */     // GIR_Coverage, 8988,
     /*  294910 */     GIR_EraseRootFromParent_Done,
     /*  294911 */   // Label 4380: @294911
     /*  294911 */   GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(294970), // Rule ID 9004 //
     /*  294916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  294919 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294931 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294935 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  294939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  294946 */     // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  294946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  294949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  294951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  294956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  294961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  294964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  294968 */     GIR_RootConstrainSelectedInstOperands,
     /*  294969 */     // GIR_Coverage, 9004,
     /*  294969 */     GIR_EraseRootFromParent_Done,
     /*  294970 */   // Label 4381: @294970
     /*  294970 */   GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(295029), // Rule ID 9005 //
     /*  294975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  294978 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  294982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  294986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  294990 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  294994 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  294998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  295005 */     // (ld:{ *:[v8f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  295005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  295008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  295010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  295015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295027 */     GIR_RootConstrainSelectedInstOperands,
     /*  295028 */     // GIR_Coverage, 9005,
     /*  295028 */     GIR_EraseRootFromParent_Done,
     /*  295029 */   // Label 4382: @295029
     /*  295029 */   GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(295084), // Rule ID 8993 //
     /*  295034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  295037 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  295045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295049 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  295053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  295060 */     // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  295060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  295063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  295065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  295070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295082 */     GIR_RootConstrainSelectedInstOperands,
     /*  295083 */     // GIR_Coverage, 8993,
     /*  295083 */     GIR_EraseRootFromParent_Done,
     /*  295084 */   // Label 4383: @295084
     /*  295084 */   GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(295139), // Rule ID 9010 //
     /*  295089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  295092 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  295100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295104 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  295108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  295115 */     // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  295115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  295118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  295120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  295125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295133 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295137 */     GIR_RootConstrainSelectedInstOperands,
     /*  295138 */     // GIR_Coverage, 9010,
     /*  295138 */     GIR_EraseRootFromParent_Done,
     /*  295139 */   // Label 4384: @295139
     /*  295139 */   GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(295199), // Rule ID 29903 //
     /*  295144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  295147 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295151 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295156 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295175 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295197 */     GIR_RootConstrainSelectedInstOperands,
     /*  295198 */     // GIR_Coverage, 29903,
     /*  295198 */     GIR_EraseRootFromParent_Done,
     /*  295199 */   // Label 4385: @295199
     /*  295199 */   GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(295259), // Rule ID 29904 //
     /*  295204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  295207 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295211 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295216 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295235 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295257 */     GIR_RootConstrainSelectedInstOperands,
     /*  295258 */     // GIR_Coverage, 29904,
     /*  295258 */     GIR_EraseRootFromParent_Done,
     /*  295259 */   // Label 4386: @295259
     /*  295259 */   GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(295319), // Rule ID 29905 //
     /*  295264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  295267 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295271 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295276 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295284 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295288 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295295 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295317 */     GIR_RootConstrainSelectedInstOperands,
     /*  295318 */     // GIR_Coverage, 29905,
     /*  295318 */     GIR_EraseRootFromParent_Done,
     /*  295319 */   // Label 4387: @295319
     /*  295319 */   GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(295379), // Rule ID 29906 //
     /*  295324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  295327 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295331 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295336 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295344 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295355 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295377 */     GIR_RootConstrainSelectedInstOperands,
     /*  295378 */     // GIR_Coverage, 29906,
     /*  295378 */     GIR_EraseRootFromParent_Done,
     /*  295379 */   // Label 4388: @295379
     /*  295379 */   GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(295439), // Rule ID 29907 //
     /*  295384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  295387 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295396 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295415 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295437 */     GIR_RootConstrainSelectedInstOperands,
     /*  295438 */     // GIR_Coverage, 29907,
     /*  295438 */     GIR_EraseRootFromParent_Done,
     /*  295439 */   // Label 4389: @295439
     /*  295439 */   GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(295499), // Rule ID 29923 //
     /*  295444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  295447 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295456 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295475 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295497 */     GIR_RootConstrainSelectedInstOperands,
     /*  295498 */     // GIR_Coverage, 29923,
     /*  295498 */     GIR_EraseRootFromParent_Done,
     /*  295499 */   // Label 4390: @295499
     /*  295499 */   GIM_Try, /*On fail goto*//*Label 4391*/ GIMT_Encode4(295559), // Rule ID 29924 //
     /*  295504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  295507 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295516 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295535 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295553 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295557 */     GIR_RootConstrainSelectedInstOperands,
     /*  295558 */     // GIR_Coverage, 29924,
     /*  295558 */     GIR_EraseRootFromParent_Done,
     /*  295559 */   // Label 4391: @295559
     /*  295559 */   GIM_Try, /*On fail goto*//*Label 4392*/ GIMT_Encode4(295619), // Rule ID 29925 //
     /*  295564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  295567 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295571 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295576 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295595 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295617 */     GIR_RootConstrainSelectedInstOperands,
     /*  295618 */     // GIR_Coverage, 29925,
     /*  295618 */     GIR_EraseRootFromParent_Done,
     /*  295619 */   // Label 4392: @295619
     /*  295619 */   GIM_Try, /*On fail goto*//*Label 4393*/ GIMT_Encode4(295679), // Rule ID 29926 //
     /*  295624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  295627 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295636 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295644 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295655 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295677 */     GIR_RootConstrainSelectedInstOperands,
     /*  295678 */     // GIR_Coverage, 29926,
     /*  295678 */     GIR_EraseRootFromParent_Done,
     /*  295679 */   // Label 4393: @295679
     /*  295679 */   GIM_Try, /*On fail goto*//*Label 4394*/ GIMT_Encode4(295739), // Rule ID 29927 //
     /*  295684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  295687 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295691 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295696 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  295700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295715 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295737 */     GIR_RootConstrainSelectedInstOperands,
     /*  295738 */     // GIR_Coverage, 29927,
     /*  295738 */     GIR_EraseRootFromParent_Done,
     /*  295739 */   // Label 4394: @295739
     /*  295739 */   GIM_Try, /*On fail goto*//*Label 4395*/ GIMT_Encode4(295804), // Rule ID 30243 //
     /*  295744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  295747 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295751 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295769 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  295773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295780 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295802 */     GIR_RootConstrainSelectedInstOperands,
     /*  295803 */     // GIR_Coverage, 30243,
     /*  295803 */     GIR_EraseRootFromParent_Done,
     /*  295804 */   // Label 4395: @295804
     /*  295804 */   GIM_Try, /*On fail goto*//*Label 4396*/ GIMT_Encode4(295869), // Rule ID 30244 //
     /*  295809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  295812 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295830 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295834 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  295838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295845 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295867 */     GIR_RootConstrainSelectedInstOperands,
     /*  295868 */     // GIR_Coverage, 30244,
     /*  295868 */     GIR_EraseRootFromParent_Done,
     /*  295869 */   // Label 4396: @295869
     /*  295869 */   GIM_Try, /*On fail goto*//*Label 4397*/ GIMT_Encode4(295934), // Rule ID 30245 //
     /*  295874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  295877 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295881 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295886 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295899 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  295903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295910 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295932 */     GIR_RootConstrainSelectedInstOperands,
     /*  295933 */     // GIR_Coverage, 30245,
     /*  295933 */     GIR_EraseRootFromParent_Done,
     /*  295934 */   // Label 4397: @295934
     /*  295934 */   GIM_Try, /*On fail goto*//*Label 4398*/ GIMT_Encode4(295999), // Rule ID 30246 //
     /*  295939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  295942 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  295946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  295956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  295960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  295964 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  295968 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  295975 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  295975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  295978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  295980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  295985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  295990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  295993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  295997 */     GIR_RootConstrainSelectedInstOperands,
     /*  295998 */     // GIR_Coverage, 30246,
     /*  295998 */     GIR_EraseRootFromParent_Done,
     /*  295999 */   // Label 4398: @295999
     /*  295999 */   GIM_Try, /*On fail goto*//*Label 4399*/ GIMT_Encode4(296064), // Rule ID 30247 //
     /*  296004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  296007 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296011 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296025 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296029 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  296033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296040 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  296043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296062 */     GIR_RootConstrainSelectedInstOperands,
     /*  296063 */     // GIR_Coverage, 30247,
     /*  296063 */     GIR_EraseRootFromParent_Done,
     /*  296064 */   // Label 4399: @296064
     /*  296064 */   GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(296129), // Rule ID 30263 //
     /*  296069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  296072 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296090 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296094 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  296098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296105 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  296108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296123 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296127 */     GIR_RootConstrainSelectedInstOperands,
     /*  296128 */     // GIR_Coverage, 30263,
     /*  296128 */     GIR_EraseRootFromParent_Done,
     /*  296129 */   // Label 4400: @296129
     /*  296129 */   GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(296194), // Rule ID 30264 //
     /*  296134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  296137 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296159 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  296163 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296170 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  296173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296192 */     GIR_RootConstrainSelectedInstOperands,
     /*  296193 */     // GIR_Coverage, 30264,
     /*  296193 */     GIR_EraseRootFromParent_Done,
     /*  296194 */   // Label 4401: @296194
     /*  296194 */   GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(296259), // Rule ID 30265 //
     /*  296199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  296202 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296206 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296211 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296224 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  296228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296235 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  296238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296257 */     GIR_RootConstrainSelectedInstOperands,
     /*  296258 */     // GIR_Coverage, 30265,
     /*  296258 */     GIR_EraseRootFromParent_Done,
     /*  296259 */   // Label 4402: @296259
     /*  296259 */   GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(296324), // Rule ID 30266 //
     /*  296264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  296267 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296271 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296289 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  296293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296300 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  296303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296322 */     GIR_RootConstrainSelectedInstOperands,
     /*  296323 */     // GIR_Coverage, 30266,
     /*  296323 */     GIR_EraseRootFromParent_Done,
     /*  296324 */   // Label 4403: @296324
     /*  296324 */   GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(296389), // Rule ID 30267 //
     /*  296329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  296332 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296341 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296354 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
     /*  296358 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296365 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
     /*  296368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296383 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296387 */     GIR_RootConstrainSelectedInstOperands,
     /*  296388 */     // GIR_Coverage, 30267,
     /*  296388 */     GIR_EraseRootFromParent_Done,
     /*  296389 */   // Label 4404: @296389
     /*  296389 */   GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(296441), // Rule ID 8998 //
     /*  296394 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  296402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296406 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  296410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  296417 */     // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  296417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  296420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  296422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  296427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296439 */     GIR_RootConstrainSelectedInstOperands,
     /*  296440 */     // GIR_Coverage, 8998,
     /*  296440 */     GIR_EraseRootFromParent_Done,
     /*  296441 */   // Label 4405: @296441
     /*  296441 */   GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(296496), // Rule ID 8999 //
     /*  296446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  296449 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  296457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296461 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  296465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  296472 */     // (ld:{ *:[v8i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  296472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  296475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  296477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  296482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296494 */     GIR_RootConstrainSelectedInstOperands,
     /*  296495 */     // GIR_Coverage, 8999,
     /*  296495 */     GIR_EraseRootFromParent_Done,
     /*  296496 */   // Label 4406: @296496
     /*  296496 */   GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(296548), // Rule ID 9015 //
     /*  296501 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  296509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296513 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  296517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  296524 */     // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  296524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  296527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  296529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  296534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296546 */     GIR_RootConstrainSelectedInstOperands,
     /*  296547 */     // GIR_Coverage, 9015,
     /*  296547 */     GIR_EraseRootFromParent_Done,
     /*  296548 */   // Label 4407: @296548
     /*  296548 */   GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(296603), // Rule ID 9016 //
     /*  296553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  296556 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  296560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  296564 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296568 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  296572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  296579 */     // (ld:{ *:[v8f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  296579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
     /*  296582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  296584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  296589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296601 */     GIR_RootConstrainSelectedInstOperands,
     /*  296602 */     // GIR_Coverage, 9016,
     /*  296602 */     GIR_EraseRootFromParent_Done,
     /*  296603 */   // Label 4408: @296603
     /*  296603 */   GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(296659), // Rule ID 29908 //
     /*  296608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  296611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296616 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296624 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296635 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296653 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296657 */     GIR_RootConstrainSelectedInstOperands,
     /*  296658 */     // GIR_Coverage, 29908,
     /*  296658 */     GIR_EraseRootFromParent_Done,
     /*  296659 */   // Label 4409: @296659
     /*  296659 */   GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(296715), // Rule ID 29909 //
     /*  296664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  296667 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296672 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296691 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296713 */     GIR_RootConstrainSelectedInstOperands,
     /*  296714 */     // GIR_Coverage, 29909,
     /*  296714 */     GIR_EraseRootFromParent_Done,
     /*  296715 */   // Label 4410: @296715
     /*  296715 */   GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(296771), // Rule ID 29910 //
     /*  296720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  296723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296728 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296747 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296769 */     GIR_RootConstrainSelectedInstOperands,
     /*  296770 */     // GIR_Coverage, 29910,
     /*  296770 */     GIR_EraseRootFromParent_Done,
     /*  296771 */   // Label 4411: @296771
     /*  296771 */   GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(296827), // Rule ID 29911 //
     /*  296776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  296779 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296784 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296803 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296825 */     GIR_RootConstrainSelectedInstOperands,
     /*  296826 */     // GIR_Coverage, 29911,
     /*  296826 */     GIR_EraseRootFromParent_Done,
     /*  296827 */   // Label 4412: @296827
     /*  296827 */   GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(296883), // Rule ID 29912 //
     /*  296832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  296835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296840 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296859 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296881 */     GIR_RootConstrainSelectedInstOperands,
     /*  296882 */     // GIR_Coverage, 29912,
     /*  296882 */     GIR_EraseRootFromParent_Done,
     /*  296883 */   // Label 4413: @296883
     /*  296883 */   GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(296939), // Rule ID 29928 //
     /*  296888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  296891 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296896 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296904 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296915 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296937 */     GIR_RootConstrainSelectedInstOperands,
     /*  296938 */     // GIR_Coverage, 29928,
     /*  296938 */     GIR_EraseRootFromParent_Done,
     /*  296939 */   // Label 4414: @296939
     /*  296939 */   GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(296995), // Rule ID 29929 //
     /*  296944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  296947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  296952 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  296956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  296960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  296964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  296971 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  296971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  296974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  296976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  296981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  296986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  296989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  296993 */     GIR_RootConstrainSelectedInstOperands,
     /*  296994 */     // GIR_Coverage, 29929,
     /*  296994 */     GIR_EraseRootFromParent_Done,
     /*  296995 */   // Label 4415: @296995
     /*  296995 */   GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(297051), // Rule ID 29930 //
     /*  297000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  297003 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297008 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  297012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297027 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297049 */     GIR_RootConstrainSelectedInstOperands,
     /*  297050 */     // GIR_Coverage, 29930,
     /*  297050 */     GIR_EraseRootFromParent_Done,
     /*  297051 */   // Label 4416: @297051
     /*  297051 */   GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(297107), // Rule ID 29931 //
     /*  297056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  297059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297064 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  297068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297083 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297105 */     GIR_RootConstrainSelectedInstOperands,
     /*  297106 */     // GIR_Coverage, 29931,
     /*  297106 */     GIR_EraseRootFromParent_Done,
     /*  297107 */   // Label 4417: @297107
     /*  297107 */   GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(297163), // Rule ID 29932 //
     /*  297112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  297115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297120 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  297124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297139 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297161 */     GIR_RootConstrainSelectedInstOperands,
     /*  297162 */     // GIR_Coverage, 29932,
     /*  297162 */     GIR_EraseRootFromParent_Done,
     /*  297163 */   // Label 4418: @297163
     /*  297163 */   GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(297224), // Rule ID 30248 //
     /*  297168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  297171 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297176 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297189 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297200 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297222 */     GIR_RootConstrainSelectedInstOperands,
     /*  297223 */     // GIR_Coverage, 30248,
     /*  297223 */     GIR_EraseRootFromParent_Done,
     /*  297224 */   // Label 4419: @297224
     /*  297224 */   GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(297285), // Rule ID 30249 //
     /*  297229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  297232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297237 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297250 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297261 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297283 */     GIR_RootConstrainSelectedInstOperands,
     /*  297284 */     // GIR_Coverage, 30249,
     /*  297284 */     GIR_EraseRootFromParent_Done,
     /*  297285 */   // Label 4420: @297285
     /*  297285 */   GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(297346), // Rule ID 30250 //
     /*  297290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  297293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297311 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297322 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297344 */     GIR_RootConstrainSelectedInstOperands,
     /*  297345 */     // GIR_Coverage, 30250,
     /*  297345 */     GIR_EraseRootFromParent_Done,
     /*  297346 */   // Label 4421: @297346
     /*  297346 */   GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(297407), // Rule ID 30251 //
     /*  297351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  297354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297359 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297372 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297383 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297405 */     GIR_RootConstrainSelectedInstOperands,
     /*  297406 */     // GIR_Coverage, 30251,
     /*  297406 */     GIR_EraseRootFromParent_Done,
     /*  297407 */   // Label 4422: @297407
     /*  297407 */   GIM_Try, /*On fail goto*//*Label 4423*/ GIMT_Encode4(297468), // Rule ID 30252 //
     /*  297412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  297415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297420 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297433 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297444 */     // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297466 */     GIR_RootConstrainSelectedInstOperands,
     /*  297467 */     // GIR_Coverage, 30252,
     /*  297467 */     GIR_EraseRootFromParent_Done,
     /*  297468 */   // Label 4423: @297468
     /*  297468 */   GIM_Try, /*On fail goto*//*Label 4424*/ GIMT_Encode4(297529), // Rule ID 30268 //
     /*  297473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  297476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297481 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297494 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297498 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297505 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297523 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297527 */     GIR_RootConstrainSelectedInstOperands,
     /*  297528 */     // GIR_Coverage, 30268,
     /*  297528 */     GIR_EraseRootFromParent_Done,
     /*  297529 */   // Label 4424: @297529
     /*  297529 */   GIM_Try, /*On fail goto*//*Label 4425*/ GIMT_Encode4(297590), // Rule ID 30269 //
     /*  297534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  297537 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297555 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297559 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297566 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297588 */     GIR_RootConstrainSelectedInstOperands,
     /*  297589 */     // GIR_Coverage, 30269,
     /*  297589 */     GIR_EraseRootFromParent_Done,
     /*  297590 */   // Label 4425: @297590
     /*  297590 */   GIM_Try, /*On fail goto*//*Label 4426*/ GIMT_Encode4(297651), // Rule ID 30270 //
     /*  297595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  297598 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297616 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297627 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297645 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297649 */     GIR_RootConstrainSelectedInstOperands,
     /*  297650 */     // GIR_Coverage, 30270,
     /*  297650 */     GIR_EraseRootFromParent_Done,
     /*  297651 */   // Label 4426: @297651
     /*  297651 */   GIM_Try, /*On fail goto*//*Label 4427*/ GIMT_Encode4(297712), // Rule ID 30271 //
     /*  297656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  297659 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297664 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297677 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297688 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297710 */     GIR_RootConstrainSelectedInstOperands,
     /*  297711 */     // GIR_Coverage, 30271,
     /*  297711 */     GIR_EraseRootFromParent_Done,
     /*  297712 */   // Label 4427: @297712
     /*  297712 */   GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(297773), // Rule ID 30272 //
     /*  297717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  297720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  297730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  297734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297738 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
     /*  297742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  297749 */     // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  297749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
     /*  297752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  297754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  297759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  297764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297771 */     GIR_RootConstrainSelectedInstOperands,
     /*  297772 */     // GIR_Coverage, 30272,
     /*  297772 */     GIR_EraseRootFromParent_Done,
     /*  297773 */   // Label 4428: @297773
     /*  297773 */   GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(297832), // Rule ID 8989 //
     /*  297778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  297781 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  297785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  297789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297793 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  297797 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  297801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  297808 */     // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  297808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  297811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  297813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  297818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  297823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297830 */     GIR_RootConstrainSelectedInstOperands,
     /*  297831 */     // GIR_Coverage, 8989,
     /*  297831 */     GIR_EraseRootFromParent_Done,
     /*  297832 */   // Label 4429: @297832
     /*  297832 */   GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(297896), // Rule ID 8990 //
     /*  297837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  297840 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  297844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  297848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297852 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  297856 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  297860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  297867 */     // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  297867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  297870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  297872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  297877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  297882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  297890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297894 */     GIR_RootConstrainSelectedInstOperands,
     /*  297895 */     // GIR_Coverage, 8990,
     /*  297895 */     GIR_EraseRootFromParent_Done,
     /*  297896 */   // Label 4430: @297896
     /*  297896 */   GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(297955), // Rule ID 9006 //
     /*  297901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  297904 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  297908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  297912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297916 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  297920 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  297924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  297931 */     // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  297931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  297934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  297936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  297941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  297946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  297949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  297953 */     GIR_RootConstrainSelectedInstOperands,
     /*  297954 */     // GIR_Coverage, 9006,
     /*  297954 */     GIR_EraseRootFromParent_Done,
     /*  297955 */   // Label 4431: @297955
     /*  297955 */   GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(298019), // Rule ID 9007 //
     /*  297960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  297963 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  297967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  297971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  297975 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  297979 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  297983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  297990 */     // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  297990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  297993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  297995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  298013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298017 */     GIR_RootConstrainSelectedInstOperands,
     /*  298018 */     // GIR_Coverage, 9007,
     /*  298018 */     GIR_EraseRootFromParent_Done,
     /*  298019 */   // Label 4432: @298019
     /*  298019 */   GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(298070), // Rule ID 8992 //
     /*  298024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  298027 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298035 */     // MIs[0] sbase
     /*  298035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  298039 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  298043 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298047 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  298051 */     // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  298051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  298054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298056 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  298058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298068 */     GIR_RootConstrainSelectedInstOperands,
     /*  298069 */     // GIR_Coverage, 8992,
     /*  298069 */     GIR_EraseRootFromParent_Done,
     /*  298070 */   // Label 4433: @298070
     /*  298070 */   GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(298121), // Rule ID 9009 //
     /*  298075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  298078 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298086 */     // MIs[0] sbase
     /*  298086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  298090 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  298094 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298098 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  298102 */     // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  298102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  298105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298107 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  298109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298119 */     GIR_RootConstrainSelectedInstOperands,
     /*  298120 */     // GIR_Coverage, 9009,
     /*  298120 */     GIR_EraseRootFromParent_Done,
     /*  298121 */   // Label 4434: @298121
     /*  298121 */   GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(298176), // Rule ID 8994 //
     /*  298126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  298129 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298141 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298152 */     // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  298152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec),
     /*  298155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298174 */     GIR_RootConstrainSelectedInstOperands,
     /*  298175 */     // GIR_Coverage, 8994,
     /*  298175 */     GIR_EraseRootFromParent_Done,
     /*  298176 */   // Label 4435: @298176
     /*  298176 */   GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(298236), // Rule ID 8995 //
     /*  298181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  298184 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298196 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298200 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298207 */     // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  298207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  298210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  298230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298234 */     GIR_RootConstrainSelectedInstOperands,
     /*  298235 */     // GIR_Coverage, 8995,
     /*  298235 */     GIR_EraseRootFromParent_Done,
     /*  298236 */   // Label 4436: @298236
     /*  298236 */   GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(298291), // Rule ID 9011 //
     /*  298241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  298244 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298256 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298267 */     // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  298267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec),
     /*  298270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298282 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298285 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298289 */     GIR_RootConstrainSelectedInstOperands,
     /*  298290 */     // GIR_Coverage, 9011,
     /*  298290 */     GIR_EraseRootFromParent_Done,
     /*  298291 */   // Label 4437: @298291
     /*  298291 */   GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(298351), // Rule ID 9012 //
     /*  298296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  298299 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298311 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298322 */     // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  298322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec),
     /*  298325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  298345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298349 */     GIR_RootConstrainSelectedInstOperands,
     /*  298350 */     // GIR_Coverage, 9012,
     /*  298350 */     GIR_EraseRootFromParent_Done,
     /*  298351 */   // Label 4438: @298351
     /*  298351 */   GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(298398), // Rule ID 8997 //
     /*  298356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  298359 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298367 */     // MIs[0] sbase
     /*  298367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  298371 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  298375 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298379 */     // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  298379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  298382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298384 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  298386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298396 */     GIR_RootConstrainSelectedInstOperands,
     /*  298397 */     // GIR_Coverage, 8997,
     /*  298397 */     GIR_EraseRootFromParent_Done,
     /*  298398 */   // Label 4439: @298398
     /*  298398 */   GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(298445), // Rule ID 9014 //
     /*  298403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  298406 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298414 */     // MIs[0] sbase
     /*  298414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  298418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  298422 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298426 */     // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ec:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  298426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec),
     /*  298429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298431 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  298433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298443 */     GIR_RootConstrainSelectedInstOperands,
     /*  298444 */     // GIR_Coverage, 9014,
     /*  298444 */     GIR_EraseRootFromParent_Done,
     /*  298445 */   // Label 4440: @298445
     /*  298445 */   GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(298500), // Rule ID 9000 //
     /*  298450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  298453 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298465 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298476 */     // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  298476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  298479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298498 */     GIR_RootConstrainSelectedInstOperands,
     /*  298499 */     // GIR_Coverage, 9000,
     /*  298499 */     GIR_EraseRootFromParent_Done,
     /*  298500 */   // Label 4441: @298500
     /*  298500 */   GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(298560), // Rule ID 9001 //
     /*  298505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  298508 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298520 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298531 */     // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  298531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  298534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  298554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298558 */     GIR_RootConstrainSelectedInstOperands,
     /*  298559 */     // GIR_Coverage, 9001,
     /*  298559 */     GIR_EraseRootFromParent_Done,
     /*  298560 */   // Label 4442: @298560
     /*  298560 */   GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(298615), // Rule ID 9017 //
     /*  298565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  298568 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298576 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298580 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298591 */     // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  298591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
     /*  298594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298613 */     GIR_RootConstrainSelectedInstOperands,
     /*  298614 */     // GIR_Coverage, 9017,
     /*  298614 */     GIR_EraseRootFromParent_Done,
     /*  298615 */   // Label 4443: @298615
     /*  298615 */   GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(298675), // Rule ID 9018 //
     /*  298620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  298623 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298635 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  298646 */     // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  298646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
     /*  298649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  298656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  298661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  298669 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298673 */     GIR_RootConstrainSelectedInstOperands,
     /*  298674 */     // GIR_Coverage, 9018,
     /*  298674 */     GIR_EraseRootFromParent_Done,
     /*  298675 */   // Label 4444: @298675
     /*  298675 */   GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(298719), // Rule ID 9003 //
     /*  298680 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298688 */     // MIs[0] sbase
     /*  298688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  298692 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  298696 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298700 */     // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  298700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  298703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298705 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  298707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298717 */     GIR_RootConstrainSelectedInstOperands,
     /*  298718 */     // GIR_Coverage, 9003,
     /*  298718 */     GIR_EraseRootFromParent_Done,
     /*  298719 */   // Label 4445: @298719
     /*  298719 */   GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(298763), // Rule ID 9020 //
     /*  298724 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  298728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
     /*  298732 */     // MIs[0] sbase
     /*  298732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  298736 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  298740 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  298744 */     // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  298744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
     /*  298747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  298749 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  298751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  298757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298761 */     GIR_RootConstrainSelectedInstOperands,
     /*  298762 */     // GIR_Coverage, 9020,
     /*  298762 */     GIR_EraseRootFromParent_Done,
     /*  298763 */   // Label 4446: @298763
     /*  298763 */   GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(298822), // Rule ID 14707 //
     /*  298768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  298771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  298776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  298780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298784 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  298791 */     // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  298791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  298794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  298796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  298801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  298806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  298811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  298816 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298820 */     GIR_RootConstrainSelectedInstOperands,
     /*  298821 */     // GIR_Coverage, 14707,
     /*  298821 */     GIR_EraseRootFromParent_Done,
     /*  298822 */   // Label 4447: @298822
     /*  298822 */   GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(298881), // Rule ID 14708 //
     /*  298827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  298830 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  298835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  298839 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  298850 */     // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  298850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  298853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  298855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  298860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  298865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  298870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  298875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298879 */     GIR_RootConstrainSelectedInstOperands,
     /*  298880 */     // GIR_Coverage, 14708,
     /*  298880 */     GIR_EraseRootFromParent_Done,
     /*  298881 */   // Label 4448: @298881
     /*  298881 */   GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(298940), // Rule ID 14709 //
     /*  298886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  298889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  298894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  298898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  298909 */     // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  298909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  298912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  298914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  298919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  298924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  298929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  298934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298938 */     GIR_RootConstrainSelectedInstOperands,
     /*  298939 */     // GIR_Coverage, 14709,
     /*  298939 */     GIR_EraseRootFromParent_Done,
     /*  298940 */   // Label 4449: @298940
     /*  298940 */   GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(298999), // Rule ID 14710 //
     /*  298945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  298948 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  298953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  298957 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  298961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  298968 */     // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  298968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  298971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  298973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  298978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  298983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  298988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  298993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  298997 */     GIR_RootConstrainSelectedInstOperands,
     /*  298998 */     // GIR_Coverage, 14710,
     /*  298998 */     GIR_EraseRootFromParent_Done,
     /*  298999 */   // Label 4450: @298999
     /*  298999 */   GIM_Try, /*On fail goto*//*Label 4451*/ GIMT_Encode4(299058), // Rule ID 14711 //
     /*  299004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  299007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  299027 */     // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  299027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  299030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  299042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  299047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  299052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299056 */     GIR_RootConstrainSelectedInstOperands,
     /*  299057 */     // GIR_Coverage, 14711,
     /*  299057 */     GIR_EraseRootFromParent_Done,
     /*  299058 */   // Label 4451: @299058
     /*  299058 */   GIM_Try, /*On fail goto*//*Label 4452*/ GIMT_Encode4(299117), // Rule ID 14737 //
     /*  299063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  299066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  299086 */     // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  299086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  299089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  299101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  299106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  299111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299115 */     GIR_RootConstrainSelectedInstOperands,
     /*  299116 */     // GIR_Coverage, 14737,
     /*  299116 */     GIR_EraseRootFromParent_Done,
     /*  299117 */   // Label 4452: @299117
     /*  299117 */   GIM_Try, /*On fail goto*//*Label 4453*/ GIMT_Encode4(299176), // Rule ID 14738 //
     /*  299122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  299125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  299145 */     // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  299145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  299148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  299160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  299165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  299170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299174 */     GIR_RootConstrainSelectedInstOperands,
     /*  299175 */     // GIR_Coverage, 14738,
     /*  299175 */     GIR_EraseRootFromParent_Done,
     /*  299176 */   // Label 4453: @299176
     /*  299176 */   GIM_Try, /*On fail goto*//*Label 4454*/ GIMT_Encode4(299235), // Rule ID 14739 //
     /*  299181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  299184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  299204 */     // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  299204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  299207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  299219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  299224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  299229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299233 */     GIR_RootConstrainSelectedInstOperands,
     /*  299234 */     // GIR_Coverage, 14739,
     /*  299234 */     GIR_EraseRootFromParent_Done,
     /*  299235 */   // Label 4454: @299235
     /*  299235 */   GIM_Try, /*On fail goto*//*Label 4455*/ GIMT_Encode4(299294), // Rule ID 14740 //
     /*  299240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  299243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  299263 */     // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  299263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  299266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  299278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  299283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  299288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299292 */     GIR_RootConstrainSelectedInstOperands,
     /*  299293 */     // GIR_Coverage, 14740,
     /*  299293 */     GIR_EraseRootFromParent_Done,
     /*  299294 */   // Label 4455: @299294
     /*  299294 */   GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(299353), // Rule ID 14741 //
     /*  299299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  299302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  299322 */     // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  299322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
     /*  299325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  299337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  299342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  299347 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299351 */     GIR_RootConstrainSelectedInstOperands,
     /*  299352 */     // GIR_Coverage, 14741,
     /*  299352 */     GIR_EraseRootFromParent_Done,
     /*  299353 */   // Label 4456: @299353
     /*  299353 */   GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(299405), // Rule ID 14702 //
     /*  299358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  299361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299370 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299374 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299381 */     // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299399 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299403 */     GIR_RootConstrainSelectedInstOperands,
     /*  299404 */     // GIR_Coverage, 14702,
     /*  299404 */     GIR_EraseRootFromParent_Done,
     /*  299405 */   // Label 4457: @299405
     /*  299405 */   GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(299457), // Rule ID 14703 //
     /*  299410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  299413 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299433 */     // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299455 */     GIR_RootConstrainSelectedInstOperands,
     /*  299456 */     // GIR_Coverage, 14703,
     /*  299456 */     GIR_EraseRootFromParent_Done,
     /*  299457 */   // Label 4458: @299457
     /*  299457 */   GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(299509), // Rule ID 14704 //
     /*  299462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  299465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299485 */     // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299507 */     GIR_RootConstrainSelectedInstOperands,
     /*  299508 */     // GIR_Coverage, 14704,
     /*  299508 */     GIR_EraseRootFromParent_Done,
     /*  299509 */   // Label 4459: @299509
     /*  299509 */   GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(299561), // Rule ID 14705 //
     /*  299514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  299517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299537 */     // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299559 */     GIR_RootConstrainSelectedInstOperands,
     /*  299560 */     // GIR_Coverage, 14705,
     /*  299560 */     GIR_EraseRootFromParent_Done,
     /*  299561 */   // Label 4460: @299561
     /*  299561 */   GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(299613), // Rule ID 14706 //
     /*  299566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  299569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299589 */     // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299611 */     GIR_RootConstrainSelectedInstOperands,
     /*  299612 */     // GIR_Coverage, 14706,
     /*  299612 */     GIR_EraseRootFromParent_Done,
     /*  299613 */   // Label 4461: @299613
     /*  299613 */   GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(299665), // Rule ID 14732 //
     /*  299618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  299621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299630 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299641 */     // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299663 */     GIR_RootConstrainSelectedInstOperands,
     /*  299664 */     // GIR_Coverage, 14732,
     /*  299664 */     GIR_EraseRootFromParent_Done,
     /*  299665 */   // Label 4462: @299665
     /*  299665 */   GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(299717), // Rule ID 14733 //
     /*  299670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  299673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299693 */     // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299715 */     GIR_RootConstrainSelectedInstOperands,
     /*  299716 */     // GIR_Coverage, 14733,
     /*  299716 */     GIR_EraseRootFromParent_Done,
     /*  299717 */   // Label 4463: @299717
     /*  299717 */   GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(299769), // Rule ID 14734 //
     /*  299722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  299725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299745 */     // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299767 */     GIR_RootConstrainSelectedInstOperands,
     /*  299768 */     // GIR_Coverage, 14734,
     /*  299768 */     GIR_EraseRootFromParent_Done,
     /*  299769 */   // Label 4464: @299769
     /*  299769 */   GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(299821), // Rule ID 14735 //
     /*  299774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  299777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299797 */     // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299819 */     GIR_RootConstrainSelectedInstOperands,
     /*  299820 */     // GIR_Coverage, 14735,
     /*  299820 */     GIR_EraseRootFromParent_Done,
     /*  299821 */   // Label 4465: @299821
     /*  299821 */   GIM_Try, /*On fail goto*//*Label 4466*/ GIMT_Encode4(299873), // Rule ID 14736 //
     /*  299826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  299829 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299838 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  299849 */     // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  299849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
     /*  299852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  299859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299867 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299871 */     GIR_RootConstrainSelectedInstOperands,
     /*  299872 */     // GIR_Coverage, 14736,
     /*  299872 */     GIR_EraseRootFromParent_Done,
     /*  299873 */   // Label 4466: @299873
     /*  299873 */   GIM_Try, /*On fail goto*//*Label 4467*/ GIMT_Encode4(299925), // Rule ID 14697 //
     /*  299878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  299881 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299890 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  299901 */     // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  299901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  299904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299923 */     GIR_RootConstrainSelectedInstOperands,
     /*  299924 */     // GIR_Coverage, 14697,
     /*  299924 */     GIR_EraseRootFromParent_Done,
     /*  299925 */   // Label 4467: @299925
     /*  299925 */   GIM_Try, /*On fail goto*//*Label 4468*/ GIMT_Encode4(299977), // Rule ID 14698 //
     /*  299930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  299933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  299953 */     // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  299953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  299956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  299958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  299963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  299968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  299971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  299975 */     GIR_RootConstrainSelectedInstOperands,
     /*  299976 */     // GIR_Coverage, 14698,
     /*  299976 */     GIR_EraseRootFromParent_Done,
     /*  299977 */   // Label 4468: @299977
     /*  299977 */   GIM_Try, /*On fail goto*//*Label 4469*/ GIMT_Encode4(300029), // Rule ID 14699 //
     /*  299982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  299985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  299990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  299994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  299998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300005 */     // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300027 */     GIR_RootConstrainSelectedInstOperands,
     /*  300028 */     // GIR_Coverage, 14699,
     /*  300028 */     GIR_EraseRootFromParent_Done,
     /*  300029 */   // Label 4469: @300029
     /*  300029 */   GIM_Try, /*On fail goto*//*Label 4470*/ GIMT_Encode4(300081), // Rule ID 14700 //
     /*  300034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  300037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300050 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300057 */     // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300079 */     GIR_RootConstrainSelectedInstOperands,
     /*  300080 */     // GIR_Coverage, 14700,
     /*  300080 */     GIR_EraseRootFromParent_Done,
     /*  300081 */   // Label 4470: @300081
     /*  300081 */   GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(300133), // Rule ID 14701 //
     /*  300086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  300089 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300102 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300109 */     // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300131 */     GIR_RootConstrainSelectedInstOperands,
     /*  300132 */     // GIR_Coverage, 14701,
     /*  300132 */     GIR_EraseRootFromParent_Done,
     /*  300133 */   // Label 4471: @300133
     /*  300133 */   GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(300185), // Rule ID 14727 //
     /*  300138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  300141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300161 */     // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300183 */     GIR_RootConstrainSelectedInstOperands,
     /*  300184 */     // GIR_Coverage, 14727,
     /*  300184 */     GIR_EraseRootFromParent_Done,
     /*  300185 */   // Label 4472: @300185
     /*  300185 */   GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(300237), // Rule ID 14728 //
     /*  300190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  300193 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300206 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300213 */     // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300231 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300235 */     GIR_RootConstrainSelectedInstOperands,
     /*  300236 */     // GIR_Coverage, 14728,
     /*  300236 */     GIR_EraseRootFromParent_Done,
     /*  300237 */   // Label 4473: @300237
     /*  300237 */   GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(300289), // Rule ID 14729 //
     /*  300242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  300245 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300254 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300265 */     // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300287 */     GIR_RootConstrainSelectedInstOperands,
     /*  300288 */     // GIR_Coverage, 14729,
     /*  300288 */     GIR_EraseRootFromParent_Done,
     /*  300289 */   // Label 4474: @300289
     /*  300289 */   GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(300341), // Rule ID 14730 //
     /*  300294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  300297 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300306 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300310 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300317 */     // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300335 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300339 */     GIR_RootConstrainSelectedInstOperands,
     /*  300340 */     // GIR_Coverage, 14730,
     /*  300340 */     GIR_EraseRootFromParent_Done,
     /*  300341 */   // Label 4475: @300341
     /*  300341 */   GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(300393), // Rule ID 14731 //
     /*  300346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  300349 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  300354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  300369 */     // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  300369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
     /*  300372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  300374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  300379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  300384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300391 */     GIR_RootConstrainSelectedInstOperands,
     /*  300392 */     // GIR_Coverage, 14731,
     /*  300392 */     GIR_EraseRootFromParent_Done,
     /*  300393 */   // Label 4476: @300393
     /*  300393 */   GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(300460), // Rule ID 15828 //
     /*  300398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  300401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300423 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  300426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300458 */     GIR_RootConstrainSelectedInstOperands,
     /*  300459 */     // GIR_Coverage, 15828,
     /*  300459 */     GIR_EraseRootFromParent_Done,
     /*  300460 */   // Label 4477: @300460
     /*  300460 */   GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(300527), // Rule ID 15829 //
     /*  300465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  300468 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300490 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  300493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300525 */     GIR_RootConstrainSelectedInstOperands,
     /*  300526 */     // GIR_Coverage, 15829,
     /*  300526 */     GIR_EraseRootFromParent_Done,
     /*  300527 */   // Label 4478: @300527
     /*  300527 */   GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(300594), // Rule ID 15830 //
     /*  300532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  300535 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300557 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  300560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300592 */     GIR_RootConstrainSelectedInstOperands,
     /*  300593 */     // GIR_Coverage, 15830,
     /*  300593 */     GIR_EraseRootFromParent_Done,
     /*  300594 */   // Label 4479: @300594
     /*  300594 */   GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(300661), // Rule ID 15831 //
     /*  300599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  300602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300624 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  300627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300659 */     GIR_RootConstrainSelectedInstOperands,
     /*  300660 */     // GIR_Coverage, 15831,
     /*  300660 */     GIR_EraseRootFromParent_Done,
     /*  300661 */   // Label 4480: @300661
     /*  300661 */   GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(300728), // Rule ID 15832 //
     /*  300666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  300669 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300691 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  300694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300726 */     GIR_RootConstrainSelectedInstOperands,
     /*  300727 */     // GIR_Coverage, 15832,
     /*  300727 */     GIR_EraseRootFromParent_Done,
     /*  300728 */   // Label 4481: @300728
     /*  300728 */   GIM_Try, /*On fail goto*//*Label 4482*/ GIMT_Encode4(300795), // Rule ID 15838 //
     /*  300733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  300736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300758 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  300761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300783 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300793 */     GIR_RootConstrainSelectedInstOperands,
     /*  300794 */     // GIR_Coverage, 15838,
     /*  300794 */     GIR_EraseRootFromParent_Done,
     /*  300795 */   // Label 4482: @300795
     /*  300795 */   GIM_Try, /*On fail goto*//*Label 4483*/ GIMT_Encode4(300862), // Rule ID 15839 //
     /*  300800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  300803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300814 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300818 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300825 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  300828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300860 */     GIR_RootConstrainSelectedInstOperands,
     /*  300861 */     // GIR_Coverage, 15839,
     /*  300861 */     GIR_EraseRootFromParent_Done,
     /*  300862 */   // Label 4483: @300862
     /*  300862 */   GIM_Try, /*On fail goto*//*Label 4484*/ GIMT_Encode4(300929), // Rule ID 15840 //
     /*  300867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  300870 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300881 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300892 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  300895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300927 */     GIR_RootConstrainSelectedInstOperands,
     /*  300928 */     // GIR_Coverage, 15840,
     /*  300928 */     GIR_EraseRootFromParent_Done,
     /*  300929 */   // Label 4484: @300929
     /*  300929 */   GIM_Try, /*On fail goto*//*Label 4485*/ GIMT_Encode4(300996), // Rule ID 15841 //
     /*  300934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  300937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  300944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  300948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  300952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  300959 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  300959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  300962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  300964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  300969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  300974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  300979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  300984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  300990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  300994 */     GIR_RootConstrainSelectedInstOperands,
     /*  300995 */     // GIR_Coverage, 15841,
     /*  300995 */     GIR_EraseRootFromParent_Done,
     /*  300996 */   // Label 4485: @300996
     /*  300996 */   GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(301063), // Rule ID 15842 //
     /*  301001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  301004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301026 */     // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  301029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301061 */     GIR_RootConstrainSelectedInstOperands,
     /*  301062 */     // GIR_Coverage, 15842,
     /*  301062 */     GIR_EraseRootFromParent_Done,
     /*  301063 */   // Label 4486: @301063
     /*  301063 */   GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(301130), // Rule ID 15848 //
     /*  301068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  301071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301093 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  301096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301128 */     GIR_RootConstrainSelectedInstOperands,
     /*  301129 */     // GIR_Coverage, 15848,
     /*  301129 */     GIR_EraseRootFromParent_Done,
     /*  301130 */   // Label 4487: @301130
     /*  301130 */   GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(301197), // Rule ID 15849 //
     /*  301135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  301138 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301160 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  301163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301195 */     GIR_RootConstrainSelectedInstOperands,
     /*  301196 */     // GIR_Coverage, 15849,
     /*  301196 */     GIR_EraseRootFromParent_Done,
     /*  301197 */   // Label 4488: @301197
     /*  301197 */   GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(301264), // Rule ID 15850 //
     /*  301202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  301205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301227 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  301230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301262 */     GIR_RootConstrainSelectedInstOperands,
     /*  301263 */     // GIR_Coverage, 15850,
     /*  301263 */     GIR_EraseRootFromParent_Done,
     /*  301264 */   // Label 4489: @301264
     /*  301264 */   GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(301331), // Rule ID 15851 //
     /*  301269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  301272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301294 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  301297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301329 */     GIR_RootConstrainSelectedInstOperands,
     /*  301330 */     // GIR_Coverage, 15851,
     /*  301330 */     GIR_EraseRootFromParent_Done,
     /*  301331 */   // Label 4490: @301331
     /*  301331 */   GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(301398), // Rule ID 15852 //
     /*  301336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  301339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301361 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
     /*  301364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301396 */     GIR_RootConstrainSelectedInstOperands,
     /*  301397 */     // GIR_Coverage, 15852,
     /*  301397 */     GIR_EraseRootFromParent_Done,
     /*  301398 */   // Label 4491: @301398
     /*  301398 */   GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(301465), // Rule ID 15858 //
     /*  301403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  301406 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301428 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  301431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301463 */     GIR_RootConstrainSelectedInstOperands,
     /*  301464 */     // GIR_Coverage, 15858,
     /*  301464 */     GIR_EraseRootFromParent_Done,
     /*  301465 */   // Label 4492: @301465
     /*  301465 */   GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(301532), // Rule ID 15859 //
     /*  301470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  301473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301495 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  301498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301530 */     GIR_RootConstrainSelectedInstOperands,
     /*  301531 */     // GIR_Coverage, 15859,
     /*  301531 */     GIR_EraseRootFromParent_Done,
     /*  301532 */   // Label 4493: @301532
     /*  301532 */   GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(301599), // Rule ID 15860 //
     /*  301537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  301540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301562 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  301565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301597 */     GIR_RootConstrainSelectedInstOperands,
     /*  301598 */     // GIR_Coverage, 15860,
     /*  301598 */     GIR_EraseRootFromParent_Done,
     /*  301599 */   // Label 4494: @301599
     /*  301599 */   GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(301666), // Rule ID 15861 //
     /*  301604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  301607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301629 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  301632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301664 */     GIR_RootConstrainSelectedInstOperands,
     /*  301665 */     // GIR_Coverage, 15861,
     /*  301665 */     GIR_EraseRootFromParent_Done,
     /*  301666 */   // Label 4495: @301666
     /*  301666 */   GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(301733), // Rule ID 15862 //
     /*  301671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  301674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  301681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  301696 */     // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  301696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
     /*  301699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  301701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  301706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  301711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  301716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  301721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301731 */     GIR_RootConstrainSelectedInstOperands,
     /*  301732 */     // GIR_Coverage, 15862,
     /*  301732 */     GIR_EraseRootFromParent_Done,
     /*  301733 */   // Label 4496: @301733
     /*  301733 */   GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(301794), // Rule ID 29563 //
     /*  301738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  301741 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  301745 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  301750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301754 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301758 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  301765 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  301765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  301768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  301770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  301775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  301780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  301785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301792 */     GIR_RootConstrainSelectedInstOperands,
     /*  301793 */     // GIR_Coverage, 29563,
     /*  301793 */     GIR_EraseRootFromParent_Done,
     /*  301794 */   // Label 4497: @301794
     /*  301794 */   GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(301855), // Rule ID 29564 //
     /*  301799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  301802 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  301806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  301811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  301826 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  301826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  301829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  301831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  301836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  301841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  301846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301853 */     GIR_RootConstrainSelectedInstOperands,
     /*  301854 */     // GIR_Coverage, 29564,
     /*  301854 */     GIR_EraseRootFromParent_Done,
     /*  301855 */   // Label 4498: @301855
     /*  301855 */   GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(301916), // Rule ID 29565 //
     /*  301860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  301863 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  301867 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  301872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  301887 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  301887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  301890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  301892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  301897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  301902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  301907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301914 */     GIR_RootConstrainSelectedInstOperands,
     /*  301915 */     // GIR_Coverage, 29565,
     /*  301915 */     GIR_EraseRootFromParent_Done,
     /*  301916 */   // Label 4499: @301916
     /*  301916 */   GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(301977), // Rule ID 29566 //
     /*  301921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  301924 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  301928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  301933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  301941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  301948 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  301948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  301951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  301953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  301958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  301963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  301968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  301971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  301975 */     GIR_RootConstrainSelectedInstOperands,
     /*  301976 */     // GIR_Coverage, 29566,
     /*  301976 */     GIR_EraseRootFromParent_Done,
     /*  301977 */   // Label 4500: @301977
     /*  301977 */   GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(302038), // Rule ID 29567 //
     /*  301982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  301985 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  301989 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  301994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  301998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  302009 */     // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  302009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  302012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  302014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  302019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  302024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  302029 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302032 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302036 */     GIR_RootConstrainSelectedInstOperands,
     /*  302037 */     // GIR_Coverage, 29567,
     /*  302037 */     GIR_EraseRootFromParent_Done,
     /*  302038 */   // Label 4501: @302038
     /*  302038 */   GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(302099), // Rule ID 29583 //
     /*  302043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  302046 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  302050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  302055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302059 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302063 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  302070 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  302070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  302073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  302075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  302080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  302085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  302090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302093 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302097 */     GIR_RootConstrainSelectedInstOperands,
     /*  302098 */     // GIR_Coverage, 29583,
     /*  302098 */     GIR_EraseRootFromParent_Done,
     /*  302099 */   // Label 4502: @302099
     /*  302099 */   GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(302160), // Rule ID 29584 //
     /*  302104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  302107 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  302111 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  302116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  302131 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  302131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  302134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  302136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  302141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  302146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  302151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302158 */     GIR_RootConstrainSelectedInstOperands,
     /*  302159 */     // GIR_Coverage, 29584,
     /*  302159 */     GIR_EraseRootFromParent_Done,
     /*  302160 */   // Label 4503: @302160
     /*  302160 */   GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(302221), // Rule ID 29585 //
     /*  302165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  302168 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  302172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  302177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302181 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302185 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  302192 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  302192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  302195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  302197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  302202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  302207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  302212 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302215 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302219 */     GIR_RootConstrainSelectedInstOperands,
     /*  302220 */     // GIR_Coverage, 29585,
     /*  302220 */     GIR_EraseRootFromParent_Done,
     /*  302221 */   // Label 4504: @302221
     /*  302221 */   GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(302282), // Rule ID 29586 //
     /*  302226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  302229 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  302233 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  302238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302246 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  302253 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  302253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  302256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  302258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  302263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  302268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  302273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302276 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302280 */     GIR_RootConstrainSelectedInstOperands,
     /*  302281 */     // GIR_Coverage, 29586,
     /*  302281 */     GIR_EraseRootFromParent_Done,
     /*  302282 */   // Label 4505: @302282
     /*  302282 */   GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(302343), // Rule ID 29587 //
     /*  302287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  302290 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  302294 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  302299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  302314 */     // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  302314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
     /*  302317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  302319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  302324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  302329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  302334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302337 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302341 */     GIR_RootConstrainSelectedInstOperands,
     /*  302342 */     // GIR_Coverage, 29587,
     /*  302342 */     GIR_EraseRootFromParent_Done,
     /*  302343 */   // Label 4506: @302343
     /*  302343 */   GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(302405), // Rule ID 15823 //
     /*  302348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  302351 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302362 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302366 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302373 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  302376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302399 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302403 */     GIR_RootConstrainSelectedInstOperands,
     /*  302404 */     // GIR_Coverage, 15823,
     /*  302404 */     GIR_EraseRootFromParent_Done,
     /*  302405 */   // Label 4507: @302405
     /*  302405 */   GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(302467), // Rule ID 15824 //
     /*  302410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  302413 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302424 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302435 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  302438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302465 */     GIR_RootConstrainSelectedInstOperands,
     /*  302466 */     // GIR_Coverage, 15824,
     /*  302466 */     GIR_EraseRootFromParent_Done,
     /*  302467 */   // Label 4508: @302467
     /*  302467 */   GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(302529), // Rule ID 15825 //
     /*  302472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  302475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302486 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302497 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  302500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302523 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302527 */     GIR_RootConstrainSelectedInstOperands,
     /*  302528 */     // GIR_Coverage, 15825,
     /*  302528 */     GIR_EraseRootFromParent_Done,
     /*  302529 */   // Label 4509: @302529
     /*  302529 */   GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(302591), // Rule ID 15826 //
     /*  302534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  302537 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302559 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  302562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302585 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302589 */     GIR_RootConstrainSelectedInstOperands,
     /*  302590 */     // GIR_Coverage, 15826,
     /*  302590 */     GIR_EraseRootFromParent_Done,
     /*  302591 */   // Label 4510: @302591
     /*  302591 */   GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(302653), // Rule ID 15827 //
     /*  302596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  302599 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302621 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  302624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302651 */     GIR_RootConstrainSelectedInstOperands,
     /*  302652 */     // GIR_Coverage, 15827,
     /*  302652 */     GIR_EraseRootFromParent_Done,
     /*  302653 */   // Label 4511: @302653
     /*  302653 */   GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(302715), // Rule ID 15833 //
     /*  302658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  302661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302683 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  302686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302713 */     GIR_RootConstrainSelectedInstOperands,
     /*  302714 */     // GIR_Coverage, 15833,
     /*  302714 */     GIR_EraseRootFromParent_Done,
     /*  302715 */   // Label 4512: @302715
     /*  302715 */   GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(302777), // Rule ID 15834 //
     /*  302720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  302723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302745 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  302748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302775 */     GIR_RootConstrainSelectedInstOperands,
     /*  302776 */     // GIR_Coverage, 15834,
     /*  302776 */     GIR_EraseRootFromParent_Done,
     /*  302777 */   // Label 4513: @302777
     /*  302777 */   GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(302839), // Rule ID 15835 //
     /*  302782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  302785 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302807 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  302810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302837 */     GIR_RootConstrainSelectedInstOperands,
     /*  302838 */     // GIR_Coverage, 15835,
     /*  302838 */     GIR_EraseRootFromParent_Done,
     /*  302839 */   // Label 4514: @302839
     /*  302839 */   GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(302901), // Rule ID 15836 //
     /*  302844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  302847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302862 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302869 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  302872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302899 */     GIR_RootConstrainSelectedInstOperands,
     /*  302900 */     // GIR_Coverage, 15836,
     /*  302900 */     GIR_EraseRootFromParent_Done,
     /*  302901 */   // Label 4515: @302901
     /*  302901 */   GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(302963), // Rule ID 15837 //
     /*  302906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  302909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302920 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302931 */     // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  302934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  302941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  302946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  302951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  302957 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  302961 */     GIR_RootConstrainSelectedInstOperands,
     /*  302962 */     // GIR_Coverage, 15837,
     /*  302962 */     GIR_EraseRootFromParent_Done,
     /*  302963 */   // Label 4516: @302963
     /*  302963 */   GIM_Try, /*On fail goto*//*Label 4517*/ GIMT_Encode4(303025), // Rule ID 15843 //
     /*  302968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  302971 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  302978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  302982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  302986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  302993 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  302993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  302996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  302998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303023 */     GIR_RootConstrainSelectedInstOperands,
     /*  303024 */     // GIR_Coverage, 15843,
     /*  303024 */     GIR_EraseRootFromParent_Done,
     /*  303025 */   // Label 4517: @303025
     /*  303025 */   GIM_Try, /*On fail goto*//*Label 4518*/ GIMT_Encode4(303087), // Rule ID 15844 //
     /*  303030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  303033 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303044 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303048 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303055 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  303058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303085 */     GIR_RootConstrainSelectedInstOperands,
     /*  303086 */     // GIR_Coverage, 15844,
     /*  303086 */     GIR_EraseRootFromParent_Done,
     /*  303087 */   // Label 4518: @303087
     /*  303087 */   GIM_Try, /*On fail goto*//*Label 4519*/ GIMT_Encode4(303149), // Rule ID 15845 //
     /*  303092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  303095 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303117 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  303120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303147 */     GIR_RootConstrainSelectedInstOperands,
     /*  303148 */     // GIR_Coverage, 15845,
     /*  303148 */     GIR_EraseRootFromParent_Done,
     /*  303149 */   // Label 4519: @303149
     /*  303149 */   GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(303211), // Rule ID 15846 //
     /*  303154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  303157 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303179 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  303182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303209 */     GIR_RootConstrainSelectedInstOperands,
     /*  303210 */     // GIR_Coverage, 15846,
     /*  303210 */     GIR_EraseRootFromParent_Done,
     /*  303211 */   // Label 4520: @303211
     /*  303211 */   GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(303273), // Rule ID 15847 //
     /*  303216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  303219 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303241 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
     /*  303244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303267 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303271 */     GIR_RootConstrainSelectedInstOperands,
     /*  303272 */     // GIR_Coverage, 15847,
     /*  303272 */     GIR_EraseRootFromParent_Done,
     /*  303273 */   // Label 4521: @303273
     /*  303273 */   GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(303335), // Rule ID 15853 //
     /*  303278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  303281 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303303 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  303306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303333 */     GIR_RootConstrainSelectedInstOperands,
     /*  303334 */     // GIR_Coverage, 15853,
     /*  303334 */     GIR_EraseRootFromParent_Done,
     /*  303335 */   // Label 4522: @303335
     /*  303335 */   GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(303397), // Rule ID 15854 //
     /*  303340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  303343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303354 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303358 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303365 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  303368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303395 */     GIR_RootConstrainSelectedInstOperands,
     /*  303396 */     // GIR_Coverage, 15854,
     /*  303396 */     GIR_EraseRootFromParent_Done,
     /*  303397 */   // Label 4523: @303397
     /*  303397 */   GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(303459), // Rule ID 15855 //
     /*  303402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  303405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303427 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  303430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303457 */     GIR_RootConstrainSelectedInstOperands,
     /*  303458 */     // GIR_Coverage, 15855,
     /*  303458 */     GIR_EraseRootFromParent_Done,
     /*  303459 */   // Label 4524: @303459
     /*  303459 */   GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(303521), // Rule ID 15856 //
     /*  303464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  303467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303478 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303482 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303489 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  303492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303512 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303515 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303519 */     GIR_RootConstrainSelectedInstOperands,
     /*  303520 */     // GIR_Coverage, 15856,
     /*  303520 */     GIR_EraseRootFromParent_Done,
     /*  303521 */   // Label 4525: @303521
     /*  303521 */   GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(303583), // Rule ID 15857 //
     /*  303526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  303529 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  303536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  303551 */     // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  303551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
     /*  303554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  303556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  303561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  303566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  303571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303581 */     GIR_RootConstrainSelectedInstOperands,
     /*  303582 */     // GIR_Coverage, 15857,
     /*  303582 */     GIR_EraseRootFromParent_Done,
     /*  303583 */   // Label 4526: @303583
     /*  303583 */   GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(303640), // Rule ID 29573 //
     /*  303588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  303591 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303611 */     // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303638 */     GIR_RootConstrainSelectedInstOperands,
     /*  303639 */     // GIR_Coverage, 29573,
     /*  303639 */     GIR_EraseRootFromParent_Done,
     /*  303640 */   // Label 4527: @303640
     /*  303640 */   GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(303697), // Rule ID 29574 //
     /*  303645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  303648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303668 */     // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303688 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303695 */     GIR_RootConstrainSelectedInstOperands,
     /*  303696 */     // GIR_Coverage, 29574,
     /*  303696 */     GIR_EraseRootFromParent_Done,
     /*  303697 */   // Label 4528: @303697
     /*  303697 */   GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(303754), // Rule ID 29575 //
     /*  303702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  303705 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303714 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303718 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303725 */     // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303752 */     GIR_RootConstrainSelectedInstOperands,
     /*  303753 */     // GIR_Coverage, 29575,
     /*  303753 */     GIR_EraseRootFromParent_Done,
     /*  303754 */   // Label 4529: @303754
     /*  303754 */   GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(303811), // Rule ID 29576 //
     /*  303759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  303762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303771 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303782 */     // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303805 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303809 */     GIR_RootConstrainSelectedInstOperands,
     /*  303810 */     // GIR_Coverage, 29576,
     /*  303810 */     GIR_EraseRootFromParent_Done,
     /*  303811 */   // Label 4530: @303811
     /*  303811 */   GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(303868), // Rule ID 29577 //
     /*  303816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  303819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303839 */     // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303866 */     GIR_RootConstrainSelectedInstOperands,
     /*  303867 */     // GIR_Coverage, 29577,
     /*  303867 */     GIR_EraseRootFromParent_Done,
     /*  303868 */   // Label 4531: @303868
     /*  303868 */   GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(303925), // Rule ID 29593 //
     /*  303873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  303876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303896 */     // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303923 */     GIR_RootConstrainSelectedInstOperands,
     /*  303924 */     // GIR_Coverage, 29593,
     /*  303924 */     GIR_EraseRootFromParent_Done,
     /*  303925 */   // Label 4532: @303925
     /*  303925 */   GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(303982), // Rule ID 29594 //
     /*  303930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  303933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  303946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  303953 */     // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  303953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  303956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  303958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  303963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  303968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  303973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  303976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  303980 */     GIR_RootConstrainSelectedInstOperands,
     /*  303981 */     // GIR_Coverage, 29594,
     /*  303981 */     GIR_EraseRootFromParent_Done,
     /*  303982 */   // Label 4533: @303982
     /*  303982 */   GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(304039), // Rule ID 29595 //
     /*  303987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  303990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  303995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  303999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  304010 */     // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  304010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  304013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  304020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  304025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  304030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304033 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304037 */     GIR_RootConstrainSelectedInstOperands,
     /*  304038 */     // GIR_Coverage, 29595,
     /*  304038 */     GIR_EraseRootFromParent_Done,
     /*  304039 */   // Label 4534: @304039
     /*  304039 */   GIM_Try, /*On fail goto*//*Label 4535*/ GIMT_Encode4(304096), // Rule ID 29596 //
     /*  304044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  304047 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  304052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  304067 */     // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  304067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  304070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  304077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  304082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  304087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304094 */     GIR_RootConstrainSelectedInstOperands,
     /*  304095 */     // GIR_Coverage, 29596,
     /*  304095 */     GIR_EraseRootFromParent_Done,
     /*  304096 */   // Label 4535: @304096
     /*  304096 */   GIM_Try, /*On fail goto*//*Label 4536*/ GIMT_Encode4(304153), // Rule ID 29597 //
     /*  304101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  304104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  304109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  304124 */     // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  304124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
     /*  304127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  304134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  304139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  304144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304151 */     GIR_RootConstrainSelectedInstOperands,
     /*  304152 */     // GIR_Coverage, 29597,
     /*  304152 */     GIR_EraseRootFromParent_Done,
     /*  304153 */   // Label 4536: @304153
     /*  304153 */   GIM_Try, /*On fail goto*//*Label 4537*/ GIMT_Encode4(304214), // Rule ID 12533 //
     /*  304158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  304161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304183 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304212 */     GIR_RootConstrainSelectedInstOperands,
     /*  304213 */     // GIR_Coverage, 12533,
     /*  304213 */     GIR_EraseRootFromParent_Done,
     /*  304214 */   // Label 4537: @304214
     /*  304214 */   GIM_Try, /*On fail goto*//*Label 4538*/ GIMT_Encode4(304275), // Rule ID 12534 //
     /*  304219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  304222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304244 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304269 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304273 */     GIR_RootConstrainSelectedInstOperands,
     /*  304274 */     // GIR_Coverage, 12534,
     /*  304274 */     GIR_EraseRootFromParent_Done,
     /*  304275 */   // Label 4538: @304275
     /*  304275 */   GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(304336), // Rule ID 12535 //
     /*  304280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  304283 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304305 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304334 */     GIR_RootConstrainSelectedInstOperands,
     /*  304335 */     // GIR_Coverage, 12535,
     /*  304335 */     GIR_EraseRootFromParent_Done,
     /*  304336 */   // Label 4539: @304336
     /*  304336 */   GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(304397), // Rule ID 12536 //
     /*  304341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  304344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304366 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304395 */     GIR_RootConstrainSelectedInstOperands,
     /*  304396 */     // GIR_Coverage, 12536,
     /*  304396 */     GIR_EraseRootFromParent_Done,
     /*  304397 */   // Label 4540: @304397
     /*  304397 */   GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(304458), // Rule ID 12537 //
     /*  304402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  304405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304427 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304456 */     GIR_RootConstrainSelectedInstOperands,
     /*  304457 */     // GIR_Coverage, 12537,
     /*  304457 */     GIR_EraseRootFromParent_Done,
     /*  304458 */   // Label 4541: @304458
     /*  304458 */   GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(304519), // Rule ID 12553 //
     /*  304463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  304466 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304488 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304517 */     GIR_RootConstrainSelectedInstOperands,
     /*  304518 */     // GIR_Coverage, 12553,
     /*  304518 */     GIR_EraseRootFromParent_Done,
     /*  304519 */   // Label 4542: @304519
     /*  304519 */   GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(304580), // Rule ID 12554 //
     /*  304524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  304527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304542 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304549 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304578 */     GIR_RootConstrainSelectedInstOperands,
     /*  304579 */     // GIR_Coverage, 12554,
     /*  304579 */     GIR_EraseRootFromParent_Done,
     /*  304580 */   // Label 4543: @304580
     /*  304580 */   GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(304641), // Rule ID 12555 //
     /*  304585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  304588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304610 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304639 */     GIR_RootConstrainSelectedInstOperands,
     /*  304640 */     // GIR_Coverage, 12555,
     /*  304640 */     GIR_EraseRootFromParent_Done,
     /*  304641 */   // Label 4544: @304641
     /*  304641 */   GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(304702), // Rule ID 12556 //
     /*  304646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  304649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304671 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304700 */     GIR_RootConstrainSelectedInstOperands,
     /*  304701 */     // GIR_Coverage, 12556,
     /*  304701 */     GIR_EraseRootFromParent_Done,
     /*  304702 */   // Label 4545: @304702
     /*  304702 */   GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(304763), // Rule ID 12557 //
     /*  304707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  304710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  304732 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  304732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
     /*  304735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  304742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  304747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  304752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  304757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304761 */     GIR_RootConstrainSelectedInstOperands,
     /*  304762 */     // GIR_Coverage, 12557,
     /*  304762 */     GIR_EraseRootFromParent_Done,
     /*  304763 */   // Label 4546: @304763
     /*  304763 */   GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(304817), // Rule ID 12528 //
     /*  304768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  304771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  304793 */     // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  304793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  304796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  304803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  304808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304815 */     GIR_RootConstrainSelectedInstOperands,
     /*  304816 */     // GIR_Coverage, 12528,
     /*  304816 */     GIR_EraseRootFromParent_Done,
     /*  304817 */   // Label 4547: @304817
     /*  304817 */   GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(304871), // Rule ID 12529 //
     /*  304822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  304825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  304847 */     // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  304847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  304850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  304857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  304862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304865 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304869 */     GIR_RootConstrainSelectedInstOperands,
     /*  304870 */     // GIR_Coverage, 12529,
     /*  304870 */     GIR_EraseRootFromParent_Done,
     /*  304871 */   // Label 4548: @304871
     /*  304871 */   GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(304925), // Rule ID 12530 //
     /*  304876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  304879 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304890 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  304901 */     // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  304901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  304904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  304911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  304916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304923 */     GIR_RootConstrainSelectedInstOperands,
     /*  304924 */     // GIR_Coverage, 12530,
     /*  304924 */     GIR_EraseRootFromParent_Done,
     /*  304925 */   // Label 4549: @304925
     /*  304925 */   GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(304979), // Rule ID 12531 //
     /*  304930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  304933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  304948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  304955 */     // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  304955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  304958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  304960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  304965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  304970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  304973 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  304977 */     GIR_RootConstrainSelectedInstOperands,
     /*  304978 */     // GIR_Coverage, 12531,
     /*  304978 */     GIR_EraseRootFromParent_Done,
     /*  304979 */   // Label 4550: @304979
     /*  304979 */   GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(305033), // Rule ID 12532 //
     /*  304984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  304987 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  304994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  304998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  305009 */     // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  305012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305031 */     GIR_RootConstrainSelectedInstOperands,
     /*  305032 */     // GIR_Coverage, 12532,
     /*  305032 */     GIR_EraseRootFromParent_Done,
     /*  305033 */   // Label 4551: @305033
     /*  305033 */   GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(305087), // Rule ID 12548 //
     /*  305038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  305041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305052 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305056 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  305063 */     // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  305066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305085 */     GIR_RootConstrainSelectedInstOperands,
     /*  305086 */     // GIR_Coverage, 12548,
     /*  305086 */     GIR_EraseRootFromParent_Done,
     /*  305087 */   // Label 4552: @305087
     /*  305087 */   GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(305141), // Rule ID 12549 //
     /*  305092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  305095 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  305117 */     // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  305120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305139 */     GIR_RootConstrainSelectedInstOperands,
     /*  305140 */     // GIR_Coverage, 12549,
     /*  305140 */     GIR_EraseRootFromParent_Done,
     /*  305141 */   // Label 4553: @305141
     /*  305141 */   GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(305195), // Rule ID 12550 //
     /*  305146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  305149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  305171 */     // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  305174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305189 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305193 */     GIR_RootConstrainSelectedInstOperands,
     /*  305194 */     // GIR_Coverage, 12550,
     /*  305194 */     GIR_EraseRootFromParent_Done,
     /*  305195 */   // Label 4554: @305195
     /*  305195 */   GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(305249), // Rule ID 12551 //
     /*  305200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  305203 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  305225 */     // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  305228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305247 */     GIR_RootConstrainSelectedInstOperands,
     /*  305248 */     // GIR_Coverage, 12551,
     /*  305248 */     GIR_EraseRootFromParent_Done,
     /*  305249 */   // Label 4555: @305249
     /*  305249 */   GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(305303), // Rule ID 12552 //
     /*  305254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  305257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  305279 */     // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
     /*  305282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305301 */     GIR_RootConstrainSelectedInstOperands,
     /*  305302 */     // GIR_Coverage, 12552,
     /*  305302 */     GIR_EraseRootFromParent_Done,
     /*  305303 */   // Label 4556: @305303
     /*  305303 */   GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(305365), // Rule ID 10391 //
     /*  305308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  305311 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305334 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305363 */     GIR_RootConstrainSelectedInstOperands,
     /*  305364 */     // GIR_Coverage, 10391,
     /*  305364 */     GIR_EraseRootFromParent_Done,
     /*  305365 */   // Label 4557: @305365
     /*  305365 */   GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(305427), // Rule ID 10392 //
     /*  305370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  305373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305385 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305389 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305396 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305425 */     GIR_RootConstrainSelectedInstOperands,
     /*  305426 */     // GIR_Coverage, 10392,
     /*  305426 */     GIR_EraseRootFromParent_Done,
     /*  305427 */   // Label 4558: @305427
     /*  305427 */   GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(305489), // Rule ID 10393 //
     /*  305432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  305435 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305447 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305451 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305458 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305487 */     GIR_RootConstrainSelectedInstOperands,
     /*  305488 */     // GIR_Coverage, 10393,
     /*  305488 */     GIR_EraseRootFromParent_Done,
     /*  305489 */   // Label 4559: @305489
     /*  305489 */   GIM_Try, /*On fail goto*//*Label 4560*/ GIMT_Encode4(305551), // Rule ID 10394 //
     /*  305494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  305497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305520 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305545 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305549 */     GIR_RootConstrainSelectedInstOperands,
     /*  305550 */     // GIR_Coverage, 10394,
     /*  305550 */     GIR_EraseRootFromParent_Done,
     /*  305551 */   // Label 4560: @305551
     /*  305551 */   GIM_Try, /*On fail goto*//*Label 4561*/ GIMT_Encode4(305613), // Rule ID 10395 //
     /*  305556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  305559 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305582 */     // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305611 */     GIR_RootConstrainSelectedInstOperands,
     /*  305612 */     // GIR_Coverage, 10395,
     /*  305612 */     GIR_EraseRootFromParent_Done,
     /*  305613 */   // Label 4561: @305613
     /*  305613 */   GIM_Try, /*On fail goto*//*Label 4562*/ GIMT_Encode4(305675), // Rule ID 10411 //
     /*  305618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  305621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305633 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305637 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305644 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305669 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305673 */     GIR_RootConstrainSelectedInstOperands,
     /*  305674 */     // GIR_Coverage, 10411,
     /*  305674 */     GIR_EraseRootFromParent_Done,
     /*  305675 */   // Label 4562: @305675
     /*  305675 */   GIM_Try, /*On fail goto*//*Label 4563*/ GIMT_Encode4(305737), // Rule ID 10412 //
     /*  305680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  305683 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305706 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305735 */     GIR_RootConstrainSelectedInstOperands,
     /*  305736 */     // GIR_Coverage, 10412,
     /*  305736 */     GIR_EraseRootFromParent_Done,
     /*  305737 */   // Label 4563: @305737
     /*  305737 */   GIM_Try, /*On fail goto*//*Label 4564*/ GIMT_Encode4(305799), // Rule ID 10413 //
     /*  305742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  305745 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305757 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305768 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305793 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305797 */     GIR_RootConstrainSelectedInstOperands,
     /*  305798 */     // GIR_Coverage, 10413,
     /*  305798 */     GIR_EraseRootFromParent_Done,
     /*  305799 */   // Label 4564: @305799
     /*  305799 */   GIM_Try, /*On fail goto*//*Label 4565*/ GIMT_Encode4(305861), // Rule ID 10414 //
     /*  305804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  305807 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305830 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305859 */     GIR_RootConstrainSelectedInstOperands,
     /*  305860 */     // GIR_Coverage, 10414,
     /*  305860 */     GIR_EraseRootFromParent_Done,
     /*  305861 */   // Label 4565: @305861
     /*  305861 */   GIM_Try, /*On fail goto*//*Label 4566*/ GIMT_Encode4(305923), // Rule ID 10415 //
     /*  305866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  305869 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305881 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  305892 */     // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  305892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4_SADDR),
     /*  305895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  305902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  305907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  305912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  305917 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305921 */     GIR_RootConstrainSelectedInstOperands,
     /*  305922 */     // GIR_Coverage, 10415,
     /*  305922 */     GIR_EraseRootFromParent_Done,
     /*  305923 */   // Label 4566: @305923
     /*  305923 */   GIM_Try, /*On fail goto*//*Label 4567*/ GIMT_Encode4(305978), // Rule ID 10386 //
     /*  305928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  305931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  305947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  305954 */     // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  305954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  305957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  305959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  305964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  305969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  305972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  305976 */     GIR_RootConstrainSelectedInstOperands,
     /*  305977 */     // GIR_Coverage, 10386,
     /*  305977 */     GIR_EraseRootFromParent_Done,
     /*  305978 */   // Label 4567: @305978
     /*  305978 */   GIM_Try, /*On fail goto*//*Label 4568*/ GIMT_Encode4(306033), // Rule ID 10387 //
     /*  305983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  305986 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  305994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  305998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306009 */     // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306031 */     GIR_RootConstrainSelectedInstOperands,
     /*  306032 */     // GIR_Coverage, 10387,
     /*  306032 */     GIR_EraseRootFromParent_Done,
     /*  306033 */   // Label 4568: @306033
     /*  306033 */   GIM_Try, /*On fail goto*//*Label 4569*/ GIMT_Encode4(306088), // Rule ID 10388 //
     /*  306038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  306041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306064 */     // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306086 */     GIR_RootConstrainSelectedInstOperands,
     /*  306087 */     // GIR_Coverage, 10388,
     /*  306087 */     GIR_EraseRootFromParent_Done,
     /*  306088 */   // Label 4569: @306088
     /*  306088 */   GIM_Try, /*On fail goto*//*Label 4570*/ GIMT_Encode4(306143), // Rule ID 10389 //
     /*  306093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  306096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306119 */     // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306141 */     GIR_RootConstrainSelectedInstOperands,
     /*  306142 */     // GIR_Coverage, 10389,
     /*  306142 */     GIR_EraseRootFromParent_Done,
     /*  306143 */   // Label 4570: @306143
     /*  306143 */   GIM_Try, /*On fail goto*//*Label 4571*/ GIMT_Encode4(306198), // Rule ID 10390 //
     /*  306148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  306151 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306174 */     // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306196 */     GIR_RootConstrainSelectedInstOperands,
     /*  306197 */     // GIR_Coverage, 10390,
     /*  306197 */     GIR_EraseRootFromParent_Done,
     /*  306198 */   // Label 4571: @306198
     /*  306198 */   GIM_Try, /*On fail goto*//*Label 4572*/ GIMT_Encode4(306253), // Rule ID 10406 //
     /*  306203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  306206 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306229 */     // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306251 */     GIR_RootConstrainSelectedInstOperands,
     /*  306252 */     // GIR_Coverage, 10406,
     /*  306252 */     GIR_EraseRootFromParent_Done,
     /*  306253 */   // Label 4572: @306253
     /*  306253 */   GIM_Try, /*On fail goto*//*Label 4573*/ GIMT_Encode4(306308), // Rule ID 10407 //
     /*  306258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  306261 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306284 */     // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306306 */     GIR_RootConstrainSelectedInstOperands,
     /*  306307 */     // GIR_Coverage, 10407,
     /*  306307 */     GIR_EraseRootFromParent_Done,
     /*  306308 */   // Label 4573: @306308
     /*  306308 */   GIM_Try, /*On fail goto*//*Label 4574*/ GIMT_Encode4(306363), // Rule ID 10408 //
     /*  306313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  306316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306339 */     // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306361 */     GIR_RootConstrainSelectedInstOperands,
     /*  306362 */     // GIR_Coverage, 10408,
     /*  306362 */     GIR_EraseRootFromParent_Done,
     /*  306363 */   // Label 4574: @306363
     /*  306363 */   GIM_Try, /*On fail goto*//*Label 4575*/ GIMT_Encode4(306418), // Rule ID 10409 //
     /*  306368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  306371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306383 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306394 */     // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306416 */     GIR_RootConstrainSelectedInstOperands,
     /*  306417 */     // GIR_Coverage, 10409,
     /*  306417 */     GIR_EraseRootFromParent_Done,
     /*  306418 */   // Label 4575: @306418
     /*  306418 */   GIM_Try, /*On fail goto*//*Label 4576*/ GIMT_Encode4(306473), // Rule ID 10410 //
     /*  306423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  306426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  306434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  306438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  306449 */     // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  306449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
     /*  306452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  306454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  306459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306471 */     GIR_RootConstrainSelectedInstOperands,
     /*  306472 */     // GIR_Coverage, 10410,
     /*  306472 */     GIR_EraseRootFromParent_Done,
     /*  306473 */   // Label 4576: @306473
     /*  306473 */   GIM_Reject,
     /*  306474 */ // Label 4372: @306474
     /*  306474 */ GIM_Reject,
     /*  306475 */ // Label 1137: @306475
     /*  306475 */ GIM_Try, /*On fail goto*//*Label 4577*/ GIMT_Encode4(308150),
     /*  306480 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  306483 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  306487 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  306491 */   GIM_Try, /*On fail goto*//*Label 4578*/ GIMT_Encode4(306549), // Rule ID 9025 //
     /*  306496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  306499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306507 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  306511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  306518 */     // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  306518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  306521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  306533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  306538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  306543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306547 */     GIR_RootConstrainSelectedInstOperands,
     /*  306548 */     // GIR_Coverage, 9025,
     /*  306548 */     GIR_EraseRootFromParent_Done,
     /*  306549 */   // Label 4578: @306549
     /*  306549 */   GIM_Try, /*On fail goto*//*Label 4579*/ GIMT_Encode4(306607), // Rule ID 9042 //
     /*  306554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  306557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306565 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  306569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  306576 */     // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  306576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  306579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  306591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  306596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  306601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306605 */     GIR_RootConstrainSelectedInstOperands,
     /*  306606 */     // GIR_Coverage, 9042,
     /*  306606 */     GIR_EraseRootFromParent_Done,
     /*  306607 */   // Label 4579: @306607
     /*  306607 */   GIM_Try, /*On fail goto*//*Label 4580*/ GIMT_Encode4(306661), // Rule ID 9030 //
     /*  306612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  306615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  306630 */     // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  306630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  306633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  306645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  306650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  306655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306659 */     GIR_RootConstrainSelectedInstOperands,
     /*  306660 */     // GIR_Coverage, 9030,
     /*  306660 */     GIR_EraseRootFromParent_Done,
     /*  306661 */   // Label 4580: @306661
     /*  306661 */   GIM_Try, /*On fail goto*//*Label 4581*/ GIMT_Encode4(306715), // Rule ID 9047 //
     /*  306666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  306669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  306684 */     // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  306684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  306687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  306699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  306704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  306709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306713 */     GIR_RootConstrainSelectedInstOperands,
     /*  306714 */     // GIR_Coverage, 9047,
     /*  306714 */     GIR_EraseRootFromParent_Done,
     /*  306715 */   // Label 4581: @306715
     /*  306715 */   GIM_Try, /*On fail goto*//*Label 4582*/ GIMT_Encode4(306769), // Rule ID 9036 //
     /*  306720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  306723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  306738 */     // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  306738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  306741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  306753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  306758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  306763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306767 */     GIR_RootConstrainSelectedInstOperands,
     /*  306768 */     // GIR_Coverage, 9036,
     /*  306768 */     GIR_EraseRootFromParent_Done,
     /*  306769 */   // Label 4582: @306769
     /*  306769 */   GIM_Try, /*On fail goto*//*Label 4583*/ GIMT_Encode4(306823), // Rule ID 9053 //
     /*  306774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  306777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  306792 */     // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  306792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  306795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  306807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  306812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  306817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306821 */     GIR_RootConstrainSelectedInstOperands,
     /*  306822 */     // GIR_Coverage, 9053,
     /*  306822 */     GIR_EraseRootFromParent_Done,
     /*  306823 */   // Label 4583: @306823
     /*  306823 */   GIM_Try, /*On fail goto*//*Label 4584*/ GIMT_Encode4(306874), // Rule ID 9021 //
     /*  306828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  306831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306839 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  306843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  306850 */     // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  306850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  306853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306872 */     GIR_RootConstrainSelectedInstOperands,
     /*  306873 */     // GIR_Coverage, 9021,
     /*  306873 */     GIR_EraseRootFromParent_Done,
     /*  306874 */   // Label 4584: @306874
     /*  306874 */   GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(306925), // Rule ID 9022 //
     /*  306879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  306882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306890 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  306894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  306901 */     // (ld:{ *:[v8i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  306901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  306904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306923 */     GIR_RootConstrainSelectedInstOperands,
     /*  306924 */     // GIR_Coverage, 9022,
     /*  306924 */     GIR_EraseRootFromParent_Done,
     /*  306925 */   // Label 4585: @306925
     /*  306925 */   GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(306976), // Rule ID 9038 //
     /*  306930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  306933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306941 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  306945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  306952 */     // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  306952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  306955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  306957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  306962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  306967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  306970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  306974 */     GIR_RootConstrainSelectedInstOperands,
     /*  306975 */     // GIR_Coverage, 9038,
     /*  306975 */     GIR_EraseRootFromParent_Done,
     /*  306976 */   // Label 4586: @306976
     /*  306976 */   GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(307027), // Rule ID 9039 //
     /*  306981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  306984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  306988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  306992 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  306996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  307003 */     // (ld:{ *:[v8f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  307006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307025 */     GIR_RootConstrainSelectedInstOperands,
     /*  307026 */     // GIR_Coverage, 9039,
     /*  307026 */     GIR_EraseRootFromParent_Done,
     /*  307027 */   // Label 4587: @307027
     /*  307027 */   GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(307074), // Rule ID 9027 //
     /*  307032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  307035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  307050 */     // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  307053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307072 */     GIR_RootConstrainSelectedInstOperands,
     /*  307073 */     // GIR_Coverage, 9027,
     /*  307073 */     GIR_EraseRootFromParent_Done,
     /*  307074 */   // Label 4588: @307074
     /*  307074 */   GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(307121), // Rule ID 9044 //
     /*  307079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  307082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  307097 */     // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  307100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307119 */     GIR_RootConstrainSelectedInstOperands,
     /*  307120 */     // GIR_Coverage, 9044,
     /*  307120 */     GIR_EraseRootFromParent_Done,
     /*  307121 */   // Label 4589: @307121
     /*  307121 */   GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(307165), // Rule ID 9032 //
     /*  307126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307130 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307134 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  307141 */     // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  307144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307163 */     GIR_RootConstrainSelectedInstOperands,
     /*  307164 */     // GIR_Coverage, 9032,
     /*  307164 */     GIR_EraseRootFromParent_Done,
     /*  307165 */   // Label 4590: @307165
     /*  307165 */   GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(307212), // Rule ID 9033 //
     /*  307170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  307173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  307188 */     // (ld:{ *:[v8i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  307191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307210 */     GIR_RootConstrainSelectedInstOperands,
     /*  307211 */     // GIR_Coverage, 9033,
     /*  307211 */     GIR_EraseRootFromParent_Done,
     /*  307212 */   // Label 4591: @307212
     /*  307212 */   GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(307256), // Rule ID 9049 //
     /*  307217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  307232 */     // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  307235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307254 */     GIR_RootConstrainSelectedInstOperands,
     /*  307255 */     // GIR_Coverage, 9049,
     /*  307255 */     GIR_EraseRootFromParent_Done,
     /*  307256 */   // Label 4592: @307256
     /*  307256 */   GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(307303), // Rule ID 9050 //
     /*  307261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  307264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  307279 */     // (ld:{ *:[v8f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  307279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  307282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  307294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307301 */     GIR_RootConstrainSelectedInstOperands,
     /*  307302 */     // GIR_Coverage, 9050,
     /*  307302 */     GIR_EraseRootFromParent_Done,
     /*  307303 */   // Label 4593: @307303
     /*  307303 */   GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(307354), // Rule ID 9023 //
     /*  307308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  307311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307319 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  307323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307330 */     // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  307330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  307333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307352 */     GIR_RootConstrainSelectedInstOperands,
     /*  307353 */     // GIR_Coverage, 9023,
     /*  307353 */     GIR_EraseRootFromParent_Done,
     /*  307354 */   // Label 4594: @307354
     /*  307354 */   GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(307410), // Rule ID 9024 //
     /*  307359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  307362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307370 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  307374 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307381 */     // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  307381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  307384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  307404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307408 */     GIR_RootConstrainSelectedInstOperands,
     /*  307409 */     // GIR_Coverage, 9024,
     /*  307409 */     GIR_EraseRootFromParent_Done,
     /*  307410 */   // Label 4595: @307410
     /*  307410 */   GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(307461), // Rule ID 9040 //
     /*  307415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  307418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307426 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  307430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307437 */     // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  307437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  307440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307455 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307459 */     GIR_RootConstrainSelectedInstOperands,
     /*  307460 */     // GIR_Coverage, 9040,
     /*  307460 */     GIR_EraseRootFromParent_Done,
     /*  307461 */   // Label 4596: @307461
     /*  307461 */   GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(307517), // Rule ID 9041 //
     /*  307466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  307469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307477 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  307481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307488 */     // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  307488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  307491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  307511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307515 */     GIR_RootConstrainSelectedInstOperands,
     /*  307516 */     // GIR_Coverage, 9041,
     /*  307516 */     GIR_EraseRootFromParent_Done,
     /*  307517 */   // Label 4597: @307517
     /*  307517 */   GIM_Try, /*On fail goto*//*Label 4598*/ GIMT_Encode4(307560), // Rule ID 9026 //
     /*  307522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  307525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307529 */     // MIs[0] sbase
     /*  307529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  307533 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  307537 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  307541 */     // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  307541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  307544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307546 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  307548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307558 */     GIR_RootConstrainSelectedInstOperands,
     /*  307559 */     // GIR_Coverage, 9026,
     /*  307559 */     GIR_EraseRootFromParent_Done,
     /*  307560 */   // Label 4598: @307560
     /*  307560 */   GIM_Try, /*On fail goto*//*Label 4599*/ GIMT_Encode4(307603), // Rule ID 9043 //
     /*  307565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  307568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307572 */     // MIs[0] sbase
     /*  307572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  307576 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  307580 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  307584 */     // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  307584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  307587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307589 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  307591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307601 */     GIR_RootConstrainSelectedInstOperands,
     /*  307602 */     // GIR_Coverage, 9043,
     /*  307602 */     GIR_EraseRootFromParent_Done,
     /*  307603 */   // Label 4599: @307603
     /*  307603 */   GIM_Try, /*On fail goto*//*Label 4600*/ GIMT_Encode4(307650), // Rule ID 9028 //
     /*  307608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  307611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307626 */     // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  307626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec),
     /*  307629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307644 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307648 */     GIR_RootConstrainSelectedInstOperands,
     /*  307649 */     // GIR_Coverage, 9028,
     /*  307649 */     GIR_EraseRootFromParent_Done,
     /*  307650 */   // Label 4600: @307650
     /*  307650 */   GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(307702), // Rule ID 9029 //
     /*  307655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  307658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307673 */     // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  307673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  307676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307688 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  307696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307700 */     GIR_RootConstrainSelectedInstOperands,
     /*  307701 */     // GIR_Coverage, 9029,
     /*  307701 */     GIR_EraseRootFromParent_Done,
     /*  307702 */   // Label 4601: @307702
     /*  307702 */   GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(307749), // Rule ID 9045 //
     /*  307707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  307710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307714 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307718 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307725 */     // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  307725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec),
     /*  307728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307743 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307747 */     GIR_RootConstrainSelectedInstOperands,
     /*  307748 */     // GIR_Coverage, 9045,
     /*  307748 */     GIR_EraseRootFromParent_Done,
     /*  307749 */   // Label 4602: @307749
     /*  307749 */   GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(307801), // Rule ID 9046 //
     /*  307754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  307757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307772 */     // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  307772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  307775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  307795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307799 */     GIR_RootConstrainSelectedInstOperands,
     /*  307800 */     // GIR_Coverage, 9046,
     /*  307800 */     GIR_EraseRootFromParent_Done,
     /*  307801 */   // Label 4603: @307801
     /*  307801 */   GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(307840), // Rule ID 9031 //
     /*  307806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  307809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307813 */     // MIs[0] sbase
     /*  307813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  307817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  307821 */     // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  307821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  307824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307826 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  307828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307838 */     GIR_RootConstrainSelectedInstOperands,
     /*  307839 */     // GIR_Coverage, 9031,
     /*  307839 */     GIR_EraseRootFromParent_Done,
     /*  307840 */   // Label 4604: @307840
     /*  307840 */   GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(307879), // Rule ID 9048 //
     /*  307845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  307848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307852 */     // MIs[0] sbase
     /*  307852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  307856 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  307860 */     // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  307860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  307863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307865 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  307867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307877 */     GIR_RootConstrainSelectedInstOperands,
     /*  307878 */     // GIR_Coverage, 9048,
     /*  307878 */     GIR_EraseRootFromParent_Done,
     /*  307879 */   // Label 4605: @307879
     /*  307879 */   GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(307926), // Rule ID 9034 //
     /*  307884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  307887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307902 */     // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  307902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  307905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307920 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307924 */     GIR_RootConstrainSelectedInstOperands,
     /*  307925 */     // GIR_Coverage, 9034,
     /*  307925 */     GIR_EraseRootFromParent_Done,
     /*  307926 */   // Label 4606: @307926
     /*  307926 */   GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(307978), // Rule ID 9035 //
     /*  307931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  307934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  307949 */     // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  307949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  307952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  307954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  307959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  307964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  307967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  307972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  307976 */     GIR_RootConstrainSelectedInstOperands,
     /*  307977 */     // GIR_Coverage, 9035,
     /*  307977 */     GIR_EraseRootFromParent_Done,
     /*  307978 */   // Label 4607: @307978
     /*  307978 */   GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(308025), // Rule ID 9051 //
     /*  307983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  307986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  307990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  307994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  308001 */     // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  308001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  308004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308023 */     GIR_RootConstrainSelectedInstOperands,
     /*  308024 */     // GIR_Coverage, 9051,
     /*  308024 */     GIR_EraseRootFromParent_Done,
     /*  308025 */   // Label 4608: @308025
     /*  308025 */   GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(308077), // Rule ID 9052 //
     /*  308030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  308033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  308037 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308041 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  308048 */     // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  308048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  308051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  308071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308075 */     GIR_RootConstrainSelectedInstOperands,
     /*  308076 */     // GIR_Coverage, 9052,
     /*  308076 */     GIR_EraseRootFromParent_Done,
     /*  308077 */   // Label 4609: @308077
     /*  308077 */   GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(308113), // Rule ID 9037 //
     /*  308082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  308086 */     // MIs[0] sbase
     /*  308086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  308090 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  308094 */     // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  308094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  308097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308099 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  308101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308111 */     GIR_RootConstrainSelectedInstOperands,
     /*  308112 */     // GIR_Coverage, 9037,
     /*  308112 */     GIR_EraseRootFromParent_Done,
     /*  308113 */   // Label 4610: @308113
     /*  308113 */   GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(308149), // Rule ID 9054 //
     /*  308118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  308122 */     // MIs[0] sbase
     /*  308122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  308126 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  308130 */     // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  308130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  308133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308135 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  308137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308147 */     GIR_RootConstrainSelectedInstOperands,
     /*  308148 */     // GIR_Coverage, 9054,
     /*  308148 */     GIR_EraseRootFromParent_Done,
     /*  308149 */   // Label 4611: @308149
     /*  308149 */   GIM_Reject,
     /*  308150 */ // Label 4577: @308150
     /*  308150 */ GIM_Reject,
     /*  308151 */ // Label 1138: @308151
     /*  308151 */ GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(309826),
     /*  308156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  308159 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  308163 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  308167 */   GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(308225), // Rule ID 9161 //
     /*  308172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  308175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308183 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  308194 */     // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  308194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  308197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  308214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  308219 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308223 */     GIR_RootConstrainSelectedInstOperands,
     /*  308224 */     // GIR_Coverage, 9161,
     /*  308224 */     GIR_EraseRootFromParent_Done,
     /*  308225 */   // Label 4613: @308225
     /*  308225 */   GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(308283), // Rule ID 9178 //
     /*  308230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  308233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308241 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  308252 */     // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  308252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  308255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  308272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  308277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308281 */     GIR_RootConstrainSelectedInstOperands,
     /*  308282 */     // GIR_Coverage, 9178,
     /*  308282 */     GIR_EraseRootFromParent_Done,
     /*  308283 */   // Label 4614: @308283
     /*  308283 */   GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(308337), // Rule ID 9166 //
     /*  308288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  308291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  308306 */     // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  308306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  308309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  308326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  308331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308335 */     GIR_RootConstrainSelectedInstOperands,
     /*  308336 */     // GIR_Coverage, 9166,
     /*  308336 */     GIR_EraseRootFromParent_Done,
     /*  308337 */   // Label 4615: @308337
     /*  308337 */   GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(308391), // Rule ID 9183 //
     /*  308342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  308345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  308360 */     // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  308360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  308363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  308380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  308385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308389 */     GIR_RootConstrainSelectedInstOperands,
     /*  308390 */     // GIR_Coverage, 9183,
     /*  308390 */     GIR_EraseRootFromParent_Done,
     /*  308391 */   // Label 4616: @308391
     /*  308391 */   GIM_Try, /*On fail goto*//*Label 4617*/ GIMT_Encode4(308445), // Rule ID 9172 //
     /*  308396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  308399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  308414 */     // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  308414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  308417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  308434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  308439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308443 */     GIR_RootConstrainSelectedInstOperands,
     /*  308444 */     // GIR_Coverage, 9172,
     /*  308444 */     GIR_EraseRootFromParent_Done,
     /*  308445 */   // Label 4617: @308445
     /*  308445 */   GIM_Try, /*On fail goto*//*Label 4618*/ GIMT_Encode4(308499), // Rule ID 9189 //
     /*  308450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  308453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  308468 */     // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  308468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  308471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  308483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  308488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  308493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308497 */     GIR_RootConstrainSelectedInstOperands,
     /*  308498 */     // GIR_Coverage, 9189,
     /*  308498 */     GIR_EraseRootFromParent_Done,
     /*  308499 */   // Label 4618: @308499
     /*  308499 */   GIM_Try, /*On fail goto*//*Label 4619*/ GIMT_Encode4(308550), // Rule ID 9157 //
     /*  308504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  308507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308515 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308519 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  308526 */     // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  308529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308548 */     GIR_RootConstrainSelectedInstOperands,
     /*  308549 */     // GIR_Coverage, 9157,
     /*  308549 */     GIR_EraseRootFromParent_Done,
     /*  308550 */   // Label 4619: @308550
     /*  308550 */   GIM_Try, /*On fail goto*//*Label 4620*/ GIMT_Encode4(308601), // Rule ID 9158 //
     /*  308555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  308558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308562 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308566 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  308577 */     // (ld:{ *:[v8i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  308580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308599 */     GIR_RootConstrainSelectedInstOperands,
     /*  308600 */     // GIR_Coverage, 9158,
     /*  308600 */     GIR_EraseRootFromParent_Done,
     /*  308601 */   // Label 4620: @308601
     /*  308601 */   GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(308652), // Rule ID 9174 //
     /*  308606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  308609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308617 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  308628 */     // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  308631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308650 */     GIR_RootConstrainSelectedInstOperands,
     /*  308651 */     // GIR_Coverage, 9174,
     /*  308651 */     GIR_EraseRootFromParent_Done,
     /*  308652 */   // Label 4621: @308652
     /*  308652 */   GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(308703), // Rule ID 9175 //
     /*  308657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  308660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308668 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308672 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  308679 */     // (ld:{ *:[v8f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  308682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308701 */     GIR_RootConstrainSelectedInstOperands,
     /*  308702 */     // GIR_Coverage, 9175,
     /*  308702 */     GIR_EraseRootFromParent_Done,
     /*  308703 */   // Label 4622: @308703
     /*  308703 */   GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(308750), // Rule ID 9163 //
     /*  308708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  308711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  308726 */     // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  308729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308748 */     GIR_RootConstrainSelectedInstOperands,
     /*  308749 */     // GIR_Coverage, 9163,
     /*  308749 */     GIR_EraseRootFromParent_Done,
     /*  308750 */   // Label 4623: @308750
     /*  308750 */   GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(308797), // Rule ID 9180 //
     /*  308755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  308758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  308773 */     // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  308776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308788 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308795 */     GIR_RootConstrainSelectedInstOperands,
     /*  308796 */     // GIR_Coverage, 9180,
     /*  308796 */     GIR_EraseRootFromParent_Done,
     /*  308797 */   // Label 4624: @308797
     /*  308797 */   GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(308841), // Rule ID 9168 //
     /*  308802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308806 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  308817 */     // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  308820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308839 */     GIR_RootConstrainSelectedInstOperands,
     /*  308840 */     // GIR_Coverage, 9168,
     /*  308840 */     GIR_EraseRootFromParent_Done,
     /*  308841 */   // Label 4625: @308841
     /*  308841 */   GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(308888), // Rule ID 9169 //
     /*  308846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  308849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  308864 */     // (ld:{ *:[v8i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  308867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308886 */     GIR_RootConstrainSelectedInstOperands,
     /*  308887 */     // GIR_Coverage, 9169,
     /*  308887 */     GIR_EraseRootFromParent_Done,
     /*  308888 */   // Label 4626: @308888
     /*  308888 */   GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(308932), // Rule ID 9185 //
     /*  308893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  308908 */     // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  308911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308930 */     GIR_RootConstrainSelectedInstOperands,
     /*  308931 */     // GIR_Coverage, 9185,
     /*  308931 */     GIR_EraseRootFromParent_Done,
     /*  308932 */   // Label 4627: @308932
     /*  308932 */   GIM_Try, /*On fail goto*//*Label 4628*/ GIMT_Encode4(308979), // Rule ID 9186 //
     /*  308937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  308940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  308955 */     // (ld:{ *:[v8f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  308955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  308958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  308960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  308965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  308970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  308973 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  308977 */     GIR_RootConstrainSelectedInstOperands,
     /*  308978 */     // GIR_Coverage, 9186,
     /*  308978 */     GIR_EraseRootFromParent_Done,
     /*  308979 */   // Label 4628: @308979
     /*  308979 */   GIM_Try, /*On fail goto*//*Label 4629*/ GIMT_Encode4(309030), // Rule ID 9159 //
     /*  308984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  308987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  308991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  308995 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  308999 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309006 */     // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  309006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  309009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309028 */     GIR_RootConstrainSelectedInstOperands,
     /*  309029 */     // GIR_Coverage, 9159,
     /*  309029 */     GIR_EraseRootFromParent_Done,
     /*  309030 */   // Label 4629: @309030
     /*  309030 */   GIM_Try, /*On fail goto*//*Label 4630*/ GIMT_Encode4(309086), // Rule ID 9160 //
     /*  309035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309042 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309046 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309050 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309057 */     // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  309057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  309060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  309080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309084 */     GIR_RootConstrainSelectedInstOperands,
     /*  309085 */     // GIR_Coverage, 9160,
     /*  309085 */     GIR_EraseRootFromParent_Done,
     /*  309086 */   // Label 4630: @309086
     /*  309086 */   GIM_Try, /*On fail goto*//*Label 4631*/ GIMT_Encode4(309137), // Rule ID 9176 //
     /*  309091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  309094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309102 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309113 */     // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  309113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  309116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309135 */     GIR_RootConstrainSelectedInstOperands,
     /*  309136 */     // GIR_Coverage, 9176,
     /*  309136 */     GIR_EraseRootFromParent_Done,
     /*  309137 */   // Label 4631: @309137
     /*  309137 */   GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(309193), // Rule ID 9177 //
     /*  309142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309153 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309164 */     // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  309164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  309167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  309187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309191 */     GIR_RootConstrainSelectedInstOperands,
     /*  309192 */     // GIR_Coverage, 9177,
     /*  309192 */     GIR_EraseRootFromParent_Done,
     /*  309193 */   // Label 4632: @309193
     /*  309193 */   GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(309236), // Rule ID 9162 //
     /*  309198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  309201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309205 */     // MIs[0] sbase
     /*  309205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  309209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  309213 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309217 */     // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  309217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  309220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309222 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  309224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309234 */     GIR_RootConstrainSelectedInstOperands,
     /*  309235 */     // GIR_Coverage, 9162,
     /*  309235 */     GIR_EraseRootFromParent_Done,
     /*  309236 */   // Label 4633: @309236
     /*  309236 */   GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(309279), // Rule ID 9179 //
     /*  309241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  309244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309248 */     // MIs[0] sbase
     /*  309248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  309252 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  309256 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309260 */     // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  309260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  309263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309265 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  309267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309277 */     GIR_RootConstrainSelectedInstOperands,
     /*  309278 */     // GIR_Coverage, 9179,
     /*  309278 */     GIR_EraseRootFromParent_Done,
     /*  309279 */   // Label 4634: @309279
     /*  309279 */   GIM_Try, /*On fail goto*//*Label 4635*/ GIMT_Encode4(309326), // Rule ID 9164 //
     /*  309284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  309287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309302 */     // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  309302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec),
     /*  309305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309324 */     GIR_RootConstrainSelectedInstOperands,
     /*  309325 */     // GIR_Coverage, 9164,
     /*  309325 */     GIR_EraseRootFromParent_Done,
     /*  309326 */   // Label 4635: @309326
     /*  309326 */   GIM_Try, /*On fail goto*//*Label 4636*/ GIMT_Encode4(309378), // Rule ID 9165 //
     /*  309331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309349 */     // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  309349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  309352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  309372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309376 */     GIR_RootConstrainSelectedInstOperands,
     /*  309377 */     // GIR_Coverage, 9165,
     /*  309377 */     GIR_EraseRootFromParent_Done,
     /*  309378 */   // Label 4636: @309378
     /*  309378 */   GIM_Try, /*On fail goto*//*Label 4637*/ GIMT_Encode4(309425), // Rule ID 9181 //
     /*  309383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  309386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309394 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309401 */     // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  309401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec),
     /*  309404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309423 */     GIR_RootConstrainSelectedInstOperands,
     /*  309424 */     // GIR_Coverage, 9181,
     /*  309424 */     GIR_EraseRootFromParent_Done,
     /*  309425 */   // Label 4637: @309425
     /*  309425 */   GIM_Try, /*On fail goto*//*Label 4638*/ GIMT_Encode4(309477), // Rule ID 9182 //
     /*  309430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309448 */     // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  309448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  309451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  309471 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309475 */     GIR_RootConstrainSelectedInstOperands,
     /*  309476 */     // GIR_Coverage, 9182,
     /*  309476 */     GIR_EraseRootFromParent_Done,
     /*  309477 */   // Label 4638: @309477
     /*  309477 */   GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(309516), // Rule ID 9167 //
     /*  309482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  309485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309489 */     // MIs[0] sbase
     /*  309489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  309493 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  309497 */     // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  309497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  309500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309502 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  309504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309514 */     GIR_RootConstrainSelectedInstOperands,
     /*  309515 */     // GIR_Coverage, 9167,
     /*  309515 */     GIR_EraseRootFromParent_Done,
     /*  309516 */   // Label 4639: @309516
     /*  309516 */   GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(309555), // Rule ID 9184 //
     /*  309521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  309524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309528 */     // MIs[0] sbase
     /*  309528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  309532 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  309536 */     // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  309536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  309539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309541 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  309543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309553 */     GIR_RootConstrainSelectedInstOperands,
     /*  309554 */     // GIR_Coverage, 9184,
     /*  309554 */     GIR_EraseRootFromParent_Done,
     /*  309555 */   // Label 4640: @309555
     /*  309555 */   GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(309602), // Rule ID 9170 //
     /*  309560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  309563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309578 */     // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  309578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  309581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309600 */     GIR_RootConstrainSelectedInstOperands,
     /*  309601 */     // GIR_Coverage, 9170,
     /*  309601 */     GIR_EraseRootFromParent_Done,
     /*  309602 */   // Label 4641: @309602
     /*  309602 */   GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(309654), // Rule ID 9171 //
     /*  309607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  309610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309625 */     // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  309625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  309628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  309648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309652 */     GIR_RootConstrainSelectedInstOperands,
     /*  309653 */     // GIR_Coverage, 9171,
     /*  309653 */     GIR_EraseRootFromParent_Done,
     /*  309654 */   // Label 4642: @309654
     /*  309654 */   GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(309701), // Rule ID 9187 //
     /*  309659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  309662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309666 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309670 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309677 */     // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  309677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  309680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309695 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309699 */     GIR_RootConstrainSelectedInstOperands,
     /*  309700 */     // GIR_Coverage, 9187,
     /*  309700 */     GIR_EraseRootFromParent_Done,
     /*  309701 */   // Label 4643: @309701
     /*  309701 */   GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(309753), // Rule ID 9188 //
     /*  309706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  309709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  309724 */     // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  309724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  309727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  309747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309751 */     GIR_RootConstrainSelectedInstOperands,
     /*  309752 */     // GIR_Coverage, 9188,
     /*  309752 */     GIR_EraseRootFromParent_Done,
     /*  309753 */   // Label 4644: @309753
     /*  309753 */   GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(309789), // Rule ID 9173 //
     /*  309758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309762 */     // MIs[0] sbase
     /*  309762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  309766 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  309770 */     // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  309770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  309773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309775 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  309777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309787 */     GIR_RootConstrainSelectedInstOperands,
     /*  309788 */     // GIR_Coverage, 9173,
     /*  309788 */     GIR_EraseRootFromParent_Done,
     /*  309789 */   // Label 4645: @309789
     /*  309789 */   GIM_Try, /*On fail goto*//*Label 4646*/ GIMT_Encode4(309825), // Rule ID 9190 //
     /*  309794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  309798 */     // MIs[0] sbase
     /*  309798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  309802 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  309806 */     // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  309806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  309809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309811 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  309813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  309819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309823 */     GIR_RootConstrainSelectedInstOperands,
     /*  309824 */     // GIR_Coverage, 9190,
     /*  309824 */     GIR_EraseRootFromParent_Done,
     /*  309825 */   // Label 4646: @309825
     /*  309825 */   GIM_Reject,
     /*  309826 */ // Label 4612: @309826
     /*  309826 */ GIM_Reject,
     /*  309827 */ // Label 1139: @309827
     /*  309827 */ GIM_Try, /*On fail goto*//*Label 4647*/ GIMT_Encode4(311502),
     /*  309832 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  309835 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  309839 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  309843 */   GIM_Try, /*On fail goto*//*Label 4648*/ GIMT_Encode4(309901), // Rule ID 9093 //
     /*  309848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  309855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309859 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  309870 */     // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  309870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  309873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  309890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  309895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309899 */     GIR_RootConstrainSelectedInstOperands,
     /*  309900 */     // GIR_Coverage, 9093,
     /*  309900 */     GIR_EraseRootFromParent_Done,
     /*  309901 */   // Label 4648: @309901
     /*  309901 */   GIM_Try, /*On fail goto*//*Label 4649*/ GIMT_Encode4(309959), // Rule ID 9110 //
     /*  309906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  309913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309917 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  309921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  309928 */     // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  309928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  309931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  309948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  309953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  309957 */     GIR_RootConstrainSelectedInstOperands,
     /*  309958 */     // GIR_Coverage, 9110,
     /*  309958 */     GIR_EraseRootFromParent_Done,
     /*  309959 */   // Label 4649: @309959
     /*  309959 */   GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(310013), // Rule ID 9098 //
     /*  309964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  309967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  309971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  309975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  309982 */     // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  309982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  309985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  309987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  309992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  309997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  310002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  310007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310011 */     GIR_RootConstrainSelectedInstOperands,
     /*  310012 */     // GIR_Coverage, 9098,
     /*  310012 */     GIR_EraseRootFromParent_Done,
     /*  310013 */   // Label 4650: @310013
     /*  310013 */   GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(310067), // Rule ID 9115 //
     /*  310018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  310021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310025 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310029 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  310036 */     // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  310036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  310039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  310056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  310061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310065 */     GIR_RootConstrainSelectedInstOperands,
     /*  310066 */     // GIR_Coverage, 9115,
     /*  310066 */     GIR_EraseRootFromParent_Done,
     /*  310067 */   // Label 4651: @310067
     /*  310067 */   GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(310121), // Rule ID 9104 //
     /*  310072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  310075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  310090 */     // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  310090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  310093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  310110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  310115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310119 */     GIR_RootConstrainSelectedInstOperands,
     /*  310120 */     // GIR_Coverage, 9104,
     /*  310120 */     GIR_EraseRootFromParent_Done,
     /*  310121 */   // Label 4652: @310121
     /*  310121 */   GIM_Try, /*On fail goto*//*Label 4653*/ GIMT_Encode4(310175), // Rule ID 9121 //
     /*  310126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  310129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  310144 */     // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  310144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  310147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  310164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  310169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310173 */     GIR_RootConstrainSelectedInstOperands,
     /*  310174 */     // GIR_Coverage, 9121,
     /*  310174 */     GIR_EraseRootFromParent_Done,
     /*  310175 */   // Label 4653: @310175
     /*  310175 */   GIM_Try, /*On fail goto*//*Label 4654*/ GIMT_Encode4(310226), // Rule ID 9089 //
     /*  310180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  310183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310191 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  310202 */     // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  310205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310224 */     GIR_RootConstrainSelectedInstOperands,
     /*  310225 */     // GIR_Coverage, 9089,
     /*  310225 */     GIR_EraseRootFromParent_Done,
     /*  310226 */   // Label 4654: @310226
     /*  310226 */   GIM_Try, /*On fail goto*//*Label 4655*/ GIMT_Encode4(310277), // Rule ID 9090 //
     /*  310231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  310234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310238 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310242 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310246 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  310253 */     // (ld:{ *:[v16i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  310256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310275 */     GIR_RootConstrainSelectedInstOperands,
     /*  310276 */     // GIR_Coverage, 9090,
     /*  310276 */     GIR_EraseRootFromParent_Done,
     /*  310277 */   // Label 4655: @310277
     /*  310277 */   GIM_Try, /*On fail goto*//*Label 4656*/ GIMT_Encode4(310328), // Rule ID 9106 //
     /*  310282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  310285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310293 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  310304 */     // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  310307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310326 */     GIR_RootConstrainSelectedInstOperands,
     /*  310327 */     // GIR_Coverage, 9106,
     /*  310327 */     GIR_EraseRootFromParent_Done,
     /*  310328 */   // Label 4656: @310328
     /*  310328 */   GIM_Try, /*On fail goto*//*Label 4657*/ GIMT_Encode4(310379), // Rule ID 9107 //
     /*  310333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  310336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310344 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  310355 */     // (ld:{ *:[v16f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  310358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310377 */     GIR_RootConstrainSelectedInstOperands,
     /*  310378 */     // GIR_Coverage, 9107,
     /*  310378 */     GIR_EraseRootFromParent_Done,
     /*  310379 */   // Label 4657: @310379
     /*  310379 */   GIM_Try, /*On fail goto*//*Label 4658*/ GIMT_Encode4(310426), // Rule ID 9095 //
     /*  310384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  310387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  310402 */     // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  310405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310420 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310424 */     GIR_RootConstrainSelectedInstOperands,
     /*  310425 */     // GIR_Coverage, 9095,
     /*  310425 */     GIR_EraseRootFromParent_Done,
     /*  310426 */   // Label 4658: @310426
     /*  310426 */   GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(310473), // Rule ID 9112 //
     /*  310431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  310434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  310449 */     // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  310452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310471 */     GIR_RootConstrainSelectedInstOperands,
     /*  310472 */     // GIR_Coverage, 9112,
     /*  310472 */     GIR_EraseRootFromParent_Done,
     /*  310473 */   // Label 4659: @310473
     /*  310473 */   GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(310517), // Rule ID 9100 //
     /*  310478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  310493 */     // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  310496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310515 */     GIR_RootConstrainSelectedInstOperands,
     /*  310516 */     // GIR_Coverage, 9100,
     /*  310516 */     GIR_EraseRootFromParent_Done,
     /*  310517 */   // Label 4660: @310517
     /*  310517 */   GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(310564), // Rule ID 9101 //
     /*  310522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  310525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310533 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  310540 */     // (ld:{ *:[v16i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  310543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310562 */     GIR_RootConstrainSelectedInstOperands,
     /*  310563 */     // GIR_Coverage, 9101,
     /*  310563 */     GIR_EraseRootFromParent_Done,
     /*  310564 */   // Label 4661: @310564
     /*  310564 */   GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(310608), // Rule ID 9117 //
     /*  310569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  310584 */     // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  310587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310606 */     GIR_RootConstrainSelectedInstOperands,
     /*  310607 */     // GIR_Coverage, 9117,
     /*  310607 */     GIR_EraseRootFromParent_Done,
     /*  310608 */   // Label 4662: @310608
     /*  310608 */   GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(310655), // Rule ID 9118 //
     /*  310613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  310616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  310631 */     // (ld:{ *:[v16f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  310631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
     /*  310634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  310646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310653 */     GIR_RootConstrainSelectedInstOperands,
     /*  310654 */     // GIR_Coverage, 9118,
     /*  310654 */     GIR_EraseRootFromParent_Done,
     /*  310655 */   // Label 4663: @310655
     /*  310655 */   GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(310706), // Rule ID 9091 //
     /*  310660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  310663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310671 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  310682 */     // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  310682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  310685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310704 */     GIR_RootConstrainSelectedInstOperands,
     /*  310705 */     // GIR_Coverage, 9091,
     /*  310705 */     GIR_EraseRootFromParent_Done,
     /*  310706 */   // Label 4664: @310706
     /*  310706 */   GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(310762), // Rule ID 9092 //
     /*  310711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  310714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310718 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310722 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  310733 */     // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  310733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  310736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  310756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310760 */     GIR_RootConstrainSelectedInstOperands,
     /*  310761 */     // GIR_Coverage, 9092,
     /*  310761 */     GIR_EraseRootFromParent_Done,
     /*  310762 */   // Label 4665: @310762
     /*  310762 */   GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(310813), // Rule ID 9108 //
     /*  310767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  310770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310778 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310782 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  310789 */     // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  310789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  310792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310811 */     GIR_RootConstrainSelectedInstOperands,
     /*  310812 */     // GIR_Coverage, 9108,
     /*  310812 */     GIR_EraseRootFromParent_Done,
     /*  310813 */   // Label 4666: @310813
     /*  310813 */   GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(310869), // Rule ID 9109 //
     /*  310818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  310821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310829 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  310840 */     // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  310840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  310843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  310863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310867 */     GIR_RootConstrainSelectedInstOperands,
     /*  310868 */     // GIR_Coverage, 9109,
     /*  310868 */     GIR_EraseRootFromParent_Done,
     /*  310869 */   // Label 4667: @310869
     /*  310869 */   GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(310912), // Rule ID 9094 //
     /*  310874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  310877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310881 */     // MIs[0] sbase
     /*  310881 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  310885 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  310889 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310893 */     // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  310893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  310896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310898 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  310900 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310910 */     GIR_RootConstrainSelectedInstOperands,
     /*  310911 */     // GIR_Coverage, 9094,
     /*  310911 */     GIR_EraseRootFromParent_Done,
     /*  310912 */   // Label 4668: @310912
     /*  310912 */   GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(310955), // Rule ID 9111 //
     /*  310917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  310920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310924 */     // MIs[0] sbase
     /*  310924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  310928 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  310932 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  310936 */     // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  310936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  310939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310941 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  310943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  310953 */     GIR_RootConstrainSelectedInstOperands,
     /*  310954 */     // GIR_Coverage, 9111,
     /*  310954 */     GIR_EraseRootFromParent_Done,
     /*  310955 */   // Label 4669: @310955
     /*  310955 */   GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(311002), // Rule ID 9096 //
     /*  310960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  310963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  310967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  310971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  310978 */     // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  310978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec),
     /*  310981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  310983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  310988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  310993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  310996 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311000 */     GIR_RootConstrainSelectedInstOperands,
     /*  311001 */     // GIR_Coverage, 9096,
     /*  311001 */     GIR_EraseRootFromParent_Done,
     /*  311002 */   // Label 4670: @311002
     /*  311002 */   GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(311054), // Rule ID 9097 //
     /*  311007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  311010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311014 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311018 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311025 */     // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  311025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  311028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  311048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311052 */     GIR_RootConstrainSelectedInstOperands,
     /*  311053 */     // GIR_Coverage, 9097,
     /*  311053 */     GIR_EraseRootFromParent_Done,
     /*  311054 */   // Label 4671: @311054
     /*  311054 */   GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(311101), // Rule ID 9113 //
     /*  311059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  311062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311066 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311070 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311077 */     // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  311077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec),
     /*  311080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311099 */     GIR_RootConstrainSelectedInstOperands,
     /*  311100 */     // GIR_Coverage, 9113,
     /*  311100 */     GIR_EraseRootFromParent_Done,
     /*  311101 */   // Label 4672: @311101
     /*  311101 */   GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(311153), // Rule ID 9114 //
     /*  311106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  311109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311124 */     // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  311124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec),
     /*  311127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  311147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311151 */     GIR_RootConstrainSelectedInstOperands,
     /*  311152 */     // GIR_Coverage, 9114,
     /*  311152 */     GIR_EraseRootFromParent_Done,
     /*  311153 */   // Label 4673: @311153
     /*  311153 */   GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(311192), // Rule ID 9099 //
     /*  311158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  311161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311165 */     // MIs[0] sbase
     /*  311165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  311169 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  311173 */     // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  311173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  311176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311178 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  311180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311190 */     GIR_RootConstrainSelectedInstOperands,
     /*  311191 */     // GIR_Coverage, 9099,
     /*  311191 */     GIR_EraseRootFromParent_Done,
     /*  311192 */   // Label 4674: @311192
     /*  311192 */   GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(311231), // Rule ID 9116 //
     /*  311197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  311200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311204 */     // MIs[0] sbase
     /*  311204 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  311208 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  311212 */     // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ec:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  311212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec),
     /*  311215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311217 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  311219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311225 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311229 */     GIR_RootConstrainSelectedInstOperands,
     /*  311230 */     // GIR_Coverage, 9116,
     /*  311230 */     GIR_EraseRootFromParent_Done,
     /*  311231 */   // Label 4675: @311231
     /*  311231 */   GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(311278), // Rule ID 9102 //
     /*  311236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  311239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311254 */     // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  311254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  311257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311276 */     GIR_RootConstrainSelectedInstOperands,
     /*  311277 */     // GIR_Coverage, 9102,
     /*  311277 */     GIR_EraseRootFromParent_Done,
     /*  311278 */   // Label 4676: @311278
     /*  311278 */   GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(311330), // Rule ID 9103 //
     /*  311283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  311286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311290 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311294 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311301 */     // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  311301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  311304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  311324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311328 */     GIR_RootConstrainSelectedInstOperands,
     /*  311329 */     // GIR_Coverage, 9103,
     /*  311329 */     GIR_EraseRootFromParent_Done,
     /*  311330 */   // Label 4677: @311330
     /*  311330 */   GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(311377), // Rule ID 9119 //
     /*  311335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  311338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311353 */     // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  311353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
     /*  311356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311371 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311375 */     GIR_RootConstrainSelectedInstOperands,
     /*  311376 */     // GIR_Coverage, 9119,
     /*  311376 */     GIR_EraseRootFromParent_Done,
     /*  311377 */   // Label 4678: @311377
     /*  311377 */   GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(311429), // Rule ID 9120 //
     /*  311382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  311385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  311400 */     // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  311400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
     /*  311403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  311423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311427 */     GIR_RootConstrainSelectedInstOperands,
     /*  311428 */     // GIR_Coverage, 9120,
     /*  311428 */     GIR_EraseRootFromParent_Done,
     /*  311429 */   // Label 4679: @311429
     /*  311429 */   GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(311465), // Rule ID 9105 //
     /*  311434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311438 */     // MIs[0] sbase
     /*  311438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  311442 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  311446 */     // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  311446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  311449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311451 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  311453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311463 */     GIR_RootConstrainSelectedInstOperands,
     /*  311464 */     // GIR_Coverage, 9105,
     /*  311464 */     GIR_EraseRootFromParent_Done,
     /*  311465 */   // Label 4680: @311465
     /*  311465 */   GIM_Try, /*On fail goto*//*Label 4681*/ GIMT_Encode4(311501), // Rule ID 9122 //
     /*  311470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
     /*  311474 */     // MIs[0] sbase
     /*  311474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  311478 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  311482 */     // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  311482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
     /*  311485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311487 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  311489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311499 */     GIR_RootConstrainSelectedInstOperands,
     /*  311500 */     // GIR_Coverage, 9122,
     /*  311500 */     GIR_EraseRootFromParent_Done,
     /*  311501 */   // Label 4681: @311501
     /*  311501 */   GIM_Reject,
     /*  311502 */ // Label 4647: @311502
     /*  311502 */ GIM_Reject,
     /*  311503 */ // Label 1140: @311503
     /*  311503 */ GIM_Try, /*On fail goto*//*Label 4682*/ GIMT_Encode4(313178),
     /*  311508 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  311511 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  311515 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  311519 */   GIM_Try, /*On fail goto*//*Label 4683*/ GIMT_Encode4(311577), // Rule ID 9127 //
     /*  311524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  311527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311535 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  311539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  311546 */     // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  311546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  311549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  311566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  311571 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311575 */     GIR_RootConstrainSelectedInstOperands,
     /*  311576 */     // GIR_Coverage, 9127,
     /*  311576 */     GIR_EraseRootFromParent_Done,
     /*  311577 */   // Label 4683: @311577
     /*  311577 */   GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(311635), // Rule ID 9144 //
     /*  311582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  311585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311593 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  311597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  311604 */     // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  311604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  311607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  311624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  311629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311633 */     GIR_RootConstrainSelectedInstOperands,
     /*  311634 */     // GIR_Coverage, 9144,
     /*  311634 */     GIR_EraseRootFromParent_Done,
     /*  311635 */   // Label 4684: @311635
     /*  311635 */   GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(311689), // Rule ID 9132 //
     /*  311640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  311643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  311658 */     // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  311658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  311661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  311678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  311683 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311687 */     GIR_RootConstrainSelectedInstOperands,
     /*  311688 */     // GIR_Coverage, 9132,
     /*  311688 */     GIR_EraseRootFromParent_Done,
     /*  311689 */   // Label 4685: @311689
     /*  311689 */   GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(311743), // Rule ID 9149 //
     /*  311694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  311697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311705 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  311712 */     // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  311712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  311715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  311732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  311737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311741 */     GIR_RootConstrainSelectedInstOperands,
     /*  311742 */     // GIR_Coverage, 9149,
     /*  311742 */     GIR_EraseRootFromParent_Done,
     /*  311743 */   // Label 4686: @311743
     /*  311743 */   GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(311797), // Rule ID 9138 //
     /*  311748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  311751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311755 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  311766 */     // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  311766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  311769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  311786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  311791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311795 */     GIR_RootConstrainSelectedInstOperands,
     /*  311796 */     // GIR_Coverage, 9138,
     /*  311796 */     GIR_EraseRootFromParent_Done,
     /*  311797 */   // Label 4687: @311797
     /*  311797 */   GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(311851), // Rule ID 9155 //
     /*  311802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  311805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  311820 */     // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  311820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  311823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  311835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  311840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  311845 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311849 */     GIR_RootConstrainSelectedInstOperands,
     /*  311850 */     // GIR_Coverage, 9155,
     /*  311850 */     GIR_EraseRootFromParent_Done,
     /*  311851 */   // Label 4688: @311851
     /*  311851 */   GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(311902), // Rule ID 9123 //
     /*  311856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  311859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311867 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  311871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  311878 */     // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  311878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  311881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  311893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311900 */     GIR_RootConstrainSelectedInstOperands,
     /*  311901 */     // GIR_Coverage, 9123,
     /*  311901 */     GIR_EraseRootFromParent_Done,
     /*  311902 */   // Label 4689: @311902
     /*  311902 */   GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(311953), // Rule ID 9124 //
     /*  311907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  311910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311918 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  311922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  311929 */     // (ld:{ *:[v16i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  311929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  311932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  311944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  311951 */     GIR_RootConstrainSelectedInstOperands,
     /*  311952 */     // GIR_Coverage, 9124,
     /*  311952 */     GIR_EraseRootFromParent_Done,
     /*  311953 */   // Label 4690: @311953
     /*  311953 */   GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(312004), // Rule ID 9140 //
     /*  311958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  311961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  311965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  311969 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  311973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  311980 */     // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  311980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  311983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  311985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  311990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  311995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  311998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312002 */     GIR_RootConstrainSelectedInstOperands,
     /*  312003 */     // GIR_Coverage, 9140,
     /*  312003 */     GIR_EraseRootFromParent_Done,
     /*  312004 */   // Label 4691: @312004
     /*  312004 */   GIM_Try, /*On fail goto*//*Label 4692*/ GIMT_Encode4(312055), // Rule ID 9141 //
     /*  312009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  312012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312020 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  312031 */     // (ld:{ *:[v16f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  312034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312053 */     GIR_RootConstrainSelectedInstOperands,
     /*  312054 */     // GIR_Coverage, 9141,
     /*  312054 */     GIR_EraseRootFromParent_Done,
     /*  312055 */   // Label 4692: @312055
     /*  312055 */   GIM_Try, /*On fail goto*//*Label 4693*/ GIMT_Encode4(312102), // Rule ID 9129 //
     /*  312060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  312063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  312078 */     // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  312081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312100 */     GIR_RootConstrainSelectedInstOperands,
     /*  312101 */     // GIR_Coverage, 9129,
     /*  312101 */     GIR_EraseRootFromParent_Done,
     /*  312102 */   // Label 4693: @312102
     /*  312102 */   GIM_Try, /*On fail goto*//*Label 4694*/ GIMT_Encode4(312149), // Rule ID 9146 //
     /*  312107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  312110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  312125 */     // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  312128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312147 */     GIR_RootConstrainSelectedInstOperands,
     /*  312148 */     // GIR_Coverage, 9146,
     /*  312148 */     GIR_EraseRootFromParent_Done,
     /*  312149 */   // Label 4694: @312149
     /*  312149 */   GIM_Try, /*On fail goto*//*Label 4695*/ GIMT_Encode4(312193), // Rule ID 9134 //
     /*  312154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312158 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312162 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  312169 */     // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  312172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312191 */     GIR_RootConstrainSelectedInstOperands,
     /*  312192 */     // GIR_Coverage, 9134,
     /*  312192 */     GIR_EraseRootFromParent_Done,
     /*  312193 */   // Label 4695: @312193
     /*  312193 */   GIM_Try, /*On fail goto*//*Label 4696*/ GIMT_Encode4(312240), // Rule ID 9135 //
     /*  312198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  312201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  312216 */     // (ld:{ *:[v16i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  312219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312238 */     GIR_RootConstrainSelectedInstOperands,
     /*  312239 */     // GIR_Coverage, 9135,
     /*  312239 */     GIR_EraseRootFromParent_Done,
     /*  312240 */   // Label 4696: @312240
     /*  312240 */   GIM_Try, /*On fail goto*//*Label 4697*/ GIMT_Encode4(312284), // Rule ID 9151 //
     /*  312245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312249 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312253 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  312260 */     // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  312263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312282 */     GIR_RootConstrainSelectedInstOperands,
     /*  312283 */     // GIR_Coverage, 9151,
     /*  312283 */     GIR_EraseRootFromParent_Done,
     /*  312284 */   // Label 4697: @312284
     /*  312284 */   GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(312331), // Rule ID 9152 //
     /*  312289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  312292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  312307 */     // (ld:{ *:[v16f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  312307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  312310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  312322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312329 */     GIR_RootConstrainSelectedInstOperands,
     /*  312330 */     // GIR_Coverage, 9152,
     /*  312330 */     GIR_EraseRootFromParent_Done,
     /*  312331 */   // Label 4698: @312331
     /*  312331 */   GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(312382), // Rule ID 9125 //
     /*  312336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  312339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312347 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312358 */     // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  312358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  312361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312380 */     GIR_RootConstrainSelectedInstOperands,
     /*  312381 */     // GIR_Coverage, 9125,
     /*  312381 */     GIR_EraseRootFromParent_Done,
     /*  312382 */   // Label 4699: @312382
     /*  312382 */   GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(312438), // Rule ID 9126 //
     /*  312387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  312390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312394 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312398 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312409 */     // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  312409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  312412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  312432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312436 */     GIR_RootConstrainSelectedInstOperands,
     /*  312437 */     // GIR_Coverage, 9126,
     /*  312437 */     GIR_EraseRootFromParent_Done,
     /*  312438 */   // Label 4700: @312438
     /*  312438 */   GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(312489), // Rule ID 9142 //
     /*  312443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  312446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312454 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312465 */     // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  312465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  312468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312487 */     GIR_RootConstrainSelectedInstOperands,
     /*  312488 */     // GIR_Coverage, 9142,
     /*  312488 */     GIR_EraseRootFromParent_Done,
     /*  312489 */   // Label 4701: @312489
     /*  312489 */   GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(312545), // Rule ID 9143 //
     /*  312494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  312497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312505 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312509 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312516 */     // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  312516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  312519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  312539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312543 */     GIR_RootConstrainSelectedInstOperands,
     /*  312544 */     // GIR_Coverage, 9143,
     /*  312544 */     GIR_EraseRootFromParent_Done,
     /*  312545 */   // Label 4702: @312545
     /*  312545 */   GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(312588), // Rule ID 9128 //
     /*  312550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  312553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312557 */     // MIs[0] sbase
     /*  312557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  312561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  312565 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312569 */     // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  312569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  312572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312574 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  312576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312586 */     GIR_RootConstrainSelectedInstOperands,
     /*  312587 */     // GIR_Coverage, 9128,
     /*  312587 */     GIR_EraseRootFromParent_Done,
     /*  312588 */   // Label 4703: @312588
     /*  312588 */   GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(312631), // Rule ID 9145 //
     /*  312593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  312596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312600 */     // MIs[0] sbase
     /*  312600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  312604 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  312608 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  312612 */     // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  312612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  312615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312617 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  312619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312629 */     GIR_RootConstrainSelectedInstOperands,
     /*  312630 */     // GIR_Coverage, 9145,
     /*  312630 */     GIR_EraseRootFromParent_Done,
     /*  312631 */   // Label 4704: @312631
     /*  312631 */   GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(312678), // Rule ID 9130 //
     /*  312636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  312639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312654 */     // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  312654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec),
     /*  312657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312676 */     GIR_RootConstrainSelectedInstOperands,
     /*  312677 */     // GIR_Coverage, 9130,
     /*  312677 */     GIR_EraseRootFromParent_Done,
     /*  312678 */   // Label 4705: @312678
     /*  312678 */   GIM_Try, /*On fail goto*//*Label 4706*/ GIMT_Encode4(312730), // Rule ID 9131 //
     /*  312683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  312686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312690 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312701 */     // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  312701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  312704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  312724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312728 */     GIR_RootConstrainSelectedInstOperands,
     /*  312729 */     // GIR_Coverage, 9131,
     /*  312729 */     GIR_EraseRootFromParent_Done,
     /*  312730 */   // Label 4706: @312730
     /*  312730 */   GIM_Try, /*On fail goto*//*Label 4707*/ GIMT_Encode4(312777), // Rule ID 9147 //
     /*  312735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  312738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312753 */     // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  312753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec),
     /*  312756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312775 */     GIR_RootConstrainSelectedInstOperands,
     /*  312776 */     // GIR_Coverage, 9147,
     /*  312776 */     GIR_EraseRootFromParent_Done,
     /*  312777 */   // Label 4707: @312777
     /*  312777 */   GIM_Try, /*On fail goto*//*Label 4708*/ GIMT_Encode4(312829), // Rule ID 9148 //
     /*  312782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  312785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312800 */     // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  312800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  312803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  312823 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312827 */     GIR_RootConstrainSelectedInstOperands,
     /*  312828 */     // GIR_Coverage, 9148,
     /*  312828 */     GIR_EraseRootFromParent_Done,
     /*  312829 */   // Label 4708: @312829
     /*  312829 */   GIM_Try, /*On fail goto*//*Label 4709*/ GIMT_Encode4(312868), // Rule ID 9133 //
     /*  312834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  312837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312841 */     // MIs[0] sbase
     /*  312841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  312845 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  312849 */     // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  312849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  312852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312854 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  312856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312866 */     GIR_RootConstrainSelectedInstOperands,
     /*  312867 */     // GIR_Coverage, 9133,
     /*  312867 */     GIR_EraseRootFromParent_Done,
     /*  312868 */   // Label 4709: @312868
     /*  312868 */   GIM_Try, /*On fail goto*//*Label 4710*/ GIMT_Encode4(312907), // Rule ID 9150 //
     /*  312873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  312876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312880 */     // MIs[0] sbase
     /*  312880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  312884 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  312888 */     // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  312888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  312891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312893 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  312895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312905 */     GIR_RootConstrainSelectedInstOperands,
     /*  312906 */     // GIR_Coverage, 9150,
     /*  312906 */     GIR_EraseRootFromParent_Done,
     /*  312907 */   // Label 4710: @312907
     /*  312907 */   GIM_Try, /*On fail goto*//*Label 4711*/ GIMT_Encode4(312954), // Rule ID 9136 //
     /*  312912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  312915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312930 */     // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  312930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  312933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  312952 */     GIR_RootConstrainSelectedInstOperands,
     /*  312953 */     // GIR_Coverage, 9136,
     /*  312953 */     GIR_EraseRootFromParent_Done,
     /*  312954 */   // Label 4711: @312954
     /*  312954 */   GIM_Try, /*On fail goto*//*Label 4712*/ GIMT_Encode4(313006), // Rule ID 9137 //
     /*  312959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  312962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  312966 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  312970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  312977 */     // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  312977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  312980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  312982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  312987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  312992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  312995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  313000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313004 */     GIR_RootConstrainSelectedInstOperands,
     /*  313005 */     // GIR_Coverage, 9137,
     /*  313005 */     GIR_EraseRootFromParent_Done,
     /*  313006 */   // Label 4712: @313006
     /*  313006 */   GIM_Try, /*On fail goto*//*Label 4713*/ GIMT_Encode4(313053), // Rule ID 9153 //
     /*  313011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  313014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  313029 */     // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  313029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  313032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313051 */     GIR_RootConstrainSelectedInstOperands,
     /*  313052 */     // GIR_Coverage, 9153,
     /*  313052 */     GIR_EraseRootFromParent_Done,
     /*  313053 */   // Label 4713: @313053
     /*  313053 */   GIM_Try, /*On fail goto*//*Label 4714*/ GIMT_Encode4(313105), // Rule ID 9154 //
     /*  313058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  313061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  313076 */     // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  313076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  313079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  313099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313103 */     GIR_RootConstrainSelectedInstOperands,
     /*  313104 */     // GIR_Coverage, 9154,
     /*  313104 */     GIR_EraseRootFromParent_Done,
     /*  313105 */   // Label 4714: @313105
     /*  313105 */   GIM_Try, /*On fail goto*//*Label 4715*/ GIMT_Encode4(313141), // Rule ID 9139 //
     /*  313110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313114 */     // MIs[0] sbase
     /*  313114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  313118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  313122 */     // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  313122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  313125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313127 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  313129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313139 */     GIR_RootConstrainSelectedInstOperands,
     /*  313140 */     // GIR_Coverage, 9139,
     /*  313140 */     GIR_EraseRootFromParent_Done,
     /*  313141 */   // Label 4715: @313141
     /*  313141 */   GIM_Try, /*On fail goto*//*Label 4716*/ GIMT_Encode4(313177), // Rule ID 9156 //
     /*  313146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313150 */     // MIs[0] sbase
     /*  313150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  313154 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  313158 */     // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  313158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  313161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313163 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  313165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313171 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313175 */     GIR_RootConstrainSelectedInstOperands,
     /*  313176 */     // GIR_Coverage, 9156,
     /*  313176 */     GIR_EraseRootFromParent_Done,
     /*  313177 */   // Label 4716: @313177
     /*  313177 */   GIM_Reject,
     /*  313178 */ // Label 4682: @313178
     /*  313178 */ GIM_Reject,
     /*  313179 */ // Label 1141: @313179
     /*  313179 */ GIM_Try, /*On fail goto*//*Label 4717*/ GIMT_Encode4(314854),
     /*  313184 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  313187 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  313191 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
     /*  313195 */   GIM_Try, /*On fail goto*//*Label 4718*/ GIMT_Encode4(313253), // Rule ID 9195 //
     /*  313200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  313203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313211 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  313215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  313222 */     // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  313222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  313225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  313242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  313247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313251 */     GIR_RootConstrainSelectedInstOperands,
     /*  313252 */     // GIR_Coverage, 9195,
     /*  313252 */     GIR_EraseRootFromParent_Done,
     /*  313253 */   // Label 4718: @313253
     /*  313253 */   GIM_Try, /*On fail goto*//*Label 4719*/ GIMT_Encode4(313311), // Rule ID 9212 //
     /*  313258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  313261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313269 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  313273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  313280 */     // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  313280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  313283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  313300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  313305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313309 */     GIR_RootConstrainSelectedInstOperands,
     /*  313310 */     // GIR_Coverage, 9212,
     /*  313310 */     GIR_EraseRootFromParent_Done,
     /*  313311 */   // Label 4719: @313311
     /*  313311 */   GIM_Try, /*On fail goto*//*Label 4720*/ GIMT_Encode4(313365), // Rule ID 9200 //
     /*  313316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  313319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  313334 */     // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  313334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  313337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  313354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  313359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313363 */     GIR_RootConstrainSelectedInstOperands,
     /*  313364 */     // GIR_Coverage, 9200,
     /*  313364 */     GIR_EraseRootFromParent_Done,
     /*  313365 */   // Label 4720: @313365
     /*  313365 */   GIM_Try, /*On fail goto*//*Label 4721*/ GIMT_Encode4(313419), // Rule ID 9217 //
     /*  313370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  313373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  313388 */     // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  313388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  313391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  313408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  313413 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313417 */     GIR_RootConstrainSelectedInstOperands,
     /*  313418 */     // GIR_Coverage, 9217,
     /*  313418 */     GIR_EraseRootFromParent_Done,
     /*  313419 */   // Label 4721: @313419
     /*  313419 */   GIM_Try, /*On fail goto*//*Label 4722*/ GIMT_Encode4(313473), // Rule ID 9206 //
     /*  313424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  313427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  313442 */     // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  313442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  313445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  313462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  313467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313471 */     GIR_RootConstrainSelectedInstOperands,
     /*  313472 */     // GIR_Coverage, 9206,
     /*  313472 */     GIR_EraseRootFromParent_Done,
     /*  313473 */   // Label 4722: @313473
     /*  313473 */   GIM_Try, /*On fail goto*//*Label 4723*/ GIMT_Encode4(313527), // Rule ID 9223 //
     /*  313478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  313481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  313496 */     // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  313496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  313499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  313511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  313516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  313521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313525 */     GIR_RootConstrainSelectedInstOperands,
     /*  313526 */     // GIR_Coverage, 9223,
     /*  313526 */     GIR_EraseRootFromParent_Done,
     /*  313527 */   // Label 4723: @313527
     /*  313527 */   GIM_Try, /*On fail goto*//*Label 4724*/ GIMT_Encode4(313578), // Rule ID 9191 //
     /*  313532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  313535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313543 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  313547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  313554 */     // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  313557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313576 */     GIR_RootConstrainSelectedInstOperands,
     /*  313577 */     // GIR_Coverage, 9191,
     /*  313577 */     GIR_EraseRootFromParent_Done,
     /*  313578 */   // Label 4724: @313578
     /*  313578 */   GIM_Try, /*On fail goto*//*Label 4725*/ GIMT_Encode4(313629), // Rule ID 9192 //
     /*  313583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  313586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313594 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  313598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  313605 */     // (ld:{ *:[v32i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  313608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313627 */     GIR_RootConstrainSelectedInstOperands,
     /*  313628 */     // GIR_Coverage, 9192,
     /*  313628 */     GIR_EraseRootFromParent_Done,
     /*  313629 */   // Label 4725: @313629
     /*  313629 */   GIM_Try, /*On fail goto*//*Label 4726*/ GIMT_Encode4(313680), // Rule ID 9208 //
     /*  313634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  313637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313641 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313645 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  313649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  313656 */     // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  313659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313678 */     GIR_RootConstrainSelectedInstOperands,
     /*  313679 */     // GIR_Coverage, 9208,
     /*  313679 */     GIR_EraseRootFromParent_Done,
     /*  313680 */   // Label 4726: @313680
     /*  313680 */   GIM_Try, /*On fail goto*//*Label 4727*/ GIMT_Encode4(313731), // Rule ID 9209 //
     /*  313685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only),
     /*  313688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313692 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313696 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  313700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  313707 */     // (ld:{ *:[v32f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  313710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313729 */     GIR_RootConstrainSelectedInstOperands,
     /*  313730 */     // GIR_Coverage, 9209,
     /*  313730 */     GIR_EraseRootFromParent_Done,
     /*  313731 */   // Label 4727: @313731
     /*  313731 */   GIM_Try, /*On fail goto*//*Label 4728*/ GIMT_Encode4(313778), // Rule ID 9197 //
     /*  313736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  313739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  313754 */     // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  313757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313776 */     GIR_RootConstrainSelectedInstOperands,
     /*  313777 */     // GIR_Coverage, 9197,
     /*  313777 */     GIR_EraseRootFromParent_Done,
     /*  313778 */   // Label 4728: @313778
     /*  313778 */   GIM_Try, /*On fail goto*//*Label 4729*/ GIMT_Encode4(313825), // Rule ID 9214 //
     /*  313783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  313786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  313801 */     // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  313804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313823 */     GIR_RootConstrainSelectedInstOperands,
     /*  313824 */     // GIR_Coverage, 9214,
     /*  313824 */     GIR_EraseRootFromParent_Done,
     /*  313825 */   // Label 4729: @313825
     /*  313825 */   GIM_Try, /*On fail goto*//*Label 4730*/ GIMT_Encode4(313869), // Rule ID 9202 //
     /*  313830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  313845 */     // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  313848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313867 */     GIR_RootConstrainSelectedInstOperands,
     /*  313868 */     // GIR_Coverage, 9202,
     /*  313868 */     GIR_EraseRootFromParent_Done,
     /*  313869 */   // Label 4730: @313869
     /*  313869 */   GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(313916), // Rule ID 9203 //
     /*  313874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  313877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313881 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  313892 */     // (ld:{ *:[v32i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  313895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313914 */     GIR_RootConstrainSelectedInstOperands,
     /*  313915 */     // GIR_Coverage, 9203,
     /*  313915 */     GIR_EraseRootFromParent_Done,
     /*  313916 */   // Label 4731: @313916
     /*  313916 */   GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(313960), // Rule ID 9219 //
     /*  313921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  313936 */     // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  313939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  313954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  313958 */     GIR_RootConstrainSelectedInstOperands,
     /*  313959 */     // GIR_Coverage, 9219,
     /*  313959 */     GIR_EraseRootFromParent_Done,
     /*  313960 */   // Label 4732: @313960
     /*  313960 */   GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(314007), // Rule ID 9220 //
     /*  313965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
     /*  313968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  313972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  313976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
     /*  313983 */     // (ld:{ *:[v32f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  313983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
     /*  313986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  313988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  313993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  313998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314005 */     GIR_RootConstrainSelectedInstOperands,
     /*  314006 */     // GIR_Coverage, 9220,
     /*  314006 */     GIR_EraseRootFromParent_Done,
     /*  314007 */   // Label 4733: @314007
     /*  314007 */   GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(314058), // Rule ID 9193 //
     /*  314012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  314015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314019 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314023 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  314027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314034 */     // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  314034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  314037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314056 */     GIR_RootConstrainSelectedInstOperands,
     /*  314057 */     // GIR_Coverage, 9193,
     /*  314057 */     GIR_EraseRootFromParent_Done,
     /*  314058 */   // Label 4734: @314058
     /*  314058 */   GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(314114), // Rule ID 9194 //
     /*  314063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  314066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314074 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  314078 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314085 */     // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  314085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  314088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  314108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314112 */     GIR_RootConstrainSelectedInstOperands,
     /*  314113 */     // GIR_Coverage, 9194,
     /*  314113 */     GIR_EraseRootFromParent_Done,
     /*  314114 */   // Label 4735: @314114
     /*  314114 */   GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(314165), // Rule ID 9210 //
     /*  314119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  314122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314130 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  314134 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314141 */     // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  314141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  314144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314163 */     GIR_RootConstrainSelectedInstOperands,
     /*  314164 */     // GIR_Coverage, 9210,
     /*  314164 */     GIR_EraseRootFromParent_Done,
     /*  314165 */   // Label 4736: @314165
     /*  314165 */   GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(314221), // Rule ID 9211 //
     /*  314170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  314173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314181 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  314185 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314192 */     // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  314192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  314195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  314215 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314219 */     GIR_RootConstrainSelectedInstOperands,
     /*  314220 */     // GIR_Coverage, 9211,
     /*  314220 */     GIR_EraseRootFromParent_Done,
     /*  314221 */   // Label 4737: @314221
     /*  314221 */   GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(314264), // Rule ID 9196 //
     /*  314226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  314229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314233 */     // MIs[0] sbase
     /*  314233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  314237 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  314241 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  314245 */     // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  314245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  314248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314250 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  314252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314262 */     GIR_RootConstrainSelectedInstOperands,
     /*  314263 */     // GIR_Coverage, 9196,
     /*  314263 */     GIR_EraseRootFromParent_Done,
     /*  314264 */   // Label 4738: @314264
     /*  314264 */   GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(314307), // Rule ID 9213 //
     /*  314269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  314272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314276 */     // MIs[0] sbase
     /*  314276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  314280 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  314284 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load),
     /*  314288 */     // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  314288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  314291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314293 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  314295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314305 */     GIR_RootConstrainSelectedInstOperands,
     /*  314306 */     // GIR_Coverage, 9213,
     /*  314306 */     GIR_EraseRootFromParent_Done,
     /*  314307 */   // Label 4739: @314307
     /*  314307 */   GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(314354), // Rule ID 9198 //
     /*  314312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  314315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314330 */     // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  314330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec),
     /*  314333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314352 */     GIR_RootConstrainSelectedInstOperands,
     /*  314353 */     // GIR_Coverage, 9198,
     /*  314353 */     GIR_EraseRootFromParent_Done,
     /*  314354 */   // Label 4740: @314354
     /*  314354 */   GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(314406), // Rule ID 9199 //
     /*  314359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  314362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314377 */     // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  314377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  314380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  314400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314404 */     GIR_RootConstrainSelectedInstOperands,
     /*  314405 */     // GIR_Coverage, 9199,
     /*  314405 */     GIR_EraseRootFromParent_Done,
     /*  314406 */   // Label 4741: @314406
     /*  314406 */   GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(314453), // Rule ID 9215 //
     /*  314411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus),
     /*  314414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314429 */     // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  314429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec),
     /*  314432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314451 */     GIR_RootConstrainSelectedInstOperands,
     /*  314452 */     // GIR_Coverage, 9215,
     /*  314452 */     GIR_EraseRootFromParent_Done,
     /*  314453 */   // Label 4742: @314453
     /*  314453 */   GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(314505), // Rule ID 9216 //
     /*  314458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus),
     /*  314461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314476 */     // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  314476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec),
     /*  314479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  314499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314503 */     GIR_RootConstrainSelectedInstOperands,
     /*  314504 */     // GIR_Coverage, 9216,
     /*  314504 */     GIR_EraseRootFromParent_Done,
     /*  314505 */   // Label 4743: @314505
     /*  314505 */   GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(314544), // Rule ID 9201 //
     /*  314510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  314513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314517 */     // MIs[0] sbase
     /*  314517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  314521 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  314525 */     // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  314525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  314528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314530 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  314532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314542 */     GIR_RootConstrainSelectedInstOperands,
     /*  314543 */     // GIR_Coverage, 9201,
     /*  314543 */     GIR_EraseRootFromParent_Done,
     /*  314544 */   // Label 4744: @314544
     /*  314544 */   GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(314583), // Rule ID 9218 //
     /*  314549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled),
     /*  314552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314556 */     // MIs[0] sbase
     /*  314556 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  314560 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  314564 */     // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ec:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  314564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec),
     /*  314567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314569 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  314571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314581 */     GIR_RootConstrainSelectedInstOperands,
     /*  314582 */     // GIR_Coverage, 9218,
     /*  314582 */     GIR_EraseRootFromParent_Done,
     /*  314583 */   // Label 4745: @314583
     /*  314583 */   GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(314630), // Rule ID 9204 //
     /*  314588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  314591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314606 */     // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  314606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  314609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314624 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314628 */     GIR_RootConstrainSelectedInstOperands,
     /*  314629 */     // GIR_Coverage, 9204,
     /*  314629 */     GIR_EraseRootFromParent_Done,
     /*  314630 */   // Label 4746: @314630
     /*  314630 */   GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(314682), // Rule ID 9205 //
     /*  314635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  314638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314653 */     // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  314653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  314656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  314676 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314680 */     GIR_RootConstrainSelectedInstOperands,
     /*  314681 */     // GIR_Coverage, 9205,
     /*  314681 */     GIR_EraseRootFromParent_Done,
     /*  314682 */   // Label 4747: @314682
     /*  314682 */   GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(314729), // Rule ID 9221 //
     /*  314687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
     /*  314690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314705 */     // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
     /*  314705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
     /*  314708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314727 */     GIR_RootConstrainSelectedInstOperands,
     /*  314728 */     // GIR_Coverage, 9221,
     /*  314728 */     GIR_EraseRootFromParent_Done,
     /*  314729 */   // Label 4748: @314729
     /*  314729 */   GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(314781), // Rule ID 9222 //
     /*  314734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  314737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  314752 */     // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  314752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
     /*  314755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  314762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  314775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314779 */     GIR_RootConstrainSelectedInstOperands,
     /*  314780 */     // GIR_Coverage, 9222,
     /*  314780 */     GIR_EraseRootFromParent_Done,
     /*  314781 */   // Label 4749: @314781
     /*  314781 */   GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(314817), // Rule ID 9207 //
     /*  314786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314790 */     // MIs[0] sbase
     /*  314790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  314794 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  314798 */     // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  314798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  314801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314803 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  314805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314815 */     GIR_RootConstrainSelectedInstOperands,
     /*  314816 */     // GIR_Coverage, 9207,
     /*  314816 */     GIR_EraseRootFromParent_Done,
     /*  314817 */   // Label 4750: @314817
     /*  314817 */   GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(314853), // Rule ID 9224 //
     /*  314822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
     /*  314826 */     // MIs[0] sbase
     /*  314826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  314830 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  314834 */     // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  314834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
     /*  314837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  314839 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  314841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314851 */     GIR_RootConstrainSelectedInstOperands,
     /*  314852 */     // GIR_Coverage, 9224,
     /*  314852 */     GIR_EraseRootFromParent_Done,
     /*  314853 */   // Label 4751: @314853
     /*  314853 */   GIM_Reject,
     /*  314854 */ // Label 4717: @314854
     /*  314854 */ GIM_Reject,
     /*  314855 */ // Label 1142: @314855
     /*  314855 */ GIM_Reject,
     /*  314856 */ // Label 15: @314856
     /*  314856 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4754*/ GIMT_Encode4(353261),
     /*  314867 */ /*GILLT_s16*//*Label 4752*/ GIMT_Encode4(314875),
     /*  314871 */ /*GILLT_s32*//*Label 4753*/ GIMT_Encode4(330829),
     /*  314875 */ // Label 4752: @314875
     /*  314875 */ GIM_Try, /*On fail goto*//*Label 4755*/ GIMT_Encode4(314945), // Rule ID 25036 //
     /*  314880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  314883 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  314886 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  314893 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  314898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  314902 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314906 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  314913 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  314913 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  314916 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  314918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  314923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  314933 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314936 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  314939 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  314943 */   GIR_RootConstrainSelectedInstOperands,
     /*  314944 */   // GIR_Coverage, 25036,
     /*  314944 */   GIR_EraseRootFromParent_Done,
     /*  314945 */ // Label 4755: @314945
     /*  314945 */ GIM_Try, /*On fail goto*//*Label 4756*/ GIMT_Encode4(315015), // Rule ID 25037 //
     /*  314950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  314953 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  314956 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  314963 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  314968 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  314972 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  314976 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  314983 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  314983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  314986 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  314988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  314993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  314998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315009 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315013 */   GIR_RootConstrainSelectedInstOperands,
     /*  315014 */   // GIR_Coverage, 25037,
     /*  315014 */   GIR_EraseRootFromParent_Done,
     /*  315015 */ // Label 4756: @315015
     /*  315015 */ GIM_Try, /*On fail goto*//*Label 4757*/ GIMT_Encode4(315085), // Rule ID 25038 //
     /*  315020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  315023 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315026 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315033 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315042 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315046 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315053 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  315056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315073 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315076 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315079 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315083 */   GIR_RootConstrainSelectedInstOperands,
     /*  315084 */   // GIR_Coverage, 25038,
     /*  315084 */   GIR_EraseRootFromParent_Done,
     /*  315085 */ // Label 4757: @315085
     /*  315085 */ GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(315155), // Rule ID 25039 //
     /*  315090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  315093 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315096 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315103 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315108 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315112 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315116 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315123 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315123 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  315126 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315143 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315146 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315149 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315153 */   GIR_RootConstrainSelectedInstOperands,
     /*  315154 */   // GIR_Coverage, 25039,
     /*  315154 */   GIR_EraseRootFromParent_Done,
     /*  315155 */ // Label 4758: @315155
     /*  315155 */ GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(315225), // Rule ID 25040 //
     /*  315160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  315163 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315166 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315173 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315178 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315182 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315186 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315193 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315193 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  315196 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315213 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315216 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315219 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315223 */   GIR_RootConstrainSelectedInstOperands,
     /*  315224 */   // GIR_Coverage, 25040,
     /*  315224 */   GIR_EraseRootFromParent_Done,
     /*  315225 */ // Label 4759: @315225
     /*  315225 */ GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(315295), // Rule ID 25046 //
     /*  315230 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  315233 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315236 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315243 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315252 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315256 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315263 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  315266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315283 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315293 */   GIR_RootConstrainSelectedInstOperands,
     /*  315294 */   // GIR_Coverage, 25046,
     /*  315294 */   GIR_EraseRootFromParent_Done,
     /*  315295 */ // Label 4760: @315295
     /*  315295 */ GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(315365), // Rule ID 25047 //
     /*  315300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  315303 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315333 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  315336 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315359 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315363 */   GIR_RootConstrainSelectedInstOperands,
     /*  315364 */   // GIR_Coverage, 25047,
     /*  315364 */   GIR_EraseRootFromParent_Done,
     /*  315365 */ // Label 4761: @315365
     /*  315365 */ GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(315435), // Rule ID 25048 //
     /*  315370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  315373 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315403 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  315406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315423 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315426 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315429 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315433 */   GIR_RootConstrainSelectedInstOperands,
     /*  315434 */   // GIR_Coverage, 25048,
     /*  315434 */   GIR_EraseRootFromParent_Done,
     /*  315435 */ // Label 4762: @315435
     /*  315435 */ GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(315505), // Rule ID 25049 //
     /*  315440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  315443 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315446 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315453 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315462 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315466 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315473 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  315476 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315499 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315503 */   GIR_RootConstrainSelectedInstOperands,
     /*  315504 */   // GIR_Coverage, 25049,
     /*  315504 */   GIR_EraseRootFromParent_Done,
     /*  315505 */ // Label 4763: @315505
     /*  315505 */ GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(315575), // Rule ID 25050 //
     /*  315510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  315513 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315516 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315523 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  315543 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  315543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  315546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  315548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  315553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  315558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315563 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  315569 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315573 */   GIR_RootConstrainSelectedInstOperands,
     /*  315574 */   // GIR_Coverage, 25050,
     /*  315574 */   GIR_EraseRootFromParent_Done,
     /*  315575 */ // Label 4764: @315575
     /*  315575 */ GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(315644), // Rule ID 13960 //
     /*  315580 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  315583 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315586 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315593 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  315613 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  315613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  315616 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  315618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  315623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  315628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  315638 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315642 */   GIR_RootConstrainSelectedInstOperands,
     /*  315643 */   // GIR_Coverage, 13960,
     /*  315643 */   GIR_EraseRootFromParent_Done,
     /*  315644 */ // Label 4765: @315644
     /*  315644 */ GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(315713), // Rule ID 13961 //
     /*  315649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  315652 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315655 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315662 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315671 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315675 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  315682 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  315682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  315685 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  315687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  315692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  315697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  315707 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315711 */   GIR_RootConstrainSelectedInstOperands,
     /*  315712 */   // GIR_Coverage, 13961,
     /*  315712 */   GIR_EraseRootFromParent_Done,
     /*  315713 */ // Label 4766: @315713
     /*  315713 */ GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(315782), // Rule ID 13962 //
     /*  315718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  315721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315724 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315731 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315740 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315744 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  315751 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  315751 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  315754 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  315756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  315761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  315766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  315776 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315780 */   GIR_RootConstrainSelectedInstOperands,
     /*  315781 */   // GIR_Coverage, 13962,
     /*  315781 */   GIR_EraseRootFromParent_Done,
     /*  315782 */ // Label 4767: @315782
     /*  315782 */ GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(315851), // Rule ID 13963 //
     /*  315787 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  315790 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315793 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315800 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  315820 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  315820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  315823 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  315825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  315830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  315835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  315845 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315849 */   GIR_RootConstrainSelectedInstOperands,
     /*  315850 */   // GIR_Coverage, 13963,
     /*  315850 */   GIR_EraseRootFromParent_Done,
     /*  315851 */ // Label 4768: @315851
     /*  315851 */ GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(315920), // Rule ID 13964 //
     /*  315856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  315859 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315862 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315869 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315874 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  315878 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315882 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  315889 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  315889 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  315892 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  315894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  315899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  315904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  315914 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315918 */   GIR_RootConstrainSelectedInstOperands,
     /*  315919 */   // GIR_Coverage, 13964,
     /*  315919 */   GIR_EraseRootFromParent_Done,
     /*  315920 */ // Label 4769: @315920
     /*  315920 */ GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(316019), // Rule ID 14020 //
     /*  315925 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode0),
     /*  315928 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  315931 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  315938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  315943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  315947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  315951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  315958 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  315958 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  315961 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  315965 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  315970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  315975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  315980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  315985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  315990 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  315994 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  315996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  315999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316001 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316008 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316013 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316018 */   // GIR_Coverage, 14020,
     /*  316018 */   GIR_EraseRootFromParent_Done,
     /*  316019 */ // Label 4770: @316019
     /*  316019 */ GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(316118), // Rule ID 14021 //
     /*  316024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode1),
     /*  316027 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316030 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316037 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316042 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316046 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316050 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  316057 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  316057 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  316060 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  316064 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  316069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  316074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  316079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  316084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  316089 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316093 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  316095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  316098 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316100 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316107 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316112 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316117 */   // GIR_Coverage, 14021,
     /*  316117 */   GIR_EraseRootFromParent_Done,
     /*  316118 */ // Label 4771: @316118
     /*  316118 */ GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(316217), // Rule ID 14022 //
     /*  316123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode2),
     /*  316126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316129 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316141 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316145 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316149 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  316156 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  316156 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  316159 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  316163 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  316168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  316173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  316178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  316183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  316188 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316192 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  316194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  316197 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316199 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316206 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316211 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316216 */   // GIR_Coverage, 14022,
     /*  316216 */   GIR_EraseRootFromParent_Done,
     /*  316217 */ // Label 4772: @316217
     /*  316217 */ GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(316316), // Rule ID 14023 //
     /*  316222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode3),
     /*  316225 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316228 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316235 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316240 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316244 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316248 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  316255 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  316255 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  316258 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  316262 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  316267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  316272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  316277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  316282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  316287 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316291 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  316293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  316296 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316298 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316305 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316310 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316315 */   // GIR_Coverage, 14023,
     /*  316315 */   GIR_EraseRootFromParent_Done,
     /*  316316 */ // Label 4773: @316316
     /*  316316 */ GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(316415), // Rule ID 14024 //
     /*  316321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode4),
     /*  316324 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316327 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316334 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  316354 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  316354 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  316357 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  316361 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  316366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  316371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  316376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  316381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  316386 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316390 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  316392 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  316395 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316397 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316404 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316409 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316414 */   // GIR_Coverage, 14024,
     /*  316414 */   GIR_EraseRootFromParent_Done,
     /*  316415 */ // Label 4774: @316415
     /*  316415 */ GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(316484), // Rule ID 14045 //
     /*  316420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatScratchSVSMode_UseRealTrue16Insts),
     /*  316423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316426 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316433 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  316453 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_D16_SVS_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  316453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_D16_SVS_t16),
     /*  316456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  316458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  316463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  316468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  316473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  316478 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316482 */   GIR_RootConstrainSelectedInstOperands,
     /*  316483 */   // GIR_Coverage, 14045,
     /*  316483 */   GIR_EraseRootFromParent_Done,
     /*  316484 */ // Label 4775: @316484
     /*  316484 */ GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(316546), // Rule ID 13955 //
     /*  316489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  316492 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316495 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316502 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316511 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316515 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316522 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  316522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316525 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  316527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316537 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  316540 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316544 */   GIR_RootConstrainSelectedInstOperands,
     /*  316545 */   // GIR_Coverage, 13955,
     /*  316545 */   GIR_EraseRootFromParent_Done,
     /*  316546 */ // Label 4776: @316546
     /*  316546 */ GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(316608), // Rule ID 13956 //
     /*  316551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  316554 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316557 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316564 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316577 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316584 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  316584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316587 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  316589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  316602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316606 */   GIR_RootConstrainSelectedInstOperands,
     /*  316607 */   // GIR_Coverage, 13956,
     /*  316607 */   GIR_EraseRootFromParent_Done,
     /*  316608 */ // Label 4777: @316608
     /*  316608 */ GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(316670), // Rule ID 13957 //
     /*  316613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  316616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316619 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316626 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316635 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316639 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316646 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  316646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  316651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316661 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  316664 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316668 */   GIR_RootConstrainSelectedInstOperands,
     /*  316669 */   // GIR_Coverage, 13957,
     /*  316669 */   GIR_EraseRootFromParent_Done,
     /*  316670 */ // Label 4778: @316670
     /*  316670 */ GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(316732), // Rule ID 13958 //
     /*  316675 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  316678 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316681 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316688 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316693 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316697 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316708 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  316708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  316713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  316726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316730 */   GIR_RootConstrainSelectedInstOperands,
     /*  316731 */   // GIR_Coverage, 13958,
     /*  316731 */   GIR_EraseRootFromParent_Done,
     /*  316732 */ // Label 4779: @316732
     /*  316732 */ GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(316794), // Rule ID 13959 //
     /*  316737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  316740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316743 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316750 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316759 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316763 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316770 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  316770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316773 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  316775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  316788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316792 */   GIR_RootConstrainSelectedInstOperands,
     /*  316793 */   // GIR_Coverage, 13959,
     /*  316793 */   GIR_EraseRootFromParent_Done,
     /*  316794 */ // Label 4780: @316794
     /*  316794 */ GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(316886), // Rule ID 14015 //
     /*  316799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  316802 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316832 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  316832 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  316835 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316839 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  316844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316854 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  316857 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316861 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  316863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  316866 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316868 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316875 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316880 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316885 */   // GIR_Coverage, 14015,
     /*  316885 */   GIR_EraseRootFromParent_Done,
     /*  316886 */ // Label 4781: @316886
     /*  316886 */ GIM_Try, /*On fail goto*//*Label 4782*/ GIMT_Encode4(316978), // Rule ID 14016 //
     /*  316891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  316894 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316897 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  316909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  316917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  316924 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  316924 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  316927 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  316931 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  316936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  316941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  316946 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  316949 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  316953 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  316955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  316958 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  316960 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  316967 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  316972 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  316977 */   // GIR_Coverage, 14016,
     /*  316977 */   GIR_EraseRootFromParent_Done,
     /*  316978 */ // Label 4782: @316978
     /*  316978 */ GIM_Try, /*On fail goto*//*Label 4783*/ GIMT_Encode4(317070), // Rule ID 14017 //
     /*  316983 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  316986 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  316989 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  316996 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317005 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317009 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  317016 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317016 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317019 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  317023 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  317033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317038 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317041 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317045 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317047 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317050 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317052 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317059 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317064 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317069 */   // GIR_Coverage, 14017,
     /*  317069 */   GIR_EraseRootFromParent_Done,
     /*  317070 */ // Label 4783: @317070
     /*  317070 */ GIM_Try, /*On fail goto*//*Label 4784*/ GIMT_Encode4(317162), // Rule ID 14018 //
     /*  317075 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  317078 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317081 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  317108 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317108 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317111 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  317115 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  317125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317130 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317133 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317137 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317144 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317151 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317156 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317161 */   // GIR_Coverage, 14018,
     /*  317161 */   GIR_EraseRootFromParent_Done,
     /*  317162 */ // Label 4784: @317162
     /*  317162 */ GIM_Try, /*On fail goto*//*Label 4785*/ GIMT_Encode4(317254), // Rule ID 14019 //
     /*  317167 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  317170 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317173 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317180 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317185 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317189 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317193 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  317200 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317200 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317203 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  317207 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  317217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317222 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317225 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317229 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317231 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317234 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317236 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317243 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317248 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317253 */   // GIR_Coverage, 14019,
     /*  317253 */   GIR_EraseRootFromParent_Done,
     /*  317254 */ // Label 4785: @317254
     /*  317254 */ GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(317316), // Rule ID 14044 //
     /*  317259 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  317262 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317265 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  317292 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  317292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_t16),
     /*  317295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  317297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  317302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  317310 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317314 */   GIR_RootConstrainSelectedInstOperands,
     /*  317315 */   // GIR_Coverage, 14044,
     /*  317315 */   GIR_EraseRootFromParent_Done,
     /*  317316 */ // Label 4786: @317316
     /*  317316 */ GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(317378), // Rule ID 13950 //
     /*  317321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  317324 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317327 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317334 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317354 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  317354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317357 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  317359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  317372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317376 */   GIR_RootConstrainSelectedInstOperands,
     /*  317377 */   // GIR_Coverage, 13950,
     /*  317377 */   GIR_EraseRootFromParent_Done,
     /*  317378 */ // Label 4787: @317378
     /*  317378 */ GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(317440), // Rule ID 13951 //
     /*  317383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  317386 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317389 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317396 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317405 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317409 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317416 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  317416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317419 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  317421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317431 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  317434 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317438 */   GIR_RootConstrainSelectedInstOperands,
     /*  317439 */   // GIR_Coverage, 13951,
     /*  317439 */   GIR_EraseRootFromParent_Done,
     /*  317440 */ // Label 4788: @317440
     /*  317440 */ GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(317502), // Rule ID 13952 //
     /*  317445 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  317448 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317451 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317458 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317463 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317467 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317471 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317478 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  317478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317481 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  317483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  317496 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317500 */   GIR_RootConstrainSelectedInstOperands,
     /*  317501 */   // GIR_Coverage, 13952,
     /*  317501 */   GIR_EraseRootFromParent_Done,
     /*  317502 */ // Label 4789: @317502
     /*  317502 */ GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(317564), // Rule ID 13953 //
     /*  317507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  317510 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317513 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317520 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317525 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317540 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  317540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317543 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  317545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  317558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317562 */   GIR_RootConstrainSelectedInstOperands,
     /*  317563 */   // GIR_Coverage, 13953,
     /*  317563 */   GIR_EraseRootFromParent_Done,
     /*  317564 */ // Label 4790: @317564
     /*  317564 */ GIM_Try, /*On fail goto*//*Label 4791*/ GIMT_Encode4(317626), // Rule ID 13954 //
     /*  317569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  317572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317575 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317582 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317587 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317591 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317595 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317602 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  317602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317605 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  317607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317617 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  317620 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317624 */   GIR_RootConstrainSelectedInstOperands,
     /*  317625 */   // GIR_Coverage, 13954,
     /*  317625 */   GIR_EraseRootFromParent_Done,
     /*  317626 */ // Label 4791: @317626
     /*  317626 */ GIM_Try, /*On fail goto*//*Label 4792*/ GIMT_Encode4(317718), // Rule ID 14010 //
     /*  317631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  317634 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317637 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317644 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317653 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317657 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317664 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317664 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317667 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317671 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317686 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317689 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317693 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317700 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317707 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317712 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317717 */   // GIR_Coverage, 14010,
     /*  317717 */   GIR_EraseRootFromParent_Done,
     /*  317718 */ // Label 4792: @317718
     /*  317718 */ GIM_Try, /*On fail goto*//*Label 4793*/ GIMT_Encode4(317810), // Rule ID 14011 //
     /*  317723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  317726 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317729 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317736 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317745 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317749 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317756 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317756 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317759 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317763 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317778 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317781 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317785 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317787 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317790 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317792 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317799 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317804 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317809 */   // GIR_Coverage, 14011,
     /*  317809 */   GIR_EraseRootFromParent_Done,
     /*  317810 */ // Label 4793: @317810
     /*  317810 */ GIM_Try, /*On fail goto*//*Label 4794*/ GIMT_Encode4(317902), // Rule ID 14012 //
     /*  317815 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  317818 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317821 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317828 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317837 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317841 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317848 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317848 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317851 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317855 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317870 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317873 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317877 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317882 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317884 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317891 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317896 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317901 */   // GIR_Coverage, 14012,
     /*  317901 */   GIR_EraseRootFromParent_Done,
     /*  317902 */ // Label 4794: @317902
     /*  317902 */ GIM_Try, /*On fail goto*//*Label 4795*/ GIMT_Encode4(317994), // Rule ID 14013 //
     /*  317907 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  317910 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  317913 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  317920 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  317925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317929 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  317933 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  317940 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  317940 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  317943 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  317947 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  317952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  317957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  317962 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  317965 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  317969 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  317971 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  317974 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  317976 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  317983 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  317988 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  317993 */   // GIR_Coverage, 14013,
     /*  317993 */   GIR_EraseRootFromParent_Done,
     /*  317994 */ // Label 4795: @317994
     /*  317994 */ GIM_Try, /*On fail goto*//*Label 4796*/ GIMT_Encode4(318086), // Rule ID 14014 //
     /*  317999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  318002 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318005 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318012 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  318021 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318025 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  318032 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  318032 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  318035 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  318039 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  318044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  318049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  318054 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  318057 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318061 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  318063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  318066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  318068 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  318075 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  318080 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318085 */   // GIR_Coverage, 14014,
     /*  318085 */   GIR_EraseRootFromParent_Done,
     /*  318086 */ // Label 4796: @318086
     /*  318086 */ GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(318148), // Rule ID 14043 //
     /*  318091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  318094 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318097 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318104 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  318113 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318117 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  318124 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  318124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_D16_t16),
     /*  318127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  318129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  318134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  318139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318146 */   GIR_RootConstrainSelectedInstOperands,
     /*  318147 */   // GIR_Coverage, 14043,
     /*  318147 */   GIR_EraseRootFromParent_Done,
     /*  318148 */ // Label 4797: @318148
     /*  318148 */ GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(318223), // Rule ID 25031 //
     /*  318153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  318156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318159 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318166 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318175 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318179 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318186 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318186 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  318189 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318221 */   GIR_RootConstrainSelectedInstOperands,
     /*  318222 */   // GIR_Coverage, 25031,
     /*  318222 */   GIR_EraseRootFromParent_Done,
     /*  318223 */ // Label 4798: @318223
     /*  318223 */ GIM_Try, /*On fail goto*//*Label 4799*/ GIMT_Encode4(318298), // Rule ID 25032 //
     /*  318228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  318231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318261 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  318264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318289 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318292 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318296 */   GIR_RootConstrainSelectedInstOperands,
     /*  318297 */   // GIR_Coverage, 25032,
     /*  318297 */   GIR_EraseRootFromParent_Done,
     /*  318298 */ // Label 4799: @318298
     /*  318298 */ GIM_Try, /*On fail goto*//*Label 4800*/ GIMT_Encode4(318373), // Rule ID 25033 //
     /*  318303 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  318306 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318309 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318316 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318325 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318329 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318336 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318336 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  318339 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318361 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318364 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318367 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318371 */   GIR_RootConstrainSelectedInstOperands,
     /*  318372 */   // GIR_Coverage, 25033,
     /*  318372 */   GIR_EraseRootFromParent_Done,
     /*  318373 */ // Label 4800: @318373
     /*  318373 */ GIM_Try, /*On fail goto*//*Label 4801*/ GIMT_Encode4(318448), // Rule ID 25034 //
     /*  318378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  318381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318384 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318391 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318400 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318404 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318411 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  318414 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318436 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318439 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318442 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318446 */   GIR_RootConstrainSelectedInstOperands,
     /*  318447 */   // GIR_Coverage, 25034,
     /*  318447 */   GIR_EraseRootFromParent_Done,
     /*  318448 */ // Label 4801: @318448
     /*  318448 */ GIM_Try, /*On fail goto*//*Label 4802*/ GIMT_Encode4(318523), // Rule ID 25035 //
     /*  318453 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  318456 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318459 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318466 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318475 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318479 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318486 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318486 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  318489 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318511 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318514 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318517 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318521 */   GIR_RootConstrainSelectedInstOperands,
     /*  318522 */   // GIR_Coverage, 25035,
     /*  318522 */   GIR_EraseRootFromParent_Done,
     /*  318523 */ // Label 4802: @318523
     /*  318523 */ GIM_Try, /*On fail goto*//*Label 4803*/ GIMT_Encode4(318598), // Rule ID 25041 //
     /*  318528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  318531 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318534 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318541 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318550 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318554 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318561 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  318564 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318586 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318589 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318592 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318596 */   GIR_RootConstrainSelectedInstOperands,
     /*  318597 */   // GIR_Coverage, 25041,
     /*  318597 */   GIR_EraseRootFromParent_Done,
     /*  318598 */ // Label 4803: @318598
     /*  318598 */ GIM_Try, /*On fail goto*//*Label 4804*/ GIMT_Encode4(318673), // Rule ID 25042 //
     /*  318603 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  318606 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318609 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318616 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318625 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318629 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318636 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  318639 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318661 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318664 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318667 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318671 */   GIR_RootConstrainSelectedInstOperands,
     /*  318672 */   // GIR_Coverage, 25042,
     /*  318672 */   GIR_EraseRootFromParent_Done,
     /*  318673 */ // Label 4804: @318673
     /*  318673 */ GIM_Try, /*On fail goto*//*Label 4805*/ GIMT_Encode4(318748), // Rule ID 25043 //
     /*  318678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  318681 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318684 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318691 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318700 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318704 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318711 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318711 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  318714 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318736 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318739 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318742 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318746 */   GIR_RootConstrainSelectedInstOperands,
     /*  318747 */   // GIR_Coverage, 25043,
     /*  318747 */   GIR_EraseRootFromParent_Done,
     /*  318748 */ // Label 4805: @318748
     /*  318748 */ GIM_Try, /*On fail goto*//*Label 4806*/ GIMT_Encode4(318823), // Rule ID 25044 //
     /*  318753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  318756 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318759 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318766 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318771 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318775 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318779 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318786 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  318789 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318817 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318821 */   GIR_RootConstrainSelectedInstOperands,
     /*  318822 */   // GIR_Coverage, 25044,
     /*  318822 */   GIR_EraseRootFromParent_Done,
     /*  318823 */ // Label 4806: @318823
     /*  318823 */ GIM_Try, /*On fail goto*//*Label 4807*/ GIMT_Encode4(318898), // Rule ID 25045 //
     /*  318828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  318831 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318834 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318841 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  318846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318850 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318854 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  318861 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  318861 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  318864 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  318871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  318881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  318886 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318889 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318892 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318896 */   GIR_RootConstrainSelectedInstOperands,
     /*  318897 */   // GIR_Coverage, 25045,
     /*  318897 */   GIR_EraseRootFromParent_Done,
     /*  318898 */ // Label 4807: @318898
     /*  318898 */ GIM_Try, /*On fail goto*//*Label 4808*/ GIMT_Encode4(318969), // Rule ID 24891 //
     /*  318903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  318906 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318909 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318916 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  318922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318926 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  318930 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  318937 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  318937 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  318940 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  318942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  318947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  318952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  318957 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318960 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  318963 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  318967 */   GIR_RootConstrainSelectedInstOperands,
     /*  318968 */   // GIR_Coverage, 24891,
     /*  318968 */   GIR_EraseRootFromParent_Done,
     /*  318969 */ // Label 4808: @318969
     /*  318969 */ GIM_Try, /*On fail goto*//*Label 4809*/ GIMT_Encode4(319040), // Rule ID 24892 //
     /*  318974 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  318977 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  318980 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  318987 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  318993 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  318997 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319001 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319008 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319011 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319038 */   GIR_RootConstrainSelectedInstOperands,
     /*  319039 */   // GIR_Coverage, 24892,
     /*  319039 */   GIR_EraseRootFromParent_Done,
     /*  319040 */ // Label 4809: @319040
     /*  319040 */ GIM_Try, /*On fail goto*//*Label 4810*/ GIMT_Encode4(319111), // Rule ID 24893 //
     /*  319045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  319048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319051 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319058 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319079 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319082 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319099 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319102 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319105 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319109 */   GIR_RootConstrainSelectedInstOperands,
     /*  319110 */   // GIR_Coverage, 24893,
     /*  319110 */   GIR_EraseRootFromParent_Done,
     /*  319111 */ // Label 4810: @319111
     /*  319111 */ GIM_Try, /*On fail goto*//*Label 4811*/ GIMT_Encode4(319182), // Rule ID 24894 //
     /*  319116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  319119 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319122 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319129 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319139 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319143 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319150 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319153 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319173 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319176 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319180 */   GIR_RootConstrainSelectedInstOperands,
     /*  319181 */   // GIR_Coverage, 24894,
     /*  319181 */   GIR_EraseRootFromParent_Done,
     /*  319182 */ // Label 4811: @319182
     /*  319182 */ GIM_Try, /*On fail goto*//*Label 4812*/ GIMT_Encode4(319253), // Rule ID 24895 //
     /*  319187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  319190 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319193 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319210 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319214 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319221 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319241 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319251 */   GIR_RootConstrainSelectedInstOperands,
     /*  319252 */   // GIR_Coverage, 24895,
     /*  319252 */   GIR_EraseRootFromParent_Done,
     /*  319253 */ // Label 4812: @319253
     /*  319253 */ GIM_Try, /*On fail goto*//*Label 4813*/ GIMT_Encode4(319324), // Rule ID 24896 //
     /*  319258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  319261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319264 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319271 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319292 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  319295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319322 */   GIR_RootConstrainSelectedInstOperands,
     /*  319323 */   // GIR_Coverage, 24896,
     /*  319323 */   GIR_EraseRootFromParent_Done,
     /*  319324 */ // Label 4813: @319324
     /*  319324 */ GIM_Try, /*On fail goto*//*Label 4814*/ GIMT_Encode4(319395), // Rule ID 24897 //
     /*  319329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  319332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319335 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319342 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319363 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  319366 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319383 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319386 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319389 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319393 */   GIR_RootConstrainSelectedInstOperands,
     /*  319394 */   // GIR_Coverage, 24897,
     /*  319394 */   GIR_EraseRootFromParent_Done,
     /*  319395 */ // Label 4814: @319395
     /*  319395 */ GIM_Try, /*On fail goto*//*Label 4815*/ GIMT_Encode4(319466), // Rule ID 24898 //
     /*  319400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  319403 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319406 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319413 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319434 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  319437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319457 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319460 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319464 */   GIR_RootConstrainSelectedInstOperands,
     /*  319465 */   // GIR_Coverage, 24898,
     /*  319465 */   GIR_EraseRootFromParent_Done,
     /*  319466 */ // Label 4815: @319466
     /*  319466 */ GIM_Try, /*On fail goto*//*Label 4816*/ GIMT_Encode4(319537), // Rule ID 24899 //
     /*  319471 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  319474 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319477 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319484 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319490 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319494 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319498 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319505 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  319508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319531 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319535 */   GIR_RootConstrainSelectedInstOperands,
     /*  319536 */   // GIR_Coverage, 24899,
     /*  319536 */   GIR_EraseRootFromParent_Done,
     /*  319537 */ // Label 4816: @319537
     /*  319537 */ GIM_Try, /*On fail goto*//*Label 4817*/ GIMT_Encode4(319608), // Rule ID 24900 //
     /*  319542 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  319545 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319548 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319555 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319569 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319576 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319576 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  319579 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319606 */   GIR_RootConstrainSelectedInstOperands,
     /*  319607 */   // GIR_Coverage, 24900,
     /*  319607 */   GIR_EraseRootFromParent_Done,
     /*  319608 */ // Label 4817: @319608
     /*  319608 */ GIM_Try, /*On fail goto*//*Label 4818*/ GIMT_Encode4(319680), // Rule ID 24921 //
     /*  319613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  319616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319619 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319626 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319633 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319637 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319641 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319648 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319648 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319651 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319678 */   GIR_RootConstrainSelectedInstOperands,
     /*  319679 */   // GIR_Coverage, 24921,
     /*  319679 */   GIR_EraseRootFromParent_Done,
     /*  319680 */ // Label 4818: @319680
     /*  319680 */ GIM_Try, /*On fail goto*//*Label 4819*/ GIMT_Encode4(319752), // Rule ID 24922 //
     /*  319685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  319688 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319691 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319698 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319709 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319713 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319720 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319720 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319723 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319740 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319743 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319746 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319750 */   GIR_RootConstrainSelectedInstOperands,
     /*  319751 */   // GIR_Coverage, 24922,
     /*  319751 */   GIR_EraseRootFromParent_Done,
     /*  319752 */ // Label 4819: @319752
     /*  319752 */ GIM_Try, /*On fail goto*//*Label 4820*/ GIMT_Encode4(319824), // Rule ID 24923 //
     /*  319757 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  319760 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319763 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319770 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319781 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319785 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319792 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319792 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319795 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319807 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319812 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319815 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319818 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319822 */   GIR_RootConstrainSelectedInstOperands,
     /*  319823 */   // GIR_Coverage, 24923,
     /*  319823 */   GIR_EraseRootFromParent_Done,
     /*  319824 */ // Label 4820: @319824
     /*  319824 */ GIM_Try, /*On fail goto*//*Label 4821*/ GIMT_Encode4(319896), // Rule ID 24924 //
     /*  319829 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  319832 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319835 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319842 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319853 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319857 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319864 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319864 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319867 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319890 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319894 */   GIR_RootConstrainSelectedInstOperands,
     /*  319895 */   // GIR_Coverage, 24924,
     /*  319895 */   GIR_EraseRootFromParent_Done,
     /*  319896 */ // Label 4821: @319896
     /*  319896 */ GIM_Try, /*On fail goto*//*Label 4822*/ GIMT_Encode4(319968), // Rule ID 24925 //
     /*  319901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  319904 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319907 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319914 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  319929 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  319936 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  319936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  319939 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  319941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  319946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  319951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  319956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  319962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  319966 */   GIR_RootConstrainSelectedInstOperands,
     /*  319967 */   // GIR_Coverage, 24925,
     /*  319967 */   GIR_EraseRootFromParent_Done,
     /*  319968 */ // Label 4822: @319968
     /*  319968 */ GIM_Try, /*On fail goto*//*Label 4823*/ GIMT_Encode4(320040), // Rule ID 24926 //
     /*  319973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  319976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  319979 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  319986 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  319993 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  319997 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320001 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  320008 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  320008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  320011 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  320013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  320018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  320023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  320028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320038 */   GIR_RootConstrainSelectedInstOperands,
     /*  320039 */   // GIR_Coverage, 24926,
     /*  320039 */   GIR_EraseRootFromParent_Done,
     /*  320040 */ // Label 4823: @320040
     /*  320040 */ GIM_Try, /*On fail goto*//*Label 4824*/ GIMT_Encode4(320112), // Rule ID 24927 //
     /*  320045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  320048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320051 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320058 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  320065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320069 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320073 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  320080 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  320080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  320083 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  320085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  320090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  320095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  320100 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320103 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320106 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320110 */   GIR_RootConstrainSelectedInstOperands,
     /*  320111 */   // GIR_Coverage, 24927,
     /*  320111 */   GIR_EraseRootFromParent_Done,
     /*  320112 */ // Label 4824: @320112
     /*  320112 */ GIM_Try, /*On fail goto*//*Label 4825*/ GIMT_Encode4(320184), // Rule ID 24928 //
     /*  320117 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  320120 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320123 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320130 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  320137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320145 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  320152 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  320152 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  320155 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  320157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  320162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  320167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  320172 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320175 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320178 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320182 */   GIR_RootConstrainSelectedInstOperands,
     /*  320183 */   // GIR_Coverage, 24928,
     /*  320183 */   GIR_EraseRootFromParent_Done,
     /*  320184 */ // Label 4825: @320184
     /*  320184 */ GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(320256), // Rule ID 24929 //
     /*  320189 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  320192 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320195 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320202 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  320209 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320217 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  320224 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  320224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  320227 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  320229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  320234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  320239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  320244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320247 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320250 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320254 */   GIR_RootConstrainSelectedInstOperands,
     /*  320255 */   // GIR_Coverage, 24929,
     /*  320255 */   GIR_EraseRootFromParent_Done,
     /*  320256 */ // Label 4826: @320256
     /*  320256 */ GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(320328), // Rule ID 24930 //
     /*  320261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  320264 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320267 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320274 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  320281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  320296 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  320296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  320299 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  320301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  320306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  320311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  320316 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320319 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320322 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320326 */   GIR_RootConstrainSelectedInstOperands,
     /*  320327 */   // GIR_Coverage, 24930,
     /*  320327 */   GIR_EraseRootFromParent_Done,
     /*  320328 */ // Label 4827: @320328
     /*  320328 */ GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(320390), // Rule ID 28783 //
     /*  320333 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  320336 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320339 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320355 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320359 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320366 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  320369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320381 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320384 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320388 */   GIR_RootConstrainSelectedInstOperands,
     /*  320389 */   // GIR_Coverage, 28783,
     /*  320389 */   GIR_EraseRootFromParent_Done,
     /*  320390 */ // Label 4828: @320390
     /*  320390 */ GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(320452), // Rule ID 28784 //
     /*  320395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  320398 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320401 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320408 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320413 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320428 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  320431 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320443 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320446 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320450 */   GIR_RootConstrainSelectedInstOperands,
     /*  320451 */   // GIR_Coverage, 28784,
     /*  320451 */   GIR_EraseRootFromParent_Done,
     /*  320452 */ // Label 4829: @320452
     /*  320452 */ GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(320514), // Rule ID 28785 //
     /*  320457 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  320460 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320463 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320470 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320475 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320479 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320483 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320490 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  320493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320505 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320508 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320512 */   GIR_RootConstrainSelectedInstOperands,
     /*  320513 */   // GIR_Coverage, 28785,
     /*  320513 */   GIR_EraseRootFromParent_Done,
     /*  320514 */ // Label 4830: @320514
     /*  320514 */ GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(320576), // Rule ID 28786 //
     /*  320519 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  320522 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320525 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320532 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320537 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320541 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320545 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320552 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320552 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  320555 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320567 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320570 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320574 */   GIR_RootConstrainSelectedInstOperands,
     /*  320575 */   // GIR_Coverage, 28786,
     /*  320575 */   GIR_EraseRootFromParent_Done,
     /*  320576 */ // Label 4831: @320576
     /*  320576 */ GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(320638), // Rule ID 28787 //
     /*  320581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  320584 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320587 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320594 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320599 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320603 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320607 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320614 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320614 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  320617 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320629 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320632 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320636 */   GIR_RootConstrainSelectedInstOperands,
     /*  320637 */   // GIR_Coverage, 28787,
     /*  320637 */   GIR_EraseRootFromParent_Done,
     /*  320638 */ // Label 4832: @320638
     /*  320638 */ GIM_Try, /*On fail goto*//*Label 4833*/ GIMT_Encode4(320700), // Rule ID 28788 //
     /*  320643 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  320646 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320649 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320656 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320661 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320665 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320669 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320676 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320676 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  320679 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320691 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320694 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320698 */   GIR_RootConstrainSelectedInstOperands,
     /*  320699 */   // GIR_Coverage, 28788,
     /*  320699 */   GIR_EraseRootFromParent_Done,
     /*  320700 */ // Label 4833: @320700
     /*  320700 */ GIM_Try, /*On fail goto*//*Label 4834*/ GIMT_Encode4(320762), // Rule ID 28789 //
     /*  320705 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  320708 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320711 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320727 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320731 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320738 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320738 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  320741 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320753 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320756 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320760 */   GIR_RootConstrainSelectedInstOperands,
     /*  320761 */   // GIR_Coverage, 28789,
     /*  320761 */   GIR_EraseRootFromParent_Done,
     /*  320762 */ // Label 4834: @320762
     /*  320762 */ GIM_Try, /*On fail goto*//*Label 4835*/ GIMT_Encode4(320824), // Rule ID 28790 //
     /*  320767 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  320770 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320773 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320780 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320789 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320793 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320800 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320800 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  320803 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320815 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320818 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320822 */   GIR_RootConstrainSelectedInstOperands,
     /*  320823 */   // GIR_Coverage, 28790,
     /*  320823 */   GIR_EraseRootFromParent_Done,
     /*  320824 */ // Label 4835: @320824
     /*  320824 */ GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(320886), // Rule ID 28791 //
     /*  320829 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  320832 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320835 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320842 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320855 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320862 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  320865 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320884 */   GIR_RootConstrainSelectedInstOperands,
     /*  320885 */   // GIR_Coverage, 28791,
     /*  320885 */   GIR_EraseRootFromParent_Done,
     /*  320886 */ // Label 4836: @320886
     /*  320886 */ GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(320948), // Rule ID 28792 //
     /*  320891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  320894 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320897 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  320913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320924 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  320927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  320939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  320942 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  320946 */   GIR_RootConstrainSelectedInstOperands,
     /*  320947 */   // GIR_Coverage, 28792,
     /*  320947 */   GIR_EraseRootFromParent_Done,
     /*  320948 */ // Label 4837: @320948
     /*  320948 */ GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(321010), // Rule ID 28793 //
     /*  320953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  320956 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  320959 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  320966 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  320971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  320975 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  320979 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  320986 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  320986 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_t16),
     /*  320989 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  320991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  320996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321004 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321008 */   GIR_RootConstrainSelectedInstOperands,
     /*  321009 */   // GIR_Coverage, 28793,
     /*  321009 */   GIR_EraseRootFromParent_Done,
     /*  321010 */ // Label 4838: @321010
     /*  321010 */ GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(321102), // Rule ID 28794 //
     /*  321015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  321018 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  321021 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321028 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321037 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321041 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321048 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  321048 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  321051 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321055 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  321060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321070 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  321073 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321077 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  321079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  321082 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  321084 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  321091 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321096 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321101 */   // GIR_Coverage, 28794,
     /*  321101 */   GIR_EraseRootFromParent_Done,
     /*  321102 */ // Label 4839: @321102
     /*  321102 */ GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(321194), // Rule ID 28795 //
     /*  321107 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  321110 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  321113 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321120 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321140 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  321140 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  321143 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321147 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  321152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321162 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  321165 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321169 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  321171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  321174 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  321176 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  321183 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321188 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321193 */   // GIR_Coverage, 28795,
     /*  321193 */   GIR_EraseRootFromParent_Done,
     /*  321194 */ // Label 4840: @321194
     /*  321194 */ GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(321286), // Rule ID 28796 //
     /*  321199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  321202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  321205 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321212 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321217 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321221 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321225 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321232 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  321232 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  321235 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321239 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  321244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321254 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  321257 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321261 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  321263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  321266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  321268 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  321275 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321280 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321285 */   // GIR_Coverage, 28796,
     /*  321285 */   GIR_EraseRootFromParent_Done,
     /*  321286 */ // Label 4841: @321286
     /*  321286 */ GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(321378), // Rule ID 28797 //
     /*  321291 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  321294 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  321297 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321304 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321324 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  321324 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  321327 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321331 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  321336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321346 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  321349 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321353 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  321355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  321358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  321360 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  321367 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321372 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321377 */   // GIR_Coverage, 28797,
     /*  321377 */   GIR_EraseRootFromParent_Done,
     /*  321378 */ // Label 4842: @321378
     /*  321378 */ GIM_Try, /*On fail goto*//*Label 4843*/ GIMT_Encode4(321470), // Rule ID 28798 //
     /*  321383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  321386 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  321389 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321396 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321405 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321409 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321416 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  321416 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  321419 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321423 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  321428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321438 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  321441 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321445 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  321447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  321450 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  321452 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  321459 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  321464 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321469 */   // GIR_Coverage, 28798,
     /*  321469 */   GIR_EraseRootFromParent_Done,
     /*  321470 */ // Label 4843: @321470
     /*  321470 */ GIM_Try, /*On fail goto*//*Label 4844*/ GIMT_Encode4(321532), // Rule ID 29029 //
     /*  321475 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  321478 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321481 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321488 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321497 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321501 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321508 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  321511 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321523 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321526 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321530 */   GIR_RootConstrainSelectedInstOperands,
     /*  321531 */   // GIR_Coverage, 29029,
     /*  321531 */   GIR_EraseRootFromParent_Done,
     /*  321532 */ // Label 4844: @321532
     /*  321532 */ GIM_Try, /*On fail goto*//*Label 4845*/ GIMT_Encode4(321594), // Rule ID 29030 //
     /*  321537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  321540 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321543 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321559 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321563 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321570 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321570 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  321573 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321585 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321588 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321592 */   GIR_RootConstrainSelectedInstOperands,
     /*  321593 */   // GIR_Coverage, 29030,
     /*  321593 */   GIR_EraseRootFromParent_Done,
     /*  321594 */ // Label 4845: @321594
     /*  321594 */ GIM_Try, /*On fail goto*//*Label 4846*/ GIMT_Encode4(321656), // Rule ID 29031 //
     /*  321599 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  321602 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321605 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321612 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321617 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321621 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321625 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321632 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321632 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  321635 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321647 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321650 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321654 */   GIR_RootConstrainSelectedInstOperands,
     /*  321655 */   // GIR_Coverage, 29031,
     /*  321655 */   GIR_EraseRootFromParent_Done,
     /*  321656 */ // Label 4846: @321656
     /*  321656 */ GIM_Try, /*On fail goto*//*Label 4847*/ GIMT_Encode4(321718), // Rule ID 29032 //
     /*  321661 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  321664 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321667 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321674 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321679 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321683 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321687 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321694 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  321697 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321709 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321712 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321716 */   GIR_RootConstrainSelectedInstOperands,
     /*  321717 */   // GIR_Coverage, 29032,
     /*  321717 */   GIR_EraseRootFromParent_Done,
     /*  321718 */ // Label 4847: @321718
     /*  321718 */ GIM_Try, /*On fail goto*//*Label 4848*/ GIMT_Encode4(321780), // Rule ID 29033 //
     /*  321723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  321726 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321729 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321736 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321745 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321749 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321756 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321756 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  321759 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321771 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321774 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321778 */   GIR_RootConstrainSelectedInstOperands,
     /*  321779 */   // GIR_Coverage, 29033,
     /*  321779 */   GIR_EraseRootFromParent_Done,
     /*  321780 */ // Label 4848: @321780
     /*  321780 */ GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(321842), // Rule ID 29034 //
     /*  321785 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  321788 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321791 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321798 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321811 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321818 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321821 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321840 */   GIR_RootConstrainSelectedInstOperands,
     /*  321841 */   // GIR_Coverage, 29034,
     /*  321841 */   GIR_EraseRootFromParent_Done,
     /*  321842 */ // Label 4849: @321842
     /*  321842 */ GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(321904), // Rule ID 29035 //
     /*  321847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  321850 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321853 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321860 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321865 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321869 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321873 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321880 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321880 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321883 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321895 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321898 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321902 */   GIR_RootConstrainSelectedInstOperands,
     /*  321903 */   // GIR_Coverage, 29035,
     /*  321903 */   GIR_EraseRootFromParent_Done,
     /*  321904 */ // Label 4850: @321904
     /*  321904 */ GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(321966), // Rule ID 29036 //
     /*  321909 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  321912 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321915 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321922 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321927 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321931 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321935 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  321942 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  321942 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  321945 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  321947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  321952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  321957 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  321960 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  321964 */   GIR_RootConstrainSelectedInstOperands,
     /*  321965 */   // GIR_Coverage, 29036,
     /*  321965 */   GIR_EraseRootFromParent_Done,
     /*  321966 */ // Label 4851: @321966
     /*  321966 */ GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(322028), // Rule ID 29037 //
     /*  321971 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  321974 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  321977 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  321984 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  321989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  321993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  321997 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322004 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  322004 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322007 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  322022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322026 */   GIR_RootConstrainSelectedInstOperands,
     /*  322027 */   // GIR_Coverage, 29037,
     /*  322027 */   GIR_EraseRootFromParent_Done,
     /*  322028 */ // Label 4852: @322028
     /*  322028 */ GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(322090), // Rule ID 29038 //
     /*  322033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  322036 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322039 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322046 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322059 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322066 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  322066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322069 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  322084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322088 */   GIR_RootConstrainSelectedInstOperands,
     /*  322089 */   // GIR_Coverage, 29038,
     /*  322089 */   GIR_EraseRootFromParent_Done,
     /*  322090 */ // Label 4853: @322090
     /*  322090 */ GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(322152), // Rule ID 29039 //
     /*  322095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  322098 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322101 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322128 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  322128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_t16),
     /*  322131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322143 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  322146 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322150 */   GIR_RootConstrainSelectedInstOperands,
     /*  322151 */   // GIR_Coverage, 29039,
     /*  322151 */   GIR_EraseRootFromParent_Done,
     /*  322152 */ // Label 4854: @322152
     /*  322152 */ GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(322244), // Rule ID 29040 //
     /*  322157 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  322160 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322163 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322175 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322179 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322183 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322190 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  322190 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  322193 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322197 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  322202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322212 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  322215 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322219 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  322221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  322224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  322226 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  322233 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322238 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322243 */   // GIR_Coverage, 29040,
     /*  322243 */   GIR_EraseRootFromParent_Done,
     /*  322244 */ // Label 4855: @322244
     /*  322244 */ GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(322336), // Rule ID 29041 //
     /*  322249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  322252 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322255 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322262 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322267 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322271 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322275 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322282 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  322282 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  322285 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322289 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  322294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322304 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  322307 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322311 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  322313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  322316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  322318 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  322325 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322330 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322335 */   // GIR_Coverage, 29041,
     /*  322335 */   GIR_EraseRootFromParent_Done,
     /*  322336 */ // Label 4856: @322336
     /*  322336 */ GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(322428), // Rule ID 29042 //
     /*  322341 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  322344 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322347 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322354 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322367 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322374 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  322374 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  322377 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322381 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  322386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322396 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  322399 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322403 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  322405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  322408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  322410 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  322417 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322422 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322427 */   // GIR_Coverage, 29042,
     /*  322427 */   GIR_EraseRootFromParent_Done,
     /*  322428 */ // Label 4857: @322428
     /*  322428 */ GIM_Try, /*On fail goto*//*Label 4858*/ GIMT_Encode4(322520), // Rule ID 29043 //
     /*  322433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  322436 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322439 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322446 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322466 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  322466 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  322469 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322473 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  322478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322488 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  322491 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322495 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  322497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  322500 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  322502 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  322509 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322514 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322519 */   // GIR_Coverage, 29043,
     /*  322519 */   GIR_EraseRootFromParent_Done,
     /*  322520 */ // Label 4858: @322520
     /*  322520 */ GIM_Try, /*On fail goto*//*Label 4859*/ GIMT_Encode4(322612), // Rule ID 29044 //
     /*  322525 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  322528 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322531 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322538 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  322543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322547 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322551 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  322558 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  322558 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  322561 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  322565 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  322570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  322575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  322580 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  322583 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322587 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  322589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  322592 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  322594 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  322601 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  322606 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322611 */   // GIR_Coverage, 29044,
     /*  322611 */   GIR_EraseRootFromParent_Done,
     /*  322612 */ // Label 4859: @322612
     /*  322612 */ GIM_Try, /*On fail goto*//*Label 4860*/ GIMT_Encode4(322683), // Rule ID 11857 //
     /*  322617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  322620 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  322623 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322630 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  322637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322645 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  322652 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  322652 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  322655 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  322662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  322667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  322672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  322677 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322681 */   GIR_RootConstrainSelectedInstOperands,
     /*  322682 */   // GIR_Coverage, 11857,
     /*  322682 */   GIR_EraseRootFromParent_Done,
     /*  322683 */ // Label 4860: @322683
     /*  322683 */ GIM_Try, /*On fail goto*//*Label 4861*/ GIMT_Encode4(322754), // Rule ID 11858 //
     /*  322688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  322691 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  322694 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322701 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  322708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322712 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322716 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  322723 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  322723 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  322726 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  322733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  322738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  322743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  322748 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322752 */   GIR_RootConstrainSelectedInstOperands,
     /*  322753 */   // GIR_Coverage, 11858,
     /*  322753 */   GIR_EraseRootFromParent_Done,
     /*  322754 */ // Label 4861: @322754
     /*  322754 */ GIM_Try, /*On fail goto*//*Label 4862*/ GIMT_Encode4(322825), // Rule ID 11859 //
     /*  322759 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  322762 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  322765 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322772 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  322779 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322783 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322787 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  322794 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  322794 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  322797 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  322804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  322809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  322814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  322819 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322823 */   GIR_RootConstrainSelectedInstOperands,
     /*  322824 */   // GIR_Coverage, 11859,
     /*  322824 */   GIR_EraseRootFromParent_Done,
     /*  322825 */ // Label 4862: @322825
     /*  322825 */ GIM_Try, /*On fail goto*//*Label 4863*/ GIMT_Encode4(322896), // Rule ID 11860 //
     /*  322830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  322833 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  322836 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322843 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  322850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322854 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322858 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  322865 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  322865 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  322868 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  322875 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  322880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  322885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  322890 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322894 */   GIR_RootConstrainSelectedInstOperands,
     /*  322895 */   // GIR_Coverage, 11860,
     /*  322895 */   GIR_EraseRootFromParent_Done,
     /*  322896 */ // Label 4863: @322896
     /*  322896 */ GIM_Try, /*On fail goto*//*Label 4864*/ GIMT_Encode4(322967), // Rule ID 11861 //
     /*  322901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  322904 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  322907 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322914 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  322921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  322929 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  322936 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  322936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  322939 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  322941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  322946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  322951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  322956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  322961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  322965 */   GIR_RootConstrainSelectedInstOperands,
     /*  322966 */   // GIR_Coverage, 11861,
     /*  322966 */   GIR_EraseRootFromParent_Done,
     /*  322967 */ // Label 4864: @322967
     /*  322967 */ GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(323038), // Rule ID 11917 //
     /*  322972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  322975 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  322978 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  322985 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  322992 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  322996 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323000 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323007 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  323007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323010 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  323012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323032 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323036 */   GIR_RootConstrainSelectedInstOperands,
     /*  323037 */   // GIR_Coverage, 11917,
     /*  323037 */   GIR_EraseRootFromParent_Done,
     /*  323038 */ // Label 4865: @323038
     /*  323038 */ GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(323109), // Rule ID 11918 //
     /*  323043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  323046 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  323049 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323056 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323067 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323071 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323078 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  323078 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323081 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  323083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323107 */   GIR_RootConstrainSelectedInstOperands,
     /*  323108 */   // GIR_Coverage, 11918,
     /*  323108 */   GIR_EraseRootFromParent_Done,
     /*  323109 */ // Label 4866: @323109
     /*  323109 */ GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(323180), // Rule ID 11919 //
     /*  323114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  323117 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  323120 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323138 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323142 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323149 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  323149 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323152 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  323154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323178 */   GIR_RootConstrainSelectedInstOperands,
     /*  323179 */   // GIR_Coverage, 11919,
     /*  323179 */   GIR_EraseRootFromParent_Done,
     /*  323180 */ // Label 4867: @323180
     /*  323180 */ GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(323251), // Rule ID 11920 //
     /*  323185 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  323188 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  323191 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323198 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323205 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323209 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323213 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323220 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  323220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323223 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  323225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323245 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323249 */   GIR_RootConstrainSelectedInstOperands,
     /*  323250 */   // GIR_Coverage, 11920,
     /*  323250 */   GIR_EraseRootFromParent_Done,
     /*  323251 */ // Label 4868: @323251
     /*  323251 */ GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(323322), // Rule ID 11921 //
     /*  323256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  323259 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  323262 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323280 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323284 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323291 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  323291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  323296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323320 */   GIR_RootConstrainSelectedInstOperands,
     /*  323321 */   // GIR_Coverage, 11921,
     /*  323321 */   GIR_EraseRootFromParent_Done,
     /*  323322 */ // Label 4869: @323322
     /*  323322 */ GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(323423), // Rule ID 11957 //
     /*  323327 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  323330 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  323333 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323340 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323362 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323362 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323365 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323369 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323394 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323398 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  323400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  323403 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  323405 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  323412 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323417 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323422 */   // GIR_Coverage, 11957,
     /*  323422 */   GIR_EraseRootFromParent_Done,
     /*  323423 */ // Label 4870: @323423
     /*  323423 */ GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(323524), // Rule ID 11958 //
     /*  323428 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  323431 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  323434 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323441 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323448 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323452 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323456 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323463 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323463 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323466 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323470 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323495 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323499 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  323501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  323504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  323506 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  323513 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323518 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323523 */   // GIR_Coverage, 11958,
     /*  323523 */   GIR_EraseRootFromParent_Done,
     /*  323524 */ // Label 4871: @323524
     /*  323524 */ GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(323625), // Rule ID 11959 //
     /*  323529 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  323532 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  323535 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323542 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323553 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323557 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323564 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323564 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323567 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323571 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323596 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323600 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  323602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  323605 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  323607 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  323614 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323619 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323624 */   // GIR_Coverage, 11959,
     /*  323624 */   GIR_EraseRootFromParent_Done,
     /*  323625 */ // Label 4872: @323625
     /*  323625 */ GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(323726), // Rule ID 11960 //
     /*  323630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  323633 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  323636 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323654 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323658 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323665 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323665 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323668 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323672 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323697 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323701 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  323703 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  323706 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  323708 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  323715 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323720 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323725 */   // GIR_Coverage, 11960,
     /*  323725 */   GIR_EraseRootFromParent_Done,
     /*  323726 */ // Label 4873: @323726
     /*  323726 */ GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(323827), // Rule ID 11961 //
     /*  323731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  323734 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  323737 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323744 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323751 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323755 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323759 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323766 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323766 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323769 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323773 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323798 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323802 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  323804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  323807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  323809 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  323816 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323821 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323826 */   // GIR_Coverage, 11961,
     /*  323826 */   GIR_EraseRootFromParent_Done,
     /*  323827 */ // Label 4874: @323827
     /*  323827 */ GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(323928), // Rule ID 12017 //
     /*  323832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  323835 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  323838 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323845 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323867 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323867 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323870 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323874 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  323899 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  323903 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  323905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  323908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  323910 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  323917 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323922 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  323927 */   // GIR_Coverage, 12017,
     /*  323927 */   GIR_EraseRootFromParent_Done,
     /*  323928 */ // Label 4875: @323928
     /*  323928 */ GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(324029), // Rule ID 12018 //
     /*  323933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  323936 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  323939 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  323946 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  323953 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  323957 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  323961 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  323968 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  323968 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  323971 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  323975 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  323980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  323985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  323990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  323995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  324000 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324004 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  324006 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  324009 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  324011 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  324018 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324023 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324028 */   // GIR_Coverage, 12018,
     /*  324028 */   GIR_EraseRootFromParent_Done,
     /*  324029 */ // Label 4876: @324029
     /*  324029 */ GIM_Try, /*On fail goto*//*Label 4877*/ GIMT_Encode4(324130), // Rule ID 12019 //
     /*  324034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  324037 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324040 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324047 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324054 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324062 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  324069 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  324069 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  324072 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  324076 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  324081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  324086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  324091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  324096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  324101 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324105 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  324107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  324110 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  324112 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  324119 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324124 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324129 */   // GIR_Coverage, 12019,
     /*  324129 */   GIR_EraseRootFromParent_Done,
     /*  324130 */ // Label 4877: @324130
     /*  324130 */ GIM_Try, /*On fail goto*//*Label 4878*/ GIMT_Encode4(324231), // Rule ID 12020 //
     /*  324135 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  324138 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324141 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324148 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324155 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  324170 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  324170 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  324173 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  324177 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  324182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  324187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  324192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  324197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  324202 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324206 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  324208 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  324211 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  324213 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  324220 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324225 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324230 */   // GIR_Coverage, 12020,
     /*  324230 */   GIR_EraseRootFromParent_Done,
     /*  324231 */ // Label 4878: @324231
     /*  324231 */ GIM_Try, /*On fail goto*//*Label 4879*/ GIMT_Encode4(324332), // Rule ID 12021 //
     /*  324236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  324239 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324242 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324249 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  324271 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  324271 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  324274 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  324278 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  324283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  324288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  324293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  324298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  324303 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  324309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  324312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  324314 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  324321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324326 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324331 */   // GIR_Coverage, 12021,
     /*  324331 */   GIR_EraseRootFromParent_Done,
     /*  324332 */ // Label 4879: @324332
     /*  324332 */ GIM_Try, /*On fail goto*//*Label 4880*/ GIMT_Encode4(324403), // Rule ID 12053 //
     /*  324337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  324340 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  324343 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324350 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324361 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324365 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  324372 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  324372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_t16),
     /*  324375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  324382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  324387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  324392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  324397 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324401 */   GIR_RootConstrainSelectedInstOperands,
     /*  324402 */   // GIR_Coverage, 12053,
     /*  324402 */   GIR_EraseRootFromParent_Done,
     /*  324403 */ // Label 4880: @324403
     /*  324403 */ GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(324474), // Rule ID 12077 //
     /*  324408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  324411 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324414 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324421 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  324432 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324436 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  324443 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  324443 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_t16),
     /*  324446 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  324453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  324458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  324463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  324468 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324472 */   GIR_RootConstrainSelectedInstOperands,
     /*  324473 */   // GIR_Coverage, 12077,
     /*  324473 */   GIR_EraseRootFromParent_Done,
     /*  324474 */ // Label 4881: @324474
     /*  324474 */ GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(324538), // Rule ID 11852 //
     /*  324479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  324482 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  324485 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324514 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324517 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324536 */   GIR_RootConstrainSelectedInstOperands,
     /*  324537 */   // GIR_Coverage, 11852,
     /*  324537 */   GIR_EraseRootFromParent_Done,
     /*  324538 */ // Label 4882: @324538
     /*  324538 */ GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(324602), // Rule ID 11853 //
     /*  324543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  324546 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  324549 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324578 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324596 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324600 */   GIR_RootConstrainSelectedInstOperands,
     /*  324601 */   // GIR_Coverage, 11853,
     /*  324601 */   GIR_EraseRootFromParent_Done,
     /*  324602 */ // Label 4883: @324602
     /*  324602 */ GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(324666), // Rule ID 11854 //
     /*  324607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  324610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  324613 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324642 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324645 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324657 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324660 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324664 */   GIR_RootConstrainSelectedInstOperands,
     /*  324665 */   // GIR_Coverage, 11854,
     /*  324665 */   GIR_EraseRootFromParent_Done,
     /*  324666 */ // Label 4884: @324666
     /*  324666 */ GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(324730), // Rule ID 11855 //
     /*  324671 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  324674 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  324677 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324691 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324695 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324699 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324706 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324706 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324709 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324724 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324728 */   GIR_RootConstrainSelectedInstOperands,
     /*  324729 */   // GIR_Coverage, 11855,
     /*  324729 */   GIR_EraseRootFromParent_Done,
     /*  324730 */ // Label 4885: @324730
     /*  324730 */ GIM_Try, /*On fail goto*//*Label 4886*/ GIMT_Encode4(324794), // Rule ID 11856 //
     /*  324735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  324738 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  324741 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324748 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324759 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324763 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324770 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324773 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324792 */   GIR_RootConstrainSelectedInstOperands,
     /*  324793 */   // GIR_Coverage, 11856,
     /*  324793 */   GIR_EraseRootFromParent_Done,
     /*  324794 */ // Label 4886: @324794
     /*  324794 */ GIM_Try, /*On fail goto*//*Label 4887*/ GIMT_Encode4(324858), // Rule ID 11912 //
     /*  324799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  324802 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324823 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324827 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324834 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324834 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324837 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324856 */   GIR_RootConstrainSelectedInstOperands,
     /*  324857 */   // GIR_Coverage, 11912,
     /*  324857 */   GIR_EraseRootFromParent_Done,
     /*  324858 */ // Label 4887: @324858
     /*  324858 */ GIM_Try, /*On fail goto*//*Label 4888*/ GIMT_Encode4(324922), // Rule ID 11913 //
     /*  324863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  324866 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324869 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324898 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324913 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324916 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324920 */   GIR_RootConstrainSelectedInstOperands,
     /*  324921 */   // GIR_Coverage, 11913,
     /*  324921 */   GIR_EraseRootFromParent_Done,
     /*  324922 */ // Label 4888: @324922
     /*  324922 */ GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(324986), // Rule ID 11914 //
     /*  324927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  324930 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324933 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  324940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  324947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  324951 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  324955 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  324962 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  324962 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  324965 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  324967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  324972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  324977 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  324980 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  324984 */   GIR_RootConstrainSelectedInstOperands,
     /*  324985 */   // GIR_Coverage, 11914,
     /*  324985 */   GIR_EraseRootFromParent_Done,
     /*  324986 */ // Label 4889: @324986
     /*  324986 */ GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(325050), // Rule ID 11915 //
     /*  324991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  324994 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  324997 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325026 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  325026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  325031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  325044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325048 */   GIR_RootConstrainSelectedInstOperands,
     /*  325049 */   // GIR_Coverage, 11915,
     /*  325049 */   GIR_EraseRootFromParent_Done,
     /*  325050 */ // Label 4890: @325050
     /*  325050 */ GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(325114), // Rule ID 11916 //
     /*  325055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  325058 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  325061 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325079 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325083 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325090 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  325090 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325093 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  325095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325105 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  325108 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325112 */   GIR_RootConstrainSelectedInstOperands,
     /*  325113 */   // GIR_Coverage, 11916,
     /*  325113 */   GIR_EraseRootFromParent_Done,
     /*  325114 */ // Label 4891: @325114
     /*  325114 */ GIM_Try, /*On fail goto*//*Label 4892*/ GIMT_Encode4(325208), // Rule ID 11952 //
     /*  325119 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  325122 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  325125 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325132 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325147 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325154 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325154 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325157 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325161 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325176 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325179 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325183 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325185 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325188 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325190 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325197 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325202 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325207 */   // GIR_Coverage, 11952,
     /*  325207 */   GIR_EraseRootFromParent_Done,
     /*  325208 */ // Label 4892: @325208
     /*  325208 */ GIM_Try, /*On fail goto*//*Label 4893*/ GIMT_Encode4(325302), // Rule ID 11953 //
     /*  325213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  325216 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  325219 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325237 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325241 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325248 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325248 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325251 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325255 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325270 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325273 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325277 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325284 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325291 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325296 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325301 */   // GIR_Coverage, 11953,
     /*  325301 */   GIR_EraseRootFromParent_Done,
     /*  325302 */ // Label 4893: @325302
     /*  325302 */ GIM_Try, /*On fail goto*//*Label 4894*/ GIMT_Encode4(325396), // Rule ID 11954 //
     /*  325307 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  325310 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  325313 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325320 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325331 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325335 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325342 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325342 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325345 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325349 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325364 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325367 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325371 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325376 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325378 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325385 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325390 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325395 */   // GIR_Coverage, 11954,
     /*  325395 */   GIR_EraseRootFromParent_Done,
     /*  325396 */ // Label 4894: @325396
     /*  325396 */ GIM_Try, /*On fail goto*//*Label 4895*/ GIMT_Encode4(325490), // Rule ID 11955 //
     /*  325401 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  325404 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  325407 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325414 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325421 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325425 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325429 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325436 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325436 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325439 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325443 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325458 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325461 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325465 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325472 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325479 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325484 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325489 */   // GIR_Coverage, 11955,
     /*  325489 */   GIR_EraseRootFromParent_Done,
     /*  325490 */ // Label 4895: @325490
     /*  325490 */ GIM_Try, /*On fail goto*//*Label 4896*/ GIMT_Encode4(325584), // Rule ID 11956 //
     /*  325495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  325498 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  325501 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325508 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325530 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325530 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325533 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325537 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325552 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325555 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325559 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325564 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325566 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325573 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325578 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325583 */   // GIR_Coverage, 11956,
     /*  325583 */   GIR_EraseRootFromParent_Done,
     /*  325584 */ // Label 4896: @325584
     /*  325584 */ GIM_Try, /*On fail goto*//*Label 4897*/ GIMT_Encode4(325678), // Rule ID 12012 //
     /*  325589 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  325592 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  325595 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325602 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325624 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325624 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325627 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325631 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325646 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325649 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325653 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325658 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325660 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325667 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325672 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325677 */   // GIR_Coverage, 12012,
     /*  325677 */   GIR_EraseRootFromParent_Done,
     /*  325678 */ // Label 4897: @325678
     /*  325678 */ GIM_Try, /*On fail goto*//*Label 4898*/ GIMT_Encode4(325772), // Rule ID 12013 //
     /*  325683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  325686 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  325689 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325696 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325707 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325711 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325718 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325718 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325721 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325725 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325740 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325743 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325747 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325752 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325754 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325761 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325766 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325771 */   // GIR_Coverage, 12013,
     /*  325771 */   GIR_EraseRootFromParent_Done,
     /*  325772 */ // Label 4898: @325772
     /*  325772 */ GIM_Try, /*On fail goto*//*Label 4899*/ GIMT_Encode4(325866), // Rule ID 12014 //
     /*  325777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  325780 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  325783 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325790 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325801 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325812 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325812 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325815 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325819 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325834 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325837 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325841 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325846 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325848 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325855 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325860 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325865 */   // GIR_Coverage, 12014,
     /*  325865 */   GIR_EraseRootFromParent_Done,
     /*  325866 */ // Label 4899: @325866
     /*  325866 */ GIM_Try, /*On fail goto*//*Label 4900*/ GIMT_Encode4(325960), // Rule ID 12015 //
     /*  325871 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  325874 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  325877 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325884 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325891 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325895 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325899 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  325906 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  325906 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  325909 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  325913 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  325918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  325923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  325928 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  325931 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  325935 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  325937 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  325940 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  325942 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  325949 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325954 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  325959 */   // GIR_Coverage, 12015,
     /*  325959 */   GIR_EraseRootFromParent_Done,
     /*  325960 */ // Label 4900: @325960
     /*  325960 */ GIM_Try, /*On fail goto*//*Label 4901*/ GIMT_Encode4(326054), // Rule ID 12016 //
     /*  325965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  325968 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  325971 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  325978 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  325985 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  325989 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  325993 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326000 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  326000 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  326003 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  326007 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  326012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326022 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  326025 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326029 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  326031 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  326034 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  326036 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  326043 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326048 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  326053 */   // GIR_Coverage, 12016,
     /*  326053 */   GIR_EraseRootFromParent_Done,
     /*  326054 */ // Label 4901: @326054
     /*  326054 */ GIM_Try, /*On fail goto*//*Label 4902*/ GIMT_Encode4(326118), // Rule ID 12048 //
     /*  326059 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  326062 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326065 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326072 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326094 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326094 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326097 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326116 */   GIR_RootConstrainSelectedInstOperands,
     /*  326117 */   // GIR_Coverage, 12048,
     /*  326117 */   GIR_EraseRootFromParent_Done,
     /*  326118 */ // Label 4902: @326118
     /*  326118 */ GIM_Try, /*On fail goto*//*Label 4903*/ GIMT_Encode4(326182), // Rule ID 12049 //
     /*  326123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  326126 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326129 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326147 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326151 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326158 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326161 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326173 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326176 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326180 */   GIR_RootConstrainSelectedInstOperands,
     /*  326181 */   // GIR_Coverage, 12049,
     /*  326181 */   GIR_EraseRootFromParent_Done,
     /*  326182 */ // Label 4903: @326182
     /*  326182 */ GIM_Try, /*On fail goto*//*Label 4904*/ GIMT_Encode4(326246), // Rule ID 12050 //
     /*  326187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  326190 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326193 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326211 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326215 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326222 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326225 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326237 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326240 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326244 */   GIR_RootConstrainSelectedInstOperands,
     /*  326245 */   // GIR_Coverage, 12050,
     /*  326245 */   GIR_EraseRootFromParent_Done,
     /*  326246 */ // Label 4904: @326246
     /*  326246 */ GIM_Try, /*On fail goto*//*Label 4905*/ GIMT_Encode4(326310), // Rule ID 12051 //
     /*  326251 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  326254 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326257 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326275 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326279 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326286 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326301 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326304 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326308 */   GIR_RootConstrainSelectedInstOperands,
     /*  326309 */   // GIR_Coverage, 12051,
     /*  326309 */   GIR_EraseRootFromParent_Done,
     /*  326310 */ // Label 4905: @326310
     /*  326310 */ GIM_Try, /*On fail goto*//*Label 4906*/ GIMT_Encode4(326374), // Rule ID 12052 //
     /*  326315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  326318 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326321 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326328 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326339 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326343 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326350 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326353 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326365 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326372 */   GIR_RootConstrainSelectedInstOperands,
     /*  326373 */   // GIR_Coverage, 12052,
     /*  326373 */   GIR_EraseRootFromParent_Done,
     /*  326374 */ // Label 4906: @326374
     /*  326374 */ GIM_Try, /*On fail goto*//*Label 4907*/ GIMT_Encode4(326438), // Rule ID 12072 //
     /*  326379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  326382 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  326385 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326392 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326414 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326417 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326436 */   GIR_RootConstrainSelectedInstOperands,
     /*  326437 */   // GIR_Coverage, 12072,
     /*  326437 */   GIR_EraseRootFromParent_Done,
     /*  326438 */ // Label 4907: @326438
     /*  326438 */ GIM_Try, /*On fail goto*//*Label 4908*/ GIMT_Encode4(326502), // Rule ID 12073 //
     /*  326443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  326446 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  326449 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326456 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326463 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326467 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326471 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326478 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326481 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326496 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326500 */   GIR_RootConstrainSelectedInstOperands,
     /*  326501 */   // GIR_Coverage, 12073,
     /*  326501 */   GIR_EraseRootFromParent_Done,
     /*  326502 */ // Label 4908: @326502
     /*  326502 */ GIM_Try, /*On fail goto*//*Label 4909*/ GIMT_Encode4(326566), // Rule ID 12074 //
     /*  326507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  326510 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  326513 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326520 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326535 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326542 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326542 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326545 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326557 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326560 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326564 */   GIR_RootConstrainSelectedInstOperands,
     /*  326565 */   // GIR_Coverage, 12074,
     /*  326565 */   GIR_EraseRootFromParent_Done,
     /*  326566 */ // Label 4909: @326566
     /*  326566 */ GIM_Try, /*On fail goto*//*Label 4910*/ GIMT_Encode4(326630), // Rule ID 12075 //
     /*  326571 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  326574 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  326577 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326606 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326621 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326624 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326628 */   GIR_RootConstrainSelectedInstOperands,
     /*  326629 */   // GIR_Coverage, 12075,
     /*  326629 */   GIR_EraseRootFromParent_Done,
     /*  326630 */ // Label 4910: @326630
     /*  326630 */ GIM_Try, /*On fail goto*//*Label 4911*/ GIMT_Encode4(326694), // Rule ID 12076 //
     /*  326635 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  326638 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  326641 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326648 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  326659 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326663 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  326670 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  326670 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_D16_t16),
     /*  326673 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  326680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  326685 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  326688 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326692 */   GIR_RootConstrainSelectedInstOperands,
     /*  326693 */   // GIR_Coverage, 12076,
     /*  326693 */   GIR_EraseRootFromParent_Done,
     /*  326694 */ // Label 4911: @326694
     /*  326694 */ GIM_Try, /*On fail goto*//*Label 4912*/ GIMT_Encode4(326766), // Rule ID 9681 //
     /*  326699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  326702 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326705 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326712 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  326724 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326728 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  326735 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  326735 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  326738 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  326745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  326750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  326755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  326760 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326764 */   GIR_RootConstrainSelectedInstOperands,
     /*  326765 */   // GIR_Coverage, 9681,
     /*  326765 */   GIR_EraseRootFromParent_Done,
     /*  326766 */ // Label 4912: @326766
     /*  326766 */ GIM_Try, /*On fail goto*//*Label 4913*/ GIMT_Encode4(326838), // Rule ID 9682 //
     /*  326771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  326774 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326777 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326784 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  326796 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326800 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  326807 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  326807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  326810 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  326817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  326822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  326827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  326832 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326836 */   GIR_RootConstrainSelectedInstOperands,
     /*  326837 */   // GIR_Coverage, 9682,
     /*  326837 */   GIR_EraseRootFromParent_Done,
     /*  326838 */ // Label 4913: @326838
     /*  326838 */ GIM_Try, /*On fail goto*//*Label 4914*/ GIMT_Encode4(326910), // Rule ID 9683 //
     /*  326843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  326846 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326849 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  326868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  326879 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  326879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  326882 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  326889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  326894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  326899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  326904 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326908 */   GIR_RootConstrainSelectedInstOperands,
     /*  326909 */   // GIR_Coverage, 9683,
     /*  326909 */   GIR_EraseRootFromParent_Done,
     /*  326910 */ // Label 4914: @326910
     /*  326910 */ GIM_Try, /*On fail goto*//*Label 4915*/ GIMT_Encode4(326982), // Rule ID 9684 //
     /*  326915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  326918 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326921 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  326928 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  326936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  326940 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  326944 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  326951 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  326951 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  326954 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  326956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  326961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  326966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  326971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  326976 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  326980 */   GIR_RootConstrainSelectedInstOperands,
     /*  326981 */   // GIR_Coverage, 9684,
     /*  326981 */   GIR_EraseRootFromParent_Done,
     /*  326982 */ // Label 4915: @326982
     /*  326982 */ GIM_Try, /*On fail goto*//*Label 4916*/ GIMT_Encode4(327054), // Rule ID 9685 //
     /*  326987 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  326990 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  326993 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327000 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327023 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  327023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327026 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  327028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327048 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327052 */   GIR_RootConstrainSelectedInstOperands,
     /*  327053 */   // GIR_Coverage, 9685,
     /*  327053 */   GIR_EraseRootFromParent_Done,
     /*  327054 */ // Label 4916: @327054
     /*  327054 */ GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(327126), // Rule ID 9731 //
     /*  327059 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  327062 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  327065 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327072 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327088 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327095 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  327095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327098 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  327100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327124 */   GIR_RootConstrainSelectedInstOperands,
     /*  327125 */   // GIR_Coverage, 9731,
     /*  327125 */   GIR_EraseRootFromParent_Done,
     /*  327126 */ // Label 4917: @327126
     /*  327126 */ GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(327198), // Rule ID 9732 //
     /*  327131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  327134 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  327137 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327144 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327152 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327167 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  327167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327170 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  327172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327192 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327196 */   GIR_RootConstrainSelectedInstOperands,
     /*  327197 */   // GIR_Coverage, 9732,
     /*  327197 */   GIR_EraseRootFromParent_Done,
     /*  327198 */ // Label 4918: @327198
     /*  327198 */ GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(327270), // Rule ID 9733 //
     /*  327203 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  327206 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  327209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327224 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327228 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327232 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327239 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  327239 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327242 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  327244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327264 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327268 */   GIR_RootConstrainSelectedInstOperands,
     /*  327269 */   // GIR_Coverage, 9733,
     /*  327269 */   GIR_EraseRootFromParent_Done,
     /*  327270 */ // Label 4919: @327270
     /*  327270 */ GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(327342), // Rule ID 9734 //
     /*  327275 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  327278 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  327281 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327288 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327311 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  327311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327314 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  327316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327336 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327340 */   GIR_RootConstrainSelectedInstOperands,
     /*  327341 */   // GIR_Coverage, 9734,
     /*  327341 */   GIR_EraseRootFromParent_Done,
     /*  327342 */ // Label 4920: @327342
     /*  327342 */ GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(327414), // Rule ID 9735 //
     /*  327347 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  327350 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  327353 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327360 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327368 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327372 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327376 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327383 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  327383 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327386 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  327388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327408 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327412 */   GIR_RootConstrainSelectedInstOperands,
     /*  327413 */   // GIR_Coverage, 9735,
     /*  327413 */   GIR_EraseRootFromParent_Done,
     /*  327414 */ // Label 4921: @327414
     /*  327414 */ GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(327516), // Rule ID 9781 //
     /*  327419 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  327422 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  327425 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327432 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327444 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327448 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327455 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  327455 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  327458 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327462 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  327467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327487 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327491 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  327493 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  327496 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  327498 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  327505 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327510 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327515 */   // GIR_Coverage, 9781,
     /*  327515 */   GIR_EraseRootFromParent_Done,
     /*  327516 */ // Label 4922: @327516
     /*  327516 */ GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(327618), // Rule ID 9782 //
     /*  327521 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  327524 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  327527 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327534 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327546 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327550 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327557 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  327557 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  327560 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327564 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  327569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327589 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327593 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  327595 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  327598 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  327600 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  327607 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327612 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327617 */   // GIR_Coverage, 9782,
     /*  327617 */   GIR_EraseRootFromParent_Done,
     /*  327618 */ // Label 4923: @327618
     /*  327618 */ GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(327720), // Rule ID 9783 //
     /*  327623 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  327626 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  327629 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327636 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327659 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  327659 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  327662 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327666 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  327671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327691 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327695 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  327697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  327700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  327702 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  327709 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327714 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327719 */   // GIR_Coverage, 9783,
     /*  327719 */   GIR_EraseRootFromParent_Done,
     /*  327720 */ // Label 4924: @327720
     /*  327720 */ GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(327822), // Rule ID 9784 //
     /*  327725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  327728 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  327731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327738 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327761 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  327761 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  327764 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327768 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  327773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327793 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327797 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  327799 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  327802 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  327804 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  327811 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327816 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327821 */   // GIR_Coverage, 9784,
     /*  327821 */   GIR_EraseRootFromParent_Done,
     /*  327822 */ // Label 4925: @327822
     /*  327822 */ GIM_Try, /*On fail goto*//*Label 4926*/ GIMT_Encode4(327924), // Rule ID 9785 //
     /*  327827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  327830 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  327833 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327840 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327848 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327852 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327856 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327863 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  327863 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  327866 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327870 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  327875 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327895 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  327899 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  327901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  327904 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  327906 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  327913 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327918 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  327923 */   // GIR_Coverage, 9785,
     /*  327923 */   GIR_EraseRootFromParent_Done,
     /*  327924 */ // Label 4926: @327924
     /*  327924 */ GIM_Try, /*On fail goto*//*Label 4927*/ GIMT_Encode4(328026), // Rule ID 9831 //
     /*  327929 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  327932 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  327935 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  327942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  327950 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  327954 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  327958 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  327965 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  327965 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  327968 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  327972 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  327977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  327982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  327987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  327992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  327997 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328001 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  328003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  328006 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  328008 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  328015 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328020 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328025 */   // GIR_Coverage, 9831,
     /*  328025 */   GIR_EraseRootFromParent_Done,
     /*  328026 */ // Label 4927: @328026
     /*  328026 */ GIM_Try, /*On fail goto*//*Label 4928*/ GIMT_Encode4(328128), // Rule ID 9832 //
     /*  328031 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  328034 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328037 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328044 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328052 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328056 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328060 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  328067 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  328067 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  328070 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  328074 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  328079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  328084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  328089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  328094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  328099 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328103 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  328105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  328108 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  328110 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  328117 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328122 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328127 */   // GIR_Coverage, 9832,
     /*  328127 */   GIR_EraseRootFromParent_Done,
     /*  328128 */ // Label 4928: @328128
     /*  328128 */ GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(328230), // Rule ID 9833 //
     /*  328133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  328136 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328139 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328146 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328158 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328162 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  328169 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  328169 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  328172 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  328176 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  328181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  328186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  328191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  328196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  328201 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328205 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  328207 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  328210 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  328212 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  328219 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328224 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328229 */   // GIR_Coverage, 9833,
     /*  328229 */   GIR_EraseRootFromParent_Done,
     /*  328230 */ // Label 4929: @328230
     /*  328230 */ GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(328332), // Rule ID 9834 //
     /*  328235 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  328238 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328241 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328248 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  328271 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  328271 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  328274 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  328278 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  328283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  328288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  328293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  328298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  328303 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  328309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  328312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  328314 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  328321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328326 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328331 */   // GIR_Coverage, 9834,
     /*  328331 */   GIR_EraseRootFromParent_Done,
     /*  328332 */ // Label 4930: @328332
     /*  328332 */ GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(328434), // Rule ID 9835 //
     /*  328337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  328340 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328343 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328350 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328362 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328366 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  328373 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  328373 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  328376 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  328380 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  328385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  328390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  328395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  328400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  328405 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328409 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  328411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  328414 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  328416 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  328423 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328428 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328433 */   // GIR_Coverage, 9835,
     /*  328433 */   GIR_EraseRootFromParent_Done,
     /*  328434 */ // Label 4931: @328434
     /*  328434 */ GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(328506), // Rule ID 9847 //
     /*  328439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  328442 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  328445 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328452 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328464 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328468 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  328475 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  328475 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16_SADDR),
     /*  328478 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  328485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  328490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  328495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  328500 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328504 */   GIR_RootConstrainSelectedInstOperands,
     /*  328505 */   // GIR_Coverage, 9847,
     /*  328505 */   GIR_EraseRootFromParent_Done,
     /*  328506 */ // Label 4932: @328506
     /*  328506 */ GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(328578), // Rule ID 9877 //
     /*  328511 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  328514 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328517 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328524 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328532 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  328536 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328540 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  328547 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  328547 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16_SADDR),
     /*  328550 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  328557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  328562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  328567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  328572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328576 */   GIR_RootConstrainSelectedInstOperands,
     /*  328577 */   // GIR_Coverage, 9877,
     /*  328577 */   GIR_EraseRootFromParent_Done,
     /*  328578 */ // Label 4933: @328578
     /*  328578 */ GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(328643), // Rule ID 9676 //
     /*  328583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  328586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  328589 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328596 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328608 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328612 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  328619 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  328619 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  328622 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  328629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  328634 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  328637 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328641 */   GIR_RootConstrainSelectedInstOperands,
     /*  328642 */   // GIR_Coverage, 9676,
     /*  328642 */   GIR_EraseRootFromParent_Done,
     /*  328643 */ // Label 4934: @328643
     /*  328643 */ GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(328708), // Rule ID 9677 //
     /*  328648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  328651 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  328654 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328661 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328669 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328673 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328677 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  328684 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  328684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  328687 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  328694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  328699 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  328702 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328706 */   GIR_RootConstrainSelectedInstOperands,
     /*  328707 */   // GIR_Coverage, 9677,
     /*  328707 */   GIR_EraseRootFromParent_Done,
     /*  328708 */ // Label 4935: @328708
     /*  328708 */ GIM_Try, /*On fail goto*//*Label 4936*/ GIMT_Encode4(328773), // Rule ID 9678 //
     /*  328713 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  328716 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  328719 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328726 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328734 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328738 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328742 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  328749 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  328749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  328752 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  328759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  328764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  328767 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328771 */   GIR_RootConstrainSelectedInstOperands,
     /*  328772 */   // GIR_Coverage, 9678,
     /*  328772 */   GIR_EraseRootFromParent_Done,
     /*  328773 */ // Label 4936: @328773
     /*  328773 */ GIM_Try, /*On fail goto*//*Label 4937*/ GIMT_Encode4(328838), // Rule ID 9679 //
     /*  328778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  328781 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  328784 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328791 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328799 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328803 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328807 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  328814 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  328814 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  328817 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  328824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  328829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  328832 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328836 */   GIR_RootConstrainSelectedInstOperands,
     /*  328837 */   // GIR_Coverage, 9679,
     /*  328837 */   GIR_EraseRootFromParent_Done,
     /*  328838 */ // Label 4937: @328838
     /*  328838 */ GIM_Try, /*On fail goto*//*Label 4938*/ GIMT_Encode4(328903), // Rule ID 9680 //
     /*  328843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  328846 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  328849 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  328879 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  328879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  328882 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  328889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  328894 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  328897 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328901 */   GIR_RootConstrainSelectedInstOperands,
     /*  328902 */   // GIR_Coverage, 9680,
     /*  328902 */   GIR_EraseRootFromParent_Done,
     /*  328903 */ // Label 4938: @328903
     /*  328903 */ GIM_Try, /*On fail goto*//*Label 4939*/ GIMT_Encode4(328968), // Rule ID 9726 //
     /*  328908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  328911 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328914 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328921 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  328937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  328944 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  328944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  328947 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  328949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  328954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  328959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  328962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  328966 */   GIR_RootConstrainSelectedInstOperands,
     /*  328967 */   // GIR_Coverage, 9726,
     /*  328967 */   GIR_EraseRootFromParent_Done,
     /*  328968 */ // Label 4939: @328968
     /*  328968 */ GIM_Try, /*On fail goto*//*Label 4940*/ GIMT_Encode4(329033), // Rule ID 9727 //
     /*  328973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  328976 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  328979 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  328986 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  328994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  328998 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329002 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329009 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  329009 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329012 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  329014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329024 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  329027 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329031 */   GIR_RootConstrainSelectedInstOperands,
     /*  329032 */   // GIR_Coverage, 9727,
     /*  329032 */   GIR_EraseRootFromParent_Done,
     /*  329033 */ // Label 4940: @329033
     /*  329033 */ GIM_Try, /*On fail goto*//*Label 4941*/ GIMT_Encode4(329098), // Rule ID 9728 //
     /*  329038 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  329041 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329044 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329051 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329059 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329063 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329067 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329074 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  329074 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329077 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  329079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  329092 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329096 */   GIR_RootConstrainSelectedInstOperands,
     /*  329097 */   // GIR_Coverage, 9728,
     /*  329097 */   GIR_EraseRootFromParent_Done,
     /*  329098 */ // Label 4941: @329098
     /*  329098 */ GIM_Try, /*On fail goto*//*Label 4942*/ GIMT_Encode4(329163), // Rule ID 9729 //
     /*  329103 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  329106 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329109 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329116 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329139 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  329139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  329144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329154 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  329157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329161 */   GIR_RootConstrainSelectedInstOperands,
     /*  329162 */   // GIR_Coverage, 9729,
     /*  329162 */   GIR_EraseRootFromParent_Done,
     /*  329163 */ // Label 4942: @329163
     /*  329163 */ GIM_Try, /*On fail goto*//*Label 4943*/ GIMT_Encode4(329228), // Rule ID 9730 //
     /*  329168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  329171 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329174 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329181 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329197 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329204 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  329204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329207 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  329209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  329222 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329226 */   GIR_RootConstrainSelectedInstOperands,
     /*  329227 */   // GIR_Coverage, 9730,
     /*  329227 */   GIR_EraseRootFromParent_Done,
     /*  329228 */ // Label 4943: @329228
     /*  329228 */ GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(329323), // Rule ID 9776 //
     /*  329233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  329236 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  329239 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329246 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329258 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329262 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329269 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329269 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329272 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329276 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329291 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329294 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329298 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329300 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329303 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329305 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329312 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329317 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329322 */   // GIR_Coverage, 9776,
     /*  329322 */   GIR_EraseRootFromParent_Done,
     /*  329323 */ // Label 4944: @329323
     /*  329323 */ GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(329418), // Rule ID 9777 //
     /*  329328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  329331 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  329334 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329341 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329353 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329357 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329364 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329364 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329367 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329371 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329386 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329389 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329393 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329395 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329398 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329400 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329407 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329412 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329417 */   // GIR_Coverage, 9777,
     /*  329417 */   GIR_EraseRootFromParent_Done,
     /*  329418 */ // Label 4945: @329418
     /*  329418 */ GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(329513), // Rule ID 9778 //
     /*  329423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  329426 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  329429 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329436 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329459 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329459 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329462 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329466 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329481 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329484 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329488 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329495 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329502 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329507 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329512 */   // GIR_Coverage, 9778,
     /*  329512 */   GIR_EraseRootFromParent_Done,
     /*  329513 */ // Label 4946: @329513
     /*  329513 */ GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(329608), // Rule ID 9779 //
     /*  329518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  329521 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  329524 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329531 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329543 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329547 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329554 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329554 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329557 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329561 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329576 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329579 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329583 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329585 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329588 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329590 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329597 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329602 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329607 */   // GIR_Coverage, 9779,
     /*  329607 */   GIR_EraseRootFromParent_Done,
     /*  329608 */ // Label 4947: @329608
     /*  329608 */ GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(329703), // Rule ID 9780 //
     /*  329613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  329616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  329619 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329626 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329638 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329642 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329649 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329649 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329652 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329656 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329671 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329674 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329678 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329685 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329692 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329697 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329702 */   // GIR_Coverage, 9780,
     /*  329702 */   GIR_EraseRootFromParent_Done,
     /*  329703 */ // Label 4948: @329703
     /*  329703 */ GIM_Try, /*On fail goto*//*Label 4949*/ GIMT_Encode4(329798), // Rule ID 9826 //
     /*  329708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  329711 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329714 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329721 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329737 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329744 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329744 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329747 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329751 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329766 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329769 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329773 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329780 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329787 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329792 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329797 */   // GIR_Coverage, 9826,
     /*  329797 */   GIR_EraseRootFromParent_Done,
     /*  329798 */ // Label 4949: @329798
     /*  329798 */ GIM_Try, /*On fail goto*//*Label 4950*/ GIMT_Encode4(329893), // Rule ID 9827 //
     /*  329803 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  329806 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329809 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329816 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329832 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329839 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329839 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329842 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329846 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329861 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329864 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329868 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329873 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329875 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329882 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329887 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329892 */   // GIR_Coverage, 9827,
     /*  329892 */   GIR_EraseRootFromParent_Done,
     /*  329893 */ // Label 4950: @329893
     /*  329893 */ GIM_Try, /*On fail goto*//*Label 4951*/ GIMT_Encode4(329988), // Rule ID 9828 //
     /*  329898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  329901 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329904 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  329911 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  329919 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329923 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  329927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  329934 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  329934 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  329937 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  329941 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  329946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  329951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  329956 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  329959 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  329963 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  329965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  329968 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  329970 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  329977 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  329982 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  329987 */   // GIR_Coverage, 9828,
     /*  329987 */   GIR_EraseRootFromParent_Done,
     /*  329988 */ // Label 4951: @329988
     /*  329988 */ GIM_Try, /*On fail goto*//*Label 4952*/ GIMT_Encode4(330083), // Rule ID 9829 //
     /*  329993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  329996 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  329999 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330006 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330018 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330022 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330029 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  330029 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  330032 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  330036 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  330041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330051 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  330054 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330058 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  330060 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  330063 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  330065 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  330072 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330077 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  330082 */   // GIR_Coverage, 9829,
     /*  330082 */   GIR_EraseRootFromParent_Done,
     /*  330083 */ // Label 4952: @330083
     /*  330083 */ GIM_Try, /*On fail goto*//*Label 4953*/ GIMT_Encode4(330178), // Rule ID 9830 //
     /*  330088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  330091 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  330094 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330101 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330113 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330117 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330124 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  330124 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  330127 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  330131 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  330136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330146 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  330149 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330153 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  330155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  330158 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  330160 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  330167 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330172 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  330177 */   // GIR_Coverage, 9830,
     /*  330177 */   GIR_EraseRootFromParent_Done,
     /*  330178 */ // Label 4953: @330178
     /*  330178 */ GIM_Try, /*On fail goto*//*Label 4954*/ GIMT_Encode4(330243), // Rule ID 9842 //
     /*  330183 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  330186 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330189 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330196 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330219 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330222 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330234 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330237 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330241 */   GIR_RootConstrainSelectedInstOperands,
     /*  330242 */   // GIR_Coverage, 9842,
     /*  330242 */   GIR_EraseRootFromParent_Done,
     /*  330243 */ // Label 4954: @330243
     /*  330243 */ GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(330308), // Rule ID 9843 //
     /*  330248 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  330251 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330254 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330261 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330277 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330284 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330306 */   GIR_RootConstrainSelectedInstOperands,
     /*  330307 */   // GIR_Coverage, 9843,
     /*  330307 */   GIR_EraseRootFromParent_Done,
     /*  330308 */ // Label 4955: @330308
     /*  330308 */ GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(330373), // Rule ID 9844 //
     /*  330313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  330316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330319 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330326 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330338 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330342 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330349 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330352 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330364 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330367 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330371 */   GIR_RootConstrainSelectedInstOperands,
     /*  330372 */   // GIR_Coverage, 9844,
     /*  330372 */   GIR_EraseRootFromParent_Done,
     /*  330373 */ // Label 4956: @330373
     /*  330373 */ GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(330438), // Rule ID 9845 //
     /*  330378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  330381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330384 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330391 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330414 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330417 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330436 */   GIR_RootConstrainSelectedInstOperands,
     /*  330437 */   // GIR_Coverage, 9845,
     /*  330437 */   GIR_EraseRootFromParent_Done,
     /*  330438 */ // Label 4957: @330438
     /*  330438 */ GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(330503), // Rule ID 9846 //
     /*  330443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  330446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330449 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330456 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330464 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330468 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330472 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330479 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330479 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330482 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330501 */   GIR_RootConstrainSelectedInstOperands,
     /*  330502 */   // GIR_Coverage, 9846,
     /*  330502 */   GIR_EraseRootFromParent_Done,
     /*  330503 */ // Label 4958: @330503
     /*  330503 */ GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(330568), // Rule ID 9872 //
     /*  330508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  330511 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  330514 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330521 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330537 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330544 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330559 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330562 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330566 */   GIR_RootConstrainSelectedInstOperands,
     /*  330567 */   // GIR_Coverage, 9872,
     /*  330567 */   GIR_EraseRootFromParent_Done,
     /*  330568 */ // Label 4959: @330568
     /*  330568 */ GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(330633), // Rule ID 9873 //
     /*  330573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  330576 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  330579 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330586 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330609 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330612 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330624 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330627 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330631 */   GIR_RootConstrainSelectedInstOperands,
     /*  330632 */   // GIR_Coverage, 9873,
     /*  330632 */   GIR_EraseRootFromParent_Done,
     /*  330633 */ // Label 4960: @330633
     /*  330633 */ GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(330698), // Rule ID 9874 //
     /*  330638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  330641 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  330644 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330651 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330659 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330663 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330667 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330674 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330674 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330677 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330689 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330692 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330696 */   GIR_RootConstrainSelectedInstOperands,
     /*  330697 */   // GIR_Coverage, 9874,
     /*  330697 */   GIR_EraseRootFromParent_Done,
     /*  330698 */ // Label 4961: @330698
     /*  330698 */ GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(330763), // Rule ID 9875 //
     /*  330703 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  330706 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  330709 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330716 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330732 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330739 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330754 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330757 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330761 */   GIR_RootConstrainSelectedInstOperands,
     /*  330762 */   // GIR_Coverage, 9875,
     /*  330762 */   GIR_EraseRootFromParent_Done,
     /*  330763 */ // Label 4962: @330763
     /*  330763 */ GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(330828), // Rule ID 9876 //
     /*  330768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  330771 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  330774 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330781 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  330789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  330793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  330804 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  330804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_D16_t16),
     /*  330807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  330809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  330814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  330819 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  330822 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330826 */   GIR_RootConstrainSelectedInstOperands,
     /*  330827 */   // GIR_Coverage, 9876,
     /*  330827 */   GIR_EraseRootFromParent_Done,
     /*  330828 */ // Label 4963: @330828
     /*  330828 */ GIM_Reject,
     /*  330829 */ // Label 4753: @330829
     /*  330829 */ GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(330897), // Rule ID 8662 //
     /*  330834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  330837 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330840 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  330851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330855 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
     /*  330859 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  330866 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  330866 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_SGPR_IMM),
     /*  330869 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  330871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  330876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  330881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  330886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  330891 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330895 */   GIR_RootConstrainSelectedInstOperands,
     /*  330896 */   // GIR_Coverage, 8662,
     /*  330896 */   GIR_EraseRootFromParent_Done,
     /*  330897 */ // Label 4964: @330897
     /*  330897 */ GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(330965), // Rule ID 8674 //
     /*  330902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  330905 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330908 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  330915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  330919 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330923 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
     /*  330927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  330934 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  330934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_SGPR_IMM),
     /*  330937 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  330939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  330944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  330949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  330954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  330959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  330963 */   GIR_RootConstrainSelectedInstOperands,
     /*  330964 */   // GIR_Coverage, 8674,
     /*  330964 */   GIR_EraseRootFromParent_Done,
     /*  330965 */ // Label 4965: @330965
     /*  330965 */ GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(331026), // Rule ID 8660 //
     /*  330970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  330973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  330976 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  330983 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  330987 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  330991 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
     /*  330995 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  331002 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  331002 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_IMM),
     /*  331005 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  331007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  331012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  331017 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331020 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331024 */   GIR_RootConstrainSelectedInstOperands,
     /*  331025 */   // GIR_Coverage, 8660,
     /*  331025 */   GIR_EraseRootFromParent_Done,
     /*  331026 */ // Label 4966: @331026
     /*  331026 */ GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(331087), // Rule ID 8672 //
     /*  331031 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  331034 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331037 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  331044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  331048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331052 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
     /*  331056 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  331063 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  331063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_IMM),
     /*  331066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  331068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  331073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  331078 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331081 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331085 */   GIR_RootConstrainSelectedInstOperands,
     /*  331086 */   // GIR_Coverage, 8672,
     /*  331086 */   GIR_EraseRootFromParent_Done,
     /*  331087 */ // Label 4967: @331087
     /*  331087 */ GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(331153), // Rule ID 8661 //
     /*  331092 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  331095 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331098 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331105 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  331109 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331113 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
     /*  331117 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  331124 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  331124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_SGPR_IMM),
     /*  331127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  331129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  331134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  331147 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331151 */   GIR_RootConstrainSelectedInstOperands,
     /*  331152 */   // GIR_Coverage, 8661,
     /*  331152 */   GIR_EraseRootFromParent_Done,
     /*  331153 */ // Label 4968: @331153
     /*  331153 */ GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(331219), // Rule ID 8673 //
     /*  331158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  331161 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331164 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  331171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  331175 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331179 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
     /*  331183 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  331190 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  331190 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_SGPR_IMM),
     /*  331193 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  331195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  331200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331205 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  331213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331217 */   GIR_RootConstrainSelectedInstOperands,
     /*  331218 */   // GIR_Coverage, 8673,
     /*  331218 */   GIR_EraseRootFromParent_Done,
     /*  331219 */ // Label 4969: @331219
     /*  331219 */ GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(331272), // Rule ID 8663 //
     /*  331224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  331227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331230 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  331241 */   // MIs[0] sbase
     /*  331241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  331245 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  331249 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
     /*  331253 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  331253 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_IMM),
     /*  331256 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  331258 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  331260 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331263 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331266 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331270 */   GIR_RootConstrainSelectedInstOperands,
     /*  331271 */   // GIR_Coverage, 8663,
     /*  331271 */   GIR_EraseRootFromParent_Done,
     /*  331272 */ // Label 4970: @331272
     /*  331272 */ GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(331325), // Rule ID 8675 //
     /*  331277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  331280 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331283 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  331290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  331294 */   // MIs[0] sbase
     /*  331294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  331298 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  331302 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
     /*  331306 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  331306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_IMM),
     /*  331309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  331311 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  331313 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331316 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331319 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331323 */   GIR_RootConstrainSelectedInstOperands,
     /*  331324 */   // GIR_Coverage, 8675,
     /*  331324 */   GIR_EraseRootFromParent_Done,
     /*  331325 */ // Label 4971: @331325
     /*  331325 */ GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(331395), // Rule ID 24966 //
     /*  331330 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  331333 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331336 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331343 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331363 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  331366 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331383 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331386 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331389 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331393 */   GIR_RootConstrainSelectedInstOperands,
     /*  331394 */   // GIR_Coverage, 24966,
     /*  331394 */   GIR_EraseRootFromParent_Done,
     /*  331395 */ // Label 4972: @331395
     /*  331395 */ GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(331465), // Rule ID 24967 //
     /*  331400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  331403 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331406 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331413 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331418 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331422 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331426 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331433 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  331436 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331453 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331456 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331459 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331463 */   GIR_RootConstrainSelectedInstOperands,
     /*  331464 */   // GIR_Coverage, 24967,
     /*  331464 */   GIR_EraseRootFromParent_Done,
     /*  331465 */ // Label 4973: @331465
     /*  331465 */ GIM_Try, /*On fail goto*//*Label 4974*/ GIMT_Encode4(331535), // Rule ID 24968 //
     /*  331470 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  331473 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331476 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331483 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331492 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331496 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331503 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  331506 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331523 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331526 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331529 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331533 */   GIR_RootConstrainSelectedInstOperands,
     /*  331534 */   // GIR_Coverage, 24968,
     /*  331534 */   GIR_EraseRootFromParent_Done,
     /*  331535 */ // Label 4974: @331535
     /*  331535 */ GIM_Try, /*On fail goto*//*Label 4975*/ GIMT_Encode4(331605), // Rule ID 24969 //
     /*  331540 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  331543 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331546 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331553 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331562 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331566 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331573 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  331576 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331603 */   GIR_RootConstrainSelectedInstOperands,
     /*  331604 */   // GIR_Coverage, 24969,
     /*  331604 */   GIR_EraseRootFromParent_Done,
     /*  331605 */ // Label 4975: @331605
     /*  331605 */ GIM_Try, /*On fail goto*//*Label 4976*/ GIMT_Encode4(331675), // Rule ID 24970 //
     /*  331610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  331613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331616 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331623 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331643 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  331646 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331663 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331666 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331669 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331673 */   GIR_RootConstrainSelectedInstOperands,
     /*  331674 */   // GIR_Coverage, 24970,
     /*  331674 */   GIR_EraseRootFromParent_Done,
     /*  331675 */ // Label 4976: @331675
     /*  331675 */ GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(331745), // Rule ID 24986 //
     /*  331680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  331683 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331713 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  331716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331733 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331736 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331739 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331743 */   GIR_RootConstrainSelectedInstOperands,
     /*  331744 */   // GIR_Coverage, 24986,
     /*  331744 */   GIR_EraseRootFromParent_Done,
     /*  331745 */ // Label 4977: @331745
     /*  331745 */ GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(331815), // Rule ID 24987 //
     /*  331750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  331753 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331756 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331763 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331768 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331772 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331776 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331783 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  331786 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331803 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331806 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331809 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331813 */   GIR_RootConstrainSelectedInstOperands,
     /*  331814 */   // GIR_Coverage, 24987,
     /*  331814 */   GIR_EraseRootFromParent_Done,
     /*  331815 */ // Label 4978: @331815
     /*  331815 */ GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(331885), // Rule ID 24988 //
     /*  331820 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  331823 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331826 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331833 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331842 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331846 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331853 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  331856 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331873 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331879 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331883 */   GIR_RootConstrainSelectedInstOperands,
     /*  331884 */   // GIR_Coverage, 24988,
     /*  331884 */   GIR_EraseRootFromParent_Done,
     /*  331885 */ // Label 4979: @331885
     /*  331885 */ GIM_Try, /*On fail goto*//*Label 4980*/ GIMT_Encode4(331955), // Rule ID 24989 //
     /*  331890 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  331893 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331896 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331903 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331908 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331912 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331916 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331923 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  331926 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  331933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  331938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  331943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331946 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  331949 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  331953 */   GIR_RootConstrainSelectedInstOperands,
     /*  331954 */   // GIR_Coverage, 24989,
     /*  331954 */   GIR_EraseRootFromParent_Done,
     /*  331955 */ // Label 4980: @331955
     /*  331955 */ GIM_Try, /*On fail goto*//*Label 4981*/ GIMT_Encode4(332025), // Rule ID 24990 //
     /*  331960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  331963 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  331966 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  331973 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  331978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  331982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  331986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  331993 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  331993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  331996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  331998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332013 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332023 */   GIR_RootConstrainSelectedInstOperands,
     /*  332024 */   // GIR_Coverage, 24990,
     /*  332024 */   GIR_EraseRootFromParent_Done,
     /*  332025 */ // Label 4981: @332025
     /*  332025 */ GIM_Try, /*On fail goto*//*Label 4982*/ GIMT_Encode4(332095), // Rule ID 25096 //
     /*  332030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  332033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332036 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332043 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332052 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332056 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332063 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  332066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332093 */   GIR_RootConstrainSelectedInstOperands,
     /*  332094 */   // GIR_Coverage, 25096,
     /*  332094 */   GIR_EraseRootFromParent_Done,
     /*  332095 */ // Label 4982: @332095
     /*  332095 */ GIM_Try, /*On fail goto*//*Label 4983*/ GIMT_Encode4(332165), // Rule ID 25097 //
     /*  332100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  332103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332106 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332113 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332122 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332126 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332133 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  332136 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332153 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332156 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332159 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332163 */   GIR_RootConstrainSelectedInstOperands,
     /*  332164 */   // GIR_Coverage, 25097,
     /*  332164 */   GIR_EraseRootFromParent_Done,
     /*  332165 */ // Label 4983: @332165
     /*  332165 */ GIM_Try, /*On fail goto*//*Label 4984*/ GIMT_Encode4(332235), // Rule ID 25098 //
     /*  332170 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  332173 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332176 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332183 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332192 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332196 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332203 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  332206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332223 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332226 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332229 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332233 */   GIR_RootConstrainSelectedInstOperands,
     /*  332234 */   // GIR_Coverage, 25098,
     /*  332234 */   GIR_EraseRootFromParent_Done,
     /*  332235 */ // Label 4984: @332235
     /*  332235 */ GIM_Try, /*On fail goto*//*Label 4985*/ GIMT_Encode4(332305), // Rule ID 25099 //
     /*  332240 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  332243 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332246 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332253 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332262 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332266 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332273 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  332276 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332293 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332299 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332303 */   GIR_RootConstrainSelectedInstOperands,
     /*  332304 */   // GIR_Coverage, 25099,
     /*  332304 */   GIR_EraseRootFromParent_Done,
     /*  332305 */ // Label 4985: @332305
     /*  332305 */ GIM_Try, /*On fail goto*//*Label 4986*/ GIMT_Encode4(332375), // Rule ID 25100 //
     /*  332310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  332313 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332316 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332323 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332328 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332343 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  332346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332373 */   GIR_RootConstrainSelectedInstOperands,
     /*  332374 */   // GIR_Coverage, 25100,
     /*  332374 */   GIR_EraseRootFromParent_Done,
     /*  332375 */ // Label 4986: @332375
     /*  332375 */ GIM_Try, /*On fail goto*//*Label 4987*/ GIMT_Encode4(332445), // Rule ID 25106 //
     /*  332380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  332383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332386 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332393 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332402 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332413 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  332416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332433 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332436 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332439 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332443 */   GIR_RootConstrainSelectedInstOperands,
     /*  332444 */   // GIR_Coverage, 25106,
     /*  332444 */   GIR_EraseRootFromParent_Done,
     /*  332445 */ // Label 4987: @332445
     /*  332445 */ GIM_Try, /*On fail goto*//*Label 4988*/ GIMT_Encode4(332515), // Rule ID 25107 //
     /*  332450 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  332453 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332456 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332463 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332472 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332476 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332483 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332483 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  332486 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332503 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332506 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332509 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332513 */   GIR_RootConstrainSelectedInstOperands,
     /*  332514 */   // GIR_Coverage, 25107,
     /*  332514 */   GIR_EraseRootFromParent_Done,
     /*  332515 */ // Label 4988: @332515
     /*  332515 */ GIM_Try, /*On fail goto*//*Label 4989*/ GIMT_Encode4(332585), // Rule ID 25108 //
     /*  332520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  332523 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332526 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332533 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332538 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332542 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332546 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332553 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  332556 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332573 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332579 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332583 */   GIR_RootConstrainSelectedInstOperands,
     /*  332584 */   // GIR_Coverage, 25108,
     /*  332584 */   GIR_EraseRootFromParent_Done,
     /*  332585 */ // Label 4989: @332585
     /*  332585 */ GIM_Try, /*On fail goto*//*Label 4990*/ GIMT_Encode4(332655), // Rule ID 25109 //
     /*  332590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  332593 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332608 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332616 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332623 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  332626 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332643 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332653 */   GIR_RootConstrainSelectedInstOperands,
     /*  332654 */   // GIR_Coverage, 25109,
     /*  332654 */   GIR_EraseRootFromParent_Done,
     /*  332655 */ // Label 4990: @332655
     /*  332655 */ GIM_Try, /*On fail goto*//*Label 4991*/ GIMT_Encode4(332725), // Rule ID 25110 //
     /*  332660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  332663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332666 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  332673 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332682 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332686 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  332693 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  332693 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  332696 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  332698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  332703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  332708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332713 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332716 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  332719 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332723 */   GIR_RootConstrainSelectedInstOperands,
     /*  332724 */   // GIR_Coverage, 25110,
     /*  332724 */   GIR_EraseRootFromParent_Done,
     /*  332725 */ // Label 4991: @332725
     /*  332725 */ GIM_Try, /*On fail goto*//*Label 4992*/ GIMT_Encode4(332794), // Rule ID 13870 //
     /*  332730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  332733 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332736 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  332743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332752 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332756 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  332763 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  332763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  332766 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  332768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  332773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  332778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  332788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332792 */   GIR_RootConstrainSelectedInstOperands,
     /*  332793 */   // GIR_Coverage, 13870,
     /*  332793 */   GIR_EraseRootFromParent_Done,
     /*  332794 */ // Label 4992: @332794
     /*  332794 */ GIM_Try, /*On fail goto*//*Label 4993*/ GIMT_Encode4(332863), // Rule ID 13871 //
     /*  332799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  332802 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  332812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  332832 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  332832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  332835 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  332837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  332842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  332847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  332857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332861 */   GIR_RootConstrainSelectedInstOperands,
     /*  332862 */   // GIR_Coverage, 13871,
     /*  332862 */   GIR_EraseRootFromParent_Done,
     /*  332863 */ // Label 4993: @332863
     /*  332863 */ GIM_Try, /*On fail goto*//*Label 4994*/ GIMT_Encode4(332932), // Rule ID 13872 //
     /*  332868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  332871 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332874 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  332881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332890 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332894 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  332901 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  332901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  332904 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  332906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  332911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  332916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  332926 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332930 */   GIR_RootConstrainSelectedInstOperands,
     /*  332931 */   // GIR_Coverage, 13872,
     /*  332931 */   GIR_EraseRootFromParent_Done,
     /*  332932 */ // Label 4994: @332932
     /*  332932 */ GIM_Try, /*On fail goto*//*Label 4995*/ GIMT_Encode4(333001), // Rule ID 13873 //
     /*  332937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  332940 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  332943 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  332950 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  332955 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  332959 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  332963 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  332970 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  332970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  332973 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  332975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  332980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  332985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  332990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  332995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  332999 */   GIR_RootConstrainSelectedInstOperands,
     /*  333000 */   // GIR_Coverage, 13873,
     /*  333000 */   GIR_EraseRootFromParent_Done,
     /*  333001 */ // Label 4995: @333001
     /*  333001 */ GIM_Try, /*On fail goto*//*Label 4996*/ GIMT_Encode4(333070), // Rule ID 13874 //
     /*  333006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  333009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333012 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  333019 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333032 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  333039 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  333039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
     /*  333042 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  333049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  333054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  333059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  333064 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333068 */   GIR_RootConstrainSelectedInstOperands,
     /*  333069 */   // GIR_Coverage, 13874,
     /*  333069 */   GIR_EraseRootFromParent_Done,
     /*  333070 */ // Label 4996: @333070
     /*  333070 */ GIM_Try, /*On fail goto*//*Label 4997*/ GIMT_Encode4(333139), // Rule ID 13915 //
     /*  333075 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  333078 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333081 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  333108 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  333108 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS),
     /*  333111 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  333118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  333123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  333128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  333133 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333137 */   GIR_RootConstrainSelectedInstOperands,
     /*  333138 */   // GIR_Coverage, 13915,
     /*  333138 */   GIR_EraseRootFromParent_Done,
     /*  333139 */ // Label 4997: @333139
     /*  333139 */ GIM_Try, /*On fail goto*//*Label 4998*/ GIMT_Encode4(333208), // Rule ID 13916 //
     /*  333144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  333147 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333150 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333166 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333170 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  333177 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  333177 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS),
     /*  333180 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  333187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  333192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  333197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  333202 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333206 */   GIR_RootConstrainSelectedInstOperands,
     /*  333207 */   // GIR_Coverage, 13916,
     /*  333207 */   GIR_EraseRootFromParent_Done,
     /*  333208 */ // Label 4998: @333208
     /*  333208 */ GIM_Try, /*On fail goto*//*Label 4999*/ GIMT_Encode4(333277), // Rule ID 13917 //
     /*  333213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  333216 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333219 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333235 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333239 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  333246 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  333246 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS),
     /*  333249 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  333256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  333261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  333266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  333271 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333275 */   GIR_RootConstrainSelectedInstOperands,
     /*  333276 */   // GIR_Coverage, 13917,
     /*  333276 */   GIR_EraseRootFromParent_Done,
     /*  333277 */ // Label 4999: @333277
     /*  333277 */ GIM_Try, /*On fail goto*//*Label 5000*/ GIMT_Encode4(333346), // Rule ID 13918 //
     /*  333282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  333285 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333288 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333304 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333308 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  333315 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  333315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS),
     /*  333318 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  333325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  333330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  333335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  333340 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333344 */   GIR_RootConstrainSelectedInstOperands,
     /*  333345 */   // GIR_Coverage, 13918,
     /*  333345 */   GIR_EraseRootFromParent_Done,
     /*  333346 */ // Label 5000: @333346
     /*  333346 */ GIM_Try, /*On fail goto*//*Label 5001*/ GIMT_Encode4(333415), // Rule ID 13919 //
     /*  333351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  333354 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333357 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333364 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  333384 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  333384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS),
     /*  333387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  333394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  333399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  333404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  333409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333413 */   GIR_RootConstrainSelectedInstOperands,
     /*  333414 */   // GIR_Coverage, 13919,
     /*  333414 */   GIR_EraseRootFromParent_Done,
     /*  333415 */ // Label 5001: @333415
     /*  333415 */ GIM_Try, /*On fail goto*//*Label 5002*/ GIMT_Encode4(333477), // Rule ID 13865 //
     /*  333420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  333423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333426 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  333433 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333453 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  333456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333471 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333475 */   GIR_RootConstrainSelectedInstOperands,
     /*  333476 */   // GIR_Coverage, 13865,
     /*  333476 */   GIR_EraseRootFromParent_Done,
     /*  333477 */ // Label 5002: @333477
     /*  333477 */ GIM_Try, /*On fail goto*//*Label 5003*/ GIMT_Encode4(333539), // Rule ID 13866 //
     /*  333482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  333485 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333488 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  333495 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333515 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  333518 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333537 */   GIR_RootConstrainSelectedInstOperands,
     /*  333538 */   // GIR_Coverage, 13866,
     /*  333538 */   GIR_EraseRootFromParent_Done,
     /*  333539 */ // Label 5003: @333539
     /*  333539 */ GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(333601), // Rule ID 13867 //
     /*  333544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  333547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333550 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  333557 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333562 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333570 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333577 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  333580 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333592 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333595 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333599 */   GIR_RootConstrainSelectedInstOperands,
     /*  333600 */   // GIR_Coverage, 13867,
     /*  333600 */   GIR_EraseRootFromParent_Done,
     /*  333601 */ // Label 5004: @333601
     /*  333601 */ GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(333663), // Rule ID 13868 //
     /*  333606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  333609 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333612 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  333619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333632 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333639 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  333642 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333654 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333661 */   GIR_RootConstrainSelectedInstOperands,
     /*  333662 */   // GIR_Coverage, 13868,
     /*  333662 */   GIR_EraseRootFromParent_Done,
     /*  333663 */ // Label 5005: @333663
     /*  333663 */ GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(333725), // Rule ID 13869 //
     /*  333668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  333671 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333674 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  333681 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333686 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333690 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333694 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333701 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
     /*  333704 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333716 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333719 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333723 */   GIR_RootConstrainSelectedInstOperands,
     /*  333724 */   // GIR_Coverage, 13869,
     /*  333724 */   GIR_EraseRootFromParent_Done,
     /*  333725 */ // Label 5006: @333725
     /*  333725 */ GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(333787), // Rule ID 13910 //
     /*  333730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  333733 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333736 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333752 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333756 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333763 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR),
     /*  333766 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333778 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333781 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333785 */   GIR_RootConstrainSelectedInstOperands,
     /*  333786 */   // GIR_Coverage, 13910,
     /*  333786 */   GIR_EraseRootFromParent_Done,
     /*  333787 */ // Label 5007: @333787
     /*  333787 */ GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(333849), // Rule ID 13911 //
     /*  333792 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  333795 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333798 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333805 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333825 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR),
     /*  333828 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333843 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333847 */   GIR_RootConstrainSelectedInstOperands,
     /*  333848 */   // GIR_Coverage, 13911,
     /*  333848 */   GIR_EraseRootFromParent_Done,
     /*  333849 */ // Label 5008: @333849
     /*  333849 */ GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(333911), // Rule ID 13912 //
     /*  333854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  333857 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333860 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333867 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333887 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR),
     /*  333890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333902 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333905 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333909 */   GIR_RootConstrainSelectedInstOperands,
     /*  333910 */   // GIR_Coverage, 13912,
     /*  333910 */   GIR_EraseRootFromParent_Done,
     /*  333911 */ // Label 5009: @333911
     /*  333911 */ GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(333973), // Rule ID 13913 //
     /*  333916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  333919 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333922 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  333938 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  333942 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  333949 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  333949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR),
     /*  333952 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  333954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  333959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  333964 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  333967 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  333971 */   GIR_RootConstrainSelectedInstOperands,
     /*  333972 */   // GIR_Coverage, 13913,
     /*  333972 */   GIR_EraseRootFromParent_Done,
     /*  333973 */ // Label 5010: @333973
     /*  333973 */ GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(334035), // Rule ID 13914 //
     /*  333978 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  333981 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  333984 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  333991 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  333996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334000 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334004 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  334011 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  334011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR),
     /*  334014 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  334021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334026 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334029 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334033 */   GIR_RootConstrainSelectedInstOperands,
     /*  334034 */   // GIR_Coverage, 13914,
     /*  334034 */   GIR_EraseRootFromParent_Done,
     /*  334035 */ // Label 5011: @334035
     /*  334035 */ GIM_Try, /*On fail goto*//*Label 5012*/ GIMT_Encode4(334097), // Rule ID 13860 //
     /*  334040 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  334043 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334046 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334058 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334062 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334066 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334073 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  334076 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334088 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334091 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334095 */   GIR_RootConstrainSelectedInstOperands,
     /*  334096 */   // GIR_Coverage, 13860,
     /*  334096 */   GIR_EraseRootFromParent_Done,
     /*  334097 */ // Label 5012: @334097
     /*  334097 */ GIM_Try, /*On fail goto*//*Label 5013*/ GIMT_Encode4(334159), // Rule ID 13861 //
     /*  334102 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  334105 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334108 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334115 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334135 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  334138 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334150 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334153 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334157 */   GIR_RootConstrainSelectedInstOperands,
     /*  334158 */   // GIR_Coverage, 13861,
     /*  334158 */   GIR_EraseRootFromParent_Done,
     /*  334159 */ // Label 5013: @334159
     /*  334159 */ GIM_Try, /*On fail goto*//*Label 5014*/ GIMT_Encode4(334221), // Rule ID 13862 //
     /*  334164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  334167 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334170 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334177 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334186 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334190 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334197 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334197 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  334200 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334215 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334219 */   GIR_RootConstrainSelectedInstOperands,
     /*  334220 */   // GIR_Coverage, 13862,
     /*  334220 */   GIR_EraseRootFromParent_Done,
     /*  334221 */ // Label 5014: @334221
     /*  334221 */ GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(334283), // Rule ID 13863 //
     /*  334226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  334229 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334252 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334259 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  334262 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334274 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334277 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334281 */   GIR_RootConstrainSelectedInstOperands,
     /*  334282 */   // GIR_Coverage, 13863,
     /*  334282 */   GIR_EraseRootFromParent_Done,
     /*  334283 */ // Label 5015: @334283
     /*  334283 */ GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(334345), // Rule ID 13864 //
     /*  334288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  334291 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334294 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334301 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334321 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334321 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
     /*  334324 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334339 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334343 */   GIR_RootConstrainSelectedInstOperands,
     /*  334344 */   // GIR_Coverage, 13864,
     /*  334344 */   GIR_EraseRootFromParent_Done,
     /*  334345 */ // Label 5016: @334345
     /*  334345 */ GIM_Try, /*On fail goto*//*Label 5017*/ GIMT_Encode4(334407), // Rule ID 13905 //
     /*  334350 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  334353 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334356 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  334363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334368 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334372 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334376 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334383 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334383 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT),
     /*  334386 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334398 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334401 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334405 */   GIR_RootConstrainSelectedInstOperands,
     /*  334406 */   // GIR_Coverage, 13905,
     /*  334406 */   GIR_EraseRootFromParent_Done,
     /*  334407 */ // Label 5017: @334407
     /*  334407 */ GIM_Try, /*On fail goto*//*Label 5018*/ GIMT_Encode4(334469), // Rule ID 13906 //
     /*  334412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  334415 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334418 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  334425 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334430 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334434 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334438 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334445 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334445 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT),
     /*  334448 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334460 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334463 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334467 */   GIR_RootConstrainSelectedInstOperands,
     /*  334468 */   // GIR_Coverage, 13906,
     /*  334468 */   GIR_EraseRootFromParent_Done,
     /*  334469 */ // Label 5018: @334469
     /*  334469 */ GIM_Try, /*On fail goto*//*Label 5019*/ GIMT_Encode4(334531), // Rule ID 13907 //
     /*  334474 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  334477 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334480 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  334487 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334496 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334500 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334507 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334507 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT),
     /*  334510 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334522 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334525 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334529 */   GIR_RootConstrainSelectedInstOperands,
     /*  334530 */   // GIR_Coverage, 13907,
     /*  334530 */   GIR_EraseRootFromParent_Done,
     /*  334531 */ // Label 5019: @334531
     /*  334531 */ GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(334593), // Rule ID 13908 //
     /*  334536 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  334539 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334542 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  334549 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334554 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334558 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334562 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334569 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT),
     /*  334572 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334584 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334587 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334591 */   GIR_RootConstrainSelectedInstOperands,
     /*  334592 */   // GIR_Coverage, 13908,
     /*  334592 */   GIR_EraseRootFromParent_Done,
     /*  334593 */ // Label 5020: @334593
     /*  334593 */ GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(334655), // Rule ID 13909 //
     /*  334598 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  334601 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334604 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  334611 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  334616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334620 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334624 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  334631 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  334631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT),
     /*  334634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  334636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  334641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  334646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334653 */   GIR_RootConstrainSelectedInstOperands,
     /*  334654 */   // GIR_Coverage, 13909,
     /*  334654 */   GIR_EraseRootFromParent_Done,
     /*  334655 */ // Label 5021: @334655
     /*  334655 */ GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(334732), // Rule ID 15228 //
     /*  334660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  334663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334666 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334673 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  334680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  334695 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  334695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  334698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  334700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  334705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  334710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  334715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  334720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334730 */   GIR_RootConstrainSelectedInstOperands,
     /*  334731 */   // GIR_Coverage, 15228,
     /*  334731 */   GIR_EraseRootFromParent_Done,
     /*  334732 */ // Label 5022: @334732
     /*  334732 */ GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(334809), // Rule ID 15229 //
     /*  334737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  334740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334743 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334750 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  334757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  334772 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  334772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  334775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  334777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  334782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  334787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  334792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  334797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334807 */   GIR_RootConstrainSelectedInstOperands,
     /*  334808 */   // GIR_Coverage, 15229,
     /*  334808 */   GIR_EraseRootFromParent_Done,
     /*  334809 */ // Label 5023: @334809
     /*  334809 */ GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(334886), // Rule ID 15230 //
     /*  334814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  334817 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334820 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334827 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  334834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334842 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  334849 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  334849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  334852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  334854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  334859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  334864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  334869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  334874 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334884 */   GIR_RootConstrainSelectedInstOperands,
     /*  334885 */   // GIR_Coverage, 15230,
     /*  334885 */   GIR_EraseRootFromParent_Done,
     /*  334886 */ // Label 5024: @334886
     /*  334886 */ GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(334963), // Rule ID 15231 //
     /*  334891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  334894 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334897 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  334911 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334915 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334919 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  334926 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  334926 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  334929 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  334931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  334936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  334941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  334946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  334951 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  334957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  334961 */   GIR_RootConstrainSelectedInstOperands,
     /*  334962 */   // GIR_Coverage, 15231,
     /*  334962 */   GIR_EraseRootFromParent_Done,
     /*  334963 */ // Label 5025: @334963
     /*  334963 */ GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(335040), // Rule ID 15232 //
     /*  334968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  334971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  334974 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  334981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  334988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  334992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  334996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335003 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  335006 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335038 */   GIR_RootConstrainSelectedInstOperands,
     /*  335039 */   // GIR_Coverage, 15232,
     /*  335039 */   GIR_EraseRootFromParent_Done,
     /*  335040 */ // Label 5026: @335040
     /*  335040 */ GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(335117), // Rule ID 15238 //
     /*  335045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  335048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  335051 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335058 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335069 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335073 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335080 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335083 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335105 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335111 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335115 */   GIR_RootConstrainSelectedInstOperands,
     /*  335116 */   // GIR_Coverage, 15238,
     /*  335116 */   GIR_EraseRootFromParent_Done,
     /*  335117 */ // Label 5027: @335117
     /*  335117 */ GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(335194), // Rule ID 15239 //
     /*  335122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  335125 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  335128 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335135 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335142 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335146 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335150 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335157 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335182 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335192 */   GIR_RootConstrainSelectedInstOperands,
     /*  335193 */   // GIR_Coverage, 15239,
     /*  335193 */   GIR_EraseRootFromParent_Done,
     /*  335194 */ // Label 5028: @335194
     /*  335194 */ GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(335271), // Rule ID 15240 //
     /*  335199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  335202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  335205 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335212 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335223 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335227 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335234 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335262 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335265 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335269 */   GIR_RootConstrainSelectedInstOperands,
     /*  335270 */   // GIR_Coverage, 15240,
     /*  335270 */   GIR_EraseRootFromParent_Done,
     /*  335271 */ // Label 5029: @335271
     /*  335271 */ GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(335348), // Rule ID 15241 //
     /*  335276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  335279 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  335282 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335311 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335314 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335346 */   GIR_RootConstrainSelectedInstOperands,
     /*  335347 */   // GIR_Coverage, 15241,
     /*  335347 */   GIR_EraseRootFromParent_Done,
     /*  335348 */ // Label 5030: @335348
     /*  335348 */ GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(335425), // Rule ID 15242 //
     /*  335353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  335356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  335359 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335366 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335377 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335388 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335391 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335413 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335416 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335419 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335423 */   GIR_RootConstrainSelectedInstOperands,
     /*  335424 */   // GIR_Coverage, 15242,
     /*  335424 */   GIR_EraseRootFromParent_Done,
     /*  335425 */ // Label 5031: @335425
     /*  335425 */ GIM_Try, /*On fail goto*//*Label 5032*/ GIMT_Encode4(335502), // Rule ID 15248 //
     /*  335430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  335433 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335436 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335454 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335458 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335465 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  335468 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335490 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335496 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335500 */   GIR_RootConstrainSelectedInstOperands,
     /*  335501 */   // GIR_Coverage, 15248,
     /*  335501 */   GIR_EraseRootFromParent_Done,
     /*  335502 */ // Label 5032: @335502
     /*  335502 */ GIM_Try, /*On fail goto*//*Label 5033*/ GIMT_Encode4(335579), // Rule ID 15249 //
     /*  335507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  335510 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335513 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335520 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335535 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335542 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335542 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  335545 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335567 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335570 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335573 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335577 */   GIR_RootConstrainSelectedInstOperands,
     /*  335578 */   // GIR_Coverage, 15249,
     /*  335578 */   GIR_EraseRootFromParent_Done,
     /*  335579 */ // Label 5033: @335579
     /*  335579 */ GIM_Try, /*On fail goto*//*Label 5034*/ GIMT_Encode4(335656), // Rule ID 15250 //
     /*  335584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  335587 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335590 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335597 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335608 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335612 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335619 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335619 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  335622 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335644 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335647 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335650 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335654 */   GIR_RootConstrainSelectedInstOperands,
     /*  335655 */   // GIR_Coverage, 15250,
     /*  335655 */   GIR_EraseRootFromParent_Done,
     /*  335656 */ // Label 5034: @335656
     /*  335656 */ GIM_Try, /*On fail goto*//*Label 5035*/ GIMT_Encode4(335733), // Rule ID 15251 //
     /*  335661 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  335664 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335667 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335674 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335696 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  335699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335731 */   GIR_RootConstrainSelectedInstOperands,
     /*  335732 */   // GIR_Coverage, 15251,
     /*  335732 */   GIR_EraseRootFromParent_Done,
     /*  335733 */ // Label 5035: @335733
     /*  335733 */ GIM_Try, /*On fail goto*//*Label 5036*/ GIMT_Encode4(335810), // Rule ID 15252 //
     /*  335738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  335741 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335744 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335751 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335758 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335762 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335766 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335773 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335773 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  335776 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335804 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335808 */   GIR_RootConstrainSelectedInstOperands,
     /*  335809 */   // GIR_Coverage, 15252,
     /*  335809 */   GIR_EraseRootFromParent_Done,
     /*  335810 */ // Label 5036: @335810
     /*  335810 */ GIM_Try, /*On fail goto*//*Label 5037*/ GIMT_Encode4(335887), // Rule ID 15258 //
     /*  335815 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  335818 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335821 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335828 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335839 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335843 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335850 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335878 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335881 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335885 */   GIR_RootConstrainSelectedInstOperands,
     /*  335886 */   // GIR_Coverage, 15258,
     /*  335886 */   GIR_EraseRootFromParent_Done,
     /*  335887 */ // Label 5037: @335887
     /*  335887 */ GIM_Try, /*On fail goto*//*Label 5038*/ GIMT_Encode4(335964), // Rule ID 15259 //
     /*  335892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  335895 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335898 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335905 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335916 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335920 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  335927 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  335927 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  335930 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  335932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  335937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  335942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  335947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  335952 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335955 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  335958 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  335962 */   GIR_RootConstrainSelectedInstOperands,
     /*  335963 */   // GIR_Coverage, 15259,
     /*  335963 */   GIR_EraseRootFromParent_Done,
     /*  335964 */ // Label 5038: @335964
     /*  335964 */ GIM_Try, /*On fail goto*//*Label 5039*/ GIMT_Encode4(336041), // Rule ID 15260 //
     /*  335969 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  335972 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  335975 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  335982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  335989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  335993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  335997 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336004 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336004 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336007 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336029 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336032 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336035 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336039 */   GIR_RootConstrainSelectedInstOperands,
     /*  336040 */   // GIR_Coverage, 15260,
     /*  336040 */   GIR_EraseRootFromParent_Done,
     /*  336041 */ // Label 5039: @336041
     /*  336041 */ GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(336118), // Rule ID 15261 //
     /*  336046 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  336049 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336052 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  336059 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336081 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336106 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336112 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336116 */   GIR_RootConstrainSelectedInstOperands,
     /*  336117 */   // GIR_Coverage, 15261,
     /*  336117 */   GIR_EraseRootFromParent_Done,
     /*  336118 */ // Label 5040: @336118
     /*  336118 */ GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(336195), // Rule ID 15262 //
     /*  336123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  336126 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336129 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  336136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336147 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336151 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336158 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336161 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336183 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336186 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336189 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336193 */   GIR_RootConstrainSelectedInstOperands,
     /*  336194 */   // GIR_Coverage, 15262,
     /*  336194 */   GIR_EraseRootFromParent_Done,
     /*  336195 */ // Label 5041: @336195
     /*  336195 */ GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(336272), // Rule ID 15268 //
     /*  336200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  336203 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336220 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336224 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336228 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336235 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336235 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  336238 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336260 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336263 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336266 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336270 */   GIR_RootConstrainSelectedInstOperands,
     /*  336271 */   // GIR_Coverage, 15268,
     /*  336271 */   GIR_EraseRootFromParent_Done,
     /*  336272 */ // Label 5042: @336272
     /*  336272 */ GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(336349), // Rule ID 15269 //
     /*  336277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  336280 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336283 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336290 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336297 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336301 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336305 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336312 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336312 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  336315 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336340 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336343 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336347 */   GIR_RootConstrainSelectedInstOperands,
     /*  336348 */   // GIR_Coverage, 15269,
     /*  336348 */   GIR_EraseRootFromParent_Done,
     /*  336349 */ // Label 5043: @336349
     /*  336349 */ GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(336426), // Rule ID 15270 //
     /*  336354 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  336357 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336360 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336367 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336378 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336389 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  336392 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336414 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336417 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336420 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336424 */   GIR_RootConstrainSelectedInstOperands,
     /*  336425 */   // GIR_Coverage, 15270,
     /*  336425 */   GIR_EraseRootFromParent_Done,
     /*  336426 */ // Label 5044: @336426
     /*  336426 */ GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(336503), // Rule ID 15271 //
     /*  336431 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  336434 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336437 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336444 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336466 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  336469 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336501 */   GIR_RootConstrainSelectedInstOperands,
     /*  336502 */   // GIR_Coverage, 15271,
     /*  336502 */   GIR_EraseRootFromParent_Done,
     /*  336503 */ // Label 5045: @336503
     /*  336503 */ GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(336580), // Rule ID 15272 //
     /*  336508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  336511 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336514 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336521 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336543 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  336546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336578 */   GIR_RootConstrainSelectedInstOperands,
     /*  336579 */   // GIR_Coverage, 15272,
     /*  336579 */   GIR_EraseRootFromParent_Done,
     /*  336580 */ // Label 5046: @336580
     /*  336580 */ GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(336657), // Rule ID 15278 //
     /*  336585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  336588 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336591 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336598 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336609 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336613 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336620 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336620 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336623 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336645 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336648 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336651 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336655 */   GIR_RootConstrainSelectedInstOperands,
     /*  336656 */   // GIR_Coverage, 15278,
     /*  336656 */   GIR_EraseRootFromParent_Done,
     /*  336657 */ // Label 5047: @336657
     /*  336657 */ GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(336734), // Rule ID 15279 //
     /*  336662 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  336665 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336668 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336675 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336686 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336697 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336722 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336725 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336728 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336732 */   GIR_RootConstrainSelectedInstOperands,
     /*  336733 */   // GIR_Coverage, 15279,
     /*  336733 */   GIR_EraseRootFromParent_Done,
     /*  336734 */ // Label 5048: @336734
     /*  336734 */ GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(336811), // Rule ID 15280 //
     /*  336739 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  336742 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336745 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336752 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336774 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336799 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336802 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336805 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336809 */   GIR_RootConstrainSelectedInstOperands,
     /*  336810 */   // GIR_Coverage, 15280,
     /*  336810 */   GIR_EraseRootFromParent_Done,
     /*  336811 */ // Label 5049: @336811
     /*  336811 */ GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(336888), // Rule ID 15281 //
     /*  336816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  336819 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336851 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336854 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336886 */   GIR_RootConstrainSelectedInstOperands,
     /*  336887 */   // GIR_Coverage, 15281,
     /*  336887 */   GIR_EraseRootFromParent_Done,
     /*  336888 */ // Label 5050: @336888
     /*  336888 */ GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(336965), // Rule ID 15282 //
     /*  336893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  336896 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  336899 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336906 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  336928 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  336928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
     /*  336931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  336933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  336938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  336943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  336948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  336953 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  336959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  336963 */   GIR_RootConstrainSelectedInstOperands,
     /*  336964 */   // GIR_Coverage, 15282,
     /*  336964 */   GIR_EraseRootFromParent_Done,
     /*  336965 */ // Label 5051: @336965
     /*  336965 */ GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(337042), // Rule ID 15328 //
     /*  336970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  336973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  336976 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  336983 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  336990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  336994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  336998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337005 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337030 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337033 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337036 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337040 */   GIR_RootConstrainSelectedInstOperands,
     /*  337041 */   // GIR_Coverage, 15328,
     /*  337041 */   GIR_EraseRootFromParent_Done,
     /*  337042 */ // Label 5052: @337042
     /*  337042 */ GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(337119), // Rule ID 15329 //
     /*  337047 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  337050 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337053 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337082 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337107 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337110 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337117 */   GIR_RootConstrainSelectedInstOperands,
     /*  337118 */   // GIR_Coverage, 15329,
     /*  337118 */   GIR_EraseRootFromParent_Done,
     /*  337119 */ // Label 5053: @337119
     /*  337119 */ GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(337196), // Rule ID 15330 //
     /*  337124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  337127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337159 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337190 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337194 */   GIR_RootConstrainSelectedInstOperands,
     /*  337195 */   // GIR_Coverage, 15330,
     /*  337195 */   GIR_EraseRootFromParent_Done,
     /*  337196 */ // Label 5054: @337196
     /*  337196 */ GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(337273), // Rule ID 15331 //
     /*  337201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  337204 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337207 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337214 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337236 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337271 */   GIR_RootConstrainSelectedInstOperands,
     /*  337272 */   // GIR_Coverage, 15331,
     /*  337272 */   GIR_EraseRootFromParent_Done,
     /*  337273 */ // Label 5055: @337273
     /*  337273 */ GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(337350), // Rule ID 15332 //
     /*  337278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  337281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337284 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337291 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337313 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337338 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337344 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337348 */   GIR_RootConstrainSelectedInstOperands,
     /*  337349 */   // GIR_Coverage, 15332,
     /*  337349 */   GIR_EraseRootFromParent_Done,
     /*  337350 */ // Label 5056: @337350
     /*  337350 */ GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(337427), // Rule ID 15338 //
     /*  337355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  337358 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337361 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337368 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337375 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337379 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337383 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337390 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337390 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  337393 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337415 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337425 */   GIR_RootConstrainSelectedInstOperands,
     /*  337426 */   // GIR_Coverage, 15338,
     /*  337426 */   GIR_EraseRootFromParent_Done,
     /*  337427 */ // Label 5057: @337427
     /*  337427 */ GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(337504), // Rule ID 15339 //
     /*  337432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  337435 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337438 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337445 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337456 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337460 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337467 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  337470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337495 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337498 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337502 */   GIR_RootConstrainSelectedInstOperands,
     /*  337503 */   // GIR_Coverage, 15339,
     /*  337503 */   GIR_EraseRootFromParent_Done,
     /*  337504 */ // Label 5058: @337504
     /*  337504 */ GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(337581), // Rule ID 15340 //
     /*  337509 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  337512 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337515 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337522 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337537 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337544 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  337547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337572 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337575 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337579 */   GIR_RootConstrainSelectedInstOperands,
     /*  337580 */   // GIR_Coverage, 15340,
     /*  337580 */   GIR_EraseRootFromParent_Done,
     /*  337581 */ // Label 5059: @337581
     /*  337581 */ GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(337658), // Rule ID 15341 //
     /*  337586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  337589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337592 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337599 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337606 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337610 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337614 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337621 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337621 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  337624 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337656 */   GIR_RootConstrainSelectedInstOperands,
     /*  337657 */   // GIR_Coverage, 15341,
     /*  337657 */   GIR_EraseRootFromParent_Done,
     /*  337658 */ // Label 5060: @337658
     /*  337658 */ GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(337735), // Rule ID 15342 //
     /*  337663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  337666 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  337669 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337676 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337687 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337691 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337698 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  337701 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337726 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337729 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337733 */   GIR_RootConstrainSelectedInstOperands,
     /*  337734 */   // GIR_Coverage, 15342,
     /*  337734 */   GIR_EraseRootFromParent_Done,
     /*  337735 */ // Label 5061: @337735
     /*  337735 */ GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(337812), // Rule ID 15348 //
     /*  337740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  337743 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  337746 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337753 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337775 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337803 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337806 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337810 */   GIR_RootConstrainSelectedInstOperands,
     /*  337811 */   // GIR_Coverage, 15348,
     /*  337811 */   GIR_EraseRootFromParent_Done,
     /*  337812 */ // Label 5062: @337812
     /*  337812 */ GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(337889), // Rule ID 15349 //
     /*  337817 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  337820 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  337823 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337830 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337841 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337845 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337852 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337852 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337855 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337880 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337883 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337887 */   GIR_RootConstrainSelectedInstOperands,
     /*  337888 */   // GIR_Coverage, 15349,
     /*  337888 */   GIR_EraseRootFromParent_Done,
     /*  337889 */ // Label 5063: @337889
     /*  337889 */ GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(337966), // Rule ID 15350 //
     /*  337894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  337897 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  337900 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337907 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337918 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337922 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  337929 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  337929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  337932 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  337934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  337939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  337944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  337949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  337954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337957 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  337960 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  337964 */   GIR_RootConstrainSelectedInstOperands,
     /*  337965 */   // GIR_Coverage, 15350,
     /*  337965 */   GIR_EraseRootFromParent_Done,
     /*  337966 */ // Label 5064: @337966
     /*  337966 */ GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(338043), // Rule ID 15351 //
     /*  337971 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  337974 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  337977 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  337984 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  337991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  337995 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  337999 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338006 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338006 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  338009 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338034 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338037 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338041 */   GIR_RootConstrainSelectedInstOperands,
     /*  338042 */   // GIR_Coverage, 15351,
     /*  338042 */   GIR_EraseRootFromParent_Done,
     /*  338043 */ // Label 5065: @338043
     /*  338043 */ GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(338120), // Rule ID 15352 //
     /*  338048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  338051 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  338054 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338061 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338072 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338076 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338083 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338083 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  338086 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338111 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338114 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338118 */   GIR_RootConstrainSelectedInstOperands,
     /*  338119 */   // GIR_Coverage, 15352,
     /*  338119 */   GIR_EraseRootFromParent_Done,
     /*  338120 */ // Label 5066: @338120
     /*  338120 */ GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(338197), // Rule ID 15358 //
     /*  338125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  338128 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  338131 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338138 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338149 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338153 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338160 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  338163 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338191 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338195 */   GIR_RootConstrainSelectedInstOperands,
     /*  338196 */   // GIR_Coverage, 15358,
     /*  338196 */   GIR_EraseRootFromParent_Done,
     /*  338197 */ // Label 5067: @338197
     /*  338197 */ GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(338274), // Rule ID 15359 //
     /*  338202 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  338205 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  338208 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338215 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338230 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338237 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  338240 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338262 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338265 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338268 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338272 */   GIR_RootConstrainSelectedInstOperands,
     /*  338273 */   // GIR_Coverage, 15359,
     /*  338273 */   GIR_EraseRootFromParent_Done,
     /*  338274 */ // Label 5068: @338274
     /*  338274 */ GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(338351), // Rule ID 15360 //
     /*  338279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  338282 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  338285 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338292 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338303 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338307 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338314 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338314 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  338317 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338342 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338349 */   GIR_RootConstrainSelectedInstOperands,
     /*  338350 */   // GIR_Coverage, 15360,
     /*  338350 */   GIR_EraseRootFromParent_Done,
     /*  338351 */ // Label 5069: @338351
     /*  338351 */ GIM_Try, /*On fail goto*//*Label 5070*/ GIMT_Encode4(338428), // Rule ID 15361 //
     /*  338356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  338359 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  338362 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338369 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338376 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338380 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338384 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338391 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  338394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338416 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338426 */   GIR_RootConstrainSelectedInstOperands,
     /*  338427 */   // GIR_Coverage, 15361,
     /*  338427 */   GIR_EraseRootFromParent_Done,
     /*  338428 */ // Label 5070: @338428
     /*  338428 */ GIM_Try, /*On fail goto*//*Label 5071*/ GIMT_Encode4(338505), // Rule ID 15362 //
     /*  338433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  338436 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  338439 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338446 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338453 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338457 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338461 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338468 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  338468 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
     /*  338471 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338493 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338499 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338503 */   GIR_RootConstrainSelectedInstOperands,
     /*  338504 */   // GIR_Coverage, 15362,
     /*  338504 */   GIR_EraseRootFromParent_Done,
     /*  338505 */ // Label 5071: @338505
     /*  338505 */ GIM_Try, /*On fail goto*//*Label 5072*/ GIMT_Encode4(338581), // Rule ID 24851 //
     /*  338510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  338513 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338516 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  338523 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338537 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338544 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  338544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  338547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338572 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338575 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338579 */   GIR_RootConstrainSelectedInstOperands,
     /*  338580 */   // GIR_Coverage, 24851,
     /*  338580 */   GIR_EraseRootFromParent_Done,
     /*  338581 */ // Label 5072: @338581
     /*  338581 */ GIM_Try, /*On fail goto*//*Label 5073*/ GIMT_Encode4(338657), // Rule ID 24852 //
     /*  338586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  338589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338592 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  338599 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338609 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338613 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338620 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  338620 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  338623 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338645 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338648 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338651 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338655 */   GIR_RootConstrainSelectedInstOperands,
     /*  338656 */   // GIR_Coverage, 24852,
     /*  338656 */   GIR_EraseRootFromParent_Done,
     /*  338657 */ // Label 5073: @338657
     /*  338657 */ GIM_Try, /*On fail goto*//*Label 5074*/ GIMT_Encode4(338733), // Rule ID 24853 //
     /*  338662 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  338665 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338668 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  338675 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338696 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  338696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  338699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338731 */   GIR_RootConstrainSelectedInstOperands,
     /*  338732 */   // GIR_Coverage, 24853,
     /*  338732 */   GIR_EraseRootFromParent_Done,
     /*  338733 */ // Label 5074: @338733
     /*  338733 */ GIM_Try, /*On fail goto*//*Label 5075*/ GIMT_Encode4(338809), // Rule ID 24854 //
     /*  338738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  338741 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338744 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  338751 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338772 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  338772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  338775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338807 */   GIR_RootConstrainSelectedInstOperands,
     /*  338808 */   // GIR_Coverage, 24854,
     /*  338808 */   GIR_EraseRootFromParent_Done,
     /*  338809 */ // Label 5075: @338809
     /*  338809 */ GIM_Try, /*On fail goto*//*Label 5076*/ GIMT_Encode4(338885), // Rule ID 24855 //
     /*  338814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  338817 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338820 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  338827 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338837 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338841 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338848 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  338848 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
     /*  338851 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338873 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338879 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338883 */   GIR_RootConstrainSelectedInstOperands,
     /*  338884 */   // GIR_Coverage, 24855,
     /*  338884 */   GIR_EraseRootFromParent_Done,
     /*  338885 */ // Label 5076: @338885
     /*  338885 */ GIM_Try, /*On fail goto*//*Label 5077*/ GIMT_Encode4(338961), // Rule ID 24866 //
     /*  338890 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  338893 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338896 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338903 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338913 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338917 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  338924 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  338924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  338927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  338929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  338934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  338939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  338944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  338949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338952 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  338955 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  338959 */   GIR_RootConstrainSelectedInstOperands,
     /*  338960 */   // GIR_Coverage, 24866,
     /*  338960 */   GIR_EraseRootFromParent_Done,
     /*  338961 */ // Label 5077: @338961
     /*  338961 */ GIM_Try, /*On fail goto*//*Label 5078*/ GIMT_Encode4(339037), // Rule ID 24867 //
     /*  338966 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  338969 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  338972 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  338979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  338985 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  338989 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  338993 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  339000 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  339000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  339003 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339025 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339031 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339035 */   GIR_RootConstrainSelectedInstOperands,
     /*  339036 */   // GIR_Coverage, 24867,
     /*  339036 */   GIR_EraseRootFromParent_Done,
     /*  339037 */ // Label 5078: @339037
     /*  339037 */ GIM_Try, /*On fail goto*//*Label 5079*/ GIMT_Encode4(339113), // Rule ID 24868 //
     /*  339042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  339045 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339048 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  339055 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  339061 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339065 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339069 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  339076 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  339076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  339079 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339101 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339104 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339111 */   GIR_RootConstrainSelectedInstOperands,
     /*  339112 */   // GIR_Coverage, 24868,
     /*  339112 */   GIR_EraseRootFromParent_Done,
     /*  339113 */ // Label 5079: @339113
     /*  339113 */ GIM_Try, /*On fail goto*//*Label 5080*/ GIMT_Encode4(339189), // Rule ID 24869 //
     /*  339118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  339121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339124 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  339131 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  339137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339145 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  339152 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  339152 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  339155 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339177 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339187 */   GIR_RootConstrainSelectedInstOperands,
     /*  339188 */   // GIR_Coverage, 24869,
     /*  339188 */   GIR_EraseRootFromParent_Done,
     /*  339189 */ // Label 5080: @339189
     /*  339189 */ GIM_Try, /*On fail goto*//*Label 5081*/ GIMT_Encode4(339265), // Rule ID 24870 //
     /*  339194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  339197 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339200 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  339207 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  339213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339217 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339221 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  339228 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  339228 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
     /*  339231 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339253 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339259 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339263 */   GIR_RootConstrainSelectedInstOperands,
     /*  339264 */   // GIR_Coverage, 24870,
     /*  339264 */   GIR_EraseRootFromParent_Done,
     /*  339265 */ // Label 5081: @339265
     /*  339265 */ GIM_Try, /*On fail goto*//*Label 5082*/ GIMT_Encode4(339340), // Rule ID 24961 //
     /*  339270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  339273 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339276 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339283 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339288 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339292 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339296 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339303 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  339306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339328 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339331 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339334 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339338 */   GIR_RootConstrainSelectedInstOperands,
     /*  339339 */   // GIR_Coverage, 24961,
     /*  339339 */   GIR_EraseRootFromParent_Done,
     /*  339340 */ // Label 5082: @339340
     /*  339340 */ GIM_Try, /*On fail goto*//*Label 5083*/ GIMT_Encode4(339415), // Rule ID 24962 //
     /*  339345 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  339348 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339351 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339358 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339367 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339378 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  339381 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339413 */   GIR_RootConstrainSelectedInstOperands,
     /*  339414 */   // GIR_Coverage, 24962,
     /*  339414 */   GIR_EraseRootFromParent_Done,
     /*  339415 */ // Label 5083: @339415
     /*  339415 */ GIM_Try, /*On fail goto*//*Label 5084*/ GIMT_Encode4(339490), // Rule ID 24963 //
     /*  339420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  339423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339426 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339433 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339453 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  339456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339478 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339484 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339488 */   GIR_RootConstrainSelectedInstOperands,
     /*  339489 */   // GIR_Coverage, 24963,
     /*  339489 */   GIR_EraseRootFromParent_Done,
     /*  339490 */ // Label 5084: @339490
     /*  339490 */ GIM_Try, /*On fail goto*//*Label 5085*/ GIMT_Encode4(339565), // Rule ID 24964 //
     /*  339495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  339498 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339501 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339508 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339521 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339528 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  339531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339553 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339556 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339559 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339563 */   GIR_RootConstrainSelectedInstOperands,
     /*  339564 */   // GIR_Coverage, 24964,
     /*  339564 */   GIR_EraseRootFromParent_Done,
     /*  339565 */ // Label 5085: @339565
     /*  339565 */ GIM_Try, /*On fail goto*//*Label 5086*/ GIMT_Encode4(339640), // Rule ID 24965 //
     /*  339570 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  339573 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339576 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339583 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339592 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339596 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339603 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
     /*  339606 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339628 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339631 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339634 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339638 */   GIR_RootConstrainSelectedInstOperands,
     /*  339639 */   // GIR_Coverage, 24965,
     /*  339639 */   GIR_EraseRootFromParent_Done,
     /*  339640 */ // Label 5086: @339640
     /*  339640 */ GIM_Try, /*On fail goto*//*Label 5087*/ GIMT_Encode4(339715), // Rule ID 24981 //
     /*  339645 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  339648 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339651 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339658 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339663 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339667 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339671 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339678 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339678 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  339681 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339703 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339706 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339709 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339713 */   GIR_RootConstrainSelectedInstOperands,
     /*  339714 */   // GIR_Coverage, 24981,
     /*  339714 */   GIR_EraseRootFromParent_Done,
     /*  339715 */ // Label 5087: @339715
     /*  339715 */ GIM_Try, /*On fail goto*//*Label 5088*/ GIMT_Encode4(339790), // Rule ID 24982 //
     /*  339720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  339723 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339726 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339733 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339738 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339742 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339746 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339753 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  339756 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339778 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339781 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339784 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339788 */   GIR_RootConstrainSelectedInstOperands,
     /*  339789 */   // GIR_Coverage, 24982,
     /*  339789 */   GIR_EraseRootFromParent_Done,
     /*  339790 */ // Label 5088: @339790
     /*  339790 */ GIM_Try, /*On fail goto*//*Label 5089*/ GIMT_Encode4(339865), // Rule ID 24983 //
     /*  339795 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  339798 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339801 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339808 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339813 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339817 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339821 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339828 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  339831 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339853 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339856 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339859 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339863 */   GIR_RootConstrainSelectedInstOperands,
     /*  339864 */   // GIR_Coverage, 24983,
     /*  339864 */   GIR_EraseRootFromParent_Done,
     /*  339865 */ // Label 5089: @339865
     /*  339865 */ GIM_Try, /*On fail goto*//*Label 5090*/ GIMT_Encode4(339940), // Rule ID 24984 //
     /*  339870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  339873 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339876 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339892 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339896 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339903 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  339906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  339928 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339931 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  339934 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  339938 */   GIR_RootConstrainSelectedInstOperands,
     /*  339939 */   // GIR_Coverage, 24984,
     /*  339939 */   GIR_EraseRootFromParent_Done,
     /*  339940 */ // Label 5090: @339940
     /*  339940 */ GIM_Try, /*On fail goto*//*Label 5091*/ GIMT_Encode4(340015), // Rule ID 24985 //
     /*  339945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  339948 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  339951 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  339958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  339963 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  339967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  339971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  339978 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  339978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
     /*  339981 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  339983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  339988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  339993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  339998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340009 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340013 */   GIR_RootConstrainSelectedInstOperands,
     /*  340014 */   // GIR_Coverage, 24985,
     /*  340014 */   GIR_EraseRootFromParent_Done,
     /*  340015 */ // Label 5091: @340015
     /*  340015 */ GIM_Try, /*On fail goto*//*Label 5092*/ GIMT_Encode4(340090), // Rule ID 25091 //
     /*  340020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  340023 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340026 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340033 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340042 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340046 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340053 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
     /*  340056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340078 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340088 */   GIR_RootConstrainSelectedInstOperands,
     /*  340089 */   // GIR_Coverage, 25091,
     /*  340089 */   GIR_EraseRootFromParent_Done,
     /*  340090 */ // Label 5092: @340090
     /*  340090 */ GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(340165), // Rule ID 25092 //
     /*  340095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  340098 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340101 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340128 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
     /*  340131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340153 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340156 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340159 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340163 */   GIR_RootConstrainSelectedInstOperands,
     /*  340164 */   // GIR_Coverage, 25092,
     /*  340164 */   GIR_EraseRootFromParent_Done,
     /*  340165 */ // Label 5093: @340165
     /*  340165 */ GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(340240), // Rule ID 25093 //
     /*  340170 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  340173 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340176 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340183 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340192 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340196 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340203 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
     /*  340206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340228 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340231 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340234 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340238 */   GIR_RootConstrainSelectedInstOperands,
     /*  340239 */   // GIR_Coverage, 25093,
     /*  340239 */   GIR_EraseRootFromParent_Done,
     /*  340240 */ // Label 5094: @340240
     /*  340240 */ GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(340315), // Rule ID 25094 //
     /*  340245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  340248 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340251 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340258 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340278 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
     /*  340281 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340303 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340306 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340309 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340313 */   GIR_RootConstrainSelectedInstOperands,
     /*  340314 */   // GIR_Coverage, 25094,
     /*  340314 */   GIR_EraseRootFromParent_Done,
     /*  340315 */ // Label 5095: @340315
     /*  340315 */ GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(340390), // Rule ID 25095 //
     /*  340320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  340323 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340326 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340353 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
     /*  340356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340381 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340384 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340388 */   GIR_RootConstrainSelectedInstOperands,
     /*  340389 */   // GIR_Coverage, 25095,
     /*  340389 */   GIR_EraseRootFromParent_Done,
     /*  340390 */ // Label 5096: @340390
     /*  340390 */ GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(340465), // Rule ID 25101 //
     /*  340395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  340398 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340401 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340408 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340413 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340428 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
     /*  340431 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340453 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340456 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340459 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340463 */   GIR_RootConstrainSelectedInstOperands,
     /*  340464 */   // GIR_Coverage, 25101,
     /*  340464 */   GIR_EraseRootFromParent_Done,
     /*  340465 */ // Label 5097: @340465
     /*  340465 */ GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(340540), // Rule ID 25102 //
     /*  340470 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  340473 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340476 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340483 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340492 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340496 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340503 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
     /*  340506 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340531 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340534 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340538 */   GIR_RootConstrainSelectedInstOperands,
     /*  340539 */   // GIR_Coverage, 25102,
     /*  340539 */   GIR_EraseRootFromParent_Done,
     /*  340540 */ // Label 5098: @340540
     /*  340540 */ GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(340615), // Rule ID 25103 //
     /*  340545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  340548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340551 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340558 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340578 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
     /*  340581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340613 */   GIR_RootConstrainSelectedInstOperands,
     /*  340614 */   // GIR_Coverage, 25103,
     /*  340614 */   GIR_EraseRootFromParent_Done,
     /*  340615 */ // Label 5099: @340615
     /*  340615 */ GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(340690), // Rule ID 25104 //
     /*  340620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  340623 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340633 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340653 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
     /*  340656 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340678 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340688 */   GIR_RootConstrainSelectedInstOperands,
     /*  340689 */   // GIR_Coverage, 25104,
     /*  340689 */   GIR_EraseRootFromParent_Done,
     /*  340690 */ // Label 5100: @340690
     /*  340690 */ GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(340765), // Rule ID 25105 //
     /*  340695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  340698 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340701 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  340708 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  340713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340717 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340721 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  340728 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  340728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
     /*  340731 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  340738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  340748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  340753 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340756 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340759 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340763 */   GIR_RootConstrainSelectedInstOperands,
     /*  340764 */   // GIR_Coverage, 25105,
     /*  340764 */   GIR_EraseRootFromParent_Done,
     /*  340765 */ // Label 5101: @340765
     /*  340765 */ GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(340837), // Rule ID 15223 //
     /*  340770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  340773 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340776 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  340783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  340790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340794 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340798 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  340805 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  340805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  340808 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  340820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  340825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340828 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340831 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340835 */   GIR_RootConstrainSelectedInstOperands,
     /*  340836 */   // GIR_Coverage, 15223,
     /*  340836 */   GIR_EraseRootFromParent_Done,
     /*  340837 */ // Label 5102: @340837
     /*  340837 */ GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(340909), // Rule ID 15224 //
     /*  340842 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  340845 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340848 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  340855 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  340862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340866 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340870 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  340877 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  340877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  340880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  340892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  340897 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340900 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340907 */   GIR_RootConstrainSelectedInstOperands,
     /*  340908 */   // GIR_Coverage, 15224,
     /*  340908 */   GIR_EraseRootFromParent_Done,
     /*  340909 */ // Label 5103: @340909
     /*  340909 */ GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(340981), // Rule ID 15225 //
     /*  340914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  340917 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340920 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  340927 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  340934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  340938 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  340942 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  340949 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  340949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  340952 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  340954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  340959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  340964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  340969 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340972 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  340975 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  340979 */   GIR_RootConstrainSelectedInstOperands,
     /*  340980 */   // GIR_Coverage, 15225,
     /*  340980 */   GIR_EraseRootFromParent_Done,
     /*  340981 */ // Label 5104: @340981
     /*  340981 */ GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(341053), // Rule ID 15226 //
     /*  340986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  340989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  340992 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  340999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341021 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341047 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341051 */   GIR_RootConstrainSelectedInstOperands,
     /*  341052 */   // GIR_Coverage, 15226,
     /*  341052 */   GIR_EraseRootFromParent_Done,
     /*  341053 */ // Label 5105: @341053
     /*  341053 */ GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(341125), // Rule ID 15227 //
     /*  341058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  341061 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  341064 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341071 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341082 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341093 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341113 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341123 */   GIR_RootConstrainSelectedInstOperands,
     /*  341124 */   // GIR_Coverage, 15227,
     /*  341124 */   GIR_EraseRootFromParent_Done,
     /*  341125 */ // Label 5106: @341125
     /*  341125 */ GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(341197), // Rule ID 15233 //
     /*  341130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  341133 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  341136 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341143 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341150 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341158 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341165 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341165 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341168 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341191 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341195 */   GIR_RootConstrainSelectedInstOperands,
     /*  341196 */   // GIR_Coverage, 15233,
     /*  341196 */   GIR_EraseRootFromParent_Done,
     /*  341197 */ // Label 5107: @341197
     /*  341197 */ GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(341269), // Rule ID 15234 //
     /*  341202 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  341205 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  341208 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341215 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341230 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341237 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341240 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341257 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341260 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341263 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341267 */   GIR_RootConstrainSelectedInstOperands,
     /*  341268 */   // GIR_Coverage, 15234,
     /*  341268 */   GIR_EraseRootFromParent_Done,
     /*  341269 */ // Label 5108: @341269
     /*  341269 */ GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(341341), // Rule ID 15235 //
     /*  341274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  341277 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  341280 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341287 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341294 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341298 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341302 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341309 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341329 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341332 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341335 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341339 */   GIR_RootConstrainSelectedInstOperands,
     /*  341340 */   // GIR_Coverage, 15235,
     /*  341340 */   GIR_EraseRootFromParent_Done,
     /*  341341 */ // Label 5109: @341341
     /*  341341 */ GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(341413), // Rule ID 15236 //
     /*  341346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  341349 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  341352 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341370 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341374 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341381 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341384 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341401 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341404 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341411 */   GIR_RootConstrainSelectedInstOperands,
     /*  341412 */   // GIR_Coverage, 15236,
     /*  341412 */   GIR_EraseRootFromParent_Done,
     /*  341413 */ // Label 5110: @341413
     /*  341413 */ GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(341485), // Rule ID 15237 //
     /*  341418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  341421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  341424 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341431 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341453 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341473 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341476 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341479 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341483 */   GIR_RootConstrainSelectedInstOperands,
     /*  341484 */   // GIR_Coverage, 15237,
     /*  341484 */   GIR_EraseRootFromParent_Done,
     /*  341485 */ // Label 5111: @341485
     /*  341485 */ GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(341557), // Rule ID 15243 //
     /*  341490 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  341493 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341525 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341528 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341545 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341548 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341551 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341555 */   GIR_RootConstrainSelectedInstOperands,
     /*  341556 */   // GIR_Coverage, 15243,
     /*  341556 */   GIR_EraseRootFromParent_Done,
     /*  341557 */ // Label 5112: @341557
     /*  341557 */ GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(341629), // Rule ID 15244 //
     /*  341562 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  341565 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341568 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341575 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341597 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341617 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341620 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341623 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341627 */   GIR_RootConstrainSelectedInstOperands,
     /*  341628 */   // GIR_Coverage, 15244,
     /*  341628 */   GIR_EraseRootFromParent_Done,
     /*  341629 */ // Label 5113: @341629
     /*  341629 */ GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(341701), // Rule ID 15245 //
     /*  341634 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  341637 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341640 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341647 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341658 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341662 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341669 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341669 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341672 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341689 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341692 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341695 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341699 */   GIR_RootConstrainSelectedInstOperands,
     /*  341700 */   // GIR_Coverage, 15245,
     /*  341700 */   GIR_EraseRootFromParent_Done,
     /*  341701 */ // Label 5114: @341701
     /*  341701 */ GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(341773), // Rule ID 15246 //
     /*  341706 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  341709 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341712 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341719 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341726 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341730 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341734 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341741 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341744 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341761 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341767 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341771 */   GIR_RootConstrainSelectedInstOperands,
     /*  341772 */   // GIR_Coverage, 15246,
     /*  341772 */   GIR_EraseRootFromParent_Done,
     /*  341773 */ // Label 5115: @341773
     /*  341773 */ GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(341845), // Rule ID 15247 //
     /*  341778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  341781 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341784 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341791 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341798 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341802 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341806 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341813 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341813 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  341816 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341843 */   GIR_RootConstrainSelectedInstOperands,
     /*  341844 */   // GIR_Coverage, 15247,
     /*  341844 */   GIR_EraseRootFromParent_Done,
     /*  341845 */ // Label 5116: @341845
     /*  341845 */ GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(341917), // Rule ID 15253 //
     /*  341850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  341853 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341856 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341885 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341888 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341905 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341908 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341911 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341915 */   GIR_RootConstrainSelectedInstOperands,
     /*  341916 */   // GIR_Coverage, 15253,
     /*  341916 */   GIR_EraseRootFromParent_Done,
     /*  341917 */ // Label 5117: @341917
     /*  341917 */ GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(341989), // Rule ID 15254 //
     /*  341922 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  341925 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  341928 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  341935 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  341942 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  341946 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  341950 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  341957 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  341957 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  341960 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  341962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  341967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  341972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  341977 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341980 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  341983 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  341987 */   GIR_RootConstrainSelectedInstOperands,
     /*  341988 */   // GIR_Coverage, 15254,
     /*  341988 */   GIR_EraseRootFromParent_Done,
     /*  341989 */ // Label 5118: @341989
     /*  341989 */ GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(342061), // Rule ID 15255 //
     /*  341994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  341997 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342000 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  342007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342018 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342022 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342029 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342032 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342049 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342052 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342055 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342059 */   GIR_RootConstrainSelectedInstOperands,
     /*  342060 */   // GIR_Coverage, 15255,
     /*  342060 */   GIR_EraseRootFromParent_Done,
     /*  342061 */ // Label 5119: @342061
     /*  342061 */ GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(342133), // Rule ID 15256 //
     /*  342066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  342069 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342072 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  342079 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342101 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342121 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342124 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342127 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342131 */   GIR_RootConstrainSelectedInstOperands,
     /*  342132 */   // GIR_Coverage, 15256,
     /*  342132 */   GIR_EraseRootFromParent_Done,
     /*  342133 */ // Label 5120: @342133
     /*  342133 */ GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(342205), // Rule ID 15257 //
     /*  342138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  342141 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342144 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  342151 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342158 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342166 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342173 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342176 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342196 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342199 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342203 */   GIR_RootConstrainSelectedInstOperands,
     /*  342204 */   // GIR_Coverage, 15257,
     /*  342204 */   GIR_EraseRootFromParent_Done,
     /*  342205 */ // Label 5121: @342205
     /*  342205 */ GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(342277), // Rule ID 15263 //
     /*  342210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  342213 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342216 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342223 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342230 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342234 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342238 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342245 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  342248 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342265 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342268 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342271 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342275 */   GIR_RootConstrainSelectedInstOperands,
     /*  342276 */   // GIR_Coverage, 15263,
     /*  342276 */   GIR_EraseRootFromParent_Done,
     /*  342277 */ // Label 5122: @342277
     /*  342277 */ GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(342349), // Rule ID 15264 //
     /*  342282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  342285 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342288 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342306 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342310 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342317 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  342320 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342340 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342343 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342347 */   GIR_RootConstrainSelectedInstOperands,
     /*  342348 */   // GIR_Coverage, 15264,
     /*  342348 */   GIR_EraseRootFromParent_Done,
     /*  342349 */ // Label 5123: @342349
     /*  342349 */ GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(342421), // Rule ID 15265 //
     /*  342354 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  342357 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342360 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342367 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342378 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342389 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  342392 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342409 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342412 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342415 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342419 */   GIR_RootConstrainSelectedInstOperands,
     /*  342420 */   // GIR_Coverage, 15265,
     /*  342420 */   GIR_EraseRootFromParent_Done,
     /*  342421 */ // Label 5124: @342421
     /*  342421 */ GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(342493), // Rule ID 15266 //
     /*  342426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  342429 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342432 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342439 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342450 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342454 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342461 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  342464 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342487 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342491 */   GIR_RootConstrainSelectedInstOperands,
     /*  342492 */   // GIR_Coverage, 15266,
     /*  342492 */   GIR_EraseRootFromParent_Done,
     /*  342493 */ // Label 5125: @342493
     /*  342493 */ GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(342565), // Rule ID 15267 //
     /*  342498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  342501 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342504 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342511 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342522 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342526 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342533 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342533 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
     /*  342536 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342553 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342556 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342559 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342563 */   GIR_RootConstrainSelectedInstOperands,
     /*  342564 */   // GIR_Coverage, 15267,
     /*  342564 */   GIR_EraseRootFromParent_Done,
     /*  342565 */ // Label 5126: @342565
     /*  342565 */ GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(342637), // Rule ID 15273 //
     /*  342570 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  342573 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342576 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342583 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342590 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342594 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342598 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342605 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342605 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342608 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342615 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342625 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342628 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342631 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342635 */   GIR_RootConstrainSelectedInstOperands,
     /*  342636 */   // GIR_Coverage, 15273,
     /*  342636 */   GIR_EraseRootFromParent_Done,
     /*  342637 */ // Label 5127: @342637
     /*  342637 */ GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(342709), // Rule ID 15274 //
     /*  342642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  342645 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342648 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342655 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342666 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342670 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342677 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342677 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342680 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342697 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342700 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342703 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342707 */   GIR_RootConstrainSelectedInstOperands,
     /*  342708 */   // GIR_Coverage, 15274,
     /*  342708 */   GIR_EraseRootFromParent_Done,
     /*  342709 */ // Label 5128: @342709
     /*  342709 */ GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(342781), // Rule ID 15275 //
     /*  342714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  342717 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342720 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342727 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342734 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342738 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342742 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342749 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342752 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342769 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342772 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342775 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342779 */   GIR_RootConstrainSelectedInstOperands,
     /*  342780 */   // GIR_Coverage, 15275,
     /*  342780 */   GIR_EraseRootFromParent_Done,
     /*  342781 */ // Label 5129: @342781
     /*  342781 */ GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(342853), // Rule ID 15276 //
     /*  342786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  342789 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342792 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342821 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342824 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342841 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342844 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342851 */   GIR_RootConstrainSelectedInstOperands,
     /*  342852 */   // GIR_Coverage, 15276,
     /*  342852 */   GIR_EraseRootFromParent_Done,
     /*  342853 */ // Label 5130: @342853
     /*  342853 */ GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(342925), // Rule ID 15277 //
     /*  342858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  342861 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  342864 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342878 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342882 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342886 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342893 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342893 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
     /*  342896 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342913 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342919 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342923 */   GIR_RootConstrainSelectedInstOperands,
     /*  342924 */   // GIR_Coverage, 15277,
     /*  342924 */   GIR_EraseRootFromParent_Done,
     /*  342925 */ // Label 5131: @342925
     /*  342925 */ GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(342997), // Rule ID 15323 //
     /*  342930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  342933 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  342936 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  342943 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  342950 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  342954 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  342958 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  342965 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  342965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  342968 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  342970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  342975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  342980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  342985 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342988 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  342991 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  342995 */   GIR_RootConstrainSelectedInstOperands,
     /*  342996 */   // GIR_Coverage, 15323,
     /*  342996 */   GIR_EraseRootFromParent_Done,
     /*  342997 */ // Label 5132: @342997
     /*  342997 */ GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(343069), // Rule ID 15324 //
     /*  343002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  343005 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343008 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343022 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343026 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343030 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343037 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343037 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343040 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343057 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343063 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343067 */   GIR_RootConstrainSelectedInstOperands,
     /*  343068 */   // GIR_Coverage, 15324,
     /*  343068 */   GIR_EraseRootFromParent_Done,
     /*  343069 */ // Label 5133: @343069
     /*  343069 */ GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(343141), // Rule ID 15325 //
     /*  343074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  343077 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343080 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343098 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343102 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343109 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343109 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343112 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343132 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343135 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343139 */   GIR_RootConstrainSelectedInstOperands,
     /*  343140 */   // GIR_Coverage, 15325,
     /*  343140 */   GIR_EraseRootFromParent_Done,
     /*  343141 */ // Label 5134: @343141
     /*  343141 */ GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(343213), // Rule ID 15326 //
     /*  343146 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  343149 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343152 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343159 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343170 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343174 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343181 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343201 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343204 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343207 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343211 */   GIR_RootConstrainSelectedInstOperands,
     /*  343212 */   // GIR_Coverage, 15326,
     /*  343212 */   GIR_EraseRootFromParent_Done,
     /*  343213 */ // Label 5135: @343213
     /*  343213 */ GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(343285), // Rule ID 15327 //
     /*  343218 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  343221 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343224 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343231 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343242 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343246 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343253 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343253 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343256 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343273 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343283 */   GIR_RootConstrainSelectedInstOperands,
     /*  343284 */   // GIR_Coverage, 15327,
     /*  343284 */   GIR_EraseRootFromParent_Done,
     /*  343285 */ // Label 5136: @343285
     /*  343285 */ GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(343357), // Rule ID 15333 //
     /*  343290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  343293 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343314 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343318 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343325 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343325 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  343328 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343345 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343348 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343355 */   GIR_RootConstrainSelectedInstOperands,
     /*  343356 */   // GIR_Coverage, 15333,
     /*  343356 */   GIR_EraseRootFromParent_Done,
     /*  343357 */ // Label 5137: @343357
     /*  343357 */ GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(343429), // Rule ID 15334 //
     /*  343362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  343365 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343382 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343386 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343390 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343397 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343397 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  343400 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343417 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343420 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343423 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343427 */   GIR_RootConstrainSelectedInstOperands,
     /*  343428 */   // GIR_Coverage, 15334,
     /*  343428 */   GIR_EraseRootFromParent_Done,
     /*  343429 */ // Label 5138: @343429
     /*  343429 */ GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(343501), // Rule ID 15335 //
     /*  343434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  343437 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343440 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343469 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  343472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343489 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343495 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343499 */   GIR_RootConstrainSelectedInstOperands,
     /*  343500 */   // GIR_Coverage, 15335,
     /*  343500 */   GIR_EraseRootFromParent_Done,
     /*  343501 */ // Label 5139: @343501
     /*  343501 */ GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(343573), // Rule ID 15336 //
     /*  343506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  343509 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343512 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343530 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343541 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  343544 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343561 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343564 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343571 */   GIR_RootConstrainSelectedInstOperands,
     /*  343572 */   // GIR_Coverage, 15336,
     /*  343572 */   GIR_EraseRootFromParent_Done,
     /*  343573 */ // Label 5140: @343573
     /*  343573 */ GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(343645), // Rule ID 15337 //
     /*  343578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  343581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  343584 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343613 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  343616 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343633 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343636 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343639 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343643 */   GIR_RootConstrainSelectedInstOperands,
     /*  343644 */   // GIR_Coverage, 15337,
     /*  343644 */   GIR_EraseRootFromParent_Done,
     /*  343645 */ // Label 5141: @343645
     /*  343645 */ GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(343717), // Rule ID 15343 //
     /*  343650 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  343653 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  343656 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343663 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343670 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343674 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343678 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343685 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343705 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343711 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343715 */   GIR_RootConstrainSelectedInstOperands,
     /*  343716 */   // GIR_Coverage, 15343,
     /*  343716 */   GIR_EraseRootFromParent_Done,
     /*  343717 */ // Label 5142: @343717
     /*  343717 */ GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(343789), // Rule ID 15344 //
     /*  343722 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  343725 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  343728 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343746 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343750 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343757 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343757 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343760 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343777 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343783 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343787 */   GIR_RootConstrainSelectedInstOperands,
     /*  343788 */   // GIR_Coverage, 15344,
     /*  343788 */   GIR_EraseRootFromParent_Done,
     /*  343789 */ // Label 5143: @343789
     /*  343789 */ GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(343861), // Rule ID 15345 //
     /*  343794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  343797 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  343800 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343818 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343822 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343829 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343859 */   GIR_RootConstrainSelectedInstOperands,
     /*  343860 */   // GIR_Coverage, 15345,
     /*  343860 */   GIR_EraseRootFromParent_Done,
     /*  343861 */ // Label 5144: @343861
     /*  343861 */ GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(343933), // Rule ID 15346 //
     /*  343866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  343869 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  343872 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343879 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343890 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343894 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343901 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343904 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343921 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343927 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  343931 */   GIR_RootConstrainSelectedInstOperands,
     /*  343932 */   // GIR_Coverage, 15346,
     /*  343932 */   GIR_EraseRootFromParent_Done,
     /*  343933 */ // Label 5145: @343933
     /*  343933 */ GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(344005), // Rule ID 15347 //
     /*  343938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  343941 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  343944 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  343951 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  343958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  343962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  343966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  343973 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  343973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
     /*  343976 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  343978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  343983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  343988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  343993 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343996 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  343999 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344003 */   GIR_RootConstrainSelectedInstOperands,
     /*  344004 */   // GIR_Coverage, 15347,
     /*  344004 */   GIR_EraseRootFromParent_Done,
     /*  344005 */ // Label 5146: @344005
     /*  344005 */ GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(344077), // Rule ID 15353 //
     /*  344010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  344013 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  344016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  344023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  344030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  344045 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  344045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  344048 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  344050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  344055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  344060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  344065 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344068 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344071 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344075 */   GIR_RootConstrainSelectedInstOperands,
     /*  344076 */   // GIR_Coverage, 15353,
     /*  344076 */   GIR_EraseRootFromParent_Done,
     /*  344077 */ // Label 5147: @344077
     /*  344077 */ GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(344149), // Rule ID 15354 //
     /*  344082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  344085 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  344088 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  344095 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  344102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344106 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344110 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  344117 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  344117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  344120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  344122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  344127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  344132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  344137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344143 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344147 */   GIR_RootConstrainSelectedInstOperands,
     /*  344148 */   // GIR_Coverage, 15354,
     /*  344148 */   GIR_EraseRootFromParent_Done,
     /*  344149 */ // Label 5148: @344149
     /*  344149 */ GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(344221), // Rule ID 15355 //
     /*  344154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  344157 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  344160 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  344167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  344174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344178 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344182 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  344189 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  344189 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  344192 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  344194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  344199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  344204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  344209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344215 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344219 */   GIR_RootConstrainSelectedInstOperands,
     /*  344220 */   // GIR_Coverage, 15355,
     /*  344220 */   GIR_EraseRootFromParent_Done,
     /*  344221 */ // Label 5149: @344221
     /*  344221 */ GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(344293), // Rule ID 15356 //
     /*  344226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  344229 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  344232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  344239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  344246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  344261 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  344261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  344264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  344266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  344271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  344276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  344281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344287 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344291 */   GIR_RootConstrainSelectedInstOperands,
     /*  344292 */   // GIR_Coverage, 15356,
     /*  344292 */   GIR_EraseRootFromParent_Done,
     /*  344293 */ // Label 5150: @344293
     /*  344293 */ GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(344365), // Rule ID 15357 //
     /*  344298 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  344301 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  344304 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  344311 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  344318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  344333 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  344333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
     /*  344336 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  344338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  344343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  344348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  344353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344359 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344363 */   GIR_RootConstrainSelectedInstOperands,
     /*  344364 */   // GIR_Coverage, 15357,
     /*  344364 */   GIR_EraseRootFromParent_Done,
     /*  344365 */ // Label 5151: @344365
     /*  344365 */ GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(344427), // Rule ID 28773 //
     /*  344370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  344373 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344403 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  344406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344425 */   GIR_RootConstrainSelectedInstOperands,
     /*  344426 */   // GIR_Coverage, 28773,
     /*  344426 */   GIR_EraseRootFromParent_Done,
     /*  344427 */ // Label 5152: @344427
     /*  344427 */ GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(344489), // Rule ID 28774 //
     /*  344432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  344435 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344438 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344445 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344454 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344458 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344465 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  344468 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344483 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344487 */   GIR_RootConstrainSelectedInstOperands,
     /*  344488 */   // GIR_Coverage, 28774,
     /*  344488 */   GIR_EraseRootFromParent_Done,
     /*  344489 */ // Label 5153: @344489
     /*  344489 */ GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(344551), // Rule ID 28775 //
     /*  344494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  344497 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344500 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344516 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344520 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344527 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344527 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  344530 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344542 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344549 */   GIR_RootConstrainSelectedInstOperands,
     /*  344550 */   // GIR_Coverage, 28775,
     /*  344550 */   GIR_EraseRootFromParent_Done,
     /*  344551 */ // Label 5154: @344551
     /*  344551 */ GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(344613), // Rule ID 28776 //
     /*  344556 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  344559 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344562 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344578 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344589 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  344592 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344604 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344607 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344611 */   GIR_RootConstrainSelectedInstOperands,
     /*  344612 */   // GIR_Coverage, 28776,
     /*  344612 */   GIR_EraseRootFromParent_Done,
     /*  344613 */ // Label 5155: @344613
     /*  344613 */ GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(344675), // Rule ID 28777 //
     /*  344618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  344621 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344624 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344631 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344640 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344644 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344651 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344651 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  344654 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344666 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344669 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344673 */   GIR_RootConstrainSelectedInstOperands,
     /*  344674 */   // GIR_Coverage, 28777,
     /*  344674 */   GIR_EraseRootFromParent_Done,
     /*  344675 */ // Label 5156: @344675
     /*  344675 */ GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(344737), // Rule ID 28778 //
     /*  344680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  344683 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344713 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  344716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344728 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344731 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344735 */   GIR_RootConstrainSelectedInstOperands,
     /*  344736 */   // GIR_Coverage, 28778,
     /*  344736 */   GIR_EraseRootFromParent_Done,
     /*  344737 */ // Label 5157: @344737
     /*  344737 */ GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(344799), // Rule ID 28779 //
     /*  344742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  344745 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344748 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344755 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344775 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  344778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344790 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344797 */   GIR_RootConstrainSelectedInstOperands,
     /*  344798 */   // GIR_Coverage, 28779,
     /*  344798 */   GIR_EraseRootFromParent_Done,
     /*  344799 */ // Label 5158: @344799
     /*  344799 */ GIM_Try, /*On fail goto*//*Label 5159*/ GIMT_Encode4(344861), // Rule ID 28780 //
     /*  344804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  344807 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344810 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344817 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344826 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344830 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344837 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  344840 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344859 */   GIR_RootConstrainSelectedInstOperands,
     /*  344860 */   // GIR_Coverage, 28780,
     /*  344860 */   GIR_EraseRootFromParent_Done,
     /*  344861 */ // Label 5159: @344861
     /*  344861 */ GIM_Try, /*On fail goto*//*Label 5160*/ GIMT_Encode4(344923), // Rule ID 28781 //
     /*  344866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  344869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344872 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344879 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344884 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344888 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344892 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344899 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344899 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  344902 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344917 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344921 */   GIR_RootConstrainSelectedInstOperands,
     /*  344922 */   // GIR_Coverage, 28781,
     /*  344922 */   GIR_EraseRootFromParent_Done,
     /*  344923 */ // Label 5160: @344923
     /*  344923 */ GIM_Try, /*On fail goto*//*Label 5161*/ GIMT_Encode4(344985), // Rule ID 28782 //
     /*  344928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  344931 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344934 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  344941 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  344946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  344950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  344954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  344961 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  344961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  344964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  344966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  344971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  344976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  344979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  344983 */   GIR_RootConstrainSelectedInstOperands,
     /*  344984 */   // GIR_Coverage, 28782,
     /*  344984 */   GIR_EraseRootFromParent_Done,
     /*  344985 */ // Label 5161: @344985
     /*  344985 */ GIM_Try, /*On fail goto*//*Label 5162*/ GIMT_Encode4(345047), // Rule ID 28819 //
     /*  344990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  344993 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  344996 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345023 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  345026 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345038 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345041 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345045 */   GIR_RootConstrainSelectedInstOperands,
     /*  345046 */   // GIR_Coverage, 28819,
     /*  345046 */   GIR_EraseRootFromParent_Done,
     /*  345047 */ // Label 5162: @345047
     /*  345047 */ GIM_Try, /*On fail goto*//*Label 5163*/ GIMT_Encode4(345109), // Rule ID 28820 //
     /*  345052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  345055 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345058 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345085 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  345088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345100 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345107 */   GIR_RootConstrainSelectedInstOperands,
     /*  345108 */   // GIR_Coverage, 28820,
     /*  345108 */   GIR_EraseRootFromParent_Done,
     /*  345109 */ // Label 5163: @345109
     /*  345109 */ GIM_Try, /*On fail goto*//*Label 5164*/ GIMT_Encode4(345171), // Rule ID 28821 //
     /*  345114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  345117 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345120 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345147 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  345150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345169 */   GIR_RootConstrainSelectedInstOperands,
     /*  345170 */   // GIR_Coverage, 28821,
     /*  345170 */   GIR_EraseRootFromParent_Done,
     /*  345171 */ // Label 5164: @345171
     /*  345171 */ GIM_Try, /*On fail goto*//*Label 5165*/ GIMT_Encode4(345233), // Rule ID 28822 //
     /*  345176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  345179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345182 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345189 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345209 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  345212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345224 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345227 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345231 */   GIR_RootConstrainSelectedInstOperands,
     /*  345232 */   // GIR_Coverage, 28822,
     /*  345232 */   GIR_EraseRootFromParent_Done,
     /*  345233 */ // Label 5165: @345233
     /*  345233 */ GIM_Try, /*On fail goto*//*Label 5166*/ GIMT_Encode4(345295), // Rule ID 28823 //
     /*  345238 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  345241 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345244 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345271 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  345274 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345293 */   GIR_RootConstrainSelectedInstOperands,
     /*  345294 */   // GIR_Coverage, 28823,
     /*  345294 */   GIR_EraseRootFromParent_Done,
     /*  345295 */ // Label 5166: @345295
     /*  345295 */ GIM_Try, /*On fail goto*//*Label 5167*/ GIMT_Encode4(345357), // Rule ID 28824 //
     /*  345300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  345303 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345333 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  345336 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345348 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345355 */   GIR_RootConstrainSelectedInstOperands,
     /*  345356 */   // GIR_Coverage, 28824,
     /*  345356 */   GIR_EraseRootFromParent_Done,
     /*  345357 */ // Label 5167: @345357
     /*  345357 */ GIM_Try, /*On fail goto*//*Label 5168*/ GIMT_Encode4(345419), // Rule ID 28825 //
     /*  345362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  345365 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345384 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345388 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345395 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345395 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  345398 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345410 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345413 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345417 */   GIR_RootConstrainSelectedInstOperands,
     /*  345418 */   // GIR_Coverage, 28825,
     /*  345418 */   GIR_EraseRootFromParent_Done,
     /*  345419 */ // Label 5168: @345419
     /*  345419 */ GIM_Try, /*On fail goto*//*Label 5169*/ GIMT_Encode4(345481), // Rule ID 28826 //
     /*  345424 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  345427 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345430 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345457 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  345460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345472 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345479 */   GIR_RootConstrainSelectedInstOperands,
     /*  345480 */   // GIR_Coverage, 28826,
     /*  345480 */   GIR_EraseRootFromParent_Done,
     /*  345481 */ // Label 5169: @345481
     /*  345481 */ GIM_Try, /*On fail goto*//*Label 5170*/ GIMT_Encode4(345543), // Rule ID 28827 //
     /*  345486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  345489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345519 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  345522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345534 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345541 */   GIR_RootConstrainSelectedInstOperands,
     /*  345542 */   // GIR_Coverage, 28827,
     /*  345542 */   GIR_EraseRootFromParent_Done,
     /*  345543 */ // Label 5170: @345543
     /*  345543 */ GIM_Try, /*On fail goto*//*Label 5171*/ GIMT_Encode4(345605), // Rule ID 28828 //
     /*  345548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  345551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  345554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  345561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345570 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345581 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  345584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345603 */   GIR_RootConstrainSelectedInstOperands,
     /*  345604 */   // GIR_Coverage, 28828,
     /*  345604 */   GIR_EraseRootFromParent_Done,
     /*  345605 */ // Label 5171: @345605
     /*  345605 */ GIM_Try, /*On fail goto*//*Label 5172*/ GIMT_Encode4(345667), // Rule ID 29045 //
     /*  345610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  345613 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345616 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345623 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345643 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  345646 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345658 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345661 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345665 */   GIR_RootConstrainSelectedInstOperands,
     /*  345666 */   // GIR_Coverage, 29045,
     /*  345666 */   GIR_EraseRootFromParent_Done,
     /*  345667 */ // Label 5172: @345667
     /*  345667 */ GIM_Try, /*On fail goto*//*Label 5173*/ GIMT_Encode4(345729), // Rule ID 29046 //
     /*  345672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  345675 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345678 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345685 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345705 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  345708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345723 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345727 */   GIR_RootConstrainSelectedInstOperands,
     /*  345728 */   // GIR_Coverage, 29046,
     /*  345728 */   GIR_EraseRootFromParent_Done,
     /*  345729 */ // Label 5173: @345729
     /*  345729 */ GIM_Try, /*On fail goto*//*Label 5174*/ GIMT_Encode4(345791), // Rule ID 29047 //
     /*  345734 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  345737 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345740 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345747 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345767 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  345770 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345789 */   GIR_RootConstrainSelectedInstOperands,
     /*  345790 */   // GIR_Coverage, 29047,
     /*  345790 */   GIR_EraseRootFromParent_Done,
     /*  345791 */ // Label 5174: @345791
     /*  345791 */ GIM_Try, /*On fail goto*//*Label 5175*/ GIMT_Encode4(345853), // Rule ID 29048 //
     /*  345796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  345799 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345802 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345818 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345822 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345829 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  345832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345844 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345851 */   GIR_RootConstrainSelectedInstOperands,
     /*  345852 */   // GIR_Coverage, 29048,
     /*  345852 */   GIR_EraseRootFromParent_Done,
     /*  345853 */ // Label 5175: @345853
     /*  345853 */ GIM_Try, /*On fail goto*//*Label 5176*/ GIMT_Encode4(345915), // Rule ID 29049 //
     /*  345858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  345861 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345864 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345891 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_8_glue>><<P:Predicate_atomic_load_sext_8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
     /*  345894 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345906 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345909 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345913 */   GIR_RootConstrainSelectedInstOperands,
     /*  345914 */   // GIR_Coverage, 29049,
     /*  345914 */   GIR_EraseRootFromParent_Done,
     /*  345915 */ // Label 5176: @345915
     /*  345915 */ GIM_Try, /*On fail goto*//*Label 5177*/ GIMT_Encode4(345977), // Rule ID 29050 //
     /*  345920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  345923 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345926 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  345938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  345942 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  345946 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  345953 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  345953 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  345956 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  345958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  345963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  345968 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  345971 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  345975 */   GIR_RootConstrainSelectedInstOperands,
     /*  345976 */   // GIR_Coverage, 29050,
     /*  345976 */   GIR_EraseRootFromParent_Done,
     /*  345977 */ // Label 5177: @345977
     /*  345977 */ GIM_Try, /*On fail goto*//*Label 5178*/ GIMT_Encode4(346039), // Rule ID 29051 //
     /*  345982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  345985 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  345988 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  345995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346004 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346008 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346015 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  346018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346030 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346033 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346037 */   GIR_RootConstrainSelectedInstOperands,
     /*  346038 */   // GIR_Coverage, 29051,
     /*  346038 */   GIR_EraseRootFromParent_Done,
     /*  346039 */ // Label 5178: @346039
     /*  346039 */ GIM_Try, /*On fail goto*//*Label 5179*/ GIMT_Encode4(346101), // Rule ID 29052 //
     /*  346044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  346047 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346050 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  346057 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346066 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346070 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346077 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346077 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  346080 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346095 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346099 */   GIR_RootConstrainSelectedInstOperands,
     /*  346100 */   // GIR_Coverage, 29052,
     /*  346100 */   GIR_EraseRootFromParent_Done,
     /*  346101 */ // Label 5179: @346101
     /*  346101 */ GIM_Try, /*On fail goto*//*Label 5180*/ GIMT_Encode4(346163), // Rule ID 29053 //
     /*  346106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  346109 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346112 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  346119 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346139 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  346142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346154 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346161 */   GIR_RootConstrainSelectedInstOperands,
     /*  346162 */   // GIR_Coverage, 29053,
     /*  346162 */   GIR_EraseRootFromParent_Done,
     /*  346163 */ // Label 5180: @346163
     /*  346163 */ GIM_Try, /*On fail goto*//*Label 5181*/ GIMT_Encode4(346225), // Rule ID 29054 //
     /*  346168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  346171 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346174 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  346181 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346190 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346194 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346201 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
     /*  346204 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346216 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346219 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346223 */   GIR_RootConstrainSelectedInstOperands,
     /*  346224 */   // GIR_Coverage, 29054,
     /*  346224 */   GIR_EraseRootFromParent_Done,
     /*  346225 */ // Label 5181: @346225
     /*  346225 */ GIM_Try, /*On fail goto*//*Label 5182*/ GIMT_Encode4(346287), // Rule ID 29091 //
     /*  346230 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  346233 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346236 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346243 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346252 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346256 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346263 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_16_glue>><<P:Predicate_atomic_load_sext_16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  346266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346278 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346281 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346285 */   GIR_RootConstrainSelectedInstOperands,
     /*  346286 */   // GIR_Coverage, 29091,
     /*  346286 */   GIR_EraseRootFromParent_Done,
     /*  346287 */ // Label 5182: @346287
     /*  346287 */ GIM_Try, /*On fail goto*//*Label 5183*/ GIMT_Encode4(346349), // Rule ID 29092 //
     /*  346292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  346295 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346298 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346305 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346314 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346318 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346325 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_16_glue>><<P:Predicate_atomic_load_sext_16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346325 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  346328 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346340 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346343 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346347 */   GIR_RootConstrainSelectedInstOperands,
     /*  346348 */   // GIR_Coverage, 29092,
     /*  346348 */   GIR_EraseRootFromParent_Done,
     /*  346349 */ // Label 5183: @346349
     /*  346349 */ GIM_Try, /*On fail goto*//*Label 5184*/ GIMT_Encode4(346411), // Rule ID 29093 //
     /*  346354 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  346357 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346360 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346367 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346372 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346376 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346380 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346387 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_16_glue>><<P:Predicate_atomic_load_sext_16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346387 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  346390 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346402 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346405 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346409 */   GIR_RootConstrainSelectedInstOperands,
     /*  346410 */   // GIR_Coverage, 29093,
     /*  346410 */   GIR_EraseRootFromParent_Done,
     /*  346411 */ // Label 5184: @346411
     /*  346411 */ GIM_Try, /*On fail goto*//*Label 5185*/ GIMT_Encode4(346473), // Rule ID 29094 //
     /*  346416 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  346419 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346422 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346429 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346434 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346438 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346442 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346449 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_16_glue>><<P:Predicate_atomic_load_sext_16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346449 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  346452 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346464 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346471 */   GIR_RootConstrainSelectedInstOperands,
     /*  346472 */   // GIR_Coverage, 29094,
     /*  346472 */   GIR_EraseRootFromParent_Done,
     /*  346473 */ // Label 5185: @346473
     /*  346473 */ GIM_Try, /*On fail goto*//*Label 5186*/ GIMT_Encode4(346535), // Rule ID 29095 //
     /*  346478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  346481 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346484 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346491 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346496 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346500 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346504 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346511 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext_glue>><<P:Predicate_atomic_load_sext_16_glue>><<P:Predicate_atomic_load_sext_16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346511 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
     /*  346514 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346526 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346529 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346533 */   GIR_RootConstrainSelectedInstOperands,
     /*  346534 */   // GIR_Coverage, 29095,
     /*  346534 */   GIR_EraseRootFromParent_Done,
     /*  346535 */ // Label 5186: @346535
     /*  346535 */ GIM_Try, /*On fail goto*//*Label 5187*/ GIMT_Encode4(346597), // Rule ID 29096 //
     /*  346540 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  346543 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346546 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346553 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346562 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346566 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346573 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  346576 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346588 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346591 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346595 */   GIR_RootConstrainSelectedInstOperands,
     /*  346596 */   // GIR_Coverage, 29096,
     /*  346596 */   GIR_EraseRootFromParent_Done,
     /*  346597 */ // Label 5187: @346597
     /*  346597 */ GIM_Try, /*On fail goto*//*Label 5188*/ GIMT_Encode4(346659), // Rule ID 29097 //
     /*  346602 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  346605 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346608 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346620 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346624 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346628 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346635 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  346638 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346650 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346653 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346657 */   GIR_RootConstrainSelectedInstOperands,
     /*  346658 */   // GIR_Coverage, 29097,
     /*  346658 */   GIR_EraseRootFromParent_Done,
     /*  346659 */ // Label 5188: @346659
     /*  346659 */ GIM_Try, /*On fail goto*//*Label 5189*/ GIMT_Encode4(346721), // Rule ID 29098 //
     /*  346664 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  346667 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346670 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346677 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346686 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346697 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  346700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346715 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346719 */   GIR_RootConstrainSelectedInstOperands,
     /*  346720 */   // GIR_Coverage, 29098,
     /*  346720 */   GIR_EraseRootFromParent_Done,
     /*  346721 */ // Label 5189: @346721
     /*  346721 */ GIM_Try, /*On fail goto*//*Label 5190*/ GIMT_Encode4(346783), // Rule ID 29099 //
     /*  346726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  346729 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346732 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346739 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346759 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  346762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346777 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346781 */   GIR_RootConstrainSelectedInstOperands,
     /*  346782 */   // GIR_Coverage, 29099,
     /*  346782 */   GIR_EraseRootFromParent_Done,
     /*  346783 */ // Label 5190: @346783
     /*  346783 */ GIM_Try, /*On fail goto*//*Label 5191*/ GIMT_Encode4(346845), // Rule ID 29100 //
     /*  346788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  346791 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346794 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  346801 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  346806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  346821 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  346821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
     /*  346824 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  346831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  346836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  346839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346843 */   GIR_RootConstrainSelectedInstOperands,
     /*  346844 */   // GIR_Coverage, 29100,
     /*  346844 */   GIR_EraseRootFromParent_Done,
     /*  346845 */ // Label 5191: @346845
     /*  346845 */ GIM_Try, /*On fail goto*//*Label 5192*/ GIMT_Encode4(346916), // Rule ID 11767 //
     /*  346850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  346853 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346856 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  346863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  346870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  346885 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  346885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  346888 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  346895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  346900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  346905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  346910 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346914 */   GIR_RootConstrainSelectedInstOperands,
     /*  346915 */   // GIR_Coverage, 11767,
     /*  346915 */   GIR_EraseRootFromParent_Done,
     /*  346916 */ // Label 5192: @346916
     /*  346916 */ GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(346987), // Rule ID 11768 //
     /*  346921 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  346924 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346927 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  346934 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  346941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  346945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  346949 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  346956 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  346956 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  346959 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  346961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  346966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  346971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  346976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  346981 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  346985 */   GIR_RootConstrainSelectedInstOperands,
     /*  346986 */   // GIR_Coverage, 11768,
     /*  346986 */   GIR_EraseRootFromParent_Done,
     /*  346987 */ // Label 5193: @346987
     /*  346987 */ GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(347058), // Rule ID 11769 //
     /*  346992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  346995 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  346998 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347005 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347012 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347020 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347027 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347030 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347052 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347056 */   GIR_RootConstrainSelectedInstOperands,
     /*  347057 */   // GIR_Coverage, 11769,
     /*  347057 */   GIR_EraseRootFromParent_Done,
     /*  347058 */ // Label 5194: @347058
     /*  347058 */ GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(347129), // Rule ID 11770 //
     /*  347063 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  347066 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  347069 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347076 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347083 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347087 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347091 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347098 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347101 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347123 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347127 */   GIR_RootConstrainSelectedInstOperands,
     /*  347128 */   // GIR_Coverage, 11770,
     /*  347128 */   GIR_EraseRootFromParent_Done,
     /*  347129 */ // Label 5195: @347129
     /*  347129 */ GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(347200), // Rule ID 11771 //
     /*  347134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  347137 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  347140 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347158 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347162 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347169 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347194 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347198 */   GIR_RootConstrainSelectedInstOperands,
     /*  347199 */   // GIR_Coverage, 11771,
     /*  347199 */   GIR_EraseRootFromParent_Done,
     /*  347200 */ // Label 5196: @347200
     /*  347200 */ GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(347271), // Rule ID 11797 //
     /*  347205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  347208 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347211 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347229 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347233 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347240 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347240 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347243 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347265 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347269 */   GIR_RootConstrainSelectedInstOperands,
     /*  347270 */   // GIR_Coverage, 11797,
     /*  347270 */   GIR_EraseRootFromParent_Done,
     /*  347271 */ // Label 5197: @347271
     /*  347271 */ GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(347342), // Rule ID 11798 //
     /*  347276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  347279 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347282 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347311 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347314 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347336 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347340 */   GIR_RootConstrainSelectedInstOperands,
     /*  347341 */   // GIR_Coverage, 11798,
     /*  347341 */   GIR_EraseRootFromParent_Done,
     /*  347342 */ // Label 5198: @347342
     /*  347342 */ GIM_Try, /*On fail goto*//*Label 5199*/ GIMT_Encode4(347413), // Rule ID 11799 //
     /*  347347 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  347350 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347353 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347360 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347367 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347371 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347375 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347382 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347385 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347411 */   GIR_RootConstrainSelectedInstOperands,
     /*  347412 */   // GIR_Coverage, 11799,
     /*  347412 */   GIR_EraseRootFromParent_Done,
     /*  347413 */ // Label 5199: @347413
     /*  347413 */ GIM_Try, /*On fail goto*//*Label 5200*/ GIMT_Encode4(347484), // Rule ID 11800 //
     /*  347418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  347421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347424 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347431 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347453 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347478 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347482 */   GIR_RootConstrainSelectedInstOperands,
     /*  347483 */   // GIR_Coverage, 11800,
     /*  347483 */   GIR_EraseRootFromParent_Done,
     /*  347484 */ // Label 5200: @347484
     /*  347484 */ GIM_Try, /*On fail goto*//*Label 5201*/ GIMT_Encode4(347555), // Rule ID 11801 //
     /*  347489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  347492 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347495 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  347502 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347513 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347517 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347524 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347524 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
     /*  347527 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347549 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347553 */   GIR_RootConstrainSelectedInstOperands,
     /*  347554 */   // GIR_Coverage, 11801,
     /*  347554 */   GIR_EraseRootFromParent_Done,
     /*  347555 */ // Label 5201: @347555
     /*  347555 */ GIM_Try, /*On fail goto*//*Label 5202*/ GIMT_Encode4(347626), // Rule ID 11827 //
     /*  347560 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  347563 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347566 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347573 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347580 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347584 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347588 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347595 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347595 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  347598 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347615 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347620 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347624 */   GIR_RootConstrainSelectedInstOperands,
     /*  347625 */   // GIR_Coverage, 11827,
     /*  347625 */   GIR_EraseRootFromParent_Done,
     /*  347626 */ // Label 5202: @347626
     /*  347626 */ GIM_Try, /*On fail goto*//*Label 5203*/ GIMT_Encode4(347697), // Rule ID 11828 //
     /*  347631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  347634 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347637 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347644 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347651 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347655 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347666 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  347669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347691 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347695 */   GIR_RootConstrainSelectedInstOperands,
     /*  347696 */   // GIR_Coverage, 11828,
     /*  347696 */   GIR_EraseRootFromParent_Done,
     /*  347697 */ // Label 5203: @347697
     /*  347697 */ GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(347768), // Rule ID 11829 //
     /*  347702 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  347705 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347708 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347715 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347722 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347726 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347730 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347737 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347737 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  347740 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347757 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347762 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347766 */   GIR_RootConstrainSelectedInstOperands,
     /*  347767 */   // GIR_Coverage, 11829,
     /*  347767 */   GIR_EraseRootFromParent_Done,
     /*  347768 */ // Label 5204: @347768
     /*  347768 */ GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(347839), // Rule ID 11830 //
     /*  347773 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  347776 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347779 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347786 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347797 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347801 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347808 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  347811 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347833 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347837 */   GIR_RootConstrainSelectedInstOperands,
     /*  347838 */   // GIR_Coverage, 11830,
     /*  347838 */   GIR_EraseRootFromParent_Done,
     /*  347839 */ // Label 5205: @347839
     /*  347839 */ GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(347910), // Rule ID 11831 //
     /*  347844 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  347847 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  347850 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347857 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347879 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  347882 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347904 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347908 */   GIR_RootConstrainSelectedInstOperands,
     /*  347909 */   // GIR_Coverage, 11831,
     /*  347909 */   GIR_EraseRootFromParent_Done,
     /*  347910 */ // Label 5206: @347910
     /*  347910 */ GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(347981), // Rule ID 11867 //
     /*  347915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  347918 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  347921 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347928 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  347935 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  347939 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  347943 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  347950 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  347950 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  347953 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  347955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  347960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  347965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  347970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  347975 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  347979 */   GIR_RootConstrainSelectedInstOperands,
     /*  347980 */   // GIR_Coverage, 11867,
     /*  347980 */   GIR_EraseRootFromParent_Done,
     /*  347981 */ // Label 5207: @347981
     /*  347981 */ GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(348052), // Rule ID 11868 //
     /*  347986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  347989 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  347992 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  347999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348021 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  348021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348050 */   GIR_RootConstrainSelectedInstOperands,
     /*  348051 */   // GIR_Coverage, 11868,
     /*  348051 */   GIR_EraseRootFromParent_Done,
     /*  348052 */ // Label 5208: @348052
     /*  348052 */ GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(348123), // Rule ID 11869 //
     /*  348057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  348060 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348063 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348070 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348077 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348081 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348085 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348092 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  348092 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348095 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348117 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348121 */   GIR_RootConstrainSelectedInstOperands,
     /*  348122 */   // GIR_Coverage, 11869,
     /*  348122 */   GIR_EraseRootFromParent_Done,
     /*  348123 */ // Label 5209: @348123
     /*  348123 */ GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(348194), // Rule ID 11870 //
     /*  348128 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  348131 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348134 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348141 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348152 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348156 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348163 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  348163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348166 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348192 */   GIR_RootConstrainSelectedInstOperands,
     /*  348193 */   // GIR_Coverage, 11870,
     /*  348193 */   GIR_EraseRootFromParent_Done,
     /*  348194 */ // Label 5210: @348194
     /*  348194 */ GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(348265), // Rule ID 11871 //
     /*  348199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  348202 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348205 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348212 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348223 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348227 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348234 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  348234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348259 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348263 */   GIR_RootConstrainSelectedInstOperands,
     /*  348264 */   // GIR_Coverage, 11871,
     /*  348264 */   GIR_EraseRootFromParent_Done,
     /*  348265 */ // Label 5211: @348265
     /*  348265 */ GIM_Try, /*On fail goto*//*Label 5212*/ GIMT_Encode4(348366), // Rule ID 11967 //
     /*  348270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  348273 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348276 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348283 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348305 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  348305 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  348308 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348312 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  348317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348337 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348341 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  348343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  348346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  348348 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  348355 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348360 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348365 */   // GIR_Coverage, 11967,
     /*  348365 */   GIR_EraseRootFromParent_Done,
     /*  348366 */ // Label 5212: @348366
     /*  348366 */ GIM_Try, /*On fail goto*//*Label 5213*/ GIMT_Encode4(348467), // Rule ID 11968 //
     /*  348371 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  348374 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348377 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348384 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348391 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348395 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348399 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348406 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  348406 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  348409 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348413 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  348418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348438 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348442 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  348444 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  348447 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  348449 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  348456 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348461 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348466 */   // GIR_Coverage, 11968,
     /*  348466 */   GIR_EraseRootFromParent_Done,
     /*  348467 */ // Label 5213: @348467
     /*  348467 */ GIM_Try, /*On fail goto*//*Label 5214*/ GIMT_Encode4(348568), // Rule ID 11969 //
     /*  348472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  348475 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348485 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348496 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348500 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348507 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  348507 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  348510 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348514 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  348519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348539 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348543 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  348545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  348548 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  348550 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  348557 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348562 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348567 */   // GIR_Coverage, 11969,
     /*  348567 */   GIR_EraseRootFromParent_Done,
     /*  348568 */ // Label 5214: @348568
     /*  348568 */ GIM_Try, /*On fail goto*//*Label 5215*/ GIMT_Encode4(348669), // Rule ID 11970 //
     /*  348573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  348576 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348579 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348586 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348593 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348597 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348601 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348608 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  348608 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  348611 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348615 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  348620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348640 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348644 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  348646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  348649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  348651 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  348658 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348663 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348668 */   // GIR_Coverage, 11970,
     /*  348668 */   GIR_EraseRootFromParent_Done,
     /*  348669 */ // Label 5215: @348669
     /*  348669 */ GIM_Try, /*On fail goto*//*Label 5216*/ GIMT_Encode4(348770), // Rule ID 11971 //
     /*  348674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  348677 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348680 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  348687 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348694 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348698 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348702 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  348709 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  348709 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  348712 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
     /*  348716 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  348721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  348726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  348731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  348736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  348741 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348745 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  348747 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  348750 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  348752 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  348759 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  348764 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348769 */   // GIR_Coverage, 11971,
     /*  348769 */   GIR_EraseRootFromParent_Done,
     /*  348770 */ // Label 5216: @348770
     /*  348770 */ GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(348834), // Rule ID 11762 //
     /*  348775 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  348778 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348781 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  348788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  348810 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  348810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  348813 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  348820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  348825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  348828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348832 */   GIR_RootConstrainSelectedInstOperands,
     /*  348833 */   // GIR_Coverage, 11762,
     /*  348833 */   GIR_EraseRootFromParent_Done,
     /*  348834 */ // Label 5217: @348834
     /*  348834 */ GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(348898), // Rule ID 11763 //
     /*  348839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  348842 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348845 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  348852 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348863 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348867 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  348874 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  348874 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  348877 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  348884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  348889 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  348892 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348896 */   GIR_RootConstrainSelectedInstOperands,
     /*  348897 */   // GIR_Coverage, 11763,
     /*  348897 */   GIR_EraseRootFromParent_Done,
     /*  348898 */ // Label 5218: @348898
     /*  348898 */ GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(348962), // Rule ID 11764 //
     /*  348903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  348906 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348909 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  348916 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348923 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348927 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348931 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  348938 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  348938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  348941 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  348943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  348948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  348953 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  348956 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  348960 */   GIR_RootConstrainSelectedInstOperands,
     /*  348961 */   // GIR_Coverage, 11764,
     /*  348961 */   GIR_EraseRootFromParent_Done,
     /*  348962 */ // Label 5219: @348962
     /*  348962 */ GIM_Try, /*On fail goto*//*Label 5220*/ GIMT_Encode4(349026), // Rule ID 11765 //
     /*  348967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  348970 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  348973 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  348980 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  348987 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  348991 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  348995 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349002 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349002 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349005 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349017 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349020 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349024 */   GIR_RootConstrainSelectedInstOperands,
     /*  349025 */   // GIR_Coverage, 11765,
     /*  349025 */   GIR_EraseRootFromParent_Done,
     /*  349026 */ // Label 5220: @349026
     /*  349026 */ GIM_Try, /*On fail goto*//*Label 5221*/ GIMT_Encode4(349090), // Rule ID 11766 //
     /*  349031 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  349034 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  349037 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  349044 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349059 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349066 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349069 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349088 */   GIR_RootConstrainSelectedInstOperands,
     /*  349089 */   // GIR_Coverage, 11766,
     /*  349089 */   GIR_EraseRootFromParent_Done,
     /*  349090 */ // Label 5221: @349090
     /*  349090 */ GIM_Try, /*On fail goto*//*Label 5222*/ GIMT_Encode4(349154), // Rule ID 11792 //
     /*  349095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  349098 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349101 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  349108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349115 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349123 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349130 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349133 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349145 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349148 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349152 */   GIR_RootConstrainSelectedInstOperands,
     /*  349153 */   // GIR_Coverage, 11792,
     /*  349153 */   GIR_EraseRootFromParent_Done,
     /*  349154 */ // Label 5222: @349154
     /*  349154 */ GIM_Try, /*On fail goto*//*Label 5223*/ GIMT_Encode4(349218), // Rule ID 11793 //
     /*  349159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  349162 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349165 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  349172 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349183 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349187 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349194 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349197 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349216 */   GIR_RootConstrainSelectedInstOperands,
     /*  349217 */   // GIR_Coverage, 11793,
     /*  349217 */   GIR_EraseRootFromParent_Done,
     /*  349218 */ // Label 5223: @349218
     /*  349218 */ GIM_Try, /*On fail goto*//*Label 5224*/ GIMT_Encode4(349282), // Rule ID 11794 //
     /*  349223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  349226 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349229 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  349236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349258 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349261 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349273 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349276 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349280 */   GIR_RootConstrainSelectedInstOperands,
     /*  349281 */   // GIR_Coverage, 11794,
     /*  349281 */   GIR_EraseRootFromParent_Done,
     /*  349282 */ // Label 5224: @349282
     /*  349282 */ GIM_Try, /*On fail goto*//*Label 5225*/ GIMT_Encode4(349346), // Rule ID 11795 //
     /*  349287 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  349290 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349293 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  349300 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349311 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349315 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349322 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349322 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349325 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349340 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349344 */   GIR_RootConstrainSelectedInstOperands,
     /*  349345 */   // GIR_Coverage, 11795,
     /*  349345 */   GIR_EraseRootFromParent_Done,
     /*  349346 */ // Label 5225: @349346
     /*  349346 */ GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(349410), // Rule ID 11796 //
     /*  349351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  349354 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349357 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  349364 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349375 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349379 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349386 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349386 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
     /*  349389 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349401 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349404 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349408 */   GIR_RootConstrainSelectedInstOperands,
     /*  349409 */   // GIR_Coverage, 11796,
     /*  349409 */   GIR_EraseRootFromParent_Done,
     /*  349410 */ // Label 5226: @349410
     /*  349410 */ GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(349474), // Rule ID 11822 //
     /*  349415 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  349418 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349421 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349435 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349439 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349443 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349450 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349450 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349453 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349465 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349468 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349472 */   GIR_RootConstrainSelectedInstOperands,
     /*  349473 */   // GIR_Coverage, 11822,
     /*  349473 */   GIR_EraseRootFromParent_Done,
     /*  349474 */ // Label 5227: @349474
     /*  349474 */ GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(349538), // Rule ID 11823 //
     /*  349479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  349482 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349485 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349514 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349517 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349536 */   GIR_RootConstrainSelectedInstOperands,
     /*  349537 */   // GIR_Coverage, 11823,
     /*  349537 */   GIR_EraseRootFromParent_Done,
     /*  349538 */ // Label 5228: @349538
     /*  349538 */ GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(349602), // Rule ID 11824 //
     /*  349543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  349546 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349549 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349578 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349596 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349600 */   GIR_RootConstrainSelectedInstOperands,
     /*  349601 */   // GIR_Coverage, 11824,
     /*  349601 */   GIR_EraseRootFromParent_Done,
     /*  349602 */ // Label 5229: @349602
     /*  349602 */ GIM_Try, /*On fail goto*//*Label 5230*/ GIMT_Encode4(349666), // Rule ID 11825 //
     /*  349607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  349610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349613 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349642 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349645 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349657 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349660 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349664 */   GIR_RootConstrainSelectedInstOperands,
     /*  349665 */   // GIR_Coverage, 11825,
     /*  349665 */   GIR_EraseRootFromParent_Done,
     /*  349666 */ // Label 5230: @349666
     /*  349666 */ GIM_Try, /*On fail goto*//*Label 5231*/ GIMT_Encode4(349730), // Rule ID 11826 //
     /*  349671 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  349674 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  349677 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349691 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349695 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349699 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349706 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349706 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349709 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349724 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349728 */   GIR_RootConstrainSelectedInstOperands,
     /*  349729 */   // GIR_Coverage, 11826,
     /*  349729 */   GIR_EraseRootFromParent_Done,
     /*  349730 */ // Label 5231: @349730
     /*  349730 */ GIM_Try, /*On fail goto*//*Label 5232*/ GIMT_Encode4(349794), // Rule ID 11862 //
     /*  349735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  349738 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  349741 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349748 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349759 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349763 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349770 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349773 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349792 */   GIR_RootConstrainSelectedInstOperands,
     /*  349793 */   // GIR_Coverage, 11862,
     /*  349793 */   GIR_EraseRootFromParent_Done,
     /*  349794 */ // Label 5232: @349794
     /*  349794 */ GIM_Try, /*On fail goto*//*Label 5233*/ GIMT_Encode4(349858), // Rule ID 11863 //
     /*  349799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  349802 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  349805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349823 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349827 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349834 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349834 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349837 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349849 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349856 */   GIR_RootConstrainSelectedInstOperands,
     /*  349857 */   // GIR_Coverage, 11863,
     /*  349857 */   GIR_EraseRootFromParent_Done,
     /*  349858 */ // Label 5233: @349858
     /*  349858 */ GIM_Try, /*On fail goto*//*Label 5234*/ GIMT_Encode4(349922), // Rule ID 11864 //
     /*  349863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  349866 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  349869 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349883 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349898 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349913 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349916 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349920 */   GIR_RootConstrainSelectedInstOperands,
     /*  349921 */   // GIR_Coverage, 11864,
     /*  349921 */   GIR_EraseRootFromParent_Done,
     /*  349922 */ // Label 5234: @349922
     /*  349922 */ GIM_Try, /*On fail goto*//*Label 5235*/ GIMT_Encode4(349986), // Rule ID 11865 //
     /*  349927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  349930 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  349933 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  349940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  349947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  349951 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  349955 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  349962 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  349962 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  349965 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  349967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  349972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  349977 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  349980 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  349984 */   GIR_RootConstrainSelectedInstOperands,
     /*  349985 */   // GIR_Coverage, 11865,
     /*  349985 */   GIR_EraseRootFromParent_Done,
     /*  349986 */ // Label 5235: @349986
     /*  349986 */ GIM_Try, /*On fail goto*//*Label 5236*/ GIMT_Encode4(350050), // Rule ID 11866 //
     /*  349991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  349994 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  349997 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  350004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  350026 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  350026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  350029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  350036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  350041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  350044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350048 */   GIR_RootConstrainSelectedInstOperands,
     /*  350049 */   // GIR_Coverage, 11866,
     /*  350049 */   GIR_EraseRootFromParent_Done,
     /*  350050 */ // Label 5236: @350050
     /*  350050 */ GIM_Try, /*On fail goto*//*Label 5237*/ GIMT_Encode4(350144), // Rule ID 11962 //
     /*  350055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  350058 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350061 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  350068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350079 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350083 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  350090 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  350090 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  350093 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  350097 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  350102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  350107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  350112 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  350115 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350119 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  350121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  350124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  350126 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  350133 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350138 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350143 */   // GIR_Coverage, 11962,
     /*  350143 */   GIR_EraseRootFromParent_Done,
     /*  350144 */ // Label 5237: @350144
     /*  350144 */ GIM_Try, /*On fail goto*//*Label 5238*/ GIMT_Encode4(350238), // Rule ID 11963 //
     /*  350149 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  350152 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350155 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  350162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350173 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350177 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  350184 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  350184 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  350187 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  350191 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  350196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  350201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  350206 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  350209 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350213 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  350215 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  350218 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  350220 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  350227 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350232 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350237 */   // GIR_Coverage, 11963,
     /*  350237 */   GIR_EraseRootFromParent_Done,
     /*  350238 */ // Label 5238: @350238
     /*  350238 */ GIM_Try, /*On fail goto*//*Label 5239*/ GIMT_Encode4(350332), // Rule ID 11964 //
     /*  350243 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  350246 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350249 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  350256 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  350278 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  350278 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  350281 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  350285 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  350290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  350295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  350300 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  350303 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  350309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  350312 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  350314 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  350321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350326 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350331 */   // GIR_Coverage, 11964,
     /*  350331 */   GIR_EraseRootFromParent_Done,
     /*  350332 */ // Label 5239: @350332
     /*  350332 */ GIM_Try, /*On fail goto*//*Label 5240*/ GIMT_Encode4(350426), // Rule ID 11965 //
     /*  350337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  350340 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350343 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  350350 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350361 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350365 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  350372 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  350372 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  350375 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  350379 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  350384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  350389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  350394 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  350397 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350401 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  350403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  350406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  350408 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  350415 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350420 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350425 */   // GIR_Coverage, 11965,
     /*  350425 */   GIR_EraseRootFromParent_Done,
     /*  350426 */ // Label 5240: @350426
     /*  350426 */ GIM_Try, /*On fail goto*//*Label 5241*/ GIMT_Encode4(350520), // Rule ID 11966 //
     /*  350431 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  350434 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350437 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  350444 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  350466 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_SSHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  350466 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  350469 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
     /*  350473 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  350478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  350483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  350488 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  350491 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350495 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  350497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  350500 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  350502 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  350509 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  350514 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350519 */   // GIR_Coverage, 11966,
     /*  350519 */   GIR_EraseRootFromParent_Done,
     /*  350520 */ // Label 5241: @350520
     /*  350520 */ GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(350592), // Rule ID 9591 //
     /*  350525 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  350528 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  350531 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350538 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350550 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350554 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350561 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350564 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  350571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  350576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  350581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  350586 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350590 */   GIR_RootConstrainSelectedInstOperands,
     /*  350591 */   // GIR_Coverage, 9591,
     /*  350591 */   GIR_EraseRootFromParent_Done,
     /*  350592 */ // Label 5242: @350592
     /*  350592 */ GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(350664), // Rule ID 9592 //
     /*  350597 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  350600 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  350603 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350610 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350622 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350626 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350633 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350633 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350636 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  350643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  350648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  350653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  350658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350662 */   GIR_RootConstrainSelectedInstOperands,
     /*  350663 */   // GIR_Coverage, 9592,
     /*  350663 */   GIR_EraseRootFromParent_Done,
     /*  350664 */ // Label 5243: @350664
     /*  350664 */ GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(350736), // Rule ID 9593 //
     /*  350669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  350672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  350675 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350705 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  350715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  350720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  350725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  350730 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350734 */   GIR_RootConstrainSelectedInstOperands,
     /*  350735 */   // GIR_Coverage, 9593,
     /*  350735 */   GIR_EraseRootFromParent_Done,
     /*  350736 */ // Label 5244: @350736
     /*  350736 */ GIM_Try, /*On fail goto*//*Label 5245*/ GIMT_Encode4(350808), // Rule ID 9594 //
     /*  350741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  350744 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  350747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350762 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350766 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350770 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350777 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350777 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350780 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  350787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  350792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  350797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  350802 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350806 */   GIR_RootConstrainSelectedInstOperands,
     /*  350807 */   // GIR_Coverage, 9594,
     /*  350807 */   GIR_EraseRootFromParent_Done,
     /*  350808 */ // Label 5245: @350808
     /*  350808 */ GIM_Try, /*On fail goto*//*Label 5246*/ GIMT_Encode4(350880), // Rule ID 9595 //
     /*  350813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  350816 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  350819 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350826 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350842 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350849 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  350859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  350864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  350869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  350874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350878 */   GIR_RootConstrainSelectedInstOperands,
     /*  350879 */   // GIR_Coverage, 9595,
     /*  350879 */   GIR_EraseRootFromParent_Done,
     /*  350880 */ // Label 5246: @350880
     /*  350880 */ GIM_Try, /*On fail goto*//*Label 5247*/ GIMT_Encode4(350952), // Rule ID 9601 //
     /*  350885 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  350888 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350891 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350910 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350914 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350921 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350924 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  350931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  350936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  350941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  350946 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  350950 */   GIR_RootConstrainSelectedInstOperands,
     /*  350951 */   // GIR_Coverage, 9601,
     /*  350951 */   GIR_EraseRootFromParent_Done,
     /*  350952 */ // Label 5247: @350952
     /*  350952 */ GIM_Try, /*On fail goto*//*Label 5248*/ GIMT_Encode4(351024), // Rule ID 9602 //
     /*  350957 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  350960 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  350963 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  350970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  350978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  350982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  350986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  350993 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  350993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  350996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  350998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351018 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351022 */   GIR_RootConstrainSelectedInstOperands,
     /*  351023 */   // GIR_Coverage, 9602,
     /*  351023 */   GIR_EraseRootFromParent_Done,
     /*  351024 */ // Label 5248: @351024
     /*  351024 */ GIM_Try, /*On fail goto*//*Label 5249*/ GIMT_Encode4(351096), // Rule ID 9603 //
     /*  351029 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  351032 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351035 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  351042 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351054 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351058 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351065 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351065 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  351068 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351090 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351094 */   GIR_RootConstrainSelectedInstOperands,
     /*  351095 */   // GIR_Coverage, 9603,
     /*  351095 */   GIR_EraseRootFromParent_Done,
     /*  351096 */ // Label 5249: @351096
     /*  351096 */ GIM_Try, /*On fail goto*//*Label 5250*/ GIMT_Encode4(351168), // Rule ID 9604 //
     /*  351101 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  351104 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351107 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  351114 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351122 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351126 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351130 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351137 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351137 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  351140 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351162 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351166 */   GIR_RootConstrainSelectedInstOperands,
     /*  351167 */   // GIR_Coverage, 9604,
     /*  351167 */   GIR_EraseRootFromParent_Done,
     /*  351168 */ // Label 5250: @351168
     /*  351168 */ GIM_Try, /*On fail goto*//*Label 5251*/ GIMT_Encode4(351240), // Rule ID 9605 //
     /*  351173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  351176 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351179 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  351186 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351209 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE_SADDR),
     /*  351212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351234 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351238 */   GIR_RootConstrainSelectedInstOperands,
     /*  351239 */   // GIR_Coverage, 9605,
     /*  351239 */   GIR_EraseRootFromParent_Done,
     /*  351240 */ // Label 5251: @351240
     /*  351240 */ GIM_Try, /*On fail goto*//*Label 5252*/ GIMT_Encode4(351312), // Rule ID 9631 //
     /*  351245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  351248 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  351251 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351258 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351274 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351281 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351281 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351284 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351306 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351310 */   GIR_RootConstrainSelectedInstOperands,
     /*  351311 */   // GIR_Coverage, 9631,
     /*  351311 */   GIR_EraseRootFromParent_Done,
     /*  351312 */ // Label 5252: @351312
     /*  351312 */ GIM_Try, /*On fail goto*//*Label 5253*/ GIMT_Encode4(351384), // Rule ID 9632 //
     /*  351317 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  351320 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  351323 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351330 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351353 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351382 */   GIR_RootConstrainSelectedInstOperands,
     /*  351383 */   // GIR_Coverage, 9632,
     /*  351383 */   GIR_EraseRootFromParent_Done,
     /*  351384 */ // Label 5253: @351384
     /*  351384 */ GIM_Try, /*On fail goto*//*Label 5254*/ GIMT_Encode4(351456), // Rule ID 9633 //
     /*  351389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  351392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  351395 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351402 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351410 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351414 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351418 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351425 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351425 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351428 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351450 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351454 */   GIR_RootConstrainSelectedInstOperands,
     /*  351455 */   // GIR_Coverage, 9633,
     /*  351455 */   GIR_EraseRootFromParent_Done,
     /*  351456 */ // Label 5254: @351456
     /*  351456 */ GIM_Try, /*On fail goto*//*Label 5255*/ GIMT_Encode4(351528), // Rule ID 9634 //
     /*  351461 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  351464 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  351467 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351474 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351486 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351490 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351497 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351500 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351502 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351522 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351526 */   GIR_RootConstrainSelectedInstOperands,
     /*  351527 */   // GIR_Coverage, 9634,
     /*  351527 */   GIR_EraseRootFromParent_Done,
     /*  351528 */ // Label 5255: @351528
     /*  351528 */ GIM_Try, /*On fail goto*//*Label 5256*/ GIMT_Encode4(351600), // Rule ID 9635 //
     /*  351533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  351536 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  351539 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351546 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351554 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351558 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351562 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351569 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351572 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351594 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351598 */   GIR_RootConstrainSelectedInstOperands,
     /*  351599 */   // GIR_Coverage, 9635,
     /*  351599 */   GIR_EraseRootFromParent_Done,
     /*  351600 */ // Label 5256: @351600
     /*  351600 */ GIM_Try, /*On fail goto*//*Label 5257*/ GIMT_Encode4(351672), // Rule ID 9641 //
     /*  351605 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  351608 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351611 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351626 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351630 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351641 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351666 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351670 */   GIR_RootConstrainSelectedInstOperands,
     /*  351671 */   // GIR_Coverage, 9641,
     /*  351671 */   GIR_EraseRootFromParent_Done,
     /*  351672 */ // Label 5257: @351672
     /*  351672 */ GIM_Try, /*On fail goto*//*Label 5258*/ GIMT_Encode4(351744), // Rule ID 9642 //
     /*  351677 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  351680 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351683 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351690 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351713 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351738 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351742 */   GIR_RootConstrainSelectedInstOperands,
     /*  351743 */   // GIR_Coverage, 9642,
     /*  351743 */   GIR_EraseRootFromParent_Done,
     /*  351744 */ // Label 5258: @351744
     /*  351744 */ GIM_Try, /*On fail goto*//*Label 5259*/ GIMT_Encode4(351816), // Rule ID 9643 //
     /*  351749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  351752 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351755 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351762 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351770 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351774 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351778 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351785 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351788 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351810 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351814 */   GIR_RootConstrainSelectedInstOperands,
     /*  351815 */   // GIR_Coverage, 9643,
     /*  351815 */   GIR_EraseRootFromParent_Done,
     /*  351816 */ // Label 5259: @351816
     /*  351816 */ GIM_Try, /*On fail goto*//*Label 5260*/ GIMT_Encode4(351888), // Rule ID 9644 //
     /*  351821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  351824 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351827 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351846 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351850 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351857 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351860 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351886 */   GIR_RootConstrainSelectedInstOperands,
     /*  351887 */   // GIR_Coverage, 9644,
     /*  351887 */   GIR_EraseRootFromParent_Done,
     /*  351888 */ // Label 5260: @351888
     /*  351888 */ GIM_Try, /*On fail goto*//*Label 5261*/ GIMT_Encode4(351960), // Rule ID 9645 //
     /*  351893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  351896 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  351899 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  351906 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351918 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351922 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  351929 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  351929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT_SADDR),
     /*  351932 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  351934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  351939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  351944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  351949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  351954 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  351958 */   GIR_RootConstrainSelectedInstOperands,
     /*  351959 */   // GIR_Coverage, 9645,
     /*  351959 */   GIR_EraseRootFromParent_Done,
     /*  351960 */ // Label 5261: @351960
     /*  351960 */ GIM_Try, /*On fail goto*//*Label 5262*/ GIMT_Encode4(352025), // Rule ID 9586 //
     /*  351965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  351968 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  351971 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  351978 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  351986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  351990 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  351994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352001 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352023 */   GIR_RootConstrainSelectedInstOperands,
     /*  352024 */   // GIR_Coverage, 9586,
     /*  352024 */   GIR_EraseRootFromParent_Done,
     /*  352025 */ // Label 5262: @352025
     /*  352025 */ GIM_Try, /*On fail goto*//*Label 5263*/ GIMT_Encode4(352090), // Rule ID 9587 //
     /*  352030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  352033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352036 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352043 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352059 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352066 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352069 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352088 */   GIR_RootConstrainSelectedInstOperands,
     /*  352089 */   // GIR_Coverage, 9587,
     /*  352089 */   GIR_EraseRootFromParent_Done,
     /*  352090 */ // Label 5263: @352090
     /*  352090 */ GIM_Try, /*On fail goto*//*Label 5264*/ GIMT_Encode4(352155), // Rule ID 9588 //
     /*  352095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  352098 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352101 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352116 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352120 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352124 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352131 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352131 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352134 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352146 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352149 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352153 */   GIR_RootConstrainSelectedInstOperands,
     /*  352154 */   // GIR_Coverage, 9588,
     /*  352154 */   GIR_EraseRootFromParent_Done,
     /*  352155 */ // Label 5264: @352155
     /*  352155 */ GIM_Try, /*On fail goto*//*Label 5265*/ GIMT_Encode4(352220), // Rule ID 9589 //
     /*  352160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  352163 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352166 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352173 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352185 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352189 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352196 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352196 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352199 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352214 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352218 */   GIR_RootConstrainSelectedInstOperands,
     /*  352219 */   // GIR_Coverage, 9589,
     /*  352219 */   GIR_EraseRootFromParent_Done,
     /*  352220 */ // Label 5265: @352220
     /*  352220 */ GIM_Try, /*On fail goto*//*Label 5266*/ GIMT_Encode4(352285), // Rule ID 9590 //
     /*  352225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  352228 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352231 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352238 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352261 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352283 */   GIR_RootConstrainSelectedInstOperands,
     /*  352284 */   // GIR_Coverage, 9590,
     /*  352284 */   GIR_EraseRootFromParent_Done,
     /*  352285 */ // Label 5266: @352285
     /*  352285 */ GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(352350), // Rule ID 9596 //
     /*  352290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  352293 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  352296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352326 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352329 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352344 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352348 */   GIR_RootConstrainSelectedInstOperands,
     /*  352349 */   // GIR_Coverage, 9596,
     /*  352349 */   GIR_EraseRootFromParent_Done,
     /*  352350 */ // Label 5267: @352350
     /*  352350 */ GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(352415), // Rule ID 9597 //
     /*  352355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  352358 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  352361 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352368 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352376 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352380 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352384 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352391 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352413 */   GIR_RootConstrainSelectedInstOperands,
     /*  352414 */   // GIR_Coverage, 9597,
     /*  352414 */   GIR_EraseRootFromParent_Done,
     /*  352415 */ // Label 5268: @352415
     /*  352415 */ GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(352480), // Rule ID 9598 //
     /*  352420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  352423 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  352426 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352433 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352445 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352449 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352456 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352456 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352459 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352478 */   GIR_RootConstrainSelectedInstOperands,
     /*  352479 */   // GIR_Coverage, 9598,
     /*  352479 */   GIR_EraseRootFromParent_Done,
     /*  352480 */ // Label 5269: @352480
     /*  352480 */ GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(352545), // Rule ID 9599 //
     /*  352485 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  352488 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  352491 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352498 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352514 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352521 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352524 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352536 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352543 */   GIR_RootConstrainSelectedInstOperands,
     /*  352544 */   // GIR_Coverage, 9599,
     /*  352544 */   GIR_EraseRootFromParent_Done,
     /*  352545 */ // Label 5270: @352545
     /*  352545 */ GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(352610), // Rule ID 9600 //
     /*  352550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  352553 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  352556 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  352563 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352571 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352575 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352579 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352586 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_8>><<P:Predicate_atomic_load_sext_8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352586 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
     /*  352589 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352601 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352604 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352608 */   GIR_RootConstrainSelectedInstOperands,
     /*  352609 */   // GIR_Coverage, 9600,
     /*  352609 */   GIR_EraseRootFromParent_Done,
     /*  352610 */ // Label 5271: @352610
     /*  352610 */ GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(352675), // Rule ID 9626 //
     /*  352615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  352618 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352621 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  352628 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352640 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352644 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352651 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352651 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  352654 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352666 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352669 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352673 */   GIR_RootConstrainSelectedInstOperands,
     /*  352674 */   // GIR_Coverage, 9626,
     /*  352674 */   GIR_EraseRootFromParent_Done,
     /*  352675 */ // Label 5272: @352675
     /*  352675 */ GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(352740), // Rule ID 9627 //
     /*  352680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  352683 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  352693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352701 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352705 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352709 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352716 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352716 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  352719 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352731 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352734 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352738 */   GIR_RootConstrainSelectedInstOperands,
     /*  352739 */   // GIR_Coverage, 9627,
     /*  352739 */   GIR_EraseRootFromParent_Done,
     /*  352740 */ // Label 5273: @352740
     /*  352740 */ GIM_Try, /*On fail goto*//*Label 5274*/ GIMT_Encode4(352805), // Rule ID 9628 //
     /*  352745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  352748 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352751 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  352758 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352781 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  352784 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352796 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352799 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352803 */   GIR_RootConstrainSelectedInstOperands,
     /*  352804 */   // GIR_Coverage, 9628,
     /*  352804 */   GIR_EraseRootFromParent_Done,
     /*  352805 */ // Label 5274: @352805
     /*  352805 */ GIM_Try, /*On fail goto*//*Label 5275*/ GIMT_Encode4(352870), // Rule ID 9629 //
     /*  352810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  352813 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352816 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  352823 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352831 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352835 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352839 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352846 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352846 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  352849 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352861 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352864 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352868 */   GIR_RootConstrainSelectedInstOperands,
     /*  352869 */   // GIR_Coverage, 9629,
     /*  352869 */   GIR_EraseRootFromParent_Done,
     /*  352870 */ // Label 5275: @352870
     /*  352870 */ GIM_Try, /*On fail goto*//*Label 5276*/ GIMT_Encode4(352935), // Rule ID 9630 //
     /*  352875 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  352878 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  352881 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  352888 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352904 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352911 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  352914 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352926 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352929 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352933 */   GIR_RootConstrainSelectedInstOperands,
     /*  352934 */   // GIR_Coverage, 9630,
     /*  352934 */   GIR_EraseRootFromParent_Done,
     /*  352935 */ // Label 5276: @352935
     /*  352935 */ GIM_Try, /*On fail goto*//*Label 5277*/ GIMT_Encode4(353000), // Rule ID 9636 //
     /*  352940 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  352943 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  352946 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  352953 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  352961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  352965 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  352969 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  352976 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  352976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  352979 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  352981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  352986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  352991 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  352994 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  352998 */   GIR_RootConstrainSelectedInstOperands,
     /*  352999 */   // GIR_Coverage, 9636,
     /*  352999 */   GIR_EraseRootFromParent_Done,
     /*  353000 */ // Label 5277: @353000
     /*  353000 */ GIM_Try, /*On fail goto*//*Label 5278*/ GIMT_Encode4(353065), // Rule ID 9637 //
     /*  353005 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  353008 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  353011 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  353018 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  353026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353030 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353034 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  353041 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  353041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  353044 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  353046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  353051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  353056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353059 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353063 */   GIR_RootConstrainSelectedInstOperands,
     /*  353064 */   // GIR_Coverage, 9637,
     /*  353064 */   GIR_EraseRootFromParent_Done,
     /*  353065 */ // Label 5278: @353065
     /*  353065 */ GIM_Try, /*On fail goto*//*Label 5279*/ GIMT_Encode4(353130), // Rule ID 9638 //
     /*  353070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  353073 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  353076 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  353083 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  353091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353095 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353099 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  353106 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  353106 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  353109 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  353111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  353116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  353121 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353124 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353128 */   GIR_RootConstrainSelectedInstOperands,
     /*  353129 */   // GIR_Coverage, 9638,
     /*  353129 */   GIR_EraseRootFromParent_Done,
     /*  353130 */ // Label 5279: @353130
     /*  353130 */ GIM_Try, /*On fail goto*//*Label 5280*/ GIMT_Encode4(353195), // Rule ID 9639 //
     /*  353135 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  353138 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  353141 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  353148 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  353156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353160 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353164 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  353171 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  353171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  353174 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  353176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  353181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  353186 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353189 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353193 */   GIR_RootConstrainSelectedInstOperands,
     /*  353194 */   // GIR_Coverage, 9639,
     /*  353194 */   GIR_EraseRootFromParent_Done,
     /*  353195 */ // Label 5280: @353195
     /*  353195 */ GIM_Try, /*On fail goto*//*Label 5281*/ GIMT_Encode4(353260), // Rule ID 9640 //
     /*  353200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  353203 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  353206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  353213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  353221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  353236 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_sext>><<P:Predicate_atomic_load_sext_16>><<P:Predicate_atomic_load_sext_16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  353236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
     /*  353239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  353241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  353246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  353251 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353254 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353258 */   GIR_RootConstrainSelectedInstOperands,
     /*  353259 */   // GIR_Coverage, 9640,
     /*  353259 */   GIR_EraseRootFromParent_Done,
     /*  353260 */ // Label 5281: @353260
     /*  353260 */ GIM_Reject,
     /*  353261 */ // Label 4754: @353261
     /*  353261 */ GIM_Reject,
     /*  353262 */ // Label 16: @353262
     /*  353262 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 5284*/ GIMT_Encode4(395068),
     /*  353273 */ /*GILLT_s16*//*Label 5282*/ GIMT_Encode4(353281),
     /*  353277 */ /*GILLT_s32*//*Label 5283*/ GIMT_Encode4(373451),
     /*  353281 */ // Label 5282: @353281
     /*  353281 */ GIM_Try, /*On fail goto*//*Label 5285*/ GIMT_Encode4(353351), // Rule ID 25076 //
     /*  353286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  353289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353308 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353312 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353319 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353319 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  353322 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353342 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353349 */   GIR_RootConstrainSelectedInstOperands,
     /*  353350 */   // GIR_Coverage, 25076,
     /*  353350 */   GIR_EraseRootFromParent_Done,
     /*  353351 */ // Label 5285: @353351
     /*  353351 */ GIM_Try, /*On fail goto*//*Label 5286*/ GIMT_Encode4(353421), // Rule ID 25077 //
     /*  353356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  353359 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353362 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353369 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353378 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353389 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  353392 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353409 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353412 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353415 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353419 */   GIR_RootConstrainSelectedInstOperands,
     /*  353420 */   // GIR_Coverage, 25077,
     /*  353420 */   GIR_EraseRootFromParent_Done,
     /*  353421 */ // Label 5286: @353421
     /*  353421 */ GIM_Try, /*On fail goto*//*Label 5287*/ GIMT_Encode4(353491), // Rule ID 25078 //
     /*  353426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  353429 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353432 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353439 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353459 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  353462 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353479 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353482 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353485 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353489 */   GIR_RootConstrainSelectedInstOperands,
     /*  353490 */   // GIR_Coverage, 25078,
     /*  353490 */   GIR_EraseRootFromParent_Done,
     /*  353491 */ // Label 5287: @353491
     /*  353491 */ GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(353561), // Rule ID 25079 //
     /*  353496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  353499 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353502 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353522 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353529 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  353532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353549 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353552 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353555 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353559 */   GIR_RootConstrainSelectedInstOperands,
     /*  353560 */   // GIR_Coverage, 25079,
     /*  353560 */   GIR_EraseRootFromParent_Done,
     /*  353561 */ // Label 5288: @353561
     /*  353561 */ GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(353631), // Rule ID 25080 //
     /*  353566 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  353569 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353572 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353584 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353588 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353592 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353599 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  353602 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353625 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353629 */   GIR_RootConstrainSelectedInstOperands,
     /*  353630 */   // GIR_Coverage, 25080,
     /*  353630 */   GIR_EraseRootFromParent_Done,
     /*  353631 */ // Label 5289: @353631
     /*  353631 */ GIM_Try, /*On fail goto*//*Label 5290*/ GIMT_Encode4(353701), // Rule ID 25086 //
     /*  353636 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  353639 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353642 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353658 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353662 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353669 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353669 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  353672 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353689 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353692 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353695 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353699 */   GIR_RootConstrainSelectedInstOperands,
     /*  353700 */   // GIR_Coverage, 25086,
     /*  353700 */   GIR_EraseRootFromParent_Done,
     /*  353701 */ // Label 5290: @353701
     /*  353701 */ GIM_Try, /*On fail goto*//*Label 5291*/ GIMT_Encode4(353771), // Rule ID 25087 //
     /*  353706 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  353709 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353712 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353719 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353732 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353739 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  353742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353759 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353762 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353765 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353769 */   GIR_RootConstrainSelectedInstOperands,
     /*  353770 */   // GIR_Coverage, 25087,
     /*  353770 */   GIR_EraseRootFromParent_Done,
     /*  353771 */ // Label 5291: @353771
     /*  353771 */ GIM_Try, /*On fail goto*//*Label 5292*/ GIMT_Encode4(353841), // Rule ID 25088 //
     /*  353776 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  353779 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353782 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353789 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353798 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353802 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353809 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353809 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  353812 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353839 */   GIR_RootConstrainSelectedInstOperands,
     /*  353840 */   // GIR_Coverage, 25088,
     /*  353840 */   GIR_EraseRootFromParent_Done,
     /*  353841 */ // Label 5292: @353841
     /*  353841 */ GIM_Try, /*On fail goto*//*Label 5293*/ GIMT_Encode4(353911), // Rule ID 25089 //
     /*  353846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  353849 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353852 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353859 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353864 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353879 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  353882 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353899 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353902 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353905 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353909 */   GIR_RootConstrainSelectedInstOperands,
     /*  353910 */   // GIR_Coverage, 25089,
     /*  353910 */   GIR_EraseRootFromParent_Done,
     /*  353911 */ // Label 5293: @353911
     /*  353911 */ GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(353981), // Rule ID 25090 //
     /*  353916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  353919 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353922 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  353934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  353938 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  353942 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  353949 */   // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  353949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  353952 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  353954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  353959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  353964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  353969 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353972 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  353975 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  353979 */   GIR_RootConstrainSelectedInstOperands,
     /*  353980 */   // GIR_Coverage, 25090,
     /*  353980 */   GIR_EraseRootFromParent_Done,
     /*  353981 */ // Label 5294: @353981
     /*  353981 */ GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(354050), // Rule ID 13945 //
     /*  353986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  353989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  353992 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  353999 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354004 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354008 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354012 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354019 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  354019 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354022 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354048 */   GIR_RootConstrainSelectedInstOperands,
     /*  354049 */   // GIR_Coverage, 13945,
     /*  354049 */   GIR_EraseRootFromParent_Done,
     /*  354050 */ // Label 5295: @354050
     /*  354050 */ GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(354119), // Rule ID 13946 //
     /*  354055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  354058 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354061 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354077 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354088 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  354088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354091 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354117 */   GIR_RootConstrainSelectedInstOperands,
     /*  354118 */   // GIR_Coverage, 13946,
     /*  354118 */   GIR_EraseRootFromParent_Done,
     /*  354119 */ // Label 5296: @354119
     /*  354119 */ GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(354188), // Rule ID 13947 //
     /*  354124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  354127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354142 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354146 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354150 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354157 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  354157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354182 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354186 */   GIR_RootConstrainSelectedInstOperands,
     /*  354187 */   // GIR_Coverage, 13947,
     /*  354187 */   GIR_EraseRootFromParent_Done,
     /*  354188 */ // Label 5297: @354188
     /*  354188 */ GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(354257), // Rule ID 13948 //
     /*  354193 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  354196 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354199 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354206 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354211 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354215 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354219 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354226 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  354226 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354229 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354251 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354255 */   GIR_RootConstrainSelectedInstOperands,
     /*  354256 */   // GIR_Coverage, 13948,
     /*  354256 */   GIR_EraseRootFromParent_Done,
     /*  354257 */ // Label 5298: @354257
     /*  354257 */ GIM_Try, /*On fail goto*//*Label 5299*/ GIMT_Encode4(354326), // Rule ID 13949 //
     /*  354262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  354265 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354268 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354275 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354284 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354288 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354295 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  354295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354298 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354320 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354324 */   GIR_RootConstrainSelectedInstOperands,
     /*  354325 */   // GIR_Coverage, 13949,
     /*  354325 */   GIR_EraseRootFromParent_Done,
     /*  354326 */ // Label 5299: @354326
     /*  354326 */ GIM_Try, /*On fail goto*//*Label 5300*/ GIMT_Encode4(354425), // Rule ID 14005 //
     /*  354331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode0),
     /*  354334 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354337 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354344 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354353 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354357 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354364 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  354364 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  354367 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354371 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  354376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354396 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354400 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  354402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  354405 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  354407 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  354414 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354419 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354424 */   // GIR_Coverage, 14005,
     /*  354424 */   GIR_EraseRootFromParent_Done,
     /*  354425 */ // Label 5300: @354425
     /*  354425 */ GIM_Try, /*On fail goto*//*Label 5301*/ GIMT_Encode4(354524), // Rule ID 14006 //
     /*  354430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode1),
     /*  354433 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354436 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354448 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354452 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354456 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354463 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  354463 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  354466 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354470 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  354475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354495 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354499 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  354501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  354504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  354506 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  354513 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354518 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354523 */   // GIR_Coverage, 14006,
     /*  354523 */   GIR_EraseRootFromParent_Done,
     /*  354524 */ // Label 5301: @354524
     /*  354524 */ GIM_Try, /*On fail goto*//*Label 5302*/ GIMT_Encode4(354623), // Rule ID 14007 //
     /*  354529 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode2),
     /*  354532 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354535 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354542 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354547 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354551 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354555 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354562 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  354562 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  354565 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354569 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  354574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354594 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354598 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  354600 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  354603 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  354605 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  354612 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354617 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354622 */   // GIR_Coverage, 14007,
     /*  354622 */   GIR_EraseRootFromParent_Done,
     /*  354623 */ // Label 5302: @354623
     /*  354623 */ GIM_Try, /*On fail goto*//*Label 5303*/ GIMT_Encode4(354722), // Rule ID 14008 //
     /*  354628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode3),
     /*  354631 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354634 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354641 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354650 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354654 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354661 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  354661 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  354664 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354668 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  354673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354693 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354697 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  354699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  354702 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  354704 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  354711 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354716 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354721 */   // GIR_Coverage, 14008,
     /*  354721 */   GIR_EraseRootFromParent_Done,
     /*  354722 */ // Label 5303: @354722
     /*  354722 */ GIM_Try, /*On fail goto*//*Label 5304*/ GIMT_Encode4(354821), // Rule ID 14009 //
     /*  354727 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseTrue16WithSramECC_HwMode4),
     /*  354730 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354733 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354740 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354749 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354753 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354760 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  354760 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  354763 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  354767 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  354772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354792 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354796 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  354798 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  354801 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  354803 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  354810 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354815 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354820 */   // GIR_Coverage, 14009,
     /*  354820 */   GIR_EraseRootFromParent_Done,
     /*  354821 */ // Label 5304: @354821
     /*  354821 */ GIM_Try, /*On fail goto*//*Label 5305*/ GIMT_Encode4(354890), // Rule ID 14042 //
     /*  354826 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatScratchSVSMode_UseRealTrue16Insts),
     /*  354829 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354832 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354839 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354844 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  354848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354852 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  354859 */   // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_D16_SVS_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  354859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_D16_SVS_t16),
     /*  354862 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  354869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  354874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  354879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  354884 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354888 */   GIR_RootConstrainSelectedInstOperands,
     /*  354889 */   // GIR_Coverage, 14042,
     /*  354889 */   GIR_EraseRootFromParent_Done,
     /*  354890 */ // Label 5305: @354890
     /*  354890 */ GIM_Try, /*On fail goto*//*Label 5306*/ GIMT_Encode4(354952), // Rule ID 13940 //
     /*  354895 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  354898 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354901 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354908 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  354928 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  354928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  354931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  354938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  354943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  354946 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  354950 */   GIR_RootConstrainSelectedInstOperands,
     /*  354951 */   // GIR_Coverage, 13940,
     /*  354951 */   GIR_EraseRootFromParent_Done,
     /*  354952 */ // Label 5306: @354952
     /*  354952 */ GIM_Try, /*On fail goto*//*Label 5307*/ GIMT_Encode4(355014), // Rule ID 13941 //
     /*  354957 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  354960 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  354963 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  354970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  354975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  354979 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  354983 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  354990 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  354990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  354993 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  354995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355005 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355008 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355012 */   GIR_RootConstrainSelectedInstOperands,
     /*  355013 */   // GIR_Coverage, 13941,
     /*  355013 */   GIR_EraseRootFromParent_Done,
     /*  355014 */ // Label 5307: @355014
     /*  355014 */ GIM_Try, /*On fail goto*//*Label 5308*/ GIMT_Encode4(355076), // Rule ID 13942 //
     /*  355019 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  355022 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355025 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355032 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355037 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355041 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355045 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355052 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  355052 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355055 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355070 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355074 */   GIR_RootConstrainSelectedInstOperands,
     /*  355075 */   // GIR_Coverage, 13942,
     /*  355075 */   GIR_EraseRootFromParent_Done,
     /*  355076 */ // Label 5308: @355076
     /*  355076 */ GIM_Try, /*On fail goto*//*Label 5309*/ GIMT_Encode4(355138), // Rule ID 13943 //
     /*  355081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  355084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355087 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355103 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355107 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355114 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  355114 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355117 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355132 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355136 */   GIR_RootConstrainSelectedInstOperands,
     /*  355137 */   // GIR_Coverage, 13943,
     /*  355137 */   GIR_EraseRootFromParent_Done,
     /*  355138 */ // Label 5309: @355138
     /*  355138 */ GIM_Try, /*On fail goto*//*Label 5310*/ GIMT_Encode4(355200), // Rule ID 13944 //
     /*  355143 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  355146 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355149 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355156 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355176 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  355176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355179 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355194 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355198 */   GIR_RootConstrainSelectedInstOperands,
     /*  355199 */   // GIR_Coverage, 13944,
     /*  355199 */   GIR_EraseRootFromParent_Done,
     /*  355200 */ // Label 5310: @355200
     /*  355200 */ GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(355292), // Rule ID 14000 //
     /*  355205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  355208 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355211 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355223 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355227 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355231 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355238 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  355238 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  355241 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355245 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  355250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355260 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  355263 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355267 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  355269 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  355272 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  355274 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  355281 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355286 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355291 */   // GIR_Coverage, 14000,
     /*  355291 */   GIR_EraseRootFromParent_Done,
     /*  355292 */ // Label 5311: @355292
     /*  355292 */ GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(355384), // Rule ID 14001 //
     /*  355297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  355300 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355303 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355310 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355319 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355323 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355330 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  355330 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  355333 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355337 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  355342 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355352 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  355355 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355359 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  355361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  355364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  355366 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  355373 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355378 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355383 */   // GIR_Coverage, 14001,
     /*  355383 */   GIR_EraseRootFromParent_Done,
     /*  355384 */ // Label 5312: @355384
     /*  355384 */ GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(355476), // Rule ID 14002 //
     /*  355389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  355392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355395 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355402 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355422 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  355422 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  355425 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355429 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  355434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355444 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  355447 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355451 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  355453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  355456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  355458 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  355465 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355470 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355475 */   // GIR_Coverage, 14002,
     /*  355475 */   GIR_EraseRootFromParent_Done,
     /*  355476 */ // Label 5313: @355476
     /*  355476 */ GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(355568), // Rule ID 14003 //
     /*  355481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  355484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355487 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355494 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355514 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  355514 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  355517 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355521 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  355526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355536 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  355539 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355543 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  355545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  355548 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  355550 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  355557 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355562 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355567 */   // GIR_Coverage, 14003,
     /*  355567 */   GIR_EraseRootFromParent_Done,
     /*  355568 */ // Label 5314: @355568
     /*  355568 */ GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(355660), // Rule ID 14004 //
     /*  355573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  355576 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355579 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355586 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355606 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  355606 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  355609 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  355613 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  355618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355628 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  355631 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355635 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  355637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  355640 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  355642 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  355649 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355654 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355659 */   // GIR_Coverage, 14004,
     /*  355659 */   GIR_EraseRootFromParent_Done,
     /*  355660 */ // Label 5315: @355660
     /*  355660 */ GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(355722), // Rule ID 14041 //
     /*  355665 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  355668 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355671 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355678 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355683 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  355687 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355691 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  355698 */   // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  355698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_t16),
     /*  355701 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  355708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355713 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355716 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355720 */   GIR_RootConstrainSelectedInstOperands,
     /*  355721 */   // GIR_Coverage, 14041,
     /*  355721 */   GIR_EraseRootFromParent_Done,
     /*  355722 */ // Label 5316: @355722
     /*  355722 */ GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(355784), // Rule ID 13935 //
     /*  355727 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  355730 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355733 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355740 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355749 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355753 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  355760 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  355760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  355763 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  355770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355775 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355778 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355782 */   GIR_RootConstrainSelectedInstOperands,
     /*  355783 */   // GIR_Coverage, 13935,
     /*  355783 */   GIR_EraseRootFromParent_Done,
     /*  355784 */ // Label 5317: @355784
     /*  355784 */ GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(355846), // Rule ID 13936 //
     /*  355789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  355792 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355795 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355811 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355815 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  355822 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  355822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  355825 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  355832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355837 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355840 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355844 */   GIR_RootConstrainSelectedInstOperands,
     /*  355845 */   // GIR_Coverage, 13936,
     /*  355845 */   GIR_EraseRootFromParent_Done,
     /*  355846 */ // Label 5318: @355846
     /*  355846 */ GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(355908), // Rule ID 13937 //
     /*  355851 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  355854 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355857 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355877 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  355884 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  355884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  355887 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  355894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355899 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355902 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355906 */   GIR_RootConstrainSelectedInstOperands,
     /*  355907 */   // GIR_Coverage, 13937,
     /*  355907 */   GIR_EraseRootFromParent_Done,
     /*  355908 */ // Label 5319: @355908
     /*  355908 */ GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(355970), // Rule ID 13938 //
     /*  355913 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  355916 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355919 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355926 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355935 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  355939 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  355946 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  355946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  355949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  355951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  355956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  355961 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  355964 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  355968 */   GIR_RootConstrainSelectedInstOperands,
     /*  355969 */   // GIR_Coverage, 13938,
     /*  355969 */   GIR_EraseRootFromParent_Done,
     /*  355970 */ // Label 5320: @355970
     /*  355970 */ GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(356032), // Rule ID 13939 //
     /*  355975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  355978 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  355981 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  355988 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  355993 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  355997 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356001 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356008 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  356008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  356011 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  356013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356023 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356026 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356030 */   GIR_RootConstrainSelectedInstOperands,
     /*  356031 */   // GIR_Coverage, 13939,
     /*  356031 */   GIR_EraseRootFromParent_Done,
     /*  356032 */ // Label 5321: @356032
     /*  356032 */ GIM_Try, /*On fail goto*//*Label 5322*/ GIMT_Encode4(356124), // Rule ID 13995 //
     /*  356037 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode0),
     /*  356040 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  356043 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356050 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  356055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356059 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356063 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356070 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  356070 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  356073 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  356077 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  356082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356092 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  356095 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356099 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  356101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  356104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  356106 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  356113 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356118 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356123 */   // GIR_Coverage, 13995,
     /*  356123 */   GIR_EraseRootFromParent_Done,
     /*  356124 */ // Label 5322: @356124
     /*  356124 */ GIM_Try, /*On fail goto*//*Label 5323*/ GIMT_Encode4(356216), // Rule ID 13996 //
     /*  356129 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode1),
     /*  356132 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  356135 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356142 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  356147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356151 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356155 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356162 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  356162 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  356165 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  356169 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  356174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356184 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  356187 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356191 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  356193 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  356196 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  356198 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  356205 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356210 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356215 */   // GIR_Coverage, 13996,
     /*  356215 */   GIR_EraseRootFromParent_Done,
     /*  356216 */ // Label 5323: @356216
     /*  356216 */ GIM_Try, /*On fail goto*//*Label 5324*/ GIMT_Encode4(356308), // Rule ID 13997 //
     /*  356221 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode2),
     /*  356224 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  356227 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  356239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356254 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  356254 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  356257 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  356261 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  356266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356276 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  356279 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356283 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  356285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  356288 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  356290 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  356297 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356302 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356307 */   // GIR_Coverage, 13997,
     /*  356307 */   GIR_EraseRootFromParent_Done,
     /*  356308 */ // Label 5324: @356308
     /*  356308 */ GIM_Try, /*On fail goto*//*Label 5325*/ GIMT_Encode4(356400), // Rule ID 13998 //
     /*  356313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode3),
     /*  356316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  356319 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356326 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  356331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356335 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356339 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356346 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  356346 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  356349 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  356353 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  356358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356368 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  356371 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356375 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  356377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  356380 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  356382 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  356389 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356394 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356399 */   // GIR_Coverage, 13998,
     /*  356399 */   GIR_EraseRootFromParent_Done,
     /*  356400 */ // Label 5325: @356400
     /*  356400 */ GIM_Try, /*On fail goto*//*Label 5326*/ GIMT_Encode4(356492), // Rule ID 13999 //
     /*  356405 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseTrue16WithSramECC_HwMode4),
     /*  356408 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  356411 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356418 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  356423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356427 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356431 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356438 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  356438 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  356441 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  356445 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  356450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356460 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  356463 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356467 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  356469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  356472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  356474 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  356481 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356486 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356491 */   // GIR_Coverage, 13999,
     /*  356491 */   GIR_EraseRootFromParent_Done,
     /*  356492 */ // Label 5326: @356492
     /*  356492 */ GIM_Try, /*On fail goto*//*Label 5327*/ GIMT_Encode4(356554), // Rule ID 14040 //
     /*  356497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  356500 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  356503 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356510 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  356515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  356519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  356530 */   // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  356530 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_D16_t16),
     /*  356533 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  356535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  356540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  356545 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356548 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356552 */   GIR_RootConstrainSelectedInstOperands,
     /*  356553 */   // GIR_Coverage, 14040,
     /*  356553 */   GIR_EraseRootFromParent_Done,
     /*  356554 */ // Label 5327: @356554
     /*  356554 */ GIM_Try, /*On fail goto*//*Label 5328*/ GIMT_Encode4(356631), // Rule ID 15148 //
     /*  356559 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  356562 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  356565 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356572 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  356579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356583 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356587 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  356594 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  356594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  356597 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  356599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  356604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  356609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  356614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  356619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356625 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356629 */   GIR_RootConstrainSelectedInstOperands,
     /*  356630 */   // GIR_Coverage, 15148,
     /*  356630 */   GIR_EraseRootFromParent_Done,
     /*  356631 */ // Label 5328: @356631
     /*  356631 */ GIM_Try, /*On fail goto*//*Label 5329*/ GIMT_Encode4(356708), // Rule ID 15149 //
     /*  356636 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  356639 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  356642 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  356656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356660 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356664 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  356671 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  356671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  356674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  356676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  356681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  356686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  356691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  356696 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356699 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356702 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356706 */   GIR_RootConstrainSelectedInstOperands,
     /*  356707 */   // GIR_Coverage, 15149,
     /*  356707 */   GIR_EraseRootFromParent_Done,
     /*  356708 */ // Label 5329: @356708
     /*  356708 */ GIM_Try, /*On fail goto*//*Label 5330*/ GIMT_Encode4(356785), // Rule ID 15150 //
     /*  356713 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  356716 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  356719 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356726 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  356733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356737 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356741 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  356748 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  356748 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  356751 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  356753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  356758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  356763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  356768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  356773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356783 */   GIR_RootConstrainSelectedInstOperands,
     /*  356784 */   // GIR_Coverage, 15150,
     /*  356784 */   GIR_EraseRootFromParent_Done,
     /*  356785 */ // Label 5330: @356785
     /*  356785 */ GIM_Try, /*On fail goto*//*Label 5331*/ GIMT_Encode4(356862), // Rule ID 15151 //
     /*  356790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  356793 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  356796 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  356810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  356825 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  356825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  356828 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  356830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  356835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  356840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  356845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  356850 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356853 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356856 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356860 */   GIR_RootConstrainSelectedInstOperands,
     /*  356861 */   // GIR_Coverage, 15151,
     /*  356861 */   GIR_EraseRootFromParent_Done,
     /*  356862 */ // Label 5331: @356862
     /*  356862 */ GIM_Try, /*On fail goto*//*Label 5332*/ GIMT_Encode4(356939), // Rule ID 15152 //
     /*  356867 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  356870 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  356873 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356880 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  356887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356891 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356895 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  356902 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  356902 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  356905 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  356907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  356912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  356917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  356922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  356927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356930 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  356933 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  356937 */   GIR_RootConstrainSelectedInstOperands,
     /*  356938 */   // GIR_Coverage, 15152,
     /*  356938 */   GIR_EraseRootFromParent_Done,
     /*  356939 */ // Label 5332: @356939
     /*  356939 */ GIM_Try, /*On fail goto*//*Label 5333*/ GIMT_Encode4(357016), // Rule ID 15158 //
     /*  356944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  356947 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  356950 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  356957 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  356964 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  356968 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  356972 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  356979 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  356979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  356982 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  356984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  356989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  356994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  356999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357004 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357007 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357010 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357014 */   GIR_RootConstrainSelectedInstOperands,
     /*  357015 */   // GIR_Coverage, 15158,
     /*  357015 */   GIR_EraseRootFromParent_Done,
     /*  357016 */ // Label 5333: @357016
     /*  357016 */ GIM_Try, /*On fail goto*//*Label 5334*/ GIMT_Encode4(357093), // Rule ID 15159 //
     /*  357021 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  357024 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  357027 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357034 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  357041 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357045 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357049 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  357056 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  357056 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  357059 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357084 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357087 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357091 */   GIR_RootConstrainSelectedInstOperands,
     /*  357092 */   // GIR_Coverage, 15159,
     /*  357092 */   GIR_EraseRootFromParent_Done,
     /*  357093 */ // Label 5334: @357093
     /*  357093 */ GIM_Try, /*On fail goto*//*Label 5335*/ GIMT_Encode4(357170), // Rule ID 15160 //
     /*  357098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  357101 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  357104 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357111 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  357118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357122 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357126 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  357133 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  357133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  357136 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357158 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357161 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357164 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357168 */   GIR_RootConstrainSelectedInstOperands,
     /*  357169 */   // GIR_Coverage, 15160,
     /*  357169 */   GIR_EraseRootFromParent_Done,
     /*  357170 */ // Label 5335: @357170
     /*  357170 */ GIM_Try, /*On fail goto*//*Label 5336*/ GIMT_Encode4(357247), // Rule ID 15161 //
     /*  357175 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  357178 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  357181 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357188 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  357195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357199 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357203 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  357210 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  357210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  357213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357241 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357245 */   GIR_RootConstrainSelectedInstOperands,
     /*  357246 */   // GIR_Coverage, 15161,
     /*  357246 */   GIR_EraseRootFromParent_Done,
     /*  357247 */ // Label 5336: @357247
     /*  357247 */ GIM_Try, /*On fail goto*//*Label 5337*/ GIMT_Encode4(357324), // Rule ID 15162 //
     /*  357252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  357255 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  357258 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357265 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  357272 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357276 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357280 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  357287 */   // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  357287 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  357290 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357322 */   GIR_RootConstrainSelectedInstOperands,
     /*  357323 */   // GIR_Coverage, 15162,
     /*  357323 */   GIR_EraseRootFromParent_Done,
     /*  357324 */ // Label 5337: @357324
     /*  357324 */ GIM_Try, /*On fail goto*//*Label 5338*/ GIMT_Encode4(357399), // Rule ID 25071 //
     /*  357329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  357332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357335 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357342 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357362 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  357365 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357390 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357397 */   GIR_RootConstrainSelectedInstOperands,
     /*  357398 */   // GIR_Coverage, 25071,
     /*  357398 */   GIR_EraseRootFromParent_Done,
     /*  357399 */ // Label 5338: @357399
     /*  357399 */ GIM_Try, /*On fail goto*//*Label 5339*/ GIMT_Encode4(357474), // Rule ID 25072 //
     /*  357404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  357407 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357410 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357426 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357430 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357437 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  357440 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357442 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357462 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357465 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357468 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357472 */   GIR_RootConstrainSelectedInstOperands,
     /*  357473 */   // GIR_Coverage, 25072,
     /*  357473 */   GIR_EraseRootFromParent_Done,
     /*  357474 */ // Label 5339: @357474
     /*  357474 */ GIM_Try, /*On fail goto*//*Label 5340*/ GIMT_Encode4(357549), // Rule ID 25073 //
     /*  357479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  357482 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357485 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357512 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  357515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357537 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357547 */   GIR_RootConstrainSelectedInstOperands,
     /*  357548 */   // GIR_Coverage, 25073,
     /*  357548 */   GIR_EraseRootFromParent_Done,
     /*  357549 */ // Label 5340: @357549
     /*  357549 */ GIM_Try, /*On fail goto*//*Label 5341*/ GIMT_Encode4(357624), // Rule ID 25074 //
     /*  357554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  357557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357560 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357567 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357576 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357580 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357587 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  357590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357615 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357618 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357622 */   GIR_RootConstrainSelectedInstOperands,
     /*  357623 */   // GIR_Coverage, 25074,
     /*  357623 */   GIR_EraseRootFromParent_Done,
     /*  357624 */ // Label 5341: @357624
     /*  357624 */ GIM_Try, /*On fail goto*//*Label 5342*/ GIMT_Encode4(357699), // Rule ID 25075 //
     /*  357629 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  357632 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357635 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357642 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357651 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357655 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357662 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357662 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  357665 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357687 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357690 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357693 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357697 */   GIR_RootConstrainSelectedInstOperands,
     /*  357698 */   // GIR_Coverage, 25075,
     /*  357698 */   GIR_EraseRootFromParent_Done,
     /*  357699 */ // Label 5342: @357699
     /*  357699 */ GIM_Try, /*On fail goto*//*Label 5343*/ GIMT_Encode4(357774), // Rule ID 25081 //
     /*  357704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  357707 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357710 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357717 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357722 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357726 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357730 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357737 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357737 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  357740 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357757 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357762 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357765 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357768 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357772 */   GIR_RootConstrainSelectedInstOperands,
     /*  357773 */   // GIR_Coverage, 25081,
     /*  357773 */   GIR_EraseRootFromParent_Done,
     /*  357774 */ // Label 5343: @357774
     /*  357774 */ GIM_Try, /*On fail goto*//*Label 5344*/ GIMT_Encode4(357849), // Rule ID 25082 //
     /*  357779 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  357782 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357785 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357792 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357801 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357812 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357812 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  357815 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357837 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357843 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357847 */   GIR_RootConstrainSelectedInstOperands,
     /*  357848 */   // GIR_Coverage, 25082,
     /*  357848 */   GIR_EraseRootFromParent_Done,
     /*  357849 */ // Label 5344: @357849
     /*  357849 */ GIM_Try, /*On fail goto*//*Label 5345*/ GIMT_Encode4(357924), // Rule ID 25083 //
     /*  357854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  357857 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357860 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357867 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357887 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  357890 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357912 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357915 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357918 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357922 */   GIR_RootConstrainSelectedInstOperands,
     /*  357923 */   // GIR_Coverage, 25083,
     /*  357923 */   GIR_EraseRootFromParent_Done,
     /*  357924 */ // Label 5345: @357924
     /*  357924 */ GIM_Try, /*On fail goto*//*Label 5346*/ GIMT_Encode4(357999), // Rule ID 25084 //
     /*  357929 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  357932 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  357935 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  357942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  357947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  357951 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  357955 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  357962 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  357962 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  357965 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  357967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  357972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  357977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  357982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  357987 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357990 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  357993 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  357997 */   GIR_RootConstrainSelectedInstOperands,
     /*  357998 */   // GIR_Coverage, 25084,
     /*  357998 */   GIR_EraseRootFromParent_Done,
     /*  357999 */ // Label 5346: @357999
     /*  357999 */ GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(358074), // Rule ID 25085 //
     /*  358004 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  358007 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  358010 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358017 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  358022 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358026 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358030 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  358037 */   // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  358037 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  358040 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  358047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  358057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  358062 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358065 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358068 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358072 */   GIR_RootConstrainSelectedInstOperands,
     /*  358073 */   // GIR_Coverage, 25085,
     /*  358073 */   GIR_EraseRootFromParent_Done,
     /*  358074 */ // Label 5347: @358074
     /*  358074 */ GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(358146), // Rule ID 15143 //
     /*  358079 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  358082 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358085 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358092 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358103 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358107 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358114 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358114 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358117 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358140 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358144 */   GIR_RootConstrainSelectedInstOperands,
     /*  358145 */   // GIR_Coverage, 15143,
     /*  358145 */   GIR_EraseRootFromParent_Done,
     /*  358146 */ // Label 5348: @358146
     /*  358146 */ GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(358218), // Rule ID 15144 //
     /*  358151 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  358154 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358157 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358164 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358175 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358179 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358186 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358186 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358189 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358206 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358216 */   GIR_RootConstrainSelectedInstOperands,
     /*  358217 */   // GIR_Coverage, 15144,
     /*  358217 */   GIR_EraseRootFromParent_Done,
     /*  358218 */ // Label 5349: @358218
     /*  358218 */ GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(358290), // Rule ID 15145 //
     /*  358223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  358226 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358229 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358258 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358261 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358278 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358284 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358288 */   GIR_RootConstrainSelectedInstOperands,
     /*  358289 */   // GIR_Coverage, 15145,
     /*  358289 */   GIR_EraseRootFromParent_Done,
     /*  358290 */ // Label 5350: @358290
     /*  358290 */ GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(358362), // Rule ID 15146 //
     /*  358295 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  358298 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358301 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358308 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358319 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358323 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358330 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358330 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358333 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358350 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358356 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358360 */   GIR_RootConstrainSelectedInstOperands,
     /*  358361 */   // GIR_Coverage, 15146,
     /*  358361 */   GIR_EraseRootFromParent_Done,
     /*  358362 */ // Label 5351: @358362
     /*  358362 */ GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(358434), // Rule ID 15147 //
     /*  358367 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  358370 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358373 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358380 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358391 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358395 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358402 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358405 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358425 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358428 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358432 */   GIR_RootConstrainSelectedInstOperands,
     /*  358433 */   // GIR_Coverage, 15147,
     /*  358433 */   GIR_EraseRootFromParent_Done,
     /*  358434 */ // Label 5352: @358434
     /*  358434 */ GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(358506), // Rule ID 15153 //
     /*  358439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  358442 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358445 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358452 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358463 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358467 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358474 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358474 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  358477 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358497 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358500 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358504 */   GIR_RootConstrainSelectedInstOperands,
     /*  358505 */   // GIR_Coverage, 15153,
     /*  358505 */   GIR_EraseRootFromParent_Done,
     /*  358506 */ // Label 5353: @358506
     /*  358506 */ GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(358578), // Rule ID 15154 //
     /*  358511 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  358514 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358517 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358524 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358535 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358539 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358546 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  358549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358576 */   GIR_RootConstrainSelectedInstOperands,
     /*  358577 */   // GIR_Coverage, 15154,
     /*  358577 */   GIR_EraseRootFromParent_Done,
     /*  358578 */ // Label 5354: @358578
     /*  358578 */ GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(358650), // Rule ID 15155 //
     /*  358583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  358586 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358589 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358596 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358607 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358611 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358618 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  358621 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358641 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358648 */   GIR_RootConstrainSelectedInstOperands,
     /*  358649 */   // GIR_Coverage, 15155,
     /*  358649 */   GIR_EraseRootFromParent_Done,
     /*  358650 */ // Label 5355: @358650
     /*  358650 */ GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(358722), // Rule ID 15156 //
     /*  358655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  358658 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358661 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358668 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358679 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358683 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358690 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  358693 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358710 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358713 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358716 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358720 */   GIR_RootConstrainSelectedInstOperands,
     /*  358721 */   // GIR_Coverage, 15156,
     /*  358721 */   GIR_EraseRootFromParent_Done,
     /*  358722 */ // Label 5356: @358722
     /*  358722 */ GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(358794), // Rule ID 15157 //
     /*  358727 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  358730 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  358733 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358740 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358751 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358755 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358762 */   // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  358762 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  358765 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358792 */   GIR_RootConstrainSelectedInstOperands,
     /*  358793 */   // GIR_Coverage, 15157,
     /*  358793 */   GIR_EraseRootFromParent_Done,
     /*  358794 */ // Label 5357: @358794
     /*  358794 */ GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(358865), // Rule ID 24911 //
     /*  358799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  358802 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  358805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358818 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358826 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358833 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  358833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358836 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358853 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358856 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358859 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358863 */   GIR_RootConstrainSelectedInstOperands,
     /*  358864 */   // GIR_Coverage, 24911,
     /*  358864 */   GIR_EraseRootFromParent_Done,
     /*  358865 */ // Label 5358: @358865
     /*  358865 */ GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(358936), // Rule ID 24912 //
     /*  358870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  358873 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  358876 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358897 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358904 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  358904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358907 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  358934 */   GIR_RootConstrainSelectedInstOperands,
     /*  358935 */   // GIR_Coverage, 24912,
     /*  358935 */   GIR_EraseRootFromParent_Done,
     /*  358936 */ // Label 5359: @358936
     /*  358936 */ GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(359007), // Rule ID 24913 //
     /*  358941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  358944 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  358947 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  358954 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  358960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  358964 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  358968 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  358975 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  358975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  358978 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  358980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  358985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  358990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  358995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  358998 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359001 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359005 */   GIR_RootConstrainSelectedInstOperands,
     /*  359006 */   // GIR_Coverage, 24913,
     /*  359006 */   GIR_EraseRootFromParent_Done,
     /*  359007 */ // Label 5360: @359007
     /*  359007 */ GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(359078), // Rule ID 24914 //
     /*  359012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  359015 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359018 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359025 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359046 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359066 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359069 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359072 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359076 */   GIR_RootConstrainSelectedInstOperands,
     /*  359077 */   // GIR_Coverage, 24914,
     /*  359077 */   GIR_EraseRootFromParent_Done,
     /*  359078 */ // Label 5361: @359078
     /*  359078 */ GIM_Try, /*On fail goto*//*Label 5362*/ GIMT_Encode4(359149), // Rule ID 24915 //
     /*  359083 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  359086 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359089 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359096 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359106 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359110 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359117 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359143 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359147 */   GIR_RootConstrainSelectedInstOperands,
     /*  359148 */   // GIR_Coverage, 24915,
     /*  359148 */   GIR_EraseRootFromParent_Done,
     /*  359149 */ // Label 5362: @359149
     /*  359149 */ GIM_Try, /*On fail goto*//*Label 5363*/ GIMT_Encode4(359220), // Rule ID 24916 //
     /*  359154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  359157 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359160 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359173 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359177 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359181 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359188 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359188 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359191 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359208 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359214 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359218 */   GIR_RootConstrainSelectedInstOperands,
     /*  359219 */   // GIR_Coverage, 24916,
     /*  359219 */   GIR_EraseRootFromParent_Done,
     /*  359220 */ // Label 5363: @359220
     /*  359220 */ GIM_Try, /*On fail goto*//*Label 5364*/ GIMT_Encode4(359291), // Rule ID 24917 //
     /*  359225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  359228 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359231 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359238 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359252 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359259 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359262 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359279 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359282 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359285 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359289 */   GIR_RootConstrainSelectedInstOperands,
     /*  359290 */   // GIR_Coverage, 24917,
     /*  359290 */   GIR_EraseRootFromParent_Done,
     /*  359291 */ // Label 5364: @359291
     /*  359291 */ GIM_Try, /*On fail goto*//*Label 5365*/ GIMT_Encode4(359362), // Rule ID 24918 //
     /*  359296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  359299 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359302 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359309 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359319 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359323 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359330 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359330 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359333 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359350 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359356 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359360 */   GIR_RootConstrainSelectedInstOperands,
     /*  359361 */   // GIR_Coverage, 24918,
     /*  359361 */   GIR_EraseRootFromParent_Done,
     /*  359362 */ // Label 5365: @359362
     /*  359362 */ GIM_Try, /*On fail goto*//*Label 5366*/ GIMT_Encode4(359433), // Rule ID 24919 //
     /*  359367 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  359370 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359373 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359380 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359390 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359394 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359401 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359401 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359404 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359421 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359427 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359431 */   GIR_RootConstrainSelectedInstOperands,
     /*  359432 */   // GIR_Coverage, 24919,
     /*  359432 */   GIR_EraseRootFromParent_Done,
     /*  359433 */ // Label 5366: @359433
     /*  359433 */ GIM_Try, /*On fail goto*//*Label 5367*/ GIMT_Encode4(359504), // Rule ID 24920 //
     /*  359438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  359441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359444 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359451 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359472 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359495 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359498 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359502 */   GIR_RootConstrainSelectedInstOperands,
     /*  359503 */   // GIR_Coverage, 24920,
     /*  359503 */   GIR_EraseRootFromParent_Done,
     /*  359504 */ // Label 5367: @359504
     /*  359504 */ GIM_Try, /*On fail goto*//*Label 5368*/ GIMT_Encode4(359576), // Rule ID 24941 //
     /*  359509 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  359512 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359515 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359522 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359537 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359544 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359564 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359567 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359570 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359574 */   GIR_RootConstrainSelectedInstOperands,
     /*  359575 */   // GIR_Coverage, 24941,
     /*  359575 */   GIR_EraseRootFromParent_Done,
     /*  359576 */ // Label 5368: @359576
     /*  359576 */ GIM_Try, /*On fail goto*//*Label 5369*/ GIMT_Encode4(359648), // Rule ID 24942 //
     /*  359581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  359584 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359587 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359594 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359605 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359609 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359616 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359616 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359619 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359636 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359639 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359642 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359646 */   GIR_RootConstrainSelectedInstOperands,
     /*  359647 */   // GIR_Coverage, 24942,
     /*  359647 */   GIR_EraseRootFromParent_Done,
     /*  359648 */ // Label 5369: @359648
     /*  359648 */ GIM_Try, /*On fail goto*//*Label 5370*/ GIMT_Encode4(359720), // Rule ID 24943 //
     /*  359653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  359656 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359659 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359666 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359677 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359681 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359688 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359688 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359691 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359714 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359718 */   GIR_RootConstrainSelectedInstOperands,
     /*  359719 */   // GIR_Coverage, 24943,
     /*  359719 */   GIR_EraseRootFromParent_Done,
     /*  359720 */ // Label 5370: @359720
     /*  359720 */ GIM_Try, /*On fail goto*//*Label 5371*/ GIMT_Encode4(359792), // Rule ID 24944 //
     /*  359725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  359728 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359738 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359749 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359753 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359760 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359763 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359783 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359786 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359790 */   GIR_RootConstrainSelectedInstOperands,
     /*  359791 */   // GIR_Coverage, 24944,
     /*  359791 */   GIR_EraseRootFromParent_Done,
     /*  359792 */ // Label 5371: @359792
     /*  359792 */ GIM_Try, /*On fail goto*//*Label 5372*/ GIMT_Encode4(359864), // Rule ID 24945 //
     /*  359797 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  359800 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359803 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359810 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359832 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  359835 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359855 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359858 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359862 */   GIR_RootConstrainSelectedInstOperands,
     /*  359863 */   // GIR_Coverage, 24945,
     /*  359863 */   GIR_EraseRootFromParent_Done,
     /*  359864 */ // Label 5372: @359864
     /*  359864 */ GIM_Try, /*On fail goto*//*Label 5373*/ GIMT_Encode4(359936), // Rule ID 24946 //
     /*  359869 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  359872 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359875 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359882 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359897 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359904 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359907 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  359934 */   GIR_RootConstrainSelectedInstOperands,
     /*  359935 */   // GIR_Coverage, 24946,
     /*  359935 */   GIR_EraseRootFromParent_Done,
     /*  359936 */ // Label 5373: @359936
     /*  359936 */ GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(360008), // Rule ID 24947 //
     /*  359941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  359944 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  359947 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  359954 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  359961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  359965 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  359969 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  359976 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  359976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  359979 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  359981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  359986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  359991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  359996 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  359999 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360002 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360006 */   GIR_RootConstrainSelectedInstOperands,
     /*  360007 */   // GIR_Coverage, 24947,
     /*  360007 */   GIR_EraseRootFromParent_Done,
     /*  360008 */ // Label 5374: @360008
     /*  360008 */ GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(360080), // Rule ID 24948 //
     /*  360013 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  360016 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360019 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  360033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360037 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360041 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  360048 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  360048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  360051 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  360053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  360058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  360063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  360068 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360074 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360078 */   GIR_RootConstrainSelectedInstOperands,
     /*  360079 */   // GIR_Coverage, 24948,
     /*  360079 */   GIR_EraseRootFromParent_Done,
     /*  360080 */ // Label 5375: @360080
     /*  360080 */ GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(360152), // Rule ID 24949 //
     /*  360085 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  360088 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360091 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360098 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  360105 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360109 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360113 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  360120 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  360120 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  360123 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  360125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  360130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  360135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  360140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360143 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360146 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360150 */   GIR_RootConstrainSelectedInstOperands,
     /*  360151 */   // GIR_Coverage, 24949,
     /*  360151 */   GIR_EraseRootFromParent_Done,
     /*  360152 */ // Label 5376: @360152
     /*  360152 */ GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(360224), // Rule ID 24950 //
     /*  360157 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  360160 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360163 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  360177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  360192 */   // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  360192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  360195 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  360197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  360202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  360207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  360212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360215 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360218 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360222 */   GIR_RootConstrainSelectedInstOperands,
     /*  360223 */   // GIR_Coverage, 24950,
     /*  360223 */   GIR_EraseRootFromParent_Done,
     /*  360224 */ // Label 5377: @360224
     /*  360224 */ GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(360286), // Rule ID 28865 //
     /*  360229 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  360232 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360235 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360242 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360251 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360255 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360262 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  360265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360277 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360280 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360284 */   GIR_RootConstrainSelectedInstOperands,
     /*  360285 */   // GIR_Coverage, 28865,
     /*  360285 */   GIR_EraseRootFromParent_Done,
     /*  360286 */ // Label 5378: @360286
     /*  360286 */ GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(360348), // Rule ID 28866 //
     /*  360291 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  360294 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360297 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360304 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360324 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  360327 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360346 */   GIR_RootConstrainSelectedInstOperands,
     /*  360347 */   // GIR_Coverage, 28866,
     /*  360347 */   GIR_EraseRootFromParent_Done,
     /*  360348 */ // Label 5379: @360348
     /*  360348 */ GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(360410), // Rule ID 28867 //
     /*  360353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  360356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360359 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360366 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360375 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360379 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360386 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360386 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  360389 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360401 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360404 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360408 */   GIR_RootConstrainSelectedInstOperands,
     /*  360409 */   // GIR_Coverage, 28867,
     /*  360409 */   GIR_EraseRootFromParent_Done,
     /*  360410 */ // Label 5380: @360410
     /*  360410 */ GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(360472), // Rule ID 28868 //
     /*  360415 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  360418 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360421 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360448 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  360451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360463 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360466 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360470 */   GIR_RootConstrainSelectedInstOperands,
     /*  360471 */   // GIR_Coverage, 28868,
     /*  360471 */   GIR_EraseRootFromParent_Done,
     /*  360472 */ // Label 5381: @360472
     /*  360472 */ GIM_Try, /*On fail goto*//*Label 5382*/ GIMT_Encode4(360534), // Rule ID 28869 //
     /*  360477 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  360480 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360483 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360490 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360499 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360503 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360510 */   // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  360513 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360532 */   GIR_RootConstrainSelectedInstOperands,
     /*  360533 */   // GIR_Coverage, 28869,
     /*  360533 */   GIR_EraseRootFromParent_Done,
     /*  360534 */ // Label 5382: @360534
     /*  360534 */ GIM_Try, /*On fail goto*//*Label 5383*/ GIMT_Encode4(360596), // Rule ID 28870 //
     /*  360539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  360542 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360545 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360552 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360572 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  360575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360587 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360594 */   GIR_RootConstrainSelectedInstOperands,
     /*  360595 */   // GIR_Coverage, 28870,
     /*  360595 */   GIR_EraseRootFromParent_Done,
     /*  360596 */ // Label 5383: @360596
     /*  360596 */ GIM_Try, /*On fail goto*//*Label 5384*/ GIMT_Encode4(360658), // Rule ID 28871 //
     /*  360601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  360604 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360607 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360614 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360634 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  360637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360656 */   GIR_RootConstrainSelectedInstOperands,
     /*  360657 */   // GIR_Coverage, 28871,
     /*  360657 */   GIR_EraseRootFromParent_Done,
     /*  360658 */ // Label 5384: @360658
     /*  360658 */ GIM_Try, /*On fail goto*//*Label 5385*/ GIMT_Encode4(360720), // Rule ID 28872 //
     /*  360663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  360666 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360669 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360676 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360696 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  360699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360714 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360718 */   GIR_RootConstrainSelectedInstOperands,
     /*  360719 */   // GIR_Coverage, 28872,
     /*  360719 */   GIR_EraseRootFromParent_Done,
     /*  360720 */ // Label 5385: @360720
     /*  360720 */ GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(360782), // Rule ID 28873 //
     /*  360725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  360728 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360738 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360747 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360751 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360758 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360758 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  360761 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360776 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360780 */   GIR_RootConstrainSelectedInstOperands,
     /*  360781 */   // GIR_Coverage, 28873,
     /*  360781 */   GIR_EraseRootFromParent_Done,
     /*  360782 */ // Label 5386: @360782
     /*  360782 */ GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(360844), // Rule ID 28874 //
     /*  360787 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  360790 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360793 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360800 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360820 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  360823 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360835 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360838 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360842 */   GIR_RootConstrainSelectedInstOperands,
     /*  360843 */   // GIR_Coverage, 28874,
     /*  360843 */   GIR_EraseRootFromParent_Done,
     /*  360844 */ // Label 5387: @360844
     /*  360844 */ GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(360906), // Rule ID 28875 //
     /*  360849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  360852 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360855 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360862 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  360871 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360875 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360882 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  360882 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_t16),
     /*  360885 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  360887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360897 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  360900 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360904 */   GIR_RootConstrainSelectedInstOperands,
     /*  360905 */   // GIR_Coverage, 28875,
     /*  360905 */   GIR_EraseRootFromParent_Done,
     /*  360906 */ // Label 5388: @360906
     /*  360906 */ GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(360998), // Rule ID 28876 //
     /*  360911 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  360914 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  360917 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  360924 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  360929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  360933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  360937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  360944 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  360944 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  360947 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  360951 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  360956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  360961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  360966 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  360969 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  360973 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  360975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  360978 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  360980 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  360987 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  360992 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  360997 */   // GIR_Coverage, 28876,
     /*  360997 */   GIR_EraseRootFromParent_Done,
     /*  360998 */ // Label 5389: @360998
     /*  360998 */ GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(361090), // Rule ID 28877 //
     /*  361003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  361006 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  361009 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361016 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361025 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361029 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361036 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  361036 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  361039 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361043 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  361048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361058 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  361061 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361065 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  361067 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  361070 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  361072 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  361079 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361084 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361089 */   // GIR_Coverage, 28877,
     /*  361089 */   GIR_EraseRootFromParent_Done,
     /*  361090 */ // Label 5390: @361090
     /*  361090 */ GIM_Try, /*On fail goto*//*Label 5391*/ GIMT_Encode4(361182), // Rule ID 28878 //
     /*  361095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  361098 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  361101 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361128 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  361128 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  361131 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361135 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  361140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361150 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  361153 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361157 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  361159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  361162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  361164 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  361171 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361176 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361181 */   // GIR_Coverage, 28878,
     /*  361181 */   GIR_EraseRootFromParent_Done,
     /*  361182 */ // Label 5391: @361182
     /*  361182 */ GIM_Try, /*On fail goto*//*Label 5392*/ GIMT_Encode4(361274), // Rule ID 28879 //
     /*  361187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  361190 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  361193 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361205 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361209 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361213 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361220 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  361220 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  361223 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361227 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  361232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361242 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  361245 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361249 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  361251 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  361254 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  361256 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  361263 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361268 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361273 */   // GIR_Coverage, 28879,
     /*  361273 */   GIR_EraseRootFromParent_Done,
     /*  361274 */ // Label 5392: @361274
     /*  361274 */ GIM_Try, /*On fail goto*//*Label 5393*/ GIMT_Encode4(361366), // Rule ID 28880 //
     /*  361279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  361282 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  361285 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361292 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361297 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361301 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361305 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361312 */   // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  361312 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  361315 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361319 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  361324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361334 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  361337 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361341 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  361343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  361346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  361348 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  361355 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  361360 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361365 */   // GIR_Coverage, 28880,
     /*  361365 */   GIR_EraseRootFromParent_Done,
     /*  361366 */ // Label 5393: @361366
     /*  361366 */ GIM_Try, /*On fail goto*//*Label 5394*/ GIMT_Encode4(361428), // Rule ID 29003 //
     /*  361371 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  361374 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361377 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361384 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361393 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361397 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361404 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  361407 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361426 */   GIR_RootConstrainSelectedInstOperands,
     /*  361427 */   // GIR_Coverage, 29003,
     /*  361427 */   GIR_EraseRootFromParent_Done,
     /*  361428 */ // Label 5394: @361428
     /*  361428 */ GIM_Try, /*On fail goto*//*Label 5395*/ GIMT_Encode4(361490), // Rule ID 29004 //
     /*  361433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  361436 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361439 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361446 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361466 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  361469 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361484 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361488 */   GIR_RootConstrainSelectedInstOperands,
     /*  361489 */   // GIR_Coverage, 29004,
     /*  361489 */   GIR_EraseRootFromParent_Done,
     /*  361490 */ // Label 5395: @361490
     /*  361490 */ GIM_Try, /*On fail goto*//*Label 5396*/ GIMT_Encode4(361552), // Rule ID 29005 //
     /*  361495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  361498 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361501 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361508 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361521 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361528 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  361531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361543 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361546 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361550 */   GIR_RootConstrainSelectedInstOperands,
     /*  361551 */   // GIR_Coverage, 29005,
     /*  361551 */   GIR_EraseRootFromParent_Done,
     /*  361552 */ // Label 5396: @361552
     /*  361552 */ GIM_Try, /*On fail goto*//*Label 5397*/ GIMT_Encode4(361614), // Rule ID 29006 //
     /*  361557 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  361560 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361563 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361570 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361575 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361579 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361583 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361590 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361590 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  361593 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361605 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361608 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361612 */   GIR_RootConstrainSelectedInstOperands,
     /*  361613 */   // GIR_Coverage, 29006,
     /*  361613 */   GIR_EraseRootFromParent_Done,
     /*  361614 */ // Label 5397: @361614
     /*  361614 */ GIM_Try, /*On fail goto*//*Label 5398*/ GIMT_Encode4(361676), // Rule ID 29007 //
     /*  361619 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  361622 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361625 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361632 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361645 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361652 */   // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361652 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  361655 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361667 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361670 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361674 */   GIR_RootConstrainSelectedInstOperands,
     /*  361675 */   // GIR_Coverage, 29007,
     /*  361675 */   GIR_EraseRootFromParent_Done,
     /*  361676 */ // Label 5398: @361676
     /*  361676 */ GIM_Try, /*On fail goto*//*Label 5399*/ GIMT_Encode4(361738), // Rule ID 29008 //
     /*  361681 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  361684 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361687 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361694 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361707 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361714 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361717 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361729 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361736 */   GIR_RootConstrainSelectedInstOperands,
     /*  361737 */   // GIR_Coverage, 29008,
     /*  361737 */   GIR_EraseRootFromParent_Done,
     /*  361738 */ // Label 5399: @361738
     /*  361738 */ GIM_Try, /*On fail goto*//*Label 5400*/ GIMT_Encode4(361800), // Rule ID 29009 //
     /*  361743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  361746 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361749 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361756 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361765 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361776 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361779 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361791 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361794 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361798 */   GIR_RootConstrainSelectedInstOperands,
     /*  361799 */   // GIR_Coverage, 29009,
     /*  361799 */   GIR_EraseRootFromParent_Done,
     /*  361800 */ // Label 5400: @361800
     /*  361800 */ GIM_Try, /*On fail goto*//*Label 5401*/ GIMT_Encode4(361862), // Rule ID 29010 //
     /*  361805 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  361808 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361811 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361818 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361823 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361831 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361838 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361841 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361853 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361856 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361860 */   GIR_RootConstrainSelectedInstOperands,
     /*  361861 */   // GIR_Coverage, 29010,
     /*  361861 */   GIR_EraseRootFromParent_Done,
     /*  361862 */ // Label 5401: @361862
     /*  361862 */ GIM_Try, /*On fail goto*//*Label 5402*/ GIMT_Encode4(361924), // Rule ID 29011 //
     /*  361867 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  361870 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361873 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361880 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361885 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361889 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361893 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361900 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361903 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361915 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361918 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361922 */   GIR_RootConstrainSelectedInstOperands,
     /*  361923 */   // GIR_Coverage, 29011,
     /*  361923 */   GIR_EraseRootFromParent_Done,
     /*  361924 */ // Label 5402: @361924
     /*  361924 */ GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(361986), // Rule ID 29012 //
     /*  361929 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  361932 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361935 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  361942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  361947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  361951 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  361955 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  361962 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  361962 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  361965 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  361967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  361972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  361977 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  361980 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  361984 */   GIR_RootConstrainSelectedInstOperands,
     /*  361985 */   // GIR_Coverage, 29012,
     /*  361985 */   GIR_EraseRootFromParent_Done,
     /*  361986 */ // Label 5403: @361986
     /*  361986 */ GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(362048), // Rule ID 29013 //
     /*  361991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  361994 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  361997 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  362009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  362024 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_t16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  362024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_t16),
     /*  362027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  362034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  362039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  362042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362046 */   GIR_RootConstrainSelectedInstOperands,
     /*  362047 */   // GIR_Coverage, 29013,
     /*  362047 */   GIR_EraseRootFromParent_Done,
     /*  362048 */ // Label 5404: @362048
     /*  362048 */ GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(362140), // Rule ID 29014 //
     /*  362053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode0),
     /*  362056 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362059 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362066 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  362071 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362075 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362079 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  362086 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  362086 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  362089 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  362093 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  362098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  362103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  362108 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  362111 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362115 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  362117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  362120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  362122 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  362129 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362134 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362139 */   // GIR_Coverage, 29014,
     /*  362139 */   GIR_EraseRootFromParent_Done,
     /*  362140 */ // Label 5405: @362140
     /*  362140 */ GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(362232), // Rule ID 29015 //
     /*  362145 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode1),
     /*  362148 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362151 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362158 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  362163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362167 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362171 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  362178 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  362178 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  362181 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  362185 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  362190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  362195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  362200 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  362203 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362207 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  362209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  362212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  362214 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  362221 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362226 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362231 */   // GIR_Coverage, 29015,
     /*  362231 */   GIR_EraseRootFromParent_Done,
     /*  362232 */ // Label 5406: @362232
     /*  362232 */ GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(362324), // Rule ID 29016 //
     /*  362237 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode2),
     /*  362240 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362243 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362250 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  362255 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362259 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362263 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  362270 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  362270 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  362273 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  362277 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  362282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  362287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  362292 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  362295 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362299 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  362301 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  362304 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  362306 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  362313 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362318 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362323 */   // GIR_Coverage, 29016,
     /*  362323 */   GIR_EraseRootFromParent_Done,
     /*  362324 */ // Label 5407: @362324
     /*  362324 */ GIM_Try, /*On fail goto*//*Label 5408*/ GIMT_Encode4(362416), // Rule ID 29017 //
     /*  362329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode3),
     /*  362332 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362335 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362342 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  362347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  362362 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  362362 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  362365 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  362369 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  362374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  362379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  362384 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  362387 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362391 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  362393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  362396 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  362398 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  362405 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362410 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362415 */   // GIR_Coverage, 29017,
     /*  362415 */   GIR_EraseRootFromParent_Done,
     /*  362416 */ // Label 5408: @362416
     /*  362416 */ GIM_Try, /*On fail goto*//*Label 5409*/ GIMT_Encode4(362508), // Rule ID 29018 //
     /*  362421 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseTrue16WithSramECC_HwMode4),
     /*  362424 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362427 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362434 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  362439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362443 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362447 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  362454 */   // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }), lo16:{ *:[i32] })
     /*  362454 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  362457 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  362461 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  362466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  362471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  362476 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  362479 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362483 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  362485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  362488 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  362490 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  362497 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  362502 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362507 */   // GIR_Coverage, 29018,
     /*  362507 */   GIR_EraseRootFromParent_Done,
     /*  362508 */ // Label 5409: @362508
     /*  362508 */ GIM_Try, /*On fail goto*//*Label 5410*/ GIMT_Encode4(362579), // Rule ID 11847 //
     /*  362513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  362516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  362519 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362526 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362537 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362541 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362548 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362573 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362577 */   GIR_RootConstrainSelectedInstOperands,
     /*  362578 */   // GIR_Coverage, 11847,
     /*  362578 */   GIR_EraseRootFromParent_Done,
     /*  362579 */ // Label 5410: @362579
     /*  362579 */ GIM_Try, /*On fail goto*//*Label 5411*/ GIMT_Encode4(362650), // Rule ID 11848 //
     /*  362584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  362587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  362590 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362597 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362608 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362612 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362619 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362619 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362622 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362648 */   GIR_RootConstrainSelectedInstOperands,
     /*  362649 */   // GIR_Coverage, 11848,
     /*  362649 */   GIR_EraseRootFromParent_Done,
     /*  362650 */ // Label 5411: @362650
     /*  362650 */ GIM_Try, /*On fail goto*//*Label 5412*/ GIMT_Encode4(362721), // Rule ID 11849 //
     /*  362655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  362658 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  362661 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362668 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362679 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362683 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362690 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362693 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362715 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362719 */   GIR_RootConstrainSelectedInstOperands,
     /*  362720 */   // GIR_Coverage, 11849,
     /*  362720 */   GIR_EraseRootFromParent_Done,
     /*  362721 */ // Label 5412: @362721
     /*  362721 */ GIM_Try, /*On fail goto*//*Label 5413*/ GIMT_Encode4(362792), // Rule ID 11850 //
     /*  362726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  362729 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  362732 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362739 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362761 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362764 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362786 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362790 */   GIR_RootConstrainSelectedInstOperands,
     /*  362791 */   // GIR_Coverage, 11850,
     /*  362791 */   GIR_EraseRootFromParent_Done,
     /*  362792 */ // Label 5413: @362792
     /*  362792 */ GIM_Try, /*On fail goto*//*Label 5414*/ GIMT_Encode4(362863), // Rule ID 11851 //
     /*  362797 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  362800 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  362803 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362810 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362817 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362832 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362835 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362861 */   GIR_RootConstrainSelectedInstOperands,
     /*  362862 */   // GIR_Coverage, 11851,
     /*  362862 */   GIR_EraseRootFromParent_Done,
     /*  362863 */ // Label 5414: @362863
     /*  362863 */ GIM_Try, /*On fail goto*//*Label 5415*/ GIMT_Encode4(362934), // Rule ID 11907 //
     /*  362868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  362871 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362874 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362892 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362896 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362903 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362928 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  362932 */   GIR_RootConstrainSelectedInstOperands,
     /*  362933 */   // GIR_Coverage, 11907,
     /*  362933 */   GIR_EraseRootFromParent_Done,
     /*  362934 */ // Label 5415: @362934
     /*  362934 */ GIM_Try, /*On fail goto*//*Label 5416*/ GIMT_Encode4(363005), // Rule ID 11908 //
     /*  362939 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  362942 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  362945 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  362952 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  362959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  362963 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  362967 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  362974 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  362974 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  362977 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  362979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  362984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  362989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  362994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  362999 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363003 */   GIR_RootConstrainSelectedInstOperands,
     /*  363004 */   // GIR_Coverage, 11908,
     /*  363004 */   GIR_EraseRootFromParent_Done,
     /*  363005 */ // Label 5416: @363005
     /*  363005 */ GIM_Try, /*On fail goto*//*Label 5417*/ GIMT_Encode4(363076), // Rule ID 11909 //
     /*  363010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  363013 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363045 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363048 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363070 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363074 */   GIR_RootConstrainSelectedInstOperands,
     /*  363075 */   // GIR_Coverage, 11909,
     /*  363075 */   GIR_EraseRootFromParent_Done,
     /*  363076 */ // Label 5417: @363076
     /*  363076 */ GIM_Try, /*On fail goto*//*Label 5418*/ GIMT_Encode4(363147), // Rule ID 11910 //
     /*  363081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  363084 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363087 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363116 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363141 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363145 */   GIR_RootConstrainSelectedInstOperands,
     /*  363146 */   // GIR_Coverage, 11910,
     /*  363146 */   GIR_EraseRootFromParent_Done,
     /*  363147 */ // Label 5418: @363147
     /*  363147 */ GIM_Try, /*On fail goto*//*Label 5419*/ GIMT_Encode4(363218), // Rule ID 11911 //
     /*  363152 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  363155 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363158 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363165 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363176 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363180 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363187 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363187 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363190 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363216 */   GIR_RootConstrainSelectedInstOperands,
     /*  363217 */   // GIR_Coverage, 11911,
     /*  363217 */   GIR_EraseRootFromParent_Done,
     /*  363218 */ // Label 5419: @363218
     /*  363218 */ GIM_Try, /*On fail goto*//*Label 5420*/ GIMT_Encode4(363289), // Rule ID 11937 //
     /*  363223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  363226 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363229 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  363236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363258 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  363261 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363283 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363287 */   GIR_RootConstrainSelectedInstOperands,
     /*  363288 */   // GIR_Coverage, 11937,
     /*  363288 */   GIR_EraseRootFromParent_Done,
     /*  363289 */ // Label 5420: @363289
     /*  363289 */ GIM_Try, /*On fail goto*//*Label 5421*/ GIMT_Encode4(363360), // Rule ID 11938 //
     /*  363294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  363297 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363300 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  363307 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363318 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363322 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363329 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  363332 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363354 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363358 */   GIR_RootConstrainSelectedInstOperands,
     /*  363359 */   // GIR_Coverage, 11938,
     /*  363359 */   GIR_EraseRootFromParent_Done,
     /*  363360 */ // Label 5421: @363360
     /*  363360 */ GIM_Try, /*On fail goto*//*Label 5422*/ GIMT_Encode4(363431), // Rule ID 11939 //
     /*  363365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  363368 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363371 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  363378 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363389 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363393 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363400 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  363403 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363429 */   GIR_RootConstrainSelectedInstOperands,
     /*  363430 */   // GIR_Coverage, 11939,
     /*  363430 */   GIR_EraseRootFromParent_Done,
     /*  363431 */ // Label 5422: @363431
     /*  363431 */ GIM_Try, /*On fail goto*//*Label 5423*/ GIMT_Encode4(363502), // Rule ID 11940 //
     /*  363436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  363439 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363442 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  363449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363471 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  363474 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363496 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363500 */   GIR_RootConstrainSelectedInstOperands,
     /*  363501 */   // GIR_Coverage, 11940,
     /*  363501 */   GIR_EraseRootFromParent_Done,
     /*  363502 */ // Label 5423: @363502
     /*  363502 */ GIM_Try, /*On fail goto*//*Label 5424*/ GIMT_Encode4(363573), // Rule ID 11941 //
     /*  363507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  363510 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  363513 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  363520 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363535 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363542 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  363542 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  363545 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  363547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363571 */   GIR_RootConstrainSelectedInstOperands,
     /*  363572 */   // GIR_Coverage, 11941,
     /*  363572 */   GIR_EraseRootFromParent_Done,
     /*  363573 */ // Label 5424: @363573
     /*  363573 */ GIM_Try, /*On fail goto*//*Label 5425*/ GIMT_Encode4(363674), // Rule ID 11947 //
     /*  363578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  363581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  363584 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363613 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  363613 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  363616 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363620 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  363625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363645 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363649 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  363651 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  363654 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  363656 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  363663 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363668 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363673 */   // GIR_Coverage, 11947,
     /*  363673 */   GIR_EraseRootFromParent_Done,
     /*  363674 */ // Label 5425: @363674
     /*  363674 */ GIM_Try, /*On fail goto*//*Label 5426*/ GIMT_Encode4(363775), // Rule ID 11948 //
     /*  363679 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  363682 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  363685 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363692 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363707 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363714 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  363714 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  363717 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363721 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  363726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363746 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363750 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  363752 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  363755 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  363757 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  363764 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363769 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363774 */   // GIR_Coverage, 11948,
     /*  363774 */   GIR_EraseRootFromParent_Done,
     /*  363775 */ // Label 5426: @363775
     /*  363775 */ GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(363876), // Rule ID 11949 //
     /*  363780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  363783 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  363786 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363793 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363808 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363815 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  363815 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  363818 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363822 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  363827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363847 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363851 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  363853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  363856 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  363858 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  363865 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363870 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363875 */   // GIR_Coverage, 11949,
     /*  363875 */   GIR_EraseRootFromParent_Done,
     /*  363876 */ // Label 5427: @363876
     /*  363876 */ GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(363977), // Rule ID 11950 //
     /*  363881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  363884 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  363887 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363894 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  363901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363905 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  363909 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  363916 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  363916 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  363919 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  363923 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  363928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  363933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  363938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  363943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  363948 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  363952 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  363954 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  363957 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  363959 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  363966 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  363971 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  363976 */   // GIR_Coverage, 11950,
     /*  363976 */   GIR_EraseRootFromParent_Done,
     /*  363977 */ // Label 5428: @363977
     /*  363977 */ GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(364078), // Rule ID 11951 //
     /*  363982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  363985 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  363988 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  363995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364010 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364017 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364017 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364020 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  364024 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364049 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364053 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364058 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364060 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364067 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364072 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364077 */   // GIR_Coverage, 11951,
     /*  364077 */   GIR_EraseRootFromParent_Done,
     /*  364078 */ // Label 5429: @364078
     /*  364078 */ GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(364179), // Rule ID 12007 //
     /*  364083 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  364086 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364089 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  364096 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364103 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364107 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364111 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364118 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364118 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364121 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  364125 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364150 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364154 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364156 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364159 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364161 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364168 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364173 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364178 */   // GIR_Coverage, 12007,
     /*  364178 */   GIR_EraseRootFromParent_Done,
     /*  364179 */ // Label 5430: @364179
     /*  364179 */ GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(364280), // Rule ID 12008 //
     /*  364184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  364187 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364190 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  364197 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364219 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364219 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364222 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  364226 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364251 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364255 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364262 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364269 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364274 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364279 */   // GIR_Coverage, 12008,
     /*  364279 */   GIR_EraseRootFromParent_Done,
     /*  364280 */ // Label 5431: @364280
     /*  364280 */ GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(364381), // Rule ID 12009 //
     /*  364285 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  364288 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364291 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  364298 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364320 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364320 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364323 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  364327 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364342 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364352 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364356 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364358 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364361 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364363 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364370 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364375 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364380 */   // GIR_Coverage, 12009,
     /*  364380 */   GIR_EraseRootFromParent_Done,
     /*  364381 */ // Label 5432: @364381
     /*  364381 */ GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(364482), // Rule ID 12010 //
     /*  364386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  364389 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364392 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  364399 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364406 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364410 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364414 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364421 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364421 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364424 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  364428 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364453 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364457 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364462 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364464 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364471 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364476 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364481 */   // GIR_Coverage, 12010,
     /*  364481 */   GIR_EraseRootFromParent_Done,
     /*  364482 */ // Label 5433: @364482
     /*  364482 */ GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(364583), // Rule ID 12011 //
     /*  364487 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  364490 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364493 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  364500 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364511 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364515 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364522 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364522 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364525 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  364529 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364554 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364558 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364560 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364563 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364565 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364572 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364577 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364582 */   // GIR_Coverage, 12011,
     /*  364582 */   GIR_EraseRootFromParent_Done,
     /*  364583 */ // Label 5434: @364583
     /*  364583 */ GIM_Try, /*On fail goto*//*Label 5435*/ GIMT_Encode4(364684), // Rule ID 12037 //
     /*  364588 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  364591 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364594 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  364601 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364608 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364616 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364623 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364623 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364626 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  364630 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364655 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364659 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364661 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364664 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364666 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364673 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364678 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364683 */   // GIR_Coverage, 12037,
     /*  364683 */   GIR_EraseRootFromParent_Done,
     /*  364684 */ // Label 5435: @364684
     /*  364684 */ GIM_Try, /*On fail goto*//*Label 5436*/ GIMT_Encode4(364785), // Rule ID 12038 //
     /*  364689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  364692 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364695 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  364702 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364709 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364713 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364717 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364724 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364724 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364727 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  364731 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364756 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364760 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364762 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364765 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364767 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364774 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364779 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364784 */   // GIR_Coverage, 12038,
     /*  364784 */   GIR_EraseRootFromParent_Done,
     /*  364785 */ // Label 5436: @364785
     /*  364785 */ GIM_Try, /*On fail goto*//*Label 5437*/ GIMT_Encode4(364886), // Rule ID 12039 //
     /*  364790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  364793 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364796 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  364803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364825 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364825 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364828 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  364832 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364857 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364861 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364866 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364868 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364875 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364880 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364885 */   // GIR_Coverage, 12039,
     /*  364885 */   GIR_EraseRootFromParent_Done,
     /*  364886 */ // Label 5437: @364886
     /*  364886 */ GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(364987), // Rule ID 12040 //
     /*  364891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  364894 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364897 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  364904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  364911 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364915 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  364919 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  364926 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  364926 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  364929 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  364933 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  364938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  364943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  364948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  364953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  364958 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  364962 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  364964 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  364967 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  364969 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  364976 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  364981 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  364986 */   // GIR_Coverage, 12040,
     /*  364986 */   GIR_EraseRootFromParent_Done,
     /*  364987 */ // Label 5438: @364987
     /*  364987 */ GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(365088), // Rule ID 12041 //
     /*  364992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  364995 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  364998 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  365005 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365012 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  365016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365020 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  365027 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  365027 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  365030 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  365034 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  365039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  365044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  365049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  365054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  365059 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365063 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  365065 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  365068 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  365070 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  365077 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  365082 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365087 */   // GIR_Coverage, 12041,
     /*  365087 */   GIR_EraseRootFromParent_Done,
     /*  365088 */ // Label 5439: @365088
     /*  365088 */ GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(365159), // Rule ID 12047 //
     /*  365093 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  365096 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  365099 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  365117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365121 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  365128 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  365128 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_t16),
     /*  365131 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  365138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  365143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  365148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  365153 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365157 */   GIR_RootConstrainSelectedInstOperands,
     /*  365158 */   // GIR_Coverage, 12047,
     /*  365158 */   GIR_EraseRootFromParent_Done,
     /*  365159 */ // Label 5440: @365159
     /*  365159 */ GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(365230), // Rule ID 12071 //
     /*  365164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  365167 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365170 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365177 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  365188 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365192 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  365199 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  365199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_t16),
     /*  365202 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  365209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  365214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  365219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  365224 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365228 */   GIR_RootConstrainSelectedInstOperands,
     /*  365229 */   // GIR_Coverage, 12071,
     /*  365229 */   GIR_EraseRootFromParent_Done,
     /*  365230 */ // Label 5441: @365230
     /*  365230 */ GIM_Try, /*On fail goto*//*Label 5442*/ GIMT_Encode4(365301), // Rule ID 12089 //
     /*  365235 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  365238 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365241 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  365248 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365255 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  365259 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365263 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  365270 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_SADDR_t16:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  365270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_t16),
     /*  365273 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  365280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  365285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  365290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  365295 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365299 */   GIR_RootConstrainSelectedInstOperands,
     /*  365300 */   // GIR_Coverage, 12089,
     /*  365300 */   GIR_EraseRootFromParent_Done,
     /*  365301 */ // Label 5442: @365301
     /*  365301 */ GIM_Try, /*On fail goto*//*Label 5443*/ GIMT_Encode4(365365), // Rule ID 11842 //
     /*  365306 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  365309 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  365312 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365341 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365344 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365359 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365363 */   GIR_RootConstrainSelectedInstOperands,
     /*  365364 */   // GIR_Coverage, 11842,
     /*  365364 */   GIR_EraseRootFromParent_Done,
     /*  365365 */ // Label 5443: @365365
     /*  365365 */ GIM_Try, /*On fail goto*//*Label 5444*/ GIMT_Encode4(365429), // Rule ID 11843 //
     /*  365370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  365373 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  365376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365394 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365398 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365405 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365420 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365423 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365427 */   GIR_RootConstrainSelectedInstOperands,
     /*  365428 */   // GIR_Coverage, 11843,
     /*  365428 */   GIR_EraseRootFromParent_Done,
     /*  365429 */ // Label 5444: @365429
     /*  365429 */ GIM_Try, /*On fail goto*//*Label 5445*/ GIMT_Encode4(365493), // Rule ID 11844 //
     /*  365434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  365437 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  365440 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365469 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365487 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365491 */   GIR_RootConstrainSelectedInstOperands,
     /*  365492 */   // GIR_Coverage, 11844,
     /*  365492 */   GIR_EraseRootFromParent_Done,
     /*  365493 */ // Label 5445: @365493
     /*  365493 */ GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(365557), // Rule ID 11845 //
     /*  365498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  365501 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  365504 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365511 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365522 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365526 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365533 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365533 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365536 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365548 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365551 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365555 */   GIR_RootConstrainSelectedInstOperands,
     /*  365556 */   // GIR_Coverage, 11845,
     /*  365556 */   GIR_EraseRootFromParent_Done,
     /*  365557 */ // Label 5446: @365557
     /*  365557 */ GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(365621), // Rule ID 11846 //
     /*  365562 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  365565 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  365568 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365575 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365597 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365619 */   GIR_RootConstrainSelectedInstOperands,
     /*  365620 */   // GIR_Coverage, 11846,
     /*  365620 */   GIR_EraseRootFromParent_Done,
     /*  365621 */ // Label 5447: @365621
     /*  365621 */ GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(365685), // Rule ID 11902 //
     /*  365626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  365629 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365632 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365639 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365650 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365654 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365661 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365661 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365664 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365676 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365679 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365683 */   GIR_RootConstrainSelectedInstOperands,
     /*  365684 */   // GIR_Coverage, 11902,
     /*  365684 */   GIR_EraseRootFromParent_Done,
     /*  365685 */ // Label 5448: @365685
     /*  365685 */ GIM_Try, /*On fail goto*//*Label 5449*/ GIMT_Encode4(365749), // Rule ID 11903 //
     /*  365690 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  365693 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365696 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365714 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365718 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365725 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365725 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365728 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365740 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365743 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365747 */   GIR_RootConstrainSelectedInstOperands,
     /*  365748 */   // GIR_Coverage, 11903,
     /*  365748 */   GIR_EraseRootFromParent_Done,
     /*  365749 */ // Label 5449: @365749
     /*  365749 */ GIM_Try, /*On fail goto*//*Label 5450*/ GIMT_Encode4(365813), // Rule ID 11904 //
     /*  365754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  365757 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365760 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365778 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365782 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365789 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365789 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365792 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365804 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365811 */   GIR_RootConstrainSelectedInstOperands,
     /*  365812 */   // GIR_Coverage, 11904,
     /*  365812 */   GIR_EraseRootFromParent_Done,
     /*  365813 */ // Label 5450: @365813
     /*  365813 */ GIM_Try, /*On fail goto*//*Label 5451*/ GIMT_Encode4(365877), // Rule ID 11905 //
     /*  365818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  365821 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365824 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365842 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365846 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365853 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365856 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365871 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365875 */   GIR_RootConstrainSelectedInstOperands,
     /*  365876 */   // GIR_Coverage, 11905,
     /*  365876 */   GIR_EraseRootFromParent_Done,
     /*  365877 */ // Label 5451: @365877
     /*  365877 */ GIM_Try, /*On fail goto*//*Label 5452*/ GIMT_Encode4(365941), // Rule ID 11906 //
     /*  365882 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  365885 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365888 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  365895 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365902 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365906 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365910 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365917 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365917 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  365920 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365935 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  365939 */   GIR_RootConstrainSelectedInstOperands,
     /*  365940 */   // GIR_Coverage, 11906,
     /*  365940 */   GIR_EraseRootFromParent_Done,
     /*  365941 */ // Label 5452: @365941
     /*  365941 */ GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(366005), // Rule ID 11932 //
     /*  365946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  365949 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  365952 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  365959 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  365966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  365970 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  365974 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  365981 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  365981 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  365984 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  365986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  365991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  365996 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  365999 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366003 */   GIR_RootConstrainSelectedInstOperands,
     /*  366004 */   // GIR_Coverage, 11932,
     /*  366004 */   GIR_EraseRootFromParent_Done,
     /*  366005 */ // Label 5453: @366005
     /*  366005 */ GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(366069), // Rule ID 11933 //
     /*  366010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  366013 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  366023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366045 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  366045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  366048 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  366050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  366063 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366067 */   GIR_RootConstrainSelectedInstOperands,
     /*  366068 */   // GIR_Coverage, 11933,
     /*  366068 */   GIR_EraseRootFromParent_Done,
     /*  366069 */ // Label 5454: @366069
     /*  366069 */ GIM_Try, /*On fail goto*//*Label 5455*/ GIMT_Encode4(366133), // Rule ID 11934 //
     /*  366074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  366077 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366080 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  366087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366098 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366102 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366109 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  366109 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  366112 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  366114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366124 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  366127 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366131 */   GIR_RootConstrainSelectedInstOperands,
     /*  366132 */   // GIR_Coverage, 11934,
     /*  366132 */   GIR_EraseRootFromParent_Done,
     /*  366133 */ // Label 5455: @366133
     /*  366133 */ GIM_Try, /*On fail goto*//*Label 5456*/ GIMT_Encode4(366197), // Rule ID 11935 //
     /*  366138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  366141 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366144 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  366151 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366158 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366166 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366173 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  366173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  366176 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  366178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  366191 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366195 */   GIR_RootConstrainSelectedInstOperands,
     /*  366196 */   // GIR_Coverage, 11935,
     /*  366196 */   GIR_EraseRootFromParent_Done,
     /*  366197 */ // Label 5456: @366197
     /*  366197 */ GIM_Try, /*On fail goto*//*Label 5457*/ GIMT_Encode4(366261), // Rule ID 11936 //
     /*  366202 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  366205 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366208 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  366215 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366230 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366237 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  366237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  366240 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  366242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366252 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  366255 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366259 */   GIR_RootConstrainSelectedInstOperands,
     /*  366260 */   // GIR_Coverage, 11936,
     /*  366260 */   GIR_EraseRootFromParent_Done,
     /*  366261 */ // Label 5457: @366261
     /*  366261 */ GIM_Try, /*On fail goto*//*Label 5458*/ GIMT_Encode4(366355), // Rule ID 11942 //
     /*  366266 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  366269 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  366272 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366290 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366294 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366301 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366301 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366304 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366308 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366323 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366326 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366330 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366332 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366335 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366337 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366344 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366349 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366354 */   // GIR_Coverage, 11942,
     /*  366354 */   GIR_EraseRootFromParent_Done,
     /*  366355 */ // Label 5458: @366355
     /*  366355 */ GIM_Try, /*On fail goto*//*Label 5459*/ GIMT_Encode4(366449), // Rule ID 11943 //
     /*  366360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  366363 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  366366 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366373 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366384 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366388 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366395 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366395 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366398 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366402 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366417 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366420 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366424 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366429 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366431 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366438 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366443 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366448 */   // GIR_Coverage, 11943,
     /*  366448 */   GIR_EraseRootFromParent_Done,
     /*  366449 */ // Label 5459: @366449
     /*  366449 */ GIM_Try, /*On fail goto*//*Label 5460*/ GIMT_Encode4(366543), // Rule ID 11944 //
     /*  366454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  366457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  366460 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366467 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366489 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366489 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366492 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366496 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366511 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366514 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366518 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366525 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366532 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366537 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366542 */   // GIR_Coverage, 11944,
     /*  366542 */   GIR_EraseRootFromParent_Done,
     /*  366543 */ // Label 5460: @366543
     /*  366543 */ GIM_Try, /*On fail goto*//*Label 5461*/ GIMT_Encode4(366637), // Rule ID 11945 //
     /*  366548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  366551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  366554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366568 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366572 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366576 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366583 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366583 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366586 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366590 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366605 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366608 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366612 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366614 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366617 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366619 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366626 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366631 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366636 */   // GIR_Coverage, 11945,
     /*  366636 */   GIR_EraseRootFromParent_Done,
     /*  366637 */ // Label 5461: @366637
     /*  366637 */ GIM_Try, /*On fail goto*//*Label 5462*/ GIMT_Encode4(366731), // Rule ID 11946 //
     /*  366642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  366645 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  366648 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366655 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366666 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366670 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366677 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366677 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366680 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366684 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366699 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366702 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366706 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366713 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366720 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366725 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366730 */   // GIR_Coverage, 11946,
     /*  366730 */   GIR_EraseRootFromParent_Done,
     /*  366731 */ // Label 5462: @366731
     /*  366731 */ GIM_Try, /*On fail goto*//*Label 5463*/ GIMT_Encode4(366825), // Rule ID 12002 //
     /*  366736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  366739 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366742 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366756 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366760 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366764 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366771 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366771 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366774 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366778 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366793 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366796 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366800 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366802 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366805 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366807 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366814 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366819 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366824 */   // GIR_Coverage, 12002,
     /*  366824 */   GIR_EraseRootFromParent_Done,
     /*  366825 */ // Label 5463: @366825
     /*  366825 */ GIM_Try, /*On fail goto*//*Label 5464*/ GIMT_Encode4(366919), // Rule ID 12003 //
     /*  366830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  366833 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366836 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366843 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366854 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366858 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366865 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366865 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366868 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366872 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366887 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366890 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366894 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366899 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366901 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  366908 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366913 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  366918 */   // GIR_Coverage, 12003,
     /*  366918 */   GIR_EraseRootFromParent_Done,
     /*  366919 */ // Label 5464: @366919
     /*  366919 */ GIM_Try, /*On fail goto*//*Label 5465*/ GIMT_Encode4(367013), // Rule ID 12004 //
     /*  366924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  366927 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  366930 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  366937 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  366944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  366948 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  366952 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  366959 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  366959 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  366962 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  366966 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  366971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  366976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  366981 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  366984 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  366988 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  366990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  366993 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  366995 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367002 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367007 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367012 */   // GIR_Coverage, 12004,
     /*  367012 */   GIR_EraseRootFromParent_Done,
     /*  367013 */ // Label 5465: @367013
     /*  367013 */ GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(367107), // Rule ID 12005 //
     /*  367018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  367021 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367024 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367031 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367042 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367046 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367053 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367053 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367056 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  367060 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367075 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367078 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367082 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367084 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367087 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367089 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367096 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367101 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367106 */   // GIR_Coverage, 12005,
     /*  367106 */   GIR_EraseRootFromParent_Done,
     /*  367107 */ // Label 5466: @367107
     /*  367107 */ GIM_Try, /*On fail goto*//*Label 5467*/ GIMT_Encode4(367201), // Rule ID 12006 //
     /*  367112 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  367115 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367118 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367125 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367147 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367147 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367150 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  367154 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367169 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367172 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367176 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367178 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367181 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367183 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367190 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367195 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367200 */   // GIR_Coverage, 12006,
     /*  367200 */   GIR_EraseRootFromParent_Done,
     /*  367201 */ // Label 5467: @367201
     /*  367201 */ GIM_Try, /*On fail goto*//*Label 5468*/ GIMT_Encode4(367295), // Rule ID 12032 //
     /*  367206 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  367209 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367212 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  367219 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367241 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367241 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367244 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  367248 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367263 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367266 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367270 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367272 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367275 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367277 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367284 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367289 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367294 */   // GIR_Coverage, 12032,
     /*  367294 */   GIR_EraseRootFromParent_Done,
     /*  367295 */ // Label 5468: @367295
     /*  367295 */ GIM_Try, /*On fail goto*//*Label 5469*/ GIMT_Encode4(367389), // Rule ID 12033 //
     /*  367300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  367303 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  367313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367335 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367335 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367338 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  367342 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367357 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367360 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367364 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367371 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367378 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367383 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367388 */   // GIR_Coverage, 12033,
     /*  367388 */   GIR_EraseRootFromParent_Done,
     /*  367389 */ // Label 5469: @367389
     /*  367389 */ GIM_Try, /*On fail goto*//*Label 5470*/ GIMT_Encode4(367483), // Rule ID 12034 //
     /*  367394 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  367397 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367400 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  367407 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367418 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367422 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367429 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367429 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367432 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  367436 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367451 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367454 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367458 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367460 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367463 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367465 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367472 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367477 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367482 */   // GIR_Coverage, 12034,
     /*  367482 */   GIR_EraseRootFromParent_Done,
     /*  367483 */ // Label 5470: @367483
     /*  367483 */ GIM_Try, /*On fail goto*//*Label 5471*/ GIMT_Encode4(367577), // Rule ID 12035 //
     /*  367488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  367491 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367494 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  367501 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367512 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367516 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367523 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367523 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367526 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  367530 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367545 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367548 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367552 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367554 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367557 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367559 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367566 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367571 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367576 */   // GIR_Coverage, 12035,
     /*  367576 */   GIR_EraseRootFromParent_Done,
     /*  367577 */ // Label 5471: @367577
     /*  367577 */ GIM_Try, /*On fail goto*//*Label 5472*/ GIMT_Encode4(367671), // Rule ID 12036 //
     /*  367582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  367585 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  367588 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  367595 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367617 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  367617 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  367620 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  367624 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  367629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367639 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  367642 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367646 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  367648 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  367651 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  367653 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  367660 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367665 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  367670 */   // GIR_Coverage, 12036,
     /*  367670 */   GIR_EraseRootFromParent_Done,
     /*  367671 */ // Label 5472: @367671
     /*  367671 */ GIM_Try, /*On fail goto*//*Label 5473*/ GIMT_Encode4(367735), // Rule ID 12042 //
     /*  367676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  367679 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  367682 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367700 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367704 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367711 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  367711 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  367714 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  367716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367726 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  367729 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367733 */   GIR_RootConstrainSelectedInstOperands,
     /*  367734 */   // GIR_Coverage, 12042,
     /*  367734 */   GIR_EraseRootFromParent_Done,
     /*  367735 */ // Label 5473: @367735
     /*  367735 */ GIM_Try, /*On fail goto*//*Label 5474*/ GIMT_Encode4(367799), // Rule ID 12043 //
     /*  367740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  367743 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  367746 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367753 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367775 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  367775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  367778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  367780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367790 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  367793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367797 */   GIR_RootConstrainSelectedInstOperands,
     /*  367798 */   // GIR_Coverage, 12043,
     /*  367798 */   GIR_EraseRootFromParent_Done,
     /*  367799 */ // Label 5474: @367799
     /*  367799 */ GIM_Try, /*On fail goto*//*Label 5475*/ GIMT_Encode4(367863), // Rule ID 12044 //
     /*  367804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  367807 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  367810 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367817 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367832 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367839 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  367839 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  367842 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  367844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367854 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  367857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367861 */   GIR_RootConstrainSelectedInstOperands,
     /*  367862 */   // GIR_Coverage, 12044,
     /*  367862 */   GIR_EraseRootFromParent_Done,
     /*  367863 */ // Label 5475: @367863
     /*  367863 */ GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(367927), // Rule ID 12045 //
     /*  367868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  367871 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  367874 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367892 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367896 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367903 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  367903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  367906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  367908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367918 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  367921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367925 */   GIR_RootConstrainSelectedInstOperands,
     /*  367926 */   // GIR_Coverage, 12045,
     /*  367926 */   GIR_EraseRootFromParent_Done,
     /*  367927 */ // Label 5476: @367927
     /*  367927 */ GIM_Try, /*On fail goto*//*Label 5477*/ GIMT_Encode4(367991), // Rule ID 12046 //
     /*  367932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  367935 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  367938 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  367945 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  367952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  367956 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  367960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  367967 */   // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  367967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  367970 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  367972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  367977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  367982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  367985 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  367989 */   GIR_RootConstrainSelectedInstOperands,
     /*  367990 */   // GIR_Coverage, 12046,
     /*  367990 */   GIR_EraseRootFromParent_Done,
     /*  367991 */ // Label 5477: @367991
     /*  367991 */ GIM_Try, /*On fail goto*//*Label 5478*/ GIMT_Encode4(368055), // Rule ID 12066 //
     /*  367996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  367999 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368002 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  368009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368020 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368024 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368031 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368031 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  368034 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368046 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368053 */   GIR_RootConstrainSelectedInstOperands,
     /*  368054 */   // GIR_Coverage, 12066,
     /*  368054 */   GIR_EraseRootFromParent_Done,
     /*  368055 */ // Label 5478: @368055
     /*  368055 */ GIM_Try, /*On fail goto*//*Label 5479*/ GIMT_Encode4(368119), // Rule ID 12067 //
     /*  368060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  368063 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368066 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  368073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368088 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368095 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  368098 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368110 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368117 */   GIR_RootConstrainSelectedInstOperands,
     /*  368118 */   // GIR_Coverage, 12067,
     /*  368118 */   GIR_EraseRootFromParent_Done,
     /*  368119 */ // Label 5479: @368119
     /*  368119 */ GIM_Try, /*On fail goto*//*Label 5480*/ GIMT_Encode4(368183), // Rule ID 12068 //
     /*  368124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  368127 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  368137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368159 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  368162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368181 */   GIR_RootConstrainSelectedInstOperands,
     /*  368182 */   // GIR_Coverage, 12068,
     /*  368182 */   GIR_EraseRootFromParent_Done,
     /*  368183 */ // Label 5480: @368183
     /*  368183 */ GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(368247), // Rule ID 12069 //
     /*  368188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  368191 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368194 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  368201 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368208 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368212 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368216 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368223 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  368226 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368241 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368245 */   GIR_RootConstrainSelectedInstOperands,
     /*  368246 */   // GIR_Coverage, 12069,
     /*  368246 */   GIR_EraseRootFromParent_Done,
     /*  368247 */ // Label 5481: @368247
     /*  368247 */ GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(368311), // Rule ID 12070 //
     /*  368252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  368255 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368258 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  368265 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368272 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368276 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368280 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368287 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368287 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_D16_t16),
     /*  368290 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368302 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368309 */   GIR_RootConstrainSelectedInstOperands,
     /*  368310 */   // GIR_Coverage, 12070,
     /*  368310 */   GIR_EraseRootFromParent_Done,
     /*  368311 */ // Label 5482: @368311
     /*  368311 */ GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(368375), // Rule ID 12084 //
     /*  368316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  368319 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368322 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368329 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368336 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368340 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368344 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368351 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  368354 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368373 */   GIR_RootConstrainSelectedInstOperands,
     /*  368374 */   // GIR_Coverage, 12084,
     /*  368374 */   GIR_EraseRootFromParent_Done,
     /*  368375 */ // Label 5483: @368375
     /*  368375 */ GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(368439), // Rule ID 12085 //
     /*  368380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  368383 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368386 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368393 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368415 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  368418 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368430 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368433 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368437 */   GIR_RootConstrainSelectedInstOperands,
     /*  368438 */   // GIR_Coverage, 12085,
     /*  368438 */   GIR_EraseRootFromParent_Done,
     /*  368439 */ // Label 5484: @368439
     /*  368439 */ GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(368503), // Rule ID 12086 //
     /*  368444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  368447 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368450 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368457 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368464 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368468 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368472 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368479 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368479 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  368482 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368501 */   GIR_RootConstrainSelectedInstOperands,
     /*  368502 */   // GIR_Coverage, 12086,
     /*  368502 */   GIR_EraseRootFromParent_Done,
     /*  368503 */ // Label 5485: @368503
     /*  368503 */ GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(368567), // Rule ID 12087 //
     /*  368508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  368511 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368514 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368521 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368543 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  368546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368558 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368561 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368565 */   GIR_RootConstrainSelectedInstOperands,
     /*  368566 */   // GIR_Coverage, 12087,
     /*  368566 */   GIR_EraseRootFromParent_Done,
     /*  368567 */ // Label 5486: @368567
     /*  368567 */ GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(368631), // Rule ID 12088 //
     /*  368572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  368575 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368578 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368585 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  368596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368600 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  368607 */   // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_SHORT_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  368607 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SHORT_D16_t16),
     /*  368610 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  368617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  368622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  368625 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368629 */   GIR_RootConstrainSelectedInstOperands,
     /*  368630 */   // GIR_Coverage, 12088,
     /*  368630 */   GIR_EraseRootFromParent_Done,
     /*  368631 */ // Label 5487: @368631
     /*  368631 */ GIM_Try, /*On fail goto*//*Label 5488*/ GIMT_Encode4(368703), // Rule ID 9561 //
     /*  368636 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  368639 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368642 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  368661 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368665 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  368672 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  368672 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  368675 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  368682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  368687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  368692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  368697 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368701 */   GIR_RootConstrainSelectedInstOperands,
     /*  368702 */   // GIR_Coverage, 9561,
     /*  368702 */   GIR_EraseRootFromParent_Done,
     /*  368703 */ // Label 5488: @368703
     /*  368703 */ GIM_Try, /*On fail goto*//*Label 5489*/ GIMT_Encode4(368775), // Rule ID 9562 //
     /*  368708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  368711 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368714 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368721 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  368733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368737 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  368744 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  368744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  368747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  368754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  368759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  368764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  368769 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368773 */   GIR_RootConstrainSelectedInstOperands,
     /*  368774 */   // GIR_Coverage, 9562,
     /*  368774 */   GIR_EraseRootFromParent_Done,
     /*  368775 */ // Label 5489: @368775
     /*  368775 */ GIM_Try, /*On fail goto*//*Label 5490*/ GIMT_Encode4(368847), // Rule ID 9563 //
     /*  368780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  368783 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368786 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368793 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368801 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  368805 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368809 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  368816 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  368816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  368819 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  368826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  368831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  368836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  368841 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368845 */   GIR_RootConstrainSelectedInstOperands,
     /*  368846 */   // GIR_Coverage, 9563,
     /*  368846 */   GIR_EraseRootFromParent_Done,
     /*  368847 */ // Label 5490: @368847
     /*  368847 */ GIM_Try, /*On fail goto*//*Label 5491*/ GIMT_Encode4(368919), // Rule ID 9564 //
     /*  368852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  368855 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368858 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368865 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368873 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  368877 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368881 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  368888 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  368888 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  368891 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  368898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  368903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  368908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  368913 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368917 */   GIR_RootConstrainSelectedInstOperands,
     /*  368918 */   // GIR_Coverage, 9564,
     /*  368918 */   GIR_EraseRootFromParent_Done,
     /*  368919 */ // Label 5491: @368919
     /*  368919 */ GIM_Try, /*On fail goto*//*Label 5492*/ GIMT_Encode4(368991), // Rule ID 9565 //
     /*  368924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  368927 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  368930 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  368937 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  368945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  368949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  368953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  368960 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  368960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  368963 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  368965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  368970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  368975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  368980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  368985 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  368989 */   GIR_RootConstrainSelectedInstOperands,
     /*  368990 */   // GIR_Coverage, 9565,
     /*  368990 */   GIR_EraseRootFromParent_Done,
     /*  368991 */ // Label 5492: @368991
     /*  368991 */ GIM_Try, /*On fail goto*//*Label 5493*/ GIMT_Encode4(369063), // Rule ID 9671 //
     /*  368996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  368999 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369002 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369021 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369025 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369032 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369032 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369035 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369057 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369061 */   GIR_RootConstrainSelectedInstOperands,
     /*  369062 */   // GIR_Coverage, 9671,
     /*  369062 */   GIR_EraseRootFromParent_Done,
     /*  369063 */ // Label 5493: @369063
     /*  369063 */ GIM_Try, /*On fail goto*//*Label 5494*/ GIMT_Encode4(369135), // Rule ID 9672 //
     /*  369068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  369071 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369074 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369081 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369093 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369097 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369104 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369107 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369129 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369133 */   GIR_RootConstrainSelectedInstOperands,
     /*  369134 */   // GIR_Coverage, 9672,
     /*  369134 */   GIR_EraseRootFromParent_Done,
     /*  369135 */ // Label 5494: @369135
     /*  369135 */ GIM_Try, /*On fail goto*//*Label 5495*/ GIMT_Encode4(369207), // Rule ID 9673 //
     /*  369140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  369143 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369146 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369153 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369176 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369179 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369201 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369205 */   GIR_RootConstrainSelectedInstOperands,
     /*  369206 */   // GIR_Coverage, 9673,
     /*  369206 */   GIR_EraseRootFromParent_Done,
     /*  369207 */ // Label 5495: @369207
     /*  369207 */ GIM_Try, /*On fail goto*//*Label 5496*/ GIMT_Encode4(369279), // Rule ID 9674 //
     /*  369212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  369215 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369218 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369225 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369237 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369241 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369248 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369248 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369251 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369273 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369277 */   GIR_RootConstrainSelectedInstOperands,
     /*  369278 */   // GIR_Coverage, 9674,
     /*  369278 */   GIR_EraseRootFromParent_Done,
     /*  369279 */ // Label 5496: @369279
     /*  369279 */ GIM_Try, /*On fail goto*//*Label 5497*/ GIMT_Encode4(369351), // Rule ID 9675 //
     /*  369284 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  369287 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369290 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369297 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369320 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369345 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369349 */   GIR_RootConstrainSelectedInstOperands,
     /*  369350 */   // GIR_Coverage, 9675,
     /*  369350 */   GIR_EraseRootFromParent_Done,
     /*  369351 */ // Label 5497: @369351
     /*  369351 */ GIM_Try, /*On fail goto*//*Label 5498*/ GIMT_Encode4(369423), // Rule ID 9711 //
     /*  369356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  369359 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  369362 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369369 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369377 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369381 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369385 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369392 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369392 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369395 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369417 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369421 */   GIR_RootConstrainSelectedInstOperands,
     /*  369422 */   // GIR_Coverage, 9711,
     /*  369422 */   GIR_EraseRootFromParent_Done,
     /*  369423 */ // Label 5498: @369423
     /*  369423 */ GIM_Try, /*On fail goto*//*Label 5499*/ GIMT_Encode4(369495), // Rule ID 9712 //
     /*  369428 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  369431 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  369434 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369441 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369449 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369453 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369457 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369464 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369467 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369489 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369493 */   GIR_RootConstrainSelectedInstOperands,
     /*  369494 */   // GIR_Coverage, 9712,
     /*  369494 */   GIR_EraseRootFromParent_Done,
     /*  369495 */ // Label 5499: @369495
     /*  369495 */ GIM_Try, /*On fail goto*//*Label 5500*/ GIMT_Encode4(369567), // Rule ID 9713 //
     /*  369500 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  369503 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  369506 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369513 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369521 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369525 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369529 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369536 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369536 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369539 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369541 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369561 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369565 */   GIR_RootConstrainSelectedInstOperands,
     /*  369566 */   // GIR_Coverage, 9713,
     /*  369566 */   GIR_EraseRootFromParent_Done,
     /*  369567 */ // Label 5500: @369567
     /*  369567 */ GIM_Try, /*On fail goto*//*Label 5501*/ GIMT_Encode4(369639), // Rule ID 9714 //
     /*  369572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  369575 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  369578 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369585 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369593 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369597 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369601 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369608 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369611 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369633 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369637 */   GIR_RootConstrainSelectedInstOperands,
     /*  369638 */   // GIR_Coverage, 9714,
     /*  369638 */   GIR_EraseRootFromParent_Done,
     /*  369639 */ // Label 5501: @369639
     /*  369639 */ GIM_Try, /*On fail goto*//*Label 5502*/ GIMT_Encode4(369711), // Rule ID 9715 //
     /*  369644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  369647 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  369650 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369657 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369669 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369680 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  369680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  369685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369705 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369709 */   GIR_RootConstrainSelectedInstOperands,
     /*  369710 */   // GIR_Coverage, 9715,
     /*  369710 */   GIR_EraseRootFromParent_Done,
     /*  369711 */ // Label 5502: @369711
     /*  369711 */ GIM_Try, /*On fail goto*//*Label 5503*/ GIMT_Encode4(369813), // Rule ID 9771 //
     /*  369716 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  369719 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369722 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369729 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369737 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  369741 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369745 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369752 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  369752 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  369755 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369759 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  369764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369784 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369788 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  369790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  369793 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  369795 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  369802 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  369807 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369812 */   // GIR_Coverage, 9771,
     /*  369812 */   GIR_EraseRootFromParent_Done,
     /*  369813 */ // Label 5503: @369813
     /*  369813 */ GIM_Try, /*On fail goto*//*Label 5504*/ GIMT_Encode4(369915), // Rule ID 9772 //
     /*  369818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  369821 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369824 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  369843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369847 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369854 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  369854 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  369857 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369861 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  369866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369886 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369890 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  369892 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  369895 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  369897 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  369904 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  369909 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  369914 */   // GIR_Coverage, 9772,
     /*  369914 */   GIR_EraseRootFromParent_Done,
     /*  369915 */ // Label 5504: @369915
     /*  369915 */ GIM_Try, /*On fail goto*//*Label 5505*/ GIMT_Encode4(370017), // Rule ID 9773 //
     /*  369920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  369923 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  369926 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  369933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  369941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  369945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  369949 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  369956 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  369956 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  369959 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  369963 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  369968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  369973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  369978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  369983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  369988 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  369992 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  369994 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  369997 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  369999 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370006 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370011 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370016 */   // GIR_Coverage, 9773,
     /*  370016 */   GIR_EraseRootFromParent_Done,
     /*  370017 */ // Label 5505: @370017
     /*  370017 */ GIM_Try, /*On fail goto*//*Label 5506*/ GIMT_Encode4(370119), // Rule ID 9774 //
     /*  370022 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  370025 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  370028 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370035 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370058 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370058 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370061 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370065 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370090 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370094 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370096 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370099 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370101 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370108 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370113 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370118 */   // GIR_Coverage, 9774,
     /*  370118 */   GIR_EraseRootFromParent_Done,
     /*  370119 */ // Label 5506: @370119
     /*  370119 */ GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(370221), // Rule ID 9775 //
     /*  370124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  370127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  370130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370149 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370153 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370160 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370160 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370163 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370167 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370192 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370196 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370201 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370203 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370210 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370215 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370220 */   // GIR_Coverage, 9775,
     /*  370220 */   GIR_EraseRootFromParent_Done,
     /*  370221 */ // Label 5507: @370221
     /*  370221 */ GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(370323), // Rule ID 9811 //
     /*  370226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode0),
     /*  370229 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370251 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370255 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370262 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370262 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370265 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370269 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370279 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370294 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370298 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370300 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370303 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370305 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370312 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370317 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370322 */   // GIR_Coverage, 9811,
     /*  370322 */   GIR_EraseRootFromParent_Done,
     /*  370323 */ // Label 5508: @370323
     /*  370323 */ GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(370425), // Rule ID 9812 //
     /*  370328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode1),
     /*  370331 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370334 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370341 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370349 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370353 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370357 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370364 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370364 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370367 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370371 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370396 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370400 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370405 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370407 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370414 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370419 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370424 */   // GIR_Coverage, 9812,
     /*  370424 */   GIR_EraseRootFromParent_Done,
     /*  370425 */ // Label 5509: @370425
     /*  370425 */ GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(370527), // Rule ID 9813 //
     /*  370430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode2),
     /*  370433 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370436 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370466 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370466 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370469 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370473 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370498 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370502 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370507 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370509 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370516 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370521 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370526 */   // GIR_Coverage, 9813,
     /*  370526 */   GIR_EraseRootFromParent_Done,
     /*  370527 */ // Label 5510: @370527
     /*  370527 */ GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(370629), // Rule ID 9814 //
     /*  370532 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode3),
     /*  370535 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370538 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370545 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370557 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370561 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370568 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370568 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370571 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370575 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370600 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370604 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370611 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370618 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370623 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370628 */   // GIR_Coverage, 9814,
     /*  370628 */   GIR_EraseRootFromParent_Done,
     /*  370629 */ // Label 5511: @370629
     /*  370629 */ GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(370731), // Rule ID 9815 //
     /*  370634 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_UseTrue16WithSramECC_HwMode4),
     /*  370637 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370640 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370647 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370659 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370663 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370670 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  370670 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  370673 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  370677 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  370682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370702 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370706 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  370708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  370711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  370713 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  370720 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370725 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370730 */   // GIR_Coverage, 9815,
     /*  370730 */   GIR_EraseRootFromParent_Done,
     /*  370731 */ // Label 5512: @370731
     /*  370731 */ GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(370803), // Rule ID 9841 //
     /*  370736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  370739 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  370742 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370772 */   // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  370772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16_SADDR),
     /*  370775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  370777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370797 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370801 */   GIR_RootConstrainSelectedInstOperands,
     /*  370802 */   // GIR_Coverage, 9841,
     /*  370802 */   GIR_EraseRootFromParent_Done,
     /*  370803 */ // Label 5513: @370803
     /*  370803 */ GIM_Try, /*On fail goto*//*Label 5514*/ GIMT_Encode4(370875), // Rule ID 9865 //
     /*  370808 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_HasFlatGVSMode_UseRealTrue16Insts),
     /*  370811 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370814 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  370821 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  370833 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370837 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  370844 */   // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  370844 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16_SADDR),
     /*  370847 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  370849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  370854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  370859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  370864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  370869 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370873 */   GIR_RootConstrainSelectedInstOperands,
     /*  370874 */   // GIR_Coverage, 9865,
     /*  370874 */   GIR_EraseRootFromParent_Done,
     /*  370875 */ // Label 5514: @370875
     /*  370875 */ GIM_Try, /*On fail goto*//*Label 5515*/ GIMT_Encode4(370940), // Rule ID 9556 //
     /*  370880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  370883 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370886 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  370893 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370905 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370909 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  370916 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  370916 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  370919 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  370921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  370926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  370931 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  370934 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  370938 */   GIR_RootConstrainSelectedInstOperands,
     /*  370939 */   // GIR_Coverage, 9556,
     /*  370939 */   GIR_EraseRootFromParent_Done,
     /*  370940 */ // Label 5515: @370940
     /*  370940 */ GIM_Try, /*On fail goto*//*Label 5516*/ GIMT_Encode4(371005), // Rule ID 9557 //
     /*  370945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  370948 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  370951 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  370958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  370966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  370970 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  370974 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  370981 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  370981 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  370984 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  370986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  370991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  370996 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  370999 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371003 */   GIR_RootConstrainSelectedInstOperands,
     /*  371004 */   // GIR_Coverage, 9557,
     /*  371004 */   GIR_EraseRootFromParent_Done,
     /*  371005 */ // Label 5516: @371005
     /*  371005 */ GIM_Try, /*On fail goto*//*Label 5517*/ GIMT_Encode4(371070), // Rule ID 9558 //
     /*  371010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  371013 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  371023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371046 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  371049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371061 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371064 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371068 */   GIR_RootConstrainSelectedInstOperands,
     /*  371069 */   // GIR_Coverage, 9558,
     /*  371069 */   GIR_EraseRootFromParent_Done,
     /*  371070 */ // Label 5517: @371070
     /*  371070 */ GIM_Try, /*On fail goto*//*Label 5518*/ GIMT_Encode4(371135), // Rule ID 9559 //
     /*  371075 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  371078 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371081 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  371088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371100 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371104 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371111 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371111 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  371114 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371126 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371129 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371133 */   GIR_RootConstrainSelectedInstOperands,
     /*  371134 */   // GIR_Coverage, 9559,
     /*  371134 */   GIR_EraseRootFromParent_Done,
     /*  371135 */ // Label 5518: @371135
     /*  371135 */ GIM_Try, /*On fail goto*//*Label 5519*/ GIMT_Encode4(371200), // Rule ID 9560 //
     /*  371140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  371143 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371146 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  371153 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371176 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  371179 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371194 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371198 */   GIR_RootConstrainSelectedInstOperands,
     /*  371199 */   // GIR_Coverage, 9560,
     /*  371199 */   GIR_EraseRootFromParent_Done,
     /*  371200 */ // Label 5519: @371200
     /*  371200 */ GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(371265), // Rule ID 9666 //
     /*  371205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  371208 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371211 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371241 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371259 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371263 */   GIR_RootConstrainSelectedInstOperands,
     /*  371264 */   // GIR_Coverage, 9666,
     /*  371264 */   GIR_EraseRootFromParent_Done,
     /*  371265 */ // Label 5520: @371265
     /*  371265 */ GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(371330), // Rule ID 9667 //
     /*  371270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  371273 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371276 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371283 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371291 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371295 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371306 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371309 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371321 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371324 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371328 */   GIR_RootConstrainSelectedInstOperands,
     /*  371329 */   // GIR_Coverage, 9667,
     /*  371329 */   GIR_EraseRootFromParent_Done,
     /*  371330 */ // Label 5521: @371330
     /*  371330 */ GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(371395), // Rule ID 9668 //
     /*  371335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  371338 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371341 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371348 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371360 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371364 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371371 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371374 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371386 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371389 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371393 */   GIR_RootConstrainSelectedInstOperands,
     /*  371394 */   // GIR_Coverage, 9668,
     /*  371394 */   GIR_EraseRootFromParent_Done,
     /*  371395 */ // Label 5522: @371395
     /*  371395 */ GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(371460), // Rule ID 9669 //
     /*  371400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  371403 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371406 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371413 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371421 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371425 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371429 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371436 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371439 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371451 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371454 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371458 */   GIR_RootConstrainSelectedInstOperands,
     /*  371459 */   // GIR_Coverage, 9669,
     /*  371459 */   GIR_EraseRootFromParent_Done,
     /*  371460 */ // Label 5523: @371460
     /*  371460 */ GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(371525), // Rule ID 9670 //
     /*  371465 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  371468 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371471 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371478 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371490 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371494 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371501 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371516 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371519 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371523 */   GIR_RootConstrainSelectedInstOperands,
     /*  371524 */   // GIR_Coverage, 9670,
     /*  371524 */   GIR_EraseRootFromParent_Done,
     /*  371525 */ // Label 5524: @371525
     /*  371525 */ GIM_Try, /*On fail goto*//*Label 5525*/ GIMT_Encode4(371590), // Rule ID 9706 //
     /*  371530 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  371533 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371536 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371543 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371551 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371566 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371569 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371581 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371584 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371588 */   GIR_RootConstrainSelectedInstOperands,
     /*  371589 */   // GIR_Coverage, 9706,
     /*  371589 */   GIR_EraseRootFromParent_Done,
     /*  371590 */ // Label 5525: @371590
     /*  371590 */ GIM_Try, /*On fail goto*//*Label 5526*/ GIMT_Encode4(371655), // Rule ID 9707 //
     /*  371595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  371598 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371601 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371608 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371616 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371620 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371624 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371631 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371653 */   GIR_RootConstrainSelectedInstOperands,
     /*  371654 */   // GIR_Coverage, 9707,
     /*  371654 */   GIR_EraseRootFromParent_Done,
     /*  371655 */ // Label 5526: @371655
     /*  371655 */ GIM_Try, /*On fail goto*//*Label 5527*/ GIMT_Encode4(371720), // Rule ID 9708 //
     /*  371660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  371663 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371666 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371673 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371696 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371714 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371718 */   GIR_RootConstrainSelectedInstOperands,
     /*  371719 */   // GIR_Coverage, 9708,
     /*  371719 */   GIR_EraseRootFromParent_Done,
     /*  371720 */ // Label 5527: @371720
     /*  371720 */ GIM_Try, /*On fail goto*//*Label 5528*/ GIMT_Encode4(371785), // Rule ID 9709 //
     /*  371725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  371728 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371738 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371761 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371764 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371783 */   GIR_RootConstrainSelectedInstOperands,
     /*  371784 */   // GIR_Coverage, 9709,
     /*  371784 */   GIR_EraseRootFromParent_Done,
     /*  371785 */ // Label 5528: @371785
     /*  371785 */ GIM_Try, /*On fail goto*//*Label 5529*/ GIMT_Encode4(371850), // Rule ID 9710 //
     /*  371790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  371793 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  371796 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371815 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371819 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371826 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  371826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371829 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  371831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371841 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  371844 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371848 */   GIR_RootConstrainSelectedInstOperands,
     /*  371849 */   // GIR_Coverage, 9710,
     /*  371849 */   GIR_EraseRootFromParent_Done,
     /*  371850 */ // Label 5529: @371850
     /*  371850 */ GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(371945), // Rule ID 9766 //
     /*  371855 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  371858 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371861 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371868 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  371880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371891 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  371891 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  371894 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371898 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  371903 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  371908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  371913 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  371916 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  371920 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  371922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  371925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  371927 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  371934 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  371939 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  371944 */   // GIR_Coverage, 9766,
     /*  371944 */   GIR_EraseRootFromParent_Done,
     /*  371945 */ // Label 5530: @371945
     /*  371945 */ GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(372040), // Rule ID 9767 //
     /*  371950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  371953 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  371956 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  371963 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  371971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  371975 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  371979 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  371986 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  371986 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  371989 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  371993 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  371998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372008 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372011 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372015 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372022 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372029 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372034 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372039 */   // GIR_Coverage, 9767,
     /*  372039 */   GIR_EraseRootFromParent_Done,
     /*  372040 */ // Label 5531: @372040
     /*  372040 */ GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(372135), // Rule ID 9768 //
     /*  372045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  372048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  372051 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372058 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372081 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372081 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372084 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372088 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372103 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372106 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372110 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372115 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372117 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372124 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372129 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372134 */   // GIR_Coverage, 9768,
     /*  372134 */   GIR_EraseRootFromParent_Done,
     /*  372135 */ // Label 5532: @372135
     /*  372135 */ GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(372230), // Rule ID 9769 //
     /*  372140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  372143 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  372146 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372153 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372176 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372176 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372179 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372183 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372198 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372201 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372205 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372207 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372210 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372212 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372219 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372224 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372229 */   // GIR_Coverage, 9769,
     /*  372229 */   GIR_EraseRootFromParent_Done,
     /*  372230 */ // Label 5533: @372230
     /*  372230 */ GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(372325), // Rule ID 9770 //
     /*  372235 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  372238 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  372241 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372248 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372271 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372271 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372274 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372278 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372293 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372296 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372300 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372302 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372305 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372307 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372314 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372319 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372324 */   // GIR_Coverage, 9770,
     /*  372324 */   GIR_EraseRootFromParent_Done,
     /*  372325 */ // Label 5534: @372325
     /*  372325 */ GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(372420), // Rule ID 9806 //
     /*  372330 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode0),
     /*  372333 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  372336 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372343 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372355 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372359 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372366 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372366 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372369 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372373 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372388 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372391 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372395 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372397 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372400 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372402 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372409 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372414 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372419 */   // GIR_Coverage, 9806,
     /*  372419 */   GIR_EraseRootFromParent_Done,
     /*  372420 */ // Label 5535: @372420
     /*  372420 */ GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(372515), // Rule ID 9807 //
     /*  372425 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode1),
     /*  372428 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  372431 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372438 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372450 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372454 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372461 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372461 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372464 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372468 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372483 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372486 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372490 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372492 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372495 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372497 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372504 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372509 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372514 */   // GIR_Coverage, 9807,
     /*  372514 */   GIR_EraseRootFromParent_Done,
     /*  372515 */ // Label 5536: @372515
     /*  372515 */ GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(372610), // Rule ID 9808 //
     /*  372520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode2),
     /*  372523 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  372526 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372533 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372541 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372545 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372549 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372556 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372556 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372559 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372563 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372578 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372581 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372585 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372592 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372599 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372604 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372609 */   // GIR_Coverage, 9808,
     /*  372609 */   GIR_EraseRootFromParent_Done,
     /*  372610 */ // Label 5537: @372610
     /*  372610 */ GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(372705), // Rule ID 9809 //
     /*  372615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode3),
     /*  372618 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  372621 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372628 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372640 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372644 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372651 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372651 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372654 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372658 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372673 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372676 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372680 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372685 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372687 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372694 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372699 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372704 */   // GIR_Coverage, 9809,
     /*  372704 */   GIR_EraseRootFromParent_Done,
     /*  372705 */ // Label 5538: @372705
     /*  372705 */ GIM_Try, /*On fail goto*//*Label 5539*/ GIMT_Encode4(372800), // Rule ID 9810 //
     /*  372710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_UseTrue16WithSramECC_HwMode4),
     /*  372713 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  372716 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372723 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372731 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372735 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372746 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (EXTRACT_SUBREG:{ *:[i16] } (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset), lo16:{ *:[i32] })
     /*  372746 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  372749 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  372753 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  372758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372768 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  372771 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372775 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  372777 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  372780 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  372782 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  372789 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372794 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  372799 */   // GIR_Coverage, 9810,
     /*  372799 */   GIR_EraseRootFromParent_Done,
     /*  372800 */ // Label 5539: @372800
     /*  372800 */ GIM_Try, /*On fail goto*//*Label 5540*/ GIMT_Encode4(372865), // Rule ID 9836 //
     /*  372805 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  372808 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  372811 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372818 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372826 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372830 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372834 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372841 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  372841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  372844 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  372846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372856 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  372859 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372863 */   GIR_RootConstrainSelectedInstOperands,
     /*  372864 */   // GIR_Coverage, 9836,
     /*  372864 */   GIR_EraseRootFromParent_Done,
     /*  372865 */ // Label 5540: @372865
     /*  372865 */ GIM_Try, /*On fail goto*//*Label 5541*/ GIMT_Encode4(372930), // Rule ID 9837 //
     /*  372870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  372873 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  372876 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372891 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372895 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372899 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372906 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  372906 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  372909 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  372911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372921 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  372924 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372928 */   GIR_RootConstrainSelectedInstOperands,
     /*  372929 */   // GIR_Coverage, 9837,
     /*  372929 */   GIR_EraseRootFromParent_Done,
     /*  372930 */ // Label 5541: @372930
     /*  372930 */ GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(372995), // Rule ID 9838 //
     /*  372935 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  372938 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  372941 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  372948 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  372956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  372960 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  372964 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  372971 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  372971 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  372974 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  372976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  372981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  372986 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  372989 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  372993 */   GIR_RootConstrainSelectedInstOperands,
     /*  372994 */   // GIR_Coverage, 9838,
     /*  372994 */   GIR_EraseRootFromParent_Done,
     /*  372995 */ // Label 5542: @372995
     /*  372995 */ GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(373060), // Rule ID 9839 //
     /*  373000 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  373003 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373006 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373013 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373025 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373029 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373036 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373036 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373039 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373051 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373054 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373058 */   GIR_RootConstrainSelectedInstOperands,
     /*  373059 */   // GIR_Coverage, 9839,
     /*  373059 */   GIR_EraseRootFromParent_Done,
     /*  373060 */ // Label 5543: @373060
     /*  373060 */ GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(373125), // Rule ID 9840 //
     /*  373065 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  373068 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373071 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373101 */   // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373123 */   GIR_RootConstrainSelectedInstOperands,
     /*  373124 */   // GIR_Coverage, 9840,
     /*  373124 */   GIR_EraseRootFromParent_Done,
     /*  373125 */ // Label 5544: @373125
     /*  373125 */ GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(373190), // Rule ID 9860 //
     /*  373130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode0),
     /*  373133 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  373136 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373143 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373151 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373155 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373159 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373166 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373166 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373169 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373181 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373184 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373188 */   GIR_RootConstrainSelectedInstOperands,
     /*  373189 */   // GIR_Coverage, 9860,
     /*  373189 */   GIR_EraseRootFromParent_Done,
     /*  373190 */ // Label 5545: @373190
     /*  373190 */ GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(373255), // Rule ID 9861 //
     /*  373195 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode1),
     /*  373198 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  373201 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373208 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373216 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373220 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373224 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373231 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373231 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373234 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373249 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373253 */   GIR_RootConstrainSelectedInstOperands,
     /*  373254 */   // GIR_Coverage, 9861,
     /*  373254 */   GIR_EraseRootFromParent_Done,
     /*  373255 */ // Label 5546: @373255
     /*  373255 */ GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(373320), // Rule ID 9862 //
     /*  373260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode2),
     /*  373263 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  373266 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373273 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373296 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373299 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373314 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373318 */   GIR_RootConstrainSelectedInstOperands,
     /*  373319 */   // GIR_Coverage, 9862,
     /*  373319 */   GIR_EraseRootFromParent_Done,
     /*  373320 */ // Label 5547: @373320
     /*  373320 */ GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(373385), // Rule ID 9863 //
     /*  373325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode3),
     /*  373328 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  373331 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373338 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373350 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373354 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373361 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373376 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373383 */   GIR_RootConstrainSelectedInstOperands,
     /*  373384 */   // GIR_Coverage, 9863,
     /*  373384 */   GIR_EraseRootFromParent_Done,
     /*  373385 */ // Label 5548: @373385
     /*  373385 */ GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(373450), // Rule ID 9864 //
     /*  373390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatAddressSpace_UseRealTrue16Insts_HwMode4),
     /*  373393 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  373396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  373411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  373415 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373419 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  373426 */   // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_D16_t16:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_D16_t16),
     /*  373429 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  373431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  373436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373441 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373444 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373448 */   GIR_RootConstrainSelectedInstOperands,
     /*  373449 */   // GIR_Coverage, 9864,
     /*  373449 */   GIR_EraseRootFromParent_Done,
     /*  373450 */ // Label 5549: @373450
     /*  373450 */ GIM_Reject,
     /*  373451 */ // Label 5283: @373451
     /*  373451 */ GIM_Try, /*On fail goto*//*Label 5550*/ GIMT_Encode4(373519), // Rule ID 8658 //
     /*  373456 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373459 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373462 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373473 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373477 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
     /*  373481 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  373488 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  373488 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
     /*  373491 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  373498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  373503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  373508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  373513 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373517 */   GIR_RootConstrainSelectedInstOperands,
     /*  373518 */   // GIR_Coverage, 8658,
     /*  373518 */   GIR_EraseRootFromParent_Done,
     /*  373519 */ // Label 5550: @373519
     /*  373519 */ GIM_Try, /*On fail goto*//*Label 5551*/ GIMT_Encode4(373587), // Rule ID 8670 //
     /*  373524 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373527 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373530 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  373537 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373541 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373545 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
     /*  373549 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
     /*  373556 */   // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  373556 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
     /*  373559 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  373566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  373571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  373576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  373581 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373585 */   GIR_RootConstrainSelectedInstOperands,
     /*  373586 */   // GIR_Coverage, 8670,
     /*  373586 */   GIR_EraseRootFromParent_Done,
     /*  373587 */ // Label 5551: @373587
     /*  373587 */ GIM_Try, /*On fail goto*//*Label 5552*/ GIMT_Encode4(373648), // Rule ID 8656 //
     /*  373592 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373595 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373598 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373609 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373613 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
     /*  373617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  373624 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
     /*  373627 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  373634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373639 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373642 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373646 */   GIR_RootConstrainSelectedInstOperands,
     /*  373647 */   // GIR_Coverage, 8656,
     /*  373647 */   GIR_EraseRootFromParent_Done,
     /*  373648 */ // Label 5552: @373648
     /*  373648 */ GIM_Try, /*On fail goto*//*Label 5553*/ GIMT_Encode4(373709), // Rule ID 8668 //
     /*  373653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373656 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373659 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  373666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373670 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373674 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
     /*  373678 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  373685 */   // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
     /*  373685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
     /*  373688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  373695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  373700 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373703 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373707 */   GIR_RootConstrainSelectedInstOperands,
     /*  373708 */   // GIR_Coverage, 8668,
     /*  373708 */   GIR_EraseRootFromParent_Done,
     /*  373709 */ // Label 5553: @373709
     /*  373709 */ GIM_Try, /*On fail goto*//*Label 5554*/ GIMT_Encode4(373775), // Rule ID 8657 //
     /*  373714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373717 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373720 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373727 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373731 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373735 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
     /*  373739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  373746 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  373746 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
     /*  373749 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  373756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  373761 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  373769 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373773 */   GIR_RootConstrainSelectedInstOperands,
     /*  373774 */   // GIR_Coverage, 8657,
     /*  373774 */   GIR_EraseRootFromParent_Done,
     /*  373775 */ // Label 5554: @373775
     /*  373775 */ GIM_Try, /*On fail goto*//*Label 5555*/ GIMT_Encode4(373841), // Rule ID 8669 //
     /*  373780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373783 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373786 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  373793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373797 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373801 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
     /*  373805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
     /*  373812 */   // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, ?:{ *:[i32] }:$cpol)
     /*  373812 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
     /*  373815 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  373822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  373827 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  373835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373839 */   GIR_RootConstrainSelectedInstOperands,
     /*  373840 */   // GIR_Coverage, 8669,
     /*  373840 */   GIR_EraseRootFromParent_Done,
     /*  373841 */ // Label 5555: @373841
     /*  373841 */ GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(373894), // Rule ID 8659 //
     /*  373846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373849 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373852 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373863 */   // MIs[0] sbase
     /*  373863 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  373867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  373871 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
     /*  373875 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  373875 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
     /*  373878 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373880 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  373882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373885 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373888 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373892 */   GIR_RootConstrainSelectedInstOperands,
     /*  373893 */   // GIR_Coverage, 8659,
     /*  373893 */   GIR_EraseRootFromParent_Done,
     /*  373894 */ // Label 5556: @373894
     /*  373894 */ GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(373947), // Rule ID 8671 //
     /*  373899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  373902 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373905 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  373912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  373916 */   // MIs[0] sbase
     /*  373916 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  373920 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  373924 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
     /*  373928 */   // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  373928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
     /*  373931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  373933 */   GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  373935 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373938 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  373941 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  373945 */   GIR_RootConstrainSelectedInstOperands,
     /*  373946 */   // GIR_Coverage, 8671,
     /*  373946 */   GIR_EraseRootFromParent_Done,
     /*  373947 */ // Label 5557: @373947
     /*  373947 */ GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(374017), // Rule ID 25016 //
     /*  373952 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  373955 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  373958 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  373965 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  373970 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  373974 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  373978 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  373985 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  373985 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  373988 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  373990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  373995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374005 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374008 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374011 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374015 */   GIR_RootConstrainSelectedInstOperands,
     /*  374016 */   // GIR_Coverage, 25016,
     /*  374016 */   GIR_EraseRootFromParent_Done,
     /*  374017 */ // Label 5558: @374017
     /*  374017 */ GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(374087), // Rule ID 25017 //
     /*  374022 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  374025 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374028 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374035 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374048 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374055 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  374058 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374075 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374078 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374081 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374085 */   GIR_RootConstrainSelectedInstOperands,
     /*  374086 */   // GIR_Coverage, 25017,
     /*  374086 */   GIR_EraseRootFromParent_Done,
     /*  374087 */ // Label 5559: @374087
     /*  374087 */ GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(374157), // Rule ID 25018 //
     /*  374092 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  374095 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374098 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374105 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374110 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374114 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374118 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374125 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374125 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  374128 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374145 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374148 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374151 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374155 */   GIR_RootConstrainSelectedInstOperands,
     /*  374156 */   // GIR_Coverage, 25018,
     /*  374156 */   GIR_EraseRootFromParent_Done,
     /*  374157 */ // Label 5560: @374157
     /*  374157 */ GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(374227), // Rule ID 25019 //
     /*  374162 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  374165 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374168 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374175 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374184 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374188 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374195 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  374198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374205 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374215 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374218 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374221 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374225 */   GIR_RootConstrainSelectedInstOperands,
     /*  374226 */   // GIR_Coverage, 25019,
     /*  374226 */   GIR_EraseRootFromParent_Done,
     /*  374227 */ // Label 5561: @374227
     /*  374227 */ GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(374297), // Rule ID 25020 //
     /*  374232 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  374235 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374238 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374245 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374250 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374254 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374258 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374265 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374265 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  374268 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374285 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374288 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374291 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374295 */   GIR_RootConstrainSelectedInstOperands,
     /*  374296 */   // GIR_Coverage, 25020,
     /*  374296 */   GIR_EraseRootFromParent_Done,
     /*  374297 */ // Label 5562: @374297
     /*  374297 */ GIM_Try, /*On fail goto*//*Label 5563*/ GIMT_Encode4(374367), // Rule ID 25026 //
     /*  374302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  374305 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374308 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374315 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374335 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  374338 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374355 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374358 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374361 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374365 */   GIR_RootConstrainSelectedInstOperands,
     /*  374366 */   // GIR_Coverage, 25026,
     /*  374366 */   GIR_EraseRootFromParent_Done,
     /*  374367 */ // Label 5563: @374367
     /*  374367 */ GIM_Try, /*On fail goto*//*Label 5564*/ GIMT_Encode4(374437), // Rule ID 25027 //
     /*  374372 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  374375 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374378 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374385 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374394 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374398 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374405 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  374408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374425 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374428 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374431 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374435 */   GIR_RootConstrainSelectedInstOperands,
     /*  374436 */   // GIR_Coverage, 25027,
     /*  374436 */   GIR_EraseRootFromParent_Done,
     /*  374437 */ // Label 5564: @374437
     /*  374437 */ GIM_Try, /*On fail goto*//*Label 5565*/ GIMT_Encode4(374507), // Rule ID 25028 //
     /*  374442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  374445 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374448 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374455 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374464 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374468 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374475 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374475 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  374478 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374495 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374498 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374501 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374505 */   GIR_RootConstrainSelectedInstOperands,
     /*  374506 */   // GIR_Coverage, 25028,
     /*  374506 */   GIR_EraseRootFromParent_Done,
     /*  374507 */ // Label 5565: @374507
     /*  374507 */ GIM_Try, /*On fail goto*//*Label 5566*/ GIMT_Encode4(374577), // Rule ID 25029 //
     /*  374512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  374515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374518 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374525 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374530 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374534 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374538 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374545 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  374548 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374565 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374571 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374575 */   GIR_RootConstrainSelectedInstOperands,
     /*  374576 */   // GIR_Coverage, 25029,
     /*  374576 */   GIR_EraseRootFromParent_Done,
     /*  374577 */ // Label 5566: @374577
     /*  374577 */ GIM_Try, /*On fail goto*//*Label 5567*/ GIMT_Encode4(374647), // Rule ID 25030 //
     /*  374582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  374585 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374588 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  374595 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374604 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374608 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374615 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374615 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  374618 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374635 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374641 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374645 */   GIR_RootConstrainSelectedInstOperands,
     /*  374646 */   // GIR_Coverage, 25030,
     /*  374646 */   GIR_EraseRootFromParent_Done,
     /*  374647 */ // Label 5567: @374647
     /*  374647 */ GIM_Try, /*On fail goto*//*Label 5568*/ GIMT_Encode4(374717), // Rule ID 25136 //
     /*  374652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  374655 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374658 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  374665 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374670 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374674 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374678 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374685 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  374688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374705 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374711 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374715 */   GIR_RootConstrainSelectedInstOperands,
     /*  374716 */   // GIR_Coverage, 25136,
     /*  374716 */   GIR_EraseRootFromParent_Done,
     /*  374717 */ // Label 5568: @374717
     /*  374717 */ GIM_Try, /*On fail goto*//*Label 5569*/ GIMT_Encode4(374787), // Rule ID 25137 //
     /*  374722 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  374725 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374728 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  374735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374755 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  374758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374775 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374778 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374781 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374785 */   GIR_RootConstrainSelectedInstOperands,
     /*  374786 */   // GIR_Coverage, 25137,
     /*  374786 */   GIR_EraseRootFromParent_Done,
     /*  374787 */ // Label 5569: @374787
     /*  374787 */ GIM_Try, /*On fail goto*//*Label 5570*/ GIMT_Encode4(374857), // Rule ID 25138 //
     /*  374792 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  374795 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374798 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  374805 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374825 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  374828 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374845 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374855 */   GIR_RootConstrainSelectedInstOperands,
     /*  374856 */   // GIR_Coverage, 25138,
     /*  374856 */   GIR_EraseRootFromParent_Done,
     /*  374857 */ // Label 5570: @374857
     /*  374857 */ GIM_Try, /*On fail goto*//*Label 5571*/ GIMT_Encode4(374927), // Rule ID 25139 //
     /*  374862 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  374865 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374868 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  374875 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374880 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374884 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374888 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374895 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374895 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  374898 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374915 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374918 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374925 */   GIR_RootConstrainSelectedInstOperands,
     /*  374926 */   // GIR_Coverage, 25139,
     /*  374926 */   GIR_EraseRootFromParent_Done,
     /*  374927 */ // Label 5571: @374927
     /*  374927 */ GIM_Try, /*On fail goto*//*Label 5572*/ GIMT_Encode4(374997), // Rule ID 25140 //
     /*  374932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  374935 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  374938 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  374945 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  374950 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  374954 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  374958 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  374965 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  374965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  374968 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  374970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  374975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  374980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  374985 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374988 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  374991 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  374995 */   GIR_RootConstrainSelectedInstOperands,
     /*  374996 */   // GIR_Coverage, 25140,
     /*  374996 */   GIR_EraseRootFromParent_Done,
     /*  374997 */ // Label 5572: @374997
     /*  374997 */ GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(375067), // Rule ID 25146 //
     /*  375002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  375005 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375008 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375024 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375028 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  375035 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  375035 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  375038 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  375040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  375045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  375050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375055 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375065 */   GIR_RootConstrainSelectedInstOperands,
     /*  375066 */   // GIR_Coverage, 25146,
     /*  375066 */   GIR_EraseRootFromParent_Done,
     /*  375067 */ // Label 5573: @375067
     /*  375067 */ GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(375137), // Rule ID 25147 //
     /*  375072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  375075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375078 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375085 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  375105 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  375105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  375108 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  375110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  375115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  375120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375125 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375128 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375131 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375135 */   GIR_RootConstrainSelectedInstOperands,
     /*  375136 */   // GIR_Coverage, 25147,
     /*  375136 */   GIR_EraseRootFromParent_Done,
     /*  375137 */ // Label 5574: @375137
     /*  375137 */ GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(375207), // Rule ID 25148 //
     /*  375142 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  375145 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375148 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375155 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375160 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375164 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375168 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  375175 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  375175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  375178 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  375180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  375185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  375190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375195 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375198 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375201 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375205 */   GIR_RootConstrainSelectedInstOperands,
     /*  375206 */   // GIR_Coverage, 25148,
     /*  375206 */   GIR_EraseRootFromParent_Done,
     /*  375207 */ // Label 5575: @375207
     /*  375207 */ GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(375277), // Rule ID 25149 //
     /*  375212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  375215 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375218 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375225 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375230 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375234 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375238 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  375245 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  375245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  375248 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  375250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  375255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  375260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375265 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375268 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375271 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375275 */   GIR_RootConstrainSelectedInstOperands,
     /*  375276 */   // GIR_Coverage, 25149,
     /*  375276 */   GIR_EraseRootFromParent_Done,
     /*  375277 */ // Label 5576: @375277
     /*  375277 */ GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(375347), // Rule ID 25150 //
     /*  375282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  375285 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375288 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375304 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375308 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  375315 */   // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  375315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  375318 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  375320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  375325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  375330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375335 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375338 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  375341 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375345 */   GIR_RootConstrainSelectedInstOperands,
     /*  375346 */   // GIR_Coverage, 25150,
     /*  375346 */   GIR_EraseRootFromParent_Done,
     /*  375347 */ // Label 5577: @375347
     /*  375347 */ GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(375416), // Rule ID 13855 //
     /*  375352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  375355 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375358 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  375365 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375374 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375378 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375385 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  375388 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375410 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375414 */   GIR_RootConstrainSelectedInstOperands,
     /*  375415 */   // GIR_Coverage, 13855,
     /*  375415 */   GIR_EraseRootFromParent_Done,
     /*  375416 */ // Label 5578: @375416
     /*  375416 */ GIM_Try, /*On fail goto*//*Label 5579*/ GIMT_Encode4(375485), // Rule ID 13856 //
     /*  375421 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  375424 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375427 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  375434 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375443 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375447 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375454 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375454 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  375457 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375479 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375483 */   GIR_RootConstrainSelectedInstOperands,
     /*  375484 */   // GIR_Coverage, 13856,
     /*  375484 */   GIR_EraseRootFromParent_Done,
     /*  375485 */ // Label 5579: @375485
     /*  375485 */ GIM_Try, /*On fail goto*//*Label 5580*/ GIMT_Encode4(375554), // Rule ID 13857 //
     /*  375490 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  375493 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  375503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375512 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375516 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375523 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  375526 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375548 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375552 */   GIR_RootConstrainSelectedInstOperands,
     /*  375553 */   // GIR_Coverage, 13857,
     /*  375553 */   GIR_EraseRootFromParent_Done,
     /*  375554 */ // Label 5580: @375554
     /*  375554 */ GIM_Try, /*On fail goto*//*Label 5581*/ GIMT_Encode4(375623), // Rule ID 13858 //
     /*  375559 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  375562 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375565 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  375572 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375577 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375581 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375585 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375592 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375592 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  375595 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375617 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375621 */   GIR_RootConstrainSelectedInstOperands,
     /*  375622 */   // GIR_Coverage, 13858,
     /*  375622 */   GIR_EraseRootFromParent_Done,
     /*  375623 */ // Label 5581: @375623
     /*  375623 */ GIM_Try, /*On fail goto*//*Label 5582*/ GIMT_Encode4(375692), // Rule ID 13859 //
     /*  375628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  375631 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375634 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  375641 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375650 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375654 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375661 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375661 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
     /*  375664 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375690 */   GIR_RootConstrainSelectedInstOperands,
     /*  375691 */   // GIR_Coverage, 13859,
     /*  375691 */   GIR_EraseRootFromParent_Done,
     /*  375692 */ // Label 5582: @375692
     /*  375692 */ GIM_Try, /*On fail goto*//*Label 5583*/ GIMT_Encode4(375761), // Rule ID 13900 //
     /*  375697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  375700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375703 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375710 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375719 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375723 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375730 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375730 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  375733 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375759 */   GIR_RootConstrainSelectedInstOperands,
     /*  375760 */   // GIR_Coverage, 13900,
     /*  375760 */   GIR_EraseRootFromParent_Done,
     /*  375761 */ // Label 5583: @375761
     /*  375761 */ GIM_Try, /*On fail goto*//*Label 5584*/ GIMT_Encode4(375830), // Rule ID 13901 //
     /*  375766 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  375769 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375772 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375779 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375784 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375788 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375792 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375799 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375799 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  375802 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375824 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375828 */   GIR_RootConstrainSelectedInstOperands,
     /*  375829 */   // GIR_Coverage, 13901,
     /*  375829 */   GIR_EraseRootFromParent_Done,
     /*  375830 */ // Label 5584: @375830
     /*  375830 */ GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(375899), // Rule ID 13902 //
     /*  375835 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  375838 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375841 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375848 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375853 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375857 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375861 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375868 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375868 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  375871 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375893 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375897 */   GIR_RootConstrainSelectedInstOperands,
     /*  375898 */   // GIR_Coverage, 13902,
     /*  375898 */   GIR_EraseRootFromParent_Done,
     /*  375899 */ // Label 5585: @375899
     /*  375899 */ GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(375968), // Rule ID 13903 //
     /*  375904 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  375907 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375910 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375917 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375926 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375930 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  375937 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  375937 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  375940 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  375942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  375947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  375952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  375957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  375962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  375966 */   GIR_RootConstrainSelectedInstOperands,
     /*  375967 */   // GIR_Coverage, 13903,
     /*  375967 */   GIR_EraseRootFromParent_Done,
     /*  375968 */ // Label 5586: @375968
     /*  375968 */ GIM_Try, /*On fail goto*//*Label 5587*/ GIMT_Encode4(376037), // Rule ID 13904 //
     /*  375973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  375976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  375979 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  375986 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  375991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  375995 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  375999 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  376006 */   // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  376006 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
     /*  376009 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  376016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  376021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  376026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  376031 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376035 */   GIR_RootConstrainSelectedInstOperands,
     /*  376036 */   // GIR_Coverage, 13904,
     /*  376036 */   GIR_EraseRootFromParent_Done,
     /*  376037 */ // Label 5587: @376037
     /*  376037 */ GIM_Try, /*On fail goto*//*Label 5588*/ GIMT_Encode4(376099), // Rule ID 13850 //
     /*  376042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  376045 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376048 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376055 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376060 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376064 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376068 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376075 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  376078 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376090 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376093 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376097 */   GIR_RootConstrainSelectedInstOperands,
     /*  376098 */   // GIR_Coverage, 13850,
     /*  376098 */   GIR_EraseRootFromParent_Done,
     /*  376099 */ // Label 5588: @376099
     /*  376099 */ GIM_Try, /*On fail goto*//*Label 5589*/ GIMT_Encode4(376161), // Rule ID 13851 //
     /*  376104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  376107 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376122 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376126 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376130 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376137 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376137 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  376140 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376152 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376155 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376159 */   GIR_RootConstrainSelectedInstOperands,
     /*  376160 */   // GIR_Coverage, 13851,
     /*  376160 */   GIR_EraseRootFromParent_Done,
     /*  376161 */ // Label 5589: @376161
     /*  376161 */ GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(376223), // Rule ID 13852 //
     /*  376166 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  376169 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376172 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376179 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376188 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376192 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376199 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  376202 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376221 */   GIR_RootConstrainSelectedInstOperands,
     /*  376222 */   // GIR_Coverage, 13852,
     /*  376222 */   GIR_EraseRootFromParent_Done,
     /*  376223 */ // Label 5590: @376223
     /*  376223 */ GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(376285), // Rule ID 13853 //
     /*  376228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  376231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376261 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  376264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376283 */   GIR_RootConstrainSelectedInstOperands,
     /*  376284 */   // GIR_Coverage, 13853,
     /*  376284 */   GIR_EraseRootFromParent_Done,
     /*  376285 */ // Label 5591: @376285
     /*  376285 */ GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(376347), // Rule ID 13854 //
     /*  376290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  376293 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376308 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376312 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376316 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376323 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376323 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
     /*  376326 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376338 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376341 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376345 */   GIR_RootConstrainSelectedInstOperands,
     /*  376346 */   // GIR_Coverage, 13854,
     /*  376346 */   GIR_EraseRootFromParent_Done,
     /*  376347 */ // Label 5592: @376347
     /*  376347 */ GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(376409), // Rule ID 13895 //
     /*  376352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  376355 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376358 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  376365 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376374 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376378 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376385 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  376388 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376400 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376403 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376407 */   GIR_RootConstrainSelectedInstOperands,
     /*  376408 */   // GIR_Coverage, 13895,
     /*  376408 */   GIR_EraseRootFromParent_Done,
     /*  376409 */ // Label 5593: @376409
     /*  376409 */ GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(376471), // Rule ID 13896 //
     /*  376414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  376417 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376420 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  376427 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376432 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376436 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376440 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376447 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  376450 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376462 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376465 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376469 */   GIR_RootConstrainSelectedInstOperands,
     /*  376470 */   // GIR_Coverage, 13896,
     /*  376470 */   GIR_EraseRootFromParent_Done,
     /*  376471 */ // Label 5594: @376471
     /*  376471 */ GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(376533), // Rule ID 13897 //
     /*  376476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  376479 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376482 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  376489 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376494 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376498 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376502 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376509 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376509 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  376512 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376524 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376527 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376531 */   GIR_RootConstrainSelectedInstOperands,
     /*  376532 */   // GIR_Coverage, 13897,
     /*  376532 */   GIR_EraseRootFromParent_Done,
     /*  376533 */ // Label 5595: @376533
     /*  376533 */ GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(376595), // Rule ID 13898 //
     /*  376538 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  376541 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376544 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  376551 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376560 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376564 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376571 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  376574 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376586 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376589 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376593 */   GIR_RootConstrainSelectedInstOperands,
     /*  376594 */   // GIR_Coverage, 13898,
     /*  376594 */   GIR_EraseRootFromParent_Done,
     /*  376595 */ // Label 5596: @376595
     /*  376595 */ GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(376657), // Rule ID 13899 //
     /*  376600 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  376603 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376606 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  376613 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376622 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376626 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  376633 */   // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  376633 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
     /*  376636 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  376643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376648 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376651 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376655 */   GIR_RootConstrainSelectedInstOperands,
     /*  376656 */   // GIR_Coverage, 13899,
     /*  376656 */   GIR_EraseRootFromParent_Done,
     /*  376657 */ // Label 5597: @376657
     /*  376657 */ GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(376719), // Rule ID 13845 //
     /*  376662 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  376665 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376668 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376675 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  376695 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  376695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  376698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  376705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376710 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376713 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376717 */   GIR_RootConstrainSelectedInstOperands,
     /*  376718 */   // GIR_Coverage, 13845,
     /*  376718 */   GIR_EraseRootFromParent_Done,
     /*  376719 */ // Label 5598: @376719
     /*  376719 */ GIM_Try, /*On fail goto*//*Label 5599*/ GIMT_Encode4(376781), // Rule ID 13846 //
     /*  376724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  376727 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376730 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376737 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376746 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376750 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  376757 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  376757 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  376760 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  376767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376772 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376775 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376779 */   GIR_RootConstrainSelectedInstOperands,
     /*  376780 */   // GIR_Coverage, 13846,
     /*  376780 */   GIR_EraseRootFromParent_Done,
     /*  376781 */ // Label 5599: @376781
     /*  376781 */ GIM_Try, /*On fail goto*//*Label 5600*/ GIMT_Encode4(376843), // Rule ID 13847 //
     /*  376786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  376789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376792 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376804 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376808 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376812 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  376819 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  376819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  376822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  376829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376834 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376837 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376841 */   GIR_RootConstrainSelectedInstOperands,
     /*  376842 */   // GIR_Coverage, 13847,
     /*  376842 */   GIR_EraseRootFromParent_Done,
     /*  376843 */ // Label 5600: @376843
     /*  376843 */ GIM_Try, /*On fail goto*//*Label 5601*/ GIMT_Encode4(376905), // Rule ID 13848 //
     /*  376848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  376851 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376854 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376861 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  376881 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  376881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  376884 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  376891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376903 */   GIR_RootConstrainSelectedInstOperands,
     /*  376904 */   // GIR_Coverage, 13848,
     /*  376904 */   GIR_EraseRootFromParent_Done,
     /*  376905 */ // Label 5601: @376905
     /*  376905 */ GIM_Try, /*On fail goto*//*Label 5602*/ GIMT_Encode4(376967), // Rule ID 13849 //
     /*  376910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  376913 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  376923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376928 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376932 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376936 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  376943 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  376943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
     /*  376946 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  376948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  376953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  376958 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  376961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  376965 */   GIR_RootConstrainSelectedInstOperands,
     /*  376966 */   // GIR_Coverage, 13849,
     /*  376966 */   GIR_EraseRootFromParent_Done,
     /*  376967 */ // Label 5602: @376967
     /*  376967 */ GIM_Try, /*On fail goto*//*Label 5603*/ GIMT_Encode4(377029), // Rule ID 13890 //
     /*  376972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  376975 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  376978 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  376985 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  376990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  376994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  376998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  377005 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  377005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  377008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  377010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  377015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  377020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377027 */   GIR_RootConstrainSelectedInstOperands,
     /*  377028 */   // GIR_Coverage, 13890,
     /*  377028 */   GIR_EraseRootFromParent_Done,
     /*  377029 */ // Label 5603: @377029
     /*  377029 */ GIM_Try, /*On fail goto*//*Label 5604*/ GIMT_Encode4(377091), // Rule ID 13891 //
     /*  377034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  377037 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  377040 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  377047 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  377052 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377056 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377060 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  377067 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  377067 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  377070 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  377072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  377077 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  377082 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377085 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377089 */   GIR_RootConstrainSelectedInstOperands,
     /*  377090 */   // GIR_Coverage, 13891,
     /*  377090 */   GIR_EraseRootFromParent_Done,
     /*  377091 */ // Label 5604: @377091
     /*  377091 */ GIM_Try, /*On fail goto*//*Label 5605*/ GIMT_Encode4(377153), // Rule ID 13892 //
     /*  377096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  377099 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  377102 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  377109 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  377114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377118 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377122 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  377129 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  377129 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  377132 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  377134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  377139 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  377144 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377147 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377151 */   GIR_RootConstrainSelectedInstOperands,
     /*  377152 */   // GIR_Coverage, 13892,
     /*  377152 */   GIR_EraseRootFromParent_Done,
     /*  377153 */ // Label 5605: @377153
     /*  377153 */ GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(377215), // Rule ID 13893 //
     /*  377158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  377161 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  377164 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  377171 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  377176 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  377191 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  377191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  377194 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  377196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  377201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  377206 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377209 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377213 */   GIR_RootConstrainSelectedInstOperands,
     /*  377214 */   // GIR_Coverage, 13893,
     /*  377214 */   GIR_EraseRootFromParent_Done,
     /*  377215 */ // Label 5606: @377215
     /*  377215 */ GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(377277), // Rule ID 13894 //
     /*  377220 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  377223 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  377226 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  377233 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  377238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377242 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377246 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  377253 */   // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  377253 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
     /*  377256 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  377258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  377263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  377268 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377271 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377275 */   GIR_RootConstrainSelectedInstOperands,
     /*  377276 */   // GIR_Coverage, 13894,
     /*  377276 */   GIR_EraseRootFromParent_Done,
     /*  377277 */ // Label 5607: @377277
     /*  377277 */ GIM_Try, /*On fail goto*//*Label 5608*/ GIMT_Encode4(377354), // Rule ID 15068 //
     /*  377282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  377285 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377288 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377306 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377310 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377317 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  377320 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377342 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377345 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377348 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377352 */   GIR_RootConstrainSelectedInstOperands,
     /*  377353 */   // GIR_Coverage, 15068,
     /*  377353 */   GIR_EraseRootFromParent_Done,
     /*  377354 */ // Label 5608: @377354
     /*  377354 */ GIM_Try, /*On fail goto*//*Label 5609*/ GIMT_Encode4(377431), // Rule ID 15069 //
     /*  377359 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  377362 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377365 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377372 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377383 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377387 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377394 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377394 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  377397 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377429 */   GIR_RootConstrainSelectedInstOperands,
     /*  377430 */   // GIR_Coverage, 15069,
     /*  377430 */   GIR_EraseRootFromParent_Done,
     /*  377431 */ // Label 5609: @377431
     /*  377431 */ GIM_Try, /*On fail goto*//*Label 5610*/ GIMT_Encode4(377508), // Rule ID 15070 //
     /*  377436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  377439 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377442 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377471 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  377474 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377506 */   GIR_RootConstrainSelectedInstOperands,
     /*  377507 */   // GIR_Coverage, 15070,
     /*  377507 */   GIR_EraseRootFromParent_Done,
     /*  377508 */ // Label 5610: @377508
     /*  377508 */ GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(377585), // Rule ID 15071 //
     /*  377513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  377516 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377519 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377526 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377537 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377541 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377548 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  377551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377573 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377579 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377583 */   GIR_RootConstrainSelectedInstOperands,
     /*  377584 */   // GIR_Coverage, 15071,
     /*  377584 */   GIR_EraseRootFromParent_Done,
     /*  377585 */ // Label 5611: @377585
     /*  377585 */ GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(377662), // Rule ID 15072 //
     /*  377590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  377593 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377610 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377614 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377618 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377625 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  377628 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377650 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377653 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377656 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377660 */   GIR_RootConstrainSelectedInstOperands,
     /*  377661 */   // GIR_Coverage, 15072,
     /*  377661 */   GIR_EraseRootFromParent_Done,
     /*  377662 */ // Label 5612: @377662
     /*  377662 */ GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(377739), // Rule ID 15078 //
     /*  377667 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  377670 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377673 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377691 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377695 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377702 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377702 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  377705 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377727 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377730 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377733 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377737 */   GIR_RootConstrainSelectedInstOperands,
     /*  377738 */   // GIR_Coverage, 15078,
     /*  377738 */   GIR_EraseRootFromParent_Done,
     /*  377739 */ // Label 5613: @377739
     /*  377739 */ GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(377816), // Rule ID 15079 //
     /*  377744 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  377747 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377750 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377757 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377764 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377768 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377772 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377779 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377779 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  377782 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377804 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377807 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377810 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377814 */   GIR_RootConstrainSelectedInstOperands,
     /*  377815 */   // GIR_Coverage, 15079,
     /*  377815 */   GIR_EraseRootFromParent_Done,
     /*  377816 */ // Label 5614: @377816
     /*  377816 */ GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(377893), // Rule ID 15080 //
     /*  377821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  377824 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377827 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377845 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377849 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377856 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377856 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  377859 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377881 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377891 */   GIR_RootConstrainSelectedInstOperands,
     /*  377892 */   // GIR_Coverage, 15080,
     /*  377892 */   GIR_EraseRootFromParent_Done,
     /*  377893 */ // Label 5615: @377893
     /*  377893 */ GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(377970), // Rule ID 15081 //
     /*  377898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  377901 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377904 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377911 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377918 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377922 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  377926 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  377933 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  377933 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  377936 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  377938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  377943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  377948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  377953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  377958 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377961 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  377964 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  377968 */   GIR_RootConstrainSelectedInstOperands,
     /*  377969 */   // GIR_Coverage, 15081,
     /*  377969 */   GIR_EraseRootFromParent_Done,
     /*  377970 */ // Label 5616: @377970
     /*  377970 */ GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(378047), // Rule ID 15082 //
     /*  377975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  377978 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  377981 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  377988 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  377995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  377999 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378003 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378010 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378010 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  378013 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378035 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378038 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378041 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378045 */   GIR_RootConstrainSelectedInstOperands,
     /*  378046 */   // GIR_Coverage, 15082,
     /*  378046 */   GIR_EraseRootFromParent_Done,
     /*  378047 */ // Label 5617: @378047
     /*  378047 */ GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(378124), // Rule ID 15108 //
     /*  378052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  378055 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378058 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378076 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378080 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378087 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  378090 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378112 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378115 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378118 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378122 */   GIR_RootConstrainSelectedInstOperands,
     /*  378123 */   // GIR_Coverage, 15108,
     /*  378123 */   GIR_EraseRootFromParent_Done,
     /*  378124 */ // Label 5618: @378124
     /*  378124 */ GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(378201), // Rule ID 15109 //
     /*  378129 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  378132 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378135 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378142 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378149 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378153 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378157 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378164 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378164 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  378167 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378189 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378192 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378195 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378199 */   GIR_RootConstrainSelectedInstOperands,
     /*  378200 */   // GIR_Coverage, 15109,
     /*  378200 */   GIR_EraseRootFromParent_Done,
     /*  378201 */ // Label 5619: @378201
     /*  378201 */ GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(378278), // Rule ID 15110 //
     /*  378206 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  378209 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378212 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378219 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378241 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  378244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378266 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378276 */   GIR_RootConstrainSelectedInstOperands,
     /*  378277 */   // GIR_Coverage, 15110,
     /*  378277 */   GIR_EraseRootFromParent_Done,
     /*  378278 */ // Label 5620: @378278
     /*  378278 */ GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(378355), // Rule ID 15111 //
     /*  378283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  378286 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378289 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378296 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378307 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378311 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378318 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378318 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  378321 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378343 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378346 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378349 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378353 */   GIR_RootConstrainSelectedInstOperands,
     /*  378354 */   // GIR_Coverage, 15111,
     /*  378354 */   GIR_EraseRootFromParent_Done,
     /*  378355 */ // Label 5621: @378355
     /*  378355 */ GIM_Try, /*On fail goto*//*Label 5622*/ GIMT_Encode4(378432), // Rule ID 15112 //
     /*  378360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  378363 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378366 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378373 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378384 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378388 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378395 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378395 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  378398 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378420 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378423 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378426 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378430 */   GIR_RootConstrainSelectedInstOperands,
     /*  378431 */   // GIR_Coverage, 15112,
     /*  378431 */   GIR_EraseRootFromParent_Done,
     /*  378432 */ // Label 5622: @378432
     /*  378432 */ GIM_Try, /*On fail goto*//*Label 5623*/ GIMT_Encode4(378509), // Rule ID 15118 //
     /*  378437 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  378440 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378443 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378472 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  378475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378497 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378500 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378507 */   GIR_RootConstrainSelectedInstOperands,
     /*  378508 */   // GIR_Coverage, 15118,
     /*  378508 */   GIR_EraseRootFromParent_Done,
     /*  378509 */ // Label 5623: @378509
     /*  378509 */ GIM_Try, /*On fail goto*//*Label 5624*/ GIMT_Encode4(378586), // Rule ID 15119 //
     /*  378514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  378517 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378520 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378527 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378538 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378542 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378549 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378549 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  378552 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378574 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378577 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378580 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378584 */   GIR_RootConstrainSelectedInstOperands,
     /*  378585 */   // GIR_Coverage, 15119,
     /*  378585 */   GIR_EraseRootFromParent_Done,
     /*  378586 */ // Label 5624: @378586
     /*  378586 */ GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(378663), // Rule ID 15120 //
     /*  378591 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  378594 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378597 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378604 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378611 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378615 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378619 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378626 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  378629 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378651 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378654 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378661 */   GIR_RootConstrainSelectedInstOperands,
     /*  378662 */   // GIR_Coverage, 15120,
     /*  378662 */   GIR_EraseRootFromParent_Done,
     /*  378663 */ // Label 5625: @378663
     /*  378663 */ GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(378740), // Rule ID 15121 //
     /*  378668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  378671 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378674 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378681 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378692 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378696 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378703 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378703 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  378706 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378728 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378731 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378734 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378738 */   GIR_RootConstrainSelectedInstOperands,
     /*  378739 */   // GIR_Coverage, 15121,
     /*  378739 */   GIR_EraseRootFromParent_Done,
     /*  378740 */ // Label 5626: @378740
     /*  378740 */ GIM_Try, /*On fail goto*//*Label 5627*/ GIMT_Encode4(378817), // Rule ID 15122 //
     /*  378745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  378748 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  378751 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  378758 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378769 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378773 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378780 */   // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378780 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  378783 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378805 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378808 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378811 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378815 */   GIR_RootConstrainSelectedInstOperands,
     /*  378816 */   // GIR_Coverage, 15122,
     /*  378816 */   GIR_EraseRootFromParent_Done,
     /*  378817 */ // Label 5627: @378817
     /*  378817 */ GIM_Try, /*On fail goto*//*Label 5628*/ GIMT_Encode4(378894), // Rule ID 15208 //
     /*  378822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  378825 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  378828 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  378835 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378846 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378850 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378857 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  378860 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378885 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378888 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378892 */   GIR_RootConstrainSelectedInstOperands,
     /*  378893 */   // GIR_Coverage, 15208,
     /*  378893 */   GIR_EraseRootFromParent_Done,
     /*  378894 */ // Label 5628: @378894
     /*  378894 */ GIM_Try, /*On fail goto*//*Label 5629*/ GIMT_Encode4(378971), // Rule ID 15209 //
     /*  378899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  378902 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  378905 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  378912 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378919 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  378923 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  378927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  378934 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  378934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  378937 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  378939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  378944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  378949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  378954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  378959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378962 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  378965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  378969 */   GIR_RootConstrainSelectedInstOperands,
     /*  378970 */   // GIR_Coverage, 15209,
     /*  378970 */   GIR_EraseRootFromParent_Done,
     /*  378971 */ // Label 5629: @378971
     /*  378971 */ GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(379048), // Rule ID 15210 //
     /*  378976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  378979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  378982 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  378989 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  378996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379000 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379004 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379011 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  379014 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379036 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379046 */   GIR_RootConstrainSelectedInstOperands,
     /*  379047 */   // GIR_Coverage, 15210,
     /*  379047 */   GIR_EraseRootFromParent_Done,
     /*  379048 */ // Label 5630: @379048
     /*  379048 */ GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(379125), // Rule ID 15211 //
     /*  379053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  379056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379059 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379066 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379077 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379088 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  379091 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379113 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379123 */   GIR_RootConstrainSelectedInstOperands,
     /*  379124 */   // GIR_Coverage, 15211,
     /*  379124 */   GIR_EraseRootFromParent_Done,
     /*  379125 */ // Label 5631: @379125
     /*  379125 */ GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(379202), // Rule ID 15212 //
     /*  379130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  379133 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379136 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379143 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379150 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379158 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379165 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379165 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  379168 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379190 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379196 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379200 */   GIR_RootConstrainSelectedInstOperands,
     /*  379201 */   // GIR_Coverage, 15212,
     /*  379201 */   GIR_EraseRootFromParent_Done,
     /*  379202 */ // Label 5632: @379202
     /*  379202 */ GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(379279), // Rule ID 15218 //
     /*  379207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  379210 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379213 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379220 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379227 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379231 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379235 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379242 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379242 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  379245 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379267 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379270 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379273 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379277 */   GIR_RootConstrainSelectedInstOperands,
     /*  379278 */   // GIR_Coverage, 15218,
     /*  379278 */   GIR_EraseRootFromParent_Done,
     /*  379279 */ // Label 5633: @379279
     /*  379279 */ GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(379356), // Rule ID 15219 //
     /*  379284 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  379287 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379290 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379297 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379308 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379312 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379319 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379319 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  379322 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379344 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379347 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379350 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379354 */   GIR_RootConstrainSelectedInstOperands,
     /*  379355 */   // GIR_Coverage, 15219,
     /*  379355 */   GIR_EraseRootFromParent_Done,
     /*  379356 */ // Label 5634: @379356
     /*  379356 */ GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(379433), // Rule ID 15220 //
     /*  379361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  379364 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379367 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379374 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379396 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  379399 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379421 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379427 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379431 */   GIR_RootConstrainSelectedInstOperands,
     /*  379432 */   // GIR_Coverage, 15220,
     /*  379432 */   GIR_EraseRootFromParent_Done,
     /*  379433 */ // Label 5635: @379433
     /*  379433 */ GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(379510), // Rule ID 15221 //
     /*  379438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  379441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379444 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379451 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379462 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379466 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379473 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  379476 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379498 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379501 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379504 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379508 */   GIR_RootConstrainSelectedInstOperands,
     /*  379509 */   // GIR_Coverage, 15221,
     /*  379509 */   GIR_EraseRootFromParent_Done,
     /*  379510 */ // Label 5636: @379510
     /*  379510 */ GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(379587), // Rule ID 15222 //
     /*  379515 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  379518 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379521 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  379528 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379539 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379543 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379550 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
     /*  379553 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379575 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379578 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379581 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379585 */   GIR_RootConstrainSelectedInstOperands,
     /*  379586 */   // GIR_Coverage, 15222,
     /*  379586 */   GIR_EraseRootFromParent_Done,
     /*  379587 */ // Label 5637: @379587
     /*  379587 */ GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(379664), // Rule ID 15308 //
     /*  379592 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  379595 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379598 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  379605 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379612 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379616 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379620 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379627 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379627 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  379630 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379652 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379655 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379662 */   GIR_RootConstrainSelectedInstOperands,
     /*  379663 */   // GIR_Coverage, 15308,
     /*  379663 */   GIR_EraseRootFromParent_Done,
     /*  379664 */ // Label 5638: @379664
     /*  379664 */ GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(379741), // Rule ID 15309 //
     /*  379669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  379672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379675 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  379682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379693 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379697 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379704 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379704 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  379707 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379729 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379732 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379735 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379739 */   GIR_RootConstrainSelectedInstOperands,
     /*  379740 */   // GIR_Coverage, 15309,
     /*  379740 */   GIR_EraseRootFromParent_Done,
     /*  379741 */ // Label 5639: @379741
     /*  379741 */ GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(379818), // Rule ID 15310 //
     /*  379746 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  379749 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379752 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  379759 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379781 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  379784 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379806 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379809 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379812 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379816 */   GIR_RootConstrainSelectedInstOperands,
     /*  379817 */   // GIR_Coverage, 15310,
     /*  379817 */   GIR_EraseRootFromParent_Done,
     /*  379818 */ // Label 5640: @379818
     /*  379818 */ GIM_Try, /*On fail goto*//*Label 5641*/ GIMT_Encode4(379895), // Rule ID 15311 //
     /*  379823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  379826 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379829 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  379836 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379847 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379851 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379858 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379858 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  379861 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379883 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379886 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379889 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379893 */   GIR_RootConstrainSelectedInstOperands,
     /*  379894 */   // GIR_Coverage, 15311,
     /*  379894 */   GIR_EraseRootFromParent_Done,
     /*  379895 */ // Label 5641: @379895
     /*  379895 */ GIM_Try, /*On fail goto*//*Label 5642*/ GIMT_Encode4(379972), // Rule ID 15312 //
     /*  379900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  379903 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379906 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  379913 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379920 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  379924 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  379928 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  379935 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  379935 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  379938 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  379940 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  379945 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  379950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  379955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  379960 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379963 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  379966 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  379970 */   GIR_RootConstrainSelectedInstOperands,
     /*  379971 */   // GIR_Coverage, 15312,
     /*  379971 */   GIR_EraseRootFromParent_Done,
     /*  379972 */ // Label 5642: @379972
     /*  379972 */ GIM_Try, /*On fail goto*//*Label 5643*/ GIMT_Encode4(380049), // Rule ID 15318 //
     /*  379977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  379980 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  379983 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  379990 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  379997 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380001 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380005 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380012 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  380012 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  380015 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380040 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380047 */   GIR_RootConstrainSelectedInstOperands,
     /*  380048 */   // GIR_Coverage, 15318,
     /*  380048 */   GIR_EraseRootFromParent_Done,
     /*  380049 */ // Label 5643: @380049
     /*  380049 */ GIM_Try, /*On fail goto*//*Label 5644*/ GIMT_Encode4(380126), // Rule ID 15319 //
     /*  380054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  380057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380060 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380067 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380082 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380089 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  380089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  380092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380114 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380124 */   GIR_RootConstrainSelectedInstOperands,
     /*  380125 */   // GIR_Coverage, 15319,
     /*  380125 */   GIR_EraseRootFromParent_Done,
     /*  380126 */ // Label 5644: @380126
     /*  380126 */ GIM_Try, /*On fail goto*//*Label 5645*/ GIMT_Encode4(380203), // Rule ID 15320 //
     /*  380131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  380134 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380137 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380144 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380151 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380155 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380159 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380166 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  380166 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  380169 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380194 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380197 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380201 */   GIR_RootConstrainSelectedInstOperands,
     /*  380202 */   // GIR_Coverage, 15320,
     /*  380202 */   GIR_EraseRootFromParent_Done,
     /*  380203 */ // Label 5645: @380203
     /*  380203 */ GIM_Try, /*On fail goto*//*Label 5646*/ GIMT_Encode4(380280), // Rule ID 15321 //
     /*  380208 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  380211 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380214 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380221 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380228 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380232 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380236 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380243 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  380243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  380246 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380268 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380271 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380278 */   GIR_RootConstrainSelectedInstOperands,
     /*  380279 */   // GIR_Coverage, 15321,
     /*  380279 */   GIR_EraseRootFromParent_Done,
     /*  380280 */ // Label 5646: @380280
     /*  380280 */ GIM_Try, /*On fail goto*//*Label 5647*/ GIMT_Encode4(380357), // Rule ID 15322 //
     /*  380285 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  380288 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380291 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380298 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380313 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380320 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  380320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
     /*  380323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380345 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380348 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380355 */   GIR_RootConstrainSelectedInstOperands,
     /*  380356 */   // GIR_Coverage, 15322,
     /*  380356 */   GIR_EraseRootFromParent_Done,
     /*  380357 */ // Label 5647: @380357
     /*  380357 */ GIM_Try, /*On fail goto*//*Label 5648*/ GIMT_Encode4(380433), // Rule ID 24861 //
     /*  380362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  380365 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  380375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380396 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  380399 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380421 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380427 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380431 */   GIR_RootConstrainSelectedInstOperands,
     /*  380432 */   // GIR_Coverage, 24861,
     /*  380432 */   GIR_EraseRootFromParent_Done,
     /*  380433 */ // Label 5648: @380433
     /*  380433 */ GIM_Try, /*On fail goto*//*Label 5649*/ GIMT_Encode4(380509), // Rule ID 24862 //
     /*  380438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  380441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380444 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  380451 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380472 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  380475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380497 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380500 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380507 */   GIR_RootConstrainSelectedInstOperands,
     /*  380508 */   // GIR_Coverage, 24862,
     /*  380508 */   GIR_EraseRootFromParent_Done,
     /*  380509 */ // Label 5649: @380509
     /*  380509 */ GIM_Try, /*On fail goto*//*Label 5650*/ GIMT_Encode4(380585), // Rule ID 24863 //
     /*  380514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  380517 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380520 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  380527 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380537 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380541 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380548 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  380551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380573 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380579 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380583 */   GIR_RootConstrainSelectedInstOperands,
     /*  380584 */   // GIR_Coverage, 24863,
     /*  380584 */   GIR_EraseRootFromParent_Done,
     /*  380585 */ // Label 5650: @380585
     /*  380585 */ GIM_Try, /*On fail goto*//*Label 5651*/ GIMT_Encode4(380661), // Rule ID 24864 //
     /*  380590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  380593 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  380603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380624 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  380627 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380652 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380655 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380659 */   GIR_RootConstrainSelectedInstOperands,
     /*  380660 */   // GIR_Coverage, 24864,
     /*  380660 */   GIR_EraseRootFromParent_Done,
     /*  380661 */ // Label 5651: @380661
     /*  380661 */ GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(380737), // Rule ID 24865 //
     /*  380666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  380669 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380672 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  380679 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380689 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380693 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380700 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
     /*  380703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380725 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380728 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380731 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380735 */   GIR_RootConstrainSelectedInstOperands,
     /*  380736 */   // GIR_Coverage, 24865,
     /*  380736 */   GIR_EraseRootFromParent_Done,
     /*  380737 */ // Label 5652: @380737
     /*  380737 */ GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(380813), // Rule ID 24876 //
     /*  380742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  380745 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380748 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380755 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380765 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380776 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  380779 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380804 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380811 */   GIR_RootConstrainSelectedInstOperands,
     /*  380812 */   // GIR_Coverage, 24876,
     /*  380812 */   GIR_EraseRootFromParent_Done,
     /*  380813 */ // Label 5653: @380813
     /*  380813 */ GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(380889), // Rule ID 24877 //
     /*  380818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  380821 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380824 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380841 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380845 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380852 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380852 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  380855 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380877 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380880 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380883 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380887 */   GIR_RootConstrainSelectedInstOperands,
     /*  380888 */   // GIR_Coverage, 24877,
     /*  380888 */   GIR_EraseRootFromParent_Done,
     /*  380889 */ // Label 5654: @380889
     /*  380889 */ GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(380965), // Rule ID 24878 //
     /*  380894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  380897 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380900 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380907 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  380928 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  380928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  380931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  380933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  380938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  380943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  380948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  380953 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  380959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  380963 */   GIR_RootConstrainSelectedInstOperands,
     /*  380964 */   // GIR_Coverage, 24878,
     /*  380964 */   GIR_EraseRootFromParent_Done,
     /*  380965 */ // Label 5655: @380965
     /*  380965 */ GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(381041), // Rule ID 24879 //
     /*  380970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  380973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  380976 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  380983 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  380989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  380993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  380997 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  381004 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  381004 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  381007 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381029 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381032 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381035 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381039 */   GIR_RootConstrainSelectedInstOperands,
     /*  381040 */   // GIR_Coverage, 24879,
     /*  381040 */   GIR_EraseRootFromParent_Done,
     /*  381041 */ // Label 5656: @381041
     /*  381041 */ GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(381117), // Rule ID 24880 //
     /*  381046 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  381049 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381052 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  381059 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  381065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381069 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381073 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  381080 */   // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  381080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
     /*  381083 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381105 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381111 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381115 */   GIR_RootConstrainSelectedInstOperands,
     /*  381116 */   // GIR_Coverage, 24880,
     /*  381116 */   GIR_EraseRootFromParent_Done,
     /*  381117 */ // Label 5657: @381117
     /*  381117 */ GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(381192), // Rule ID 25011 //
     /*  381122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  381125 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381128 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381135 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381148 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381155 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  381158 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381183 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381186 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381190 */   GIR_RootConstrainSelectedInstOperands,
     /*  381191 */   // GIR_Coverage, 25011,
     /*  381191 */   GIR_EraseRootFromParent_Done,
     /*  381192 */ // Label 5658: @381192
     /*  381192 */ GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(381267), // Rule ID 25012 //
     /*  381197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  381200 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381203 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381210 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381223 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381230 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381230 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  381233 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381255 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381258 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381261 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381265 */   GIR_RootConstrainSelectedInstOperands,
     /*  381266 */   // GIR_Coverage, 25012,
     /*  381266 */   GIR_EraseRootFromParent_Done,
     /*  381267 */ // Label 5659: @381267
     /*  381267 */ GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(381342), // Rule ID 25013 //
     /*  381272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  381275 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381278 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381285 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381305 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  381308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381330 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381333 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381336 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381340 */   GIR_RootConstrainSelectedInstOperands,
     /*  381341 */   // GIR_Coverage, 25013,
     /*  381341 */   GIR_EraseRootFromParent_Done,
     /*  381342 */ // Label 5660: @381342
     /*  381342 */ GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(381417), // Rule ID 25014 //
     /*  381347 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  381350 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381353 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381360 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381369 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381373 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381380 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381380 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  381383 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381405 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381415 */   GIR_RootConstrainSelectedInstOperands,
     /*  381416 */   // GIR_Coverage, 25014,
     /*  381416 */   GIR_EraseRootFromParent_Done,
     /*  381417 */ // Label 5661: @381417
     /*  381417 */ GIM_Try, /*On fail goto*//*Label 5662*/ GIMT_Encode4(381492), // Rule ID 25015 //
     /*  381422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  381425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381428 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381435 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381444 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381448 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381455 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381455 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
     /*  381458 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381483 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381486 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381490 */   GIR_RootConstrainSelectedInstOperands,
     /*  381491 */   // GIR_Coverage, 25015,
     /*  381491 */   GIR_EraseRootFromParent_Done,
     /*  381492 */ // Label 5662: @381492
     /*  381492 */ GIM_Try, /*On fail goto*//*Label 5663*/ GIMT_Encode4(381567), // Rule ID 25021 //
     /*  381497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  381500 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381503 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381510 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381515 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381530 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381530 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  381533 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381558 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381561 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381565 */   GIR_RootConstrainSelectedInstOperands,
     /*  381566 */   // GIR_Coverage, 25021,
     /*  381566 */   GIR_EraseRootFromParent_Done,
     /*  381567 */ // Label 5663: @381567
     /*  381567 */ GIM_Try, /*On fail goto*//*Label 5664*/ GIMT_Encode4(381642), // Rule ID 25022 //
     /*  381572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  381575 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381578 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381585 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381590 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381594 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381598 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381605 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381605 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  381608 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381615 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381630 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381633 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381636 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381640 */   GIR_RootConstrainSelectedInstOperands,
     /*  381641 */   // GIR_Coverage, 25022,
     /*  381641 */   GIR_EraseRootFromParent_Done,
     /*  381642 */ // Label 5664: @381642
     /*  381642 */ GIM_Try, /*On fail goto*//*Label 5665*/ GIMT_Encode4(381717), // Rule ID 25023 //
     /*  381647 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  381650 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381653 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381660 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381669 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381680 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  381683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381705 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381711 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381715 */   GIR_RootConstrainSelectedInstOperands,
     /*  381716 */   // GIR_Coverage, 25023,
     /*  381716 */   GIR_EraseRootFromParent_Done,
     /*  381717 */ // Label 5665: @381717
     /*  381717 */ GIM_Try, /*On fail goto*//*Label 5666*/ GIMT_Encode4(381792), // Rule ID 25024 //
     /*  381722 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  381725 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381728 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381740 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381755 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  381758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381783 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381786 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381790 */   GIR_RootConstrainSelectedInstOperands,
     /*  381791 */   // GIR_Coverage, 25024,
     /*  381791 */   GIR_EraseRootFromParent_Done,
     /*  381792 */ // Label 5666: @381792
     /*  381792 */ GIM_Try, /*On fail goto*//*Label 5667*/ GIMT_Encode4(381867), // Rule ID 25025 //
     /*  381797 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  381800 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381803 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  381810 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381819 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381823 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381830 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381830 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
     /*  381833 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381855 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381858 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381861 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381865 */   GIR_RootConstrainSelectedInstOperands,
     /*  381866 */   // GIR_Coverage, 25025,
     /*  381866 */   GIR_EraseRootFromParent_Done,
     /*  381867 */ // Label 5667: @381867
     /*  381867 */ GIM_Try, /*On fail goto*//*Label 5668*/ GIMT_Encode4(381942), // Rule ID 25131 //
     /*  381872 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  381875 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381878 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  381885 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381898 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381905 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  381908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  381925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  381930 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381933 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  381936 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  381940 */   GIR_RootConstrainSelectedInstOperands,
     /*  381941 */   // GIR_Coverage, 25131,
     /*  381941 */   GIR_EraseRootFromParent_Done,
     /*  381942 */ // Label 5668: @381942
     /*  381942 */ GIM_Try, /*On fail goto*//*Label 5669*/ GIMT_Encode4(382017), // Rule ID 25132 //
     /*  381947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  381950 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  381953 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  381960 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  381965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  381969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  381973 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  381980 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  381980 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  381983 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  381985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  381990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  381995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382005 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382008 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382011 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382015 */   GIR_RootConstrainSelectedInstOperands,
     /*  382016 */   // GIR_Coverage, 25132,
     /*  382016 */   GIR_EraseRootFromParent_Done,
     /*  382017 */ // Label 5669: @382017
     /*  382017 */ GIM_Try, /*On fail goto*//*Label 5670*/ GIMT_Encode4(382092), // Rule ID 25133 //
     /*  382022 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  382025 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382028 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382035 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382048 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382055 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  382058 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382086 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382090 */   GIR_RootConstrainSelectedInstOperands,
     /*  382091 */   // GIR_Coverage, 25133,
     /*  382091 */   GIR_EraseRootFromParent_Done,
     /*  382092 */ // Label 5670: @382092
     /*  382092 */ GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(382167), // Rule ID 25134 //
     /*  382097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  382100 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382103 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382110 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382115 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382123 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382130 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  382133 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382155 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382158 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382161 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382165 */   GIR_RootConstrainSelectedInstOperands,
     /*  382166 */   // GIR_Coverage, 25134,
     /*  382166 */   GIR_EraseRootFromParent_Done,
     /*  382167 */ // Label 5671: @382167
     /*  382167 */ GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(382242), // Rule ID 25135 //
     /*  382172 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  382175 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382178 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382185 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382194 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382198 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382205 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
     /*  382208 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382230 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382236 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382240 */   GIR_RootConstrainSelectedInstOperands,
     /*  382241 */   // GIR_Coverage, 25135,
     /*  382241 */   GIR_EraseRootFromParent_Done,
     /*  382242 */ // Label 5672: @382242
     /*  382242 */ GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(382317), // Rule ID 25141 //
     /*  382247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  382250 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382253 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382260 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382269 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382273 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382280 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  382283 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382305 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382308 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382311 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382315 */   GIR_RootConstrainSelectedInstOperands,
     /*  382316 */   // GIR_Coverage, 25141,
     /*  382316 */   GIR_EraseRootFromParent_Done,
     /*  382317 */ // Label 5673: @382317
     /*  382317 */ GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(382392), // Rule ID 25142 //
     /*  382322 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  382325 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382328 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382335 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382344 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382355 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  382358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382380 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382383 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382386 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382390 */   GIR_RootConstrainSelectedInstOperands,
     /*  382391 */   // GIR_Coverage, 25142,
     /*  382391 */   GIR_EraseRootFromParent_Done,
     /*  382392 */ // Label 5674: @382392
     /*  382392 */ GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(382467), // Rule ID 25143 //
     /*  382397 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  382400 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382403 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382410 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382415 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382419 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382423 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382430 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  382433 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382455 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382458 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382461 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382465 */   GIR_RootConstrainSelectedInstOperands,
     /*  382466 */   // GIR_Coverage, 25143,
     /*  382466 */   GIR_EraseRootFromParent_Done,
     /*  382467 */ // Label 5675: @382467
     /*  382467 */ GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(382542), // Rule ID 25144 //
     /*  382472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  382475 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382485 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382490 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382494 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382498 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382505 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  382508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382533 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382536 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382540 */   GIR_RootConstrainSelectedInstOperands,
     /*  382541 */   // GIR_Coverage, 25144,
     /*  382541 */   GIR_EraseRootFromParent_Done,
     /*  382542 */ // Label 5676: @382542
     /*  382542 */ GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(382617), // Rule ID 25145 //
     /*  382547 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  382550 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  382553 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  382560 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  382565 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382569 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  382580 */   // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  382580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
     /*  382583 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  382590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  382600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  382605 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382608 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382611 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382615 */   GIR_RootConstrainSelectedInstOperands,
     /*  382616 */   // GIR_Coverage, 25145,
     /*  382616 */   GIR_EraseRootFromParent_Done,
     /*  382617 */ // Label 5677: @382617
     /*  382617 */ GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(382689), // Rule ID 15063 //
     /*  382622 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  382625 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  382628 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  382635 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  382642 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382646 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382650 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  382657 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  382657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  382660 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  382672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  382677 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382680 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382683 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382687 */   GIR_RootConstrainSelectedInstOperands,
     /*  382688 */   // GIR_Coverage, 15063,
     /*  382688 */   GIR_EraseRootFromParent_Done,
     /*  382689 */ // Label 5678: @382689
     /*  382689 */ GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(382761), // Rule ID 15064 //
     /*  382694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  382697 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  382700 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  382707 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  382714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382718 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382722 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  382729 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  382729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  382732 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  382744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  382749 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382752 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382759 */   GIR_RootConstrainSelectedInstOperands,
     /*  382760 */   // GIR_Coverage, 15064,
     /*  382760 */   GIR_EraseRootFromParent_Done,
     /*  382761 */ // Label 5679: @382761
     /*  382761 */ GIM_Try, /*On fail goto*//*Label 5680*/ GIMT_Encode4(382833), // Rule ID 15065 //
     /*  382766 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  382769 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  382772 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  382779 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  382786 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382790 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  382801 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  382801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  382804 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  382816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  382821 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382831 */   GIR_RootConstrainSelectedInstOperands,
     /*  382832 */   // GIR_Coverage, 15065,
     /*  382832 */   GIR_EraseRootFromParent_Done,
     /*  382833 */ // Label 5680: @382833
     /*  382833 */ GIM_Try, /*On fail goto*//*Label 5681*/ GIMT_Encode4(382905), // Rule ID 15066 //
     /*  382838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  382841 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  382844 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  382851 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  382858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382862 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382866 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  382873 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  382873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  382876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  382888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  382893 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382903 */   GIR_RootConstrainSelectedInstOperands,
     /*  382904 */   // GIR_Coverage, 15066,
     /*  382904 */   GIR_EraseRootFromParent_Done,
     /*  382905 */ // Label 5681: @382905
     /*  382905 */ GIM_Try, /*On fail goto*//*Label 5682*/ GIMT_Encode4(382977), // Rule ID 15067 //
     /*  382910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  382913 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  382916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  382923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  382930 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  382934 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  382938 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  382945 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  382945 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  382948 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  382950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  382955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  382960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  382965 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382968 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  382971 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  382975 */   GIR_RootConstrainSelectedInstOperands,
     /*  382976 */   // GIR_Coverage, 15067,
     /*  382976 */   GIR_EraseRootFromParent_Done,
     /*  382977 */ // Label 5682: @382977
     /*  382977 */ GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(383049), // Rule ID 15073 //
     /*  382982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  382985 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  382988 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  382995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383010 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383017 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  383020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383040 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383047 */   GIR_RootConstrainSelectedInstOperands,
     /*  383048 */   // GIR_Coverage, 15073,
     /*  383048 */   GIR_EraseRootFromParent_Done,
     /*  383049 */ // Label 5683: @383049
     /*  383049 */ GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(383121), // Rule ID 15074 //
     /*  383054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  383057 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383060 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  383067 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383082 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383089 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  383092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383112 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383115 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383119 */   GIR_RootConstrainSelectedInstOperands,
     /*  383120 */   // GIR_Coverage, 15074,
     /*  383120 */   GIR_EraseRootFromParent_Done,
     /*  383121 */ // Label 5684: @383121
     /*  383121 */ GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(383193), // Rule ID 15075 //
     /*  383126 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  383129 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383132 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  383139 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383150 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383154 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383161 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  383164 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383181 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383191 */   GIR_RootConstrainSelectedInstOperands,
     /*  383192 */   // GIR_Coverage, 15075,
     /*  383192 */   GIR_EraseRootFromParent_Done,
     /*  383193 */ // Label 5685: @383193
     /*  383193 */ GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(383265), // Rule ID 15076 //
     /*  383198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  383201 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383204 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  383211 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383218 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383222 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383226 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383233 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  383236 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383253 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383259 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383263 */   GIR_RootConstrainSelectedInstOperands,
     /*  383264 */   // GIR_Coverage, 15076,
     /*  383264 */   GIR_EraseRootFromParent_Done,
     /*  383265 */ // Label 5686: @383265
     /*  383265 */ GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(383337), // Rule ID 15077 //
     /*  383270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  383273 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383276 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  383283 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383305 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  383308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383325 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383328 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383331 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383335 */   GIR_RootConstrainSelectedInstOperands,
     /*  383336 */   // GIR_Coverage, 15077,
     /*  383336 */   GIR_EraseRootFromParent_Done,
     /*  383337 */ // Label 5687: @383337
     /*  383337 */ GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(383409), // Rule ID 15103 //
     /*  383342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  383345 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383348 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383355 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383362 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383366 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383370 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383377 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  383380 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383397 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383400 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383403 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383407 */   GIR_RootConstrainSelectedInstOperands,
     /*  383408 */   // GIR_Coverage, 15103,
     /*  383408 */   GIR_EraseRootFromParent_Done,
     /*  383409 */ // Label 5688: @383409
     /*  383409 */ GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(383481), // Rule ID 15104 //
     /*  383414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  383417 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383420 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383427 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383434 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383438 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383442 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383449 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383449 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  383452 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383469 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383472 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383479 */   GIR_RootConstrainSelectedInstOperands,
     /*  383480 */   // GIR_Coverage, 15104,
     /*  383480 */   GIR_EraseRootFromParent_Done,
     /*  383481 */ // Label 5689: @383481
     /*  383481 */ GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(383553), // Rule ID 15105 //
     /*  383486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  383489 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383514 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383521 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  383524 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383541 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383544 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383547 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383551 */   GIR_RootConstrainSelectedInstOperands,
     /*  383552 */   // GIR_Coverage, 15105,
     /*  383552 */   GIR_EraseRootFromParent_Done,
     /*  383553 */ // Label 5690: @383553
     /*  383553 */ GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(383625), // Rule ID 15106 //
     /*  383558 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  383561 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383564 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383571 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383582 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383586 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383593 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383593 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  383596 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383613 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383616 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383619 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383623 */   GIR_RootConstrainSelectedInstOperands,
     /*  383624 */   // GIR_Coverage, 15106,
     /*  383624 */   GIR_EraseRootFromParent_Done,
     /*  383625 */ // Label 5691: @383625
     /*  383625 */ GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(383697), // Rule ID 15107 //
     /*  383630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  383633 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383636 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383654 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383658 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383665 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  383668 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383685 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383688 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383691 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383695 */   GIR_RootConstrainSelectedInstOperands,
     /*  383696 */   // GIR_Coverage, 15107,
     /*  383696 */   GIR_EraseRootFromParent_Done,
     /*  383697 */ // Label 5692: @383697
     /*  383697 */ GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(383769), // Rule ID 15113 //
     /*  383702 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  383705 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383708 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383715 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383722 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383726 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383730 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383737 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383737 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  383740 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383757 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383760 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383763 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383767 */   GIR_RootConstrainSelectedInstOperands,
     /*  383768 */   // GIR_Coverage, 15113,
     /*  383768 */   GIR_EraseRootFromParent_Done,
     /*  383769 */ // Label 5693: @383769
     /*  383769 */ GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(383841), // Rule ID 15114 //
     /*  383774 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  383777 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383780 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383787 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383798 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383802 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383809 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383809 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  383812 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383839 */   GIR_RootConstrainSelectedInstOperands,
     /*  383840 */   // GIR_Coverage, 15114,
     /*  383840 */   GIR_EraseRootFromParent_Done,
     /*  383841 */ // Label 5694: @383841
     /*  383841 */ GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(383913), // Rule ID 15115 //
     /*  383846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  383849 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383852 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383859 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383881 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  383884 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383901 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383904 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383907 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383911 */   GIR_RootConstrainSelectedInstOperands,
     /*  383912 */   // GIR_Coverage, 15115,
     /*  383912 */   GIR_EraseRootFromParent_Done,
     /*  383913 */ // Label 5695: @383913
     /*  383913 */ GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(383985), // Rule ID 15116 //
     /*  383918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  383921 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383924 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  383931 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  383938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  383942 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  383946 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  383953 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  383953 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  383956 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  383958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  383963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  383968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  383973 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  383979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  383983 */   GIR_RootConstrainSelectedInstOperands,
     /*  383984 */   // GIR_Coverage, 15116,
     /*  383984 */   GIR_EraseRootFromParent_Done,
     /*  383985 */ // Label 5696: @383985
     /*  383985 */ GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(384057), // Rule ID 15117 //
     /*  383990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  383993 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  383996 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  384003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384010 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384014 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384018 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384025 */   // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  384028 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384045 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384048 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384051 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384055 */   GIR_RootConstrainSelectedInstOperands,
     /*  384056 */   // GIR_Coverage, 15117,
     /*  384056 */   GIR_EraseRootFromParent_Done,
     /*  384057 */ // Label 5697: @384057
     /*  384057 */ GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(384129), // Rule ID 15203 //
     /*  384062 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  384065 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384068 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384075 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384086 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384090 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384097 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384097 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  384100 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384120 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384123 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384127 */   GIR_RootConstrainSelectedInstOperands,
     /*  384128 */   // GIR_Coverage, 15203,
     /*  384128 */   GIR_EraseRootFromParent_Done,
     /*  384129 */ // Label 5698: @384129
     /*  384129 */ GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(384201), // Rule ID 15204 //
     /*  384134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  384137 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384140 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384158 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384162 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384169 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  384172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384189 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384192 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384195 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384199 */   GIR_RootConstrainSelectedInstOperands,
     /*  384200 */   // GIR_Coverage, 15204,
     /*  384200 */   GIR_EraseRootFromParent_Done,
     /*  384201 */ // Label 5699: @384201
     /*  384201 */ GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(384273), // Rule ID 15205 //
     /*  384206 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  384209 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384212 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384219 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384241 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  384244 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384271 */   GIR_RootConstrainSelectedInstOperands,
     /*  384272 */   // GIR_Coverage, 15205,
     /*  384272 */   GIR_EraseRootFromParent_Done,
     /*  384273 */ // Label 5700: @384273
     /*  384273 */ GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(384345), // Rule ID 15206 //
     /*  384278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  384281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384284 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384291 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384313 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  384316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384333 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384339 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384343 */   GIR_RootConstrainSelectedInstOperands,
     /*  384344 */   // GIR_Coverage, 15206,
     /*  384344 */   GIR_EraseRootFromParent_Done,
     /*  384345 */ // Label 5701: @384345
     /*  384345 */ GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(384417), // Rule ID 15207 //
     /*  384350 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  384353 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384356 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384374 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384378 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384385 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
     /*  384388 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384405 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384415 */   GIR_RootConstrainSelectedInstOperands,
     /*  384416 */   // GIR_Coverage, 15207,
     /*  384416 */   GIR_EraseRootFromParent_Done,
     /*  384417 */ // Label 5702: @384417
     /*  384417 */ GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(384489), // Rule ID 15213 //
     /*  384422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  384425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384428 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384435 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384457 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  384460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384477 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384483 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384487 */   GIR_RootConstrainSelectedInstOperands,
     /*  384488 */   // GIR_Coverage, 15213,
     /*  384488 */   GIR_EraseRootFromParent_Done,
     /*  384489 */ // Label 5703: @384489
     /*  384489 */ GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(384561), // Rule ID 15214 //
     /*  384494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  384497 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384500 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384522 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384529 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  384532 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384549 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384552 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384555 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384559 */   GIR_RootConstrainSelectedInstOperands,
     /*  384560 */   // GIR_Coverage, 15214,
     /*  384560 */   GIR_EraseRootFromParent_Done,
     /*  384561 */ // Label 5704: @384561
     /*  384561 */ GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(384633), // Rule ID 15215 //
     /*  384566 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  384569 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384572 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384590 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384594 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384601 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  384604 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384621 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384624 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384627 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384631 */   GIR_RootConstrainSelectedInstOperands,
     /*  384632 */   // GIR_Coverage, 15215,
     /*  384632 */   GIR_EraseRootFromParent_Done,
     /*  384633 */ // Label 5705: @384633
     /*  384633 */ GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(384705), // Rule ID 15216 //
     /*  384638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  384641 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384644 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384651 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384662 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384666 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384673 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384673 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  384676 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384693 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384696 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384699 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384703 */   GIR_RootConstrainSelectedInstOperands,
     /*  384704 */   // GIR_Coverage, 15216,
     /*  384704 */   GIR_EraseRootFromParent_Done,
     /*  384705 */ // Label 5706: @384705
     /*  384705 */ GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(384777), // Rule ID 15217 //
     /*  384710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  384713 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384716 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  384723 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384734 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384738 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384745 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384745 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
     /*  384748 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384765 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384771 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384775 */   GIR_RootConstrainSelectedInstOperands,
     /*  384776 */   // GIR_Coverage, 15217,
     /*  384776 */   GIR_EraseRootFromParent_Done,
     /*  384777 */ // Label 5707: @384777
     /*  384777 */ GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(384849), // Rule ID 15303 //
     /*  384782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  384785 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384788 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  384795 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384802 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384806 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384810 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384817 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384817 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  384820 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384837 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384843 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384847 */   GIR_RootConstrainSelectedInstOperands,
     /*  384848 */   // GIR_Coverage, 15303,
     /*  384848 */   GIR_EraseRootFromParent_Done,
     /*  384849 */ // Label 5708: @384849
     /*  384849 */ GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(384921), // Rule ID 15304 //
     /*  384854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  384857 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384860 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  384867 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384874 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384878 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384882 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384889 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384889 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  384892 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384912 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384915 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384919 */   GIR_RootConstrainSelectedInstOperands,
     /*  384920 */   // GIR_Coverage, 15304,
     /*  384920 */   GIR_EraseRootFromParent_Done,
     /*  384921 */ // Label 5709: @384921
     /*  384921 */ GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(384993), // Rule ID 15305 //
     /*  384926 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  384929 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  384932 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  384939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  384946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  384950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  384954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  384961 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  384961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  384964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  384966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  384971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  384976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  384981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  384987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  384991 */   GIR_RootConstrainSelectedInstOperands,
     /*  384992 */   // GIR_Coverage, 15305,
     /*  384992 */   GIR_EraseRootFromParent_Done,
     /*  384993 */ // Label 5710: @384993
     /*  384993 */ GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(385065), // Rule ID 15306 //
     /*  384998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  385001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385004 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385011 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385022 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385026 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385033 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385033 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  385036 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385053 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385059 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385063 */   GIR_RootConstrainSelectedInstOperands,
     /*  385064 */   // GIR_Coverage, 15306,
     /*  385064 */   GIR_EraseRootFromParent_Done,
     /*  385065 */ // Label 5711: @385065
     /*  385065 */ GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(385137), // Rule ID 15307 //
     /*  385070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  385073 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385076 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385083 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385105 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
     /*  385108 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385125 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385128 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385131 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385135 */   GIR_RootConstrainSelectedInstOperands,
     /*  385136 */   // GIR_Coverage, 15307,
     /*  385136 */   GIR_EraseRootFromParent_Done,
     /*  385137 */ // Label 5712: @385137
     /*  385137 */ GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(385209), // Rule ID 15313 //
     /*  385142 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  385145 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385148 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385155 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385166 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385170 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385177 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385177 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  385180 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385197 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385203 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385207 */   GIR_RootConstrainSelectedInstOperands,
     /*  385208 */   // GIR_Coverage, 15313,
     /*  385208 */   GIR_EraseRootFromParent_Done,
     /*  385209 */ // Label 5713: @385209
     /*  385209 */ GIM_Try, /*On fail goto*//*Label 5714*/ GIMT_Encode4(385281), // Rule ID 15314 //
     /*  385214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  385217 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385220 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385227 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385234 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385238 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385249 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  385252 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385279 */   GIR_RootConstrainSelectedInstOperands,
     /*  385280 */   // GIR_Coverage, 15314,
     /*  385280 */   GIR_EraseRootFromParent_Done,
     /*  385281 */ // Label 5714: @385281
     /*  385281 */ GIM_Try, /*On fail goto*//*Label 5715*/ GIMT_Encode4(385353), // Rule ID 15315 //
     /*  385286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  385289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385321 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385321 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  385324 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385344 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385351 */   GIR_RootConstrainSelectedInstOperands,
     /*  385352 */   // GIR_Coverage, 15315,
     /*  385352 */   GIR_EraseRootFromParent_Done,
     /*  385353 */ // Label 5715: @385353
     /*  385353 */ GIM_Try, /*On fail goto*//*Label 5716*/ GIMT_Encode4(385425), // Rule ID 15316 //
     /*  385358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  385361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385364 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385371 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385382 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385393 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  385396 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385413 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385416 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385419 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385423 */   GIR_RootConstrainSelectedInstOperands,
     /*  385424 */   // GIR_Coverage, 15316,
     /*  385424 */   GIR_EraseRootFromParent_Done,
     /*  385425 */ // Label 5716: @385425
     /*  385425 */ GIM_Try, /*On fail goto*//*Label 5717*/ GIMT_Encode4(385497), // Rule ID 15317 //
     /*  385430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  385433 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385436 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  385443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  385450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385454 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385458 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  385465 */   // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  385465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
     /*  385468 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  385470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  385475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  385480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  385485 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385488 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385491 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385495 */   GIR_RootConstrainSelectedInstOperands,
     /*  385496 */   // GIR_Coverage, 15317,
     /*  385496 */   GIR_EraseRootFromParent_Done,
     /*  385497 */ // Label 5717: @385497
     /*  385497 */ GIM_Try, /*On fail goto*//*Label 5718*/ GIMT_Encode4(385559), // Rule ID 28809 //
     /*  385502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  385505 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385508 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385515 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385535 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  385538 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385557 */   GIR_RootConstrainSelectedInstOperands,
     /*  385558 */   // GIR_Coverage, 28809,
     /*  385558 */   GIR_EraseRootFromParent_Done,
     /*  385559 */ // Label 5718: @385559
     /*  385559 */ GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(385621), // Rule ID 28810 //
     /*  385564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  385567 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385570 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385577 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385597 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  385600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385619 */   GIR_RootConstrainSelectedInstOperands,
     /*  385620 */   // GIR_Coverage, 28810,
     /*  385620 */   GIR_EraseRootFromParent_Done,
     /*  385621 */ // Label 5719: @385621
     /*  385621 */ GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(385683), // Rule ID 28811 //
     /*  385626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  385629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385632 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385639 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385659 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  385662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385674 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385677 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385681 */   GIR_RootConstrainSelectedInstOperands,
     /*  385682 */   // GIR_Coverage, 28811,
     /*  385682 */   GIR_EraseRootFromParent_Done,
     /*  385683 */ // Label 5720: @385683
     /*  385683 */ GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(385745), // Rule ID 28812 //
     /*  385688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  385691 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385694 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385701 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385706 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385710 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385714 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385721 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  385724 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385736 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385739 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385743 */   GIR_RootConstrainSelectedInstOperands,
     /*  385744 */   // GIR_Coverage, 28812,
     /*  385744 */   GIR_EraseRootFromParent_Done,
     /*  385745 */ // Label 5721: @385745
     /*  385745 */ GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(385807), // Rule ID 28813 //
     /*  385750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  385753 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385756 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385763 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385768 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385772 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385776 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385783 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  385786 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385805 */   GIR_RootConstrainSelectedInstOperands,
     /*  385806 */   // GIR_Coverage, 28813,
     /*  385806 */   GIR_EraseRootFromParent_Done,
     /*  385807 */ // Label 5722: @385807
     /*  385807 */ GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(385869), // Rule ID 28814 //
     /*  385812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  385815 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385818 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385825 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385845 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  385848 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385867 */   GIR_RootConstrainSelectedInstOperands,
     /*  385868 */   // GIR_Coverage, 28814,
     /*  385868 */   GIR_EraseRootFromParent_Done,
     /*  385869 */ // Label 5723: @385869
     /*  385869 */ GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(385931), // Rule ID 28815 //
     /*  385874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  385877 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385880 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385887 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385907 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  385910 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385929 */   GIR_RootConstrainSelectedInstOperands,
     /*  385930 */   // GIR_Coverage, 28815,
     /*  385930 */   GIR_EraseRootFromParent_Done,
     /*  385931 */ // Label 5724: @385931
     /*  385931 */ GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(385993), // Rule ID 28816 //
     /*  385936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  385939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  385942 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  385949 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  385954 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  385958 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  385962 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  385969 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  385969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  385972 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  385974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  385979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  385984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  385987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  385991 */   GIR_RootConstrainSelectedInstOperands,
     /*  385992 */   // GIR_Coverage, 28816,
     /*  385992 */   GIR_EraseRootFromParent_Done,
     /*  385993 */ // Label 5725: @385993
     /*  385993 */ GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(386055), // Rule ID 28817 //
     /*  385998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  386001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386004 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  386011 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386020 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386024 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386031 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386031 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  386034 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386046 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386053 */   GIR_RootConstrainSelectedInstOperands,
     /*  386054 */   // GIR_Coverage, 28817,
     /*  386054 */   GIR_EraseRootFromParent_Done,
     /*  386055 */ // Label 5726: @386055
     /*  386055 */ GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(386117), // Rule ID 28818 //
     /*  386060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  386063 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386066 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  386073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386082 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386093 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  386096 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386111 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386115 */   GIR_RootConstrainSelectedInstOperands,
     /*  386116 */   // GIR_Coverage, 28818,
     /*  386116 */   GIR_EraseRootFromParent_Done,
     /*  386117 */ // Label 5727: @386117
     /*  386117 */ GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(386179), // Rule ID 28839 //
     /*  386122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  386125 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386128 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386135 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386148 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386155 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  386158 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386173 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386177 */   GIR_RootConstrainSelectedInstOperands,
     /*  386178 */   // GIR_Coverage, 28839,
     /*  386178 */   GIR_EraseRootFromParent_Done,
     /*  386179 */ // Label 5728: @386179
     /*  386179 */ GIM_Try, /*On fail goto*//*Label 5729*/ GIMT_Encode4(386241), // Rule ID 28840 //
     /*  386184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  386187 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386190 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386197 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386206 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386210 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386217 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  386220 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386239 */   GIR_RootConstrainSelectedInstOperands,
     /*  386240 */   // GIR_Coverage, 28840,
     /*  386240 */   GIR_EraseRootFromParent_Done,
     /*  386241 */ // Label 5729: @386241
     /*  386241 */ GIM_Try, /*On fail goto*//*Label 5730*/ GIMT_Encode4(386303), // Rule ID 28841 //
     /*  386246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  386249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386252 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386259 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386279 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  386282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386294 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386297 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386301 */   GIR_RootConstrainSelectedInstOperands,
     /*  386302 */   // GIR_Coverage, 28841,
     /*  386302 */   GIR_EraseRootFromParent_Done,
     /*  386303 */ // Label 5730: @386303
     /*  386303 */ GIM_Try, /*On fail goto*//*Label 5731*/ GIMT_Encode4(386365), // Rule ID 28842 //
     /*  386308 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  386311 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386314 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386321 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386341 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  386344 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386359 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386363 */   GIR_RootConstrainSelectedInstOperands,
     /*  386364 */   // GIR_Coverage, 28842,
     /*  386364 */   GIR_EraseRootFromParent_Done,
     /*  386365 */ // Label 5731: @386365
     /*  386365 */ GIM_Try, /*On fail goto*//*Label 5732*/ GIMT_Encode4(386427), // Rule ID 28843 //
     /*  386370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  386373 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386403 */   // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  386406 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386425 */   GIR_RootConstrainSelectedInstOperands,
     /*  386426 */   // GIR_Coverage, 28843,
     /*  386426 */   GIR_EraseRootFromParent_Done,
     /*  386427 */ // Label 5732: @386427
     /*  386427 */ GIM_Try, /*On fail goto*//*Label 5733*/ GIMT_Encode4(386489), // Rule ID 28844 //
     /*  386432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  386435 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386438 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386445 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386454 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386458 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386465 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  386468 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386483 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386487 */   GIR_RootConstrainSelectedInstOperands,
     /*  386488 */   // GIR_Coverage, 28844,
     /*  386488 */   GIR_EraseRootFromParent_Done,
     /*  386489 */ // Label 5733: @386489
     /*  386489 */ GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(386551), // Rule ID 28845 //
     /*  386494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  386497 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386500 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386516 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386520 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386527 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386527 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  386530 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386542 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386549 */   GIR_RootConstrainSelectedInstOperands,
     /*  386550 */   // GIR_Coverage, 28845,
     /*  386550 */   GIR_EraseRootFromParent_Done,
     /*  386551 */ // Label 5734: @386551
     /*  386551 */ GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(386613), // Rule ID 28846 //
     /*  386556 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  386559 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386562 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386578 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386589 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  386592 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386604 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386607 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386611 */   GIR_RootConstrainSelectedInstOperands,
     /*  386612 */   // GIR_Coverage, 28846,
     /*  386612 */   GIR_EraseRootFromParent_Done,
     /*  386613 */ // Label 5735: @386613
     /*  386613 */ GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(386675), // Rule ID 28847 //
     /*  386618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  386621 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386624 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386631 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386640 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386644 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386651 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386651 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  386654 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386666 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386669 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386673 */   GIR_RootConstrainSelectedInstOperands,
     /*  386674 */   // GIR_Coverage, 28847,
     /*  386674 */   GIR_EraseRootFromParent_Done,
     /*  386675 */ // Label 5736: @386675
     /*  386675 */ GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(386737), // Rule ID 28848 //
     /*  386680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  386683 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  386686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  386693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386713 */   // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  386716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386728 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386731 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386735 */   GIR_RootConstrainSelectedInstOperands,
     /*  386736 */   // GIR_Coverage, 28848,
     /*  386736 */   GIR_EraseRootFromParent_Done,
     /*  386737 */ // Label 5737: @386737
     /*  386737 */ GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(386799), // Rule ID 29019 //
     /*  386742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  386745 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  386748 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  386755 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386775 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  386778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386790 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386793 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386797 */   GIR_RootConstrainSelectedInstOperands,
     /*  386798 */   // GIR_Coverage, 29019,
     /*  386798 */   GIR_EraseRootFromParent_Done,
     /*  386799 */ // Label 5738: @386799
     /*  386799 */ GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(386861), // Rule ID 29020 //
     /*  386804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  386807 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  386810 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  386817 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386826 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386830 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386837 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  386840 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386859 */   GIR_RootConstrainSelectedInstOperands,
     /*  386860 */   // GIR_Coverage, 29020,
     /*  386860 */   GIR_EraseRootFromParent_Done,
     /*  386861 */ // Label 5739: @386861
     /*  386861 */ GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(386923), // Rule ID 29021 //
     /*  386866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  386869 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  386872 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  386879 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386884 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386888 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386892 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386899 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386899 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  386902 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386917 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386921 */   GIR_RootConstrainSelectedInstOperands,
     /*  386922 */   // GIR_Coverage, 29021,
     /*  386922 */   GIR_EraseRootFromParent_Done,
     /*  386923 */ // Label 5740: @386923
     /*  386923 */ GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(386985), // Rule ID 29022 //
     /*  386928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  386931 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  386934 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  386941 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  386946 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  386950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  386954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  386961 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  386961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  386964 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  386966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  386971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  386976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  386979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  386983 */   GIR_RootConstrainSelectedInstOperands,
     /*  386984 */   // GIR_Coverage, 29022,
     /*  386984 */   GIR_EraseRootFromParent_Done,
     /*  386985 */ // Label 5741: @386985
     /*  386985 */ GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(387047), // Rule ID 29023 //
     /*  386990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  386993 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  386996 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387023 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_8_glue>><<P:Predicate_atomic_load_zext_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
     /*  387026 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387038 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387041 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387045 */   GIR_RootConstrainSelectedInstOperands,
     /*  387046 */   // GIR_Coverage, 29023,
     /*  387046 */   GIR_EraseRootFromParent_Done,
     /*  387047 */ // Label 5742: @387047
     /*  387047 */ GIM_Try, /*On fail goto*//*Label 5743*/ GIMT_Encode4(387109), // Rule ID 29024 //
     /*  387052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  387055 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387058 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387085 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  387088 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387100 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387107 */   GIR_RootConstrainSelectedInstOperands,
     /*  387108 */   // GIR_Coverage, 29024,
     /*  387108 */   GIR_EraseRootFromParent_Done,
     /*  387109 */ // Label 5743: @387109
     /*  387109 */ GIM_Try, /*On fail goto*//*Label 5744*/ GIMT_Encode4(387171), // Rule ID 29025 //
     /*  387114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  387117 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387120 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387147 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  387150 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387169 */   GIR_RootConstrainSelectedInstOperands,
     /*  387170 */   // GIR_Coverage, 29025,
     /*  387170 */   GIR_EraseRootFromParent_Done,
     /*  387171 */ // Label 5744: @387171
     /*  387171 */ GIM_Try, /*On fail goto*//*Label 5745*/ GIMT_Encode4(387233), // Rule ID 29026 //
     /*  387176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  387179 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387182 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387189 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387209 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  387212 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387224 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387227 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387231 */   GIR_RootConstrainSelectedInstOperands,
     /*  387232 */   // GIR_Coverage, 29026,
     /*  387232 */   GIR_EraseRootFromParent_Done,
     /*  387233 */ // Label 5745: @387233
     /*  387233 */ GIM_Try, /*On fail goto*//*Label 5746*/ GIMT_Encode4(387295), // Rule ID 29027 //
     /*  387238 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  387241 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387244 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387271 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  387274 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387293 */   GIR_RootConstrainSelectedInstOperands,
     /*  387294 */   // GIR_Coverage, 29027,
     /*  387294 */   GIR_EraseRootFromParent_Done,
     /*  387295 */ // Label 5746: @387295
     /*  387295 */ GIM_Try, /*On fail goto*//*Label 5747*/ GIMT_Encode4(387357), // Rule ID 29028 //
     /*  387300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  387303 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387333 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
     /*  387336 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387348 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387355 */   GIR_RootConstrainSelectedInstOperands,
     /*  387356 */   // GIR_Coverage, 29028,
     /*  387356 */   GIR_EraseRootFromParent_Done,
     /*  387357 */ // Label 5747: @387357
     /*  387357 */ GIM_Try, /*On fail goto*//*Label 5748*/ GIMT_Encode4(387419), // Rule ID 29081 //
     /*  387362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  387365 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387384 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387388 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387395 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_16_glue>><<P:Predicate_atomic_load_zext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387395 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  387398 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387410 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387413 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387417 */   GIR_RootConstrainSelectedInstOperands,
     /*  387418 */   // GIR_Coverage, 29081,
     /*  387418 */   GIR_EraseRootFromParent_Done,
     /*  387419 */ // Label 5748: @387419
     /*  387419 */ GIM_Try, /*On fail goto*//*Label 5749*/ GIMT_Encode4(387481), // Rule ID 29082 //
     /*  387424 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  387427 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387430 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387457 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_16_glue>><<P:Predicate_atomic_load_zext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  387460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387472 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387479 */   GIR_RootConstrainSelectedInstOperands,
     /*  387480 */   // GIR_Coverage, 29082,
     /*  387480 */   GIR_EraseRootFromParent_Done,
     /*  387481 */ // Label 5749: @387481
     /*  387481 */ GIM_Try, /*On fail goto*//*Label 5750*/ GIMT_Encode4(387543), // Rule ID 29083 //
     /*  387486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  387489 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387519 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_16_glue>><<P:Predicate_atomic_load_zext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  387522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387534 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387541 */   GIR_RootConstrainSelectedInstOperands,
     /*  387542 */   // GIR_Coverage, 29083,
     /*  387542 */   GIR_EraseRootFromParent_Done,
     /*  387543 */ // Label 5750: @387543
     /*  387543 */ GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(387605), // Rule ID 29084 //
     /*  387548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  387551 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387570 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387581 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_16_glue>><<P:Predicate_atomic_load_zext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  387584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387603 */   GIR_RootConstrainSelectedInstOperands,
     /*  387604 */   // GIR_Coverage, 29084,
     /*  387604 */   GIR_EraseRootFromParent_Done,
     /*  387605 */ // Label 5751: @387605
     /*  387605 */ GIM_Try, /*On fail goto*//*Label 5752*/ GIMT_Encode4(387667), // Rule ID 29085 //
     /*  387610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  387613 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387616 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387623 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387643 */   // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext_glue>><<P:Predicate_atomic_load_zext_16_glue>><<P:Predicate_atomic_load_zext_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
     /*  387646 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387658 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387661 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387665 */   GIR_RootConstrainSelectedInstOperands,
     /*  387666 */   // GIR_Coverage, 29085,
     /*  387666 */   GIR_EraseRootFromParent_Done,
     /*  387667 */ // Label 5752: @387667
     /*  387667 */ GIM_Try, /*On fail goto*//*Label 5753*/ GIMT_Encode4(387729), // Rule ID 29086 //
     /*  387672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  387675 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387678 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387685 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387705 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  387708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387723 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387727 */   GIR_RootConstrainSelectedInstOperands,
     /*  387728 */   // GIR_Coverage, 29086,
     /*  387728 */   GIR_EraseRootFromParent_Done,
     /*  387729 */ // Label 5753: @387729
     /*  387729 */ GIM_Try, /*On fail goto*//*Label 5754*/ GIMT_Encode4(387791), // Rule ID 29087 //
     /*  387734 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  387737 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387740 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387747 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387767 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  387770 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387789 */   GIR_RootConstrainSelectedInstOperands,
     /*  387790 */   // GIR_Coverage, 29087,
     /*  387790 */   GIR_EraseRootFromParent_Done,
     /*  387791 */ // Label 5754: @387791
     /*  387791 */ GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(387853), // Rule ID 29088 //
     /*  387796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  387799 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387802 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387818 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387822 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387829 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  387832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387844 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387851 */   GIR_RootConstrainSelectedInstOperands,
     /*  387852 */   // GIR_Coverage, 29088,
     /*  387852 */   GIR_EraseRootFromParent_Done,
     /*  387853 */ // Label 5755: @387853
     /*  387853 */ GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(387915), // Rule ID 29089 //
     /*  387858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  387861 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387864 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387891 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  387894 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387906 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387909 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387913 */   GIR_RootConstrainSelectedInstOperands,
     /*  387914 */   // GIR_Coverage, 29089,
     /*  387914 */   GIR_EraseRootFromParent_Done,
     /*  387915 */ // Label 5756: @387915
     /*  387915 */ GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(387977), // Rule ID 29090 //
     /*  387920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  387923 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387926 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  387933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  387938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  387942 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  387946 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  387953 */   // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  387953 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
     /*  387956 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  387958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  387963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  387968 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  387971 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  387975 */   GIR_RootConstrainSelectedInstOperands,
     /*  387976 */   // GIR_Coverage, 29090,
     /*  387976 */   GIR_EraseRootFromParent_Done,
     /*  387977 */ // Label 5757: @387977
     /*  387977 */ GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(388048), // Rule ID 11737 //
     /*  387982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  387985 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  387988 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  387995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388010 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388017 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388046 */   GIR_RootConstrainSelectedInstOperands,
     /*  388047 */   // GIR_Coverage, 11737,
     /*  388047 */   GIR_EraseRootFromParent_Done,
     /*  388048 */ // Label 5758: @388048
     /*  388048 */ GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(388119), // Rule ID 11738 //
     /*  388053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  388056 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388059 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388066 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388077 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388088 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388091 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388117 */   GIR_RootConstrainSelectedInstOperands,
     /*  388118 */   // GIR_Coverage, 11738,
     /*  388118 */   GIR_EraseRootFromParent_Done,
     /*  388119 */ // Label 5759: @388119
     /*  388119 */ GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(388190), // Rule ID 11739 //
     /*  388124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  388127 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388159 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388162 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388184 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388188 */   GIR_RootConstrainSelectedInstOperands,
     /*  388189 */   // GIR_Coverage, 11739,
     /*  388189 */   GIR_EraseRootFromParent_Done,
     /*  388190 */ // Label 5760: @388190
     /*  388190 */ GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(388261), // Rule ID 11740 //
     /*  388195 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  388198 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388201 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388208 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388223 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388230 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388230 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388233 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388255 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388259 */   GIR_RootConstrainSelectedInstOperands,
     /*  388260 */   // GIR_Coverage, 11740,
     /*  388260 */   GIR_EraseRootFromParent_Done,
     /*  388261 */ // Label 5761: @388261
     /*  388261 */ GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(388332), // Rule ID 11741 //
     /*  388266 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  388269 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388272 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388290 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388294 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388301 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388301 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388304 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388326 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388330 */   GIR_RootConstrainSelectedInstOperands,
     /*  388331 */   // GIR_Coverage, 11741,
     /*  388331 */   GIR_EraseRootFromParent_Done,
     /*  388332 */ // Label 5762: @388332
     /*  388332 */ GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(388403), // Rule ID 11757 //
     /*  388337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  388340 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388343 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  388350 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388361 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388365 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388372 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  388375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388397 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388401 */   GIR_RootConstrainSelectedInstOperands,
     /*  388402 */   // GIR_Coverage, 11757,
     /*  388402 */   GIR_EraseRootFromParent_Done,
     /*  388403 */ // Label 5763: @388403
     /*  388403 */ GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(388474), // Rule ID 11758 //
     /*  388408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  388411 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388414 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  388421 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388432 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388436 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388443 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388443 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  388446 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388468 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388472 */   GIR_RootConstrainSelectedInstOperands,
     /*  388473 */   // GIR_Coverage, 11758,
     /*  388473 */   GIR_EraseRootFromParent_Done,
     /*  388474 */ // Label 5764: @388474
     /*  388474 */ GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(388545), // Rule ID 11759 //
     /*  388479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  388482 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388485 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  388492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388514 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  388517 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388543 */   GIR_RootConstrainSelectedInstOperands,
     /*  388544 */   // GIR_Coverage, 11759,
     /*  388544 */   GIR_EraseRootFromParent_Done,
     /*  388545 */ // Label 5765: @388545
     /*  388545 */ GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(388616), // Rule ID 11760 //
     /*  388550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  388553 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388556 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  388563 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388574 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388578 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388585 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388585 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  388588 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388610 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388614 */   GIR_RootConstrainSelectedInstOperands,
     /*  388615 */   // GIR_Coverage, 11760,
     /*  388615 */   GIR_EraseRootFromParent_Done,
     /*  388616 */ // Label 5766: @388616
     /*  388616 */ GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(388687), // Rule ID 11761 //
     /*  388621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  388624 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  388627 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  388634 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388645 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388649 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388656 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388656 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  388659 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388681 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388685 */   GIR_RootConstrainSelectedInstOperands,
     /*  388686 */   // GIR_Coverage, 11761,
     /*  388686 */   GIR_EraseRootFromParent_Done,
     /*  388687 */ // Label 5767: @388687
     /*  388687 */ GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(388758), // Rule ID 11787 //
     /*  388692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  388695 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  388698 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388705 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388712 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388716 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388720 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388727 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388730 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388752 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388756 */   GIR_RootConstrainSelectedInstOperands,
     /*  388757 */   // GIR_Coverage, 11787,
     /*  388757 */   GIR_EraseRootFromParent_Done,
     /*  388758 */ // Label 5768: @388758
     /*  388758 */ GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(388829), // Rule ID 11788 //
     /*  388763 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  388766 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  388769 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388776 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388783 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388787 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388791 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388798 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388798 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388801 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388823 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388827 */   GIR_RootConstrainSelectedInstOperands,
     /*  388828 */   // GIR_Coverage, 11788,
     /*  388828 */   GIR_EraseRootFromParent_Done,
     /*  388829 */ // Label 5769: @388829
     /*  388829 */ GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(388900), // Rule ID 11789 //
     /*  388834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  388837 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  388840 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388847 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388854 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388869 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388872 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388894 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388898 */   GIR_RootConstrainSelectedInstOperands,
     /*  388899 */   // GIR_Coverage, 11789,
     /*  388899 */   GIR_EraseRootFromParent_Done,
     /*  388900 */ // Label 5770: @388900
     /*  388900 */ GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(388971), // Rule ID 11790 //
     /*  388905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  388908 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  388911 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388918 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  388929 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  388933 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  388940 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  388940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  388943 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  388945 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  388950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  388955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  388960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  388965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  388969 */   GIR_RootConstrainSelectedInstOperands,
     /*  388970 */   // GIR_Coverage, 11790,
     /*  388970 */   GIR_EraseRootFromParent_Done,
     /*  388971 */ // Label 5771: @388971
     /*  388971 */ GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(389042), // Rule ID 11791 //
     /*  388976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  388979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  388982 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  388989 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  388996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389000 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389004 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389011 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
     /*  389014 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389036 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389040 */   GIR_RootConstrainSelectedInstOperands,
     /*  389041 */   // GIR_Coverage, 11791,
     /*  389041 */   GIR_EraseRootFromParent_Done,
     /*  389042 */ // Label 5772: @389042
     /*  389042 */ GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(389113), // Rule ID 11817 //
     /*  389047 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  389050 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  389053 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389082 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389085 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389111 */   GIR_RootConstrainSelectedInstOperands,
     /*  389112 */   // GIR_Coverage, 11817,
     /*  389112 */   GIR_EraseRootFromParent_Done,
     /*  389113 */ // Label 5773: @389113
     /*  389113 */ GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(389184), // Rule ID 11818 //
     /*  389118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  389121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  389124 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389131 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389142 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389146 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389153 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389156 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389178 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389182 */   GIR_RootConstrainSelectedInstOperands,
     /*  389183 */   // GIR_Coverage, 11818,
     /*  389183 */   GIR_EraseRootFromParent_Done,
     /*  389184 */ // Label 5774: @389184
     /*  389184 */ GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(389255), // Rule ID 11819 //
     /*  389189 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  389192 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  389195 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389202 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389209 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389217 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389224 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389227 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389249 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389253 */   GIR_RootConstrainSelectedInstOperands,
     /*  389254 */   // GIR_Coverage, 11819,
     /*  389254 */   GIR_EraseRootFromParent_Done,
     /*  389255 */ // Label 5775: @389255
     /*  389255 */ GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(389326), // Rule ID 11820 //
     /*  389260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  389263 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  389266 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389273 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389284 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389288 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389295 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389298 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389320 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389324 */   GIR_RootConstrainSelectedInstOperands,
     /*  389325 */   // GIR_Coverage, 11820,
     /*  389325 */   GIR_EraseRootFromParent_Done,
     /*  389326 */ // Label 5776: @389326
     /*  389326 */ GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(389397), // Rule ID 11821 //
     /*  389331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  389334 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  389337 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389344 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389355 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389359 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389366 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389391 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389395 */   GIR_RootConstrainSelectedInstOperands,
     /*  389396 */   // GIR_Coverage, 11821,
     /*  389396 */   GIR_EraseRootFromParent_Done,
     /*  389397 */ // Label 5777: @389397
     /*  389397 */ GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(389468), // Rule ID 11877 //
     /*  389402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  389405 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389408 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389415 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389426 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389430 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389437 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389440 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389442 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389466 */   GIR_RootConstrainSelectedInstOperands,
     /*  389467 */   // GIR_Coverage, 11877,
     /*  389467 */   GIR_EraseRootFromParent_Done,
     /*  389468 */ // Label 5778: @389468
     /*  389468 */ GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(389539), // Rule ID 11878 //
     /*  389473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  389476 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389479 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389486 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389497 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389501 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389508 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389511 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389537 */   GIR_RootConstrainSelectedInstOperands,
     /*  389538 */   // GIR_Coverage, 11878,
     /*  389538 */   GIR_EraseRootFromParent_Done,
     /*  389539 */ // Label 5779: @389539
     /*  389539 */ GIM_Try, /*On fail goto*//*Label 5780*/ GIMT_Encode4(389610), // Rule ID 11879 //
     /*  389544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  389547 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389550 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389557 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389564 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389568 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389572 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389579 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389582 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389604 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389608 */   GIR_RootConstrainSelectedInstOperands,
     /*  389609 */   // GIR_Coverage, 11879,
     /*  389609 */   GIR_EraseRootFromParent_Done,
     /*  389610 */ // Label 5780: @389610
     /*  389610 */ GIM_Try, /*On fail goto*//*Label 5781*/ GIMT_Encode4(389681), // Rule ID 11880 //
     /*  389615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  389618 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389621 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389628 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389635 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389639 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389643 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389650 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389650 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389653 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389675 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389679 */   GIR_RootConstrainSelectedInstOperands,
     /*  389680 */   // GIR_Coverage, 11880,
     /*  389680 */   GIR_EraseRootFromParent_Done,
     /*  389681 */ // Label 5781: @389681
     /*  389681 */ GIM_Try, /*On fail goto*//*Label 5782*/ GIMT_Encode4(389752), // Rule ID 11881 //
     /*  389686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  389689 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389692 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389699 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389706 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389710 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389714 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389721 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  389721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389724 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  389726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389746 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389750 */   GIR_RootConstrainSelectedInstOperands,
     /*  389751 */   // GIR_Coverage, 11881,
     /*  389751 */   GIR_EraseRootFromParent_Done,
     /*  389752 */ // Label 5782: @389752
     /*  389752 */ GIM_Try, /*On fail goto*//*Label 5783*/ GIMT_Encode4(389853), // Rule ID 11977 //
     /*  389757 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  389760 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389763 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389770 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  389781 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389785 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389792 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  389792 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  389795 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389799 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  389804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389824 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389828 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  389830 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  389833 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  389835 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  389842 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  389847 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389852 */   // GIR_Coverage, 11977,
     /*  389852 */   GIR_EraseRootFromParent_Done,
     /*  389853 */ // Label 5783: @389853
     /*  389853 */ GIM_Try, /*On fail goto*//*Label 5784*/ GIMT_Encode4(389954), // Rule ID 11978 //
     /*  389858 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  389861 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389864 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389878 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  389882 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389886 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389893 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  389893 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  389896 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  389900 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  389905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  389910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  389915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  389920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  389925 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  389929 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  389931 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  389934 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  389936 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  389943 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  389948 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  389953 */   // GIR_Coverage, 11978,
     /*  389953 */   GIR_EraseRootFromParent_Done,
     /*  389954 */ // Label 5784: @389954
     /*  389954 */ GIM_Try, /*On fail goto*//*Label 5785*/ GIMT_Encode4(390055), // Rule ID 11979 //
     /*  389959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  389962 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  389965 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  389972 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  389979 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  389983 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  389987 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  389994 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  389994 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  389997 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  390001 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  390006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  390011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  390016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  390021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  390026 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390030 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  390032 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  390035 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  390037 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  390044 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  390049 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390054 */   // GIR_Coverage, 11979,
     /*  390054 */   GIR_EraseRootFromParent_Done,
     /*  390055 */ // Label 5785: @390055
     /*  390055 */ GIM_Try, /*On fail goto*//*Label 5786*/ GIMT_Encode4(390156), // Rule ID 11980 //
     /*  390060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  390063 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390066 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  390084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390088 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  390095 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  390095 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  390098 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  390102 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  390107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  390112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  390117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  390122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  390127 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390131 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  390133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  390136 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  390138 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  390145 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  390150 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390155 */   // GIR_Coverage, 11980,
     /*  390155 */   GIR_EraseRootFromParent_Done,
     /*  390156 */ // Label 5786: @390156
     /*  390156 */ GIM_Try, /*On fail goto*//*Label 5787*/ GIMT_Encode4(390257), // Rule ID 11981 //
     /*  390161 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  390164 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390167 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390174 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  390185 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390189 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  390196 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol), lo16:{ *:[i32] })
     /*  390196 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  390199 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
     /*  390203 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  390208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  390213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  390218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  390223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  390228 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390232 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  390234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  390237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  390239 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  390246 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  390251 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390256 */   // GIR_Coverage, 11981,
     /*  390256 */   GIR_EraseRootFromParent_Done,
     /*  390257 */ // Label 5787: @390257
     /*  390257 */ GIM_Try, /*On fail goto*//*Label 5788*/ GIMT_Encode4(390321), // Rule ID 11732 //
     /*  390262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  390265 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390268 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390275 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390286 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390290 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390297 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  390300 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390315 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390319 */   GIR_RootConstrainSelectedInstOperands,
     /*  390320 */   // GIR_Coverage, 11732,
     /*  390320 */   GIR_EraseRootFromParent_Done,
     /*  390321 */ // Label 5788: @390321
     /*  390321 */ GIM_Try, /*On fail goto*//*Label 5789*/ GIMT_Encode4(390385), // Rule ID 11733 //
     /*  390326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  390329 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390332 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390339 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390350 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390354 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390361 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  390364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390371 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390376 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390383 */   GIR_RootConstrainSelectedInstOperands,
     /*  390384 */   // GIR_Coverage, 11733,
     /*  390384 */   GIR_EraseRootFromParent_Done,
     /*  390385 */ // Label 5789: @390385
     /*  390385 */ GIM_Try, /*On fail goto*//*Label 5790*/ GIMT_Encode4(390449), // Rule ID 11734 //
     /*  390390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  390393 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390410 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390414 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390418 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390425 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390425 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  390428 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390447 */   GIR_RootConstrainSelectedInstOperands,
     /*  390448 */   // GIR_Coverage, 11734,
     /*  390448 */   GIR_EraseRootFromParent_Done,
     /*  390449 */ // Label 5790: @390449
     /*  390449 */ GIM_Try, /*On fail goto*//*Label 5791*/ GIMT_Encode4(390513), // Rule ID 11735 //
     /*  390454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  390457 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390460 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390467 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390489 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  390492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390504 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390507 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390511 */   GIR_RootConstrainSelectedInstOperands,
     /*  390512 */   // GIR_Coverage, 11735,
     /*  390512 */   GIR_EraseRootFromParent_Done,
     /*  390513 */ // Label 5791: @390513
     /*  390513 */ GIM_Try, /*On fail goto*//*Label 5792*/ GIMT_Encode4(390577), // Rule ID 11736 //
     /*  390518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  390521 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390524 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390531 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390538 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390542 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390546 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390553 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  390556 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390571 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390575 */   GIR_RootConstrainSelectedInstOperands,
     /*  390576 */   // GIR_Coverage, 11736,
     /*  390576 */   GIR_EraseRootFromParent_Done,
     /*  390577 */ // Label 5792: @390577
     /*  390577 */ GIM_Try, /*On fail goto*//*Label 5793*/ GIMT_Encode4(390641), // Rule ID 11752 //
     /*  390582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  390585 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390588 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390595 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390617 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  390620 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390635 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390639 */   GIR_RootConstrainSelectedInstOperands,
     /*  390640 */   // GIR_Coverage, 11752,
     /*  390640 */   GIR_EraseRootFromParent_Done,
     /*  390641 */ // Label 5793: @390641
     /*  390641 */ GIM_Try, /*On fail goto*//*Label 5794*/ GIMT_Encode4(390705), // Rule ID 11753 //
     /*  390646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  390649 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390652 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390659 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390670 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390674 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390681 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  390684 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390696 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390699 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390703 */   GIR_RootConstrainSelectedInstOperands,
     /*  390704 */   // GIR_Coverage, 11753,
     /*  390704 */   GIR_EraseRootFromParent_Done,
     /*  390705 */ // Label 5794: @390705
     /*  390705 */ GIM_Try, /*On fail goto*//*Label 5795*/ GIMT_Encode4(390769), // Rule ID 11754 //
     /*  390710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  390713 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390716 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390723 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390734 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390738 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390745 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390745 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  390748 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390760 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390763 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390767 */   GIR_RootConstrainSelectedInstOperands,
     /*  390768 */   // GIR_Coverage, 11754,
     /*  390768 */   GIR_EraseRootFromParent_Done,
     /*  390769 */ // Label 5795: @390769
     /*  390769 */ GIM_Try, /*On fail goto*//*Label 5796*/ GIMT_Encode4(390833), // Rule ID 11755 //
     /*  390774 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  390777 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390780 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390787 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390798 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390802 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390809 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390809 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  390812 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390831 */   GIR_RootConstrainSelectedInstOperands,
     /*  390832 */   // GIR_Coverage, 11755,
     /*  390832 */   GIR_EraseRootFromParent_Done,
     /*  390833 */ // Label 5796: @390833
     /*  390833 */ GIM_Try, /*On fail goto*//*Label 5797*/ GIMT_Encode4(390897), // Rule ID 11756 //
     /*  390838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  390841 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  390844 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  390851 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390862 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390866 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390873 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  390876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390888 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390891 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390895 */   GIR_RootConstrainSelectedInstOperands,
     /*  390896 */   // GIR_Coverage, 11756,
     /*  390896 */   GIR_EraseRootFromParent_Done,
     /*  390897 */ // Label 5797: @390897
     /*  390897 */ GIM_Try, /*On fail goto*//*Label 5798*/ GIMT_Encode4(390961), // Rule ID 11782 //
     /*  390902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  390905 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  390908 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390915 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390926 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390930 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  390937 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  390937 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  390940 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  390942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  390947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  390952 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  390955 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  390959 */   GIR_RootConstrainSelectedInstOperands,
     /*  390960 */   // GIR_Coverage, 11782,
     /*  390960 */   GIR_EraseRootFromParent_Done,
     /*  390961 */ // Label 5798: @390961
     /*  390961 */ GIM_Try, /*On fail goto*//*Label 5799*/ GIMT_Encode4(391025), // Rule ID 11783 //
     /*  390966 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  390969 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  390972 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  390979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  390986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  390990 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  390994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391001 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  391004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391023 */   GIR_RootConstrainSelectedInstOperands,
     /*  391024 */   // GIR_Coverage, 11783,
     /*  391024 */   GIR_EraseRootFromParent_Done,
     /*  391025 */ // Label 5799: @391025
     /*  391025 */ GIM_Try, /*On fail goto*//*Label 5800*/ GIMT_Encode4(391089), // Rule ID 11784 //
     /*  391030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  391033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391036 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  391043 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391054 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391058 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391065 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391065 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  391068 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391087 */   GIR_RootConstrainSelectedInstOperands,
     /*  391088 */   // GIR_Coverage, 11784,
     /*  391088 */   GIR_EraseRootFromParent_Done,
     /*  391089 */ // Label 5800: @391089
     /*  391089 */ GIM_Try, /*On fail goto*//*Label 5801*/ GIMT_Encode4(391153), // Rule ID 11785 //
     /*  391094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  391097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391100 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  391107 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391118 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391122 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391129 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391129 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  391132 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391139 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391144 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391147 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391151 */   GIR_RootConstrainSelectedInstOperands,
     /*  391152 */   // GIR_Coverage, 11785,
     /*  391152 */   GIR_EraseRootFromParent_Done,
     /*  391153 */ // Label 5801: @391153
     /*  391153 */ GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(391217), // Rule ID 11786 //
     /*  391158 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  391161 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391164 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  391171 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391178 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391182 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391186 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391193 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391193 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
     /*  391196 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391208 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391211 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391215 */   GIR_RootConstrainSelectedInstOperands,
     /*  391216 */   // GIR_Coverage, 11786,
     /*  391216 */   GIR_EraseRootFromParent_Done,
     /*  391217 */ // Label 5802: @391217
     /*  391217 */ GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(391281), // Rule ID 11812 //
     /*  391222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  391225 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391228 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391235 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391242 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391246 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391250 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391257 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391279 */   GIR_RootConstrainSelectedInstOperands,
     /*  391280 */   // GIR_Coverage, 11812,
     /*  391280 */   GIR_EraseRootFromParent_Done,
     /*  391281 */ // Label 5803: @391281
     /*  391281 */ GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(391345), // Rule ID 11813 //
     /*  391286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  391289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391321 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391321 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391324 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391339 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391343 */   GIR_RootConstrainSelectedInstOperands,
     /*  391344 */   // GIR_Coverage, 11813,
     /*  391344 */   GIR_EraseRootFromParent_Done,
     /*  391345 */ // Label 5804: @391345
     /*  391345 */ GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(391409), // Rule ID 11814 //
     /*  391350 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  391353 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391356 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391374 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391378 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391385 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391388 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391400 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391403 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391407 */   GIR_RootConstrainSelectedInstOperands,
     /*  391408 */   // GIR_Coverage, 11814,
     /*  391408 */   GIR_EraseRootFromParent_Done,
     /*  391409 */ // Label 5805: @391409
     /*  391409 */ GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(391473), // Rule ID 11815 //
     /*  391414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  391417 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391420 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391427 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391434 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391438 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391442 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391449 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391449 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391452 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391464 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391471 */   GIR_RootConstrainSelectedInstOperands,
     /*  391472 */   // GIR_Coverage, 11815,
     /*  391472 */   GIR_EraseRootFromParent_Done,
     /*  391473 */ // Label 5806: @391473
     /*  391473 */ GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(391537), // Rule ID 11816 //
     /*  391478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  391481 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  391484 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391491 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391502 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391506 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391513 */   // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391513 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391516 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391531 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391535 */   GIR_RootConstrainSelectedInstOperands,
     /*  391536 */   // GIR_Coverage, 11816,
     /*  391536 */   GIR_EraseRootFromParent_Done,
     /*  391537 */ // Label 5807: @391537
     /*  391537 */ GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(391601), // Rule ID 11872 //
     /*  391542 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  391545 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391548 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391555 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391562 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391570 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391577 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391580 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391592 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391595 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391599 */   GIR_RootConstrainSelectedInstOperands,
     /*  391600 */   // GIR_Coverage, 11872,
     /*  391600 */   GIR_EraseRootFromParent_Done,
     /*  391601 */ // Label 5808: @391601
     /*  391601 */ GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(391665), // Rule ID 11873 //
     /*  391606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  391609 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391612 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391626 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391630 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391641 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391656 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391659 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391663 */   GIR_RootConstrainSelectedInstOperands,
     /*  391664 */   // GIR_Coverage, 11873,
     /*  391664 */   GIR_EraseRootFromParent_Done,
     /*  391665 */ // Label 5809: @391665
     /*  391665 */ GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(391729), // Rule ID 11874 //
     /*  391670 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  391673 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391676 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391683 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391705 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391708 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391723 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391727 */   GIR_RootConstrainSelectedInstOperands,
     /*  391728 */   // GIR_Coverage, 11874,
     /*  391728 */   GIR_EraseRootFromParent_Done,
     /*  391729 */ // Label 5810: @391729
     /*  391729 */ GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(391793), // Rule ID 11875 //
     /*  391734 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  391737 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391740 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391747 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391758 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391762 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391769 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391772 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391784 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391787 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391791 */   GIR_RootConstrainSelectedInstOperands,
     /*  391792 */   // GIR_Coverage, 11875,
     /*  391792 */   GIR_EraseRootFromParent_Done,
     /*  391793 */ // Label 5811: @391793
     /*  391793 */ GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(391857), // Rule ID 11876 //
     /*  391798 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  391801 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391804 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391811 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391818 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391826 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391833 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  391833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391836 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  391838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  391851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391855 */   GIR_RootConstrainSelectedInstOperands,
     /*  391856 */   // GIR_Coverage, 11876,
     /*  391856 */   GIR_EraseRootFromParent_Done,
     /*  391857 */ // Label 5812: @391857
     /*  391857 */ GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(391951), // Rule ID 11972 //
     /*  391862 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode0),
     /*  391865 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391868 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391875 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391882 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  391886 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391890 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391897 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  391897 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  391900 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391904 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  391909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  391914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  391919 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  391922 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  391926 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  391928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  391931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  391933 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  391940 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  391945 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  391950 */   // GIR_Coverage, 11972,
     /*  391950 */   GIR_EraseRootFromParent_Done,
     /*  391951 */ // Label 5813: @391951
     /*  391951 */ GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(392045), // Rule ID 11973 //
     /*  391956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode1),
     /*  391959 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  391962 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  391969 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  391976 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  391980 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  391984 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  391991 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  391991 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  391994 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  391998 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  392003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  392008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  392013 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  392016 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392020 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  392022 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  392025 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  392027 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  392034 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392039 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392044 */   // GIR_Coverage, 11973,
     /*  392044 */   GIR_EraseRootFromParent_Done,
     /*  392045 */ // Label 5814: @392045
     /*  392045 */ GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(392139), // Rule ID 11974 //
     /*  392050 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode2),
     /*  392053 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392056 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392063 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  392085 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  392085 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  392088 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  392092 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  392097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  392102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  392107 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  392110 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392114 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  392116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  392119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  392121 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  392128 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392133 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392138 */   // GIR_Coverage, 11974,
     /*  392138 */   GIR_EraseRootFromParent_Done,
     /*  392139 */ // Label 5815: @392139
     /*  392139 */ GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(392233), // Rule ID 11975 //
     /*  392144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode3),
     /*  392147 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392150 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392168 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392172 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  392179 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  392179 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  392182 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  392186 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  392191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  392196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  392201 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  392204 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392208 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  392210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  392213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  392215 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  392222 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392227 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392232 */   // GIR_Coverage, 11975,
     /*  392232 */   GIR_EraseRootFromParent_Done,
     /*  392233 */ // Label 5816: @392233
     /*  392233 */ GIM_Try, /*On fail goto*//*Label 5817*/ GIMT_Encode4(392327), // Rule ID 11976 //
     /*  392238 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseTrue16WithSramECC_HwMode4),
     /*  392241 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392244 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392262 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392266 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  392273 */   // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_global>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }), lo16:{ *:[i32] })
     /*  392273 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  392276 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
     /*  392280 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  392285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  392290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  392295 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  392298 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392302 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  392304 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  392307 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  392309 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::lo16),
     /*  392316 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  392321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392326 */   // GIR_Coverage, 11976,
     /*  392326 */   GIR_EraseRootFromParent_Done,
     /*  392327 */ // Label 5817: @392327
     /*  392327 */ GIM_Try, /*On fail goto*//*Label 5818*/ GIMT_Encode4(392399), // Rule ID 9531 //
     /*  392332 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  392335 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392338 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  392345 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392353 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392357 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392361 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392368 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392368 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  392371 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392397 */   GIR_RootConstrainSelectedInstOperands,
     /*  392398 */   // GIR_Coverage, 9531,
     /*  392398 */   GIR_EraseRootFromParent_Done,
     /*  392399 */ // Label 5818: @392399
     /*  392399 */ GIM_Try, /*On fail goto*//*Label 5819*/ GIMT_Encode4(392471), // Rule ID 9532 //
     /*  392404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  392407 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392410 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  392417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392425 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392429 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392433 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392440 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392440 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  392443 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392465 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392469 */   GIR_RootConstrainSelectedInstOperands,
     /*  392470 */   // GIR_Coverage, 9532,
     /*  392470 */   GIR_EraseRootFromParent_Done,
     /*  392471 */ // Label 5819: @392471
     /*  392471 */ GIM_Try, /*On fail goto*//*Label 5820*/ GIMT_Encode4(392543), // Rule ID 9533 //
     /*  392476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  392479 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392482 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  392489 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392497 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392512 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  392515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392541 */   GIR_RootConstrainSelectedInstOperands,
     /*  392542 */   // GIR_Coverage, 9533,
     /*  392542 */   GIR_EraseRootFromParent_Done,
     /*  392543 */ // Label 5820: @392543
     /*  392543 */ GIM_Try, /*On fail goto*//*Label 5821*/ GIMT_Encode4(392615), // Rule ID 9534 //
     /*  392548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  392551 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  392561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392577 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392584 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  392587 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392613 */   GIR_RootConstrainSelectedInstOperands,
     /*  392614 */   // GIR_Coverage, 9534,
     /*  392614 */   GIR_EraseRootFromParent_Done,
     /*  392615 */ // Label 5821: @392615
     /*  392615 */ GIM_Try, /*On fail goto*//*Label 5822*/ GIMT_Encode4(392687), // Rule ID 9535 //
     /*  392620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  392623 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  392633 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392645 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392649 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392656 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392656 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  392659 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392681 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392685 */   GIR_RootConstrainSelectedInstOperands,
     /*  392686 */   // GIR_Coverage, 9535,
     /*  392686 */   GIR_EraseRootFromParent_Done,
     /*  392687 */ // Label 5822: @392687
     /*  392687 */ GIM_Try, /*On fail goto*//*Label 5823*/ GIMT_Encode4(392759), // Rule ID 9551 //
     /*  392692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  392695 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392698 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392705 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392717 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392721 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392728 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  392731 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392753 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392757 */   GIR_RootConstrainSelectedInstOperands,
     /*  392758 */   // GIR_Coverage, 9551,
     /*  392758 */   GIR_EraseRootFromParent_Done,
     /*  392759 */ // Label 5823: @392759
     /*  392759 */ GIM_Try, /*On fail goto*//*Label 5824*/ GIMT_Encode4(392831), // Rule ID 9552 //
     /*  392764 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  392767 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392770 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392777 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392789 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392793 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392800 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392800 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  392803 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392825 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392829 */   GIR_RootConstrainSelectedInstOperands,
     /*  392830 */   // GIR_Coverage, 9552,
     /*  392830 */   GIR_EraseRootFromParent_Done,
     /*  392831 */ // Label 5824: @392831
     /*  392831 */ GIM_Try, /*On fail goto*//*Label 5825*/ GIMT_Encode4(392903), // Rule ID 9553 //
     /*  392836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  392839 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392842 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392849 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392861 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392865 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392872 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  392875 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392897 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392901 */   GIR_RootConstrainSelectedInstOperands,
     /*  392902 */   // GIR_Coverage, 9553,
     /*  392902 */   GIR_EraseRootFromParent_Done,
     /*  392903 */ // Label 5825: @392903
     /*  392903 */ GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(392975), // Rule ID 9554 //
     /*  392908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  392911 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392914 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392921 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  392929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  392933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  392937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  392944 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  392944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  392947 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  392949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  392954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  392959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  392964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  392969 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  392973 */   GIR_RootConstrainSelectedInstOperands,
     /*  392974 */   // GIR_Coverage, 9554,
     /*  392974 */   GIR_EraseRootFromParent_Done,
     /*  392975 */ // Label 5826: @392975
     /*  392975 */ GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(393047), // Rule ID 9555 //
     /*  392980 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  392983 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  392986 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  392993 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393005 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393009 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393016 */   // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393016 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  393019 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393041 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393045 */   GIR_RootConstrainSelectedInstOperands,
     /*  393046 */   // GIR_Coverage, 9555,
     /*  393046 */   GIR_EraseRootFromParent_Done,
     /*  393047 */ // Label 5827: @393047
     /*  393047 */ GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(393119), // Rule ID 9581 //
     /*  393052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  393055 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393058 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393077 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393088 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  393091 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393117 */   GIR_RootConstrainSelectedInstOperands,
     /*  393118 */   // GIR_Coverage, 9581,
     /*  393118 */   GIR_EraseRootFromParent_Done,
     /*  393119 */ // Label 5828: @393119
     /*  393119 */ GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(393191), // Rule ID 9582 //
     /*  393124 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  393127 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393149 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393153 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393160 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  393163 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393185 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393189 */   GIR_RootConstrainSelectedInstOperands,
     /*  393190 */   // GIR_Coverage, 9582,
     /*  393190 */   GIR_EraseRootFromParent_Done,
     /*  393191 */ // Label 5829: @393191
     /*  393191 */ GIM_Try, /*On fail goto*//*Label 5830*/ GIMT_Encode4(393263), // Rule ID 9583 //
     /*  393196 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  393199 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393202 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393209 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393217 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393221 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393225 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393232 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  393235 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393257 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393261 */   GIR_RootConstrainSelectedInstOperands,
     /*  393262 */   // GIR_Coverage, 9583,
     /*  393262 */   GIR_EraseRootFromParent_Done,
     /*  393263 */ // Label 5830: @393263
     /*  393263 */ GIM_Try, /*On fail goto*//*Label 5831*/ GIMT_Encode4(393335), // Rule ID 9584 //
     /*  393268 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  393271 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393274 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393281 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393293 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393297 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393304 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393304 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  393307 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393309 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393333 */   GIR_RootConstrainSelectedInstOperands,
     /*  393334 */   // GIR_Coverage, 9584,
     /*  393334 */   GIR_EraseRootFromParent_Done,
     /*  393335 */ // Label 5831: @393335
     /*  393335 */ GIM_Try, /*On fail goto*//*Label 5832*/ GIMT_Encode4(393407), // Rule ID 9585 //
     /*  393340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  393343 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393346 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393353 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393376 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE_SADDR),
     /*  393379 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393401 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393405 */   GIR_RootConstrainSelectedInstOperands,
     /*  393406 */   // GIR_Coverage, 9585,
     /*  393406 */   GIR_EraseRootFromParent_Done,
     /*  393407 */ // Label 5832: @393407
     /*  393407 */ GIM_Try, /*On fail goto*//*Label 5833*/ GIMT_Encode4(393479), // Rule ID 9621 //
     /*  393412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  393415 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393418 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  393425 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393448 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  393451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393477 */   GIR_RootConstrainSelectedInstOperands,
     /*  393478 */   // GIR_Coverage, 9621,
     /*  393478 */   GIR_EraseRootFromParent_Done,
     /*  393479 */ // Label 5833: @393479
     /*  393479 */ GIM_Try, /*On fail goto*//*Label 5834*/ GIMT_Encode4(393551), // Rule ID 9622 //
     /*  393484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  393487 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393490 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  393497 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393505 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393509 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393513 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393520 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  393523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393549 */   GIR_RootConstrainSelectedInstOperands,
     /*  393550 */   // GIR_Coverage, 9622,
     /*  393550 */   GIR_EraseRootFromParent_Done,
     /*  393551 */ // Label 5834: @393551
     /*  393551 */ GIM_Try, /*On fail goto*//*Label 5835*/ GIMT_Encode4(393623), // Rule ID 9623 //
     /*  393556 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  393559 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393562 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  393569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393577 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393581 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393585 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393592 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393592 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  393595 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393617 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393621 */   GIR_RootConstrainSelectedInstOperands,
     /*  393622 */   // GIR_Coverage, 9623,
     /*  393622 */   GIR_EraseRootFromParent_Done,
     /*  393623 */ // Label 5835: @393623
     /*  393623 */ GIM_Try, /*On fail goto*//*Label 5836*/ GIMT_Encode4(393695), // Rule ID 9624 //
     /*  393628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  393631 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393634 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  393641 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393653 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393657 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393664 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  393667 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393689 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393693 */   GIR_RootConstrainSelectedInstOperands,
     /*  393694 */   // GIR_Coverage, 9624,
     /*  393694 */   GIR_EraseRootFromParent_Done,
     /*  393695 */ // Label 5836: @393695
     /*  393695 */ GIM_Try, /*On fail goto*//*Label 5837*/ GIMT_Encode4(393767), // Rule ID 9625 //
     /*  393700 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  393703 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  393706 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  393713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393721 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393725 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393729 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  393736 */   // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  393736 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT_SADDR),
     /*  393739 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  393746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  393751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  393756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  393761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393765 */   GIR_RootConstrainSelectedInstOperands,
     /*  393766 */   // GIR_Coverage, 9625,
     /*  393766 */   GIR_EraseRootFromParent_Done,
     /*  393767 */ // Label 5837: @393767
     /*  393767 */ GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(393832), // Rule ID 9526 //
     /*  393772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  393775 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  393778 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393785 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393797 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393801 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  393808 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  393808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  393811 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  393818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  393823 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  393826 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393830 */   GIR_RootConstrainSelectedInstOperands,
     /*  393831 */   // GIR_Coverage, 9526,
     /*  393831 */   GIR_EraseRootFromParent_Done,
     /*  393832 */ // Label 5838: @393832
     /*  393832 */ GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(393897), // Rule ID 9527 //
     /*  393837 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  393840 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  393843 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393850 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393862 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393866 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  393873 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  393873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  393876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  393883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  393888 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  393891 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393895 */   GIR_RootConstrainSelectedInstOperands,
     /*  393896 */   // GIR_Coverage, 9527,
     /*  393896 */   GIR_EraseRootFromParent_Done,
     /*  393897 */ // Label 5839: @393897
     /*  393897 */ GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(393962), // Rule ID 9528 //
     /*  393902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  393905 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  393908 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393915 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393923 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393927 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393931 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  393938 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  393938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  393941 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  393943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  393948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  393953 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  393956 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  393960 */   GIR_RootConstrainSelectedInstOperands,
     /*  393961 */   // GIR_Coverage, 9528,
     /*  393961 */   GIR_EraseRootFromParent_Done,
     /*  393962 */ // Label 5840: @393962
     /*  393962 */ GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(394027), // Rule ID 9529 //
     /*  393967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  393970 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  393973 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  393980 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  393988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  393992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  393996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394003 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394006 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394021 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394025 */   GIR_RootConstrainSelectedInstOperands,
     /*  394026 */   // GIR_Coverage, 9529,
     /*  394026 */   GIR_EraseRootFromParent_Done,
     /*  394027 */ // Label 5841: @394027
     /*  394027 */ GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(394092), // Rule ID 9530 //
     /*  394032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  394035 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  394038 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  394045 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394053 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394057 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394061 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394068 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_atomic_load_zext_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394068 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394071 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394086 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394090 */   GIR_RootConstrainSelectedInstOperands,
     /*  394091 */   // GIR_Coverage, 9530,
     /*  394091 */   GIR_EraseRootFromParent_Done,
     /*  394092 */ // Label 5842: @394092
     /*  394092 */ GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(394157), // Rule ID 9546 //
     /*  394097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  394100 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  394103 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394110 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394118 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394122 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394126 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394133 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394136 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394148 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394151 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394155 */   GIR_RootConstrainSelectedInstOperands,
     /*  394156 */   // GIR_Coverage, 9546,
     /*  394156 */   GIR_EraseRootFromParent_Done,
     /*  394157 */ // Label 5843: @394157
     /*  394157 */ GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(394222), // Rule ID 9547 //
     /*  394162 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  394165 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  394168 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394175 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394187 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394191 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394198 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394201 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394213 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394216 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394220 */   GIR_RootConstrainSelectedInstOperands,
     /*  394221 */   // GIR_Coverage, 9547,
     /*  394221 */   GIR_EraseRootFromParent_Done,
     /*  394222 */ // Label 5844: @394222
     /*  394222 */ GIM_Try, /*On fail goto*//*Label 5845*/ GIMT_Encode4(394287), // Rule ID 9548 //
     /*  394227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  394230 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  394233 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394240 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394252 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394256 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394263 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394278 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394281 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394285 */   GIR_RootConstrainSelectedInstOperands,
     /*  394286 */   // GIR_Coverage, 9548,
     /*  394286 */   GIR_EraseRootFromParent_Done,
     /*  394287 */ // Label 5845: @394287
     /*  394287 */ GIM_Try, /*On fail goto*//*Label 5846*/ GIMT_Encode4(394352), // Rule ID 9549 //
     /*  394292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  394295 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  394298 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394305 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394313 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394317 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394321 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394328 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394328 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394331 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394343 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394346 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394350 */   GIR_RootConstrainSelectedInstOperands,
     /*  394351 */   // GIR_Coverage, 9549,
     /*  394351 */   GIR_EraseRootFromParent_Done,
     /*  394352 */ // Label 5846: @394352
     /*  394352 */ GIM_Try, /*On fail goto*//*Label 5847*/ GIMT_Encode4(394417), // Rule ID 9550 //
     /*  394357 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  394360 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  394363 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394370 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394382 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394393 */   // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_atomic_load_zext_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394396 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394415 */   GIR_RootConstrainSelectedInstOperands,
     /*  394416 */   // GIR_Coverage, 9550,
     /*  394416 */   GIR_EraseRootFromParent_Done,
     /*  394417 */ // Label 5847: @394417
     /*  394417 */ GIM_Try, /*On fail goto*//*Label 5848*/ GIMT_Encode4(394482), // Rule ID 9576 //
     /*  394422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  394425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394428 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  394435 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394443 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394447 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394451 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394458 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394458 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394461 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394473 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394476 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394480 */   GIR_RootConstrainSelectedInstOperands,
     /*  394481 */   // GIR_Coverage, 9576,
     /*  394481 */   GIR_EraseRootFromParent_Done,
     /*  394482 */ // Label 5848: @394482
     /*  394482 */ GIM_Try, /*On fail goto*//*Label 5849*/ GIMT_Encode4(394547), // Rule ID 9577 //
     /*  394487 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  394490 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394493 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  394500 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394512 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394516 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394523 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394526 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394538 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394541 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394545 */   GIR_RootConstrainSelectedInstOperands,
     /*  394546 */   // GIR_Coverage, 9577,
     /*  394546 */   GIR_EraseRootFromParent_Done,
     /*  394547 */ // Label 5849: @394547
     /*  394547 */ GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(394612), // Rule ID 9578 //
     /*  394552 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  394555 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394558 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  394565 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394577 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394581 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394588 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394588 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394591 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394606 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394610 */   GIR_RootConstrainSelectedInstOperands,
     /*  394611 */   // GIR_Coverage, 9578,
     /*  394611 */   GIR_EraseRootFromParent_Done,
     /*  394612 */ // Label 5850: @394612
     /*  394612 */ GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(394677), // Rule ID 9579 //
     /*  394617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  394620 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394623 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  394630 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394653 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394656 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394671 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394675 */   GIR_RootConstrainSelectedInstOperands,
     /*  394676 */   // GIR_Coverage, 9579,
     /*  394676 */   GIR_EraseRootFromParent_Done,
     /*  394677 */ // Label 5851: @394677
     /*  394677 */ GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(394742), // Rule ID 9580 //
     /*  394682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  394685 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394688 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  394695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394707 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394711 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394718 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394718 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
     /*  394721 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394733 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394736 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394740 */   GIR_RootConstrainSelectedInstOperands,
     /*  394741 */   // GIR_Coverage, 9580,
     /*  394741 */   GIR_EraseRootFromParent_Done,
     /*  394742 */ // Label 5852: @394742
     /*  394742 */ GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(394807), // Rule ID 9616 //
     /*  394747 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  394750 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394753 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394760 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394768 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394772 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394776 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394783 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394786 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394805 */   GIR_RootConstrainSelectedInstOperands,
     /*  394806 */   // GIR_Coverage, 9616,
     /*  394806 */   GIR_EraseRootFromParent_Done,
     /*  394807 */ // Label 5853: @394807
     /*  394807 */ GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(394872), // Rule ID 9617 //
     /*  394812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  394815 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394818 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394825 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394837 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394841 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394848 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394848 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394851 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394863 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394866 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394870 */   GIR_RootConstrainSelectedInstOperands,
     /*  394871 */   // GIR_Coverage, 9617,
     /*  394871 */   GIR_EraseRootFromParent_Done,
     /*  394872 */ // Label 5854: @394872
     /*  394872 */ GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(394937), // Rule ID 9618 //
     /*  394877 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  394880 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394883 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394890 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394902 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394906 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394913 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394913 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394916 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394928 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394931 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  394935 */   GIR_RootConstrainSelectedInstOperands,
     /*  394936 */   // GIR_Coverage, 9618,
     /*  394936 */   GIR_EraseRootFromParent_Done,
     /*  394937 */ // Label 5855: @394937
     /*  394937 */ GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(395002), // Rule ID 9619 //
     /*  394942 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  394945 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  394948 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  394955 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  394963 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  394967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  394971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  394978 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  394978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  394981 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  394983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  394988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  394993 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  394996 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395000 */   GIR_RootConstrainSelectedInstOperands,
     /*  395001 */   // GIR_Coverage, 9619,
     /*  395001 */   GIR_EraseRootFromParent_Done,
     /*  395002 */ // Label 5856: @395002
     /*  395002 */ GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(395067), // Rule ID 9620 //
     /*  395007 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  395010 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  395013 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  395020 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  395028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  395032 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  395043 */   // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  395043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
     /*  395046 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  395048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  395053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395065 */   GIR_RootConstrainSelectedInstOperands,
     /*  395066 */   // GIR_Coverage, 9620,
     /*  395066 */   GIR_EraseRootFromParent_Done,
     /*  395067 */ // Label 5857: @395067
     /*  395067 */ GIM_Reject,
     /*  395068 */ // Label 5284: @395068
     /*  395068 */ GIM_Reject,
     /*  395069 */ // Label 17: @395069
     /*  395069 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(23), /*)*//*default:*//*Label 5875*/ GIMT_Encode4(570164),
     /*  395080 */ /*GILLT_p0s64*//*Label 5858*/ GIMT_Encode4(395172),
     /*  395084 */ /*GILLT_p1s64*//*Label 5859*/ GIMT_Encode4(399567),
     /*  395088 */ /*GILLT_p2s32*//*Label 5860*/ GIMT_Encode4(403962),
     /*  395092 */ /*GILLT_p3s32*//*Label 5861*/ GIMT_Encode4(408667),
     /*  395096 */ /*GILLT_p4s64*//*Label 5862*/ GIMT_Encode4(413372),
     /*  395100 */ /*GILLT_p5s32*//*Label 5863*/ GIMT_Encode4(417767),
     /*  395104 */ /*GILLT_p6s32*//*Label 5864*/ GIMT_Encode4(422472), GIMT_Encode4(0),
     /*  395112 */ /*GILLT_s16*//*Label 5865*/ GIMT_Encode4(427177),
     /*  395116 */ /*GILLT_s32*//*Label 5866*/ GIMT_Encode4(447101),
     /*  395120 */ /*GILLT_s64*//*Label 5867*/ GIMT_Encode4(486477),
     /*  395124 */ /*GILLT_v2s16*//*Label 5868*/ GIMT_Encode4(497915),
     /*  395128 */ /*GILLT_v2s32*//*Label 5869*/ GIMT_Encode4(507315),
     /*  395132 */ /*GILLT_v2s64*//*Label 5870*/ GIMT_Encode4(519038),
     /*  395136 */ /*GILLT_v3s32*//*Label 5871*/ GIMT_Encode4(529658), GIMT_Encode4(0),
     /*  395144 */ /*GILLT_v4s16*//*Label 5872*/ GIMT_Encode4(537153),
     /*  395148 */ /*GILLT_v4s32*//*Label 5873*/ GIMT_Encode4(545933), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  395168 */ /*GILLT_v8s16*//*Label 5874*/ GIMT_Encode4(559544),
     /*  395172 */ // Label 5858: @395172
     /*  395172 */ GIM_Try, /*On fail goto*//*Label 5876*/ GIMT_Encode4(399566),
     /*  395177 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  395180 */   GIM_Try, /*On fail goto*//*Label 5877*/ GIMT_Encode4(395241), // Rule ID 30073 //
     /*  395185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  395188 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395206 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  395210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395217 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395225 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395235 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395239 */     GIR_RootConstrainSelectedInstOperands,
     /*  395240 */     // GIR_Coverage, 30073,
     /*  395240 */     GIR_EraseRootFromParent_Done,
     /*  395241 */   // Label 5877: @395241
     /*  395241 */   GIM_Try, /*On fail goto*//*Label 5878*/ GIMT_Encode4(395302), // Rule ID 30074 //
     /*  395246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  395249 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395253 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395267 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  395271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395278 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395286 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395300 */     GIR_RootConstrainSelectedInstOperands,
     /*  395301 */     // GIR_Coverage, 30074,
     /*  395301 */     GIR_EraseRootFromParent_Done,
     /*  395302 */   // Label 5878: @395302
     /*  395302 */   GIM_Try, /*On fail goto*//*Label 5879*/ GIMT_Encode4(395363), // Rule ID 30075 //
     /*  395307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  395310 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395328 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  395332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395339 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395347 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395361 */     GIR_RootConstrainSelectedInstOperands,
     /*  395362 */     // GIR_Coverage, 30075,
     /*  395362 */     GIR_EraseRootFromParent_Done,
     /*  395363 */   // Label 5879: @395363
     /*  395363 */   GIM_Try, /*On fail goto*//*Label 5880*/ GIMT_Encode4(395424), // Rule ID 30076 //
     /*  395368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  395371 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395375 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395385 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395389 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  395393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395400 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395408 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395422 */     GIR_RootConstrainSelectedInstOperands,
     /*  395423 */     // GIR_Coverage, 30076,
     /*  395423 */     GIR_EraseRootFromParent_Done,
     /*  395424 */   // Label 5880: @395424
     /*  395424 */   GIM_Try, /*On fail goto*//*Label 5881*/ GIMT_Encode4(395485), // Rule ID 30077 //
     /*  395429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  395432 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395446 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395450 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  395454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395461 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395469 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395476 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395479 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395483 */     GIR_RootConstrainSelectedInstOperands,
     /*  395484 */     // GIR_Coverage, 30077,
     /*  395484 */     GIR_EraseRootFromParent_Done,
     /*  395485 */   // Label 5881: @395485
     /*  395485 */   GIM_Try, /*On fail goto*//*Label 5882*/ GIMT_Encode4(395541), // Rule ID 29733 //
     /*  395490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  395493 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395502 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  395506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395517 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395525 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395539 */     GIR_RootConstrainSelectedInstOperands,
     /*  395540 */     // GIR_Coverage, 29733,
     /*  395540 */     GIR_EraseRootFromParent_Done,
     /*  395541 */   // Label 5882: @395541
     /*  395541 */   GIM_Try, /*On fail goto*//*Label 5883*/ GIMT_Encode4(395597), // Rule ID 29734 //
     /*  395546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  395549 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395553 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395558 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  395562 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395566 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395573 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395581 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395591 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395595 */     GIR_RootConstrainSelectedInstOperands,
     /*  395596 */     // GIR_Coverage, 29734,
     /*  395596 */     GIR_EraseRootFromParent_Done,
     /*  395597 */   // Label 5883: @395597
     /*  395597 */   GIM_Try, /*On fail goto*//*Label 5884*/ GIMT_Encode4(395653), // Rule ID 29735 //
     /*  395602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  395605 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395614 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  395618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395629 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395637 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395651 */     GIR_RootConstrainSelectedInstOperands,
     /*  395652 */     // GIR_Coverage, 29735,
     /*  395652 */     GIR_EraseRootFromParent_Done,
     /*  395653 */   // Label 5884: @395653
     /*  395653 */   GIM_Try, /*On fail goto*//*Label 5885*/ GIMT_Encode4(395709), // Rule ID 29736 //
     /*  395658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  395661 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395670 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  395674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395685 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395693 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395703 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395707 */     GIR_RootConstrainSelectedInstOperands,
     /*  395708 */     // GIR_Coverage, 29736,
     /*  395708 */     GIR_EraseRootFromParent_Done,
     /*  395709 */   // Label 5885: @395709
     /*  395709 */   GIM_Try, /*On fail goto*//*Label 5886*/ GIMT_Encode4(395765), // Rule ID 29737 //
     /*  395714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  395717 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  395721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395726 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  395730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395741 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  395744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395749 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395759 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395763 */     GIR_RootConstrainSelectedInstOperands,
     /*  395764 */     // GIR_Coverage, 29737,
     /*  395764 */     GIR_EraseRootFromParent_Done,
     /*  395765 */   // Label 5886: @395765
     /*  395765 */   GIM_Try, /*On fail goto*//*Label 5887*/ GIMT_Encode4(395822), // Rule ID 30078 //
     /*  395770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  395773 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395778 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395787 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  395791 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395798 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  395801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395806 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395816 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395820 */     GIR_RootConstrainSelectedInstOperands,
     /*  395821 */     // GIR_Coverage, 30078,
     /*  395821 */     GIR_EraseRootFromParent_Done,
     /*  395822 */   // Label 5887: @395822
     /*  395822 */   GIM_Try, /*On fail goto*//*Label 5888*/ GIMT_Encode4(395879), // Rule ID 30079 //
     /*  395827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  395830 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395844 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  395848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395855 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  395858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395863 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395877 */     GIR_RootConstrainSelectedInstOperands,
     /*  395878 */     // GIR_Coverage, 30079,
     /*  395878 */     GIR_EraseRootFromParent_Done,
     /*  395879 */   // Label 5888: @395879
     /*  395879 */   GIM_Try, /*On fail goto*//*Label 5889*/ GIMT_Encode4(395936), // Rule ID 30080 //
     /*  395884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  395887 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395901 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  395905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395912 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  395915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395920 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395934 */     GIR_RootConstrainSelectedInstOperands,
     /*  395935 */     // GIR_Coverage, 30080,
     /*  395935 */     GIR_EraseRootFromParent_Done,
     /*  395936 */   // Label 5889: @395936
     /*  395936 */   GIM_Try, /*On fail goto*//*Label 5890*/ GIMT_Encode4(395993), // Rule ID 30081 //
     /*  395941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  395944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395949 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  395954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  395958 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  395962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  395969 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  395969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  395972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  395977 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  395979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  395984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  395987 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  395991 */     GIR_RootConstrainSelectedInstOperands,
     /*  395992 */     // GIR_Coverage, 30081,
     /*  395992 */     GIR_EraseRootFromParent_Done,
     /*  395993 */   // Label 5890: @395993
     /*  395993 */   GIM_Try, /*On fail goto*//*Label 5891*/ GIMT_Encode4(396050), // Rule ID 30082 //
     /*  395998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  396001 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396015 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  396019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  396026 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  396026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  396029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  396034 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  396036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396044 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396048 */     GIR_RootConstrainSelectedInstOperands,
     /*  396049 */     // GIR_Coverage, 30082,
     /*  396049 */     GIR_EraseRootFromParent_Done,
     /*  396050 */   // Label 5891: @396050
     /*  396050 */   GIM_Try, /*On fail goto*//*Label 5892*/ GIMT_Encode4(396102), // Rule ID 29738 //
     /*  396055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  396058 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396063 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  396067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  396078 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  396078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  396081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  396086 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  396088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396100 */     GIR_RootConstrainSelectedInstOperands,
     /*  396101 */     // GIR_Coverage, 29738,
     /*  396101 */     GIR_EraseRootFromParent_Done,
     /*  396102 */   // Label 5892: @396102
     /*  396102 */   GIM_Try, /*On fail goto*//*Label 5893*/ GIMT_Encode4(396154), // Rule ID 29739 //
     /*  396107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  396110 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396115 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  396119 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396123 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  396130 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  396130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  396133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  396138 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  396140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396148 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396152 */     GIR_RootConstrainSelectedInstOperands,
     /*  396153 */     // GIR_Coverage, 29739,
     /*  396153 */     GIR_EraseRootFromParent_Done,
     /*  396154 */   // Label 5893: @396154
     /*  396154 */   GIM_Try, /*On fail goto*//*Label 5894*/ GIMT_Encode4(396206), // Rule ID 29740 //
     /*  396159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  396162 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396167 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  396171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  396182 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  396182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  396185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  396190 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  396192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396204 */     GIR_RootConstrainSelectedInstOperands,
     /*  396205 */     // GIR_Coverage, 29740,
     /*  396205 */     GIR_EraseRootFromParent_Done,
     /*  396206 */   // Label 5894: @396206
     /*  396206 */   GIM_Try, /*On fail goto*//*Label 5895*/ GIMT_Encode4(396258), // Rule ID 29741 //
     /*  396211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  396214 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396219 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  396223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  396234 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  396234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  396237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  396242 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  396244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396249 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396252 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396256 */     GIR_RootConstrainSelectedInstOperands,
     /*  396257 */     // GIR_Coverage, 29741,
     /*  396257 */     GIR_EraseRootFromParent_Done,
     /*  396258 */   // Label 5895: @396258
     /*  396258 */   GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(396310), // Rule ID 29742 //
     /*  396263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  396266 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  396271 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  396275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  396286 */     // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  396286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  396289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  396294 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  396296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396308 */     GIR_RootConstrainSelectedInstOperands,
     /*  396309 */     // GIR_Coverage, 29742,
     /*  396309 */     GIR_EraseRootFromParent_Done,
     /*  396310 */   // Label 5896: @396310
     /*  396310 */   GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(396365), // Rule ID 14497 //
     /*  396315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  396318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  396334 */     // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  396334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  396337 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  396349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  396354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  396359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396363 */     GIR_RootConstrainSelectedInstOperands,
     /*  396364 */     // GIR_Coverage, 14497,
     /*  396364 */     GIR_EraseRootFromParent_Done,
     /*  396365 */   // Label 5897: @396365
     /*  396365 */   GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(396420), // Rule ID 14498 //
     /*  396370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  396373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  396389 */     // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  396389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  396392 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  396404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  396409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  396414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396418 */     GIR_RootConstrainSelectedInstOperands,
     /*  396419 */     // GIR_Coverage, 14498,
     /*  396419 */     GIR_EraseRootFromParent_Done,
     /*  396420 */   // Label 5898: @396420
     /*  396420 */   GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(396475), // Rule ID 14499 //
     /*  396425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  396428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  396444 */     // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  396444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  396447 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  396459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  396464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  396469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396473 */     GIR_RootConstrainSelectedInstOperands,
     /*  396474 */     // GIR_Coverage, 14499,
     /*  396474 */     GIR_EraseRootFromParent_Done,
     /*  396475 */   // Label 5899: @396475
     /*  396475 */   GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(396530), // Rule ID 14500 //
     /*  396480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  396483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  396499 */     // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  396499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  396502 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  396514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  396519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  396524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396528 */     GIR_RootConstrainSelectedInstOperands,
     /*  396529 */     // GIR_Coverage, 14500,
     /*  396529 */     GIR_EraseRootFromParent_Done,
     /*  396530 */   // Label 5900: @396530
     /*  396530 */   GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(396585), // Rule ID 14501 //
     /*  396535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  396538 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  396554 */     // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  396554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  396557 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  396569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  396574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  396579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396583 */     GIR_RootConstrainSelectedInstOperands,
     /*  396584 */     // GIR_Coverage, 14501,
     /*  396584 */     GIR_EraseRootFromParent_Done,
     /*  396585 */   // Label 5901: @396585
     /*  396585 */   GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(396633), // Rule ID 14492 //
     /*  396590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  396593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  396609 */     // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  396609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  396612 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  396619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396627 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396631 */     GIR_RootConstrainSelectedInstOperands,
     /*  396632 */     // GIR_Coverage, 14492,
     /*  396632 */     GIR_EraseRootFromParent_Done,
     /*  396633 */   // Label 5902: @396633
     /*  396633 */   GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(396681), // Rule ID 14493 //
     /*  396638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  396641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  396657 */     // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  396657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  396660 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  396667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396679 */     GIR_RootConstrainSelectedInstOperands,
     /*  396680 */     // GIR_Coverage, 14493,
     /*  396680 */     GIR_EraseRootFromParent_Done,
     /*  396681 */   // Label 5903: @396681
     /*  396681 */   GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(396729), // Rule ID 14494 //
     /*  396686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  396689 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  396705 */     // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  396705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  396708 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  396715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396727 */     GIR_RootConstrainSelectedInstOperands,
     /*  396728 */     // GIR_Coverage, 14494,
     /*  396728 */     GIR_EraseRootFromParent_Done,
     /*  396729 */   // Label 5904: @396729
     /*  396729 */   GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(396777), // Rule ID 14495 //
     /*  396734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  396737 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  396753 */     // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  396753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  396756 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  396763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396775 */     GIR_RootConstrainSelectedInstOperands,
     /*  396776 */     // GIR_Coverage, 14495,
     /*  396776 */     GIR_EraseRootFromParent_Done,
     /*  396777 */   // Label 5905: @396777
     /*  396777 */   GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(396825), // Rule ID 14496 //
     /*  396782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  396785 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  396801 */     // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  396801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  396804 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  396811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396823 */     GIR_RootConstrainSelectedInstOperands,
     /*  396824 */     // GIR_Coverage, 14496,
     /*  396824 */     GIR_EraseRootFromParent_Done,
     /*  396825 */   // Label 5906: @396825
     /*  396825 */   GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(396873), // Rule ID 14487 //
     /*  396830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  396833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396838 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  396849 */     // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  396849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  396852 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396867 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396871 */     GIR_RootConstrainSelectedInstOperands,
     /*  396872 */     // GIR_Coverage, 14487,
     /*  396872 */     GIR_EraseRootFromParent_Done,
     /*  396873 */   // Label 5907: @396873
     /*  396873 */   GIM_Try, /*On fail goto*//*Label 5908*/ GIMT_Encode4(396921), // Rule ID 14488 //
     /*  396878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  396881 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  396897 */     // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  396897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  396900 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396912 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396915 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396919 */     GIR_RootConstrainSelectedInstOperands,
     /*  396920 */     // GIR_Coverage, 14488,
     /*  396920 */     GIR_EraseRootFromParent_Done,
     /*  396921 */   // Label 5908: @396921
     /*  396921 */   GIM_Try, /*On fail goto*//*Label 5909*/ GIMT_Encode4(396969), // Rule ID 14489 //
     /*  396926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  396929 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396934 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396938 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  396945 */     // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  396945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  396948 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  396955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  396960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  396963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  396967 */     GIR_RootConstrainSelectedInstOperands,
     /*  396968 */     // GIR_Coverage, 14489,
     /*  396968 */     GIR_EraseRootFromParent_Done,
     /*  396969 */   // Label 5909: @396969
     /*  396969 */   GIM_Try, /*On fail goto*//*Label 5910*/ GIMT_Encode4(397017), // Rule ID 14490 //
     /*  396974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  396977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  396982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  396986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  396993 */     // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  396993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  396996 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  396998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  397003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  397008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397011 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397015 */     GIR_RootConstrainSelectedInstOperands,
     /*  397016 */     // GIR_Coverage, 14490,
     /*  397016 */     GIR_EraseRootFromParent_Done,
     /*  397017 */   // Label 5910: @397017
     /*  397017 */   GIM_Try, /*On fail goto*//*Label 5911*/ GIMT_Encode4(397065), // Rule ID 14491 //
     /*  397022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  397025 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  397030 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397034 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  397041 */     // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  397041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  397044 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  397046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  397051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  397056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397063 */     GIR_RootConstrainSelectedInstOperands,
     /*  397064 */     // GIR_Coverage, 14491,
     /*  397064 */     GIR_EraseRootFromParent_Done,
     /*  397065 */   // Label 5911: @397065
     /*  397065 */   GIM_Try, /*On fail goto*//*Label 5912*/ GIMT_Encode4(397128), // Rule ID 16178 //
     /*  397070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  397073 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397091 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  397094 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397126 */     GIR_RootConstrainSelectedInstOperands,
     /*  397127 */     // GIR_Coverage, 16178,
     /*  397127 */     GIR_EraseRootFromParent_Done,
     /*  397128 */   // Label 5912: @397128
     /*  397128 */   GIM_Try, /*On fail goto*//*Label 5913*/ GIMT_Encode4(397191), // Rule ID 16179 //
     /*  397133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  397136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397154 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  397157 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397185 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397189 */     GIR_RootConstrainSelectedInstOperands,
     /*  397190 */     // GIR_Coverage, 16179,
     /*  397190 */     GIR_EraseRootFromParent_Done,
     /*  397191 */   // Label 5913: @397191
     /*  397191 */   GIM_Try, /*On fail goto*//*Label 5914*/ GIMT_Encode4(397254), // Rule ID 16180 //
     /*  397196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  397199 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397217 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  397220 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397252 */     GIR_RootConstrainSelectedInstOperands,
     /*  397253 */     // GIR_Coverage, 16180,
     /*  397253 */     GIR_EraseRootFromParent_Done,
     /*  397254 */   // Label 5914: @397254
     /*  397254 */   GIM_Try, /*On fail goto*//*Label 5915*/ GIMT_Encode4(397317), // Rule ID 16181 //
     /*  397259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  397262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397280 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  397283 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397315 */     GIR_RootConstrainSelectedInstOperands,
     /*  397316 */     // GIR_Coverage, 16181,
     /*  397316 */     GIR_EraseRootFromParent_Done,
     /*  397317 */   // Label 5915: @397317
     /*  397317 */   GIM_Try, /*On fail goto*//*Label 5916*/ GIMT_Encode4(397380), // Rule ID 16182 //
     /*  397322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  397325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397332 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397343 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  397346 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397378 */     GIR_RootConstrainSelectedInstOperands,
     /*  397379 */     // GIR_Coverage, 16182,
     /*  397379 */     GIR_EraseRootFromParent_Done,
     /*  397380 */   // Label 5916: @397380
     /*  397380 */   GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(397443), // Rule ID 16188 //
     /*  397385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  397388 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397406 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  397409 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397441 */     GIR_RootConstrainSelectedInstOperands,
     /*  397442 */     // GIR_Coverage, 16188,
     /*  397442 */     GIR_EraseRootFromParent_Done,
     /*  397443 */   // Label 5917: @397443
     /*  397443 */   GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(397506), // Rule ID 16189 //
     /*  397448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  397451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397458 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397469 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  397472 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397504 */     GIR_RootConstrainSelectedInstOperands,
     /*  397505 */     // GIR_Coverage, 16189,
     /*  397505 */     GIR_EraseRootFromParent_Done,
     /*  397506 */   // Label 5918: @397506
     /*  397506 */   GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(397569), // Rule ID 16190 //
     /*  397511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  397514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397532 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  397535 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397567 */     GIR_RootConstrainSelectedInstOperands,
     /*  397568 */     // GIR_Coverage, 16190,
     /*  397568 */     GIR_EraseRootFromParent_Done,
     /*  397569 */   // Label 5919: @397569
     /*  397569 */   GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(397632), // Rule ID 16191 //
     /*  397574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  397577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397595 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  397598 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397630 */     GIR_RootConstrainSelectedInstOperands,
     /*  397631 */     // GIR_Coverage, 16191,
     /*  397631 */     GIR_EraseRootFromParent_Done,
     /*  397632 */   // Label 5920: @397632
     /*  397632 */   GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(397695), // Rule ID 16192 //
     /*  397637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  397640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  397658 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  397661 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  397668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  397678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  397683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397693 */     GIR_RootConstrainSelectedInstOperands,
     /*  397694 */     // GIR_Coverage, 16192,
     /*  397694 */     GIR_EraseRootFromParent_Done,
     /*  397695 */   // Label 5921: @397695
     /*  397695 */   GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(397812), // Rule ID 29472 //
     /*  397700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  397703 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  397707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  397712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  397723 */     // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  397723 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  397726 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  397730 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  397735 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  397741 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  397746 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  397751 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  397754 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  397758 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  397763 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  397769 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  397774 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  397779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  397782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  397787 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  397790 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  397793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  397798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  397803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397810 */     GIR_RootConstrainSelectedInstOperands,
     /*  397811 */     // GIR_Coverage, 29472,
     /*  397811 */     GIR_EraseRootFromParent_Done,
     /*  397812 */   // Label 5922: @397812
     /*  397812 */   GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(397870), // Rule ID 16173 //
     /*  397817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  397820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  397838 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  397841 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  397853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  397858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397868 */     GIR_RootConstrainSelectedInstOperands,
     /*  397869 */     // GIR_Coverage, 16173,
     /*  397869 */     GIR_EraseRootFromParent_Done,
     /*  397870 */   // Label 5923: @397870
     /*  397870 */   GIM_Try, /*On fail goto*//*Label 5924*/ GIMT_Encode4(397928), // Rule ID 16174 //
     /*  397875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  397878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  397896 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  397899 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  397911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  397916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397926 */     GIR_RootConstrainSelectedInstOperands,
     /*  397927 */     // GIR_Coverage, 16174,
     /*  397927 */     GIR_EraseRootFromParent_Done,
     /*  397928 */   // Label 5924: @397928
     /*  397928 */   GIM_Try, /*On fail goto*//*Label 5925*/ GIMT_Encode4(397986), // Rule ID 16175 //
     /*  397933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  397936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  397943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  397947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  397954 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  397954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  397957 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  397959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  397964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  397969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  397974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  397980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  397984 */     GIR_RootConstrainSelectedInstOperands,
     /*  397985 */     // GIR_Coverage, 16175,
     /*  397985 */     GIR_EraseRootFromParent_Done,
     /*  397986 */   // Label 5925: @397986
     /*  397986 */   GIM_Try, /*On fail goto*//*Label 5926*/ GIMT_Encode4(398044), // Rule ID 16176 //
     /*  397991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  397994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398012 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  398015 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398042 */     GIR_RootConstrainSelectedInstOperands,
     /*  398043 */     // GIR_Coverage, 16176,
     /*  398043 */     GIR_EraseRootFromParent_Done,
     /*  398044 */   // Label 5926: @398044
     /*  398044 */   GIM_Try, /*On fail goto*//*Label 5927*/ GIMT_Encode4(398102), // Rule ID 16177 //
     /*  398049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  398052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398059 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398063 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398070 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  398073 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398100 */     GIR_RootConstrainSelectedInstOperands,
     /*  398101 */     // GIR_Coverage, 16177,
     /*  398101 */     GIR_EraseRootFromParent_Done,
     /*  398102 */   // Label 5927: @398102
     /*  398102 */   GIM_Try, /*On fail goto*//*Label 5928*/ GIMT_Encode4(398160), // Rule ID 16183 //
     /*  398107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  398110 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398128 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  398131 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398158 */     GIR_RootConstrainSelectedInstOperands,
     /*  398159 */     // GIR_Coverage, 16183,
     /*  398159 */     GIR_EraseRootFromParent_Done,
     /*  398160 */   // Label 5928: @398160
     /*  398160 */   GIM_Try, /*On fail goto*//*Label 5929*/ GIMT_Encode4(398218), // Rule ID 16184 //
     /*  398165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  398168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398175 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398186 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  398189 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398209 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398216 */     GIR_RootConstrainSelectedInstOperands,
     /*  398217 */     // GIR_Coverage, 16184,
     /*  398217 */     GIR_EraseRootFromParent_Done,
     /*  398218 */   // Label 5929: @398218
     /*  398218 */   GIM_Try, /*On fail goto*//*Label 5930*/ GIMT_Encode4(398276), // Rule ID 16185 //
     /*  398223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  398226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398244 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  398247 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398274 */     GIR_RootConstrainSelectedInstOperands,
     /*  398275 */     // GIR_Coverage, 16185,
     /*  398275 */     GIR_EraseRootFromParent_Done,
     /*  398276 */   // Label 5930: @398276
     /*  398276 */   GIM_Try, /*On fail goto*//*Label 5931*/ GIMT_Encode4(398334), // Rule ID 16186 //
     /*  398281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  398284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398302 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  398305 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398328 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398332 */     GIR_RootConstrainSelectedInstOperands,
     /*  398333 */     // GIR_Coverage, 16186,
     /*  398333 */     GIR_EraseRootFromParent_Done,
     /*  398334 */   // Label 5931: @398334
     /*  398334 */   GIM_Try, /*On fail goto*//*Label 5932*/ GIMT_Encode4(398392), // Rule ID 16187 //
     /*  398339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  398342 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  398360 */     // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  398360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  398363 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  398365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  398370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  398375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398390 */     GIR_RootConstrainSelectedInstOperands,
     /*  398391 */     // GIR_Coverage, 16187,
     /*  398391 */     GIR_EraseRootFromParent_Done,
     /*  398392 */   // Label 5932: @398392
     /*  398392 */   GIM_Try, /*On fail goto*//*Label 5933*/ GIMT_Encode4(398505), // Rule ID 29478 //
     /*  398397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  398400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  398405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  398416 */     // (st p0:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  398416 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  398419 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  398423 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  398428 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  398434 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  398439 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  398444 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  398447 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  398451 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  398456 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  398462 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  398467 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  398472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  398475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  398480 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  398483 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  398486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  398491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  398496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398503 */     GIR_RootConstrainSelectedInstOperands,
     /*  398504 */     // GIR_Coverage, 29478,
     /*  398504 */     GIR_EraseRootFromParent_Done,
     /*  398505 */   // Label 5933: @398505
     /*  398505 */   GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(398562), // Rule ID 12393 //
     /*  398510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  398513 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  398531 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  398531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  398534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  398539 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  398546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  398556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398560 */     GIR_RootConstrainSelectedInstOperands,
     /*  398561 */     // GIR_Coverage, 12393,
     /*  398561 */     GIR_EraseRootFromParent_Done,
     /*  398562 */   // Label 5934: @398562
     /*  398562 */   GIM_Try, /*On fail goto*//*Label 5935*/ GIMT_Encode4(398619), // Rule ID 12394 //
     /*  398567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  398570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  398588 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  398588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  398591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  398596 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  398603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  398613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398617 */     GIR_RootConstrainSelectedInstOperands,
     /*  398618 */     // GIR_Coverage, 12394,
     /*  398618 */     GIR_EraseRootFromParent_Done,
     /*  398619 */   // Label 5935: @398619
     /*  398619 */   GIM_Try, /*On fail goto*//*Label 5936*/ GIMT_Encode4(398676), // Rule ID 12395 //
     /*  398624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  398627 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398638 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  398645 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  398645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  398648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  398653 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  398660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  398670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398674 */     GIR_RootConstrainSelectedInstOperands,
     /*  398675 */     // GIR_Coverage, 12395,
     /*  398675 */     GIR_EraseRootFromParent_Done,
     /*  398676 */   // Label 5936: @398676
     /*  398676 */   GIM_Try, /*On fail goto*//*Label 5937*/ GIMT_Encode4(398733), // Rule ID 12396 //
     /*  398681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  398684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  398702 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  398702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  398705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  398710 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  398717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  398727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398731 */     GIR_RootConstrainSelectedInstOperands,
     /*  398732 */     // GIR_Coverage, 12396,
     /*  398732 */     GIR_EraseRootFromParent_Done,
     /*  398733 */   // Label 5937: @398733
     /*  398733 */   GIM_Try, /*On fail goto*//*Label 5938*/ GIMT_Encode4(398790), // Rule ID 12397 //
     /*  398738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  398741 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  398759 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  398759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  398762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  398767 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  398774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  398779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  398784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398788 */     GIR_RootConstrainSelectedInstOperands,
     /*  398789 */     // GIR_Coverage, 12397,
     /*  398789 */     GIR_EraseRootFromParent_Done,
     /*  398790 */   // Label 5938: @398790
     /*  398790 */   GIM_Try, /*On fail goto*//*Label 5939*/ GIMT_Encode4(398840), // Rule ID 12388 //
     /*  398795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  398798 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  398816 */     // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  398816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  398819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  398824 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  398831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398838 */     GIR_RootConstrainSelectedInstOperands,
     /*  398839 */     // GIR_Coverage, 12388,
     /*  398839 */     GIR_EraseRootFromParent_Done,
     /*  398840 */   // Label 5939: @398840
     /*  398840 */   GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(398890), // Rule ID 12389 //
     /*  398845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  398848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  398866 */     // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  398866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  398869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  398874 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  398881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398888 */     GIR_RootConstrainSelectedInstOperands,
     /*  398889 */     // GIR_Coverage, 12389,
     /*  398889 */     GIR_EraseRootFromParent_Done,
     /*  398890 */   // Label 5940: @398890
     /*  398890 */   GIM_Try, /*On fail goto*//*Label 5941*/ GIMT_Encode4(398940), // Rule ID 12390 //
     /*  398895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  398898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  398916 */     // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  398916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  398919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  398924 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  398931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398938 */     GIR_RootConstrainSelectedInstOperands,
     /*  398939 */     // GIR_Coverage, 12390,
     /*  398939 */     GIR_EraseRootFromParent_Done,
     /*  398940 */   // Label 5941: @398940
     /*  398940 */   GIM_Try, /*On fail goto*//*Label 5942*/ GIMT_Encode4(398990), // Rule ID 12391 //
     /*  398945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  398948 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  398955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  398959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  398966 */     // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  398966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  398969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  398974 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  398976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  398981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  398984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  398988 */     GIR_RootConstrainSelectedInstOperands,
     /*  398989 */     // GIR_Coverage, 12391,
     /*  398989 */     GIR_EraseRootFromParent_Done,
     /*  398990 */   // Label 5942: @398990
     /*  398990 */   GIM_Try, /*On fail goto*//*Label 5943*/ GIMT_Encode4(399040), // Rule ID 12392 //
     /*  398995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  398998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  399005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  399016 */     // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  399016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  399019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  399024 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399038 */     GIR_RootConstrainSelectedInstOperands,
     /*  399039 */     // GIR_Coverage, 12392,
     /*  399039 */     GIR_EraseRootFromParent_Done,
     /*  399040 */   // Label 5943: @399040
     /*  399040 */   GIM_Try, /*On fail goto*//*Label 5944*/ GIMT_Encode4(399096), // Rule ID 10241 //
     /*  399045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  399048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  399065 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  399065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  399068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  399073 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  399080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  399085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  399090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399094 */     GIR_RootConstrainSelectedInstOperands,
     /*  399095 */     // GIR_Coverage, 10241,
     /*  399095 */     GIR_EraseRootFromParent_Done,
     /*  399096 */   // Label 5944: @399096
     /*  399096 */   GIM_Try, /*On fail goto*//*Label 5945*/ GIMT_Encode4(399152), // Rule ID 10242 //
     /*  399101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  399104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  399121 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  399121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  399124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  399129 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  399136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  399141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  399146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399150 */     GIR_RootConstrainSelectedInstOperands,
     /*  399151 */     // GIR_Coverage, 10242,
     /*  399151 */     GIR_EraseRootFromParent_Done,
     /*  399152 */   // Label 5945: @399152
     /*  399152 */   GIM_Try, /*On fail goto*//*Label 5946*/ GIMT_Encode4(399208), // Rule ID 10243 //
     /*  399157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  399160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  399177 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  399177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  399180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  399185 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  399192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  399197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  399202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399206 */     GIR_RootConstrainSelectedInstOperands,
     /*  399207 */     // GIR_Coverage, 10243,
     /*  399207 */     GIR_EraseRootFromParent_Done,
     /*  399208 */   // Label 5946: @399208
     /*  399208 */   GIM_Try, /*On fail goto*//*Label 5947*/ GIMT_Encode4(399264), // Rule ID 10244 //
     /*  399213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  399216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  399233 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  399233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  399236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  399241 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  399248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  399253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  399258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399262 */     GIR_RootConstrainSelectedInstOperands,
     /*  399263 */     // GIR_Coverage, 10244,
     /*  399263 */     GIR_EraseRootFromParent_Done,
     /*  399264 */   // Label 5947: @399264
     /*  399264 */   GIM_Try, /*On fail goto*//*Label 5948*/ GIMT_Encode4(399320), // Rule ID 10245 //
     /*  399269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  399272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  399289 */     // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  399289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  399292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  399297 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  399304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  399309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  399314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399318 */     GIR_RootConstrainSelectedInstOperands,
     /*  399319 */     // GIR_Coverage, 10245,
     /*  399319 */     GIR_EraseRootFromParent_Done,
     /*  399320 */   // Label 5948: @399320
     /*  399320 */   GIM_Try, /*On fail goto*//*Label 5949*/ GIMT_Encode4(399369), // Rule ID 10236 //
     /*  399325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  399328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  399345 */     // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  399345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  399348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  399353 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399367 */     GIR_RootConstrainSelectedInstOperands,
     /*  399368 */     // GIR_Coverage, 10236,
     /*  399368 */     GIR_EraseRootFromParent_Done,
     /*  399369 */   // Label 5949: @399369
     /*  399369 */   GIM_Try, /*On fail goto*//*Label 5950*/ GIMT_Encode4(399418), // Rule ID 10237 //
     /*  399374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  399377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399383 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  399394 */     // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  399394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  399397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  399402 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399416 */     GIR_RootConstrainSelectedInstOperands,
     /*  399417 */     // GIR_Coverage, 10237,
     /*  399417 */     GIR_EraseRootFromParent_Done,
     /*  399418 */   // Label 5950: @399418
     /*  399418 */   GIM_Try, /*On fail goto*//*Label 5951*/ GIMT_Encode4(399467), // Rule ID 10238 //
     /*  399423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  399426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399432 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  399443 */     // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  399443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  399446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  399451 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399465 */     GIR_RootConstrainSelectedInstOperands,
     /*  399466 */     // GIR_Coverage, 10238,
     /*  399466 */     GIR_EraseRootFromParent_Done,
     /*  399467 */   // Label 5951: @399467
     /*  399467 */   GIM_Try, /*On fail goto*//*Label 5952*/ GIMT_Encode4(399516), // Rule ID 10239 //
     /*  399472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  399475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399481 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  399492 */     // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  399492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  399495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  399500 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399514 */     GIR_RootConstrainSelectedInstOperands,
     /*  399515 */     // GIR_Coverage, 10239,
     /*  399515 */     GIR_EraseRootFromParent_Done,
     /*  399516 */   // Label 5952: @399516
     /*  399516 */   GIM_Try, /*On fail goto*//*Label 5953*/ GIMT_Encode4(399565), // Rule ID 10240 //
     /*  399521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  399524 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  399530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  399541 */     // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  399541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  399544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  399549 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  399551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399563 */     GIR_RootConstrainSelectedInstOperands,
     /*  399564 */     // GIR_Coverage, 10240,
     /*  399564 */     GIR_EraseRootFromParent_Done,
     /*  399565 */   // Label 5953: @399565
     /*  399565 */   GIM_Reject,
     /*  399566 */ // Label 5876: @399566
     /*  399566 */ GIM_Reject,
     /*  399567 */ // Label 5859: @399567
     /*  399567 */ GIM_Try, /*On fail goto*//*Label 5954*/ GIMT_Encode4(403961),
     /*  399572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  399575 */   GIM_Try, /*On fail goto*//*Label 5955*/ GIMT_Encode4(399636), // Rule ID 30093 //
     /*  399580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  399583 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399587 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399601 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  399605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399612 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399620 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399634 */     GIR_RootConstrainSelectedInstOperands,
     /*  399635 */     // GIR_Coverage, 30093,
     /*  399635 */     GIR_EraseRootFromParent_Done,
     /*  399636 */   // Label 5955: @399636
     /*  399636 */   GIM_Try, /*On fail goto*//*Label 5956*/ GIMT_Encode4(399697), // Rule ID 30094 //
     /*  399641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  399644 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399653 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399658 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399662 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  399666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399673 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399681 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399688 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399695 */     GIR_RootConstrainSelectedInstOperands,
     /*  399696 */     // GIR_Coverage, 30094,
     /*  399696 */     GIR_EraseRootFromParent_Done,
     /*  399697 */   // Label 5956: @399697
     /*  399697 */   GIM_Try, /*On fail goto*//*Label 5957*/ GIMT_Encode4(399758), // Rule ID 30095 //
     /*  399702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  399705 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399709 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399723 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  399727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399734 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399742 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399756 */     GIR_RootConstrainSelectedInstOperands,
     /*  399757 */     // GIR_Coverage, 30095,
     /*  399757 */     GIR_EraseRootFromParent_Done,
     /*  399758 */   // Label 5957: @399758
     /*  399758 */   GIM_Try, /*On fail goto*//*Label 5958*/ GIMT_Encode4(399819), // Rule ID 30096 //
     /*  399763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  399766 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399775 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399784 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  399788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399795 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399803 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399817 */     GIR_RootConstrainSelectedInstOperands,
     /*  399818 */     // GIR_Coverage, 30096,
     /*  399818 */     GIR_EraseRootFromParent_Done,
     /*  399819 */   // Label 5958: @399819
     /*  399819 */   GIM_Try, /*On fail goto*//*Label 5959*/ GIMT_Encode4(399880), // Rule ID 30097 //
     /*  399824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  399827 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399831 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399836 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399845 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  399849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399856 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399864 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399878 */     GIR_RootConstrainSelectedInstOperands,
     /*  399879 */     // GIR_Coverage, 30097,
     /*  399879 */     GIR_EraseRootFromParent_Done,
     /*  399880 */   // Label 5959: @399880
     /*  399880 */   GIM_Try, /*On fail goto*//*Label 5960*/ GIMT_Encode4(399936), // Rule ID 29753 //
     /*  399885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  399888 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399897 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  399901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399912 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399920 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399934 */     GIR_RootConstrainSelectedInstOperands,
     /*  399935 */     // GIR_Coverage, 29753,
     /*  399935 */     GIR_EraseRootFromParent_Done,
     /*  399936 */   // Label 5960: @399936
     /*  399936 */   GIM_Try, /*On fail goto*//*Label 5961*/ GIMT_Encode4(399992), // Rule ID 29754 //
     /*  399941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  399944 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  399948 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  399953 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  399957 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  399961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  399968 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  399968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  399971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  399976 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  399978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  399983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  399986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  399990 */     GIR_RootConstrainSelectedInstOperands,
     /*  399991 */     // GIR_Coverage, 29754,
     /*  399991 */     GIR_EraseRootFromParent_Done,
     /*  399992 */   // Label 5961: @399992
     /*  399992 */   GIM_Try, /*On fail goto*//*Label 5962*/ GIMT_Encode4(400048), // Rule ID 29755 //
     /*  399997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  400000 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  400004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400009 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400024 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  400027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400032 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400046 */     GIR_RootConstrainSelectedInstOperands,
     /*  400047 */     // GIR_Coverage, 29755,
     /*  400047 */     GIR_EraseRootFromParent_Done,
     /*  400048 */   // Label 5962: @400048
     /*  400048 */   GIM_Try, /*On fail goto*//*Label 5963*/ GIMT_Encode4(400104), // Rule ID 29756 //
     /*  400053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  400056 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  400060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400065 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400080 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  400083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400088 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400102 */     GIR_RootConstrainSelectedInstOperands,
     /*  400103 */     // GIR_Coverage, 29756,
     /*  400103 */     GIR_EraseRootFromParent_Done,
     /*  400104 */   // Label 5963: @400104
     /*  400104 */   GIM_Try, /*On fail goto*//*Label 5964*/ GIMT_Encode4(400160), // Rule ID 29757 //
     /*  400109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  400112 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  400116 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400121 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400136 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  400139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400144 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400158 */     GIR_RootConstrainSelectedInstOperands,
     /*  400159 */     // GIR_Coverage, 29757,
     /*  400159 */     GIR_EraseRootFromParent_Done,
     /*  400160 */   // Label 5964: @400160
     /*  400160 */   GIM_Try, /*On fail goto*//*Label 5965*/ GIMT_Encode4(400217), // Rule ID 30098 //
     /*  400165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  400168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400173 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400182 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  400186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400193 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400201 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400215 */     GIR_RootConstrainSelectedInstOperands,
     /*  400216 */     // GIR_Coverage, 30098,
     /*  400216 */     GIR_EraseRootFromParent_Done,
     /*  400217 */   // Label 5965: @400217
     /*  400217 */   GIM_Try, /*On fail goto*//*Label 5966*/ GIMT_Encode4(400274), // Rule ID 30099 //
     /*  400222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  400225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400230 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400235 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400239 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  400243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400250 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400258 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400272 */     GIR_RootConstrainSelectedInstOperands,
     /*  400273 */     // GIR_Coverage, 30099,
     /*  400273 */     GIR_EraseRootFromParent_Done,
     /*  400274 */   // Label 5966: @400274
     /*  400274 */   GIM_Try, /*On fail goto*//*Label 5967*/ GIMT_Encode4(400331), // Rule ID 30100 //
     /*  400279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  400282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400296 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  400300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400307 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400315 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400329 */     GIR_RootConstrainSelectedInstOperands,
     /*  400330 */     // GIR_Coverage, 30100,
     /*  400330 */     GIR_EraseRootFromParent_Done,
     /*  400331 */   // Label 5967: @400331
     /*  400331 */   GIM_Try, /*On fail goto*//*Label 5968*/ GIMT_Encode4(400388), // Rule ID 30101 //
     /*  400336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  400339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400353 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  400357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400364 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400372 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400386 */     GIR_RootConstrainSelectedInstOperands,
     /*  400387 */     // GIR_Coverage, 30101,
     /*  400387 */     GIR_EraseRootFromParent_Done,
     /*  400388 */   // Label 5968: @400388
     /*  400388 */   GIM_Try, /*On fail goto*//*Label 5969*/ GIMT_Encode4(400445), // Rule ID 30102 //
     /*  400393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  400396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400410 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  400414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400421 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400429 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400443 */     GIR_RootConstrainSelectedInstOperands,
     /*  400444 */     // GIR_Coverage, 30102,
     /*  400444 */     GIR_EraseRootFromParent_Done,
     /*  400445 */   // Label 5969: @400445
     /*  400445 */   GIM_Try, /*On fail goto*//*Label 5970*/ GIMT_Encode4(400497), // Rule ID 29758 //
     /*  400450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  400453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400458 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400466 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400473 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400481 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400495 */     GIR_RootConstrainSelectedInstOperands,
     /*  400496 */     // GIR_Coverage, 29758,
     /*  400496 */     GIR_EraseRootFromParent_Done,
     /*  400497 */   // Label 5970: @400497
     /*  400497 */   GIM_Try, /*On fail goto*//*Label 5971*/ GIMT_Encode4(400549), // Rule ID 29759 //
     /*  400502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  400505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400510 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400525 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400533 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400540 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400547 */     GIR_RootConstrainSelectedInstOperands,
     /*  400548 */     // GIR_Coverage, 29759,
     /*  400548 */     GIR_EraseRootFromParent_Done,
     /*  400549 */   // Label 5971: @400549
     /*  400549 */   GIM_Try, /*On fail goto*//*Label 5972*/ GIMT_Encode4(400601), // Rule ID 29760 //
     /*  400554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  400557 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400562 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400577 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400585 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400599 */     GIR_RootConstrainSelectedInstOperands,
     /*  400600 */     // GIR_Coverage, 29760,
     /*  400600 */     GIR_EraseRootFromParent_Done,
     /*  400601 */   // Label 5972: @400601
     /*  400601 */   GIM_Try, /*On fail goto*//*Label 5973*/ GIMT_Encode4(400653), // Rule ID 29761 //
     /*  400606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  400609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400614 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400629 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400637 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400651 */     GIR_RootConstrainSelectedInstOperands,
     /*  400652 */     // GIR_Coverage, 29761,
     /*  400652 */     GIR_EraseRootFromParent_Done,
     /*  400653 */   // Label 5973: @400653
     /*  400653 */   GIM_Try, /*On fail goto*//*Label 5974*/ GIMT_Encode4(400705), // Rule ID 29762 //
     /*  400658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  400661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  400666 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  400670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400674 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  400681 */     // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  400681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  400684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  400689 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  400691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  400696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  400699 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400703 */     GIR_RootConstrainSelectedInstOperands,
     /*  400704 */     // GIR_Coverage, 29762,
     /*  400704 */     GIR_EraseRootFromParent_Done,
     /*  400705 */   // Label 5974: @400705
     /*  400705 */   GIM_Try, /*On fail goto*//*Label 5975*/ GIMT_Encode4(400760), // Rule ID 14527 //
     /*  400710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  400713 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  400718 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400722 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  400729 */     // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  400729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  400732 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  400734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  400739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  400744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  400749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  400754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400758 */     GIR_RootConstrainSelectedInstOperands,
     /*  400759 */     // GIR_Coverage, 14527,
     /*  400759 */     GIR_EraseRootFromParent_Done,
     /*  400760 */   // Label 5975: @400760
     /*  400760 */   GIM_Try, /*On fail goto*//*Label 5976*/ GIMT_Encode4(400815), // Rule ID 14528 //
     /*  400765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  400768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  400773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  400784 */     // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  400784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  400787 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  400789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  400794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  400799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  400804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  400809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400813 */     GIR_RootConstrainSelectedInstOperands,
     /*  400814 */     // GIR_Coverage, 14528,
     /*  400814 */     GIR_EraseRootFromParent_Done,
     /*  400815 */   // Label 5976: @400815
     /*  400815 */   GIM_Try, /*On fail goto*//*Label 5977*/ GIMT_Encode4(400870), // Rule ID 14529 //
     /*  400820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  400823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  400828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  400839 */     // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  400839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  400842 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  400844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  400849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  400854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  400859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  400864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400868 */     GIR_RootConstrainSelectedInstOperands,
     /*  400869 */     // GIR_Coverage, 14529,
     /*  400869 */     GIR_EraseRootFromParent_Done,
     /*  400870 */   // Label 5977: @400870
     /*  400870 */   GIM_Try, /*On fail goto*//*Label 5978*/ GIMT_Encode4(400925), // Rule ID 14530 //
     /*  400875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  400878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  400883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  400894 */     // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  400894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  400897 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  400899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  400904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  400909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  400914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  400919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400923 */     GIR_RootConstrainSelectedInstOperands,
     /*  400924 */     // GIR_Coverage, 14530,
     /*  400924 */     GIR_EraseRootFromParent_Done,
     /*  400925 */   // Label 5978: @400925
     /*  400925 */   GIM_Try, /*On fail goto*//*Label 5979*/ GIMT_Encode4(400980), // Rule ID 14531 //
     /*  400930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  400933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  400938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  400949 */     // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  400949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  400952 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  400954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  400959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  400964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  400969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  400974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  400978 */     GIR_RootConstrainSelectedInstOperands,
     /*  400979 */     // GIR_Coverage, 14531,
     /*  400979 */     GIR_EraseRootFromParent_Done,
     /*  400980 */   // Label 5979: @400980
     /*  400980 */   GIM_Try, /*On fail goto*//*Label 5980*/ GIMT_Encode4(401028), // Rule ID 14522 //
     /*  400985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  400988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  400993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  400997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  401004 */     // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  401004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  401007 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  401014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401026 */     GIR_RootConstrainSelectedInstOperands,
     /*  401027 */     // GIR_Coverage, 14522,
     /*  401027 */     GIR_EraseRootFromParent_Done,
     /*  401028 */   // Label 5980: @401028
     /*  401028 */   GIM_Try, /*On fail goto*//*Label 5981*/ GIMT_Encode4(401076), // Rule ID 14523 //
     /*  401033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  401036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  401052 */     // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  401052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  401055 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  401062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401074 */     GIR_RootConstrainSelectedInstOperands,
     /*  401075 */     // GIR_Coverage, 14523,
     /*  401075 */     GIR_EraseRootFromParent_Done,
     /*  401076 */   // Label 5981: @401076
     /*  401076 */   GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(401124), // Rule ID 14524 //
     /*  401081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  401084 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401089 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401093 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  401100 */     // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  401100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  401103 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  401110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401122 */     GIR_RootConstrainSelectedInstOperands,
     /*  401123 */     // GIR_Coverage, 14524,
     /*  401123 */     GIR_EraseRootFromParent_Done,
     /*  401124 */   // Label 5982: @401124
     /*  401124 */   GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(401172), // Rule ID 14525 //
     /*  401129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  401132 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  401148 */     // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  401148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  401151 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  401158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401170 */     GIR_RootConstrainSelectedInstOperands,
     /*  401171 */     // GIR_Coverage, 14525,
     /*  401171 */     GIR_EraseRootFromParent_Done,
     /*  401172 */   // Label 5983: @401172
     /*  401172 */   GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(401220), // Rule ID 14526 //
     /*  401177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  401180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  401196 */     // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  401196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  401199 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  401206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401218 */     GIR_RootConstrainSelectedInstOperands,
     /*  401219 */     // GIR_Coverage, 14526,
     /*  401219 */     GIR_EraseRootFromParent_Done,
     /*  401220 */   // Label 5984: @401220
     /*  401220 */   GIM_Try, /*On fail goto*//*Label 5985*/ GIMT_Encode4(401268), // Rule ID 14517 //
     /*  401225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  401228 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  401244 */     // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  401244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  401247 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  401254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401266 */     GIR_RootConstrainSelectedInstOperands,
     /*  401267 */     // GIR_Coverage, 14517,
     /*  401267 */     GIR_EraseRootFromParent_Done,
     /*  401268 */   // Label 5985: @401268
     /*  401268 */   GIM_Try, /*On fail goto*//*Label 5986*/ GIMT_Encode4(401316), // Rule ID 14518 //
     /*  401273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  401276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401281 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401285 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  401292 */     // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  401292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  401295 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  401302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401310 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401314 */     GIR_RootConstrainSelectedInstOperands,
     /*  401315 */     // GIR_Coverage, 14518,
     /*  401315 */     GIR_EraseRootFromParent_Done,
     /*  401316 */   // Label 5986: @401316
     /*  401316 */   GIM_Try, /*On fail goto*//*Label 5987*/ GIMT_Encode4(401364), // Rule ID 14519 //
     /*  401321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  401324 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  401340 */     // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  401340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  401343 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  401350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401362 */     GIR_RootConstrainSelectedInstOperands,
     /*  401363 */     // GIR_Coverage, 14519,
     /*  401363 */     GIR_EraseRootFromParent_Done,
     /*  401364 */   // Label 5987: @401364
     /*  401364 */   GIM_Try, /*On fail goto*//*Label 5988*/ GIMT_Encode4(401412), // Rule ID 14520 //
     /*  401369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  401372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  401388 */     // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  401388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  401391 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  401398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401406 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401410 */     GIR_RootConstrainSelectedInstOperands,
     /*  401411 */     // GIR_Coverage, 14520,
     /*  401411 */     GIR_EraseRootFromParent_Done,
     /*  401412 */   // Label 5988: @401412
     /*  401412 */   GIM_Try, /*On fail goto*//*Label 5989*/ GIMT_Encode4(401460), // Rule ID 14521 //
     /*  401417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  401420 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  401425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  401436 */     // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  401436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  401439 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  401441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  401446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  401451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401458 */     GIR_RootConstrainSelectedInstOperands,
     /*  401459 */     // GIR_Coverage, 14521,
     /*  401459 */     GIR_EraseRootFromParent_Done,
     /*  401460 */   // Label 5989: @401460
     /*  401460 */   GIM_Try, /*On fail goto*//*Label 5990*/ GIMT_Encode4(401523), // Rule ID 16198 //
     /*  401465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  401468 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401486 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  401489 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401521 */     GIR_RootConstrainSelectedInstOperands,
     /*  401522 */     // GIR_Coverage, 16198,
     /*  401522 */     GIR_EraseRootFromParent_Done,
     /*  401523 */   // Label 5990: @401523
     /*  401523 */   GIM_Try, /*On fail goto*//*Label 5991*/ GIMT_Encode4(401586), // Rule ID 16199 //
     /*  401528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  401531 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401542 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401549 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  401552 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401580 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401584 */     GIR_RootConstrainSelectedInstOperands,
     /*  401585 */     // GIR_Coverage, 16199,
     /*  401585 */     GIR_EraseRootFromParent_Done,
     /*  401586 */   // Label 5991: @401586
     /*  401586 */   GIM_Try, /*On fail goto*//*Label 5992*/ GIMT_Encode4(401649), // Rule ID 16200 //
     /*  401591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  401594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401601 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401612 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  401615 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401647 */     GIR_RootConstrainSelectedInstOperands,
     /*  401648 */     // GIR_Coverage, 16200,
     /*  401648 */     GIR_EraseRootFromParent_Done,
     /*  401649 */   // Label 5992: @401649
     /*  401649 */   GIM_Try, /*On fail goto*//*Label 5993*/ GIMT_Encode4(401712), // Rule ID 16201 //
     /*  401654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  401657 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401675 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  401678 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401710 */     GIR_RootConstrainSelectedInstOperands,
     /*  401711 */     // GIR_Coverage, 16201,
     /*  401711 */     GIR_EraseRootFromParent_Done,
     /*  401712 */   // Label 5993: @401712
     /*  401712 */   GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(401775), // Rule ID 16202 //
     /*  401717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  401720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401738 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  401741 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401763 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401766 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401773 */     GIR_RootConstrainSelectedInstOperands,
     /*  401774 */     // GIR_Coverage, 16202,
     /*  401774 */     GIR_EraseRootFromParent_Done,
     /*  401775 */   // Label 5994: @401775
     /*  401775 */   GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(401838), // Rule ID 16208 //
     /*  401780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  401783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401801 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  401804 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401836 */     GIR_RootConstrainSelectedInstOperands,
     /*  401837 */     // GIR_Coverage, 16208,
     /*  401837 */     GIR_EraseRootFromParent_Done,
     /*  401838 */   // Label 5995: @401838
     /*  401838 */   GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(401901), // Rule ID 16209 //
     /*  401843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  401846 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401864 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  401867 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401899 */     GIR_RootConstrainSelectedInstOperands,
     /*  401900 */     // GIR_Coverage, 16209,
     /*  401900 */     GIR_EraseRootFromParent_Done,
     /*  401901 */   // Label 5996: @401901
     /*  401901 */   GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(401964), // Rule ID 16210 //
     /*  401906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  401909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401927 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  401930 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  401937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  401942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  401947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  401952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  401958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  401962 */     GIR_RootConstrainSelectedInstOperands,
     /*  401963 */     // GIR_Coverage, 16210,
     /*  401963 */     GIR_EraseRootFromParent_Done,
     /*  401964 */   // Label 5997: @401964
     /*  401964 */   GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(402027), // Rule ID 16211 //
     /*  401969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  401972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  401979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  401983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  401990 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  401990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  401993 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  401995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  402000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  402010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  402015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402025 */     GIR_RootConstrainSelectedInstOperands,
     /*  402026 */     // GIR_Coverage, 16211,
     /*  402026 */     GIR_EraseRootFromParent_Done,
     /*  402027 */   // Label 5998: @402027
     /*  402027 */   GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(402090), // Rule ID 16212 //
     /*  402032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  402035 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402042 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402046 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  402053 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  402056 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  402063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  402073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  402078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402088 */     GIR_RootConstrainSelectedInstOperands,
     /*  402089 */     // GIR_Coverage, 16212,
     /*  402089 */     GIR_EraseRootFromParent_Done,
     /*  402090 */   // Label 5999: @402090
     /*  402090 */   GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(402207), // Rule ID 29484 //
     /*  402095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  402098 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  402102 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  402107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  402118 */     // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  402118 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  402121 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  402125 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  402130 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  402136 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  402141 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  402146 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  402149 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  402153 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  402158 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  402164 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  402169 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  402174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  402177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  402182 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  402185 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  402188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  402193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  402198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402205 */     GIR_RootConstrainSelectedInstOperands,
     /*  402206 */     // GIR_Coverage, 29484,
     /*  402206 */     GIR_EraseRootFromParent_Done,
     /*  402207 */   // Label 6000: @402207
     /*  402207 */   GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(402265), // Rule ID 16193 //
     /*  402212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  402215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402233 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  402236 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402263 */     GIR_RootConstrainSelectedInstOperands,
     /*  402264 */     // GIR_Coverage, 16193,
     /*  402264 */     GIR_EraseRootFromParent_Done,
     /*  402265 */   // Label 6001: @402265
     /*  402265 */   GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(402323), // Rule ID 16194 //
     /*  402270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  402273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402291 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  402294 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402321 */     GIR_RootConstrainSelectedInstOperands,
     /*  402322 */     // GIR_Coverage, 16194,
     /*  402322 */     GIR_EraseRootFromParent_Done,
     /*  402323 */   // Label 6002: @402323
     /*  402323 */   GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(402381), // Rule ID 16195 //
     /*  402328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  402331 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402349 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  402352 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402375 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402379 */     GIR_RootConstrainSelectedInstOperands,
     /*  402380 */     // GIR_Coverage, 16195,
     /*  402380 */     GIR_EraseRootFromParent_Done,
     /*  402381 */   // Label 6003: @402381
     /*  402381 */   GIM_Try, /*On fail goto*//*Label 6004*/ GIMT_Encode4(402439), // Rule ID 16196 //
     /*  402386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  402389 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402407 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  402410 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402437 */     GIR_RootConstrainSelectedInstOperands,
     /*  402438 */     // GIR_Coverage, 16196,
     /*  402438 */     GIR_EraseRootFromParent_Done,
     /*  402439 */   // Label 6004: @402439
     /*  402439 */   GIM_Try, /*On fail goto*//*Label 6005*/ GIMT_Encode4(402497), // Rule ID 16197 //
     /*  402444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  402447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402465 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  402468 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402495 */     GIR_RootConstrainSelectedInstOperands,
     /*  402496 */     // GIR_Coverage, 16197,
     /*  402496 */     GIR_EraseRootFromParent_Done,
     /*  402497 */   // Label 6005: @402497
     /*  402497 */   GIM_Try, /*On fail goto*//*Label 6006*/ GIMT_Encode4(402555), // Rule ID 16203 //
     /*  402502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  402505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402512 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402516 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402523 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  402526 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402553 */     GIR_RootConstrainSelectedInstOperands,
     /*  402554 */     // GIR_Coverage, 16203,
     /*  402554 */     GIR_EraseRootFromParent_Done,
     /*  402555 */   // Label 6006: @402555
     /*  402555 */   GIM_Try, /*On fail goto*//*Label 6007*/ GIMT_Encode4(402613), // Rule ID 16204 //
     /*  402560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  402563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402581 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  402584 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402611 */     GIR_RootConstrainSelectedInstOperands,
     /*  402612 */     // GIR_Coverage, 16204,
     /*  402612 */     GIR_EraseRootFromParent_Done,
     /*  402613 */   // Label 6007: @402613
     /*  402613 */   GIM_Try, /*On fail goto*//*Label 6008*/ GIMT_Encode4(402671), // Rule ID 16205 //
     /*  402618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  402621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402639 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  402642 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402662 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402669 */     GIR_RootConstrainSelectedInstOperands,
     /*  402670 */     // GIR_Coverage, 16205,
     /*  402670 */     GIR_EraseRootFromParent_Done,
     /*  402671 */   // Label 6008: @402671
     /*  402671 */   GIM_Try, /*On fail goto*//*Label 6009*/ GIMT_Encode4(402729), // Rule ID 16206 //
     /*  402676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  402679 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402697 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  402700 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402727 */     GIR_RootConstrainSelectedInstOperands,
     /*  402728 */     // GIR_Coverage, 16206,
     /*  402728 */     GIR_EraseRootFromParent_Done,
     /*  402729 */   // Label 6009: @402729
     /*  402729 */   GIM_Try, /*On fail goto*//*Label 6010*/ GIMT_Encode4(402787), // Rule ID 16207 //
     /*  402734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  402737 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  402755 */     // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  402755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  402758 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  402760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  402765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  402770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402785 */     GIR_RootConstrainSelectedInstOperands,
     /*  402786 */     // GIR_Coverage, 16207,
     /*  402786 */     GIR_EraseRootFromParent_Done,
     /*  402787 */   // Label 6010: @402787
     /*  402787 */   GIM_Try, /*On fail goto*//*Label 6011*/ GIMT_Encode4(402900), // Rule ID 29490 //
     /*  402792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  402795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  402800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402804 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  402811 */     // (st p1:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  402811 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  402814 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  402818 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  402823 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  402829 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  402834 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  402839 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  402842 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  402846 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  402851 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  402857 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  402862 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  402867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  402870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  402875 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  402878 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  402881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  402886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  402891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  402894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402898 */     GIR_RootConstrainSelectedInstOperands,
     /*  402899 */     // GIR_Coverage, 29490,
     /*  402899 */     GIR_EraseRootFromParent_Done,
     /*  402900 */   // Label 6011: @402900
     /*  402900 */   GIM_Try, /*On fail goto*//*Label 6012*/ GIMT_Encode4(402957), // Rule ID 12413 //
     /*  402905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  402908 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  402926 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  402926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  402929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  402934 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  402936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  402941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  402946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  402951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  402955 */     GIR_RootConstrainSelectedInstOperands,
     /*  402956 */     // GIR_Coverage, 12413,
     /*  402956 */     GIR_EraseRootFromParent_Done,
     /*  402957 */   // Label 6012: @402957
     /*  402957 */   GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(403014), // Rule ID 12414 //
     /*  402962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  402965 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  402972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  402976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  402983 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  402983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  402986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  402991 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  402993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  402998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403012 */     GIR_RootConstrainSelectedInstOperands,
     /*  403013 */     // GIR_Coverage, 12414,
     /*  403013 */     GIR_EraseRootFromParent_Done,
     /*  403014 */   // Label 6013: @403014
     /*  403014 */   GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(403071), // Rule ID 12415 //
     /*  403019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  403022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403040 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  403043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403048 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403069 */     GIR_RootConstrainSelectedInstOperands,
     /*  403070 */     // GIR_Coverage, 12415,
     /*  403070 */     GIR_EraseRootFromParent_Done,
     /*  403071 */   // Label 6014: @403071
     /*  403071 */   GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(403128), // Rule ID 12416 //
     /*  403076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  403079 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403097 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  403100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403105 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403126 */     GIR_RootConstrainSelectedInstOperands,
     /*  403127 */     // GIR_Coverage, 12416,
     /*  403127 */     GIR_EraseRootFromParent_Done,
     /*  403128 */   // Label 6015: @403128
     /*  403128 */   GIM_Try, /*On fail goto*//*Label 6016*/ GIMT_Encode4(403185), // Rule ID 12417 //
     /*  403133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  403136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403154 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  403157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403162 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403183 */     GIR_RootConstrainSelectedInstOperands,
     /*  403184 */     // GIR_Coverage, 12417,
     /*  403184 */     GIR_EraseRootFromParent_Done,
     /*  403185 */   // Label 6016: @403185
     /*  403185 */   GIM_Try, /*On fail goto*//*Label 6017*/ GIMT_Encode4(403235), // Rule ID 12408 //
     /*  403190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  403193 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403200 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  403211 */     // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  403214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403219 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403233 */     GIR_RootConstrainSelectedInstOperands,
     /*  403234 */     // GIR_Coverage, 12408,
     /*  403234 */     GIR_EraseRootFromParent_Done,
     /*  403235 */   // Label 6017: @403235
     /*  403235 */   GIM_Try, /*On fail goto*//*Label 6018*/ GIMT_Encode4(403285), // Rule ID 12409 //
     /*  403240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  403243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  403261 */     // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  403264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403269 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403283 */     GIR_RootConstrainSelectedInstOperands,
     /*  403284 */     // GIR_Coverage, 12409,
     /*  403284 */     GIR_EraseRootFromParent_Done,
     /*  403285 */   // Label 6018: @403285
     /*  403285 */   GIM_Try, /*On fail goto*//*Label 6019*/ GIMT_Encode4(403335), // Rule ID 12410 //
     /*  403290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  403293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  403311 */     // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  403314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403319 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403333 */     GIR_RootConstrainSelectedInstOperands,
     /*  403334 */     // GIR_Coverage, 12410,
     /*  403334 */     GIR_EraseRootFromParent_Done,
     /*  403335 */   // Label 6019: @403335
     /*  403335 */   GIM_Try, /*On fail goto*//*Label 6020*/ GIMT_Encode4(403385), // Rule ID 12411 //
     /*  403340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  403343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  403361 */     // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  403364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403369 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403383 */     GIR_RootConstrainSelectedInstOperands,
     /*  403384 */     // GIR_Coverage, 12411,
     /*  403384 */     GIR_EraseRootFromParent_Done,
     /*  403385 */   // Label 6020: @403385
     /*  403385 */   GIM_Try, /*On fail goto*//*Label 6021*/ GIMT_Encode4(403435), // Rule ID 12412 //
     /*  403390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  403393 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  403400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  403411 */     // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  403414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403419 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403433 */     GIR_RootConstrainSelectedInstOperands,
     /*  403434 */     // GIR_Coverage, 12412,
     /*  403434 */     GIR_EraseRootFromParent_Done,
     /*  403435 */   // Label 6021: @403435
     /*  403435 */   GIM_Try, /*On fail goto*//*Label 6022*/ GIMT_Encode4(403491), // Rule ID 10261 //
     /*  403440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  403443 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403460 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  403463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403468 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403485 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403489 */     GIR_RootConstrainSelectedInstOperands,
     /*  403490 */     // GIR_Coverage, 10261,
     /*  403490 */     GIR_EraseRootFromParent_Done,
     /*  403491 */   // Label 6022: @403491
     /*  403491 */   GIM_Try, /*On fail goto*//*Label 6023*/ GIMT_Encode4(403547), // Rule ID 10262 //
     /*  403496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  403499 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403505 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403509 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403516 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  403519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403524 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403545 */     GIR_RootConstrainSelectedInstOperands,
     /*  403546 */     // GIR_Coverage, 10262,
     /*  403546 */     GIR_EraseRootFromParent_Done,
     /*  403547 */   // Label 6023: @403547
     /*  403547 */   GIM_Try, /*On fail goto*//*Label 6024*/ GIMT_Encode4(403603), // Rule ID 10263 //
     /*  403552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  403555 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403572 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  403575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403580 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403601 */     GIR_RootConstrainSelectedInstOperands,
     /*  403602 */     // GIR_Coverage, 10263,
     /*  403602 */     GIR_EraseRootFromParent_Done,
     /*  403603 */   // Label 6024: @403603
     /*  403603 */   GIM_Try, /*On fail goto*//*Label 6025*/ GIMT_Encode4(403659), // Rule ID 10264 //
     /*  403608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  403611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403628 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  403631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403636 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403653 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403657 */     GIR_RootConstrainSelectedInstOperands,
     /*  403658 */     // GIR_Coverage, 10264,
     /*  403658 */     GIR_EraseRootFromParent_Done,
     /*  403659 */   // Label 6025: @403659
     /*  403659 */   GIM_Try, /*On fail goto*//*Label 6026*/ GIMT_Encode4(403715), // Rule ID 10265 //
     /*  403664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  403667 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  403684 */     // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  403684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  403687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  403692 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  403699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  403704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  403709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403713 */     GIR_RootConstrainSelectedInstOperands,
     /*  403714 */     // GIR_Coverage, 10265,
     /*  403714 */     GIR_EraseRootFromParent_Done,
     /*  403715 */   // Label 6026: @403715
     /*  403715 */   GIM_Try, /*On fail goto*//*Label 6027*/ GIMT_Encode4(403764), // Rule ID 10256 //
     /*  403720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  403723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  403740 */     // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  403743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403748 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403762 */     GIR_RootConstrainSelectedInstOperands,
     /*  403763 */     // GIR_Coverage, 10256,
     /*  403763 */     GIR_EraseRootFromParent_Done,
     /*  403764 */   // Label 6027: @403764
     /*  403764 */   GIM_Try, /*On fail goto*//*Label 6028*/ GIMT_Encode4(403813), // Rule ID 10257 //
     /*  403769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  403772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403782 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  403789 */     // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  403792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403797 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403811 */     GIR_RootConstrainSelectedInstOperands,
     /*  403812 */     // GIR_Coverage, 10257,
     /*  403812 */     GIR_EraseRootFromParent_Done,
     /*  403813 */   // Label 6028: @403813
     /*  403813 */   GIM_Try, /*On fail goto*//*Label 6029*/ GIMT_Encode4(403862), // Rule ID 10258 //
     /*  403818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  403821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  403838 */     // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  403841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403846 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403860 */     GIR_RootConstrainSelectedInstOperands,
     /*  403861 */     // GIR_Coverage, 10258,
     /*  403861 */     GIR_EraseRootFromParent_Done,
     /*  403862 */   // Label 6029: @403862
     /*  403862 */   GIM_Try, /*On fail goto*//*Label 6030*/ GIMT_Encode4(403911), // Rule ID 10259 //
     /*  403867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  403870 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  403887 */     // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  403890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403895 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403909 */     GIR_RootConstrainSelectedInstOperands,
     /*  403910 */     // GIR_Coverage, 10259,
     /*  403910 */     GIR_EraseRootFromParent_Done,
     /*  403911 */   // Label 6030: @403911
     /*  403911 */   GIM_Try, /*On fail goto*//*Label 6031*/ GIMT_Encode4(403960), // Rule ID 10260 //
     /*  403916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  403919 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  403925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  403936 */     // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  403936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  403939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  403944 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  403946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  403951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  403954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  403958 */     GIR_RootConstrainSelectedInstOperands,
     /*  403959 */     // GIR_Coverage, 10260,
     /*  403959 */     GIR_EraseRootFromParent_Done,
     /*  403960 */   // Label 6031: @403960
     /*  403960 */   GIM_Reject,
     /*  403961 */ // Label 5954: @403961
     /*  403961 */ GIM_Reject,
     /*  403962 */ // Label 5860: @403962
     /*  403962 */ GIM_Try, /*On fail goto*//*Label 6032*/ GIMT_Encode4(408666),
     /*  403967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  403970 */   GIM_Try, /*On fail goto*//*Label 6033*/ GIMT_Encode4(404026), // Rule ID 25866 //
     /*  403975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  403978 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  403983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  403987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  403994 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  403994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  403997 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  403999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404024 */     GIR_RootConstrainSelectedInstOperands,
     /*  404025 */     // GIR_Coverage, 25866,
     /*  404025 */     GIR_EraseRootFromParent_Done,
     /*  404026 */   // Label 6033: @404026
     /*  404026 */   GIM_Try, /*On fail goto*//*Label 6034*/ GIMT_Encode4(404082), // Rule ID 25867 //
     /*  404031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  404034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404050 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  404053 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404080 */     GIR_RootConstrainSelectedInstOperands,
     /*  404081 */     // GIR_Coverage, 25867,
     /*  404081 */     GIR_EraseRootFromParent_Done,
     /*  404082 */   // Label 6034: @404082
     /*  404082 */   GIM_Try, /*On fail goto*//*Label 6035*/ GIMT_Encode4(404138), // Rule ID 25868 //
     /*  404087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  404090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404106 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  404109 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404136 */     GIR_RootConstrainSelectedInstOperands,
     /*  404137 */     // GIR_Coverage, 25868,
     /*  404137 */     GIR_EraseRootFromParent_Done,
     /*  404138 */   // Label 6035: @404138
     /*  404138 */   GIM_Try, /*On fail goto*//*Label 6036*/ GIMT_Encode4(404194), // Rule ID 25869 //
     /*  404143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  404146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404162 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  404165 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404192 */     GIR_RootConstrainSelectedInstOperands,
     /*  404193 */     // GIR_Coverage, 25869,
     /*  404193 */     GIR_EraseRootFromParent_Done,
     /*  404194 */   // Label 6036: @404194
     /*  404194 */   GIM_Try, /*On fail goto*//*Label 6037*/ GIMT_Encode4(404250), // Rule ID 25870 //
     /*  404199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  404202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404218 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  404221 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404248 */     GIR_RootConstrainSelectedInstOperands,
     /*  404249 */     // GIR_Coverage, 25870,
     /*  404249 */     GIR_EraseRootFromParent_Done,
     /*  404250 */   // Label 6037: @404250
     /*  404250 */   GIM_Try, /*On fail goto*//*Label 6038*/ GIMT_Encode4(404306), // Rule ID 25876 //
     /*  404255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  404258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404274 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  404277 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404304 */     GIR_RootConstrainSelectedInstOperands,
     /*  404305 */     // GIR_Coverage, 25876,
     /*  404305 */     GIR_EraseRootFromParent_Done,
     /*  404306 */   // Label 6038: @404306
     /*  404306 */   GIM_Try, /*On fail goto*//*Label 6039*/ GIMT_Encode4(404362), // Rule ID 25877 //
     /*  404311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  404314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404330 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  404333 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404360 */     GIR_RootConstrainSelectedInstOperands,
     /*  404361 */     // GIR_Coverage, 25877,
     /*  404361 */     GIR_EraseRootFromParent_Done,
     /*  404362 */   // Label 6039: @404362
     /*  404362 */   GIM_Try, /*On fail goto*//*Label 6040*/ GIMT_Encode4(404418), // Rule ID 25878 //
     /*  404367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  404370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404386 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  404389 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404416 */     GIR_RootConstrainSelectedInstOperands,
     /*  404417 */     // GIR_Coverage, 25878,
     /*  404417 */     GIR_EraseRootFromParent_Done,
     /*  404418 */   // Label 6040: @404418
     /*  404418 */   GIM_Try, /*On fail goto*//*Label 6041*/ GIMT_Encode4(404474), // Rule ID 25879 //
     /*  404423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  404426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404442 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  404445 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404472 */     GIR_RootConstrainSelectedInstOperands,
     /*  404473 */     // GIR_Coverage, 25879,
     /*  404473 */     GIR_EraseRootFromParent_Done,
     /*  404474 */   // Label 6041: @404474
     /*  404474 */   GIM_Try, /*On fail goto*//*Label 6042*/ GIMT_Encode4(404530), // Rule ID 25880 //
     /*  404479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  404482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  404498 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  404498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  404501 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  404503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  404508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  404513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404528 */     GIR_RootConstrainSelectedInstOperands,
     /*  404529 */     // GIR_Coverage, 25880,
     /*  404529 */     GIR_EraseRootFromParent_Done,
     /*  404530 */   // Label 6042: @404530
     /*  404530 */   GIM_Try, /*On fail goto*//*Label 6043*/ GIMT_Encode4(404585), // Rule ID 14197 //
     /*  404535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  404538 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  404554 */     // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  404554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  404557 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  404564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  404569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  404579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404583 */     GIR_RootConstrainSelectedInstOperands,
     /*  404584 */     // GIR_Coverage, 14197,
     /*  404584 */     GIR_EraseRootFromParent_Done,
     /*  404585 */   // Label 6043: @404585
     /*  404585 */   GIM_Try, /*On fail goto*//*Label 6044*/ GIMT_Encode4(404640), // Rule ID 14198 //
     /*  404590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  404593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  404609 */     // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  404609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  404612 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  404619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  404624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  404634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404638 */     GIR_RootConstrainSelectedInstOperands,
     /*  404639 */     // GIR_Coverage, 14198,
     /*  404639 */     GIR_EraseRootFromParent_Done,
     /*  404640 */   // Label 6044: @404640
     /*  404640 */   GIM_Try, /*On fail goto*//*Label 6045*/ GIMT_Encode4(404695), // Rule ID 14199 //
     /*  404645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  404648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  404664 */     // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  404664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  404667 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  404674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  404679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  404689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404693 */     GIR_RootConstrainSelectedInstOperands,
     /*  404694 */     // GIR_Coverage, 14199,
     /*  404694 */     GIR_EraseRootFromParent_Done,
     /*  404695 */   // Label 6045: @404695
     /*  404695 */   GIM_Try, /*On fail goto*//*Label 6046*/ GIMT_Encode4(404750), // Rule ID 14200 //
     /*  404700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  404703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404708 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  404719 */     // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  404719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  404722 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  404729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  404734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  404744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404748 */     GIR_RootConstrainSelectedInstOperands,
     /*  404749 */     // GIR_Coverage, 14200,
     /*  404749 */     GIR_EraseRootFromParent_Done,
     /*  404750 */   // Label 6046: @404750
     /*  404750 */   GIM_Try, /*On fail goto*//*Label 6047*/ GIMT_Encode4(404805), // Rule ID 14201 //
     /*  404755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  404758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  404774 */     // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  404774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  404777 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  404784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  404789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  404794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  404799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404803 */     GIR_RootConstrainSelectedInstOperands,
     /*  404804 */     // GIR_Coverage, 14201,
     /*  404804 */     GIR_EraseRootFromParent_Done,
     /*  404805 */   // Label 6047: @404805
     /*  404805 */   GIM_Try, /*On fail goto*//*Label 6048*/ GIMT_Encode4(404853), // Rule ID 14192 //
     /*  404810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  404813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  404829 */     // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  404829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  404832 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  404839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  404844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404851 */     GIR_RootConstrainSelectedInstOperands,
     /*  404852 */     // GIR_Coverage, 14192,
     /*  404852 */     GIR_EraseRootFromParent_Done,
     /*  404853 */   // Label 6048: @404853
     /*  404853 */   GIM_Try, /*On fail goto*//*Label 6049*/ GIMT_Encode4(404901), // Rule ID 14193 //
     /*  404858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  404861 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  404877 */     // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  404877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  404880 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  404887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  404892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404899 */     GIR_RootConstrainSelectedInstOperands,
     /*  404900 */     // GIR_Coverage, 14193,
     /*  404900 */     GIR_EraseRootFromParent_Done,
     /*  404901 */   // Label 6049: @404901
     /*  404901 */   GIM_Try, /*On fail goto*//*Label 6050*/ GIMT_Encode4(404949), // Rule ID 14194 //
     /*  404906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  404909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404918 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  404925 */     // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  404925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  404928 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  404935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  404940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404947 */     GIR_RootConstrainSelectedInstOperands,
     /*  404948 */     // GIR_Coverage, 14194,
     /*  404948 */     GIR_EraseRootFromParent_Done,
     /*  404949 */   // Label 6050: @404949
     /*  404949 */   GIM_Try, /*On fail goto*//*Label 6051*/ GIMT_Encode4(404997), // Rule ID 14195 //
     /*  404954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  404957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  404962 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  404966 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  404973 */     // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  404973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  404976 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  404978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  404983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  404988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  404991 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  404995 */     GIR_RootConstrainSelectedInstOperands,
     /*  404996 */     // GIR_Coverage, 14195,
     /*  404996 */     GIR_EraseRootFromParent_Done,
     /*  404997 */   // Label 6051: @404997
     /*  404997 */   GIM_Try, /*On fail goto*//*Label 6052*/ GIMT_Encode4(405045), // Rule ID 14196 //
     /*  405002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  405005 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405010 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405014 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  405021 */     // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  405021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  405024 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  405026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  405031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  405036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405043 */     GIR_RootConstrainSelectedInstOperands,
     /*  405044 */     // GIR_Coverage, 14196,
     /*  405044 */     GIR_EraseRootFromParent_Done,
     /*  405045 */   // Label 6052: @405045
     /*  405045 */   GIM_Try, /*On fail goto*//*Label 6053*/ GIMT_Encode4(405093), // Rule ID 14187 //
     /*  405050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  405053 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405058 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405062 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  405069 */     // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  405069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  405072 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  405074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  405079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  405084 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405087 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405091 */     GIR_RootConstrainSelectedInstOperands,
     /*  405092 */     // GIR_Coverage, 14187,
     /*  405092 */     GIR_EraseRootFromParent_Done,
     /*  405093 */   // Label 6053: @405093
     /*  405093 */   GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(405141), // Rule ID 14188 //
     /*  405098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  405101 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  405117 */     // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  405117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  405120 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  405122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  405127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  405132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405139 */     GIR_RootConstrainSelectedInstOperands,
     /*  405140 */     // GIR_Coverage, 14188,
     /*  405140 */     GIR_EraseRootFromParent_Done,
     /*  405141 */   // Label 6054: @405141
     /*  405141 */   GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(405189), // Rule ID 14189 //
     /*  405146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  405149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  405165 */     // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  405165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  405168 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  405170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  405175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  405180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405187 */     GIR_RootConstrainSelectedInstOperands,
     /*  405188 */     // GIR_Coverage, 14189,
     /*  405188 */     GIR_EraseRootFromParent_Done,
     /*  405189 */   // Label 6055: @405189
     /*  405189 */   GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(405237), // Rule ID 14190 //
     /*  405194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  405197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405206 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  405213 */     // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  405213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  405216 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  405218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  405223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  405228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405231 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405235 */     GIR_RootConstrainSelectedInstOperands,
     /*  405236 */     // GIR_Coverage, 14190,
     /*  405236 */     GIR_EraseRootFromParent_Done,
     /*  405237 */   // Label 6056: @405237
     /*  405237 */   GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(405285), // Rule ID 14191 //
     /*  405242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  405245 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  405261 */     // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  405261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  405264 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  405266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  405271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  405276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405283 */     GIR_RootConstrainSelectedInstOperands,
     /*  405284 */     // GIR_Coverage, 14191,
     /*  405284 */     GIR_EraseRootFromParent_Done,
     /*  405285 */   // Label 6057: @405285
     /*  405285 */   GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(405348), // Rule ID 15978 //
     /*  405290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  405293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405311 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  405314 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405342 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405346 */     GIR_RootConstrainSelectedInstOperands,
     /*  405347 */     // GIR_Coverage, 15978,
     /*  405347 */     GIR_EraseRootFromParent_Done,
     /*  405348 */   // Label 6058: @405348
     /*  405348 */   GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(405411), // Rule ID 15979 //
     /*  405353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  405356 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405374 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  405377 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405409 */     GIR_RootConstrainSelectedInstOperands,
     /*  405410 */     // GIR_Coverage, 15979,
     /*  405410 */     GIR_EraseRootFromParent_Done,
     /*  405411 */   // Label 6059: @405411
     /*  405411 */   GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(405474), // Rule ID 15980 //
     /*  405416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  405419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405437 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  405440 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405472 */     GIR_RootConstrainSelectedInstOperands,
     /*  405473 */     // GIR_Coverage, 15980,
     /*  405473 */     GIR_EraseRootFromParent_Done,
     /*  405474 */   // Label 6060: @405474
     /*  405474 */   GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(405537), // Rule ID 15981 //
     /*  405479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  405482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405500 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  405503 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405528 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405531 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405535 */     GIR_RootConstrainSelectedInstOperands,
     /*  405536 */     // GIR_Coverage, 15981,
     /*  405536 */     GIR_EraseRootFromParent_Done,
     /*  405537 */   // Label 6061: @405537
     /*  405537 */   GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(405600), // Rule ID 15982 //
     /*  405542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  405545 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405563 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  405566 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405598 */     GIR_RootConstrainSelectedInstOperands,
     /*  405599 */     // GIR_Coverage, 15982,
     /*  405599 */     GIR_EraseRootFromParent_Done,
     /*  405600 */   // Label 6062: @405600
     /*  405600 */   GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(405663), // Rule ID 15988 //
     /*  405605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  405608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405626 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  405629 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405661 */     GIR_RootConstrainSelectedInstOperands,
     /*  405662 */     // GIR_Coverage, 15988,
     /*  405662 */     GIR_EraseRootFromParent_Done,
     /*  405663 */   // Label 6063: @405663
     /*  405663 */   GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(405726), // Rule ID 15989 //
     /*  405668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  405671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405682 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405689 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  405692 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405724 */     GIR_RootConstrainSelectedInstOperands,
     /*  405725 */     // GIR_Coverage, 15989,
     /*  405725 */     GIR_EraseRootFromParent_Done,
     /*  405726 */   // Label 6064: @405726
     /*  405726 */   GIM_Try, /*On fail goto*//*Label 6065*/ GIMT_Encode4(405789), // Rule ID 15990 //
     /*  405731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  405734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405752 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  405755 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405787 */     GIR_RootConstrainSelectedInstOperands,
     /*  405788 */     // GIR_Coverage, 15990,
     /*  405788 */     GIR_EraseRootFromParent_Done,
     /*  405789 */   // Label 6065: @405789
     /*  405789 */   GIM_Try, /*On fail goto*//*Label 6066*/ GIMT_Encode4(405852), // Rule ID 15991 //
     /*  405794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  405797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405815 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  405818 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405850 */     GIR_RootConstrainSelectedInstOperands,
     /*  405851 */     // GIR_Coverage, 15991,
     /*  405851 */     GIR_EraseRootFromParent_Done,
     /*  405852 */   // Label 6066: @405852
     /*  405852 */   GIM_Try, /*On fail goto*//*Label 6067*/ GIMT_Encode4(405915), // Rule ID 15992 //
     /*  405857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  405860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  405867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  405878 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  405878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  405881 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  405883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405913 */     GIR_RootConstrainSelectedInstOperands,
     /*  405914 */     // GIR_Coverage, 15992,
     /*  405914 */     GIR_EraseRootFromParent_Done,
     /*  405915 */   // Label 6067: @405915
     /*  405915 */   GIM_Try, /*On fail goto*//*Label 6068*/ GIMT_Encode4(405976), // Rule ID 25861 //
     /*  405920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  405923 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405928 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405932 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  405939 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  405939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  405942 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  405944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  405949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  405954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  405959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  405964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  405970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  405974 */     GIR_RootConstrainSelectedInstOperands,
     /*  405975 */     // GIR_Coverage, 25861,
     /*  405975 */     GIR_EraseRootFromParent_Done,
     /*  405976 */   // Label 6068: @405976
     /*  405976 */   GIM_Try, /*On fail goto*//*Label 6069*/ GIMT_Encode4(406037), // Rule ID 25862 //
     /*  405981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  405984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  405989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  405993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406000 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  406003 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406031 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406035 */     GIR_RootConstrainSelectedInstOperands,
     /*  406036 */     // GIR_Coverage, 25862,
     /*  406036 */     GIR_EraseRootFromParent_Done,
     /*  406037 */   // Label 6069: @406037
     /*  406037 */   GIM_Try, /*On fail goto*//*Label 6070*/ GIMT_Encode4(406098), // Rule ID 25863 //
     /*  406042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  406045 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406061 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  406064 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406086 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406096 */     GIR_RootConstrainSelectedInstOperands,
     /*  406097 */     // GIR_Coverage, 25863,
     /*  406097 */     GIR_EraseRootFromParent_Done,
     /*  406098 */   // Label 6070: @406098
     /*  406098 */   GIM_Try, /*On fail goto*//*Label 6071*/ GIMT_Encode4(406159), // Rule ID 25864 //
     /*  406103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  406106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406122 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  406125 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406150 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406153 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406157 */     GIR_RootConstrainSelectedInstOperands,
     /*  406158 */     // GIR_Coverage, 25864,
     /*  406158 */     GIR_EraseRootFromParent_Done,
     /*  406159 */   // Label 6071: @406159
     /*  406159 */   GIM_Try, /*On fail goto*//*Label 6072*/ GIMT_Encode4(406220), // Rule ID 25865 //
     /*  406164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  406167 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406183 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  406186 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406218 */     GIR_RootConstrainSelectedInstOperands,
     /*  406219 */     // GIR_Coverage, 25865,
     /*  406219 */     GIR_EraseRootFromParent_Done,
     /*  406220 */   // Label 6072: @406220
     /*  406220 */   GIM_Try, /*On fail goto*//*Label 6073*/ GIMT_Encode4(406281), // Rule ID 25871 //
     /*  406225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  406228 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406244 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  406247 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406279 */     GIR_RootConstrainSelectedInstOperands,
     /*  406280 */     // GIR_Coverage, 25871,
     /*  406280 */     GIR_EraseRootFromParent_Done,
     /*  406281 */   // Label 6073: @406281
     /*  406281 */   GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(406342), // Rule ID 25872 //
     /*  406286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  406289 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406305 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  406308 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406340 */     GIR_RootConstrainSelectedInstOperands,
     /*  406341 */     // GIR_Coverage, 25872,
     /*  406341 */     GIR_EraseRootFromParent_Done,
     /*  406342 */   // Label 6074: @406342
     /*  406342 */   GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(406403), // Rule ID 25873 //
     /*  406347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  406350 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406366 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  406369 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406401 */     GIR_RootConstrainSelectedInstOperands,
     /*  406402 */     // GIR_Coverage, 25873,
     /*  406402 */     GIR_EraseRootFromParent_Done,
     /*  406403 */   // Label 6075: @406403
     /*  406403 */   GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(406464), // Rule ID 25874 //
     /*  406408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  406411 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406427 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  406430 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406462 */     GIR_RootConstrainSelectedInstOperands,
     /*  406463 */     // GIR_Coverage, 25874,
     /*  406463 */     GIR_EraseRootFromParent_Done,
     /*  406464 */   // Label 6076: @406464
     /*  406464 */   GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(406525), // Rule ID 25875 //
     /*  406469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  406472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  406477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  406488 */     // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  406488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  406491 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  406493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  406498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  406508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  406513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406523 */     GIR_RootConstrainSelectedInstOperands,
     /*  406524 */     // GIR_Coverage, 25875,
     /*  406524 */     GIR_EraseRootFromParent_Done,
     /*  406525 */   // Label 6077: @406525
     /*  406525 */   GIM_Try, /*On fail goto*//*Label 6078*/ GIMT_Encode4(406583), // Rule ID 15973 //
     /*  406530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  406533 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406551 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  406554 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406581 */     GIR_RootConstrainSelectedInstOperands,
     /*  406582 */     // GIR_Coverage, 15973,
     /*  406582 */     GIR_EraseRootFromParent_Done,
     /*  406583 */   // Label 6078: @406583
     /*  406583 */   GIM_Try, /*On fail goto*//*Label 6079*/ GIMT_Encode4(406641), // Rule ID 15974 //
     /*  406588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  406591 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406609 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  406612 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406639 */     GIR_RootConstrainSelectedInstOperands,
     /*  406640 */     // GIR_Coverage, 15974,
     /*  406640 */     GIR_EraseRootFromParent_Done,
     /*  406641 */   // Label 6079: @406641
     /*  406641 */   GIM_Try, /*On fail goto*//*Label 6080*/ GIMT_Encode4(406699), // Rule ID 15975 //
     /*  406646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  406649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406667 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  406670 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406697 */     GIR_RootConstrainSelectedInstOperands,
     /*  406698 */     // GIR_Coverage, 15975,
     /*  406698 */     GIR_EraseRootFromParent_Done,
     /*  406699 */   // Label 6080: @406699
     /*  406699 */   GIM_Try, /*On fail goto*//*Label 6081*/ GIMT_Encode4(406757), // Rule ID 15976 //
     /*  406704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  406707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406714 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406718 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406725 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  406728 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406751 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406755 */     GIR_RootConstrainSelectedInstOperands,
     /*  406756 */     // GIR_Coverage, 15976,
     /*  406756 */     GIR_EraseRootFromParent_Done,
     /*  406757 */   // Label 6081: @406757
     /*  406757 */   GIM_Try, /*On fail goto*//*Label 6082*/ GIMT_Encode4(406815), // Rule ID 15977 //
     /*  406762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  406765 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406772 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406783 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  406786 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406813 */     GIR_RootConstrainSelectedInstOperands,
     /*  406814 */     // GIR_Coverage, 15977,
     /*  406814 */     GIR_EraseRootFromParent_Done,
     /*  406815 */   // Label 6082: @406815
     /*  406815 */   GIM_Try, /*On fail goto*//*Label 6083*/ GIMT_Encode4(406873), // Rule ID 15983 //
     /*  406820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  406823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406830 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406841 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  406844 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406867 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406871 */     GIR_RootConstrainSelectedInstOperands,
     /*  406872 */     // GIR_Coverage, 15983,
     /*  406872 */     GIR_EraseRootFromParent_Done,
     /*  406873 */   // Label 6083: @406873
     /*  406873 */   GIM_Try, /*On fail goto*//*Label 6084*/ GIMT_Encode4(406931), // Rule ID 15984 //
     /*  406878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  406881 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406888 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406899 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  406902 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406929 */     GIR_RootConstrainSelectedInstOperands,
     /*  406930 */     // GIR_Coverage, 15984,
     /*  406930 */     GIR_EraseRootFromParent_Done,
     /*  406931 */   // Label 6084: @406931
     /*  406931 */   GIM_Try, /*On fail goto*//*Label 6085*/ GIMT_Encode4(406989), // Rule ID 15985 //
     /*  406936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  406939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  406946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  406950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  406957 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  406957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  406960 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  406962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  406967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  406972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  406977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  406983 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  406987 */     GIR_RootConstrainSelectedInstOperands,
     /*  406988 */     // GIR_Coverage, 15985,
     /*  406988 */     GIR_EraseRootFromParent_Done,
     /*  406989 */   // Label 6085: @406989
     /*  406989 */   GIM_Try, /*On fail goto*//*Label 6086*/ GIMT_Encode4(407047), // Rule ID 15986 //
     /*  406994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  406997 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407004 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407008 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  407015 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  407015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  407018 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  407020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  407025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  407030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407045 */     GIR_RootConstrainSelectedInstOperands,
     /*  407046 */     // GIR_Coverage, 15986,
     /*  407046 */     GIR_EraseRootFromParent_Done,
     /*  407047 */   // Label 6086: @407047
     /*  407047 */   GIM_Try, /*On fail goto*//*Label 6087*/ GIMT_Encode4(407105), // Rule ID 15987 //
     /*  407052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  407055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  407073 */     // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  407073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  407076 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  407078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  407083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  407088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407103 */     GIR_RootConstrainSelectedInstOperands,
     /*  407104 */     // GIR_Coverage, 15987,
     /*  407104 */     GIR_EraseRootFromParent_Done,
     /*  407105 */   // Label 6087: @407105
     /*  407105 */   GIM_Try, /*On fail goto*//*Label 6088*/ GIMT_Encode4(407157), // Rule ID 29263 //
     /*  407110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  407113 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  407117 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407133 */     // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  407136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407141 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407155 */     GIR_RootConstrainSelectedInstOperands,
     /*  407156 */     // GIR_Coverage, 29263,
     /*  407156 */     GIR_EraseRootFromParent_Done,
     /*  407157 */   // Label 6088: @407157
     /*  407157 */   GIM_Try, /*On fail goto*//*Label 6089*/ GIMT_Encode4(407209), // Rule ID 29264 //
     /*  407162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  407165 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  407169 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407185 */     // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  407188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407193 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407203 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407207 */     GIR_RootConstrainSelectedInstOperands,
     /*  407208 */     // GIR_Coverage, 29264,
     /*  407208 */     GIR_EraseRootFromParent_Done,
     /*  407209 */   // Label 6089: @407209
     /*  407209 */   GIM_Try, /*On fail goto*//*Label 6090*/ GIMT_Encode4(407261), // Rule ID 29265 //
     /*  407214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  407217 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  407221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407237 */     // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  407240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407245 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407259 */     GIR_RootConstrainSelectedInstOperands,
     /*  407260 */     // GIR_Coverage, 29265,
     /*  407260 */     GIR_EraseRootFromParent_Done,
     /*  407261 */   // Label 6090: @407261
     /*  407261 */   GIM_Try, /*On fail goto*//*Label 6091*/ GIMT_Encode4(407313), // Rule ID 29266 //
     /*  407266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  407269 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  407273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407289 */     // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  407292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407297 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407311 */     GIR_RootConstrainSelectedInstOperands,
     /*  407312 */     // GIR_Coverage, 29266,
     /*  407312 */     GIR_EraseRootFromParent_Done,
     /*  407313 */   // Label 6091: @407313
     /*  407313 */   GIM_Try, /*On fail goto*//*Label 6092*/ GIMT_Encode4(407365), // Rule ID 29267 //
     /*  407318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  407321 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  407325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407341 */     // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  407344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407349 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407363 */     GIR_RootConstrainSelectedInstOperands,
     /*  407364 */     // GIR_Coverage, 29267,
     /*  407364 */     GIR_EraseRootFromParent_Done,
     /*  407365 */   // Label 6092: @407365
     /*  407365 */   GIM_Try, /*On fail goto*//*Label 6093*/ GIMT_Encode4(407413), // Rule ID 29268 //
     /*  407370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  407373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407389 */     // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  407392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407397 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407407 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407411 */     GIR_RootConstrainSelectedInstOperands,
     /*  407412 */     // GIR_Coverage, 29268,
     /*  407412 */     GIR_EraseRootFromParent_Done,
     /*  407413 */   // Label 6093: @407413
     /*  407413 */   GIM_Try, /*On fail goto*//*Label 6094*/ GIMT_Encode4(407461), // Rule ID 29269 //
     /*  407418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  407421 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407437 */     // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  407440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407445 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407455 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407459 */     GIR_RootConstrainSelectedInstOperands,
     /*  407460 */     // GIR_Coverage, 29269,
     /*  407460 */     GIR_EraseRootFromParent_Done,
     /*  407461 */   // Label 6094: @407461
     /*  407461 */   GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(407509), // Rule ID 29270 //
     /*  407466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  407469 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407485 */     // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  407488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407493 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407507 */     GIR_RootConstrainSelectedInstOperands,
     /*  407508 */     // GIR_Coverage, 29270,
     /*  407508 */     GIR_EraseRootFromParent_Done,
     /*  407509 */   // Label 6095: @407509
     /*  407509 */   GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(407557), // Rule ID 29271 //
     /*  407514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  407517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407533 */     // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  407536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407541 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407555 */     GIR_RootConstrainSelectedInstOperands,
     /*  407556 */     // GIR_Coverage, 29271,
     /*  407556 */     GIR_EraseRootFromParent_Done,
     /*  407557 */   // Label 6096: @407557
     /*  407557 */   GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(407605), // Rule ID 29272 //
     /*  407562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  407565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  407570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  407581 */     // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  407581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  407584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  407589 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  407591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407599 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407603 */     GIR_RootConstrainSelectedInstOperands,
     /*  407604 */     // GIR_Coverage, 29272,
     /*  407604 */     GIR_EraseRootFromParent_Done,
     /*  407605 */   // Label 6097: @407605
     /*  407605 */   GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(407662), // Rule ID 12193 //
     /*  407610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  407613 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  407631 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  407631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  407634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  407639 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  407646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  407656 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407660 */     GIR_RootConstrainSelectedInstOperands,
     /*  407661 */     // GIR_Coverage, 12193,
     /*  407661 */     GIR_EraseRootFromParent_Done,
     /*  407662 */   // Label 6098: @407662
     /*  407662 */   GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(407719), // Rule ID 12194 //
     /*  407667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  407670 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  407688 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  407688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  407691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  407696 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  407703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  407713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407717 */     GIR_RootConstrainSelectedInstOperands,
     /*  407718 */     // GIR_Coverage, 12194,
     /*  407718 */     GIR_EraseRootFromParent_Done,
     /*  407719 */   // Label 6099: @407719
     /*  407719 */   GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(407776), // Rule ID 12195 //
     /*  407724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  407727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  407745 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  407745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  407748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  407753 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  407760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  407770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407774 */     GIR_RootConstrainSelectedInstOperands,
     /*  407775 */     // GIR_Coverage, 12195,
     /*  407775 */     GIR_EraseRootFromParent_Done,
     /*  407776 */   // Label 6100: @407776
     /*  407776 */   GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(407833), // Rule ID 12196 //
     /*  407781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  407784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  407802 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  407802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  407805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  407810 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  407817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  407827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407831 */     GIR_RootConstrainSelectedInstOperands,
     /*  407832 */     // GIR_Coverage, 12196,
     /*  407832 */     GIR_EraseRootFromParent_Done,
     /*  407833 */   // Label 6101: @407833
     /*  407833 */   GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(407890), // Rule ID 12197 //
     /*  407838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  407841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  407859 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  407859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  407862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  407867 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  407874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  407879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  407884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407888 */     GIR_RootConstrainSelectedInstOperands,
     /*  407889 */     // GIR_Coverage, 12197,
     /*  407889 */     GIR_EraseRootFromParent_Done,
     /*  407890 */   // Label 6102: @407890
     /*  407890 */   GIM_Try, /*On fail goto*//*Label 6103*/ GIMT_Encode4(407940), // Rule ID 12188 //
     /*  407895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  407898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  407916 */     // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  407916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  407919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  407924 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407938 */     GIR_RootConstrainSelectedInstOperands,
     /*  407939 */     // GIR_Coverage, 12188,
     /*  407939 */     GIR_EraseRootFromParent_Done,
     /*  407940 */   // Label 6103: @407940
     /*  407940 */   GIM_Try, /*On fail goto*//*Label 6104*/ GIMT_Encode4(407990), // Rule ID 12189 //
     /*  407945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  407948 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  407955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  407959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  407966 */     // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  407966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  407969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  407974 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  407976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  407981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  407984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  407988 */     GIR_RootConstrainSelectedInstOperands,
     /*  407989 */     // GIR_Coverage, 12189,
     /*  407989 */     GIR_EraseRootFromParent_Done,
     /*  407990 */   // Label 6104: @407990
     /*  407990 */   GIM_Try, /*On fail goto*//*Label 6105*/ GIMT_Encode4(408040), // Rule ID 12190 //
     /*  407995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  407998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  408005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  408016 */     // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  408019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408024 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408038 */     GIR_RootConstrainSelectedInstOperands,
     /*  408039 */     // GIR_Coverage, 12190,
     /*  408039 */     GIR_EraseRootFromParent_Done,
     /*  408040 */   // Label 6105: @408040
     /*  408040 */   GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(408090), // Rule ID 12191 //
     /*  408045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  408048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  408055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  408066 */     // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  408069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408074 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408088 */     GIR_RootConstrainSelectedInstOperands,
     /*  408089 */     // GIR_Coverage, 12191,
     /*  408089 */     GIR_EraseRootFromParent_Done,
     /*  408090 */   // Label 6106: @408090
     /*  408090 */   GIM_Try, /*On fail goto*//*Label 6107*/ GIMT_Encode4(408140), // Rule ID 12192 //
     /*  408095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  408098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  408105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  408116 */     // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  408119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408124 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408138 */     GIR_RootConstrainSelectedInstOperands,
     /*  408139 */     // GIR_Coverage, 12192,
     /*  408139 */     GIR_EraseRootFromParent_Done,
     /*  408140 */   // Label 6107: @408140
     /*  408140 */   GIM_Try, /*On fail goto*//*Label 6108*/ GIMT_Encode4(408196), // Rule ID 10051 //
     /*  408145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  408148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  408165 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  408165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  408168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  408173 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  408180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  408190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408194 */     GIR_RootConstrainSelectedInstOperands,
     /*  408195 */     // GIR_Coverage, 10051,
     /*  408195 */     GIR_EraseRootFromParent_Done,
     /*  408196 */   // Label 6108: @408196
     /*  408196 */   GIM_Try, /*On fail goto*//*Label 6109*/ GIMT_Encode4(408252), // Rule ID 10052 //
     /*  408201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  408204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  408221 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  408221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  408224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  408229 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  408236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  408246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408250 */     GIR_RootConstrainSelectedInstOperands,
     /*  408251 */     // GIR_Coverage, 10052,
     /*  408251 */     GIR_EraseRootFromParent_Done,
     /*  408252 */   // Label 6109: @408252
     /*  408252 */   GIM_Try, /*On fail goto*//*Label 6110*/ GIMT_Encode4(408308), // Rule ID 10053 //
     /*  408257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  408260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408266 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  408277 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  408277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  408280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  408285 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  408292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  408302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408306 */     GIR_RootConstrainSelectedInstOperands,
     /*  408307 */     // GIR_Coverage, 10053,
     /*  408307 */     GIR_EraseRootFromParent_Done,
     /*  408308 */   // Label 6110: @408308
     /*  408308 */   GIM_Try, /*On fail goto*//*Label 6111*/ GIMT_Encode4(408364), // Rule ID 10054 //
     /*  408313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  408316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  408333 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  408333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  408336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  408341 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  408348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  408358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408362 */     GIR_RootConstrainSelectedInstOperands,
     /*  408363 */     // GIR_Coverage, 10054,
     /*  408363 */     GIR_EraseRootFromParent_Done,
     /*  408364 */   // Label 6111: @408364
     /*  408364 */   GIM_Try, /*On fail goto*//*Label 6112*/ GIMT_Encode4(408420), // Rule ID 10055 //
     /*  408369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  408372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  408389 */     // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  408389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  408392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  408397 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  408404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  408414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408418 */     GIR_RootConstrainSelectedInstOperands,
     /*  408419 */     // GIR_Coverage, 10055,
     /*  408419 */     GIR_EraseRootFromParent_Done,
     /*  408420 */   // Label 6112: @408420
     /*  408420 */   GIM_Try, /*On fail goto*//*Label 6113*/ GIMT_Encode4(408469), // Rule ID 10046 //
     /*  408425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  408428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  408445 */     // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  408448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408453 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408467 */     GIR_RootConstrainSelectedInstOperands,
     /*  408468 */     // GIR_Coverage, 10046,
     /*  408468 */     GIR_EraseRootFromParent_Done,
     /*  408469 */   // Label 6113: @408469
     /*  408469 */   GIM_Try, /*On fail goto*//*Label 6114*/ GIMT_Encode4(408518), // Rule ID 10047 //
     /*  408474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  408477 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  408494 */     // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  408497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408502 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408512 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408516 */     GIR_RootConstrainSelectedInstOperands,
     /*  408517 */     // GIR_Coverage, 10047,
     /*  408517 */     GIR_EraseRootFromParent_Done,
     /*  408518 */   // Label 6114: @408518
     /*  408518 */   GIM_Try, /*On fail goto*//*Label 6115*/ GIMT_Encode4(408567), // Rule ID 10048 //
     /*  408523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  408526 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  408543 */     // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  408546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408551 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408561 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408565 */     GIR_RootConstrainSelectedInstOperands,
     /*  408566 */     // GIR_Coverage, 10048,
     /*  408566 */     GIR_EraseRootFromParent_Done,
     /*  408567 */   // Label 6115: @408567
     /*  408567 */   GIM_Try, /*On fail goto*//*Label 6116*/ GIMT_Encode4(408616), // Rule ID 10049 //
     /*  408572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  408575 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  408592 */     // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  408595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408600 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408614 */     GIR_RootConstrainSelectedInstOperands,
     /*  408615 */     // GIR_Coverage, 10049,
     /*  408615 */     GIR_EraseRootFromParent_Done,
     /*  408616 */   // Label 6116: @408616
     /*  408616 */   GIM_Try, /*On fail goto*//*Label 6117*/ GIMT_Encode4(408665), // Rule ID 10050 //
     /*  408621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  408624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  408630 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  408641 */     // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  408641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  408644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  408649 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  408651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  408656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408663 */     GIR_RootConstrainSelectedInstOperands,
     /*  408664 */     // GIR_Coverage, 10050,
     /*  408664 */     GIR_EraseRootFromParent_Done,
     /*  408665 */   // Label 6117: @408665
     /*  408665 */   GIM_Reject,
     /*  408666 */ // Label 6032: @408666
     /*  408666 */ GIM_Reject,
     /*  408667 */ // Label 5861: @408667
     /*  408667 */ GIM_Try, /*On fail goto*//*Label 6118*/ GIMT_Encode4(413371),
     /*  408672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  408675 */   GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(408731), // Rule ID 25886 //
     /*  408680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  408683 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  408688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408692 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  408699 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  408699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  408702 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  408704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  408709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  408714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408729 */     GIR_RootConstrainSelectedInstOperands,
     /*  408730 */     // GIR_Coverage, 25886,
     /*  408730 */     GIR_EraseRootFromParent_Done,
     /*  408731 */   // Label 6119: @408731
     /*  408731 */   GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(408787), // Rule ID 25887 //
     /*  408736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  408739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  408744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  408755 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  408755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  408758 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  408760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  408765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  408770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408785 */     GIR_RootConstrainSelectedInstOperands,
     /*  408786 */     // GIR_Coverage, 25887,
     /*  408786 */     GIR_EraseRootFromParent_Done,
     /*  408787 */   // Label 6120: @408787
     /*  408787 */   GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(408843), // Rule ID 25888 //
     /*  408792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  408795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  408800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408804 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  408811 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  408811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  408814 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  408816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  408821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  408826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408837 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408841 */     GIR_RootConstrainSelectedInstOperands,
     /*  408842 */     // GIR_Coverage, 25888,
     /*  408842 */     GIR_EraseRootFromParent_Done,
     /*  408843 */   // Label 6121: @408843
     /*  408843 */   GIM_Try, /*On fail goto*//*Label 6122*/ GIMT_Encode4(408899), // Rule ID 25889 //
     /*  408848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  408851 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  408856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  408867 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  408867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  408870 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  408872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  408877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  408882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408897 */     GIR_RootConstrainSelectedInstOperands,
     /*  408898 */     // GIR_Coverage, 25889,
     /*  408898 */     GIR_EraseRootFromParent_Done,
     /*  408899 */   // Label 6122: @408899
     /*  408899 */   GIM_Try, /*On fail goto*//*Label 6123*/ GIMT_Encode4(408955), // Rule ID 25890 //
     /*  408904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  408907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  408912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  408923 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  408923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  408926 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  408928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  408933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  408938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  408949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  408953 */     GIR_RootConstrainSelectedInstOperands,
     /*  408954 */     // GIR_Coverage, 25890,
     /*  408954 */     GIR_EraseRootFromParent_Done,
     /*  408955 */   // Label 6123: @408955
     /*  408955 */   GIM_Try, /*On fail goto*//*Label 6124*/ GIMT_Encode4(409011), // Rule ID 25896 //
     /*  408960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  408963 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  408968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  408972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  408979 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  408979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  408982 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  408984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  408989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  408994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  408999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409009 */     GIR_RootConstrainSelectedInstOperands,
     /*  409010 */     // GIR_Coverage, 25896,
     /*  409010 */     GIR_EraseRootFromParent_Done,
     /*  409011 */   // Label 6124: @409011
     /*  409011 */   GIM_Try, /*On fail goto*//*Label 6125*/ GIMT_Encode4(409067), // Rule ID 25897 //
     /*  409016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  409019 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  409035 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  409035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  409038 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  409040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  409045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  409050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409065 */     GIR_RootConstrainSelectedInstOperands,
     /*  409066 */     // GIR_Coverage, 25897,
     /*  409066 */     GIR_EraseRootFromParent_Done,
     /*  409067 */   // Label 6125: @409067
     /*  409067 */   GIM_Try, /*On fail goto*//*Label 6126*/ GIMT_Encode4(409123), // Rule ID 25898 //
     /*  409072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  409075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  409091 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  409091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  409094 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  409096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  409101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  409106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409121 */     GIR_RootConstrainSelectedInstOperands,
     /*  409122 */     // GIR_Coverage, 25898,
     /*  409122 */     GIR_EraseRootFromParent_Done,
     /*  409123 */   // Label 6126: @409123
     /*  409123 */   GIM_Try, /*On fail goto*//*Label 6127*/ GIMT_Encode4(409179), // Rule ID 25899 //
     /*  409128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  409131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  409147 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  409147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  409150 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  409152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  409157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  409162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409177 */     GIR_RootConstrainSelectedInstOperands,
     /*  409178 */     // GIR_Coverage, 25899,
     /*  409178 */     GIR_EraseRootFromParent_Done,
     /*  409179 */   // Label 6127: @409179
     /*  409179 */   GIM_Try, /*On fail goto*//*Label 6128*/ GIMT_Encode4(409235), // Rule ID 25900 //
     /*  409184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  409187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  409203 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  409203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  409206 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  409208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  409213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  409218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409233 */     GIR_RootConstrainSelectedInstOperands,
     /*  409234 */     // GIR_Coverage, 25900,
     /*  409234 */     GIR_EraseRootFromParent_Done,
     /*  409235 */   // Label 6128: @409235
     /*  409235 */   GIM_Try, /*On fail goto*//*Label 6129*/ GIMT_Encode4(409290), // Rule ID 14227 //
     /*  409240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  409243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  409259 */     // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  409259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  409262 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  409274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  409284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409288 */     GIR_RootConstrainSelectedInstOperands,
     /*  409289 */     // GIR_Coverage, 14227,
     /*  409289 */     GIR_EraseRootFromParent_Done,
     /*  409290 */   // Label 6129: @409290
     /*  409290 */   GIM_Try, /*On fail goto*//*Label 6130*/ GIMT_Encode4(409345), // Rule ID 14228 //
     /*  409295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  409298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  409314 */     // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  409314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  409317 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  409329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  409339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409343 */     GIR_RootConstrainSelectedInstOperands,
     /*  409344 */     // GIR_Coverage, 14228,
     /*  409344 */     GIR_EraseRootFromParent_Done,
     /*  409345 */   // Label 6130: @409345
     /*  409345 */   GIM_Try, /*On fail goto*//*Label 6131*/ GIMT_Encode4(409400), // Rule ID 14229 //
     /*  409350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  409353 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  409369 */     // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  409369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  409372 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  409384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  409394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409398 */     GIR_RootConstrainSelectedInstOperands,
     /*  409399 */     // GIR_Coverage, 14229,
     /*  409399 */     GIR_EraseRootFromParent_Done,
     /*  409400 */   // Label 6131: @409400
     /*  409400 */   GIM_Try, /*On fail goto*//*Label 6132*/ GIMT_Encode4(409455), // Rule ID 14230 //
     /*  409405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  409408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409413 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409417 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  409424 */     // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  409424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  409427 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  409439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  409449 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409453 */     GIR_RootConstrainSelectedInstOperands,
     /*  409454 */     // GIR_Coverage, 14230,
     /*  409454 */     GIR_EraseRootFromParent_Done,
     /*  409455 */   // Label 6132: @409455
     /*  409455 */   GIM_Try, /*On fail goto*//*Label 6133*/ GIMT_Encode4(409510), // Rule ID 14231 //
     /*  409460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  409463 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  409479 */     // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  409479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  409482 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  409494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  409499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  409504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409508 */     GIR_RootConstrainSelectedInstOperands,
     /*  409509 */     // GIR_Coverage, 14231,
     /*  409509 */     GIR_EraseRootFromParent_Done,
     /*  409510 */   // Label 6133: @409510
     /*  409510 */   GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(409558), // Rule ID 14222 //
     /*  409515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  409518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  409534 */     // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  409534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  409537 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  409544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409552 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409556 */     GIR_RootConstrainSelectedInstOperands,
     /*  409557 */     // GIR_Coverage, 14222,
     /*  409557 */     GIR_EraseRootFromParent_Done,
     /*  409558 */   // Label 6134: @409558
     /*  409558 */   GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(409606), // Rule ID 14223 //
     /*  409563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  409566 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  409582 */     // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  409582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  409585 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  409592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409604 */     GIR_RootConstrainSelectedInstOperands,
     /*  409605 */     // GIR_Coverage, 14223,
     /*  409605 */     GIR_EraseRootFromParent_Done,
     /*  409606 */   // Label 6135: @409606
     /*  409606 */   GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(409654), // Rule ID 14224 //
     /*  409611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  409614 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  409630 */     // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  409630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  409633 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  409640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409652 */     GIR_RootConstrainSelectedInstOperands,
     /*  409653 */     // GIR_Coverage, 14224,
     /*  409653 */     GIR_EraseRootFromParent_Done,
     /*  409654 */   // Label 6136: @409654
     /*  409654 */   GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(409702), // Rule ID 14225 //
     /*  409659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  409662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  409678 */     // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  409678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  409681 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  409688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409700 */     GIR_RootConstrainSelectedInstOperands,
     /*  409701 */     // GIR_Coverage, 14225,
     /*  409701 */     GIR_EraseRootFromParent_Done,
     /*  409702 */   // Label 6137: @409702
     /*  409702 */   GIM_Try, /*On fail goto*//*Label 6138*/ GIMT_Encode4(409750), // Rule ID 14226 //
     /*  409707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  409710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  409726 */     // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  409726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  409729 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  409736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409748 */     GIR_RootConstrainSelectedInstOperands,
     /*  409749 */     // GIR_Coverage, 14226,
     /*  409749 */     GIR_EraseRootFromParent_Done,
     /*  409750 */   // Label 6138: @409750
     /*  409750 */   GIM_Try, /*On fail goto*//*Label 6139*/ GIMT_Encode4(409798), // Rule ID 14217 //
     /*  409755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  409758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  409774 */     // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  409774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  409777 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409796 */     GIR_RootConstrainSelectedInstOperands,
     /*  409797 */     // GIR_Coverage, 14217,
     /*  409797 */     GIR_EraseRootFromParent_Done,
     /*  409798 */   // Label 6139: @409798
     /*  409798 */   GIM_Try, /*On fail goto*//*Label 6140*/ GIMT_Encode4(409846), // Rule ID 14218 //
     /*  409803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  409806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  409822 */     // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  409822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  409825 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409844 */     GIR_RootConstrainSelectedInstOperands,
     /*  409845 */     // GIR_Coverage, 14218,
     /*  409845 */     GIR_EraseRootFromParent_Done,
     /*  409846 */   // Label 6140: @409846
     /*  409846 */   GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(409894), // Rule ID 14219 //
     /*  409851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  409854 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  409870 */     // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  409870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  409873 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409892 */     GIR_RootConstrainSelectedInstOperands,
     /*  409893 */     // GIR_Coverage, 14219,
     /*  409893 */     GIR_EraseRootFromParent_Done,
     /*  409894 */   // Label 6141: @409894
     /*  409894 */   GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(409942), // Rule ID 14220 //
     /*  409899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  409902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  409918 */     // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  409918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  409921 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409940 */     GIR_RootConstrainSelectedInstOperands,
     /*  409941 */     // GIR_Coverage, 14220,
     /*  409941 */     GIR_EraseRootFromParent_Done,
     /*  409942 */   // Label 6142: @409942
     /*  409942 */   GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(409990), // Rule ID 14221 //
     /*  409947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  409950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  409955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  409959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  409966 */     // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  409966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  409969 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  409971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  409976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  409981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  409984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  409988 */     GIR_RootConstrainSelectedInstOperands,
     /*  409989 */     // GIR_Coverage, 14221,
     /*  409989 */     GIR_EraseRootFromParent_Done,
     /*  409990 */   // Label 6143: @409990
     /*  409990 */   GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(410053), // Rule ID 15998 //
     /*  409995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  409998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410016 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  410019 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410051 */     GIR_RootConstrainSelectedInstOperands,
     /*  410052 */     // GIR_Coverage, 15998,
     /*  410052 */     GIR_EraseRootFromParent_Done,
     /*  410053 */   // Label 6144: @410053
     /*  410053 */   GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(410116), // Rule ID 15999 //
     /*  410058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  410061 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410079 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  410082 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410114 */     GIR_RootConstrainSelectedInstOperands,
     /*  410115 */     // GIR_Coverage, 15999,
     /*  410115 */     GIR_EraseRootFromParent_Done,
     /*  410116 */   // Label 6145: @410116
     /*  410116 */   GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(410179), // Rule ID 16000 //
     /*  410121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  410124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410142 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  410145 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410177 */     GIR_RootConstrainSelectedInstOperands,
     /*  410178 */     // GIR_Coverage, 16000,
     /*  410178 */     GIR_EraseRootFromParent_Done,
     /*  410179 */   // Label 6146: @410179
     /*  410179 */   GIM_Try, /*On fail goto*//*Label 6147*/ GIMT_Encode4(410242), // Rule ID 16001 //
     /*  410184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  410187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410194 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410205 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  410208 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410240 */     GIR_RootConstrainSelectedInstOperands,
     /*  410241 */     // GIR_Coverage, 16001,
     /*  410241 */     GIR_EraseRootFromParent_Done,
     /*  410242 */   // Label 6147: @410242
     /*  410242 */   GIM_Try, /*On fail goto*//*Label 6148*/ GIMT_Encode4(410305), // Rule ID 16002 //
     /*  410247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  410250 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410268 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  410271 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410303 */     GIR_RootConstrainSelectedInstOperands,
     /*  410304 */     // GIR_Coverage, 16002,
     /*  410304 */     GIR_EraseRootFromParent_Done,
     /*  410305 */   // Label 6148: @410305
     /*  410305 */   GIM_Try, /*On fail goto*//*Label 6149*/ GIMT_Encode4(410368), // Rule ID 16008 //
     /*  410310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  410313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410320 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410324 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410331 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  410334 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410362 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410366 */     GIR_RootConstrainSelectedInstOperands,
     /*  410367 */     // GIR_Coverage, 16008,
     /*  410367 */     GIR_EraseRootFromParent_Done,
     /*  410368 */   // Label 6149: @410368
     /*  410368 */   GIM_Try, /*On fail goto*//*Label 6150*/ GIMT_Encode4(410431), // Rule ID 16009 //
     /*  410373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  410376 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410383 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410394 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  410397 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410429 */     GIR_RootConstrainSelectedInstOperands,
     /*  410430 */     // GIR_Coverage, 16009,
     /*  410430 */     GIR_EraseRootFromParent_Done,
     /*  410431 */   // Label 6150: @410431
     /*  410431 */   GIM_Try, /*On fail goto*//*Label 6151*/ GIMT_Encode4(410494), // Rule ID 16010 //
     /*  410436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  410439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410446 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410450 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410457 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  410460 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410482 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410492 */     GIR_RootConstrainSelectedInstOperands,
     /*  410493 */     // GIR_Coverage, 16010,
     /*  410493 */     GIR_EraseRootFromParent_Done,
     /*  410494 */   // Label 6151: @410494
     /*  410494 */   GIM_Try, /*On fail goto*//*Label 6152*/ GIMT_Encode4(410557), // Rule ID 16011 //
     /*  410499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  410502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410520 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  410523 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410555 */     GIR_RootConstrainSelectedInstOperands,
     /*  410556 */     // GIR_Coverage, 16011,
     /*  410556 */     GIR_EraseRootFromParent_Done,
     /*  410557 */   // Label 6152: @410557
     /*  410557 */   GIM_Try, /*On fail goto*//*Label 6153*/ GIMT_Encode4(410620), // Rule ID 16012 //
     /*  410562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  410565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  410572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  410583 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  410583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  410586 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  410588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410618 */     GIR_RootConstrainSelectedInstOperands,
     /*  410619 */     // GIR_Coverage, 16012,
     /*  410619 */     GIR_EraseRootFromParent_Done,
     /*  410620 */   // Label 6153: @410620
     /*  410620 */   GIM_Try, /*On fail goto*//*Label 6154*/ GIMT_Encode4(410681), // Rule ID 25881 //
     /*  410625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  410628 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410633 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410637 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  410644 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  410644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  410647 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  410649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410679 */     GIR_RootConstrainSelectedInstOperands,
     /*  410680 */     // GIR_Coverage, 25881,
     /*  410680 */     GIR_EraseRootFromParent_Done,
     /*  410681 */   // Label 6154: @410681
     /*  410681 */   GIM_Try, /*On fail goto*//*Label 6155*/ GIMT_Encode4(410742), // Rule ID 25882 //
     /*  410686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  410689 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  410705 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  410705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  410708 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  410710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410740 */     GIR_RootConstrainSelectedInstOperands,
     /*  410741 */     // GIR_Coverage, 25882,
     /*  410741 */     GIR_EraseRootFromParent_Done,
     /*  410742 */   // Label 6155: @410742
     /*  410742 */   GIM_Try, /*On fail goto*//*Label 6156*/ GIMT_Encode4(410803), // Rule ID 25883 //
     /*  410747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  410750 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410755 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  410766 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  410766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  410769 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  410771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410797 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410801 */     GIR_RootConstrainSelectedInstOperands,
     /*  410802 */     // GIR_Coverage, 25883,
     /*  410802 */     GIR_EraseRootFromParent_Done,
     /*  410803 */   // Label 6156: @410803
     /*  410803 */   GIM_Try, /*On fail goto*//*Label 6157*/ GIMT_Encode4(410864), // Rule ID 25884 //
     /*  410808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  410811 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410816 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410820 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  410827 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  410827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  410830 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  410832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410852 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410862 */     GIR_RootConstrainSelectedInstOperands,
     /*  410863 */     // GIR_Coverage, 25884,
     /*  410863 */     GIR_EraseRootFromParent_Done,
     /*  410864 */   // Label 6157: @410864
     /*  410864 */   GIM_Try, /*On fail goto*//*Label 6158*/ GIMT_Encode4(410925), // Rule ID 25885 //
     /*  410869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  410872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  410888 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  410888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  410891 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  410893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410923 */     GIR_RootConstrainSelectedInstOperands,
     /*  410924 */     // GIR_Coverage, 25885,
     /*  410924 */     GIR_EraseRootFromParent_Done,
     /*  410925 */   // Label 6158: @410925
     /*  410925 */   GIM_Try, /*On fail goto*//*Label 6159*/ GIMT_Encode4(410986), // Rule ID 25891 //
     /*  410930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  410933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  410942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  410949 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  410949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  410952 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  410954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  410959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  410964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  410969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  410974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  410980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  410984 */     GIR_RootConstrainSelectedInstOperands,
     /*  410985 */     // GIR_Coverage, 25891,
     /*  410985 */     GIR_EraseRootFromParent_Done,
     /*  410986 */   // Label 6159: @410986
     /*  410986 */   GIM_Try, /*On fail goto*//*Label 6160*/ GIMT_Encode4(411047), // Rule ID 25892 //
     /*  410991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  410994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  410999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  411010 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  411010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  411013 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  411020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  411030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  411035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411045 */     GIR_RootConstrainSelectedInstOperands,
     /*  411046 */     // GIR_Coverage, 25892,
     /*  411046 */     GIR_EraseRootFromParent_Done,
     /*  411047 */   // Label 6160: @411047
     /*  411047 */   GIM_Try, /*On fail goto*//*Label 6161*/ GIMT_Encode4(411108), // Rule ID 25893 //
     /*  411052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  411055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  411060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  411071 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  411071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  411074 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  411081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  411091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  411096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411106 */     GIR_RootConstrainSelectedInstOperands,
     /*  411107 */     // GIR_Coverage, 25893,
     /*  411107 */     GIR_EraseRootFromParent_Done,
     /*  411108 */   // Label 6161: @411108
     /*  411108 */   GIM_Try, /*On fail goto*//*Label 6162*/ GIMT_Encode4(411169), // Rule ID 25894 //
     /*  411113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  411116 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  411121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  411132 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  411132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  411135 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  411142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  411152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  411157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411167 */     GIR_RootConstrainSelectedInstOperands,
     /*  411168 */     // GIR_Coverage, 25894,
     /*  411168 */     GIR_EraseRootFromParent_Done,
     /*  411169 */   // Label 6162: @411169
     /*  411169 */   GIM_Try, /*On fail goto*//*Label 6163*/ GIMT_Encode4(411230), // Rule ID 25895 //
     /*  411174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  411177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  411182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  411193 */     // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  411193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  411196 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  411203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  411213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  411218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411228 */     GIR_RootConstrainSelectedInstOperands,
     /*  411229 */     // GIR_Coverage, 25895,
     /*  411229 */     GIR_EraseRootFromParent_Done,
     /*  411230 */   // Label 6163: @411230
     /*  411230 */   GIM_Try, /*On fail goto*//*Label 6164*/ GIMT_Encode4(411288), // Rule ID 15993 //
     /*  411235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  411238 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411245 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411249 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411256 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  411259 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411286 */     GIR_RootConstrainSelectedInstOperands,
     /*  411287 */     // GIR_Coverage, 15993,
     /*  411287 */     GIR_EraseRootFromParent_Done,
     /*  411288 */   // Label 6164: @411288
     /*  411288 */   GIM_Try, /*On fail goto*//*Label 6165*/ GIMT_Encode4(411346), // Rule ID 15994 //
     /*  411293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  411296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411314 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  411317 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411344 */     GIR_RootConstrainSelectedInstOperands,
     /*  411345 */     // GIR_Coverage, 15994,
     /*  411345 */     GIR_EraseRootFromParent_Done,
     /*  411346 */   // Label 6165: @411346
     /*  411346 */   GIM_Try, /*On fail goto*//*Label 6166*/ GIMT_Encode4(411404), // Rule ID 15995 //
     /*  411351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  411354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411365 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411372 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  411375 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411402 */     GIR_RootConstrainSelectedInstOperands,
     /*  411403 */     // GIR_Coverage, 15995,
     /*  411403 */     GIR_EraseRootFromParent_Done,
     /*  411404 */   // Label 6166: @411404
     /*  411404 */   GIM_Try, /*On fail goto*//*Label 6167*/ GIMT_Encode4(411462), // Rule ID 15996 //
     /*  411409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  411412 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411430 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  411433 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411460 */     GIR_RootConstrainSelectedInstOperands,
     /*  411461 */     // GIR_Coverage, 15996,
     /*  411461 */     GIR_EraseRootFromParent_Done,
     /*  411462 */   // Label 6167: @411462
     /*  411462 */   GIM_Try, /*On fail goto*//*Label 6168*/ GIMT_Encode4(411520), // Rule ID 15997 //
     /*  411467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  411470 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411488 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  411491 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411518 */     GIR_RootConstrainSelectedInstOperands,
     /*  411519 */     // GIR_Coverage, 15997,
     /*  411519 */     GIR_EraseRootFromParent_Done,
     /*  411520 */   // Label 6168: @411520
     /*  411520 */   GIM_Try, /*On fail goto*//*Label 6169*/ GIMT_Encode4(411578), // Rule ID 16003 //
     /*  411525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  411528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411546 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  411549 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411576 */     GIR_RootConstrainSelectedInstOperands,
     /*  411577 */     // GIR_Coverage, 16003,
     /*  411577 */     GIR_EraseRootFromParent_Done,
     /*  411578 */   // Label 6169: @411578
     /*  411578 */   GIM_Try, /*On fail goto*//*Label 6170*/ GIMT_Encode4(411636), // Rule ID 16004 //
     /*  411583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  411586 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411593 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411604 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  411607 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411634 */     GIR_RootConstrainSelectedInstOperands,
     /*  411635 */     // GIR_Coverage, 16004,
     /*  411635 */     GIR_EraseRootFromParent_Done,
     /*  411636 */   // Label 6170: @411636
     /*  411636 */   GIM_Try, /*On fail goto*//*Label 6171*/ GIMT_Encode4(411694), // Rule ID 16005 //
     /*  411641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  411644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411662 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  411665 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411685 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411692 */     GIR_RootConstrainSelectedInstOperands,
     /*  411693 */     // GIR_Coverage, 16005,
     /*  411693 */     GIR_EraseRootFromParent_Done,
     /*  411694 */   // Label 6171: @411694
     /*  411694 */   GIM_Try, /*On fail goto*//*Label 6172*/ GIMT_Encode4(411752), // Rule ID 16006 //
     /*  411699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  411702 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411720 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  411723 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411750 */     GIR_RootConstrainSelectedInstOperands,
     /*  411751 */     // GIR_Coverage, 16006,
     /*  411751 */     GIR_EraseRootFromParent_Done,
     /*  411752 */   // Label 6172: @411752
     /*  411752 */   GIM_Try, /*On fail goto*//*Label 6173*/ GIMT_Encode4(411810), // Rule ID 16007 //
     /*  411757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  411760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  411767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  411778 */     // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  411778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  411781 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  411783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  411788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  411793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  411798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411808 */     GIR_RootConstrainSelectedInstOperands,
     /*  411809 */     // GIR_Coverage, 16007,
     /*  411809 */     GIR_EraseRootFromParent_Done,
     /*  411810 */   // Label 6173: @411810
     /*  411810 */   GIM_Try, /*On fail goto*//*Label 6174*/ GIMT_Encode4(411862), // Rule ID 29273 //
     /*  411815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  411818 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  411822 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  411827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  411838 */     // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  411838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  411841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  411846 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  411853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411860 */     GIR_RootConstrainSelectedInstOperands,
     /*  411861 */     // GIR_Coverage, 29273,
     /*  411861 */     GIR_EraseRootFromParent_Done,
     /*  411862 */   // Label 6174: @411862
     /*  411862 */   GIM_Try, /*On fail goto*//*Label 6175*/ GIMT_Encode4(411914), // Rule ID 29274 //
     /*  411867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  411870 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  411874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  411879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411883 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  411890 */     // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  411890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  411893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  411898 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  411905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411912 */     GIR_RootConstrainSelectedInstOperands,
     /*  411913 */     // GIR_Coverage, 29274,
     /*  411913 */     GIR_EraseRootFromParent_Done,
     /*  411914 */   // Label 6175: @411914
     /*  411914 */   GIM_Try, /*On fail goto*//*Label 6176*/ GIMT_Encode4(411966), // Rule ID 29275 //
     /*  411919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  411922 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  411926 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  411931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  411942 */     // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  411942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  411945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  411950 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  411952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  411957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  411960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  411964 */     GIR_RootConstrainSelectedInstOperands,
     /*  411965 */     // GIR_Coverage, 29275,
     /*  411965 */     GIR_EraseRootFromParent_Done,
     /*  411966 */   // Label 6176: @411966
     /*  411966 */   GIM_Try, /*On fail goto*//*Label 6177*/ GIMT_Encode4(412018), // Rule ID 29276 //
     /*  411971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  411974 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  411978 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  411983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  411987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  411994 */     // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  411994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  411997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412002 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412012 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412016 */     GIR_RootConstrainSelectedInstOperands,
     /*  412017 */     // GIR_Coverage, 29276,
     /*  412017 */     GIR_EraseRootFromParent_Done,
     /*  412018 */   // Label 6177: @412018
     /*  412018 */   GIM_Try, /*On fail goto*//*Label 6178*/ GIMT_Encode4(412070), // Rule ID 29277 //
     /*  412023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  412026 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  412030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  412035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  412046 */     // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  412046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  412049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412054 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412068 */     GIR_RootConstrainSelectedInstOperands,
     /*  412069 */     // GIR_Coverage, 29277,
     /*  412069 */     GIR_EraseRootFromParent_Done,
     /*  412070 */   // Label 6178: @412070
     /*  412070 */   GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(412118), // Rule ID 29278 //
     /*  412075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  412078 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  412083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  412094 */     // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  412094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  412097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412102 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412112 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412116 */     GIR_RootConstrainSelectedInstOperands,
     /*  412117 */     // GIR_Coverage, 29278,
     /*  412117 */     GIR_EraseRootFromParent_Done,
     /*  412118 */   // Label 6179: @412118
     /*  412118 */   GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(412166), // Rule ID 29279 //
     /*  412123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  412126 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  412131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  412142 */     // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  412142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  412145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412150 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412164 */     GIR_RootConstrainSelectedInstOperands,
     /*  412165 */     // GIR_Coverage, 29279,
     /*  412165 */     GIR_EraseRootFromParent_Done,
     /*  412166 */   // Label 6180: @412166
     /*  412166 */   GIM_Try, /*On fail goto*//*Label 6181*/ GIMT_Encode4(412214), // Rule ID 29280 //
     /*  412171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  412174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  412179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  412190 */     // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  412190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  412193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412198 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412212 */     GIR_RootConstrainSelectedInstOperands,
     /*  412213 */     // GIR_Coverage, 29280,
     /*  412213 */     GIR_EraseRootFromParent_Done,
     /*  412214 */   // Label 6181: @412214
     /*  412214 */   GIM_Try, /*On fail goto*//*Label 6182*/ GIMT_Encode4(412262), // Rule ID 29281 //
     /*  412219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  412222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  412227 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412231 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  412238 */     // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  412238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  412241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412246 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412260 */     GIR_RootConstrainSelectedInstOperands,
     /*  412261 */     // GIR_Coverage, 29281,
     /*  412261 */     GIR_EraseRootFromParent_Done,
     /*  412262 */   // Label 6182: @412262
     /*  412262 */   GIM_Try, /*On fail goto*//*Label 6183*/ GIMT_Encode4(412310), // Rule ID 29282 //
     /*  412267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  412270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  412275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  412286 */     // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  412286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  412289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  412294 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  412296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412308 */     GIR_RootConstrainSelectedInstOperands,
     /*  412309 */     // GIR_Coverage, 29282,
     /*  412309 */     GIR_EraseRootFromParent_Done,
     /*  412310 */   // Label 6183: @412310
     /*  412310 */   GIM_Try, /*On fail goto*//*Label 6184*/ GIMT_Encode4(412367), // Rule ID 12213 //
     /*  412315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  412318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412336 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  412339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412344 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412365 */     GIR_RootConstrainSelectedInstOperands,
     /*  412366 */     // GIR_Coverage, 12213,
     /*  412366 */     GIR_EraseRootFromParent_Done,
     /*  412367 */   // Label 6184: @412367
     /*  412367 */   GIM_Try, /*On fail goto*//*Label 6185*/ GIMT_Encode4(412424), // Rule ID 12214 //
     /*  412372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  412375 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412382 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412393 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  412396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412401 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412422 */     GIR_RootConstrainSelectedInstOperands,
     /*  412423 */     // GIR_Coverage, 12214,
     /*  412423 */     GIR_EraseRootFromParent_Done,
     /*  412424 */   // Label 6185: @412424
     /*  412424 */   GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(412481), // Rule ID 12215 //
     /*  412429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  412432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412443 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412450 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  412453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412458 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412475 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412479 */     GIR_RootConstrainSelectedInstOperands,
     /*  412480 */     // GIR_Coverage, 12215,
     /*  412480 */     GIR_EraseRootFromParent_Done,
     /*  412481 */   // Label 6186: @412481
     /*  412481 */   GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(412538), // Rule ID 12216 //
     /*  412486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  412489 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412507 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  412510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412515 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412536 */     GIR_RootConstrainSelectedInstOperands,
     /*  412537 */     // GIR_Coverage, 12216,
     /*  412537 */     GIR_EraseRootFromParent_Done,
     /*  412538 */   // Label 6187: @412538
     /*  412538 */   GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(412595), // Rule ID 12217 //
     /*  412543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  412546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412564 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  412567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412572 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412593 */     GIR_RootConstrainSelectedInstOperands,
     /*  412594 */     // GIR_Coverage, 12217,
     /*  412594 */     GIR_EraseRootFromParent_Done,
     /*  412595 */   // Label 6188: @412595
     /*  412595 */   GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(412645), // Rule ID 12208 //
     /*  412600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  412603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  412621 */     // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  412621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  412624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  412629 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412639 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412643 */     GIR_RootConstrainSelectedInstOperands,
     /*  412644 */     // GIR_Coverage, 12208,
     /*  412644 */     GIR_EraseRootFromParent_Done,
     /*  412645 */   // Label 6189: @412645
     /*  412645 */   GIM_Try, /*On fail goto*//*Label 6190*/ GIMT_Encode4(412695), // Rule ID 12209 //
     /*  412650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  412653 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  412671 */     // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  412671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  412674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  412679 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412693 */     GIR_RootConstrainSelectedInstOperands,
     /*  412694 */     // GIR_Coverage, 12209,
     /*  412694 */     GIR_EraseRootFromParent_Done,
     /*  412695 */   // Label 6190: @412695
     /*  412695 */   GIM_Try, /*On fail goto*//*Label 6191*/ GIMT_Encode4(412745), // Rule ID 12210 //
     /*  412700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  412703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  412721 */     // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  412721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  412724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  412729 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412743 */     GIR_RootConstrainSelectedInstOperands,
     /*  412744 */     // GIR_Coverage, 12210,
     /*  412744 */     GIR_EraseRootFromParent_Done,
     /*  412745 */   // Label 6191: @412745
     /*  412745 */   GIM_Try, /*On fail goto*//*Label 6192*/ GIMT_Encode4(412795), // Rule ID 12211 //
     /*  412750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  412753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  412771 */     // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  412771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  412774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  412779 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412793 */     GIR_RootConstrainSelectedInstOperands,
     /*  412794 */     // GIR_Coverage, 12211,
     /*  412794 */     GIR_EraseRootFromParent_Done,
     /*  412795 */   // Label 6192: @412795
     /*  412795 */   GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(412845), // Rule ID 12212 //
     /*  412800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  412803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  412810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  412821 */     // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  412821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  412824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  412829 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  412836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  412839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412843 */     GIR_RootConstrainSelectedInstOperands,
     /*  412844 */     // GIR_Coverage, 12212,
     /*  412844 */     GIR_EraseRootFromParent_Done,
     /*  412845 */   // Label 6193: @412845
     /*  412845 */   GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(412901), // Rule ID 10071 //
     /*  412850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  412853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  412859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412870 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  412873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412878 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412899 */     GIR_RootConstrainSelectedInstOperands,
     /*  412900 */     // GIR_Coverage, 10071,
     /*  412900 */     GIR_EraseRootFromParent_Done,
     /*  412901 */   // Label 6194: @412901
     /*  412901 */   GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(412957), // Rule ID 10072 //
     /*  412906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  412909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  412915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412926 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  412929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412934 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  412946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  412951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  412955 */     GIR_RootConstrainSelectedInstOperands,
     /*  412956 */     // GIR_Coverage, 10072,
     /*  412956 */     GIR_EraseRootFromParent_Done,
     /*  412957 */   // Label 6195: @412957
     /*  412957 */   GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(413013), // Rule ID 10073 //
     /*  412962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  412965 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  412971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  412975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  412982 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  412982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  412985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  412990 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  412992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  412997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  413002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  413007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413011 */     GIR_RootConstrainSelectedInstOperands,
     /*  413012 */     // GIR_Coverage, 10073,
     /*  413012 */     GIR_EraseRootFromParent_Done,
     /*  413013 */   // Label 6196: @413013
     /*  413013 */   GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(413069), // Rule ID 10074 //
     /*  413018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  413021 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  413038 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  413038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  413041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  413046 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  413053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  413058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  413063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413067 */     GIR_RootConstrainSelectedInstOperands,
     /*  413068 */     // GIR_Coverage, 10074,
     /*  413068 */     GIR_EraseRootFromParent_Done,
     /*  413069 */   // Label 6197: @413069
     /*  413069 */   GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(413125), // Rule ID 10075 //
     /*  413074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  413077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  413094 */     // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  413094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  413097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  413102 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  413109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  413114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  413119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413123 */     GIR_RootConstrainSelectedInstOperands,
     /*  413124 */     // GIR_Coverage, 10075,
     /*  413124 */     GIR_EraseRootFromParent_Done,
     /*  413125 */   // Label 6198: @413125
     /*  413125 */   GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(413174), // Rule ID 10066 //
     /*  413130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  413133 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  413150 */     // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  413150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  413153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  413158 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413172 */     GIR_RootConstrainSelectedInstOperands,
     /*  413173 */     // GIR_Coverage, 10066,
     /*  413173 */     GIR_EraseRootFromParent_Done,
     /*  413174 */   // Label 6199: @413174
     /*  413174 */   GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(413223), // Rule ID 10067 //
     /*  413179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  413182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413188 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413192 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  413199 */     // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  413199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  413202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  413207 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413217 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413221 */     GIR_RootConstrainSelectedInstOperands,
     /*  413222 */     // GIR_Coverage, 10067,
     /*  413222 */     GIR_EraseRootFromParent_Done,
     /*  413223 */   // Label 6200: @413223
     /*  413223 */   GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(413272), // Rule ID 10068 //
     /*  413228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  413231 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  413248 */     // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  413248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  413251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  413256 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413270 */     GIR_RootConstrainSelectedInstOperands,
     /*  413271 */     // GIR_Coverage, 10068,
     /*  413271 */     GIR_EraseRootFromParent_Done,
     /*  413272 */   // Label 6201: @413272
     /*  413272 */   GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(413321), // Rule ID 10069 //
     /*  413277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  413280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413286 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413290 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  413297 */     // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  413297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  413300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  413305 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413315 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413319 */     GIR_RootConstrainSelectedInstOperands,
     /*  413320 */     // GIR_Coverage, 10069,
     /*  413320 */     GIR_EraseRootFromParent_Done,
     /*  413321 */   // Label 6202: @413321
     /*  413321 */   GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(413370), // Rule ID 10070 //
     /*  413326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  413329 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  413335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  413346 */     // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  413346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  413349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  413354 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  413356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413368 */     GIR_RootConstrainSelectedInstOperands,
     /*  413369 */     // GIR_Coverage, 10070,
     /*  413369 */     GIR_EraseRootFromParent_Done,
     /*  413370 */   // Label 6203: @413370
     /*  413370 */   GIM_Reject,
     /*  413371 */ // Label 6118: @413371
     /*  413371 */ GIM_Reject,
     /*  413372 */ // Label 5862: @413372
     /*  413372 */ GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(417766),
     /*  413377 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  413380 */   GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(413441), // Rule ID 30113 //
     /*  413385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  413388 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413397 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413406 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  413410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413417 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413425 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413439 */     GIR_RootConstrainSelectedInstOperands,
     /*  413440 */     // GIR_Coverage, 30113,
     /*  413440 */     GIR_EraseRootFromParent_Done,
     /*  413441 */   // Label 6205: @413441
     /*  413441 */   GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(413502), // Rule ID 30114 //
     /*  413446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  413449 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413467 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  413471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413478 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413486 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413500 */     GIR_RootConstrainSelectedInstOperands,
     /*  413501 */     // GIR_Coverage, 30114,
     /*  413501 */     GIR_EraseRootFromParent_Done,
     /*  413502 */   // Label 6206: @413502
     /*  413502 */   GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(413563), // Rule ID 30115 //
     /*  413507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  413510 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413528 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  413532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413539 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413547 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413554 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413557 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413561 */     GIR_RootConstrainSelectedInstOperands,
     /*  413562 */     // GIR_Coverage, 30115,
     /*  413562 */     GIR_EraseRootFromParent_Done,
     /*  413563 */   // Label 6207: @413563
     /*  413563 */   GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(413624), // Rule ID 30116 //
     /*  413568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  413571 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413575 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413589 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  413593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413600 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413608 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413622 */     GIR_RootConstrainSelectedInstOperands,
     /*  413623 */     // GIR_Coverage, 30116,
     /*  413623 */     GIR_EraseRootFromParent_Done,
     /*  413624 */   // Label 6208: @413624
     /*  413624 */   GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(413685), // Rule ID 30117 //
     /*  413629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  413632 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413636 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413650 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  413654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413661 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413669 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413683 */     GIR_RootConstrainSelectedInstOperands,
     /*  413684 */     // GIR_Coverage, 30117,
     /*  413684 */     GIR_EraseRootFromParent_Done,
     /*  413685 */   // Label 6209: @413685
     /*  413685 */   GIM_Try, /*On fail goto*//*Label 6210*/ GIMT_Encode4(413741), // Rule ID 29773 //
     /*  413690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  413693 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413697 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413702 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  413706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413717 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413725 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413739 */     GIR_RootConstrainSelectedInstOperands,
     /*  413740 */     // GIR_Coverage, 29773,
     /*  413740 */     GIR_EraseRootFromParent_Done,
     /*  413741 */   // Label 6210: @413741
     /*  413741 */   GIM_Try, /*On fail goto*//*Label 6211*/ GIMT_Encode4(413797), // Rule ID 29774 //
     /*  413746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  413749 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413758 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  413762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413773 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413781 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413788 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413795 */     GIR_RootConstrainSelectedInstOperands,
     /*  413796 */     // GIR_Coverage, 29774,
     /*  413796 */     GIR_EraseRootFromParent_Done,
     /*  413797 */   // Label 6211: @413797
     /*  413797 */   GIM_Try, /*On fail goto*//*Label 6212*/ GIMT_Encode4(413853), // Rule ID 29775 //
     /*  413802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  413805 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413814 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  413818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413829 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413837 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413851 */     GIR_RootConstrainSelectedInstOperands,
     /*  413852 */     // GIR_Coverage, 29775,
     /*  413852 */     GIR_EraseRootFromParent_Done,
     /*  413853 */   // Label 6212: @413853
     /*  413853 */   GIM_Try, /*On fail goto*//*Label 6213*/ GIMT_Encode4(413909), // Rule ID 29776 //
     /*  413858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  413861 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413870 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  413874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413885 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413893 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413900 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413903 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413907 */     GIR_RootConstrainSelectedInstOperands,
     /*  413908 */     // GIR_Coverage, 29776,
     /*  413908 */     GIR_EraseRootFromParent_Done,
     /*  413909 */   // Label 6213: @413909
     /*  413909 */   GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(413965), // Rule ID 29777 //
     /*  413914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  413917 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  413921 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413926 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  413930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413941 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  413944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  413949 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  413951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  413956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  413959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  413963 */     GIR_RootConstrainSelectedInstOperands,
     /*  413964 */     // GIR_Coverage, 29777,
     /*  413964 */     GIR_EraseRootFromParent_Done,
     /*  413965 */   // Label 6214: @413965
     /*  413965 */   GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(414022), // Rule ID 30118 //
     /*  413970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  413973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413978 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  413983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  413987 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  413991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  413998 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  413998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414006 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414020 */     GIR_RootConstrainSelectedInstOperands,
     /*  414021 */     // GIR_Coverage, 30118,
     /*  414021 */     GIR_EraseRootFromParent_Done,
     /*  414022 */   // Label 6215: @414022
     /*  414022 */   GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(414079), // Rule ID 30119 //
     /*  414027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  414030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414035 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414040 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414044 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  414048 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414055 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414063 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414073 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414077 */     GIR_RootConstrainSelectedInstOperands,
     /*  414078 */     // GIR_Coverage, 30119,
     /*  414078 */     GIR_EraseRootFromParent_Done,
     /*  414079 */   // Label 6216: @414079
     /*  414079 */   GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(414136), // Rule ID 30120 //
     /*  414084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  414087 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414101 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  414105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414112 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414120 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414134 */     GIR_RootConstrainSelectedInstOperands,
     /*  414135 */     // GIR_Coverage, 30120,
     /*  414135 */     GIR_EraseRootFromParent_Done,
     /*  414136 */   // Label 6217: @414136
     /*  414136 */   GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(414193), // Rule ID 30121 //
     /*  414141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  414144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414158 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  414162 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414169 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414177 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414191 */     GIR_RootConstrainSelectedInstOperands,
     /*  414192 */     // GIR_Coverage, 30121,
     /*  414192 */     GIR_EraseRootFromParent_Done,
     /*  414193 */   // Label 6218: @414193
     /*  414193 */   GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(414250), // Rule ID 30122 //
     /*  414198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  414201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414206 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414211 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414215 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  414219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414226 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414234 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414248 */     GIR_RootConstrainSelectedInstOperands,
     /*  414249 */     // GIR_Coverage, 30122,
     /*  414249 */     GIR_EraseRootFromParent_Done,
     /*  414250 */   // Label 6219: @414250
     /*  414250 */   GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(414302), // Rule ID 29778 //
     /*  414255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  414258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414263 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  414267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414278 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414286 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414300 */     GIR_RootConstrainSelectedInstOperands,
     /*  414301 */     // GIR_Coverage, 29778,
     /*  414301 */     GIR_EraseRootFromParent_Done,
     /*  414302 */   // Label 6220: @414302
     /*  414302 */   GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(414354), // Rule ID 29779 //
     /*  414307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  414310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414315 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  414319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414330 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414338 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414352 */     GIR_RootConstrainSelectedInstOperands,
     /*  414353 */     // GIR_Coverage, 29779,
     /*  414353 */     GIR_EraseRootFromParent_Done,
     /*  414354 */   // Label 6221: @414354
     /*  414354 */   GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(414406), // Rule ID 29780 //
     /*  414359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  414362 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414367 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  414371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414382 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414390 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414404 */     GIR_RootConstrainSelectedInstOperands,
     /*  414405 */     // GIR_Coverage, 29780,
     /*  414405 */     GIR_EraseRootFromParent_Done,
     /*  414406 */   // Label 6222: @414406
     /*  414406 */   GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(414458), // Rule ID 29781 //
     /*  414411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  414414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414419 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  414423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414427 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414434 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414442 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414456 */     GIR_RootConstrainSelectedInstOperands,
     /*  414457 */     // GIR_Coverage, 29781,
     /*  414457 */     GIR_EraseRootFromParent_Done,
     /*  414458 */   // Label 6223: @414458
     /*  414458 */   GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(414510), // Rule ID 29782 //
     /*  414463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  414466 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  414471 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  414475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  414486 */     // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  414486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  414489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  414494 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  414496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414508 */     GIR_RootConstrainSelectedInstOperands,
     /*  414509 */     // GIR_Coverage, 29782,
     /*  414509 */     GIR_EraseRootFromParent_Done,
     /*  414510 */   // Label 6224: @414510
     /*  414510 */   GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(414565), // Rule ID 14557 //
     /*  414515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  414518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  414534 */     // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  414534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  414537 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  414544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  414549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  414554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  414559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414563 */     GIR_RootConstrainSelectedInstOperands,
     /*  414564 */     // GIR_Coverage, 14557,
     /*  414564 */     GIR_EraseRootFromParent_Done,
     /*  414565 */   // Label 6225: @414565
     /*  414565 */   GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(414620), // Rule ID 14558 //
     /*  414570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  414573 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  414589 */     // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  414589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  414592 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  414599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  414604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  414609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  414614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414618 */     GIR_RootConstrainSelectedInstOperands,
     /*  414619 */     // GIR_Coverage, 14558,
     /*  414619 */     GIR_EraseRootFromParent_Done,
     /*  414620 */   // Label 6226: @414620
     /*  414620 */   GIM_Try, /*On fail goto*//*Label 6227*/ GIMT_Encode4(414675), // Rule ID 14559 //
     /*  414625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  414628 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414633 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414637 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  414644 */     // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  414644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  414647 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  414654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  414659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  414664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  414669 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414673 */     GIR_RootConstrainSelectedInstOperands,
     /*  414674 */     // GIR_Coverage, 14559,
     /*  414674 */     GIR_EraseRootFromParent_Done,
     /*  414675 */   // Label 6227: @414675
     /*  414675 */   GIM_Try, /*On fail goto*//*Label 6228*/ GIMT_Encode4(414730), // Rule ID 14560 //
     /*  414680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  414683 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414692 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  414699 */     // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  414699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  414702 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  414709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  414714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  414719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  414724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414728 */     GIR_RootConstrainSelectedInstOperands,
     /*  414729 */     // GIR_Coverage, 14560,
     /*  414729 */     GIR_EraseRootFromParent_Done,
     /*  414730 */   // Label 6228: @414730
     /*  414730 */   GIM_Try, /*On fail goto*//*Label 6229*/ GIMT_Encode4(414785), // Rule ID 14561 //
     /*  414735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  414738 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  414754 */     // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  414754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  414757 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  414764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  414769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  414774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  414779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414783 */     GIR_RootConstrainSelectedInstOperands,
     /*  414784 */     // GIR_Coverage, 14561,
     /*  414784 */     GIR_EraseRootFromParent_Done,
     /*  414785 */   // Label 6229: @414785
     /*  414785 */   GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(414833), // Rule ID 14552 //
     /*  414790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  414793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  414809 */     // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  414809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  414812 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  414819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414831 */     GIR_RootConstrainSelectedInstOperands,
     /*  414832 */     // GIR_Coverage, 14552,
     /*  414832 */     GIR_EraseRootFromParent_Done,
     /*  414833 */   // Label 6230: @414833
     /*  414833 */   GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(414881), // Rule ID 14553 //
     /*  414838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  414841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  414857 */     // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  414857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  414860 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  414867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414879 */     GIR_RootConstrainSelectedInstOperands,
     /*  414880 */     // GIR_Coverage, 14553,
     /*  414880 */     GIR_EraseRootFromParent_Done,
     /*  414881 */   // Label 6231: @414881
     /*  414881 */   GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(414929), // Rule ID 14554 //
     /*  414886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  414889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  414905 */     // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  414905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  414908 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  414915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414927 */     GIR_RootConstrainSelectedInstOperands,
     /*  414928 */     // GIR_Coverage, 14554,
     /*  414928 */     GIR_EraseRootFromParent_Done,
     /*  414929 */   // Label 6232: @414929
     /*  414929 */   GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(414977), // Rule ID 14555 //
     /*  414934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  414937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  414953 */     // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  414953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  414956 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  414958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  414963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  414968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  414971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  414975 */     GIR_RootConstrainSelectedInstOperands,
     /*  414976 */     // GIR_Coverage, 14555,
     /*  414976 */     GIR_EraseRootFromParent_Done,
     /*  414977 */   // Label 6233: @414977
     /*  414977 */   GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(415025), // Rule ID 14556 //
     /*  414982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  414985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  414990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  414994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  415001 */     // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  415001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  415004 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  415006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  415011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  415016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415023 */     GIR_RootConstrainSelectedInstOperands,
     /*  415024 */     // GIR_Coverage, 14556,
     /*  415024 */     GIR_EraseRootFromParent_Done,
     /*  415025 */   // Label 6234: @415025
     /*  415025 */   GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(415073), // Rule ID 14547 //
     /*  415030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  415033 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  415038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  415049 */     // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  415049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  415052 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  415054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  415059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  415064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415071 */     GIR_RootConstrainSelectedInstOperands,
     /*  415072 */     // GIR_Coverage, 14547,
     /*  415072 */     GIR_EraseRootFromParent_Done,
     /*  415073 */   // Label 6235: @415073
     /*  415073 */   GIM_Try, /*On fail goto*//*Label 6236*/ GIMT_Encode4(415121), // Rule ID 14548 //
     /*  415078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  415081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  415086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  415097 */     // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  415097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  415100 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  415102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  415107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  415112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415119 */     GIR_RootConstrainSelectedInstOperands,
     /*  415120 */     // GIR_Coverage, 14548,
     /*  415120 */     GIR_EraseRootFromParent_Done,
     /*  415121 */   // Label 6236: @415121
     /*  415121 */   GIM_Try, /*On fail goto*//*Label 6237*/ GIMT_Encode4(415169), // Rule ID 14549 //
     /*  415126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  415129 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  415134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  415145 */     // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  415145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  415148 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  415150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  415155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  415160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415167 */     GIR_RootConstrainSelectedInstOperands,
     /*  415168 */     // GIR_Coverage, 14549,
     /*  415168 */     GIR_EraseRootFromParent_Done,
     /*  415169 */   // Label 6237: @415169
     /*  415169 */   GIM_Try, /*On fail goto*//*Label 6238*/ GIMT_Encode4(415217), // Rule ID 14550 //
     /*  415174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  415177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  415182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  415193 */     // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  415193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  415196 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  415198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  415203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  415208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415215 */     GIR_RootConstrainSelectedInstOperands,
     /*  415216 */     // GIR_Coverage, 14550,
     /*  415216 */     GIR_EraseRootFromParent_Done,
     /*  415217 */   // Label 6238: @415217
     /*  415217 */   GIM_Try, /*On fail goto*//*Label 6239*/ GIMT_Encode4(415265), // Rule ID 14551 //
     /*  415222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  415225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  415230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  415241 */     // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  415241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  415244 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  415246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  415251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  415256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415263 */     GIR_RootConstrainSelectedInstOperands,
     /*  415264 */     // GIR_Coverage, 14551,
     /*  415264 */     GIR_EraseRootFromParent_Done,
     /*  415265 */   // Label 6239: @415265
     /*  415265 */   GIM_Try, /*On fail goto*//*Label 6240*/ GIMT_Encode4(415328), // Rule ID 16218 //
     /*  415270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  415273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415291 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  415294 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415326 */     GIR_RootConstrainSelectedInstOperands,
     /*  415327 */     // GIR_Coverage, 16218,
     /*  415327 */     GIR_EraseRootFromParent_Done,
     /*  415328 */   // Label 6240: @415328
     /*  415328 */   GIM_Try, /*On fail goto*//*Label 6241*/ GIMT_Encode4(415391), // Rule ID 16219 //
     /*  415333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  415336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415354 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  415357 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415389 */     GIR_RootConstrainSelectedInstOperands,
     /*  415390 */     // GIR_Coverage, 16219,
     /*  415390 */     GIR_EraseRootFromParent_Done,
     /*  415391 */   // Label 6241: @415391
     /*  415391 */   GIM_Try, /*On fail goto*//*Label 6242*/ GIMT_Encode4(415454), // Rule ID 16220 //
     /*  415396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  415399 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415417 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  415420 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415452 */     GIR_RootConstrainSelectedInstOperands,
     /*  415453 */     // GIR_Coverage, 16220,
     /*  415453 */     GIR_EraseRootFromParent_Done,
     /*  415454 */   // Label 6242: @415454
     /*  415454 */   GIM_Try, /*On fail goto*//*Label 6243*/ GIMT_Encode4(415517), // Rule ID 16221 //
     /*  415459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  415462 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415469 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415480 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  415483 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415515 */     GIR_RootConstrainSelectedInstOperands,
     /*  415516 */     // GIR_Coverage, 16221,
     /*  415516 */     GIR_EraseRootFromParent_Done,
     /*  415517 */   // Label 6243: @415517
     /*  415517 */   GIM_Try, /*On fail goto*//*Label 6244*/ GIMT_Encode4(415580), // Rule ID 16222 //
     /*  415522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  415525 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415543 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  415546 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415578 */     GIR_RootConstrainSelectedInstOperands,
     /*  415579 */     // GIR_Coverage, 16222,
     /*  415579 */     GIR_EraseRootFromParent_Done,
     /*  415580 */   // Label 6244: @415580
     /*  415580 */   GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(415643), // Rule ID 16228 //
     /*  415585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  415588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415606 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  415609 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415637 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415641 */     GIR_RootConstrainSelectedInstOperands,
     /*  415642 */     // GIR_Coverage, 16228,
     /*  415642 */     GIR_EraseRootFromParent_Done,
     /*  415643 */   // Label 6245: @415643
     /*  415643 */   GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(415706), // Rule ID 16229 //
     /*  415648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  415651 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415658 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415662 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415669 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  415672 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415704 */     GIR_RootConstrainSelectedInstOperands,
     /*  415705 */     // GIR_Coverage, 16229,
     /*  415705 */     GIR_EraseRootFromParent_Done,
     /*  415706 */   // Label 6246: @415706
     /*  415706 */   GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(415769), // Rule ID 16230 //
     /*  415711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  415714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415732 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  415735 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415767 */     GIR_RootConstrainSelectedInstOperands,
     /*  415768 */     // GIR_Coverage, 16230,
     /*  415768 */     GIR_EraseRootFromParent_Done,
     /*  415769 */   // Label 6247: @415769
     /*  415769 */   GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(415832), // Rule ID 16231 //
     /*  415774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  415777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415795 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  415798 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415820 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415830 */     GIR_RootConstrainSelectedInstOperands,
     /*  415831 */     // GIR_Coverage, 16231,
     /*  415831 */     GIR_EraseRootFromParent_Done,
     /*  415832 */   // Label 6248: @415832
     /*  415832 */   GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(415895), // Rule ID 16232 //
     /*  415837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  415840 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  415847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  415858 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  415858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  415861 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  415863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  415868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  415873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  415878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  415883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  415889 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  415893 */     GIR_RootConstrainSelectedInstOperands,
     /*  415894 */     // GIR_Coverage, 16232,
     /*  415894 */     GIR_EraseRootFromParent_Done,
     /*  415895 */   // Label 6249: @415895
     /*  415895 */   GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(416012), // Rule ID 29496 //
     /*  415900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  415903 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  415907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  415912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  415916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  415923 */     // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  415923 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  415926 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  415930 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  415935 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  415941 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  415946 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  415951 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  415954 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  415958 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  415963 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  415969 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  415974 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  415979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  415982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  415987 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  415990 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  415993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  415998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  416003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416010 */     GIR_RootConstrainSelectedInstOperands,
     /*  416011 */     // GIR_Coverage, 29496,
     /*  416011 */     GIR_EraseRootFromParent_Done,
     /*  416012 */   // Label 6250: @416012
     /*  416012 */   GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(416070), // Rule ID 16213 //
     /*  416017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  416020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416038 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  416041 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416068 */     GIR_RootConstrainSelectedInstOperands,
     /*  416069 */     // GIR_Coverage, 16213,
     /*  416069 */     GIR_EraseRootFromParent_Done,
     /*  416070 */   // Label 6251: @416070
     /*  416070 */   GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(416128), // Rule ID 16214 //
     /*  416075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  416078 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416085 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416096 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  416099 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416126 */     GIR_RootConstrainSelectedInstOperands,
     /*  416127 */     // GIR_Coverage, 16214,
     /*  416127 */     GIR_EraseRootFromParent_Done,
     /*  416128 */   // Label 6252: @416128
     /*  416128 */   GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(416186), // Rule ID 16215 //
     /*  416133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  416136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416154 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  416157 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416184 */     GIR_RootConstrainSelectedInstOperands,
     /*  416185 */     // GIR_Coverage, 16215,
     /*  416185 */     GIR_EraseRootFromParent_Done,
     /*  416186 */   // Label 6253: @416186
     /*  416186 */   GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(416244), // Rule ID 16216 //
     /*  416191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  416194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416212 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  416215 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416242 */     GIR_RootConstrainSelectedInstOperands,
     /*  416243 */     // GIR_Coverage, 16216,
     /*  416243 */     GIR_EraseRootFromParent_Done,
     /*  416244 */   // Label 6254: @416244
     /*  416244 */   GIM_Try, /*On fail goto*//*Label 6255*/ GIMT_Encode4(416302), // Rule ID 16217 //
     /*  416249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  416252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416270 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  416273 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416300 */     GIR_RootConstrainSelectedInstOperands,
     /*  416301 */     // GIR_Coverage, 16217,
     /*  416301 */     GIR_EraseRootFromParent_Done,
     /*  416302 */   // Label 6255: @416302
     /*  416302 */   GIM_Try, /*On fail goto*//*Label 6256*/ GIMT_Encode4(416360), // Rule ID 16223 //
     /*  416307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  416310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416328 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  416331 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416358 */     GIR_RootConstrainSelectedInstOperands,
     /*  416359 */     // GIR_Coverage, 16223,
     /*  416359 */     GIR_EraseRootFromParent_Done,
     /*  416360 */   // Label 6256: @416360
     /*  416360 */   GIM_Try, /*On fail goto*//*Label 6257*/ GIMT_Encode4(416418), // Rule ID 16224 //
     /*  416365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  416368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416386 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  416389 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416416 */     GIR_RootConstrainSelectedInstOperands,
     /*  416417 */     // GIR_Coverage, 16224,
     /*  416417 */     GIR_EraseRootFromParent_Done,
     /*  416418 */   // Label 6257: @416418
     /*  416418 */   GIM_Try, /*On fail goto*//*Label 6258*/ GIMT_Encode4(416476), // Rule ID 16225 //
     /*  416423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  416426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416444 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  416447 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416474 */     GIR_RootConstrainSelectedInstOperands,
     /*  416475 */     // GIR_Coverage, 16225,
     /*  416475 */     GIR_EraseRootFromParent_Done,
     /*  416476 */   // Label 6258: @416476
     /*  416476 */   GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(416534), // Rule ID 16226 //
     /*  416481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  416484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416502 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  416505 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416532 */     GIR_RootConstrainSelectedInstOperands,
     /*  416533 */     // GIR_Coverage, 16226,
     /*  416533 */     GIR_EraseRootFromParent_Done,
     /*  416534 */   // Label 6259: @416534
     /*  416534 */   GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(416592), // Rule ID 16227 //
     /*  416539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  416542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  416560 */     // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  416560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  416563 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  416565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  416570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  416575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416590 */     GIR_RootConstrainSelectedInstOperands,
     /*  416591 */     // GIR_Coverage, 16227,
     /*  416591 */     GIR_EraseRootFromParent_Done,
     /*  416592 */   // Label 6260: @416592
     /*  416592 */   GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(416705), // Rule ID 29502 //
     /*  416597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  416600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  416605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  416616 */     // (st p4:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  416616 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  416619 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  416623 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  416628 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  416634 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  416639 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  416644 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  416647 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  416651 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  416656 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  416662 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  416667 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  416672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  416675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  416680 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  416683 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  416686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  416691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  416696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  416699 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416703 */     GIR_RootConstrainSelectedInstOperands,
     /*  416704 */     // GIR_Coverage, 29502,
     /*  416704 */     GIR_EraseRootFromParent_Done,
     /*  416705 */   // Label 6261: @416705
     /*  416705 */   GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(416762), // Rule ID 12433 //
     /*  416710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  416713 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  416731 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  416731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  416734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  416739 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  416741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  416746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  416756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416760 */     GIR_RootConstrainSelectedInstOperands,
     /*  416761 */     // GIR_Coverage, 12433,
     /*  416761 */     GIR_EraseRootFromParent_Done,
     /*  416762 */   // Label 6262: @416762
     /*  416762 */   GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(416819), // Rule ID 12434 //
     /*  416767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  416770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  416788 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  416788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  416791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  416796 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  416798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  416803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  416813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416817 */     GIR_RootConstrainSelectedInstOperands,
     /*  416818 */     // GIR_Coverage, 12434,
     /*  416818 */     GIR_EraseRootFromParent_Done,
     /*  416819 */   // Label 6263: @416819
     /*  416819 */   GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(416876), // Rule ID 12435 //
     /*  416824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  416827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  416845 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  416845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  416848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  416853 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  416855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  416860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  416870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416874 */     GIR_RootConstrainSelectedInstOperands,
     /*  416875 */     // GIR_Coverage, 12435,
     /*  416875 */     GIR_EraseRootFromParent_Done,
     /*  416876 */   // Label 6264: @416876
     /*  416876 */   GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(416933), // Rule ID 12436 //
     /*  416881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  416884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  416902 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  416902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  416905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  416910 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  416912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  416917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  416927 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416931 */     GIR_RootConstrainSelectedInstOperands,
     /*  416932 */     // GIR_Coverage, 12436,
     /*  416932 */     GIR_EraseRootFromParent_Done,
     /*  416933 */   // Label 6265: @416933
     /*  416933 */   GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(416990), // Rule ID 12437 //
     /*  416938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  416941 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  416948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  416952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  416959 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  416959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  416962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  416967 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  416969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  416974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  416979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  416984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  416988 */     GIR_RootConstrainSelectedInstOperands,
     /*  416989 */     // GIR_Coverage, 12437,
     /*  416989 */     GIR_EraseRootFromParent_Done,
     /*  416990 */   // Label 6266: @416990
     /*  416990 */   GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(417040), // Rule ID 12428 //
     /*  416995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  416998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  417005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  417016 */     // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  417019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417024 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417038 */     GIR_RootConstrainSelectedInstOperands,
     /*  417039 */     // GIR_Coverage, 12428,
     /*  417039 */     GIR_EraseRootFromParent_Done,
     /*  417040 */   // Label 6267: @417040
     /*  417040 */   GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(417090), // Rule ID 12429 //
     /*  417045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  417048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  417055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  417066 */     // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  417069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417074 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417088 */     GIR_RootConstrainSelectedInstOperands,
     /*  417089 */     // GIR_Coverage, 12429,
     /*  417089 */     GIR_EraseRootFromParent_Done,
     /*  417090 */   // Label 6268: @417090
     /*  417090 */   GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(417140), // Rule ID 12430 //
     /*  417095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  417098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  417105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  417116 */     // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  417119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417124 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417138 */     GIR_RootConstrainSelectedInstOperands,
     /*  417139 */     // GIR_Coverage, 12430,
     /*  417139 */     GIR_EraseRootFromParent_Done,
     /*  417140 */   // Label 6269: @417140
     /*  417140 */   GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(417190), // Rule ID 12431 //
     /*  417145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  417148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  417155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  417166 */     // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  417169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417174 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417188 */     GIR_RootConstrainSelectedInstOperands,
     /*  417189 */     // GIR_Coverage, 12431,
     /*  417189 */     GIR_EraseRootFromParent_Done,
     /*  417190 */   // Label 6270: @417190
     /*  417190 */   GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(417240), // Rule ID 12432 //
     /*  417195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  417198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  417205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  417216 */     // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  417219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417224 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417238 */     GIR_RootConstrainSelectedInstOperands,
     /*  417239 */     // GIR_Coverage, 12432,
     /*  417239 */     GIR_EraseRootFromParent_Done,
     /*  417240 */   // Label 6271: @417240
     /*  417240 */   GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(417296), // Rule ID 10281 //
     /*  417245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  417248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417254 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  417265 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  417265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  417268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  417273 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  417280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  417290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417294 */     GIR_RootConstrainSelectedInstOperands,
     /*  417295 */     // GIR_Coverage, 10281,
     /*  417295 */     GIR_EraseRootFromParent_Done,
     /*  417296 */   // Label 6272: @417296
     /*  417296 */   GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(417352), // Rule ID 10282 //
     /*  417301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  417304 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  417321 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  417321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  417324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  417329 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  417336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  417346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417350 */     GIR_RootConstrainSelectedInstOperands,
     /*  417351 */     // GIR_Coverage, 10282,
     /*  417351 */     GIR_EraseRootFromParent_Done,
     /*  417352 */   // Label 6273: @417352
     /*  417352 */   GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(417408), // Rule ID 10283 //
     /*  417357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  417360 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  417377 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  417377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  417380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  417385 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  417392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  417402 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417406 */     GIR_RootConstrainSelectedInstOperands,
     /*  417407 */     // GIR_Coverage, 10283,
     /*  417407 */     GIR_EraseRootFromParent_Done,
     /*  417408 */   // Label 6274: @417408
     /*  417408 */   GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(417464), // Rule ID 10284 //
     /*  417413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  417416 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  417433 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  417433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  417436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  417441 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  417448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  417458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417462 */     GIR_RootConstrainSelectedInstOperands,
     /*  417463 */     // GIR_Coverage, 10284,
     /*  417463 */     GIR_EraseRootFromParent_Done,
     /*  417464 */   // Label 6275: @417464
     /*  417464 */   GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(417520), // Rule ID 10285 //
     /*  417469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  417472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417478 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417482 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  417489 */     // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  417489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  417492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  417497 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  417504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  417514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417518 */     GIR_RootConstrainSelectedInstOperands,
     /*  417519 */     // GIR_Coverage, 10285,
     /*  417519 */     GIR_EraseRootFromParent_Done,
     /*  417520 */   // Label 6276: @417520
     /*  417520 */   GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(417569), // Rule ID 10276 //
     /*  417525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  417528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  417545 */     // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  417548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417553 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417567 */     GIR_RootConstrainSelectedInstOperands,
     /*  417568 */     // GIR_Coverage, 10276,
     /*  417568 */     GIR_EraseRootFromParent_Done,
     /*  417569 */   // Label 6277: @417569
     /*  417569 */   GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(417618), // Rule ID 10277 //
     /*  417574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  417577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  417594 */     // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  417597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417602 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417612 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417616 */     GIR_RootConstrainSelectedInstOperands,
     /*  417617 */     // GIR_Coverage, 10277,
     /*  417617 */     GIR_EraseRootFromParent_Done,
     /*  417618 */   // Label 6278: @417618
     /*  417618 */   GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(417667), // Rule ID 10278 //
     /*  417623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  417626 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  417643 */     // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  417646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417651 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417665 */     GIR_RootConstrainSelectedInstOperands,
     /*  417666 */     // GIR_Coverage, 10278,
     /*  417666 */     GIR_EraseRootFromParent_Done,
     /*  417667 */   // Label 6279: @417667
     /*  417667 */   GIM_Try, /*On fail goto*//*Label 6280*/ GIMT_Encode4(417716), // Rule ID 10279 //
     /*  417672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  417675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  417692 */     // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  417695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417700 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417714 */     GIR_RootConstrainSelectedInstOperands,
     /*  417715 */     // GIR_Coverage, 10279,
     /*  417715 */     GIR_EraseRootFromParent_Done,
     /*  417716 */   // Label 6280: @417716
     /*  417716 */   GIM_Try, /*On fail goto*//*Label 6281*/ GIMT_Encode4(417765), // Rule ID 10280 //
     /*  417721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  417724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  417730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  417741 */     // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  417741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  417744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  417749 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  417751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  417756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417759 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417763 */     GIR_RootConstrainSelectedInstOperands,
     /*  417764 */     // GIR_Coverage, 10280,
     /*  417764 */     GIR_EraseRootFromParent_Done,
     /*  417765 */   // Label 6281: @417765
     /*  417765 */   GIM_Reject,
     /*  417766 */ // Label 6204: @417766
     /*  417766 */ GIM_Reject,
     /*  417767 */ // Label 5863: @417767
     /*  417767 */ GIM_Try, /*On fail goto*//*Label 6282*/ GIMT_Encode4(422471),
     /*  417772 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  417775 */   GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(417831), // Rule ID 25906 //
     /*  417780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  417783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  417788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  417799 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  417799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  417802 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  417804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  417809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  417814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417829 */     GIR_RootConstrainSelectedInstOperands,
     /*  417830 */     // GIR_Coverage, 25906,
     /*  417830 */     GIR_EraseRootFromParent_Done,
     /*  417831 */   // Label 6283: @417831
     /*  417831 */   GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(417887), // Rule ID 25907 //
     /*  417836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  417839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  417844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  417855 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  417855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  417858 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  417860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  417865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  417870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417885 */     GIR_RootConstrainSelectedInstOperands,
     /*  417886 */     // GIR_Coverage, 25907,
     /*  417886 */     GIR_EraseRootFromParent_Done,
     /*  417887 */   // Label 6284: @417887
     /*  417887 */   GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(417943), // Rule ID 25908 //
     /*  417892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  417895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  417900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  417911 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  417911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  417914 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  417916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  417921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  417926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417941 */     GIR_RootConstrainSelectedInstOperands,
     /*  417942 */     // GIR_Coverage, 25908,
     /*  417942 */     GIR_EraseRootFromParent_Done,
     /*  417943 */   // Label 6285: @417943
     /*  417943 */   GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(417999), // Rule ID 25909 //
     /*  417948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  417951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  417956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  417960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  417967 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  417967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  417970 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  417972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  417977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  417982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  417987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  417993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  417997 */     GIR_RootConstrainSelectedInstOperands,
     /*  417998 */     // GIR_Coverage, 25909,
     /*  417998 */     GIR_EraseRootFromParent_Done,
     /*  417999 */   // Label 6286: @417999
     /*  417999 */   GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(418055), // Rule ID 25910 //
     /*  418004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  418007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418012 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418016 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  418023 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  418023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  418026 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  418028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  418033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  418038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418053 */     GIR_RootConstrainSelectedInstOperands,
     /*  418054 */     // GIR_Coverage, 25910,
     /*  418054 */     GIR_EraseRootFromParent_Done,
     /*  418055 */   // Label 6287: @418055
     /*  418055 */   GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(418111), // Rule ID 25916 //
     /*  418060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  418063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  418079 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  418079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  418082 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  418084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  418089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  418094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418105 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418109 */     GIR_RootConstrainSelectedInstOperands,
     /*  418110 */     // GIR_Coverage, 25916,
     /*  418110 */     GIR_EraseRootFromParent_Done,
     /*  418111 */   // Label 6288: @418111
     /*  418111 */   GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(418167), // Rule ID 25917 //
     /*  418116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  418119 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418124 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418128 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  418135 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  418135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  418138 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  418140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  418145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  418150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418165 */     GIR_RootConstrainSelectedInstOperands,
     /*  418166 */     // GIR_Coverage, 25917,
     /*  418166 */     GIR_EraseRootFromParent_Done,
     /*  418167 */   // Label 6289: @418167
     /*  418167 */   GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(418223), // Rule ID 25918 //
     /*  418172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  418175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  418191 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  418191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  418194 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  418196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  418201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  418206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418217 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418221 */     GIR_RootConstrainSelectedInstOperands,
     /*  418222 */     // GIR_Coverage, 25918,
     /*  418222 */     GIR_EraseRootFromParent_Done,
     /*  418223 */   // Label 6290: @418223
     /*  418223 */   GIM_Try, /*On fail goto*//*Label 6291*/ GIMT_Encode4(418279), // Rule ID 25919 //
     /*  418228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  418231 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418236 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418240 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  418247 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  418247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  418250 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  418252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  418257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  418262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418277 */     GIR_RootConstrainSelectedInstOperands,
     /*  418278 */     // GIR_Coverage, 25919,
     /*  418278 */     GIR_EraseRootFromParent_Done,
     /*  418279 */   // Label 6291: @418279
     /*  418279 */   GIM_Try, /*On fail goto*//*Label 6292*/ GIMT_Encode4(418335), // Rule ID 25920 //
     /*  418284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  418287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  418303 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  418303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  418306 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  418308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  418313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  418318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418333 */     GIR_RootConstrainSelectedInstOperands,
     /*  418334 */     // GIR_Coverage, 25920,
     /*  418334 */     GIR_EraseRootFromParent_Done,
     /*  418335 */   // Label 6292: @418335
     /*  418335 */   GIM_Try, /*On fail goto*//*Label 6293*/ GIMT_Encode4(418390), // Rule ID 14257 //
     /*  418340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  418343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  418359 */     // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  418359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  418362 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  418374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  418384 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418388 */     GIR_RootConstrainSelectedInstOperands,
     /*  418389 */     // GIR_Coverage, 14257,
     /*  418389 */     GIR_EraseRootFromParent_Done,
     /*  418390 */   // Label 6293: @418390
     /*  418390 */   GIM_Try, /*On fail goto*//*Label 6294*/ GIMT_Encode4(418445), // Rule ID 14258 //
     /*  418395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  418398 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  418414 */     // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  418414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  418417 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  418429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  418439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418443 */     GIR_RootConstrainSelectedInstOperands,
     /*  418444 */     // GIR_Coverage, 14258,
     /*  418444 */     GIR_EraseRootFromParent_Done,
     /*  418445 */   // Label 6294: @418445
     /*  418445 */   GIM_Try, /*On fail goto*//*Label 6295*/ GIMT_Encode4(418500), // Rule ID 14259 //
     /*  418450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  418453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418458 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  418469 */     // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  418469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  418472 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  418484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  418494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418498 */     GIR_RootConstrainSelectedInstOperands,
     /*  418499 */     // GIR_Coverage, 14259,
     /*  418499 */     GIR_EraseRootFromParent_Done,
     /*  418500 */   // Label 6295: @418500
     /*  418500 */   GIM_Try, /*On fail goto*//*Label 6296*/ GIMT_Encode4(418555), // Rule ID 14260 //
     /*  418505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  418508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  418524 */     // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  418524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  418527 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  418539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  418549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418553 */     GIR_RootConstrainSelectedInstOperands,
     /*  418554 */     // GIR_Coverage, 14260,
     /*  418554 */     GIR_EraseRootFromParent_Done,
     /*  418555 */   // Label 6296: @418555
     /*  418555 */   GIM_Try, /*On fail goto*//*Label 6297*/ GIMT_Encode4(418610), // Rule ID 14261 //
     /*  418560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  418563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  418579 */     // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  418579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  418582 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  418594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  418599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  418604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418608 */     GIR_RootConstrainSelectedInstOperands,
     /*  418609 */     // GIR_Coverage, 14261,
     /*  418609 */     GIR_EraseRootFromParent_Done,
     /*  418610 */   // Label 6297: @418610
     /*  418610 */   GIM_Try, /*On fail goto*//*Label 6298*/ GIMT_Encode4(418658), // Rule ID 14252 //
     /*  418615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  418618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418623 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418627 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  418634 */     // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  418634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  418637 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  418644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418656 */     GIR_RootConstrainSelectedInstOperands,
     /*  418657 */     // GIR_Coverage, 14252,
     /*  418657 */     GIR_EraseRootFromParent_Done,
     /*  418658 */   // Label 6298: @418658
     /*  418658 */   GIM_Try, /*On fail goto*//*Label 6299*/ GIMT_Encode4(418706), // Rule ID 14253 //
     /*  418663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  418666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  418682 */     // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  418682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  418685 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  418692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418704 */     GIR_RootConstrainSelectedInstOperands,
     /*  418705 */     // GIR_Coverage, 14253,
     /*  418705 */     GIR_EraseRootFromParent_Done,
     /*  418706 */   // Label 6299: @418706
     /*  418706 */   GIM_Try, /*On fail goto*//*Label 6300*/ GIMT_Encode4(418754), // Rule ID 14254 //
     /*  418711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  418714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  418730 */     // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  418730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  418733 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  418740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418752 */     GIR_RootConstrainSelectedInstOperands,
     /*  418753 */     // GIR_Coverage, 14254,
     /*  418753 */     GIR_EraseRootFromParent_Done,
     /*  418754 */   // Label 6300: @418754
     /*  418754 */   GIM_Try, /*On fail goto*//*Label 6301*/ GIMT_Encode4(418802), // Rule ID 14255 //
     /*  418759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  418762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  418778 */     // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  418778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  418781 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  418788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418800 */     GIR_RootConstrainSelectedInstOperands,
     /*  418801 */     // GIR_Coverage, 14255,
     /*  418801 */     GIR_EraseRootFromParent_Done,
     /*  418802 */   // Label 6301: @418802
     /*  418802 */   GIM_Try, /*On fail goto*//*Label 6302*/ GIMT_Encode4(418850), // Rule ID 14256 //
     /*  418807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  418810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  418826 */     // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  418826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  418829 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  418836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418848 */     GIR_RootConstrainSelectedInstOperands,
     /*  418849 */     // GIR_Coverage, 14256,
     /*  418849 */     GIR_EraseRootFromParent_Done,
     /*  418850 */   // Label 6302: @418850
     /*  418850 */   GIM_Try, /*On fail goto*//*Label 6303*/ GIMT_Encode4(418898), // Rule ID 14247 //
     /*  418855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  418858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  418874 */     // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  418874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  418877 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418896 */     GIR_RootConstrainSelectedInstOperands,
     /*  418897 */     // GIR_Coverage, 14247,
     /*  418897 */     GIR_EraseRootFromParent_Done,
     /*  418898 */   // Label 6303: @418898
     /*  418898 */   GIM_Try, /*On fail goto*//*Label 6304*/ GIMT_Encode4(418946), // Rule ID 14248 //
     /*  418903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  418906 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  418922 */     // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  418922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  418925 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418944 */     GIR_RootConstrainSelectedInstOperands,
     /*  418945 */     // GIR_Coverage, 14248,
     /*  418945 */     GIR_EraseRootFromParent_Done,
     /*  418946 */   // Label 6304: @418946
     /*  418946 */   GIM_Try, /*On fail goto*//*Label 6305*/ GIMT_Encode4(418994), // Rule ID 14249 //
     /*  418951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  418954 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  418959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  418963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  418970 */     // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  418970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  418973 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  418975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  418980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  418985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  418988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  418992 */     GIR_RootConstrainSelectedInstOperands,
     /*  418993 */     // GIR_Coverage, 14249,
     /*  418993 */     GIR_EraseRootFromParent_Done,
     /*  418994 */   // Label 6305: @418994
     /*  418994 */   GIM_Try, /*On fail goto*//*Label 6306*/ GIMT_Encode4(419042), // Rule ID 14250 //
     /*  418999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  419002 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  419018 */     // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  419018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  419021 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  419023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  419028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  419033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419040 */     GIR_RootConstrainSelectedInstOperands,
     /*  419041 */     // GIR_Coverage, 14250,
     /*  419041 */     GIR_EraseRootFromParent_Done,
     /*  419042 */   // Label 6306: @419042
     /*  419042 */   GIM_Try, /*On fail goto*//*Label 6307*/ GIMT_Encode4(419090), // Rule ID 14251 //
     /*  419047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  419050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  419066 */     // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  419066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  419069 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  419071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  419076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  419081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419088 */     GIR_RootConstrainSelectedInstOperands,
     /*  419089 */     // GIR_Coverage, 14251,
     /*  419089 */     GIR_EraseRootFromParent_Done,
     /*  419090 */   // Label 6307: @419090
     /*  419090 */   GIM_Try, /*On fail goto*//*Label 6308*/ GIMT_Encode4(419153), // Rule ID 16018 //
     /*  419095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  419098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419116 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  419119 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419151 */     GIR_RootConstrainSelectedInstOperands,
     /*  419152 */     // GIR_Coverage, 16018,
     /*  419152 */     GIR_EraseRootFromParent_Done,
     /*  419153 */   // Label 6308: @419153
     /*  419153 */   GIM_Try, /*On fail goto*//*Label 6309*/ GIMT_Encode4(419216), // Rule ID 16019 //
     /*  419158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  419161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419179 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  419182 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419214 */     GIR_RootConstrainSelectedInstOperands,
     /*  419215 */     // GIR_Coverage, 16019,
     /*  419215 */     GIR_EraseRootFromParent_Done,
     /*  419216 */   // Label 6309: @419216
     /*  419216 */   GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(419279), // Rule ID 16020 //
     /*  419221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  419224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419242 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  419245 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419277 */     GIR_RootConstrainSelectedInstOperands,
     /*  419278 */     // GIR_Coverage, 16020,
     /*  419278 */     GIR_EraseRootFromParent_Done,
     /*  419279 */   // Label 6310: @419279
     /*  419279 */   GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(419342), // Rule ID 16021 //
     /*  419284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  419287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419305 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  419308 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419340 */     GIR_RootConstrainSelectedInstOperands,
     /*  419341 */     // GIR_Coverage, 16021,
     /*  419341 */     GIR_EraseRootFromParent_Done,
     /*  419342 */   // Label 6311: @419342
     /*  419342 */   GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(419405), // Rule ID 16022 //
     /*  419347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  419350 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419368 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  419371 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419399 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419403 */     GIR_RootConstrainSelectedInstOperands,
     /*  419404 */     // GIR_Coverage, 16022,
     /*  419404 */     GIR_EraseRootFromParent_Done,
     /*  419405 */   // Label 6312: @419405
     /*  419405 */   GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(419468), // Rule ID 16028 //
     /*  419410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  419413 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419431 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  419434 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419466 */     GIR_RootConstrainSelectedInstOperands,
     /*  419467 */     // GIR_Coverage, 16028,
     /*  419467 */     GIR_EraseRootFromParent_Done,
     /*  419468 */   // Label 6313: @419468
     /*  419468 */   GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(419531), // Rule ID 16029 //
     /*  419473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  419476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419494 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  419497 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419529 */     GIR_RootConstrainSelectedInstOperands,
     /*  419530 */     // GIR_Coverage, 16029,
     /*  419530 */     GIR_EraseRootFromParent_Done,
     /*  419531 */   // Label 6314: @419531
     /*  419531 */   GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(419594), // Rule ID 16030 //
     /*  419536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  419539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419557 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  419560 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419592 */     GIR_RootConstrainSelectedInstOperands,
     /*  419593 */     // GIR_Coverage, 16030,
     /*  419593 */     GIR_EraseRootFromParent_Done,
     /*  419594 */   // Label 6315: @419594
     /*  419594 */   GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(419657), // Rule ID 16031 //
     /*  419599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  419602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419620 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  419623 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419655 */     GIR_RootConstrainSelectedInstOperands,
     /*  419656 */     // GIR_Coverage, 16031,
     /*  419656 */     GIR_EraseRootFromParent_Done,
     /*  419657 */   // Label 6316: @419657
     /*  419657 */   GIM_Try, /*On fail goto*//*Label 6317*/ GIMT_Encode4(419720), // Rule ID 16032 //
     /*  419662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  419665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  419672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  419683 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  419683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  419686 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  419688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419718 */     GIR_RootConstrainSelectedInstOperands,
     /*  419719 */     // GIR_Coverage, 16032,
     /*  419719 */     GIR_EraseRootFromParent_Done,
     /*  419720 */   // Label 6317: @419720
     /*  419720 */   GIM_Try, /*On fail goto*//*Label 6318*/ GIMT_Encode4(419781), // Rule ID 25901 //
     /*  419725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  419728 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  419744 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  419744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  419747 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  419749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419779 */     GIR_RootConstrainSelectedInstOperands,
     /*  419780 */     // GIR_Coverage, 25901,
     /*  419780 */     GIR_EraseRootFromParent_Done,
     /*  419781 */   // Label 6318: @419781
     /*  419781 */   GIM_Try, /*On fail goto*//*Label 6319*/ GIMT_Encode4(419842), // Rule ID 25902 //
     /*  419786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  419789 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419794 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419798 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  419805 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  419805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  419808 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  419810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419840 */     GIR_RootConstrainSelectedInstOperands,
     /*  419841 */     // GIR_Coverage, 25902,
     /*  419841 */     GIR_EraseRootFromParent_Done,
     /*  419842 */   // Label 6319: @419842
     /*  419842 */   GIM_Try, /*On fail goto*//*Label 6320*/ GIMT_Encode4(419903), // Rule ID 25903 //
     /*  419847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  419850 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  419866 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  419866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  419869 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  419871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419901 */     GIR_RootConstrainSelectedInstOperands,
     /*  419902 */     // GIR_Coverage, 25903,
     /*  419902 */     GIR_EraseRootFromParent_Done,
     /*  419903 */   // Label 6320: @419903
     /*  419903 */   GIM_Try, /*On fail goto*//*Label 6321*/ GIMT_Encode4(419964), // Rule ID 25904 //
     /*  419908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  419911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  419927 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  419927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  419930 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  419932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  419942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  419947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  419952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  419958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  419962 */     GIR_RootConstrainSelectedInstOperands,
     /*  419963 */     // GIR_Coverage, 25904,
     /*  419963 */     GIR_EraseRootFromParent_Done,
     /*  419964 */   // Label 6321: @419964
     /*  419964 */   GIM_Try, /*On fail goto*//*Label 6322*/ GIMT_Encode4(420025), // Rule ID 25905 //
     /*  419969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  419972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  419977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  419981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  419988 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  419988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  419991 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  419993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  419998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  420008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  420013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420023 */     GIR_RootConstrainSelectedInstOperands,
     /*  420024 */     // GIR_Coverage, 25905,
     /*  420024 */     GIR_EraseRootFromParent_Done,
     /*  420025 */   // Label 6322: @420025
     /*  420025 */   GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(420086), // Rule ID 25911 //
     /*  420030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  420033 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  420038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  420049 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  420049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  420052 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  420054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  420059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  420069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  420074 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420084 */     GIR_RootConstrainSelectedInstOperands,
     /*  420085 */     // GIR_Coverage, 25911,
     /*  420085 */     GIR_EraseRootFromParent_Done,
     /*  420086 */   // Label 6323: @420086
     /*  420086 */   GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(420147), // Rule ID 25912 //
     /*  420091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  420094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  420099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  420110 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  420110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  420113 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  420115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  420120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  420130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  420135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420145 */     GIR_RootConstrainSelectedInstOperands,
     /*  420146 */     // GIR_Coverage, 25912,
     /*  420146 */     GIR_EraseRootFromParent_Done,
     /*  420147 */   // Label 6324: @420147
     /*  420147 */   GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(420208), // Rule ID 25913 //
     /*  420152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  420155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  420160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  420171 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  420171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  420174 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  420176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  420181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  420191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  420196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420206 */     GIR_RootConstrainSelectedInstOperands,
     /*  420207 */     // GIR_Coverage, 25913,
     /*  420207 */     GIR_EraseRootFromParent_Done,
     /*  420208 */   // Label 6325: @420208
     /*  420208 */   GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(420269), // Rule ID 25914 //
     /*  420213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  420216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  420221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  420232 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  420232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  420235 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  420237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  420242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  420252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  420257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420263 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420267 */     GIR_RootConstrainSelectedInstOperands,
     /*  420268 */     // GIR_Coverage, 25914,
     /*  420268 */     GIR_EraseRootFromParent_Done,
     /*  420269 */   // Label 6326: @420269
     /*  420269 */   GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(420330), // Rule ID 25915 //
     /*  420274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  420277 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  420282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  420293 */     // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  420293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  420296 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  420298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  420303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  420313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  420318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420328 */     GIR_RootConstrainSelectedInstOperands,
     /*  420329 */     // GIR_Coverage, 25915,
     /*  420329 */     GIR_EraseRootFromParent_Done,
     /*  420330 */   // Label 6327: @420330
     /*  420330 */   GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(420388), // Rule ID 16013 //
     /*  420335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  420338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420356 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  420359 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420386 */     GIR_RootConstrainSelectedInstOperands,
     /*  420387 */     // GIR_Coverage, 16013,
     /*  420387 */     GIR_EraseRootFromParent_Done,
     /*  420388 */   // Label 6328: @420388
     /*  420388 */   GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(420446), // Rule ID 16014 //
     /*  420393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  420396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420414 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  420417 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420444 */     GIR_RootConstrainSelectedInstOperands,
     /*  420445 */     // GIR_Coverage, 16014,
     /*  420445 */     GIR_EraseRootFromParent_Done,
     /*  420446 */   // Label 6329: @420446
     /*  420446 */   GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(420504), // Rule ID 16015 //
     /*  420451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  420454 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420472 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  420475 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420502 */     GIR_RootConstrainSelectedInstOperands,
     /*  420503 */     // GIR_Coverage, 16015,
     /*  420503 */     GIR_EraseRootFromParent_Done,
     /*  420504 */   // Label 6330: @420504
     /*  420504 */   GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(420562), // Rule ID 16016 //
     /*  420509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  420512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420530 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  420533 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420560 */     GIR_RootConstrainSelectedInstOperands,
     /*  420561 */     // GIR_Coverage, 16016,
     /*  420561 */     GIR_EraseRootFromParent_Done,
     /*  420562 */   // Label 6331: @420562
     /*  420562 */   GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(420620), // Rule ID 16017 //
     /*  420567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  420570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420588 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  420591 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420618 */     GIR_RootConstrainSelectedInstOperands,
     /*  420619 */     // GIR_Coverage, 16017,
     /*  420619 */     GIR_EraseRootFromParent_Done,
     /*  420620 */   // Label 6332: @420620
     /*  420620 */   GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(420678), // Rule ID 16023 //
     /*  420625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  420628 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420646 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  420649 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420676 */     GIR_RootConstrainSelectedInstOperands,
     /*  420677 */     // GIR_Coverage, 16023,
     /*  420677 */     GIR_EraseRootFromParent_Done,
     /*  420678 */   // Label 6333: @420678
     /*  420678 */   GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(420736), // Rule ID 16024 //
     /*  420683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  420686 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420704 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  420707 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420734 */     GIR_RootConstrainSelectedInstOperands,
     /*  420735 */     // GIR_Coverage, 16024,
     /*  420735 */     GIR_EraseRootFromParent_Done,
     /*  420736 */   // Label 6334: @420736
     /*  420736 */   GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(420794), // Rule ID 16025 //
     /*  420741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  420744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420762 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  420765 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420792 */     GIR_RootConstrainSelectedInstOperands,
     /*  420793 */     // GIR_Coverage, 16025,
     /*  420793 */     GIR_EraseRootFromParent_Done,
     /*  420794 */   // Label 6335: @420794
     /*  420794 */   GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(420852), // Rule ID 16026 //
     /*  420799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  420802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420820 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  420823 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420850 */     GIR_RootConstrainSelectedInstOperands,
     /*  420851 */     // GIR_Coverage, 16026,
     /*  420851 */     GIR_EraseRootFromParent_Done,
     /*  420852 */   // Label 6336: @420852
     /*  420852 */   GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(420910), // Rule ID 16027 //
     /*  420857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  420860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  420867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  420878 */     // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  420878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  420881 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  420883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  420888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  420893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  420898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420908 */     GIR_RootConstrainSelectedInstOperands,
     /*  420909 */     // GIR_Coverage, 16027,
     /*  420909 */     GIR_EraseRootFromParent_Done,
     /*  420910 */   // Label 6337: @420910
     /*  420910 */   GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(420962), // Rule ID 29283 //
     /*  420915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  420918 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  420922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  420927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  420938 */     // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  420938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  420941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  420946 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  420948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  420953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  420956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  420960 */     GIR_RootConstrainSelectedInstOperands,
     /*  420961 */     // GIR_Coverage, 29283,
     /*  420961 */     GIR_EraseRootFromParent_Done,
     /*  420962 */   // Label 6338: @420962
     /*  420962 */   GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(421014), // Rule ID 29284 //
     /*  420967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  420970 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  420974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  420979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  420983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  420990 */     // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  420990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  420993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  420998 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421012 */     GIR_RootConstrainSelectedInstOperands,
     /*  421013 */     // GIR_Coverage, 29284,
     /*  421013 */     GIR_EraseRootFromParent_Done,
     /*  421014 */   // Label 6339: @421014
     /*  421014 */   GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(421066), // Rule ID 29285 //
     /*  421019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  421022 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  421026 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421042 */     // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  421045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421050 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421060 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421064 */     GIR_RootConstrainSelectedInstOperands,
     /*  421065 */     // GIR_Coverage, 29285,
     /*  421065 */     GIR_EraseRootFromParent_Done,
     /*  421066 */   // Label 6340: @421066
     /*  421066 */   GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(421118), // Rule ID 29286 //
     /*  421071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  421074 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  421078 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421094 */     // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  421097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421102 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421112 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421116 */     GIR_RootConstrainSelectedInstOperands,
     /*  421117 */     // GIR_Coverage, 29286,
     /*  421117 */     GIR_EraseRootFromParent_Done,
     /*  421118 */   // Label 6341: @421118
     /*  421118 */   GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(421170), // Rule ID 29287 //
     /*  421123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  421126 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  421130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421146 */     // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  421149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421154 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421164 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421168 */     GIR_RootConstrainSelectedInstOperands,
     /*  421169 */     // GIR_Coverage, 29287,
     /*  421169 */     GIR_EraseRootFromParent_Done,
     /*  421170 */   // Label 6342: @421170
     /*  421170 */   GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(421218), // Rule ID 29288 //
     /*  421175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  421178 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421194 */     // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  421197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421202 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421209 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421216 */     GIR_RootConstrainSelectedInstOperands,
     /*  421217 */     // GIR_Coverage, 29288,
     /*  421217 */     GIR_EraseRootFromParent_Done,
     /*  421218 */   // Label 6343: @421218
     /*  421218 */   GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(421266), // Rule ID 29289 //
     /*  421223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  421226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421242 */     // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  421245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421250 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421264 */     GIR_RootConstrainSelectedInstOperands,
     /*  421265 */     // GIR_Coverage, 29289,
     /*  421265 */     GIR_EraseRootFromParent_Done,
     /*  421266 */   // Label 6344: @421266
     /*  421266 */   GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(421314), // Rule ID 29290 //
     /*  421271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  421274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421279 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421290 */     // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  421293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421298 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421312 */     GIR_RootConstrainSelectedInstOperands,
     /*  421313 */     // GIR_Coverage, 29290,
     /*  421313 */     GIR_EraseRootFromParent_Done,
     /*  421314 */   // Label 6345: @421314
     /*  421314 */   GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(421362), // Rule ID 29291 //
     /*  421319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  421322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421338 */     // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  421341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421346 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421360 */     GIR_RootConstrainSelectedInstOperands,
     /*  421361 */     // GIR_Coverage, 29291,
     /*  421361 */     GIR_EraseRootFromParent_Done,
     /*  421362 */   // Label 6346: @421362
     /*  421362 */   GIM_Try, /*On fail goto*//*Label 6347*/ GIMT_Encode4(421410), // Rule ID 29292 //
     /*  421367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  421370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  421375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  421386 */     // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  421386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  421389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  421394 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  421396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421408 */     GIR_RootConstrainSelectedInstOperands,
     /*  421409 */     // GIR_Coverage, 29292,
     /*  421409 */     GIR_EraseRootFromParent_Done,
     /*  421410 */   // Label 6347: @421410
     /*  421410 */   GIM_Try, /*On fail goto*//*Label 6348*/ GIMT_Encode4(421467), // Rule ID 12233 //
     /*  421415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  421418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  421436 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  421436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  421439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  421444 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  421451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  421456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  421461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421465 */     GIR_RootConstrainSelectedInstOperands,
     /*  421466 */     // GIR_Coverage, 12233,
     /*  421466 */     GIR_EraseRootFromParent_Done,
     /*  421467 */   // Label 6348: @421467
     /*  421467 */   GIM_Try, /*On fail goto*//*Label 6349*/ GIMT_Encode4(421524), // Rule ID 12234 //
     /*  421472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  421475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  421493 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  421493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  421496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  421501 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  421508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  421513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  421518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421522 */     GIR_RootConstrainSelectedInstOperands,
     /*  421523 */     // GIR_Coverage, 12234,
     /*  421523 */     GIR_EraseRootFromParent_Done,
     /*  421524 */   // Label 6349: @421524
     /*  421524 */   GIM_Try, /*On fail goto*//*Label 6350*/ GIMT_Encode4(421581), // Rule ID 12235 //
     /*  421529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  421532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  421550 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  421550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  421553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  421558 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  421565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  421570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  421575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421579 */     GIR_RootConstrainSelectedInstOperands,
     /*  421580 */     // GIR_Coverage, 12235,
     /*  421580 */     GIR_EraseRootFromParent_Done,
     /*  421581 */   // Label 6350: @421581
     /*  421581 */   GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(421638), // Rule ID 12236 //
     /*  421586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  421589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  421607 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  421607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  421610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  421615 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  421622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  421627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  421632 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421636 */     GIR_RootConstrainSelectedInstOperands,
     /*  421637 */     // GIR_Coverage, 12236,
     /*  421637 */     GIR_EraseRootFromParent_Done,
     /*  421638 */   // Label 6351: @421638
     /*  421638 */   GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(421695), // Rule ID 12237 //
     /*  421643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  421646 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  421664 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  421664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  421667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  421672 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  421679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  421684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  421689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421693 */     GIR_RootConstrainSelectedInstOperands,
     /*  421694 */     // GIR_Coverage, 12237,
     /*  421694 */     GIR_EraseRootFromParent_Done,
     /*  421695 */   // Label 6352: @421695
     /*  421695 */   GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(421745), // Rule ID 12228 //
     /*  421700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  421703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  421721 */     // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  421721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  421724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  421729 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421743 */     GIR_RootConstrainSelectedInstOperands,
     /*  421744 */     // GIR_Coverage, 12228,
     /*  421744 */     GIR_EraseRootFromParent_Done,
     /*  421745 */   // Label 6353: @421745
     /*  421745 */   GIM_Try, /*On fail goto*//*Label 6354*/ GIMT_Encode4(421795), // Rule ID 12229 //
     /*  421750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  421753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  421771 */     // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  421771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  421774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  421779 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421793 */     GIR_RootConstrainSelectedInstOperands,
     /*  421794 */     // GIR_Coverage, 12229,
     /*  421794 */     GIR_EraseRootFromParent_Done,
     /*  421795 */   // Label 6354: @421795
     /*  421795 */   GIM_Try, /*On fail goto*//*Label 6355*/ GIMT_Encode4(421845), // Rule ID 12230 //
     /*  421800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  421803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  421821 */     // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  421821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  421824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  421829 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421843 */     GIR_RootConstrainSelectedInstOperands,
     /*  421844 */     // GIR_Coverage, 12230,
     /*  421844 */     GIR_EraseRootFromParent_Done,
     /*  421845 */   // Label 6355: @421845
     /*  421845 */   GIM_Try, /*On fail goto*//*Label 6356*/ GIMT_Encode4(421895), // Rule ID 12231 //
     /*  421850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  421853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421860 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  421871 */     // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  421871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  421874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  421879 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421889 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421893 */     GIR_RootConstrainSelectedInstOperands,
     /*  421894 */     // GIR_Coverage, 12231,
     /*  421894 */     GIR_EraseRootFromParent_Done,
     /*  421895 */   // Label 6356: @421895
     /*  421895 */   GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(421945), // Rule ID 12232 //
     /*  421900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  421903 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  421910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  421921 */     // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  421921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  421924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  421929 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  421936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  421939 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421943 */     GIR_RootConstrainSelectedInstOperands,
     /*  421944 */     // GIR_Coverage, 12232,
     /*  421944 */     GIR_EraseRootFromParent_Done,
     /*  421945 */   // Label 6357: @421945
     /*  421945 */   GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(422001), // Rule ID 10091 //
     /*  421950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  421953 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  421959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  421963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  421970 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  421970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  421973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  421978 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  421980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  421985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  421990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  421995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  421999 */     GIR_RootConstrainSelectedInstOperands,
     /*  422000 */     // GIR_Coverage, 10091,
     /*  422000 */     GIR_EraseRootFromParent_Done,
     /*  422001 */   // Label 6358: @422001
     /*  422001 */   GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(422057), // Rule ID 10092 //
     /*  422006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  422009 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  422026 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  422026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  422029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  422034 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  422041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  422051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422055 */     GIR_RootConstrainSelectedInstOperands,
     /*  422056 */     // GIR_Coverage, 10092,
     /*  422056 */     GIR_EraseRootFromParent_Done,
     /*  422057 */   // Label 6359: @422057
     /*  422057 */   GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(422113), // Rule ID 10093 //
     /*  422062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  422065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  422082 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  422082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  422085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  422090 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  422097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  422107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422111 */     GIR_RootConstrainSelectedInstOperands,
     /*  422112 */     // GIR_Coverage, 10093,
     /*  422112 */     GIR_EraseRootFromParent_Done,
     /*  422113 */   // Label 6360: @422113
     /*  422113 */   GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(422169), // Rule ID 10094 //
     /*  422118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  422121 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  422138 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  422138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  422141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  422146 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  422153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  422163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422167 */     GIR_RootConstrainSelectedInstOperands,
     /*  422168 */     // GIR_Coverage, 10094,
     /*  422168 */     GIR_EraseRootFromParent_Done,
     /*  422169 */   // Label 6361: @422169
     /*  422169 */   GIM_Try, /*On fail goto*//*Label 6362*/ GIMT_Encode4(422225), // Rule ID 10095 //
     /*  422174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  422177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  422194 */     // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  422194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  422197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  422202 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  422209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  422219 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422223 */     GIR_RootConstrainSelectedInstOperands,
     /*  422224 */     // GIR_Coverage, 10095,
     /*  422224 */     GIR_EraseRootFromParent_Done,
     /*  422225 */   // Label 6362: @422225
     /*  422225 */   GIM_Try, /*On fail goto*//*Label 6363*/ GIMT_Encode4(422274), // Rule ID 10086 //
     /*  422230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  422233 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422239 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  422250 */     // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  422250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  422253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  422258 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  422265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422272 */     GIR_RootConstrainSelectedInstOperands,
     /*  422273 */     // GIR_Coverage, 10086,
     /*  422273 */     GIR_EraseRootFromParent_Done,
     /*  422274 */   // Label 6363: @422274
     /*  422274 */   GIM_Try, /*On fail goto*//*Label 6364*/ GIMT_Encode4(422323), // Rule ID 10087 //
     /*  422279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  422282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  422299 */     // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  422299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  422302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  422307 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  422314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422321 */     GIR_RootConstrainSelectedInstOperands,
     /*  422322 */     // GIR_Coverage, 10087,
     /*  422322 */     GIR_EraseRootFromParent_Done,
     /*  422323 */   // Label 6364: @422323
     /*  422323 */   GIM_Try, /*On fail goto*//*Label 6365*/ GIMT_Encode4(422372), // Rule ID 10088 //
     /*  422328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  422331 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  422348 */     // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  422348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  422351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  422356 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  422363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422370 */     GIR_RootConstrainSelectedInstOperands,
     /*  422371 */     // GIR_Coverage, 10088,
     /*  422371 */     GIR_EraseRootFromParent_Done,
     /*  422372 */   // Label 6365: @422372
     /*  422372 */   GIM_Try, /*On fail goto*//*Label 6366*/ GIMT_Encode4(422421), // Rule ID 10089 //
     /*  422377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  422380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  422397 */     // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  422397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  422400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  422405 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  422412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422419 */     GIR_RootConstrainSelectedInstOperands,
     /*  422420 */     // GIR_Coverage, 10089,
     /*  422420 */     GIR_EraseRootFromParent_Done,
     /*  422421 */   // Label 6366: @422421
     /*  422421 */   GIM_Try, /*On fail goto*//*Label 6367*/ GIMT_Encode4(422470), // Rule ID 10090 //
     /*  422426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  422429 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  422435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  422446 */     // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  422446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  422449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  422454 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  422456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  422461 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422464 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422468 */     GIR_RootConstrainSelectedInstOperands,
     /*  422469 */     // GIR_Coverage, 10090,
     /*  422469 */     GIR_EraseRootFromParent_Done,
     /*  422470 */   // Label 6367: @422470
     /*  422470 */   GIM_Reject,
     /*  422471 */ // Label 6282: @422471
     /*  422471 */ GIM_Reject,
     /*  422472 */ // Label 5864: @422472
     /*  422472 */ GIM_Try, /*On fail goto*//*Label 6368*/ GIMT_Encode4(427176),
     /*  422477 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  422480 */   GIM_Try, /*On fail goto*//*Label 6369*/ GIMT_Encode4(422536), // Rule ID 25926 //
     /*  422485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  422488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422504 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  422507 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422534 */     GIR_RootConstrainSelectedInstOperands,
     /*  422535 */     // GIR_Coverage, 25926,
     /*  422535 */     GIR_EraseRootFromParent_Done,
     /*  422536 */   // Label 6369: @422536
     /*  422536 */   GIM_Try, /*On fail goto*//*Label 6370*/ GIMT_Encode4(422592), // Rule ID 25927 //
     /*  422541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  422544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422560 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  422563 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422590 */     GIR_RootConstrainSelectedInstOperands,
     /*  422591 */     // GIR_Coverage, 25927,
     /*  422591 */     GIR_EraseRootFromParent_Done,
     /*  422592 */   // Label 6370: @422592
     /*  422592 */   GIM_Try, /*On fail goto*//*Label 6371*/ GIMT_Encode4(422648), // Rule ID 25928 //
     /*  422597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  422600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422616 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  422619 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422646 */     GIR_RootConstrainSelectedInstOperands,
     /*  422647 */     // GIR_Coverage, 25928,
     /*  422647 */     GIR_EraseRootFromParent_Done,
     /*  422648 */   // Label 6371: @422648
     /*  422648 */   GIM_Try, /*On fail goto*//*Label 6372*/ GIMT_Encode4(422704), // Rule ID 25929 //
     /*  422653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  422656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422672 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  422675 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422702 */     GIR_RootConstrainSelectedInstOperands,
     /*  422703 */     // GIR_Coverage, 25929,
     /*  422703 */     GIR_EraseRootFromParent_Done,
     /*  422704 */   // Label 6372: @422704
     /*  422704 */   GIM_Try, /*On fail goto*//*Label 6373*/ GIMT_Encode4(422760), // Rule ID 25930 //
     /*  422709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  422712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422728 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  422731 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422758 */     GIR_RootConstrainSelectedInstOperands,
     /*  422759 */     // GIR_Coverage, 25930,
     /*  422759 */     GIR_EraseRootFromParent_Done,
     /*  422760 */   // Label 6373: @422760
     /*  422760 */   GIM_Try, /*On fail goto*//*Label 6374*/ GIMT_Encode4(422816), // Rule ID 25936 //
     /*  422765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  422768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422784 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  422787 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422814 */     GIR_RootConstrainSelectedInstOperands,
     /*  422815 */     // GIR_Coverage, 25936,
     /*  422815 */     GIR_EraseRootFromParent_Done,
     /*  422816 */   // Label 6374: @422816
     /*  422816 */   GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(422872), // Rule ID 25937 //
     /*  422821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  422824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422840 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  422843 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422870 */     GIR_RootConstrainSelectedInstOperands,
     /*  422871 */     // GIR_Coverage, 25937,
     /*  422871 */     GIR_EraseRootFromParent_Done,
     /*  422872 */   // Label 6375: @422872
     /*  422872 */   GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(422928), // Rule ID 25938 //
     /*  422877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  422880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422896 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  422899 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422926 */     GIR_RootConstrainSelectedInstOperands,
     /*  422927 */     // GIR_Coverage, 25938,
     /*  422927 */     GIR_EraseRootFromParent_Done,
     /*  422928 */   // Label 6376: @422928
     /*  422928 */   GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(422984), // Rule ID 25939 //
     /*  422933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  422936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  422945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  422952 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  422952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  422955 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  422957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  422962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  422967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  422972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  422978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  422982 */     GIR_RootConstrainSelectedInstOperands,
     /*  422983 */     // GIR_Coverage, 25939,
     /*  422983 */     GIR_EraseRootFromParent_Done,
     /*  422984 */   // Label 6377: @422984
     /*  422984 */   GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(423040), // Rule ID 25940 //
     /*  422989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  422992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  422997 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  423008 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  423008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  423011 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  423013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  423018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  423023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  423028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423038 */     GIR_RootConstrainSelectedInstOperands,
     /*  423039 */     // GIR_Coverage, 25940,
     /*  423039 */     GIR_EraseRootFromParent_Done,
     /*  423040 */   // Label 6378: @423040
     /*  423040 */   GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(423095), // Rule ID 14287 //
     /*  423045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  423048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  423064 */     // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  423064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  423067 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  423079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  423084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  423089 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423093 */     GIR_RootConstrainSelectedInstOperands,
     /*  423094 */     // GIR_Coverage, 14287,
     /*  423094 */     GIR_EraseRootFromParent_Done,
     /*  423095 */   // Label 6379: @423095
     /*  423095 */   GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(423150), // Rule ID 14288 //
     /*  423100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  423103 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  423119 */     // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  423119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  423122 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  423134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  423139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  423144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423148 */     GIR_RootConstrainSelectedInstOperands,
     /*  423149 */     // GIR_Coverage, 14288,
     /*  423149 */     GIR_EraseRootFromParent_Done,
     /*  423150 */   // Label 6380: @423150
     /*  423150 */   GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(423205), // Rule ID 14289 //
     /*  423155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  423158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  423174 */     // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  423174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  423177 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  423189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  423194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  423199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423203 */     GIR_RootConstrainSelectedInstOperands,
     /*  423204 */     // GIR_Coverage, 14289,
     /*  423204 */     GIR_EraseRootFromParent_Done,
     /*  423205 */   // Label 6381: @423205
     /*  423205 */   GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(423260), // Rule ID 14290 //
     /*  423210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  423213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  423229 */     // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  423229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  423232 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  423244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  423249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  423254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423258 */     GIR_RootConstrainSelectedInstOperands,
     /*  423259 */     // GIR_Coverage, 14290,
     /*  423259 */     GIR_EraseRootFromParent_Done,
     /*  423260 */   // Label 6382: @423260
     /*  423260 */   GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(423315), // Rule ID 14291 //
     /*  423265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  423268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  423284 */     // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  423284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  423287 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  423299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  423304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  423309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423313 */     GIR_RootConstrainSelectedInstOperands,
     /*  423314 */     // GIR_Coverage, 14291,
     /*  423314 */     GIR_EraseRootFromParent_Done,
     /*  423315 */   // Label 6383: @423315
     /*  423315 */   GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(423363), // Rule ID 14282 //
     /*  423320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  423323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  423339 */     // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  423339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  423342 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  423349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423361 */     GIR_RootConstrainSelectedInstOperands,
     /*  423362 */     // GIR_Coverage, 14282,
     /*  423362 */     GIR_EraseRootFromParent_Done,
     /*  423363 */   // Label 6384: @423363
     /*  423363 */   GIM_Try, /*On fail goto*//*Label 6385*/ GIMT_Encode4(423411), // Rule ID 14283 //
     /*  423368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  423371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  423387 */     // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  423387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  423390 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  423397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423409 */     GIR_RootConstrainSelectedInstOperands,
     /*  423410 */     // GIR_Coverage, 14283,
     /*  423410 */     GIR_EraseRootFromParent_Done,
     /*  423411 */   // Label 6385: @423411
     /*  423411 */   GIM_Try, /*On fail goto*//*Label 6386*/ GIMT_Encode4(423459), // Rule ID 14284 //
     /*  423416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  423419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423424 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  423435 */     // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  423435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  423438 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  423445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423457 */     GIR_RootConstrainSelectedInstOperands,
     /*  423458 */     // GIR_Coverage, 14284,
     /*  423458 */     GIR_EraseRootFromParent_Done,
     /*  423459 */   // Label 6386: @423459
     /*  423459 */   GIM_Try, /*On fail goto*//*Label 6387*/ GIMT_Encode4(423507), // Rule ID 14285 //
     /*  423464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  423467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423472 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423476 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  423483 */     // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  423483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  423486 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  423493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423505 */     GIR_RootConstrainSelectedInstOperands,
     /*  423506 */     // GIR_Coverage, 14285,
     /*  423506 */     GIR_EraseRootFromParent_Done,
     /*  423507 */   // Label 6387: @423507
     /*  423507 */   GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(423555), // Rule ID 14286 //
     /*  423512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  423515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  423531 */     // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  423531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  423534 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  423541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423553 */     GIR_RootConstrainSelectedInstOperands,
     /*  423554 */     // GIR_Coverage, 14286,
     /*  423554 */     GIR_EraseRootFromParent_Done,
     /*  423555 */   // Label 6388: @423555
     /*  423555 */   GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(423603), // Rule ID 14277 //
     /*  423560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  423563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  423579 */     // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  423579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  423582 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423601 */     GIR_RootConstrainSelectedInstOperands,
     /*  423602 */     // GIR_Coverage, 14277,
     /*  423602 */     GIR_EraseRootFromParent_Done,
     /*  423603 */   // Label 6389: @423603
     /*  423603 */   GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(423651), // Rule ID 14278 //
     /*  423608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  423611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  423627 */     // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  423627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  423630 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423645 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423649 */     GIR_RootConstrainSelectedInstOperands,
     /*  423650 */     // GIR_Coverage, 14278,
     /*  423650 */     GIR_EraseRootFromParent_Done,
     /*  423651 */   // Label 6390: @423651
     /*  423651 */   GIM_Try, /*On fail goto*//*Label 6391*/ GIMT_Encode4(423699), // Rule ID 14279 //
     /*  423656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  423659 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  423675 */     // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  423675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  423678 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423697 */     GIR_RootConstrainSelectedInstOperands,
     /*  423698 */     // GIR_Coverage, 14279,
     /*  423698 */     GIR_EraseRootFromParent_Done,
     /*  423699 */   // Label 6391: @423699
     /*  423699 */   GIM_Try, /*On fail goto*//*Label 6392*/ GIMT_Encode4(423747), // Rule ID 14280 //
     /*  423704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  423707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  423723 */     // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  423723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  423726 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423745 */     GIR_RootConstrainSelectedInstOperands,
     /*  423746 */     // GIR_Coverage, 14280,
     /*  423746 */     GIR_EraseRootFromParent_Done,
     /*  423747 */   // Label 6392: @423747
     /*  423747 */   GIM_Try, /*On fail goto*//*Label 6393*/ GIMT_Encode4(423795), // Rule ID 14281 //
     /*  423752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  423755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  423760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  423771 */     // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  423771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  423774 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  423776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  423781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  423786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423793 */     GIR_RootConstrainSelectedInstOperands,
     /*  423794 */     // GIR_Coverage, 14281,
     /*  423794 */     GIR_EraseRootFromParent_Done,
     /*  423795 */   // Label 6393: @423795
     /*  423795 */   GIM_Try, /*On fail goto*//*Label 6394*/ GIMT_Encode4(423858), // Rule ID 16038 //
     /*  423800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  423803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  423810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  423821 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  423821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  423824 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  423826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  423831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  423836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  423841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  423846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423856 */     GIR_RootConstrainSelectedInstOperands,
     /*  423857 */     // GIR_Coverage, 16038,
     /*  423857 */     GIR_EraseRootFromParent_Done,
     /*  423858 */   // Label 6394: @423858
     /*  423858 */   GIM_Try, /*On fail goto*//*Label 6395*/ GIMT_Encode4(423921), // Rule ID 16039 //
     /*  423863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  423866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  423873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  423884 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  423884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  423887 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  423889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  423894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  423899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  423904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  423909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423912 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423915 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423919 */     GIR_RootConstrainSelectedInstOperands,
     /*  423920 */     // GIR_Coverage, 16039,
     /*  423920 */     GIR_EraseRootFromParent_Done,
     /*  423921 */   // Label 6395: @423921
     /*  423921 */   GIM_Try, /*On fail goto*//*Label 6396*/ GIMT_Encode4(423984), // Rule ID 16040 //
     /*  423926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  423929 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  423936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  423940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  423947 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  423947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  423950 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  423952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  423957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  423962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  423967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  423972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  423978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  423982 */     GIR_RootConstrainSelectedInstOperands,
     /*  423983 */     // GIR_Coverage, 16040,
     /*  423983 */     GIR_EraseRootFromParent_Done,
     /*  423984 */   // Label 6396: @423984
     /*  423984 */   GIM_Try, /*On fail goto*//*Label 6397*/ GIMT_Encode4(424047), // Rule ID 16041 //
     /*  423989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  423992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  423999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424010 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  424013 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424045 */     GIR_RootConstrainSelectedInstOperands,
     /*  424046 */     // GIR_Coverage, 16041,
     /*  424046 */     GIR_EraseRootFromParent_Done,
     /*  424047 */   // Label 6397: @424047
     /*  424047 */   GIM_Try, /*On fail goto*//*Label 6398*/ GIMT_Encode4(424110), // Rule ID 16042 //
     /*  424052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  424055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  424062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424073 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  424076 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424104 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424108 */     GIR_RootConstrainSelectedInstOperands,
     /*  424109 */     // GIR_Coverage, 16042,
     /*  424109 */     GIR_EraseRootFromParent_Done,
     /*  424110 */   // Label 6398: @424110
     /*  424110 */   GIM_Try, /*On fail goto*//*Label 6399*/ GIMT_Encode4(424173), // Rule ID 16048 //
     /*  424115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  424118 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  424125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424136 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  424139 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424171 */     GIR_RootConstrainSelectedInstOperands,
     /*  424172 */     // GIR_Coverage, 16048,
     /*  424172 */     GIR_EraseRootFromParent_Done,
     /*  424173 */   // Label 6399: @424173
     /*  424173 */   GIM_Try, /*On fail goto*//*Label 6400*/ GIMT_Encode4(424236), // Rule ID 16049 //
     /*  424178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  424181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  424188 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424192 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424199 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  424202 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424234 */     GIR_RootConstrainSelectedInstOperands,
     /*  424235 */     // GIR_Coverage, 16049,
     /*  424235 */     GIR_EraseRootFromParent_Done,
     /*  424236 */   // Label 6400: @424236
     /*  424236 */   GIM_Try, /*On fail goto*//*Label 6401*/ GIMT_Encode4(424299), // Rule ID 16050 //
     /*  424241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  424244 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  424251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424262 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  424265 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424293 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424297 */     GIR_RootConstrainSelectedInstOperands,
     /*  424298 */     // GIR_Coverage, 16050,
     /*  424298 */     GIR_EraseRootFromParent_Done,
     /*  424299 */   // Label 6401: @424299
     /*  424299 */   GIM_Try, /*On fail goto*//*Label 6402*/ GIMT_Encode4(424362), // Rule ID 16051 //
     /*  424304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  424307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  424314 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424318 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424325 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  424328 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424360 */     GIR_RootConstrainSelectedInstOperands,
     /*  424361 */     // GIR_Coverage, 16051,
     /*  424361 */     GIR_EraseRootFromParent_Done,
     /*  424362 */   // Label 6402: @424362
     /*  424362 */   GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(424425), // Rule ID 16052 //
     /*  424367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  424370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  424377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  424388 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  424388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  424391 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  424393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424423 */     GIR_RootConstrainSelectedInstOperands,
     /*  424424 */     // GIR_Coverage, 16052,
     /*  424424 */     GIR_EraseRootFromParent_Done,
     /*  424425 */   // Label 6403: @424425
     /*  424425 */   GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(424486), // Rule ID 25921 //
     /*  424430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  424433 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424449 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  424452 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424484 */     GIR_RootConstrainSelectedInstOperands,
     /*  424485 */     // GIR_Coverage, 25921,
     /*  424485 */     GIR_EraseRootFromParent_Done,
     /*  424486 */   // Label 6404: @424486
     /*  424486 */   GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(424547), // Rule ID 25922 //
     /*  424491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  424494 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424503 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424510 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  424513 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424545 */     GIR_RootConstrainSelectedInstOperands,
     /*  424546 */     // GIR_Coverage, 25922,
     /*  424546 */     GIR_EraseRootFromParent_Done,
     /*  424547 */   // Label 6405: @424547
     /*  424547 */   GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(424608), // Rule ID 25923 //
     /*  424552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  424555 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424571 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  424574 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424606 */     GIR_RootConstrainSelectedInstOperands,
     /*  424607 */     // GIR_Coverage, 25923,
     /*  424607 */     GIR_EraseRootFromParent_Done,
     /*  424608 */   // Label 6406: @424608
     /*  424608 */   GIM_Try, /*On fail goto*//*Label 6407*/ GIMT_Encode4(424669), // Rule ID 25924 //
     /*  424613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  424616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424632 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  424635 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424667 */     GIR_RootConstrainSelectedInstOperands,
     /*  424668 */     // GIR_Coverage, 25924,
     /*  424668 */     GIR_EraseRootFromParent_Done,
     /*  424669 */   // Label 6407: @424669
     /*  424669 */   GIM_Try, /*On fail goto*//*Label 6408*/ GIMT_Encode4(424730), // Rule ID 25925 //
     /*  424674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  424677 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424693 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  424696 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424728 */     GIR_RootConstrainSelectedInstOperands,
     /*  424729 */     // GIR_Coverage, 25925,
     /*  424729 */     GIR_EraseRootFromParent_Done,
     /*  424730 */   // Label 6408: @424730
     /*  424730 */   GIM_Try, /*On fail goto*//*Label 6409*/ GIMT_Encode4(424791), // Rule ID 25931 //
     /*  424735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  424738 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424754 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  424757 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424785 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424789 */     GIR_RootConstrainSelectedInstOperands,
     /*  424790 */     // GIR_Coverage, 25931,
     /*  424790 */     GIR_EraseRootFromParent_Done,
     /*  424791 */   // Label 6409: @424791
     /*  424791 */   GIM_Try, /*On fail goto*//*Label 6410*/ GIMT_Encode4(424852), // Rule ID 25932 //
     /*  424796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  424799 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424815 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  424818 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424850 */     GIR_RootConstrainSelectedInstOperands,
     /*  424851 */     // GIR_Coverage, 25932,
     /*  424851 */     GIR_EraseRootFromParent_Done,
     /*  424852 */   // Label 6410: @424852
     /*  424852 */   GIM_Try, /*On fail goto*//*Label 6411*/ GIMT_Encode4(424913), // Rule ID 25933 //
     /*  424857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  424860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424865 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424876 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  424879 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424911 */     GIR_RootConstrainSelectedInstOperands,
     /*  424912 */     // GIR_Coverage, 25933,
     /*  424912 */     GIR_EraseRootFromParent_Done,
     /*  424913 */   // Label 6411: @424913
     /*  424913 */   GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(424974), // Rule ID 25934 //
     /*  424918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  424921 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424937 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  424940 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  424942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  424947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  424952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  424957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  424962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  424968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  424972 */     GIR_RootConstrainSelectedInstOperands,
     /*  424973 */     // GIR_Coverage, 25934,
     /*  424973 */     GIR_EraseRootFromParent_Done,
     /*  424974 */   // Label 6412: @424974
     /*  424974 */   GIM_Try, /*On fail goto*//*Label 6413*/ GIMT_Encode4(425035), // Rule ID 25935 //
     /*  424979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  424982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  424987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  424991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  424998 */     // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  424998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  425001 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  425008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  425018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  425023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425033 */     GIR_RootConstrainSelectedInstOperands,
     /*  425034 */     // GIR_Coverage, 25935,
     /*  425034 */     GIR_EraseRootFromParent_Done,
     /*  425035 */   // Label 6413: @425035
     /*  425035 */   GIM_Try, /*On fail goto*//*Label 6414*/ GIMT_Encode4(425093), // Rule ID 16033 //
     /*  425040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  425043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425061 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  425064 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425084 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425087 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425091 */     GIR_RootConstrainSelectedInstOperands,
     /*  425092 */     // GIR_Coverage, 16033,
     /*  425092 */     GIR_EraseRootFromParent_Done,
     /*  425093 */   // Label 6414: @425093
     /*  425093 */   GIM_Try, /*On fail goto*//*Label 6415*/ GIMT_Encode4(425151), // Rule ID 16034 //
     /*  425098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  425101 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425119 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  425122 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425149 */     GIR_RootConstrainSelectedInstOperands,
     /*  425150 */     // GIR_Coverage, 16034,
     /*  425150 */     GIR_EraseRootFromParent_Done,
     /*  425151 */   // Label 6415: @425151
     /*  425151 */   GIM_Try, /*On fail goto*//*Label 6416*/ GIMT_Encode4(425209), // Rule ID 16035 //
     /*  425156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  425159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425177 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  425180 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425203 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425207 */     GIR_RootConstrainSelectedInstOperands,
     /*  425208 */     // GIR_Coverage, 16035,
     /*  425208 */     GIR_EraseRootFromParent_Done,
     /*  425209 */   // Label 6416: @425209
     /*  425209 */   GIM_Try, /*On fail goto*//*Label 6417*/ GIMT_Encode4(425267), // Rule ID 16036 //
     /*  425214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  425217 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425235 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  425238 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425265 */     GIR_RootConstrainSelectedInstOperands,
     /*  425266 */     // GIR_Coverage, 16036,
     /*  425266 */     GIR_EraseRootFromParent_Done,
     /*  425267 */   // Label 6417: @425267
     /*  425267 */   GIM_Try, /*On fail goto*//*Label 6418*/ GIMT_Encode4(425325), // Rule ID 16037 //
     /*  425272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  425275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425293 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  425296 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425319 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425323 */     GIR_RootConstrainSelectedInstOperands,
     /*  425324 */     // GIR_Coverage, 16037,
     /*  425324 */     GIR_EraseRootFromParent_Done,
     /*  425325 */   // Label 6418: @425325
     /*  425325 */   GIM_Try, /*On fail goto*//*Label 6419*/ GIMT_Encode4(425383), // Rule ID 16043 //
     /*  425330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  425333 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425351 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  425354 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425381 */     GIR_RootConstrainSelectedInstOperands,
     /*  425382 */     // GIR_Coverage, 16043,
     /*  425382 */     GIR_EraseRootFromParent_Done,
     /*  425383 */   // Label 6419: @425383
     /*  425383 */   GIM_Try, /*On fail goto*//*Label 6420*/ GIMT_Encode4(425441), // Rule ID 16044 //
     /*  425388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  425391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425398 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425409 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  425412 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425439 */     GIR_RootConstrainSelectedInstOperands,
     /*  425440 */     // GIR_Coverage, 16044,
     /*  425440 */     GIR_EraseRootFromParent_Done,
     /*  425441 */   // Label 6420: @425441
     /*  425441 */   GIM_Try, /*On fail goto*//*Label 6421*/ GIMT_Encode4(425499), // Rule ID 16045 //
     /*  425446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  425449 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425467 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  425470 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425497 */     GIR_RootConstrainSelectedInstOperands,
     /*  425498 */     // GIR_Coverage, 16045,
     /*  425498 */     GIR_EraseRootFromParent_Done,
     /*  425499 */   // Label 6421: @425499
     /*  425499 */   GIM_Try, /*On fail goto*//*Label 6422*/ GIMT_Encode4(425557), // Rule ID 16046 //
     /*  425504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  425507 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425525 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  425528 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425555 */     GIR_RootConstrainSelectedInstOperands,
     /*  425556 */     // GIR_Coverage, 16046,
     /*  425556 */     GIR_EraseRootFromParent_Done,
     /*  425557 */   // Label 6422: @425557
     /*  425557 */   GIM_Try, /*On fail goto*//*Label 6423*/ GIMT_Encode4(425615), // Rule ID 16047 //
     /*  425562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  425565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  425572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  425583 */     // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  425583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  425586 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  425588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  425593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  425598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  425603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425613 */     GIR_RootConstrainSelectedInstOperands,
     /*  425614 */     // GIR_Coverage, 16047,
     /*  425614 */     GIR_EraseRootFromParent_Done,
     /*  425615 */   // Label 6423: @425615
     /*  425615 */   GIM_Try, /*On fail goto*//*Label 6424*/ GIMT_Encode4(425667), // Rule ID 29293 //
     /*  425620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  425623 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  425627 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425643 */     // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  425646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425651 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425665 */     GIR_RootConstrainSelectedInstOperands,
     /*  425666 */     // GIR_Coverage, 29293,
     /*  425666 */     GIR_EraseRootFromParent_Done,
     /*  425667 */   // Label 6424: @425667
     /*  425667 */   GIM_Try, /*On fail goto*//*Label 6425*/ GIMT_Encode4(425719), // Rule ID 29294 //
     /*  425672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  425675 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  425679 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425695 */     // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  425698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425703 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425717 */     GIR_RootConstrainSelectedInstOperands,
     /*  425718 */     // GIR_Coverage, 29294,
     /*  425718 */     GIR_EraseRootFromParent_Done,
     /*  425719 */   // Label 6425: @425719
     /*  425719 */   GIM_Try, /*On fail goto*//*Label 6426*/ GIMT_Encode4(425771), // Rule ID 29295 //
     /*  425724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  425727 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  425731 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425747 */     // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  425750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425755 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425769 */     GIR_RootConstrainSelectedInstOperands,
     /*  425770 */     // GIR_Coverage, 29295,
     /*  425770 */     GIR_EraseRootFromParent_Done,
     /*  425771 */   // Label 6426: @425771
     /*  425771 */   GIM_Try, /*On fail goto*//*Label 6427*/ GIMT_Encode4(425823), // Rule ID 29296 //
     /*  425776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  425779 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  425783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425799 */     // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  425802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425807 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425821 */     GIR_RootConstrainSelectedInstOperands,
     /*  425822 */     // GIR_Coverage, 29296,
     /*  425822 */     GIR_EraseRootFromParent_Done,
     /*  425823 */   // Label 6427: @425823
     /*  425823 */   GIM_Try, /*On fail goto*//*Label 6428*/ GIMT_Encode4(425875), // Rule ID 29297 //
     /*  425828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  425831 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  425835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425851 */     // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  425854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425859 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425869 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425873 */     GIR_RootConstrainSelectedInstOperands,
     /*  425874 */     // GIR_Coverage, 29297,
     /*  425874 */     GIR_EraseRootFromParent_Done,
     /*  425875 */   // Label 6428: @425875
     /*  425875 */   GIM_Try, /*On fail goto*//*Label 6429*/ GIMT_Encode4(425923), // Rule ID 29298 //
     /*  425880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  425883 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425888 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425899 */     // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  425902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425907 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425917 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425921 */     GIR_RootConstrainSelectedInstOperands,
     /*  425922 */     // GIR_Coverage, 29298,
     /*  425922 */     GIR_EraseRootFromParent_Done,
     /*  425923 */   // Label 6429: @425923
     /*  425923 */   GIM_Try, /*On fail goto*//*Label 6430*/ GIMT_Encode4(425971), // Rule ID 29299 //
     /*  425928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  425931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425947 */     // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  425950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  425955 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  425957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  425962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  425965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  425969 */     GIR_RootConstrainSelectedInstOperands,
     /*  425970 */     // GIR_Coverage, 29299,
     /*  425970 */     GIR_EraseRootFromParent_Done,
     /*  425971 */   // Label 6430: @425971
     /*  425971 */   GIM_Try, /*On fail goto*//*Label 6431*/ GIMT_Encode4(426019), // Rule ID 29300 //
     /*  425976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  425979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  425984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  425988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  425995 */     // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  425995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  425998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  426003 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  426005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426017 */     GIR_RootConstrainSelectedInstOperands,
     /*  426018 */     // GIR_Coverage, 29300,
     /*  426018 */     GIR_EraseRootFromParent_Done,
     /*  426019 */   // Label 6431: @426019
     /*  426019 */   GIM_Try, /*On fail goto*//*Label 6432*/ GIMT_Encode4(426067), // Rule ID 29301 //
     /*  426024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  426027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  426032 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  426043 */     // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  426043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  426046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  426051 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  426053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426065 */     GIR_RootConstrainSelectedInstOperands,
     /*  426066 */     // GIR_Coverage, 29301,
     /*  426066 */     GIR_EraseRootFromParent_Done,
     /*  426067 */   // Label 6432: @426067
     /*  426067 */   GIM_Try, /*On fail goto*//*Label 6433*/ GIMT_Encode4(426115), // Rule ID 29302 //
     /*  426072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  426075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  426080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  426091 */     // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  426091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  426094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  426099 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  426101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426113 */     GIR_RootConstrainSelectedInstOperands,
     /*  426114 */     // GIR_Coverage, 29302,
     /*  426114 */     GIR_EraseRootFromParent_Done,
     /*  426115 */   // Label 6433: @426115
     /*  426115 */   GIM_Try, /*On fail goto*//*Label 6434*/ GIMT_Encode4(426172), // Rule ID 12253 //
     /*  426120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  426123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426130 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426134 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426141 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  426144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426149 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426170 */     GIR_RootConstrainSelectedInstOperands,
     /*  426171 */     // GIR_Coverage, 12253,
     /*  426171 */     GIR_EraseRootFromParent_Done,
     /*  426172 */   // Label 6434: @426172
     /*  426172 */   GIM_Try, /*On fail goto*//*Label 6435*/ GIMT_Encode4(426229), // Rule ID 12254 //
     /*  426177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  426180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426198 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  426201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426206 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426227 */     GIR_RootConstrainSelectedInstOperands,
     /*  426228 */     // GIR_Coverage, 12254,
     /*  426228 */     GIR_EraseRootFromParent_Done,
     /*  426229 */   // Label 6435: @426229
     /*  426229 */   GIM_Try, /*On fail goto*//*Label 6436*/ GIMT_Encode4(426286), // Rule ID 12255 //
     /*  426234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  426237 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426255 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  426258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426263 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426284 */     GIR_RootConstrainSelectedInstOperands,
     /*  426285 */     // GIR_Coverage, 12255,
     /*  426285 */     GIR_EraseRootFromParent_Done,
     /*  426286 */   // Label 6436: @426286
     /*  426286 */   GIM_Try, /*On fail goto*//*Label 6437*/ GIMT_Encode4(426343), // Rule ID 12256 //
     /*  426291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  426294 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426312 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  426315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426320 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426337 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426341 */     GIR_RootConstrainSelectedInstOperands,
     /*  426342 */     // GIR_Coverage, 12256,
     /*  426342 */     GIR_EraseRootFromParent_Done,
     /*  426343 */   // Label 6437: @426343
     /*  426343 */   GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(426400), // Rule ID 12257 //
     /*  426348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  426351 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426369 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  426372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426377 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426398 */     GIR_RootConstrainSelectedInstOperands,
     /*  426399 */     // GIR_Coverage, 12257,
     /*  426399 */     GIR_EraseRootFromParent_Done,
     /*  426400 */   // Label 6438: @426400
     /*  426400 */   GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(426450), // Rule ID 12248 //
     /*  426405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  426408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  426426 */     // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  426426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  426429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  426434 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426448 */     GIR_RootConstrainSelectedInstOperands,
     /*  426449 */     // GIR_Coverage, 12248,
     /*  426449 */     GIR_EraseRootFromParent_Done,
     /*  426450 */   // Label 6439: @426450
     /*  426450 */   GIM_Try, /*On fail goto*//*Label 6440*/ GIMT_Encode4(426500), // Rule ID 12249 //
     /*  426455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  426458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  426476 */     // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  426476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  426479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  426484 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426498 */     GIR_RootConstrainSelectedInstOperands,
     /*  426499 */     // GIR_Coverage, 12249,
     /*  426499 */     GIR_EraseRootFromParent_Done,
     /*  426500 */   // Label 6440: @426500
     /*  426500 */   GIM_Try, /*On fail goto*//*Label 6441*/ GIMT_Encode4(426550), // Rule ID 12250 //
     /*  426505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  426508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426515 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426519 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  426526 */     // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  426526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  426529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  426534 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426548 */     GIR_RootConstrainSelectedInstOperands,
     /*  426549 */     // GIR_Coverage, 12250,
     /*  426549 */     GIR_EraseRootFromParent_Done,
     /*  426550 */   // Label 6441: @426550
     /*  426550 */   GIM_Try, /*On fail goto*//*Label 6442*/ GIMT_Encode4(426600), // Rule ID 12251 //
     /*  426555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  426558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  426576 */     // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  426576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  426579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  426584 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426598 */     GIR_RootConstrainSelectedInstOperands,
     /*  426599 */     // GIR_Coverage, 12251,
     /*  426599 */     GIR_EraseRootFromParent_Done,
     /*  426600 */   // Label 6442: @426600
     /*  426600 */   GIM_Try, /*On fail goto*//*Label 6443*/ GIMT_Encode4(426650), // Rule ID 12252 //
     /*  426605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  426608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  426615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  426626 */     // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  426626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  426629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  426634 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426644 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426648 */     GIR_RootConstrainSelectedInstOperands,
     /*  426649 */     // GIR_Coverage, 12252,
     /*  426649 */     GIR_EraseRootFromParent_Done,
     /*  426650 */   // Label 6443: @426650
     /*  426650 */   GIM_Try, /*On fail goto*//*Label 6444*/ GIMT_Encode4(426706), // Rule ID 10111 //
     /*  426655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  426658 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426675 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  426678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426683 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426704 */     GIR_RootConstrainSelectedInstOperands,
     /*  426705 */     // GIR_Coverage, 10111,
     /*  426705 */     GIR_EraseRootFromParent_Done,
     /*  426706 */   // Label 6444: @426706
     /*  426706 */   GIM_Try, /*On fail goto*//*Label 6445*/ GIMT_Encode4(426762), // Rule ID 10112 //
     /*  426711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  426714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426731 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  426734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426739 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426760 */     GIR_RootConstrainSelectedInstOperands,
     /*  426761 */     // GIR_Coverage, 10112,
     /*  426761 */     GIR_EraseRootFromParent_Done,
     /*  426762 */   // Label 6445: @426762
     /*  426762 */   GIM_Try, /*On fail goto*//*Label 6446*/ GIMT_Encode4(426818), // Rule ID 10113 //
     /*  426767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  426770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426787 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  426790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426795 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426812 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426816 */     GIR_RootConstrainSelectedInstOperands,
     /*  426817 */     // GIR_Coverage, 10113,
     /*  426817 */     GIR_EraseRootFromParent_Done,
     /*  426818 */   // Label 6446: @426818
     /*  426818 */   GIM_Try, /*On fail goto*//*Label 6447*/ GIMT_Encode4(426874), // Rule ID 10114 //
     /*  426823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  426826 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426843 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  426846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426851 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426872 */     GIR_RootConstrainSelectedInstOperands,
     /*  426873 */     // GIR_Coverage, 10114,
     /*  426873 */     GIR_EraseRootFromParent_Done,
     /*  426874 */   // Label 6447: @426874
     /*  426874 */   GIM_Try, /*On fail goto*//*Label 6448*/ GIMT_Encode4(426930), // Rule ID 10115 //
     /*  426879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  426882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426888 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  426899 */     // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  426899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  426902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  426907 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  426914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  426919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  426924 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426928 */     GIR_RootConstrainSelectedInstOperands,
     /*  426929 */     // GIR_Coverage, 10115,
     /*  426929 */     GIR_EraseRootFromParent_Done,
     /*  426930 */   // Label 6448: @426930
     /*  426930 */   GIM_Try, /*On fail goto*//*Label 6449*/ GIMT_Encode4(426979), // Rule ID 10106 //
     /*  426935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  426938 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  426955 */     // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  426955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  426958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  426963 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  426965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  426970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  426973 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  426977 */     GIR_RootConstrainSelectedInstOperands,
     /*  426978 */     // GIR_Coverage, 10106,
     /*  426978 */     GIR_EraseRootFromParent_Done,
     /*  426979 */   // Label 6449: @426979
     /*  426979 */   GIM_Try, /*On fail goto*//*Label 6450*/ GIMT_Encode4(427028), // Rule ID 10107 //
     /*  426984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  426987 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  426993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  426997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  427004 */     // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  427004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  427007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  427012 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  427014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  427019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427026 */     GIR_RootConstrainSelectedInstOperands,
     /*  427027 */     // GIR_Coverage, 10107,
     /*  427027 */     GIR_EraseRootFromParent_Done,
     /*  427028 */   // Label 6450: @427028
     /*  427028 */   GIM_Try, /*On fail goto*//*Label 6451*/ GIMT_Encode4(427077), // Rule ID 10108 //
     /*  427033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  427036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  427042 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427046 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  427053 */     // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  427053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  427056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  427061 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  427063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  427068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427075 */     GIR_RootConstrainSelectedInstOperands,
     /*  427076 */     // GIR_Coverage, 10108,
     /*  427076 */     GIR_EraseRootFromParent_Done,
     /*  427077 */   // Label 6451: @427077
     /*  427077 */   GIM_Try, /*On fail goto*//*Label 6452*/ GIMT_Encode4(427126), // Rule ID 10109 //
     /*  427082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  427085 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  427091 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  427102 */     // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  427102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  427105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  427110 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  427112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  427117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427120 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427124 */     GIR_RootConstrainSelectedInstOperands,
     /*  427125 */     // GIR_Coverage, 10109,
     /*  427125 */     GIR_EraseRootFromParent_Done,
     /*  427126 */   // Label 6452: @427126
     /*  427126 */   GIM_Try, /*On fail goto*//*Label 6453*/ GIMT_Encode4(427175), // Rule ID 10110 //
     /*  427131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  427134 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  427140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  427151 */     // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  427151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  427154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  427159 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  427161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  427166 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427173 */     GIR_RootConstrainSelectedInstOperands,
     /*  427174 */     // GIR_Coverage, 10110,
     /*  427174 */     GIR_EraseRootFromParent_Done,
     /*  427175 */   // Label 6453: @427175
     /*  427175 */   GIM_Reject,
     /*  427176 */ // Label 6368: @427176
     /*  427176 */ GIM_Reject,
     /*  427177 */ // Label 5865: @427177
     /*  427177 */ GIM_Try, /*On fail goto*//*Label 6454*/ GIMT_Encode4(427247), // Rule ID 25746 //
     /*  427182 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  427185 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427188 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427192 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427199 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427204 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427208 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427215 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427215 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  427218 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427241 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427245 */   GIR_RootConstrainSelectedInstOperands,
     /*  427246 */   // GIR_Coverage, 25746,
     /*  427246 */   GIR_EraseRootFromParent_Done,
     /*  427247 */ // Label 6454: @427247
     /*  427247 */ GIM_Try, /*On fail goto*//*Label 6455*/ GIMT_Encode4(427317), // Rule ID 25747 //
     /*  427252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  427255 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427258 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427262 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427274 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427278 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427285 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  427288 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427305 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427308 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427311 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427315 */   GIR_RootConstrainSelectedInstOperands,
     /*  427316 */   // GIR_Coverage, 25747,
     /*  427316 */   GIR_EraseRootFromParent_Done,
     /*  427317 */ // Label 6455: @427317
     /*  427317 */ GIM_Try, /*On fail goto*//*Label 6456*/ GIMT_Encode4(427387), // Rule ID 25748 //
     /*  427322 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  427325 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427328 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427332 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427339 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427344 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427355 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  427358 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427381 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427385 */   GIR_RootConstrainSelectedInstOperands,
     /*  427386 */   // GIR_Coverage, 25748,
     /*  427386 */   GIR_EraseRootFromParent_Done,
     /*  427387 */ // Label 6456: @427387
     /*  427387 */ GIM_Try, /*On fail goto*//*Label 6457*/ GIMT_Encode4(427457), // Rule ID 25749 //
     /*  427392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  427395 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427398 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427402 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427409 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427414 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427418 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427425 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427425 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  427428 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427445 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427448 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427451 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427455 */   GIR_RootConstrainSelectedInstOperands,
     /*  427456 */   // GIR_Coverage, 25749,
     /*  427456 */   GIR_EraseRootFromParent_Done,
     /*  427457 */ // Label 6457: @427457
     /*  427457 */ GIM_Try, /*On fail goto*//*Label 6458*/ GIMT_Encode4(427527), // Rule ID 25750 //
     /*  427462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  427465 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427468 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427472 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427484 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427488 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427495 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427495 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  427498 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427505 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427515 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427518 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427521 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427525 */   GIR_RootConstrainSelectedInstOperands,
     /*  427526 */   // GIR_Coverage, 25750,
     /*  427526 */   GIR_EraseRootFromParent_Done,
     /*  427527 */ // Label 6458: @427527
     /*  427527 */ GIM_Try, /*On fail goto*//*Label 6459*/ GIMT_Encode4(427597), // Rule ID 25756 //
     /*  427532 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  427535 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427538 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427542 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427549 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427554 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427558 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427565 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  427568 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427570 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427585 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427588 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427591 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427595 */   GIR_RootConstrainSelectedInstOperands,
     /*  427596 */   // GIR_Coverage, 25756,
     /*  427596 */   GIR_EraseRootFromParent_Done,
     /*  427597 */ // Label 6459: @427597
     /*  427597 */ GIM_Try, /*On fail goto*//*Label 6460*/ GIMT_Encode4(427667), // Rule ID 25757 //
     /*  427602 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  427605 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427608 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427612 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427624 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427628 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427635 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  427638 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427655 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427658 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427661 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427665 */   GIR_RootConstrainSelectedInstOperands,
     /*  427666 */   // GIR_Coverage, 25757,
     /*  427666 */   GIR_EraseRootFromParent_Done,
     /*  427667 */ // Label 6460: @427667
     /*  427667 */ GIM_Try, /*On fail goto*//*Label 6461*/ GIMT_Encode4(427737), // Rule ID 25758 //
     /*  427672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  427675 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427678 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427682 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427705 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  427708 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427725 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427728 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427731 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427735 */   GIR_RootConstrainSelectedInstOperands,
     /*  427736 */   // GIR_Coverage, 25758,
     /*  427736 */   GIR_EraseRootFromParent_Done,
     /*  427737 */ // Label 6461: @427737
     /*  427737 */ GIM_Try, /*On fail goto*//*Label 6462*/ GIMT_Encode4(427807), // Rule ID 25759 //
     /*  427742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  427745 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427748 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427752 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427759 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427775 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  427778 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427795 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427805 */   GIR_RootConstrainSelectedInstOperands,
     /*  427806 */   // GIR_Coverage, 25759,
     /*  427806 */   GIR_EraseRootFromParent_Done,
     /*  427807 */ // Label 6462: @427807
     /*  427807 */ GIM_Try, /*On fail goto*//*Label 6463*/ GIMT_Encode4(427877), // Rule ID 25760 //
     /*  427812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  427815 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427818 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  427822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  427829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427845 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  427848 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427865 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427871 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427875 */   GIR_RootConstrainSelectedInstOperands,
     /*  427876 */   // GIR_Coverage, 25760,
     /*  427876 */   GIR_EraseRootFromParent_Done,
     /*  427877 */ // Label 6463: @427877
     /*  427877 */ GIM_Try, /*On fail goto*//*Label 6464*/ GIMT_Encode4(427936), // Rule ID 25766 //
     /*  427882 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  427885 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427888 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427897 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427904 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  427907 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427934 */   GIR_RootConstrainSelectedInstOperands,
     /*  427935 */   // GIR_Coverage, 25766,
     /*  427935 */   GIR_EraseRootFromParent_Done,
     /*  427936 */ // Label 6464: @427936
     /*  427936 */ GIM_Try, /*On fail goto*//*Label 6465*/ GIMT_Encode4(427995), // Rule ID 25767 //
     /*  427941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  427944 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  427947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  427952 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  427956 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  427963 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  427963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  427966 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  427968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  427973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  427978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  427983 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427986 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  427989 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  427993 */   GIR_RootConstrainSelectedInstOperands,
     /*  427994 */   // GIR_Coverage, 25767,
     /*  427994 */   GIR_EraseRootFromParent_Done,
     /*  427995 */ // Label 6465: @427995
     /*  427995 */ GIM_Try, /*On fail goto*//*Label 6466*/ GIMT_Encode4(428054), // Rule ID 25768 //
     /*  428000 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  428003 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428006 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428011 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428015 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428022 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428022 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  428025 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428042 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428045 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428048 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428052 */   GIR_RootConstrainSelectedInstOperands,
     /*  428053 */   // GIR_Coverage, 25768,
     /*  428053 */   GIR_EraseRootFromParent_Done,
     /*  428054 */ // Label 6466: @428054
     /*  428054 */ GIM_Try, /*On fail goto*//*Label 6467*/ GIMT_Encode4(428113), // Rule ID 25769 //
     /*  428059 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  428062 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428081 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  428084 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428101 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428104 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428111 */   GIR_RootConstrainSelectedInstOperands,
     /*  428112 */   // GIR_Coverage, 25769,
     /*  428112 */   GIR_EraseRootFromParent_Done,
     /*  428113 */ // Label 6467: @428113
     /*  428113 */ GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(428172), // Rule ID 25770 //
     /*  428118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  428121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428124 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428140 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  428143 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428170 */   GIR_RootConstrainSelectedInstOperands,
     /*  428171 */   // GIR_Coverage, 25770,
     /*  428171 */   GIR_EraseRootFromParent_Done,
     /*  428172 */ // Label 6468: @428172
     /*  428172 */ GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(428231), // Rule ID 25776 //
     /*  428177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  428180 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428183 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428188 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428192 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428199 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  428202 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428222 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428225 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428229 */   GIR_RootConstrainSelectedInstOperands,
     /*  428230 */   // GIR_Coverage, 25776,
     /*  428230 */   GIR_EraseRootFromParent_Done,
     /*  428231 */ // Label 6469: @428231
     /*  428231 */ GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(428290), // Rule ID 25777 //
     /*  428236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  428239 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428242 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428258 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  428261 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428278 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428284 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428288 */   GIR_RootConstrainSelectedInstOperands,
     /*  428289 */   // GIR_Coverage, 25777,
     /*  428289 */   GIR_EraseRootFromParent_Done,
     /*  428290 */ // Label 6470: @428290
     /*  428290 */ GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(428349), // Rule ID 25778 //
     /*  428295 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  428298 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428301 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428306 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428310 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428317 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  428320 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428340 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428343 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428347 */   GIR_RootConstrainSelectedInstOperands,
     /*  428348 */   // GIR_Coverage, 25778,
     /*  428348 */   GIR_EraseRootFromParent_Done,
     /*  428349 */ // Label 6471: @428349
     /*  428349 */ GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(428408), // Rule ID 25779 //
     /*  428354 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  428357 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428360 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428376 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  428379 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428396 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428406 */   GIR_RootConstrainSelectedInstOperands,
     /*  428407 */   // GIR_Coverage, 25779,
     /*  428407 */   GIR_EraseRootFromParent_Done,
     /*  428408 */ // Label 6472: @428408
     /*  428408 */ GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(428467), // Rule ID 25780 //
     /*  428413 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  428416 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428419 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428424 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428428 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  428435 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  428435 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  428438 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  428440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  428445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  428450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428455 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428458 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  428461 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428465 */   GIR_RootConstrainSelectedInstOperands,
     /*  428466 */   // GIR_Coverage, 25780,
     /*  428466 */   GIR_EraseRootFromParent_Done,
     /*  428467 */ // Label 6473: @428467
     /*  428467 */ GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(428536), // Rule ID 13990 //
     /*  428472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  428475 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428478 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  428482 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  428489 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428494 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428498 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428505 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  428508 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428530 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428534 */   GIR_RootConstrainSelectedInstOperands,
     /*  428535 */   // GIR_Coverage, 13990,
     /*  428535 */   GIR_EraseRootFromParent_Done,
     /*  428536 */ // Label 6474: @428536
     /*  428536 */ GIM_Try, /*On fail goto*//*Label 6475*/ GIMT_Encode4(428605), // Rule ID 13991 //
     /*  428541 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  428544 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428547 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  428551 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  428558 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428563 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428567 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428574 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428574 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  428577 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428603 */   GIR_RootConstrainSelectedInstOperands,
     /*  428604 */   // GIR_Coverage, 13991,
     /*  428604 */   GIR_EraseRootFromParent_Done,
     /*  428605 */ // Label 6475: @428605
     /*  428605 */ GIM_Try, /*On fail goto*//*Label 6476*/ GIMT_Encode4(428674), // Rule ID 13992 //
     /*  428610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  428613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428616 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  428620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  428627 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428643 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  428646 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428668 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428672 */   GIR_RootConstrainSelectedInstOperands,
     /*  428673 */   // GIR_Coverage, 13992,
     /*  428673 */   GIR_EraseRootFromParent_Done,
     /*  428674 */ // Label 6476: @428674
     /*  428674 */ GIM_Try, /*On fail goto*//*Label 6477*/ GIMT_Encode4(428743), // Rule ID 13993 //
     /*  428679 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  428682 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428685 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  428689 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  428696 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428705 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428712 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  428715 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428741 */   GIR_RootConstrainSelectedInstOperands,
     /*  428742 */   // GIR_Coverage, 13993,
     /*  428742 */   GIR_EraseRootFromParent_Done,
     /*  428743 */ // Label 6477: @428743
     /*  428743 */ GIM_Try, /*On fail goto*//*Label 6478*/ GIMT_Encode4(428812), // Rule ID 13994 //
     /*  428748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  428751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428754 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  428758 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  428765 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428781 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  428784 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428806 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428810 */   GIR_RootConstrainSelectedInstOperands,
     /*  428811 */   // GIR_Coverage, 13994,
     /*  428811 */   GIR_EraseRootFromParent_Done,
     /*  428812 */ // Label 6478: @428812
     /*  428812 */ GIM_Try, /*On fail goto*//*Label 6479*/ GIMT_Encode4(428881), // Rule ID 14051 //
     /*  428817 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseRealTrue16Insts),
     /*  428820 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428823 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  428827 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  428834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428839 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428843 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428850 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS_t16 anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS_t16),
     /*  428853 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428875 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428879 */   GIR_RootConstrainSelectedInstOperands,
     /*  428880 */   // GIR_Coverage, 14051,
     /*  428880 */   GIR_EraseRootFromParent_Done,
     /*  428881 */ // Label 6479: @428881
     /*  428881 */ GIM_Try, /*On fail goto*//*Label 6480*/ GIMT_Encode4(428939), // Rule ID 9433 //
     /*  428886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  428889 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428892 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428897 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428901 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428908 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428908 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  428911 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428933 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428937 */   GIR_RootConstrainSelectedInstOperands,
     /*  428938 */   // GIR_Coverage, 9433,
     /*  428938 */   GIR_EraseRootFromParent_Done,
     /*  428939 */ // Label 6480: @428939
     /*  428939 */ GIM_Try, /*On fail goto*//*Label 6481*/ GIMT_Encode4(428997), // Rule ID 9434 //
     /*  428944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  428947 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  428950 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  428955 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  428959 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  428966 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  428966 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  428969 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  428971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  428976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  428981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  428986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  428991 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  428995 */   GIR_RootConstrainSelectedInstOperands,
     /*  428996 */   // GIR_Coverage, 9434,
     /*  428996 */   GIR_EraseRootFromParent_Done,
     /*  428997 */ // Label 6481: @428997
     /*  428997 */ GIM_Try, /*On fail goto*//*Label 6482*/ GIMT_Encode4(429055), // Rule ID 9435 //
     /*  429002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  429005 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429008 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  429024 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  429024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  429027 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  429034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  429039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  429044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  429049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429053 */   GIR_RootConstrainSelectedInstOperands,
     /*  429054 */   // GIR_Coverage, 9435,
     /*  429054 */   GIR_EraseRootFromParent_Done,
     /*  429055 */ // Label 6482: @429055
     /*  429055 */ GIM_Try, /*On fail goto*//*Label 6483*/ GIMT_Encode4(429113), // Rule ID 9436 //
     /*  429060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  429063 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429066 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  429082 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  429082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  429085 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  429092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  429097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  429102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  429107 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429111 */   GIR_RootConstrainSelectedInstOperands,
     /*  429112 */   // GIR_Coverage, 9436,
     /*  429112 */   GIR_EraseRootFromParent_Done,
     /*  429113 */ // Label 6483: @429113
     /*  429113 */ GIM_Try, /*On fail goto*//*Label 6484*/ GIMT_Encode4(429171), // Rule ID 9437 //
     /*  429118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  429121 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429124 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  429140 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  429140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  429143 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  429150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  429155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  429160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  429165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429169 */   GIR_RootConstrainSelectedInstOperands,
     /*  429170 */   // GIR_Coverage, 9437,
     /*  429170 */   GIR_EraseRootFromParent_Done,
     /*  429171 */ // Label 6484: @429171
     /*  429171 */ GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(429229), // Rule ID 9440 //
     /*  429176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_UseRealTrue16Insts),
     /*  429179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429182 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429187 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429191 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  429198 */   // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS_t16 anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  429198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS_t16),
     /*  429201 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  429208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  429213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  429218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  429223 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429227 */   GIR_RootConstrainSelectedInstOperands,
     /*  429228 */   // GIR_Coverage, 9440,
     /*  429228 */   GIR_EraseRootFromParent_Done,
     /*  429229 */ // Label 6485: @429229
     /*  429229 */ GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(429291), // Rule ID 13985 //
     /*  429234 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  429237 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429240 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429244 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429256 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429260 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429267 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429267 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  429270 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429282 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429285 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429289 */   GIR_RootConstrainSelectedInstOperands,
     /*  429290 */   // GIR_Coverage, 13985,
     /*  429290 */   GIR_EraseRootFromParent_Done,
     /*  429291 */ // Label 6486: @429291
     /*  429291 */ GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(429353), // Rule ID 13986 //
     /*  429296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  429299 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429302 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429318 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429322 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429329 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  429332 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429344 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429351 */   GIR_RootConstrainSelectedInstOperands,
     /*  429352 */   // GIR_Coverage, 13986,
     /*  429352 */   GIR_EraseRootFromParent_Done,
     /*  429353 */ // Label 6487: @429353
     /*  429353 */ GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(429415), // Rule ID 13987 //
     /*  429358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  429361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429364 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429380 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429384 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429391 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  429394 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429406 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429413 */   GIR_RootConstrainSelectedInstOperands,
     /*  429414 */   // GIR_Coverage, 13987,
     /*  429414 */   GIR_EraseRootFromParent_Done,
     /*  429415 */ // Label 6488: @429415
     /*  429415 */ GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(429477), // Rule ID 13988 //
     /*  429420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  429423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429426 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429430 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429453 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  429456 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429471 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429475 */   GIR_RootConstrainSelectedInstOperands,
     /*  429476 */   // GIR_Coverage, 13988,
     /*  429476 */   GIR_EraseRootFromParent_Done,
     /*  429477 */ // Label 6489: @429477
     /*  429477 */ GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(429539), // Rule ID 13989 //
     /*  429482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  429485 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429488 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429515 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  429518 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429537 */   GIR_RootConstrainSelectedInstOperands,
     /*  429538 */   // GIR_Coverage, 13989,
     /*  429538 */   GIR_EraseRootFromParent_Done,
     /*  429539 */ // Label 6490: @429539
     /*  429539 */ GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(429601), // Rule ID 14050 //
     /*  429544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseRealTrue16Insts),
     /*  429547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429550 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429554 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429570 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429577 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR_t16 anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR_t16),
     /*  429580 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429592 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429595 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429599 */   GIR_RootConstrainSelectedInstOperands,
     /*  429600 */   // GIR_Coverage, 14050,
     /*  429600 */   GIR_EraseRootFromParent_Done,
     /*  429601 */ // Label 6491: @429601
     /*  429601 */ GIM_Try, /*On fail goto*//*Label 6492*/ GIMT_Encode4(429652), // Rule ID 9428 //
     /*  429606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  429609 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429612 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429617 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429621 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429628 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429628 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  429631 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429643 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429646 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429650 */   GIR_RootConstrainSelectedInstOperands,
     /*  429651 */   // GIR_Coverage, 9428,
     /*  429651 */   GIR_EraseRootFromParent_Done,
     /*  429652 */ // Label 6492: @429652
     /*  429652 */ GIM_Try, /*On fail goto*//*Label 6493*/ GIMT_Encode4(429703), // Rule ID 9429 //
     /*  429657 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  429660 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429663 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429668 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429672 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429679 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  429682 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429694 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429697 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429701 */   GIR_RootConstrainSelectedInstOperands,
     /*  429702 */   // GIR_Coverage, 9429,
     /*  429702 */   GIR_EraseRootFromParent_Done,
     /*  429703 */ // Label 6493: @429703
     /*  429703 */ GIM_Try, /*On fail goto*//*Label 6494*/ GIMT_Encode4(429754), // Rule ID 9430 //
     /*  429708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  429711 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429714 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429719 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429723 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429730 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429730 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  429733 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429745 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429748 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429752 */   GIR_RootConstrainSelectedInstOperands,
     /*  429753 */   // GIR_Coverage, 9430,
     /*  429753 */   GIR_EraseRootFromParent_Done,
     /*  429754 */ // Label 6494: @429754
     /*  429754 */ GIM_Try, /*On fail goto*//*Label 6495*/ GIMT_Encode4(429805), // Rule ID 9431 //
     /*  429759 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  429762 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429765 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429781 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  429784 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429796 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429799 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429803 */   GIR_RootConstrainSelectedInstOperands,
     /*  429804 */   // GIR_Coverage, 9431,
     /*  429804 */   GIR_EraseRootFromParent_Done,
     /*  429805 */ // Label 6495: @429805
     /*  429805 */ GIM_Try, /*On fail goto*//*Label 6496*/ GIMT_Encode4(429856), // Rule ID 9432 //
     /*  429810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  429813 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429816 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429832 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  429835 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429847 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429850 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429854 */   GIR_RootConstrainSelectedInstOperands,
     /*  429855 */   // GIR_Coverage, 9432,
     /*  429855 */   GIR_EraseRootFromParent_Done,
     /*  429856 */ // Label 6496: @429856
     /*  429856 */ GIM_Try, /*On fail goto*//*Label 6497*/ GIMT_Encode4(429907), // Rule ID 9439 //
     /*  429861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseRealTrue16Insts),
     /*  429864 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429867 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429872 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429876 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  429883 */   // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR_t16 anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  429883 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR_t16),
     /*  429886 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  429893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429898 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429901 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429905 */   GIR_RootConstrainSelectedInstOperands,
     /*  429906 */   // GIR_Coverage, 9439,
     /*  429906 */   GIR_EraseRootFromParent_Done,
     /*  429907 */ // Label 6497: @429907
     /*  429907 */ GIM_Try, /*On fail goto*//*Label 6498*/ GIMT_Encode4(429969), // Rule ID 13980 //
     /*  429912 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  429915 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429918 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429922 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429934 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  429938 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  429945 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  429945 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  429948 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  429950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  429955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  429960 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  429963 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  429967 */   GIR_RootConstrainSelectedInstOperands,
     /*  429968 */   // GIR_Coverage, 13980,
     /*  429968 */   GIR_EraseRootFromParent_Done,
     /*  429969 */ // Label 6498: @429969
     /*  429969 */ GIM_Try, /*On fail goto*//*Label 6499*/ GIMT_Encode4(430031), // Rule ID 13981 //
     /*  429974 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  429977 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  429980 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  429984 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  429991 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  429996 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430000 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430007 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  430010 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430022 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430029 */   GIR_RootConstrainSelectedInstOperands,
     /*  430030 */   // GIR_Coverage, 13981,
     /*  430030 */   GIR_EraseRootFromParent_Done,
     /*  430031 */ // Label 6499: @430031
     /*  430031 */ GIM_Try, /*On fail goto*//*Label 6500*/ GIMT_Encode4(430093), // Rule ID 13982 //
     /*  430036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  430039 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430042 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  430046 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430062 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430069 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430069 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  430072 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430084 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430087 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430091 */   GIR_RootConstrainSelectedInstOperands,
     /*  430092 */   // GIR_Coverage, 13982,
     /*  430092 */   GIR_EraseRootFromParent_Done,
     /*  430093 */ // Label 6500: @430093
     /*  430093 */ GIM_Try, /*On fail goto*//*Label 6501*/ GIMT_Encode4(430155), // Rule ID 13983 //
     /*  430098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  430101 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430104 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  430108 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430115 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430120 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430124 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430131 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430131 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  430134 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430146 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430149 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430153 */   GIR_RootConstrainSelectedInstOperands,
     /*  430154 */   // GIR_Coverage, 13983,
     /*  430154 */   GIR_EraseRootFromParent_Done,
     /*  430155 */ // Label 6501: @430155
     /*  430155 */ GIM_Try, /*On fail goto*//*Label 6502*/ GIMT_Encode4(430217), // Rule ID 13984 //
     /*  430160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  430163 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430166 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  430170 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430177 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430182 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430186 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430193 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430193 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  430196 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430208 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430211 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430215 */   GIR_RootConstrainSelectedInstOperands,
     /*  430216 */   // GIR_Coverage, 13984,
     /*  430216 */   GIR_EraseRootFromParent_Done,
     /*  430217 */ // Label 6502: @430217
     /*  430217 */ GIM_Try, /*On fail goto*//*Label 6503*/ GIMT_Encode4(430279), // Rule ID 14049 //
     /*  430222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseRealTrue16Insts),
     /*  430225 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430228 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  430232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430244 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430248 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430255 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_t16 anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430255 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_t16),
     /*  430258 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430270 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430273 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430277 */   GIR_RootConstrainSelectedInstOperands,
     /*  430278 */   // GIR_Coverage, 14049,
     /*  430278 */   GIR_EraseRootFromParent_Done,
     /*  430279 */ // Label 6503: @430279
     /*  430279 */ GIM_Try, /*On fail goto*//*Label 6504*/ GIMT_Encode4(430330), // Rule ID 9423 //
     /*  430284 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode0),
     /*  430287 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430290 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430295 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430306 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  430309 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430321 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430324 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430328 */   GIR_RootConstrainSelectedInstOperands,
     /*  430329 */   // GIR_Coverage, 9423,
     /*  430329 */   GIR_EraseRootFromParent_Done,
     /*  430330 */ // Label 6504: @430330
     /*  430330 */ GIM_Try, /*On fail goto*//*Label 6505*/ GIMT_Encode4(430381), // Rule ID 9424 //
     /*  430335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode1),
     /*  430338 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430341 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430346 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430350 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430357 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430357 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  430360 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430372 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430375 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430379 */   GIR_RootConstrainSelectedInstOperands,
     /*  430380 */   // GIR_Coverage, 9424,
     /*  430380 */   GIR_EraseRootFromParent_Done,
     /*  430381 */ // Label 6505: @430381
     /*  430381 */ GIM_Try, /*On fail goto*//*Label 6506*/ GIMT_Encode4(430432), // Rule ID 9425 //
     /*  430386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode2),
     /*  430389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430392 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430397 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430401 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430408 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430408 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  430411 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430423 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430426 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430430 */   GIR_RootConstrainSelectedInstOperands,
     /*  430431 */   // GIR_Coverage, 9425,
     /*  430431 */   GIR_EraseRootFromParent_Done,
     /*  430432 */ // Label 6506: @430432
     /*  430432 */ GIM_Try, /*On fail goto*//*Label 6507*/ GIMT_Encode4(430483), // Rule ID 9426 //
     /*  430437 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode3),
     /*  430440 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430459 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  430462 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430474 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430477 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430481 */   GIR_RootConstrainSelectedInstOperands,
     /*  430482 */   // GIR_Coverage, 9426,
     /*  430482 */   GIR_EraseRootFromParent_Done,
     /*  430483 */ // Label 6507: @430483
     /*  430483 */ GIM_Try, /*On fail goto*//*Label 6508*/ GIMT_Encode4(430534), // Rule ID 9427 //
     /*  430488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_NotUseRealTrue16Insts_HwMode4),
     /*  430491 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430494 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430499 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430503 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430510 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  430513 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430532 */   GIR_RootConstrainSelectedInstOperands,
     /*  430533 */   // GIR_Coverage, 9427,
     /*  430533 */   GIR_EraseRootFromParent_Done,
     /*  430534 */ // Label 6508: @430534
     /*  430534 */ GIM_Try, /*On fail goto*//*Label 6509*/ GIMT_Encode4(430585), // Rule ID 9438 //
     /*  430539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_UseRealTrue16Insts),
     /*  430542 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  430545 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  430550 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430554 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  430561 */   // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_t16 anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  430561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_t16),
     /*  430564 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  430566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  430571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  430576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430579 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430583 */   GIR_RootConstrainSelectedInstOperands,
     /*  430584 */   // GIR_Coverage, 9438,
     /*  430584 */   GIR_EraseRootFromParent_Done,
     /*  430585 */ // Label 6509: @430585
     /*  430585 */ GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(430658), // Rule ID 25631 //
     /*  430590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  430593 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  430596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  430610 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430614 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  430621 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  430621 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  430624 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  430626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  430631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  430636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  430641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  430646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430656 */   GIR_RootConstrainSelectedInstOperands,
     /*  430657 */   // GIR_Coverage, 25631,
     /*  430657 */   GIR_EraseRootFromParent_Done,
     /*  430658 */ // Label 6510: @430658
     /*  430658 */ GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(430731), // Rule ID 25632 //
     /*  430663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  430666 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  430669 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430676 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  430683 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430687 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  430694 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  430694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  430697 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  430699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  430704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  430709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  430714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  430719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430722 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430729 */   GIR_RootConstrainSelectedInstOperands,
     /*  430730 */   // GIR_Coverage, 25632,
     /*  430730 */   GIR_EraseRootFromParent_Done,
     /*  430731 */ // Label 6511: @430731
     /*  430731 */ GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(430804), // Rule ID 25633 //
     /*  430736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  430739 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  430742 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  430756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  430767 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  430767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  430770 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  430772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  430777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  430782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  430787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  430792 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430795 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430798 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430802 */   GIR_RootConstrainSelectedInstOperands,
     /*  430803 */   // GIR_Coverage, 25633,
     /*  430803 */   GIR_EraseRootFromParent_Done,
     /*  430804 */ // Label 6512: @430804
     /*  430804 */ GIM_Try, /*On fail goto*//*Label 6513*/ GIMT_Encode4(430877), // Rule ID 25634 //
     /*  430809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  430812 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  430815 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430822 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  430829 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430833 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  430840 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  430840 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  430843 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  430845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  430850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  430855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  430860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  430865 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430871 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430875 */   GIR_RootConstrainSelectedInstOperands,
     /*  430876 */   // GIR_Coverage, 25634,
     /*  430876 */   GIR_EraseRootFromParent_Done,
     /*  430877 */ // Label 6513: @430877
     /*  430877 */ GIM_Try, /*On fail goto*//*Label 6514*/ GIMT_Encode4(430950), // Rule ID 25635 //
     /*  430882 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  430885 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  430888 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  430895 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  430902 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430906 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  430913 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  430913 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  430916 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  430918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  430923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  430928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  430933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  430938 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430941 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  430944 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  430948 */   GIR_RootConstrainSelectedInstOperands,
     /*  430949 */   // GIR_Coverage, 25635,
     /*  430949 */   GIR_EraseRootFromParent_Done,
     /*  430950 */ // Label 6514: @430950
     /*  430950 */ GIM_Try, /*On fail goto*//*Label 6515*/ GIMT_Encode4(431023), // Rule ID 25651 //
     /*  430955 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  430958 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  430961 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  430968 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  430975 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  430979 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  430986 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  430986 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  430989 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  430991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  430996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431011 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431014 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431017 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431021 */   GIR_RootConstrainSelectedInstOperands,
     /*  431022 */   // GIR_Coverage, 25651,
     /*  431022 */   GIR_EraseRootFromParent_Done,
     /*  431023 */ // Label 6515: @431023
     /*  431023 */ GIM_Try, /*On fail goto*//*Label 6516*/ GIMT_Encode4(431096), // Rule ID 25652 //
     /*  431028 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  431031 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  431034 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  431041 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  431048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431052 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  431059 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  431059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  431062 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  431064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431084 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431087 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431090 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431094 */   GIR_RootConstrainSelectedInstOperands,
     /*  431095 */   // GIR_Coverage, 25652,
     /*  431095 */   GIR_EraseRootFromParent_Done,
     /*  431096 */ // Label 6516: @431096
     /*  431096 */ GIM_Try, /*On fail goto*//*Label 6517*/ GIMT_Encode4(431169), // Rule ID 25653 //
     /*  431101 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  431104 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  431107 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  431114 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  431121 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  431132 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  431132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  431135 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  431137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431157 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431163 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431167 */   GIR_RootConstrainSelectedInstOperands,
     /*  431168 */   // GIR_Coverage, 25653,
     /*  431168 */   GIR_EraseRootFromParent_Done,
     /*  431169 */ // Label 6517: @431169
     /*  431169 */ GIM_Try, /*On fail goto*//*Label 6518*/ GIMT_Encode4(431242), // Rule ID 25654 //
     /*  431174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  431177 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  431180 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  431187 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  431194 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431198 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  431205 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  431205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  431208 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  431210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431230 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431236 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431240 */   GIR_RootConstrainSelectedInstOperands,
     /*  431241 */   // GIR_Coverage, 25654,
     /*  431241 */   GIR_EraseRootFromParent_Done,
     /*  431242 */ // Label 6518: @431242
     /*  431242 */ GIM_Try, /*On fail goto*//*Label 6519*/ GIMT_Encode4(431315), // Rule ID 25655 //
     /*  431247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  431250 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  431253 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  431260 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  431267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  431278 */   // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  431278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  431281 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  431283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431303 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431306 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431309 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431313 */   GIR_RootConstrainSelectedInstOperands,
     /*  431314 */   // GIR_Coverage, 25655,
     /*  431314 */   GIR_EraseRootFromParent_Done,
     /*  431315 */ // Label 6519: @431315
     /*  431315 */ GIM_Try, /*On fail goto*//*Label 6520*/ GIMT_Encode4(431390), // Rule ID 25741 //
     /*  431320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  431323 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431326 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431330 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431337 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431353 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  431356 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431381 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431384 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431388 */   GIR_RootConstrainSelectedInstOperands,
     /*  431389 */   // GIR_Coverage, 25741,
     /*  431389 */   GIR_EraseRootFromParent_Done,
     /*  431390 */ // Label 6520: @431390
     /*  431390 */ GIM_Try, /*On fail goto*//*Label 6521*/ GIMT_Encode4(431465), // Rule ID 25742 //
     /*  431395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  431398 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431401 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431405 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431412 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431428 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  431431 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431453 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431456 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431459 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431463 */   GIR_RootConstrainSelectedInstOperands,
     /*  431464 */   // GIR_Coverage, 25742,
     /*  431464 */   GIR_EraseRootFromParent_Done,
     /*  431465 */ // Label 6521: @431465
     /*  431465 */ GIM_Try, /*On fail goto*//*Label 6522*/ GIMT_Encode4(431540), // Rule ID 25743 //
     /*  431470 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  431473 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431476 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431480 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431487 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431492 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431496 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431503 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  431506 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431531 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431534 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431538 */   GIR_RootConstrainSelectedInstOperands,
     /*  431539 */   // GIR_Coverage, 25743,
     /*  431539 */   GIR_EraseRootFromParent_Done,
     /*  431540 */ // Label 6522: @431540
     /*  431540 */ GIM_Try, /*On fail goto*//*Label 6523*/ GIMT_Encode4(431615), // Rule ID 25744 //
     /*  431545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  431548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431551 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431555 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431562 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431578 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  431581 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431613 */   GIR_RootConstrainSelectedInstOperands,
     /*  431614 */   // GIR_Coverage, 25744,
     /*  431614 */   GIR_EraseRootFromParent_Done,
     /*  431615 */ // Label 6523: @431615
     /*  431615 */ GIM_Try, /*On fail goto*//*Label 6524*/ GIMT_Encode4(431690), // Rule ID 25745 //
     /*  431620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  431623 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431626 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431637 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431653 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  431656 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431678 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431688 */   GIR_RootConstrainSelectedInstOperands,
     /*  431689 */   // GIR_Coverage, 25745,
     /*  431689 */   GIR_EraseRootFromParent_Done,
     /*  431690 */ // Label 6524: @431690
     /*  431690 */ GIM_Try, /*On fail goto*//*Label 6525*/ GIMT_Encode4(431765), // Rule ID 25751 //
     /*  431695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  431698 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431701 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431705 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431712 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431717 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431721 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431728 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  431731 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431753 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431756 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431759 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431763 */   GIR_RootConstrainSelectedInstOperands,
     /*  431764 */   // GIR_Coverage, 25751,
     /*  431764 */   GIR_EraseRootFromParent_Done,
     /*  431765 */ // Label 6525: @431765
     /*  431765 */ GIM_Try, /*On fail goto*//*Label 6526*/ GIMT_Encode4(431840), // Rule ID 25752 //
     /*  431770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  431773 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431776 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431780 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431787 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431792 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431796 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431803 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431803 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  431806 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431828 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431831 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431834 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431838 */   GIR_RootConstrainSelectedInstOperands,
     /*  431839 */   // GIR_Coverage, 25752,
     /*  431839 */   GIR_EraseRootFromParent_Done,
     /*  431840 */ // Label 6526: @431840
     /*  431840 */ GIM_Try, /*On fail goto*//*Label 6527*/ GIMT_Encode4(431915), // Rule ID 25753 //
     /*  431845 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  431848 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431851 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431855 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431862 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431867 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431871 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431878 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  431881 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431903 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431906 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431909 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431913 */   GIR_RootConstrainSelectedInstOperands,
     /*  431914 */   // GIR_Coverage, 25753,
     /*  431914 */   GIR_EraseRootFromParent_Done,
     /*  431915 */ // Label 6527: @431915
     /*  431915 */ GIM_Try, /*On fail goto*//*Label 6528*/ GIMT_Encode4(431990), // Rule ID 25754 //
     /*  431920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  431923 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  431926 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  431930 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  431937 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  431942 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  431946 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  431953 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  431953 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  431956 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  431958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  431963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  431968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  431973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  431978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  431984 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  431988 */   GIR_RootConstrainSelectedInstOperands,
     /*  431989 */   // GIR_Coverage, 25754,
     /*  431989 */   GIR_EraseRootFromParent_Done,
     /*  431990 */ // Label 6528: @431990
     /*  431990 */ GIM_Try, /*On fail goto*//*Label 6529*/ GIMT_Encode4(432065), // Rule ID 25755 //
     /*  431995 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  431998 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432001 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  432005 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  432012 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432017 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432021 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432028 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432028 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  432031 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432053 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432059 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432063 */   GIR_RootConstrainSelectedInstOperands,
     /*  432064 */   // GIR_Coverage, 25755,
     /*  432064 */   GIR_EraseRootFromParent_Done,
     /*  432065 */ // Label 6529: @432065
     /*  432065 */ GIM_Try, /*On fail goto*//*Label 6530*/ GIMT_Encode4(432129), // Rule ID 25761 //
     /*  432070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  432073 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432076 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432081 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432085 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432092 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432092 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  432095 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432120 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432123 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432127 */   GIR_RootConstrainSelectedInstOperands,
     /*  432128 */   // GIR_Coverage, 25761,
     /*  432128 */   GIR_EraseRootFromParent_Done,
     /*  432129 */ // Label 6530: @432129
     /*  432129 */ GIM_Try, /*On fail goto*//*Label 6531*/ GIMT_Encode4(432193), // Rule ID 25762 //
     /*  432134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  432137 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432140 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432145 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432149 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432156 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432156 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  432159 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432181 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432191 */   GIR_RootConstrainSelectedInstOperands,
     /*  432192 */   // GIR_Coverage, 25762,
     /*  432192 */   GIR_EraseRootFromParent_Done,
     /*  432193 */ // Label 6531: @432193
     /*  432193 */ GIM_Try, /*On fail goto*//*Label 6532*/ GIMT_Encode4(432257), // Rule ID 25763 //
     /*  432198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  432201 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432204 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432209 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432213 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432220 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  432223 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432245 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432248 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432251 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432255 */   GIR_RootConstrainSelectedInstOperands,
     /*  432256 */   // GIR_Coverage, 25763,
     /*  432256 */   GIR_EraseRootFromParent_Done,
     /*  432257 */ // Label 6532: @432257
     /*  432257 */ GIM_Try, /*On fail goto*//*Label 6533*/ GIMT_Encode4(432321), // Rule ID 25764 //
     /*  432262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  432265 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432268 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432277 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432284 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  432287 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432309 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432315 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432319 */   GIR_RootConstrainSelectedInstOperands,
     /*  432320 */   // GIR_Coverage, 25764,
     /*  432320 */   GIR_EraseRootFromParent_Done,
     /*  432321 */ // Label 6533: @432321
     /*  432321 */ GIM_Try, /*On fail goto*//*Label 6534*/ GIMT_Encode4(432385), // Rule ID 25765 //
     /*  432326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  432329 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432332 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432337 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432341 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432348 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  432351 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432373 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432376 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432383 */   GIR_RootConstrainSelectedInstOperands,
     /*  432384 */   // GIR_Coverage, 25765,
     /*  432384 */   GIR_EraseRootFromParent_Done,
     /*  432385 */ // Label 6534: @432385
     /*  432385 */ GIM_Try, /*On fail goto*//*Label 6535*/ GIMT_Encode4(432449), // Rule ID 25771 //
     /*  432390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  432393 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432396 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432412 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  432415 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432447 */   GIR_RootConstrainSelectedInstOperands,
     /*  432448 */   // GIR_Coverage, 25771,
     /*  432448 */   GIR_EraseRootFromParent_Done,
     /*  432449 */ // Label 6535: @432449
     /*  432449 */ GIM_Try, /*On fail goto*//*Label 6536*/ GIMT_Encode4(432513), // Rule ID 25772 //
     /*  432454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  432457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432460 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432476 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  432479 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432501 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432504 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432507 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432511 */   GIR_RootConstrainSelectedInstOperands,
     /*  432512 */   // GIR_Coverage, 25772,
     /*  432512 */   GIR_EraseRootFromParent_Done,
     /*  432513 */ // Label 6536: @432513
     /*  432513 */ GIM_Try, /*On fail goto*//*Label 6537*/ GIMT_Encode4(432577), // Rule ID 25773 //
     /*  432518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  432521 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432524 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432540 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  432543 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432565 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432571 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432575 */   GIR_RootConstrainSelectedInstOperands,
     /*  432576 */   // GIR_Coverage, 25773,
     /*  432576 */   GIR_EraseRootFromParent_Done,
     /*  432577 */ // Label 6537: @432577
     /*  432577 */ GIM_Try, /*On fail goto*//*Label 6538*/ GIMT_Encode4(432641), // Rule ID 25774 //
     /*  432582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  432585 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432588 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432593 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432597 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432604 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432604 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  432607 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432629 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432635 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432639 */   GIR_RootConstrainSelectedInstOperands,
     /*  432640 */   // GIR_Coverage, 25774,
     /*  432640 */   GIR_EraseRootFromParent_Done,
     /*  432641 */ // Label 6538: @432641
     /*  432641 */ GIM_Try, /*On fail goto*//*Label 6539*/ GIMT_Encode4(432705), // Rule ID 25775 //
     /*  432646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  432649 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432652 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  432657 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432661 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  432668 */   // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  432668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  432671 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  432673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  432678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  432688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  432693 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432696 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432699 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432703 */   GIR_RootConstrainSelectedInstOperands,
     /*  432704 */   // GIR_Coverage, 25775,
     /*  432704 */   GIR_EraseRootFromParent_Done,
     /*  432705 */ // Label 6539: @432705
     /*  432705 */ GIM_Try, /*On fail goto*//*Label 6540*/ GIMT_Encode4(432777), // Rule ID 25681 //
     /*  432710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  432713 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432716 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  432720 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  432727 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  432734 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432738 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  432745 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  432745 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  432748 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  432750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  432760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  432765 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432771 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432775 */   GIR_RootConstrainSelectedInstOperands,
     /*  432776 */   // GIR_Coverage, 25681,
     /*  432776 */   GIR_EraseRootFromParent_Done,
     /*  432777 */ // Label 6540: @432777
     /*  432777 */ GIM_Try, /*On fail goto*//*Label 6541*/ GIMT_Encode4(432849), // Rule ID 25682 //
     /*  432782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  432785 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432788 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  432792 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  432799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  432806 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432810 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  432817 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  432817 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  432820 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  432822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  432832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  432837 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432843 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432847 */   GIR_RootConstrainSelectedInstOperands,
     /*  432848 */   // GIR_Coverage, 25682,
     /*  432848 */   GIR_EraseRootFromParent_Done,
     /*  432849 */ // Label 6541: @432849
     /*  432849 */ GIM_Try, /*On fail goto*//*Label 6542*/ GIMT_Encode4(432921), // Rule ID 25683 //
     /*  432854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  432857 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432860 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  432864 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  432871 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  432878 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432882 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  432889 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  432889 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  432892 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  432894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  432904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  432909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432912 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432915 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432919 */   GIR_RootConstrainSelectedInstOperands,
     /*  432920 */   // GIR_Coverage, 25683,
     /*  432920 */   GIR_EraseRootFromParent_Done,
     /*  432921 */ // Label 6542: @432921
     /*  432921 */ GIM_Try, /*On fail goto*//*Label 6543*/ GIMT_Encode4(432993), // Rule ID 25684 //
     /*  432926 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  432929 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  432932 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  432936 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  432943 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  432950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  432954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  432961 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  432961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  432964 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  432966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  432971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  432976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  432981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  432987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  432991 */   GIR_RootConstrainSelectedInstOperands,
     /*  432992 */   // GIR_Coverage, 25684,
     /*  432992 */   GIR_EraseRootFromParent_Done,
     /*  432993 */ // Label 6543: @432993
     /*  432993 */ GIM_Try, /*On fail goto*//*Label 6544*/ GIMT_Encode4(433065), // Rule ID 25685 //
     /*  432998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  433001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433004 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  433008 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  433015 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433022 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433026 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433033 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433033 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  433036 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433053 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433059 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433063 */   GIR_RootConstrainSelectedInstOperands,
     /*  433064 */   // GIR_Coverage, 25685,
     /*  433064 */   GIR_EraseRootFromParent_Done,
     /*  433065 */ // Label 6544: @433065
     /*  433065 */ GIM_Try, /*On fail goto*//*Label 6545*/ GIMT_Encode4(433137), // Rule ID 25686 //
     /*  433070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  433073 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433076 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  433080 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  433087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433105 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  433108 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433125 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433128 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433131 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433135 */   GIR_RootConstrainSelectedInstOperands,
     /*  433136 */   // GIR_Coverage, 25686,
     /*  433136 */   GIR_EraseRootFromParent_Done,
     /*  433137 */ // Label 6545: @433137
     /*  433137 */ GIM_Try, /*On fail goto*//*Label 6546*/ GIMT_Encode4(433209), // Rule ID 25687 //
     /*  433142 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  433145 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433148 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  433152 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  433159 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433166 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433170 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433177 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433177 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  433180 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433197 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433203 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433207 */   GIR_RootConstrainSelectedInstOperands,
     /*  433208 */   // GIR_Coverage, 25687,
     /*  433208 */   GIR_EraseRootFromParent_Done,
     /*  433209 */ // Label 6546: @433209
     /*  433209 */ GIM_Try, /*On fail goto*//*Label 6547*/ GIMT_Encode4(433281), // Rule ID 25688 //
     /*  433214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  433217 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433220 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  433224 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  433231 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433238 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433249 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  433252 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433279 */   GIR_RootConstrainSelectedInstOperands,
     /*  433280 */   // GIR_Coverage, 25688,
     /*  433280 */   GIR_EraseRootFromParent_Done,
     /*  433281 */ // Label 6547: @433281
     /*  433281 */ GIM_Try, /*On fail goto*//*Label 6548*/ GIMT_Encode4(433353), // Rule ID 25689 //
     /*  433286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  433289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433292 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  433296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  433303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433321 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433321 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  433324 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433344 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433351 */   GIR_RootConstrainSelectedInstOperands,
     /*  433352 */   // GIR_Coverage, 25689,
     /*  433352 */   GIR_EraseRootFromParent_Done,
     /*  433353 */ // Label 6548: @433353
     /*  433353 */ GIM_Try, /*On fail goto*//*Label 6549*/ GIMT_Encode4(433425), // Rule ID 25690 //
     /*  433358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  433361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433364 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  433368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  433375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433382 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433393 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  433396 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433413 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433416 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433419 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433423 */   GIR_RootConstrainSelectedInstOperands,
     /*  433424 */   // GIR_Coverage, 25690,
     /*  433424 */   GIR_EraseRootFromParent_Done,
     /*  433425 */ // Label 6549: @433425
     /*  433425 */ GIM_Try, /*On fail goto*//*Label 6550*/ GIMT_Encode4(433486), // Rule ID 25691 //
     /*  433430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  433433 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433436 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433443 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433447 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433454 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433454 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  433457 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433474 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433477 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433480 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433484 */   GIR_RootConstrainSelectedInstOperands,
     /*  433485 */   // GIR_Coverage, 25691,
     /*  433485 */   GIR_EraseRootFromParent_Done,
     /*  433486 */ // Label 6550: @433486
     /*  433486 */ GIM_Try, /*On fail goto*//*Label 6551*/ GIMT_Encode4(433547), // Rule ID 25692 //
     /*  433491 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  433494 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433497 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433515 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  433518 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433535 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433538 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433541 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433545 */   GIR_RootConstrainSelectedInstOperands,
     /*  433546 */   // GIR_Coverage, 25692,
     /*  433546 */   GIR_EraseRootFromParent_Done,
     /*  433547 */ // Label 6551: @433547
     /*  433547 */ GIM_Try, /*On fail goto*//*Label 6552*/ GIMT_Encode4(433608), // Rule ID 25693 //
     /*  433552 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  433555 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433558 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433569 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433576 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433576 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  433579 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433606 */   GIR_RootConstrainSelectedInstOperands,
     /*  433607 */   // GIR_Coverage, 25693,
     /*  433607 */   GIR_EraseRootFromParent_Done,
     /*  433608 */ // Label 6552: @433608
     /*  433608 */ GIM_Try, /*On fail goto*//*Label 6553*/ GIMT_Encode4(433669), // Rule ID 25694 //
     /*  433613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  433616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433626 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433630 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433637 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  433640 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433657 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433660 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433667 */   GIR_RootConstrainSelectedInstOperands,
     /*  433668 */   // GIR_Coverage, 25694,
     /*  433668 */   GIR_EraseRootFromParent_Done,
     /*  433669 */ // Label 6553: @433669
     /*  433669 */ GIM_Try, /*On fail goto*//*Label 6554*/ GIMT_Encode4(433730), // Rule ID 25695 //
     /*  433674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  433677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433687 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433691 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433698 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  433701 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433718 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433724 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433728 */   GIR_RootConstrainSelectedInstOperands,
     /*  433729 */   // GIR_Coverage, 25695,
     /*  433729 */   GIR_EraseRootFromParent_Done,
     /*  433730 */ // Label 6554: @433730
     /*  433730 */ GIM_Try, /*On fail goto*//*Label 6555*/ GIMT_Encode4(433791), // Rule ID 25696 //
     /*  433735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  433738 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433741 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433759 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  433762 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433789 */   GIR_RootConstrainSelectedInstOperands,
     /*  433790 */   // GIR_Coverage, 25696,
     /*  433790 */   GIR_EraseRootFromParent_Done,
     /*  433791 */ // Label 6555: @433791
     /*  433791 */ GIM_Try, /*On fail goto*//*Label 6556*/ GIMT_Encode4(433852), // Rule ID 25697 //
     /*  433796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  433799 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433820 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  433823 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433843 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433846 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433850 */   GIR_RootConstrainSelectedInstOperands,
     /*  433851 */   // GIR_Coverage, 25697,
     /*  433851 */   GIR_EraseRootFromParent_Done,
     /*  433852 */ // Label 6556: @433852
     /*  433852 */ GIM_Try, /*On fail goto*//*Label 6557*/ GIMT_Encode4(433913), // Rule ID 25698 //
     /*  433857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  433860 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433881 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  433884 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433901 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433904 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433907 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433911 */   GIR_RootConstrainSelectedInstOperands,
     /*  433912 */   // GIR_Coverage, 25698,
     /*  433912 */   GIR_EraseRootFromParent_Done,
     /*  433913 */ // Label 6557: @433913
     /*  433913 */ GIM_Try, /*On fail goto*//*Label 6558*/ GIMT_Encode4(433974), // Rule ID 25699 //
     /*  433918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  433921 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433924 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433931 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433935 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  433942 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  433942 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  433945 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  433947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  433952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  433957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  433962 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433965 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  433968 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  433972 */   GIR_RootConstrainSelectedInstOperands,
     /*  433973 */   // GIR_Coverage, 25699,
     /*  433973 */   GIR_EraseRootFromParent_Done,
     /*  433974 */ // Label 6558: @433974
     /*  433974 */ GIM_Try, /*On fail goto*//*Label 6559*/ GIMT_Encode4(434035), // Rule ID 25700 //
     /*  433979 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  433982 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  433985 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  433992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  433996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  434003 */   // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  434003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  434006 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  434008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  434013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  434018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  434023 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434026 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434029 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434033 */   GIR_RootConstrainSelectedInstOperands,
     /*  434034 */   // GIR_Coverage, 25700,
     /*  434034 */   GIR_EraseRootFromParent_Done,
     /*  434035 */ // Label 6559: @434035
     /*  434035 */ GIM_Try, /*On fail goto*//*Label 6560*/ GIMT_Encode4(434093), // Rule ID 29303 //
     /*  434040 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  434043 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434046 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434062 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434069 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434069 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  434072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434077 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434084 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434087 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434091 */   GIR_RootConstrainSelectedInstOperands,
     /*  434092 */   // GIR_Coverage, 29303,
     /*  434092 */   GIR_EraseRootFromParent_Done,
     /*  434093 */ // Label 6560: @434093
     /*  434093 */ GIM_Try, /*On fail goto*//*Label 6561*/ GIMT_Encode4(434151), // Rule ID 29304 //
     /*  434098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  434101 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434104 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434111 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434116 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434120 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434127 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  434130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434135 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434142 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434145 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434149 */   GIR_RootConstrainSelectedInstOperands,
     /*  434150 */   // GIR_Coverage, 29304,
     /*  434150 */   GIR_EraseRootFromParent_Done,
     /*  434151 */ // Label 6561: @434151
     /*  434151 */ GIM_Try, /*On fail goto*//*Label 6562*/ GIMT_Encode4(434209), // Rule ID 29305 //
     /*  434156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  434159 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434162 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434169 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434174 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434178 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434185 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434185 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  434188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434193 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434203 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434207 */   GIR_RootConstrainSelectedInstOperands,
     /*  434208 */   // GIR_Coverage, 29305,
     /*  434208 */   GIR_EraseRootFromParent_Done,
     /*  434209 */ // Label 6562: @434209
     /*  434209 */ GIM_Try, /*On fail goto*//*Label 6563*/ GIMT_Encode4(434267), // Rule ID 29306 //
     /*  434214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  434217 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434220 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434227 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434232 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434236 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434243 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  434246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434251 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434258 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434261 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434265 */   GIR_RootConstrainSelectedInstOperands,
     /*  434266 */   // GIR_Coverage, 29306,
     /*  434266 */   GIR_EraseRootFromParent_Done,
     /*  434267 */ // Label 6563: @434267
     /*  434267 */ GIM_Try, /*On fail goto*//*Label 6564*/ GIMT_Encode4(434325), // Rule ID 29307 //
     /*  434272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  434275 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434278 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434285 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434290 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434294 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434301 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434301 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  434304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434309 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434316 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434319 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434323 */   GIR_RootConstrainSelectedInstOperands,
     /*  434324 */   // GIR_Coverage, 29307,
     /*  434324 */   GIR_EraseRootFromParent_Done,
     /*  434325 */ // Label 6564: @434325
     /*  434325 */ GIM_Try, /*On fail goto*//*Label 6565*/ GIMT_Encode4(434383), // Rule ID 29308 //
     /*  434330 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  434333 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434336 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434343 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434359 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  434362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434367 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434374 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434377 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434381 */   GIR_RootConstrainSelectedInstOperands,
     /*  434382 */   // GIR_Coverage, 29308,
     /*  434382 */   GIR_EraseRootFromParent_Done,
     /*  434383 */ // Label 6565: @434383
     /*  434383 */ GIM_Try, /*On fail goto*//*Label 6566*/ GIMT_Encode4(434441), // Rule ID 29309 //
     /*  434388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  434391 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434394 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434401 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434406 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434410 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434417 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434417 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  434420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434425 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434432 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434435 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434439 */   GIR_RootConstrainSelectedInstOperands,
     /*  434440 */   // GIR_Coverage, 29309,
     /*  434440 */   GIR_EraseRootFromParent_Done,
     /*  434441 */ // Label 6566: @434441
     /*  434441 */ GIM_Try, /*On fail goto*//*Label 6567*/ GIMT_Encode4(434499), // Rule ID 29310 //
     /*  434446 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  434449 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434452 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434459 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434464 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434468 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434475 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434475 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  434478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434483 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434490 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434493 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434497 */   GIR_RootConstrainSelectedInstOperands,
     /*  434498 */   // GIR_Coverage, 29310,
     /*  434498 */   GIR_EraseRootFromParent_Done,
     /*  434499 */ // Label 6567: @434499
     /*  434499 */ GIM_Try, /*On fail goto*//*Label 6568*/ GIMT_Encode4(434557), // Rule ID 29311 //
     /*  434504 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  434507 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434510 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434517 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434522 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434526 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434533 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434533 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  434536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434541 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434548 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434551 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434555 */   GIR_RootConstrainSelectedInstOperands,
     /*  434556 */   // GIR_Coverage, 29311,
     /*  434556 */   GIR_EraseRootFromParent_Done,
     /*  434557 */ // Label 6568: @434557
     /*  434557 */ GIM_Try, /*On fail goto*//*Label 6569*/ GIMT_Encode4(434615), // Rule ID 29312 //
     /*  434562 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  434565 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434568 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434575 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434591 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  434594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434599 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434606 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434613 */   GIR_RootConstrainSelectedInstOperands,
     /*  434614 */   // GIR_Coverage, 29312,
     /*  434614 */   GIR_EraseRootFromParent_Done,
     /*  434615 */ // Label 6569: @434615
     /*  434615 */ GIM_Try, /*On fail goto*//*Label 6570*/ GIMT_Encode4(434673), // Rule ID 29313 //
     /*  434620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  434623 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  434633 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434638 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434642 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434649 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_t16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434649 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_t16),
     /*  434652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434657 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434664 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434667 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434671 */   GIR_RootConstrainSelectedInstOperands,
     /*  434672 */   // GIR_Coverage, 29313,
     /*  434672 */   GIR_EraseRootFromParent_Done,
     /*  434673 */ // Label 6570: @434673
     /*  434673 */ GIM_Try, /*On fail goto*//*Label 6571*/ GIMT_Encode4(434731), // Rule ID 29324 //
     /*  434678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  434681 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434684 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  434691 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434696 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434700 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434707 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434707 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  434710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434715 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434722 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434729 */   GIR_RootConstrainSelectedInstOperands,
     /*  434730 */   // GIR_Coverage, 29324,
     /*  434730 */   GIR_EraseRootFromParent_Done,
     /*  434731 */ // Label 6571: @434731
     /*  434731 */ GIM_Try, /*On fail goto*//*Label 6572*/ GIMT_Encode4(434789), // Rule ID 29325 //
     /*  434736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  434739 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434742 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  434749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434754 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434758 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434765 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434765 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  434768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434773 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434783 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434787 */   GIR_RootConstrainSelectedInstOperands,
     /*  434788 */   // GIR_Coverage, 29325,
     /*  434788 */   GIR_EraseRootFromParent_Done,
     /*  434789 */ // Label 6572: @434789
     /*  434789 */ GIM_Try, /*On fail goto*//*Label 6573*/ GIMT_Encode4(434847), // Rule ID 29326 //
     /*  434794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  434797 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434800 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  434807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434812 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434816 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434823 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434823 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  434826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434831 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434838 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434841 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434845 */   GIR_RootConstrainSelectedInstOperands,
     /*  434846 */   // GIR_Coverage, 29326,
     /*  434846 */   GIR_EraseRootFromParent_Done,
     /*  434847 */ // Label 6573: @434847
     /*  434847 */ GIM_Try, /*On fail goto*//*Label 6574*/ GIMT_Encode4(434905), // Rule ID 29327 //
     /*  434852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  434855 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434858 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  434865 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434881 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  434884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434889 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434903 */   GIR_RootConstrainSelectedInstOperands,
     /*  434904 */   // GIR_Coverage, 29327,
     /*  434904 */   GIR_EraseRootFromParent_Done,
     /*  434905 */ // Label 6574: @434905
     /*  434905 */ GIM_Try, /*On fail goto*//*Label 6575*/ GIMT_Encode4(434963), // Rule ID 29328 //
     /*  434910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  434913 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  434923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434928 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434932 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434939 */   // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434939 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  434942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  434947 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  434949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  434954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  434957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  434961 */   GIR_RootConstrainSelectedInstOperands,
     /*  434962 */   // GIR_Coverage, 29328,
     /*  434962 */   GIR_EraseRootFromParent_Done,
     /*  434963 */ // Label 6575: @434963
     /*  434963 */ GIM_Try, /*On fail goto*//*Label 6576*/ GIMT_Encode4(435021), // Rule ID 29329 //
     /*  434968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  434971 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  434974 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  434981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  434986 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  434990 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  434997 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  434997 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  435000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435005 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435012 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435015 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435019 */   GIR_RootConstrainSelectedInstOperands,
     /*  435020 */   // GIR_Coverage, 29329,
     /*  435020 */   GIR_EraseRootFromParent_Done,
     /*  435021 */ // Label 6576: @435021
     /*  435021 */ GIM_Try, /*On fail goto*//*Label 6577*/ GIMT_Encode4(435079), // Rule ID 29330 //
     /*  435026 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  435029 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  435032 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  435039 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435044 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435048 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435055 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435055 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  435058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435063 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435070 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435073 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435077 */   GIR_RootConstrainSelectedInstOperands,
     /*  435078 */   // GIR_Coverage, 29330,
     /*  435078 */   GIR_EraseRootFromParent_Done,
     /*  435079 */ // Label 6577: @435079
     /*  435079 */ GIM_Try, /*On fail goto*//*Label 6578*/ GIMT_Encode4(435137), // Rule ID 29331 //
     /*  435084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  435087 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  435090 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  435097 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435102 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435106 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435113 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  435116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435121 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435128 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435131 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435135 */   GIR_RootConstrainSelectedInstOperands,
     /*  435136 */   // GIR_Coverage, 29331,
     /*  435136 */   GIR_EraseRootFromParent_Done,
     /*  435137 */ // Label 6578: @435137
     /*  435137 */ GIM_Try, /*On fail goto*//*Label 6579*/ GIMT_Encode4(435195), // Rule ID 29332 //
     /*  435142 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  435145 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  435148 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  435155 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435160 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435164 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435171 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  435174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435179 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435186 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435189 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435193 */   GIR_RootConstrainSelectedInstOperands,
     /*  435194 */   // GIR_Coverage, 29332,
     /*  435194 */   GIR_EraseRootFromParent_Done,
     /*  435195 */ // Label 6579: @435195
     /*  435195 */ GIM_Try, /*On fail goto*//*Label 6580*/ GIMT_Encode4(435253), // Rule ID 29333 //
     /*  435200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  435203 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  435206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  435213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435229 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  435232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435237 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435251 */   GIR_RootConstrainSelectedInstOperands,
     /*  435252 */   // GIR_Coverage, 29333,
     /*  435252 */   GIR_EraseRootFromParent_Done,
     /*  435253 */ // Label 6580: @435253
     /*  435253 */ GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(435311), // Rule ID 29334 //
     /*  435258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  435261 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  435264 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  435271 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435276 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435280 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435287 */   // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_t16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435287 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_t16),
     /*  435290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435295 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435302 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435309 */   GIR_RootConstrainSelectedInstOperands,
     /*  435310 */   // GIR_Coverage, 29334,
     /*  435310 */   GIR_EraseRootFromParent_Done,
     /*  435311 */ // Label 6581: @435311
     /*  435311 */ GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(435373), // Rule ID 29191 //
     /*  435316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  435319 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435322 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435326 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435338 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435342 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435349 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  435352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435357 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435364 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435367 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435371 */   GIR_RootConstrainSelectedInstOperands,
     /*  435372 */   // GIR_Coverage, 29191,
     /*  435372 */   GIR_EraseRootFromParent_Done,
     /*  435373 */ // Label 6582: @435373
     /*  435373 */ GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(435435), // Rule ID 29192 //
     /*  435378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  435381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435384 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435388 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435400 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435404 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435411 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  435414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435419 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435426 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435429 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435433 */   GIR_RootConstrainSelectedInstOperands,
     /*  435434 */   // GIR_Coverage, 29192,
     /*  435434 */   GIR_EraseRootFromParent_Done,
     /*  435435 */ // Label 6583: @435435
     /*  435435 */ GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(435497), // Rule ID 29193 //
     /*  435440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  435443 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435446 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435450 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435457 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435462 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435466 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435473 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  435476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435481 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435488 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435491 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435495 */   GIR_RootConstrainSelectedInstOperands,
     /*  435496 */   // GIR_Coverage, 29193,
     /*  435496 */   GIR_EraseRootFromParent_Done,
     /*  435497 */ // Label 6584: @435497
     /*  435497 */ GIM_Try, /*On fail goto*//*Label 6585*/ GIMT_Encode4(435559), // Rule ID 29194 //
     /*  435502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  435505 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435508 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435512 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435535 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  435538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435543 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435557 */   GIR_RootConstrainSelectedInstOperands,
     /*  435558 */   // GIR_Coverage, 29194,
     /*  435558 */   GIR_EraseRootFromParent_Done,
     /*  435559 */ // Label 6585: @435559
     /*  435559 */ GIM_Try, /*On fail goto*//*Label 6586*/ GIMT_Encode4(435621), // Rule ID 29195 //
     /*  435564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  435567 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435570 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435574 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435581 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435597 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  435600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435605 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435619 */   GIR_RootConstrainSelectedInstOperands,
     /*  435620 */   // GIR_Coverage, 29195,
     /*  435620 */   GIR_EraseRootFromParent_Done,
     /*  435621 */ // Label 6586: @435621
     /*  435621 */ GIM_Try, /*On fail goto*//*Label 6587*/ GIMT_Encode4(435683), // Rule ID 29196 //
     /*  435626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  435629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435632 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435636 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435648 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435652 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435659 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  435662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435667 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435674 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435677 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435681 */   GIR_RootConstrainSelectedInstOperands,
     /*  435682 */   // GIR_Coverage, 29196,
     /*  435682 */   GIR_EraseRootFromParent_Done,
     /*  435683 */ // Label 6587: @435683
     /*  435683 */ GIM_Try, /*On fail goto*//*Label 6588*/ GIMT_Encode4(435745), // Rule ID 29197 //
     /*  435688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  435691 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435694 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435698 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435705 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435710 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435714 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435721 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  435724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435729 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435736 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435739 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435743 */   GIR_RootConstrainSelectedInstOperands,
     /*  435744 */   // GIR_Coverage, 29197,
     /*  435744 */   GIR_EraseRootFromParent_Done,
     /*  435745 */ // Label 6588: @435745
     /*  435745 */ GIM_Try, /*On fail goto*//*Label 6589*/ GIMT_Encode4(435807), // Rule ID 29198 //
     /*  435750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  435753 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435756 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435760 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435772 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435776 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435783 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  435786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435791 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435805 */   GIR_RootConstrainSelectedInstOperands,
     /*  435806 */   // GIR_Coverage, 29198,
     /*  435806 */   GIR_EraseRootFromParent_Done,
     /*  435807 */ // Label 6589: @435807
     /*  435807 */ GIM_Try, /*On fail goto*//*Label 6590*/ GIMT_Encode4(435869), // Rule ID 29199 //
     /*  435812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  435815 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435818 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435845 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  435848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435853 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435867 */   GIR_RootConstrainSelectedInstOperands,
     /*  435868 */   // GIR_Coverage, 29199,
     /*  435868 */   GIR_EraseRootFromParent_Done,
     /*  435869 */ // Label 6590: @435869
     /*  435869 */ GIM_Try, /*On fail goto*//*Label 6591*/ GIMT_Encode4(435931), // Rule ID 29200 //
     /*  435874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  435877 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435880 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435884 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435891 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435907 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  435910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435915 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435929 */   GIR_RootConstrainSelectedInstOperands,
     /*  435930 */   // GIR_Coverage, 29200,
     /*  435930 */   GIR_EraseRootFromParent_Done,
     /*  435931 */ // Label 6591: @435931
     /*  435931 */ GIM_Try, /*On fail goto*//*Label 6592*/ GIMT_Encode4(435993), // Rule ID 29201 //
     /*  435936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  435939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  435942 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  435946 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  435953 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  435958 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  435962 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  435969 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_t16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  435969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_t16),
     /*  435972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  435977 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  435979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  435984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  435987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  435991 */   GIR_RootConstrainSelectedInstOperands,
     /*  435992 */   // GIR_Coverage, 29201,
     /*  435992 */   GIR_EraseRootFromParent_Done,
     /*  435993 */ // Label 6592: @435993
     /*  435993 */ GIM_Try, /*On fail goto*//*Label 6593*/ GIMT_Encode4(436048), // Rule ID 29212 //
     /*  435998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  436001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436004 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  436008 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436024 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  436027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436032 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436046 */   GIR_RootConstrainSelectedInstOperands,
     /*  436047 */   // GIR_Coverage, 29212,
     /*  436047 */   GIR_EraseRootFromParent_Done,
     /*  436048 */ // Label 6593: @436048
     /*  436048 */ GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(436103), // Rule ID 29213 //
     /*  436053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  436056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436059 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  436063 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436079 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  436082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436087 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436094 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436097 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436101 */   GIR_RootConstrainSelectedInstOperands,
     /*  436102 */   // GIR_Coverage, 29213,
     /*  436102 */   GIR_EraseRootFromParent_Done,
     /*  436103 */ // Label 6594: @436103
     /*  436103 */ GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(436158), // Rule ID 29214 //
     /*  436108 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  436111 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436114 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  436118 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436123 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436127 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436134 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  436137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436142 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436149 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436152 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436156 */   GIR_RootConstrainSelectedInstOperands,
     /*  436157 */   // GIR_Coverage, 29214,
     /*  436157 */   GIR_EraseRootFromParent_Done,
     /*  436158 */ // Label 6595: @436158
     /*  436158 */ GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(436213), // Rule ID 29215 //
     /*  436163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  436166 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436169 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  436173 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436178 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436182 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436189 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436189 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  436192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436197 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436204 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436207 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436211 */   GIR_RootConstrainSelectedInstOperands,
     /*  436212 */   // GIR_Coverage, 29215,
     /*  436212 */   GIR_EraseRootFromParent_Done,
     /*  436213 */ // Label 6596: @436213
     /*  436213 */ GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(436268), // Rule ID 29216 //
     /*  436218 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  436221 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436224 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  436228 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436244 */   // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  436247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436252 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436266 */   GIR_RootConstrainSelectedInstOperands,
     /*  436267 */   // GIR_Coverage, 29216,
     /*  436267 */   GIR_EraseRootFromParent_Done,
     /*  436268 */ // Label 6597: @436268
     /*  436268 */ GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(436319), // Rule ID 29217 //
     /*  436273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode0),
     /*  436276 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436284 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436288 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436295 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  436298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436303 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436310 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436313 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436317 */   GIR_RootConstrainSelectedInstOperands,
     /*  436318 */   // GIR_Coverage, 29217,
     /*  436318 */   GIR_EraseRootFromParent_Done,
     /*  436319 */ // Label 6598: @436319
     /*  436319 */ GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(436370), // Rule ID 29218 //
     /*  436324 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode1),
     /*  436327 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436330 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436335 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436339 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436346 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  436349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436354 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436361 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436364 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436368 */   GIR_RootConstrainSelectedInstOperands,
     /*  436369 */   // GIR_Coverage, 29218,
     /*  436369 */   GIR_EraseRootFromParent_Done,
     /*  436370 */ // Label 6599: @436370
     /*  436370 */ GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(436421), // Rule ID 29219 //
     /*  436375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode2),
     /*  436378 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436381 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436386 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436390 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436397 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436397 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  436400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436405 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436412 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436415 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436419 */   GIR_RootConstrainSelectedInstOperands,
     /*  436420 */   // GIR_Coverage, 29219,
     /*  436420 */   GIR_EraseRootFromParent_Done,
     /*  436421 */ // Label 6600: @436421
     /*  436421 */ GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(436472), // Rule ID 29220 //
     /*  436426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode3),
     /*  436429 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436432 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436448 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  436451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436456 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436463 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436466 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436470 */   GIR_RootConstrainSelectedInstOperands,
     /*  436471 */   // GIR_Coverage, 29220,
     /*  436471 */   GIR_EraseRootFromParent_Done,
     /*  436472 */ // Label 6601: @436472
     /*  436472 */ GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(436523), // Rule ID 29221 //
     /*  436477 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_NotUseRealTrue16Insts_HwMode4),
     /*  436480 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436483 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436488 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436492 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436499 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  436502 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436507 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436514 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436517 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436521 */   GIR_RootConstrainSelectedInstOperands,
     /*  436522 */   // GIR_Coverage, 29221,
     /*  436522 */   GIR_EraseRootFromParent_Done,
     /*  436523 */ // Label 6602: @436523
     /*  436523 */ GIM_Try, /*On fail goto*//*Label 6603*/ GIMT_Encode4(436574), // Rule ID 29222 //
     /*  436528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_UseRealTrue16Insts),
     /*  436531 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  436534 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  436539 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436543 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  436550 */   // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_t16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  436550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_t16),
     /*  436553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  436558 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  436560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  436565 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  436568 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436572 */   GIR_RootConstrainSelectedInstOperands,
     /*  436573 */   // GIR_Coverage, 29222,
     /*  436573 */   GIR_EraseRootFromParent_Done,
     /*  436574 */ // Label 6603: @436574
     /*  436574 */ GIM_Try, /*On fail goto*//*Label 6604*/ GIMT_Encode4(436641), // Rule ID 12101 //
     /*  436579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  436582 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436585 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  436592 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  436599 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436603 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  436610 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  436610 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR_t16),
     /*  436613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  436618 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  436620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  436625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  436630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  436635 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436639 */   GIR_RootConstrainSelectedInstOperands,
     /*  436640 */   // GIR_Coverage, 12101,
     /*  436640 */   GIR_EraseRootFromParent_Done,
     /*  436641 */ // Label 6604: @436641
     /*  436641 */ GIM_Try, /*On fail goto*//*Label 6605*/ GIMT_Encode4(436708), // Rule ID 12107 //
     /*  436646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  436649 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436652 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  436659 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  436666 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436670 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  436677 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  436677 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR_t16),
     /*  436680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  436685 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  436687 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  436692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  436697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  436702 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436706 */   GIR_RootConstrainSelectedInstOperands,
     /*  436707 */   // GIR_Coverage, 12107,
     /*  436707 */   GIR_EraseRootFromParent_Done,
     /*  436708 */ // Label 6605: @436708
     /*  436708 */ GIM_Try, /*On fail goto*//*Label 6606*/ GIMT_Encode4(436775), // Rule ID 12663 //
     /*  436713 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  436716 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436719 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  436726 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  436733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436737 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  436744 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  436744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  436747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  436752 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  436754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  436759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  436764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  436769 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436773 */   GIR_RootConstrainSelectedInstOperands,
     /*  436774 */   // GIR_Coverage, 12663,
     /*  436774 */   GIR_EraseRootFromParent_Done,
     /*  436775 */ // Label 6606: @436775
     /*  436775 */ GIM_Try, /*On fail goto*//*Label 6607*/ GIMT_Encode4(436842), // Rule ID 12664 //
     /*  436780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  436783 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436786 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  436793 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  436800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436804 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  436811 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  436811 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  436814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  436819 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  436821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  436826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  436831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  436836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436840 */   GIR_RootConstrainSelectedInstOperands,
     /*  436841 */   // GIR_Coverage, 12664,
     /*  436841 */   GIR_EraseRootFromParent_Done,
     /*  436842 */ // Label 6607: @436842
     /*  436842 */ GIM_Try, /*On fail goto*//*Label 6608*/ GIMT_Encode4(436909), // Rule ID 12665 //
     /*  436847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  436850 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436853 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  436860 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  436867 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436871 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  436878 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  436878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  436881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  436886 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  436888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  436893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  436898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  436903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436907 */   GIR_RootConstrainSelectedInstOperands,
     /*  436908 */   // GIR_Coverage, 12665,
     /*  436908 */   GIR_EraseRootFromParent_Done,
     /*  436909 */ // Label 6608: @436909
     /*  436909 */ GIM_Try, /*On fail goto*//*Label 6609*/ GIMT_Encode4(436976), // Rule ID 12666 //
     /*  436914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  436917 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436920 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  436927 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  436934 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  436938 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  436945 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  436945 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  436948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  436953 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  436955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  436960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  436965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  436970 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  436974 */   GIR_RootConstrainSelectedInstOperands,
     /*  436975 */   // GIR_Coverage, 12666,
     /*  436975 */   GIR_EraseRootFromParent_Done,
     /*  436976 */ // Label 6609: @436976
     /*  436976 */ GIM_Try, /*On fail goto*//*Label 6610*/ GIMT_Encode4(437043), // Rule ID 12667 //
     /*  436981 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  436984 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  436987 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  436994 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437001 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437005 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437012 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437012 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  437015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437020 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437037 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437041 */   GIR_RootConstrainSelectedInstOperands,
     /*  437042 */   // GIR_Coverage, 12667,
     /*  437042 */   GIR_EraseRootFromParent_Done,
     /*  437043 */ // Label 6610: @437043
     /*  437043 */ GIM_Try, /*On fail goto*//*Label 6611*/ GIMT_Encode4(437110), // Rule ID 12673 //
     /*  437048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  437051 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437054 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  437061 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437079 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  437082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437087 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437104 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437108 */   GIR_RootConstrainSelectedInstOperands,
     /*  437109 */   // GIR_Coverage, 12673,
     /*  437109 */   GIR_EraseRootFromParent_Done,
     /*  437110 */ // Label 6611: @437110
     /*  437110 */ GIM_Try, /*On fail goto*//*Label 6612*/ GIMT_Encode4(437177), // Rule ID 12674 //
     /*  437115 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  437118 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437121 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  437128 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437135 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437139 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437146 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  437149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437154 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437171 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437175 */   GIR_RootConstrainSelectedInstOperands,
     /*  437176 */   // GIR_Coverage, 12674,
     /*  437176 */   GIR_EraseRootFromParent_Done,
     /*  437177 */ // Label 6612: @437177
     /*  437177 */ GIM_Try, /*On fail goto*//*Label 6613*/ GIMT_Encode4(437244), // Rule ID 12675 //
     /*  437182 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  437185 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437188 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  437195 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437213 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  437216 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437221 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437242 */   GIR_RootConstrainSelectedInstOperands,
     /*  437243 */   // GIR_Coverage, 12675,
     /*  437243 */   GIR_EraseRootFromParent_Done,
     /*  437244 */ // Label 6613: @437244
     /*  437244 */ GIM_Try, /*On fail goto*//*Label 6614*/ GIMT_Encode4(437311), // Rule ID 12676 //
     /*  437249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  437252 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437255 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  437262 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437269 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437273 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437280 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  437283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437288 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437309 */   GIR_RootConstrainSelectedInstOperands,
     /*  437310 */   // GIR_Coverage, 12676,
     /*  437310 */   GIR_EraseRootFromParent_Done,
     /*  437311 */ // Label 6614: @437311
     /*  437311 */ GIM_Try, /*On fail goto*//*Label 6615*/ GIMT_Encode4(437378), // Rule ID 12677 //
     /*  437316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  437319 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437322 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  437329 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437336 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437340 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437347 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  437350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437355 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437376 */   GIR_RootConstrainSelectedInstOperands,
     /*  437377 */   // GIR_Coverage, 12677,
     /*  437377 */   GIR_EraseRootFromParent_Done,
     /*  437378 */ // Label 6615: @437378
     /*  437378 */ GIM_Try, /*On fail goto*//*Label 6616*/ GIMT_Encode4(437445), // Rule ID 12695 //
     /*  437383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts),
     /*  437386 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437389 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437396 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437414 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR_t16),
     /*  437417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437422 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437439 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437443 */   GIR_RootConstrainSelectedInstOperands,
     /*  437444 */   // GIR_Coverage, 12695,
     /*  437444 */   GIR_EraseRootFromParent_Done,
     /*  437445 */ // Label 6616: @437445
     /*  437445 */ GIM_Try, /*On fail goto*//*Label 6617*/ GIMT_Encode4(437512), // Rule ID 12701 //
     /*  437450 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts),
     /*  437453 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  437456 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  437463 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437470 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437474 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437481 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437481 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR_t16),
     /*  437484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437489 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437506 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437510 */   GIR_RootConstrainSelectedInstOperands,
     /*  437511 */   // GIR_Coverage, 12701,
     /*  437511 */   GIR_EraseRootFromParent_Done,
     /*  437512 */ // Label 6617: @437512
     /*  437512 */ GIM_Try, /*On fail goto*//*Label 6618*/ GIMT_Encode4(437583), // Rule ID 9391 //
     /*  437517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  437520 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437523 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437527 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437534 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437541 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437545 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437552 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437552 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR_t16),
     /*  437555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437560 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437572 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437577 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437581 */   GIR_RootConstrainSelectedInstOperands,
     /*  437582 */   // GIR_Coverage, 9391,
     /*  437582 */   GIR_EraseRootFromParent_Done,
     /*  437583 */ // Label 6618: @437583
     /*  437583 */ GIM_Try, /*On fail goto*//*Label 6619*/ GIMT_Encode4(437654), // Rule ID 12643 //
     /*  437588 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  437591 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437594 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437598 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437605 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437616 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437623 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  437626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437631 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437648 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437652 */   GIR_RootConstrainSelectedInstOperands,
     /*  437653 */   // GIR_Coverage, 12643,
     /*  437653 */   GIR_EraseRootFromParent_Done,
     /*  437654 */ // Label 6619: @437654
     /*  437654 */ GIM_Try, /*On fail goto*//*Label 6620*/ GIMT_Encode4(437725), // Rule ID 12644 //
     /*  437659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  437662 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437665 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437669 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437676 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437683 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437687 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437694 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  437697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437702 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437719 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437723 */   GIR_RootConstrainSelectedInstOperands,
     /*  437724 */   // GIR_Coverage, 12644,
     /*  437724 */   GIR_EraseRootFromParent_Done,
     /*  437725 */ // Label 6620: @437725
     /*  437725 */ GIM_Try, /*On fail goto*//*Label 6621*/ GIMT_Encode4(437796), // Rule ID 12645 //
     /*  437730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  437733 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437736 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437740 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437747 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437754 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437758 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437765 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437765 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  437768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437773 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437790 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437794 */   GIR_RootConstrainSelectedInstOperands,
     /*  437795 */   // GIR_Coverage, 12645,
     /*  437795 */   GIR_EraseRootFromParent_Done,
     /*  437796 */ // Label 6621: @437796
     /*  437796 */ GIM_Try, /*On fail goto*//*Label 6622*/ GIMT_Encode4(437867), // Rule ID 12646 //
     /*  437801 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  437804 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437807 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437811 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437818 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437825 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437829 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437836 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  437839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437844 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437861 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437865 */   GIR_RootConstrainSelectedInstOperands,
     /*  437866 */   // GIR_Coverage, 12646,
     /*  437866 */   GIR_EraseRootFromParent_Done,
     /*  437867 */ // Label 6622: @437867
     /*  437867 */ GIM_Try, /*On fail goto*//*Label 6623*/ GIMT_Encode4(437938), // Rule ID 12647 //
     /*  437872 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  437875 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437878 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437882 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437907 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  437910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437915 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  437932 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  437936 */   GIR_RootConstrainSelectedInstOperands,
     /*  437937 */   // GIR_Coverage, 12647,
     /*  437937 */   GIR_EraseRootFromParent_Done,
     /*  437938 */ // Label 6623: @437938
     /*  437938 */ GIM_Try, /*On fail goto*//*Label 6624*/ GIMT_Encode4(438009), // Rule ID 12683 //
     /*  437943 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts),
     /*  437946 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  437949 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  437953 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  437960 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  437967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  437971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  437978 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  437978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR_t16),
     /*  437981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  437986 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  437988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  437993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  437998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438007 */   GIR_RootConstrainSelectedInstOperands,
     /*  438008 */   // GIR_Coverage, 12683,
     /*  438008 */   GIR_EraseRootFromParent_Done,
     /*  438009 */ // Label 6624: @438009
     /*  438009 */ GIM_Try, /*On fail goto*//*Label 6625*/ GIMT_Encode4(438069), // Rule ID 12095 //
     /*  438014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts),
     /*  438017 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438020 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438027 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438031 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438038 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438038 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR_t16),
     /*  438041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438046 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438063 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438067 */   GIR_RootConstrainSelectedInstOperands,
     /*  438068 */   // GIR_Coverage, 12095,
     /*  438068 */   GIR_EraseRootFromParent_Done,
     /*  438069 */ // Label 6625: @438069
     /*  438069 */ GIM_Try, /*On fail goto*//*Label 6626*/ GIMT_Encode4(438129), // Rule ID 12653 //
     /*  438074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  438077 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438080 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438087 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438091 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438098 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  438101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438106 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438123 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438127 */   GIR_RootConstrainSelectedInstOperands,
     /*  438128 */   // GIR_Coverage, 12653,
     /*  438128 */   GIR_EraseRootFromParent_Done,
     /*  438129 */ // Label 6626: @438129
     /*  438129 */ GIM_Try, /*On fail goto*//*Label 6627*/ GIMT_Encode4(438189), // Rule ID 12654 //
     /*  438134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  438137 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438140 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438147 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438151 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438158 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  438161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438166 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438187 */   GIR_RootConstrainSelectedInstOperands,
     /*  438188 */   // GIR_Coverage, 12654,
     /*  438188 */   GIR_EraseRootFromParent_Done,
     /*  438189 */ // Label 6627: @438189
     /*  438189 */ GIM_Try, /*On fail goto*//*Label 6628*/ GIMT_Encode4(438249), // Rule ID 12655 //
     /*  438194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  438197 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438207 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438211 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438218 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438218 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  438221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438226 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438243 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438247 */   GIR_RootConstrainSelectedInstOperands,
     /*  438248 */   // GIR_Coverage, 12655,
     /*  438248 */   GIR_EraseRootFromParent_Done,
     /*  438249 */ // Label 6628: @438249
     /*  438249 */ GIM_Try, /*On fail goto*//*Label 6629*/ GIMT_Encode4(438309), // Rule ID 12656 //
     /*  438254 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  438257 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438260 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438278 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  438281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438286 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438307 */   GIR_RootConstrainSelectedInstOperands,
     /*  438308 */   // GIR_Coverage, 12656,
     /*  438308 */   GIR_EraseRootFromParent_Done,
     /*  438309 */ // Label 6629: @438309
     /*  438309 */ GIM_Try, /*On fail goto*//*Label 6630*/ GIMT_Encode4(438369), // Rule ID 12657 //
     /*  438314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  438317 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438320 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438327 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438331 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438338 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438338 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  438341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438346 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438363 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438367 */   GIR_RootConstrainSelectedInstOperands,
     /*  438368 */   // GIR_Coverage, 12657,
     /*  438368 */   GIR_EraseRootFromParent_Done,
     /*  438369 */ // Label 6630: @438369
     /*  438369 */ GIM_Try, /*On fail goto*//*Label 6631*/ GIMT_Encode4(438429), // Rule ID 12689 //
     /*  438374 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts),
     /*  438377 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  438380 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438387 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438391 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  438398 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  438398 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR_t16),
     /*  438401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  438406 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  438413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  438418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  438423 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438427 */   GIR_RootConstrainSelectedInstOperands,
     /*  438428 */   // GIR_Coverage, 12689,
     /*  438428 */   GIR_EraseRootFromParent_Done,
     /*  438429 */ // Label 6631: @438429
     /*  438429 */ GIM_Try, /*On fail goto*//*Label 6632*/ GIMT_Encode4(438489), // Rule ID 12096 //
     /*  438434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  438437 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438440 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  438447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438454 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438458 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438465 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  438468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438473 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438483 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438487 */   GIR_RootConstrainSelectedInstOperands,
     /*  438488 */   // GIR_Coverage, 12096,
     /*  438488 */   GIR_EraseRootFromParent_Done,
     /*  438489 */ // Label 6632: @438489
     /*  438489 */ GIM_Try, /*On fail goto*//*Label 6633*/ GIMT_Encode4(438549), // Rule ID 12097 //
     /*  438494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  438497 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438500 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  438507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438525 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  438528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438533 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438547 */   GIR_RootConstrainSelectedInstOperands,
     /*  438548 */   // GIR_Coverage, 12097,
     /*  438548 */   GIR_EraseRootFromParent_Done,
     /*  438549 */ // Label 6633: @438549
     /*  438549 */ GIM_Try, /*On fail goto*//*Label 6634*/ GIMT_Encode4(438609), // Rule ID 12098 //
     /*  438554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  438557 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438560 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  438567 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438574 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438578 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438585 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438585 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  438588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438593 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438600 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438603 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438607 */   GIR_RootConstrainSelectedInstOperands,
     /*  438608 */   // GIR_Coverage, 12098,
     /*  438608 */   GIR_EraseRootFromParent_Done,
     /*  438609 */ // Label 6634: @438609
     /*  438609 */ GIM_Try, /*On fail goto*//*Label 6635*/ GIMT_Encode4(438669), // Rule ID 12099 //
     /*  438614 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  438617 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  438627 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438634 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438638 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438645 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438645 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  438648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438653 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438660 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438667 */   GIR_RootConstrainSelectedInstOperands,
     /*  438668 */   // GIR_Coverage, 12099,
     /*  438668 */   GIR_EraseRootFromParent_Done,
     /*  438669 */ // Label 6635: @438669
     /*  438669 */ GIM_Try, /*On fail goto*//*Label 6636*/ GIMT_Encode4(438729), // Rule ID 12100 //
     /*  438674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  438677 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438680 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  438687 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438698 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438705 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  438708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438713 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438723 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438727 */   GIR_RootConstrainSelectedInstOperands,
     /*  438728 */   // GIR_Coverage, 12100,
     /*  438728 */   GIR_EraseRootFromParent_Done,
     /*  438729 */ // Label 6636: @438729
     /*  438729 */ GIM_Try, /*On fail goto*//*Label 6637*/ GIMT_Encode4(438789), // Rule ID 12102 //
     /*  438734 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  438737 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438740 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  438747 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438754 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438758 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438765 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438765 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  438768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438773 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438783 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438787 */   GIR_RootConstrainSelectedInstOperands,
     /*  438788 */   // GIR_Coverage, 12102,
     /*  438788 */   GIR_EraseRootFromParent_Done,
     /*  438789 */ // Label 6637: @438789
     /*  438789 */ GIM_Try, /*On fail goto*//*Label 6638*/ GIMT_Encode4(438849), // Rule ID 12103 //
     /*  438794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  438797 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438800 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  438807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438825 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  438828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438833 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438843 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438847 */   GIR_RootConstrainSelectedInstOperands,
     /*  438848 */   // GIR_Coverage, 12103,
     /*  438848 */   GIR_EraseRootFromParent_Done,
     /*  438849 */ // Label 6638: @438849
     /*  438849 */ GIM_Try, /*On fail goto*//*Label 6639*/ GIMT_Encode4(438909), // Rule ID 12104 //
     /*  438854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  438857 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438860 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  438867 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438885 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  438888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438893 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438900 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438907 */   GIR_RootConstrainSelectedInstOperands,
     /*  438908 */   // GIR_Coverage, 12104,
     /*  438908 */   GIR_EraseRootFromParent_Done,
     /*  438909 */ // Label 6639: @438909
     /*  438909 */ GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(438969), // Rule ID 12105 //
     /*  438914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  438917 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438920 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  438927 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438934 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438938 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  438945 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  438945 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  438948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  438953 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  438955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  438960 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  438963 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  438967 */   GIR_RootConstrainSelectedInstOperands,
     /*  438968 */   // GIR_Coverage, 12105,
     /*  438968 */   GIR_EraseRootFromParent_Done,
     /*  438969 */ // Label 6640: @438969
     /*  438969 */ GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(439029), // Rule ID 12106 //
     /*  438974 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  438977 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  438980 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  438987 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  438994 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  438998 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439005 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  439008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439013 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439027 */   GIR_RootConstrainSelectedInstOperands,
     /*  439028 */   // GIR_Coverage, 12106,
     /*  439028 */   GIR_EraseRootFromParent_Done,
     /*  439029 */ // Label 6641: @439029
     /*  439029 */ GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(439089), // Rule ID 12658 //
     /*  439034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  439037 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439040 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439047 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439054 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439058 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439065 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439065 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  439068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439073 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439087 */   GIR_RootConstrainSelectedInstOperands,
     /*  439088 */   // GIR_Coverage, 12658,
     /*  439088 */   GIR_EraseRootFromParent_Done,
     /*  439089 */ // Label 6642: @439089
     /*  439089 */ GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(439149), // Rule ID 12659 //
     /*  439094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  439097 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439100 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439107 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439114 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439118 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439125 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439125 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  439128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439133 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439143 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439147 */   GIR_RootConstrainSelectedInstOperands,
     /*  439148 */   // GIR_Coverage, 12659,
     /*  439148 */   GIR_EraseRootFromParent_Done,
     /*  439149 */ // Label 6643: @439149
     /*  439149 */ GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(439209), // Rule ID 12660 //
     /*  439154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  439157 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439160 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439174 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439178 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439185 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439185 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  439188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439193 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439203 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439207 */   GIR_RootConstrainSelectedInstOperands,
     /*  439208 */   // GIR_Coverage, 12660,
     /*  439208 */   GIR_EraseRootFromParent_Done,
     /*  439209 */ // Label 6644: @439209
     /*  439209 */ GIM_Try, /*On fail goto*//*Label 6645*/ GIMT_Encode4(439269), // Rule ID 12661 //
     /*  439214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  439217 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439220 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439227 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439234 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439238 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439245 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  439248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439253 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439260 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439263 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439267 */   GIR_RootConstrainSelectedInstOperands,
     /*  439268 */   // GIR_Coverage, 12661,
     /*  439268 */   GIR_EraseRootFromParent_Done,
     /*  439269 */ // Label 6645: @439269
     /*  439269 */ GIM_Try, /*On fail goto*//*Label 6646*/ GIMT_Encode4(439329), // Rule ID 12662 //
     /*  439274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  439277 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439280 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439287 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439305 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  439308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439313 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439323 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439327 */   GIR_RootConstrainSelectedInstOperands,
     /*  439328 */   // GIR_Coverage, 12662,
     /*  439328 */   GIR_EraseRootFromParent_Done,
     /*  439329 */ // Label 6646: @439329
     /*  439329 */ GIM_Try, /*On fail goto*//*Label 6647*/ GIMT_Encode4(439389), // Rule ID 12668 //
     /*  439334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  439337 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439340 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  439347 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439354 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439358 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439365 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  439368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439373 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439380 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439383 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439387 */   GIR_RootConstrainSelectedInstOperands,
     /*  439388 */   // GIR_Coverage, 12668,
     /*  439388 */   GIR_EraseRootFromParent_Done,
     /*  439389 */ // Label 6647: @439389
     /*  439389 */ GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(439449), // Rule ID 12669 //
     /*  439394 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  439397 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439400 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  439407 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439414 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439418 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439425 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439425 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  439428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439433 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439447 */   GIR_RootConstrainSelectedInstOperands,
     /*  439448 */   // GIR_Coverage, 12669,
     /*  439448 */   GIR_EraseRootFromParent_Done,
     /*  439449 */ // Label 6648: @439449
     /*  439449 */ GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(439509), // Rule ID 12670 //
     /*  439454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  439457 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439460 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  439467 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439474 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439478 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439485 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  439488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439493 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439500 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439507 */   GIR_RootConstrainSelectedInstOperands,
     /*  439508 */   // GIR_Coverage, 12670,
     /*  439508 */   GIR_EraseRootFromParent_Done,
     /*  439509 */ // Label 6649: @439509
     /*  439509 */ GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(439569), // Rule ID 12671 //
     /*  439514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  439517 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439520 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  439527 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439534 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439538 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439545 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  439548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439553 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439560 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439563 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439567 */   GIR_RootConstrainSelectedInstOperands,
     /*  439568 */   // GIR_Coverage, 12671,
     /*  439568 */   GIR_EraseRootFromParent_Done,
     /*  439569 */ // Label 6650: @439569
     /*  439569 */ GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(439629), // Rule ID 12672 //
     /*  439574 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  439577 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439580 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  439587 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439594 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439598 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439605 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439605 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  439608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439613 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439615 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439620 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439623 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439627 */   GIR_RootConstrainSelectedInstOperands,
     /*  439628 */   // GIR_Coverage, 12672,
     /*  439628 */   GIR_EraseRootFromParent_Done,
     /*  439629 */ // Label 6651: @439629
     /*  439629 */ GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(439689), // Rule ID 12690 //
     /*  439634 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode0),
     /*  439637 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439640 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439647 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439654 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439658 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439665 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  439668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439673 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439680 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439683 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439687 */   GIR_RootConstrainSelectedInstOperands,
     /*  439688 */   // GIR_Coverage, 12690,
     /*  439688 */   GIR_EraseRootFromParent_Done,
     /*  439689 */ // Label 6652: @439689
     /*  439689 */ GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(439749), // Rule ID 12691 //
     /*  439694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode1),
     /*  439697 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439700 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439707 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439714 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439718 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439725 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439725 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  439728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439733 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439740 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439743 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439747 */   GIR_RootConstrainSelectedInstOperands,
     /*  439748 */   // GIR_Coverage, 12691,
     /*  439748 */   GIR_EraseRootFromParent_Done,
     /*  439749 */ // Label 6653: @439749
     /*  439749 */ GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(439809), // Rule ID 12692 //
     /*  439754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode2),
     /*  439757 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439760 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439774 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439778 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439785 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  439788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439793 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439807 */   GIR_RootConstrainSelectedInstOperands,
     /*  439808 */   // GIR_Coverage, 12692,
     /*  439808 */   GIR_EraseRootFromParent_Done,
     /*  439809 */ // Label 6654: @439809
     /*  439809 */ GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(439869), // Rule ID 12693 //
     /*  439814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode3),
     /*  439817 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439820 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439827 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439845 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  439848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439853 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439867 */   GIR_RootConstrainSelectedInstOperands,
     /*  439868 */   // GIR_Coverage, 12693,
     /*  439868 */   GIR_EraseRootFromParent_Done,
     /*  439869 */ // Label 6655: @439869
     /*  439869 */ GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(439929), // Rule ID 12694 //
     /*  439874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode4),
     /*  439877 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439880 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  439887 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439898 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439905 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  439908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439913 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439920 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439923 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439927 */   GIR_RootConstrainSelectedInstOperands,
     /*  439928 */   // GIR_Coverage, 12694,
     /*  439928 */   GIR_EraseRootFromParent_Done,
     /*  439929 */ // Label 6656: @439929
     /*  439929 */ GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(439989), // Rule ID 12696 //
     /*  439934 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode0),
     /*  439937 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  439940 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  439947 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  439954 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  439958 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  439965 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  439965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  439968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  439973 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  439975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  439980 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  439983 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  439987 */   GIR_RootConstrainSelectedInstOperands,
     /*  439988 */   // GIR_Coverage, 12696,
     /*  439988 */   GIR_EraseRootFromParent_Done,
     /*  439989 */ // Label 6657: @439989
     /*  439989 */ GIM_Try, /*On fail goto*//*Label 6658*/ GIMT_Encode4(440049), // Rule ID 12697 //
     /*  439994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode1),
     /*  439997 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  440000 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  440007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440014 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440018 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440025 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  440028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440033 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440040 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440047 */   GIR_RootConstrainSelectedInstOperands,
     /*  440048 */   // GIR_Coverage, 12697,
     /*  440048 */   GIR_EraseRootFromParent_Done,
     /*  440049 */ // Label 6658: @440049
     /*  440049 */ GIM_Try, /*On fail goto*//*Label 6659*/ GIMT_Encode4(440109), // Rule ID 12698 //
     /*  440054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode2),
     /*  440057 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  440060 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  440067 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440085 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  440088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440093 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440100 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440107 */   GIR_RootConstrainSelectedInstOperands,
     /*  440108 */   // GIR_Coverage, 12698,
     /*  440108 */   GIR_EraseRootFromParent_Done,
     /*  440109 */ // Label 6659: @440109
     /*  440109 */ GIM_Try, /*On fail goto*//*Label 6660*/ GIMT_Encode4(440169), // Rule ID 12699 //
     /*  440114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode3),
     /*  440117 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  440120 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  440127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440134 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440138 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440145 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440145 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  440148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440153 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440163 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440167 */   GIR_RootConstrainSelectedInstOperands,
     /*  440168 */   // GIR_Coverage, 12699,
     /*  440168 */   GIR_EraseRootFromParent_Done,
     /*  440169 */ // Label 6660: @440169
     /*  440169 */ GIM_Try, /*On fail goto*//*Label 6661*/ GIMT_Encode4(440229), // Rule ID 12700 //
     /*  440174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode4),
     /*  440177 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  440180 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  440187 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440194 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440198 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440205 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  440208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440213 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440220 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440223 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440227 */   GIR_RootConstrainSelectedInstOperands,
     /*  440228 */   // GIR_Coverage, 12700,
     /*  440228 */   GIR_EraseRootFromParent_Done,
     /*  440229 */ // Label 6661: @440229
     /*  440229 */ GIM_Try, /*On fail goto*//*Label 6662*/ GIMT_Encode4(440293), // Rule ID 9386 //
     /*  440234 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  440237 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440240 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440244 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440251 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440258 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440262 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440269 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440269 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440272 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440277 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440279 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440287 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440291 */   GIR_RootConstrainSelectedInstOperands,
     /*  440292 */   // GIR_Coverage, 9386,
     /*  440292 */   GIR_EraseRootFromParent_Done,
     /*  440293 */ // Label 6662: @440293
     /*  440293 */ GIM_Try, /*On fail goto*//*Label 6663*/ GIMT_Encode4(440357), // Rule ID 9387 //
     /*  440298 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  440301 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440304 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440308 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440315 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440322 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440326 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440333 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440341 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440348 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440355 */   GIR_RootConstrainSelectedInstOperands,
     /*  440356 */   // GIR_Coverage, 9387,
     /*  440356 */   GIR_EraseRootFromParent_Done,
     /*  440357 */ // Label 6663: @440357
     /*  440357 */ GIM_Try, /*On fail goto*//*Label 6664*/ GIMT_Encode4(440421), // Rule ID 9388 //
     /*  440362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  440365 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440368 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440372 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440379 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440386 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440390 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440397 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440397 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440405 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440412 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440415 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440419 */   GIR_RootConstrainSelectedInstOperands,
     /*  440420 */   // GIR_Coverage, 9388,
     /*  440420 */   GIR_EraseRootFromParent_Done,
     /*  440421 */ // Label 6664: @440421
     /*  440421 */ GIM_Try, /*On fail goto*//*Label 6665*/ GIMT_Encode4(440485), // Rule ID 9389 //
     /*  440426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  440429 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440432 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440436 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440450 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440454 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440461 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440469 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440476 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440479 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440483 */   GIR_RootConstrainSelectedInstOperands,
     /*  440484 */   // GIR_Coverage, 9389,
     /*  440484 */   GIR_EraseRootFromParent_Done,
     /*  440485 */ // Label 6665: @440485
     /*  440485 */ GIM_Try, /*On fail goto*//*Label 6666*/ GIMT_Encode4(440549), // Rule ID 9390 //
     /*  440490 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  440493 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440496 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440500 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440507 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440525 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440533 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440547 */   GIR_RootConstrainSelectedInstOperands,
     /*  440548 */   // GIR_Coverage, 9390,
     /*  440548 */   GIR_EraseRootFromParent_Done,
     /*  440549 */ // Label 6666: @440549
     /*  440549 */ GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(440613), // Rule ID 12638 //
     /*  440554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  440557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440560 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440564 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440571 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440578 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440589 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  440592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440597 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440604 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440607 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440611 */   GIR_RootConstrainSelectedInstOperands,
     /*  440612 */   // GIR_Coverage, 12638,
     /*  440612 */   GIR_EraseRootFromParent_Done,
     /*  440613 */ // Label 6667: @440613
     /*  440613 */ GIM_Try, /*On fail goto*//*Label 6668*/ GIMT_Encode4(440677), // Rule ID 12639 //
     /*  440618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  440621 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440624 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440628 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440635 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440653 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  440656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440661 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440671 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440675 */   GIR_RootConstrainSelectedInstOperands,
     /*  440676 */   // GIR_Coverage, 12639,
     /*  440676 */   GIR_EraseRootFromParent_Done,
     /*  440677 */ // Label 6668: @440677
     /*  440677 */ GIM_Try, /*On fail goto*//*Label 6669*/ GIMT_Encode4(440741), // Rule ID 12640 //
     /*  440682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  440685 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440688 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440692 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440699 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440706 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440710 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440717 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440717 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  440720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440725 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440732 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440735 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440739 */   GIR_RootConstrainSelectedInstOperands,
     /*  440740 */   // GIR_Coverage, 12640,
     /*  440740 */   GIR_EraseRootFromParent_Done,
     /*  440741 */ // Label 6669: @440741
     /*  440741 */ GIM_Try, /*On fail goto*//*Label 6670*/ GIMT_Encode4(440805), // Rule ID 12641 //
     /*  440746 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  440749 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440752 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440756 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440763 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440781 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  440784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440789 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440796 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440799 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440803 */   GIR_RootConstrainSelectedInstOperands,
     /*  440804 */   // GIR_Coverage, 12641,
     /*  440804 */   GIR_EraseRootFromParent_Done,
     /*  440805 */ // Label 6670: @440805
     /*  440805 */ GIM_Try, /*On fail goto*//*Label 6671*/ GIMT_Encode4(440869), // Rule ID 12642 //
     /*  440810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  440813 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440816 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440820 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440827 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440834 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440838 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440845 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  440848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440853 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440867 */   GIR_RootConstrainSelectedInstOperands,
     /*  440868 */   // GIR_Coverage, 12642,
     /*  440868 */   GIR_EraseRootFromParent_Done,
     /*  440869 */ // Label 6671: @440869
     /*  440869 */ GIM_Try, /*On fail goto*//*Label 6672*/ GIMT_Encode4(440933), // Rule ID 12678 //
     /*  440874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode0),
     /*  440877 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440880 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440884 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440891 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440898 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440902 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440909 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440909 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440917 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440927 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440931 */   GIR_RootConstrainSelectedInstOperands,
     /*  440932 */   // GIR_Coverage, 12678,
     /*  440932 */   GIR_EraseRootFromParent_Done,
     /*  440933 */ // Label 6672: @440933
     /*  440933 */ GIM_Try, /*On fail goto*//*Label 6673*/ GIMT_Encode4(440997), // Rule ID 12679 //
     /*  440938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode1),
     /*  440941 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  440944 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  440948 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  440955 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  440962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  440966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  440973 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  440973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  440976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  440981 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  440983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  440988 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  440991 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  440995 */   GIR_RootConstrainSelectedInstOperands,
     /*  440996 */   // GIR_Coverage, 12679,
     /*  440996 */   GIR_EraseRootFromParent_Done,
     /*  440997 */ // Label 6673: @440997
     /*  440997 */ GIM_Try, /*On fail goto*//*Label 6674*/ GIMT_Encode4(441061), // Rule ID 12680 //
     /*  441002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode2),
     /*  441005 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441008 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  441012 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  441019 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441026 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441030 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441037 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441037 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  441040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441045 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441052 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441055 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441059 */   GIR_RootConstrainSelectedInstOperands,
     /*  441060 */   // GIR_Coverage, 12680,
     /*  441060 */   GIR_EraseRootFromParent_Done,
     /*  441061 */ // Label 6674: @441061
     /*  441061 */ GIM_Try, /*On fail goto*//*Label 6675*/ GIMT_Encode4(441125), // Rule ID 12681 //
     /*  441066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode3),
     /*  441069 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441072 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  441076 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  441083 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441101 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  441104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441109 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441116 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441123 */   GIR_RootConstrainSelectedInstOperands,
     /*  441124 */   // GIR_Coverage, 12681,
     /*  441124 */   GIR_EraseRootFromParent_Done,
     /*  441125 */ // Label 6675: @441125
     /*  441125 */ GIM_Try, /*On fail goto*//*Label 6676*/ GIMT_Encode4(441189), // Rule ID 12682 //
     /*  441130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode4),
     /*  441133 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441136 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  441140 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  441147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441158 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441165 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441165 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_t16),
     /*  441168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441173 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441183 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441187 */   GIR_RootConstrainSelectedInstOperands,
     /*  441188 */   // GIR_Coverage, 12682,
     /*  441188 */   GIR_EraseRootFromParent_Done,
     /*  441189 */ // Label 6676: @441189
     /*  441189 */ GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(441242), // Rule ID 12090 //
     /*  441194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  441197 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441207 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441211 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441218 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441218 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441226 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441236 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441240 */   GIR_RootConstrainSelectedInstOperands,
     /*  441241 */   // GIR_Coverage, 12090,
     /*  441241 */   GIR_EraseRootFromParent_Done,
     /*  441242 */ // Label 6677: @441242
     /*  441242 */ GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(441295), // Rule ID 12091 //
     /*  441247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  441250 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441253 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441271 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441279 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441293 */   GIR_RootConstrainSelectedInstOperands,
     /*  441294 */   // GIR_Coverage, 12091,
     /*  441294 */   GIR_EraseRootFromParent_Done,
     /*  441295 */ // Label 6678: @441295
     /*  441295 */ GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(441348), // Rule ID 12092 //
     /*  441300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  441303 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441306 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441324 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441332 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441339 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441342 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441346 */   GIR_RootConstrainSelectedInstOperands,
     /*  441347 */   // GIR_Coverage, 12092,
     /*  441347 */   GIR_EraseRootFromParent_Done,
     /*  441348 */ // Label 6679: @441348
     /*  441348 */ GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(441401), // Rule ID 12093 //
     /*  441353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  441356 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441359 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441366 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441370 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441377 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441385 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441392 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441395 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441399 */   GIR_RootConstrainSelectedInstOperands,
     /*  441400 */   // GIR_Coverage, 12093,
     /*  441400 */   GIR_EraseRootFromParent_Done,
     /*  441401 */ // Label 6680: @441401
     /*  441401 */ GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(441454), // Rule ID 12094 //
     /*  441406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  441409 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441412 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441419 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441423 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441430 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441438 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441445 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441448 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441452 */   GIR_RootConstrainSelectedInstOperands,
     /*  441453 */   // GIR_Coverage, 12094,
     /*  441453 */   GIR_EraseRootFromParent_Done,
     /*  441454 */ // Label 6681: @441454
     /*  441454 */ GIM_Try, /*On fail goto*//*Label 6682*/ GIMT_Encode4(441507), // Rule ID 12648 //
     /*  441459 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode0),
     /*  441462 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441465 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441472 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441476 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441483 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441483 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  441486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441491 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441498 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441501 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441505 */   GIR_RootConstrainSelectedInstOperands,
     /*  441506 */   // GIR_Coverage, 12648,
     /*  441506 */   GIR_EraseRootFromParent_Done,
     /*  441507 */ // Label 6682: @441507
     /*  441507 */ GIM_Try, /*On fail goto*//*Label 6683*/ GIMT_Encode4(441560), // Rule ID 12649 //
     /*  441512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode1),
     /*  441515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441518 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441525 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441529 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441536 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441536 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  441539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441544 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441551 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441554 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441558 */   GIR_RootConstrainSelectedInstOperands,
     /*  441559 */   // GIR_Coverage, 12649,
     /*  441559 */   GIR_EraseRootFromParent_Done,
     /*  441560 */ // Label 6683: @441560
     /*  441560 */ GIM_Try, /*On fail goto*//*Label 6684*/ GIMT_Encode4(441613), // Rule ID 12650 //
     /*  441565 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode2),
     /*  441568 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441571 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441578 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441589 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  441592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441597 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441604 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441607 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441611 */   GIR_RootConstrainSelectedInstOperands,
     /*  441612 */   // GIR_Coverage, 12650,
     /*  441612 */   GIR_EraseRootFromParent_Done,
     /*  441613 */ // Label 6684: @441613
     /*  441613 */ GIM_Try, /*On fail goto*//*Label 6685*/ GIMT_Encode4(441666), // Rule ID 12651 //
     /*  441618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode3),
     /*  441621 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441624 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441642 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  441645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441650 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441657 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441660 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441664 */   GIR_RootConstrainSelectedInstOperands,
     /*  441665 */   // GIR_Coverage, 12651,
     /*  441665 */   GIR_EraseRootFromParent_Done,
     /*  441666 */ // Label 6685: @441666
     /*  441666 */ GIM_Try, /*On fail goto*//*Label 6686*/ GIMT_Encode4(441719), // Rule ID 12652 //
     /*  441671 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_NotUseRealTrue16Insts_HwMode4),
     /*  441674 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441677 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441688 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441695 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  441698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441703 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441710 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441713 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441717 */   GIR_RootConstrainSelectedInstOperands,
     /*  441718 */   // GIR_Coverage, 12652,
     /*  441718 */   GIR_EraseRootFromParent_Done,
     /*  441719 */ // Label 6686: @441719
     /*  441719 */ GIM_Try, /*On fail goto*//*Label 6687*/ GIMT_Encode4(441772), // Rule ID 12684 //
     /*  441724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode0),
     /*  441727 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441730 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441737 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441741 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441748 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441748 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441756 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441763 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441766 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441770 */   GIR_RootConstrainSelectedInstOperands,
     /*  441771 */   // GIR_Coverage, 12684,
     /*  441771 */   GIR_EraseRootFromParent_Done,
     /*  441772 */ // Label 6687: @441772
     /*  441772 */ GIM_Try, /*On fail goto*//*Label 6688*/ GIMT_Encode4(441825), // Rule ID 12685 //
     /*  441777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode1),
     /*  441780 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441790 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441801 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441809 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441816 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441819 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441823 */   GIR_RootConstrainSelectedInstOperands,
     /*  441824 */   // GIR_Coverage, 12685,
     /*  441824 */   GIR_EraseRootFromParent_Done,
     /*  441825 */ // Label 6688: @441825
     /*  441825 */ GIM_Try, /*On fail goto*//*Label 6689*/ GIMT_Encode4(441878), // Rule ID 12686 //
     /*  441830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode2),
     /*  441833 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441836 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441847 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441854 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441854 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441862 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441869 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441872 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441876 */   GIR_RootConstrainSelectedInstOperands,
     /*  441877 */   // GIR_Coverage, 12686,
     /*  441877 */   GIR_EraseRootFromParent_Done,
     /*  441878 */ // Label 6689: @441878
     /*  441878 */ GIM_Try, /*On fail goto*//*Label 6690*/ GIMT_Encode4(441931), // Rule ID 12687 //
     /*  441883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode3),
     /*  441886 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441907 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441915 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441929 */   GIR_RootConstrainSelectedInstOperands,
     /*  441930 */   // GIR_Coverage, 12687,
     /*  441930 */   GIR_EraseRootFromParent_Done,
     /*  441931 */ // Label 6690: @441931
     /*  441931 */ GIM_Try, /*On fail goto*//*Label 6691*/ GIMT_Encode4(441984), // Rule ID 12688 //
     /*  441936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_UseRealTrue16Insts_HwMode4),
     /*  441939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  441942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  441949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  441953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  441960 */   // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  441960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_t16),
     /*  441963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  441968 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  441970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  441975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  441978 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  441982 */   GIR_RootConstrainSelectedInstOperands,
     /*  441983 */   // GIR_Coverage, 12688,
     /*  441983 */   GIR_EraseRootFromParent_Done,
     /*  441984 */ // Label 6691: @441984
     /*  441984 */ GIM_Try, /*On fail goto*//*Label 6692*/ GIMT_Encode4(442050), // Rule ID 9751 //
     /*  441989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  441992 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  441995 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442002 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442008 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442012 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442019 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442019 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442027 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442048 */   GIR_RootConstrainSelectedInstOperands,
     /*  442049 */   // GIR_Coverage, 9751,
     /*  442049 */   GIR_EraseRootFromParent_Done,
     /*  442050 */ // Label 6692: @442050
     /*  442050 */ GIM_Try, /*On fail goto*//*Label 6693*/ GIMT_Encode4(442116), // Rule ID 9752 //
     /*  442055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  442058 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442061 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442085 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442085 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442093 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442110 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442114 */   GIR_RootConstrainSelectedInstOperands,
     /*  442115 */   // GIR_Coverage, 9752,
     /*  442115 */   GIR_EraseRootFromParent_Done,
     /*  442116 */ // Label 6693: @442116
     /*  442116 */ GIM_Try, /*On fail goto*//*Label 6694*/ GIMT_Encode4(442182), // Rule ID 9753 //
     /*  442121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  442124 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442127 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442134 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442151 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442159 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442176 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442180 */   GIR_RootConstrainSelectedInstOperands,
     /*  442181 */   // GIR_Coverage, 9753,
     /*  442181 */   GIR_EraseRootFromParent_Done,
     /*  442182 */ // Label 6694: @442182
     /*  442182 */ GIM_Try, /*On fail goto*//*Label 6695*/ GIMT_Encode4(442248), // Rule ID 9754 //
     /*  442187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  442190 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442193 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442206 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442210 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442217 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442225 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442246 */   GIR_RootConstrainSelectedInstOperands,
     /*  442247 */   // GIR_Coverage, 9754,
     /*  442247 */   GIR_EraseRootFromParent_Done,
     /*  442248 */ // Label 6695: @442248
     /*  442248 */ GIM_Try, /*On fail goto*//*Label 6696*/ GIMT_Encode4(442314), // Rule ID 9755 //
     /*  442253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  442256 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442259 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442266 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442272 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442276 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442283 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442283 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442291 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442308 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442312 */   GIR_RootConstrainSelectedInstOperands,
     /*  442313 */   // GIR_Coverage, 9755,
     /*  442313 */   GIR_EraseRootFromParent_Done,
     /*  442314 */ // Label 6696: @442314
     /*  442314 */ GIM_Try, /*On fail goto*//*Label 6697*/ GIMT_Encode4(442380), // Rule ID 9761 //
     /*  442319 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  442322 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442325 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  442332 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442338 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442342 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442349 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  442352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442357 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442374 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442378 */   GIR_RootConstrainSelectedInstOperands,
     /*  442379 */   // GIR_Coverage, 9761,
     /*  442379 */   GIR_EraseRootFromParent_Done,
     /*  442380 */ // Label 6697: @442380
     /*  442380 */ GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(442446), // Rule ID 9762 //
     /*  442385 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  442388 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442391 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  442398 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442415 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  442418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442423 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442444 */   GIR_RootConstrainSelectedInstOperands,
     /*  442445 */   // GIR_Coverage, 9762,
     /*  442445 */   GIR_EraseRootFromParent_Done,
     /*  442446 */ // Label 6698: @442446
     /*  442446 */ GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(442512), // Rule ID 9763 //
     /*  442451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  442454 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442457 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  442464 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442470 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442474 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442481 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442481 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  442484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442489 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442506 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442510 */   GIR_RootConstrainSelectedInstOperands,
     /*  442511 */   // GIR_Coverage, 9763,
     /*  442511 */   GIR_EraseRootFromParent_Done,
     /*  442512 */ // Label 6699: @442512
     /*  442512 */ GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(442578), // Rule ID 9764 //
     /*  442517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  442520 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442523 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  442530 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442536 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442540 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442547 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442547 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  442550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442555 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442576 */   GIR_RootConstrainSelectedInstOperands,
     /*  442577 */   // GIR_Coverage, 9764,
     /*  442577 */   GIR_EraseRootFromParent_Done,
     /*  442578 */ // Label 6700: @442578
     /*  442578 */ GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(442644), // Rule ID 9765 //
     /*  442583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  442586 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442589 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  442596 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442613 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  442616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442621 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442638 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442642 */   GIR_RootConstrainSelectedInstOperands,
     /*  442643 */   // GIR_Coverage, 9765,
     /*  442643 */   GIR_EraseRootFromParent_Done,
     /*  442644 */ // Label 6701: @442644
     /*  442644 */ GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(442710), // Rule ID 9889 //
     /*  442649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_UseRealTrue16Insts),
     /*  442652 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442655 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442662 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442668 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442672 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442679 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR_t16),
     /*  442682 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442687 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442704 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442708 */   GIR_RootConstrainSelectedInstOperands,
     /*  442709 */   // GIR_Coverage, 9889,
     /*  442709 */   GIR_EraseRootFromParent_Done,
     /*  442710 */ // Label 6702: @442710
     /*  442710 */ GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(442776), // Rule ID 9895 //
     /*  442715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_UseRealTrue16Insts),
     /*  442718 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  442721 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  442728 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442734 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442738 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442745 */   // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442745 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR_t16),
     /*  442748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442753 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442770 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442774 */   GIR_RootConstrainSelectedInstOperands,
     /*  442775 */   // GIR_Coverage, 9895,
     /*  442775 */   GIR_EraseRootFromParent_Done,
     /*  442776 */ // Label 6703: @442776
     /*  442776 */ GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(442846), // Rule ID 9515 //
     /*  442781 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  442784 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  442787 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  442791 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442798 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442808 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442815 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442815 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442823 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442840 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442844 */   GIR_RootConstrainSelectedInstOperands,
     /*  442845 */   // GIR_Coverage, 9515,
     /*  442845 */   GIR_EraseRootFromParent_Done,
     /*  442846 */ // Label 6704: @442846
     /*  442846 */ GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(442916), // Rule ID 9516 //
     /*  442851 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  442854 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  442857 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  442861 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442868 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442885 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442893 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442910 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442914 */   GIR_RootConstrainSelectedInstOperands,
     /*  442915 */   // GIR_Coverage, 9516,
     /*  442915 */   GIR_EraseRootFromParent_Done,
     /*  442916 */ // Label 6705: @442916
     /*  442916 */ GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(442986), // Rule ID 9517 //
     /*  442921 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  442924 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  442927 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  442931 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  442938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  442944 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  442948 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  442955 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  442955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  442958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  442963 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  442965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  442970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  442975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  442980 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  442984 */   GIR_RootConstrainSelectedInstOperands,
     /*  442985 */   // GIR_Coverage, 9517,
     /*  442985 */   GIR_EraseRootFromParent_Done,
     /*  442986 */ // Label 6706: @442986
     /*  442986 */ GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(443056), // Rule ID 9518 //
     /*  442991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  442994 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  442997 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443001 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443008 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443014 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443018 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443025 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443033 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443040 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443050 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443054 */   GIR_RootConstrainSelectedInstOperands,
     /*  443055 */   // GIR_Coverage, 9518,
     /*  443055 */   GIR_EraseRootFromParent_Done,
     /*  443056 */ // Label 6707: @443056
     /*  443056 */ GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(443126), // Rule ID 9519 //
     /*  443061 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  443064 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443067 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443071 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443088 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443095 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443103 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443124 */   GIR_RootConstrainSelectedInstOperands,
     /*  443125 */   // GIR_Coverage, 9519,
     /*  443125 */   GIR_EraseRootFromParent_Done,
     /*  443126 */ // Label 6708: @443126
     /*  443126 */ GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(443196), // Rule ID 9525 //
     /*  443131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_UseRealTrue16Insts),
     /*  443134 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443137 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443141 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443148 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443158 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443165 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443165 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR_t16),
     /*  443168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443173 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443190 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443194 */   GIR_RootConstrainSelectedInstOperands,
     /*  443195 */   // GIR_Coverage, 9525,
     /*  443195 */   GIR_EraseRootFromParent_Done,
     /*  443196 */ // Label 6709: @443196
     /*  443196 */ GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(443266), // Rule ID 11587 //
     /*  443201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  443204 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443207 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443211 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443224 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443228 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443235 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443235 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443243 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443260 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443264 */   GIR_RootConstrainSelectedInstOperands,
     /*  443265 */   // GIR_Coverage, 11587,
     /*  443265 */   GIR_EraseRootFromParent_Done,
     /*  443266 */ // Label 6710: @443266
     /*  443266 */ GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(443336), // Rule ID 11588 //
     /*  443271 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  443274 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443277 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443281 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443288 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443298 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443305 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443313 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443330 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443334 */   GIR_RootConstrainSelectedInstOperands,
     /*  443335 */   // GIR_Coverage, 11588,
     /*  443335 */   GIR_EraseRootFromParent_Done,
     /*  443336 */ // Label 6711: @443336
     /*  443336 */ GIM_Try, /*On fail goto*//*Label 6712*/ GIMT_Encode4(443406), // Rule ID 11589 //
     /*  443341 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  443344 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443347 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443351 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443358 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443364 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443368 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443375 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443375 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443383 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443400 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443404 */   GIR_RootConstrainSelectedInstOperands,
     /*  443405 */   // GIR_Coverage, 11589,
     /*  443405 */   GIR_EraseRootFromParent_Done,
     /*  443406 */ // Label 6712: @443406
     /*  443406 */ GIM_Try, /*On fail goto*//*Label 6713*/ GIMT_Encode4(443476), // Rule ID 11590 //
     /*  443411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  443414 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443417 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443421 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443434 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443438 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443445 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443445 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443453 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443470 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443474 */   GIR_RootConstrainSelectedInstOperands,
     /*  443475 */   // GIR_Coverage, 11590,
     /*  443475 */   GIR_EraseRootFromParent_Done,
     /*  443476 */ // Label 6713: @443476
     /*  443476 */ GIM_Try, /*On fail goto*//*Label 6714*/ GIMT_Encode4(443546), // Rule ID 11591 //
     /*  443481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  443484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443487 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  443491 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  443498 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443515 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  443518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443523 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443540 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443544 */   GIR_RootConstrainSelectedInstOperands,
     /*  443545 */   // GIR_Coverage, 11591,
     /*  443545 */   GIR_EraseRootFromParent_Done,
     /*  443546 */ // Label 6714: @443546
     /*  443546 */ GIM_Try, /*On fail goto*//*Label 6715*/ GIMT_Encode4(443605), // Rule ID 9741 //
     /*  443551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode0),
     /*  443554 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443557 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443563 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443567 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443574 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443574 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443582 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443603 */   GIR_RootConstrainSelectedInstOperands,
     /*  443604 */   // GIR_Coverage, 9741,
     /*  443604 */   GIR_EraseRootFromParent_Done,
     /*  443605 */ // Label 6715: @443605
     /*  443605 */ GIM_Try, /*On fail goto*//*Label 6716*/ GIMT_Encode4(443664), // Rule ID 9742 //
     /*  443610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode1),
     /*  443613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443616 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443622 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443626 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443633 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443633 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443641 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443658 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443662 */   GIR_RootConstrainSelectedInstOperands,
     /*  443663 */   // GIR_Coverage, 9742,
     /*  443663 */   GIR_EraseRootFromParent_Done,
     /*  443664 */ // Label 6716: @443664
     /*  443664 */ GIM_Try, /*On fail goto*//*Label 6717*/ GIMT_Encode4(443723), // Rule ID 9743 //
     /*  443669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode2),
     /*  443672 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443675 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443681 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443685 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443692 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443692 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443700 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443717 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443721 */   GIR_RootConstrainSelectedInstOperands,
     /*  443722 */   // GIR_Coverage, 9743,
     /*  443722 */   GIR_EraseRootFromParent_Done,
     /*  443723 */ // Label 6717: @443723
     /*  443723 */ GIM_Try, /*On fail goto*//*Label 6718*/ GIMT_Encode4(443782), // Rule ID 9744 //
     /*  443728 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode3),
     /*  443731 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443734 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443740 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443744 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443751 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443751 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443759 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443776 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443780 */   GIR_RootConstrainSelectedInstOperands,
     /*  443781 */   // GIR_Coverage, 9744,
     /*  443781 */   GIR_EraseRootFromParent_Done,
     /*  443782 */ // Label 6718: @443782
     /*  443782 */ GIM_Try, /*On fail goto*//*Label 6719*/ GIMT_Encode4(443841), // Rule ID 9745 //
     /*  443787 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_NotUseRealTrue16Insts_HwMode4),
     /*  443790 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443793 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443810 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443818 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443839 */   GIR_RootConstrainSelectedInstOperands,
     /*  443840 */   // GIR_Coverage, 9745,
     /*  443840 */   GIR_EraseRootFromParent_Done,
     /*  443841 */ // Label 6719: @443841
     /*  443841 */ GIM_Try, /*On fail goto*//*Label 6720*/ GIMT_Encode4(443900), // Rule ID 9883 //
     /*  443846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_HasFlatGVSMode_UseRealTrue16Insts),
     /*  443849 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443852 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443869 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR_t16 ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR_t16),
     /*  443872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443877 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443894 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443898 */   GIR_RootConstrainSelectedInstOperands,
     /*  443899 */   // GIR_Coverage, 9883,
     /*  443899 */   GIR_EraseRootFromParent_Done,
     /*  443900 */ // Label 6720: @443900
     /*  443900 */ GIM_Try, /*On fail goto*//*Label 6721*/ GIMT_Encode4(443959), // Rule ID 11597 //
     /*  443905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  443908 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443911 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443928 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443936 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  443943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  443948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  443953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  443957 */   GIR_RootConstrainSelectedInstOperands,
     /*  443958 */   // GIR_Coverage, 11597,
     /*  443958 */   GIR_EraseRootFromParent_Done,
     /*  443959 */ // Label 6721: @443959
     /*  443959 */ GIM_Try, /*On fail goto*//*Label 6722*/ GIMT_Encode4(444018), // Rule ID 11598 //
     /*  443964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  443967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  443970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  443976 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  443980 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  443987 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  443987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  443990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  443995 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  443997 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  444002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  444007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  444012 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444016 */   GIR_RootConstrainSelectedInstOperands,
     /*  444017 */   // GIR_Coverage, 11598,
     /*  444017 */   GIR_EraseRootFromParent_Done,
     /*  444018 */ // Label 6722: @444018
     /*  444018 */ GIM_Try, /*On fail goto*//*Label 6723*/ GIMT_Encode4(444077), // Rule ID 11599 //
     /*  444023 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  444026 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  444029 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  444046 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  444046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  444049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  444054 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  444061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  444066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  444071 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444075 */   GIR_RootConstrainSelectedInstOperands,
     /*  444076 */   // GIR_Coverage, 11599,
     /*  444076 */   GIR_EraseRootFromParent_Done,
     /*  444077 */ // Label 6723: @444077
     /*  444077 */ GIM_Try, /*On fail goto*//*Label 6724*/ GIMT_Encode4(444136), // Rule ID 11600 //
     /*  444082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  444085 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  444088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  444105 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  444105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  444108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  444113 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  444120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  444125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  444130 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444134 */   GIR_RootConstrainSelectedInstOperands,
     /*  444135 */   // GIR_Coverage, 11600,
     /*  444135 */   GIR_EraseRootFromParent_Done,
     /*  444136 */ // Label 6724: @444136
     /*  444136 */ GIM_Try, /*On fail goto*//*Label 6725*/ GIMT_Encode4(444195), // Rule ID 11601 //
     /*  444141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  444144 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  444147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444153 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444157 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  444164 */   // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  444164 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  444167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  444172 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  444179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  444184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  444189 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444193 */   GIR_RootConstrainSelectedInstOperands,
     /*  444194 */   // GIR_Coverage, 11601,
     /*  444194 */   GIR_EraseRootFromParent_Done,
     /*  444195 */ // Label 6725: @444195
     /*  444195 */ GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(444254), // Rule ID 9746 //
     /*  444200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  444203 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444223 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444230 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444230 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  444233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444238 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444245 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444248 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444252 */   GIR_RootConstrainSelectedInstOperands,
     /*  444253 */   // GIR_Coverage, 9746,
     /*  444253 */   GIR_EraseRootFromParent_Done,
     /*  444254 */ // Label 6726: @444254
     /*  444254 */ GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(444313), // Rule ID 9747 //
     /*  444259 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  444262 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444265 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444272 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444278 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444282 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444289 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444289 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  444292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444297 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444304 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444307 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444311 */   GIR_RootConstrainSelectedInstOperands,
     /*  444312 */   // GIR_Coverage, 9747,
     /*  444312 */   GIR_EraseRootFromParent_Done,
     /*  444313 */ // Label 6727: @444313
     /*  444313 */ GIM_Try, /*On fail goto*//*Label 6728*/ GIMT_Encode4(444372), // Rule ID 9748 //
     /*  444318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  444321 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444324 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444331 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444337 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444341 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444348 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  444351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444356 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444370 */   GIR_RootConstrainSelectedInstOperands,
     /*  444371 */   // GIR_Coverage, 9748,
     /*  444371 */   GIR_EraseRootFromParent_Done,
     /*  444372 */ // Label 6728: @444372
     /*  444372 */ GIM_Try, /*On fail goto*//*Label 6729*/ GIMT_Encode4(444431), // Rule ID 9749 //
     /*  444377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  444380 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444383 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444407 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  444410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444415 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444429 */   GIR_RootConstrainSelectedInstOperands,
     /*  444430 */   // GIR_Coverage, 9749,
     /*  444430 */   GIR_EraseRootFromParent_Done,
     /*  444431 */ // Label 6729: @444431
     /*  444431 */ GIM_Try, /*On fail goto*//*Label 6730*/ GIMT_Encode4(444490), // Rule ID 9750 //
     /*  444436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  444439 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444442 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444466 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  444469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444474 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444484 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444488 */   GIR_RootConstrainSelectedInstOperands,
     /*  444489 */   // GIR_Coverage, 9750,
     /*  444489 */   GIR_EraseRootFromParent_Done,
     /*  444490 */ // Label 6730: @444490
     /*  444490 */ GIM_Try, /*On fail goto*//*Label 6731*/ GIMT_Encode4(444549), // Rule ID 9756 //
     /*  444495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  444498 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444501 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  444508 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444525 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444525 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  444528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444533 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444547 */   GIR_RootConstrainSelectedInstOperands,
     /*  444548 */   // GIR_Coverage, 9756,
     /*  444548 */   GIR_EraseRootFromParent_Done,
     /*  444549 */ // Label 6731: @444549
     /*  444549 */ GIM_Try, /*On fail goto*//*Label 6732*/ GIMT_Encode4(444608), // Rule ID 9757 //
     /*  444554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  444557 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444560 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  444567 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444577 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444584 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  444587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444592 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444606 */   GIR_RootConstrainSelectedInstOperands,
     /*  444607 */   // GIR_Coverage, 9757,
     /*  444607 */   GIR_EraseRootFromParent_Done,
     /*  444608 */ // Label 6732: @444608
     /*  444608 */ GIM_Try, /*On fail goto*//*Label 6733*/ GIMT_Encode4(444667), // Rule ID 9758 //
     /*  444613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  444616 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444619 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  444626 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444643 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  444646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444651 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444658 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444661 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444665 */   GIR_RootConstrainSelectedInstOperands,
     /*  444666 */   // GIR_Coverage, 9758,
     /*  444666 */   GIR_EraseRootFromParent_Done,
     /*  444667 */ // Label 6733: @444667
     /*  444667 */ GIM_Try, /*On fail goto*//*Label 6734*/ GIMT_Encode4(444726), // Rule ID 9759 //
     /*  444672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  444675 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444678 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  444685 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444691 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444695 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444702 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444702 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  444705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444710 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444717 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444720 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444724 */   GIR_RootConstrainSelectedInstOperands,
     /*  444725 */   // GIR_Coverage, 9759,
     /*  444725 */   GIR_EraseRootFromParent_Done,
     /*  444726 */ // Label 6734: @444726
     /*  444726 */ GIM_Try, /*On fail goto*//*Label 6735*/ GIMT_Encode4(444785), // Rule ID 9760 //
     /*  444731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  444734 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444737 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  444744 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444761 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  444764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444769 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444783 */   GIR_RootConstrainSelectedInstOperands,
     /*  444784 */   // GIR_Coverage, 9760,
     /*  444784 */   GIR_EraseRootFromParent_Done,
     /*  444785 */ // Label 6735: @444785
     /*  444785 */ GIM_Try, /*On fail goto*//*Label 6736*/ GIMT_Encode4(444844), // Rule ID 9884 //
     /*  444790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  444793 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444796 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444820 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  444823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444828 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444835 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444838 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444842 */   GIR_RootConstrainSelectedInstOperands,
     /*  444843 */   // GIR_Coverage, 9884,
     /*  444843 */   GIR_EraseRootFromParent_Done,
     /*  444844 */ // Label 6736: @444844
     /*  444844 */ GIM_Try, /*On fail goto*//*Label 6737*/ GIMT_Encode4(444903), // Rule ID 9885 //
     /*  444849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  444852 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444855 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444862 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444879 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  444882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444887 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444894 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444897 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444901 */   GIR_RootConstrainSelectedInstOperands,
     /*  444902 */   // GIR_Coverage, 9885,
     /*  444902 */   GIR_EraseRootFromParent_Done,
     /*  444903 */ // Label 6737: @444903
     /*  444903 */ GIM_Try, /*On fail goto*//*Label 6738*/ GIMT_Encode4(444962), // Rule ID 9886 //
     /*  444908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  444911 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444914 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444921 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444927 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444931 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444938 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  444941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  444946 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  444948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  444953 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  444956 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  444960 */   GIR_RootConstrainSelectedInstOperands,
     /*  444961 */   // GIR_Coverage, 9886,
     /*  444961 */   GIR_EraseRootFromParent_Done,
     /*  444962 */ // Label 6738: @444962
     /*  444962 */ GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(445021), // Rule ID 9887 //
     /*  444967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  444970 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  444973 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  444980 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  444986 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  444990 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  444997 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  444997 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445005 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445012 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445015 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445019 */   GIR_RootConstrainSelectedInstOperands,
     /*  445020 */   // GIR_Coverage, 9887,
     /*  445020 */   GIR_EraseRootFromParent_Done,
     /*  445021 */ // Label 6739: @445021
     /*  445021 */ GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(445080), // Rule ID 9888 //
     /*  445026 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  445029 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  445032 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445039 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445045 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445049 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445056 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445056 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445064 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445074 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445078 */   GIR_RootConstrainSelectedInstOperands,
     /*  445079 */   // GIR_Coverage, 9888,
     /*  445079 */   GIR_EraseRootFromParent_Done,
     /*  445080 */ // Label 6740: @445080
     /*  445080 */ GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(445139), // Rule ID 9890 //
     /*  445085 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  445088 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  445091 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  445098 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445104 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445108 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445115 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445115 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  445118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445123 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445133 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445137 */   GIR_RootConstrainSelectedInstOperands,
     /*  445138 */   // GIR_Coverage, 9890,
     /*  445138 */   GIR_EraseRootFromParent_Done,
     /*  445139 */ // Label 6741: @445139
     /*  445139 */ GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(445198), // Rule ID 9891 //
     /*  445144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  445147 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  445150 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  445157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445163 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445167 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445174 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445174 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  445177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445182 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445189 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445192 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445196 */   GIR_RootConstrainSelectedInstOperands,
     /*  445197 */   // GIR_Coverage, 9891,
     /*  445197 */   GIR_EraseRootFromParent_Done,
     /*  445198 */ // Label 6742: @445198
     /*  445198 */ GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(445257), // Rule ID 9892 //
     /*  445203 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  445206 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  445209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  445216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445222 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445226 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445233 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  445236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445241 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445248 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445251 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445255 */   GIR_RootConstrainSelectedInstOperands,
     /*  445256 */   // GIR_Coverage, 9892,
     /*  445256 */   GIR_EraseRootFromParent_Done,
     /*  445257 */ // Label 6743: @445257
     /*  445257 */ GIM_Try, /*On fail goto*//*Label 6744*/ GIMT_Encode4(445316), // Rule ID 9893 //
     /*  445262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  445265 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  445268 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  445275 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445281 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445285 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445292 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  445295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445300 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445310 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445314 */   GIR_RootConstrainSelectedInstOperands,
     /*  445315 */   // GIR_Coverage, 9893,
     /*  445315 */   GIR_EraseRootFromParent_Done,
     /*  445316 */ // Label 6744: @445316
     /*  445316 */ GIM_Try, /*On fail goto*//*Label 6745*/ GIMT_Encode4(445375), // Rule ID 9894 //
     /*  445321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  445324 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  445327 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  445334 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445340 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445344 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445351 */   // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  445354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445359 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445373 */   GIR_RootConstrainSelectedInstOperands,
     /*  445374 */   // GIR_Coverage, 9894,
     /*  445374 */   GIR_EraseRootFromParent_Done,
     /*  445375 */ // Label 6745: @445375
     /*  445375 */ GIM_Try, /*On fail goto*//*Label 6746*/ GIMT_Encode4(445438), // Rule ID 9510 //
     /*  445380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  445383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445386 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445390 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445397 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445414 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  445417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445422 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445436 */   GIR_RootConstrainSelectedInstOperands,
     /*  445437 */   // GIR_Coverage, 9510,
     /*  445437 */   GIR_EraseRootFromParent_Done,
     /*  445438 */ // Label 6746: @445438
     /*  445438 */ GIM_Try, /*On fail goto*//*Label 6747*/ GIMT_Encode4(445501), // Rule ID 9511 //
     /*  445443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  445446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445449 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445453 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445460 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445466 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445470 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445477 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445477 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  445480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445485 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445495 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445499 */   GIR_RootConstrainSelectedInstOperands,
     /*  445500 */   // GIR_Coverage, 9511,
     /*  445500 */   GIR_EraseRootFromParent_Done,
     /*  445501 */ // Label 6747: @445501
     /*  445501 */ GIM_Try, /*On fail goto*//*Label 6748*/ GIMT_Encode4(445564), // Rule ID 9512 //
     /*  445506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  445509 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445512 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445516 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445523 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445540 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  445543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445548 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445562 */   GIR_RootConstrainSelectedInstOperands,
     /*  445563 */   // GIR_Coverage, 9512,
     /*  445563 */   GIR_EraseRootFromParent_Done,
     /*  445564 */ // Label 6748: @445564
     /*  445564 */ GIM_Try, /*On fail goto*//*Label 6749*/ GIMT_Encode4(445627), // Rule ID 9513 //
     /*  445569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  445572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445575 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445579 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445586 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445592 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445596 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445603 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  445606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445611 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445618 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445621 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445625 */   GIR_RootConstrainSelectedInstOperands,
     /*  445626 */   // GIR_Coverage, 9513,
     /*  445626 */   GIR_EraseRootFromParent_Done,
     /*  445627 */ // Label 6749: @445627
     /*  445627 */ GIM_Try, /*On fail goto*//*Label 6750*/ GIMT_Encode4(445690), // Rule ID 9514 //
     /*  445632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  445635 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445638 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445642 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445655 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445666 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  445669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445674 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445688 */   GIR_RootConstrainSelectedInstOperands,
     /*  445689 */   // GIR_Coverage, 9514,
     /*  445689 */   GIR_EraseRootFromParent_Done,
     /*  445690 */ // Label 6750: @445690
     /*  445690 */ GIM_Try, /*On fail goto*//*Label 6751*/ GIMT_Encode4(445753), // Rule ID 9520 //
     /*  445695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  445698 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445701 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445705 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445712 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445718 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445722 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445729 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445737 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445744 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445747 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445751 */   GIR_RootConstrainSelectedInstOperands,
     /*  445752 */   // GIR_Coverage, 9520,
     /*  445752 */   GIR_EraseRootFromParent_Done,
     /*  445753 */ // Label 6751: @445753
     /*  445753 */ GIM_Try, /*On fail goto*//*Label 6752*/ GIMT_Encode4(445816), // Rule ID 9521 //
     /*  445758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  445761 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445764 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445768 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445781 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445785 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445792 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445792 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445800 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445807 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445810 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445814 */   GIR_RootConstrainSelectedInstOperands,
     /*  445815 */   // GIR_Coverage, 9521,
     /*  445815 */   GIR_EraseRootFromParent_Done,
     /*  445816 */ // Label 6752: @445816
     /*  445816 */ GIM_Try, /*On fail goto*//*Label 6753*/ GIMT_Encode4(445879), // Rule ID 9522 //
     /*  445821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  445824 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445827 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445831 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445838 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445844 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445848 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445855 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445855 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445863 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445870 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445873 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445877 */   GIR_RootConstrainSelectedInstOperands,
     /*  445878 */   // GIR_Coverage, 9522,
     /*  445878 */   GIR_EraseRootFromParent_Done,
     /*  445879 */ // Label 6753: @445879
     /*  445879 */ GIM_Try, /*On fail goto*//*Label 6754*/ GIMT_Encode4(445942), // Rule ID 9523 //
     /*  445884 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  445887 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445890 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445894 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445901 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445907 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445911 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445918 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445918 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445926 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445933 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445936 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  445940 */   GIR_RootConstrainSelectedInstOperands,
     /*  445941 */   // GIR_Coverage, 9523,
     /*  445941 */   GIR_EraseRootFromParent_Done,
     /*  445942 */ // Label 6754: @445942
     /*  445942 */ GIM_Try, /*On fail goto*//*Label 6755*/ GIMT_Encode4(446005), // Rule ID 9524 //
     /*  445947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  445950 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  445953 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  445957 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  445964 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  445970 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  445974 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  445981 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  445981 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_t16),
     /*  445984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  445989 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  445991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  445996 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  445999 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446003 */   GIR_RootConstrainSelectedInstOperands,
     /*  446004 */   // GIR_Coverage, 9524,
     /*  446004 */   GIR_EraseRootFromParent_Done,
     /*  446005 */ // Label 6755: @446005
     /*  446005 */ GIM_Try, /*On fail goto*//*Label 6756*/ GIMT_Encode4(446068), // Rule ID 11582 //
     /*  446010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  446013 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446016 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  446020 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  446027 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446033 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446037 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446044 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446044 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  446047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446052 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446059 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446062 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446066 */   GIR_RootConstrainSelectedInstOperands,
     /*  446067 */   // GIR_Coverage, 11582,
     /*  446067 */   GIR_EraseRootFromParent_Done,
     /*  446068 */ // Label 6756: @446068
     /*  446068 */ GIM_Try, /*On fail goto*//*Label 6757*/ GIMT_Encode4(446131), // Rule ID 11583 //
     /*  446073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  446076 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446079 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  446083 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  446090 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446096 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446100 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446107 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  446110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446115 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446122 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446125 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446129 */   GIR_RootConstrainSelectedInstOperands,
     /*  446130 */   // GIR_Coverage, 11583,
     /*  446130 */   GIR_EraseRootFromParent_Done,
     /*  446131 */ // Label 6757: @446131
     /*  446131 */ GIM_Try, /*On fail goto*//*Label 6758*/ GIMT_Encode4(446194), // Rule ID 11584 //
     /*  446136 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  446139 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446142 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  446146 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  446153 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446170 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  446173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446178 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446185 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446188 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446192 */   GIR_RootConstrainSelectedInstOperands,
     /*  446193 */   // GIR_Coverage, 11584,
     /*  446193 */   GIR_EraseRootFromParent_Done,
     /*  446194 */ // Label 6758: @446194
     /*  446194 */ GIM_Try, /*On fail goto*//*Label 6759*/ GIMT_Encode4(446257), // Rule ID 11585 //
     /*  446199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  446202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446205 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  446209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  446216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446222 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446226 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446233 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446233 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  446236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446241 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446248 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446251 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446255 */   GIR_RootConstrainSelectedInstOperands,
     /*  446256 */   // GIR_Coverage, 11585,
     /*  446256 */   GIR_EraseRootFromParent_Done,
     /*  446257 */ // Label 6759: @446257
     /*  446257 */ GIM_Try, /*On fail goto*//*Label 6760*/ GIMT_Encode4(446320), // Rule ID 11586 //
     /*  446262 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  446265 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446268 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  446272 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  446279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446296 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  446299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446304 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446314 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446318 */   GIR_RootConstrainSelectedInstOperands,
     /*  446319 */   // GIR_Coverage, 11586,
     /*  446319 */   GIR_EraseRootFromParent_Done,
     /*  446320 */ // Label 6760: @446320
     /*  446320 */ GIM_Try, /*On fail goto*//*Label 6761*/ GIMT_Encode4(446372), // Rule ID 9736 //
     /*  446325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode0),
     /*  446328 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446331 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446337 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446341 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446348 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446356 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446370 */   GIR_RootConstrainSelectedInstOperands,
     /*  446371 */   // GIR_Coverage, 9736,
     /*  446371 */   GIR_EraseRootFromParent_Done,
     /*  446372 */ // Label 6761: @446372
     /*  446372 */ GIM_Try, /*On fail goto*//*Label 6762*/ GIMT_Encode4(446424), // Rule ID 9737 //
     /*  446377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode1),
     /*  446380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446389 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446393 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446400 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446408 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446415 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446418 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446422 */   GIR_RootConstrainSelectedInstOperands,
     /*  446423 */   // GIR_Coverage, 9737,
     /*  446423 */   GIR_EraseRootFromParent_Done,
     /*  446424 */ // Label 6762: @446424
     /*  446424 */ GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(446476), // Rule ID 9738 //
     /*  446429 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode2),
     /*  446432 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446435 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446441 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446452 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446460 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446467 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446470 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446474 */   GIR_RootConstrainSelectedInstOperands,
     /*  446475 */   // GIR_Coverage, 9738,
     /*  446475 */   GIR_EraseRootFromParent_Done,
     /*  446476 */ // Label 6763: @446476
     /*  446476 */ GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(446528), // Rule ID 9739 //
     /*  446481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode3),
     /*  446484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446487 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446493 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446497 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446504 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446512 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446519 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446522 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446526 */   GIR_RootConstrainSelectedInstOperands,
     /*  446527 */   // GIR_Coverage, 9739,
     /*  446527 */   GIR_EraseRootFromParent_Done,
     /*  446528 */ // Label 6764: @446528
     /*  446528 */ GIM_Try, /*On fail goto*//*Label 6765*/ GIMT_Encode4(446580), // Rule ID 9740 //
     /*  446533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_NotUseRealTrue16Insts_HwMode4),
     /*  446536 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446539 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446545 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446549 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446556 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446556 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446564 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446578 */   GIR_RootConstrainSelectedInstOperands,
     /*  446579 */   // GIR_Coverage, 9740,
     /*  446579 */   GIR_EraseRootFromParent_Done,
     /*  446580 */ // Label 6765: @446580
     /*  446580 */ GIM_Try, /*On fail goto*//*Label 6766*/ GIMT_Encode4(446632), // Rule ID 9878 //
     /*  446585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode0),
     /*  446588 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446597 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446601 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446608 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  446611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446616 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446623 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446626 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446630 */   GIR_RootConstrainSelectedInstOperands,
     /*  446631 */   // GIR_Coverage, 9878,
     /*  446631 */   GIR_EraseRootFromParent_Done,
     /*  446632 */ // Label 6766: @446632
     /*  446632 */ GIM_Try, /*On fail goto*//*Label 6767*/ GIMT_Encode4(446684), // Rule ID 9879 //
     /*  446637 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode1),
     /*  446640 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446660 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  446663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446668 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446678 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446682 */   GIR_RootConstrainSelectedInstOperands,
     /*  446683 */   // GIR_Coverage, 9879,
     /*  446683 */   GIR_EraseRootFromParent_Done,
     /*  446684 */ // Label 6767: @446684
     /*  446684 */ GIM_Try, /*On fail goto*//*Label 6768*/ GIMT_Encode4(446736), // Rule ID 9880 //
     /*  446689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode2),
     /*  446692 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446705 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446712 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  446715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446720 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446727 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446730 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446734 */   GIR_RootConstrainSelectedInstOperands,
     /*  446735 */   // GIR_Coverage, 9880,
     /*  446735 */   GIR_EraseRootFromParent_Done,
     /*  446736 */ // Label 6768: @446736
     /*  446736 */ GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(446788), // Rule ID 9881 //
     /*  446741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode3),
     /*  446744 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446747 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446753 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446757 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446764 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  446767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446772 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446782 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446786 */   GIR_RootConstrainSelectedInstOperands,
     /*  446787 */   // GIR_Coverage, 9881,
     /*  446787 */   GIR_EraseRootFromParent_Done,
     /*  446788 */ // Label 6769: @446788
     /*  446788 */ GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(446840), // Rule ID 9882 //
     /*  446793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_D16PreservesUnusedBits_UseRealTrue16Insts_HwMode4),
     /*  446796 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446805 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446809 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446816 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT_t16 ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_t16),
     /*  446819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446824 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446831 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446834 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446838 */   GIR_RootConstrainSelectedInstOperands,
     /*  446839 */   // GIR_Coverage, 9882,
     /*  446839 */   GIR_EraseRootFromParent_Done,
     /*  446840 */ // Label 6770: @446840
     /*  446840 */ GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(446892), // Rule ID 11592 //
     /*  446845 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  446848 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446851 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446857 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446861 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446868 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446868 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446876 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446883 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446886 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446890 */   GIR_RootConstrainSelectedInstOperands,
     /*  446891 */   // GIR_Coverage, 11592,
     /*  446891 */   GIR_EraseRootFromParent_Done,
     /*  446892 */ // Label 6771: @446892
     /*  446892 */ GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(446944), // Rule ID 11593 //
     /*  446897 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  446900 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446903 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446909 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446913 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446920 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446928 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446930 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446935 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446938 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446942 */   GIR_RootConstrainSelectedInstOperands,
     /*  446943 */   // GIR_Coverage, 11593,
     /*  446943 */   GIR_EraseRootFromParent_Done,
     /*  446944 */ // Label 6772: @446944
     /*  446944 */ GIM_Try, /*On fail goto*//*Label 6773*/ GIMT_Encode4(446996), // Rule ID 11594 //
     /*  446949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  446952 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  446955 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  446961 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  446965 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  446972 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  446972 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  446975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  446980 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  446982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  446987 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  446990 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  446994 */   GIR_RootConstrainSelectedInstOperands,
     /*  446995 */   // GIR_Coverage, 11594,
     /*  446995 */   GIR_EraseRootFromParent_Done,
     /*  446996 */ // Label 6773: @446996
     /*  446996 */ GIM_Try, /*On fail goto*//*Label 6774*/ GIMT_Encode4(447048), // Rule ID 11595 //
     /*  447001 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  447004 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  447013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447017 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  447024 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  447024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  447027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  447032 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  447034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  447039 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447042 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  447046 */   GIR_RootConstrainSelectedInstOperands,
     /*  447047 */   // GIR_Coverage, 11595,
     /*  447047 */   GIR_EraseRootFromParent_Done,
     /*  447048 */ // Label 6774: @447048
     /*  447048 */ GIM_Try, /*On fail goto*//*Label 6775*/ GIMT_Encode4(447100), // Rule ID 11596 //
     /*  447053 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  447056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447059 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  447065 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447069 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  447076 */   // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  447076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  447079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  447084 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  447086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  447091 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447094 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  447098 */   GIR_RootConstrainSelectedInstOperands,
     /*  447099 */   // GIR_Coverage, 11596,
     /*  447099 */   GIR_EraseRootFromParent_Done,
     /*  447100 */ // Label 6775: @447100
     /*  447100 */ GIM_Reject,
     /*  447101 */ // Label 5866: @447101
     /*  447101 */ GIM_Try, /*On fail goto*//*Label 6776*/ GIMT_Encode4(447196), // Rule ID 26006 //
     /*  447106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode0),
     /*  447109 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447112 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447116 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447123 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447128 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447132 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447136 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447140 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447144 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447152 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447154 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447161 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET),
     /*  447164 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447183 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447186 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447189 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447194 */   GIR_RootConstrainSelectedInstOperands,
     /*  447195 */   // GIR_Coverage, 26006,
     /*  447195 */   GIR_EraseRootFromParent_Done,
     /*  447196 */ // Label 6776: @447196
     /*  447196 */ GIM_Try, /*On fail goto*//*Label 6777*/ GIMT_Encode4(447291), // Rule ID 26007 //
     /*  447201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode1),
     /*  447204 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447207 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447211 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447223 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447227 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447231 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447235 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447239 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447247 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447256 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET),
     /*  447259 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447278 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447284 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447289 */   GIR_RootConstrainSelectedInstOperands,
     /*  447290 */   // GIR_Coverage, 26007,
     /*  447290 */   GIR_EraseRootFromParent_Done,
     /*  447291 */ // Label 6777: @447291
     /*  447291 */ GIM_Try, /*On fail goto*//*Label 6778*/ GIMT_Encode4(447386), // Rule ID 26008 //
     /*  447296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode2),
     /*  447299 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447302 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447313 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447318 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447322 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447326 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447330 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447334 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447338 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447342 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447344 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447351 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET),
     /*  447354 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447373 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447376 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447384 */   GIR_RootConstrainSelectedInstOperands,
     /*  447385 */   // GIR_Coverage, 26008,
     /*  447385 */   GIR_EraseRootFromParent_Done,
     /*  447386 */ // Label 6778: @447386
     /*  447386 */ GIM_Try, /*On fail goto*//*Label 6779*/ GIMT_Encode4(447481), // Rule ID 26009 //
     /*  447391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode3),
     /*  447394 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447397 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447401 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447408 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447413 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447417 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447421 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447425 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447429 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447433 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447437 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447439 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447446 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447446 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET),
     /*  447449 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447479 */   GIR_RootConstrainSelectedInstOperands,
     /*  447480 */   // GIR_Coverage, 26009,
     /*  447480 */   GIR_EraseRootFromParent_Done,
     /*  447481 */ // Label 6779: @447481
     /*  447481 */ GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(447576), // Rule ID 26010 //
     /*  447486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode4),
     /*  447489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447492 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447508 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447512 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447516 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447520 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447524 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447532 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447541 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET),
     /*  447544 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447563 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447569 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447574 */   GIR_RootConstrainSelectedInstOperands,
     /*  447575 */   // GIR_Coverage, 26010,
     /*  447575 */   GIR_EraseRootFromParent_Done,
     /*  447576 */ // Label 6780: @447576
     /*  447576 */ GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(447671), // Rule ID 26016 //
     /*  447581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode0),
     /*  447584 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447587 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447591 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447598 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447603 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447607 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447611 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447615 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447619 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447627 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447629 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447636 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET),
     /*  447639 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447658 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447661 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447664 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447669 */   GIR_RootConstrainSelectedInstOperands,
     /*  447670 */   // GIR_Coverage, 26016,
     /*  447670 */   GIR_EraseRootFromParent_Done,
     /*  447671 */ // Label 6781: @447671
     /*  447671 */ GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(447766), // Rule ID 26017 //
     /*  447676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode1),
     /*  447679 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447682 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447698 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447702 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447706 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447710 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447714 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447718 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447722 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447724 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447731 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET),
     /*  447734 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447753 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447756 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447759 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447764 */   GIR_RootConstrainSelectedInstOperands,
     /*  447765 */   // GIR_Coverage, 26017,
     /*  447765 */   GIR_EraseRootFromParent_Done,
     /*  447766 */ // Label 6782: @447766
     /*  447766 */ GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(447861), // Rule ID 26018 //
     /*  447771 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode2),
     /*  447774 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447777 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447781 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447793 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447797 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447801 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447805 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447809 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447813 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447817 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447819 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447826 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET),
     /*  447829 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447851 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447854 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447859 */   GIR_RootConstrainSelectedInstOperands,
     /*  447860 */   // GIR_Coverage, 26018,
     /*  447860 */   GIR_EraseRootFromParent_Done,
     /*  447861 */ // Label 6783: @447861
     /*  447861 */ GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(447956), // Rule ID 26019 //
     /*  447866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode3),
     /*  447869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447872 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447876 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447888 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447892 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447896 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447900 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447904 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  447908 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  447912 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  447914 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  447921 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  447921 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET),
     /*  447924 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  447928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  447933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  447938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  447943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447946 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  447949 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  447954 */   GIR_RootConstrainSelectedInstOperands,
     /*  447955 */   // GIR_Coverage, 26019,
     /*  447955 */   GIR_EraseRootFromParent_Done,
     /*  447956 */ // Label 6784: @447956
     /*  447956 */ GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(448051), // Rule ID 26020 //
     /*  447961 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode4),
     /*  447964 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  447967 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  447971 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  447978 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  447983 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  447987 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  447991 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  447995 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  447999 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448003 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448007 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448009 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448016 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448016 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET),
     /*  448019 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448038 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448049 */   GIR_RootConstrainSelectedInstOperands,
     /*  448050 */   // GIR_Coverage, 26020,
     /*  448050 */   GIR_EraseRootFromParent_Done,
     /*  448051 */ // Label 6785: @448051
     /*  448051 */ GIM_Try, /*On fail goto*//*Label 6786*/ GIMT_Encode4(448146), // Rule ID 26026 //
     /*  448056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode0),
     /*  448059 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448062 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448066 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448078 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448082 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448086 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448090 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448094 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448098 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448102 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448104 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448111 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448111 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET),
     /*  448114 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448133 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448139 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448144 */   GIR_RootConstrainSelectedInstOperands,
     /*  448145 */   // GIR_Coverage, 26026,
     /*  448145 */   GIR_EraseRootFromParent_Done,
     /*  448146 */ // Label 6786: @448146
     /*  448146 */ GIM_Try, /*On fail goto*//*Label 6787*/ GIMT_Encode4(448241), // Rule ID 26027 //
     /*  448151 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode1),
     /*  448154 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448157 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448161 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448168 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448173 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448177 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448181 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448185 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448189 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448197 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448199 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448206 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448206 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET),
     /*  448209 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448228 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448231 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448234 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448239 */   GIR_RootConstrainSelectedInstOperands,
     /*  448240 */   // GIR_Coverage, 26027,
     /*  448240 */   GIR_EraseRootFromParent_Done,
     /*  448241 */ // Label 6787: @448241
     /*  448241 */ GIM_Try, /*On fail goto*//*Label 6788*/ GIMT_Encode4(448336), // Rule ID 26028 //
     /*  448246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode2),
     /*  448249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448252 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448268 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448272 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448276 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448280 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448284 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448288 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448292 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448294 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448301 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448301 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET),
     /*  448304 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448334 */   GIR_RootConstrainSelectedInstOperands,
     /*  448335 */   // GIR_Coverage, 26028,
     /*  448335 */   GIR_EraseRootFromParent_Done,
     /*  448336 */ // Label 6788: @448336
     /*  448336 */ GIM_Try, /*On fail goto*//*Label 6789*/ GIMT_Encode4(448431), // Rule ID 26029 //
     /*  448341 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode3),
     /*  448344 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448347 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448351 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448358 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448363 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448367 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448371 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448375 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448379 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448383 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448387 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448396 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET),
     /*  448399 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448421 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448424 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448429 */   GIR_RootConstrainSelectedInstOperands,
     /*  448430 */   // GIR_Coverage, 26029,
     /*  448430 */   GIR_EraseRootFromParent_Done,
     /*  448431 */ // Label 6789: @448431
     /*  448431 */ GIM_Try, /*On fail goto*//*Label 6790*/ GIMT_Encode4(448526), // Rule ID 26030 //
     /*  448436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode4),
     /*  448439 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448442 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448446 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448453 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448458 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448462 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448466 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448470 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448474 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448482 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448484 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448491 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET),
     /*  448494 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448513 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448516 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448519 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448524 */   GIR_RootConstrainSelectedInstOperands,
     /*  448525 */   // GIR_Coverage, 26030,
     /*  448525 */   GIR_EraseRootFromParent_Done,
     /*  448526 */ // Label 6790: @448526
     /*  448526 */ GIM_Try, /*On fail goto*//*Label 6791*/ GIMT_Encode4(448621), // Rule ID 26036 //
     /*  448531 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode0),
     /*  448534 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448537 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448541 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448548 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448553 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448557 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448561 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448565 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448569 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448577 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448579 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448586 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448586 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET),
     /*  448589 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448608 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448611 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448614 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448619 */   GIR_RootConstrainSelectedInstOperands,
     /*  448620 */   // GIR_Coverage, 26036,
     /*  448620 */   GIR_EraseRootFromParent_Done,
     /*  448621 */ // Label 6791: @448621
     /*  448621 */ GIM_Try, /*On fail goto*//*Label 6792*/ GIMT_Encode4(448716), // Rule ID 26037 //
     /*  448626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode1),
     /*  448629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448632 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448636 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448648 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448652 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448656 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448660 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448664 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448668 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448672 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448674 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448681 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET),
     /*  448684 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448703 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448706 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448709 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448714 */   GIR_RootConstrainSelectedInstOperands,
     /*  448715 */   // GIR_Coverage, 26037,
     /*  448715 */   GIR_EraseRootFromParent_Done,
     /*  448716 */ // Label 6792: @448716
     /*  448716 */ GIM_Try, /*On fail goto*//*Label 6793*/ GIMT_Encode4(448811), // Rule ID 26038 //
     /*  448721 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode2),
     /*  448724 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448727 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448738 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448743 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448747 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448751 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448755 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448759 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448767 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448776 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET),
     /*  448779 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448804 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448809 */   GIR_RootConstrainSelectedInstOperands,
     /*  448810 */   // GIR_Coverage, 26038,
     /*  448810 */   GIR_EraseRootFromParent_Done,
     /*  448811 */ // Label 6793: @448811
     /*  448811 */ GIM_Try, /*On fail goto*//*Label 6794*/ GIMT_Encode4(448906), // Rule ID 26039 //
     /*  448816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode3),
     /*  448819 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448822 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448826 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448833 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448838 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448842 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448846 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448850 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448854 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448862 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448864 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448871 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448871 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET),
     /*  448874 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448893 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448904 */   GIR_RootConstrainSelectedInstOperands,
     /*  448905 */   // GIR_Coverage, 26039,
     /*  448905 */   GIR_EraseRootFromParent_Done,
     /*  448906 */ // Label 6794: @448906
     /*  448906 */ GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(449001), // Rule ID 26040 //
     /*  448911 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode4),
     /*  448914 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  448917 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  448921 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  448928 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  448933 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  448937 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  448941 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  448945 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  448949 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  448953 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  448957 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  448959 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  448966 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  448966 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET),
     /*  448969 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  448973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  448978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  448983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  448988 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448991 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  448994 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  448999 */   GIR_RootConstrainSelectedInstOperands,
     /*  449000 */   // GIR_Coverage, 26040,
     /*  449000 */   GIR_EraseRootFromParent_Done,
     /*  449001 */ // Label 6795: @449001
     /*  449001 */ GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(449095), // Rule ID 14812 //
     /*  449006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  449009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449012 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  449023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449028 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449032 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449036 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449040 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449044 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449048 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449052 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449054 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449061 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS),
     /*  449064 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449088 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449093 */   GIR_RootConstrainSelectedInstOperands,
     /*  449094 */   // GIR_Coverage, 14812,
     /*  449094 */   GIR_EraseRootFromParent_Done,
     /*  449095 */ // Label 6796: @449095
     /*  449095 */ GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(449189), // Rule ID 14813 //
     /*  449100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  449103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449106 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  449117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449122 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449126 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449130 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449134 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449138 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449142 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449146 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449148 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449155 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS),
     /*  449158 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449182 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449187 */   GIR_RootConstrainSelectedInstOperands,
     /*  449188 */   // GIR_Coverage, 14813,
     /*  449188 */   GIR_EraseRootFromParent_Done,
     /*  449189 */ // Label 6797: @449189
     /*  449189 */ GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(449283), // Rule ID 14814 //
     /*  449194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  449197 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449200 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449204 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  449211 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449216 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449220 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449224 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449228 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449232 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449236 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449240 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449249 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS),
     /*  449252 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449276 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449281 */   GIR_RootConstrainSelectedInstOperands,
     /*  449282 */   // GIR_Coverage, 14814,
     /*  449282 */   GIR_EraseRootFromParent_Done,
     /*  449283 */ // Label 6798: @449283
     /*  449283 */ GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(449377), // Rule ID 14815 //
     /*  449288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  449291 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449294 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449298 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  449305 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449310 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449314 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449318 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449322 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449326 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449334 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449343 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS),
     /*  449346 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449370 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449375 */   GIR_RootConstrainSelectedInstOperands,
     /*  449376 */   // GIR_Coverage, 14815,
     /*  449376 */   GIR_EraseRootFromParent_Done,
     /*  449377 */ // Label 6799: @449377
     /*  449377 */ GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(449471), // Rule ID 14816 //
     /*  449382 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  449385 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449388 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449392 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  449399 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449404 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449408 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449412 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449416 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449420 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449424 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449428 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449430 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449437 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS),
     /*  449440 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449464 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449469 */   GIR_RootConstrainSelectedInstOperands,
     /*  449470 */   // GIR_Coverage, 14816,
     /*  449470 */   GIR_EraseRootFromParent_Done,
     /*  449471 */ // Label 6800: @449471
     /*  449471 */ GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(449565), // Rule ID 14827 //
     /*  449476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  449479 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449482 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449486 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  449493 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449498 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449502 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449506 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449510 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449514 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449518 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449522 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449524 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449531 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449531 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS),
     /*  449534 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449563 */   GIR_RootConstrainSelectedInstOperands,
     /*  449564 */   // GIR_Coverage, 14827,
     /*  449564 */   GIR_EraseRootFromParent_Done,
     /*  449565 */ // Label 6801: @449565
     /*  449565 */ GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(449659), // Rule ID 14828 //
     /*  449570 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  449573 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449576 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449580 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  449587 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449592 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449596 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449600 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449604 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449608 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449616 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449618 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449625 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS),
     /*  449628 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449657 */   GIR_RootConstrainSelectedInstOperands,
     /*  449658 */   // GIR_Coverage, 14828,
     /*  449658 */   GIR_EraseRootFromParent_Done,
     /*  449659 */ // Label 6802: @449659
     /*  449659 */ GIM_Try, /*On fail goto*//*Label 6803*/ GIMT_Encode4(449753), // Rule ID 14829 //
     /*  449664 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  449667 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449670 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449674 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  449681 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449686 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449690 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449694 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449698 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449702 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449706 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449710 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449719 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS),
     /*  449722 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449746 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449751 */   GIR_RootConstrainSelectedInstOperands,
     /*  449752 */   // GIR_Coverage, 14829,
     /*  449752 */   GIR_EraseRootFromParent_Done,
     /*  449753 */ // Label 6803: @449753
     /*  449753 */ GIM_Try, /*On fail goto*//*Label 6804*/ GIMT_Encode4(449847), // Rule ID 14830 //
     /*  449758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  449761 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449764 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449768 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  449775 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449780 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449784 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449788 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449792 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449796 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449800 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449804 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449806 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449813 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449813 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS),
     /*  449816 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449840 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449845 */   GIR_RootConstrainSelectedInstOperands,
     /*  449846 */   // GIR_Coverage, 14830,
     /*  449846 */   GIR_EraseRootFromParent_Done,
     /*  449847 */ // Label 6804: @449847
     /*  449847 */ GIM_Try, /*On fail goto*//*Label 6805*/ GIMT_Encode4(449941), // Rule ID 14831 //
     /*  449852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  449855 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449858 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449862 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  449869 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449874 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449878 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449882 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449886 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449890 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449898 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  449907 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  449907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS),
     /*  449910 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  449914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  449919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  449924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  449929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  449934 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  449939 */   GIR_RootConstrainSelectedInstOperands,
     /*  449940 */   // GIR_Coverage, 14831,
     /*  449940 */   GIR_EraseRootFromParent_Done,
     /*  449941 */ // Label 6805: @449941
     /*  449941 */ GIM_Try, /*On fail goto*//*Label 6806*/ GIMT_Encode4(450028), // Rule ID 14807 //
     /*  449946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode0),
     /*  449949 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  449952 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  449956 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  449963 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  449968 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  449972 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  449976 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  449980 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  449984 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  449988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  449992 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  449994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450001 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR),
     /*  450004 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450021 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450026 */   GIR_RootConstrainSelectedInstOperands,
     /*  450027 */   // GIR_Coverage, 14807,
     /*  450027 */   GIR_EraseRootFromParent_Done,
     /*  450028 */ // Label 6806: @450028
     /*  450028 */ GIM_Try, /*On fail goto*//*Label 6807*/ GIMT_Encode4(450115), // Rule ID 14808 //
     /*  450033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode1),
     /*  450036 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450039 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450043 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  450050 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450055 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450059 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450063 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450067 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450071 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450075 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450079 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450088 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR),
     /*  450091 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450105 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450108 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450113 */   GIR_RootConstrainSelectedInstOperands,
     /*  450114 */   // GIR_Coverage, 14808,
     /*  450114 */   GIR_EraseRootFromParent_Done,
     /*  450115 */ // Label 6807: @450115
     /*  450115 */ GIM_Try, /*On fail goto*//*Label 6808*/ GIMT_Encode4(450202), // Rule ID 14809 //
     /*  450120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode2),
     /*  450123 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450126 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  450137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450142 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450146 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450150 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450154 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450158 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450166 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450168 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450175 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR),
     /*  450178 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450192 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450195 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450200 */   GIR_RootConstrainSelectedInstOperands,
     /*  450201 */   // GIR_Coverage, 14809,
     /*  450201 */   GIR_EraseRootFromParent_Done,
     /*  450202 */ // Label 6808: @450202
     /*  450202 */ GIM_Try, /*On fail goto*//*Label 6809*/ GIMT_Encode4(450289), // Rule ID 14810 //
     /*  450207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode3),
     /*  450210 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450213 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450217 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  450224 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450229 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450233 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450237 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450241 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450245 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450249 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450253 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450255 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450262 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR),
     /*  450265 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450279 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450282 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450287 */   GIR_RootConstrainSelectedInstOperands,
     /*  450288 */   // GIR_Coverage, 14810,
     /*  450288 */   GIR_EraseRootFromParent_Done,
     /*  450289 */ // Label 6809: @450289
     /*  450289 */ GIM_Try, /*On fail goto*//*Label 6810*/ GIMT_Encode4(450376), // Rule ID 14811 //
     /*  450294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode4),
     /*  450297 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450300 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450304 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  450311 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450316 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450320 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450324 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450328 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450332 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450336 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450340 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450342 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450349 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR),
     /*  450352 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450374 */   GIR_RootConstrainSelectedInstOperands,
     /*  450375 */   // GIR_Coverage, 14811,
     /*  450375 */   GIR_EraseRootFromParent_Done,
     /*  450376 */ // Label 6810: @450376
     /*  450376 */ GIM_Try, /*On fail goto*//*Label 6811*/ GIMT_Encode4(450463), // Rule ID 14822 //
     /*  450381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode0),
     /*  450384 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450387 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450391 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  450398 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450403 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450407 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450411 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450415 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450419 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450427 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450429 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450436 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR),
     /*  450439 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450453 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450456 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450461 */   GIR_RootConstrainSelectedInstOperands,
     /*  450462 */   // GIR_Coverage, 14822,
     /*  450462 */   GIR_EraseRootFromParent_Done,
     /*  450463 */ // Label 6811: @450463
     /*  450463 */ GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(450550), // Rule ID 14823 //
     /*  450468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode1),
     /*  450471 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450474 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  450485 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450490 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450494 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450498 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450502 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450506 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450514 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450516 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450523 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR),
     /*  450526 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450548 */   GIR_RootConstrainSelectedInstOperands,
     /*  450549 */   // GIR_Coverage, 14823,
     /*  450549 */   GIR_EraseRootFromParent_Done,
     /*  450550 */ // Label 6812: @450550
     /*  450550 */ GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(450637), // Rule ID 14824 //
     /*  450555 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode2),
     /*  450558 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450561 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450565 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  450572 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450577 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450581 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450585 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450589 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450593 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450597 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450601 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450603 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450610 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450610 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR),
     /*  450613 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450627 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450630 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450635 */   GIR_RootConstrainSelectedInstOperands,
     /*  450636 */   // GIR_Coverage, 14824,
     /*  450636 */   GIR_EraseRootFromParent_Done,
     /*  450637 */ // Label 6813: @450637
     /*  450637 */ GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(450724), // Rule ID 14825 //
     /*  450642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode3),
     /*  450645 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450648 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450652 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  450659 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450664 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450668 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450672 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450676 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450680 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450688 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450697 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR),
     /*  450700 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450714 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450717 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450722 */   GIR_RootConstrainSelectedInstOperands,
     /*  450723 */   // GIR_Coverage, 14825,
     /*  450723 */   GIR_EraseRootFromParent_Done,
     /*  450724 */ // Label 6814: @450724
     /*  450724 */ GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(450811), // Rule ID 14826 //
     /*  450729 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode4),
     /*  450732 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450735 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  450746 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450751 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450755 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450759 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450763 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450767 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450775 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450777 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  450784 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  450784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR),
     /*  450787 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  450796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450804 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450809 */   GIR_RootConstrainSelectedInstOperands,
     /*  450810 */   // GIR_Coverage, 14826,
     /*  450810 */   GIR_EraseRootFromParent_Done,
     /*  450811 */ // Label 6815: @450811
     /*  450811 */ GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(450898), // Rule ID 14802 //
     /*  450816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode0),
     /*  450819 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450822 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450826 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  450833 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450838 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450842 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450846 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450850 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450854 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450862 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450864 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  450871 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  450871 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI),
     /*  450874 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  450883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450888 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450891 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450896 */   GIR_RootConstrainSelectedInstOperands,
     /*  450897 */   // GIR_Coverage, 14802,
     /*  450897 */   GIR_EraseRootFromParent_Done,
     /*  450898 */ // Label 6816: @450898
     /*  450898 */ GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(450985), // Rule ID 14803 //
     /*  450903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode1),
     /*  450906 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450909 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  450913 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  450920 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  450925 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  450929 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  450933 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  450937 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  450941 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  450945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  450949 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  450951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  450958 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  450958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI),
     /*  450961 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  450965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  450970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  450975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  450978 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  450983 */   GIR_RootConstrainSelectedInstOperands,
     /*  450984 */   // GIR_Coverage, 14803,
     /*  450984 */   GIR_EraseRootFromParent_Done,
     /*  450985 */ // Label 6817: @450985
     /*  450985 */ GIM_Try, /*On fail goto*//*Label 6818*/ GIMT_Encode4(451072), // Rule ID 14804 //
     /*  450990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode2),
     /*  450993 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  450996 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451000 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  451007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451012 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451016 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451020 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451024 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451028 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451032 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451036 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451045 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI),
     /*  451048 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451062 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451065 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451070 */   GIR_RootConstrainSelectedInstOperands,
     /*  451071 */   // GIR_Coverage, 14804,
     /*  451071 */   GIR_EraseRootFromParent_Done,
     /*  451072 */ // Label 6818: @451072
     /*  451072 */ GIM_Try, /*On fail goto*//*Label 6819*/ GIMT_Encode4(451159), // Rule ID 14805 //
     /*  451077 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode3),
     /*  451080 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451083 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451087 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  451094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451099 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451103 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451107 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451111 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451115 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451123 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451132 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI),
     /*  451135 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451139 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451149 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451152 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451157 */   GIR_RootConstrainSelectedInstOperands,
     /*  451158 */   // GIR_Coverage, 14805,
     /*  451158 */   GIR_EraseRootFromParent_Done,
     /*  451159 */ // Label 6819: @451159
     /*  451159 */ GIM_Try, /*On fail goto*//*Label 6820*/ GIMT_Encode4(451246), // Rule ID 14806 //
     /*  451164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode4),
     /*  451167 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451170 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451174 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  451181 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451186 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451190 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451194 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451198 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451202 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451206 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451210 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451212 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451219 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI),
     /*  451222 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451236 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451239 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451244 */   GIR_RootConstrainSelectedInstOperands,
     /*  451245 */   // GIR_Coverage, 14806,
     /*  451245 */   GIR_EraseRootFromParent_Done,
     /*  451246 */ // Label 6820: @451246
     /*  451246 */ GIM_Try, /*On fail goto*//*Label 6821*/ GIMT_Encode4(451333), // Rule ID 14817 //
     /*  451251 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode0),
     /*  451254 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451257 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451261 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  451268 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451273 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451277 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451281 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451285 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451289 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451293 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451297 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451299 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451306 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451306 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI),
     /*  451309 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451326 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451331 */   GIR_RootConstrainSelectedInstOperands,
     /*  451332 */   // GIR_Coverage, 14817,
     /*  451332 */   GIR_EraseRootFromParent_Done,
     /*  451333 */ // Label 6821: @451333
     /*  451333 */ GIM_Try, /*On fail goto*//*Label 6822*/ GIMT_Encode4(451420), // Rule ID 14818 //
     /*  451338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode1),
     /*  451341 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451344 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451348 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  451355 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451360 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451364 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451368 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451372 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451376 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451380 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451384 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451393 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI),
     /*  451396 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451410 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451413 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451418 */   GIR_RootConstrainSelectedInstOperands,
     /*  451419 */   // GIR_Coverage, 14818,
     /*  451419 */   GIR_EraseRootFromParent_Done,
     /*  451420 */ // Label 6822: @451420
     /*  451420 */ GIM_Try, /*On fail goto*//*Label 6823*/ GIMT_Encode4(451507), // Rule ID 14819 //
     /*  451425 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode2),
     /*  451428 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451431 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451435 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  451442 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451447 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451451 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451455 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451459 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451463 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451467 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451471 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451473 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451480 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI),
     /*  451483 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451492 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451497 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451500 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451505 */   GIR_RootConstrainSelectedInstOperands,
     /*  451506 */   // GIR_Coverage, 14819,
     /*  451506 */   GIR_EraseRootFromParent_Done,
     /*  451507 */ // Label 6823: @451507
     /*  451507 */ GIM_Try, /*On fail goto*//*Label 6824*/ GIMT_Encode4(451594), // Rule ID 14820 //
     /*  451512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode3),
     /*  451515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451518 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451522 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  451529 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451534 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451538 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451542 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451546 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451550 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451554 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451558 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451560 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451567 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI),
     /*  451570 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451584 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451587 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451592 */   GIR_RootConstrainSelectedInstOperands,
     /*  451593 */   // GIR_Coverage, 14820,
     /*  451593 */   GIR_EraseRootFromParent_Done,
     /*  451594 */ // Label 6824: @451594
     /*  451594 */ GIM_Try, /*On fail goto*//*Label 6825*/ GIMT_Encode4(451681), // Rule ID 14821 //
     /*  451599 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HwMode4),
     /*  451602 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451605 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451609 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  451616 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451621 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451625 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451629 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451633 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451637 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451641 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451645 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451647 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  451654 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  451654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI),
     /*  451657 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  451661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  451666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  451671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451679 */   GIR_RootConstrainSelectedInstOperands,
     /*  451680 */   // GIR_Coverage, 14821,
     /*  451680 */   GIR_EraseRootFromParent_Done,
     /*  451681 */ // Label 6825: @451681
     /*  451681 */ GIM_Try, /*On fail goto*//*Label 6826*/ GIMT_Encode4(451781), // Rule ID 26001 //
     /*  451686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode0),
     /*  451689 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451692 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451696 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  451703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451708 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451712 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451716 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451720 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451724 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451732 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451734 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  451741 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  451741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN),
     /*  451744 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  451748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  451753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  451758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  451763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  451768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451771 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451774 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451779 */   GIR_RootConstrainSelectedInstOperands,
     /*  451780 */   // GIR_Coverage, 26001,
     /*  451780 */   GIR_EraseRootFromParent_Done,
     /*  451781 */ // Label 6826: @451781
     /*  451781 */ GIM_Try, /*On fail goto*//*Label 6827*/ GIMT_Encode4(451881), // Rule ID 26002 //
     /*  451786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode1),
     /*  451789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451792 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451796 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  451803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451808 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451812 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451816 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451820 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451824 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451832 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451834 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  451841 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  451841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN),
     /*  451844 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  451848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  451853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  451858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  451863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  451868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451879 */   GIR_RootConstrainSelectedInstOperands,
     /*  451880 */   // GIR_Coverage, 26002,
     /*  451880 */   GIR_EraseRootFromParent_Done,
     /*  451881 */ // Label 6827: @451881
     /*  451881 */ GIM_Try, /*On fail goto*//*Label 6828*/ GIMT_Encode4(451981), // Rule ID 26003 //
     /*  451886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode2),
     /*  451889 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451892 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451896 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  451903 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  451908 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  451912 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  451916 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  451920 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  451924 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  451928 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  451932 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  451934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  451941 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  451941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN),
     /*  451944 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  451948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  451953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  451958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  451963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  451968 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451971 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  451974 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  451979 */   GIR_RootConstrainSelectedInstOperands,
     /*  451980 */   // GIR_Coverage, 26003,
     /*  451980 */   GIR_EraseRootFromParent_Done,
     /*  451981 */ // Label 6828: @451981
     /*  451981 */ GIM_Try, /*On fail goto*//*Label 6829*/ GIMT_Encode4(452081), // Rule ID 26004 //
     /*  451986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode3),
     /*  451989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  451992 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  451996 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452008 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452012 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452016 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452020 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452024 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452032 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452034 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452041 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN),
     /*  452044 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452068 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452074 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452079 */   GIR_RootConstrainSelectedInstOperands,
     /*  452080 */   // GIR_Coverage, 26004,
     /*  452080 */   GIR_EraseRootFromParent_Done,
     /*  452081 */ // Label 6829: @452081
     /*  452081 */ GIM_Try, /*On fail goto*//*Label 6830*/ GIMT_Encode4(452181), // Rule ID 26005 //
     /*  452086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode4),
     /*  452089 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452092 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452096 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452103 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452108 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452112 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452116 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452120 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452124 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452132 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452134 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452141 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452141 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN),
     /*  452144 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452168 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452179 */   GIR_RootConstrainSelectedInstOperands,
     /*  452180 */   // GIR_Coverage, 26005,
     /*  452180 */   GIR_EraseRootFromParent_Done,
     /*  452181 */ // Label 6830: @452181
     /*  452181 */ GIM_Try, /*On fail goto*//*Label 6831*/ GIMT_Encode4(452281), // Rule ID 26011 //
     /*  452186 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode0),
     /*  452189 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452192 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452196 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452203 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452208 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452212 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452216 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452220 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452224 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452228 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452232 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452241 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN),
     /*  452244 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452268 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452271 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452279 */   GIR_RootConstrainSelectedInstOperands,
     /*  452280 */   // GIR_Coverage, 26011,
     /*  452280 */   GIR_EraseRootFromParent_Done,
     /*  452281 */ // Label 6831: @452281
     /*  452281 */ GIM_Try, /*On fail goto*//*Label 6832*/ GIMT_Encode4(452381), // Rule ID 26012 //
     /*  452286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode1),
     /*  452289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452292 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452308 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452312 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452316 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452320 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452324 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452328 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452332 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452341 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN),
     /*  452344 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452368 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452371 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452374 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452379 */   GIR_RootConstrainSelectedInstOperands,
     /*  452380 */   // GIR_Coverage, 26012,
     /*  452380 */   GIR_EraseRootFromParent_Done,
     /*  452381 */ // Label 6832: @452381
     /*  452381 */ GIM_Try, /*On fail goto*//*Label 6833*/ GIMT_Encode4(452481), // Rule ID 26013 //
     /*  452386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode2),
     /*  452389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452392 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452408 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452412 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452416 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452420 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452424 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452428 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452432 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452434 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452441 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452441 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN),
     /*  452444 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452479 */   GIR_RootConstrainSelectedInstOperands,
     /*  452480 */   // GIR_Coverage, 26013,
     /*  452480 */   GIR_EraseRootFromParent_Done,
     /*  452481 */ // Label 6833: @452481
     /*  452481 */ GIM_Try, /*On fail goto*//*Label 6834*/ GIMT_Encode4(452581), // Rule ID 26014 //
     /*  452486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode3),
     /*  452489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452492 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452508 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452512 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452516 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452520 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452524 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452532 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452541 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN),
     /*  452544 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452579 */   GIR_RootConstrainSelectedInstOperands,
     /*  452580 */   // GIR_Coverage, 26014,
     /*  452580 */   GIR_EraseRootFromParent_Done,
     /*  452581 */ // Label 6834: @452581
     /*  452581 */ GIM_Try, /*On fail goto*//*Label 6835*/ GIMT_Encode4(452681), // Rule ID 26015 //
     /*  452586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode4),
     /*  452589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452592 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  452603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452608 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452612 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452616 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452620 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452624 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452632 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452641 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN),
     /*  452644 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452679 */   GIR_RootConstrainSelectedInstOperands,
     /*  452680 */   // GIR_Coverage, 26015,
     /*  452680 */   GIR_EraseRootFromParent_Done,
     /*  452681 */ // Label 6835: @452681
     /*  452681 */ GIM_Try, /*On fail goto*//*Label 6836*/ GIMT_Encode4(452781), // Rule ID 26021 //
     /*  452686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode0),
     /*  452689 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452692 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452696 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  452703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452708 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452712 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452716 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452720 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452724 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452732 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452734 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452741 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN),
     /*  452744 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452748 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452771 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452774 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452779 */   GIR_RootConstrainSelectedInstOperands,
     /*  452780 */   // GIR_Coverage, 26021,
     /*  452780 */   GIR_EraseRootFromParent_Done,
     /*  452781 */ // Label 6836: @452781
     /*  452781 */ GIM_Try, /*On fail goto*//*Label 6837*/ GIMT_Encode4(452881), // Rule ID 26022 //
     /*  452786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode1),
     /*  452789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452792 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452796 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  452803 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452808 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452812 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452816 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452820 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452824 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452832 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452834 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452841 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN),
     /*  452844 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452879 */   GIR_RootConstrainSelectedInstOperands,
     /*  452880 */   // GIR_Coverage, 26022,
     /*  452880 */   GIR_EraseRootFromParent_Done,
     /*  452881 */ // Label 6837: @452881
     /*  452881 */ GIM_Try, /*On fail goto*//*Label 6838*/ GIMT_Encode4(452981), // Rule ID 26023 //
     /*  452886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode2),
     /*  452889 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452892 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452896 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  452903 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  452908 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  452912 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  452916 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  452920 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  452924 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  452928 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  452932 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  452934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  452941 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  452941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN),
     /*  452944 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  452948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  452953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  452958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  452963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  452968 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452971 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  452974 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  452979 */   GIR_RootConstrainSelectedInstOperands,
     /*  452980 */   // GIR_Coverage, 26023,
     /*  452980 */   GIR_EraseRootFromParent_Done,
     /*  452981 */ // Label 6838: @452981
     /*  452981 */ GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(453081), // Rule ID 26024 //
     /*  452986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode3),
     /*  452989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  452992 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  452996 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453008 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453012 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453016 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453020 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453024 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453032 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453034 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453041 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN),
     /*  453044 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453058 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453068 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453074 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453079 */   GIR_RootConstrainSelectedInstOperands,
     /*  453080 */   // GIR_Coverage, 26024,
     /*  453080 */   GIR_EraseRootFromParent_Done,
     /*  453081 */ // Label 6839: @453081
     /*  453081 */ GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(453181), // Rule ID 26025 //
     /*  453086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset_HwMode4),
     /*  453089 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453092 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453096 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453103 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453108 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453112 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453116 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453120 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453124 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453132 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453134 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453141 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453141 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN),
     /*  453144 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453168 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453179 */   GIR_RootConstrainSelectedInstOperands,
     /*  453180 */   // GIR_Coverage, 26025,
     /*  453180 */   GIR_EraseRootFromParent_Done,
     /*  453181 */ // Label 6840: @453181
     /*  453181 */ GIM_Try, /*On fail goto*//*Label 6841*/ GIMT_Encode4(453281), // Rule ID 26031 //
     /*  453186 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode0),
     /*  453189 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453192 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453196 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453203 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453208 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453212 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453216 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453220 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453224 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453228 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453232 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453241 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN),
     /*  453244 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453268 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453271 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453274 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453279 */   GIR_RootConstrainSelectedInstOperands,
     /*  453280 */   // GIR_Coverage, 26031,
     /*  453280 */   GIR_EraseRootFromParent_Done,
     /*  453281 */ // Label 6841: @453281
     /*  453281 */ GIM_Try, /*On fail goto*//*Label 6842*/ GIMT_Encode4(453381), // Rule ID 26032 //
     /*  453286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode1),
     /*  453289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453292 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453296 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453308 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453312 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453316 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453320 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453324 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453328 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453332 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453341 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN),
     /*  453344 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453368 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453371 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453374 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453379 */   GIR_RootConstrainSelectedInstOperands,
     /*  453380 */   // GIR_Coverage, 26032,
     /*  453380 */   GIR_EraseRootFromParent_Done,
     /*  453381 */ // Label 6842: @453381
     /*  453381 */ GIM_Try, /*On fail goto*//*Label 6843*/ GIMT_Encode4(453481), // Rule ID 26033 //
     /*  453386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode2),
     /*  453389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453392 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453408 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453412 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453416 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453420 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453424 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453428 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453432 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453434 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453441 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453441 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN),
     /*  453444 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453479 */   GIR_RootConstrainSelectedInstOperands,
     /*  453480 */   // GIR_Coverage, 26033,
     /*  453480 */   GIR_EraseRootFromParent_Done,
     /*  453481 */ // Label 6843: @453481
     /*  453481 */ GIM_Try, /*On fail goto*//*Label 6844*/ GIMT_Encode4(453581), // Rule ID 26034 //
     /*  453486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode3),
     /*  453489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453492 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453508 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453512 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453516 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453520 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453524 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453528 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453532 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453541 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN),
     /*  453544 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453579 */   GIR_RootConstrainSelectedInstOperands,
     /*  453580 */   // GIR_Coverage, 26034,
     /*  453580 */   GIR_EraseRootFromParent_Done,
     /*  453581 */ // Label 6844: @453581
     /*  453581 */ GIM_Try, /*On fail goto*//*Label 6845*/ GIMT_Encode4(453681), // Rule ID 26035 //
     /*  453586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HwMode4),
     /*  453589 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453592 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453596 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453603 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453608 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  453612 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  453616 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  453620 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  453624 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  453628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453632 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  453634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  453641 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN),
     /*  453644 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  453648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  453653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  453663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  453668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  453679 */   GIR_RootConstrainSelectedInstOperands,
     /*  453680 */   // GIR_Coverage, 26035,
     /*  453680 */   GIR_EraseRootFromParent_Done,
     /*  453681 */ // Label 6845: @453681
     /*  453681 */ GIM_Try, /*On fail goto*//*Label 6846*/ GIMT_Encode4(453751), // Rule ID 25706 //
     /*  453686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  453689 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453692 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453696 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  453719 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  453722 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  453724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  453734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  453739 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453742 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453745 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  453749 */   GIR_RootConstrainSelectedInstOperands,
     /*  453750 */   // GIR_Coverage, 25706,
     /*  453750 */   GIR_EraseRootFromParent_Done,
     /*  453751 */ // Label 6846: @453751
     /*  453751 */ GIM_Try, /*On fail goto*//*Label 6847*/ GIMT_Encode4(453821), // Rule ID 25707 //
     /*  453756 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  453759 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453762 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453766 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453773 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453778 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453782 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  453789 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453789 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  453792 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  453794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  453804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  453809 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453812 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453815 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  453819 */   GIR_RootConstrainSelectedInstOperands,
     /*  453820 */   // GIR_Coverage, 25707,
     /*  453820 */   GIR_EraseRootFromParent_Done,
     /*  453821 */ // Label 6847: @453821
     /*  453821 */ GIM_Try, /*On fail goto*//*Label 6848*/ GIMT_Encode4(453891), // Rule ID 25708 //
     /*  453826 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  453829 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453832 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453836 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453843 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453852 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  453859 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  453862 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  453864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  453874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  453879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  453889 */   GIR_RootConstrainSelectedInstOperands,
     /*  453890 */   // GIR_Coverage, 25708,
     /*  453890 */   GIR_EraseRootFromParent_Done,
     /*  453891 */ // Label 6848: @453891
     /*  453891 */ GIM_Try, /*On fail goto*//*Label 6849*/ GIMT_Encode4(453961), // Rule ID 25709 //
     /*  453896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  453899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453902 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453906 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453913 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453918 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453922 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  453929 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  453932 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  453934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  453939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  453944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  453949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453952 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  453955 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  453959 */   GIR_RootConstrainSelectedInstOperands,
     /*  453960 */   // GIR_Coverage, 25709,
     /*  453960 */   GIR_EraseRootFromParent_Done,
     /*  453961 */ // Label 6849: @453961
     /*  453961 */ GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(454031), // Rule ID 25710 //
     /*  453966 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  453969 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  453972 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  453976 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  453983 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  453988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  453992 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  453999 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  453999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  454002 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454022 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454029 */   GIR_RootConstrainSelectedInstOperands,
     /*  454030 */   // GIR_Coverage, 25710,
     /*  454030 */   GIR_EraseRootFromParent_Done,
     /*  454031 */ // Label 6850: @454031
     /*  454031 */ GIM_Try, /*On fail goto*//*Label 6851*/ GIMT_Encode4(454101), // Rule ID 25716 //
     /*  454036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  454039 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454042 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454046 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  454053 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454062 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454069 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454069 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  454072 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454095 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454099 */   GIR_RootConstrainSelectedInstOperands,
     /*  454100 */   // GIR_Coverage, 25716,
     /*  454100 */   GIR_EraseRootFromParent_Done,
     /*  454101 */ // Label 6851: @454101
     /*  454101 */ GIM_Try, /*On fail goto*//*Label 6852*/ GIMT_Encode4(454171), // Rule ID 25717 //
     /*  454106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  454109 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454112 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454116 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  454123 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454128 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454139 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  454142 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454159 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454169 */   GIR_RootConstrainSelectedInstOperands,
     /*  454170 */   // GIR_Coverage, 25717,
     /*  454170 */   GIR_EraseRootFromParent_Done,
     /*  454171 */ // Label 6852: @454171
     /*  454171 */ GIM_Try, /*On fail goto*//*Label 6853*/ GIMT_Encode4(454241), // Rule ID 25718 //
     /*  454176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  454179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454182 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454186 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  454193 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454209 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  454212 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454229 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454239 */   GIR_RootConstrainSelectedInstOperands,
     /*  454240 */   // GIR_Coverage, 25718,
     /*  454240 */   GIR_EraseRootFromParent_Done,
     /*  454241 */ // Label 6853: @454241
     /*  454241 */ GIM_Try, /*On fail goto*//*Label 6854*/ GIMT_Encode4(454311), // Rule ID 25719 //
     /*  454246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  454249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454252 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  454263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454279 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  454282 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454302 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454309 */   GIR_RootConstrainSelectedInstOperands,
     /*  454310 */   // GIR_Coverage, 25719,
     /*  454310 */   GIR_EraseRootFromParent_Done,
     /*  454311 */ // Label 6854: @454311
     /*  454311 */ GIM_Try, /*On fail goto*//*Label 6855*/ GIMT_Encode4(454381), // Rule ID 25720 //
     /*  454316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  454319 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454322 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454326 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  454333 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454338 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454342 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454349 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  454352 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454372 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454375 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454379 */   GIR_RootConstrainSelectedInstOperands,
     /*  454380 */   // GIR_Coverage, 25720,
     /*  454380 */   GIR_EraseRootFromParent_Done,
     /*  454381 */ // Label 6855: @454381
     /*  454381 */ GIM_Try, /*On fail goto*//*Label 6856*/ GIMT_Encode4(454451), // Rule ID 25726 //
     /*  454386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  454389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454392 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454408 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454419 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  454422 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454439 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454442 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454445 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454449 */   GIR_RootConstrainSelectedInstOperands,
     /*  454450 */   // GIR_Coverage, 25726,
     /*  454450 */   GIR_EraseRootFromParent_Done,
     /*  454451 */ // Label 6856: @454451
     /*  454451 */ GIM_Try, /*On fail goto*//*Label 6857*/ GIMT_Encode4(454521), // Rule ID 25727 //
     /*  454456 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  454459 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454462 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454466 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454473 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454489 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  454492 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454509 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454512 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454515 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454519 */   GIR_RootConstrainSelectedInstOperands,
     /*  454520 */   // GIR_Coverage, 25727,
     /*  454520 */   GIR_EraseRootFromParent_Done,
     /*  454521 */ // Label 6857: @454521
     /*  454521 */ GIM_Try, /*On fail goto*//*Label 6858*/ GIMT_Encode4(454591), // Rule ID 25728 //
     /*  454526 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  454529 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454532 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454536 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454543 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454548 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454552 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454559 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454559 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  454562 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454579 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454582 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454585 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454589 */   GIR_RootConstrainSelectedInstOperands,
     /*  454590 */   // GIR_Coverage, 25728,
     /*  454590 */   GIR_EraseRootFromParent_Done,
     /*  454591 */ // Label 6858: @454591
     /*  454591 */ GIM_Try, /*On fail goto*//*Label 6859*/ GIMT_Encode4(454661), // Rule ID 25729 //
     /*  454596 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  454599 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454602 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454606 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454613 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454618 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454622 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454629 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454629 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  454632 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454652 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454655 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454659 */   GIR_RootConstrainSelectedInstOperands,
     /*  454660 */   // GIR_Coverage, 25729,
     /*  454660 */   GIR_EraseRootFromParent_Done,
     /*  454661 */ // Label 6859: @454661
     /*  454661 */ GIM_Try, /*On fail goto*//*Label 6860*/ GIMT_Encode4(454731), // Rule ID 25730 //
     /*  454666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  454669 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454672 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454676 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454683 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454688 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454692 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454699 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  454702 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454722 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454729 */   GIR_RootConstrainSelectedInstOperands,
     /*  454730 */   // GIR_Coverage, 25730,
     /*  454730 */   GIR_EraseRootFromParent_Done,
     /*  454731 */ // Label 6860: @454731
     /*  454731 */ GIM_Try, /*On fail goto*//*Label 6861*/ GIMT_Encode4(454801), // Rule ID 25736 //
     /*  454736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  454739 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454742 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454746 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454753 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454758 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454762 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454769 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  454772 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454789 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454792 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454795 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454799 */   GIR_RootConstrainSelectedInstOperands,
     /*  454800 */   // GIR_Coverage, 25736,
     /*  454800 */   GIR_EraseRootFromParent_Done,
     /*  454801 */ // Label 6861: @454801
     /*  454801 */ GIM_Try, /*On fail goto*//*Label 6862*/ GIMT_Encode4(454871), // Rule ID 25737 //
     /*  454806 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  454809 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454812 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454816 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454823 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454828 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454832 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454839 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454839 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  454842 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454859 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454862 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454865 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454869 */   GIR_RootConstrainSelectedInstOperands,
     /*  454870 */   // GIR_Coverage, 25737,
     /*  454870 */   GIR_EraseRootFromParent_Done,
     /*  454871 */ // Label 6862: @454871
     /*  454871 */ GIM_Try, /*On fail goto*//*Label 6863*/ GIMT_Encode4(454941), // Rule ID 25738 //
     /*  454876 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  454879 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454882 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454886 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454893 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454898 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454902 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454909 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454909 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  454912 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454929 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  454935 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  454939 */   GIR_RootConstrainSelectedInstOperands,
     /*  454940 */   // GIR_Coverage, 25738,
     /*  454940 */   GIR_EraseRootFromParent_Done,
     /*  454941 */ // Label 6863: @454941
     /*  454941 */ GIM_Try, /*On fail goto*//*Label 6864*/ GIMT_Encode4(455011), // Rule ID 25739 //
     /*  454946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  454949 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  454952 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  454956 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  454963 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  454968 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  454972 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  454979 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  454979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  454982 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  454984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  454989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  454994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  454999 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455002 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455005 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455009 */   GIR_RootConstrainSelectedInstOperands,
     /*  455010 */   // GIR_Coverage, 25739,
     /*  455010 */   GIR_EraseRootFromParent_Done,
     /*  455011 */ // Label 6864: @455011
     /*  455011 */ GIM_Try, /*On fail goto*//*Label 6865*/ GIMT_Encode4(455081), // Rule ID 25740 //
     /*  455016 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  455019 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455022 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  455026 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  455033 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455038 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455042 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455049 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  455052 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455069 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455072 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455075 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455079 */   GIR_RootConstrainSelectedInstOperands,
     /*  455080 */   // GIR_Coverage, 25740,
     /*  455080 */   GIR_EraseRootFromParent_Done,
     /*  455081 */ // Label 6865: @455081
     /*  455081 */ GIM_Try, /*On fail goto*//*Label 6866*/ GIMT_Encode4(455140), // Rule ID 25786 //
     /*  455086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  455089 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455092 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455108 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455108 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455111 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455128 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455134 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455138 */   GIR_RootConstrainSelectedInstOperands,
     /*  455139 */   // GIR_Coverage, 25786,
     /*  455139 */   GIR_EraseRootFromParent_Done,
     /*  455140 */ // Label 6866: @455140
     /*  455140 */ GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(455199), // Rule ID 25787 //
     /*  455145 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  455148 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455151 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455167 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455170 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455190 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455193 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455197 */   GIR_RootConstrainSelectedInstOperands,
     /*  455198 */   // GIR_Coverage, 25787,
     /*  455198 */   GIR_EraseRootFromParent_Done,
     /*  455199 */ // Label 6867: @455199
     /*  455199 */ GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(455258), // Rule ID 25788 //
     /*  455204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  455207 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455210 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455215 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455219 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455226 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455226 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455229 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455252 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455256 */   GIR_RootConstrainSelectedInstOperands,
     /*  455257 */   // GIR_Coverage, 25788,
     /*  455257 */   GIR_EraseRootFromParent_Done,
     /*  455258 */ // Label 6868: @455258
     /*  455258 */ GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(455317), // Rule ID 25789 //
     /*  455263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  455266 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455274 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455278 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455285 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455288 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455305 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455308 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455311 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455315 */   GIR_RootConstrainSelectedInstOperands,
     /*  455316 */   // GIR_Coverage, 25789,
     /*  455316 */   GIR_EraseRootFromParent_Done,
     /*  455317 */ // Label 6869: @455317
     /*  455317 */ GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(455376), // Rule ID 25790 //
     /*  455322 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  455325 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455328 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455333 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455337 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455344 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455344 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455347 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455364 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455367 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455370 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455374 */   GIR_RootConstrainSelectedInstOperands,
     /*  455375 */   // GIR_Coverage, 25790,
     /*  455375 */   GIR_EraseRootFromParent_Done,
     /*  455376 */ // Label 6870: @455376
     /*  455376 */ GIM_Try, /*On fail goto*//*Label 6871*/ GIMT_Encode4(455435), // Rule ID 25796 //
     /*  455381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  455384 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455387 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455403 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  455406 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455423 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455426 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455429 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455433 */   GIR_RootConstrainSelectedInstOperands,
     /*  455434 */   // GIR_Coverage, 25796,
     /*  455434 */   GIR_EraseRootFromParent_Done,
     /*  455435 */ // Label 6871: @455435
     /*  455435 */ GIM_Try, /*On fail goto*//*Label 6872*/ GIMT_Encode4(455494), // Rule ID 25797 //
     /*  455440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  455443 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455446 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455451 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455455 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455462 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  455465 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455482 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455485 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455488 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455492 */   GIR_RootConstrainSelectedInstOperands,
     /*  455493 */   // GIR_Coverage, 25797,
     /*  455493 */   GIR_EraseRootFromParent_Done,
     /*  455494 */ // Label 6872: @455494
     /*  455494 */ GIM_Try, /*On fail goto*//*Label 6873*/ GIMT_Encode4(455553), // Rule ID 25798 //
     /*  455499 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  455502 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455505 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455514 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455521 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  455524 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455541 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455544 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455547 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455551 */   GIR_RootConstrainSelectedInstOperands,
     /*  455552 */   // GIR_Coverage, 25798,
     /*  455552 */   GIR_EraseRootFromParent_Done,
     /*  455553 */ // Label 6873: @455553
     /*  455553 */ GIM_Try, /*On fail goto*//*Label 6874*/ GIMT_Encode4(455612), // Rule ID 25799 //
     /*  455558 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  455561 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455564 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455569 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455580 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  455583 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455600 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455603 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455606 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455610 */   GIR_RootConstrainSelectedInstOperands,
     /*  455611 */   // GIR_Coverage, 25799,
     /*  455611 */   GIR_EraseRootFromParent_Done,
     /*  455612 */ // Label 6874: @455612
     /*  455612 */ GIM_Try, /*On fail goto*//*Label 6875*/ GIMT_Encode4(455671), // Rule ID 25800 //
     /*  455617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  455620 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455623 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455632 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455639 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  455642 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455662 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455665 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455669 */   GIR_RootConstrainSelectedInstOperands,
     /*  455670 */   // GIR_Coverage, 25800,
     /*  455670 */   GIR_EraseRootFromParent_Done,
     /*  455671 */ // Label 6875: @455671
     /*  455671 */ GIM_Try, /*On fail goto*//*Label 6876*/ GIMT_Encode4(455730), // Rule ID 25806 //
     /*  455676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  455679 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455687 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455691 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455698 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455701 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455708 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455718 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455724 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455728 */   GIR_RootConstrainSelectedInstOperands,
     /*  455729 */   // GIR_Coverage, 25806,
     /*  455729 */   GIR_EraseRootFromParent_Done,
     /*  455730 */ // Label 6876: @455730
     /*  455730 */ GIM_Try, /*On fail goto*//*Label 6877*/ GIMT_Encode4(455789), // Rule ID 25807 //
     /*  455735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  455738 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455741 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455746 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455750 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455757 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455757 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455760 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455762 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455767 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455777 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455783 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455787 */   GIR_RootConstrainSelectedInstOperands,
     /*  455788 */   // GIR_Coverage, 25807,
     /*  455788 */   GIR_EraseRootFromParent_Done,
     /*  455789 */ // Label 6877: @455789
     /*  455789 */ GIM_Try, /*On fail goto*//*Label 6878*/ GIMT_Encode4(455848), // Rule ID 25808 //
     /*  455794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  455797 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455800 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455805 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455809 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455816 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455819 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455839 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455842 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455846 */   GIR_RootConstrainSelectedInstOperands,
     /*  455847 */   // GIR_Coverage, 25808,
     /*  455847 */   GIR_EraseRootFromParent_Done,
     /*  455848 */ // Label 6878: @455848
     /*  455848 */ GIM_Try, /*On fail goto*//*Label 6879*/ GIMT_Encode4(455907), // Rule ID 25809 //
     /*  455853 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  455856 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455859 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455864 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455868 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455875 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455875 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455878 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455895 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455898 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455901 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455905 */   GIR_RootConstrainSelectedInstOperands,
     /*  455906 */   // GIR_Coverage, 25809,
     /*  455906 */   GIR_EraseRootFromParent_Done,
     /*  455907 */ // Label 6879: @455907
     /*  455907 */ GIM_Try, /*On fail goto*//*Label 6880*/ GIMT_Encode4(455966), // Rule ID 25810 //
     /*  455912 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  455915 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455918 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455923 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455934 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  455937 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  455944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  455949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  455954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455957 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  455960 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  455964 */   GIR_RootConstrainSelectedInstOperands,
     /*  455965 */   // GIR_Coverage, 25810,
     /*  455965 */   GIR_EraseRootFromParent_Done,
     /*  455966 */ // Label 6880: @455966
     /*  455966 */ GIM_Try, /*On fail goto*//*Label 6881*/ GIMT_Encode4(456025), // Rule ID 25816 //
     /*  455971 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  455974 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  455977 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  455982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  455986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  455993 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  455993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  455996 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  455998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  456003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  456008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456013 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456023 */   GIR_RootConstrainSelectedInstOperands,
     /*  456024 */   // GIR_Coverage, 25816,
     /*  456024 */   GIR_EraseRootFromParent_Done,
     /*  456025 */ // Label 6881: @456025
     /*  456025 */ GIM_Try, /*On fail goto*//*Label 6882*/ GIMT_Encode4(456084), // Rule ID 25817 //
     /*  456030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  456033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456036 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456041 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456045 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  456052 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  456052 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  456055 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  456057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  456062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  456067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456072 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456075 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456078 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456082 */   GIR_RootConstrainSelectedInstOperands,
     /*  456083 */   // GIR_Coverage, 25817,
     /*  456083 */   GIR_EraseRootFromParent_Done,
     /*  456084 */ // Label 6882: @456084
     /*  456084 */ GIM_Try, /*On fail goto*//*Label 6883*/ GIMT_Encode4(456143), // Rule ID 25818 //
     /*  456089 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  456092 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456095 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456100 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456104 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  456111 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  456111 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  456114 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  456116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  456121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  456126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456137 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456141 */   GIR_RootConstrainSelectedInstOperands,
     /*  456142 */   // GIR_Coverage, 25818,
     /*  456142 */   GIR_EraseRootFromParent_Done,
     /*  456143 */ // Label 6883: @456143
     /*  456143 */ GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(456202), // Rule ID 25819 //
     /*  456148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  456151 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456154 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  456170 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  456170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  456173 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  456175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  456180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  456185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456190 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456196 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456200 */   GIR_RootConstrainSelectedInstOperands,
     /*  456201 */   // GIR_Coverage, 25819,
     /*  456201 */   GIR_EraseRootFromParent_Done,
     /*  456202 */ // Label 6884: @456202
     /*  456202 */ GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(456261), // Rule ID 25820 //
     /*  456207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  456210 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  456229 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  456229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  456232 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  456234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  456239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  456244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456252 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  456255 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456259 */   GIR_RootConstrainSelectedInstOperands,
     /*  456260 */   // GIR_Coverage, 25820,
     /*  456260 */   GIR_EraseRootFromParent_Done,
     /*  456261 */ // Label 6885: @456261
     /*  456261 */ GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(456330), // Rule ID 14767 //
     /*  456266 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  456269 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456272 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456276 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  456283 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456288 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456292 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456299 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456299 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  456302 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456309 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456324 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456328 */   GIR_RootConstrainSelectedInstOperands,
     /*  456329 */   // GIR_Coverage, 14767,
     /*  456329 */   GIR_EraseRootFromParent_Done,
     /*  456330 */ // Label 6886: @456330
     /*  456330 */ GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(456399), // Rule ID 14768 //
     /*  456335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  456338 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456341 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456345 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  456352 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456357 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456361 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456368 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456368 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  456371 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456397 */   GIR_RootConstrainSelectedInstOperands,
     /*  456398 */   // GIR_Coverage, 14768,
     /*  456398 */   GIR_EraseRootFromParent_Done,
     /*  456399 */ // Label 6887: @456399
     /*  456399 */ GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(456468), // Rule ID 14769 //
     /*  456404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  456407 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456410 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456414 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  456421 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456426 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456430 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456437 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  456440 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456442 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456466 */   GIR_RootConstrainSelectedInstOperands,
     /*  456467 */   // GIR_Coverage, 14769,
     /*  456467 */   GIR_EraseRootFromParent_Done,
     /*  456468 */ // Label 6888: @456468
     /*  456468 */ GIM_Try, /*On fail goto*//*Label 6889*/ GIMT_Encode4(456537), // Rule ID 14770 //
     /*  456473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  456476 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456479 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456483 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  456490 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456495 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456499 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456506 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456506 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  456509 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456531 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456535 */   GIR_RootConstrainSelectedInstOperands,
     /*  456536 */   // GIR_Coverage, 14770,
     /*  456536 */   GIR_EraseRootFromParent_Done,
     /*  456537 */ // Label 6889: @456537
     /*  456537 */ GIM_Try, /*On fail goto*//*Label 6890*/ GIMT_Encode4(456606), // Rule ID 14771 //
     /*  456542 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  456545 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456548 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456552 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  456559 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456564 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456568 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456575 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456575 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
     /*  456578 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456600 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456604 */   GIR_RootConstrainSelectedInstOperands,
     /*  456605 */   // GIR_Coverage, 14771,
     /*  456605 */   GIR_EraseRootFromParent_Done,
     /*  456606 */ // Label 6890: @456606
     /*  456606 */ GIM_Try, /*On fail goto*//*Label 6891*/ GIMT_Encode4(456675), // Rule ID 14782 //
     /*  456611 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  456614 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456617 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456621 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  456628 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456633 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456637 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456644 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456644 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  456647 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456669 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456673 */   GIR_RootConstrainSelectedInstOperands,
     /*  456674 */   // GIR_Coverage, 14782,
     /*  456674 */   GIR_EraseRootFromParent_Done,
     /*  456675 */ // Label 6891: @456675
     /*  456675 */ GIM_Try, /*On fail goto*//*Label 6892*/ GIMT_Encode4(456744), // Rule ID 14783 //
     /*  456680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  456683 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456686 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456690 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  456697 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456713 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  456716 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456738 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456742 */   GIR_RootConstrainSelectedInstOperands,
     /*  456743 */   // GIR_Coverage, 14783,
     /*  456743 */   GIR_EraseRootFromParent_Done,
     /*  456744 */ // Label 6892: @456744
     /*  456744 */ GIM_Try, /*On fail goto*//*Label 6893*/ GIMT_Encode4(456813), // Rule ID 14784 //
     /*  456749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  456752 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456755 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456759 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  456766 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456775 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456782 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456782 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  456785 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456811 */   GIR_RootConstrainSelectedInstOperands,
     /*  456812 */   // GIR_Coverage, 14784,
     /*  456812 */   GIR_EraseRootFromParent_Done,
     /*  456813 */ // Label 6893: @456813
     /*  456813 */ GIM_Try, /*On fail goto*//*Label 6894*/ GIMT_Encode4(456882), // Rule ID 14785 //
     /*  456818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  456821 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456824 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456828 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  456835 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456851 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  456854 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456876 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456880 */   GIR_RootConstrainSelectedInstOperands,
     /*  456881 */   // GIR_Coverage, 14785,
     /*  456881 */   GIR_EraseRootFromParent_Done,
     /*  456882 */ // Label 6894: @456882
     /*  456882 */ GIM_Try, /*On fail goto*//*Label 6895*/ GIMT_Encode4(456951), // Rule ID 14786 //
     /*  456887 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  456890 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456893 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  456897 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  456904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456909 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456913 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456920 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
     /*  456923 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456930 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456940 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  456945 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  456949 */   GIR_RootConstrainSelectedInstOperands,
     /*  456950 */   // GIR_Coverage, 14786,
     /*  456950 */   GIR_EraseRootFromParent_Done,
     /*  456951 */ // Label 6895: @456951
     /*  456951 */ GIM_Try, /*On fail goto*//*Label 6896*/ GIMT_Encode4(457009), // Rule ID 14077 //
     /*  456956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  456959 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  456962 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  456967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  456971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  456978 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  456978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  456981 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  456983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  456988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  456993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  456998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457007 */   GIR_RootConstrainSelectedInstOperands,
     /*  457008 */   // GIR_Coverage, 14077,
     /*  457008 */   GIR_EraseRootFromParent_Done,
     /*  457009 */ // Label 6896: @457009
     /*  457009 */ GIM_Try, /*On fail goto*//*Label 6897*/ GIMT_Encode4(457067), // Rule ID 14078 //
     /*  457014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  457017 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457020 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457025 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457029 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457036 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457036 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457039 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457065 */   GIR_RootConstrainSelectedInstOperands,
     /*  457066 */   // GIR_Coverage, 14078,
     /*  457066 */   GIR_EraseRootFromParent_Done,
     /*  457067 */ // Label 6897: @457067
     /*  457067 */ GIM_Try, /*On fail goto*//*Label 6898*/ GIMT_Encode4(457125), // Rule ID 14079 //
     /*  457072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  457075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457094 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457094 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457097 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457119 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457123 */   GIR_RootConstrainSelectedInstOperands,
     /*  457124 */   // GIR_Coverage, 14079,
     /*  457124 */   GIR_EraseRootFromParent_Done,
     /*  457125 */ // Label 6898: @457125
     /*  457125 */ GIM_Try, /*On fail goto*//*Label 6899*/ GIMT_Encode4(457183), // Rule ID 14080 //
     /*  457130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  457133 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457145 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457152 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457152 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457155 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457181 */   GIR_RootConstrainSelectedInstOperands,
     /*  457182 */   // GIR_Coverage, 14080,
     /*  457182 */   GIR_EraseRootFromParent_Done,
     /*  457183 */ // Label 6899: @457183
     /*  457183 */ GIM_Try, /*On fail goto*//*Label 6900*/ GIMT_Encode4(457241), // Rule ID 14081 //
     /*  457188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  457191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457199 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457203 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457210 */   // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457213 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457235 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457239 */   GIR_RootConstrainSelectedInstOperands,
     /*  457240 */   // GIR_Coverage, 14081,
     /*  457240 */   GIR_EraseRootFromParent_Done,
     /*  457241 */ // Label 6900: @457241
     /*  457241 */ GIM_Try, /*On fail goto*//*Label 6901*/ GIMT_Encode4(457299), // Rule ID 14107 //
     /*  457246 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  457249 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457252 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457257 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457261 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457268 */   // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457268 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457271 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457293 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457297 */   GIR_RootConstrainSelectedInstOperands,
     /*  457298 */   // GIR_Coverage, 14107,
     /*  457298 */   GIR_EraseRootFromParent_Done,
     /*  457299 */ // Label 6901: @457299
     /*  457299 */ GIM_Try, /*On fail goto*//*Label 6902*/ GIMT_Encode4(457357), // Rule ID 14108 //
     /*  457304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  457307 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457310 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457326 */   // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457329 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457355 */   GIR_RootConstrainSelectedInstOperands,
     /*  457356 */   // GIR_Coverage, 14108,
     /*  457356 */   GIR_EraseRootFromParent_Done,
     /*  457357 */ // Label 6902: @457357
     /*  457357 */ GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(457415), // Rule ID 14109 //
     /*  457362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  457365 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457368 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457384 */   // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457387 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457409 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457413 */   GIR_RootConstrainSelectedInstOperands,
     /*  457414 */   // GIR_Coverage, 14109,
     /*  457414 */   GIR_EraseRootFromParent_Done,
     /*  457415 */ // Label 6903: @457415
     /*  457415 */ GIM_Try, /*On fail goto*//*Label 6904*/ GIMT_Encode4(457473), // Rule ID 14110 //
     /*  457420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  457423 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457426 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457431 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457435 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457442 */   // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457442 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457445 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457471 */   GIR_RootConstrainSelectedInstOperands,
     /*  457472 */   // GIR_Coverage, 14110,
     /*  457472 */   GIR_EraseRootFromParent_Done,
     /*  457473 */ // Label 6904: @457473
     /*  457473 */ GIM_Try, /*On fail goto*//*Label 6905*/ GIMT_Encode4(457531), // Rule ID 14111 //
     /*  457478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  457481 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457484 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457489 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457493 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  457500 */   // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  457500 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  457503 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457505 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  457510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  457515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  457520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  457525 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457529 */   GIR_RootConstrainSelectedInstOperands,
     /*  457530 */   // GIR_Coverage, 14111,
     /*  457530 */   GIR_EraseRootFromParent_Done,
     /*  457531 */ // Label 6905: @457531
     /*  457531 */ GIM_Try, /*On fail goto*//*Label 6906*/ GIMT_Encode4(457593), // Rule ID 14762 //
     /*  457536 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  457539 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457542 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457546 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  457553 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457558 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457562 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457569 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  457572 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457584 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457587 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457591 */   GIR_RootConstrainSelectedInstOperands,
     /*  457592 */   // GIR_Coverage, 14762,
     /*  457592 */   GIR_EraseRootFromParent_Done,
     /*  457593 */ // Label 6906: @457593
     /*  457593 */ GIM_Try, /*On fail goto*//*Label 6907*/ GIMT_Encode4(457655), // Rule ID 14763 //
     /*  457598 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  457601 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457604 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457608 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  457615 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457620 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457624 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457631 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  457634 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457646 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457649 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457653 */   GIR_RootConstrainSelectedInstOperands,
     /*  457654 */   // GIR_Coverage, 14763,
     /*  457654 */   GIR_EraseRootFromParent_Done,
     /*  457655 */ // Label 6907: @457655
     /*  457655 */ GIM_Try, /*On fail goto*//*Label 6908*/ GIMT_Encode4(457717), // Rule ID 14764 //
     /*  457660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  457663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457666 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457670 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  457677 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457682 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457686 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457693 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457693 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  457696 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457711 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457715 */   GIR_RootConstrainSelectedInstOperands,
     /*  457716 */   // GIR_Coverage, 14764,
     /*  457716 */   GIR_EraseRootFromParent_Done,
     /*  457717 */ // Label 6908: @457717
     /*  457717 */ GIM_Try, /*On fail goto*//*Label 6909*/ GIMT_Encode4(457779), // Rule ID 14765 //
     /*  457722 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  457725 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457728 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457732 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  457739 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457755 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  457758 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457770 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457773 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457777 */   GIR_RootConstrainSelectedInstOperands,
     /*  457778 */   // GIR_Coverage, 14765,
     /*  457778 */   GIR_EraseRootFromParent_Done,
     /*  457779 */ // Label 6909: @457779
     /*  457779 */ GIM_Try, /*On fail goto*//*Label 6910*/ GIMT_Encode4(457841), // Rule ID 14766 //
     /*  457784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  457787 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457790 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457794 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  457801 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457806 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457810 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457817 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457817 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
     /*  457820 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457835 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457839 */   GIR_RootConstrainSelectedInstOperands,
     /*  457840 */   // GIR_Coverage, 14766,
     /*  457840 */   GIR_EraseRootFromParent_Done,
     /*  457841 */ // Label 6910: @457841
     /*  457841 */ GIM_Try, /*On fail goto*//*Label 6911*/ GIMT_Encode4(457903), // Rule ID 14777 //
     /*  457846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  457849 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457852 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457856 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  457863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457879 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  457882 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457894 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457897 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457901 */   GIR_RootConstrainSelectedInstOperands,
     /*  457902 */   // GIR_Coverage, 14777,
     /*  457902 */   GIR_EraseRootFromParent_Done,
     /*  457903 */ // Label 6911: @457903
     /*  457903 */ GIM_Try, /*On fail goto*//*Label 6912*/ GIMT_Encode4(457965), // Rule ID 14778 //
     /*  457908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  457911 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457914 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457918 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  457925 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457930 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  457941 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  457941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  457944 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  457946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  457951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  457956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  457959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  457963 */   GIR_RootConstrainSelectedInstOperands,
     /*  457964 */   // GIR_Coverage, 14778,
     /*  457964 */   GIR_EraseRootFromParent_Done,
     /*  457965 */ // Label 6912: @457965
     /*  457965 */ GIM_Try, /*On fail goto*//*Label 6913*/ GIMT_Encode4(458027), // Rule ID 14779 //
     /*  457970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  457973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  457976 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  457980 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  457987 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  457992 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  457996 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458003 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458003 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  458006 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458018 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458021 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458025 */   GIR_RootConstrainSelectedInstOperands,
     /*  458026 */   // GIR_Coverage, 14779,
     /*  458026 */   GIR_EraseRootFromParent_Done,
     /*  458027 */ // Label 6913: @458027
     /*  458027 */ GIM_Try, /*On fail goto*//*Label 6914*/ GIMT_Encode4(458089), // Rule ID 14780 //
     /*  458032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  458035 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458038 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458042 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  458049 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458054 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458058 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458065 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458065 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  458068 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458087 */   GIR_RootConstrainSelectedInstOperands,
     /*  458088 */   // GIR_Coverage, 14780,
     /*  458088 */   GIR_EraseRootFromParent_Done,
     /*  458089 */ // Label 6914: @458089
     /*  458089 */ GIM_Try, /*On fail goto*//*Label 6915*/ GIMT_Encode4(458151), // Rule ID 14781 //
     /*  458094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  458097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458100 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458104 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  458111 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458116 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458120 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458127 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
     /*  458130 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458142 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458145 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458149 */   GIR_RootConstrainSelectedInstOperands,
     /*  458150 */   // GIR_Coverage, 14781,
     /*  458150 */   GIR_EraseRootFromParent_Done,
     /*  458151 */ // Label 6915: @458151
     /*  458151 */ GIM_Try, /*On fail goto*//*Label 6916*/ GIMT_Encode4(458202), // Rule ID 14072 //
     /*  458156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  458159 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458167 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458171 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458178 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458178 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458181 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458196 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458200 */   GIR_RootConstrainSelectedInstOperands,
     /*  458201 */   // GIR_Coverage, 14072,
     /*  458201 */   GIR_EraseRootFromParent_Done,
     /*  458202 */ // Label 6916: @458202
     /*  458202 */ GIM_Try, /*On fail goto*//*Label 6917*/ GIMT_Encode4(458253), // Rule ID 14073 //
     /*  458207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  458210 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458229 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458232 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458251 */   GIR_RootConstrainSelectedInstOperands,
     /*  458252 */   // GIR_Coverage, 14073,
     /*  458252 */   GIR_EraseRootFromParent_Done,
     /*  458253 */ // Label 6917: @458253
     /*  458253 */ GIM_Try, /*On fail goto*//*Label 6918*/ GIMT_Encode4(458304), // Rule ID 14074 //
     /*  458258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  458261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458269 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458273 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458280 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458283 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458295 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458298 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458302 */   GIR_RootConstrainSelectedInstOperands,
     /*  458303 */   // GIR_Coverage, 14074,
     /*  458303 */   GIR_EraseRootFromParent_Done,
     /*  458304 */ // Label 6918: @458304
     /*  458304 */ GIM_Try, /*On fail goto*//*Label 6919*/ GIMT_Encode4(458355), // Rule ID 14075 //
     /*  458309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  458312 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458315 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458320 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458324 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458331 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458331 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458334 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458346 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458349 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458353 */   GIR_RootConstrainSelectedInstOperands,
     /*  458354 */   // GIR_Coverage, 14075,
     /*  458354 */   GIR_EraseRootFromParent_Done,
     /*  458355 */ // Label 6919: @458355
     /*  458355 */ GIM_Try, /*On fail goto*//*Label 6920*/ GIMT_Encode4(458406), // Rule ID 14076 //
     /*  458360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  458363 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458366 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458371 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458375 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458382 */   // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458385 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458397 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458400 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458404 */   GIR_RootConstrainSelectedInstOperands,
     /*  458405 */   // GIR_Coverage, 14076,
     /*  458405 */   GIR_EraseRootFromParent_Done,
     /*  458406 */ // Label 6920: @458406
     /*  458406 */ GIM_Try, /*On fail goto*//*Label 6921*/ GIMT_Encode4(458457), // Rule ID 14102 //
     /*  458411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  458414 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458422 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458426 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458433 */   // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458436 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458448 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458451 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458455 */   GIR_RootConstrainSelectedInstOperands,
     /*  458456 */   // GIR_Coverage, 14102,
     /*  458456 */   GIR_EraseRootFromParent_Done,
     /*  458457 */ // Label 6921: @458457
     /*  458457 */ GIM_Try, /*On fail goto*//*Label 6922*/ GIMT_Encode4(458508), // Rule ID 14103 //
     /*  458462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  458465 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458468 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458473 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458477 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458484 */   // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458484 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458487 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458506 */   GIR_RootConstrainSelectedInstOperands,
     /*  458507 */   // GIR_Coverage, 14103,
     /*  458507 */   GIR_EraseRootFromParent_Done,
     /*  458508 */ // Label 6922: @458508
     /*  458508 */ GIM_Try, /*On fail goto*//*Label 6923*/ GIMT_Encode4(458559), // Rule ID 14104 //
     /*  458513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  458516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458519 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458535 */   // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458538 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458557 */   GIR_RootConstrainSelectedInstOperands,
     /*  458558 */   // GIR_Coverage, 14104,
     /*  458558 */   GIR_EraseRootFromParent_Done,
     /*  458559 */ // Label 6923: @458559
     /*  458559 */ GIM_Try, /*On fail goto*//*Label 6924*/ GIMT_Encode4(458610), // Rule ID 14105 //
     /*  458564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  458567 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458570 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458575 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458579 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458586 */   // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458586 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458589 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458601 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458604 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458608 */   GIR_RootConstrainSelectedInstOperands,
     /*  458609 */   // GIR_Coverage, 14105,
     /*  458609 */   GIR_EraseRootFromParent_Done,
     /*  458610 */ // Label 6924: @458610
     /*  458610 */ GIM_Try, /*On fail goto*//*Label 6925*/ GIMT_Encode4(458661), // Rule ID 14106 //
     /*  458615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  458618 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458621 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458626 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458630 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  458637 */   // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  458637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  458640 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  458647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458652 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458655 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458659 */   GIR_RootConstrainSelectedInstOperands,
     /*  458660 */   // GIR_Coverage, 14106,
     /*  458660 */   GIR_EraseRootFromParent_Done,
     /*  458661 */ // Label 6925: @458661
     /*  458661 */ GIM_Try, /*On fail goto*//*Label 6926*/ GIMT_Encode4(458723), // Rule ID 14757 //
     /*  458666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  458669 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458672 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458676 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  458683 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458688 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458692 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  458699 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  458699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  458702 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  458709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458714 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458717 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458721 */   GIR_RootConstrainSelectedInstOperands,
     /*  458722 */   // GIR_Coverage, 14757,
     /*  458722 */   GIR_EraseRootFromParent_Done,
     /*  458723 */ // Label 6926: @458723
     /*  458723 */ GIM_Try, /*On fail goto*//*Label 6927*/ GIMT_Encode4(458785), // Rule ID 14758 //
     /*  458728 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  458731 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458734 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458738 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  458745 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458750 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  458761 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  458761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  458764 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  458771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458783 */   GIR_RootConstrainSelectedInstOperands,
     /*  458784 */   // GIR_Coverage, 14758,
     /*  458784 */   GIR_EraseRootFromParent_Done,
     /*  458785 */ // Label 6927: @458785
     /*  458785 */ GIM_Try, /*On fail goto*//*Label 6928*/ GIMT_Encode4(458847), // Rule ID 14759 //
     /*  458790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  458793 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458796 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458800 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  458807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458812 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458816 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  458823 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  458823 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  458826 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  458833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458838 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458841 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458845 */   GIR_RootConstrainSelectedInstOperands,
     /*  458846 */   // GIR_Coverage, 14759,
     /*  458846 */   GIR_EraseRootFromParent_Done,
     /*  458847 */ // Label 6928: @458847
     /*  458847 */ GIM_Try, /*On fail goto*//*Label 6929*/ GIMT_Encode4(458909), // Rule ID 14760 //
     /*  458852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  458855 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458858 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458862 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  458869 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458874 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458878 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  458885 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  458885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  458888 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  458895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458900 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458907 */   GIR_RootConstrainSelectedInstOperands,
     /*  458908 */   // GIR_Coverage, 14760,
     /*  458908 */   GIR_EraseRootFromParent_Done,
     /*  458909 */ // Label 6929: @458909
     /*  458909 */ GIM_Try, /*On fail goto*//*Label 6930*/ GIMT_Encode4(458971), // Rule ID 14761 //
     /*  458914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  458917 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458920 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458924 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  458931 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458936 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  458940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  458947 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  458947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
     /*  458950 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  458952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  458957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  458962 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  458965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  458969 */   GIR_RootConstrainSelectedInstOperands,
     /*  458970 */   // GIR_Coverage, 14761,
     /*  458970 */   GIR_EraseRootFromParent_Done,
     /*  458971 */ // Label 6930: @458971
     /*  458971 */ GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(459033), // Rule ID 14772 //
     /*  458976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  458979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  458982 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  458986 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  458993 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  458998 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459002 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459009 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459009 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  459012 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459024 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459027 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459031 */   GIR_RootConstrainSelectedInstOperands,
     /*  459032 */   // GIR_Coverage, 14772,
     /*  459032 */   GIR_EraseRootFromParent_Done,
     /*  459033 */ // Label 6931: @459033
     /*  459033 */ GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(459095), // Rule ID 14773 //
     /*  459038 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  459041 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459044 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459048 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459055 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459060 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459064 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459071 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  459074 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459093 */   GIR_RootConstrainSelectedInstOperands,
     /*  459094 */   // GIR_Coverage, 14773,
     /*  459094 */   GIR_EraseRootFromParent_Done,
     /*  459095 */ // Label 6932: @459095
     /*  459095 */ GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(459157), // Rule ID 14774 //
     /*  459100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  459103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459106 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459122 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459126 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459133 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  459136 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459148 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459151 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459155 */   GIR_RootConstrainSelectedInstOperands,
     /*  459156 */   // GIR_Coverage, 14774,
     /*  459156 */   GIR_EraseRootFromParent_Done,
     /*  459157 */ // Label 6933: @459157
     /*  459157 */ GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(459219), // Rule ID 14775 //
     /*  459162 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  459165 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459168 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459172 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459179 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459184 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459188 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459195 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  459198 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459205 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459217 */   GIR_RootConstrainSelectedInstOperands,
     /*  459218 */   // GIR_Coverage, 14775,
     /*  459218 */   GIR_EraseRootFromParent_Done,
     /*  459219 */ // Label 6934: @459219
     /*  459219 */ GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(459281), // Rule ID 14776 //
     /*  459224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  459227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459230 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459246 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459250 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459257 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
     /*  459260 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459279 */   GIR_RootConstrainSelectedInstOperands,
     /*  459280 */   // GIR_Coverage, 14776,
     /*  459280 */   GIR_EraseRootFromParent_Done,
     /*  459281 */ // Label 6935: @459281
     /*  459281 */ GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(459332), // Rule ID 14067 //
     /*  459286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  459289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459292 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459297 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459301 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459308 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459308 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459311 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459326 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459330 */   GIR_RootConstrainSelectedInstOperands,
     /*  459331 */   // GIR_Coverage, 14067,
     /*  459331 */   GIR_EraseRootFromParent_Done,
     /*  459332 */ // Label 6936: @459332
     /*  459332 */ GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(459383), // Rule ID 14068 //
     /*  459337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  459340 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459343 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459359 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459362 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459374 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459377 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459381 */   GIR_RootConstrainSelectedInstOperands,
     /*  459382 */   // GIR_Coverage, 14068,
     /*  459382 */   GIR_EraseRootFromParent_Done,
     /*  459383 */ // Label 6937: @459383
     /*  459383 */ GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(459434), // Rule ID 14069 //
     /*  459388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  459391 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459394 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459399 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459403 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459410 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459410 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459413 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459420 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459425 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459428 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459432 */   GIR_RootConstrainSelectedInstOperands,
     /*  459433 */   // GIR_Coverage, 14069,
     /*  459433 */   GIR_EraseRootFromParent_Done,
     /*  459434 */ // Label 6938: @459434
     /*  459434 */ GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(459485), // Rule ID 14070 //
     /*  459439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  459442 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459445 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459450 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459454 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459461 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459464 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459476 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459479 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459483 */   GIR_RootConstrainSelectedInstOperands,
     /*  459484 */   // GIR_Coverage, 14070,
     /*  459484 */   GIR_EraseRootFromParent_Done,
     /*  459485 */ // Label 6939: @459485
     /*  459485 */ GIM_Try, /*On fail goto*//*Label 6940*/ GIMT_Encode4(459536), // Rule ID 14071 //
     /*  459490 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  459493 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459496 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459501 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459505 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459512 */   // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459515 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459527 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459530 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459534 */   GIR_RootConstrainSelectedInstOperands,
     /*  459535 */   // GIR_Coverage, 14071,
     /*  459535 */   GIR_EraseRootFromParent_Done,
     /*  459536 */ // Label 6940: @459536
     /*  459536 */ GIM_Try, /*On fail goto*//*Label 6941*/ GIMT_Encode4(459587), // Rule ID 14097 //
     /*  459541 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  459544 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459547 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459552 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459556 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459563 */   // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459563 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459566 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459578 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459581 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459585 */   GIR_RootConstrainSelectedInstOperands,
     /*  459586 */   // GIR_Coverage, 14097,
     /*  459586 */   GIR_EraseRootFromParent_Done,
     /*  459587 */ // Label 6941: @459587
     /*  459587 */ GIM_Try, /*On fail goto*//*Label 6942*/ GIMT_Encode4(459638), // Rule ID 14098 //
     /*  459592 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  459595 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459598 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459603 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459607 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459614 */   // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459614 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459617 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459629 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459632 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459636 */   GIR_RootConstrainSelectedInstOperands,
     /*  459637 */   // GIR_Coverage, 14098,
     /*  459637 */   GIR_EraseRootFromParent_Done,
     /*  459638 */ // Label 6942: @459638
     /*  459638 */ GIM_Try, /*On fail goto*//*Label 6943*/ GIMT_Encode4(459689), // Rule ID 14099 //
     /*  459643 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  459646 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459654 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459658 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459665 */   // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459668 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459680 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459683 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459687 */   GIR_RootConstrainSelectedInstOperands,
     /*  459688 */   // GIR_Coverage, 14099,
     /*  459688 */   GIR_EraseRootFromParent_Done,
     /*  459689 */ // Label 6943: @459689
     /*  459689 */ GIM_Try, /*On fail goto*//*Label 6944*/ GIMT_Encode4(459740), // Rule ID 14100 //
     /*  459694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  459697 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459700 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459705 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459709 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459716 */   // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459716 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459719 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459731 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459734 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459738 */   GIR_RootConstrainSelectedInstOperands,
     /*  459739 */   // GIR_Coverage, 14100,
     /*  459739 */   GIR_EraseRootFromParent_Done,
     /*  459740 */ // Label 6944: @459740
     /*  459740 */ GIM_Try, /*On fail goto*//*Label 6945*/ GIMT_Encode4(459791), // Rule ID 14101 //
     /*  459745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  459748 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459751 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  459756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  459767 */   // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  459767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  459770 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  459772 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  459777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459782 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  459789 */   GIR_RootConstrainSelectedInstOperands,
     /*  459790 */   // GIR_Coverage, 14101,
     /*  459790 */   GIR_EraseRootFromParent_Done,
     /*  459791 */ // Label 6945: @459791
     /*  459791 */ GIM_Try, /*On fail goto*//*Label 6946*/ GIMT_Encode4(459878), // Rule ID 29365 //
     /*  459796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode0),
     /*  459799 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459802 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459806 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459813 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  459818 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  459822 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  459826 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  459830 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  459834 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  459838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459842 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  459844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  459851 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>>  =>  (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  459851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI),
     /*  459854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  459859 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  459863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459871 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  459876 */   GIR_RootConstrainSelectedInstOperands,
     /*  459877 */   // GIR_Coverage, 29365,
     /*  459877 */   GIR_EraseRootFromParent_Done,
     /*  459878 */ // Label 6946: @459878
     /*  459878 */ GIM_Try, /*On fail goto*//*Label 6947*/ GIMT_Encode4(459965), // Rule ID 29366 //
     /*  459883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode1),
     /*  459886 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459889 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459893 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459900 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  459905 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  459909 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  459913 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  459917 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  459921 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  459925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  459929 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  459931 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  459938 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>>  =>  (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  459938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI),
     /*  459941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  459946 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  459950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  459955 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  459958 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  459963 */   GIR_RootConstrainSelectedInstOperands,
     /*  459964 */   // GIR_Coverage, 29366,
     /*  459964 */   GIR_EraseRootFromParent_Done,
     /*  459965 */ // Label 6947: @459965
     /*  459965 */ GIM_Try, /*On fail goto*//*Label 6948*/ GIMT_Encode4(460052), // Rule ID 29367 //
     /*  459970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode2),
     /*  459973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  459976 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  459980 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  459987 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  459992 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  459996 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460000 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460004 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460008 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460016 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460018 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460025 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>>  =>  (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI),
     /*  460028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460033 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460042 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460045 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460050 */   GIR_RootConstrainSelectedInstOperands,
     /*  460051 */   // GIR_Coverage, 29367,
     /*  460051 */   GIR_EraseRootFromParent_Done,
     /*  460052 */ // Label 6948: @460052
     /*  460052 */ GIM_Try, /*On fail goto*//*Label 6949*/ GIMT_Encode4(460139), // Rule ID 29368 //
     /*  460057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode3),
     /*  460060 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460063 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460067 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  460074 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460079 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460083 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460087 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460091 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460095 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460099 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460103 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460105 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460112 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>>  =>  (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI),
     /*  460115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460120 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460132 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460137 */   GIR_RootConstrainSelectedInstOperands,
     /*  460138 */   // GIR_Coverage, 29368,
     /*  460138 */   GIR_EraseRootFromParent_Done,
     /*  460139 */ // Label 6949: @460139
     /*  460139 */ GIM_Try, /*On fail goto*//*Label 6950*/ GIMT_Encode4(460226), // Rule ID 29369 //
     /*  460144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode4),
     /*  460147 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460150 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460154 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  460161 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460166 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460170 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460174 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460178 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460182 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460186 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460190 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460192 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460199 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>>  =>  (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI),
     /*  460202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460207 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460216 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460219 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460224 */   GIR_RootConstrainSelectedInstOperands,
     /*  460225 */   // GIR_Coverage, 29369,
     /*  460225 */   GIR_EraseRootFromParent_Done,
     /*  460226 */ // Label 6950: @460226
     /*  460226 */ GIM_Try, /*On fail goto*//*Label 6951*/ GIMT_Encode4(460313), // Rule ID 29370 //
     /*  460231 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode0),
     /*  460234 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460237 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460241 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460248 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460253 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460257 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460261 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460265 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460269 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460277 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460279 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460286 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>>  =>  (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI),
     /*  460289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460294 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460303 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460306 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460311 */   GIR_RootConstrainSelectedInstOperands,
     /*  460312 */   // GIR_Coverage, 29370,
     /*  460312 */   GIR_EraseRootFromParent_Done,
     /*  460313 */ // Label 6951: @460313
     /*  460313 */ GIM_Try, /*On fail goto*//*Label 6952*/ GIMT_Encode4(460400), // Rule ID 29371 //
     /*  460318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode1),
     /*  460321 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460324 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460328 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460335 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460340 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460344 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460348 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460352 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460356 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460360 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460364 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460366 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460373 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>>  =>  (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI),
     /*  460376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460381 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460390 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460398 */   GIR_RootConstrainSelectedInstOperands,
     /*  460399 */   // GIR_Coverage, 29371,
     /*  460399 */   GIR_EraseRootFromParent_Done,
     /*  460400 */ // Label 6952: @460400
     /*  460400 */ GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(460487), // Rule ID 29372 //
     /*  460405 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode2),
     /*  460408 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460411 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460415 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460422 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460427 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460431 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460435 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460439 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460443 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460447 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460451 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460453 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460460 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>>  =>  (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460460 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI),
     /*  460463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460468 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460477 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460480 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460485 */   GIR_RootConstrainSelectedInstOperands,
     /*  460486 */   // GIR_Coverage, 29372,
     /*  460486 */   GIR_EraseRootFromParent_Done,
     /*  460487 */ // Label 6953: @460487
     /*  460487 */ GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(460574), // Rule ID 29373 //
     /*  460492 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode3),
     /*  460495 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460498 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460502 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460514 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460518 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460522 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460526 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460530 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460534 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460538 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460540 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460547 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>>  =>  (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460547 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI),
     /*  460550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460555 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460564 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460572 */   GIR_RootConstrainSelectedInstOperands,
     /*  460573 */   // GIR_Coverage, 29373,
     /*  460573 */   GIR_EraseRootFromParent_Done,
     /*  460574 */ // Label 6954: @460574
     /*  460574 */ GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(460661), // Rule ID 29374 //
     /*  460579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode4),
     /*  460582 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  460585 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  460589 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460596 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  460601 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  460605 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  460609 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  460613 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  460617 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  460621 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460625 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  460627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  460634 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>>  =>  (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  460634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI),
     /*  460637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  460642 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
     /*  460646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  460651 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460654 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  460659 */   GIR_RootConstrainSelectedInstOperands,
     /*  460660 */   // GIR_Coverage, 29374,
     /*  460660 */   GIR_EraseRootFromParent_Done,
     /*  460661 */ // Label 6955: @460661
     /*  460661 */ GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(460734), // Rule ID 25621 //
     /*  460666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  460669 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  460672 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460679 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  460686 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  460697 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  460697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  460700 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  460702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  460707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  460712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  460717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  460722 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460725 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460728 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  460732 */   GIR_RootConstrainSelectedInstOperands,
     /*  460733 */   // GIR_Coverage, 25621,
     /*  460733 */   GIR_EraseRootFromParent_Done,
     /*  460734 */ // Label 6956: @460734
     /*  460734 */ GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(460807), // Rule ID 25622 //
     /*  460739 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  460742 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  460745 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460752 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  460759 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460763 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  460770 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  460770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  460773 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  460775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  460780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  460785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  460790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  460795 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460798 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  460805 */   GIR_RootConstrainSelectedInstOperands,
     /*  460806 */   // GIR_Coverage, 25622,
     /*  460806 */   GIR_EraseRootFromParent_Done,
     /*  460807 */ // Label 6957: @460807
     /*  460807 */ GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(460880), // Rule ID 25623 //
     /*  460812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  460815 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  460818 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460825 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  460832 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460836 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  460843 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  460843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  460846 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  460848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  460853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  460858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  460863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  460868 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460874 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  460878 */   GIR_RootConstrainSelectedInstOperands,
     /*  460879 */   // GIR_Coverage, 25623,
     /*  460879 */   GIR_EraseRootFromParent_Done,
     /*  460880 */ // Label 6958: @460880
     /*  460880 */ GIM_Try, /*On fail goto*//*Label 6959*/ GIMT_Encode4(460953), // Rule ID 25624 //
     /*  460885 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  460888 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  460891 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  460905 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460909 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  460916 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  460916 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  460919 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  460921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  460926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  460931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  460936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  460941 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460944 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  460947 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  460951 */   GIR_RootConstrainSelectedInstOperands,
     /*  460952 */   // GIR_Coverage, 25624,
     /*  460952 */   GIR_EraseRootFromParent_Done,
     /*  460953 */ // Label 6959: @460953
     /*  460953 */ GIM_Try, /*On fail goto*//*Label 6960*/ GIMT_Encode4(461026), // Rule ID 25625 //
     /*  460958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  460961 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  460964 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  460971 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  460978 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  460982 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  460989 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  460989 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  460992 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  460994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  460999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461014 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461017 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461020 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461024 */   GIR_RootConstrainSelectedInstOperands,
     /*  461025 */   // GIR_Coverage, 25625,
     /*  461025 */   GIR_EraseRootFromParent_Done,
     /*  461026 */ // Label 6960: @461026
     /*  461026 */ GIM_Try, /*On fail goto*//*Label 6961*/ GIMT_Encode4(461099), // Rule ID 25641 //
     /*  461031 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  461034 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461037 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  461044 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461051 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461062 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  461065 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461072 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461077 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461087 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461090 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461093 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461097 */   GIR_RootConstrainSelectedInstOperands,
     /*  461098 */   // GIR_Coverage, 25641,
     /*  461098 */   GIR_EraseRootFromParent_Done,
     /*  461099 */ // Label 6961: @461099
     /*  461099 */ GIM_Try, /*On fail goto*//*Label 6962*/ GIMT_Encode4(461172), // Rule ID 25642 //
     /*  461104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  461107 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  461117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461135 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  461138 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461170 */   GIR_RootConstrainSelectedInstOperands,
     /*  461171 */   // GIR_Coverage, 25642,
     /*  461171 */   GIR_EraseRootFromParent_Done,
     /*  461172 */ // Label 6962: @461172
     /*  461172 */ GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(461245), // Rule ID 25643 //
     /*  461177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  461180 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461183 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  461190 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461197 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461201 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461208 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461208 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  461211 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461233 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461236 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461239 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461243 */   GIR_RootConstrainSelectedInstOperands,
     /*  461244 */   // GIR_Coverage, 25643,
     /*  461244 */   GIR_EraseRootFromParent_Done,
     /*  461245 */ // Label 6963: @461245
     /*  461245 */ GIM_Try, /*On fail goto*//*Label 6964*/ GIMT_Encode4(461318), // Rule ID 25644 //
     /*  461250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  461253 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  461263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461274 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461281 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461281 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  461284 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461306 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461309 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461312 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461316 */   GIR_RootConstrainSelectedInstOperands,
     /*  461317 */   // GIR_Coverage, 25644,
     /*  461317 */   GIR_EraseRootFromParent_Done,
     /*  461318 */ // Label 6964: @461318
     /*  461318 */ GIM_Try, /*On fail goto*//*Label 6965*/ GIMT_Encode4(461391), // Rule ID 25645 //
     /*  461323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  461326 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461329 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  461336 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461354 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  461357 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461379 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461382 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461385 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461389 */   GIR_RootConstrainSelectedInstOperands,
     /*  461390 */   // GIR_Coverage, 25645,
     /*  461390 */   GIR_EraseRootFromParent_Done,
     /*  461391 */ // Label 6965: @461391
     /*  461391 */ GIM_Try, /*On fail goto*//*Label 6966*/ GIMT_Encode4(461464), // Rule ID 25661 //
     /*  461396 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  461399 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461402 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  461409 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461416 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461420 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461427 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461427 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  461430 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461437 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461442 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461452 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461455 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461458 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461462 */   GIR_RootConstrainSelectedInstOperands,
     /*  461463 */   // GIR_Coverage, 25661,
     /*  461463 */   GIR_EraseRootFromParent_Done,
     /*  461464 */ // Label 6966: @461464
     /*  461464 */ GIM_Try, /*On fail goto*//*Label 6967*/ GIMT_Encode4(461537), // Rule ID 25662 //
     /*  461469 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  461472 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461475 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  461482 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461489 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461493 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461500 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461500 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  461503 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461505 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461510 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461531 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461535 */   GIR_RootConstrainSelectedInstOperands,
     /*  461536 */   // GIR_Coverage, 25662,
     /*  461536 */   GIR_EraseRootFromParent_Done,
     /*  461537 */ // Label 6967: @461537
     /*  461537 */ GIM_Try, /*On fail goto*//*Label 6968*/ GIMT_Encode4(461610), // Rule ID 25663 //
     /*  461542 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  461545 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461548 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  461555 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461562 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461566 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461573 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  461576 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461598 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461601 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461604 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461608 */   GIR_RootConstrainSelectedInstOperands,
     /*  461609 */   // GIR_Coverage, 25663,
     /*  461609 */   GIR_EraseRootFromParent_Done,
     /*  461610 */ // Label 6968: @461610
     /*  461610 */ GIM_Try, /*On fail goto*//*Label 6969*/ GIMT_Encode4(461683), // Rule ID 25664 //
     /*  461615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  461618 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461621 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  461628 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461635 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461639 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461646 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  461649 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461674 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461677 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461681 */   GIR_RootConstrainSelectedInstOperands,
     /*  461682 */   // GIR_Coverage, 25664,
     /*  461682 */   GIR_EraseRootFromParent_Done,
     /*  461683 */ // Label 6969: @461683
     /*  461683 */ GIM_Try, /*On fail goto*//*Label 6970*/ GIMT_Encode4(461756), // Rule ID 25665 //
     /*  461688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  461691 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  461694 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  461701 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461719 */   // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  461719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  461722 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  461724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461744 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461747 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461750 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461754 */   GIR_RootConstrainSelectedInstOperands,
     /*  461755 */   // GIR_Coverage, 25665,
     /*  461755 */   GIR_EraseRootFromParent_Done,
     /*  461756 */ // Label 6970: @461756
     /*  461756 */ GIM_Try, /*On fail goto*//*Label 6971*/ GIMT_Encode4(461833), // Rule ID 15048 //
     /*  461761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  461764 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  461767 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  461771 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  461778 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461789 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461796 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  461796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  461799 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  461801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461821 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461831 */   GIR_RootConstrainSelectedInstOperands,
     /*  461832 */   // GIR_Coverage, 15048,
     /*  461832 */   GIR_EraseRootFromParent_Done,
     /*  461833 */ // Label 6971: @461833
     /*  461833 */ GIM_Try, /*On fail goto*//*Label 6972*/ GIMT_Encode4(461910), // Rule ID 15049 //
     /*  461838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  461841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  461844 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  461848 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  461855 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461862 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461866 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461873 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  461873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  461876 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  461878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461888 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461898 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461901 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461904 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461908 */   GIR_RootConstrainSelectedInstOperands,
     /*  461909 */   // GIR_Coverage, 15049,
     /*  461909 */   GIR_EraseRootFromParent_Done,
     /*  461910 */ // Label 6972: @461910
     /*  461910 */ GIM_Try, /*On fail goto*//*Label 6973*/ GIMT_Encode4(461987), // Rule ID 15050 //
     /*  461915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  461918 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  461921 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  461925 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  461932 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  461939 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  461943 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  461950 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  461950 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  461953 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  461955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  461960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  461965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  461970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  461975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  461981 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  461985 */   GIR_RootConstrainSelectedInstOperands,
     /*  461986 */   // GIR_Coverage, 15050,
     /*  461986 */   GIR_EraseRootFromParent_Done,
     /*  461987 */ // Label 6973: @461987
     /*  461987 */ GIM_Try, /*On fail goto*//*Label 6974*/ GIMT_Encode4(462064), // Rule ID 15051 //
     /*  461992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  461995 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  461998 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462002 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462020 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462027 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  462030 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462052 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462055 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462058 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462062 */   GIR_RootConstrainSelectedInstOperands,
     /*  462063 */   // GIR_Coverage, 15051,
     /*  462063 */   GIR_EraseRootFromParent_Done,
     /*  462064 */ // Label 6974: @462064
     /*  462064 */ GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(462141), // Rule ID 15052 //
     /*  462069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  462072 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462075 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462079 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462086 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462093 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462097 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462104 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
     /*  462107 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462132 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462135 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462139 */   GIR_RootConstrainSelectedInstOperands,
     /*  462140 */   // GIR_Coverage, 15052,
     /*  462140 */   GIR_EraseRootFromParent_Done,
     /*  462141 */ // Label 6975: @462141
     /*  462141 */ GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(462218), // Rule ID 15868 //
     /*  462146 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  462149 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462152 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462156 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462163 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462170 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462174 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462181 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64),
     /*  462184 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462206 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462216 */   GIR_RootConstrainSelectedInstOperands,
     /*  462217 */   // GIR_Coverage, 15868,
     /*  462217 */   GIR_EraseRootFromParent_Done,
     /*  462218 */ // Label 6976: @462218
     /*  462218 */ GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(462295), // Rule ID 15869 //
     /*  462223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  462226 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462229 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462233 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462240 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462258 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64),
     /*  462261 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462283 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462293 */   GIR_RootConstrainSelectedInstOperands,
     /*  462294 */   // GIR_Coverage, 15869,
     /*  462294 */   GIR_EraseRootFromParent_Done,
     /*  462295 */ // Label 6977: @462295
     /*  462295 */ GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(462372), // Rule ID 15870 //
     /*  462300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  462303 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462306 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462310 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462317 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462335 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64),
     /*  462338 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462360 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462370 */   GIR_RootConstrainSelectedInstOperands,
     /*  462371 */   // GIR_Coverage, 15870,
     /*  462371 */   GIR_EraseRootFromParent_Done,
     /*  462372 */ // Label 6978: @462372
     /*  462372 */ GIM_Try, /*On fail goto*//*Label 6979*/ GIMT_Encode4(462449), // Rule ID 15871 //
     /*  462377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  462380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462383 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462387 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462394 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462412 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64),
     /*  462415 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462440 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462443 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462447 */   GIR_RootConstrainSelectedInstOperands,
     /*  462448 */   // GIR_Coverage, 15871,
     /*  462448 */   GIR_EraseRootFromParent_Done,
     /*  462449 */ // Label 6979: @462449
     /*  462449 */ GIM_Try, /*On fail goto*//*Label 6980*/ GIMT_Encode4(462526), // Rule ID 15872 //
     /*  462454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  462457 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462460 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462464 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  462471 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462489 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64),
     /*  462492 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462514 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462517 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462520 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462524 */   GIR_RootConstrainSelectedInstOperands,
     /*  462525 */   // GIR_Coverage, 15872,
     /*  462525 */   GIR_EraseRootFromParent_Done,
     /*  462526 */ // Label 6980: @462526
     /*  462526 */ GIM_Try, /*On fail goto*//*Label 6981*/ GIMT_Encode4(462603), // Rule ID 15878 //
     /*  462531 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  462534 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462537 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462541 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  462548 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462566 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  462569 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462591 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462594 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462597 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462601 */   GIR_RootConstrainSelectedInstOperands,
     /*  462602 */   // GIR_Coverage, 15878,
     /*  462602 */   GIR_EraseRootFromParent_Done,
     /*  462603 */ // Label 6981: @462603
     /*  462603 */ GIM_Try, /*On fail goto*//*Label 6982*/ GIMT_Encode4(462680), // Rule ID 15879 //
     /*  462608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  462611 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462614 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462618 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  462625 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462643 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  462646 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462678 */   GIR_RootConstrainSelectedInstOperands,
     /*  462679 */   // GIR_Coverage, 15879,
     /*  462679 */   GIR_EraseRootFromParent_Done,
     /*  462680 */ // Label 6982: @462680
     /*  462680 */ GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(462757), // Rule ID 15880 //
     /*  462685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  462688 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462691 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462695 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  462702 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462709 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462713 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462720 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462720 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  462723 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462745 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462748 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462751 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462755 */   GIR_RootConstrainSelectedInstOperands,
     /*  462756 */   // GIR_Coverage, 15880,
     /*  462756 */   GIR_EraseRootFromParent_Done,
     /*  462757 */ // Label 6983: @462757
     /*  462757 */ GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(462834), // Rule ID 15881 //
     /*  462762 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  462765 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462768 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462772 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  462779 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462786 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462790 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462797 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462797 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  462800 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462807 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462822 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462832 */   GIR_RootConstrainSelectedInstOperands,
     /*  462833 */   // GIR_Coverage, 15881,
     /*  462833 */   GIR_EraseRootFromParent_Done,
     /*  462834 */ // Label 6984: @462834
     /*  462834 */ GIM_Try, /*On fail goto*//*Label 6985*/ GIMT_Encode4(462911), // Rule ID 15882 //
     /*  462839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  462842 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462845 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462849 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  462856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462863 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462867 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462874 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462874 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
     /*  462877 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462899 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462902 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462905 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462909 */   GIR_RootConstrainSelectedInstOperands,
     /*  462910 */   // GIR_Coverage, 15882,
     /*  462910 */   GIR_EraseRootFromParent_Done,
     /*  462911 */ // Label 6985: @462911
     /*  462911 */ GIM_Try, /*On fail goto*//*Label 6986*/ GIMT_Encode4(462988), // Rule ID 15888 //
     /*  462916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  462919 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462922 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  462926 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  462933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  462940 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  462944 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  462951 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  462951 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64),
     /*  462954 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  462956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  462961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  462966 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  462971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  462976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462979 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  462982 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  462986 */   GIR_RootConstrainSelectedInstOperands,
     /*  462987 */   // GIR_Coverage, 15888,
     /*  462987 */   GIR_EraseRootFromParent_Done,
     /*  462988 */ // Label 6986: @462988
     /*  462988 */ GIM_Try, /*On fail goto*//*Label 6987*/ GIMT_Encode4(463065), // Rule ID 15889 //
     /*  462993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  462996 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  462999 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463003 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  463010 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  463017 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463021 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  463028 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  463028 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64),
     /*  463031 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  463033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463053 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463056 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463059 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463063 */   GIR_RootConstrainSelectedInstOperands,
     /*  463064 */   // GIR_Coverage, 15889,
     /*  463064 */   GIR_EraseRootFromParent_Done,
     /*  463065 */ // Label 6987: @463065
     /*  463065 */ GIM_Try, /*On fail goto*//*Label 6988*/ GIMT_Encode4(463142), // Rule ID 15890 //
     /*  463070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  463073 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463076 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463080 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  463087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  463094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  463105 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  463105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64),
     /*  463108 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  463110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463133 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463136 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463140 */   GIR_RootConstrainSelectedInstOperands,
     /*  463141 */   // GIR_Coverage, 15890,
     /*  463141 */   GIR_EraseRootFromParent_Done,
     /*  463142 */ // Label 6988: @463142
     /*  463142 */ GIM_Try, /*On fail goto*//*Label 6989*/ GIMT_Encode4(463219), // Rule ID 15891 //
     /*  463147 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  463150 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463153 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463157 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  463164 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  463171 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463175 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  463182 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  463182 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64),
     /*  463185 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  463187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463192 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463213 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463217 */   GIR_RootConstrainSelectedInstOperands,
     /*  463218 */   // GIR_Coverage, 15891,
     /*  463218 */   GIR_EraseRootFromParent_Done,
     /*  463219 */ // Label 6989: @463219
     /*  463219 */ GIM_Try, /*On fail goto*//*Label 6990*/ GIMT_Encode4(463296), // Rule ID 15892 //
     /*  463224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  463227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463230 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463234 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  463241 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  463248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463252 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  463259 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  463259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64),
     /*  463262 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  463264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463279 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463287 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463290 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463294 */   GIR_RootConstrainSelectedInstOperands,
     /*  463295 */   // GIR_Coverage, 15892,
     /*  463295 */   GIR_EraseRootFromParent_Done,
     /*  463296 */ // Label 6990: @463296
     /*  463296 */ GIM_Try, /*On fail goto*//*Label 6991*/ GIMT_Encode4(463371), // Rule ID 25701 //
     /*  463301 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  463304 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463307 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463311 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463318 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463323 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463327 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463334 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463334 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  463337 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463359 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463362 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463365 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463369 */   GIR_RootConstrainSelectedInstOperands,
     /*  463370 */   // GIR_Coverage, 25701,
     /*  463370 */   GIR_EraseRootFromParent_Done,
     /*  463371 */ // Label 6991: @463371
     /*  463371 */ GIM_Try, /*On fail goto*//*Label 6992*/ GIMT_Encode4(463446), // Rule ID 25702 //
     /*  463376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  463379 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463382 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463386 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463393 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463398 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463402 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463409 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463409 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  463412 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463444 */   GIR_RootConstrainSelectedInstOperands,
     /*  463445 */   // GIR_Coverage, 25702,
     /*  463445 */   GIR_EraseRootFromParent_Done,
     /*  463446 */ // Label 6992: @463446
     /*  463446 */ GIM_Try, /*On fail goto*//*Label 6993*/ GIMT_Encode4(463521), // Rule ID 25703 //
     /*  463451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  463454 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463457 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463461 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463468 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463473 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463477 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463484 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463484 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  463487 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463504 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463509 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463512 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463515 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463519 */   GIR_RootConstrainSelectedInstOperands,
     /*  463520 */   // GIR_Coverage, 25703,
     /*  463520 */   GIR_EraseRootFromParent_Done,
     /*  463521 */ // Label 6993: @463521
     /*  463521 */ GIM_Try, /*On fail goto*//*Label 6994*/ GIMT_Encode4(463596), // Rule ID 25704 //
     /*  463526 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  463529 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463532 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463536 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463543 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463548 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463552 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463559 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463559 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  463562 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463584 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463587 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463594 */   GIR_RootConstrainSelectedInstOperands,
     /*  463595 */   // GIR_Coverage, 25704,
     /*  463595 */   GIR_EraseRootFromParent_Done,
     /*  463596 */ // Label 6994: @463596
     /*  463596 */ GIM_Try, /*On fail goto*//*Label 6995*/ GIMT_Encode4(463671), // Rule ID 25705 //
     /*  463601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  463604 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463607 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463611 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463634 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
     /*  463637 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463639 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463662 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463665 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463669 */   GIR_RootConstrainSelectedInstOperands,
     /*  463670 */   // GIR_Coverage, 25705,
     /*  463670 */   GIR_EraseRootFromParent_Done,
     /*  463671 */ // Label 6995: @463671
     /*  463671 */ GIM_Try, /*On fail goto*//*Label 6996*/ GIMT_Encode4(463746), // Rule ID 25711 //
     /*  463676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  463679 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463682 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463686 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463693 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463698 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463702 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463709 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463709 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  463712 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463737 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463740 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463744 */   GIR_RootConstrainSelectedInstOperands,
     /*  463745 */   // GIR_Coverage, 25711,
     /*  463745 */   GIR_EraseRootFromParent_Done,
     /*  463746 */ // Label 6996: @463746
     /*  463746 */ GIM_Try, /*On fail goto*//*Label 6997*/ GIMT_Encode4(463821), // Rule ID 25712 //
     /*  463751 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  463754 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463757 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463761 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463768 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463773 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463777 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463784 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  463787 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463799 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463809 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463812 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463815 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463819 */   GIR_RootConstrainSelectedInstOperands,
     /*  463820 */   // GIR_Coverage, 25712,
     /*  463820 */   GIR_EraseRootFromParent_Done,
     /*  463821 */ // Label 6997: @463821
     /*  463821 */ GIM_Try, /*On fail goto*//*Label 6998*/ GIMT_Encode4(463896), // Rule ID 25713 //
     /*  463826 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  463829 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463832 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463836 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463843 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463852 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463859 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463859 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  463862 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463869 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463874 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463890 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463894 */   GIR_RootConstrainSelectedInstOperands,
     /*  463895 */   // GIR_Coverage, 25713,
     /*  463895 */   GIR_EraseRootFromParent_Done,
     /*  463896 */ // Label 6998: @463896
     /*  463896 */ GIM_Try, /*On fail goto*//*Label 6999*/ GIMT_Encode4(463971), // Rule ID 25714 //
     /*  463901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  463904 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463907 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463911 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463918 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463923 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  463927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  463934 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  463934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  463937 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  463939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  463944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  463949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  463954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  463959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463962 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  463965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  463969 */   GIR_RootConstrainSelectedInstOperands,
     /*  463970 */   // GIR_Coverage, 25714,
     /*  463970 */   GIR_EraseRootFromParent_Done,
     /*  463971 */ // Label 6999: @463971
     /*  463971 */ GIM_Try, /*On fail goto*//*Label 7000*/ GIMT_Encode4(464046), // Rule ID 25715 //
     /*  463976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  463979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  463982 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  463986 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  463993 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  463998 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464002 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464009 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464009 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
     /*  464012 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464034 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464040 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464044 */   GIR_RootConstrainSelectedInstOperands,
     /*  464045 */   // GIR_Coverage, 25715,
     /*  464045 */   GIR_EraseRootFromParent_Done,
     /*  464046 */ // Label 7000: @464046
     /*  464046 */ GIM_Try, /*On fail goto*//*Label 7001*/ GIMT_Encode4(464121), // Rule ID 25721 //
     /*  464051 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  464054 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464057 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464061 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464073 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464077 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464084 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464084 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  464087 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464112 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464115 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464119 */   GIR_RootConstrainSelectedInstOperands,
     /*  464120 */   // GIR_Coverage, 25721,
     /*  464120 */   GIR_EraseRootFromParent_Done,
     /*  464121 */ // Label 7001: @464121
     /*  464121 */ GIM_Try, /*On fail goto*//*Label 7002*/ GIMT_Encode4(464196), // Rule ID 25722 //
     /*  464126 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  464129 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464132 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464136 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464143 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464152 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464159 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  464162 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464190 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464194 */   GIR_RootConstrainSelectedInstOperands,
     /*  464195 */   // GIR_Coverage, 25722,
     /*  464195 */   GIR_EraseRootFromParent_Done,
     /*  464196 */ // Label 7002: @464196
     /*  464196 */ GIM_Try, /*On fail goto*//*Label 7003*/ GIMT_Encode4(464271), // Rule ID 25723 //
     /*  464201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  464204 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464207 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464211 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464223 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464227 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464234 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  464237 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464262 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464265 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464269 */   GIR_RootConstrainSelectedInstOperands,
     /*  464270 */   // GIR_Coverage, 25723,
     /*  464270 */   GIR_EraseRootFromParent_Done,
     /*  464271 */ // Label 7003: @464271
     /*  464271 */ GIM_Try, /*On fail goto*//*Label 7004*/ GIMT_Encode4(464346), // Rule ID 25724 //
     /*  464276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  464279 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464282 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464286 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464293 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464298 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464302 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464309 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464309 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  464312 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464334 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464340 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464344 */   GIR_RootConstrainSelectedInstOperands,
     /*  464345 */   // GIR_Coverage, 25724,
     /*  464345 */   GIR_EraseRootFromParent_Done,
     /*  464346 */ // Label 7004: @464346
     /*  464346 */ GIM_Try, /*On fail goto*//*Label 7005*/ GIMT_Encode4(464421), // Rule ID 25725 //
     /*  464351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  464354 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464357 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464361 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464368 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464373 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464377 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464384 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
     /*  464387 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464409 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464412 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464415 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464419 */   GIR_RootConstrainSelectedInstOperands,
     /*  464420 */   // GIR_Coverage, 25725,
     /*  464420 */   GIR_EraseRootFromParent_Done,
     /*  464421 */ // Label 7005: @464421
     /*  464421 */ GIM_Try, /*On fail goto*//*Label 7006*/ GIMT_Encode4(464496), // Rule ID 25731 //
     /*  464426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  464429 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464432 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464436 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464443 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464448 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464452 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464459 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464459 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  464462 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464487 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464490 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464494 */   GIR_RootConstrainSelectedInstOperands,
     /*  464495 */   // GIR_Coverage, 25731,
     /*  464495 */   GIR_EraseRootFromParent_Done,
     /*  464496 */ // Label 7006: @464496
     /*  464496 */ GIM_Try, /*On fail goto*//*Label 7007*/ GIMT_Encode4(464571), // Rule ID 25732 //
     /*  464501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  464504 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464507 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464511 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464518 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464523 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464527 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464534 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464534 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  464537 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464539 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464544 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464559 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464562 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464565 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464569 */   GIR_RootConstrainSelectedInstOperands,
     /*  464570 */   // GIR_Coverage, 25732,
     /*  464570 */   GIR_EraseRootFromParent_Done,
     /*  464571 */ // Label 7007: @464571
     /*  464571 */ GIM_Try, /*On fail goto*//*Label 7008*/ GIMT_Encode4(464646), // Rule ID 25733 //
     /*  464576 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  464579 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464582 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464586 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464593 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464609 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  464612 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464634 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464637 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464640 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464644 */   GIR_RootConstrainSelectedInstOperands,
     /*  464645 */   // GIR_Coverage, 25733,
     /*  464645 */   GIR_EraseRootFromParent_Done,
     /*  464646 */ // Label 7008: @464646
     /*  464646 */ GIM_Try, /*On fail goto*//*Label 7009*/ GIMT_Encode4(464721), // Rule ID 25734 //
     /*  464651 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  464654 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464657 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464661 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464668 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464673 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464677 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464684 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  464687 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464709 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464715 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464719 */   GIR_RootConstrainSelectedInstOperands,
     /*  464720 */   // GIR_Coverage, 25734,
     /*  464720 */   GIR_EraseRootFromParent_Done,
     /*  464721 */ // Label 7009: @464721
     /*  464721 */ GIM_Try, /*On fail goto*//*Label 7010*/ GIMT_Encode4(464796), // Rule ID 25735 //
     /*  464726 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  464729 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464732 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  464736 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  464743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  464748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  464759 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  464759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
     /*  464762 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  464764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464784 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464787 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464790 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464794 */   GIR_RootConstrainSelectedInstOperands,
     /*  464795 */   // GIR_Coverage, 25735,
     /*  464795 */   GIR_EraseRootFromParent_Done,
     /*  464796 */ // Label 7010: @464796
     /*  464796 */ GIM_Try, /*On fail goto*//*Label 7011*/ GIMT_Encode4(464862), // Rule ID 15898 //
     /*  464801 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  464804 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  464814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  464825 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  464825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  464828 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  464830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464850 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464853 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464856 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464860 */   GIR_RootConstrainSelectedInstOperands,
     /*  464861 */   // GIR_Coverage, 15898,
     /*  464861 */   GIR_EraseRootFromParent_Done,
     /*  464862 */ // Label 7011: @464862
     /*  464862 */ GIM_Try, /*On fail goto*//*Label 7012*/ GIMT_Encode4(464928), // Rule ID 15899 //
     /*  464867 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  464870 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464873 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  464880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  464891 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  464891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  464894 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  464896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464922 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464926 */   GIR_RootConstrainSelectedInstOperands,
     /*  464927 */   // GIR_Coverage, 15899,
     /*  464927 */   GIR_EraseRootFromParent_Done,
     /*  464928 */ // Label 7012: @464928
     /*  464928 */ GIM_Try, /*On fail goto*//*Label 7013*/ GIMT_Encode4(464994), // Rule ID 15900 //
     /*  464933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  464936 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  464939 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  464946 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  464950 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  464957 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  464957 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  464960 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  464962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  464967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  464972 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  464977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  464982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464985 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  464988 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  464992 */   GIR_RootConstrainSelectedInstOperands,
     /*  464993 */   // GIR_Coverage, 15900,
     /*  464993 */   GIR_EraseRootFromParent_Done,
     /*  464994 */ // Label 7013: @464994
     /*  464994 */ GIM_Try, /*On fail goto*//*Label 7014*/ GIMT_Encode4(465060), // Rule ID 15901 //
     /*  464999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  465002 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465005 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465023 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465026 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465048 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465051 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465054 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465058 */   GIR_RootConstrainSelectedInstOperands,
     /*  465059 */   // GIR_Coverage, 15901,
     /*  465059 */   GIR_EraseRootFromParent_Done,
     /*  465060 */ // Label 7014: @465060
     /*  465060 */ GIM_Try, /*On fail goto*//*Label 7015*/ GIMT_Encode4(465126), // Rule ID 15902 //
     /*  465065 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  465068 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465071 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465082 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465089 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465092 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465114 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465124 */   GIR_RootConstrainSelectedInstOperands,
     /*  465125 */   // GIR_Coverage, 15902,
     /*  465125 */   GIR_EraseRootFromParent_Done,
     /*  465126 */ // Label 7015: @465126
     /*  465126 */ GIM_Try, /*On fail goto*//*Label 7016*/ GIMT_Encode4(465192), // Rule ID 15908 //
     /*  465131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  465134 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465148 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465155 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465158 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465180 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465183 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465186 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465190 */   GIR_RootConstrainSelectedInstOperands,
     /*  465191 */   // GIR_Coverage, 15908,
     /*  465191 */   GIR_EraseRootFromParent_Done,
     /*  465192 */ // Label 7016: @465192
     /*  465192 */ GIM_Try, /*On fail goto*//*Label 7017*/ GIMT_Encode4(465258), // Rule ID 15909 //
     /*  465197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  465200 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465203 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465210 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465214 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465221 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465224 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465231 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465252 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465256 */   GIR_RootConstrainSelectedInstOperands,
     /*  465257 */   // GIR_Coverage, 15909,
     /*  465257 */   GIR_EraseRootFromParent_Done,
     /*  465258 */ // Label 7017: @465258
     /*  465258 */ GIM_Try, /*On fail goto*//*Label 7018*/ GIMT_Encode4(465324), // Rule ID 15910 //
     /*  465263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  465266 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465276 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465280 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465287 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465287 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465290 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465312 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465322 */   GIR_RootConstrainSelectedInstOperands,
     /*  465323 */   // GIR_Coverage, 15910,
     /*  465323 */   GIR_EraseRootFromParent_Done,
     /*  465324 */ // Label 7018: @465324
     /*  465324 */ GIM_Try, /*On fail goto*//*Label 7019*/ GIMT_Encode4(465390), // Rule ID 15911 //
     /*  465329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  465332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465335 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465353 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465356 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465381 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465384 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465388 */   GIR_RootConstrainSelectedInstOperands,
     /*  465389 */   // GIR_Coverage, 15911,
     /*  465389 */   GIR_EraseRootFromParent_Done,
     /*  465390 */ // Label 7019: @465390
     /*  465390 */ GIM_Try, /*On fail goto*//*Label 7020*/ GIMT_Encode4(465456), // Rule ID 15912 //
     /*  465395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  465398 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465401 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465408 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465419 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465422 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465444 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465447 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465450 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465454 */   GIR_RootConstrainSelectedInstOperands,
     /*  465455 */   // GIR_Coverage, 15912,
     /*  465455 */   GIR_EraseRootFromParent_Done,
     /*  465456 */ // Label 7020: @465456
     /*  465456 */ GIM_Try, /*On fail goto*//*Label 7021*/ GIMT_Encode4(465522), // Rule ID 15918 //
     /*  465461 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  465464 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465467 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465474 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465478 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465485 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465488 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465505 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465510 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465513 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465516 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465520 */   GIR_RootConstrainSelectedInstOperands,
     /*  465521 */   // GIR_Coverage, 15918,
     /*  465521 */   GIR_EraseRootFromParent_Done,
     /*  465522 */ // Label 7021: @465522
     /*  465522 */ GIM_Try, /*On fail goto*//*Label 7022*/ GIMT_Encode4(465588), // Rule ID 15919 //
     /*  465527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  465530 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465533 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465540 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465544 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465551 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465551 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465554 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465579 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465582 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465586 */   GIR_RootConstrainSelectedInstOperands,
     /*  465587 */   // GIR_Coverage, 15919,
     /*  465587 */   GIR_EraseRootFromParent_Done,
     /*  465588 */ // Label 7022: @465588
     /*  465588 */ GIM_Try, /*On fail goto*//*Label 7023*/ GIMT_Encode4(465654), // Rule ID 15920 //
     /*  465593 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  465596 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465599 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465617 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465620 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465642 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465645 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465648 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465652 */   GIR_RootConstrainSelectedInstOperands,
     /*  465653 */   // GIR_Coverage, 15920,
     /*  465653 */   GIR_EraseRootFromParent_Done,
     /*  465654 */ // Label 7023: @465654
     /*  465654 */ GIM_Try, /*On fail goto*//*Label 7024*/ GIMT_Encode4(465720), // Rule ID 15921 //
     /*  465659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  465662 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465665 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465672 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465676 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465683 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465686 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465714 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465718 */   GIR_RootConstrainSelectedInstOperands,
     /*  465719 */   // GIR_Coverage, 15921,
     /*  465719 */   GIR_EraseRootFromParent_Done,
     /*  465720 */ // Label 7024: @465720
     /*  465720 */ GIM_Try, /*On fail goto*//*Label 7025*/ GIMT_Encode4(465786), // Rule ID 15922 //
     /*  465725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  465728 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465731 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465738 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465742 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465749 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  465752 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465777 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465780 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465784 */   GIR_RootConstrainSelectedInstOperands,
     /*  465785 */   // GIR_Coverage, 15922,
     /*  465785 */   GIR_EraseRootFromParent_Done,
     /*  465786 */ // Label 7025: @465786
     /*  465786 */ GIM_Try, /*On fail goto*//*Label 7026*/ GIMT_Encode4(465852), // Rule ID 15928 //
     /*  465791 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  465794 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465797 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465808 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465815 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465815 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465818 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465843 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465846 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465850 */   GIR_RootConstrainSelectedInstOperands,
     /*  465851 */   // GIR_Coverage, 15928,
     /*  465851 */   GIR_EraseRootFromParent_Done,
     /*  465852 */ // Label 7026: @465852
     /*  465852 */ GIM_Try, /*On fail goto*//*Label 7027*/ GIMT_Encode4(465918), // Rule ID 15929 //
     /*  465857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  465860 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465881 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465884 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465906 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465912 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465916 */   GIR_RootConstrainSelectedInstOperands,
     /*  465917 */   // GIR_Coverage, 15929,
     /*  465917 */   GIR_EraseRootFromParent_Done,
     /*  465918 */ // Label 7027: @465918
     /*  465918 */ GIM_Try, /*On fail goto*//*Label 7028*/ GIMT_Encode4(465984), // Rule ID 15930 //
     /*  465923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  465926 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  465936 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  465940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  465947 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  465947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  465950 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  465952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  465957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  465962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  465967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  465972 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  465978 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  465982 */   GIR_RootConstrainSelectedInstOperands,
     /*  465983 */   // GIR_Coverage, 15930,
     /*  465983 */   GIR_EraseRootFromParent_Done,
     /*  465984 */ // Label 7028: @465984
     /*  465984 */ GIM_Try, /*On fail goto*//*Label 7029*/ GIMT_Encode4(466050), // Rule ID 15931 //
     /*  465989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  465992 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  465995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  466002 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466006 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  466013 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  466013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  466016 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  466018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466038 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466044 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466048 */   GIR_RootConstrainSelectedInstOperands,
     /*  466049 */   // GIR_Coverage, 15931,
     /*  466049 */   GIR_EraseRootFromParent_Done,
     /*  466050 */ // Label 7029: @466050
     /*  466050 */ GIM_Try, /*On fail goto*//*Label 7030*/ GIMT_Encode4(466116), // Rule ID 15932 //
     /*  466055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  466058 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466061 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  466068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  466079 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  466079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  466082 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  466084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466104 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466107 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466110 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466114 */   GIR_RootConstrainSelectedInstOperands,
     /*  466115 */   // GIR_Coverage, 15932,
     /*  466115 */   GIR_EraseRootFromParent_Done,
     /*  466116 */ // Label 7030: @466116
     /*  466116 */ GIM_Try, /*On fail goto*//*Label 7031*/ GIMT_Encode4(466180), // Rule ID 25781 //
     /*  466121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  466124 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466136 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466143 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466146 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466168 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466178 */   GIR_RootConstrainSelectedInstOperands,
     /*  466179 */   // GIR_Coverage, 25781,
     /*  466179 */   GIR_EraseRootFromParent_Done,
     /*  466180 */ // Label 7031: @466180
     /*  466180 */ GIM_Try, /*On fail goto*//*Label 7032*/ GIMT_Encode4(466244), // Rule ID 25782 //
     /*  466185 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  466188 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466191 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466196 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466200 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466207 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466207 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466210 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466242 */   GIR_RootConstrainSelectedInstOperands,
     /*  466243 */   // GIR_Coverage, 25782,
     /*  466243 */   GIR_EraseRootFromParent_Done,
     /*  466244 */ // Label 7032: @466244
     /*  466244 */ GIM_Try, /*On fail goto*//*Label 7033*/ GIMT_Encode4(466308), // Rule ID 25783 //
     /*  466249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  466252 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466255 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466260 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466264 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466271 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466271 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466274 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466306 */   GIR_RootConstrainSelectedInstOperands,
     /*  466307 */   // GIR_Coverage, 25783,
     /*  466307 */   GIR_EraseRootFromParent_Done,
     /*  466308 */ // Label 7033: @466308
     /*  466308 */ GIM_Try, /*On fail goto*//*Label 7034*/ GIMT_Encode4(466372), // Rule ID 25784 //
     /*  466313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  466316 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466319 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466335 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466338 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466360 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466370 */   GIR_RootConstrainSelectedInstOperands,
     /*  466371 */   // GIR_Coverage, 25784,
     /*  466371 */   GIR_EraseRootFromParent_Done,
     /*  466372 */ // Label 7034: @466372
     /*  466372 */ GIM_Try, /*On fail goto*//*Label 7035*/ GIMT_Encode4(466436), // Rule ID 25785 //
     /*  466377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  466380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466388 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466392 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466399 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466399 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466402 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466434 */   GIR_RootConstrainSelectedInstOperands,
     /*  466435 */   // GIR_Coverage, 25785,
     /*  466435 */   GIR_EraseRootFromParent_Done,
     /*  466436 */ // Label 7035: @466436
     /*  466436 */ GIM_Try, /*On fail goto*//*Label 7036*/ GIMT_Encode4(466500), // Rule ID 25791 //
     /*  466441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  466444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466447 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466452 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466456 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466463 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  466466 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466488 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466498 */   GIR_RootConstrainSelectedInstOperands,
     /*  466499 */   // GIR_Coverage, 25791,
     /*  466499 */   GIR_EraseRootFromParent_Done,
     /*  466500 */ // Label 7036: @466500
     /*  466500 */ GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(466564), // Rule ID 25792 //
     /*  466505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  466508 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466511 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466516 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466520 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466527 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466527 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  466530 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466552 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466555 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466562 */   GIR_RootConstrainSelectedInstOperands,
     /*  466563 */   // GIR_Coverage, 25792,
     /*  466563 */   GIR_EraseRootFromParent_Done,
     /*  466564 */ // Label 7037: @466564
     /*  466564 */ GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(466628), // Rule ID 25793 //
     /*  466569 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  466572 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466575 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466591 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  466594 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466616 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466619 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466622 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466626 */   GIR_RootConstrainSelectedInstOperands,
     /*  466627 */   // GIR_Coverage, 25793,
     /*  466627 */   GIR_EraseRootFromParent_Done,
     /*  466628 */ // Label 7038: @466628
     /*  466628 */ GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(466692), // Rule ID 25794 //
     /*  466633 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  466636 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466639 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466644 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466648 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466655 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  466658 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466680 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466683 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466690 */   GIR_RootConstrainSelectedInstOperands,
     /*  466691 */   // GIR_Coverage, 25794,
     /*  466691 */   GIR_EraseRootFromParent_Done,
     /*  466692 */ // Label 7039: @466692
     /*  466692 */ GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(466756), // Rule ID 25795 //
     /*  466697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  466700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466719 */   // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  466722 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466744 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466747 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466750 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466754 */   GIR_RootConstrainSelectedInstOperands,
     /*  466755 */   // GIR_Coverage, 25795,
     /*  466755 */   GIR_EraseRootFromParent_Done,
     /*  466756 */ // Label 7040: @466756
     /*  466756 */ GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(466820), // Rule ID 25801 //
     /*  466761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  466764 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466772 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466776 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466783 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466786 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466808 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466814 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466818 */   GIR_RootConstrainSelectedInstOperands,
     /*  466819 */   // GIR_Coverage, 25801,
     /*  466819 */   GIR_EraseRootFromParent_Done,
     /*  466820 */ // Label 7041: @466820
     /*  466820 */ GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(466884), // Rule ID 25802 //
     /*  466825 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  466828 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466831 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466836 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466840 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466847 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466847 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466850 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466862 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466872 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466882 */   GIR_RootConstrainSelectedInstOperands,
     /*  466883 */   // GIR_Coverage, 25802,
     /*  466883 */   GIR_EraseRootFromParent_Done,
     /*  466884 */ // Label 7042: @466884
     /*  466884 */ GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(466948), // Rule ID 25803 //
     /*  466889 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  466892 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466895 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466900 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466904 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466911 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466911 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466914 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  466936 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  466942 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  466946 */   GIR_RootConstrainSelectedInstOperands,
     /*  466947 */   // GIR_Coverage, 25803,
     /*  466947 */   GIR_EraseRootFromParent_Done,
     /*  466948 */ // Label 7043: @466948
     /*  466948 */ GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(467012), // Rule ID 25804 //
     /*  466953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  466956 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  466959 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  466964 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  466968 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  466975 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  466975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  466978 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  466980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  466985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  466990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  466995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467000 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467006 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467010 */   GIR_RootConstrainSelectedInstOperands,
     /*  467011 */   // GIR_Coverage, 25804,
     /*  467011 */   GIR_EraseRootFromParent_Done,
     /*  467012 */ // Label 7044: @467012
     /*  467012 */ GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(467076), // Rule ID 25805 //
     /*  467017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  467020 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  467028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467032 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  467039 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  467039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  467042 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  467044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  467049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  467054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  467059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467070 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467074 */   GIR_RootConstrainSelectedInstOperands,
     /*  467075 */   // GIR_Coverage, 25805,
     /*  467075 */   GIR_EraseRootFromParent_Done,
     /*  467076 */ // Label 7045: @467076
     /*  467076 */ GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(467140), // Rule ID 25811 //
     /*  467081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  467084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  467092 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467096 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  467103 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  467103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  467106 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  467108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  467113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  467118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  467123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467128 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467134 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467138 */   GIR_RootConstrainSelectedInstOperands,
     /*  467139 */   // GIR_Coverage, 25811,
     /*  467139 */   GIR_EraseRootFromParent_Done,
     /*  467140 */ // Label 7046: @467140
     /*  467140 */ GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(467204), // Rule ID 25812 //
     /*  467145 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  467148 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467151 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  467156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  467167 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  467167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  467170 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  467172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  467177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  467182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  467187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467192 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467195 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467198 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467202 */   GIR_RootConstrainSelectedInstOperands,
     /*  467203 */   // GIR_Coverage, 25812,
     /*  467203 */   GIR_EraseRootFromParent_Done,
     /*  467204 */ // Label 7047: @467204
     /*  467204 */ GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(467268), // Rule ID 25813 //
     /*  467209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  467212 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467215 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  467220 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467224 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  467231 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  467231 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  467234 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  467236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  467241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  467246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  467251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467266 */   GIR_RootConstrainSelectedInstOperands,
     /*  467267 */   // GIR_Coverage, 25813,
     /*  467267 */   GIR_EraseRootFromParent_Done,
     /*  467268 */ // Label 7048: @467268
     /*  467268 */ GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(467332), // Rule ID 25814 //
     /*  467273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  467276 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  467284 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467288 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  467295 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  467295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  467298 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  467300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  467305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  467310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  467315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467326 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467330 */   GIR_RootConstrainSelectedInstOperands,
     /*  467331 */   // GIR_Coverage, 25814,
     /*  467331 */   GIR_EraseRootFromParent_Done,
     /*  467332 */ // Label 7049: @467332
     /*  467332 */ GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(467396), // Rule ID 25815 //
     /*  467337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  467340 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467343 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  467348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  467359 */   // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  467359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  467362 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  467364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  467369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  467374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  467379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  467384 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  467390 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  467394 */   GIR_RootConstrainSelectedInstOperands,
     /*  467395 */   // GIR_Coverage, 25815,
     /*  467395 */   GIR_EraseRootFromParent_Done,
     /*  467396 */ // Label 7050: @467396
     /*  467396 */ GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(467492), // Rule ID 12707 //
     /*  467401 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode0),
     /*  467404 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467407 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467411 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  467418 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  467425 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  467429 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  467433 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  467437 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  467441 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  467445 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467449 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  467451 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  467458 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  467458 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR),
     /*  467461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  467466 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  467470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  467475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  467480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  467485 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  467490 */   GIR_RootConstrainSelectedInstOperands,
     /*  467491 */   // GIR_Coverage, 12707,
     /*  467491 */   GIR_EraseRootFromParent_Done,
     /*  467492 */ // Label 7051: @467492
     /*  467492 */ GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(467588), // Rule ID 12708 //
     /*  467497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode1),
     /*  467500 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467503 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467507 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  467514 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  467521 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  467525 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  467529 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  467533 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  467537 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  467541 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467545 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  467547 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  467554 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  467554 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR),
     /*  467557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  467562 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  467566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  467571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  467576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  467581 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  467586 */   GIR_RootConstrainSelectedInstOperands,
     /*  467587 */   // GIR_Coverage, 12708,
     /*  467587 */   GIR_EraseRootFromParent_Done,
     /*  467588 */ // Label 7052: @467588
     /*  467588 */ GIM_Try, /*On fail goto*//*Label 7053*/ GIMT_Encode4(467684), // Rule ID 12709 //
     /*  467593 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode2),
     /*  467596 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467599 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467603 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  467610 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  467617 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  467621 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  467625 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  467629 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  467633 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  467637 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467641 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  467643 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  467650 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  467650 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR),
     /*  467653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  467658 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  467662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  467667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  467672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  467677 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  467682 */   GIR_RootConstrainSelectedInstOperands,
     /*  467683 */   // GIR_Coverage, 12709,
     /*  467683 */   GIR_EraseRootFromParent_Done,
     /*  467684 */ // Label 7053: @467684
     /*  467684 */ GIM_Try, /*On fail goto*//*Label 7054*/ GIMT_Encode4(467780), // Rule ID 12710 //
     /*  467689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode3),
     /*  467692 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467695 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467699 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  467706 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  467713 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  467717 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  467721 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  467725 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  467729 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  467733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467737 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  467739 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  467746 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  467746 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR),
     /*  467749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  467754 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  467758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  467763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  467768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  467773 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  467778 */   GIR_RootConstrainSelectedInstOperands,
     /*  467779 */   // GIR_Coverage, 12710,
     /*  467779 */   GIR_EraseRootFromParent_Done,
     /*  467780 */ // Label 7054: @467780
     /*  467780 */ GIM_Try, /*On fail goto*//*Label 7055*/ GIMT_Encode4(467876), // Rule ID 12711 //
     /*  467785 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode4),
     /*  467788 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467791 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467795 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  467802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  467809 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  467813 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  467817 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  467821 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  467825 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  467829 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467833 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  467835 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  467842 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  467842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR),
     /*  467845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  467850 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  467854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  467859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  467864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  467869 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  467874 */   GIR_RootConstrainSelectedInstOperands,
     /*  467875 */   // GIR_Coverage, 12711,
     /*  467875 */   GIR_EraseRootFromParent_Done,
     /*  467876 */ // Label 7055: @467876
     /*  467876 */ GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(467972), // Rule ID 12717 //
     /*  467881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode0),
     /*  467884 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467887 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467891 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  467898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  467905 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  467909 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  467913 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  467917 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  467921 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  467925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  467929 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  467931 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  467938 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  467938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR),
     /*  467941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  467946 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  467950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  467955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  467960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  467965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  467970 */   GIR_RootConstrainSelectedInstOperands,
     /*  467971 */   // GIR_Coverage, 12717,
     /*  467971 */   GIR_EraseRootFromParent_Done,
     /*  467972 */ // Label 7056: @467972
     /*  467972 */ GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(468068), // Rule ID 12718 //
     /*  467977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode1),
     /*  467980 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  467983 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  467987 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  467994 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468001 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  468005 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  468009 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  468013 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  468017 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  468021 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468025 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  468027 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  468034 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  468034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR),
     /*  468037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  468042 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  468046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  468051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  468061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  468066 */   GIR_RootConstrainSelectedInstOperands,
     /*  468067 */   // GIR_Coverage, 12718,
     /*  468067 */   GIR_EraseRootFromParent_Done,
     /*  468068 */ // Label 7057: @468068
     /*  468068 */ GIM_Try, /*On fail goto*//*Label 7058*/ GIMT_Encode4(468164), // Rule ID 12719 //
     /*  468073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode2),
     /*  468076 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468079 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468083 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468090 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468097 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  468101 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  468105 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  468109 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  468113 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  468117 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468121 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  468123 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  468130 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  468130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR),
     /*  468133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  468138 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  468142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  468147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  468157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  468162 */   GIR_RootConstrainSelectedInstOperands,
     /*  468163 */   // GIR_Coverage, 12719,
     /*  468163 */   GIR_EraseRootFromParent_Done,
     /*  468164 */ // Label 7058: @468164
     /*  468164 */ GIM_Try, /*On fail goto*//*Label 7059*/ GIMT_Encode4(468260), // Rule ID 12720 //
     /*  468169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode3),
     /*  468172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468175 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468179 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468186 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468193 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  468197 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  468201 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  468205 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  468209 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  468213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468217 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  468219 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  468226 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  468226 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR),
     /*  468229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  468234 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  468238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  468243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  468253 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  468258 */   GIR_RootConstrainSelectedInstOperands,
     /*  468259 */   // GIR_Coverage, 12720,
     /*  468259 */   GIR_EraseRootFromParent_Done,
     /*  468260 */ // Label 7059: @468260
     /*  468260 */ GIM_Try, /*On fail goto*//*Label 7060*/ GIMT_Encode4(468356), // Rule ID 12721 //
     /*  468265 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode4),
     /*  468268 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468271 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468275 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468282 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468289 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  468293 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  468297 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  468301 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  468305 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  468309 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468313 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  468315 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  468322 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  468322 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR),
     /*  468325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  468330 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  468334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  468339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  468349 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  468354 */   GIR_RootConstrainSelectedInstOperands,
     /*  468355 */   // GIR_Coverage, 12721,
     /*  468355 */   GIR_EraseRootFromParent_Done,
     /*  468356 */ // Label 7060: @468356
     /*  468356 */ GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(468428), // Rule ID 15043 //
     /*  468361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  468364 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468367 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468371 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468378 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468396 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  468399 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468416 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468422 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468426 */   GIR_RootConstrainSelectedInstOperands,
     /*  468427 */   // GIR_Coverage, 15043,
     /*  468427 */   GIR_EraseRootFromParent_Done,
     /*  468428 */ // Label 7061: @468428
     /*  468428 */ GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(468500), // Rule ID 15044 //
     /*  468433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  468436 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468439 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468443 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468457 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468461 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468468 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468468 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  468471 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468488 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468498 */   GIR_RootConstrainSelectedInstOperands,
     /*  468499 */   // GIR_Coverage, 15044,
     /*  468499 */   GIR_EraseRootFromParent_Done,
     /*  468500 */ // Label 7062: @468500
     /*  468500 */ GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(468572), // Rule ID 15045 //
     /*  468505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  468508 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468511 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468515 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468522 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468540 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  468543 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468560 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468563 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468566 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468570 */   GIR_RootConstrainSelectedInstOperands,
     /*  468571 */   // GIR_Coverage, 15045,
     /*  468571 */   GIR_EraseRootFromParent_Done,
     /*  468572 */ // Label 7063: @468572
     /*  468572 */ GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(468644), // Rule ID 15046 //
     /*  468577 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  468580 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468583 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468587 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468594 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468601 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468605 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468612 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468612 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  468615 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468635 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468638 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468642 */   GIR_RootConstrainSelectedInstOperands,
     /*  468643 */   // GIR_Coverage, 15046,
     /*  468643 */   GIR_EraseRootFromParent_Done,
     /*  468644 */ // Label 7064: @468644
     /*  468644 */ GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(468716), // Rule ID 15047 //
     /*  468649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  468652 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468655 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468659 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468666 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468673 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468677 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468684 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
     /*  468687 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468704 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468707 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468710 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468714 */   GIR_RootConstrainSelectedInstOperands,
     /*  468715 */   // GIR_Coverage, 15047,
     /*  468715 */   GIR_EraseRootFromParent_Done,
     /*  468716 */ // Label 7065: @468716
     /*  468716 */ GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(468788), // Rule ID 15863 //
     /*  468721 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  468724 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468727 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468731 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468738 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468745 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468749 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468756 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468756 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  468759 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468779 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468782 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468786 */   GIR_RootConstrainSelectedInstOperands,
     /*  468787 */   // GIR_Coverage, 15863,
     /*  468787 */   GIR_EraseRootFromParent_Done,
     /*  468788 */ // Label 7066: @468788
     /*  468788 */ GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(468860), // Rule ID 15864 //
     /*  468793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  468796 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468799 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468803 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468810 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468817 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468821 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468828 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  468831 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468838 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468851 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468854 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468858 */   GIR_RootConstrainSelectedInstOperands,
     /*  468859 */   // GIR_Coverage, 15864,
     /*  468859 */   GIR_EraseRootFromParent_Done,
     /*  468860 */ // Label 7067: @468860
     /*  468860 */ GIM_Try, /*On fail goto*//*Label 7068*/ GIMT_Encode4(468932), // Rule ID 15865 //
     /*  468865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  468868 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468871 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468875 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468882 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468889 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468893 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468900 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  468903 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468905 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468920 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468923 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468926 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  468930 */   GIR_RootConstrainSelectedInstOperands,
     /*  468931 */   // GIR_Coverage, 15865,
     /*  468931 */   GIR_EraseRootFromParent_Done,
     /*  468932 */ // Label 7068: @468932
     /*  468932 */ GIM_Try, /*On fail goto*//*Label 7069*/ GIMT_Encode4(469004), // Rule ID 15866 //
     /*  468937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  468940 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  468943 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  468947 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  468954 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  468961 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  468965 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  468972 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  468972 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  468975 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  468977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  468982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  468987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  468992 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  468998 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469002 */   GIR_RootConstrainSelectedInstOperands,
     /*  469003 */   // GIR_Coverage, 15866,
     /*  469003 */   GIR_EraseRootFromParent_Done,
     /*  469004 */ // Label 7069: @469004
     /*  469004 */ GIM_Try, /*On fail goto*//*Label 7070*/ GIMT_Encode4(469076), // Rule ID 15867 //
     /*  469009 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  469012 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469015 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469019 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  469026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469033 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469037 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469044 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469044 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
     /*  469047 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469070 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469074 */   GIR_RootConstrainSelectedInstOperands,
     /*  469075 */   // GIR_Coverage, 15867,
     /*  469075 */   GIR_EraseRootFromParent_Done,
     /*  469076 */ // Label 7070: @469076
     /*  469076 */ GIM_Try, /*On fail goto*//*Label 7071*/ GIMT_Encode4(469148), // Rule ID 15873 //
     /*  469081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  469084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469087 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469091 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469098 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469116 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  469119 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469146 */   GIR_RootConstrainSelectedInstOperands,
     /*  469147 */   // GIR_Coverage, 15873,
     /*  469147 */   GIR_EraseRootFromParent_Done,
     /*  469148 */ // Label 7071: @469148
     /*  469148 */ GIM_Try, /*On fail goto*//*Label 7072*/ GIMT_Encode4(469220), // Rule ID 15874 //
     /*  469153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  469156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469159 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469163 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469170 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469177 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469181 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469188 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469188 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  469191 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469208 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469214 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469218 */   GIR_RootConstrainSelectedInstOperands,
     /*  469219 */   // GIR_Coverage, 15874,
     /*  469219 */   GIR_EraseRootFromParent_Done,
     /*  469220 */ // Label 7072: @469220
     /*  469220 */ GIM_Try, /*On fail goto*//*Label 7073*/ GIMT_Encode4(469292), // Rule ID 15875 //
     /*  469225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  469228 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469231 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469235 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469242 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469249 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469253 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469260 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469260 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  469263 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469265 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469280 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469283 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469286 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469290 */   GIR_RootConstrainSelectedInstOperands,
     /*  469291 */   // GIR_Coverage, 15875,
     /*  469291 */   GIR_EraseRootFromParent_Done,
     /*  469292 */ // Label 7073: @469292
     /*  469292 */ GIM_Try, /*On fail goto*//*Label 7074*/ GIMT_Encode4(469364), // Rule ID 15876 //
     /*  469297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  469300 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469303 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469307 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469314 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469321 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469325 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469332 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469332 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  469335 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469342 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469352 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469355 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469358 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469362 */   GIR_RootConstrainSelectedInstOperands,
     /*  469363 */   // GIR_Coverage, 15876,
     /*  469363 */   GIR_EraseRootFromParent_Done,
     /*  469364 */ // Label 7074: @469364
     /*  469364 */ GIM_Try, /*On fail goto*//*Label 7075*/ GIMT_Encode4(469436), // Rule ID 15877 //
     /*  469369 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  469372 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469375 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469379 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469386 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469393 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469397 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469404 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
     /*  469407 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469419 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469424 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469434 */   GIR_RootConstrainSelectedInstOperands,
     /*  469435 */   // GIR_Coverage, 15877,
     /*  469435 */   GIR_EraseRootFromParent_Done,
     /*  469436 */ // Label 7075: @469436
     /*  469436 */ GIM_Try, /*On fail goto*//*Label 7076*/ GIMT_Encode4(469508), // Rule ID 15883 //
     /*  469441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  469444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469447 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469451 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469458 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469476 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  469479 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469496 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469499 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469502 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469506 */   GIR_RootConstrainSelectedInstOperands,
     /*  469507 */   // GIR_Coverage, 15883,
     /*  469507 */   GIR_EraseRootFromParent_Done,
     /*  469508 */ // Label 7076: @469508
     /*  469508 */ GIM_Try, /*On fail goto*//*Label 7077*/ GIMT_Encode4(469580), // Rule ID 15884 //
     /*  469513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  469516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469519 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469523 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469530 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469537 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469541 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469548 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  469551 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469568 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469571 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469574 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469578 */   GIR_RootConstrainSelectedInstOperands,
     /*  469579 */   // GIR_Coverage, 15884,
     /*  469579 */   GIR_EraseRootFromParent_Done,
     /*  469580 */ // Label 7077: @469580
     /*  469580 */ GIM_Try, /*On fail goto*//*Label 7078*/ GIMT_Encode4(469652), // Rule ID 15885 //
     /*  469585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  469588 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469591 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469595 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469602 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469609 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469613 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469620 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469620 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  469623 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469640 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469643 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469646 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469650 */   GIR_RootConstrainSelectedInstOperands,
     /*  469651 */   // GIR_Coverage, 15885,
     /*  469651 */   GIR_EraseRootFromParent_Done,
     /*  469652 */ // Label 7078: @469652
     /*  469652 */ GIM_Try, /*On fail goto*//*Label 7079*/ GIMT_Encode4(469724), // Rule ID 15886 //
     /*  469657 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  469660 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469663 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469667 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469674 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469681 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469685 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469692 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469692 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  469695 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469715 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469718 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469722 */   GIR_RootConstrainSelectedInstOperands,
     /*  469723 */   // GIR_Coverage, 15886,
     /*  469723 */   GIR_EraseRootFromParent_Done,
     /*  469724 */ // Label 7079: @469724
     /*  469724 */ GIM_Try, /*On fail goto*//*Label 7080*/ GIMT_Encode4(469796), // Rule ID 15887 //
     /*  469729 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  469732 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469735 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  469739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  469746 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469753 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469757 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469764 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
     /*  469767 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469784 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469787 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469790 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469794 */   GIR_RootConstrainSelectedInstOperands,
     /*  469795 */   // GIR_Coverage, 15887,
     /*  469795 */   GIR_EraseRootFromParent_Done,
     /*  469796 */ // Label 7080: @469796
     /*  469796 */ GIM_Try, /*On fail goto*//*Label 7081*/ GIMT_Encode4(469857), // Rule ID 15893 //
     /*  469801 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  469804 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469807 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469825 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  469828 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469845 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469855 */   GIR_RootConstrainSelectedInstOperands,
     /*  469856 */   // GIR_Coverage, 15893,
     /*  469856 */   GIR_EraseRootFromParent_Done,
     /*  469857 */ // Label 7081: @469857
     /*  469857 */ GIM_Try, /*On fail goto*//*Label 7082*/ GIMT_Encode4(469918), // Rule ID 15894 //
     /*  469862 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  469865 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469868 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469875 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469879 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469886 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  469889 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469906 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469912 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469916 */   GIR_RootConstrainSelectedInstOperands,
     /*  469917 */   // GIR_Coverage, 15894,
     /*  469917 */   GIR_EraseRootFromParent_Done,
     /*  469918 */ // Label 7082: @469918
     /*  469918 */ GIM_Try, /*On fail goto*//*Label 7083*/ GIMT_Encode4(469979), // Rule ID 15895 //
     /*  469923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  469926 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469936 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  469940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  469947 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  469947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  469950 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  469952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  469957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  469962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  469967 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469970 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  469973 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  469977 */   GIR_RootConstrainSelectedInstOperands,
     /*  469978 */   // GIR_Coverage, 15895,
     /*  469978 */   GIR_EraseRootFromParent_Done,
     /*  469979 */ // Label 7083: @469979
     /*  469979 */ GIM_Try, /*On fail goto*//*Label 7084*/ GIMT_Encode4(470040), // Rule ID 15896 //
     /*  469984 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  469987 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  469990 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  469997 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470001 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470008 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470008 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470011 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470038 */   GIR_RootConstrainSelectedInstOperands,
     /*  470039 */   // GIR_Coverage, 15896,
     /*  470039 */   GIR_EraseRootFromParent_Done,
     /*  470040 */ // Label 7084: @470040
     /*  470040 */ GIM_Try, /*On fail goto*//*Label 7085*/ GIMT_Encode4(470101), // Rule ID 15897 //
     /*  470045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  470048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470051 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470062 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470069 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470069 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470072 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470092 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470095 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470099 */   GIR_RootConstrainSelectedInstOperands,
     /*  470100 */   // GIR_Coverage, 15897,
     /*  470100 */   GIR_EraseRootFromParent_Done,
     /*  470101 */ // Label 7085: @470101
     /*  470101 */ GIM_Try, /*On fail goto*//*Label 7086*/ GIMT_Encode4(470162), // Rule ID 15903 //
     /*  470106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  470109 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470112 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470123 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470130 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470133 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470150 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470153 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470156 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470160 */   GIR_RootConstrainSelectedInstOperands,
     /*  470161 */   // GIR_Coverage, 15903,
     /*  470161 */   GIR_EraseRootFromParent_Done,
     /*  470162 */ // Label 7086: @470162
     /*  470162 */ GIM_Try, /*On fail goto*//*Label 7087*/ GIMT_Encode4(470223), // Rule ID 15904 //
     /*  470167 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  470170 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470173 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470191 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470194 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470211 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470217 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470221 */   GIR_RootConstrainSelectedInstOperands,
     /*  470222 */   // GIR_Coverage, 15904,
     /*  470222 */   GIR_EraseRootFromParent_Done,
     /*  470223 */ // Label 7087: @470223
     /*  470223 */ GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(470284), // Rule ID 15905 //
     /*  470228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  470231 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470234 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470245 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470252 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470255 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470278 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470282 */   GIR_RootConstrainSelectedInstOperands,
     /*  470283 */   // GIR_Coverage, 15905,
     /*  470283 */   GIR_EraseRootFromParent_Done,
     /*  470284 */ // Label 7088: @470284
     /*  470284 */ GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(470345), // Rule ID 15906 //
     /*  470289 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  470292 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470313 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470316 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470333 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470339 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470343 */   GIR_RootConstrainSelectedInstOperands,
     /*  470344 */   // GIR_Coverage, 15906,
     /*  470344 */   GIR_EraseRootFromParent_Done,
     /*  470345 */ // Label 7089: @470345
     /*  470345 */ GIM_Try, /*On fail goto*//*Label 7090*/ GIMT_Encode4(470406), // Rule ID 15907 //
     /*  470350 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  470353 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470356 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470367 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470374 */   // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470377 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470394 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470397 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470400 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470404 */   GIR_RootConstrainSelectedInstOperands,
     /*  470405 */   // GIR_Coverage, 15907,
     /*  470405 */   GIR_EraseRootFromParent_Done,
     /*  470406 */ // Label 7090: @470406
     /*  470406 */ GIM_Try, /*On fail goto*//*Label 7091*/ GIMT_Encode4(470467), // Rule ID 15913 //
     /*  470411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  470414 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470424 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470428 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470435 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470435 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470438 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470440 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470455 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470458 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470461 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470465 */   GIR_RootConstrainSelectedInstOperands,
     /*  470466 */   // GIR_Coverage, 15913,
     /*  470466 */   GIR_EraseRootFromParent_Done,
     /*  470467 */ // Label 7091: @470467
     /*  470467 */ GIM_Try, /*On fail goto*//*Label 7092*/ GIMT_Encode4(470528), // Rule ID 15914 //
     /*  470472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  470475 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470478 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470485 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470489 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470496 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470496 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470499 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470516 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470519 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470522 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470526 */   GIR_RootConstrainSelectedInstOperands,
     /*  470527 */   // GIR_Coverage, 15914,
     /*  470527 */   GIR_EraseRootFromParent_Done,
     /*  470528 */ // Label 7092: @470528
     /*  470528 */ GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(470589), // Rule ID 15915 //
     /*  470533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  470536 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470539 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470546 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470550 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470557 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470557 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470560 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470572 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470577 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470580 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470583 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470587 */   GIR_RootConstrainSelectedInstOperands,
     /*  470588 */   // GIR_Coverage, 15915,
     /*  470588 */   GIR_EraseRootFromParent_Done,
     /*  470589 */ // Label 7093: @470589
     /*  470589 */ GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(470650), // Rule ID 15916 //
     /*  470594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  470597 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470600 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470607 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470611 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470618 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470621 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470638 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470641 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470648 */   GIR_RootConstrainSelectedInstOperands,
     /*  470649 */   // GIR_Coverage, 15916,
     /*  470649 */   GIR_EraseRootFromParent_Done,
     /*  470650 */ // Label 7094: @470650
     /*  470650 */ GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(470711), // Rule ID 15917 //
     /*  470655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  470658 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470661 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470668 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470672 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470679 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  470682 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470699 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470702 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470705 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470709 */   GIR_RootConstrainSelectedInstOperands,
     /*  470710 */   // GIR_Coverage, 15917,
     /*  470710 */   GIR_EraseRootFromParent_Done,
     /*  470711 */ // Label 7095: @470711
     /*  470711 */ GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(470772), // Rule ID 15923 //
     /*  470716 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  470719 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470722 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470740 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470743 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470760 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470763 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470766 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470770 */   GIR_RootConstrainSelectedInstOperands,
     /*  470771 */   // GIR_Coverage, 15923,
     /*  470771 */   GIR_EraseRootFromParent_Done,
     /*  470772 */ // Label 7096: @470772
     /*  470772 */ GIM_Try, /*On fail goto*//*Label 7097*/ GIMT_Encode4(470833), // Rule ID 15924 //
     /*  470777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  470780 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470790 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470801 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470804 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470821 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470831 */   GIR_RootConstrainSelectedInstOperands,
     /*  470832 */   // GIR_Coverage, 15924,
     /*  470832 */   GIR_EraseRootFromParent_Done,
     /*  470833 */ // Label 7097: @470833
     /*  470833 */ GIM_Try, /*On fail goto*//*Label 7098*/ GIMT_Encode4(470894), // Rule ID 15925 //
     /*  470838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  470841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470855 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470862 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470865 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470885 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470888 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470892 */   GIR_RootConstrainSelectedInstOperands,
     /*  470893 */   // GIR_Coverage, 15925,
     /*  470893 */   GIR_EraseRootFromParent_Done,
     /*  470894 */ // Label 7098: @470894
     /*  470894 */ GIM_Try, /*On fail goto*//*Label 7099*/ GIMT_Encode4(470955), // Rule ID 15926 //
     /*  470899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  470902 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470905 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470912 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470916 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470923 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470926 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  470943 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470946 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  470949 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  470953 */   GIR_RootConstrainSelectedInstOperands,
     /*  470954 */   // GIR_Coverage, 15926,
     /*  470954 */   GIR_EraseRootFromParent_Done,
     /*  470955 */ // Label 7099: @470955
     /*  470955 */ GIM_Try, /*On fail goto*//*Label 7100*/ GIMT_Encode4(471016), // Rule ID 15927 //
     /*  470960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  470963 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  470966 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  470973 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  470977 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  470984 */   // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  470984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  470987 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  470989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  470994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  470999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  471004 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471007 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471010 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  471014 */   GIR_RootConstrainSelectedInstOperands,
     /*  471015 */   // GIR_Coverage, 15927,
     /*  471015 */   GIR_EraseRootFromParent_Done,
     /*  471016 */ // Label 7100: @471016
     /*  471016 */ GIM_Try, /*On fail goto*//*Label 7101*/ GIMT_Encode4(471105), // Rule ID 12702 //
     /*  471021 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode0),
     /*  471024 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471027 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471031 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  471038 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471045 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471049 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471053 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471057 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471061 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471065 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471069 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471071 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471078 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471078 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI),
     /*  471081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471086 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471095 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471098 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471103 */   GIR_RootConstrainSelectedInstOperands,
     /*  471104 */   // GIR_Coverage, 12702,
     /*  471104 */   GIR_EraseRootFromParent_Done,
     /*  471105 */ // Label 7101: @471105
     /*  471105 */ GIM_Try, /*On fail goto*//*Label 7102*/ GIMT_Encode4(471194), // Rule ID 12703 //
     /*  471110 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode1),
     /*  471113 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471116 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471120 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  471127 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471134 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471138 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471142 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471146 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471150 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471158 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471167 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI),
     /*  471170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471175 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471192 */   GIR_RootConstrainSelectedInstOperands,
     /*  471193 */   // GIR_Coverage, 12703,
     /*  471193 */   GIR_EraseRootFromParent_Done,
     /*  471194 */ // Label 7102: @471194
     /*  471194 */ GIM_Try, /*On fail goto*//*Label 7103*/ GIMT_Encode4(471283), // Rule ID 12704 //
     /*  471199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode2),
     /*  471202 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471205 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  471216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471223 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471227 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471231 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471235 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471239 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471247 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471249 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471256 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI),
     /*  471259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471264 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471273 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471276 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471281 */   GIR_RootConstrainSelectedInstOperands,
     /*  471282 */   // GIR_Coverage, 12704,
     /*  471282 */   GIR_EraseRootFromParent_Done,
     /*  471283 */ // Label 7103: @471283
     /*  471283 */ GIM_Try, /*On fail goto*//*Label 7104*/ GIMT_Encode4(471372), // Rule ID 12705 //
     /*  471288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode3),
     /*  471291 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471294 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471298 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  471305 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471312 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471316 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471320 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471324 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471328 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471336 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471338 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471345 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471345 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI),
     /*  471348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471353 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471362 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471365 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471370 */   GIR_RootConstrainSelectedInstOperands,
     /*  471371 */   // GIR_Coverage, 12705,
     /*  471371 */   GIR_EraseRootFromParent_Done,
     /*  471372 */ // Label 7104: @471372
     /*  471372 */ GIM_Try, /*On fail goto*//*Label 7105*/ GIMT_Encode4(471461), // Rule ID 12706 //
     /*  471377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode4),
     /*  471380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471383 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471387 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  471394 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471401 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471405 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471409 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471413 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471417 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471421 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471425 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471434 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI),
     /*  471437 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471442 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471451 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471454 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471459 */   GIR_RootConstrainSelectedInstOperands,
     /*  471460 */   // GIR_Coverage, 12706,
     /*  471460 */   GIR_EraseRootFromParent_Done,
     /*  471461 */ // Label 7105: @471461
     /*  471461 */ GIM_Try, /*On fail goto*//*Label 7106*/ GIMT_Encode4(471550), // Rule ID 12712 //
     /*  471466 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode0),
     /*  471469 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471472 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471476 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  471483 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471490 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471494 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471498 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471502 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471506 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471514 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471516 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471523 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI),
     /*  471526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471531 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471548 */   GIR_RootConstrainSelectedInstOperands,
     /*  471549 */   // GIR_Coverage, 12712,
     /*  471549 */   GIR_EraseRootFromParent_Done,
     /*  471550 */ // Label 7106: @471550
     /*  471550 */ GIM_Try, /*On fail goto*//*Label 7107*/ GIMT_Encode4(471639), // Rule ID 12713 //
     /*  471555 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode1),
     /*  471558 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471561 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471565 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  471572 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471579 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471583 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471587 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471591 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471595 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471599 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471603 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471605 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471612 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471612 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI),
     /*  471615 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471620 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471629 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471632 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471637 */   GIR_RootConstrainSelectedInstOperands,
     /*  471638 */   // GIR_Coverage, 12713,
     /*  471638 */   GIR_EraseRootFromParent_Done,
     /*  471639 */ // Label 7107: @471639
     /*  471639 */ GIM_Try, /*On fail goto*//*Label 7108*/ GIMT_Encode4(471728), // Rule ID 12714 //
     /*  471644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode2),
     /*  471647 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471650 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471654 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  471661 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471668 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471672 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471676 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471680 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471684 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471688 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471692 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471694 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471701 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI),
     /*  471704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471709 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471718 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471721 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471726 */   GIR_RootConstrainSelectedInstOperands,
     /*  471727 */   // GIR_Coverage, 12714,
     /*  471727 */   GIR_EraseRootFromParent_Done,
     /*  471728 */ // Label 7108: @471728
     /*  471728 */ GIM_Try, /*On fail goto*//*Label 7109*/ GIMT_Encode4(471817), // Rule ID 12715 //
     /*  471733 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode3),
     /*  471736 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471739 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471743 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  471750 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471757 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471761 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471765 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471769 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471773 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471777 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471781 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471783 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471790 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI),
     /*  471793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471798 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471807 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471810 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471815 */   GIR_RootConstrainSelectedInstOperands,
     /*  471816 */   // GIR_Coverage, 12715,
     /*  471816 */   GIR_EraseRootFromParent_Done,
     /*  471817 */ // Label 7109: @471817
     /*  471817 */ GIM_Try, /*On fail goto*//*Label 7110*/ GIMT_Encode4(471906), // Rule ID 12716 //
     /*  471822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGlobalInsts_HwMode4),
     /*  471825 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471828 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471832 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  471839 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  471846 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471850 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471854 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471858 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471862 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471866 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471870 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471872 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  471879 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  471879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI),
     /*  471882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  471887 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  471896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  471899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471904 */   GIR_RootConstrainSelectedInstOperands,
     /*  471905 */   // GIR_Coverage, 12716,
     /*  471905 */   GIR_EraseRootFromParent_Done,
     /*  471906 */ // Label 7110: @471906
     /*  471906 */ GIM_Try, /*On fail goto*//*Label 7111*/ GIMT_Encode4(472001), // Rule ID 11607 //
     /*  471911 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode0),
     /*  471914 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  471917 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  471921 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  471928 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  471934 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  471938 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  471942 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  471946 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  471950 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  471954 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  471958 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  471960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  471967 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  471967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR),
     /*  471970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  471975 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  471979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  471984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  471989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  471994 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  471999 */   GIR_RootConstrainSelectedInstOperands,
     /*  472000 */   // GIR_Coverage, 11607,
     /*  472000 */   GIR_EraseRootFromParent_Done,
     /*  472001 */ // Label 7111: @472001
     /*  472001 */ GIM_Try, /*On fail goto*//*Label 7112*/ GIMT_Encode4(472096), // Rule ID 11608 //
     /*  472006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode1),
     /*  472009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472012 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  472023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472029 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472033 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472037 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472041 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472045 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472049 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472053 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472062 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR),
     /*  472065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472070 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472079 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472094 */   GIR_RootConstrainSelectedInstOperands,
     /*  472095 */   // GIR_Coverage, 11608,
     /*  472095 */   GIR_EraseRootFromParent_Done,
     /*  472096 */ // Label 7112: @472096
     /*  472096 */ GIM_Try, /*On fail goto*//*Label 7113*/ GIMT_Encode4(472191), // Rule ID 11609 //
     /*  472101 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode2),
     /*  472104 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472107 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472111 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  472118 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472124 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472128 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472132 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472136 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472140 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472148 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472150 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472157 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR),
     /*  472160 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472165 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472184 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472189 */   GIR_RootConstrainSelectedInstOperands,
     /*  472190 */   // GIR_Coverage, 11609,
     /*  472190 */   GIR_EraseRootFromParent_Done,
     /*  472191 */ // Label 7113: @472191
     /*  472191 */ GIM_Try, /*On fail goto*//*Label 7114*/ GIMT_Encode4(472286), // Rule ID 11610 //
     /*  472196 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode3),
     /*  472199 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472202 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472206 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  472213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472219 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472223 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472227 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472231 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472235 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472239 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472243 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472245 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472252 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR),
     /*  472255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472260 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472274 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472284 */   GIR_RootConstrainSelectedInstOperands,
     /*  472285 */   // GIR_Coverage, 11610,
     /*  472285 */   GIR_EraseRootFromParent_Done,
     /*  472286 */ // Label 7114: @472286
     /*  472286 */ GIM_Try, /*On fail goto*//*Label 7115*/ GIMT_Encode4(472381), // Rule ID 11611 //
     /*  472291 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode4),
     /*  472294 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472297 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472301 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  472308 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472314 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472318 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472322 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472326 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472330 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472334 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472338 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472340 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472347 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI_SADDR),
     /*  472350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472355 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472359 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472374 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472379 */   GIR_RootConstrainSelectedInstOperands,
     /*  472380 */   // GIR_Coverage, 11611,
     /*  472380 */   GIR_EraseRootFromParent_Done,
     /*  472381 */ // Label 7115: @472381
     /*  472381 */ GIM_Try, /*On fail goto*//*Label 7116*/ GIMT_Encode4(472476), // Rule ID 11617 //
     /*  472386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode0),
     /*  472389 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472392 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472396 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472403 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472409 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472413 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472417 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472421 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472425 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472429 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472433 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472435 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472442 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472442 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR),
     /*  472445 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472450 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472469 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472474 */   GIR_RootConstrainSelectedInstOperands,
     /*  472475 */   // GIR_Coverage, 11617,
     /*  472475 */   GIR_EraseRootFromParent_Done,
     /*  472476 */ // Label 7116: @472476
     /*  472476 */ GIM_Try, /*On fail goto*//*Label 7117*/ GIMT_Encode4(472571), // Rule ID 11618 //
     /*  472481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode1),
     /*  472484 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472487 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472491 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472498 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472504 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472508 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472512 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472516 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472520 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472528 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472530 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472537 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR),
     /*  472540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472545 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472564 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472569 */   GIR_RootConstrainSelectedInstOperands,
     /*  472570 */   // GIR_Coverage, 11618,
     /*  472570 */   GIR_EraseRootFromParent_Done,
     /*  472571 */ // Label 7117: @472571
     /*  472571 */ GIM_Try, /*On fail goto*//*Label 7118*/ GIMT_Encode4(472666), // Rule ID 11619 //
     /*  472576 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode2),
     /*  472579 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472582 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472586 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472593 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472599 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472603 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472607 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472611 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472615 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472619 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472623 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472625 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472632 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472632 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR),
     /*  472635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472640 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472659 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472664 */   GIR_RootConstrainSelectedInstOperands,
     /*  472665 */   // GIR_Coverage, 11619,
     /*  472665 */   GIR_EraseRootFromParent_Done,
     /*  472666 */ // Label 7118: @472666
     /*  472666 */ GIM_Try, /*On fail goto*//*Label 7119*/ GIMT_Encode4(472761), // Rule ID 11620 //
     /*  472671 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode3),
     /*  472674 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472677 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472681 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472688 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472694 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472698 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472702 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472706 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472710 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472714 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472718 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472720 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472727 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR),
     /*  472730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472735 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472754 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472759 */   GIR_RootConstrainSelectedInstOperands,
     /*  472760 */   // GIR_Coverage, 11620,
     /*  472760 */   GIR_EraseRootFromParent_Done,
     /*  472761 */ // Label 7119: @472761
     /*  472761 */ GIM_Try, /*On fail goto*//*Label 7120*/ GIMT_Encode4(472856), // Rule ID 11621 //
     /*  472766 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HasFlatGVSMode_HwMode4),
     /*  472769 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  472772 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  472776 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  472789 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  472793 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  472797 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  472801 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  472805 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  472809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472813 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  472815 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  472822 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  472822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI_SADDR),
     /*  472825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  472830 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  472834 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  472839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  472844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  472849 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  472854 */   GIR_RootConstrainSelectedInstOperands,
     /*  472855 */   // GIR_Coverage, 11621,
     /*  472855 */   GIR_EraseRootFromParent_Done,
     /*  472856 */ // Label 7120: @472856
     /*  472856 */ GIM_Try, /*On fail goto*//*Label 7121*/ GIMT_Encode4(472914), // Rule ID 29314 //
     /*  472861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  472864 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  472867 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472874 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  472879 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472883 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  472890 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  472890 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  472893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  472898 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  472900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  472905 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  472908 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  472912 */   GIR_RootConstrainSelectedInstOperands,
     /*  472913 */   // GIR_Coverage, 29314,
     /*  472913 */   GIR_EraseRootFromParent_Done,
     /*  472914 */ // Label 7121: @472914
     /*  472914 */ GIM_Try, /*On fail goto*//*Label 7122*/ GIMT_Encode4(472972), // Rule ID 29315 //
     /*  472919 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  472922 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  472925 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472932 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  472937 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472941 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  472948 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  472948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  472951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  472956 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  472958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  472963 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  472966 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  472970 */   GIR_RootConstrainSelectedInstOperands,
     /*  472971 */   // GIR_Coverage, 29315,
     /*  472971 */   GIR_EraseRootFromParent_Done,
     /*  472972 */ // Label 7122: @472972
     /*  472972 */ GIM_Try, /*On fail goto*//*Label 7123*/ GIMT_Encode4(473030), // Rule ID 29316 //
     /*  472977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  472980 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  472983 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  472990 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  472995 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  472999 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473006 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473006 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  473009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473014 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473021 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473024 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473028 */   GIR_RootConstrainSelectedInstOperands,
     /*  473029 */   // GIR_Coverage, 29316,
     /*  473029 */   GIR_EraseRootFromParent_Done,
     /*  473030 */ // Label 7123: @473030
     /*  473030 */ GIM_Try, /*On fail goto*//*Label 7124*/ GIMT_Encode4(473088), // Rule ID 29317 //
     /*  473035 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  473038 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473041 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473048 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473053 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473057 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473064 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  473067 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473072 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473079 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473082 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473086 */   GIR_RootConstrainSelectedInstOperands,
     /*  473087 */   // GIR_Coverage, 29317,
     /*  473087 */   GIR_EraseRootFromParent_Done,
     /*  473088 */ // Label 7124: @473088
     /*  473088 */ GIM_Try, /*On fail goto*//*Label 7125*/ GIMT_Encode4(473146), // Rule ID 29318 //
     /*  473093 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  473096 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473099 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473111 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473115 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473122 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  473125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473130 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473140 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473144 */   GIR_RootConstrainSelectedInstOperands,
     /*  473145 */   // GIR_Coverage, 29318,
     /*  473145 */   GIR_EraseRootFromParent_Done,
     /*  473146 */ // Label 7125: @473146
     /*  473146 */ GIM_Try, /*On fail goto*//*Label 7126*/ GIMT_Encode4(473204), // Rule ID 29319 //
     /*  473151 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  473154 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473157 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473164 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473180 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473180 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  473183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473188 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473195 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473198 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473202 */   GIR_RootConstrainSelectedInstOperands,
     /*  473203 */   // GIR_Coverage, 29319,
     /*  473203 */   GIR_EraseRootFromParent_Done,
     /*  473204 */ // Label 7126: @473204
     /*  473204 */ GIM_Try, /*On fail goto*//*Label 7127*/ GIMT_Encode4(473262), // Rule ID 29320 //
     /*  473209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  473212 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473215 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473222 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473227 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473231 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473238 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  473241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473246 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473253 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473256 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473260 */   GIR_RootConstrainSelectedInstOperands,
     /*  473261 */   // GIR_Coverage, 29320,
     /*  473261 */   GIR_EraseRootFromParent_Done,
     /*  473262 */ // Label 7127: @473262
     /*  473262 */ GIM_Try, /*On fail goto*//*Label 7128*/ GIMT_Encode4(473320), // Rule ID 29321 //
     /*  473267 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  473270 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473273 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473280 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473296 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  473299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473304 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473314 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473318 */   GIR_RootConstrainSelectedInstOperands,
     /*  473319 */   // GIR_Coverage, 29321,
     /*  473319 */   GIR_EraseRootFromParent_Done,
     /*  473320 */ // Label 7128: @473320
     /*  473320 */ GIM_Try, /*On fail goto*//*Label 7129*/ GIMT_Encode4(473378), // Rule ID 29322 //
     /*  473325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  473328 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473331 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473338 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473347 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473354 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473354 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  473357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473362 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473364 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473376 */   GIR_RootConstrainSelectedInstOperands,
     /*  473377 */   // GIR_Coverage, 29322,
     /*  473377 */   GIR_EraseRootFromParent_Done,
     /*  473378 */ // Label 7129: @473378
     /*  473378 */ GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(473436), // Rule ID 29323 //
     /*  473383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  473386 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473389 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  473396 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473412 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  473415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473420 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473427 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473430 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473434 */   GIR_RootConstrainSelectedInstOperands,
     /*  473435 */   // GIR_Coverage, 29323,
     /*  473435 */   GIR_EraseRootFromParent_Done,
     /*  473436 */ // Label 7130: @473436
     /*  473436 */ GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(473494), // Rule ID 29335 //
     /*  473441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  473444 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473447 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473454 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473459 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473463 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473470 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  473473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473478 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473485 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473488 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473492 */   GIR_RootConstrainSelectedInstOperands,
     /*  473493 */   // GIR_Coverage, 29335,
     /*  473493 */   GIR_EraseRootFromParent_Done,
     /*  473494 */ // Label 7131: @473494
     /*  473494 */ GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(473552), // Rule ID 29336 //
     /*  473499 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  473502 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473505 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473512 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473517 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473521 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473528 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  473531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473536 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473543 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473546 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473550 */   GIR_RootConstrainSelectedInstOperands,
     /*  473551 */   // GIR_Coverage, 29336,
     /*  473551 */   GIR_EraseRootFromParent_Done,
     /*  473552 */ // Label 7132: @473552
     /*  473552 */ GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(473610), // Rule ID 29337 //
     /*  473557 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  473560 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473563 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473570 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473575 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473579 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473586 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473586 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  473589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473594 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473601 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473604 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473608 */   GIR_RootConstrainSelectedInstOperands,
     /*  473609 */   // GIR_Coverage, 29337,
     /*  473609 */   GIR_EraseRootFromParent_Done,
     /*  473610 */ // Label 7133: @473610
     /*  473610 */ GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(473668), // Rule ID 29338 //
     /*  473615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  473618 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473621 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473628 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473633 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473637 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473644 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473644 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  473647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473652 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473659 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473662 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473666 */   GIR_RootConstrainSelectedInstOperands,
     /*  473667 */   // GIR_Coverage, 29338,
     /*  473667 */   GIR_EraseRootFromParent_Done,
     /*  473668 */ // Label 7134: @473668
     /*  473668 */ GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(473726), // Rule ID 29339 //
     /*  473673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  473676 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473679 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473686 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473691 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473695 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473702 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473702 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  473705 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473710 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473717 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473720 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473724 */   GIR_RootConstrainSelectedInstOperands,
     /*  473725 */   // GIR_Coverage, 29339,
     /*  473725 */   GIR_EraseRootFromParent_Done,
     /*  473726 */ // Label 7135: @473726
     /*  473726 */ GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(473784), // Rule ID 29340 //
     /*  473731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  473734 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473737 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473744 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473749 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473753 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473760 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  473763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473768 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473775 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473778 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473782 */   GIR_RootConstrainSelectedInstOperands,
     /*  473783 */   // GIR_Coverage, 29340,
     /*  473783 */   GIR_EraseRootFromParent_Done,
     /*  473784 */ // Label 7136: @473784
     /*  473784 */ GIM_Try, /*On fail goto*//*Label 7137*/ GIMT_Encode4(473842), // Rule ID 29341 //
     /*  473789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  473792 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473795 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473807 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473811 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473818 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  473821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473826 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473836 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473840 */   GIR_RootConstrainSelectedInstOperands,
     /*  473841 */   // GIR_Coverage, 29341,
     /*  473841 */   GIR_EraseRootFromParent_Done,
     /*  473842 */ // Label 7137: @473842
     /*  473842 */ GIM_Try, /*On fail goto*//*Label 7138*/ GIMT_Encode4(473900), // Rule ID 29342 //
     /*  473847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  473850 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473853 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473860 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473865 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473869 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473876 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473876 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  473879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473884 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473891 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473894 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473898 */   GIR_RootConstrainSelectedInstOperands,
     /*  473899 */   // GIR_Coverage, 29342,
     /*  473899 */   GIR_EraseRootFromParent_Done,
     /*  473900 */ // Label 7138: @473900
     /*  473900 */ GIM_Try, /*On fail goto*//*Label 7139*/ GIMT_Encode4(473958), // Rule ID 29343 //
     /*  473905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  473908 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473911 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473918 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473923 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473934 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  473937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  473942 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  473944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  473949 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  473952 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  473956 */   GIR_RootConstrainSelectedInstOperands,
     /*  473957 */   // GIR_Coverage, 29343,
     /*  473957 */   GIR_EraseRootFromParent_Done,
     /*  473958 */ // Label 7139: @473958
     /*  473958 */ GIM_Try, /*On fail goto*//*Label 7140*/ GIMT_Encode4(474016), // Rule ID 29344 //
     /*  473963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  473966 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  473969 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  473976 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  473981 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  473985 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  473992 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  473992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  473995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474000 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474007 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474010 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474014 */   GIR_RootConstrainSelectedInstOperands,
     /*  474015 */   // GIR_Coverage, 29344,
     /*  474015 */   GIR_EraseRootFromParent_Done,
     /*  474016 */ // Label 7140: @474016
     /*  474016 */ GIM_Try, /*On fail goto*//*Label 7141*/ GIMT_Encode4(474074), // Rule ID 29345 //
     /*  474021 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  474024 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474027 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474034 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474039 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474043 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474050 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474050 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  474053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474058 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474065 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474068 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474072 */   GIR_RootConstrainSelectedInstOperands,
     /*  474073 */   // GIR_Coverage, 29345,
     /*  474073 */   GIR_EraseRootFromParent_Done,
     /*  474074 */ // Label 7141: @474074
     /*  474074 */ GIM_Try, /*On fail goto*//*Label 7142*/ GIMT_Encode4(474132), // Rule ID 29346 //
     /*  474079 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  474082 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474085 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474092 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474108 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474108 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  474111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474116 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474123 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474126 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474130 */   GIR_RootConstrainSelectedInstOperands,
     /*  474131 */   // GIR_Coverage, 29346,
     /*  474131 */   GIR_EraseRootFromParent_Done,
     /*  474132 */ // Label 7142: @474132
     /*  474132 */ GIM_Try, /*On fail goto*//*Label 7143*/ GIMT_Encode4(474190), // Rule ID 29347 //
     /*  474137 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  474140 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474143 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474150 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474155 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474159 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474166 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474166 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  474169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474174 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474181 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474184 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474188 */   GIR_RootConstrainSelectedInstOperands,
     /*  474189 */   // GIR_Coverage, 29347,
     /*  474189 */   GIR_EraseRootFromParent_Done,
     /*  474190 */ // Label 7143: @474190
     /*  474190 */ GIM_Try, /*On fail goto*//*Label 7144*/ GIMT_Encode4(474248), // Rule ID 29348 //
     /*  474195 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  474198 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474201 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474208 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474217 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474224 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  474227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474232 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474246 */   GIR_RootConstrainSelectedInstOperands,
     /*  474247 */   // GIR_Coverage, 29348,
     /*  474247 */   GIR_EraseRootFromParent_Done,
     /*  474248 */ // Label 7144: @474248
     /*  474248 */ GIM_Try, /*On fail goto*//*Label 7145*/ GIMT_Encode4(474306), // Rule ID 29349 //
     /*  474253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  474256 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474259 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474266 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474271 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474275 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474282 */   // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474282 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  474285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474290 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474300 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474304 */   GIR_RootConstrainSelectedInstOperands,
     /*  474305 */   // GIR_Coverage, 29349,
     /*  474305 */   GIR_EraseRootFromParent_Done,
     /*  474306 */ // Label 7145: @474306
     /*  474306 */ GIM_Try, /*On fail goto*//*Label 7146*/ GIMT_Encode4(474364), // Rule ID 29350 //
     /*  474311 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  474314 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474317 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474324 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474329 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474333 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474340 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474340 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  474343 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474348 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474355 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474358 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474362 */   GIR_RootConstrainSelectedInstOperands,
     /*  474363 */   // GIR_Coverage, 29350,
     /*  474363 */   GIR_EraseRootFromParent_Done,
     /*  474364 */ // Label 7146: @474364
     /*  474364 */ GIM_Try, /*On fail goto*//*Label 7147*/ GIMT_Encode4(474422), // Rule ID 29351 //
     /*  474369 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  474372 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474375 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474382 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474387 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474391 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474398 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474398 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  474401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474406 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474408 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474413 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474416 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474420 */   GIR_RootConstrainSelectedInstOperands,
     /*  474421 */   // GIR_Coverage, 29351,
     /*  474421 */   GIR_EraseRootFromParent_Done,
     /*  474422 */ // Label 7147: @474422
     /*  474422 */ GIM_Try, /*On fail goto*//*Label 7148*/ GIMT_Encode4(474480), // Rule ID 29352 //
     /*  474427 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  474430 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474433 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474440 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474445 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474449 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474456 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474456 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  474459 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474464 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474478 */   GIR_RootConstrainSelectedInstOperands,
     /*  474479 */   // GIR_Coverage, 29352,
     /*  474479 */   GIR_EraseRootFromParent_Done,
     /*  474480 */ // Label 7148: @474480
     /*  474480 */ GIM_Try, /*On fail goto*//*Label 7149*/ GIMT_Encode4(474538), // Rule ID 29353 //
     /*  474485 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  474488 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474491 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474498 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474514 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  474517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474522 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474532 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474536 */   GIR_RootConstrainSelectedInstOperands,
     /*  474537 */   // GIR_Coverage, 29353,
     /*  474537 */   GIR_EraseRootFromParent_Done,
     /*  474538 */ // Label 7149: @474538
     /*  474538 */ GIM_Try, /*On fail goto*//*Label 7150*/ GIMT_Encode4(474596), // Rule ID 29354 //
     /*  474543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  474546 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  474549 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  474556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474572 */   // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  474575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474580 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474587 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474594 */   GIR_RootConstrainSelectedInstOperands,
     /*  474595 */   // GIR_Coverage, 29354,
     /*  474595 */   GIR_EraseRootFromParent_Done,
     /*  474596 */ // Label 7150: @474596
     /*  474596 */ GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(474658), // Rule ID 29181 //
     /*  474601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  474604 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474607 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474611 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474618 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474634 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  474637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474642 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474656 */   GIR_RootConstrainSelectedInstOperands,
     /*  474657 */   // GIR_Coverage, 29181,
     /*  474657 */   GIR_EraseRootFromParent_Done,
     /*  474658 */ // Label 7151: @474658
     /*  474658 */ GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(474720), // Rule ID 29182 //
     /*  474663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  474666 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474669 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474673 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474696 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  474699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474704 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474711 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474714 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474718 */   GIR_RootConstrainSelectedInstOperands,
     /*  474719 */   // GIR_Coverage, 29182,
     /*  474719 */   GIR_EraseRootFromParent_Done,
     /*  474720 */ // Label 7152: @474720
     /*  474720 */ GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(474782), // Rule ID 29183 //
     /*  474725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  474728 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474731 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474735 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474742 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474747 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474751 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474758 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474758 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  474761 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474766 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474776 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474780 */   GIR_RootConstrainSelectedInstOperands,
     /*  474781 */   // GIR_Coverage, 29183,
     /*  474781 */   GIR_EraseRootFromParent_Done,
     /*  474782 */ // Label 7153: @474782
     /*  474782 */ GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(474844), // Rule ID 29184 //
     /*  474787 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  474790 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474793 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474797 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474804 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474820 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  474823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474828 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474835 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474838 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474842 */   GIR_RootConstrainSelectedInstOperands,
     /*  474843 */   // GIR_Coverage, 29184,
     /*  474843 */   GIR_EraseRootFromParent_Done,
     /*  474844 */ // Label 7154: @474844
     /*  474844 */ GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(474906), // Rule ID 29185 //
     /*  474849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  474852 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474855 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474859 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474866 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474871 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474875 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474882 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474882 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
     /*  474885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474890 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474897 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474900 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474904 */   GIR_RootConstrainSelectedInstOperands,
     /*  474905 */   // GIR_Coverage, 29185,
     /*  474905 */   GIR_EraseRootFromParent_Done,
     /*  474906 */ // Label 7155: @474906
     /*  474906 */ GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(474968), // Rule ID 29186 //
     /*  474911 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  474914 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474917 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474921 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474928 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  474944 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  474944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  474947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  474952 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  474954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  474959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  474962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  474966 */   GIR_RootConstrainSelectedInstOperands,
     /*  474967 */   // GIR_Coverage, 29186,
     /*  474967 */   GIR_EraseRootFromParent_Done,
     /*  474968 */ // Label 7156: @474968
     /*  474968 */ GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(475030), // Rule ID 29187 //
     /*  474973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  474976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  474979 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  474983 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  474990 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  474995 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  474999 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475006 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475006 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  475009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475014 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475021 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475024 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475028 */   GIR_RootConstrainSelectedInstOperands,
     /*  475029 */   // GIR_Coverage, 29187,
     /*  475029 */   GIR_EraseRootFromParent_Done,
     /*  475030 */ // Label 7157: @475030
     /*  475030 */ GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(475092), // Rule ID 29188 //
     /*  475035 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  475038 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475041 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475045 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  475052 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475057 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475061 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475068 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475068 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  475071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475076 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475083 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475086 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475090 */   GIR_RootConstrainSelectedInstOperands,
     /*  475091 */   // GIR_Coverage, 29188,
     /*  475091 */   GIR_EraseRootFromParent_Done,
     /*  475092 */ // Label 7158: @475092
     /*  475092 */ GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(475154), // Rule ID 29189 //
     /*  475097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  475100 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475103 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475107 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  475114 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475123 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475130 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475130 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  475133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475138 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475145 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475148 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475152 */   GIR_RootConstrainSelectedInstOperands,
     /*  475153 */   // GIR_Coverage, 29189,
     /*  475153 */   GIR_EraseRootFromParent_Done,
     /*  475154 */ // Label 7159: @475154
     /*  475154 */ GIM_Try, /*On fail goto*//*Label 7160*/ GIMT_Encode4(475216), // Rule ID 29190 //
     /*  475159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  475162 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475165 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475169 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  475176 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475192 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
     /*  475195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475200 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475210 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475214 */   GIR_RootConstrainSelectedInstOperands,
     /*  475215 */   // GIR_Coverage, 29190,
     /*  475215 */   GIR_EraseRootFromParent_Done,
     /*  475216 */ // Label 7160: @475216
     /*  475216 */ GIM_Try, /*On fail goto*//*Label 7161*/ GIMT_Encode4(475278), // Rule ID 29202 //
     /*  475221 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  475224 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475227 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475231 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475238 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475254 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  475257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475262 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475276 */   GIR_RootConstrainSelectedInstOperands,
     /*  475277 */   // GIR_Coverage, 29202,
     /*  475277 */   GIR_EraseRootFromParent_Done,
     /*  475278 */ // Label 7161: @475278
     /*  475278 */ GIM_Try, /*On fail goto*//*Label 7162*/ GIMT_Encode4(475340), // Rule ID 29203 //
     /*  475283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  475286 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475289 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475293 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475300 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475305 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475309 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475316 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  475319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475324 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475331 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475334 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475338 */   GIR_RootConstrainSelectedInstOperands,
     /*  475339 */   // GIR_Coverage, 29203,
     /*  475339 */   GIR_EraseRootFromParent_Done,
     /*  475340 */ // Label 7162: @475340
     /*  475340 */ GIM_Try, /*On fail goto*//*Label 7163*/ GIMT_Encode4(475402), // Rule ID 29204 //
     /*  475345 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  475348 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475351 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475355 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475362 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475367 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475378 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  475381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475386 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475393 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475396 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475400 */   GIR_RootConstrainSelectedInstOperands,
     /*  475401 */   // GIR_Coverage, 29204,
     /*  475401 */   GIR_EraseRootFromParent_Done,
     /*  475402 */ // Label 7163: @475402
     /*  475402 */ GIM_Try, /*On fail goto*//*Label 7164*/ GIMT_Encode4(475464), // Rule ID 29205 //
     /*  475407 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  475410 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475413 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475417 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475424 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475429 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475433 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475440 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475440 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  475443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475448 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475455 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475458 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475462 */   GIR_RootConstrainSelectedInstOperands,
     /*  475463 */   // GIR_Coverage, 29205,
     /*  475463 */   GIR_EraseRootFromParent_Done,
     /*  475464 */ // Label 7164: @475464
     /*  475464 */ GIM_Try, /*On fail goto*//*Label 7165*/ GIMT_Encode4(475526), // Rule ID 29206 //
     /*  475469 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  475472 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475475 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475479 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475486 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475491 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475495 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475502 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475502 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
     /*  475505 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475510 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475517 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475520 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475524 */   GIR_RootConstrainSelectedInstOperands,
     /*  475525 */   // GIR_Coverage, 29206,
     /*  475525 */   GIR_EraseRootFromParent_Done,
     /*  475526 */ // Label 7165: @475526
     /*  475526 */ GIM_Try, /*On fail goto*//*Label 7166*/ GIMT_Encode4(475588), // Rule ID 29207 //
     /*  475531 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  475534 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475537 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475541 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475548 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475553 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475557 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475564 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475564 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  475567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475572 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475574 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475579 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475582 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475586 */   GIR_RootConstrainSelectedInstOperands,
     /*  475587 */   // GIR_Coverage, 29207,
     /*  475587 */   GIR_EraseRootFromParent_Done,
     /*  475588 */ // Label 7166: @475588
     /*  475588 */ GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(475650), // Rule ID 29208 //
     /*  475593 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  475596 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475599 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475603 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475610 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475615 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475619 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475626 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  475629 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475634 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475641 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475644 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475648 */   GIR_RootConstrainSelectedInstOperands,
     /*  475649 */   // GIR_Coverage, 29208,
     /*  475649 */   GIR_EraseRootFromParent_Done,
     /*  475650 */ // Label 7167: @475650
     /*  475650 */ GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(475712), // Rule ID 29209 //
     /*  475655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  475658 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475661 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475665 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475672 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475677 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475681 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475688 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475688 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  475691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475696 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475703 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475706 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475710 */   GIR_RootConstrainSelectedInstOperands,
     /*  475711 */   // GIR_Coverage, 29209,
     /*  475711 */   GIR_EraseRootFromParent_Done,
     /*  475712 */ // Label 7168: @475712
     /*  475712 */ GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(475774), // Rule ID 29210 //
     /*  475717 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  475720 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475723 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475727 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475734 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475739 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475743 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475750 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  475753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475758 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475765 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475768 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475772 */   GIR_RootConstrainSelectedInstOperands,
     /*  475773 */   // GIR_Coverage, 29210,
     /*  475773 */   GIR_EraseRootFromParent_Done,
     /*  475774 */ // Label 7169: @475774
     /*  475774 */ GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(475836), // Rule ID 29211 //
     /*  475779 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  475782 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475785 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475789 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  475796 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475801 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475812 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475812 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
     /*  475815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475820 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475827 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475830 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475834 */   GIR_RootConstrainSelectedInstOperands,
     /*  475835 */   // GIR_Coverage, 29211,
     /*  475835 */   GIR_EraseRootFromParent_Done,
     /*  475836 */ // Label 7170: @475836
     /*  475836 */ GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(475891), // Rule ID 29223 //
     /*  475841 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  475844 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475847 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475851 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475867 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  475870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475875 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475889 */   GIR_RootConstrainSelectedInstOperands,
     /*  475890 */   // GIR_Coverage, 29223,
     /*  475890 */   GIR_EraseRootFromParent_Done,
     /*  475891 */ // Label 7171: @475891
     /*  475891 */ GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(475946), // Rule ID 29224 //
     /*  475896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  475899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475902 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475906 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475911 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475915 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475922 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  475925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475930 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475937 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475940 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475944 */   GIR_RootConstrainSelectedInstOperands,
     /*  475945 */   // GIR_Coverage, 29224,
     /*  475945 */   GIR_EraseRootFromParent_Done,
     /*  475946 */ // Label 7172: @475946
     /*  475946 */ GIM_Try, /*On fail goto*//*Label 7173*/ GIMT_Encode4(476001), // Rule ID 29225 //
     /*  475951 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  475954 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  475957 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  475961 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  475966 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  475970 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  475977 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  475977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  475980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  475985 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  475987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  475992 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  475995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  475999 */   GIR_RootConstrainSelectedInstOperands,
     /*  476000 */   // GIR_Coverage, 29225,
     /*  476000 */   GIR_EraseRootFromParent_Done,
     /*  476001 */ // Label 7173: @476001
     /*  476001 */ GIM_Try, /*On fail goto*//*Label 7174*/ GIMT_Encode4(476056), // Rule ID 29226 //
     /*  476006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  476009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476012 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476016 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476021 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476025 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476032 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476032 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476040 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476042 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476047 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476050 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476054 */   GIR_RootConstrainSelectedInstOperands,
     /*  476055 */   // GIR_Coverage, 29226,
     /*  476055 */   GIR_EraseRootFromParent_Done,
     /*  476056 */ // Label 7174: @476056
     /*  476056 */ GIM_Try, /*On fail goto*//*Label 7175*/ GIMT_Encode4(476111), // Rule ID 29227 //
     /*  476061 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  476064 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476067 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476071 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476076 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476080 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476087 */   // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476095 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476102 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476105 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476109 */   GIR_RootConstrainSelectedInstOperands,
     /*  476110 */   // GIR_Coverage, 29227,
     /*  476110 */   GIR_EraseRootFromParent_Done,
     /*  476111 */ // Label 7175: @476111
     /*  476111 */ GIM_Try, /*On fail goto*//*Label 7176*/ GIMT_Encode4(476166), // Rule ID 29233 //
     /*  476116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  476119 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476122 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476126 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476131 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476135 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476142 */   // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476142 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476150 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476157 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476160 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476164 */   GIR_RootConstrainSelectedInstOperands,
     /*  476165 */   // GIR_Coverage, 29233,
     /*  476165 */   GIR_EraseRootFromParent_Done,
     /*  476166 */ // Label 7176: @476166
     /*  476166 */ GIM_Try, /*On fail goto*//*Label 7177*/ GIMT_Encode4(476221), // Rule ID 29234 //
     /*  476171 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  476174 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476177 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476181 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476186 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476190 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476197 */   // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476197 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476205 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476215 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476219 */   GIR_RootConstrainSelectedInstOperands,
     /*  476220 */   // GIR_Coverage, 29234,
     /*  476220 */   GIR_EraseRootFromParent_Done,
     /*  476221 */ // Label 7177: @476221
     /*  476221 */ GIM_Try, /*On fail goto*//*Label 7178*/ GIMT_Encode4(476276), // Rule ID 29235 //
     /*  476226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  476229 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476232 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476245 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476252 */   // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476260 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476267 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476270 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476274 */   GIR_RootConstrainSelectedInstOperands,
     /*  476275 */   // GIR_Coverage, 29235,
     /*  476275 */   GIR_EraseRootFromParent_Done,
     /*  476276 */ // Label 7178: @476276
     /*  476276 */ GIM_Try, /*On fail goto*//*Label 7179*/ GIMT_Encode4(476331), // Rule ID 29236 //
     /*  476281 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  476284 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476287 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476291 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476296 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476300 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476307 */   // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476315 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476325 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476329 */   GIR_RootConstrainSelectedInstOperands,
     /*  476330 */   // GIR_Coverage, 29236,
     /*  476330 */   GIR_EraseRootFromParent_Done,
     /*  476331 */ // Label 7179: @476331
     /*  476331 */ GIM_Try, /*On fail goto*//*Label 7180*/ GIMT_Encode4(476386), // Rule ID 29237 //
     /*  476336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  476339 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476342 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  476346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476362 */   // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  476365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476370 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476377 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476380 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476384 */   GIR_RootConstrainSelectedInstOperands,
     /*  476385 */   // GIR_Coverage, 29237,
     /*  476385 */   GIR_EraseRootFromParent_Done,
     /*  476386 */ // Label 7180: @476386
     /*  476386 */ GIM_Try, /*On fail goto*//*Label 7181*/ GIMT_Encode4(476437), // Rule ID 29228 //
     /*  476391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  476394 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476397 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476402 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476413 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476421 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476428 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476431 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476435 */   GIR_RootConstrainSelectedInstOperands,
     /*  476436 */   // GIR_Coverage, 29228,
     /*  476436 */   GIR_EraseRootFromParent_Done,
     /*  476437 */ // Label 7181: @476437
     /*  476437 */ GIM_Try, /*On fail goto*//*Label 7182*/ GIMT_Encode4(476488), // Rule ID 29229 //
     /*  476442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  476445 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476448 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476453 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476457 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476464 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476472 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476479 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476482 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476486 */   GIR_RootConstrainSelectedInstOperands,
     /*  476487 */   // GIR_Coverage, 29229,
     /*  476487 */   GIR_EraseRootFromParent_Done,
     /*  476488 */ // Label 7182: @476488
     /*  476488 */ GIM_Try, /*On fail goto*//*Label 7183*/ GIMT_Encode4(476539), // Rule ID 29230 //
     /*  476493 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  476496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476515 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476523 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476537 */   GIR_RootConstrainSelectedInstOperands,
     /*  476538 */   // GIR_Coverage, 29230,
     /*  476538 */   GIR_EraseRootFromParent_Done,
     /*  476539 */ // Label 7183: @476539
     /*  476539 */ GIM_Try, /*On fail goto*//*Label 7184*/ GIMT_Encode4(476590), // Rule ID 29231 //
     /*  476544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  476547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476566 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476574 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476581 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476584 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476588 */   GIR_RootConstrainSelectedInstOperands,
     /*  476589 */   // GIR_Coverage, 29231,
     /*  476589 */   GIR_EraseRootFromParent_Done,
     /*  476590 */ // Label 7184: @476590
     /*  476590 */ GIM_Try, /*On fail goto*//*Label 7185*/ GIMT_Encode4(476641), // Rule ID 29232 //
     /*  476595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  476598 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476601 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476617 */   // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476625 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476635 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476639 */   GIR_RootConstrainSelectedInstOperands,
     /*  476640 */   // GIR_Coverage, 29232,
     /*  476640 */   GIR_EraseRootFromParent_Done,
     /*  476641 */ // Label 7185: @476641
     /*  476641 */ GIM_Try, /*On fail goto*//*Label 7186*/ GIMT_Encode4(476692), // Rule ID 29238 //
     /*  476646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  476649 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476652 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476657 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476661 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476668 */   // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476676 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476683 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476690 */   GIR_RootConstrainSelectedInstOperands,
     /*  476691 */   // GIR_Coverage, 29238,
     /*  476691 */   GIR_EraseRootFromParent_Done,
     /*  476692 */ // Label 7186: @476692
     /*  476692 */ GIM_Try, /*On fail goto*//*Label 7187*/ GIMT_Encode4(476743), // Rule ID 29239 //
     /*  476697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  476700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476719 */   // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476727 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476741 */   GIR_RootConstrainSelectedInstOperands,
     /*  476742 */   // GIR_Coverage, 29239,
     /*  476742 */   GIR_EraseRootFromParent_Done,
     /*  476743 */ // Label 7187: @476743
     /*  476743 */ GIM_Try, /*On fail goto*//*Label 7188*/ GIMT_Encode4(476794), // Rule ID 29240 //
     /*  476748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  476751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476759 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476763 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476770 */   // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476778 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476792 */   GIR_RootConstrainSelectedInstOperands,
     /*  476793 */   // GIR_Coverage, 29240,
     /*  476793 */   GIR_EraseRootFromParent_Done,
     /*  476794 */ // Label 7188: @476794
     /*  476794 */ GIM_Try, /*On fail goto*//*Label 7189*/ GIMT_Encode4(476845), // Rule ID 29241 //
     /*  476799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  476802 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476805 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476821 */   // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476829 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476843 */   GIR_RootConstrainSelectedInstOperands,
     /*  476844 */   // GIR_Coverage, 29241,
     /*  476844 */   GIR_EraseRootFromParent_Done,
     /*  476845 */ // Label 7189: @476845
     /*  476845 */ GIM_Try, /*On fail goto*//*Label 7190*/ GIMT_Encode4(476896), // Rule ID 29242 //
     /*  476850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  476853 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  476856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  476861 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476865 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  476872 */   // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  476872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  476875 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  476880 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  476882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  476887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  476890 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476894 */   GIR_RootConstrainSelectedInstOperands,
     /*  476895 */   // GIR_Coverage, 29242,
     /*  476895 */   GIR_EraseRootFromParent_Done,
     /*  476896 */ // Label 7190: @476896
     /*  476896 */ GIM_Try, /*On fail goto*//*Label 7191*/ GIMT_Encode4(476963), // Rule ID 12837 //
     /*  476901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  476904 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  476907 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  476914 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  476921 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476925 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  476932 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  476932 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  476935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  476940 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  476942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  476947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  476952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  476957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  476961 */   GIR_RootConstrainSelectedInstOperands,
     /*  476962 */   // GIR_Coverage, 12837,
     /*  476962 */   GIR_EraseRootFromParent_Done,
     /*  476963 */ // Label 7191: @476963
     /*  476963 */ GIM_Try, /*On fail goto*//*Label 7192*/ GIMT_Encode4(477030), // Rule ID 12838 //
     /*  476968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  476971 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  476974 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  476981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  476988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  476992 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  476999 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  476999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  477002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477007 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477024 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477028 */   GIR_RootConstrainSelectedInstOperands,
     /*  477029 */   // GIR_Coverage, 12838,
     /*  477029 */   GIR_EraseRootFromParent_Done,
     /*  477030 */ // Label 7192: @477030
     /*  477030 */ GIM_Try, /*On fail goto*//*Label 7193*/ GIMT_Encode4(477097), // Rule ID 12839 //
     /*  477035 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  477038 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477041 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  477048 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477059 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477066 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  477069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477074 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477091 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477095 */   GIR_RootConstrainSelectedInstOperands,
     /*  477096 */   // GIR_Coverage, 12839,
     /*  477096 */   GIR_EraseRootFromParent_Done,
     /*  477097 */ // Label 7193: @477097
     /*  477097 */ GIM_Try, /*On fail goto*//*Label 7194*/ GIMT_Encode4(477164), // Rule ID 12840 //
     /*  477102 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  477105 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477108 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  477115 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477122 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477126 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477133 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  477136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477141 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477162 */   GIR_RootConstrainSelectedInstOperands,
     /*  477163 */   // GIR_Coverage, 12840,
     /*  477163 */   GIR_EraseRootFromParent_Done,
     /*  477164 */ // Label 7194: @477164
     /*  477164 */ GIM_Try, /*On fail goto*//*Label 7195*/ GIMT_Encode4(477231), // Rule ID 12841 //
     /*  477169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  477172 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477175 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  477182 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477189 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477193 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477200 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477200 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  477203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477208 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477215 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477220 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477225 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477229 */   GIR_RootConstrainSelectedInstOperands,
     /*  477230 */   // GIR_Coverage, 12841,
     /*  477230 */   GIR_EraseRootFromParent_Done,
     /*  477231 */ // Label 7195: @477231
     /*  477231 */ GIM_Try, /*On fail goto*//*Label 7196*/ GIMT_Encode4(477298), // Rule ID 12847 //
     /*  477236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  477239 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477242 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  477249 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477256 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477260 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477267 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477267 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  477270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477275 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477292 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477296 */   GIR_RootConstrainSelectedInstOperands,
     /*  477297 */   // GIR_Coverage, 12847,
     /*  477297 */   GIR_EraseRootFromParent_Done,
     /*  477298 */ // Label 7196: @477298
     /*  477298 */ GIM_Try, /*On fail goto*//*Label 7197*/ GIMT_Encode4(477365), // Rule ID 12848 //
     /*  477303 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  477306 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477309 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  477316 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477323 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477327 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477334 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477334 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  477337 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477342 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477359 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477363 */   GIR_RootConstrainSelectedInstOperands,
     /*  477364 */   // GIR_Coverage, 12848,
     /*  477364 */   GIR_EraseRootFromParent_Done,
     /*  477365 */ // Label 7197: @477365
     /*  477365 */ GIM_Try, /*On fail goto*//*Label 7198*/ GIMT_Encode4(477432), // Rule ID 12849 //
     /*  477370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  477373 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  477383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477390 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477394 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477401 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477401 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  477404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477409 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477426 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477430 */   GIR_RootConstrainSelectedInstOperands,
     /*  477431 */   // GIR_Coverage, 12849,
     /*  477431 */   GIR_EraseRootFromParent_Done,
     /*  477432 */ // Label 7198: @477432
     /*  477432 */ GIM_Try, /*On fail goto*//*Label 7199*/ GIMT_Encode4(477499), // Rule ID 12850 //
     /*  477437 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  477440 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477443 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  477450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477457 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477461 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477468 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477468 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  477471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477476 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477478 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477483 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477493 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477497 */   GIR_RootConstrainSelectedInstOperands,
     /*  477498 */   // GIR_Coverage, 12850,
     /*  477498 */   GIR_EraseRootFromParent_Done,
     /*  477499 */ // Label 7199: @477499
     /*  477499 */ GIM_Try, /*On fail goto*//*Label 7200*/ GIMT_Encode4(477566), // Rule ID 12851 //
     /*  477504 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  477507 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477510 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  477517 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477535 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  477538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477543 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477560 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477564 */   GIR_RootConstrainSelectedInstOperands,
     /*  477565 */   // GIR_Coverage, 12851,
     /*  477565 */   GIR_EraseRootFromParent_Done,
     /*  477566 */ // Label 7200: @477566
     /*  477566 */ GIM_Try, /*On fail goto*//*Label 7201*/ GIMT_Encode4(477633), // Rule ID 12857 //
     /*  477571 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  477574 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477577 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  477584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477591 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477595 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477602 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  477605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477610 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477627 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477631 */   GIR_RootConstrainSelectedInstOperands,
     /*  477632 */   // GIR_Coverage, 12857,
     /*  477632 */   GIR_EraseRootFromParent_Done,
     /*  477633 */ // Label 7201: @477633
     /*  477633 */ GIM_Try, /*On fail goto*//*Label 7202*/ GIMT_Encode4(477700), // Rule ID 12858 //
     /*  477638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  477641 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477644 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  477651 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477658 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477662 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477669 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477669 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  477672 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477677 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477694 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477698 */   GIR_RootConstrainSelectedInstOperands,
     /*  477699 */   // GIR_Coverage, 12858,
     /*  477699 */   GIR_EraseRootFromParent_Done,
     /*  477700 */ // Label 7202: @477700
     /*  477700 */ GIM_Try, /*On fail goto*//*Label 7203*/ GIMT_Encode4(477767), // Rule ID 12859 //
     /*  477705 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  477708 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477711 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  477718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477725 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477729 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477736 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477736 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  477739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477744 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477765 */   GIR_RootConstrainSelectedInstOperands,
     /*  477766 */   // GIR_Coverage, 12859,
     /*  477766 */   GIR_EraseRootFromParent_Done,
     /*  477767 */ // Label 7203: @477767
     /*  477767 */ GIM_Try, /*On fail goto*//*Label 7204*/ GIMT_Encode4(477834), // Rule ID 12860 //
     /*  477772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  477775 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477778 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  477785 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477792 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477796 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477803 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477803 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  477806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477811 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477832 */   GIR_RootConstrainSelectedInstOperands,
     /*  477833 */   // GIR_Coverage, 12860,
     /*  477833 */   GIR_EraseRootFromParent_Done,
     /*  477834 */ // Label 7204: @477834
     /*  477834 */ GIM_Try, /*On fail goto*//*Label 7205*/ GIMT_Encode4(477901), // Rule ID 12861 //
     /*  477839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  477842 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  477845 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  477852 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477859 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477863 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477870 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  477873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477878 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477895 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477899 */   GIR_RootConstrainSelectedInstOperands,
     /*  477900 */   // GIR_Coverage, 12861,
     /*  477900 */   GIR_EraseRootFromParent_Done,
     /*  477901 */ // Label 7205: @477901
     /*  477901 */ GIM_Try, /*On fail goto*//*Label 7206*/ GIMT_Encode4(477972), // Rule ID 12613 //
     /*  477906 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  477909 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  477912 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  477916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  477923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  477930 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  477934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  477941 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  477941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  477944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  477949 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  477951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  477956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  477961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  477966 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  477970 */   GIR_RootConstrainSelectedInstOperands,
     /*  477971 */   // GIR_Coverage, 12613,
     /*  477971 */   GIR_EraseRootFromParent_Done,
     /*  477972 */ // Label 7206: @477972
     /*  477972 */ GIM_Try, /*On fail goto*//*Label 7207*/ GIMT_Encode4(478043), // Rule ID 12614 //
     /*  477977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  477980 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  477983 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  477987 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  477994 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478001 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478005 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478012 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478012 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  478015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478020 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478037 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478041 */   GIR_RootConstrainSelectedInstOperands,
     /*  478042 */   // GIR_Coverage, 12614,
     /*  478042 */   GIR_EraseRootFromParent_Done,
     /*  478043 */ // Label 7207: @478043
     /*  478043 */ GIM_Try, /*On fail goto*//*Label 7208*/ GIMT_Encode4(478114), // Rule ID 12615 //
     /*  478048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  478051 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478054 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478058 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  478065 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478072 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478076 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478083 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478083 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  478086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478091 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478108 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478112 */   GIR_RootConstrainSelectedInstOperands,
     /*  478113 */   // GIR_Coverage, 12615,
     /*  478113 */   GIR_EraseRootFromParent_Done,
     /*  478114 */ // Label 7208: @478114
     /*  478114 */ GIM_Try, /*On fail goto*//*Label 7209*/ GIMT_Encode4(478185), // Rule ID 12616 //
     /*  478119 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  478122 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478125 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478129 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  478136 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478147 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478154 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  478157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478162 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478179 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478183 */   GIR_RootConstrainSelectedInstOperands,
     /*  478184 */   // GIR_Coverage, 12616,
     /*  478184 */   GIR_EraseRootFromParent_Done,
     /*  478185 */ // Label 7209: @478185
     /*  478185 */ GIM_Try, /*On fail goto*//*Label 7210*/ GIMT_Encode4(478256), // Rule ID 12617 //
     /*  478190 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  478193 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478196 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478200 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  478207 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478214 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478218 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478225 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478225 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
     /*  478228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478233 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478250 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478254 */   GIR_RootConstrainSelectedInstOperands,
     /*  478255 */   // GIR_Coverage, 12617,
     /*  478255 */   GIR_EraseRootFromParent_Done,
     /*  478256 */ // Label 7210: @478256
     /*  478256 */ GIM_Try, /*On fail goto*//*Label 7211*/ GIMT_Encode4(478327), // Rule ID 12623 //
     /*  478261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  478264 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478267 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478271 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  478278 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478296 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  478299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478304 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478321 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478325 */   GIR_RootConstrainSelectedInstOperands,
     /*  478326 */   // GIR_Coverage, 12623,
     /*  478326 */   GIR_EraseRootFromParent_Done,
     /*  478327 */ // Label 7211: @478327
     /*  478327 */ GIM_Try, /*On fail goto*//*Label 7212*/ GIMT_Encode4(478398), // Rule ID 12624 //
     /*  478332 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  478335 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478338 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478342 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  478349 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478356 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478360 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478367 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478367 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  478370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478375 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478392 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478396 */   GIR_RootConstrainSelectedInstOperands,
     /*  478397 */   // GIR_Coverage, 12624,
     /*  478397 */   GIR_EraseRootFromParent_Done,
     /*  478398 */ // Label 7212: @478398
     /*  478398 */ GIM_Try, /*On fail goto*//*Label 7213*/ GIMT_Encode4(478469), // Rule ID 12625 //
     /*  478403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  478406 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478409 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478413 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  478420 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478427 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478431 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478438 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  478441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478446 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478463 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478467 */   GIR_RootConstrainSelectedInstOperands,
     /*  478468 */   // GIR_Coverage, 12625,
     /*  478468 */   GIR_EraseRootFromParent_Done,
     /*  478469 */ // Label 7213: @478469
     /*  478469 */ GIM_Try, /*On fail goto*//*Label 7214*/ GIMT_Encode4(478540), // Rule ID 12626 //
     /*  478474 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  478477 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478480 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478484 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  478491 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478498 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478502 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478509 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478509 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  478512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478517 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478534 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478538 */   GIR_RootConstrainSelectedInstOperands,
     /*  478539 */   // GIR_Coverage, 12626,
     /*  478539 */   GIR_EraseRootFromParent_Done,
     /*  478540 */ // Label 7214: @478540
     /*  478540 */ GIM_Try, /*On fail goto*//*Label 7215*/ GIMT_Encode4(478611), // Rule ID 12627 //
     /*  478545 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  478548 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478551 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  478555 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  478562 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478569 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478580 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
     /*  478583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478588 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478605 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478609 */   GIR_RootConstrainSelectedInstOperands,
     /*  478610 */   // GIR_Coverage, 12627,
     /*  478610 */   GIR_EraseRootFromParent_Done,
     /*  478611 */ // Label 7215: @478611
     /*  478611 */ GIM_Try, /*On fail goto*//*Label 7216*/ GIMT_Encode4(478671), // Rule ID 9381 //
     /*  478616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  478619 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478622 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478640 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  478643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478648 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478665 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478669 */   GIR_RootConstrainSelectedInstOperands,
     /*  478670 */   // GIR_Coverage, 9381,
     /*  478670 */   GIR_EraseRootFromParent_Done,
     /*  478671 */ // Label 7216: @478671
     /*  478671 */ GIM_Try, /*On fail goto*//*Label 7217*/ GIMT_Encode4(478731), // Rule ID 9382 //
     /*  478676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  478679 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478682 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478689 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478693 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478700 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  478703 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478708 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478720 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478725 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478729 */   GIR_RootConstrainSelectedInstOperands,
     /*  478730 */   // GIR_Coverage, 9382,
     /*  478730 */   GIR_EraseRootFromParent_Done,
     /*  478731 */ // Label 7217: @478731
     /*  478731 */ GIM_Try, /*On fail goto*//*Label 7218*/ GIMT_Encode4(478791), // Rule ID 9383 //
     /*  478736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  478739 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478742 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478749 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478753 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478760 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  478763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478768 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478785 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478789 */   GIR_RootConstrainSelectedInstOperands,
     /*  478790 */   // GIR_Coverage, 9383,
     /*  478790 */   GIR_EraseRootFromParent_Done,
     /*  478791 */ // Label 7218: @478791
     /*  478791 */ GIM_Try, /*On fail goto*//*Label 7219*/ GIMT_Encode4(478851), // Rule ID 9384 //
     /*  478796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  478799 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478802 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478809 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478813 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478820 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  478823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478828 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478845 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478849 */   GIR_RootConstrainSelectedInstOperands,
     /*  478850 */   // GIR_Coverage, 9384,
     /*  478850 */   GIR_EraseRootFromParent_Done,
     /*  478851 */ // Label 7219: @478851
     /*  478851 */ GIM_Try, /*On fail goto*//*Label 7220*/ GIMT_Encode4(478911), // Rule ID 9385 //
     /*  478856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  478859 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478862 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478869 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478873 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478880 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478880 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  478883 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478888 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478905 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478909 */   GIR_RootConstrainSelectedInstOperands,
     /*  478910 */   // GIR_Coverage, 9385,
     /*  478910 */   GIR_EraseRootFromParent_Done,
     /*  478911 */ // Label 7220: @478911
     /*  478911 */ GIM_Try, /*On fail goto*//*Label 7221*/ GIMT_Encode4(478971), // Rule ID 12133 //
     /*  478916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  478919 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478922 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478929 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478933 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  478940 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  478940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  478943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  478948 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  478950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  478955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  478960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  478965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  478969 */   GIR_RootConstrainSelectedInstOperands,
     /*  478970 */   // GIR_Coverage, 12133,
     /*  478970 */   GIR_EraseRootFromParent_Done,
     /*  478971 */ // Label 7221: @478971
     /*  478971 */ GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(479031), // Rule ID 12134 //
     /*  478976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  478979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  478982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  478989 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  478993 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  479000 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  479000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  479003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  479008 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  479015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  479020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  479025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479029 */   GIR_RootConstrainSelectedInstOperands,
     /*  479030 */   // GIR_Coverage, 12134,
     /*  479030 */   GIR_EraseRootFromParent_Done,
     /*  479031 */ // Label 7222: @479031
     /*  479031 */ GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(479091), // Rule ID 12135 //
     /*  479036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  479039 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  479042 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479049 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479053 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  479060 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  479060 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  479063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  479068 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  479075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  479080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  479085 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479089 */   GIR_RootConstrainSelectedInstOperands,
     /*  479090 */   // GIR_Coverage, 12135,
     /*  479090 */   GIR_EraseRootFromParent_Done,
     /*  479091 */ // Label 7223: @479091
     /*  479091 */ GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(479151), // Rule ID 12136 //
     /*  479096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  479099 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  479102 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479109 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479113 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  479120 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  479120 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  479123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  479128 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  479135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  479140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  479145 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479149 */   GIR_RootConstrainSelectedInstOperands,
     /*  479150 */   // GIR_Coverage, 12136,
     /*  479150 */   GIR_EraseRootFromParent_Done,
     /*  479151 */ // Label 7224: @479151
     /*  479151 */ GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(479211), // Rule ID 12137 //
     /*  479156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  479159 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  479162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  479180 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  479180 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  479183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  479188 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  479195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  479200 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  479205 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479209 */   GIR_RootConstrainSelectedInstOperands,
     /*  479210 */   // GIR_Coverage, 12137,
     /*  479210 */   GIR_EraseRootFromParent_Done,
     /*  479211 */ // Label 7225: @479211
     /*  479211 */ GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(479271), // Rule ID 12832 //
     /*  479216 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  479219 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479222 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  479229 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479236 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479240 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479247 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479247 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  479250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479255 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479262 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479265 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479269 */   GIR_RootConstrainSelectedInstOperands,
     /*  479270 */   // GIR_Coverage, 12832,
     /*  479270 */   GIR_EraseRootFromParent_Done,
     /*  479271 */ // Label 7226: @479271
     /*  479271 */ GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(479331), // Rule ID 12833 //
     /*  479276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  479279 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479282 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  479289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479296 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479300 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479307 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  479310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479315 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479325 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479329 */   GIR_RootConstrainSelectedInstOperands,
     /*  479330 */   // GIR_Coverage, 12833,
     /*  479330 */   GIR_EraseRootFromParent_Done,
     /*  479331 */ // Label 7227: @479331
     /*  479331 */ GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(479391), // Rule ID 12834 //
     /*  479336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  479339 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479342 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  479349 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479356 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479360 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479367 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479367 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  479370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479375 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479382 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479385 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479389 */   GIR_RootConstrainSelectedInstOperands,
     /*  479390 */   // GIR_Coverage, 12834,
     /*  479390 */   GIR_EraseRootFromParent_Done,
     /*  479391 */ // Label 7228: @479391
     /*  479391 */ GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(479451), // Rule ID 12835 //
     /*  479396 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  479399 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479402 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  479409 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479416 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479420 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479427 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479427 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  479430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479435 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479437 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479442 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479445 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479449 */   GIR_RootConstrainSelectedInstOperands,
     /*  479450 */   // GIR_Coverage, 12835,
     /*  479450 */   GIR_EraseRootFromParent_Done,
     /*  479451 */ // Label 7229: @479451
     /*  479451 */ GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(479511), // Rule ID 12836 //
     /*  479456 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  479459 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479462 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  479469 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479476 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479480 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479487 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479487 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  479490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479495 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479497 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479502 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479505 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479509 */   GIR_RootConstrainSelectedInstOperands,
     /*  479510 */   // GIR_Coverage, 12836,
     /*  479510 */   GIR_EraseRootFromParent_Done,
     /*  479511 */ // Label 7230: @479511
     /*  479511 */ GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(479571), // Rule ID 12842 //
     /*  479516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  479519 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479522 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  479529 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479536 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479540 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479547 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479547 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  479550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479555 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479562 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479565 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479569 */   GIR_RootConstrainSelectedInstOperands,
     /*  479570 */   // GIR_Coverage, 12842,
     /*  479570 */   GIR_EraseRootFromParent_Done,
     /*  479571 */ // Label 7231: @479571
     /*  479571 */ GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(479631), // Rule ID 12843 //
     /*  479576 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  479579 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479582 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  479589 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479600 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479607 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479607 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  479610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479615 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479625 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479629 */   GIR_RootConstrainSelectedInstOperands,
     /*  479630 */   // GIR_Coverage, 12843,
     /*  479630 */   GIR_EraseRootFromParent_Done,
     /*  479631 */ // Label 7232: @479631
     /*  479631 */ GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(479691), // Rule ID 12844 //
     /*  479636 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  479639 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479642 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  479649 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479656 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479660 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479667 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479667 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  479670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479675 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479677 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479682 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479689 */   GIR_RootConstrainSelectedInstOperands,
     /*  479690 */   // GIR_Coverage, 12844,
     /*  479690 */   GIR_EraseRootFromParent_Done,
     /*  479691 */ // Label 7233: @479691
     /*  479691 */ GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(479751), // Rule ID 12845 //
     /*  479696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  479699 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479702 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  479709 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479716 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479720 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479727 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  479730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479735 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479742 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479745 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479749 */   GIR_RootConstrainSelectedInstOperands,
     /*  479750 */   // GIR_Coverage, 12845,
     /*  479750 */   GIR_EraseRootFromParent_Done,
     /*  479751 */ // Label 7234: @479751
     /*  479751 */ GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(479811), // Rule ID 12846 //
     /*  479756 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  479759 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479762 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  479769 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479780 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479787 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479787 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  479790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479795 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479802 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479805 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479809 */   GIR_RootConstrainSelectedInstOperands,
     /*  479810 */   // GIR_Coverage, 12846,
     /*  479810 */   GIR_EraseRootFromParent_Done,
     /*  479811 */ // Label 7235: @479811
     /*  479811 */ GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(479871), // Rule ID 12852 //
     /*  479816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  479819 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  479829 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479836 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479840 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479847 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479847 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  479850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479855 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479862 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479865 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479869 */   GIR_RootConstrainSelectedInstOperands,
     /*  479870 */   // GIR_Coverage, 12852,
     /*  479870 */   GIR_EraseRootFromParent_Done,
     /*  479871 */ // Label 7236: @479871
     /*  479871 */ GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(479931), // Rule ID 12853 //
     /*  479876 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  479879 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479882 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  479889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479907 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  479910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479915 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479929 */   GIR_RootConstrainSelectedInstOperands,
     /*  479930 */   // GIR_Coverage, 12853,
     /*  479930 */   GIR_EraseRootFromParent_Done,
     /*  479931 */ // Label 7237: @479931
     /*  479931 */ GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(479991), // Rule ID 12854 //
     /*  479936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  479939 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  479942 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  479949 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  479956 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  479960 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  479967 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  479967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  479970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  479975 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  479977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  479982 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  479985 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  479989 */   GIR_RootConstrainSelectedInstOperands,
     /*  479990 */   // GIR_Coverage, 12854,
     /*  479990 */   GIR_EraseRootFromParent_Done,
     /*  479991 */ // Label 7238: @479991
     /*  479991 */ GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(480051), // Rule ID 12855 //
     /*  479996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  479999 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  480002 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  480009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480020 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480027 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480035 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480042 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480045 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480049 */   GIR_RootConstrainSelectedInstOperands,
     /*  480050 */   // GIR_Coverage, 12855,
     /*  480050 */   GIR_EraseRootFromParent_Done,
     /*  480051 */ // Label 7239: @480051
     /*  480051 */ GIM_Try, /*On fail goto*//*Label 7240*/ GIMT_Encode4(480111), // Rule ID 12856 //
     /*  480056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  480059 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  480062 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  480069 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480076 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480080 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480087 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480087 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480090 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480095 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480102 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480105 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480109 */   GIR_RootConstrainSelectedInstOperands,
     /*  480110 */   // GIR_Coverage, 12856,
     /*  480110 */   GIR_EraseRootFromParent_Done,
     /*  480111 */ // Label 7240: @480111
     /*  480111 */ GIM_Try, /*On fail goto*//*Label 7241*/ GIMT_Encode4(480175), // Rule ID 12608 //
     /*  480116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  480119 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480122 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480126 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  480133 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480151 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  480154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480159 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480166 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480169 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480173 */   GIR_RootConstrainSelectedInstOperands,
     /*  480174 */   // GIR_Coverage, 12608,
     /*  480174 */   GIR_EraseRootFromParent_Done,
     /*  480175 */ // Label 7241: @480175
     /*  480175 */ GIM_Try, /*On fail goto*//*Label 7242*/ GIMT_Encode4(480239), // Rule ID 12609 //
     /*  480180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  480183 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480186 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480190 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  480197 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480204 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480208 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480215 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480215 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  480218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480223 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480230 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480233 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480237 */   GIR_RootConstrainSelectedInstOperands,
     /*  480238 */   // GIR_Coverage, 12609,
     /*  480238 */   GIR_EraseRootFromParent_Done,
     /*  480239 */ // Label 7242: @480239
     /*  480239 */ GIM_Try, /*On fail goto*//*Label 7243*/ GIMT_Encode4(480303), // Rule ID 12610 //
     /*  480244 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  480247 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480250 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480254 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  480261 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480272 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480279 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  480282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480287 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480294 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480297 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480301 */   GIR_RootConstrainSelectedInstOperands,
     /*  480302 */   // GIR_Coverage, 12610,
     /*  480302 */   GIR_EraseRootFromParent_Done,
     /*  480303 */ // Label 7243: @480303
     /*  480303 */ GIM_Try, /*On fail goto*//*Label 7244*/ GIMT_Encode4(480367), // Rule ID 12611 //
     /*  480308 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  480311 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480314 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480318 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  480325 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480343 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  480346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480351 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480358 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480361 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480365 */   GIR_RootConstrainSelectedInstOperands,
     /*  480366 */   // GIR_Coverage, 12611,
     /*  480366 */   GIR_EraseRootFromParent_Done,
     /*  480367 */ // Label 7244: @480367
     /*  480367 */ GIM_Try, /*On fail goto*//*Label 7245*/ GIMT_Encode4(480431), // Rule ID 12612 //
     /*  480372 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  480375 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480378 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480382 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  480389 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480407 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
     /*  480410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480415 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480429 */   GIR_RootConstrainSelectedInstOperands,
     /*  480430 */   // GIR_Coverage, 12612,
     /*  480430 */   GIR_EraseRootFromParent_Done,
     /*  480431 */ // Label 7245: @480431
     /*  480431 */ GIM_Try, /*On fail goto*//*Label 7246*/ GIMT_Encode4(480495), // Rule ID 12618 //
     /*  480436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  480439 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480442 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480446 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  480453 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480471 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  480474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480479 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480486 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480489 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480493 */   GIR_RootConstrainSelectedInstOperands,
     /*  480494 */   // GIR_Coverage, 12618,
     /*  480494 */   GIR_EraseRootFromParent_Done,
     /*  480495 */ // Label 7246: @480495
     /*  480495 */ GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(480559), // Rule ID 12619 //
     /*  480500 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  480503 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480506 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480510 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  480517 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480535 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  480538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480543 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480557 */   GIR_RootConstrainSelectedInstOperands,
     /*  480558 */   // GIR_Coverage, 12619,
     /*  480558 */   GIR_EraseRootFromParent_Done,
     /*  480559 */ // Label 7247: @480559
     /*  480559 */ GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(480623), // Rule ID 12620 //
     /*  480564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  480567 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480570 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480574 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  480581 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480588 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480592 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480599 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  480602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480607 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480614 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480617 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480621 */   GIR_RootConstrainSelectedInstOperands,
     /*  480622 */   // GIR_Coverage, 12620,
     /*  480622 */   GIR_EraseRootFromParent_Done,
     /*  480623 */ // Label 7248: @480623
     /*  480623 */ GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(480687), // Rule ID 12621 //
     /*  480628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  480631 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480634 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480638 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  480645 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480652 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480656 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480663 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  480666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480671 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480678 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480681 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480685 */   GIR_RootConstrainSelectedInstOperands,
     /*  480686 */   // GIR_Coverage, 12621,
     /*  480686 */   GIR_EraseRootFromParent_Done,
     /*  480687 */ // Label 7249: @480687
     /*  480687 */ GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(480751), // Rule ID 12622 //
     /*  480692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  480695 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480698 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  480702 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  480709 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480716 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480720 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480727 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
     /*  480730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480735 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480742 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480745 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480749 */   GIR_RootConstrainSelectedInstOperands,
     /*  480750 */   // GIR_Coverage, 12622,
     /*  480750 */   GIR_EraseRootFromParent_Done,
     /*  480751 */ // Label 7250: @480751
     /*  480751 */ GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(480804), // Rule ID 9376 //
     /*  480756 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  480759 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480762 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480769 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480773 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480780 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480780 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480788 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480795 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480798 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480802 */   GIR_RootConstrainSelectedInstOperands,
     /*  480803 */   // GIR_Coverage, 9376,
     /*  480803 */   GIR_EraseRootFromParent_Done,
     /*  480804 */ // Label 7251: @480804
     /*  480804 */ GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(480857), // Rule ID 9377 //
     /*  480809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  480812 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480815 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480826 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480833 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480841 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480855 */   GIR_RootConstrainSelectedInstOperands,
     /*  480856 */   // GIR_Coverage, 9377,
     /*  480856 */   GIR_EraseRootFromParent_Done,
     /*  480857 */ // Label 7252: @480857
     /*  480857 */ GIM_Try, /*On fail goto*//*Label 7253*/ GIMT_Encode4(480910), // Rule ID 9378 //
     /*  480862 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  480865 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480868 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480875 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480879 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480886 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480894 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480901 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480904 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480908 */   GIR_RootConstrainSelectedInstOperands,
     /*  480909 */   // GIR_Coverage, 9378,
     /*  480909 */   GIR_EraseRootFromParent_Done,
     /*  480910 */ // Label 7253: @480910
     /*  480910 */ GIM_Try, /*On fail goto*//*Label 7254*/ GIMT_Encode4(480963), // Rule ID 9379 //
     /*  480915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  480918 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480921 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480928 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480932 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480939 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480939 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  480947 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  480949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  480954 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  480957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  480961 */   GIR_RootConstrainSelectedInstOperands,
     /*  480962 */   // GIR_Coverage, 9379,
     /*  480962 */   GIR_EraseRootFromParent_Done,
     /*  480963 */ // Label 7254: @480963
     /*  480963 */ GIM_Try, /*On fail goto*//*Label 7255*/ GIMT_Encode4(481016), // Rule ID 9380 //
     /*  480968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  480971 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  480974 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  480981 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  480985 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  480992 */   // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  480992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  480995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  481000 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  481007 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  481010 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481014 */   GIR_RootConstrainSelectedInstOperands,
     /*  481015 */   // GIR_Coverage, 9380,
     /*  481015 */   GIR_EraseRootFromParent_Done,
     /*  481016 */ // Label 7255: @481016
     /*  481016 */ GIM_Try, /*On fail goto*//*Label 7256*/ GIMT_Encode4(481069), // Rule ID 12128 //
     /*  481021 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  481024 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  481027 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  481034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  481045 */   // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  481045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  481048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  481053 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  481060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  481063 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481067 */   GIR_RootConstrainSelectedInstOperands,
     /*  481068 */   // GIR_Coverage, 12128,
     /*  481068 */   GIR_EraseRootFromParent_Done,
     /*  481069 */ // Label 7256: @481069
     /*  481069 */ GIM_Try, /*On fail goto*//*Label 7257*/ GIMT_Encode4(481122), // Rule ID 12129 //
     /*  481074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  481077 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  481080 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  481087 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481091 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  481098 */   // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  481098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  481101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  481106 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481108 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  481113 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  481116 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481120 */   GIR_RootConstrainSelectedInstOperands,
     /*  481121 */   // GIR_Coverage, 12129,
     /*  481121 */   GIR_EraseRootFromParent_Done,
     /*  481122 */ // Label 7257: @481122
     /*  481122 */ GIM_Try, /*On fail goto*//*Label 7258*/ GIMT_Encode4(481175), // Rule ID 12130 //
     /*  481127 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  481130 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  481133 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  481140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  481151 */   // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  481151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  481154 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  481159 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  481166 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  481169 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481173 */   GIR_RootConstrainSelectedInstOperands,
     /*  481174 */   // GIR_Coverage, 12130,
     /*  481174 */   GIR_EraseRootFromParent_Done,
     /*  481175 */ // Label 7258: @481175
     /*  481175 */ GIM_Try, /*On fail goto*//*Label 7259*/ GIMT_Encode4(481228), // Rule ID 12131 //
     /*  481180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  481183 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  481186 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  481193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481197 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  481204 */   // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  481204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  481207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  481212 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  481219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  481222 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481226 */   GIR_RootConstrainSelectedInstOperands,
     /*  481227 */   // GIR_Coverage, 12131,
     /*  481227 */   GIR_EraseRootFromParent_Done,
     /*  481228 */ // Label 7259: @481228
     /*  481228 */ GIM_Try, /*On fail goto*//*Label 7260*/ GIMT_Encode4(481281), // Rule ID 12132 //
     /*  481233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  481236 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  481239 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  481246 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481250 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  481257 */   // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  481257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  481260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  481265 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  481272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  481275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481279 */   GIR_RootConstrainSelectedInstOperands,
     /*  481280 */   // GIR_Coverage, 12132,
     /*  481280 */   GIR_EraseRootFromParent_Done,
     /*  481281 */ // Label 7260: @481281
     /*  481281 */ GIM_Try, /*On fail goto*//*Label 7261*/ GIMT_Encode4(481347), // Rule ID 10431 //
     /*  481286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  481289 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  481299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481305 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481309 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481316 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  481319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481324 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481341 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481345 */   GIR_RootConstrainSelectedInstOperands,
     /*  481346 */   // GIR_Coverage, 10431,
     /*  481346 */   GIR_EraseRootFromParent_Done,
     /*  481347 */ // Label 7261: @481347
     /*  481347 */ GIM_Try, /*On fail goto*//*Label 7262*/ GIMT_Encode4(481413), // Rule ID 10432 //
     /*  481352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  481355 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481358 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  481365 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481371 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481375 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481382 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  481385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481390 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481411 */   GIR_RootConstrainSelectedInstOperands,
     /*  481412 */   // GIR_Coverage, 10432,
     /*  481412 */   GIR_EraseRootFromParent_Done,
     /*  481413 */ // Label 7262: @481413
     /*  481413 */ GIM_Try, /*On fail goto*//*Label 7263*/ GIMT_Encode4(481479), // Rule ID 10433 //
     /*  481418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  481421 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481424 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  481431 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481448 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  481451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481456 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481477 */   GIR_RootConstrainSelectedInstOperands,
     /*  481478 */   // GIR_Coverage, 10433,
     /*  481478 */   GIR_EraseRootFromParent_Done,
     /*  481479 */ // Label 7263: @481479
     /*  481479 */ GIM_Try, /*On fail goto*//*Label 7264*/ GIMT_Encode4(481545), // Rule ID 10434 //
     /*  481484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  481487 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481490 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  481497 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481503 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481507 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481514 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  481517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481522 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481543 */   GIR_RootConstrainSelectedInstOperands,
     /*  481544 */   // GIR_Coverage, 10434,
     /*  481544 */   GIR_EraseRootFromParent_Done,
     /*  481545 */ // Label 7264: @481545
     /*  481545 */ GIM_Try, /*On fail goto*//*Label 7265*/ GIMT_Encode4(481611), // Rule ID 10435 //
     /*  481550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  481553 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481556 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  481563 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481569 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481573 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481580 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  481583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481588 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481595 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481605 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481609 */   GIR_RootConstrainSelectedInstOperands,
     /*  481610 */   // GIR_Coverage, 10435,
     /*  481610 */   GIR_EraseRootFromParent_Done,
     /*  481611 */ // Label 7265: @481611
     /*  481611 */ GIM_Try, /*On fail goto*//*Label 7266*/ GIMT_Encode4(481677), // Rule ID 10471 //
     /*  481616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  481619 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481622 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  481629 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481635 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481639 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481646 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  481649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481654 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481671 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481675 */   GIR_RootConstrainSelectedInstOperands,
     /*  481676 */   // GIR_Coverage, 10471,
     /*  481676 */   GIR_EraseRootFromParent_Done,
     /*  481677 */ // Label 7266: @481677
     /*  481677 */ GIM_Try, /*On fail goto*//*Label 7267*/ GIMT_Encode4(481743), // Rule ID 10472 //
     /*  481682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  481685 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481688 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  481695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481705 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481712 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  481715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481720 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481741 */   GIR_RootConstrainSelectedInstOperands,
     /*  481742 */   // GIR_Coverage, 10472,
     /*  481742 */   GIR_EraseRootFromParent_Done,
     /*  481743 */ // Label 7267: @481743
     /*  481743 */ GIM_Try, /*On fail goto*//*Label 7268*/ GIMT_Encode4(481809), // Rule ID 10473 //
     /*  481748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  481751 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481754 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  481761 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481778 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  481781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481786 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481807 */   GIR_RootConstrainSelectedInstOperands,
     /*  481808 */   // GIR_Coverage, 10473,
     /*  481808 */   GIR_EraseRootFromParent_Done,
     /*  481809 */ // Label 7268: @481809
     /*  481809 */ GIM_Try, /*On fail goto*//*Label 7269*/ GIMT_Encode4(481875), // Rule ID 10474 //
     /*  481814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  481817 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481820 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  481827 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481833 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481837 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481844 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481844 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  481847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481852 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481869 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481873 */   GIR_RootConstrainSelectedInstOperands,
     /*  481874 */   // GIR_Coverage, 10474,
     /*  481874 */   GIR_EraseRootFromParent_Done,
     /*  481875 */ // Label 7269: @481875
     /*  481875 */ GIM_Try, /*On fail goto*//*Label 7270*/ GIMT_Encode4(481941), // Rule ID 10475 //
     /*  481880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  481883 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481886 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  481893 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481899 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481903 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481910 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  481913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481918 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481930 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  481935 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  481939 */   GIR_RootConstrainSelectedInstOperands,
     /*  481940 */   // GIR_Coverage, 10475,
     /*  481940 */   GIR_EraseRootFromParent_Done,
     /*  481941 */ // Label 7270: @481941
     /*  481941 */ GIM_Try, /*On fail goto*//*Label 7271*/ GIMT_Encode4(482007), // Rule ID 10481 //
     /*  481946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  481949 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  481952 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  481959 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  481965 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  481969 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  481976 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  481976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  481979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  481984 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  481986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  481991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  481996 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482001 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482005 */   GIR_RootConstrainSelectedInstOperands,
     /*  482006 */   // GIR_Coverage, 10481,
     /*  482006 */   GIR_EraseRootFromParent_Done,
     /*  482007 */ // Label 7271: @482007
     /*  482007 */ GIM_Try, /*On fail goto*//*Label 7272*/ GIMT_Encode4(482073), // Rule ID 10482 //
     /*  482012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  482015 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  482018 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482025 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482031 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482035 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482042 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482050 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482067 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482071 */   GIR_RootConstrainSelectedInstOperands,
     /*  482072 */   // GIR_Coverage, 10482,
     /*  482072 */   GIR_EraseRootFromParent_Done,
     /*  482073 */ // Label 7272: @482073
     /*  482073 */ GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(482139), // Rule ID 10483 //
     /*  482078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  482081 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  482084 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482091 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482108 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482108 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482116 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482123 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482133 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482137 */   GIR_RootConstrainSelectedInstOperands,
     /*  482138 */   // GIR_Coverage, 10483,
     /*  482138 */   GIR_EraseRootFromParent_Done,
     /*  482139 */ // Label 7273: @482139
     /*  482139 */ GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(482205), // Rule ID 10484 //
     /*  482144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  482147 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  482150 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482163 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482167 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482174 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482174 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482182 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482199 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482203 */   GIR_RootConstrainSelectedInstOperands,
     /*  482204 */   // GIR_Coverage, 10484,
     /*  482204 */   GIR_EraseRootFromParent_Done,
     /*  482205 */ // Label 7274: @482205
     /*  482205 */ GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(482271), // Rule ID 10485 //
     /*  482210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  482213 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  482216 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482223 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482229 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482233 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482240 */   // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482240 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482248 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482265 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482269 */   GIR_RootConstrainSelectedInstOperands,
     /*  482270 */   // GIR_Coverage, 10485,
     /*  482270 */   GIR_EraseRootFromParent_Done,
     /*  482271 */ // Label 7275: @482271
     /*  482271 */ GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(482341), // Rule ID 9941 //
     /*  482276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  482279 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482282 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482286 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  482293 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482299 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482303 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482310 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482310 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  482313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482318 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482335 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482339 */   GIR_RootConstrainSelectedInstOperands,
     /*  482340 */   // GIR_Coverage, 9941,
     /*  482340 */   GIR_EraseRootFromParent_Done,
     /*  482341 */ // Label 7276: @482341
     /*  482341 */ GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(482411), // Rule ID 9942 //
     /*  482346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  482349 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482352 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482356 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  482363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482369 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482373 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482380 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482380 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  482383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482388 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482405 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482409 */   GIR_RootConstrainSelectedInstOperands,
     /*  482410 */   // GIR_Coverage, 9942,
     /*  482410 */   GIR_EraseRootFromParent_Done,
     /*  482411 */ // Label 7277: @482411
     /*  482411 */ GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(482481), // Rule ID 9943 //
     /*  482416 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  482419 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482422 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482426 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  482433 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482439 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482443 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482450 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482450 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  482453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482458 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482479 */   GIR_RootConstrainSelectedInstOperands,
     /*  482480 */   // GIR_Coverage, 9943,
     /*  482480 */   GIR_EraseRootFromParent_Done,
     /*  482481 */ // Label 7278: @482481
     /*  482481 */ GIM_Try, /*On fail goto*//*Label 7279*/ GIMT_Encode4(482551), // Rule ID 9944 //
     /*  482486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  482489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482492 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  482503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482509 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482513 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482520 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  482523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482528 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482549 */   GIR_RootConstrainSelectedInstOperands,
     /*  482550 */   // GIR_Coverage, 9944,
     /*  482550 */   GIR_EraseRootFromParent_Done,
     /*  482551 */ // Label 7279: @482551
     /*  482551 */ GIM_Try, /*On fail goto*//*Label 7280*/ GIMT_Encode4(482621), // Rule ID 9945 //
     /*  482556 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  482559 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482562 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482566 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  482573 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482579 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482583 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482590 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482590 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_SADDR),
     /*  482593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482598 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482619 */   GIR_RootConstrainSelectedInstOperands,
     /*  482620 */   // GIR_Coverage, 9945,
     /*  482620 */   GIR_EraseRootFromParent_Done,
     /*  482621 */ // Label 7280: @482621
     /*  482621 */ GIM_Try, /*On fail goto*//*Label 7281*/ GIMT_Encode4(482691), // Rule ID 9951 //
     /*  482626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  482629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482632 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482636 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482660 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482668 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482689 */   GIR_RootConstrainSelectedInstOperands,
     /*  482690 */   // GIR_Coverage, 9951,
     /*  482690 */   GIR_EraseRootFromParent_Done,
     /*  482691 */ // Label 7281: @482691
     /*  482691 */ GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(482761), // Rule ID 9952 //
     /*  482696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  482699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482702 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482706 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482719 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482723 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482730 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482730 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482738 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482759 */   GIR_RootConstrainSelectedInstOperands,
     /*  482760 */   // GIR_Coverage, 9952,
     /*  482760 */   GIR_EraseRootFromParent_Done,
     /*  482761 */ // Label 7282: @482761
     /*  482761 */ GIM_Try, /*On fail goto*//*Label 7283*/ GIMT_Encode4(482831), // Rule ID 9953 //
     /*  482766 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  482769 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482772 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482776 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482789 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482793 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482800 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482800 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482803 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482808 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482825 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482829 */   GIR_RootConstrainSelectedInstOperands,
     /*  482830 */   // GIR_Coverage, 9953,
     /*  482830 */   GIR_EraseRootFromParent_Done,
     /*  482831 */ // Label 7283: @482831
     /*  482831 */ GIM_Try, /*On fail goto*//*Label 7284*/ GIMT_Encode4(482901), // Rule ID 9954 //
     /*  482836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  482839 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482842 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482846 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482853 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482859 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482863 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482870 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482878 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482895 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482899 */   GIR_RootConstrainSelectedInstOperands,
     /*  482900 */   // GIR_Coverage, 9954,
     /*  482900 */   GIR_EraseRootFromParent_Done,
     /*  482901 */ // Label 7284: @482901
     /*  482901 */ GIM_Try, /*On fail goto*//*Label 7285*/ GIMT_Encode4(482971), // Rule ID 9955 //
     /*  482906 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  482909 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482912 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  482916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  482923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482929 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482933 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482940 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_SADDR),
     /*  482943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  482948 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  482950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  482955 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  482960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  482965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  482969 */   GIR_RootConstrainSelectedInstOperands,
     /*  482970 */   // GIR_Coverage, 9955,
     /*  482970 */   GIR_EraseRootFromParent_Done,
     /*  482971 */ // Label 7285: @482971
     /*  482971 */ GIM_Try, /*On fail goto*//*Label 7286*/ GIMT_Encode4(483030), // Rule ID 9971 //
     /*  482976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  482979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  482982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  482988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  482992 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  482999 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  482999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483007 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483024 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483028 */   GIR_RootConstrainSelectedInstOperands,
     /*  483029 */   // GIR_Coverage, 9971,
     /*  483029 */   GIR_EraseRootFromParent_Done,
     /*  483030 */ // Label 7286: @483030
     /*  483030 */ GIM_Try, /*On fail goto*//*Label 7287*/ GIMT_Encode4(483089), // Rule ID 9972 //
     /*  483035 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  483038 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483041 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483058 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483066 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483087 */   GIR_RootConstrainSelectedInstOperands,
     /*  483088 */   // GIR_Coverage, 9972,
     /*  483088 */   GIR_EraseRootFromParent_Done,
     /*  483089 */ // Label 7287: @483089
     /*  483089 */ GIM_Try, /*On fail goto*//*Label 7288*/ GIMT_Encode4(483148), // Rule ID 9973 //
     /*  483094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  483097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483100 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483106 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483110 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483117 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483125 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483142 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483146 */   GIR_RootConstrainSelectedInstOperands,
     /*  483147 */   // GIR_Coverage, 9973,
     /*  483147 */   GIR_EraseRootFromParent_Done,
     /*  483148 */ // Label 7288: @483148
     /*  483148 */ GIM_Try, /*On fail goto*//*Label 7289*/ GIMT_Encode4(483207), // Rule ID 9974 //
     /*  483153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  483156 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483159 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483176 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483184 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483201 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483205 */   GIR_RootConstrainSelectedInstOperands,
     /*  483206 */   // GIR_Coverage, 9974,
     /*  483206 */   GIR_EraseRootFromParent_Done,
     /*  483207 */ // Label 7289: @483207
     /*  483207 */ GIM_Try, /*On fail goto*//*Label 7290*/ GIMT_Encode4(483266), // Rule ID 9975 //
     /*  483212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  483215 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483224 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483228 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483235 */   // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483235 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483238 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483243 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483260 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483264 */   GIR_RootConstrainSelectedInstOperands,
     /*  483265 */   // GIR_Coverage, 9975,
     /*  483265 */   GIR_EraseRootFromParent_Done,
     /*  483266 */ // Label 7290: @483266
     /*  483266 */ GIM_Try, /*On fail goto*//*Label 7291*/ GIMT_Encode4(483325), // Rule ID 9991 //
     /*  483271 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  483274 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483277 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483283 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483287 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483294 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483294 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483302 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483309 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483319 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483323 */   GIR_RootConstrainSelectedInstOperands,
     /*  483324 */   // GIR_Coverage, 9991,
     /*  483324 */   GIR_EraseRootFromParent_Done,
     /*  483325 */ // Label 7291: @483325
     /*  483325 */ GIM_Try, /*On fail goto*//*Label 7292*/ GIMT_Encode4(483384), // Rule ID 9992 //
     /*  483330 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  483333 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483336 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483342 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483346 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483353 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483361 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483382 */   GIR_RootConstrainSelectedInstOperands,
     /*  483383 */   // GIR_Coverage, 9992,
     /*  483383 */   GIR_EraseRootFromParent_Done,
     /*  483384 */ // Label 7292: @483384
     /*  483384 */ GIM_Try, /*On fail goto*//*Label 7293*/ GIMT_Encode4(483443), // Rule ID 9993 //
     /*  483389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  483392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483412 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483420 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483441 */   GIR_RootConstrainSelectedInstOperands,
     /*  483442 */   // GIR_Coverage, 9993,
     /*  483442 */   GIR_EraseRootFromParent_Done,
     /*  483443 */ // Label 7293: @483443
     /*  483443 */ GIM_Try, /*On fail goto*//*Label 7294*/ GIMT_Encode4(483502), // Rule ID 9994 //
     /*  483448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  483451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483454 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483460 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483464 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483471 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483471 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483479 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483496 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483500 */   GIR_RootConstrainSelectedInstOperands,
     /*  483501 */   // GIR_Coverage, 9994,
     /*  483501 */   GIR_EraseRootFromParent_Done,
     /*  483502 */ // Label 7294: @483502
     /*  483502 */ GIM_Try, /*On fail goto*//*Label 7295*/ GIMT_Encode4(483561), // Rule ID 9995 //
     /*  483507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  483510 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483513 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483519 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483523 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  483530 */   // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  483530 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  483533 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  483538 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  483540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  483545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  483550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  483555 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  483559 */   GIR_RootConstrainSelectedInstOperands,
     /*  483560 */   // GIR_Coverage, 9995,
     /*  483560 */   GIR_EraseRootFromParent_Done,
     /*  483561 */ // Label 7295: @483561
     /*  483561 */ GIM_Try, /*On fail goto*//*Label 7296*/ GIMT_Encode4(483649), // Rule ID 11602 //
     /*  483566 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode0),
     /*  483569 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483572 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  483576 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  483583 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483589 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  483593 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  483597 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  483601 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  483605 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  483609 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483613 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  483615 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  483622 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  483622 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI),
     /*  483625 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  483630 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  483634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  483639 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  483642 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  483647 */   GIR_RootConstrainSelectedInstOperands,
     /*  483648 */   // GIR_Coverage, 11602,
     /*  483648 */   GIR_EraseRootFromParent_Done,
     /*  483649 */ // Label 7296: @483649
     /*  483649 */ GIM_Try, /*On fail goto*//*Label 7297*/ GIMT_Encode4(483737), // Rule ID 11603 //
     /*  483654 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode1),
     /*  483657 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483660 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  483664 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  483671 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483677 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  483681 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  483685 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  483689 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  483693 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  483697 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483701 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  483703 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  483710 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  483710 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI),
     /*  483713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  483718 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  483722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  483727 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  483730 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  483735 */   GIR_RootConstrainSelectedInstOperands,
     /*  483736 */   // GIR_Coverage, 11603,
     /*  483736 */   GIR_EraseRootFromParent_Done,
     /*  483737 */ // Label 7297: @483737
     /*  483737 */ GIM_Try, /*On fail goto*//*Label 7298*/ GIMT_Encode4(483825), // Rule ID 11604 //
     /*  483742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode2),
     /*  483745 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483748 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  483752 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  483759 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483765 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  483769 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  483773 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  483777 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  483781 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  483785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483789 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  483791 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  483798 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  483798 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI),
     /*  483801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  483806 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  483810 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  483815 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  483818 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  483823 */   GIR_RootConstrainSelectedInstOperands,
     /*  483824 */   // GIR_Coverage, 11604,
     /*  483824 */   GIR_EraseRootFromParent_Done,
     /*  483825 */ // Label 7298: @483825
     /*  483825 */ GIM_Try, /*On fail goto*//*Label 7299*/ GIMT_Encode4(483913), // Rule ID 11605 //
     /*  483830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode3),
     /*  483833 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483836 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  483840 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  483847 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483853 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  483857 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  483861 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  483865 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  483869 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  483873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483877 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  483879 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  483886 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  483886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI),
     /*  483889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  483894 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  483898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  483903 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  483906 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  483911 */   GIR_RootConstrainSelectedInstOperands,
     /*  483912 */   // GIR_Coverage, 11605,
     /*  483912 */   GIR_EraseRootFromParent_Done,
     /*  483913 */ // Label 7299: @483913
     /*  483913 */ GIM_Try, /*On fail goto*//*Label 7300*/ GIMT_Encode4(484001), // Rule ID 11606 //
     /*  483918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode4),
     /*  483921 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  483924 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  483928 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  483935 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  483941 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  483945 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  483949 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  483953 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  483957 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  483961 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  483965 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  483967 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  483974 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  483974 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI),
     /*  483977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  483982 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  483986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  483991 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  483994 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  483999 */   GIR_RootConstrainSelectedInstOperands,
     /*  484000 */   // GIR_Coverage, 11606,
     /*  484000 */   GIR_EraseRootFromParent_Done,
     /*  484001 */ // Label 7300: @484001
     /*  484001 */ GIM_Try, /*On fail goto*//*Label 7301*/ GIMT_Encode4(484089), // Rule ID 11612 //
     /*  484006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode0),
     /*  484009 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  484012 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  484016 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484029 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  484033 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  484037 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  484041 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  484045 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  484049 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484053 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  484055 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484062 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484062 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI),
     /*  484065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484070 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  484074 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484079 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484082 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  484087 */   GIR_RootConstrainSelectedInstOperands,
     /*  484088 */   // GIR_Coverage, 11612,
     /*  484088 */   GIR_EraseRootFromParent_Done,
     /*  484089 */ // Label 7301: @484089
     /*  484089 */ GIM_Try, /*On fail goto*//*Label 7302*/ GIMT_Encode4(484177), // Rule ID 11613 //
     /*  484094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode1),
     /*  484097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  484100 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  484104 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484111 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484117 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  484121 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  484125 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  484129 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  484133 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  484137 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484141 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  484143 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484150 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI),
     /*  484153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484158 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  484162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484170 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  484175 */   GIR_RootConstrainSelectedInstOperands,
     /*  484176 */   // GIR_Coverage, 11613,
     /*  484176 */   GIR_EraseRootFromParent_Done,
     /*  484177 */ // Label 7302: @484177
     /*  484177 */ GIM_Try, /*On fail goto*//*Label 7303*/ GIMT_Encode4(484265), // Rule ID 11614 //
     /*  484182 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode2),
     /*  484185 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  484188 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  484192 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484199 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484205 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  484209 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  484213 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  484217 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  484221 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  484225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484229 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  484231 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484238 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI),
     /*  484241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484246 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  484250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484255 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484258 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  484263 */   GIR_RootConstrainSelectedInstOperands,
     /*  484264 */   // GIR_Coverage, 11614,
     /*  484264 */   GIR_EraseRootFromParent_Done,
     /*  484265 */ // Label 7303: @484265
     /*  484265 */ GIM_Try, /*On fail goto*//*Label 7304*/ GIMT_Encode4(484353), // Rule ID 11615 //
     /*  484270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode3),
     /*  484273 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  484276 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  484280 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484287 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484293 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  484297 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  484301 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  484305 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  484309 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  484313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484317 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  484319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484326 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI),
     /*  484329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484334 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  484338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484343 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484346 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  484351 */   GIR_RootConstrainSelectedInstOperands,
     /*  484352 */   // GIR_Coverage, 11615,
     /*  484352 */   GIR_EraseRootFromParent_Done,
     /*  484353 */ // Label 7304: @484353
     /*  484353 */ GIM_Try, /*On fail goto*//*Label 7305*/ GIMT_Encode4(484441), // Rule ID 11616 //
     /*  484358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore_HwMode4),
     /*  484361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  484364 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  484368 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484375 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484381 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /*  484385 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  484389 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  484393 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  484397 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /*  484401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484405 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  484407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484414 */   // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI),
     /*  484417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484422 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
     /*  484426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484431 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484434 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  484439 */   GIR_RootConstrainSelectedInstOperands,
     /*  484440 */   // GIR_Coverage, 11616,
     /*  484440 */   GIR_EraseRootFromParent_Done,
     /*  484441 */ // Label 7305: @484441
     /*  484441 */ GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(484500), // Rule ID 10426 //
     /*  484446 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  484449 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484452 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  484459 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484465 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484469 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484476 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484476 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  484479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484484 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484498 */   GIR_RootConstrainSelectedInstOperands,
     /*  484499 */   // GIR_Coverage, 10426,
     /*  484499 */   GIR_EraseRootFromParent_Done,
     /*  484500 */ // Label 7306: @484500
     /*  484500 */ GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(484559), // Rule ID 10427 //
     /*  484505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  484508 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484511 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  484518 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484535 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  484538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484543 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484557 */   GIR_RootConstrainSelectedInstOperands,
     /*  484558 */   // GIR_Coverage, 10427,
     /*  484558 */   GIR_EraseRootFromParent_Done,
     /*  484559 */ // Label 7307: @484559
     /*  484559 */ GIM_Try, /*On fail goto*//*Label 7308*/ GIMT_Encode4(484618), // Rule ID 10428 //
     /*  484564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  484567 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484570 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  484577 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484583 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484587 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484594 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  484597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484602 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484609 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484612 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484616 */   GIR_RootConstrainSelectedInstOperands,
     /*  484617 */   // GIR_Coverage, 10428,
     /*  484617 */   GIR_EraseRootFromParent_Done,
     /*  484618 */ // Label 7308: @484618
     /*  484618 */ GIM_Try, /*On fail goto*//*Label 7309*/ GIMT_Encode4(484677), // Rule ID 10429 //
     /*  484623 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  484626 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484629 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  484636 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484642 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484646 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484653 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  484656 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484661 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484671 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484675 */   GIR_RootConstrainSelectedInstOperands,
     /*  484676 */   // GIR_Coverage, 10429,
     /*  484676 */   GIR_EraseRootFromParent_Done,
     /*  484677 */ // Label 7309: @484677
     /*  484677 */ GIM_Try, /*On fail goto*//*Label 7310*/ GIMT_Encode4(484736), // Rule ID 10430 //
     /*  484682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  484685 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484688 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /*  484695 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484705 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484712 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  484715 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484720 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484727 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484730 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484734 */   GIR_RootConstrainSelectedInstOperands,
     /*  484735 */   // GIR_Coverage, 10430,
     /*  484735 */   GIR_EraseRootFromParent_Done,
     /*  484736 */ // Label 7310: @484736
     /*  484736 */ GIM_Try, /*On fail goto*//*Label 7311*/ GIMT_Encode4(484795), // Rule ID 10466 //
     /*  484741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  484744 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484760 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484764 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484771 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484771 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  484774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484779 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484786 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484789 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484793 */   GIR_RootConstrainSelectedInstOperands,
     /*  484794 */   // GIR_Coverage, 10466,
     /*  484794 */   GIR_EraseRootFromParent_Done,
     /*  484795 */ // Label 7311: @484795
     /*  484795 */ GIM_Try, /*On fail goto*//*Label 7312*/ GIMT_Encode4(484854), // Rule ID 10467 //
     /*  484800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  484803 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484806 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484813 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484819 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484823 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484830 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484830 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  484833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484838 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484845 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484848 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484852 */   GIR_RootConstrainSelectedInstOperands,
     /*  484853 */   // GIR_Coverage, 10467,
     /*  484853 */   GIR_EraseRootFromParent_Done,
     /*  484854 */ // Label 7312: @484854
     /*  484854 */ GIM_Try, /*On fail goto*//*Label 7313*/ GIMT_Encode4(484913), // Rule ID 10468 //
     /*  484859 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  484862 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484865 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484872 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484878 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484882 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484889 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484889 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  484892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484897 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484904 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484907 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484911 */   GIR_RootConstrainSelectedInstOperands,
     /*  484912 */   // GIR_Coverage, 10468,
     /*  484912 */   GIR_EraseRootFromParent_Done,
     /*  484913 */ // Label 7313: @484913
     /*  484913 */ GIM_Try, /*On fail goto*//*Label 7314*/ GIMT_Encode4(484972), // Rule ID 10469 //
     /*  484918 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  484921 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484924 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484931 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484937 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  484941 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  484948 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  484948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  484951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  484956 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  484958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  484963 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  484966 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  484970 */   GIR_RootConstrainSelectedInstOperands,
     /*  484971 */   // GIR_Coverage, 10469,
     /*  484971 */   GIR_EraseRootFromParent_Done,
     /*  484972 */ // Label 7314: @484972
     /*  484972 */ GIM_Try, /*On fail goto*//*Label 7315*/ GIMT_Encode4(485031), // Rule ID 10470 //
     /*  484977 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  484980 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  484983 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  484990 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  484996 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485000 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485007 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  485010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485015 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485022 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485029 */   GIR_RootConstrainSelectedInstOperands,
     /*  485030 */   // GIR_Coverage, 10470,
     /*  485030 */   GIR_EraseRootFromParent_Done,
     /*  485031 */ // Label 7315: @485031
     /*  485031 */ GIM_Try, /*On fail goto*//*Label 7316*/ GIMT_Encode4(485090), // Rule ID 10476 //
     /*  485036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  485039 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  485042 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485049 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485059 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485066 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485074 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485088 */   GIR_RootConstrainSelectedInstOperands,
     /*  485089 */   // GIR_Coverage, 10476,
     /*  485089 */   GIR_EraseRootFromParent_Done,
     /*  485090 */ // Label 7316: @485090
     /*  485090 */ GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(485149), // Rule ID 10477 //
     /*  485095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  485098 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  485101 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485114 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485118 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485125 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485125 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485128 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485133 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485143 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485147 */   GIR_RootConstrainSelectedInstOperands,
     /*  485148 */   // GIR_Coverage, 10477,
     /*  485148 */   GIR_EraseRootFromParent_Done,
     /*  485149 */ // Label 7317: @485149
     /*  485149 */ GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(485208), // Rule ID 10478 //
     /*  485154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  485157 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  485160 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485167 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485173 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485177 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485184 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485184 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485187 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485192 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485199 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485202 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485206 */   GIR_RootConstrainSelectedInstOperands,
     /*  485207 */   // GIR_Coverage, 10478,
     /*  485207 */   GIR_EraseRootFromParent_Done,
     /*  485208 */ // Label 7318: @485208
     /*  485208 */ GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(485267), // Rule ID 10479 //
     /*  485213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  485216 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  485219 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485232 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485236 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485243 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485251 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485258 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485261 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485265 */   GIR_RootConstrainSelectedInstOperands,
     /*  485266 */   // GIR_Coverage, 10479,
     /*  485266 */   GIR_EraseRootFromParent_Done,
     /*  485267 */ // Label 7319: @485267
     /*  485267 */ GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(485326), // Rule ID 10480 //
     /*  485272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  485275 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  485278 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485285 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485291 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485295 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485302 */   // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485302 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485310 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485317 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485320 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485324 */   GIR_RootConstrainSelectedInstOperands,
     /*  485325 */   // GIR_Coverage, 10480,
     /*  485325 */   GIR_EraseRootFromParent_Done,
     /*  485326 */ // Label 7320: @485326
     /*  485326 */ GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(485389), // Rule ID 9936 //
     /*  485331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  485334 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485337 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485341 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  485348 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485354 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485358 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485365 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  485368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485373 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485380 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485383 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485387 */   GIR_RootConstrainSelectedInstOperands,
     /*  485388 */   // GIR_Coverage, 9936,
     /*  485388 */   GIR_EraseRootFromParent_Done,
     /*  485389 */ // Label 7321: @485389
     /*  485389 */ GIM_Try, /*On fail goto*//*Label 7322*/ GIMT_Encode4(485452), // Rule ID 9937 //
     /*  485394 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  485397 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485400 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485404 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  485411 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485428 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  485431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485436 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485443 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485446 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485450 */   GIR_RootConstrainSelectedInstOperands,
     /*  485451 */   // GIR_Coverage, 9937,
     /*  485451 */   GIR_EraseRootFromParent_Done,
     /*  485452 */ // Label 7322: @485452
     /*  485452 */ GIM_Try, /*On fail goto*//*Label 7323*/ GIMT_Encode4(485515), // Rule ID 9938 //
     /*  485457 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  485460 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485463 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485467 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  485474 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485480 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485484 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485491 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  485494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485499 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485506 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485509 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485513 */   GIR_RootConstrainSelectedInstOperands,
     /*  485514 */   // GIR_Coverage, 9938,
     /*  485514 */   GIR_EraseRootFromParent_Done,
     /*  485515 */ // Label 7323: @485515
     /*  485515 */ GIM_Try, /*On fail goto*//*Label 7324*/ GIMT_Encode4(485578), // Rule ID 9939 //
     /*  485520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  485523 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485526 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485530 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  485537 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485543 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485547 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485554 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485554 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  485557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485562 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485576 */   GIR_RootConstrainSelectedInstOperands,
     /*  485577 */   // GIR_Coverage, 9939,
     /*  485577 */   GIR_EraseRootFromParent_Done,
     /*  485578 */ // Label 7324: @485578
     /*  485578 */ GIM_Try, /*On fail goto*//*Label 7325*/ GIMT_Encode4(485641), // Rule ID 9940 //
     /*  485583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  485586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485589 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485593 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /*  485600 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485617 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
     /*  485620 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485625 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485635 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485639 */   GIR_RootConstrainSelectedInstOperands,
     /*  485640 */   // GIR_Coverage, 9940,
     /*  485640 */   GIR_EraseRootFromParent_Done,
     /*  485641 */ // Label 7325: @485641
     /*  485641 */ GIM_Try, /*On fail goto*//*Label 7326*/ GIMT_Encode4(485704), // Rule ID 9946 //
     /*  485646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  485649 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485652 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485656 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485663 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485669 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485680 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485688 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485695 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485698 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485702 */   GIR_RootConstrainSelectedInstOperands,
     /*  485703 */   // GIR_Coverage, 9946,
     /*  485703 */   GIR_EraseRootFromParent_Done,
     /*  485704 */ // Label 7326: @485704
     /*  485704 */ GIM_Try, /*On fail goto*//*Label 7327*/ GIMT_Encode4(485767), // Rule ID 9947 //
     /*  485709 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  485712 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485715 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485719 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485726 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485732 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485736 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485743 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485751 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485765 */   GIR_RootConstrainSelectedInstOperands,
     /*  485766 */   // GIR_Coverage, 9947,
     /*  485766 */   GIR_EraseRootFromParent_Done,
     /*  485767 */ // Label 7327: @485767
     /*  485767 */ GIM_Try, /*On fail goto*//*Label 7328*/ GIMT_Encode4(485830), // Rule ID 9948 //
     /*  485772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  485775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485778 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485782 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485789 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485795 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485799 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485806 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485806 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485814 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485821 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485824 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485828 */   GIR_RootConstrainSelectedInstOperands,
     /*  485829 */   // GIR_Coverage, 9948,
     /*  485829 */   GIR_EraseRootFromParent_Done,
     /*  485830 */ // Label 7328: @485830
     /*  485830 */ GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(485893), // Rule ID 9949 //
     /*  485835 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  485838 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485841 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485845 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485852 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485858 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485869 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485877 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485891 */   GIR_RootConstrainSelectedInstOperands,
     /*  485892 */   // GIR_Coverage, 9949,
     /*  485892 */   GIR_EraseRootFromParent_Done,
     /*  485893 */ // Label 7329: @485893
     /*  485893 */ GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(485956), // Rule ID 9950 //
     /*  485898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  485901 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485904 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  485908 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /*  485915 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485921 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485925 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485932 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485932 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
     /*  485935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485940 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485947 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  485950 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  485954 */   GIR_RootConstrainSelectedInstOperands,
     /*  485955 */   // GIR_Coverage, 9950,
     /*  485955 */   GIR_EraseRootFromParent_Done,
     /*  485956 */ // Label 7330: @485956
     /*  485956 */ GIM_Try, /*On fail goto*//*Label 7331*/ GIMT_Encode4(486008), // Rule ID 9966 //
     /*  485961 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  485964 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  485967 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  485973 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  485977 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  485984 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  485984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  485987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  485992 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  485994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  485999 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486002 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486006 */   GIR_RootConstrainSelectedInstOperands,
     /*  486007 */   // GIR_Coverage, 9966,
     /*  486007 */   GIR_EraseRootFromParent_Done,
     /*  486008 */ // Label 7331: @486008
     /*  486008 */ GIM_Try, /*On fail goto*//*Label 7332*/ GIMT_Encode4(486060), // Rule ID 9967 //
     /*  486013 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  486016 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486019 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486025 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486029 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486036 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486036 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486044 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486051 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486054 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486058 */   GIR_RootConstrainSelectedInstOperands,
     /*  486059 */   // GIR_Coverage, 9967,
     /*  486059 */   GIR_EraseRootFromParent_Done,
     /*  486060 */ // Label 7332: @486060
     /*  486060 */ GIM_Try, /*On fail goto*//*Label 7333*/ GIMT_Encode4(486112), // Rule ID 9968 //
     /*  486065 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  486068 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486071 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486077 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486081 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486088 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486096 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486103 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486106 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486110 */   GIR_RootConstrainSelectedInstOperands,
     /*  486111 */   // GIR_Coverage, 9968,
     /*  486111 */   GIR_EraseRootFromParent_Done,
     /*  486112 */ // Label 7333: @486112
     /*  486112 */ GIM_Try, /*On fail goto*//*Label 7334*/ GIMT_Encode4(486164), // Rule ID 9969 //
     /*  486117 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  486120 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486123 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486129 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486133 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486140 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486148 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486155 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486162 */   GIR_RootConstrainSelectedInstOperands,
     /*  486163 */   // GIR_Coverage, 9969,
     /*  486163 */   GIR_EraseRootFromParent_Done,
     /*  486164 */ // Label 7334: @486164
     /*  486164 */ GIM_Try, /*On fail goto*//*Label 7335*/ GIMT_Encode4(486216), // Rule ID 9970 //
     /*  486169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  486172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486175 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486192 */   // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486200 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486210 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486214 */   GIR_RootConstrainSelectedInstOperands,
     /*  486215 */   // GIR_Coverage, 9970,
     /*  486215 */   GIR_EraseRootFromParent_Done,
     /*  486216 */ // Label 7335: @486216
     /*  486216 */ GIM_Try, /*On fail goto*//*Label 7336*/ GIMT_Encode4(486268), // Rule ID 9986 //
     /*  486221 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  486224 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486227 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486244 */   // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486252 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486266 */   GIR_RootConstrainSelectedInstOperands,
     /*  486267 */   // GIR_Coverage, 9986,
     /*  486267 */   GIR_EraseRootFromParent_Done,
     /*  486268 */ // Label 7336: @486268
     /*  486268 */ GIM_Try, /*On fail goto*//*Label 7337*/ GIMT_Encode4(486320), // Rule ID 9987 //
     /*  486273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  486276 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486296 */   // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486304 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486314 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486318 */   GIR_RootConstrainSelectedInstOperands,
     /*  486319 */   // GIR_Coverage, 9987,
     /*  486319 */   GIR_EraseRootFromParent_Done,
     /*  486320 */ // Label 7337: @486320
     /*  486320 */ GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(486372), // Rule ID 9988 //
     /*  486325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  486328 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486331 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486337 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486341 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486348 */   // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486356 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486370 */   GIR_RootConstrainSelectedInstOperands,
     /*  486371 */   // GIR_Coverage, 9988,
     /*  486371 */   GIR_EraseRootFromParent_Done,
     /*  486372 */ // Label 7338: @486372
     /*  486372 */ GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(486424), // Rule ID 9989 //
     /*  486377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  486380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486389 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486393 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486400 */   // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486408 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486415 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486418 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486422 */   GIR_RootConstrainSelectedInstOperands,
     /*  486423 */   // GIR_Coverage, 9989,
     /*  486423 */   GIR_EraseRootFromParent_Done,
     /*  486424 */ // Label 7339: @486424
     /*  486424 */ GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(486476), // Rule ID 9990 //
     /*  486429 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  486432 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486435 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  486441 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  486452 */   // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  486452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  486455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  486460 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  486462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486467 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486470 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486474 */   GIR_RootConstrainSelectedInstOperands,
     /*  486475 */   // GIR_Coverage, 9990,
     /*  486475 */   GIR_EraseRootFromParent_Done,
     /*  486476 */ // Label 7340: @486476
     /*  486476 */ GIM_Reject,
     /*  486477 */ // Label 5867: @486477
     /*  486477 */ GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(486541), // Rule ID 29953 //
     /*  486482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  486485 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486488 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486492 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486497 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486502 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486506 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486510 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486517 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486517 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486525 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486532 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486535 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486539 */   GIR_RootConstrainSelectedInstOperands,
     /*  486540 */   // GIR_Coverage, 29953,
     /*  486540 */   GIR_EraseRootFromParent_Done,
     /*  486541 */ // Label 7341: @486541
     /*  486541 */ GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(486605), // Rule ID 29954 //
     /*  486546 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  486549 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486552 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486570 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486581 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486589 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486603 */   GIR_RootConstrainSelectedInstOperands,
     /*  486604 */   // GIR_Coverage, 29954,
     /*  486604 */   GIR_EraseRootFromParent_Done,
     /*  486605 */ // Label 7342: @486605
     /*  486605 */ GIM_Try, /*On fail goto*//*Label 7343*/ GIMT_Encode4(486669), // Rule ID 29955 //
     /*  486610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  486613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486616 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486620 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486625 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486630 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486634 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486638 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486645 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486645 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486653 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486660 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486667 */   GIR_RootConstrainSelectedInstOperands,
     /*  486668 */   // GIR_Coverage, 29955,
     /*  486668 */   GIR_EraseRootFromParent_Done,
     /*  486669 */ // Label 7343: @486669
     /*  486669 */ GIM_Try, /*On fail goto*//*Label 7344*/ GIMT_Encode4(486733), // Rule ID 29956 //
     /*  486674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  486677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486680 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486694 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486698 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486702 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486709 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486709 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486717 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486724 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486727 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486731 */   GIR_RootConstrainSelectedInstOperands,
     /*  486732 */   // GIR_Coverage, 29956,
     /*  486732 */   GIR_EraseRootFromParent_Done,
     /*  486733 */ // Label 7344: @486733
     /*  486733 */ GIM_Try, /*On fail goto*//*Label 7345*/ GIMT_Encode4(486797), // Rule ID 29957 //
     /*  486738 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  486741 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486744 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486748 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486753 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486758 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486762 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486766 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486773 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486773 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486781 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486788 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486791 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486795 */   GIR_RootConstrainSelectedInstOperands,
     /*  486796 */   // GIR_Coverage, 29957,
     /*  486796 */   GIR_EraseRootFromParent_Done,
     /*  486797 */ // Label 7345: @486797
     /*  486797 */ GIM_Try, /*On fail goto*//*Label 7346*/ GIMT_Encode4(486861), // Rule ID 29973 //
     /*  486802 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  486805 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486808 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486812 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486817 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486826 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486830 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486837 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486845 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486859 */   GIR_RootConstrainSelectedInstOperands,
     /*  486860 */   // GIR_Coverage, 29973,
     /*  486860 */   GIR_EraseRootFromParent_Done,
     /*  486861 */ // Label 7346: @486861
     /*  486861 */ GIM_Try, /*On fail goto*//*Label 7347*/ GIMT_Encode4(486925), // Rule ID 29974 //
     /*  486866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  486869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486872 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486886 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486890 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486894 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486901 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486909 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486916 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486919 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486923 */   GIR_RootConstrainSelectedInstOperands,
     /*  486924 */   // GIR_Coverage, 29974,
     /*  486924 */   GIR_EraseRootFromParent_Done,
     /*  486925 */ // Label 7347: @486925
     /*  486925 */ GIM_Try, /*On fail goto*//*Label 7348*/ GIMT_Encode4(486989), // Rule ID 29975 //
     /*  486930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  486933 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  486936 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  486940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486945 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  486950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  486954 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  486958 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  486965 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  486965 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  486968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  486973 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  486975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  486980 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  486983 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  486987 */   GIR_RootConstrainSelectedInstOperands,
     /*  486988 */   // GIR_Coverage, 29975,
     /*  486988 */   GIR_EraseRootFromParent_Done,
     /*  486989 */ // Label 7348: @486989
     /*  486989 */ GIM_Try, /*On fail goto*//*Label 7349*/ GIMT_Encode4(487053), // Rule ID 29976 //
     /*  486994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  486997 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487000 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487014 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487018 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  487022 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487029 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487037 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487047 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487051 */   GIR_RootConstrainSelectedInstOperands,
     /*  487052 */   // GIR_Coverage, 29976,
     /*  487052 */   GIR_EraseRootFromParent_Done,
     /*  487053 */ // Label 7349: @487053
     /*  487053 */ GIM_Try, /*On fail goto*//*Label 7350*/ GIMT_Encode4(487117), // Rule ID 29977 //
     /*  487058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  487061 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487064 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487068 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487073 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487082 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  487086 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487093 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487093 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487101 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487108 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487111 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487115 */   GIR_RootConstrainSelectedInstOperands,
     /*  487116 */   // GIR_Coverage, 29977,
     /*  487116 */   GIR_EraseRootFromParent_Done,
     /*  487117 */ // Label 7350: @487117
     /*  487117 */ GIM_Try, /*On fail goto*//*Label 7351*/ GIMT_Encode4(487176), // Rule ID 29613 //
     /*  487122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  487125 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487128 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487132 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487137 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487141 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487145 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487152 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487152 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487160 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487167 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487170 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487174 */   GIR_RootConstrainSelectedInstOperands,
     /*  487175 */   // GIR_Coverage, 29613,
     /*  487175 */   GIR_EraseRootFromParent_Done,
     /*  487176 */ // Label 7351: @487176
     /*  487176 */ GIM_Try, /*On fail goto*//*Label 7352*/ GIMT_Encode4(487235), // Rule ID 29614 //
     /*  487181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  487184 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487187 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487191 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487196 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487200 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487204 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487211 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487211 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487219 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487226 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487229 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487233 */   GIR_RootConstrainSelectedInstOperands,
     /*  487234 */   // GIR_Coverage, 29614,
     /*  487234 */   GIR_EraseRootFromParent_Done,
     /*  487235 */ // Label 7352: @487235
     /*  487235 */ GIM_Try, /*On fail goto*//*Label 7353*/ GIMT_Encode4(487294), // Rule ID 29615 //
     /*  487240 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  487243 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487246 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487250 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487255 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487259 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487263 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487270 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487278 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487285 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487288 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487292 */   GIR_RootConstrainSelectedInstOperands,
     /*  487293 */   // GIR_Coverage, 29615,
     /*  487293 */   GIR_EraseRootFromParent_Done,
     /*  487294 */ // Label 7353: @487294
     /*  487294 */ GIM_Try, /*On fail goto*//*Label 7354*/ GIMT_Encode4(487353), // Rule ID 29616 //
     /*  487299 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  487302 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487305 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487309 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487314 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487318 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487322 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487329 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487337 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487344 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487347 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487351 */   GIR_RootConstrainSelectedInstOperands,
     /*  487352 */   // GIR_Coverage, 29616,
     /*  487352 */   GIR_EraseRootFromParent_Done,
     /*  487353 */ // Label 7354: @487353
     /*  487353 */ GIM_Try, /*On fail goto*//*Label 7355*/ GIMT_Encode4(487412), // Rule ID 29617 //
     /*  487358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  487361 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487364 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487368 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487373 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487377 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487381 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487388 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487396 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487403 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487406 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487410 */   GIR_RootConstrainSelectedInstOperands,
     /*  487411 */   // GIR_Coverage, 29617,
     /*  487411 */   GIR_EraseRootFromParent_Done,
     /*  487412 */ // Label 7355: @487412
     /*  487412 */ GIM_Try, /*On fail goto*//*Label 7356*/ GIMT_Encode4(487471), // Rule ID 29633 //
     /*  487417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  487420 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487423 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487427 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487432 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487436 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487440 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487447 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487455 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487462 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487465 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487469 */   GIR_RootConstrainSelectedInstOperands,
     /*  487470 */   // GIR_Coverage, 29633,
     /*  487470 */   GIR_EraseRootFromParent_Done,
     /*  487471 */ // Label 7356: @487471
     /*  487471 */ GIM_Try, /*On fail goto*//*Label 7357*/ GIMT_Encode4(487530), // Rule ID 29634 //
     /*  487476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  487479 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487482 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487486 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487491 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487495 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487499 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487506 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487506 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487514 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487521 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487524 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487528 */   GIR_RootConstrainSelectedInstOperands,
     /*  487529 */   // GIR_Coverage, 29634,
     /*  487529 */   GIR_EraseRootFromParent_Done,
     /*  487530 */ // Label 7357: @487530
     /*  487530 */ GIM_Try, /*On fail goto*//*Label 7358*/ GIMT_Encode4(487589), // Rule ID 29635 //
     /*  487535 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  487538 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487541 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487545 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487550 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487554 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487558 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487565 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487573 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487580 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487583 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487587 */   GIR_RootConstrainSelectedInstOperands,
     /*  487588 */   // GIR_Coverage, 29635,
     /*  487588 */   GIR_EraseRootFromParent_Done,
     /*  487589 */ // Label 7358: @487589
     /*  487589 */ GIM_Try, /*On fail goto*//*Label 7359*/ GIMT_Encode4(487648), // Rule ID 29636 //
     /*  487594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  487597 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487600 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487604 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487609 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487613 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487617 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487624 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487632 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487634 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487639 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487642 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487646 */   GIR_RootConstrainSelectedInstOperands,
     /*  487647 */   // GIR_Coverage, 29636,
     /*  487647 */   GIR_EraseRootFromParent_Done,
     /*  487648 */ // Label 7359: @487648
     /*  487648 */ GIM_Try, /*On fail goto*//*Label 7360*/ GIMT_Encode4(487707), // Rule ID 29637 //
     /*  487653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  487656 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487659 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  487663 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487668 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  487672 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487676 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487683 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  487686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487691 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487698 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487701 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487705 */   GIR_RootConstrainSelectedInstOperands,
     /*  487706 */   // GIR_Coverage, 29637,
     /*  487706 */   GIR_EraseRootFromParent_Done,
     /*  487707 */ // Label 7360: @487707
     /*  487707 */ GIM_Try, /*On fail goto*//*Label 7361*/ GIMT_Encode4(487767), // Rule ID 29958 //
     /*  487712 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  487715 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487723 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487728 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487732 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  487736 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487743 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  487746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487751 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487753 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487765 */   GIR_RootConstrainSelectedInstOperands,
     /*  487766 */   // GIR_Coverage, 29958,
     /*  487766 */   GIR_EraseRootFromParent_Done,
     /*  487767 */ // Label 7361: @487767
     /*  487767 */ GIM_Try, /*On fail goto*//*Label 7362*/ GIMT_Encode4(487827), // Rule ID 29959 //
     /*  487772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  487775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487778 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487788 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487792 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  487796 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487803 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487803 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  487806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487811 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487818 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487821 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487825 */   GIR_RootConstrainSelectedInstOperands,
     /*  487826 */   // GIR_Coverage, 29959,
     /*  487826 */   GIR_EraseRootFromParent_Done,
     /*  487827 */ // Label 7362: @487827
     /*  487827 */ GIM_Try, /*On fail goto*//*Label 7363*/ GIMT_Encode4(487887), // Rule ID 29960 //
     /*  487832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  487835 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487838 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487843 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487848 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487852 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  487856 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487863 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487863 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  487866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487871 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487873 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487878 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487881 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487885 */   GIR_RootConstrainSelectedInstOperands,
     /*  487886 */   // GIR_Coverage, 29960,
     /*  487886 */   GIR_EraseRootFromParent_Done,
     /*  487887 */ // Label 7363: @487887
     /*  487887 */ GIM_Try, /*On fail goto*//*Label 7364*/ GIMT_Encode4(487947), // Rule ID 29961 //
     /*  487892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  487895 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487903 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487908 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487912 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  487916 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487923 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  487926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487931 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487938 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  487941 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  487945 */   GIR_RootConstrainSelectedInstOperands,
     /*  487946 */   // GIR_Coverage, 29961,
     /*  487946 */   GIR_EraseRootFromParent_Done,
     /*  487947 */ // Label 7364: @487947
     /*  487947 */ GIM_Try, /*On fail goto*//*Label 7365*/ GIMT_Encode4(488007), // Rule ID 29962 //
     /*  487952 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  487955 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  487958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487963 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  487968 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  487972 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  487976 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  487983 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  487983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  487986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  487991 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  487993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  487998 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488001 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488005 */   GIR_RootConstrainSelectedInstOperands,
     /*  488006 */   // GIR_Coverage, 29962,
     /*  488006 */   GIR_EraseRootFromParent_Done,
     /*  488007 */ // Label 7365: @488007
     /*  488007 */ GIM_Try, /*On fail goto*//*Label 7366*/ GIMT_Encode4(488067), // Rule ID 29978 //
     /*  488012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  488015 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488018 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488023 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488032 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  488036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488043 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488051 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488058 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488065 */   GIR_RootConstrainSelectedInstOperands,
     /*  488066 */   // GIR_Coverage, 29978,
     /*  488066 */   GIR_EraseRootFromParent_Done,
     /*  488067 */ // Label 7366: @488067
     /*  488067 */ GIM_Try, /*On fail goto*//*Label 7367*/ GIMT_Encode4(488127), // Rule ID 29979 //
     /*  488072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  488075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488083 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488088 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488092 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  488096 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488103 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488111 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488118 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488121 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488125 */   GIR_RootConstrainSelectedInstOperands,
     /*  488126 */   // GIR_Coverage, 29979,
     /*  488126 */   GIR_EraseRootFromParent_Done,
     /*  488127 */ // Label 7367: @488127
     /*  488127 */ GIM_Try, /*On fail goto*//*Label 7368*/ GIMT_Encode4(488187), // Rule ID 29980 //
     /*  488132 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  488135 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488138 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488143 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488148 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488152 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  488156 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488163 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488171 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488178 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488181 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488185 */   GIR_RootConstrainSelectedInstOperands,
     /*  488186 */   // GIR_Coverage, 29980,
     /*  488186 */   GIR_EraseRootFromParent_Done,
     /*  488187 */ // Label 7368: @488187
     /*  488187 */ GIM_Try, /*On fail goto*//*Label 7369*/ GIMT_Encode4(488247), // Rule ID 29981 //
     /*  488192 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  488195 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488198 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488203 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488208 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488212 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  488216 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488223 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488231 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488238 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488241 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488245 */   GIR_RootConstrainSelectedInstOperands,
     /*  488246 */   // GIR_Coverage, 29981,
     /*  488246 */   GIR_EraseRootFromParent_Done,
     /*  488247 */ // Label 7369: @488247
     /*  488247 */ GIM_Try, /*On fail goto*//*Label 7370*/ GIMT_Encode4(488307), // Rule ID 29982 //
     /*  488252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  488255 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488258 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488268 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488272 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  488276 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488283 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488283 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488291 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488298 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488301 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488305 */   GIR_RootConstrainSelectedInstOperands,
     /*  488306 */   // GIR_Coverage, 29982,
     /*  488306 */   GIR_EraseRootFromParent_Done,
     /*  488307 */ // Label 7370: @488307
     /*  488307 */ GIM_Try, /*On fail goto*//*Label 7371*/ GIMT_Encode4(488362), // Rule ID 29618 //
     /*  488312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  488315 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488318 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488323 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488327 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488331 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488338 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488338 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488346 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488348 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488356 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488360 */   GIR_RootConstrainSelectedInstOperands,
     /*  488361 */   // GIR_Coverage, 29618,
     /*  488361 */   GIR_EraseRootFromParent_Done,
     /*  488362 */ // Label 7371: @488362
     /*  488362 */ GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(488417), // Rule ID 29619 //
     /*  488367 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  488370 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488373 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488378 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488382 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488386 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488393 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488401 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488415 */   GIR_RootConstrainSelectedInstOperands,
     /*  488416 */   // GIR_Coverage, 29619,
     /*  488416 */   GIR_EraseRootFromParent_Done,
     /*  488417 */ // Label 7372: @488417
     /*  488417 */ GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(488472), // Rule ID 29620 //
     /*  488422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  488425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488428 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488433 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488448 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488456 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488463 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488466 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488470 */   GIR_RootConstrainSelectedInstOperands,
     /*  488471 */   // GIR_Coverage, 29620,
     /*  488471 */   GIR_EraseRootFromParent_Done,
     /*  488472 */ // Label 7373: @488472
     /*  488472 */ GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(488527), // Rule ID 29621 //
     /*  488477 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  488480 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488483 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488488 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488492 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488496 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488503 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488511 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488518 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488521 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488525 */   GIR_RootConstrainSelectedInstOperands,
     /*  488526 */   // GIR_Coverage, 29621,
     /*  488526 */   GIR_EraseRootFromParent_Done,
     /*  488527 */ // Label 7374: @488527
     /*  488527 */ GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(488582), // Rule ID 29622 //
     /*  488532 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  488535 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488538 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488543 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488547 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488551 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488558 */   // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488558 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488566 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488573 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488576 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488580 */   GIR_RootConstrainSelectedInstOperands,
     /*  488581 */   // GIR_Coverage, 29622,
     /*  488581 */   GIR_EraseRootFromParent_Done,
     /*  488582 */ // Label 7375: @488582
     /*  488582 */ GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(488637), // Rule ID 29638 //
     /*  488587 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  488590 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488593 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488598 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488602 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488606 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488613 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488621 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488623 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488628 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488631 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488635 */   GIR_RootConstrainSelectedInstOperands,
     /*  488636 */   // GIR_Coverage, 29638,
     /*  488636 */   GIR_EraseRootFromParent_Done,
     /*  488637 */ // Label 7376: @488637
     /*  488637 */ GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(488692), // Rule ID 29639 //
     /*  488642 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  488645 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488648 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488653 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488657 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488661 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488668 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488676 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488683 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488690 */   GIR_RootConstrainSelectedInstOperands,
     /*  488691 */   // GIR_Coverage, 29639,
     /*  488691 */   GIR_EraseRootFromParent_Done,
     /*  488692 */ // Label 7377: @488692
     /*  488692 */ GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(488747), // Rule ID 29640 //
     /*  488697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  488700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488708 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488712 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488716 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488723 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488723 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488731 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488738 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488745 */   GIR_RootConstrainSelectedInstOperands,
     /*  488746 */   // GIR_Coverage, 29640,
     /*  488746 */   GIR_EraseRootFromParent_Done,
     /*  488747 */ // Label 7378: @488747
     /*  488747 */ GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(488802), // Rule ID 29641 //
     /*  488752 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  488755 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488758 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488763 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488778 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488786 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488793 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488796 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488800 */   GIR_RootConstrainSelectedInstOperands,
     /*  488801 */   // GIR_Coverage, 29641,
     /*  488801 */   GIR_EraseRootFromParent_Done,
     /*  488802 */ // Label 7379: @488802
     /*  488802 */ GIM_Try, /*On fail goto*//*Label 7380*/ GIMT_Encode4(488857), // Rule ID 29642 //
     /*  488807 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  488810 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488813 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  488818 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  488822 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488826 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  488833 */   // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  488833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  488836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  488841 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  488843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  488848 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  488851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488855 */   GIR_RootConstrainSelectedInstOperands,
     /*  488856 */   // GIR_Coverage, 29642,
     /*  488856 */   GIR_EraseRootFromParent_Done,
     /*  488857 */ // Label 7380: @488857
     /*  488857 */ GIM_Try, /*On fail goto*//*Label 7381*/ GIMT_Encode4(488915), // Rule ID 14317 //
     /*  488862 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  488865 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488868 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  488873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488877 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  488884 */   // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  488884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  488887 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  488889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  488894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  488899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  488904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  488909 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488913 */   GIR_RootConstrainSelectedInstOperands,
     /*  488914 */   // GIR_Coverage, 14317,
     /*  488914 */   GIR_EraseRootFromParent_Done,
     /*  488915 */ // Label 7381: @488915
     /*  488915 */ GIM_Try, /*On fail goto*//*Label 7382*/ GIMT_Encode4(488973), // Rule ID 14318 //
     /*  488920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  488923 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488926 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  488931 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488935 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  488942 */   // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  488942 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  488945 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  488947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  488952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  488957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  488962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  488967 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  488971 */   GIR_RootConstrainSelectedInstOperands,
     /*  488972 */   // GIR_Coverage, 14318,
     /*  488972 */   GIR_EraseRootFromParent_Done,
     /*  488973 */ // Label 7382: @488973
     /*  488973 */ GIM_Try, /*On fail goto*//*Label 7383*/ GIMT_Encode4(489031), // Rule ID 14319 //
     /*  488978 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  488981 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  488984 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  488989 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  488993 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489000 */   // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489003 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489020 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489029 */   GIR_RootConstrainSelectedInstOperands,
     /*  489030 */   // GIR_Coverage, 14319,
     /*  489030 */   GIR_EraseRootFromParent_Done,
     /*  489031 */ // Label 7383: @489031
     /*  489031 */ GIM_Try, /*On fail goto*//*Label 7384*/ GIMT_Encode4(489089), // Rule ID 14320 //
     /*  489036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  489039 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489042 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489058 */   // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489061 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489087 */   GIR_RootConstrainSelectedInstOperands,
     /*  489088 */   // GIR_Coverage, 14320,
     /*  489088 */   GIR_EraseRootFromParent_Done,
     /*  489089 */ // Label 7384: @489089
     /*  489089 */ GIM_Try, /*On fail goto*//*Label 7385*/ GIMT_Encode4(489147), // Rule ID 14321 //
     /*  489094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  489097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489100 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489105 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489109 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489116 */   // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489119 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489141 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489145 */   GIR_RootConstrainSelectedInstOperands,
     /*  489146 */   // GIR_Coverage, 14321,
     /*  489146 */   GIR_EraseRootFromParent_Done,
     /*  489147 */ // Label 7385: @489147
     /*  489147 */ GIM_Try, /*On fail goto*//*Label 7386*/ GIMT_Encode4(489205), // Rule ID 14347 //
     /*  489152 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  489155 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489158 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489163 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489167 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489174 */   // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489174 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489177 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489199 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489203 */   GIR_RootConstrainSelectedInstOperands,
     /*  489204 */   // GIR_Coverage, 14347,
     /*  489204 */   GIR_EraseRootFromParent_Done,
     /*  489205 */ // Label 7386: @489205
     /*  489205 */ GIM_Try, /*On fail goto*//*Label 7387*/ GIMT_Encode4(489263), // Rule ID 14348 //
     /*  489210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  489213 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489221 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489225 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489232 */   // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489235 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489257 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489261 */   GIR_RootConstrainSelectedInstOperands,
     /*  489262 */   // GIR_Coverage, 14348,
     /*  489262 */   GIR_EraseRootFromParent_Done,
     /*  489263 */ // Label 7387: @489263
     /*  489263 */ GIM_Try, /*On fail goto*//*Label 7388*/ GIMT_Encode4(489321), // Rule ID 14349 //
     /*  489268 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  489271 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489274 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489279 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489283 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489290 */   // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489290 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489293 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489315 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489319 */   GIR_RootConstrainSelectedInstOperands,
     /*  489320 */   // GIR_Coverage, 14349,
     /*  489320 */   GIR_EraseRootFromParent_Done,
     /*  489321 */ // Label 7388: @489321
     /*  489321 */ GIM_Try, /*On fail goto*//*Label 7389*/ GIMT_Encode4(489379), // Rule ID 14350 //
     /*  489326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  489329 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489332 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489337 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489341 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489348 */   // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489351 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489377 */   GIR_RootConstrainSelectedInstOperands,
     /*  489378 */   // GIR_Coverage, 14350,
     /*  489378 */   GIR_EraseRootFromParent_Done,
     /*  489379 */ // Label 7389: @489379
     /*  489379 */ GIM_Try, /*On fail goto*//*Label 7390*/ GIMT_Encode4(489437), // Rule ID 14351 //
     /*  489384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  489387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489390 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489395 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489399 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  489406 */   // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  489406 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  489409 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489411 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  489421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  489426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  489431 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489435 */   GIR_RootConstrainSelectedInstOperands,
     /*  489436 */   // GIR_Coverage, 14351,
     /*  489436 */   GIR_EraseRootFromParent_Done,
     /*  489437 */ // Label 7390: @489437
     /*  489437 */ GIM_Try, /*On fail goto*//*Label 7391*/ GIMT_Encode4(489488), // Rule ID 14312 //
     /*  489442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  489445 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489448 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489453 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489457 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489464 */   // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489467 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489474 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489479 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489482 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489486 */   GIR_RootConstrainSelectedInstOperands,
     /*  489487 */   // GIR_Coverage, 14312,
     /*  489487 */   GIR_EraseRootFromParent_Done,
     /*  489488 */ // Label 7391: @489488
     /*  489488 */ GIM_Try, /*On fail goto*//*Label 7392*/ GIMT_Encode4(489539), // Rule ID 14313 //
     /*  489493 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  489496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489504 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489508 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489515 */   // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489518 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489530 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489533 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489537 */   GIR_RootConstrainSelectedInstOperands,
     /*  489538 */   // GIR_Coverage, 14313,
     /*  489538 */   GIR_EraseRootFromParent_Done,
     /*  489539 */ // Label 7392: @489539
     /*  489539 */ GIM_Try, /*On fail goto*//*Label 7393*/ GIMT_Encode4(489590), // Rule ID 14314 //
     /*  489544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  489547 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489566 */   // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489569 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489581 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489584 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489588 */   GIR_RootConstrainSelectedInstOperands,
     /*  489589 */   // GIR_Coverage, 14314,
     /*  489589 */   GIR_EraseRootFromParent_Done,
     /*  489590 */ // Label 7393: @489590
     /*  489590 */ GIM_Try, /*On fail goto*//*Label 7394*/ GIMT_Encode4(489641), // Rule ID 14315 //
     /*  489595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  489598 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489601 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489606 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489610 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489617 */   // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489620 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489635 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489639 */   GIR_RootConstrainSelectedInstOperands,
     /*  489640 */   // GIR_Coverage, 14315,
     /*  489640 */   GIR_EraseRootFromParent_Done,
     /*  489641 */ // Label 7394: @489641
     /*  489641 */ GIM_Try, /*On fail goto*//*Label 7395*/ GIMT_Encode4(489692), // Rule ID 14316 //
     /*  489646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  489649 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489652 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489657 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489661 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489668 */   // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489671 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489683 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489686 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489690 */   GIR_RootConstrainSelectedInstOperands,
     /*  489691 */   // GIR_Coverage, 14316,
     /*  489691 */   GIR_EraseRootFromParent_Done,
     /*  489692 */ // Label 7395: @489692
     /*  489692 */ GIM_Try, /*On fail goto*//*Label 7396*/ GIMT_Encode4(489743), // Rule ID 14342 //
     /*  489697 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  489700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489703 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489719 */   // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489722 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489741 */   GIR_RootConstrainSelectedInstOperands,
     /*  489742 */   // GIR_Coverage, 14342,
     /*  489742 */   GIR_EraseRootFromParent_Done,
     /*  489743 */ // Label 7396: @489743
     /*  489743 */ GIM_Try, /*On fail goto*//*Label 7397*/ GIMT_Encode4(489794), // Rule ID 14343 //
     /*  489748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  489751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489759 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489763 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489770 */   // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489773 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489785 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489792 */   GIR_RootConstrainSelectedInstOperands,
     /*  489793 */   // GIR_Coverage, 14343,
     /*  489793 */   GIR_EraseRootFromParent_Done,
     /*  489794 */ // Label 7397: @489794
     /*  489794 */ GIM_Try, /*On fail goto*//*Label 7398*/ GIMT_Encode4(489845), // Rule ID 14344 //
     /*  489799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  489802 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489805 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489810 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489821 */   // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489824 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489843 */   GIR_RootConstrainSelectedInstOperands,
     /*  489844 */   // GIR_Coverage, 14344,
     /*  489844 */   GIR_EraseRootFromParent_Done,
     /*  489845 */ // Label 7398: @489845
     /*  489845 */ GIM_Try, /*On fail goto*//*Label 7399*/ GIMT_Encode4(489896), // Rule ID 14345 //
     /*  489850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  489853 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489861 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489865 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489872 */   // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489872 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489875 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489890 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489894 */   GIR_RootConstrainSelectedInstOperands,
     /*  489895 */   // GIR_Coverage, 14345,
     /*  489895 */   GIR_EraseRootFromParent_Done,
     /*  489896 */ // Label 7399: @489896
     /*  489896 */ GIM_Try, /*On fail goto*//*Label 7400*/ GIMT_Encode4(489947), // Rule ID 14346 //
     /*  489901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  489904 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489907 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489912 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489916 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  489923 */   // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  489923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  489926 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  489933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489938 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489941 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489945 */   GIR_RootConstrainSelectedInstOperands,
     /*  489946 */   // GIR_Coverage, 14346,
     /*  489946 */   GIR_EraseRootFromParent_Done,
     /*  489947 */ // Label 7400: @489947
     /*  489947 */ GIM_Try, /*On fail goto*//*Label 7401*/ GIMT_Encode4(489998), // Rule ID 14307 //
     /*  489952 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  489955 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  489958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  489963 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  489967 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  489974 */   // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  489974 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  489977 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  489979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  489984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  489989 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  489992 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  489996 */   GIR_RootConstrainSelectedInstOperands,
     /*  489997 */   // GIR_Coverage, 14307,
     /*  489997 */   GIR_EraseRootFromParent_Done,
     /*  489998 */ // Label 7401: @489998
     /*  489998 */ GIM_Try, /*On fail goto*//*Label 7402*/ GIMT_Encode4(490049), // Rule ID 14308 //
     /*  490003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  490006 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490009 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490014 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490018 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490025 */   // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490025 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490028 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490035 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490040 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490047 */   GIR_RootConstrainSelectedInstOperands,
     /*  490048 */   // GIR_Coverage, 14308,
     /*  490048 */   GIR_EraseRootFromParent_Done,
     /*  490049 */ // Label 7402: @490049
     /*  490049 */ GIM_Try, /*On fail goto*//*Label 7403*/ GIMT_Encode4(490100), // Rule ID 14309 //
     /*  490054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  490057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490065 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490069 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490076 */   // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490079 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490091 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490094 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490098 */   GIR_RootConstrainSelectedInstOperands,
     /*  490099 */   // GIR_Coverage, 14309,
     /*  490099 */   GIR_EraseRootFromParent_Done,
     /*  490100 */ // Label 7403: @490100
     /*  490100 */ GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(490151), // Rule ID 14310 //
     /*  490105 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  490108 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490111 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490116 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490120 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490127 */   // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490130 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490142 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490145 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490149 */   GIR_RootConstrainSelectedInstOperands,
     /*  490150 */   // GIR_Coverage, 14310,
     /*  490150 */   GIR_EraseRootFromParent_Done,
     /*  490151 */ // Label 7404: @490151
     /*  490151 */ GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(490202), // Rule ID 14311 //
     /*  490156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  490159 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490167 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490171 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490178 */   // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490178 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490181 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490196 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490200 */   GIR_RootConstrainSelectedInstOperands,
     /*  490201 */   // GIR_Coverage, 14311,
     /*  490201 */   GIR_EraseRootFromParent_Done,
     /*  490202 */ // Label 7405: @490202
     /*  490202 */ GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(490253), // Rule ID 14337 //
     /*  490207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  490210 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490213 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490218 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490229 */   // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490232 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490251 */   GIR_RootConstrainSelectedInstOperands,
     /*  490252 */   // GIR_Coverage, 14337,
     /*  490252 */   GIR_EraseRootFromParent_Done,
     /*  490253 */ // Label 7406: @490253
     /*  490253 */ GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(490304), // Rule ID 14338 //
     /*  490258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  490261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490269 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490273 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490280 */   // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490283 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490295 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490298 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490302 */   GIR_RootConstrainSelectedInstOperands,
     /*  490303 */   // GIR_Coverage, 14338,
     /*  490303 */   GIR_EraseRootFromParent_Done,
     /*  490304 */ // Label 7407: @490304
     /*  490304 */ GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(490355), // Rule ID 14339 //
     /*  490309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  490312 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490315 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490320 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490324 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490331 */   // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490331 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490334 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490346 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490349 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490353 */   GIR_RootConstrainSelectedInstOperands,
     /*  490354 */   // GIR_Coverage, 14339,
     /*  490354 */   GIR_EraseRootFromParent_Done,
     /*  490355 */ // Label 7408: @490355
     /*  490355 */ GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(490406), // Rule ID 14340 //
     /*  490360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  490363 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490366 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490371 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490375 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490382 */   // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490385 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490397 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490400 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490404 */   GIR_RootConstrainSelectedInstOperands,
     /*  490405 */   // GIR_Coverage, 14340,
     /*  490405 */   GIR_EraseRootFromParent_Done,
     /*  490406 */ // Label 7409: @490406
     /*  490406 */ GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(490457), // Rule ID 14341 //
     /*  490411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  490414 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  490422 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490426 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  490433 */   // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  490433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  490436 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  490438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  490443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  490448 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490451 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490455 */   GIR_RootConstrainSelectedInstOperands,
     /*  490456 */   // GIR_Coverage, 14341,
     /*  490456 */   GIR_EraseRootFromParent_Done,
     /*  490457 */ // Label 7410: @490457
     /*  490457 */ GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(490530), // Rule ID 25671 //
     /*  490462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  490465 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  490468 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  490475 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490482 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490486 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490493 */   // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  490493 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490496 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  490498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490518 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490521 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490524 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490528 */   GIR_RootConstrainSelectedInstOperands,
     /*  490529 */   // GIR_Coverage, 25671,
     /*  490529 */   GIR_EraseRootFromParent_Done,
     /*  490530 */ // Label 7411: @490530
     /*  490530 */ GIM_Try, /*On fail goto*//*Label 7412*/ GIMT_Encode4(490603), // Rule ID 25672 //
     /*  490535 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  490538 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  490541 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  490548 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490555 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490559 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490566 */   // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  490566 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490569 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  490571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490591 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490594 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490597 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490601 */   GIR_RootConstrainSelectedInstOperands,
     /*  490602 */   // GIR_Coverage, 25672,
     /*  490602 */   GIR_EraseRootFromParent_Done,
     /*  490603 */ // Label 7412: @490603
     /*  490603 */ GIM_Try, /*On fail goto*//*Label 7413*/ GIMT_Encode4(490676), // Rule ID 25673 //
     /*  490608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  490611 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  490614 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  490621 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490628 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490632 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490639 */   // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  490639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490642 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  490644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490664 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490667 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490670 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490674 */   GIR_RootConstrainSelectedInstOperands,
     /*  490675 */   // GIR_Coverage, 25673,
     /*  490675 */   GIR_EraseRootFromParent_Done,
     /*  490676 */ // Label 7413: @490676
     /*  490676 */ GIM_Try, /*On fail goto*//*Label 7414*/ GIMT_Encode4(490749), // Rule ID 25674 //
     /*  490681 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  490684 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  490687 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  490694 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490705 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490712 */   // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  490712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490715 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  490717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490737 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490740 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490743 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490747 */   GIR_RootConstrainSelectedInstOperands,
     /*  490748 */   // GIR_Coverage, 25674,
     /*  490748 */   GIR_EraseRootFromParent_Done,
     /*  490749 */ // Label 7414: @490749
     /*  490749 */ GIM_Try, /*On fail goto*//*Label 7415*/ GIMT_Encode4(490822), // Rule ID 25675 //
     /*  490754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  490757 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  490760 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  490767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490774 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490778 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490785 */   // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
     /*  490785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490788 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /*  490790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490810 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490813 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490816 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490820 */   GIR_RootConstrainSelectedInstOperands,
     /*  490821 */   // GIR_Coverage, 25675,
     /*  490821 */   GIR_EraseRootFromParent_Done,
     /*  490822 */ // Label 7415: @490822
     /*  490822 */ GIM_Try, /*On fail goto*//*Label 7416*/ GIMT_Encode4(490888), // Rule ID 16058 //
     /*  490827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  490830 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490833 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490851 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  490851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490854 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  490856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490879 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490882 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490886 */   GIR_RootConstrainSelectedInstOperands,
     /*  490887 */   // GIR_Coverage, 16058,
     /*  490887 */   GIR_EraseRootFromParent_Done,
     /*  490888 */ // Label 7416: @490888
     /*  490888 */ GIM_Try, /*On fail goto*//*Label 7417*/ GIMT_Encode4(490954), // Rule ID 16059 //
     /*  490893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  490896 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490899 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490906 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490910 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490917 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  490917 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490920 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  490922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  490937 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  490942 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490945 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  490948 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  490952 */   GIR_RootConstrainSelectedInstOperands,
     /*  490953 */   // GIR_Coverage, 16059,
     /*  490953 */   GIR_EraseRootFromParent_Done,
     /*  490954 */ // Label 7417: @490954
     /*  490954 */ GIM_Try, /*On fail goto*//*Label 7418*/ GIMT_Encode4(491020), // Rule ID 16060 //
     /*  490959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  490962 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  490965 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  490972 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  490976 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  490983 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  490983 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  490986 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  490988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  490993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  490998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491008 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491011 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491014 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491018 */   GIR_RootConstrainSelectedInstOperands,
     /*  491019 */   // GIR_Coverage, 16060,
     /*  491019 */   GIR_EraseRootFromParent_Done,
     /*  491020 */ // Label 7418: @491020
     /*  491020 */ GIM_Try, /*On fail goto*//*Label 7419*/ GIMT_Encode4(491086), // Rule ID 16061 //
     /*  491025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  491028 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491031 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491038 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491042 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491049 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491052 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491077 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491080 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491084 */   GIR_RootConstrainSelectedInstOperands,
     /*  491085 */   // GIR_Coverage, 16061,
     /*  491085 */   GIR_EraseRootFromParent_Done,
     /*  491086 */ // Label 7419: @491086
     /*  491086 */ GIM_Try, /*On fail goto*//*Label 7420*/ GIMT_Encode4(491152), // Rule ID 16062 //
     /*  491091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  491094 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491097 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491104 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491108 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491115 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491115 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491118 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491130 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491143 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491146 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491150 */   GIR_RootConstrainSelectedInstOperands,
     /*  491151 */   // GIR_Coverage, 16062,
     /*  491151 */   GIR_EraseRootFromParent_Done,
     /*  491152 */ // Label 7420: @491152
     /*  491152 */ GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(491218), // Rule ID 16068 //
     /*  491157 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  491160 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491163 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491170 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491174 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491181 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491184 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491206 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491216 */   GIR_RootConstrainSelectedInstOperands,
     /*  491217 */   // GIR_Coverage, 16068,
     /*  491217 */   GIR_EraseRootFromParent_Done,
     /*  491218 */ // Label 7421: @491218
     /*  491218 */ GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(491284), // Rule ID 16069 //
     /*  491223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  491226 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491229 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491236 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491240 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491247 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491247 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491250 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491278 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491282 */   GIR_RootConstrainSelectedInstOperands,
     /*  491283 */   // GIR_Coverage, 16069,
     /*  491283 */   GIR_EraseRootFromParent_Done,
     /*  491284 */ // Label 7422: @491284
     /*  491284 */ GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(491350), // Rule ID 16070 //
     /*  491289 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  491292 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491295 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491302 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491306 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491313 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491316 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491323 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491338 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491344 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491348 */   GIR_RootConstrainSelectedInstOperands,
     /*  491349 */   // GIR_Coverage, 16070,
     /*  491349 */   GIR_EraseRootFromParent_Done,
     /*  491350 */ // Label 7423: @491350
     /*  491350 */ GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(491416), // Rule ID 16071 //
     /*  491355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  491358 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491361 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491368 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491372 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491379 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491379 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491382 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491389 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491394 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491404 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491407 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491410 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491414 */   GIR_RootConstrainSelectedInstOperands,
     /*  491415 */   // GIR_Coverage, 16071,
     /*  491415 */   GIR_EraseRootFromParent_Done,
     /*  491416 */ // Label 7424: @491416
     /*  491416 */ GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(491482), // Rule ID 16072 //
     /*  491421 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  491424 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491427 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491434 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491438 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491445 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491445 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491448 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491470 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491473 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491476 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491480 */   GIR_RootConstrainSelectedInstOperands,
     /*  491481 */   // GIR_Coverage, 16072,
     /*  491481 */   GIR_EraseRootFromParent_Done,
     /*  491482 */ // Label 7425: @491482
     /*  491482 */ GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(491548), // Rule ID 16078 //
     /*  491487 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  491490 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491493 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491500 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491504 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491511 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491511 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491514 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491521 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491526 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491536 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491539 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491542 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491546 */   GIR_RootConstrainSelectedInstOperands,
     /*  491547 */   // GIR_Coverage, 16078,
     /*  491547 */   GIR_EraseRootFromParent_Done,
     /*  491548 */ // Label 7426: @491548
     /*  491548 */ GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(491614), // Rule ID 16079 //
     /*  491553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  491556 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491559 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491570 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491577 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491580 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491592 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491602 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491605 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491608 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491612 */   GIR_RootConstrainSelectedInstOperands,
     /*  491613 */   // GIR_Coverage, 16079,
     /*  491613 */   GIR_EraseRootFromParent_Done,
     /*  491614 */ // Label 7427: @491614
     /*  491614 */ GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(491680), // Rule ID 16080 //
     /*  491619 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  491622 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491625 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491632 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491636 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491643 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491646 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491671 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491674 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491678 */   GIR_RootConstrainSelectedInstOperands,
     /*  491679 */   // GIR_Coverage, 16080,
     /*  491679 */   GIR_EraseRootFromParent_Done,
     /*  491680 */ // Label 7428: @491680
     /*  491680 */ GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(491746), // Rule ID 16081 //
     /*  491685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  491688 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491691 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491698 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491702 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491709 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491709 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491712 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491714 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491737 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491740 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491744 */   GIR_RootConstrainSelectedInstOperands,
     /*  491745 */   // GIR_Coverage, 16081,
     /*  491745 */   GIR_EraseRootFromParent_Done,
     /*  491746 */ // Label 7429: @491746
     /*  491746 */ GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(491812), // Rule ID 16082 //
     /*  491751 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  491754 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491757 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491764 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491768 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491775 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  491778 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491780 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491785 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491803 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491806 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491810 */   GIR_RootConstrainSelectedInstOperands,
     /*  491811 */   // GIR_Coverage, 16082,
     /*  491811 */   GIR_EraseRootFromParent_Done,
     /*  491812 */ // Label 7430: @491812
     /*  491812 */ GIM_Try, /*On fail goto*//*Label 7431*/ GIMT_Encode4(491878), // Rule ID 16088 //
     /*  491817 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  491820 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491823 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491830 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491834 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491841 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491844 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491866 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491869 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491872 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491876 */   GIR_RootConstrainSelectedInstOperands,
     /*  491877 */   // GIR_Coverage, 16088,
     /*  491877 */   GIR_EraseRootFromParent_Done,
     /*  491878 */ // Label 7431: @491878
     /*  491878 */ GIM_Try, /*On fail goto*//*Label 7432*/ GIMT_Encode4(491944), // Rule ID 16089 //
     /*  491883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  491886 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491907 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491910 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491935 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  491938 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  491942 */   GIR_RootConstrainSelectedInstOperands,
     /*  491943 */   // GIR_Coverage, 16089,
     /*  491943 */   GIR_EraseRootFromParent_Done,
     /*  491944 */ // Label 7432: @491944
     /*  491944 */ GIM_Try, /*On fail goto*//*Label 7433*/ GIMT_Encode4(492010), // Rule ID 16090 //
     /*  491949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  491952 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  491955 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  491962 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  491966 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  491973 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  491973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  491976 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  491978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  491983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  491988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  491993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  491998 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492001 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492004 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492008 */   GIR_RootConstrainSelectedInstOperands,
     /*  492009 */   // GIR_Coverage, 16090,
     /*  492009 */   GIR_EraseRootFromParent_Done,
     /*  492010 */ // Label 7433: @492010
     /*  492010 */ GIM_Try, /*On fail goto*//*Label 7434*/ GIMT_Encode4(492076), // Rule ID 16091 //
     /*  492015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  492018 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492021 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492028 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492032 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  492039 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  492042 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  492049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  492059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  492064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492070 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492074 */   GIR_RootConstrainSelectedInstOperands,
     /*  492075 */   // GIR_Coverage, 16091,
     /*  492075 */   GIR_EraseRootFromParent_Done,
     /*  492076 */ // Label 7434: @492076
     /*  492076 */ GIM_Try, /*On fail goto*//*Label 7435*/ GIMT_Encode4(492142), // Rule ID 16092 //
     /*  492081 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  492084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492087 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492098 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  492105 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492105 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  492108 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  492115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492120 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  492125 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  492130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492133 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492136 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492140 */   GIR_RootConstrainSelectedInstOperands,
     /*  492141 */   // GIR_Coverage, 16092,
     /*  492141 */   GIR_EraseRootFromParent_Done,
     /*  492142 */ // Label 7435: @492142
     /*  492142 */ GIM_Try, /*On fail goto*//*Label 7436*/ GIMT_Encode4(492262), // Rule ID 29380 //
     /*  492147 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  492150 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492153 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  492157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  492162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492166 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  492173 */   // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  492173 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  492176 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  492180 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  492185 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  492191 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  492196 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  492201 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  492204 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  492208 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  492213 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  492219 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  492224 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  492229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  492232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  492237 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  492240 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  492243 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  492248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  492253 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492256 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492260 */   GIR_RootConstrainSelectedInstOperands,
     /*  492261 */   // GIR_Coverage, 29380,
     /*  492261 */   GIR_EraseRootFromParent_Done,
     /*  492262 */ // Label 7436: @492262
     /*  492262 */ GIM_Try, /*On fail goto*//*Label 7437*/ GIMT_Encode4(492382), // Rule ID 29412 //
     /*  492267 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  492270 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492273 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  492277 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  492282 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492286 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  492293 */   // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  492293 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  492296 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  492300 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  492305 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  492311 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  492316 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  492321 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  492324 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  492328 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  492333 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  492339 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  492344 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  492349 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  492352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  492357 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  492360 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  492363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  492368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  492373 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492376 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492380 */   GIR_RootConstrainSelectedInstOperands,
     /*  492381 */   // GIR_Coverage, 29412,
     /*  492381 */   GIR_EraseRootFromParent_Done,
     /*  492382 */ // Label 7437: @492382
     /*  492382 */ GIM_Try, /*On fail goto*//*Label 7438*/ GIMT_Encode4(492443), // Rule ID 16053 //
     /*  492387 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  492390 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492393 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492400 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492404 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492411 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  492414 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492421 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492426 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492431 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492441 */   GIR_RootConstrainSelectedInstOperands,
     /*  492442 */   // GIR_Coverage, 16053,
     /*  492442 */   GIR_EraseRootFromParent_Done,
     /*  492443 */ // Label 7438: @492443
     /*  492443 */ GIM_Try, /*On fail goto*//*Label 7439*/ GIMT_Encode4(492504), // Rule ID 16054 //
     /*  492448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  492451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492454 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492461 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492465 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492472 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  492475 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492492 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492495 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492498 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492502 */   GIR_RootConstrainSelectedInstOperands,
     /*  492503 */   // GIR_Coverage, 16054,
     /*  492503 */   GIR_EraseRootFromParent_Done,
     /*  492504 */ // Label 7439: @492504
     /*  492504 */ GIM_Try, /*On fail goto*//*Label 7440*/ GIMT_Encode4(492565), // Rule ID 16055 //
     /*  492509 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  492512 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492515 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492522 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492526 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492533 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492533 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  492536 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492553 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492556 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492559 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492563 */   GIR_RootConstrainSelectedInstOperands,
     /*  492564 */   // GIR_Coverage, 16055,
     /*  492564 */   GIR_EraseRootFromParent_Done,
     /*  492565 */ // Label 7440: @492565
     /*  492565 */ GIM_Try, /*On fail goto*//*Label 7441*/ GIMT_Encode4(492626), // Rule ID 16056 //
     /*  492570 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  492573 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492576 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492583 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492587 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492594 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492594 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  492597 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492609 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492614 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492617 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492620 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492624 */   GIR_RootConstrainSelectedInstOperands,
     /*  492625 */   // GIR_Coverage, 16056,
     /*  492625 */   GIR_EraseRootFromParent_Done,
     /*  492626 */ // Label 7441: @492626
     /*  492626 */ GIM_Try, /*On fail goto*//*Label 7442*/ GIMT_Encode4(492687), // Rule ID 16057 //
     /*  492631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  492634 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492637 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492644 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492648 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492655 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  492658 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492678 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492681 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492685 */   GIR_RootConstrainSelectedInstOperands,
     /*  492686 */   // GIR_Coverage, 16057,
     /*  492686 */   GIR_EraseRootFromParent_Done,
     /*  492687 */ // Label 7442: @492687
     /*  492687 */ GIM_Try, /*On fail goto*//*Label 7443*/ GIMT_Encode4(492748), // Rule ID 16063 //
     /*  492692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  492695 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492698 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492705 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492709 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492716 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492716 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  492719 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492736 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492739 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492742 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492746 */   GIR_RootConstrainSelectedInstOperands,
     /*  492747 */   // GIR_Coverage, 16063,
     /*  492747 */   GIR_EraseRootFromParent_Done,
     /*  492748 */ // Label 7443: @492748
     /*  492748 */ GIM_Try, /*On fail goto*//*Label 7444*/ GIMT_Encode4(492809), // Rule ID 16064 //
     /*  492753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  492756 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492759 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492766 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492770 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492777 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492777 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  492780 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492807 */   GIR_RootConstrainSelectedInstOperands,
     /*  492808 */   // GIR_Coverage, 16064,
     /*  492808 */   GIR_EraseRootFromParent_Done,
     /*  492809 */ // Label 7444: @492809
     /*  492809 */ GIM_Try, /*On fail goto*//*Label 7445*/ GIMT_Encode4(492870), // Rule ID 16065 //
     /*  492814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  492817 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492820 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492831 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492838 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  492841 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492858 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492861 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492864 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492868 */   GIR_RootConstrainSelectedInstOperands,
     /*  492869 */   // GIR_Coverage, 16065,
     /*  492869 */   GIR_EraseRootFromParent_Done,
     /*  492870 */ // Label 7445: @492870
     /*  492870 */ GIM_Try, /*On fail goto*//*Label 7446*/ GIMT_Encode4(492931), // Rule ID 16066 //
     /*  492875 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  492878 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492881 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492888 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492892 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492899 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492899 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  492902 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492929 */   GIR_RootConstrainSelectedInstOperands,
     /*  492930 */   // GIR_Coverage, 16066,
     /*  492930 */   GIR_EraseRootFromParent_Done,
     /*  492931 */ // Label 7446: @492931
     /*  492931 */ GIM_Try, /*On fail goto*//*Label 7447*/ GIMT_Encode4(492992), // Rule ID 16067 //
     /*  492936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  492939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  492942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  492949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  492953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  492960 */   // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  492960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  492963 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  492965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  492970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  492975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  492980 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492983 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  492986 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  492990 */   GIR_RootConstrainSelectedInstOperands,
     /*  492991 */   // GIR_Coverage, 16067,
     /*  492991 */   GIR_EraseRootFromParent_Done,
     /*  492992 */ // Label 7447: @492992
     /*  492992 */ GIM_Try, /*On fail goto*//*Label 7448*/ GIMT_Encode4(493053), // Rule ID 16073 //
     /*  492997 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  493000 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493021 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  493024 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493026 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493041 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493044 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493047 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493051 */   GIR_RootConstrainSelectedInstOperands,
     /*  493052 */   // GIR_Coverage, 16073,
     /*  493052 */   GIR_EraseRootFromParent_Done,
     /*  493053 */ // Label 7448: @493053
     /*  493053 */ GIM_Try, /*On fail goto*//*Label 7449*/ GIMT_Encode4(493114), // Rule ID 16074 //
     /*  493058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  493061 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493064 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493082 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  493085 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493102 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493105 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493108 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493112 */   GIR_RootConstrainSelectedInstOperands,
     /*  493113 */   // GIR_Coverage, 16074,
     /*  493113 */   GIR_EraseRootFromParent_Done,
     /*  493114 */ // Label 7449: @493114
     /*  493114 */ GIM_Try, /*On fail goto*//*Label 7450*/ GIMT_Encode4(493175), // Rule ID 16075 //
     /*  493119 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  493122 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493125 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493136 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493143 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493143 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  493146 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493163 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493166 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493169 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493173 */   GIR_RootConstrainSelectedInstOperands,
     /*  493174 */   // GIR_Coverage, 16075,
     /*  493174 */   GIR_EraseRootFromParent_Done,
     /*  493175 */ // Label 7450: @493175
     /*  493175 */ GIM_Try, /*On fail goto*//*Label 7451*/ GIMT_Encode4(493236), // Rule ID 16076 //
     /*  493180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  493183 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493186 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493197 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493204 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  493207 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493224 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493227 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493230 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493234 */   GIR_RootConstrainSelectedInstOperands,
     /*  493235 */   // GIR_Coverage, 16076,
     /*  493235 */   GIR_EraseRootFromParent_Done,
     /*  493236 */ // Label 7451: @493236
     /*  493236 */ GIM_Try, /*On fail goto*//*Label 7452*/ GIMT_Encode4(493297), // Rule ID 16077 //
     /*  493241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  493244 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493247 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493254 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493258 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493265 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493265 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  493268 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493270 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493275 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493285 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493288 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493291 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493295 */   GIR_RootConstrainSelectedInstOperands,
     /*  493296 */   // GIR_Coverage, 16077,
     /*  493296 */   GIR_EraseRootFromParent_Done,
     /*  493297 */ // Label 7452: @493297
     /*  493297 */ GIM_Try, /*On fail goto*//*Label 7453*/ GIMT_Encode4(493358), // Rule ID 16083 //
     /*  493302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  493305 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493308 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493326 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  493329 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493346 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493349 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493352 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493356 */   GIR_RootConstrainSelectedInstOperands,
     /*  493357 */   // GIR_Coverage, 16083,
     /*  493357 */   GIR_EraseRootFromParent_Done,
     /*  493358 */ // Label 7453: @493358
     /*  493358 */ GIM_Try, /*On fail goto*//*Label 7454*/ GIMT_Encode4(493419), // Rule ID 16084 //
     /*  493363 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  493366 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493369 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493376 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493380 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493387 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493387 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  493390 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493407 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493410 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493413 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493417 */   GIR_RootConstrainSelectedInstOperands,
     /*  493418 */   // GIR_Coverage, 16084,
     /*  493418 */   GIR_EraseRootFromParent_Done,
     /*  493419 */ // Label 7454: @493419
     /*  493419 */ GIM_Try, /*On fail goto*//*Label 7455*/ GIMT_Encode4(493480), // Rule ID 16085 //
     /*  493424 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  493427 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493430 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493448 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  493451 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493471 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493474 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493478 */   GIR_RootConstrainSelectedInstOperands,
     /*  493479 */   // GIR_Coverage, 16085,
     /*  493479 */   GIR_EraseRootFromParent_Done,
     /*  493480 */ // Label 7455: @493480
     /*  493480 */ GIM_Try, /*On fail goto*//*Label 7456*/ GIMT_Encode4(493541), // Rule ID 16086 //
     /*  493485 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  493488 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493491 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493498 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493502 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493509 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493509 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  493512 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493529 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493532 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493535 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493539 */   GIR_RootConstrainSelectedInstOperands,
     /*  493540 */   // GIR_Coverage, 16086,
     /*  493540 */   GIR_EraseRootFromParent_Done,
     /*  493541 */ // Label 7456: @493541
     /*  493541 */ GIM_Try, /*On fail goto*//*Label 7457*/ GIMT_Encode4(493602), // Rule ID 16087 //
     /*  493546 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  493549 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493552 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  493559 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493563 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  493570 */   // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  493570 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  493573 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  493575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  493580 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  493585 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  493590 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493596 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493600 */   GIR_RootConstrainSelectedInstOperands,
     /*  493601 */   // GIR_Coverage, 16087,
     /*  493601 */   GIR_EraseRootFromParent_Done,
     /*  493602 */ // Label 7457: @493602
     /*  493602 */ GIM_Try, /*On fail goto*//*Label 7458*/ GIMT_Encode4(493718), // Rule ID 29386 //
     /*  493607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  493610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493613 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  493618 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493622 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  493629 */   // (st i64:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  493629 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  493632 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  493636 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  493641 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  493647 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  493652 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  493657 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  493660 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  493664 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  493669 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  493675 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  493680 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  493685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  493688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  493693 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  493696 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  493699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  493704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  493709 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493712 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493716 */   GIR_RootConstrainSelectedInstOperands,
     /*  493717 */   // GIR_Coverage, 29386,
     /*  493717 */   GIR_EraseRootFromParent_Done,
     /*  493718 */ // Label 7458: @493718
     /*  493718 */ GIM_Try, /*On fail goto*//*Label 7459*/ GIMT_Encode4(493834), // Rule ID 29418 //
     /*  493723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  493726 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  493729 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  493734 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493738 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  493745 */   // (st f64:{ *:[f64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  493745 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  493748 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  493752 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  493757 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  493763 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  493768 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  493773 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  493776 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  493780 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  493785 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  493791 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  493796 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  493801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  493804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  493809 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  493812 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  493815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  493820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  493825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493832 */   GIR_RootConstrainSelectedInstOperands,
     /*  493833 */   // GIR_Coverage, 29418,
     /*  493833 */   GIR_EraseRootFromParent_Done,
     /*  493834 */ // Label 7459: @493834
     /*  493834 */ GIM_Try, /*On fail goto*//*Label 7460*/ GIMT_Encode4(493892), // Rule ID 29355 //
     /*  493839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  493842 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  493845 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  493852 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  493857 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493861 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  493868 */   // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  493868 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  493871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  493876 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  493878 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  493883 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493886 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493890 */   GIR_RootConstrainSelectedInstOperands,
     /*  493891 */   // GIR_Coverage, 29355,
     /*  493891 */   GIR_EraseRootFromParent_Done,
     /*  493892 */ // Label 7460: @493892
     /*  493892 */ GIM_Try, /*On fail goto*//*Label 7461*/ GIMT_Encode4(493950), // Rule ID 29356 //
     /*  493897 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  493900 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  493903 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  493910 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  493915 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493919 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  493926 */   // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  493926 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  493929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  493934 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  493936 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  493941 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  493944 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  493948 */   GIR_RootConstrainSelectedInstOperands,
     /*  493949 */   // GIR_Coverage, 29356,
     /*  493949 */   GIR_EraseRootFromParent_Done,
     /*  493950 */ // Label 7461: @493950
     /*  493950 */ GIM_Try, /*On fail goto*//*Label 7462*/ GIMT_Encode4(494008), // Rule ID 29357 //
     /*  493955 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  493958 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  493961 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  493968 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  493973 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  493977 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  493984 */   // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  493984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  493987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  493992 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  493994 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  493999 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494002 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494006 */   GIR_RootConstrainSelectedInstOperands,
     /*  494007 */   // GIR_Coverage, 29357,
     /*  494007 */   GIR_EraseRootFromParent_Done,
     /*  494008 */ // Label 7462: @494008
     /*  494008 */ GIM_Try, /*On fail goto*//*Label 7463*/ GIMT_Encode4(494066), // Rule ID 29358 //
     /*  494013 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  494016 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494019 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494031 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494035 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494042 */   // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  494045 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494050 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494057 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494060 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494064 */   GIR_RootConstrainSelectedInstOperands,
     /*  494065 */   // GIR_Coverage, 29358,
     /*  494065 */   GIR_EraseRootFromParent_Done,
     /*  494066 */ // Label 7463: @494066
     /*  494066 */ GIM_Try, /*On fail goto*//*Label 7464*/ GIMT_Encode4(494124), // Rule ID 29359 //
     /*  494071 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  494074 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494077 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494084 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494089 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494093 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494100 */   // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494100 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  494103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494108 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494115 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494118 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494122 */   GIR_RootConstrainSelectedInstOperands,
     /*  494123 */   // GIR_Coverage, 29359,
     /*  494123 */   GIR_EraseRootFromParent_Done,
     /*  494124 */ // Label 7464: @494124
     /*  494124 */ GIM_Try, /*On fail goto*//*Label 7465*/ GIMT_Encode4(494182), // Rule ID 29360 //
     /*  494129 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  494132 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494135 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494142 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494147 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494151 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494158 */   // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  494161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494166 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494173 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494176 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494180 */   GIR_RootConstrainSelectedInstOperands,
     /*  494181 */   // GIR_Coverage, 29360,
     /*  494181 */   GIR_EraseRootFromParent_Done,
     /*  494182 */ // Label 7465: @494182
     /*  494182 */ GIM_Try, /*On fail goto*//*Label 7466*/ GIMT_Encode4(494240), // Rule ID 29361 //
     /*  494187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  494190 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494193 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494200 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494205 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494209 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494216 */   // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494216 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  494219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494224 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494226 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494231 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494234 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494238 */   GIR_RootConstrainSelectedInstOperands,
     /*  494239 */   // GIR_Coverage, 29361,
     /*  494239 */   GIR_EraseRootFromParent_Done,
     /*  494240 */ // Label 7466: @494240
     /*  494240 */ GIM_Try, /*On fail goto*//*Label 7467*/ GIMT_Encode4(494298), // Rule ID 29362 //
     /*  494245 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  494248 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494251 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494258 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494263 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494267 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494274 */   // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  494277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494282 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494289 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494292 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494296 */   GIR_RootConstrainSelectedInstOperands,
     /*  494297 */   // GIR_Coverage, 29362,
     /*  494297 */   GIR_EraseRootFromParent_Done,
     /*  494298 */ // Label 7467: @494298
     /*  494298 */ GIM_Try, /*On fail goto*//*Label 7468*/ GIMT_Encode4(494356), // Rule ID 29363 //
     /*  494303 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  494306 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494309 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494316 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494321 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494325 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494332 */   // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494332 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  494335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494340 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494342 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494347 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494350 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494354 */   GIR_RootConstrainSelectedInstOperands,
     /*  494355 */   // GIR_Coverage, 29363,
     /*  494355 */   GIR_EraseRootFromParent_Done,
     /*  494356 */ // Label 7468: @494356
     /*  494356 */ GIM_Try, /*On fail goto*//*Label 7469*/ GIMT_Encode4(494414), // Rule ID 29364 //
     /*  494361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  494364 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494367 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494374 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  494379 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494383 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  494390 */   // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  494390 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  494393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  494398 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  494400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  494405 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  494408 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494412 */   GIR_RootConstrainSelectedInstOperands,
     /*  494413 */   // GIR_Coverage, 29364,
     /*  494413 */   GIR_EraseRootFromParent_Done,
     /*  494414 */ // Label 7469: @494414
     /*  494414 */ GIM_Try, /*On fail goto*//*Label 7470*/ GIMT_Encode4(494481), // Rule ID 12867 //
     /*  494419 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  494422 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494425 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494432 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494439 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494443 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494450 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494450 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494453 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494458 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494460 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494475 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494479 */   GIR_RootConstrainSelectedInstOperands,
     /*  494480 */   // GIR_Coverage, 12867,
     /*  494480 */   GIR_EraseRootFromParent_Done,
     /*  494481 */ // Label 7470: @494481
     /*  494481 */ GIM_Try, /*On fail goto*//*Label 7471*/ GIMT_Encode4(494548), // Rule ID 12868 //
     /*  494486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  494489 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494492 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494499 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494506 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494510 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494517 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494517 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494525 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494542 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494546 */   GIR_RootConstrainSelectedInstOperands,
     /*  494547 */   // GIR_Coverage, 12868,
     /*  494547 */   GIR_EraseRootFromParent_Done,
     /*  494548 */ // Label 7471: @494548
     /*  494548 */ GIM_Try, /*On fail goto*//*Label 7472*/ GIMT_Encode4(494615), // Rule ID 12869 //
     /*  494553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  494556 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494559 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494566 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494573 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494577 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494584 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494587 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494592 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494609 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494613 */   GIR_RootConstrainSelectedInstOperands,
     /*  494614 */   // GIR_Coverage, 12869,
     /*  494614 */   GIR_EraseRootFromParent_Done,
     /*  494615 */ // Label 7472: @494615
     /*  494615 */ GIM_Try, /*On fail goto*//*Label 7473*/ GIMT_Encode4(494682), // Rule ID 12870 //
     /*  494620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  494623 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494633 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494640 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494644 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494651 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494651 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494659 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494671 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494676 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494680 */   GIR_RootConstrainSelectedInstOperands,
     /*  494681 */   // GIR_Coverage, 12870,
     /*  494681 */   GIR_EraseRootFromParent_Done,
     /*  494682 */ // Label 7473: @494682
     /*  494682 */ GIM_Try, /*On fail goto*//*Label 7474*/ GIMT_Encode4(494749), // Rule ID 12871 //
     /*  494687 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  494690 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  494693 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  494700 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494707 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494711 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494718 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494718 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494726 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494743 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494747 */   GIR_RootConstrainSelectedInstOperands,
     /*  494748 */   // GIR_Coverage, 12871,
     /*  494748 */   GIR_EraseRootFromParent_Done,
     /*  494749 */ // Label 7474: @494749
     /*  494749 */ GIM_Try, /*On fail goto*//*Label 7475*/ GIMT_Encode4(494809), // Rule ID 12273 //
     /*  494754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  494757 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  494760 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494778 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494786 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494807 */   GIR_RootConstrainSelectedInstOperands,
     /*  494808 */   // GIR_Coverage, 12273,
     /*  494808 */   GIR_EraseRootFromParent_Done,
     /*  494809 */ // Label 7475: @494809
     /*  494809 */ GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(494869), // Rule ID 12274 //
     /*  494814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  494817 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  494820 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494831 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494838 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494846 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494867 */   GIR_RootConstrainSelectedInstOperands,
     /*  494868 */   // GIR_Coverage, 12274,
     /*  494868 */   GIR_EraseRootFromParent_Done,
     /*  494869 */ // Label 7476: @494869
     /*  494869 */ GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(494929), // Rule ID 12275 //
     /*  494874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  494877 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  494880 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494887 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494891 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494898 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494906 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494918 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494923 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494927 */   GIR_RootConstrainSelectedInstOperands,
     /*  494928 */   // GIR_Coverage, 12275,
     /*  494928 */   GIR_EraseRootFromParent_Done,
     /*  494929 */ // Label 7477: @494929
     /*  494929 */ GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(494989), // Rule ID 12276 //
     /*  494934 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  494937 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  494940 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  494947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  494951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  494958 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  494958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  494961 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  494966 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  494968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  494973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  494978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  494983 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  494987 */   GIR_RootConstrainSelectedInstOperands,
     /*  494988 */   // GIR_Coverage, 12276,
     /*  494988 */   GIR_EraseRootFromParent_Done,
     /*  494989 */ // Label 7478: @494989
     /*  494989 */ GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(495049), // Rule ID 12277 //
     /*  494994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  494997 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495000 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495007 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495011 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  495018 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  495018 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  495021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  495026 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  495033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  495038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  495043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495047 */   GIR_RootConstrainSelectedInstOperands,
     /*  495048 */   // GIR_Coverage, 12277,
     /*  495048 */   GIR_EraseRootFromParent_Done,
     /*  495049 */ // Label 7479: @495049
     /*  495049 */ GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(495109), // Rule ID 12293 //
     /*  495054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  495057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495067 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495071 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  495078 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  495078 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  495081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  495086 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  495093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  495098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  495103 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495107 */   GIR_RootConstrainSelectedInstOperands,
     /*  495108 */   // GIR_Coverage, 12293,
     /*  495108 */   GIR_EraseRootFromParent_Done,
     /*  495109 */ // Label 7480: @495109
     /*  495109 */ GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(495169), // Rule ID 12294 //
     /*  495114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  495117 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495120 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495127 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495131 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  495138 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  495138 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  495141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  495146 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  495153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  495158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  495163 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495167 */   GIR_RootConstrainSelectedInstOperands,
     /*  495168 */   // GIR_Coverage, 12294,
     /*  495168 */   GIR_EraseRootFromParent_Done,
     /*  495169 */ // Label 7481: @495169
     /*  495169 */ GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(495229), // Rule ID 12295 //
     /*  495174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  495177 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495180 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495187 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495191 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  495198 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  495198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  495201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  495206 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  495213 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  495218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  495223 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495227 */   GIR_RootConstrainSelectedInstOperands,
     /*  495228 */   // GIR_Coverage, 12295,
     /*  495228 */   GIR_EraseRootFromParent_Done,
     /*  495229 */ // Label 7482: @495229
     /*  495229 */ GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(495289), // Rule ID 12296 //
     /*  495234 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  495237 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495240 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  495258 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  495258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  495261 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  495266 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  495273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  495278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  495283 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495287 */   GIR_RootConstrainSelectedInstOperands,
     /*  495288 */   // GIR_Coverage, 12296,
     /*  495288 */   GIR_EraseRootFromParent_Done,
     /*  495289 */ // Label 7483: @495289
     /*  495289 */ GIM_Try, /*On fail goto*//*Label 7484*/ GIMT_Encode4(495349), // Rule ID 12297 //
     /*  495294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  495297 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495300 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495307 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495311 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  495318 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  495318 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  495321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  495326 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  495333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  495338 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  495343 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495347 */   GIR_RootConstrainSelectedInstOperands,
     /*  495348 */   // GIR_Coverage, 12297,
     /*  495348 */   GIR_EraseRootFromParent_Done,
     /*  495349 */ // Label 7484: @495349
     /*  495349 */ GIM_Try, /*On fail goto*//*Label 7485*/ GIMT_Encode4(495409), // Rule ID 12862 //
     /*  495354 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  495357 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  495360 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  495367 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495374 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495378 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495385 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495393 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495400 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495403 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495407 */   GIR_RootConstrainSelectedInstOperands,
     /*  495408 */   // GIR_Coverage, 12862,
     /*  495408 */   GIR_EraseRootFromParent_Done,
     /*  495409 */ // Label 7485: @495409
     /*  495409 */ GIM_Try, /*On fail goto*//*Label 7486*/ GIMT_Encode4(495469), // Rule ID 12863 //
     /*  495414 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  495417 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  495420 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  495427 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495434 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495438 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495445 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495445 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495453 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495455 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495460 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495463 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495467 */   GIR_RootConstrainSelectedInstOperands,
     /*  495468 */   // GIR_Coverage, 12863,
     /*  495468 */   GIR_EraseRootFromParent_Done,
     /*  495469 */ // Label 7486: @495469
     /*  495469 */ GIM_Try, /*On fail goto*//*Label 7487*/ GIMT_Encode4(495529), // Rule ID 12864 //
     /*  495474 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  495477 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  495480 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  495487 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495494 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495498 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495505 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495513 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495520 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495523 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495527 */   GIR_RootConstrainSelectedInstOperands,
     /*  495528 */   // GIR_Coverage, 12864,
     /*  495528 */   GIR_EraseRootFromParent_Done,
     /*  495529 */ // Label 7487: @495529
     /*  495529 */ GIM_Try, /*On fail goto*//*Label 7488*/ GIMT_Encode4(495589), // Rule ID 12865 //
     /*  495534 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  495537 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  495540 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  495547 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495554 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495558 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495565 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495565 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495573 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495580 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495583 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495587 */   GIR_RootConstrainSelectedInstOperands,
     /*  495588 */   // GIR_Coverage, 12865,
     /*  495588 */   GIR_EraseRootFromParent_Done,
     /*  495589 */ // Label 7488: @495589
     /*  495589 */ GIM_Try, /*On fail goto*//*Label 7489*/ GIMT_Encode4(495649), // Rule ID 12866 //
     /*  495594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  495597 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  495600 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  495607 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495614 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495618 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495625 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495633 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495640 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495643 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495647 */   GIR_RootConstrainSelectedInstOperands,
     /*  495648 */   // GIR_Coverage, 12866,
     /*  495648 */   GIR_EraseRootFromParent_Done,
     /*  495649 */ // Label 7489: @495649
     /*  495649 */ GIM_Try, /*On fail goto*//*Label 7490*/ GIMT_Encode4(495702), // Rule ID 12268 //
     /*  495654 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  495657 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495660 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495667 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495671 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495678 */   // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495678 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495686 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495693 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495696 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495700 */   GIR_RootConstrainSelectedInstOperands,
     /*  495701 */   // GIR_Coverage, 12268,
     /*  495701 */   GIR_EraseRootFromParent_Done,
     /*  495702 */ // Label 7490: @495702
     /*  495702 */ GIM_Try, /*On fail goto*//*Label 7491*/ GIMT_Encode4(495755), // Rule ID 12269 //
     /*  495707 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  495710 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495720 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495724 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495731 */   // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495739 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495746 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495749 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495753 */   GIR_RootConstrainSelectedInstOperands,
     /*  495754 */   // GIR_Coverage, 12269,
     /*  495754 */   GIR_EraseRootFromParent_Done,
     /*  495755 */ // Label 7491: @495755
     /*  495755 */ GIM_Try, /*On fail goto*//*Label 7492*/ GIMT_Encode4(495808), // Rule ID 12270 //
     /*  495760 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  495763 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495766 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495773 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495777 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495784 */   // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495792 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495799 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495802 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495806 */   GIR_RootConstrainSelectedInstOperands,
     /*  495807 */   // GIR_Coverage, 12270,
     /*  495807 */   GIR_EraseRootFromParent_Done,
     /*  495808 */ // Label 7492: @495808
     /*  495808 */ GIM_Try, /*On fail goto*//*Label 7493*/ GIMT_Encode4(495861), // Rule ID 12271 //
     /*  495813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  495816 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495819 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495826 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495830 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495837 */   // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495845 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495852 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495855 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495859 */   GIR_RootConstrainSelectedInstOperands,
     /*  495860 */   // GIR_Coverage, 12271,
     /*  495860 */   GIR_EraseRootFromParent_Done,
     /*  495861 */ // Label 7493: @495861
     /*  495861 */ GIM_Try, /*On fail goto*//*Label 7494*/ GIMT_Encode4(495914), // Rule ID 12272 //
     /*  495866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  495869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495872 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495879 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495883 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495890 */   // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495890 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495898 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495905 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495908 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495912 */   GIR_RootConstrainSelectedInstOperands,
     /*  495913 */   // GIR_Coverage, 12272,
     /*  495913 */   GIR_EraseRootFromParent_Done,
     /*  495914 */ // Label 7494: @495914
     /*  495914 */ GIM_Try, /*On fail goto*//*Label 7495*/ GIMT_Encode4(495967), // Rule ID 12288 //
     /*  495919 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  495922 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495925 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495932 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495936 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495943 */   // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  495951 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  495953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  495958 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  495961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  495965 */   GIR_RootConstrainSelectedInstOperands,
     /*  495966 */   // GIR_Coverage, 12288,
     /*  495966 */   GIR_EraseRootFromParent_Done,
     /*  495967 */ // Label 7495: @495967
     /*  495967 */ GIM_Try, /*On fail goto*//*Label 7496*/ GIMT_Encode4(496020), // Rule ID 12289 //
     /*  495972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  495975 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  495978 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  495985 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  495989 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  495996 */   // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  495996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  495999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  496004 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  496011 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  496014 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496018 */   GIR_RootConstrainSelectedInstOperands,
     /*  496019 */   // GIR_Coverage, 12289,
     /*  496019 */   GIR_EraseRootFromParent_Done,
     /*  496020 */ // Label 7496: @496020
     /*  496020 */ GIM_Try, /*On fail goto*//*Label 7497*/ GIMT_Encode4(496073), // Rule ID 12290 //
     /*  496025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  496028 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496031 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  496038 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496042 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  496049 */   // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  496049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  496052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  496057 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  496064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  496067 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496071 */   GIR_RootConstrainSelectedInstOperands,
     /*  496072 */   // GIR_Coverage, 12290,
     /*  496072 */   GIR_EraseRootFromParent_Done,
     /*  496073 */ // Label 7497: @496073
     /*  496073 */ GIM_Try, /*On fail goto*//*Label 7498*/ GIMT_Encode4(496126), // Rule ID 12291 //
     /*  496078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  496081 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496084 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  496091 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496095 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  496102 */   // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  496102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  496105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  496110 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  496117 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  496120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496124 */   GIR_RootConstrainSelectedInstOperands,
     /*  496125 */   // GIR_Coverage, 12291,
     /*  496125 */   GIR_EraseRootFromParent_Done,
     /*  496126 */ // Label 7498: @496126
     /*  496126 */ GIM_Try, /*On fail goto*//*Label 7499*/ GIMT_Encode4(496179), // Rule ID 12292 //
     /*  496131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  496134 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496137 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  496144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496148 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  496155 */   // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  496155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  496158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  496163 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  496170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  496173 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496177 */   GIR_RootConstrainSelectedInstOperands,
     /*  496178 */   // GIR_Coverage, 12292,
     /*  496178 */   GIR_EraseRootFromParent_Done,
     /*  496179 */ // Label 7499: @496179
     /*  496179 */ GIM_Try, /*On fail goto*//*Label 7500*/ GIMT_Encode4(496245), // Rule ID 10441 //
     /*  496184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  496187 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  496190 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  496197 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496203 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496207 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496214 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496214 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496222 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496224 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496239 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496243 */   GIR_RootConstrainSelectedInstOperands,
     /*  496244 */   // GIR_Coverage, 10441,
     /*  496244 */   GIR_EraseRootFromParent_Done,
     /*  496245 */ // Label 7500: @496245
     /*  496245 */ GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(496311), // Rule ID 10442 //
     /*  496250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  496253 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  496256 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  496263 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496269 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496273 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496280 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496288 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496309 */   GIR_RootConstrainSelectedInstOperands,
     /*  496310 */   // GIR_Coverage, 10442,
     /*  496310 */   GIR_EraseRootFromParent_Done,
     /*  496311 */ // Label 7501: @496311
     /*  496311 */ GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(496377), // Rule ID 10443 //
     /*  496316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  496319 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  496322 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  496329 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496335 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496339 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496346 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496349 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496354 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496371 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496375 */   GIR_RootConstrainSelectedInstOperands,
     /*  496376 */   // GIR_Coverage, 10443,
     /*  496376 */   GIR_EraseRootFromParent_Done,
     /*  496377 */ // Label 7502: @496377
     /*  496377 */ GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(496443), // Rule ID 10444 //
     /*  496382 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  496385 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  496388 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  496395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496401 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496405 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496412 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496415 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496420 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496441 */   GIR_RootConstrainSelectedInstOperands,
     /*  496442 */   // GIR_Coverage, 10444,
     /*  496442 */   GIR_EraseRootFromParent_Done,
     /*  496443 */ // Label 7503: @496443
     /*  496443 */ GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(496509), // Rule ID 10445 //
     /*  496448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  496451 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  496454 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  496461 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496467 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496471 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496478 */   // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496478 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496486 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496488 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496507 */   GIR_RootConstrainSelectedInstOperands,
     /*  496508 */   // GIR_Coverage, 10445,
     /*  496508 */   GIR_EraseRootFromParent_Done,
     /*  496509 */ // Label 7504: @496509
     /*  496509 */ GIM_Try, /*On fail goto*//*Label 7505*/ GIMT_Encode4(496568), // Rule ID 10121 //
     /*  496514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  496517 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496520 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496526 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496530 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496537 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496545 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496562 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496566 */   GIR_RootConstrainSelectedInstOperands,
     /*  496567 */   // GIR_Coverage, 10121,
     /*  496567 */   GIR_EraseRootFromParent_Done,
     /*  496568 */ // Label 7505: @496568
     /*  496568 */ GIM_Try, /*On fail goto*//*Label 7506*/ GIMT_Encode4(496627), // Rule ID 10122 //
     /*  496573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  496576 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496579 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496585 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496589 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496596 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496604 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496621 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496625 */   GIR_RootConstrainSelectedInstOperands,
     /*  496626 */   // GIR_Coverage, 10122,
     /*  496626 */   GIR_EraseRootFromParent_Done,
     /*  496627 */ // Label 7506: @496627
     /*  496627 */ GIM_Try, /*On fail goto*//*Label 7507*/ GIMT_Encode4(496686), // Rule ID 10123 //
     /*  496632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  496635 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496638 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496644 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496648 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496655 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496663 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496680 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496684 */   GIR_RootConstrainSelectedInstOperands,
     /*  496685 */   // GIR_Coverage, 10123,
     /*  496685 */   GIR_EraseRootFromParent_Done,
     /*  496686 */ // Label 7507: @496686
     /*  496686 */ GIM_Try, /*On fail goto*//*Label 7508*/ GIMT_Encode4(496745), // Rule ID 10124 //
     /*  496691 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  496694 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496697 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496707 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496714 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496722 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496739 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496743 */   GIR_RootConstrainSelectedInstOperands,
     /*  496744 */   // GIR_Coverage, 10124,
     /*  496744 */   GIR_EraseRootFromParent_Done,
     /*  496745 */ // Label 7508: @496745
     /*  496745 */ GIM_Try, /*On fail goto*//*Label 7509*/ GIMT_Encode4(496804), // Rule ID 10125 //
     /*  496750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  496753 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496756 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496762 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496766 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496773 */   // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496773 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496776 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496781 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496798 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496802 */   GIR_RootConstrainSelectedInstOperands,
     /*  496803 */   // GIR_Coverage, 10125,
     /*  496803 */   GIR_EraseRootFromParent_Done,
     /*  496804 */ // Label 7509: @496804
     /*  496804 */ GIM_Try, /*On fail goto*//*Label 7510*/ GIMT_Encode4(496863), // Rule ID 10141 //
     /*  496809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  496812 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496815 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496821 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496825 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496832 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496840 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496857 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496861 */   GIR_RootConstrainSelectedInstOperands,
     /*  496862 */   // GIR_Coverage, 10141,
     /*  496862 */   GIR_EraseRootFromParent_Done,
     /*  496863 */ // Label 7510: @496863
     /*  496863 */ GIM_Try, /*On fail goto*//*Label 7511*/ GIMT_Encode4(496922), // Rule ID 10142 //
     /*  496868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  496871 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496874 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496880 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496884 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496891 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496891 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496899 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496901 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496916 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496920 */   GIR_RootConstrainSelectedInstOperands,
     /*  496921 */   // GIR_Coverage, 10142,
     /*  496921 */   GIR_EraseRootFromParent_Done,
     /*  496922 */ // Label 7511: @496922
     /*  496922 */ GIM_Try, /*On fail goto*//*Label 7512*/ GIMT_Encode4(496981), // Rule ID 10143 //
     /*  496927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  496930 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496933 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496939 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  496943 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  496950 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  496950 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  496953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  496958 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  496960 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  496965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  496970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  496975 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  496979 */   GIR_RootConstrainSelectedInstOperands,
     /*  496980 */   // GIR_Coverage, 10143,
     /*  496980 */   GIR_EraseRootFromParent_Done,
     /*  496981 */ // Label 7512: @496981
     /*  496981 */ GIM_Try, /*On fail goto*//*Label 7513*/ GIMT_Encode4(497040), // Rule ID 10144 //
     /*  496986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  496989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  496992 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  496998 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497002 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  497009 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  497009 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  497012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  497017 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497019 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  497024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  497029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  497034 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497038 */   GIR_RootConstrainSelectedInstOperands,
     /*  497039 */   // GIR_Coverage, 10144,
     /*  497039 */   GIR_EraseRootFromParent_Done,
     /*  497040 */ // Label 7513: @497040
     /*  497040 */ GIM_Try, /*On fail goto*//*Label 7514*/ GIMT_Encode4(497099), // Rule ID 10145 //
     /*  497045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  497048 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497051 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497057 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497061 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  497068 */   // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  497068 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  497071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  497076 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  497083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  497088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  497093 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497097 */   GIR_RootConstrainSelectedInstOperands,
     /*  497098 */   // GIR_Coverage, 10145,
     /*  497098 */   GIR_EraseRootFromParent_Done,
     /*  497099 */ // Label 7514: @497099
     /*  497099 */ GIM_Try, /*On fail goto*//*Label 7515*/ GIMT_Encode4(497158), // Rule ID 10436 //
     /*  497104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  497107 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  497110 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  497117 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497123 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497127 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497134 */   // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497142 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497149 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497152 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497156 */   GIR_RootConstrainSelectedInstOperands,
     /*  497157 */   // GIR_Coverage, 10436,
     /*  497157 */   GIR_EraseRootFromParent_Done,
     /*  497158 */ // Label 7515: @497158
     /*  497158 */ GIM_Try, /*On fail goto*//*Label 7516*/ GIMT_Encode4(497217), // Rule ID 10437 //
     /*  497163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  497166 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  497169 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  497176 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497182 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497186 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497193 */   // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497193 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497201 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497208 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497211 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497215 */   GIR_RootConstrainSelectedInstOperands,
     /*  497216 */   // GIR_Coverage, 10437,
     /*  497216 */   GIR_EraseRootFromParent_Done,
     /*  497217 */ // Label 7516: @497217
     /*  497217 */ GIM_Try, /*On fail goto*//*Label 7517*/ GIMT_Encode4(497276), // Rule ID 10438 //
     /*  497222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  497225 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  497228 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  497235 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497241 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497245 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497252 */   // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497260 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497267 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497270 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497274 */   GIR_RootConstrainSelectedInstOperands,
     /*  497275 */   // GIR_Coverage, 10438,
     /*  497275 */   GIR_EraseRootFromParent_Done,
     /*  497276 */ // Label 7517: @497276
     /*  497276 */ GIM_Try, /*On fail goto*//*Label 7518*/ GIMT_Encode4(497335), // Rule ID 10439 //
     /*  497281 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  497284 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  497287 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  497294 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497311 */   // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497319 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497333 */   GIR_RootConstrainSelectedInstOperands,
     /*  497334 */   // GIR_Coverage, 10439,
     /*  497334 */   GIR_EraseRootFromParent_Done,
     /*  497335 */ // Label 7518: @497335
     /*  497335 */ GIM_Try, /*On fail goto*//*Label 7519*/ GIMT_Encode4(497394), // Rule ID 10440 //
     /*  497340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  497343 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  497346 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  497353 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497359 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497363 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497370 */   // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497370 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497378 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497385 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497388 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497392 */   GIR_RootConstrainSelectedInstOperands,
     /*  497393 */   // GIR_Coverage, 10440,
     /*  497393 */   GIR_EraseRootFromParent_Done,
     /*  497394 */ // Label 7519: @497394
     /*  497394 */ GIM_Try, /*On fail goto*//*Label 7520*/ GIMT_Encode4(497446), // Rule ID 10116 //
     /*  497399 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  497402 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497405 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497422 */   // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497430 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497437 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497444 */   GIR_RootConstrainSelectedInstOperands,
     /*  497445 */   // GIR_Coverage, 10116,
     /*  497445 */   GIR_EraseRootFromParent_Done,
     /*  497446 */ // Label 7520: @497446
     /*  497446 */ GIM_Try, /*On fail goto*//*Label 7521*/ GIMT_Encode4(497498), // Rule ID 10117 //
     /*  497451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  497454 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497457 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497463 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497467 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497474 */   // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497474 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497482 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497489 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497492 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497496 */   GIR_RootConstrainSelectedInstOperands,
     /*  497497 */   // GIR_Coverage, 10117,
     /*  497497 */   GIR_EraseRootFromParent_Done,
     /*  497498 */ // Label 7521: @497498
     /*  497498 */ GIM_Try, /*On fail goto*//*Label 7522*/ GIMT_Encode4(497550), // Rule ID 10118 //
     /*  497503 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  497506 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497515 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497519 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497526 */   // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497526 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497534 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497536 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497541 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497544 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497548 */   GIR_RootConstrainSelectedInstOperands,
     /*  497549 */   // GIR_Coverage, 10118,
     /*  497549 */   GIR_EraseRootFromParent_Done,
     /*  497550 */ // Label 7522: @497550
     /*  497550 */ GIM_Try, /*On fail goto*//*Label 7523*/ GIMT_Encode4(497602), // Rule ID 10119 //
     /*  497555 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  497558 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497567 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497571 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497578 */   // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497586 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497596 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497600 */   GIR_RootConstrainSelectedInstOperands,
     /*  497601 */   // GIR_Coverage, 10119,
     /*  497601 */   GIR_EraseRootFromParent_Done,
     /*  497602 */ // Label 7523: @497602
     /*  497602 */ GIM_Try, /*On fail goto*//*Label 7524*/ GIMT_Encode4(497654), // Rule ID 10120 //
     /*  497607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  497610 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497613 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497619 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497623 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497630 */   // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497630 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497638 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497645 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497648 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497652 */   GIR_RootConstrainSelectedInstOperands,
     /*  497653 */   // GIR_Coverage, 10120,
     /*  497653 */   GIR_EraseRootFromParent_Done,
     /*  497654 */ // Label 7524: @497654
     /*  497654 */ GIM_Try, /*On fail goto*//*Label 7525*/ GIMT_Encode4(497706), // Rule ID 10136 //
     /*  497659 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  497662 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497665 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497671 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497675 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497682 */   // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497690 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497697 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497700 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497704 */   GIR_RootConstrainSelectedInstOperands,
     /*  497705 */   // GIR_Coverage, 10136,
     /*  497705 */   GIR_EraseRootFromParent_Done,
     /*  497706 */ // Label 7525: @497706
     /*  497706 */ GIM_Try, /*On fail goto*//*Label 7526*/ GIMT_Encode4(497758), // Rule ID 10137 //
     /*  497711 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  497714 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497717 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497723 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497727 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497734 */   // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497742 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497749 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497752 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497756 */   GIR_RootConstrainSelectedInstOperands,
     /*  497757 */   // GIR_Coverage, 10137,
     /*  497757 */   GIR_EraseRootFromParent_Done,
     /*  497758 */ // Label 7526: @497758
     /*  497758 */ GIM_Try, /*On fail goto*//*Label 7527*/ GIMT_Encode4(497810), // Rule ID 10138 //
     /*  497763 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  497766 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497769 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497775 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497779 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497786 */   // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497794 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497804 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497808 */   GIR_RootConstrainSelectedInstOperands,
     /*  497809 */   // GIR_Coverage, 10138,
     /*  497809 */   GIR_EraseRootFromParent_Done,
     /*  497810 */ // Label 7527: @497810
     /*  497810 */ GIM_Try, /*On fail goto*//*Label 7528*/ GIMT_Encode4(497862), // Rule ID 10139 //
     /*  497815 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  497818 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497821 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497831 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497838 */   // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497846 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497853 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497856 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497860 */   GIR_RootConstrainSelectedInstOperands,
     /*  497861 */   // GIR_Coverage, 10139,
     /*  497861 */   GIR_EraseRootFromParent_Done,
     /*  497862 */ // Label 7528: @497862
     /*  497862 */ GIM_Try, /*On fail goto*//*Label 7529*/ GIMT_Encode4(497914), // Rule ID 10140 //
     /*  497867 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  497870 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497873 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  497879 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497883 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  497890 */   // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  497890 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  497893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  497898 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  497900 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  497905 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497908 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497912 */   GIR_RootConstrainSelectedInstOperands,
     /*  497913 */   // GIR_Coverage, 10140,
     /*  497913 */   GIR_EraseRootFromParent_Done,
     /*  497914 */ // Label 7529: @497914
     /*  497914 */ GIM_Reject,
     /*  497915 */ // Label 5868: @497915
     /*  497915 */ GIM_Try, /*On fail goto*//*Label 7530*/ GIMT_Encode4(507314),
     /*  497920 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  497923 */   GIM_Try, /*On fail goto*//*Label 7531*/ GIMT_Encode4(497979), // Rule ID 25826 //
     /*  497928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  497931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  497936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  497947 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  497947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  497950 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  497952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  497957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  497962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  497967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  497973 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  497977 */     GIR_RootConstrainSelectedInstOperands,
     /*  497978 */     // GIR_Coverage, 25826,
     /*  497978 */     GIR_EraseRootFromParent_Done,
     /*  497979 */   // Label 7531: @497979
     /*  497979 */   GIM_Try, /*On fail goto*//*Label 7532*/ GIMT_Encode4(498035), // Rule ID 25827 //
     /*  497984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  497987 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  497992 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  497996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498003 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498006 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498033 */     GIR_RootConstrainSelectedInstOperands,
     /*  498034 */     // GIR_Coverage, 25827,
     /*  498034 */     GIR_EraseRootFromParent_Done,
     /*  498035 */   // Label 7532: @498035
     /*  498035 */   GIM_Try, /*On fail goto*//*Label 7533*/ GIMT_Encode4(498091), // Rule ID 25828 //
     /*  498040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  498043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498059 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498062 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498089 */     GIR_RootConstrainSelectedInstOperands,
     /*  498090 */     // GIR_Coverage, 25828,
     /*  498090 */     GIR_EraseRootFromParent_Done,
     /*  498091 */   // Label 7533: @498091
     /*  498091 */   GIM_Try, /*On fail goto*//*Label 7534*/ GIMT_Encode4(498147), // Rule ID 25829 //
     /*  498096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  498099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498104 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498115 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498118 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498145 */     GIR_RootConstrainSelectedInstOperands,
     /*  498146 */     // GIR_Coverage, 25829,
     /*  498146 */     GIR_EraseRootFromParent_Done,
     /*  498147 */   // Label 7534: @498147
     /*  498147 */   GIM_Try, /*On fail goto*//*Label 7535*/ GIMT_Encode4(498203), // Rule ID 25830 //
     /*  498152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  498155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498171 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498174 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498197 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498201 */     GIR_RootConstrainSelectedInstOperands,
     /*  498202 */     // GIR_Coverage, 25830,
     /*  498202 */     GIR_EraseRootFromParent_Done,
     /*  498203 */   // Label 7535: @498203
     /*  498203 */   GIM_Try, /*On fail goto*//*Label 7536*/ GIMT_Encode4(498259), // Rule ID 25836 //
     /*  498208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  498211 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498227 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498230 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498257 */     GIR_RootConstrainSelectedInstOperands,
     /*  498258 */     // GIR_Coverage, 25836,
     /*  498258 */     GIR_EraseRootFromParent_Done,
     /*  498259 */   // Label 7536: @498259
     /*  498259 */   GIM_Try, /*On fail goto*//*Label 7537*/ GIMT_Encode4(498315), // Rule ID 25837 //
     /*  498264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  498267 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498283 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498286 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498313 */     GIR_RootConstrainSelectedInstOperands,
     /*  498314 */     // GIR_Coverage, 25837,
     /*  498314 */     GIR_EraseRootFromParent_Done,
     /*  498315 */   // Label 7537: @498315
     /*  498315 */   GIM_Try, /*On fail goto*//*Label 7538*/ GIMT_Encode4(498371), // Rule ID 25838 //
     /*  498320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  498323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498339 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498342 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498365 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498369 */     GIR_RootConstrainSelectedInstOperands,
     /*  498370 */     // GIR_Coverage, 25838,
     /*  498370 */     GIR_EraseRootFromParent_Done,
     /*  498371 */   // Label 7538: @498371
     /*  498371 */   GIM_Try, /*On fail goto*//*Label 7539*/ GIMT_Encode4(498427), // Rule ID 25839 //
     /*  498376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  498379 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498384 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498395 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498398 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498425 */     GIR_RootConstrainSelectedInstOperands,
     /*  498426 */     // GIR_Coverage, 25839,
     /*  498426 */     GIR_EraseRootFromParent_Done,
     /*  498427 */   // Label 7539: @498427
     /*  498427 */   GIM_Try, /*On fail goto*//*Label 7540*/ GIMT_Encode4(498483), // Rule ID 25840 //
     /*  498432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  498435 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498451 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498454 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498481 */     GIR_RootConstrainSelectedInstOperands,
     /*  498482 */     // GIR_Coverage, 25840,
     /*  498482 */     GIR_EraseRootFromParent_Done,
     /*  498483 */   // Label 7540: @498483
     /*  498483 */   GIM_Try, /*On fail goto*//*Label 7541*/ GIMT_Encode4(498539), // Rule ID 25846 //
     /*  498488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  498491 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498507 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498510 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498537 */     GIR_RootConstrainSelectedInstOperands,
     /*  498538 */     // GIR_Coverage, 25846,
     /*  498538 */     GIR_EraseRootFromParent_Done,
     /*  498539 */   // Label 7541: @498539
     /*  498539 */   GIM_Try, /*On fail goto*//*Label 7542*/ GIMT_Encode4(498595), // Rule ID 25847 //
     /*  498544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  498547 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498563 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498566 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498593 */     GIR_RootConstrainSelectedInstOperands,
     /*  498594 */     // GIR_Coverage, 25847,
     /*  498594 */     GIR_EraseRootFromParent_Done,
     /*  498595 */   // Label 7542: @498595
     /*  498595 */   GIM_Try, /*On fail goto*//*Label 7543*/ GIMT_Encode4(498651), // Rule ID 25848 //
     /*  498600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  498603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498608 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498612 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498619 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498622 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498645 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498649 */     GIR_RootConstrainSelectedInstOperands,
     /*  498650 */     // GIR_Coverage, 25848,
     /*  498650 */     GIR_EraseRootFromParent_Done,
     /*  498651 */   // Label 7543: @498651
     /*  498651 */   GIM_Try, /*On fail goto*//*Label 7544*/ GIMT_Encode4(498707), // Rule ID 25849 //
     /*  498656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  498659 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498675 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498678 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498705 */     GIR_RootConstrainSelectedInstOperands,
     /*  498706 */     // GIR_Coverage, 25849,
     /*  498706 */     GIR_EraseRootFromParent_Done,
     /*  498707 */   // Label 7544: @498707
     /*  498707 */   GIM_Try, /*On fail goto*//*Label 7545*/ GIMT_Encode4(498763), // Rule ID 25850 //
     /*  498712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  498715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498731 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  498734 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498761 */     GIR_RootConstrainSelectedInstOperands,
     /*  498762 */     // GIR_Coverage, 25850,
     /*  498762 */     GIR_EraseRootFromParent_Done,
     /*  498763 */   // Label 7545: @498763
     /*  498763 */   GIM_Try, /*On fail goto*//*Label 7546*/ GIMT_Encode4(498819), // Rule ID 25856 //
     /*  498768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  498771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498787 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498790 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498817 */     GIR_RootConstrainSelectedInstOperands,
     /*  498818 */     // GIR_Coverage, 25856,
     /*  498818 */     GIR_EraseRootFromParent_Done,
     /*  498819 */   // Label 7546: @498819
     /*  498819 */   GIM_Try, /*On fail goto*//*Label 7547*/ GIMT_Encode4(498875), // Rule ID 25857 //
     /*  498824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  498827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498843 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498846 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498869 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498873 */     GIR_RootConstrainSelectedInstOperands,
     /*  498874 */     // GIR_Coverage, 25857,
     /*  498874 */     GIR_EraseRootFromParent_Done,
     /*  498875 */   // Label 7547: @498875
     /*  498875 */   GIM_Try, /*On fail goto*//*Label 7548*/ GIMT_Encode4(498931), // Rule ID 25858 //
     /*  498880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  498883 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498888 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498899 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498902 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498929 */     GIR_RootConstrainSelectedInstOperands,
     /*  498930 */     // GIR_Coverage, 25858,
     /*  498930 */     GIR_EraseRootFromParent_Done,
     /*  498931 */   // Label 7548: @498931
     /*  498931 */   GIM_Try, /*On fail goto*//*Label 7549*/ GIMT_Encode4(498987), // Rule ID 25859 //
     /*  498936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  498939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  498944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  498948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  498955 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  498955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  498958 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  498960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  498965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  498970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  498975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  498981 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  498985 */     GIR_RootConstrainSelectedInstOperands,
     /*  498986 */     // GIR_Coverage, 25859,
     /*  498986 */     GIR_EraseRootFromParent_Done,
     /*  498987 */   // Label 7549: @498987
     /*  498987 */   GIM_Try, /*On fail goto*//*Label 7550*/ GIMT_Encode4(499043), // Rule ID 25860 //
     /*  498992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  498995 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499000 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499004 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  499011 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  499011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  499014 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  499016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  499021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  499026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499041 */     GIR_RootConstrainSelectedInstOperands,
     /*  499042 */     // GIR_Coverage, 25860,
     /*  499042 */     GIR_EraseRootFromParent_Done,
     /*  499043 */   // Label 7550: @499043
     /*  499043 */   GIM_Try, /*On fail goto*//*Label 7551*/ GIMT_Encode4(499098), // Rule ID 14137 //
     /*  499048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  499051 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499056 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499067 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499070 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499096 */     GIR_RootConstrainSelectedInstOperands,
     /*  499097 */     // GIR_Coverage, 14137,
     /*  499097 */     GIR_EraseRootFromParent_Done,
     /*  499098 */   // Label 7551: @499098
     /*  499098 */   GIM_Try, /*On fail goto*//*Label 7552*/ GIMT_Encode4(499153), // Rule ID 14138 //
     /*  499103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  499106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499122 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499125 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499151 */     GIR_RootConstrainSelectedInstOperands,
     /*  499152 */     // GIR_Coverage, 14138,
     /*  499152 */     GIR_EraseRootFromParent_Done,
     /*  499153 */   // Label 7552: @499153
     /*  499153 */   GIM_Try, /*On fail goto*//*Label 7553*/ GIMT_Encode4(499208), // Rule ID 14139 //
     /*  499158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  499161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499177 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499180 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499206 */     GIR_RootConstrainSelectedInstOperands,
     /*  499207 */     // GIR_Coverage, 14139,
     /*  499207 */     GIR_EraseRootFromParent_Done,
     /*  499208 */   // Label 7553: @499208
     /*  499208 */   GIM_Try, /*On fail goto*//*Label 7554*/ GIMT_Encode4(499263), // Rule ID 14140 //
     /*  499213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  499216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499232 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499235 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499261 */     GIR_RootConstrainSelectedInstOperands,
     /*  499262 */     // GIR_Coverage, 14140,
     /*  499262 */     GIR_EraseRootFromParent_Done,
     /*  499263 */   // Label 7554: @499263
     /*  499263 */   GIM_Try, /*On fail goto*//*Label 7555*/ GIMT_Encode4(499318), // Rule ID 14141 //
     /*  499268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  499271 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499280 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499287 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499290 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499316 */     GIR_RootConstrainSelectedInstOperands,
     /*  499317 */     // GIR_Coverage, 14141,
     /*  499317 */     GIR_EraseRootFromParent_Done,
     /*  499318 */   // Label 7555: @499318
     /*  499318 */   GIM_Try, /*On fail goto*//*Label 7556*/ GIMT_Encode4(499373), // Rule ID 14167 //
     /*  499323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  499326 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499342 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499345 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499367 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499371 */     GIR_RootConstrainSelectedInstOperands,
     /*  499372 */     // GIR_Coverage, 14167,
     /*  499372 */     GIR_EraseRootFromParent_Done,
     /*  499373 */   // Label 7556: @499373
     /*  499373 */   GIM_Try, /*On fail goto*//*Label 7557*/ GIMT_Encode4(499428), // Rule ID 14168 //
     /*  499378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  499381 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499397 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499400 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499426 */     GIR_RootConstrainSelectedInstOperands,
     /*  499427 */     // GIR_Coverage, 14168,
     /*  499427 */     GIR_EraseRootFromParent_Done,
     /*  499428 */   // Label 7557: @499428
     /*  499428 */   GIM_Try, /*On fail goto*//*Label 7558*/ GIMT_Encode4(499483), // Rule ID 14169 //
     /*  499433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  499436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499452 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499455 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499481 */     GIR_RootConstrainSelectedInstOperands,
     /*  499482 */     // GIR_Coverage, 14169,
     /*  499482 */     GIR_EraseRootFromParent_Done,
     /*  499483 */   // Label 7558: @499483
     /*  499483 */   GIM_Try, /*On fail goto*//*Label 7559*/ GIMT_Encode4(499538), // Rule ID 14170 //
     /*  499488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  499491 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499507 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499510 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499536 */     GIR_RootConstrainSelectedInstOperands,
     /*  499537 */     // GIR_Coverage, 14170,
     /*  499537 */     GIR_EraseRootFromParent_Done,
     /*  499538 */   // Label 7559: @499538
     /*  499538 */   GIM_Try, /*On fail goto*//*Label 7560*/ GIMT_Encode4(499593), // Rule ID 14171 //
     /*  499543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  499546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  499562 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  499562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
     /*  499565 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  499572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  499577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  499582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  499587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499591 */     GIR_RootConstrainSelectedInstOperands,
     /*  499592 */     // GIR_Coverage, 14171,
     /*  499592 */     GIR_EraseRootFromParent_Done,
     /*  499593 */   // Label 7560: @499593
     /*  499593 */   GIM_Try, /*On fail goto*//*Label 7561*/ GIMT_Encode4(499641), // Rule ID 14132 //
     /*  499598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  499601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499617 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499620 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499639 */     GIR_RootConstrainSelectedInstOperands,
     /*  499640 */     // GIR_Coverage, 14132,
     /*  499640 */     GIR_EraseRootFromParent_Done,
     /*  499641 */   // Label 7561: @499641
     /*  499641 */   GIM_Try, /*On fail goto*//*Label 7562*/ GIMT_Encode4(499689), // Rule ID 14133 //
     /*  499646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  499649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499665 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499668 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499683 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499687 */     GIR_RootConstrainSelectedInstOperands,
     /*  499688 */     // GIR_Coverage, 14133,
     /*  499688 */     GIR_EraseRootFromParent_Done,
     /*  499689 */   // Label 7562: @499689
     /*  499689 */   GIM_Try, /*On fail goto*//*Label 7563*/ GIMT_Encode4(499737), // Rule ID 14134 //
     /*  499694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  499697 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499706 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499713 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499716 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499735 */     GIR_RootConstrainSelectedInstOperands,
     /*  499736 */     // GIR_Coverage, 14134,
     /*  499736 */     GIR_EraseRootFromParent_Done,
     /*  499737 */   // Label 7563: @499737
     /*  499737 */   GIM_Try, /*On fail goto*//*Label 7564*/ GIMT_Encode4(499785), // Rule ID 14135 //
     /*  499742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  499745 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499754 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499761 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499764 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499783 */     GIR_RootConstrainSelectedInstOperands,
     /*  499784 */     // GIR_Coverage, 14135,
     /*  499784 */     GIR_EraseRootFromParent_Done,
     /*  499785 */   // Label 7564: @499785
     /*  499785 */   GIM_Try, /*On fail goto*//*Label 7565*/ GIMT_Encode4(499833), // Rule ID 14136 //
     /*  499790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  499793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499809 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499812 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499831 */     GIR_RootConstrainSelectedInstOperands,
     /*  499832 */     // GIR_Coverage, 14136,
     /*  499832 */     GIR_EraseRootFromParent_Done,
     /*  499833 */   // Label 7565: @499833
     /*  499833 */   GIM_Try, /*On fail goto*//*Label 7566*/ GIMT_Encode4(499881), // Rule ID 14162 //
     /*  499838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  499841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499857 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499860 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499879 */     GIR_RootConstrainSelectedInstOperands,
     /*  499880 */     // GIR_Coverage, 14162,
     /*  499880 */     GIR_EraseRootFromParent_Done,
     /*  499881 */   // Label 7566: @499881
     /*  499881 */   GIM_Try, /*On fail goto*//*Label 7567*/ GIMT_Encode4(499929), // Rule ID 14163 //
     /*  499886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  499889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499905 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499908 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499927 */     GIR_RootConstrainSelectedInstOperands,
     /*  499928 */     // GIR_Coverage, 14163,
     /*  499928 */     GIR_EraseRootFromParent_Done,
     /*  499929 */   // Label 7567: @499929
     /*  499929 */   GIM_Try, /*On fail goto*//*Label 7568*/ GIMT_Encode4(499977), // Rule ID 14164 //
     /*  499934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  499937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  499953 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  499953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  499956 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  499958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  499963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  499968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  499971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  499975 */     GIR_RootConstrainSelectedInstOperands,
     /*  499976 */     // GIR_Coverage, 14164,
     /*  499976 */     GIR_EraseRootFromParent_Done,
     /*  499977 */   // Label 7568: @499977
     /*  499977 */   GIM_Try, /*On fail goto*//*Label 7569*/ GIMT_Encode4(500025), // Rule ID 14165 //
     /*  499982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  499985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  499990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  499994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  500001 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  500001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  500004 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  500011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500023 */     GIR_RootConstrainSelectedInstOperands,
     /*  500024 */     // GIR_Coverage, 14165,
     /*  500024 */     GIR_EraseRootFromParent_Done,
     /*  500025 */   // Label 7569: @500025
     /*  500025 */   GIM_Try, /*On fail goto*//*Label 7570*/ GIMT_Encode4(500073), // Rule ID 14166 //
     /*  500030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  500033 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  500049 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  500049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
     /*  500052 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  500059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500071 */     GIR_RootConstrainSelectedInstOperands,
     /*  500072 */     // GIR_Coverage, 14166,
     /*  500072 */     GIR_EraseRootFromParent_Done,
     /*  500073 */   // Label 7570: @500073
     /*  500073 */   GIM_Try, /*On fail goto*//*Label 7571*/ GIMT_Encode4(500121), // Rule ID 14127 //
     /*  500078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  500081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500097 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500100 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500119 */     GIR_RootConstrainSelectedInstOperands,
     /*  500120 */     // GIR_Coverage, 14127,
     /*  500120 */     GIR_EraseRootFromParent_Done,
     /*  500121 */   // Label 7571: @500121
     /*  500121 */   GIM_Try, /*On fail goto*//*Label 7572*/ GIMT_Encode4(500169), // Rule ID 14128 //
     /*  500126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  500129 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500145 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500148 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500167 */     GIR_RootConstrainSelectedInstOperands,
     /*  500168 */     // GIR_Coverage, 14128,
     /*  500168 */     GIR_EraseRootFromParent_Done,
     /*  500169 */   // Label 7572: @500169
     /*  500169 */   GIM_Try, /*On fail goto*//*Label 7573*/ GIMT_Encode4(500217), // Rule ID 14129 //
     /*  500174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  500177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500193 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500196 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500215 */     GIR_RootConstrainSelectedInstOperands,
     /*  500216 */     // GIR_Coverage, 14129,
     /*  500216 */     GIR_EraseRootFromParent_Done,
     /*  500217 */   // Label 7573: @500217
     /*  500217 */   GIM_Try, /*On fail goto*//*Label 7574*/ GIMT_Encode4(500265), // Rule ID 14130 //
     /*  500222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  500225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500241 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500244 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500263 */     GIR_RootConstrainSelectedInstOperands,
     /*  500264 */     // GIR_Coverage, 14130,
     /*  500264 */     GIR_EraseRootFromParent_Done,
     /*  500265 */   // Label 7574: @500265
     /*  500265 */   GIM_Try, /*On fail goto*//*Label 7575*/ GIMT_Encode4(500313), // Rule ID 14131 //
     /*  500270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  500273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500289 */     // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500292 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500311 */     GIR_RootConstrainSelectedInstOperands,
     /*  500312 */     // GIR_Coverage, 14131,
     /*  500312 */     GIR_EraseRootFromParent_Done,
     /*  500313 */   // Label 7575: @500313
     /*  500313 */   GIM_Try, /*On fail goto*//*Label 7576*/ GIMT_Encode4(500361), // Rule ID 14157 //
     /*  500318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  500321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500326 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500337 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500340 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500352 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500355 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500359 */     GIR_RootConstrainSelectedInstOperands,
     /*  500360 */     // GIR_Coverage, 14157,
     /*  500360 */     GIR_EraseRootFromParent_Done,
     /*  500361 */   // Label 7576: @500361
     /*  500361 */   GIM_Try, /*On fail goto*//*Label 7577*/ GIMT_Encode4(500409), // Rule ID 14158 //
     /*  500366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  500369 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500385 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500388 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500403 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500407 */     GIR_RootConstrainSelectedInstOperands,
     /*  500408 */     // GIR_Coverage, 14158,
     /*  500408 */     GIR_EraseRootFromParent_Done,
     /*  500409 */   // Label 7577: @500409
     /*  500409 */   GIM_Try, /*On fail goto*//*Label 7578*/ GIMT_Encode4(500457), // Rule ID 14159 //
     /*  500414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  500417 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500433 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500436 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500455 */     GIR_RootConstrainSelectedInstOperands,
     /*  500456 */     // GIR_Coverage, 14159,
     /*  500456 */     GIR_EraseRootFromParent_Done,
     /*  500457 */   // Label 7578: @500457
     /*  500457 */   GIM_Try, /*On fail goto*//*Label 7579*/ GIMT_Encode4(500505), // Rule ID 14160 //
     /*  500462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  500465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500470 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500474 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500481 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500484 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500503 */     GIR_RootConstrainSelectedInstOperands,
     /*  500504 */     // GIR_Coverage, 14160,
     /*  500504 */     GIR_EraseRootFromParent_Done,
     /*  500505 */   // Label 7579: @500505
     /*  500505 */   GIM_Try, /*On fail goto*//*Label 7580*/ GIMT_Encode4(500553), // Rule ID 14161 //
     /*  500510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  500513 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  500518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  500529 */     // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  500529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
     /*  500532 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  500534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  500539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  500544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500551 */     GIR_RootConstrainSelectedInstOperands,
     /*  500552 */     // GIR_Coverage, 14161,
     /*  500552 */     GIR_EraseRootFromParent_Done,
     /*  500553 */   // Label 7580: @500553
     /*  500553 */   GIM_Try, /*On fail goto*//*Label 7581*/ GIMT_Encode4(500616), // Rule ID 15938 //
     /*  500558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  500561 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500579 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  500582 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500614 */     GIR_RootConstrainSelectedInstOperands,
     /*  500615 */     // GIR_Coverage, 15938,
     /*  500615 */     GIR_EraseRootFromParent_Done,
     /*  500616 */   // Label 7581: @500616
     /*  500616 */   GIM_Try, /*On fail goto*//*Label 7582*/ GIMT_Encode4(500679), // Rule ID 15939 //
     /*  500621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  500624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500642 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  500645 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500677 */     GIR_RootConstrainSelectedInstOperands,
     /*  500678 */     // GIR_Coverage, 15939,
     /*  500678 */     GIR_EraseRootFromParent_Done,
     /*  500679 */   // Label 7582: @500679
     /*  500679 */   GIM_Try, /*On fail goto*//*Label 7583*/ GIMT_Encode4(500742), // Rule ID 15940 //
     /*  500684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  500687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500705 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  500708 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500740 */     GIR_RootConstrainSelectedInstOperands,
     /*  500741 */     // GIR_Coverage, 15940,
     /*  500741 */     GIR_EraseRootFromParent_Done,
     /*  500742 */   // Label 7583: @500742
     /*  500742 */   GIM_Try, /*On fail goto*//*Label 7584*/ GIMT_Encode4(500805), // Rule ID 15941 //
     /*  500747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  500750 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500757 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500768 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  500771 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500803 */     GIR_RootConstrainSelectedInstOperands,
     /*  500804 */     // GIR_Coverage, 15941,
     /*  500804 */     GIR_EraseRootFromParent_Done,
     /*  500805 */   // Label 7584: @500805
     /*  500805 */   GIM_Try, /*On fail goto*//*Label 7585*/ GIMT_Encode4(500868), // Rule ID 15942 //
     /*  500810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  500813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500820 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500824 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500831 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  500834 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500866 */     GIR_RootConstrainSelectedInstOperands,
     /*  500867 */     // GIR_Coverage, 15942,
     /*  500867 */     GIR_EraseRootFromParent_Done,
     /*  500868 */   // Label 7585: @500868
     /*  500868 */   GIM_Try, /*On fail goto*//*Label 7586*/ GIMT_Encode4(500931), // Rule ID 15948 //
     /*  500873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  500876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500894 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  500897 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500929 */     GIR_RootConstrainSelectedInstOperands,
     /*  500930 */     // GIR_Coverage, 15948,
     /*  500930 */     GIR_EraseRootFromParent_Done,
     /*  500931 */   // Label 7586: @500931
     /*  500931 */   GIM_Try, /*On fail goto*//*Label 7587*/ GIMT_Encode4(500994), // Rule ID 15949 //
     /*  500936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  500939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  500946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  500950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  500957 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  500957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  500960 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  500962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  500967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  500972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  500977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  500982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  500988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  500992 */     GIR_RootConstrainSelectedInstOperands,
     /*  500993 */     // GIR_Coverage, 15949,
     /*  500993 */     GIR_EraseRootFromParent_Done,
     /*  500994 */   // Label 7587: @500994
     /*  500994 */   GIM_Try, /*On fail goto*//*Label 7588*/ GIMT_Encode4(501057), // Rule ID 15950 //
     /*  500999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  501002 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501020 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501023 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501055 */     GIR_RootConstrainSelectedInstOperands,
     /*  501056 */     // GIR_Coverage, 15950,
     /*  501056 */     GIR_EraseRootFromParent_Done,
     /*  501057 */   // Label 7588: @501057
     /*  501057 */   GIM_Try, /*On fail goto*//*Label 7589*/ GIMT_Encode4(501120), // Rule ID 15951 //
     /*  501062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  501065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501083 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501086 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501118 */     GIR_RootConstrainSelectedInstOperands,
     /*  501119 */     // GIR_Coverage, 15951,
     /*  501119 */     GIR_EraseRootFromParent_Done,
     /*  501120 */   // Label 7589: @501120
     /*  501120 */   GIM_Try, /*On fail goto*//*Label 7590*/ GIMT_Encode4(501183), // Rule ID 15952 //
     /*  501125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  501128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501146 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501149 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501181 */     GIR_RootConstrainSelectedInstOperands,
     /*  501182 */     // GIR_Coverage, 15952,
     /*  501182 */     GIR_EraseRootFromParent_Done,
     /*  501183 */   // Label 7590: @501183
     /*  501183 */   GIM_Try, /*On fail goto*//*Label 7591*/ GIMT_Encode4(501246), // Rule ID 15958 //
     /*  501188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  501191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501202 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501209 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  501212 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501244 */     GIR_RootConstrainSelectedInstOperands,
     /*  501245 */     // GIR_Coverage, 15958,
     /*  501245 */     GIR_EraseRootFromParent_Done,
     /*  501246 */   // Label 7591: @501246
     /*  501246 */   GIM_Try, /*On fail goto*//*Label 7592*/ GIMT_Encode4(501309), // Rule ID 15959 //
     /*  501251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  501254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501265 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501272 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  501275 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501307 */     GIR_RootConstrainSelectedInstOperands,
     /*  501308 */     // GIR_Coverage, 15959,
     /*  501308 */     GIR_EraseRootFromParent_Done,
     /*  501309 */   // Label 7592: @501309
     /*  501309 */   GIM_Try, /*On fail goto*//*Label 7593*/ GIMT_Encode4(501372), // Rule ID 15960 //
     /*  501314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  501317 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501335 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  501338 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501370 */     GIR_RootConstrainSelectedInstOperands,
     /*  501371 */     // GIR_Coverage, 15960,
     /*  501371 */     GIR_EraseRootFromParent_Done,
     /*  501372 */   // Label 7593: @501372
     /*  501372 */   GIM_Try, /*On fail goto*//*Label 7594*/ GIMT_Encode4(501435), // Rule ID 15961 //
     /*  501377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  501380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501398 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  501401 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501433 */     GIR_RootConstrainSelectedInstOperands,
     /*  501434 */     // GIR_Coverage, 15961,
     /*  501434 */     GIR_EraseRootFromParent_Done,
     /*  501435 */   // Label 7594: @501435
     /*  501435 */   GIM_Try, /*On fail goto*//*Label 7595*/ GIMT_Encode4(501498), // Rule ID 15962 //
     /*  501440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  501443 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501461 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
     /*  501464 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501492 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501496 */     GIR_RootConstrainSelectedInstOperands,
     /*  501497 */     // GIR_Coverage, 15962,
     /*  501497 */     GIR_EraseRootFromParent_Done,
     /*  501498 */   // Label 7595: @501498
     /*  501498 */   GIM_Try, /*On fail goto*//*Label 7596*/ GIMT_Encode4(501561), // Rule ID 15968 //
     /*  501503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  501506 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501524 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501527 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501559 */     GIR_RootConstrainSelectedInstOperands,
     /*  501560 */     // GIR_Coverage, 15968,
     /*  501560 */     GIR_EraseRootFromParent_Done,
     /*  501561 */   // Label 7596: @501561
     /*  501561 */   GIM_Try, /*On fail goto*//*Label 7597*/ GIMT_Encode4(501624), // Rule ID 15969 //
     /*  501566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  501569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501576 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501580 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501587 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501590 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501622 */     GIR_RootConstrainSelectedInstOperands,
     /*  501623 */     // GIR_Coverage, 15969,
     /*  501623 */     GIR_EraseRootFromParent_Done,
     /*  501624 */   // Label 7597: @501624
     /*  501624 */   GIM_Try, /*On fail goto*//*Label 7598*/ GIMT_Encode4(501687), // Rule ID 15970 //
     /*  501629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  501632 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501650 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501653 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501681 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501685 */     GIR_RootConstrainSelectedInstOperands,
     /*  501686 */     // GIR_Coverage, 15970,
     /*  501686 */     GIR_EraseRootFromParent_Done,
     /*  501687 */   // Label 7598: @501687
     /*  501687 */   GIM_Try, /*On fail goto*//*Label 7599*/ GIMT_Encode4(501750), // Rule ID 15971 //
     /*  501692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  501695 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501706 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501713 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501716 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501748 */     GIR_RootConstrainSelectedInstOperands,
     /*  501749 */     // GIR_Coverage, 15971,
     /*  501749 */     GIR_EraseRootFromParent_Done,
     /*  501750 */   // Label 7599: @501750
     /*  501750 */   GIM_Try, /*On fail goto*//*Label 7600*/ GIMT_Encode4(501813), // Rule ID 15972 //
     /*  501755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  501758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  501765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  501776 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  501776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
     /*  501779 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  501781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501811 */     GIR_RootConstrainSelectedInstOperands,
     /*  501812 */     // GIR_Coverage, 15972,
     /*  501812 */     GIR_EraseRootFromParent_Done,
     /*  501813 */   // Label 7600: @501813
     /*  501813 */   GIM_Try, /*On fail goto*//*Label 7601*/ GIMT_Encode4(501874), // Rule ID 25821 //
     /*  501818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  501821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  501826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  501837 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  501837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  501840 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  501842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501872 */     GIR_RootConstrainSelectedInstOperands,
     /*  501873 */     // GIR_Coverage, 25821,
     /*  501873 */     GIR_EraseRootFromParent_Done,
     /*  501874 */   // Label 7601: @501874
     /*  501874 */   GIM_Try, /*On fail goto*//*Label 7602*/ GIMT_Encode4(501935), // Rule ID 25822 //
     /*  501879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  501882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  501887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  501898 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  501898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  501901 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  501903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501933 */     GIR_RootConstrainSelectedInstOperands,
     /*  501934 */     // GIR_Coverage, 25822,
     /*  501934 */     GIR_EraseRootFromParent_Done,
     /*  501935 */   // Label 7602: @501935
     /*  501935 */   GIM_Try, /*On fail goto*//*Label 7603*/ GIMT_Encode4(501996), // Rule ID 25823 //
     /*  501940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  501943 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  501948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  501952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  501959 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  501959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  501962 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  501964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  501969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  501974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  501979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  501984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  501990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  501994 */     GIR_RootConstrainSelectedInstOperands,
     /*  501995 */     // GIR_Coverage, 25823,
     /*  501995 */     GIR_EraseRootFromParent_Done,
     /*  501996 */   // Label 7603: @501996
     /*  501996 */   GIM_Try, /*On fail goto*//*Label 7604*/ GIMT_Encode4(502057), // Rule ID 25824 //
     /*  502001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  502004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502020 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502023 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502055 */     GIR_RootConstrainSelectedInstOperands,
     /*  502056 */     // GIR_Coverage, 25824,
     /*  502056 */     GIR_EraseRootFromParent_Done,
     /*  502057 */   // Label 7604: @502057
     /*  502057 */   GIM_Try, /*On fail goto*//*Label 7605*/ GIMT_Encode4(502118), // Rule ID 25825 //
     /*  502062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  502065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502081 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502084 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502112 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502116 */     GIR_RootConstrainSelectedInstOperands,
     /*  502117 */     // GIR_Coverage, 25825,
     /*  502117 */     GIR_EraseRootFromParent_Done,
     /*  502118 */   // Label 7605: @502118
     /*  502118 */   GIM_Try, /*On fail goto*//*Label 7606*/ GIMT_Encode4(502179), // Rule ID 25831 //
     /*  502123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  502126 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502142 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502145 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502177 */     GIR_RootConstrainSelectedInstOperands,
     /*  502178 */     // GIR_Coverage, 25831,
     /*  502178 */     GIR_EraseRootFromParent_Done,
     /*  502179 */   // Label 7606: @502179
     /*  502179 */   GIM_Try, /*On fail goto*//*Label 7607*/ GIMT_Encode4(502240), // Rule ID 25832 //
     /*  502184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  502187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502203 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502206 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502238 */     GIR_RootConstrainSelectedInstOperands,
     /*  502239 */     // GIR_Coverage, 25832,
     /*  502239 */     GIR_EraseRootFromParent_Done,
     /*  502240 */   // Label 7607: @502240
     /*  502240 */   GIM_Try, /*On fail goto*//*Label 7608*/ GIMT_Encode4(502301), // Rule ID 25833 //
     /*  502245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  502248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502264 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502267 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502289 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502295 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502299 */     GIR_RootConstrainSelectedInstOperands,
     /*  502300 */     // GIR_Coverage, 25833,
     /*  502300 */     GIR_EraseRootFromParent_Done,
     /*  502301 */   // Label 7608: @502301
     /*  502301 */   GIM_Try, /*On fail goto*//*Label 7609*/ GIMT_Encode4(502362), // Rule ID 25834 //
     /*  502306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  502309 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502314 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502318 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502325 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502328 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502360 */     GIR_RootConstrainSelectedInstOperands,
     /*  502361 */     // GIR_Coverage, 25834,
     /*  502361 */     GIR_EraseRootFromParent_Done,
     /*  502362 */   // Label 7609: @502362
     /*  502362 */   GIM_Try, /*On fail goto*//*Label 7610*/ GIMT_Encode4(502423), // Rule ID 25835 //
     /*  502367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  502370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502386 */     // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502389 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502414 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502417 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502421 */     GIR_RootConstrainSelectedInstOperands,
     /*  502422 */     // GIR_Coverage, 25835,
     /*  502422 */     GIR_EraseRootFromParent_Done,
     /*  502423 */   // Label 7610: @502423
     /*  502423 */   GIM_Try, /*On fail goto*//*Label 7611*/ GIMT_Encode4(502484), // Rule ID 25841 //
     /*  502428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  502431 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502447 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502450 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502482 */     GIR_RootConstrainSelectedInstOperands,
     /*  502483 */     // GIR_Coverage, 25841,
     /*  502483 */     GIR_EraseRootFromParent_Done,
     /*  502484 */   // Label 7611: @502484
     /*  502484 */   GIM_Try, /*On fail goto*//*Label 7612*/ GIMT_Encode4(502545), // Rule ID 25842 //
     /*  502489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  502492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502508 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502511 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502533 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502543 */     GIR_RootConstrainSelectedInstOperands,
     /*  502544 */     // GIR_Coverage, 25842,
     /*  502544 */     GIR_EraseRootFromParent_Done,
     /*  502545 */   // Label 7612: @502545
     /*  502545 */   GIM_Try, /*On fail goto*//*Label 7613*/ GIMT_Encode4(502606), // Rule ID 25843 //
     /*  502550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  502553 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502569 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502572 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502604 */     GIR_RootConstrainSelectedInstOperands,
     /*  502605 */     // GIR_Coverage, 25843,
     /*  502605 */     GIR_EraseRootFromParent_Done,
     /*  502606 */   // Label 7613: @502606
     /*  502606 */   GIM_Try, /*On fail goto*//*Label 7614*/ GIMT_Encode4(502667), // Rule ID 25844 //
     /*  502611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  502614 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502630 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502633 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502665 */     GIR_RootConstrainSelectedInstOperands,
     /*  502666 */     // GIR_Coverage, 25844,
     /*  502666 */     GIR_EraseRootFromParent_Done,
     /*  502667 */   // Label 7614: @502667
     /*  502667 */   GIM_Try, /*On fail goto*//*Label 7615*/ GIMT_Encode4(502728), // Rule ID 25845 //
     /*  502672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  502675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502691 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
     /*  502694 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502726 */     GIR_RootConstrainSelectedInstOperands,
     /*  502727 */     // GIR_Coverage, 25845,
     /*  502727 */     GIR_EraseRootFromParent_Done,
     /*  502728 */   // Label 7615: @502728
     /*  502728 */   GIM_Try, /*On fail goto*//*Label 7616*/ GIMT_Encode4(502789), // Rule ID 25851 //
     /*  502733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  502736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502752 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502755 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502787 */     GIR_RootConstrainSelectedInstOperands,
     /*  502788 */     // GIR_Coverage, 25851,
     /*  502788 */     GIR_EraseRootFromParent_Done,
     /*  502789 */   // Label 7616: @502789
     /*  502789 */   GIM_Try, /*On fail goto*//*Label 7617*/ GIMT_Encode4(502850), // Rule ID 25852 //
     /*  502794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  502797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502813 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502816 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502848 */     GIR_RootConstrainSelectedInstOperands,
     /*  502849 */     // GIR_Coverage, 25852,
     /*  502849 */     GIR_EraseRootFromParent_Done,
     /*  502850 */   // Label 7617: @502850
     /*  502850 */   GIM_Try, /*On fail goto*//*Label 7618*/ GIMT_Encode4(502911), // Rule ID 25853 //
     /*  502855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  502858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502874 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502877 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502909 */     GIR_RootConstrainSelectedInstOperands,
     /*  502910 */     // GIR_Coverage, 25853,
     /*  502910 */     GIR_EraseRootFromParent_Done,
     /*  502911 */   // Label 7618: @502911
     /*  502911 */   GIM_Try, /*On fail goto*//*Label 7619*/ GIMT_Encode4(502972), // Rule ID 25854 //
     /*  502916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  502919 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502935 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502938 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  502940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  502945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  502950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  502955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  502960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  502966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  502970 */     GIR_RootConstrainSelectedInstOperands,
     /*  502971 */     // GIR_Coverage, 25854,
     /*  502971 */     GIR_EraseRootFromParent_Done,
     /*  502972 */   // Label 7619: @502972
     /*  502972 */   GIM_Try, /*On fail goto*//*Label 7620*/ GIMT_Encode4(503033), // Rule ID 25855 //
     /*  502977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  502980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  502985 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  502989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  502996 */     // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  502996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
     /*  502999 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  503001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  503006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  503016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  503021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503031 */     GIR_RootConstrainSelectedInstOperands,
     /*  503032 */     // GIR_Coverage, 25855,
     /*  503032 */     GIR_EraseRootFromParent_Done,
     /*  503033 */   // Label 7620: @503033
     /*  503033 */   GIM_Try, /*On fail goto*//*Label 7621*/ GIMT_Encode4(503091), // Rule ID 15933 //
     /*  503038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  503041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503059 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503062 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503089 */     GIR_RootConstrainSelectedInstOperands,
     /*  503090 */     // GIR_Coverage, 15933,
     /*  503090 */     GIR_EraseRootFromParent_Done,
     /*  503091 */   // Label 7621: @503091
     /*  503091 */   GIM_Try, /*On fail goto*//*Label 7622*/ GIMT_Encode4(503149), // Rule ID 15934 //
     /*  503096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  503099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503117 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503120 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503147 */     GIR_RootConstrainSelectedInstOperands,
     /*  503148 */     // GIR_Coverage, 15934,
     /*  503148 */     GIR_EraseRootFromParent_Done,
     /*  503149 */   // Label 7622: @503149
     /*  503149 */   GIM_Try, /*On fail goto*//*Label 7623*/ GIMT_Encode4(503207), // Rule ID 15935 //
     /*  503154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  503157 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503175 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503178 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503205 */     GIR_RootConstrainSelectedInstOperands,
     /*  503206 */     // GIR_Coverage, 15935,
     /*  503206 */     GIR_EraseRootFromParent_Done,
     /*  503207 */   // Label 7623: @503207
     /*  503207 */   GIM_Try, /*On fail goto*//*Label 7624*/ GIMT_Encode4(503265), // Rule ID 15936 //
     /*  503212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  503215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503233 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503236 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503263 */     GIR_RootConstrainSelectedInstOperands,
     /*  503264 */     // GIR_Coverage, 15936,
     /*  503264 */     GIR_EraseRootFromParent_Done,
     /*  503265 */   // Label 7624: @503265
     /*  503265 */   GIM_Try, /*On fail goto*//*Label 7625*/ GIMT_Encode4(503323), // Rule ID 15937 //
     /*  503270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  503273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503291 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503294 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503321 */     GIR_RootConstrainSelectedInstOperands,
     /*  503322 */     // GIR_Coverage, 15937,
     /*  503322 */     GIR_EraseRootFromParent_Done,
     /*  503323 */   // Label 7625: @503323
     /*  503323 */   GIM_Try, /*On fail goto*//*Label 7626*/ GIMT_Encode4(503381), // Rule ID 15943 //
     /*  503328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  503331 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503349 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503352 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503375 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503379 */     GIR_RootConstrainSelectedInstOperands,
     /*  503380 */     // GIR_Coverage, 15943,
     /*  503380 */     GIR_EraseRootFromParent_Done,
     /*  503381 */   // Label 7626: @503381
     /*  503381 */   GIM_Try, /*On fail goto*//*Label 7627*/ GIMT_Encode4(503439), // Rule ID 15944 //
     /*  503386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  503389 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503407 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503410 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503437 */     GIR_RootConstrainSelectedInstOperands,
     /*  503438 */     // GIR_Coverage, 15944,
     /*  503438 */     GIR_EraseRootFromParent_Done,
     /*  503439 */   // Label 7627: @503439
     /*  503439 */   GIM_Try, /*On fail goto*//*Label 7628*/ GIMT_Encode4(503497), // Rule ID 15945 //
     /*  503444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  503447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503465 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503468 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503495 */     GIR_RootConstrainSelectedInstOperands,
     /*  503496 */     // GIR_Coverage, 15945,
     /*  503496 */     GIR_EraseRootFromParent_Done,
     /*  503497 */   // Label 7628: @503497
     /*  503497 */   GIM_Try, /*On fail goto*//*Label 7629*/ GIMT_Encode4(503555), // Rule ID 15946 //
     /*  503502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  503505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503512 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503516 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503523 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503526 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503553 */     GIR_RootConstrainSelectedInstOperands,
     /*  503554 */     // GIR_Coverage, 15946,
     /*  503554 */     GIR_EraseRootFromParent_Done,
     /*  503555 */   // Label 7629: @503555
     /*  503555 */   GIM_Try, /*On fail goto*//*Label 7630*/ GIMT_Encode4(503613), // Rule ID 15947 //
     /*  503560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  503563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503581 */     // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503584 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503611 */     GIR_RootConstrainSelectedInstOperands,
     /*  503612 */     // GIR_Coverage, 15947,
     /*  503612 */     GIR_EraseRootFromParent_Done,
     /*  503613 */   // Label 7630: @503613
     /*  503613 */   GIM_Try, /*On fail goto*//*Label 7631*/ GIMT_Encode4(503671), // Rule ID 15953 //
     /*  503618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  503621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503639 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503642 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503662 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503669 */     GIR_RootConstrainSelectedInstOperands,
     /*  503670 */     // GIR_Coverage, 15953,
     /*  503670 */     GIR_EraseRootFromParent_Done,
     /*  503671 */   // Label 7631: @503671
     /*  503671 */   GIM_Try, /*On fail goto*//*Label 7632*/ GIMT_Encode4(503729), // Rule ID 15954 //
     /*  503676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  503679 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503697 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503700 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503727 */     GIR_RootConstrainSelectedInstOperands,
     /*  503728 */     // GIR_Coverage, 15954,
     /*  503728 */     GIR_EraseRootFromParent_Done,
     /*  503729 */   // Label 7632: @503729
     /*  503729 */   GIM_Try, /*On fail goto*//*Label 7633*/ GIMT_Encode4(503787), // Rule ID 15955 //
     /*  503734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  503737 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503755 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503758 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503785 */     GIR_RootConstrainSelectedInstOperands,
     /*  503786 */     // GIR_Coverage, 15955,
     /*  503786 */     GIR_EraseRootFromParent_Done,
     /*  503787 */   // Label 7633: @503787
     /*  503787 */   GIM_Try, /*On fail goto*//*Label 7634*/ GIMT_Encode4(503845), // Rule ID 15956 //
     /*  503792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  503795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503813 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503816 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503843 */     GIR_RootConstrainSelectedInstOperands,
     /*  503844 */     // GIR_Coverage, 15956,
     /*  503844 */     GIR_EraseRootFromParent_Done,
     /*  503845 */   // Label 7634: @503845
     /*  503845 */   GIM_Try, /*On fail goto*//*Label 7635*/ GIMT_Encode4(503903), // Rule ID 15957 //
     /*  503850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  503853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503860 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503871 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
     /*  503874 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503901 */     GIR_RootConstrainSelectedInstOperands,
     /*  503902 */     // GIR_Coverage, 15957,
     /*  503902 */     GIR_EraseRootFromParent_Done,
     /*  503903 */   // Label 7635: @503903
     /*  503903 */   GIM_Try, /*On fail goto*//*Label 7636*/ GIMT_Encode4(503961), // Rule ID 15963 //
     /*  503908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  503911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503929 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503932 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  503944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  503949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  503955 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  503959 */     GIR_RootConstrainSelectedInstOperands,
     /*  503960 */     // GIR_Coverage, 15963,
     /*  503960 */     GIR_EraseRootFromParent_Done,
     /*  503961 */   // Label 7636: @503961
     /*  503961 */   GIM_Try, /*On fail goto*//*Label 7637*/ GIMT_Encode4(504019), // Rule ID 15964 //
     /*  503966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  503969 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  503976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  503980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  503987 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  503987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  503990 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  503992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  503997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  504002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  504007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504017 */     GIR_RootConstrainSelectedInstOperands,
     /*  504018 */     // GIR_Coverage, 15964,
     /*  504018 */     GIR_EraseRootFromParent_Done,
     /*  504019 */   // Label 7637: @504019
     /*  504019 */   GIM_Try, /*On fail goto*//*Label 7638*/ GIMT_Encode4(504077), // Rule ID 15965 //
     /*  504024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  504027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  504034 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504038 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  504045 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  504045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  504048 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  504050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  504055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  504060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  504065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504075 */     GIR_RootConstrainSelectedInstOperands,
     /*  504076 */     // GIR_Coverage, 15965,
     /*  504076 */     GIR_EraseRootFromParent_Done,
     /*  504077 */   // Label 7638: @504077
     /*  504077 */   GIM_Try, /*On fail goto*//*Label 7639*/ GIMT_Encode4(504135), // Rule ID 15966 //
     /*  504082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  504085 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  504092 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504096 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  504103 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  504103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  504106 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  504108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  504113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  504118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  504123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504133 */     GIR_RootConstrainSelectedInstOperands,
     /*  504134 */     // GIR_Coverage, 15966,
     /*  504134 */     GIR_EraseRootFromParent_Done,
     /*  504135 */   // Label 7639: @504135
     /*  504135 */   GIM_Try, /*On fail goto*//*Label 7640*/ GIMT_Encode4(504193), // Rule ID 15967 //
     /*  504140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  504143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  504150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  504161 */     // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  504161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
     /*  504164 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  504166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  504171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  504176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  504181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504191 */     GIR_RootConstrainSelectedInstOperands,
     /*  504192 */     // GIR_Coverage, 15967,
     /*  504192 */     GIR_EraseRootFromParent_Done,
     /*  504193 */   // Label 7640: @504193
     /*  504193 */   GIM_Try, /*On fail goto*//*Label 7641*/ GIMT_Encode4(504245), // Rule ID 29243 //
     /*  504198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  504201 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504221 */     // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504229 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504243 */     GIR_RootConstrainSelectedInstOperands,
     /*  504244 */     // GIR_Coverage, 29243,
     /*  504244 */     GIR_EraseRootFromParent_Done,
     /*  504245 */   // Label 7641: @504245
     /*  504245 */   GIM_Try, /*On fail goto*//*Label 7642*/ GIMT_Encode4(504297), // Rule ID 29244 //
     /*  504250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  504253 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504266 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504273 */     // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504281 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504288 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504291 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504295 */     GIR_RootConstrainSelectedInstOperands,
     /*  504296 */     // GIR_Coverage, 29244,
     /*  504296 */     GIR_EraseRootFromParent_Done,
     /*  504297 */   // Label 7642: @504297
     /*  504297 */   GIM_Try, /*On fail goto*//*Label 7643*/ GIMT_Encode4(504349), // Rule ID 29245 //
     /*  504302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  504305 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504309 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504314 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504318 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504325 */     // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504333 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504340 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504343 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504347 */     GIR_RootConstrainSelectedInstOperands,
     /*  504348 */     // GIR_Coverage, 29245,
     /*  504348 */     GIR_EraseRootFromParent_Done,
     /*  504349 */   // Label 7643: @504349
     /*  504349 */   GIM_Try, /*On fail goto*//*Label 7644*/ GIMT_Encode4(504401), // Rule ID 29246 //
     /*  504354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  504357 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504377 */     // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504385 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504399 */     GIR_RootConstrainSelectedInstOperands,
     /*  504400 */     // GIR_Coverage, 29246,
     /*  504400 */     GIR_EraseRootFromParent_Done,
     /*  504401 */   // Label 7644: @504401
     /*  504401 */   GIM_Try, /*On fail goto*//*Label 7645*/ GIMT_Encode4(504453), // Rule ID 29247 //
     /*  504406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  504409 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504413 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504429 */     // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504437 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504451 */     GIR_RootConstrainSelectedInstOperands,
     /*  504452 */     // GIR_Coverage, 29247,
     /*  504452 */     GIR_EraseRootFromParent_Done,
     /*  504453 */   // Label 7645: @504453
     /*  504453 */   GIM_Try, /*On fail goto*//*Label 7646*/ GIMT_Encode4(504505), // Rule ID 29253 //
     /*  504458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  504461 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504470 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504474 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504481 */     // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504489 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504503 */     GIR_RootConstrainSelectedInstOperands,
     /*  504504 */     // GIR_Coverage, 29253,
     /*  504504 */     GIR_EraseRootFromParent_Done,
     /*  504505 */   // Label 7646: @504505
     /*  504505 */   GIM_Try, /*On fail goto*//*Label 7647*/ GIMT_Encode4(504557), // Rule ID 29254 //
     /*  504510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  504513 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504533 */     // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504541 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504555 */     GIR_RootConstrainSelectedInstOperands,
     /*  504556 */     // GIR_Coverage, 29254,
     /*  504556 */     GIR_EraseRootFromParent_Done,
     /*  504557 */   // Label 7647: @504557
     /*  504557 */   GIM_Try, /*On fail goto*//*Label 7648*/ GIMT_Encode4(504609), // Rule ID 29255 //
     /*  504562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  504565 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504574 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504578 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504585 */     // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504593 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504607 */     GIR_RootConstrainSelectedInstOperands,
     /*  504608 */     // GIR_Coverage, 29255,
     /*  504608 */     GIR_EraseRootFromParent_Done,
     /*  504609 */   // Label 7648: @504609
     /*  504609 */   GIM_Try, /*On fail goto*//*Label 7649*/ GIMT_Encode4(504661), // Rule ID 29256 //
     /*  504614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  504617 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504626 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504637 */     // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504645 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504659 */     GIR_RootConstrainSelectedInstOperands,
     /*  504660 */     // GIR_Coverage, 29256,
     /*  504660 */     GIR_EraseRootFromParent_Done,
     /*  504661 */   // Label 7649: @504661
     /*  504661 */   GIM_Try, /*On fail goto*//*Label 7650*/ GIMT_Encode4(504713), // Rule ID 29257 //
     /*  504666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  504669 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  504673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504682 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504689 */     // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
     /*  504692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504697 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504711 */     GIR_RootConstrainSelectedInstOperands,
     /*  504712 */     // GIR_Coverage, 29257,
     /*  504712 */     GIR_EraseRootFromParent_Done,
     /*  504713 */   // Label 7650: @504713
     /*  504713 */   GIM_Try, /*On fail goto*//*Label 7651*/ GIMT_Encode4(504761), // Rule ID 29248 //
     /*  504718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  504721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504726 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504730 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504737 */     // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  504740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504745 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504759 */     GIR_RootConstrainSelectedInstOperands,
     /*  504760 */     // GIR_Coverage, 29248,
     /*  504760 */     GIR_EraseRootFromParent_Done,
     /*  504761 */   // Label 7651: @504761
     /*  504761 */   GIM_Try, /*On fail goto*//*Label 7652*/ GIMT_Encode4(504809), // Rule ID 29249 //
     /*  504766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  504769 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504785 */     // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  504788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504793 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504807 */     GIR_RootConstrainSelectedInstOperands,
     /*  504808 */     // GIR_Coverage, 29249,
     /*  504808 */     GIR_EraseRootFromParent_Done,
     /*  504809 */   // Label 7652: @504809
     /*  504809 */   GIM_Try, /*On fail goto*//*Label 7653*/ GIMT_Encode4(504857), // Rule ID 29250 //
     /*  504814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  504817 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504833 */     // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  504836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504841 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504855 */     GIR_RootConstrainSelectedInstOperands,
     /*  504856 */     // GIR_Coverage, 29250,
     /*  504856 */     GIR_EraseRootFromParent_Done,
     /*  504857 */   // Label 7653: @504857
     /*  504857 */   GIM_Try, /*On fail goto*//*Label 7654*/ GIMT_Encode4(504905), // Rule ID 29251 //
     /*  504862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  504865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504874 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504881 */     // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  504884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504889 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504903 */     GIR_RootConstrainSelectedInstOperands,
     /*  504904 */     // GIR_Coverage, 29251,
     /*  504904 */     GIR_EraseRootFromParent_Done,
     /*  504905 */   // Label 7654: @504905
     /*  504905 */   GIM_Try, /*On fail goto*//*Label 7655*/ GIMT_Encode4(504953), // Rule ID 29252 //
     /*  504910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  504913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504929 */     // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  504932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504937 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504951 */     GIR_RootConstrainSelectedInstOperands,
     /*  504952 */     // GIR_Coverage, 29252,
     /*  504952 */     GIR_EraseRootFromParent_Done,
     /*  504953 */   // Label 7655: @504953
     /*  504953 */   GIM_Try, /*On fail goto*//*Label 7656*/ GIMT_Encode4(505001), // Rule ID 29258 //
     /*  504958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  504961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  504966 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  504970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  504977 */     // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  504977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  504980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  504985 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  504987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  504992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  504995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  504999 */     GIR_RootConstrainSelectedInstOperands,
     /*  505000 */     // GIR_Coverage, 29258,
     /*  505000 */     GIR_EraseRootFromParent_Done,
     /*  505001 */   // Label 7656: @505001
     /*  505001 */   GIM_Try, /*On fail goto*//*Label 7657*/ GIMT_Encode4(505049), // Rule ID 29259 //
     /*  505006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  505009 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  505014 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505018 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  505025 */     // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  505025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  505028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  505033 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  505035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505047 */     GIR_RootConstrainSelectedInstOperands,
     /*  505048 */     // GIR_Coverage, 29259,
     /*  505048 */     GIR_EraseRootFromParent_Done,
     /*  505049 */   // Label 7657: @505049
     /*  505049 */   GIM_Try, /*On fail goto*//*Label 7658*/ GIMT_Encode4(505097), // Rule ID 29260 //
     /*  505054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  505057 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  505062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  505073 */     // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  505073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  505076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  505081 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  505083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505095 */     GIR_RootConstrainSelectedInstOperands,
     /*  505096 */     // GIR_Coverage, 29260,
     /*  505096 */     GIR_EraseRootFromParent_Done,
     /*  505097 */   // Label 7658: @505097
     /*  505097 */   GIM_Try, /*On fail goto*//*Label 7659*/ GIMT_Encode4(505145), // Rule ID 29261 //
     /*  505102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  505105 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  505110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  505121 */     // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  505121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  505124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  505129 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  505131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505143 */     GIR_RootConstrainSelectedInstOperands,
     /*  505144 */     // GIR_Coverage, 29261,
     /*  505144 */     GIR_EraseRootFromParent_Done,
     /*  505145 */   // Label 7659: @505145
     /*  505145 */   GIM_Try, /*On fail goto*//*Label 7660*/ GIMT_Encode4(505193), // Rule ID 29262 //
     /*  505150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  505153 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  505158 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505162 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  505169 */     // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  505169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
     /*  505172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  505177 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  505179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505191 */     GIR_RootConstrainSelectedInstOperands,
     /*  505192 */     // GIR_Coverage, 29262,
     /*  505192 */     GIR_EraseRootFromParent_Done,
     /*  505193 */   // Label 7660: @505193
     /*  505193 */   GIM_Try, /*On fail goto*//*Label 7661*/ GIMT_Encode4(505250), // Rule ID 12153 //
     /*  505198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  505201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505208 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505219 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505227 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505248 */     GIR_RootConstrainSelectedInstOperands,
     /*  505249 */     // GIR_Coverage, 12153,
     /*  505249 */     GIR_EraseRootFromParent_Done,
     /*  505250 */   // Label 7661: @505250
     /*  505250 */   GIM_Try, /*On fail goto*//*Label 7662*/ GIMT_Encode4(505307), // Rule ID 12154 //
     /*  505255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  505258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505276 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505284 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505305 */     GIR_RootConstrainSelectedInstOperands,
     /*  505306 */     // GIR_Coverage, 12154,
     /*  505306 */     GIR_EraseRootFromParent_Done,
     /*  505307 */   // Label 7662: @505307
     /*  505307 */   GIM_Try, /*On fail goto*//*Label 7663*/ GIMT_Encode4(505364), // Rule ID 12155 //
     /*  505312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  505315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505333 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505341 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505362 */     GIR_RootConstrainSelectedInstOperands,
     /*  505363 */     // GIR_Coverage, 12155,
     /*  505363 */     GIR_EraseRootFromParent_Done,
     /*  505364 */   // Label 7663: @505364
     /*  505364 */   GIM_Try, /*On fail goto*//*Label 7664*/ GIMT_Encode4(505421), // Rule ID 12156 //
     /*  505369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  505372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505390 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505398 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505419 */     GIR_RootConstrainSelectedInstOperands,
     /*  505420 */     // GIR_Coverage, 12156,
     /*  505420 */     GIR_EraseRootFromParent_Done,
     /*  505421 */   // Label 7664: @505421
     /*  505421 */   GIM_Try, /*On fail goto*//*Label 7665*/ GIMT_Encode4(505478), // Rule ID 12157 //
     /*  505426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  505429 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505447 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505455 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505476 */     GIR_RootConstrainSelectedInstOperands,
     /*  505477 */     // GIR_Coverage, 12157,
     /*  505477 */     GIR_EraseRootFromParent_Done,
     /*  505478 */   // Label 7665: @505478
     /*  505478 */   GIM_Try, /*On fail goto*//*Label 7666*/ GIMT_Encode4(505535), // Rule ID 12173 //
     /*  505483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  505486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505504 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505512 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505529 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505533 */     GIR_RootConstrainSelectedInstOperands,
     /*  505534 */     // GIR_Coverage, 12173,
     /*  505534 */     GIR_EraseRootFromParent_Done,
     /*  505535 */   // Label 7666: @505535
     /*  505535 */   GIM_Try, /*On fail goto*//*Label 7667*/ GIMT_Encode4(505592), // Rule ID 12174 //
     /*  505540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  505543 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505561 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505569 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505590 */     GIR_RootConstrainSelectedInstOperands,
     /*  505591 */     // GIR_Coverage, 12174,
     /*  505591 */     GIR_EraseRootFromParent_Done,
     /*  505592 */   // Label 7667: @505592
     /*  505592 */   GIM_Try, /*On fail goto*//*Label 7668*/ GIMT_Encode4(505649), // Rule ID 12175 //
     /*  505597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  505600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505618 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505626 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505647 */     GIR_RootConstrainSelectedInstOperands,
     /*  505648 */     // GIR_Coverage, 12175,
     /*  505648 */     GIR_EraseRootFromParent_Done,
     /*  505649 */   // Label 7668: @505649
     /*  505649 */   GIM_Try, /*On fail goto*//*Label 7669*/ GIMT_Encode4(505706), // Rule ID 12176 //
     /*  505654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  505657 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505664 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505675 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505683 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505704 */     GIR_RootConstrainSelectedInstOperands,
     /*  505705 */     // GIR_Coverage, 12176,
     /*  505705 */     GIR_EraseRootFromParent_Done,
     /*  505706 */   // Label 7669: @505706
     /*  505706 */   GIM_Try, /*On fail goto*//*Label 7670*/ GIMT_Encode4(505763), // Rule ID 12177 //
     /*  505711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  505714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  505732 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  505732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
     /*  505735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  505740 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  505747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  505752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  505757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505761 */     GIR_RootConstrainSelectedInstOperands,
     /*  505762 */     // GIR_Coverage, 12177,
     /*  505762 */     GIR_EraseRootFromParent_Done,
     /*  505763 */   // Label 7670: @505763
     /*  505763 */   GIM_Try, /*On fail goto*//*Label 7671*/ GIMT_Encode4(505813), // Rule ID 12148 //
     /*  505768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  505771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505782 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  505789 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  505789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  505792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  505797 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505811 */     GIR_RootConstrainSelectedInstOperands,
     /*  505812 */     // GIR_Coverage, 12148,
     /*  505812 */     GIR_EraseRootFromParent_Done,
     /*  505813 */   // Label 7671: @505813
     /*  505813 */   GIM_Try, /*On fail goto*//*Label 7672*/ GIMT_Encode4(505863), // Rule ID 12149 //
     /*  505818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  505821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  505839 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  505839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  505842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  505847 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505861 */     GIR_RootConstrainSelectedInstOperands,
     /*  505862 */     // GIR_Coverage, 12149,
     /*  505862 */     GIR_EraseRootFromParent_Done,
     /*  505863 */   // Label 7672: @505863
     /*  505863 */   GIM_Try, /*On fail goto*//*Label 7673*/ GIMT_Encode4(505913), // Rule ID 12150 //
     /*  505868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  505871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505878 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  505889 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  505889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  505892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  505897 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505911 */     GIR_RootConstrainSelectedInstOperands,
     /*  505912 */     // GIR_Coverage, 12150,
     /*  505912 */     GIR_EraseRootFromParent_Done,
     /*  505913 */   // Label 7673: @505913
     /*  505913 */   GIM_Try, /*On fail goto*//*Label 7674*/ GIMT_Encode4(505963), // Rule ID 12151 //
     /*  505918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  505921 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505928 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505932 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  505939 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  505939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  505942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  505947 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  505954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  505957 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  505961 */     GIR_RootConstrainSelectedInstOperands,
     /*  505962 */     // GIR_Coverage, 12151,
     /*  505962 */     GIR_EraseRootFromParent_Done,
     /*  505963 */   // Label 7674: @505963
     /*  505963 */   GIM_Try, /*On fail goto*//*Label 7675*/ GIMT_Encode4(506013), // Rule ID 12152 //
     /*  505968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  505971 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  505978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  505982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  505989 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  505989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  505992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  505997 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  505999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506011 */     GIR_RootConstrainSelectedInstOperands,
     /*  506012 */     // GIR_Coverage, 12152,
     /*  506012 */     GIR_EraseRootFromParent_Done,
     /*  506013 */   // Label 7675: @506013
     /*  506013 */   GIM_Try, /*On fail goto*//*Label 7676*/ GIMT_Encode4(506063), // Rule ID 12168 //
     /*  506018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  506021 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  506028 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506032 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  506039 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  506042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506047 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506061 */     GIR_RootConstrainSelectedInstOperands,
     /*  506062 */     // GIR_Coverage, 12168,
     /*  506062 */     GIR_EraseRootFromParent_Done,
     /*  506063 */   // Label 7676: @506063
     /*  506063 */   GIM_Try, /*On fail goto*//*Label 7677*/ GIMT_Encode4(506113), // Rule ID 12169 //
     /*  506068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  506071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  506078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  506089 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  506092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506097 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506111 */     GIR_RootConstrainSelectedInstOperands,
     /*  506112 */     // GIR_Coverage, 12169,
     /*  506112 */     GIR_EraseRootFromParent_Done,
     /*  506113 */   // Label 7677: @506113
     /*  506113 */   GIM_Try, /*On fail goto*//*Label 7678*/ GIMT_Encode4(506163), // Rule ID 12170 //
     /*  506118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  506121 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  506128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  506139 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  506142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506147 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506161 */     GIR_RootConstrainSelectedInstOperands,
     /*  506162 */     // GIR_Coverage, 12170,
     /*  506162 */     GIR_EraseRootFromParent_Done,
     /*  506163 */   // Label 7678: @506163
     /*  506163 */   GIM_Try, /*On fail goto*//*Label 7679*/ GIMT_Encode4(506213), // Rule ID 12171 //
     /*  506168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  506171 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  506178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506182 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  506189 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  506192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506197 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506211 */     GIR_RootConstrainSelectedInstOperands,
     /*  506212 */     // GIR_Coverage, 12171,
     /*  506212 */     GIR_EraseRootFromParent_Done,
     /*  506213 */   // Label 7679: @506213
     /*  506213 */   GIM_Try, /*On fail goto*//*Label 7680*/ GIMT_Encode4(506263), // Rule ID 12172 //
     /*  506218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  506221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  506228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  506239 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
     /*  506242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506247 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506261 */     GIR_RootConstrainSelectedInstOperands,
     /*  506262 */     // GIR_Coverage, 12172,
     /*  506262 */     GIR_EraseRootFromParent_Done,
     /*  506263 */   // Label 7680: @506263
     /*  506263 */   GIM_Try, /*On fail goto*//*Label 7681*/ GIMT_Encode4(506319), // Rule ID 10011 //
     /*  506268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  506271 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506288 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506296 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506317 */     GIR_RootConstrainSelectedInstOperands,
     /*  506318 */     // GIR_Coverage, 10011,
     /*  506318 */     GIR_EraseRootFromParent_Done,
     /*  506319 */   // Label 7681: @506319
     /*  506319 */   GIM_Try, /*On fail goto*//*Label 7682*/ GIMT_Encode4(506375), // Rule ID 10012 //
     /*  506324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  506327 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506337 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506344 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506352 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506369 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506373 */     GIR_RootConstrainSelectedInstOperands,
     /*  506374 */     // GIR_Coverage, 10012,
     /*  506374 */     GIR_EraseRootFromParent_Done,
     /*  506375 */   // Label 7682: @506375
     /*  506375 */   GIM_Try, /*On fail goto*//*Label 7683*/ GIMT_Encode4(506431), // Rule ID 10013 //
     /*  506380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  506383 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506400 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506408 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506429 */     GIR_RootConstrainSelectedInstOperands,
     /*  506430 */     // GIR_Coverage, 10013,
     /*  506430 */     GIR_EraseRootFromParent_Done,
     /*  506431 */   // Label 7683: @506431
     /*  506431 */   GIM_Try, /*On fail goto*//*Label 7684*/ GIMT_Encode4(506487), // Rule ID 10014 //
     /*  506436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  506439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506445 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506456 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506464 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506485 */     GIR_RootConstrainSelectedInstOperands,
     /*  506486 */     // GIR_Coverage, 10014,
     /*  506486 */     GIR_EraseRootFromParent_Done,
     /*  506487 */   // Label 7684: @506487
     /*  506487 */   GIM_Try, /*On fail goto*//*Label 7685*/ GIMT_Encode4(506543), // Rule ID 10015 //
     /*  506492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  506495 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506512 */     // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506520 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506537 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506541 */     GIR_RootConstrainSelectedInstOperands,
     /*  506542 */     // GIR_Coverage, 10015,
     /*  506542 */     GIR_EraseRootFromParent_Done,
     /*  506543 */   // Label 7685: @506543
     /*  506543 */   GIM_Try, /*On fail goto*//*Label 7686*/ GIMT_Encode4(506599), // Rule ID 10031 //
     /*  506548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  506551 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506568 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506576 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506597 */     GIR_RootConstrainSelectedInstOperands,
     /*  506598 */     // GIR_Coverage, 10031,
     /*  506598 */     GIR_EraseRootFromParent_Done,
     /*  506599 */   // Label 7686: @506599
     /*  506599 */   GIM_Try, /*On fail goto*//*Label 7687*/ GIMT_Encode4(506655), // Rule ID 10032 //
     /*  506604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  506607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506624 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506632 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506653 */     GIR_RootConstrainSelectedInstOperands,
     /*  506654 */     // GIR_Coverage, 10032,
     /*  506654 */     GIR_EraseRootFromParent_Done,
     /*  506655 */   // Label 7687: @506655
     /*  506655 */   GIM_Try, /*On fail goto*//*Label 7688*/ GIMT_Encode4(506711), // Rule ID 10033 //
     /*  506660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  506663 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506673 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506680 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506688 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506705 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506709 */     GIR_RootConstrainSelectedInstOperands,
     /*  506710 */     // GIR_Coverage, 10033,
     /*  506710 */     GIR_EraseRootFromParent_Done,
     /*  506711 */   // Label 7688: @506711
     /*  506711 */   GIM_Try, /*On fail goto*//*Label 7689*/ GIMT_Encode4(506767), // Rule ID 10034 //
     /*  506716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  506719 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506736 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506744 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506765 */     GIR_RootConstrainSelectedInstOperands,
     /*  506766 */     // GIR_Coverage, 10034,
     /*  506766 */     GIR_EraseRootFromParent_Done,
     /*  506767 */   // Label 7689: @506767
     /*  506767 */   GIM_Try, /*On fail goto*//*Label 7690*/ GIMT_Encode4(506823), // Rule ID 10035 //
     /*  506772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  506775 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  506792 */     // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  506792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD_SADDR),
     /*  506795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  506800 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  506807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  506812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  506817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506821 */     GIR_RootConstrainSelectedInstOperands,
     /*  506822 */     // GIR_Coverage, 10035,
     /*  506822 */     GIR_EraseRootFromParent_Done,
     /*  506823 */   // Label 7690: @506823
     /*  506823 */   GIM_Try, /*On fail goto*//*Label 7691*/ GIMT_Encode4(506872), // Rule ID 10006 //
     /*  506828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  506831 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  506848 */     // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  506851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506856 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506870 */     GIR_RootConstrainSelectedInstOperands,
     /*  506871 */     // GIR_Coverage, 10006,
     /*  506871 */     GIR_EraseRootFromParent_Done,
     /*  506872 */   // Label 7691: @506872
     /*  506872 */   GIM_Try, /*On fail goto*//*Label 7692*/ GIMT_Encode4(506921), // Rule ID 10007 //
     /*  506877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  506880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  506897 */     // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  506900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506905 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506912 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506915 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506919 */     GIR_RootConstrainSelectedInstOperands,
     /*  506920 */     // GIR_Coverage, 10007,
     /*  506920 */     GIR_EraseRootFromParent_Done,
     /*  506921 */   // Label 7692: @506921
     /*  506921 */   GIM_Try, /*On fail goto*//*Label 7693*/ GIMT_Encode4(506970), // Rule ID 10008 //
     /*  506926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  506929 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506935 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  506946 */     // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  506949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  506954 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  506956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  506961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  506964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  506968 */     GIR_RootConstrainSelectedInstOperands,
     /*  506969 */     // GIR_Coverage, 10008,
     /*  506969 */     GIR_EraseRootFromParent_Done,
     /*  506970 */   // Label 7693: @506970
     /*  506970 */   GIM_Try, /*On fail goto*//*Label 7694*/ GIMT_Encode4(507019), // Rule ID 10009 //
     /*  506975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  506978 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  506984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  506988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  506995 */     // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  506995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  506998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507003 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507017 */     GIR_RootConstrainSelectedInstOperands,
     /*  507018 */     // GIR_Coverage, 10009,
     /*  507018 */     GIR_EraseRootFromParent_Done,
     /*  507019 */   // Label 7694: @507019
     /*  507019 */   GIM_Try, /*On fail goto*//*Label 7695*/ GIMT_Encode4(507068), // Rule ID 10010 //
     /*  507024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  507027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  507033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  507044 */     // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  507044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  507047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507052 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507066 */     GIR_RootConstrainSelectedInstOperands,
     /*  507067 */     // GIR_Coverage, 10010,
     /*  507067 */     GIR_EraseRootFromParent_Done,
     /*  507068 */   // Label 7695: @507068
     /*  507068 */   GIM_Try, /*On fail goto*//*Label 7696*/ GIMT_Encode4(507117), // Rule ID 10026 //
     /*  507073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  507076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  507082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  507093 */     // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  507093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  507096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507101 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507115 */     GIR_RootConstrainSelectedInstOperands,
     /*  507116 */     // GIR_Coverage, 10026,
     /*  507116 */     GIR_EraseRootFromParent_Done,
     /*  507117 */   // Label 7696: @507117
     /*  507117 */   GIM_Try, /*On fail goto*//*Label 7697*/ GIMT_Encode4(507166), // Rule ID 10027 //
     /*  507122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  507125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  507131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  507142 */     // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  507142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  507145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507150 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507164 */     GIR_RootConstrainSelectedInstOperands,
     /*  507165 */     // GIR_Coverage, 10027,
     /*  507165 */     GIR_EraseRootFromParent_Done,
     /*  507166 */   // Label 7697: @507166
     /*  507166 */   GIM_Try, /*On fail goto*//*Label 7698*/ GIMT_Encode4(507215), // Rule ID 10028 //
     /*  507171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  507174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  507180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  507191 */     // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  507191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  507194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507199 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507213 */     GIR_RootConstrainSelectedInstOperands,
     /*  507214 */     // GIR_Coverage, 10028,
     /*  507214 */     GIR_EraseRootFromParent_Done,
     /*  507215 */   // Label 7698: @507215
     /*  507215 */   GIM_Try, /*On fail goto*//*Label 7699*/ GIMT_Encode4(507264), // Rule ID 10029 //
     /*  507220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  507223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  507229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  507240 */     // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  507240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  507243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507248 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507262 */     GIR_RootConstrainSelectedInstOperands,
     /*  507263 */     // GIR_Coverage, 10029,
     /*  507263 */     GIR_EraseRootFromParent_Done,
     /*  507264 */   // Label 7699: @507264
     /*  507264 */   GIM_Try, /*On fail goto*//*Label 7700*/ GIMT_Encode4(507313), // Rule ID 10030 //
     /*  507269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  507272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  507278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  507289 */     // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  507289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
     /*  507292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  507297 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  507299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507311 */     GIR_RootConstrainSelectedInstOperands,
     /*  507312 */     // GIR_Coverage, 10030,
     /*  507312 */     GIR_EraseRootFromParent_Done,
     /*  507313 */   // Label 7700: @507313
     /*  507313 */   GIM_Reject,
     /*  507314 */ // Label 7530: @507314
     /*  507314 */ GIM_Reject,
     /*  507315 */ // Label 5869: @507315
     /*  507315 */ GIM_Try, /*On fail goto*//*Label 7701*/ GIMT_Encode4(507379), // Rule ID 29993 //
     /*  507320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  507323 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507326 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507330 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507335 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507340 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507344 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507348 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507355 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507363 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507370 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507373 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507377 */   GIR_RootConstrainSelectedInstOperands,
     /*  507378 */   // GIR_Coverage, 29993,
     /*  507378 */   GIR_EraseRootFromParent_Done,
     /*  507379 */ // Label 7701: @507379
     /*  507379 */ GIM_Try, /*On fail goto*//*Label 7702*/ GIMT_Encode4(507443), // Rule ID 29994 //
     /*  507384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  507387 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507390 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507394 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507399 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507408 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507419 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507427 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507441 */   GIR_RootConstrainSelectedInstOperands,
     /*  507442 */   // GIR_Coverage, 29994,
     /*  507442 */   GIR_EraseRootFromParent_Done,
     /*  507443 */ // Label 7702: @507443
     /*  507443 */ GIM_Try, /*On fail goto*//*Label 7703*/ GIMT_Encode4(507507), // Rule ID 29995 //
     /*  507448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  507451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507454 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507458 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507463 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507468 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507472 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507476 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507483 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507483 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507491 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507498 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507501 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507505 */   GIR_RootConstrainSelectedInstOperands,
     /*  507506 */   // GIR_Coverage, 29995,
     /*  507506 */   GIR_EraseRootFromParent_Done,
     /*  507507 */ // Label 7703: @507507
     /*  507507 */ GIM_Try, /*On fail goto*//*Label 7704*/ GIMT_Encode4(507571), // Rule ID 29996 //
     /*  507512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  507515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507518 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507522 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507527 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507536 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507540 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507547 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507547 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507555 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507562 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507565 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507569 */   GIR_RootConstrainSelectedInstOperands,
     /*  507570 */   // GIR_Coverage, 29996,
     /*  507570 */   GIR_EraseRootFromParent_Done,
     /*  507571 */ // Label 7704: @507571
     /*  507571 */ GIM_Try, /*On fail goto*//*Label 7705*/ GIMT_Encode4(507635), // Rule ID 29997 //
     /*  507576 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  507579 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507582 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507586 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507591 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507600 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507604 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507611 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507611 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507619 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507633 */   GIR_RootConstrainSelectedInstOperands,
     /*  507634 */   // GIR_Coverage, 29997,
     /*  507634 */   GIR_EraseRootFromParent_Done,
     /*  507635 */ // Label 7705: @507635
     /*  507635 */ GIM_Try, /*On fail goto*//*Label 7706*/ GIMT_Encode4(507699), // Rule ID 30013 //
     /*  507640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  507643 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507646 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507650 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507655 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507660 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507664 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507668 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507675 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507675 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507683 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507690 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507693 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507697 */   GIR_RootConstrainSelectedInstOperands,
     /*  507698 */   // GIR_Coverage, 30013,
     /*  507698 */   GIR_EraseRootFromParent_Done,
     /*  507699 */ // Label 7706: @507699
     /*  507699 */ GIM_Try, /*On fail goto*//*Label 7707*/ GIMT_Encode4(507763), // Rule ID 30014 //
     /*  507704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  507707 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507710 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507714 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507719 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507724 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507728 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507732 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507739 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507747 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507754 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507757 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507761 */   GIR_RootConstrainSelectedInstOperands,
     /*  507762 */   // GIR_Coverage, 30014,
     /*  507762 */   GIR_EraseRootFromParent_Done,
     /*  507763 */ // Label 7707: @507763
     /*  507763 */ GIM_Try, /*On fail goto*//*Label 7708*/ GIMT_Encode4(507827), // Rule ID 30015 //
     /*  507768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  507771 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507774 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507778 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507788 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507792 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507796 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507803 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507803 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507811 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507818 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507821 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507825 */   GIR_RootConstrainSelectedInstOperands,
     /*  507826 */   // GIR_Coverage, 30015,
     /*  507826 */   GIR_EraseRootFromParent_Done,
     /*  507827 */ // Label 7708: @507827
     /*  507827 */ GIM_Try, /*On fail goto*//*Label 7709*/ GIMT_Encode4(507891), // Rule ID 30016 //
     /*  507832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  507835 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507838 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507842 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507847 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507852 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507856 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507867 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507875 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507889 */   GIR_RootConstrainSelectedInstOperands,
     /*  507890 */   // GIR_Coverage, 30016,
     /*  507890 */   GIR_EraseRootFromParent_Done,
     /*  507891 */ // Label 7709: @507891
     /*  507891 */ GIM_Try, /*On fail goto*//*Label 7710*/ GIMT_Encode4(507955), // Rule ID 30017 //
     /*  507896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  507899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507902 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507906 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507911 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507916 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507920 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  507924 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507931 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507931 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507939 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  507941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  507946 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  507949 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  507953 */   GIR_RootConstrainSelectedInstOperands,
     /*  507954 */   // GIR_Coverage, 30017,
     /*  507954 */   GIR_EraseRootFromParent_Done,
     /*  507955 */ // Label 7710: @507955
     /*  507955 */ GIM_Try, /*On fail goto*//*Label 7711*/ GIMT_Encode4(508014), // Rule ID 29653 //
     /*  507960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  507963 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  507966 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  507970 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  507975 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  507979 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  507983 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  507990 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  507990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  507993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  507998 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508005 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508008 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508012 */   GIR_RootConstrainSelectedInstOperands,
     /*  508013 */   // GIR_Coverage, 29653,
     /*  508013 */   GIR_EraseRootFromParent_Done,
     /*  508014 */ // Label 7711: @508014
     /*  508014 */ GIM_Try, /*On fail goto*//*Label 7712*/ GIMT_Encode4(508073), // Rule ID 29654 //
     /*  508019 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  508022 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508025 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508029 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508034 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508038 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508042 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508049 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508057 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508067 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508071 */   GIR_RootConstrainSelectedInstOperands,
     /*  508072 */   // GIR_Coverage, 29654,
     /*  508072 */   GIR_EraseRootFromParent_Done,
     /*  508073 */ // Label 7712: @508073
     /*  508073 */ GIM_Try, /*On fail goto*//*Label 7713*/ GIMT_Encode4(508132), // Rule ID 29655 //
     /*  508078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  508081 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508084 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508093 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508097 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508101 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508108 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508108 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508116 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508118 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508123 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508126 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508130 */   GIR_RootConstrainSelectedInstOperands,
     /*  508131 */   // GIR_Coverage, 29655,
     /*  508131 */   GIR_EraseRootFromParent_Done,
     /*  508132 */ // Label 7713: @508132
     /*  508132 */ GIM_Try, /*On fail goto*//*Label 7714*/ GIMT_Encode4(508191), // Rule ID 29656 //
     /*  508137 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  508140 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508143 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508147 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508152 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508160 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508167 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508170 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508175 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508182 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508185 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508189 */   GIR_RootConstrainSelectedInstOperands,
     /*  508190 */   // GIR_Coverage, 29656,
     /*  508190 */   GIR_EraseRootFromParent_Done,
     /*  508191 */ // Label 7714: @508191
     /*  508191 */ GIM_Try, /*On fail goto*//*Label 7715*/ GIMT_Encode4(508250), // Rule ID 29657 //
     /*  508196 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  508199 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508202 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508206 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508211 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508215 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508219 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508226 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508226 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508234 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508236 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508241 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508244 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508248 */   GIR_RootConstrainSelectedInstOperands,
     /*  508249 */   // GIR_Coverage, 29657,
     /*  508249 */   GIR_EraseRootFromParent_Done,
     /*  508250 */ // Label 7715: @508250
     /*  508250 */ GIM_Try, /*On fail goto*//*Label 7716*/ GIMT_Encode4(508309), // Rule ID 29673 //
     /*  508255 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  508258 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508261 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508265 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508270 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508274 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508278 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508285 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508293 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508300 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508307 */   GIR_RootConstrainSelectedInstOperands,
     /*  508308 */   // GIR_Coverage, 29673,
     /*  508308 */   GIR_EraseRootFromParent_Done,
     /*  508309 */ // Label 7716: @508309
     /*  508309 */ GIM_Try, /*On fail goto*//*Label 7717*/ GIMT_Encode4(508368), // Rule ID 29674 //
     /*  508314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  508317 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508320 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508324 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508329 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508333 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508337 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508344 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508344 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508352 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508354 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508359 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508362 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508366 */   GIR_RootConstrainSelectedInstOperands,
     /*  508367 */   // GIR_Coverage, 29674,
     /*  508367 */   GIR_EraseRootFromParent_Done,
     /*  508368 */ // Label 7717: @508368
     /*  508368 */ GIM_Try, /*On fail goto*//*Label 7718*/ GIMT_Encode4(508427), // Rule ID 29675 //
     /*  508373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  508376 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508379 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508388 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508403 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508411 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508425 */   GIR_RootConstrainSelectedInstOperands,
     /*  508426 */   // GIR_Coverage, 29675,
     /*  508426 */   GIR_EraseRootFromParent_Done,
     /*  508427 */ // Label 7718: @508427
     /*  508427 */ GIM_Try, /*On fail goto*//*Label 7719*/ GIMT_Encode4(508486), // Rule ID 29676 //
     /*  508432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  508435 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508438 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508442 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508447 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508451 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508455 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508462 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508470 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508477 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508480 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508484 */   GIR_RootConstrainSelectedInstOperands,
     /*  508485 */   // GIR_Coverage, 29676,
     /*  508485 */   GIR_EraseRootFromParent_Done,
     /*  508486 */ // Label 7719: @508486
     /*  508486 */ GIM_Try, /*On fail goto*//*Label 7720*/ GIMT_Encode4(508545), // Rule ID 29677 //
     /*  508491 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  508494 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508497 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  508501 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508506 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  508510 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508514 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508521 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  508524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508529 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508531 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508536 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508543 */   GIR_RootConstrainSelectedInstOperands,
     /*  508544 */   // GIR_Coverage, 29677,
     /*  508544 */   GIR_EraseRootFromParent_Done,
     /*  508545 */ // Label 7720: @508545
     /*  508545 */ GIM_Try, /*On fail goto*//*Label 7721*/ GIMT_Encode4(508605), // Rule ID 29998 //
     /*  508550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  508553 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508561 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508566 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508570 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508574 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508581 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508589 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508603 */   GIR_RootConstrainSelectedInstOperands,
     /*  508604 */   // GIR_Coverage, 29998,
     /*  508604 */   GIR_EraseRootFromParent_Done,
     /*  508605 */ // Label 7721: @508605
     /*  508605 */ GIM_Try, /*On fail goto*//*Label 7722*/ GIMT_Encode4(508665), // Rule ID 29999 //
     /*  508610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  508613 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508616 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508621 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508626 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508630 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508634 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508641 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508649 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508656 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508659 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508663 */   GIR_RootConstrainSelectedInstOperands,
     /*  508664 */   // GIR_Coverage, 29999,
     /*  508664 */   GIR_EraseRootFromParent_Done,
     /*  508665 */ // Label 7722: @508665
     /*  508665 */ GIM_Try, /*On fail goto*//*Label 7723*/ GIMT_Encode4(508725), // Rule ID 30000 //
     /*  508670 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  508673 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508676 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508681 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508686 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508690 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508694 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508701 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508709 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508716 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508719 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508723 */   GIR_RootConstrainSelectedInstOperands,
     /*  508724 */   // GIR_Coverage, 30000,
     /*  508724 */   GIR_EraseRootFromParent_Done,
     /*  508725 */ // Label 7723: @508725
     /*  508725 */ GIM_Try, /*On fail goto*//*Label 7724*/ GIMT_Encode4(508785), // Rule ID 30001 //
     /*  508730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  508733 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508736 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508741 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508746 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508750 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508754 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508761 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508769 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508771 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508783 */   GIR_RootConstrainSelectedInstOperands,
     /*  508784 */   // GIR_Coverage, 30001,
     /*  508784 */   GIR_EraseRootFromParent_Done,
     /*  508785 */ // Label 7724: @508785
     /*  508785 */ GIM_Try, /*On fail goto*//*Label 7725*/ GIMT_Encode4(508845), // Rule ID 30002 //
     /*  508790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  508793 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508796 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508801 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508806 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508810 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508814 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508821 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508829 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508831 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508843 */   GIR_RootConstrainSelectedInstOperands,
     /*  508844 */   // GIR_Coverage, 30002,
     /*  508844 */   GIR_EraseRootFromParent_Done,
     /*  508845 */ // Label 7725: @508845
     /*  508845 */ GIM_Try, /*On fail goto*//*Label 7726*/ GIMT_Encode4(508905), // Rule ID 30018 //
     /*  508850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  508853 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508856 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508861 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508866 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508870 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508881 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508889 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508903 */   GIR_RootConstrainSelectedInstOperands,
     /*  508904 */   // GIR_Coverage, 30018,
     /*  508904 */   GIR_EraseRootFromParent_Done,
     /*  508905 */ // Label 7726: @508905
     /*  508905 */ GIM_Try, /*On fail goto*//*Label 7727*/ GIMT_Encode4(508965), // Rule ID 30019 //
     /*  508910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  508913 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508916 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508921 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508926 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508930 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508934 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  508941 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  508941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  508944 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  508949 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  508951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  508956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  508959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  508963 */   GIR_RootConstrainSelectedInstOperands,
     /*  508964 */   // GIR_Coverage, 30019,
     /*  508964 */   GIR_EraseRootFromParent_Done,
     /*  508965 */ // Label 7727: @508965
     /*  508965 */ GIM_Try, /*On fail goto*//*Label 7728*/ GIMT_Encode4(509025), // Rule ID 30020 //
     /*  508970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  508973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  508976 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508981 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  508986 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  508990 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  508994 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509001 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509009 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509011 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509016 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509019 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509023 */   GIR_RootConstrainSelectedInstOperands,
     /*  509024 */   // GIR_Coverage, 30020,
     /*  509024 */   GIR_EraseRootFromParent_Done,
     /*  509025 */ // Label 7728: @509025
     /*  509025 */ GIM_Try, /*On fail goto*//*Label 7729*/ GIMT_Encode4(509085), // Rule ID 30021 //
     /*  509030 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  509033 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509036 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509041 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509046 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509050 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  509054 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509061 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509064 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509069 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509076 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509079 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509083 */   GIR_RootConstrainSelectedInstOperands,
     /*  509084 */   // GIR_Coverage, 30021,
     /*  509084 */   GIR_EraseRootFromParent_Done,
     /*  509085 */ // Label 7729: @509085
     /*  509085 */ GIM_Try, /*On fail goto*//*Label 7730*/ GIMT_Encode4(509145), // Rule ID 30022 //
     /*  509090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  509093 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509096 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509101 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509106 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509110 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  509114 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509121 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509129 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509136 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509139 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509143 */   GIR_RootConstrainSelectedInstOperands,
     /*  509144 */   // GIR_Coverage, 30022,
     /*  509144 */   GIR_EraseRootFromParent_Done,
     /*  509145 */ // Label 7730: @509145
     /*  509145 */ GIM_Try, /*On fail goto*//*Label 7731*/ GIMT_Encode4(509200), // Rule ID 29658 //
     /*  509150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  509153 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509156 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509161 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509165 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509169 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509176 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509184 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509191 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509194 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509198 */   GIR_RootConstrainSelectedInstOperands,
     /*  509199 */   // GIR_Coverage, 29658,
     /*  509199 */   GIR_EraseRootFromParent_Done,
     /*  509200 */ // Label 7731: @509200
     /*  509200 */ GIM_Try, /*On fail goto*//*Label 7732*/ GIMT_Encode4(509255), // Rule ID 29659 //
     /*  509205 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  509208 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509211 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509216 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509220 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509224 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509231 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509231 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509239 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509249 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509253 */   GIR_RootConstrainSelectedInstOperands,
     /*  509254 */   // GIR_Coverage, 29659,
     /*  509254 */   GIR_EraseRootFromParent_Done,
     /*  509255 */ // Label 7732: @509255
     /*  509255 */ GIM_Try, /*On fail goto*//*Label 7733*/ GIMT_Encode4(509310), // Rule ID 29660 //
     /*  509260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  509263 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509266 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509271 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509275 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509279 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509286 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509294 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509296 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509301 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509304 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509308 */   GIR_RootConstrainSelectedInstOperands,
     /*  509309 */   // GIR_Coverage, 29660,
     /*  509309 */   GIR_EraseRootFromParent_Done,
     /*  509310 */ // Label 7733: @509310
     /*  509310 */ GIM_Try, /*On fail goto*//*Label 7734*/ GIMT_Encode4(509365), // Rule ID 29661 //
     /*  509315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  509318 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509321 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509326 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509341 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509349 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509359 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509363 */   GIR_RootConstrainSelectedInstOperands,
     /*  509364 */   // GIR_Coverage, 29661,
     /*  509364 */   GIR_EraseRootFromParent_Done,
     /*  509365 */ // Label 7734: @509365
     /*  509365 */ GIM_Try, /*On fail goto*//*Label 7735*/ GIMT_Encode4(509420), // Rule ID 29662 //
     /*  509370 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  509373 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509376 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509381 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509396 */   // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509404 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509411 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509414 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509418 */   GIR_RootConstrainSelectedInstOperands,
     /*  509419 */   // GIR_Coverage, 29662,
     /*  509419 */   GIR_EraseRootFromParent_Done,
     /*  509420 */ // Label 7735: @509420
     /*  509420 */ GIM_Try, /*On fail goto*//*Label 7736*/ GIMT_Encode4(509475), // Rule ID 29678 //
     /*  509425 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  509428 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509431 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509436 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509440 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509444 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509451 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509451 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509454 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509459 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509466 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509469 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509473 */   GIR_RootConstrainSelectedInstOperands,
     /*  509474 */   // GIR_Coverage, 29678,
     /*  509474 */   GIR_EraseRootFromParent_Done,
     /*  509475 */ // Label 7736: @509475
     /*  509475 */ GIM_Try, /*On fail goto*//*Label 7737*/ GIMT_Encode4(509530), // Rule ID 29679 //
     /*  509480 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  509483 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509486 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509491 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509495 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509499 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509506 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509506 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509514 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509516 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509521 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509524 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509528 */   GIR_RootConstrainSelectedInstOperands,
     /*  509529 */   // GIR_Coverage, 29679,
     /*  509529 */   GIR_EraseRootFromParent_Done,
     /*  509530 */ // Label 7737: @509530
     /*  509530 */ GIM_Try, /*On fail goto*//*Label 7738*/ GIMT_Encode4(509585), // Rule ID 29680 //
     /*  509535 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  509538 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509541 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509546 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509550 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509554 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509561 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509569 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509579 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509583 */   GIR_RootConstrainSelectedInstOperands,
     /*  509584 */   // GIR_Coverage, 29680,
     /*  509584 */   GIR_EraseRootFromParent_Done,
     /*  509585 */ // Label 7738: @509585
     /*  509585 */ GIM_Try, /*On fail goto*//*Label 7739*/ GIMT_Encode4(509640), // Rule ID 29681 //
     /*  509590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  509593 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509596 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509601 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509605 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509609 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509616 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509616 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509624 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509631 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509634 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509638 */   GIR_RootConstrainSelectedInstOperands,
     /*  509639 */   // GIR_Coverage, 29681,
     /*  509639 */   GIR_EraseRootFromParent_Done,
     /*  509640 */ // Label 7739: @509640
     /*  509640 */ GIM_Try, /*On fail goto*//*Label 7740*/ GIMT_Encode4(509695), // Rule ID 29682 //
     /*  509645 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  509648 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509651 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  509656 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  509660 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509664 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  509671 */   // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  509671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  509674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  509679 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  509686 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509689 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509693 */   GIR_RootConstrainSelectedInstOperands,
     /*  509694 */   // GIR_Coverage, 29682,
     /*  509694 */   GIR_EraseRootFromParent_Done,
     /*  509695 */ // Label 7740: @509695
     /*  509695 */ GIM_Try, /*On fail goto*//*Label 7741*/ GIMT_Encode4(509754), // Rule ID 25946 //
     /*  509700 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  509703 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509706 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  509711 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509715 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  509722 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  509722 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  509725 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  509732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  509737 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  509742 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509745 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509748 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509752 */   GIR_RootConstrainSelectedInstOperands,
     /*  509753 */   // GIR_Coverage, 25946,
     /*  509753 */   GIR_EraseRootFromParent_Done,
     /*  509754 */ // Label 7741: @509754
     /*  509754 */ GIM_Try, /*On fail goto*//*Label 7742*/ GIMT_Encode4(509813), // Rule ID 25947 //
     /*  509759 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  509762 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509765 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  509770 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509774 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  509781 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  509781 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  509784 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  509791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  509796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  509801 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509804 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509811 */   GIR_RootConstrainSelectedInstOperands,
     /*  509812 */   // GIR_Coverage, 25947,
     /*  509812 */   GIR_EraseRootFromParent_Done,
     /*  509813 */ // Label 7742: @509813
     /*  509813 */ GIM_Try, /*On fail goto*//*Label 7743*/ GIMT_Encode4(509872), // Rule ID 25948 //
     /*  509818 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  509821 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509824 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  509829 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509833 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  509840 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  509840 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  509843 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  509850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  509855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  509860 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509863 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509866 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509870 */   GIR_RootConstrainSelectedInstOperands,
     /*  509871 */   // GIR_Coverage, 25948,
     /*  509871 */   GIR_EraseRootFromParent_Done,
     /*  509872 */ // Label 7743: @509872
     /*  509872 */ GIM_Try, /*On fail goto*//*Label 7744*/ GIMT_Encode4(509931), // Rule ID 25949 //
     /*  509877 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  509880 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  509888 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509892 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  509899 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  509899 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  509902 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  509909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  509914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  509919 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509929 */   GIR_RootConstrainSelectedInstOperands,
     /*  509930 */   // GIR_Coverage, 25949,
     /*  509930 */   GIR_EraseRootFromParent_Done,
     /*  509931 */ // Label 7744: @509931
     /*  509931 */ GIM_Try, /*On fail goto*//*Label 7745*/ GIMT_Encode4(509990), // Rule ID 25950 //
     /*  509936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  509939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  509942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  509947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  509951 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  509958 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  509958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  509961 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  509963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  509968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  509973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  509978 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509981 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  509984 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  509988 */   GIR_RootConstrainSelectedInstOperands,
     /*  509989 */   // GIR_Coverage, 25950,
     /*  509989 */   GIR_EraseRootFromParent_Done,
     /*  509990 */ // Label 7745: @509990
     /*  509990 */ GIM_Try, /*On fail goto*//*Label 7746*/ GIMT_Encode4(510049), // Rule ID 25956 //
     /*  509995 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  509998 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510001 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510010 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  510017 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  510017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  510020 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  510022 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  510027 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  510032 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510040 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510047 */   GIR_RootConstrainSelectedInstOperands,
     /*  510048 */   // GIR_Coverage, 25956,
     /*  510048 */   GIR_EraseRootFromParent_Done,
     /*  510049 */ // Label 7746: @510049
     /*  510049 */ GIM_Try, /*On fail goto*//*Label 7747*/ GIMT_Encode4(510108), // Rule ID 25957 //
     /*  510054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  510057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510060 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510065 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510069 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  510076 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  510076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  510079 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  510081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  510086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  510091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510096 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510099 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510102 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510106 */   GIR_RootConstrainSelectedInstOperands,
     /*  510107 */   // GIR_Coverage, 25957,
     /*  510107 */   GIR_EraseRootFromParent_Done,
     /*  510108 */ // Label 7747: @510108
     /*  510108 */ GIM_Try, /*On fail goto*//*Label 7748*/ GIMT_Encode4(510167), // Rule ID 25958 //
     /*  510113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  510116 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510119 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  510135 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  510135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  510138 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  510140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  510145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  510150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510155 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510158 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510161 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510165 */   GIR_RootConstrainSelectedInstOperands,
     /*  510166 */   // GIR_Coverage, 25958,
     /*  510166 */   GIR_EraseRootFromParent_Done,
     /*  510167 */ // Label 7748: @510167
     /*  510167 */ GIM_Try, /*On fail goto*//*Label 7749*/ GIMT_Encode4(510226), // Rule ID 25959 //
     /*  510172 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  510175 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510178 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510183 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510187 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  510194 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  510194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  510197 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  510199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  510204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  510209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510214 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510217 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510220 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510224 */   GIR_RootConstrainSelectedInstOperands,
     /*  510225 */   // GIR_Coverage, 25959,
     /*  510225 */   GIR_EraseRootFromParent_Done,
     /*  510226 */ // Label 7749: @510226
     /*  510226 */ GIM_Try, /*On fail goto*//*Label 7750*/ GIMT_Encode4(510285), // Rule ID 25960 //
     /*  510231 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  510234 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510237 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510242 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510246 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  510253 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  510253 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  510256 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  510258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  510263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  510268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510273 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510276 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510279 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510283 */   GIR_RootConstrainSelectedInstOperands,
     /*  510284 */   // GIR_Coverage, 25960,
     /*  510284 */   GIR_EraseRootFromParent_Done,
     /*  510285 */ // Label 7750: @510285
     /*  510285 */ GIM_Try, /*On fail goto*//*Label 7751*/ GIMT_Encode4(510343), // Rule ID 14377 //
     /*  510290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  510293 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510296 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510301 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510305 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510312 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510312 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510315 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510337 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510341 */   GIR_RootConstrainSelectedInstOperands,
     /*  510342 */   // GIR_Coverage, 14377,
     /*  510342 */   GIR_EraseRootFromParent_Done,
     /*  510343 */ // Label 7751: @510343
     /*  510343 */ GIM_Try, /*On fail goto*//*Label 7752*/ GIMT_Encode4(510401), // Rule ID 14378 //
     /*  510348 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  510351 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510354 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510359 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510363 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510370 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510370 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510373 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510390 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510395 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510399 */   GIR_RootConstrainSelectedInstOperands,
     /*  510400 */   // GIR_Coverage, 14378,
     /*  510400 */   GIR_EraseRootFromParent_Done,
     /*  510401 */ // Label 7752: @510401
     /*  510401 */ GIM_Try, /*On fail goto*//*Label 7753*/ GIMT_Encode4(510459), // Rule ID 14379 //
     /*  510406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  510409 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510412 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510428 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510431 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510453 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510457 */   GIR_RootConstrainSelectedInstOperands,
     /*  510458 */   // GIR_Coverage, 14379,
     /*  510458 */   GIR_EraseRootFromParent_Done,
     /*  510459 */ // Label 7753: @510459
     /*  510459 */ GIM_Try, /*On fail goto*//*Label 7754*/ GIMT_Encode4(510517), // Rule ID 14380 //
     /*  510464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  510467 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510470 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510475 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510479 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510486 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510486 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510489 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510491 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510501 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510511 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510515 */   GIR_RootConstrainSelectedInstOperands,
     /*  510516 */   // GIR_Coverage, 14380,
     /*  510516 */   GIR_EraseRootFromParent_Done,
     /*  510517 */ // Label 7754: @510517
     /*  510517 */ GIM_Try, /*On fail goto*//*Label 7755*/ GIMT_Encode4(510575), // Rule ID 14381 //
     /*  510522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  510525 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510528 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510533 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510537 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510544 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510547 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510554 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510569 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510573 */   GIR_RootConstrainSelectedInstOperands,
     /*  510574 */   // GIR_Coverage, 14381,
     /*  510574 */   GIR_EraseRootFromParent_Done,
     /*  510575 */ // Label 7755: @510575
     /*  510575 */ GIM_Try, /*On fail goto*//*Label 7756*/ GIMT_Encode4(510633), // Rule ID 14407 //
     /*  510580 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  510583 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510586 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510591 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510595 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510602 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510605 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510627 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510631 */   GIR_RootConstrainSelectedInstOperands,
     /*  510632 */   // GIR_Coverage, 14407,
     /*  510632 */   GIR_EraseRootFromParent_Done,
     /*  510633 */ // Label 7756: @510633
     /*  510633 */ GIM_Try, /*On fail goto*//*Label 7757*/ GIMT_Encode4(510691), // Rule ID 14408 //
     /*  510638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  510641 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510644 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510660 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510663 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510689 */   GIR_RootConstrainSelectedInstOperands,
     /*  510690 */   // GIR_Coverage, 14408,
     /*  510690 */   GIR_EraseRootFromParent_Done,
     /*  510691 */ // Label 7757: @510691
     /*  510691 */ GIM_Try, /*On fail goto*//*Label 7758*/ GIMT_Encode4(510749), // Rule ID 14409 //
     /*  510696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  510699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510702 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510707 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510711 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510718 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510718 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510721 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510743 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510747 */   GIR_RootConstrainSelectedInstOperands,
     /*  510748 */   // GIR_Coverage, 14409,
     /*  510748 */   GIR_EraseRootFromParent_Done,
     /*  510749 */ // Label 7758: @510749
     /*  510749 */ GIM_Try, /*On fail goto*//*Label 7759*/ GIMT_Encode4(510807), // Rule ID 14410 //
     /*  510754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  510757 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510760 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510765 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510769 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510776 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510776 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510779 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510786 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510805 */   GIR_RootConstrainSelectedInstOperands,
     /*  510806 */   // GIR_Coverage, 14410,
     /*  510806 */   GIR_EraseRootFromParent_Done,
     /*  510807 */ // Label 7759: @510807
     /*  510807 */ GIM_Try, /*On fail goto*//*Label 7760*/ GIMT_Encode4(510865), // Rule ID 14411 //
     /*  510812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  510815 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510818 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510823 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510827 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  510834 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  510834 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  510837 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510839 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  510844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  510849 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  510854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  510859 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510863 */   GIR_RootConstrainSelectedInstOperands,
     /*  510864 */   // GIR_Coverage, 14411,
     /*  510864 */   GIR_EraseRootFromParent_Done,
     /*  510865 */ // Label 7760: @510865
     /*  510865 */ GIM_Try, /*On fail goto*//*Label 7761*/ GIMT_Encode4(510916), // Rule ID 14372 //
     /*  510870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  510873 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510876 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510881 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510885 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  510892 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  510892 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  510895 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  510902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  510907 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510910 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510914 */   GIR_RootConstrainSelectedInstOperands,
     /*  510915 */   // GIR_Coverage, 14372,
     /*  510915 */   GIR_EraseRootFromParent_Done,
     /*  510916 */ // Label 7761: @510916
     /*  510916 */ GIM_Try, /*On fail goto*//*Label 7762*/ GIMT_Encode4(510967), // Rule ID 14373 //
     /*  510921 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  510924 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510927 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510932 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510936 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  510943 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  510943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  510946 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  510953 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  510958 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  510961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  510965 */   GIR_RootConstrainSelectedInstOperands,
     /*  510966 */   // GIR_Coverage, 14373,
     /*  510966 */   GIR_EraseRootFromParent_Done,
     /*  510967 */ // Label 7762: @510967
     /*  510967 */ GIM_Try, /*On fail goto*//*Label 7763*/ GIMT_Encode4(511018), // Rule ID 14374 //
     /*  510972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  510975 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  510978 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  510983 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  510987 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  510994 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  510994 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  510997 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  510999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511009 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511012 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511016 */   GIR_RootConstrainSelectedInstOperands,
     /*  511017 */   // GIR_Coverage, 14374,
     /*  511017 */   GIR_EraseRootFromParent_Done,
     /*  511018 */ // Label 7763: @511018
     /*  511018 */ GIM_Try, /*On fail goto*//*Label 7764*/ GIMT_Encode4(511069), // Rule ID 14375 //
     /*  511023 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  511026 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511029 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511038 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511045 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511048 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511050 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511063 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511067 */   GIR_RootConstrainSelectedInstOperands,
     /*  511068 */   // GIR_Coverage, 14375,
     /*  511068 */   GIR_EraseRootFromParent_Done,
     /*  511069 */ // Label 7764: @511069
     /*  511069 */ GIM_Try, /*On fail goto*//*Label 7765*/ GIMT_Encode4(511120), // Rule ID 14376 //
     /*  511074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  511077 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511080 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511085 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511089 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511096 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511096 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511099 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511111 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511114 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511118 */   GIR_RootConstrainSelectedInstOperands,
     /*  511119 */   // GIR_Coverage, 14376,
     /*  511119 */   GIR_EraseRootFromParent_Done,
     /*  511120 */ // Label 7765: @511120
     /*  511120 */ GIM_Try, /*On fail goto*//*Label 7766*/ GIMT_Encode4(511171), // Rule ID 14402 //
     /*  511125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  511128 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511131 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511136 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511140 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511147 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511150 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511162 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511165 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511169 */   GIR_RootConstrainSelectedInstOperands,
     /*  511170 */   // GIR_Coverage, 14402,
     /*  511170 */   GIR_EraseRootFromParent_Done,
     /*  511171 */ // Label 7766: @511171
     /*  511171 */ GIM_Try, /*On fail goto*//*Label 7767*/ GIMT_Encode4(511222), // Rule ID 14403 //
     /*  511176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  511179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511182 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511187 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511191 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511198 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511201 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511203 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511208 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511213 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511216 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511220 */   GIR_RootConstrainSelectedInstOperands,
     /*  511221 */   // GIR_Coverage, 14403,
     /*  511221 */   GIR_EraseRootFromParent_Done,
     /*  511222 */ // Label 7767: @511222
     /*  511222 */ GIM_Try, /*On fail goto*//*Label 7768*/ GIMT_Encode4(511273), // Rule ID 14404 //
     /*  511227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  511230 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511233 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511238 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511249 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511252 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511271 */   GIR_RootConstrainSelectedInstOperands,
     /*  511272 */   // GIR_Coverage, 14404,
     /*  511272 */   GIR_EraseRootFromParent_Done,
     /*  511273 */ // Label 7768: @511273
     /*  511273 */ GIM_Try, /*On fail goto*//*Label 7769*/ GIMT_Encode4(511324), // Rule ID 14405 //
     /*  511278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  511281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511289 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511293 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511300 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511300 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511303 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511305 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511318 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511322 */   GIR_RootConstrainSelectedInstOperands,
     /*  511323 */   // GIR_Coverage, 14405,
     /*  511323 */   GIR_EraseRootFromParent_Done,
     /*  511324 */ // Label 7769: @511324
     /*  511324 */ GIM_Try, /*On fail goto*//*Label 7770*/ GIMT_Encode4(511375), // Rule ID 14406 //
     /*  511329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  511332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511335 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511340 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511344 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  511351 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  511351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  511354 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  511361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511369 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511373 */   GIR_RootConstrainSelectedInstOperands,
     /*  511374 */   // GIR_Coverage, 14406,
     /*  511374 */   GIR_EraseRootFromParent_Done,
     /*  511375 */ // Label 7770: @511375
     /*  511375 */ GIM_Try, /*On fail goto*//*Label 7771*/ GIMT_Encode4(511426), // Rule ID 14367 //
     /*  511380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  511383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511386 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511391 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511395 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511402 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511405 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511417 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511420 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511424 */   GIR_RootConstrainSelectedInstOperands,
     /*  511425 */   // GIR_Coverage, 14367,
     /*  511425 */   GIR_EraseRootFromParent_Done,
     /*  511426 */ // Label 7771: @511426
     /*  511426 */ GIM_Try, /*On fail goto*//*Label 7772*/ GIMT_Encode4(511477), // Rule ID 14368 //
     /*  511431 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  511434 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511437 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511453 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511456 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511458 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511468 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511471 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511475 */   GIR_RootConstrainSelectedInstOperands,
     /*  511476 */   // GIR_Coverage, 14368,
     /*  511476 */   GIR_EraseRootFromParent_Done,
     /*  511477 */ // Label 7772: @511477
     /*  511477 */ GIM_Try, /*On fail goto*//*Label 7773*/ GIMT_Encode4(511528), // Rule ID 14369 //
     /*  511482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  511485 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511488 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511493 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511497 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511504 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511507 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511519 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511522 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511526 */   GIR_RootConstrainSelectedInstOperands,
     /*  511527 */   // GIR_Coverage, 14369,
     /*  511527 */   GIR_EraseRootFromParent_Done,
     /*  511528 */ // Label 7773: @511528
     /*  511528 */ GIM_Try, /*On fail goto*//*Label 7774*/ GIMT_Encode4(511579), // Rule ID 14370 //
     /*  511533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  511536 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511539 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511544 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511548 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511555 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511558 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511570 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511573 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511577 */   GIR_RootConstrainSelectedInstOperands,
     /*  511578 */   // GIR_Coverage, 14370,
     /*  511578 */   GIR_EraseRootFromParent_Done,
     /*  511579 */ // Label 7774: @511579
     /*  511579 */ GIM_Try, /*On fail goto*//*Label 7775*/ GIMT_Encode4(511630), // Rule ID 14371 //
     /*  511584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  511587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511590 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511606 */   // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511609 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511621 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511624 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511628 */   GIR_RootConstrainSelectedInstOperands,
     /*  511629 */   // GIR_Coverage, 14371,
     /*  511629 */   GIR_EraseRootFromParent_Done,
     /*  511630 */ // Label 7775: @511630
     /*  511630 */ GIM_Try, /*On fail goto*//*Label 7776*/ GIMT_Encode4(511681), // Rule ID 14397 //
     /*  511635 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  511638 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511641 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511646 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511650 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511657 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511660 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511672 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511675 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511679 */   GIR_RootConstrainSelectedInstOperands,
     /*  511680 */   // GIR_Coverage, 14397,
     /*  511680 */   GIR_EraseRootFromParent_Done,
     /*  511681 */ // Label 7776: @511681
     /*  511681 */ GIM_Try, /*On fail goto*//*Label 7777*/ GIMT_Encode4(511732), // Rule ID 14398 //
     /*  511686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  511689 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511692 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511697 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511708 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511711 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511713 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511723 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511726 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511730 */   GIR_RootConstrainSelectedInstOperands,
     /*  511731 */   // GIR_Coverage, 14398,
     /*  511731 */   GIR_EraseRootFromParent_Done,
     /*  511732 */ // Label 7777: @511732
     /*  511732 */ GIM_Try, /*On fail goto*//*Label 7778*/ GIMT_Encode4(511783), // Rule ID 14399 //
     /*  511737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  511740 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511743 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511748 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511752 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511759 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511762 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511777 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511781 */   GIR_RootConstrainSelectedInstOperands,
     /*  511782 */   // GIR_Coverage, 14399,
     /*  511782 */   GIR_EraseRootFromParent_Done,
     /*  511783 */ // Label 7778: @511783
     /*  511783 */ GIM_Try, /*On fail goto*//*Label 7779*/ GIMT_Encode4(511834), // Rule ID 14400 //
     /*  511788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  511791 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511794 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511799 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511803 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511810 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511813 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511820 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511825 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511828 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511832 */   GIR_RootConstrainSelectedInstOperands,
     /*  511833 */   // GIR_Coverage, 14400,
     /*  511833 */   GIR_EraseRootFromParent_Done,
     /*  511834 */ // Label 7779: @511834
     /*  511834 */ GIM_Try, /*On fail goto*//*Label 7780*/ GIMT_Encode4(511885), // Rule ID 14401 //
     /*  511839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  511842 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511845 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  511850 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511854 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  511861 */   // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  511861 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  511864 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  511866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  511871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  511876 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511879 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511883 */   GIR_RootConstrainSelectedInstOperands,
     /*  511884 */   // GIR_Coverage, 14401,
     /*  511884 */   GIR_EraseRootFromParent_Done,
     /*  511885 */ // Label 7780: @511885
     /*  511885 */ GIM_Try, /*On fail goto*//*Label 7781*/ GIMT_Encode4(511951), // Rule ID 16098 //
     /*  511890 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  511893 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511896 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  511903 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511907 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  511914 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  511914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  511917 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  511919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  511924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  511929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  511934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  511939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511942 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  511945 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  511949 */   GIR_RootConstrainSelectedInstOperands,
     /*  511950 */   // GIR_Coverage, 16098,
     /*  511950 */   GIR_EraseRootFromParent_Done,
     /*  511951 */ // Label 7781: @511951
     /*  511951 */ GIM_Try, /*On fail goto*//*Label 7782*/ GIMT_Encode4(512017), // Rule ID 16099 //
     /*  511956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  511959 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  511962 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  511969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  511973 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  511980 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  511980 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  511983 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  511985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  511990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  511995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512000 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512005 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512008 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512011 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512015 */   GIR_RootConstrainSelectedInstOperands,
     /*  512016 */   // GIR_Coverage, 16099,
     /*  512016 */   GIR_EraseRootFromParent_Done,
     /*  512017 */ // Label 7782: @512017
     /*  512017 */ GIM_Try, /*On fail goto*//*Label 7783*/ GIMT_Encode4(512083), // Rule ID 16100 //
     /*  512022 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  512025 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512028 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512046 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512049 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512074 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512077 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512081 */   GIR_RootConstrainSelectedInstOperands,
     /*  512082 */   // GIR_Coverage, 16100,
     /*  512082 */   GIR_EraseRootFromParent_Done,
     /*  512083 */ // Label 7783: @512083
     /*  512083 */ GIM_Try, /*On fail goto*//*Label 7784*/ GIMT_Encode4(512149), // Rule ID 16101 //
     /*  512088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  512091 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512094 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512101 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512105 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512112 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512115 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512140 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512143 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512147 */   GIR_RootConstrainSelectedInstOperands,
     /*  512148 */   // GIR_Coverage, 16101,
     /*  512148 */   GIR_EraseRootFromParent_Done,
     /*  512149 */ // Label 7784: @512149
     /*  512149 */ GIM_Try, /*On fail goto*//*Label 7785*/ GIMT_Encode4(512215), // Rule ID 16102 //
     /*  512154 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  512157 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512160 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512167 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512171 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512178 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512178 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512181 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512193 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512198 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512203 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512206 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512209 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512213 */   GIR_RootConstrainSelectedInstOperands,
     /*  512214 */   // GIR_Coverage, 16102,
     /*  512214 */   GIR_EraseRootFromParent_Done,
     /*  512215 */ // Label 7785: @512215
     /*  512215 */ GIM_Try, /*On fail goto*//*Label 7786*/ GIMT_Encode4(512281), // Rule ID 16108 //
     /*  512220 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  512223 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512226 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512233 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512237 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512244 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512244 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512247 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512279 */   GIR_RootConstrainSelectedInstOperands,
     /*  512280 */   // GIR_Coverage, 16108,
     /*  512280 */   GIR_EraseRootFromParent_Done,
     /*  512281 */ // Label 7786: @512281
     /*  512281 */ GIM_Try, /*On fail goto*//*Label 7787*/ GIMT_Encode4(512347), // Rule ID 16109 //
     /*  512286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  512289 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512292 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512299 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512303 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512310 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512310 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512313 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512315 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512320 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512330 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512335 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512338 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512341 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512345 */   GIR_RootConstrainSelectedInstOperands,
     /*  512346 */   // GIR_Coverage, 16109,
     /*  512346 */   GIR_EraseRootFromParent_Done,
     /*  512347 */ // Label 7787: @512347
     /*  512347 */ GIM_Try, /*On fail goto*//*Label 7788*/ GIMT_Encode4(512413), // Rule ID 16110 //
     /*  512352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  512355 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512358 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512365 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512369 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512376 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512379 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512401 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512404 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512407 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512411 */   GIR_RootConstrainSelectedInstOperands,
     /*  512412 */   // GIR_Coverage, 16110,
     /*  512412 */   GIR_EraseRootFromParent_Done,
     /*  512413 */ // Label 7788: @512413
     /*  512413 */ GIM_Try, /*On fail goto*//*Label 7789*/ GIMT_Encode4(512479), // Rule ID 16111 //
     /*  512418 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  512421 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512424 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512431 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512435 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512442 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512442 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512445 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512447 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512467 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512470 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512473 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512477 */   GIR_RootConstrainSelectedInstOperands,
     /*  512478 */   // GIR_Coverage, 16111,
     /*  512478 */   GIR_EraseRootFromParent_Done,
     /*  512479 */ // Label 7789: @512479
     /*  512479 */ GIM_Try, /*On fail goto*//*Label 7790*/ GIMT_Encode4(512545), // Rule ID 16112 //
     /*  512484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  512487 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512490 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512497 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512501 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512508 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512511 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512528 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512533 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512536 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512543 */   GIR_RootConstrainSelectedInstOperands,
     /*  512544 */   // GIR_Coverage, 16112,
     /*  512544 */   GIR_EraseRootFromParent_Done,
     /*  512545 */ // Label 7790: @512545
     /*  512545 */ GIM_Try, /*On fail goto*//*Label 7791*/ GIMT_Encode4(512611), // Rule ID 16118 //
     /*  512550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  512553 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512556 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512563 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512567 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512574 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512574 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512577 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512579 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512584 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512602 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512605 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512609 */   GIR_RootConstrainSelectedInstOperands,
     /*  512610 */   // GIR_Coverage, 16118,
     /*  512610 */   GIR_EraseRootFromParent_Done,
     /*  512611 */ // Label 7791: @512611
     /*  512611 */ GIM_Try, /*On fail goto*//*Label 7792*/ GIMT_Encode4(512677), // Rule ID 16119 //
     /*  512616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  512619 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512622 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512640 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512643 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512665 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512668 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512671 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512675 */   GIR_RootConstrainSelectedInstOperands,
     /*  512676 */   // GIR_Coverage, 16119,
     /*  512676 */   GIR_EraseRootFromParent_Done,
     /*  512677 */ // Label 7792: @512677
     /*  512677 */ GIM_Try, /*On fail goto*//*Label 7793*/ GIMT_Encode4(512743), // Rule ID 16120 //
     /*  512682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  512685 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512688 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512695 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512699 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512706 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512706 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512709 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512716 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512721 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512731 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512734 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512741 */   GIR_RootConstrainSelectedInstOperands,
     /*  512742 */   // GIR_Coverage, 16120,
     /*  512742 */   GIR_EraseRootFromParent_Done,
     /*  512743 */ // Label 7793: @512743
     /*  512743 */ GIM_Try, /*On fail goto*//*Label 7794*/ GIMT_Encode4(512809), // Rule ID 16121 //
     /*  512748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  512751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512754 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512772 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512775 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512797 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512807 */   GIR_RootConstrainSelectedInstOperands,
     /*  512808 */   // GIR_Coverage, 16121,
     /*  512808 */   GIR_EraseRootFromParent_Done,
     /*  512809 */ // Label 7794: @512809
     /*  512809 */ GIM_Try, /*On fail goto*//*Label 7795*/ GIMT_Encode4(512875), // Rule ID 16122 //
     /*  512814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  512817 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512820 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512831 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512838 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  512841 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512843 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512863 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512866 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512869 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512873 */   GIR_RootConstrainSelectedInstOperands,
     /*  512874 */   // GIR_Coverage, 16122,
     /*  512874 */   GIR_EraseRootFromParent_Done,
     /*  512875 */ // Label 7795: @512875
     /*  512875 */ GIM_Try, /*On fail goto*//*Label 7796*/ GIMT_Encode4(512941), // Rule ID 16128 //
     /*  512880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  512883 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512886 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512893 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512897 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512904 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512907 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512929 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512932 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512935 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  512939 */   GIR_RootConstrainSelectedInstOperands,
     /*  512940 */   // GIR_Coverage, 16128,
     /*  512940 */   GIR_EraseRootFromParent_Done,
     /*  512941 */ // Label 7796: @512941
     /*  512941 */ GIM_Try, /*On fail goto*//*Label 7797*/ GIMT_Encode4(513007), // Rule ID 16129 //
     /*  512946 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  512949 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  512952 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  512959 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  512963 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  512970 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  512970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  512973 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  512975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  512980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  512985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  512990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  512995 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  512998 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513001 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513005 */   GIR_RootConstrainSelectedInstOperands,
     /*  513006 */   // GIR_Coverage, 16129,
     /*  513006 */   GIR_EraseRootFromParent_Done,
     /*  513007 */ // Label 7797: @513007
     /*  513007 */ GIM_Try, /*On fail goto*//*Label 7798*/ GIMT_Encode4(513073), // Rule ID 16130 //
     /*  513012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  513015 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513018 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  513025 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513029 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  513036 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  513036 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  513039 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  513041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513061 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513067 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513071 */   GIR_RootConstrainSelectedInstOperands,
     /*  513072 */   // GIR_Coverage, 16130,
     /*  513072 */   GIR_EraseRootFromParent_Done,
     /*  513073 */ // Label 7798: @513073
     /*  513073 */ GIM_Try, /*On fail goto*//*Label 7799*/ GIMT_Encode4(513139), // Rule ID 16131 //
     /*  513078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  513081 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513084 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  513091 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513095 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  513102 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  513102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  513105 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  513107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513127 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513130 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513133 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513137 */   GIR_RootConstrainSelectedInstOperands,
     /*  513138 */   // GIR_Coverage, 16131,
     /*  513138 */   GIR_EraseRootFromParent_Done,
     /*  513139 */ // Label 7799: @513139
     /*  513139 */ GIM_Try, /*On fail goto*//*Label 7800*/ GIMT_Encode4(513205), // Rule ID 16132 //
     /*  513144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  513147 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513150 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  513157 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513161 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  513168 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  513168 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  513171 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  513173 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513188 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513193 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513196 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513199 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513203 */   GIR_RootConstrainSelectedInstOperands,
     /*  513204 */   // GIR_Coverage, 16132,
     /*  513204 */   GIR_EraseRootFromParent_Done,
     /*  513205 */ // Label 7800: @513205
     /*  513205 */ GIM_Try, /*On fail goto*//*Label 7801*/ GIMT_Encode4(513269), // Rule ID 25941 //
     /*  513210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  513213 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513216 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513221 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513225 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513232 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN),
     /*  513235 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513237 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513242 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513247 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513257 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513260 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513263 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513267 */   GIR_RootConstrainSelectedInstOperands,
     /*  513268 */   // GIR_Coverage, 25941,
     /*  513268 */   GIR_EraseRootFromParent_Done,
     /*  513269 */ // Label 7801: @513269
     /*  513269 */ GIM_Try, /*On fail goto*//*Label 7802*/ GIMT_Encode4(513333), // Rule ID 25942 //
     /*  513274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  513277 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513280 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513285 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513289 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513296 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513296 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN),
     /*  513299 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513301 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513306 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513311 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513316 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513321 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513324 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513327 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513331 */   GIR_RootConstrainSelectedInstOperands,
     /*  513332 */   // GIR_Coverage, 25942,
     /*  513332 */   GIR_EraseRootFromParent_Done,
     /*  513333 */ // Label 7802: @513333
     /*  513333 */ GIM_Try, /*On fail goto*//*Label 7803*/ GIMT_Encode4(513397), // Rule ID 25943 //
     /*  513338 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  513341 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513344 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513349 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513353 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513360 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN),
     /*  513363 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513365 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513375 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513385 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513388 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513391 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513395 */   GIR_RootConstrainSelectedInstOperands,
     /*  513396 */   // GIR_Coverage, 25943,
     /*  513396 */   GIR_EraseRootFromParent_Done,
     /*  513397 */ // Label 7803: @513397
     /*  513397 */ GIM_Try, /*On fail goto*//*Label 7804*/ GIMT_Encode4(513461), // Rule ID 25944 //
     /*  513402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  513405 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513408 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513413 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513417 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513424 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN),
     /*  513427 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513449 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513452 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513455 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513459 */   GIR_RootConstrainSelectedInstOperands,
     /*  513460 */   // GIR_Coverage, 25944,
     /*  513460 */   GIR_EraseRootFromParent_Done,
     /*  513461 */ // Label 7804: @513461
     /*  513461 */ GIM_Try, /*On fail goto*//*Label 7805*/ GIMT_Encode4(513525), // Rule ID 25945 //
     /*  513466 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  513469 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513472 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513477 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513481 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513488 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513488 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN),
     /*  513491 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513508 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513513 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513516 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513519 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513523 */   GIR_RootConstrainSelectedInstOperands,
     /*  513524 */   // GIR_Coverage, 25945,
     /*  513524 */   GIR_EraseRootFromParent_Done,
     /*  513525 */ // Label 7805: @513525
     /*  513525 */ GIM_Try, /*On fail goto*//*Label 7806*/ GIMT_Encode4(513589), // Rule ID 25951 //
     /*  513530 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  513533 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513536 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513541 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513545 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513552 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513552 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN),
     /*  513555 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513572 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513577 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513580 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513583 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513587 */   GIR_RootConstrainSelectedInstOperands,
     /*  513588 */   // GIR_Coverage, 25951,
     /*  513588 */   GIR_EraseRootFromParent_Done,
     /*  513589 */ // Label 7806: @513589
     /*  513589 */ GIM_Try, /*On fail goto*//*Label 7807*/ GIMT_Encode4(513653), // Rule ID 25952 //
     /*  513594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  513597 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513600 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513605 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513609 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513616 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513616 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN),
     /*  513619 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513626 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513641 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513644 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513647 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513651 */   GIR_RootConstrainSelectedInstOperands,
     /*  513652 */   // GIR_Coverage, 25952,
     /*  513652 */   GIR_EraseRootFromParent_Done,
     /*  513653 */ // Label 7807: @513653
     /*  513653 */ GIM_Try, /*On fail goto*//*Label 7808*/ GIMT_Encode4(513717), // Rule ID 25953 //
     /*  513658 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  513661 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513664 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513669 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513680 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN),
     /*  513683 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513685 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513705 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513708 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513711 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513715 */   GIR_RootConstrainSelectedInstOperands,
     /*  513716 */   // GIR_Coverage, 25953,
     /*  513716 */   GIR_EraseRootFromParent_Done,
     /*  513717 */ // Label 7808: @513717
     /*  513717 */ GIM_Try, /*On fail goto*//*Label 7809*/ GIMT_Encode4(513781), // Rule ID 25954 //
     /*  513722 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  513725 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513728 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513733 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513737 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513744 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN),
     /*  513747 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513749 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513754 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513769 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513772 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513775 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513779 */   GIR_RootConstrainSelectedInstOperands,
     /*  513780 */   // GIR_Coverage, 25954,
     /*  513780 */   GIR_EraseRootFromParent_Done,
     /*  513781 */ // Label 7809: @513781
     /*  513781 */ GIM_Try, /*On fail goto*//*Label 7810*/ GIMT_Encode4(513845), // Rule ID 25955 //
     /*  513786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  513789 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513792 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  513797 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513801 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  513808 */   // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  513808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN),
     /*  513811 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  513813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  513818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  513823 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  513828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  513833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513836 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513839 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513843 */   GIR_RootConstrainSelectedInstOperands,
     /*  513844 */   // GIR_Coverage, 25955,
     /*  513844 */   GIR_EraseRootFromParent_Done,
     /*  513845 */ // Label 7810: @513845
     /*  513845 */ GIM_Try, /*On fail goto*//*Label 7811*/ GIMT_Encode4(513965), // Rule ID 29424 //
     /*  513850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  513853 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513856 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  513860 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  513865 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513869 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  513876 */   // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  513876 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  513879 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  513883 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  513888 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  513894 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  513899 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  513904 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  513907 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  513911 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  513916 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  513922 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  513927 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  513932 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  513935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  513940 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  513943 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  513946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  513951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  513956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  513959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  513963 */   GIR_RootConstrainSelectedInstOperands,
     /*  513964 */   // GIR_Coverage, 29424,
     /*  513964 */   GIR_EraseRootFromParent_Done,
     /*  513965 */ // Label 7811: @513965
     /*  513965 */ GIM_Try, /*On fail goto*//*Label 7812*/ GIMT_Encode4(514085), // Rule ID 29436 //
     /*  513970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  513973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  513976 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  513980 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  513985 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  513989 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  513996 */   // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  513996 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  513999 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  514003 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  514008 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  514014 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  514019 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  514024 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  514027 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  514031 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  514036 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  514042 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  514047 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  514052 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  514055 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  514060 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  514063 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  514066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  514071 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  514076 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514079 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514083 */   GIR_RootConstrainSelectedInstOperands,
     /*  514084 */   // GIR_Coverage, 29436,
     /*  514084 */   GIR_EraseRootFromParent_Done,
     /*  514085 */ // Label 7812: @514085
     /*  514085 */ GIM_Try, /*On fail goto*//*Label 7813*/ GIMT_Encode4(514146), // Rule ID 16093 //
     /*  514090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  514093 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514096 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514103 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514107 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514114 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514114 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514117 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514140 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514144 */   GIR_RootConstrainSelectedInstOperands,
     /*  514145 */   // GIR_Coverage, 16093,
     /*  514145 */   GIR_EraseRootFromParent_Done,
     /*  514146 */ // Label 7813: @514146
     /*  514146 */ GIM_Try, /*On fail goto*//*Label 7814*/ GIMT_Encode4(514207), // Rule ID 16094 //
     /*  514151 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  514154 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514164 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514168 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514175 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514178 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514195 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514198 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514201 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514205 */   GIR_RootConstrainSelectedInstOperands,
     /*  514206 */   // GIR_Coverage, 16094,
     /*  514206 */   GIR_EraseRootFromParent_Done,
     /*  514207 */ // Label 7814: @514207
     /*  514207 */ GIM_Try, /*On fail goto*//*Label 7815*/ GIMT_Encode4(514268), // Rule ID 16095 //
     /*  514212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  514215 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514236 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514239 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514241 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514256 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514262 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514266 */   GIR_RootConstrainSelectedInstOperands,
     /*  514267 */   // GIR_Coverage, 16095,
     /*  514267 */   GIR_EraseRootFromParent_Done,
     /*  514268 */ // Label 7815: @514268
     /*  514268 */ GIM_Try, /*On fail goto*//*Label 7816*/ GIMT_Encode4(514329), // Rule ID 16096 //
     /*  514273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  514276 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514279 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514286 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514290 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514297 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514300 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514302 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514317 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514323 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514327 */   GIR_RootConstrainSelectedInstOperands,
     /*  514328 */   // GIR_Coverage, 16096,
     /*  514328 */   GIR_EraseRootFromParent_Done,
     /*  514329 */ // Label 7816: @514329
     /*  514329 */ GIM_Try, /*On fail goto*//*Label 7817*/ GIMT_Encode4(514390), // Rule ID 16097 //
     /*  514334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  514337 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514340 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514347 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514351 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514358 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514358 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514361 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514381 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514384 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514388 */   GIR_RootConstrainSelectedInstOperands,
     /*  514389 */   // GIR_Coverage, 16097,
     /*  514389 */   GIR_EraseRootFromParent_Done,
     /*  514390 */ // Label 7817: @514390
     /*  514390 */ GIM_Try, /*On fail goto*//*Label 7818*/ GIMT_Encode4(514451), // Rule ID 16103 //
     /*  514395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  514398 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514401 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514408 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514412 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514419 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  514422 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514439 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514442 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514445 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514449 */   GIR_RootConstrainSelectedInstOperands,
     /*  514450 */   // GIR_Coverage, 16103,
     /*  514450 */   GIR_EraseRootFromParent_Done,
     /*  514451 */ // Label 7818: @514451
     /*  514451 */ GIM_Try, /*On fail goto*//*Label 7819*/ GIMT_Encode4(514512), // Rule ID 16104 //
     /*  514456 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  514459 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514462 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514469 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514473 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514480 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  514483 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514485 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514500 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514503 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514506 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514510 */   GIR_RootConstrainSelectedInstOperands,
     /*  514511 */   // GIR_Coverage, 16104,
     /*  514511 */   GIR_EraseRootFromParent_Done,
     /*  514512 */ // Label 7819: @514512
     /*  514512 */ GIM_Try, /*On fail goto*//*Label 7820*/ GIMT_Encode4(514573), // Rule ID 16105 //
     /*  514517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  514520 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514523 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514530 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514534 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514541 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  514544 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514546 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514561 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514564 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514571 */   GIR_RootConstrainSelectedInstOperands,
     /*  514572 */   // GIR_Coverage, 16105,
     /*  514572 */   GIR_EraseRootFromParent_Done,
     /*  514573 */ // Label 7820: @514573
     /*  514573 */ GIM_Try, /*On fail goto*//*Label 7821*/ GIMT_Encode4(514634), // Rule ID 16106 //
     /*  514578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  514581 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514591 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514595 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514602 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  514605 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514622 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514625 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514628 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514632 */   GIR_RootConstrainSelectedInstOperands,
     /*  514633 */   // GIR_Coverage, 16106,
     /*  514633 */   GIR_EraseRootFromParent_Done,
     /*  514634 */ // Label 7821: @514634
     /*  514634 */ GIM_Try, /*On fail goto*//*Label 7822*/ GIMT_Encode4(514695), // Rule ID 16107 //
     /*  514639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  514642 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514645 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514652 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514656 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514663 */   // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  514666 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514683 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514686 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514689 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514693 */   GIR_RootConstrainSelectedInstOperands,
     /*  514694 */   // GIR_Coverage, 16107,
     /*  514694 */   GIR_EraseRootFromParent_Done,
     /*  514695 */ // Label 7822: @514695
     /*  514695 */ GIM_Try, /*On fail goto*//*Label 7823*/ GIMT_Encode4(514756), // Rule ID 16113 //
     /*  514700 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  514703 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514706 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514713 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514717 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514724 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514727 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514744 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514747 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514750 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514754 */   GIR_RootConstrainSelectedInstOperands,
     /*  514755 */   // GIR_Coverage, 16113,
     /*  514755 */   GIR_EraseRootFromParent_Done,
     /*  514756 */ // Label 7823: @514756
     /*  514756 */ GIM_Try, /*On fail goto*//*Label 7824*/ GIMT_Encode4(514817), // Rule ID 16114 //
     /*  514761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  514764 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514767 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514774 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514778 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514785 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514788 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514805 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514808 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514811 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514815 */   GIR_RootConstrainSelectedInstOperands,
     /*  514816 */   // GIR_Coverage, 16114,
     /*  514816 */   GIR_EraseRootFromParent_Done,
     /*  514817 */ // Label 7824: @514817
     /*  514817 */ GIM_Try, /*On fail goto*//*Label 7825*/ GIMT_Encode4(514878), // Rule ID 16115 //
     /*  514822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  514825 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514828 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514835 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514839 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514846 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514846 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514849 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514866 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514869 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514872 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514876 */   GIR_RootConstrainSelectedInstOperands,
     /*  514877 */   // GIR_Coverage, 16115,
     /*  514877 */   GIR_EraseRootFromParent_Done,
     /*  514878 */ // Label 7825: @514878
     /*  514878 */ GIM_Try, /*On fail goto*//*Label 7826*/ GIMT_Encode4(514939), // Rule ID 16116 //
     /*  514883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  514886 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514907 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514910 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514927 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514930 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514933 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514937 */   GIR_RootConstrainSelectedInstOperands,
     /*  514938 */   // GIR_Coverage, 16116,
     /*  514938 */   GIR_EraseRootFromParent_Done,
     /*  514939 */ // Label 7826: @514939
     /*  514939 */ GIM_Try, /*On fail goto*//*Label 7827*/ GIMT_Encode4(515000), // Rule ID 16117 //
     /*  514944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  514947 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  514950 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  514957 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  514961 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  514968 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  514968 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  514971 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  514973 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  514978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  514983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  514988 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514991 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  514994 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  514998 */   GIR_RootConstrainSelectedInstOperands,
     /*  514999 */   // GIR_Coverage, 16117,
     /*  514999 */   GIR_EraseRootFromParent_Done,
     /*  515000 */ // Label 7827: @515000
     /*  515000 */ GIM_Try, /*On fail goto*//*Label 7828*/ GIMT_Encode4(515061), // Rule ID 16123 //
     /*  515005 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  515008 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515011 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515018 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515022 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  515029 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  515029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  515032 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  515034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  515039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  515044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515049 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515052 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515055 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515059 */   GIR_RootConstrainSelectedInstOperands,
     /*  515060 */   // GIR_Coverage, 16123,
     /*  515060 */   GIR_EraseRootFromParent_Done,
     /*  515061 */ // Label 7828: @515061
     /*  515061 */ GIM_Try, /*On fail goto*//*Label 7829*/ GIMT_Encode4(515122), // Rule ID 16124 //
     /*  515066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  515069 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515072 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515079 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515083 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  515090 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  515090 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  515093 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  515095 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  515100 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  515105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515110 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515113 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515116 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515120 */   GIR_RootConstrainSelectedInstOperands,
     /*  515121 */   // GIR_Coverage, 16124,
     /*  515121 */   GIR_EraseRootFromParent_Done,
     /*  515122 */ // Label 7829: @515122
     /*  515122 */ GIM_Try, /*On fail goto*//*Label 7830*/ GIMT_Encode4(515183), // Rule ID 16125 //
     /*  515127 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  515130 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515133 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515140 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515144 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  515151 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  515151 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  515154 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  515156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  515161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  515166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515171 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515181 */   GIR_RootConstrainSelectedInstOperands,
     /*  515182 */   // GIR_Coverage, 16125,
     /*  515182 */   GIR_EraseRootFromParent_Done,
     /*  515183 */ // Label 7830: @515183
     /*  515183 */ GIM_Try, /*On fail goto*//*Label 7831*/ GIMT_Encode4(515244), // Rule ID 16126 //
     /*  515188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  515191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515194 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515201 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515205 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  515212 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  515212 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  515215 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  515217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  515222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  515227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515232 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515235 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515242 */   GIR_RootConstrainSelectedInstOperands,
     /*  515243 */   // GIR_Coverage, 16126,
     /*  515243 */   GIR_EraseRootFromParent_Done,
     /*  515244 */ // Label 7831: @515244
     /*  515244 */ GIM_Try, /*On fail goto*//*Label 7832*/ GIMT_Encode4(515305), // Rule ID 16127 //
     /*  515249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  515252 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515255 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515262 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515266 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  515273 */   // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  515273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  515276 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  515278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  515283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  515288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515293 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515296 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515299 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515303 */   GIR_RootConstrainSelectedInstOperands,
     /*  515304 */   // GIR_Coverage, 16127,
     /*  515304 */   GIR_EraseRootFromParent_Done,
     /*  515305 */ // Label 7832: @515305
     /*  515305 */ GIM_Try, /*On fail goto*//*Label 7833*/ GIMT_Encode4(515421), // Rule ID 29430 //
     /*  515310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  515313 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515316 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  515321 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515325 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  515332 */   // (st v2i32:{ *:[v2i32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  515332 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  515335 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  515339 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  515344 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  515350 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  515355 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  515360 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  515363 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  515367 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  515372 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  515378 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  515383 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  515388 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  515391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  515396 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  515399 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  515402 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  515407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  515412 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515415 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515419 */   GIR_RootConstrainSelectedInstOperands,
     /*  515420 */   // GIR_Coverage, 29430,
     /*  515420 */   GIR_EraseRootFromParent_Done,
     /*  515421 */ // Label 7833: @515421
     /*  515421 */ GIM_Try, /*On fail goto*//*Label 7834*/ GIMT_Encode4(515537), // Rule ID 29442 //
     /*  515426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  515429 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515432 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  515437 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515441 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  515448 */   // (st v2f32:{ *:[v2f32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  515448 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  515451 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  515455 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  515460 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  515466 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  515471 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  515476 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  515479 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  515483 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  515488 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  515494 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  515499 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  515504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  515507 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  515512 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  515515 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  515518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  515523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  515528 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  515531 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515535 */   GIR_RootConstrainSelectedInstOperands,
     /*  515536 */   // GIR_Coverage, 29442,
     /*  515536 */   GIR_EraseRootFromParent_Done,
     /*  515537 */ // Label 7834: @515537
     /*  515537 */ GIM_Try, /*On fail goto*//*Label 7835*/ GIMT_Encode4(515604), // Rule ID 12877 //
     /*  515542 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  515545 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  515548 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  515555 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515562 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515566 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515573 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515576 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515581 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515583 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515588 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515598 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515602 */   GIR_RootConstrainSelectedInstOperands,
     /*  515603 */   // GIR_Coverage, 12877,
     /*  515603 */   GIR_EraseRootFromParent_Done,
     /*  515604 */ // Label 7835: @515604
     /*  515604 */ GIM_Try, /*On fail goto*//*Label 7836*/ GIMT_Encode4(515671), // Rule ID 12878 //
     /*  515609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  515612 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  515615 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  515622 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515629 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515633 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515640 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515640 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515648 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515655 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515660 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515665 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515669 */   GIR_RootConstrainSelectedInstOperands,
     /*  515670 */   // GIR_Coverage, 12878,
     /*  515670 */   GIR_EraseRootFromParent_Done,
     /*  515671 */ // Label 7836: @515671
     /*  515671 */ GIM_Try, /*On fail goto*//*Label 7837*/ GIMT_Encode4(515738), // Rule ID 12879 //
     /*  515676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  515679 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  515682 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  515689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515696 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515700 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515707 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515707 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515715 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515736 */   GIR_RootConstrainSelectedInstOperands,
     /*  515737 */   // GIR_Coverage, 12879,
     /*  515737 */   GIR_EraseRootFromParent_Done,
     /*  515738 */ // Label 7837: @515738
     /*  515738 */ GIM_Try, /*On fail goto*//*Label 7838*/ GIMT_Encode4(515805), // Rule ID 12880 //
     /*  515743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  515746 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  515749 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  515756 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515774 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515782 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515799 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515803 */   GIR_RootConstrainSelectedInstOperands,
     /*  515804 */   // GIR_Coverage, 12880,
     /*  515804 */   GIR_EraseRootFromParent_Done,
     /*  515805 */ // Label 7838: @515805
     /*  515805 */ GIM_Try, /*On fail goto*//*Label 7839*/ GIMT_Encode4(515872), // Rule ID 12881 //
     /*  515810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  515813 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  515816 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  515823 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515830 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515834 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515841 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515844 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515849 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515866 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515870 */   GIR_RootConstrainSelectedInstOperands,
     /*  515871 */   // GIR_Coverage, 12881,
     /*  515871 */   GIR_EraseRootFromParent_Done,
     /*  515872 */ // Label 7839: @515872
     /*  515872 */ GIM_Try, /*On fail goto*//*Label 7840*/ GIMT_Encode4(515932), // Rule ID 12313 //
     /*  515877 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  515880 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515883 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515890 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515894 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515901 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515901 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515909 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515926 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515930 */   GIR_RootConstrainSelectedInstOperands,
     /*  515931 */   // GIR_Coverage, 12313,
     /*  515931 */   GIR_EraseRootFromParent_Done,
     /*  515932 */ // Label 7840: @515932
     /*  515932 */ GIM_Try, /*On fail goto*//*Label 7841*/ GIMT_Encode4(515992), // Rule ID 12314 //
     /*  515937 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  515940 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  515943 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  515950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  515954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  515961 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  515961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  515964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  515969 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  515971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  515976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  515981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  515986 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  515990 */   GIR_RootConstrainSelectedInstOperands,
     /*  515991 */   // GIR_Coverage, 12314,
     /*  515991 */   GIR_EraseRootFromParent_Done,
     /*  515992 */ // Label 7841: @515992
     /*  515992 */ GIM_Try, /*On fail goto*//*Label 7842*/ GIMT_Encode4(516052), // Rule ID 12315 //
     /*  515997 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  516000 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516003 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516010 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516014 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516021 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516029 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516050 */   GIR_RootConstrainSelectedInstOperands,
     /*  516051 */   // GIR_Coverage, 12315,
     /*  516051 */   GIR_EraseRootFromParent_Done,
     /*  516052 */ // Label 7842: @516052
     /*  516052 */ GIM_Try, /*On fail goto*//*Label 7843*/ GIMT_Encode4(516112), // Rule ID 12316 //
     /*  516057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  516060 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516063 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516070 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516074 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516081 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516089 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516091 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516106 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516110 */   GIR_RootConstrainSelectedInstOperands,
     /*  516111 */   // GIR_Coverage, 12316,
     /*  516111 */   GIR_EraseRootFromParent_Done,
     /*  516112 */ // Label 7843: @516112
     /*  516112 */ GIM_Try, /*On fail goto*//*Label 7844*/ GIMT_Encode4(516172), // Rule ID 12317 //
     /*  516117 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  516120 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516123 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516130 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516134 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516141 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516141 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516149 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516151 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516170 */   GIR_RootConstrainSelectedInstOperands,
     /*  516171 */   // GIR_Coverage, 12317,
     /*  516171 */   GIR_EraseRootFromParent_Done,
     /*  516172 */ // Label 7844: @516172
     /*  516172 */ GIM_Try, /*On fail goto*//*Label 7845*/ GIMT_Encode4(516232), // Rule ID 12333 //
     /*  516177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  516180 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516183 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516190 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516194 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516201 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516209 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516216 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516226 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516230 */   GIR_RootConstrainSelectedInstOperands,
     /*  516231 */   // GIR_Coverage, 12333,
     /*  516231 */   GIR_EraseRootFromParent_Done,
     /*  516232 */ // Label 7845: @516232
     /*  516232 */ GIM_Try, /*On fail goto*//*Label 7846*/ GIMT_Encode4(516292), // Rule ID 12334 //
     /*  516237 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  516240 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516243 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516250 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516254 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516261 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516269 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516271 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516276 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516286 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516290 */   GIR_RootConstrainSelectedInstOperands,
     /*  516291 */   // GIR_Coverage, 12334,
     /*  516291 */   GIR_EraseRootFromParent_Done,
     /*  516292 */ // Label 7846: @516292
     /*  516292 */ GIM_Try, /*On fail goto*//*Label 7847*/ GIMT_Encode4(516352), // Rule ID 12335 //
     /*  516297 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  516300 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516303 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516310 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516314 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516321 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516321 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516329 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516346 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516350 */   GIR_RootConstrainSelectedInstOperands,
     /*  516351 */   // GIR_Coverage, 12335,
     /*  516351 */   GIR_EraseRootFromParent_Done,
     /*  516352 */ // Label 7847: @516352
     /*  516352 */ GIM_Try, /*On fail goto*//*Label 7848*/ GIMT_Encode4(516412), // Rule ID 12336 //
     /*  516357 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  516360 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516363 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516370 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516374 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516381 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516389 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516406 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516410 */   GIR_RootConstrainSelectedInstOperands,
     /*  516411 */   // GIR_Coverage, 12336,
     /*  516411 */   GIR_EraseRootFromParent_Done,
     /*  516412 */ // Label 7848: @516412
     /*  516412 */ GIM_Try, /*On fail goto*//*Label 7849*/ GIMT_Encode4(516472), // Rule ID 12337 //
     /*  516417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  516420 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516423 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516430 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516434 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  516441 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  516441 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  516444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  516449 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516451 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  516456 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  516461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  516466 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516470 */   GIR_RootConstrainSelectedInstOperands,
     /*  516471 */   // GIR_Coverage, 12337,
     /*  516471 */   GIR_EraseRootFromParent_Done,
     /*  516472 */ // Label 7849: @516472
     /*  516472 */ GIM_Try, /*On fail goto*//*Label 7850*/ GIMT_Encode4(516532), // Rule ID 12872 //
     /*  516477 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  516480 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  516483 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  516490 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516497 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516501 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516508 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516516 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516518 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516523 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516526 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516530 */   GIR_RootConstrainSelectedInstOperands,
     /*  516531 */   // GIR_Coverage, 12872,
     /*  516531 */   GIR_EraseRootFromParent_Done,
     /*  516532 */ // Label 7850: @516532
     /*  516532 */ GIM_Try, /*On fail goto*//*Label 7851*/ GIMT_Encode4(516592), // Rule ID 12873 //
     /*  516537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  516540 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  516543 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  516550 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516557 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516561 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516568 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516576 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516578 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516583 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516586 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516590 */   GIR_RootConstrainSelectedInstOperands,
     /*  516591 */   // GIR_Coverage, 12873,
     /*  516591 */   GIR_EraseRootFromParent_Done,
     /*  516592 */ // Label 7851: @516592
     /*  516592 */ GIM_Try, /*On fail goto*//*Label 7852*/ GIMT_Encode4(516652), // Rule ID 12874 //
     /*  516597 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  516600 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  516603 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  516610 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516617 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516621 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516628 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516628 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516631 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516636 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516638 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516643 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516646 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516650 */   GIR_RootConstrainSelectedInstOperands,
     /*  516651 */   // GIR_Coverage, 12874,
     /*  516651 */   GIR_EraseRootFromParent_Done,
     /*  516652 */ // Label 7852: @516652
     /*  516652 */ GIM_Try, /*On fail goto*//*Label 7853*/ GIMT_Encode4(516712), // Rule ID 12875 //
     /*  516657 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  516660 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  516663 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  516670 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516677 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516681 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516688 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516688 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516696 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516703 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516706 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516710 */   GIR_RootConstrainSelectedInstOperands,
     /*  516711 */   // GIR_Coverage, 12875,
     /*  516711 */   GIR_EraseRootFromParent_Done,
     /*  516712 */ // Label 7853: @516712
     /*  516712 */ GIM_Try, /*On fail goto*//*Label 7854*/ GIMT_Encode4(516772), // Rule ID 12876 //
     /*  516717 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  516720 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  516723 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  516730 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516737 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516741 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516748 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516748 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516756 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516763 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516766 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516770 */   GIR_RootConstrainSelectedInstOperands,
     /*  516771 */   // GIR_Coverage, 12876,
     /*  516771 */   GIR_EraseRootFromParent_Done,
     /*  516772 */ // Label 7854: @516772
     /*  516772 */ GIM_Try, /*On fail goto*//*Label 7855*/ GIMT_Encode4(516825), // Rule ID 12308 //
     /*  516777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  516780 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516783 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516790 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516801 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516809 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516816 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516819 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516823 */   GIR_RootConstrainSelectedInstOperands,
     /*  516824 */   // GIR_Coverage, 12308,
     /*  516824 */   GIR_EraseRootFromParent_Done,
     /*  516825 */ // Label 7855: @516825
     /*  516825 */ GIM_Try, /*On fail goto*//*Label 7856*/ GIMT_Encode4(516878), // Rule ID 12309 //
     /*  516830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  516833 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516836 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516847 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516854 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516854 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516862 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516869 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516872 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516876 */   GIR_RootConstrainSelectedInstOperands,
     /*  516877 */   // GIR_Coverage, 12309,
     /*  516877 */   GIR_EraseRootFromParent_Done,
     /*  516878 */ // Label 7856: @516878
     /*  516878 */ GIM_Try, /*On fail goto*//*Label 7857*/ GIMT_Encode4(516931), // Rule ID 12310 //
     /*  516883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  516886 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516889 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516896 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516907 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516915 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516922 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516929 */   GIR_RootConstrainSelectedInstOperands,
     /*  516930 */   // GIR_Coverage, 12310,
     /*  516930 */   GIR_EraseRootFromParent_Done,
     /*  516931 */ // Label 7857: @516931
     /*  516931 */ GIM_Try, /*On fail goto*//*Label 7858*/ GIMT_Encode4(516984), // Rule ID 12311 //
     /*  516936 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  516939 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516942 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  516949 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  516953 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  516960 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  516960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  516963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  516968 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  516970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  516975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  516978 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  516982 */   GIR_RootConstrainSelectedInstOperands,
     /*  516983 */   // GIR_Coverage, 12311,
     /*  516983 */   GIR_EraseRootFromParent_Done,
     /*  516984 */ // Label 7858: @516984
     /*  516984 */ GIM_Try, /*On fail goto*//*Label 7859*/ GIMT_Encode4(517037), // Rule ID 12312 //
     /*  516989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  516992 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  516995 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  517002 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517006 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  517013 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  517013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  517016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  517021 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  517028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  517031 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517035 */   GIR_RootConstrainSelectedInstOperands,
     /*  517036 */   // GIR_Coverage, 12312,
     /*  517036 */   GIR_EraseRootFromParent_Done,
     /*  517037 */ // Label 7859: @517037
     /*  517037 */ GIM_Try, /*On fail goto*//*Label 7860*/ GIMT_Encode4(517090), // Rule ID 12328 //
     /*  517042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  517045 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517048 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  517055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517059 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  517066 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  517066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  517069 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  517074 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  517081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  517084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517088 */   GIR_RootConstrainSelectedInstOperands,
     /*  517089 */   // GIR_Coverage, 12328,
     /*  517089 */   GIR_EraseRootFromParent_Done,
     /*  517090 */ // Label 7860: @517090
     /*  517090 */ GIM_Try, /*On fail goto*//*Label 7861*/ GIMT_Encode4(517143), // Rule ID 12329 //
     /*  517095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  517098 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517101 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  517108 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517112 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  517119 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  517119 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  517122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  517127 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  517134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  517137 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517141 */   GIR_RootConstrainSelectedInstOperands,
     /*  517142 */   // GIR_Coverage, 12329,
     /*  517142 */   GIR_EraseRootFromParent_Done,
     /*  517143 */ // Label 7861: @517143
     /*  517143 */ GIM_Try, /*On fail goto*//*Label 7862*/ GIMT_Encode4(517196), // Rule ID 12330 //
     /*  517148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  517151 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517154 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  517161 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517165 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  517172 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  517172 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  517175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  517180 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  517187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  517190 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517194 */   GIR_RootConstrainSelectedInstOperands,
     /*  517195 */   // GIR_Coverage, 12330,
     /*  517195 */   GIR_EraseRootFromParent_Done,
     /*  517196 */ // Label 7862: @517196
     /*  517196 */ GIM_Try, /*On fail goto*//*Label 7863*/ GIMT_Encode4(517249), // Rule ID 12331 //
     /*  517201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  517204 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517207 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  517214 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517218 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  517225 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  517225 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  517228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  517233 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  517240 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  517243 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517247 */   GIR_RootConstrainSelectedInstOperands,
     /*  517248 */   // GIR_Coverage, 12331,
     /*  517248 */   GIR_EraseRootFromParent_Done,
     /*  517249 */ // Label 7863: @517249
     /*  517249 */ GIM_Try, /*On fail goto*//*Label 7864*/ GIMT_Encode4(517302), // Rule ID 12332 //
     /*  517254 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  517257 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517260 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  517267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  517278 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  517278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  517281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  517286 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  517293 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  517296 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517300 */   GIR_RootConstrainSelectedInstOperands,
     /*  517301 */   // GIR_Coverage, 12332,
     /*  517301 */   GIR_EraseRootFromParent_Done,
     /*  517302 */ // Label 7864: @517302
     /*  517302 */ GIM_Try, /*On fail goto*//*Label 7865*/ GIMT_Encode4(517368), // Rule ID 10451 //
     /*  517307 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  517310 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  517313 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  517320 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517326 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517330 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517337 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517337 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517345 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517347 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517352 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517362 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517366 */   GIR_RootConstrainSelectedInstOperands,
     /*  517367 */   // GIR_Coverage, 10451,
     /*  517367 */   GIR_EraseRootFromParent_Done,
     /*  517368 */ // Label 7865: @517368
     /*  517368 */ GIM_Try, /*On fail goto*//*Label 7866*/ GIMT_Encode4(517434), // Rule ID 10452 //
     /*  517373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  517376 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  517379 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  517386 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517392 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517396 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517403 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517403 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517411 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517428 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517432 */   GIR_RootConstrainSelectedInstOperands,
     /*  517433 */   // GIR_Coverage, 10452,
     /*  517433 */   GIR_EraseRootFromParent_Done,
     /*  517434 */ // Label 7866: @517434
     /*  517434 */ GIM_Try, /*On fail goto*//*Label 7867*/ GIMT_Encode4(517500), // Rule ID 10453 //
     /*  517439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  517442 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  517445 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  517452 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517469 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517477 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517494 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517498 */   GIR_RootConstrainSelectedInstOperands,
     /*  517499 */   // GIR_Coverage, 10453,
     /*  517499 */   GIR_EraseRootFromParent_Done,
     /*  517500 */ // Label 7867: @517500
     /*  517500 */ GIM_Try, /*On fail goto*//*Label 7868*/ GIMT_Encode4(517566), // Rule ID 10454 //
     /*  517505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  517508 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  517511 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  517518 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517524 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517528 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517535 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517538 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517543 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517560 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517564 */   GIR_RootConstrainSelectedInstOperands,
     /*  517565 */   // GIR_Coverage, 10454,
     /*  517565 */   GIR_EraseRootFromParent_Done,
     /*  517566 */ // Label 7868: @517566
     /*  517566 */ GIM_Try, /*On fail goto*//*Label 7869*/ GIMT_Encode4(517632), // Rule ID 10455 //
     /*  517571 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  517574 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  517577 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  517584 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517590 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517594 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517601 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517604 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517609 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517621 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517626 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517630 */   GIR_RootConstrainSelectedInstOperands,
     /*  517631 */   // GIR_Coverage, 10455,
     /*  517631 */   GIR_EraseRootFromParent_Done,
     /*  517632 */ // Label 7869: @517632
     /*  517632 */ GIM_Try, /*On fail goto*//*Label 7870*/ GIMT_Encode4(517691), // Rule ID 10161 //
     /*  517637 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  517640 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517643 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517653 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517660 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517663 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517668 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517689 */   GIR_RootConstrainSelectedInstOperands,
     /*  517690 */   // GIR_Coverage, 10161,
     /*  517690 */   GIR_EraseRootFromParent_Done,
     /*  517691 */ // Label 7870: @517691
     /*  517691 */ GIM_Try, /*On fail goto*//*Label 7871*/ GIMT_Encode4(517750), // Rule ID 10162 //
     /*  517696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  517699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517702 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517708 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517712 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517719 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517727 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517729 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517744 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517748 */   GIR_RootConstrainSelectedInstOperands,
     /*  517749 */   // GIR_Coverage, 10162,
     /*  517749 */   GIR_EraseRootFromParent_Done,
     /*  517750 */ // Label 7871: @517750
     /*  517750 */ GIM_Try, /*On fail goto*//*Label 7872*/ GIMT_Encode4(517809), // Rule ID 10163 //
     /*  517755 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  517758 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517761 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517778 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517786 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517798 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517803 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517807 */   GIR_RootConstrainSelectedInstOperands,
     /*  517808 */   // GIR_Coverage, 10163,
     /*  517808 */   GIR_EraseRootFromParent_Done,
     /*  517809 */ // Label 7872: @517809
     /*  517809 */ GIM_Try, /*On fail goto*//*Label 7873*/ GIMT_Encode4(517868), // Rule ID 10164 //
     /*  517814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  517817 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517820 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517826 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517830 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517837 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517845 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517852 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517857 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517862 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517866 */   GIR_RootConstrainSelectedInstOperands,
     /*  517867 */   // GIR_Coverage, 10164,
     /*  517867 */   GIR_EraseRootFromParent_Done,
     /*  517868 */ // Label 7873: @517868
     /*  517868 */ GIM_Try, /*On fail goto*//*Label 7874*/ GIMT_Encode4(517927), // Rule ID 10165 //
     /*  517873 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  517876 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517879 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517885 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517889 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517896 */   // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517904 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517906 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517911 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517916 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517925 */   GIR_RootConstrainSelectedInstOperands,
     /*  517926 */   // GIR_Coverage, 10165,
     /*  517926 */   GIR_EraseRootFromParent_Done,
     /*  517927 */ // Label 7874: @517927
     /*  517927 */ GIM_Try, /*On fail goto*//*Label 7875*/ GIMT_Encode4(517986), // Rule ID 10181 //
     /*  517932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  517935 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  517944 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  517948 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  517955 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  517955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  517958 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  517963 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  517965 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  517970 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  517975 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  517980 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  517984 */   GIR_RootConstrainSelectedInstOperands,
     /*  517985 */   // GIR_Coverage, 10181,
     /*  517985 */   GIR_EraseRootFromParent_Done,
     /*  517986 */ // Label 7875: @517986
     /*  517986 */ GIM_Try, /*On fail goto*//*Label 7876*/ GIMT_Encode4(518045), // Rule ID 10182 //
     /*  517991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  517994 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  517997 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518003 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518007 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  518014 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  518014 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  518017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  518022 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  518029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  518034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  518039 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518043 */   GIR_RootConstrainSelectedInstOperands,
     /*  518044 */   // GIR_Coverage, 10182,
     /*  518044 */   GIR_EraseRootFromParent_Done,
     /*  518045 */ // Label 7876: @518045
     /*  518045 */ GIM_Try, /*On fail goto*//*Label 7877*/ GIMT_Encode4(518104), // Rule ID 10183 //
     /*  518050 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  518053 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518056 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518062 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518066 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  518073 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  518073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  518076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  518081 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518083 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  518088 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  518093 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  518098 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518102 */   GIR_RootConstrainSelectedInstOperands,
     /*  518103 */   // GIR_Coverage, 10183,
     /*  518103 */   GIR_EraseRootFromParent_Done,
     /*  518104 */ // Label 7877: @518104
     /*  518104 */ GIM_Try, /*On fail goto*//*Label 7878*/ GIMT_Encode4(518163), // Rule ID 10184 //
     /*  518109 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  518112 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518115 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518121 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  518132 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  518132 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  518135 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  518140 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  518147 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  518152 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  518157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518161 */   GIR_RootConstrainSelectedInstOperands,
     /*  518162 */   // GIR_Coverage, 10184,
     /*  518162 */   GIR_EraseRootFromParent_Done,
     /*  518163 */ // Label 7878: @518163
     /*  518163 */ GIM_Try, /*On fail goto*//*Label 7879*/ GIMT_Encode4(518222), // Rule ID 10185 //
     /*  518168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  518171 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518174 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  518191 */   // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  518191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  518194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  518199 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  518206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  518211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  518216 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518220 */   GIR_RootConstrainSelectedInstOperands,
     /*  518221 */   // GIR_Coverage, 10185,
     /*  518221 */   GIR_EraseRootFromParent_Done,
     /*  518222 */ // Label 7879: @518222
     /*  518222 */ GIM_Try, /*On fail goto*//*Label 7880*/ GIMT_Encode4(518281), // Rule ID 10446 //
     /*  518227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  518230 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  518233 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  518240 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518246 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518250 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518257 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518260 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518265 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518267 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518272 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518275 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518279 */   GIR_RootConstrainSelectedInstOperands,
     /*  518280 */   // GIR_Coverage, 10446,
     /*  518280 */   GIR_EraseRootFromParent_Done,
     /*  518281 */ // Label 7880: @518281
     /*  518281 */ GIM_Try, /*On fail goto*//*Label 7881*/ GIMT_Encode4(518340), // Rule ID 10447 //
     /*  518286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  518289 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  518292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  518299 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518305 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518309 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518316 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518319 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518324 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518326 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518331 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518334 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518338 */   GIR_RootConstrainSelectedInstOperands,
     /*  518339 */   // GIR_Coverage, 10447,
     /*  518339 */   GIR_EraseRootFromParent_Done,
     /*  518340 */ // Label 7881: @518340
     /*  518340 */ GIM_Try, /*On fail goto*//*Label 7882*/ GIMT_Encode4(518399), // Rule ID 10448 //
     /*  518345 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  518348 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  518351 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  518358 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518364 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518368 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518375 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518375 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518383 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518390 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518397 */   GIR_RootConstrainSelectedInstOperands,
     /*  518398 */   // GIR_Coverage, 10448,
     /*  518398 */   GIR_EraseRootFromParent_Done,
     /*  518399 */ // Label 7882: @518399
     /*  518399 */ GIM_Try, /*On fail goto*//*Label 7883*/ GIMT_Encode4(518458), // Rule ID 10449 //
     /*  518404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  518407 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  518410 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  518417 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518423 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518427 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518434 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518437 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518442 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518449 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518452 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518456 */   GIR_RootConstrainSelectedInstOperands,
     /*  518457 */   // GIR_Coverage, 10449,
     /*  518457 */   GIR_EraseRootFromParent_Done,
     /*  518458 */ // Label 7883: @518458
     /*  518458 */ GIM_Try, /*On fail goto*//*Label 7884*/ GIMT_Encode4(518517), // Rule ID 10450 //
     /*  518463 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  518466 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  518469 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /*  518476 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518482 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518486 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518493 */   // (atomic_store v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518493 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518496 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518501 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518503 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518508 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518511 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518515 */   GIR_RootConstrainSelectedInstOperands,
     /*  518516 */   // GIR_Coverage, 10450,
     /*  518516 */   GIR_EraseRootFromParent_Done,
     /*  518517 */ // Label 7884: @518517
     /*  518517 */ GIM_Try, /*On fail goto*//*Label 7885*/ GIMT_Encode4(518569), // Rule ID 10156 //
     /*  518522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  518525 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518528 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518534 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518538 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518545 */   // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518553 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518555 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518560 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518563 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518567 */   GIR_RootConstrainSelectedInstOperands,
     /*  518568 */   // GIR_Coverage, 10156,
     /*  518568 */   GIR_EraseRootFromParent_Done,
     /*  518569 */ // Label 7885: @518569
     /*  518569 */ GIM_Try, /*On fail goto*//*Label 7886*/ GIMT_Encode4(518621), // Rule ID 10157 //
     /*  518574 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  518577 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518580 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518586 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518590 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518597 */   // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518600 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518605 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518612 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518615 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518619 */   GIR_RootConstrainSelectedInstOperands,
     /*  518620 */   // GIR_Coverage, 10157,
     /*  518620 */   GIR_EraseRootFromParent_Done,
     /*  518621 */ // Label 7886: @518621
     /*  518621 */ GIM_Try, /*On fail goto*//*Label 7887*/ GIMT_Encode4(518673), // Rule ID 10158 //
     /*  518626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  518629 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518632 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518638 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518642 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518649 */   // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518649 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518657 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518664 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518667 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518671 */   GIR_RootConstrainSelectedInstOperands,
     /*  518672 */   // GIR_Coverage, 10158,
     /*  518672 */   GIR_EraseRootFromParent_Done,
     /*  518673 */ // Label 7887: @518673
     /*  518673 */ GIM_Try, /*On fail goto*//*Label 7888*/ GIMT_Encode4(518725), // Rule ID 10159 //
     /*  518678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  518681 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518684 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518690 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518694 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518701 */   // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518709 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518711 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518716 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518719 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518723 */   GIR_RootConstrainSelectedInstOperands,
     /*  518724 */   // GIR_Coverage, 10159,
     /*  518724 */   GIR_EraseRootFromParent_Done,
     /*  518725 */ // Label 7888: @518725
     /*  518725 */ GIM_Try, /*On fail goto*//*Label 7889*/ GIMT_Encode4(518777), // Rule ID 10160 //
     /*  518730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  518733 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518736 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518742 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518746 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518753 */   // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518761 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518768 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518771 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518775 */   GIR_RootConstrainSelectedInstOperands,
     /*  518776 */   // GIR_Coverage, 10160,
     /*  518776 */   GIR_EraseRootFromParent_Done,
     /*  518777 */ // Label 7889: @518777
     /*  518777 */ GIM_Try, /*On fail goto*//*Label 7890*/ GIMT_Encode4(518829), // Rule ID 10176 //
     /*  518782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  518785 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518788 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518794 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518798 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518805 */   // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518813 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518815 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518820 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518823 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518827 */   GIR_RootConstrainSelectedInstOperands,
     /*  518828 */   // GIR_Coverage, 10176,
     /*  518828 */   GIR_EraseRootFromParent_Done,
     /*  518829 */ // Label 7890: @518829
     /*  518829 */ GIM_Try, /*On fail goto*//*Label 7891*/ GIMT_Encode4(518881), // Rule ID 10177 //
     /*  518834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  518837 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518840 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518846 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518850 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518857 */   // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518857 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518865 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518872 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518875 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518879 */   GIR_RootConstrainSelectedInstOperands,
     /*  518880 */   // GIR_Coverage, 10177,
     /*  518880 */   GIR_EraseRootFromParent_Done,
     /*  518881 */ // Label 7891: @518881
     /*  518881 */ GIM_Try, /*On fail goto*//*Label 7892*/ GIMT_Encode4(518933), // Rule ID 10178 //
     /*  518886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  518889 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518892 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518898 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518902 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518909 */   // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518909 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518917 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518924 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518927 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518931 */   GIR_RootConstrainSelectedInstOperands,
     /*  518932 */   // GIR_Coverage, 10178,
     /*  518932 */   GIR_EraseRootFromParent_Done,
     /*  518933 */ // Label 7892: @518933
     /*  518933 */ GIM_Try, /*On fail goto*//*Label 7893*/ GIMT_Encode4(518985), // Rule ID 10179 //
     /*  518938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  518941 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518944 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  518950 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  518954 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  518961 */   // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  518961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  518964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  518969 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  518971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  518976 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  518979 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  518983 */   GIR_RootConstrainSelectedInstOperands,
     /*  518984 */   // GIR_Coverage, 10179,
     /*  518984 */   GIR_EraseRootFromParent_Done,
     /*  518985 */ // Label 7893: @518985
     /*  518985 */ GIM_Try, /*On fail goto*//*Label 7894*/ GIMT_Encode4(519037), // Rule ID 10180 //
     /*  518990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  518993 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  518996 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  519002 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519006 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  519013 */   // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  519013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  519016 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  519021 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  519023 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519028 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519031 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519035 */   GIR_RootConstrainSelectedInstOperands,
     /*  519036 */   // GIR_Coverage, 10180,
     /*  519036 */   GIR_EraseRootFromParent_Done,
     /*  519037 */ // Label 7894: @519037
     /*  519037 */ GIM_Reject,
     /*  519038 */ // Label 5870: @519038
     /*  519038 */ GIM_Try, /*On fail goto*//*Label 7895*/ GIMT_Encode4(529657),
     /*  519043 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  519046 */   GIM_Try, /*On fail goto*//*Label 7896*/ GIMT_Encode4(519102), // Rule ID 29873 //
     /*  519051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  519054 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519058 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519063 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519078 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519086 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519100 */     GIR_RootConstrainSelectedInstOperands,
     /*  519101 */     // GIR_Coverage, 29873,
     /*  519101 */     GIR_EraseRootFromParent_Done,
     /*  519102 */   // Label 7896: @519102
     /*  519102 */   GIM_Try, /*On fail goto*//*Label 7897*/ GIMT_Encode4(519158), // Rule ID 29874 //
     /*  519107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  519110 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519119 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519127 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519134 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519142 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519156 */     GIR_RootConstrainSelectedInstOperands,
     /*  519157 */     // GIR_Coverage, 29874,
     /*  519157 */     GIR_EraseRootFromParent_Done,
     /*  519158 */   // Label 7897: @519158
     /*  519158 */   GIM_Try, /*On fail goto*//*Label 7898*/ GIMT_Encode4(519214), // Rule ID 29875 //
     /*  519163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  519166 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519175 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519190 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519198 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519212 */     GIR_RootConstrainSelectedInstOperands,
     /*  519213 */     // GIR_Coverage, 29875,
     /*  519213 */     GIR_EraseRootFromParent_Done,
     /*  519214 */   // Label 7898: @519214
     /*  519214 */   GIM_Try, /*On fail goto*//*Label 7899*/ GIMT_Encode4(519270), // Rule ID 29876 //
     /*  519219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  519222 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519231 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519235 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519239 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519246 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519254 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519268 */     GIR_RootConstrainSelectedInstOperands,
     /*  519269 */     // GIR_Coverage, 29876,
     /*  519269 */     GIR_EraseRootFromParent_Done,
     /*  519270 */   // Label 7899: @519270
     /*  519270 */   GIM_Try, /*On fail goto*//*Label 7900*/ GIMT_Encode4(519326), // Rule ID 29877 //
     /*  519275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  519278 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519287 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519302 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519310 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519324 */     GIR_RootConstrainSelectedInstOperands,
     /*  519325 */     // GIR_Coverage, 29877,
     /*  519325 */     GIR_EraseRootFromParent_Done,
     /*  519326 */   // Label 7900: @519326
     /*  519326 */   GIM_Try, /*On fail goto*//*Label 7901*/ GIMT_Encode4(519382), // Rule ID 29893 //
     /*  519331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  519334 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519343 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519358 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519366 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519380 */     GIR_RootConstrainSelectedInstOperands,
     /*  519381 */     // GIR_Coverage, 29893,
     /*  519381 */     GIR_EraseRootFromParent_Done,
     /*  519382 */   // Label 7901: @519382
     /*  519382 */   GIM_Try, /*On fail goto*//*Label 7902*/ GIMT_Encode4(519438), // Rule ID 29894 //
     /*  519387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  519390 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519399 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519414 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519422 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519436 */     GIR_RootConstrainSelectedInstOperands,
     /*  519437 */     // GIR_Coverage, 29894,
     /*  519437 */     GIR_EraseRootFromParent_Done,
     /*  519438 */   // Label 7902: @519438
     /*  519438 */   GIM_Try, /*On fail goto*//*Label 7903*/ GIMT_Encode4(519494), // Rule ID 29895 //
     /*  519443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  519446 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519455 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519459 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519470 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519478 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519492 */     GIR_RootConstrainSelectedInstOperands,
     /*  519493 */     // GIR_Coverage, 29895,
     /*  519493 */     GIR_EraseRootFromParent_Done,
     /*  519494 */   // Label 7903: @519494
     /*  519494 */   GIM_Try, /*On fail goto*//*Label 7904*/ GIMT_Encode4(519550), // Rule ID 29896 //
     /*  519499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  519502 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519506 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519511 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519515 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519519 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519526 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519534 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519548 */     GIR_RootConstrainSelectedInstOperands,
     /*  519549 */     // GIR_Coverage, 29896,
     /*  519549 */     GIR_EraseRootFromParent_Done,
     /*  519550 */   // Label 7904: @519550
     /*  519550 */   GIM_Try, /*On fail goto*//*Label 7905*/ GIMT_Encode4(519606), // Rule ID 29897 //
     /*  519555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  519558 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519567 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  519571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519582 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519590 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519604 */     GIR_RootConstrainSelectedInstOperands,
     /*  519605 */     // GIR_Coverage, 29897,
     /*  519605 */     GIR_EraseRootFromParent_Done,
     /*  519606 */   // Label 7905: @519606
     /*  519606 */   GIM_Try, /*On fail goto*//*Label 7906*/ GIMT_Encode4(519667), // Rule ID 30213 //
     /*  519611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  519614 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519623 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519632 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  519636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519643 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519651 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519665 */     GIR_RootConstrainSelectedInstOperands,
     /*  519666 */     // GIR_Coverage, 30213,
     /*  519666 */     GIR_EraseRootFromParent_Done,
     /*  519667 */   // Label 7906: @519667
     /*  519667 */   GIM_Try, /*On fail goto*//*Label 7907*/ GIMT_Encode4(519728), // Rule ID 30214 //
     /*  519672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  519675 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519679 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519693 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  519697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519704 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519712 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519726 */     GIR_RootConstrainSelectedInstOperands,
     /*  519727 */     // GIR_Coverage, 30214,
     /*  519727 */     GIR_EraseRootFromParent_Done,
     /*  519728 */   // Label 7907: @519728
     /*  519728 */   GIM_Try, /*On fail goto*//*Label 7908*/ GIMT_Encode4(519789), // Rule ID 30215 //
     /*  519733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  519736 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519745 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519754 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  519758 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519765 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519773 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519787 */     GIR_RootConstrainSelectedInstOperands,
     /*  519788 */     // GIR_Coverage, 30215,
     /*  519788 */     GIR_EraseRootFromParent_Done,
     /*  519789 */   // Label 7908: @519789
     /*  519789 */   GIM_Try, /*On fail goto*//*Label 7909*/ GIMT_Encode4(519850), // Rule ID 30216 //
     /*  519794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  519797 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519801 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519815 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  519819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519826 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519834 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519848 */     GIR_RootConstrainSelectedInstOperands,
     /*  519849 */     // GIR_Coverage, 30216,
     /*  519849 */     GIR_EraseRootFromParent_Done,
     /*  519850 */   // Label 7909: @519850
     /*  519850 */   GIM_Try, /*On fail goto*//*Label 7910*/ GIMT_Encode4(519911), // Rule ID 30217 //
     /*  519855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  519858 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519862 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519867 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519876 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  519880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519887 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519895 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519909 */     GIR_RootConstrainSelectedInstOperands,
     /*  519910 */     // GIR_Coverage, 30217,
     /*  519910 */     GIR_EraseRootFromParent_Done,
     /*  519911 */   // Label 7910: @519911
     /*  519911 */   GIM_Try, /*On fail goto*//*Label 7911*/ GIMT_Encode4(519972), // Rule ID 30233 //
     /*  519916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  519919 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519923 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519937 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  519941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  519948 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  519948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  519951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  519956 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  519958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  519963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  519966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  519970 */     GIR_RootConstrainSelectedInstOperands,
     /*  519971 */     // GIR_Coverage, 30233,
     /*  519971 */     GIR_EraseRootFromParent_Done,
     /*  519972 */   // Label 7911: @519972
     /*  519972 */   GIM_Try, /*On fail goto*//*Label 7912*/ GIMT_Encode4(520033), // Rule ID 30234 //
     /*  519977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  519980 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  519984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519989 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  519994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  519998 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  520002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520009 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  520012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520017 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520031 */     GIR_RootConstrainSelectedInstOperands,
     /*  520032 */     // GIR_Coverage, 30234,
     /*  520032 */     GIR_EraseRootFromParent_Done,
     /*  520033 */   // Label 7912: @520033
     /*  520033 */   GIM_Try, /*On fail goto*//*Label 7913*/ GIMT_Encode4(520094), // Rule ID 30235 //
     /*  520038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  520041 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  520045 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520059 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  520063 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520070 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  520073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520078 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520088 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520092 */     GIR_RootConstrainSelectedInstOperands,
     /*  520093 */     // GIR_Coverage, 30235,
     /*  520093 */     GIR_EraseRootFromParent_Done,
     /*  520094 */   // Label 7913: @520094
     /*  520094 */   GIM_Try, /*On fail goto*//*Label 7914*/ GIMT_Encode4(520155), // Rule ID 30236 //
     /*  520099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  520102 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  520106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520111 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520120 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  520124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520131 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  520134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520139 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520153 */     GIR_RootConstrainSelectedInstOperands,
     /*  520154 */     // GIR_Coverage, 30236,
     /*  520154 */     GIR_EraseRootFromParent_Done,
     /*  520155 */   // Label 7914: @520155
     /*  520155 */   GIM_Try, /*On fail goto*//*Label 7915*/ GIMT_Encode4(520216), // Rule ID 30237 //
     /*  520160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  520163 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  520167 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520181 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  520185 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520192 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  520195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520200 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520214 */     GIR_RootConstrainSelectedInstOperands,
     /*  520215 */     // GIR_Coverage, 30237,
     /*  520215 */     GIR_EraseRootFromParent_Done,
     /*  520216 */   // Label 7915: @520216
     /*  520216 */   GIM_Try, /*On fail goto*//*Label 7916*/ GIMT_Encode4(520268), // Rule ID 29878 //
     /*  520221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  520224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520229 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520244 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520252 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520266 */     GIR_RootConstrainSelectedInstOperands,
     /*  520267 */     // GIR_Coverage, 29878,
     /*  520267 */     GIR_EraseRootFromParent_Done,
     /*  520268 */   // Label 7916: @520268
     /*  520268 */   GIM_Try, /*On fail goto*//*Label 7917*/ GIMT_Encode4(520320), // Rule ID 29879 //
     /*  520273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  520276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520281 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520296 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520304 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520318 */     GIR_RootConstrainSelectedInstOperands,
     /*  520319 */     // GIR_Coverage, 29879,
     /*  520319 */     GIR_EraseRootFromParent_Done,
     /*  520320 */   // Label 7917: @520320
     /*  520320 */   GIM_Try, /*On fail goto*//*Label 7918*/ GIMT_Encode4(520372), // Rule ID 29880 //
     /*  520325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  520328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520333 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520348 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520356 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520370 */     GIR_RootConstrainSelectedInstOperands,
     /*  520371 */     // GIR_Coverage, 29880,
     /*  520371 */     GIR_EraseRootFromParent_Done,
     /*  520372 */   // Label 7918: @520372
     /*  520372 */   GIM_Try, /*On fail goto*//*Label 7919*/ GIMT_Encode4(520424), // Rule ID 29881 //
     /*  520377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  520380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520385 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520400 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520408 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520422 */     GIR_RootConstrainSelectedInstOperands,
     /*  520423 */     // GIR_Coverage, 29881,
     /*  520423 */     GIR_EraseRootFromParent_Done,
     /*  520424 */   // Label 7919: @520424
     /*  520424 */   GIM_Try, /*On fail goto*//*Label 7920*/ GIMT_Encode4(520476), // Rule ID 29882 //
     /*  520429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  520432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520437 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520452 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520460 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520474 */     GIR_RootConstrainSelectedInstOperands,
     /*  520475 */     // GIR_Coverage, 29882,
     /*  520475 */     GIR_EraseRootFromParent_Done,
     /*  520476 */   // Label 7920: @520476
     /*  520476 */   GIM_Try, /*On fail goto*//*Label 7921*/ GIMT_Encode4(520528), // Rule ID 29898 //
     /*  520481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  520484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520489 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520504 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520512 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520526 */     GIR_RootConstrainSelectedInstOperands,
     /*  520527 */     // GIR_Coverage, 29898,
     /*  520527 */     GIR_EraseRootFromParent_Done,
     /*  520528 */   // Label 7921: @520528
     /*  520528 */   GIM_Try, /*On fail goto*//*Label 7922*/ GIMT_Encode4(520580), // Rule ID 29899 //
     /*  520533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  520536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520541 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520556 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520564 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520578 */     GIR_RootConstrainSelectedInstOperands,
     /*  520579 */     // GIR_Coverage, 29899,
     /*  520579 */     GIR_EraseRootFromParent_Done,
     /*  520580 */   // Label 7922: @520580
     /*  520580 */   GIM_Try, /*On fail goto*//*Label 7923*/ GIMT_Encode4(520632), // Rule ID 29900 //
     /*  520585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  520588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520593 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520608 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520616 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520630 */     GIR_RootConstrainSelectedInstOperands,
     /*  520631 */     // GIR_Coverage, 29900,
     /*  520631 */     GIR_EraseRootFromParent_Done,
     /*  520632 */   // Label 7923: @520632
     /*  520632 */   GIM_Try, /*On fail goto*//*Label 7924*/ GIMT_Encode4(520684), // Rule ID 29901 //
     /*  520637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  520640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520645 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520649 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520653 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520660 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520668 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520682 */     GIR_RootConstrainSelectedInstOperands,
     /*  520683 */     // GIR_Coverage, 29901,
     /*  520683 */     GIR_EraseRootFromParent_Done,
     /*  520684 */   // Label 7924: @520684
     /*  520684 */   GIM_Try, /*On fail goto*//*Label 7925*/ GIMT_Encode4(520736), // Rule ID 29902 //
     /*  520689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  520692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520697 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  520701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520705 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520712 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520720 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520734 */     GIR_RootConstrainSelectedInstOperands,
     /*  520735 */     // GIR_Coverage, 29902,
     /*  520735 */     GIR_EraseRootFromParent_Done,
     /*  520736 */   // Label 7925: @520736
     /*  520736 */   GIM_Try, /*On fail goto*//*Label 7926*/ GIMT_Encode4(520793), // Rule ID 30218 //
     /*  520741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  520744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520749 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520754 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520758 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  520762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520769 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520777 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520787 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520791 */     GIR_RootConstrainSelectedInstOperands,
     /*  520792 */     // GIR_Coverage, 30218,
     /*  520792 */     GIR_EraseRootFromParent_Done,
     /*  520793 */   // Label 7926: @520793
     /*  520793 */   GIM_Try, /*On fail goto*//*Label 7927*/ GIMT_Encode4(520850), // Rule ID 30219 //
     /*  520798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  520801 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520815 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  520819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520826 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520834 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520848 */     GIR_RootConstrainSelectedInstOperands,
     /*  520849 */     // GIR_Coverage, 30219,
     /*  520849 */     GIR_EraseRootFromParent_Done,
     /*  520850 */   // Label 7927: @520850
     /*  520850 */   GIM_Try, /*On fail goto*//*Label 7928*/ GIMT_Encode4(520907), // Rule ID 30220 //
     /*  520855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  520858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520863 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520872 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  520876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520883 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520891 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520905 */     GIR_RootConstrainSelectedInstOperands,
     /*  520906 */     // GIR_Coverage, 30220,
     /*  520906 */     GIR_EraseRootFromParent_Done,
     /*  520907 */   // Label 7928: @520907
     /*  520907 */   GIM_Try, /*On fail goto*//*Label 7929*/ GIMT_Encode4(520964), // Rule ID 30221 //
     /*  520912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  520915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520929 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  520933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520940 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  520943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  520948 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  520950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  520955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  520958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  520962 */     GIR_RootConstrainSelectedInstOperands,
     /*  520963 */     // GIR_Coverage, 30221,
     /*  520963 */     GIR_EraseRootFromParent_Done,
     /*  520964 */   // Label 7929: @520964
     /*  520964 */   GIM_Try, /*On fail goto*//*Label 7930*/ GIMT_Encode4(521021), // Rule ID 30222 //
     /*  520969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  520972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  520982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  520986 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  520990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  520997 */     // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  520997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  521000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  521005 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  521007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521015 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521019 */     GIR_RootConstrainSelectedInstOperands,
     /*  521020 */     // GIR_Coverage, 30222,
     /*  521020 */     GIR_EraseRootFromParent_Done,
     /*  521021 */   // Label 7930: @521021
     /*  521021 */   GIM_Try, /*On fail goto*//*Label 7931*/ GIMT_Encode4(521078), // Rule ID 30238 //
     /*  521026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  521029 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521043 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  521047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  521054 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  521054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  521057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  521062 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  521064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521076 */     GIR_RootConstrainSelectedInstOperands,
     /*  521077 */     // GIR_Coverage, 30238,
     /*  521077 */     GIR_EraseRootFromParent_Done,
     /*  521078 */   // Label 7931: @521078
     /*  521078 */   GIM_Try, /*On fail goto*//*Label 7932*/ GIMT_Encode4(521135), // Rule ID 30239 //
     /*  521083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  521086 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521091 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521096 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521100 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  521104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  521111 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  521111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  521114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  521119 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  521121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521133 */     GIR_RootConstrainSelectedInstOperands,
     /*  521134 */     // GIR_Coverage, 30239,
     /*  521134 */     GIR_EraseRootFromParent_Done,
     /*  521135 */   // Label 7932: @521135
     /*  521135 */   GIM_Try, /*On fail goto*//*Label 7933*/ GIMT_Encode4(521192), // Rule ID 30240 //
     /*  521140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  521143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521157 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  521161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  521168 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  521168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  521171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  521176 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  521178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521190 */     GIR_RootConstrainSelectedInstOperands,
     /*  521191 */     // GIR_Coverage, 30240,
     /*  521191 */     GIR_EraseRootFromParent_Done,
     /*  521192 */   // Label 7933: @521192
     /*  521192 */   GIM_Try, /*On fail goto*//*Label 7934*/ GIMT_Encode4(521249), // Rule ID 30241 //
     /*  521197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  521200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521214 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  521218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  521225 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  521225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  521228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  521233 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  521235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521247 */     GIR_RootConstrainSelectedInstOperands,
     /*  521248 */     // GIR_Coverage, 30241,
     /*  521248 */     GIR_EraseRootFromParent_Done,
     /*  521249 */   // Label 7934: @521249
     /*  521249 */   GIM_Try, /*On fail goto*//*Label 7935*/ GIMT_Encode4(521306), // Rule ID 30242 //
     /*  521254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  521257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  521267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521271 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  521275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  521282 */     // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  521282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  521285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  521290 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  521292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521304 */     GIR_RootConstrainSelectedInstOperands,
     /*  521305 */     // GIR_Coverage, 30242,
     /*  521305 */     GIR_EraseRootFromParent_Done,
     /*  521306 */   // Label 7935: @521306
     /*  521306 */   GIM_Try, /*On fail goto*//*Label 7936*/ GIMT_Encode4(521361), // Rule ID 14662 //
     /*  521311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  521314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521330 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521333 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521355 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521359 */     GIR_RootConstrainSelectedInstOperands,
     /*  521360 */     // GIR_Coverage, 14662,
     /*  521360 */     GIR_EraseRootFromParent_Done,
     /*  521361 */   // Label 7936: @521361
     /*  521361 */   GIM_Try, /*On fail goto*//*Label 7937*/ GIMT_Encode4(521416), // Rule ID 14663 //
     /*  521366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  521369 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521385 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521388 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521414 */     GIR_RootConstrainSelectedInstOperands,
     /*  521415 */     // GIR_Coverage, 14663,
     /*  521415 */     GIR_EraseRootFromParent_Done,
     /*  521416 */   // Label 7937: @521416
     /*  521416 */   GIM_Try, /*On fail goto*//*Label 7938*/ GIMT_Encode4(521471), // Rule ID 14664 //
     /*  521421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  521424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521440 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521443 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521469 */     GIR_RootConstrainSelectedInstOperands,
     /*  521470 */     // GIR_Coverage, 14664,
     /*  521470 */     GIR_EraseRootFromParent_Done,
     /*  521471 */   // Label 7938: @521471
     /*  521471 */   GIM_Try, /*On fail goto*//*Label 7939*/ GIMT_Encode4(521526), // Rule ID 14665 //
     /*  521476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  521479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521495 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521498 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521524 */     GIR_RootConstrainSelectedInstOperands,
     /*  521525 */     // GIR_Coverage, 14665,
     /*  521525 */     GIR_EraseRootFromParent_Done,
     /*  521526 */   // Label 7939: @521526
     /*  521526 */   GIM_Try, /*On fail goto*//*Label 7940*/ GIMT_Encode4(521581), // Rule ID 14666 //
     /*  521531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  521534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521550 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521553 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521579 */     GIR_RootConstrainSelectedInstOperands,
     /*  521580 */     // GIR_Coverage, 14666,
     /*  521580 */     GIR_EraseRootFromParent_Done,
     /*  521581 */   // Label 7940: @521581
     /*  521581 */   GIM_Try, /*On fail goto*//*Label 7941*/ GIMT_Encode4(521636), // Rule ID 14692 //
     /*  521586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  521589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521605 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521608 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521634 */     GIR_RootConstrainSelectedInstOperands,
     /*  521635 */     // GIR_Coverage, 14692,
     /*  521635 */     GIR_EraseRootFromParent_Done,
     /*  521636 */   // Label 7941: @521636
     /*  521636 */   GIM_Try, /*On fail goto*//*Label 7942*/ GIMT_Encode4(521691), // Rule ID 14693 //
     /*  521641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  521644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521649 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521653 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521660 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521663 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521689 */     GIR_RootConstrainSelectedInstOperands,
     /*  521690 */     // GIR_Coverage, 14693,
     /*  521690 */     GIR_EraseRootFromParent_Done,
     /*  521691 */   // Label 7942: @521691
     /*  521691 */   GIM_Try, /*On fail goto*//*Label 7943*/ GIMT_Encode4(521746), // Rule ID 14694 //
     /*  521696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  521699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521715 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521718 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521744 */     GIR_RootConstrainSelectedInstOperands,
     /*  521745 */     // GIR_Coverage, 14694,
     /*  521745 */     GIR_EraseRootFromParent_Done,
     /*  521746 */   // Label 7943: @521746
     /*  521746 */   GIM_Try, /*On fail goto*//*Label 7944*/ GIMT_Encode4(521801), // Rule ID 14695 //
     /*  521751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  521754 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521770 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521773 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521799 */     GIR_RootConstrainSelectedInstOperands,
     /*  521800 */     // GIR_Coverage, 14695,
     /*  521800 */     GIR_EraseRootFromParent_Done,
     /*  521801 */   // Label 7944: @521801
     /*  521801 */   GIM_Try, /*On fail goto*//*Label 7945*/ GIMT_Encode4(521856), // Rule ID 14696 //
     /*  521806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  521809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521814 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521818 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  521825 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  521825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  521828 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  521835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  521840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  521845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  521850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521854 */     GIR_RootConstrainSelectedInstOperands,
     /*  521855 */     // GIR_Coverage, 14696,
     /*  521855 */     GIR_EraseRootFromParent_Done,
     /*  521856 */   // Label 7945: @521856
     /*  521856 */   GIM_Try, /*On fail goto*//*Label 7946*/ GIMT_Encode4(521904), // Rule ID 14657 //
     /*  521861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  521864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  521880 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  521880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  521883 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  521890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521902 */     GIR_RootConstrainSelectedInstOperands,
     /*  521903 */     // GIR_Coverage, 14657,
     /*  521903 */     GIR_EraseRootFromParent_Done,
     /*  521904 */   // Label 7946: @521904
     /*  521904 */   GIM_Try, /*On fail goto*//*Label 7947*/ GIMT_Encode4(521952), // Rule ID 14658 //
     /*  521909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  521912 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  521928 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  521928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  521931 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  521938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521950 */     GIR_RootConstrainSelectedInstOperands,
     /*  521951 */     // GIR_Coverage, 14658,
     /*  521951 */     GIR_EraseRootFromParent_Done,
     /*  521952 */   // Label 7947: @521952
     /*  521952 */   GIM_Try, /*On fail goto*//*Label 7948*/ GIMT_Encode4(522000), // Rule ID 14659 //
     /*  521957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  521960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  521965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  521969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  521976 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  521976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  521979 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  521981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  521986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  521991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  521994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  521998 */     GIR_RootConstrainSelectedInstOperands,
     /*  521999 */     // GIR_Coverage, 14659,
     /*  521999 */     GIR_EraseRootFromParent_Done,
     /*  522000 */   // Label 7948: @522000
     /*  522000 */   GIM_Try, /*On fail goto*//*Label 7949*/ GIMT_Encode4(522048), // Rule ID 14660 //
     /*  522005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  522008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522024 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522027 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522046 */     GIR_RootConstrainSelectedInstOperands,
     /*  522047 */     // GIR_Coverage, 14660,
     /*  522047 */     GIR_EraseRootFromParent_Done,
     /*  522048 */   // Label 7949: @522048
     /*  522048 */   GIM_Try, /*On fail goto*//*Label 7950*/ GIMT_Encode4(522096), // Rule ID 14661 //
     /*  522053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  522056 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522072 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522075 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522094 */     GIR_RootConstrainSelectedInstOperands,
     /*  522095 */     // GIR_Coverage, 14661,
     /*  522095 */     GIR_EraseRootFromParent_Done,
     /*  522096 */   // Label 7950: @522096
     /*  522096 */   GIM_Try, /*On fail goto*//*Label 7951*/ GIMT_Encode4(522144), // Rule ID 14687 //
     /*  522101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  522104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522109 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522120 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522123 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522142 */     GIR_RootConstrainSelectedInstOperands,
     /*  522143 */     // GIR_Coverage, 14687,
     /*  522143 */     GIR_EraseRootFromParent_Done,
     /*  522144 */   // Label 7951: @522144
     /*  522144 */   GIM_Try, /*On fail goto*//*Label 7952*/ GIMT_Encode4(522192), // Rule ID 14688 //
     /*  522149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  522152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522168 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522171 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522190 */     GIR_RootConstrainSelectedInstOperands,
     /*  522191 */     // GIR_Coverage, 14688,
     /*  522191 */     GIR_EraseRootFromParent_Done,
     /*  522192 */   // Label 7952: @522192
     /*  522192 */   GIM_Try, /*On fail goto*//*Label 7953*/ GIMT_Encode4(522240), // Rule ID 14689 //
     /*  522197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  522200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522216 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522219 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522238 */     GIR_RootConstrainSelectedInstOperands,
     /*  522239 */     // GIR_Coverage, 14689,
     /*  522239 */     GIR_EraseRootFromParent_Done,
     /*  522240 */   // Label 7953: @522240
     /*  522240 */   GIM_Try, /*On fail goto*//*Label 7954*/ GIMT_Encode4(522288), // Rule ID 14690 //
     /*  522245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  522248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522264 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522267 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522286 */     GIR_RootConstrainSelectedInstOperands,
     /*  522287 */     // GIR_Coverage, 14690,
     /*  522287 */     GIR_EraseRootFromParent_Done,
     /*  522288 */   // Label 7954: @522288
     /*  522288 */   GIM_Try, /*On fail goto*//*Label 7955*/ GIMT_Encode4(522336), // Rule ID 14691 //
     /*  522293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  522296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  522312 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  522312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  522315 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  522322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522334 */     GIR_RootConstrainSelectedInstOperands,
     /*  522335 */     // GIR_Coverage, 14691,
     /*  522335 */     GIR_EraseRootFromParent_Done,
     /*  522336 */   // Label 7955: @522336
     /*  522336 */   GIM_Try, /*On fail goto*//*Label 7956*/ GIMT_Encode4(522384), // Rule ID 14652 //
     /*  522341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  522344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522360 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522363 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522382 */     GIR_RootConstrainSelectedInstOperands,
     /*  522383 */     // GIR_Coverage, 14652,
     /*  522383 */     GIR_EraseRootFromParent_Done,
     /*  522384 */   // Label 7956: @522384
     /*  522384 */   GIM_Try, /*On fail goto*//*Label 7957*/ GIMT_Encode4(522432), // Rule ID 14653 //
     /*  522389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  522392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522397 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522401 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522408 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522411 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522430 */     GIR_RootConstrainSelectedInstOperands,
     /*  522431 */     // GIR_Coverage, 14653,
     /*  522431 */     GIR_EraseRootFromParent_Done,
     /*  522432 */   // Label 7957: @522432
     /*  522432 */   GIM_Try, /*On fail goto*//*Label 7958*/ GIMT_Encode4(522480), // Rule ID 14654 //
     /*  522437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  522440 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522445 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522456 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522459 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522478 */     GIR_RootConstrainSelectedInstOperands,
     /*  522479 */     // GIR_Coverage, 14654,
     /*  522479 */     GIR_EraseRootFromParent_Done,
     /*  522480 */   // Label 7958: @522480
     /*  522480 */   GIM_Try, /*On fail goto*//*Label 7959*/ GIMT_Encode4(522528), // Rule ID 14655 //
     /*  522485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  522488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522504 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522507 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522526 */     GIR_RootConstrainSelectedInstOperands,
     /*  522527 */     // GIR_Coverage, 14655,
     /*  522527 */     GIR_EraseRootFromParent_Done,
     /*  522528 */   // Label 7959: @522528
     /*  522528 */   GIM_Try, /*On fail goto*//*Label 7960*/ GIMT_Encode4(522576), // Rule ID 14656 //
     /*  522533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  522536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522552 */     // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522555 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522574 */     GIR_RootConstrainSelectedInstOperands,
     /*  522575 */     // GIR_Coverage, 14656,
     /*  522575 */     GIR_EraseRootFromParent_Done,
     /*  522576 */   // Label 7960: @522576
     /*  522576 */   GIM_Try, /*On fail goto*//*Label 7961*/ GIMT_Encode4(522624), // Rule ID 14682 //
     /*  522581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  522584 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522600 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522603 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522622 */     GIR_RootConstrainSelectedInstOperands,
     /*  522623 */     // GIR_Coverage, 14682,
     /*  522623 */     GIR_EraseRootFromParent_Done,
     /*  522624 */   // Label 7961: @522624
     /*  522624 */   GIM_Try, /*On fail goto*//*Label 7962*/ GIMT_Encode4(522672), // Rule ID 14683 //
     /*  522629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  522632 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522648 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522651 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522670 */     GIR_RootConstrainSelectedInstOperands,
     /*  522671 */     // GIR_Coverage, 14683,
     /*  522671 */     GIR_EraseRootFromParent_Done,
     /*  522672 */   // Label 7962: @522672
     /*  522672 */   GIM_Try, /*On fail goto*//*Label 7963*/ GIMT_Encode4(522720), // Rule ID 14684 //
     /*  522677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  522680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522696 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522699 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522718 */     GIR_RootConstrainSelectedInstOperands,
     /*  522719 */     // GIR_Coverage, 14684,
     /*  522719 */     GIR_EraseRootFromParent_Done,
     /*  522720 */   // Label 7963: @522720
     /*  522720 */   GIM_Try, /*On fail goto*//*Label 7964*/ GIMT_Encode4(522768), // Rule ID 14685 //
     /*  522725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  522728 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522744 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522747 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522766 */     GIR_RootConstrainSelectedInstOperands,
     /*  522767 */     // GIR_Coverage, 14685,
     /*  522767 */     GIR_EraseRootFromParent_Done,
     /*  522768 */   // Label 7964: @522768
     /*  522768 */   GIM_Try, /*On fail goto*//*Label 7965*/ GIMT_Encode4(522816), // Rule ID 14686 //
     /*  522773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  522776 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  522781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  522792 */     // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  522792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  522795 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  522797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  522802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  522807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522814 */     GIR_RootConstrainSelectedInstOperands,
     /*  522815 */     // GIR_Coverage, 14686,
     /*  522815 */     GIR_EraseRootFromParent_Done,
     /*  522816 */   // Label 7965: @522816
     /*  522816 */   GIM_Try, /*On fail goto*//*Label 7966*/ GIMT_Encode4(522879), // Rule ID 16318 //
     /*  522821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  522824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  522831 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522835 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  522842 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  522842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  522845 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  522847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  522852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  522857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  522862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  522867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522877 */     GIR_RootConstrainSelectedInstOperands,
     /*  522878 */     // GIR_Coverage, 16318,
     /*  522878 */     GIR_EraseRootFromParent_Done,
     /*  522879 */   // Label 7966: @522879
     /*  522879 */   GIM_Try, /*On fail goto*//*Label 7967*/ GIMT_Encode4(522942), // Rule ID 16319 //
     /*  522884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  522887 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  522894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  522905 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  522905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  522908 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  522910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  522915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  522920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  522925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  522930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  522940 */     GIR_RootConstrainSelectedInstOperands,
     /*  522941 */     // GIR_Coverage, 16319,
     /*  522941 */     GIR_EraseRootFromParent_Done,
     /*  522942 */   // Label 7967: @522942
     /*  522942 */   GIM_Try, /*On fail goto*//*Label 7968*/ GIMT_Encode4(523005), // Rule ID 16320 //
     /*  522947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  522950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  522957 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  522961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  522968 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  522968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  522971 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  522973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  522978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  522983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  522988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  522993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  522999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523003 */     GIR_RootConstrainSelectedInstOperands,
     /*  523004 */     // GIR_Coverage, 16320,
     /*  523004 */     GIR_EraseRootFromParent_Done,
     /*  523005 */   // Label 7968: @523005
     /*  523005 */   GIM_Try, /*On fail goto*//*Label 7969*/ GIMT_Encode4(523068), // Rule ID 16321 //
     /*  523010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  523013 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523031 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523034 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523066 */     GIR_RootConstrainSelectedInstOperands,
     /*  523067 */     // GIR_Coverage, 16321,
     /*  523067 */     GIR_EraseRootFromParent_Done,
     /*  523068 */   // Label 7969: @523068
     /*  523068 */   GIM_Try, /*On fail goto*//*Label 7970*/ GIMT_Encode4(523131), // Rule ID 16322 //
     /*  523073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  523076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523094 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523097 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523125 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523129 */     GIR_RootConstrainSelectedInstOperands,
     /*  523130 */     // GIR_Coverage, 16322,
     /*  523130 */     GIR_EraseRootFromParent_Done,
     /*  523131 */   // Label 7970: @523131
     /*  523131 */   GIM_Try, /*On fail goto*//*Label 7971*/ GIMT_Encode4(523194), // Rule ID 16328 //
     /*  523136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  523139 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523146 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523150 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523157 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523160 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523192 */     GIR_RootConstrainSelectedInstOperands,
     /*  523193 */     // GIR_Coverage, 16328,
     /*  523193 */     GIR_EraseRootFromParent_Done,
     /*  523194 */   // Label 7971: @523194
     /*  523194 */   GIM_Try, /*On fail goto*//*Label 7972*/ GIMT_Encode4(523257), // Rule ID 16329 //
     /*  523199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  523202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523209 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523220 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523223 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523255 */     GIR_RootConstrainSelectedInstOperands,
     /*  523256 */     // GIR_Coverage, 16329,
     /*  523256 */     GIR_EraseRootFromParent_Done,
     /*  523257 */   // Label 7972: @523257
     /*  523257 */   GIM_Try, /*On fail goto*//*Label 7973*/ GIMT_Encode4(523320), // Rule ID 16330 //
     /*  523262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  523265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523283 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523286 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523318 */     GIR_RootConstrainSelectedInstOperands,
     /*  523319 */     // GIR_Coverage, 16330,
     /*  523319 */     GIR_EraseRootFromParent_Done,
     /*  523320 */   // Label 7973: @523320
     /*  523320 */   GIM_Try, /*On fail goto*//*Label 7974*/ GIMT_Encode4(523383), // Rule ID 16331 //
     /*  523325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  523328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523346 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523349 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523381 */     GIR_RootConstrainSelectedInstOperands,
     /*  523382 */     // GIR_Coverage, 16331,
     /*  523382 */     GIR_EraseRootFromParent_Done,
     /*  523383 */   // Label 7974: @523383
     /*  523383 */   GIM_Try, /*On fail goto*//*Label 7975*/ GIMT_Encode4(523446), // Rule ID 16332 //
     /*  523388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  523391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523398 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523409 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523412 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523444 */     GIR_RootConstrainSelectedInstOperands,
     /*  523445 */     // GIR_Coverage, 16332,
     /*  523445 */     GIR_EraseRootFromParent_Done,
     /*  523446 */   // Label 7975: @523446
     /*  523446 */   GIM_Try, /*On fail goto*//*Label 7976*/ GIMT_Encode4(523509), // Rule ID 16338 //
     /*  523451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  523454 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523472 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523475 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523507 */     GIR_RootConstrainSelectedInstOperands,
     /*  523508 */     // GIR_Coverage, 16338,
     /*  523508 */     GIR_EraseRootFromParent_Done,
     /*  523509 */   // Label 7976: @523509
     /*  523509 */   GIM_Try, /*On fail goto*//*Label 7977*/ GIMT_Encode4(523572), // Rule ID 16339 //
     /*  523514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  523517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523535 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523538 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523566 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523570 */     GIR_RootConstrainSelectedInstOperands,
     /*  523571 */     // GIR_Coverage, 16339,
     /*  523571 */     GIR_EraseRootFromParent_Done,
     /*  523572 */   // Label 7977: @523572
     /*  523572 */   GIM_Try, /*On fail goto*//*Label 7978*/ GIMT_Encode4(523635), // Rule ID 16340 //
     /*  523577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  523580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523598 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523601 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523633 */     GIR_RootConstrainSelectedInstOperands,
     /*  523634 */     // GIR_Coverage, 16340,
     /*  523634 */     GIR_EraseRootFromParent_Done,
     /*  523635 */   // Label 7978: @523635
     /*  523635 */   GIM_Try, /*On fail goto*//*Label 7979*/ GIMT_Encode4(523698), // Rule ID 16341 //
     /*  523640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  523643 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523661 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523664 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523696 */     GIR_RootConstrainSelectedInstOperands,
     /*  523697 */     // GIR_Coverage, 16341,
     /*  523697 */     GIR_EraseRootFromParent_Done,
     /*  523698 */   // Label 7979: @523698
     /*  523698 */   GIM_Try, /*On fail goto*//*Label 7980*/ GIMT_Encode4(523761), // Rule ID 16342 //
     /*  523703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  523706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523724 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  523727 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523759 */     GIR_RootConstrainSelectedInstOperands,
     /*  523760 */     // GIR_Coverage, 16342,
     /*  523760 */     GIR_EraseRootFromParent_Done,
     /*  523761 */   // Label 7980: @523761
     /*  523761 */   GIM_Try, /*On fail goto*//*Label 7981*/ GIMT_Encode4(523824), // Rule ID 16348 //
     /*  523766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  523769 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523787 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523790 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523822 */     GIR_RootConstrainSelectedInstOperands,
     /*  523823 */     // GIR_Coverage, 16348,
     /*  523823 */     GIR_EraseRootFromParent_Done,
     /*  523824 */   // Label 7981: @523824
     /*  523824 */   GIM_Try, /*On fail goto*//*Label 7982*/ GIMT_Encode4(523887), // Rule ID 16349 //
     /*  523829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  523832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523839 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523850 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523853 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523885 */     GIR_RootConstrainSelectedInstOperands,
     /*  523886 */     // GIR_Coverage, 16349,
     /*  523886 */     GIR_EraseRootFromParent_Done,
     /*  523887 */   // Label 7982: @523887
     /*  523887 */   GIM_Try, /*On fail goto*//*Label 7983*/ GIMT_Encode4(523950), // Rule ID 16350 //
     /*  523892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  523895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523902 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523906 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523913 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523916 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  523938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  523944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  523948 */     GIR_RootConstrainSelectedInstOperands,
     /*  523949 */     // GIR_Coverage, 16350,
     /*  523949 */     GIR_EraseRootFromParent_Done,
     /*  523950 */   // Label 7983: @523950
     /*  523950 */   GIM_Try, /*On fail goto*//*Label 7984*/ GIMT_Encode4(524013), // Rule ID 16351 //
     /*  523955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  523958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  523965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  523969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  523976 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  523976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  523979 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  523981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  523986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  523991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  523996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  524001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524011 */     GIR_RootConstrainSelectedInstOperands,
     /*  524012 */     // GIR_Coverage, 16351,
     /*  524012 */     GIR_EraseRootFromParent_Done,
     /*  524013 */   // Label 7984: @524013
     /*  524013 */   GIM_Try, /*On fail goto*//*Label 7985*/ GIMT_Encode4(524076), // Rule ID 16352 //
     /*  524018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  524021 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  524028 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524032 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  524039 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  524039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  524042 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  524044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  524049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  524054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  524059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  524064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524074 */     GIR_RootConstrainSelectedInstOperands,
     /*  524075 */     // GIR_Coverage, 16352,
     /*  524075 */     GIR_EraseRootFromParent_Done,
     /*  524076 */   // Label 7985: @524076
     /*  524076 */   GIM_Try, /*On fail goto*//*Label 7986*/ GIMT_Encode4(524193), // Rule ID 29528 //
     /*  524081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  524084 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524104 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524104 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524107 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524111 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524116 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524122 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524127 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524132 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524135 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524139 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524144 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524150 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524155 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524168 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524171 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524191 */     GIR_RootConstrainSelectedInstOperands,
     /*  524192 */     // GIR_Coverage, 29528,
     /*  524192 */     GIR_EraseRootFromParent_Done,
     /*  524193 */   // Label 7986: @524193
     /*  524193 */   GIM_Try, /*On fail goto*//*Label 7987*/ GIMT_Encode4(524310), // Rule ID 29529 //
     /*  524198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  524201 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524221 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524221 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524224 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524228 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524233 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524239 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524244 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524249 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524252 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524256 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524261 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524267 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524272 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524285 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524288 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524308 */     GIR_RootConstrainSelectedInstOperands,
     /*  524309 */     // GIR_Coverage, 29529,
     /*  524309 */     GIR_EraseRootFromParent_Done,
     /*  524310 */   // Label 7987: @524310
     /*  524310 */   GIM_Try, /*On fail goto*//*Label 7988*/ GIMT_Encode4(524427), // Rule ID 29530 //
     /*  524315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  524318 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524338 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524338 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524341 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524345 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524350 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524356 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524361 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524366 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524369 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524373 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524378 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524384 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524389 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524402 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524405 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524425 */     GIR_RootConstrainSelectedInstOperands,
     /*  524426 */     // GIR_Coverage, 29530,
     /*  524426 */     GIR_EraseRootFromParent_Done,
     /*  524427 */   // Label 7988: @524427
     /*  524427 */   GIM_Try, /*On fail goto*//*Label 7989*/ GIMT_Encode4(524544), // Rule ID 29531 //
     /*  524432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  524435 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524444 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524455 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524455 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524458 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524462 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524467 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524473 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524478 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524483 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524486 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524490 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524495 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524501 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524506 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524519 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524522 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524542 */     GIR_RootConstrainSelectedInstOperands,
     /*  524543 */     // GIR_Coverage, 29531,
     /*  524543 */     GIR_EraseRootFromParent_Done,
     /*  524544 */   // Label 7989: @524544
     /*  524544 */   GIM_Try, /*On fail goto*//*Label 7990*/ GIMT_Encode4(524661), // Rule ID 29532 //
     /*  524549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  524552 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524572 */     // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524572 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524575 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524579 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524584 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524590 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524595 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524600 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524603 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524607 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524612 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524618 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524623 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524636 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524639 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524659 */     GIR_RootConstrainSelectedInstOperands,
     /*  524660 */     // GIR_Coverage, 29532,
     /*  524660 */     GIR_EraseRootFromParent_Done,
     /*  524661 */   // Label 7990: @524661
     /*  524661 */   GIM_Try, /*On fail goto*//*Label 7991*/ GIMT_Encode4(524778), // Rule ID 29548 //
     /*  524666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  524669 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524682 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524689 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524689 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524692 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524696 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524701 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524707 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524712 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524717 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524720 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524724 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524729 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524735 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524740 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524753 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524756 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524776 */     GIR_RootConstrainSelectedInstOperands,
     /*  524777 */     // GIR_Coverage, 29548,
     /*  524777 */     GIR_EraseRootFromParent_Done,
     /*  524778 */   // Label 7991: @524778
     /*  524778 */   GIM_Try, /*On fail goto*//*Label 7992*/ GIMT_Encode4(524895), // Rule ID 29549 //
     /*  524783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  524786 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524799 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524806 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524806 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524809 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524813 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524818 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524824 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524829 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524834 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524837 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524841 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524846 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524852 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524857 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524870 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524873 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  524886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  524889 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  524893 */     GIR_RootConstrainSelectedInstOperands,
     /*  524894 */     // GIR_Coverage, 29549,
     /*  524894 */     GIR_EraseRootFromParent_Done,
     /*  524895 */   // Label 7992: @524895
     /*  524895 */   GIM_Try, /*On fail goto*//*Label 7993*/ GIMT_Encode4(525012), // Rule ID 29550 //
     /*  524900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  524903 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  524907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  524912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  524916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  524923 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  524923 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  524926 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524930 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524935 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  524941 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524946 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524951 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  524954 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  524958 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  524963 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  524969 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  524974 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  524979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  524982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  524987 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  524990 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  524993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  524998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  525003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525010 */     GIR_RootConstrainSelectedInstOperands,
     /*  525011 */     // GIR_Coverage, 29550,
     /*  525011 */     GIR_EraseRootFromParent_Done,
     /*  525012 */   // Label 7993: @525012
     /*  525012 */   GIM_Try, /*On fail goto*//*Label 7994*/ GIMT_Encode4(525129), // Rule ID 29551 //
     /*  525017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  525020 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  525024 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  525029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  525040 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  525040 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  525043 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  525047 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  525052 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  525058 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  525063 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  525068 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  525071 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  525075 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  525080 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  525086 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  525091 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  525096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  525099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  525104 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  525107 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  525110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  525115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  525120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525123 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525127 */     GIR_RootConstrainSelectedInstOperands,
     /*  525128 */     // GIR_Coverage, 29551,
     /*  525128 */     GIR_EraseRootFromParent_Done,
     /*  525129 */   // Label 7994: @525129
     /*  525129 */   GIM_Try, /*On fail goto*//*Label 7995*/ GIMT_Encode4(525246), // Rule ID 29552 //
     /*  525134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  525137 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  525141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  525146 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525150 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  525157 */     // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  525157 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  525160 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  525164 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  525169 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  525175 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  525180 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  525185 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  525188 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  525192 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  525197 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  525203 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  525208 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  525213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  525216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  525221 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  525224 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  525227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  525232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  525237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525244 */     GIR_RootConstrainSelectedInstOperands,
     /*  525245 */     // GIR_Coverage, 29552,
     /*  525245 */     GIR_EraseRootFromParent_Done,
     /*  525246 */   // Label 7995: @525246
     /*  525246 */   GIM_Try, /*On fail goto*//*Label 7996*/ GIMT_Encode4(525304), // Rule ID 16313 //
     /*  525251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  525254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525265 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525272 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525275 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525302 */     GIR_RootConstrainSelectedInstOperands,
     /*  525303 */     // GIR_Coverage, 16313,
     /*  525303 */     GIR_EraseRootFromParent_Done,
     /*  525304 */   // Label 7996: @525304
     /*  525304 */   GIM_Try, /*On fail goto*//*Label 7997*/ GIMT_Encode4(525362), // Rule ID 16314 //
     /*  525309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  525312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525330 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525333 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525360 */     GIR_RootConstrainSelectedInstOperands,
     /*  525361 */     // GIR_Coverage, 16314,
     /*  525361 */     GIR_EraseRootFromParent_Done,
     /*  525362 */   // Label 7997: @525362
     /*  525362 */   GIM_Try, /*On fail goto*//*Label 7998*/ GIMT_Encode4(525420), // Rule ID 16315 //
     /*  525367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  525370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525388 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525391 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525418 */     GIR_RootConstrainSelectedInstOperands,
     /*  525419 */     // GIR_Coverage, 16315,
     /*  525419 */     GIR_EraseRootFromParent_Done,
     /*  525420 */   // Label 7998: @525420
     /*  525420 */   GIM_Try, /*On fail goto*//*Label 7999*/ GIMT_Encode4(525478), // Rule ID 16316 //
     /*  525425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  525428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525446 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525449 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525476 */     GIR_RootConstrainSelectedInstOperands,
     /*  525477 */     // GIR_Coverage, 16316,
     /*  525477 */     GIR_EraseRootFromParent_Done,
     /*  525478 */   // Label 7999: @525478
     /*  525478 */   GIM_Try, /*On fail goto*//*Label 8000*/ GIMT_Encode4(525536), // Rule ID 16317 //
     /*  525483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  525486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525504 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525507 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525534 */     GIR_RootConstrainSelectedInstOperands,
     /*  525535 */     // GIR_Coverage, 16317,
     /*  525535 */     GIR_EraseRootFromParent_Done,
     /*  525536 */   // Label 8000: @525536
     /*  525536 */   GIM_Try, /*On fail goto*//*Label 8001*/ GIMT_Encode4(525594), // Rule ID 16323 //
     /*  525541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  525544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525562 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  525565 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525592 */     GIR_RootConstrainSelectedInstOperands,
     /*  525593 */     // GIR_Coverage, 16323,
     /*  525593 */     GIR_EraseRootFromParent_Done,
     /*  525594 */   // Label 8001: @525594
     /*  525594 */   GIM_Try, /*On fail goto*//*Label 8002*/ GIMT_Encode4(525652), // Rule ID 16324 //
     /*  525599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  525602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525620 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  525623 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525650 */     GIR_RootConstrainSelectedInstOperands,
     /*  525651 */     // GIR_Coverage, 16324,
     /*  525651 */     GIR_EraseRootFromParent_Done,
     /*  525652 */   // Label 8002: @525652
     /*  525652 */   GIM_Try, /*On fail goto*//*Label 8003*/ GIMT_Encode4(525710), // Rule ID 16325 //
     /*  525657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  525660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525678 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  525681 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525708 */     GIR_RootConstrainSelectedInstOperands,
     /*  525709 */     // GIR_Coverage, 16325,
     /*  525709 */     GIR_EraseRootFromParent_Done,
     /*  525710 */   // Label 8003: @525710
     /*  525710 */   GIM_Try, /*On fail goto*//*Label 8004*/ GIMT_Encode4(525768), // Rule ID 16326 //
     /*  525715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  525718 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525736 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  525739 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525766 */     GIR_RootConstrainSelectedInstOperands,
     /*  525767 */     // GIR_Coverage, 16326,
     /*  525767 */     GIR_EraseRootFromParent_Done,
     /*  525768 */   // Label 8004: @525768
     /*  525768 */   GIM_Try, /*On fail goto*//*Label 8005*/ GIMT_Encode4(525826), // Rule ID 16327 //
     /*  525773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  525776 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525794 */     // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  525797 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525824 */     GIR_RootConstrainSelectedInstOperands,
     /*  525825 */     // GIR_Coverage, 16327,
     /*  525825 */     GIR_EraseRootFromParent_Done,
     /*  525826 */   // Label 8005: @525826
     /*  525826 */   GIM_Try, /*On fail goto*//*Label 8006*/ GIMT_Encode4(525884), // Rule ID 16333 //
     /*  525831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  525834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525852 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525855 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525878 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525882 */     GIR_RootConstrainSelectedInstOperands,
     /*  525883 */     // GIR_Coverage, 16333,
     /*  525883 */     GIR_EraseRootFromParent_Done,
     /*  525884 */   // Label 8006: @525884
     /*  525884 */   GIM_Try, /*On fail goto*//*Label 8007*/ GIMT_Encode4(525942), // Rule ID 16334 //
     /*  525889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  525892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525910 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525913 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525940 */     GIR_RootConstrainSelectedInstOperands,
     /*  525941 */     // GIR_Coverage, 16334,
     /*  525941 */     GIR_EraseRootFromParent_Done,
     /*  525942 */   // Label 8007: @525942
     /*  525942 */   GIM_Try, /*On fail goto*//*Label 8008*/ GIMT_Encode4(526000), // Rule ID 16335 //
     /*  525947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  525950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  525957 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  525961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  525968 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  525968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  525971 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  525973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  525978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  525983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  525988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  525994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  525998 */     GIR_RootConstrainSelectedInstOperands,
     /*  525999 */     // GIR_Coverage, 16335,
     /*  525999 */     GIR_EraseRootFromParent_Done,
     /*  526000 */   // Label 8008: @526000
     /*  526000 */   GIM_Try, /*On fail goto*//*Label 8009*/ GIMT_Encode4(526058), // Rule ID 16336 //
     /*  526005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  526008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526026 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  526029 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526056 */     GIR_RootConstrainSelectedInstOperands,
     /*  526057 */     // GIR_Coverage, 16336,
     /*  526057 */     GIR_EraseRootFromParent_Done,
     /*  526058 */   // Label 8009: @526058
     /*  526058 */   GIM_Try, /*On fail goto*//*Label 8010*/ GIMT_Encode4(526116), // Rule ID 16337 //
     /*  526063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  526066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526084 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  526087 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526114 */     GIR_RootConstrainSelectedInstOperands,
     /*  526115 */     // GIR_Coverage, 16337,
     /*  526115 */     GIR_EraseRootFromParent_Done,
     /*  526116 */   // Label 8010: @526116
     /*  526116 */   GIM_Try, /*On fail goto*//*Label 8011*/ GIMT_Encode4(526174), // Rule ID 16343 //
     /*  526121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  526124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526142 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  526145 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526172 */     GIR_RootConstrainSelectedInstOperands,
     /*  526173 */     // GIR_Coverage, 16343,
     /*  526173 */     GIR_EraseRootFromParent_Done,
     /*  526174 */   // Label 8011: @526174
     /*  526174 */   GIM_Try, /*On fail goto*//*Label 8012*/ GIMT_Encode4(526232), // Rule ID 16344 //
     /*  526179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  526182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526189 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526200 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  526203 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526230 */     GIR_RootConstrainSelectedInstOperands,
     /*  526231 */     // GIR_Coverage, 16344,
     /*  526231 */     GIR_EraseRootFromParent_Done,
     /*  526232 */   // Label 8012: @526232
     /*  526232 */   GIM_Try, /*On fail goto*//*Label 8013*/ GIMT_Encode4(526290), // Rule ID 16345 //
     /*  526237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  526240 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526258 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  526261 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526281 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526288 */     GIR_RootConstrainSelectedInstOperands,
     /*  526289 */     // GIR_Coverage, 16345,
     /*  526289 */     GIR_EraseRootFromParent_Done,
     /*  526290 */   // Label 8013: @526290
     /*  526290 */   GIM_Try, /*On fail goto*//*Label 8014*/ GIMT_Encode4(526348), // Rule ID 16346 //
     /*  526295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  526298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526316 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  526319 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526342 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526346 */     GIR_RootConstrainSelectedInstOperands,
     /*  526347 */     // GIR_Coverage, 16346,
     /*  526347 */     GIR_EraseRootFromParent_Done,
     /*  526348 */   // Label 8014: @526348
     /*  526348 */   GIM_Try, /*On fail goto*//*Label 8015*/ GIMT_Encode4(526406), // Rule ID 16347 //
     /*  526353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  526356 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  526363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  526374 */     // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  526374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  526377 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  526379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  526384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  526389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  526394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526404 */     GIR_RootConstrainSelectedInstOperands,
     /*  526405 */     // GIR_Coverage, 16347,
     /*  526405 */     GIR_EraseRootFromParent_Done,
     /*  526406 */   // Label 8015: @526406
     /*  526406 */   GIM_Try, /*On fail goto*//*Label 8016*/ GIMT_Encode4(526519), // Rule ID 29538 //
     /*  526411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  526414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  526419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  526430 */     // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  526430 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  526433 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526437 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526442 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  526448 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526453 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526458 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  526461 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526465 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526470 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  526476 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526481 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  526489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  526494 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  526497 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  526500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  526505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  526510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526517 */     GIR_RootConstrainSelectedInstOperands,
     /*  526518 */     // GIR_Coverage, 29538,
     /*  526518 */     GIR_EraseRootFromParent_Done,
     /*  526519 */   // Label 8016: @526519
     /*  526519 */   GIM_Try, /*On fail goto*//*Label 8017*/ GIMT_Encode4(526632), // Rule ID 29539 //
     /*  526524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  526527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  526532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  526543 */     // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  526543 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  526546 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526550 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526555 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  526561 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526566 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526571 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  526574 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526578 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526583 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  526589 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526594 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  526602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  526607 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  526610 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  526613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  526618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  526623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526630 */     GIR_RootConstrainSelectedInstOperands,
     /*  526631 */     // GIR_Coverage, 29539,
     /*  526631 */     GIR_EraseRootFromParent_Done,
     /*  526632 */   // Label 8017: @526632
     /*  526632 */   GIM_Try, /*On fail goto*//*Label 8018*/ GIMT_Encode4(526745), // Rule ID 29540 //
     /*  526637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  526640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  526645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  526656 */     // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  526656 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  526659 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526663 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526668 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  526674 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526679 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526684 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  526687 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526691 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526696 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  526702 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526707 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  526715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  526720 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  526723 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  526726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  526731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  526736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526743 */     GIR_RootConstrainSelectedInstOperands,
     /*  526744 */     // GIR_Coverage, 29540,
     /*  526744 */     GIR_EraseRootFromParent_Done,
     /*  526745 */   // Label 8018: @526745
     /*  526745 */   GIM_Try, /*On fail goto*//*Label 8019*/ GIMT_Encode4(526858), // Rule ID 29541 //
     /*  526750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  526753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  526758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  526769 */     // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  526769 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  526772 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526776 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526781 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  526787 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526792 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526797 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  526800 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526804 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526809 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  526815 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526820 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  526828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  526833 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  526836 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  526839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  526844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  526849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526856 */     GIR_RootConstrainSelectedInstOperands,
     /*  526857 */     // GIR_Coverage, 29541,
     /*  526857 */     GIR_EraseRootFromParent_Done,
     /*  526858 */   // Label 8019: @526858
     /*  526858 */   GIM_Try, /*On fail goto*//*Label 8020*/ GIMT_Encode4(526971), // Rule ID 29542 //
     /*  526863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  526866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  526871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  526882 */     // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  526882 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  526885 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526889 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526894 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  526900 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526905 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526910 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  526913 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  526917 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  526922 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  526928 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  526933 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  526938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  526941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  526946 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  526949 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  526952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  526957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  526962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  526965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  526969 */     GIR_RootConstrainSelectedInstOperands,
     /*  526970 */     // GIR_Coverage, 29542,
     /*  526970 */     GIR_EraseRootFromParent_Done,
     /*  526971 */   // Label 8020: @526971
     /*  526971 */   GIM_Try, /*On fail goto*//*Label 8021*/ GIMT_Encode4(527084), // Rule ID 29558 //
     /*  526976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  526979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  526984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  526988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  526995 */     // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  526995 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  526998 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527002 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527007 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  527013 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527018 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  527026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527035 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  527041 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527046 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  527054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  527059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  527062 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  527065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  527070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  527075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  527078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527082 */     GIR_RootConstrainSelectedInstOperands,
     /*  527083 */     // GIR_Coverage, 29558,
     /*  527083 */     GIR_EraseRootFromParent_Done,
     /*  527084 */   // Label 8021: @527084
     /*  527084 */   GIM_Try, /*On fail goto*//*Label 8022*/ GIMT_Encode4(527197), // Rule ID 29559 //
     /*  527089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  527092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  527097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527101 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  527108 */     // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  527108 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  527111 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527115 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527120 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  527126 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527131 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527136 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  527139 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527143 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527148 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  527154 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527159 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  527167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  527172 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  527175 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  527178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  527183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  527188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  527191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527195 */     GIR_RootConstrainSelectedInstOperands,
     /*  527196 */     // GIR_Coverage, 29559,
     /*  527196 */     GIR_EraseRootFromParent_Done,
     /*  527197 */   // Label 8022: @527197
     /*  527197 */   GIM_Try, /*On fail goto*//*Label 8023*/ GIMT_Encode4(527310), // Rule ID 29560 //
     /*  527202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  527205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  527210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  527221 */     // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  527221 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  527224 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527228 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527233 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  527239 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527244 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527249 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  527252 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527256 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527261 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  527267 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527272 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  527280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  527285 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  527288 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  527291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  527296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  527301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  527304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527308 */     GIR_RootConstrainSelectedInstOperands,
     /*  527309 */     // GIR_Coverage, 29560,
     /*  527309 */     GIR_EraseRootFromParent_Done,
     /*  527310 */   // Label 8023: @527310
     /*  527310 */   GIM_Try, /*On fail goto*//*Label 8024*/ GIMT_Encode4(527423), // Rule ID 29561 //
     /*  527315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  527318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  527323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  527334 */     // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  527334 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  527337 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527341 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527346 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  527352 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527357 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527362 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  527365 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527369 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527374 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  527380 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527385 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  527393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  527398 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  527401 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  527404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  527409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  527414 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  527417 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527421 */     GIR_RootConstrainSelectedInstOperands,
     /*  527422 */     // GIR_Coverage, 29561,
     /*  527422 */     GIR_EraseRootFromParent_Done,
     /*  527423 */   // Label 8024: @527423
     /*  527423 */   GIM_Try, /*On fail goto*//*Label 8025*/ GIMT_Encode4(527536), // Rule ID 29562 //
     /*  527428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  527431 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  527436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  527447 */     // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  527447 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  527450 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527454 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527459 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  527465 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527470 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527475 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  527478 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  527482 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  527487 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  527493 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  527498 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  527503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  527506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  527511 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  527514 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  527517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  527522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  527527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  527530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527534 */     GIR_RootConstrainSelectedInstOperands,
     /*  527535 */     // GIR_Coverage, 29562,
     /*  527535 */     GIR_EraseRootFromParent_Done,
     /*  527536 */   // Label 8025: @527536
     /*  527536 */   GIM_Try, /*On fail goto*//*Label 8026*/ GIMT_Encode4(527593), // Rule ID 12503 //
     /*  527541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  527544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527562 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527570 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527591 */     GIR_RootConstrainSelectedInstOperands,
     /*  527592 */     // GIR_Coverage, 12503,
     /*  527592 */     GIR_EraseRootFromParent_Done,
     /*  527593 */   // Label 8026: @527593
     /*  527593 */   GIM_Try, /*On fail goto*//*Label 8027*/ GIMT_Encode4(527650), // Rule ID 12504 //
     /*  527598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  527601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527608 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527612 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527619 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527627 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527644 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527648 */     GIR_RootConstrainSelectedInstOperands,
     /*  527649 */     // GIR_Coverage, 12504,
     /*  527649 */     GIR_EraseRootFromParent_Done,
     /*  527650 */   // Label 8027: @527650
     /*  527650 */   GIM_Try, /*On fail goto*//*Label 8028*/ GIMT_Encode4(527707), // Rule ID 12505 //
     /*  527655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  527658 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527676 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527684 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527705 */     GIR_RootConstrainSelectedInstOperands,
     /*  527706 */     // GIR_Coverage, 12505,
     /*  527706 */     GIR_EraseRootFromParent_Done,
     /*  527707 */   // Label 8028: @527707
     /*  527707 */   GIM_Try, /*On fail goto*//*Label 8029*/ GIMT_Encode4(527764), // Rule ID 12506 //
     /*  527712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  527715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527733 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527741 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527762 */     GIR_RootConstrainSelectedInstOperands,
     /*  527763 */     // GIR_Coverage, 12506,
     /*  527763 */     GIR_EraseRootFromParent_Done,
     /*  527764 */   // Label 8029: @527764
     /*  527764 */   GIM_Try, /*On fail goto*//*Label 8030*/ GIMT_Encode4(527821), // Rule ID 12507 //
     /*  527769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  527772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527783 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527790 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527798 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527819 */     GIR_RootConstrainSelectedInstOperands,
     /*  527820 */     // GIR_Coverage, 12507,
     /*  527820 */     GIR_EraseRootFromParent_Done,
     /*  527821 */   // Label 8030: @527821
     /*  527821 */   GIM_Try, /*On fail goto*//*Label 8031*/ GIMT_Encode4(527878), // Rule ID 12523 //
     /*  527826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  527829 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527847 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527855 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527876 */     GIR_RootConstrainSelectedInstOperands,
     /*  527877 */     // GIR_Coverage, 12523,
     /*  527877 */     GIR_EraseRootFromParent_Done,
     /*  527878 */   // Label 8031: @527878
     /*  527878 */   GIM_Try, /*On fail goto*//*Label 8032*/ GIMT_Encode4(527935), // Rule ID 12524 //
     /*  527883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  527886 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527893 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527897 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527904 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527912 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527933 */     GIR_RootConstrainSelectedInstOperands,
     /*  527934 */     // GIR_Coverage, 12524,
     /*  527934 */     GIR_EraseRootFromParent_Done,
     /*  527935 */   // Label 8032: @527935
     /*  527935 */   GIM_Try, /*On fail goto*//*Label 8033*/ GIMT_Encode4(527992), // Rule ID 12525 //
     /*  527940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  527943 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  527950 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  527954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  527961 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  527961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  527964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  527969 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  527971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  527976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  527981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  527986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  527990 */     GIR_RootConstrainSelectedInstOperands,
     /*  527991 */     // GIR_Coverage, 12525,
     /*  527991 */     GIR_EraseRootFromParent_Done,
     /*  527992 */   // Label 8033: @527992
     /*  527992 */   GIM_Try, /*On fail goto*//*Label 8034*/ GIMT_Encode4(528049), // Rule ID 12526 //
     /*  527997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  528000 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528018 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  528021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528026 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528047 */     GIR_RootConstrainSelectedInstOperands,
     /*  528048 */     // GIR_Coverage, 12526,
     /*  528048 */     GIR_EraseRootFromParent_Done,
     /*  528049 */   // Label 8034: @528049
     /*  528049 */   GIM_Try, /*On fail goto*//*Label 8035*/ GIMT_Encode4(528106), // Rule ID 12527 //
     /*  528054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  528057 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528075 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  528078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528083 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528104 */     GIR_RootConstrainSelectedInstOperands,
     /*  528105 */     // GIR_Coverage, 12527,
     /*  528105 */     GIR_EraseRootFromParent_Done,
     /*  528106 */   // Label 8035: @528106
     /*  528106 */   GIM_Try, /*On fail goto*//*Label 8036*/ GIMT_Encode4(528156), // Rule ID 12498 //
     /*  528111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  528114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528132 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528140 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528154 */     GIR_RootConstrainSelectedInstOperands,
     /*  528155 */     // GIR_Coverage, 12498,
     /*  528155 */     GIR_EraseRootFromParent_Done,
     /*  528156 */   // Label 8036: @528156
     /*  528156 */   GIM_Try, /*On fail goto*//*Label 8037*/ GIMT_Encode4(528206), // Rule ID 12499 //
     /*  528161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  528164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528182 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528190 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528204 */     GIR_RootConstrainSelectedInstOperands,
     /*  528205 */     // GIR_Coverage, 12499,
     /*  528205 */     GIR_EraseRootFromParent_Done,
     /*  528206 */   // Label 8037: @528206
     /*  528206 */   GIM_Try, /*On fail goto*//*Label 8038*/ GIMT_Encode4(528256), // Rule ID 12500 //
     /*  528211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  528214 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528232 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528240 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528254 */     GIR_RootConstrainSelectedInstOperands,
     /*  528255 */     // GIR_Coverage, 12500,
     /*  528255 */     GIR_EraseRootFromParent_Done,
     /*  528256 */   // Label 8038: @528256
     /*  528256 */   GIM_Try, /*On fail goto*//*Label 8039*/ GIMT_Encode4(528306), // Rule ID 12501 //
     /*  528261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  528264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528282 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528290 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528304 */     GIR_RootConstrainSelectedInstOperands,
     /*  528305 */     // GIR_Coverage, 12501,
     /*  528305 */     GIR_EraseRootFromParent_Done,
     /*  528306 */   // Label 8039: @528306
     /*  528306 */   GIM_Try, /*On fail goto*//*Label 8040*/ GIMT_Encode4(528356), // Rule ID 12502 //
     /*  528311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  528314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528332 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528340 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528354 */     GIR_RootConstrainSelectedInstOperands,
     /*  528355 */     // GIR_Coverage, 12502,
     /*  528355 */     GIR_EraseRootFromParent_Done,
     /*  528356 */   // Label 8040: @528356
     /*  528356 */   GIM_Try, /*On fail goto*//*Label 8041*/ GIMT_Encode4(528406), // Rule ID 12518 //
     /*  528361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  528364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528382 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528390 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528404 */     GIR_RootConstrainSelectedInstOperands,
     /*  528405 */     // GIR_Coverage, 12518,
     /*  528405 */     GIR_EraseRootFromParent_Done,
     /*  528406 */   // Label 8041: @528406
     /*  528406 */   GIM_Try, /*On fail goto*//*Label 8042*/ GIMT_Encode4(528456), // Rule ID 12519 //
     /*  528411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  528414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528432 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528440 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528454 */     GIR_RootConstrainSelectedInstOperands,
     /*  528455 */     // GIR_Coverage, 12519,
     /*  528455 */     GIR_EraseRootFromParent_Done,
     /*  528456 */   // Label 8042: @528456
     /*  528456 */   GIM_Try, /*On fail goto*//*Label 8043*/ GIMT_Encode4(528506), // Rule ID 12520 //
     /*  528461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  528464 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528482 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528490 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528504 */     GIR_RootConstrainSelectedInstOperands,
     /*  528505 */     // GIR_Coverage, 12520,
     /*  528505 */     GIR_EraseRootFromParent_Done,
     /*  528506 */   // Label 8043: @528506
     /*  528506 */   GIM_Try, /*On fail goto*//*Label 8044*/ GIMT_Encode4(528556), // Rule ID 12521 //
     /*  528511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  528514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528532 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528540 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528550 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528554 */     GIR_RootConstrainSelectedInstOperands,
     /*  528555 */     // GIR_Coverage, 12521,
     /*  528555 */     GIR_EraseRootFromParent_Done,
     /*  528556 */   // Label 8044: @528556
     /*  528556 */   GIM_Try, /*On fail goto*//*Label 8045*/ GIMT_Encode4(528606), // Rule ID 12522 //
     /*  528561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  528564 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  528571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  528582 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  528582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  528585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  528590 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  528597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  528600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528604 */     GIR_RootConstrainSelectedInstOperands,
     /*  528605 */     // GIR_Coverage, 12522,
     /*  528605 */     GIR_EraseRootFromParent_Done,
     /*  528606 */   // Label 8045: @528606
     /*  528606 */   GIM_Try, /*On fail goto*//*Label 8046*/ GIMT_Encode4(528662), // Rule ID 10361 //
     /*  528611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  528614 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528631 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528639 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528656 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528660 */     GIR_RootConstrainSelectedInstOperands,
     /*  528661 */     // GIR_Coverage, 10361,
     /*  528661 */     GIR_EraseRootFromParent_Done,
     /*  528662 */   // Label 8046: @528662
     /*  528662 */   GIM_Try, /*On fail goto*//*Label 8047*/ GIMT_Encode4(528718), // Rule ID 10362 //
     /*  528667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  528670 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528687 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528695 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528716 */     GIR_RootConstrainSelectedInstOperands,
     /*  528717 */     // GIR_Coverage, 10362,
     /*  528717 */     GIR_EraseRootFromParent_Done,
     /*  528718 */   // Label 8047: @528718
     /*  528718 */   GIM_Try, /*On fail goto*//*Label 8048*/ GIMT_Encode4(528774), // Rule ID 10363 //
     /*  528723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  528726 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528743 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528751 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528772 */     GIR_RootConstrainSelectedInstOperands,
     /*  528773 */     // GIR_Coverage, 10363,
     /*  528773 */     GIR_EraseRootFromParent_Done,
     /*  528774 */   // Label 8048: @528774
     /*  528774 */   GIM_Try, /*On fail goto*//*Label 8049*/ GIMT_Encode4(528830), // Rule ID 10364 //
     /*  528779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  528782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528799 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528807 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528828 */     GIR_RootConstrainSelectedInstOperands,
     /*  528829 */     // GIR_Coverage, 10364,
     /*  528829 */     GIR_EraseRootFromParent_Done,
     /*  528830 */   // Label 8049: @528830
     /*  528830 */   GIM_Try, /*On fail goto*//*Label 8050*/ GIMT_Encode4(528886), // Rule ID 10365 //
     /*  528835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  528838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528855 */     // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528863 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528884 */     GIR_RootConstrainSelectedInstOperands,
     /*  528885 */     // GIR_Coverage, 10365,
     /*  528885 */     GIR_EraseRootFromParent_Done,
     /*  528886 */   // Label 8050: @528886
     /*  528886 */   GIM_Try, /*On fail goto*//*Label 8051*/ GIMT_Encode4(528942), // Rule ID 10381 //
     /*  528891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  528894 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528911 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528919 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528940 */     GIR_RootConstrainSelectedInstOperands,
     /*  528941 */     // GIR_Coverage, 10381,
     /*  528941 */     GIR_EraseRootFromParent_Done,
     /*  528942 */   // Label 8051: @528942
     /*  528942 */   GIM_Try, /*On fail goto*//*Label 8052*/ GIMT_Encode4(528998), // Rule ID 10382 //
     /*  528947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  528950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  528956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  528960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  528967 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  528967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  528970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  528975 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  528977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  528982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  528987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  528992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  528996 */     GIR_RootConstrainSelectedInstOperands,
     /*  528997 */     // GIR_Coverage, 10382,
     /*  528997 */     GIR_EraseRootFromParent_Done,
     /*  528998 */   // Label 8052: @528998
     /*  528998 */   GIM_Try, /*On fail goto*//*Label 8053*/ GIMT_Encode4(529054), // Rule ID 10383 //
     /*  529003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  529006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529012 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529016 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  529023 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  529023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  529026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  529031 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  529038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  529043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  529048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529052 */     GIR_RootConstrainSelectedInstOperands,
     /*  529053 */     // GIR_Coverage, 10383,
     /*  529053 */     GIR_EraseRootFromParent_Done,
     /*  529054 */   // Label 8053: @529054
     /*  529054 */   GIM_Try, /*On fail goto*//*Label 8054*/ GIMT_Encode4(529110), // Rule ID 10384 //
     /*  529059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  529062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  529079 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  529079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  529082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  529087 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  529094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  529099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  529104 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529108 */     GIR_RootConstrainSelectedInstOperands,
     /*  529109 */     // GIR_Coverage, 10384,
     /*  529109 */     GIR_EraseRootFromParent_Done,
     /*  529110 */   // Label 8054: @529110
     /*  529110 */   GIM_Try, /*On fail goto*//*Label 8055*/ GIMT_Encode4(529166), // Rule ID 10385 //
     /*  529115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  529118 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529124 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529128 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  529135 */     // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  529135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  529138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  529143 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  529150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  529155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  529160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529164 */     GIR_RootConstrainSelectedInstOperands,
     /*  529165 */     // GIR_Coverage, 10385,
     /*  529165 */     GIR_EraseRootFromParent_Done,
     /*  529166 */   // Label 8055: @529166
     /*  529166 */   GIM_Try, /*On fail goto*//*Label 8056*/ GIMT_Encode4(529215), // Rule ID 10356 //
     /*  529171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  529174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529191 */     // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529199 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529213 */     GIR_RootConstrainSelectedInstOperands,
     /*  529214 */     // GIR_Coverage, 10356,
     /*  529214 */     GIR_EraseRootFromParent_Done,
     /*  529215 */   // Label 8056: @529215
     /*  529215 */   GIM_Try, /*On fail goto*//*Label 8057*/ GIMT_Encode4(529264), // Rule ID 10357 //
     /*  529220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  529223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529240 */     // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529248 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529262 */     GIR_RootConstrainSelectedInstOperands,
     /*  529263 */     // GIR_Coverage, 10357,
     /*  529263 */     GIR_EraseRootFromParent_Done,
     /*  529264 */   // Label 8057: @529264
     /*  529264 */   GIM_Try, /*On fail goto*//*Label 8058*/ GIMT_Encode4(529313), // Rule ID 10358 //
     /*  529269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  529272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529289 */     // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529297 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529311 */     GIR_RootConstrainSelectedInstOperands,
     /*  529312 */     // GIR_Coverage, 10358,
     /*  529312 */     GIR_EraseRootFromParent_Done,
     /*  529313 */   // Label 8058: @529313
     /*  529313 */   GIM_Try, /*On fail goto*//*Label 8059*/ GIMT_Encode4(529362), // Rule ID 10359 //
     /*  529318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  529321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529338 */     // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529346 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529360 */     GIR_RootConstrainSelectedInstOperands,
     /*  529361 */     // GIR_Coverage, 10359,
     /*  529361 */     GIR_EraseRootFromParent_Done,
     /*  529362 */   // Label 8059: @529362
     /*  529362 */   GIM_Try, /*On fail goto*//*Label 8060*/ GIMT_Encode4(529411), // Rule ID 10360 //
     /*  529367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  529370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529387 */     // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529395 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529409 */     GIR_RootConstrainSelectedInstOperands,
     /*  529410 */     // GIR_Coverage, 10360,
     /*  529410 */     GIR_EraseRootFromParent_Done,
     /*  529411 */   // Label 8060: @529411
     /*  529411 */   GIM_Try, /*On fail goto*//*Label 8061*/ GIMT_Encode4(529460), // Rule ID 10376 //
     /*  529416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  529419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529436 */     // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529444 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529458 */     GIR_RootConstrainSelectedInstOperands,
     /*  529459 */     // GIR_Coverage, 10376,
     /*  529459 */     GIR_EraseRootFromParent_Done,
     /*  529460 */   // Label 8061: @529460
     /*  529460 */   GIM_Try, /*On fail goto*//*Label 8062*/ GIMT_Encode4(529509), // Rule ID 10377 //
     /*  529465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  529468 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529485 */     // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529493 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529507 */     GIR_RootConstrainSelectedInstOperands,
     /*  529508 */     // GIR_Coverage, 10377,
     /*  529508 */     GIR_EraseRootFromParent_Done,
     /*  529509 */   // Label 8062: @529509
     /*  529509 */   GIM_Try, /*On fail goto*//*Label 8063*/ GIMT_Encode4(529558), // Rule ID 10378 //
     /*  529514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  529517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529534 */     // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529542 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529552 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529556 */     GIR_RootConstrainSelectedInstOperands,
     /*  529557 */     // GIR_Coverage, 10378,
     /*  529557 */     GIR_EraseRootFromParent_Done,
     /*  529558 */   // Label 8063: @529558
     /*  529558 */   GIM_Try, /*On fail goto*//*Label 8064*/ GIMT_Encode4(529607), // Rule ID 10379 //
     /*  529563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  529566 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529583 */     // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529591 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529605 */     GIR_RootConstrainSelectedInstOperands,
     /*  529606 */     // GIR_Coverage, 10379,
     /*  529606 */     GIR_EraseRootFromParent_Done,
     /*  529607 */   // Label 8064: @529607
     /*  529607 */   GIM_Try, /*On fail goto*//*Label 8065*/ GIMT_Encode4(529656), // Rule ID 10380 //
     /*  529612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  529615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  529621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  529632 */     // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  529632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  529635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  529640 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  529642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529654 */     GIR_RootConstrainSelectedInstOperands,
     /*  529655 */     // GIR_Coverage, 10380,
     /*  529655 */     GIR_EraseRootFromParent_Done,
     /*  529656 */   // Label 8065: @529656
     /*  529656 */   GIM_Reject,
     /*  529657 */ // Label 7895: @529657
     /*  529657 */ GIM_Reject,
     /*  529658 */ // Label 5871: @529658
     /*  529658 */ GIM_Try, /*On fail goto*//*Label 8066*/ GIMT_Encode4(537152),
     /*  529663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  529666 */   GIM_Try, /*On fail goto*//*Label 8067*/ GIMT_Encode4(529722), // Rule ID 29793 //
     /*  529671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  529674 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  529678 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  529683 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  529687 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  529698 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  529698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  529701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  529706 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  529708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529716 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529720 */     GIR_RootConstrainSelectedInstOperands,
     /*  529721 */     // GIR_Coverage, 29793,
     /*  529721 */     GIR_EraseRootFromParent_Done,
     /*  529722 */   // Label 8067: @529722
     /*  529722 */   GIM_Try, /*On fail goto*//*Label 8068*/ GIMT_Encode4(529778), // Rule ID 29794 //
     /*  529727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  529730 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  529734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  529739 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  529743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  529754 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  529754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  529757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  529762 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  529764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529776 */     GIR_RootConstrainSelectedInstOperands,
     /*  529777 */     // GIR_Coverage, 29794,
     /*  529777 */     GIR_EraseRootFromParent_Done,
     /*  529778 */   // Label 8068: @529778
     /*  529778 */   GIM_Try, /*On fail goto*//*Label 8069*/ GIMT_Encode4(529834), // Rule ID 29795 //
     /*  529783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  529786 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  529790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  529795 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  529799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  529810 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  529810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  529813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  529818 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  529820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529832 */     GIR_RootConstrainSelectedInstOperands,
     /*  529833 */     // GIR_Coverage, 29795,
     /*  529833 */     GIR_EraseRootFromParent_Done,
     /*  529834 */   // Label 8069: @529834
     /*  529834 */   GIM_Try, /*On fail goto*//*Label 8070*/ GIMT_Encode4(529890), // Rule ID 29796 //
     /*  529839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  529842 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  529846 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  529851 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  529855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  529866 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  529866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  529869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  529874 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  529876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529888 */     GIR_RootConstrainSelectedInstOperands,
     /*  529889 */     // GIR_Coverage, 29796,
     /*  529889 */     GIR_EraseRootFromParent_Done,
     /*  529890 */   // Label 8070: @529890
     /*  529890 */   GIM_Try, /*On fail goto*//*Label 8071*/ GIMT_Encode4(529946), // Rule ID 29797 //
     /*  529895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  529898 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  529902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  529907 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  529911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  529922 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  529922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  529925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  529930 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  529932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  529944 */     GIR_RootConstrainSelectedInstOperands,
     /*  529945 */     // GIR_Coverage, 29797,
     /*  529945 */     GIR_EraseRootFromParent_Done,
     /*  529946 */   // Label 8071: @529946
     /*  529946 */   GIM_Try, /*On fail goto*//*Label 8072*/ GIMT_Encode4(530002), // Rule ID 29813 //
     /*  529951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  529954 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  529958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  529963 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  529967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  529971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  529978 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  529978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  529981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  529986 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  529988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  529993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  529996 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530000 */     GIR_RootConstrainSelectedInstOperands,
     /*  530001 */     // GIR_Coverage, 29813,
     /*  530001 */     GIR_EraseRootFromParent_Done,
     /*  530002 */   // Label 8072: @530002
     /*  530002 */   GIM_Try, /*On fail goto*//*Label 8073*/ GIMT_Encode4(530058), // Rule ID 29814 //
     /*  530007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  530010 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530019 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530034 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530042 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530056 */     GIR_RootConstrainSelectedInstOperands,
     /*  530057 */     // GIR_Coverage, 29814,
     /*  530057 */     GIR_EraseRootFromParent_Done,
     /*  530058 */   // Label 8073: @530058
     /*  530058 */   GIM_Try, /*On fail goto*//*Label 8074*/ GIMT_Encode4(530114), // Rule ID 29815 //
     /*  530063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  530066 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530075 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530090 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530098 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530112 */     GIR_RootConstrainSelectedInstOperands,
     /*  530113 */     // GIR_Coverage, 29815,
     /*  530113 */     GIR_EraseRootFromParent_Done,
     /*  530114 */   // Label 8074: @530114
     /*  530114 */   GIM_Try, /*On fail goto*//*Label 8075*/ GIMT_Encode4(530170), // Rule ID 29816 //
     /*  530119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  530122 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530126 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530131 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530146 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530154 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530164 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530168 */     GIR_RootConstrainSelectedInstOperands,
     /*  530169 */     // GIR_Coverage, 29816,
     /*  530169 */     GIR_EraseRootFromParent_Done,
     /*  530170 */   // Label 8075: @530170
     /*  530170 */   GIM_Try, /*On fail goto*//*Label 8076*/ GIMT_Encode4(530226), // Rule ID 29817 //
     /*  530175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  530178 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530187 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530202 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530210 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530224 */     GIR_RootConstrainSelectedInstOperands,
     /*  530225 */     // GIR_Coverage, 29817,
     /*  530225 */     GIR_EraseRootFromParent_Done,
     /*  530226 */   // Label 8076: @530226
     /*  530226 */   GIM_Try, /*On fail goto*//*Label 8077*/ GIMT_Encode4(530278), // Rule ID 30133 //
     /*  530231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  530234 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530238 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530254 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530262 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530276 */     GIR_RootConstrainSelectedInstOperands,
     /*  530277 */     // GIR_Coverage, 30133,
     /*  530277 */     GIR_EraseRootFromParent_Done,
     /*  530278 */   // Label 8077: @530278
     /*  530278 */   GIM_Try, /*On fail goto*//*Label 8078*/ GIMT_Encode4(530330), // Rule ID 30134 //
     /*  530283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  530286 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530290 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530306 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530314 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530328 */     GIR_RootConstrainSelectedInstOperands,
     /*  530329 */     // GIR_Coverage, 30134,
     /*  530329 */     GIR_EraseRootFromParent_Done,
     /*  530330 */   // Label 8078: @530330
     /*  530330 */   GIM_Try, /*On fail goto*//*Label 8079*/ GIMT_Encode4(530382), // Rule ID 30135 //
     /*  530335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  530338 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530342 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530358 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530366 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530380 */     GIR_RootConstrainSelectedInstOperands,
     /*  530381 */     // GIR_Coverage, 30135,
     /*  530381 */     GIR_EraseRootFromParent_Done,
     /*  530382 */   // Label 8079: @530382
     /*  530382 */   GIM_Try, /*On fail goto*//*Label 8080*/ GIMT_Encode4(530434), // Rule ID 30136 //
     /*  530387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  530390 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530410 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530418 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530432 */     GIR_RootConstrainSelectedInstOperands,
     /*  530433 */     // GIR_Coverage, 30136,
     /*  530433 */     GIR_EraseRootFromParent_Done,
     /*  530434 */   // Label 8080: @530434
     /*  530434 */   GIM_Try, /*On fail goto*//*Label 8081*/ GIMT_Encode4(530486), // Rule ID 30137 //
     /*  530439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  530442 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530446 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530462 */     // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530470 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530484 */     GIR_RootConstrainSelectedInstOperands,
     /*  530485 */     // GIR_Coverage, 30137,
     /*  530485 */     GIR_EraseRootFromParent_Done,
     /*  530486 */   // Label 8081: @530486
     /*  530486 */   GIM_Try, /*On fail goto*//*Label 8082*/ GIMT_Encode4(530538), // Rule ID 30153 //
     /*  530491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  530494 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530514 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530522 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530536 */     GIR_RootConstrainSelectedInstOperands,
     /*  530537 */     // GIR_Coverage, 30153,
     /*  530537 */     GIR_EraseRootFromParent_Done,
     /*  530538 */   // Label 8082: @530538
     /*  530538 */   GIM_Try, /*On fail goto*//*Label 8083*/ GIMT_Encode4(530590), // Rule ID 30154 //
     /*  530543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  530546 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530550 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530555 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530559 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530566 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530574 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530588 */     GIR_RootConstrainSelectedInstOperands,
     /*  530589 */     // GIR_Coverage, 30154,
     /*  530589 */     GIR_EraseRootFromParent_Done,
     /*  530590 */   // Label 8083: @530590
     /*  530590 */   GIM_Try, /*On fail goto*//*Label 8084*/ GIMT_Encode4(530642), // Rule ID 30155 //
     /*  530595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  530598 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530618 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530626 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530640 */     GIR_RootConstrainSelectedInstOperands,
     /*  530641 */     // GIR_Coverage, 30155,
     /*  530641 */     GIR_EraseRootFromParent_Done,
     /*  530642 */   // Label 8084: @530642
     /*  530642 */   GIM_Try, /*On fail goto*//*Label 8085*/ GIMT_Encode4(530694), // Rule ID 30156 //
     /*  530647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  530650 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530654 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530670 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530678 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530685 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530692 */     GIR_RootConstrainSelectedInstOperands,
     /*  530693 */     // GIR_Coverage, 30156,
     /*  530693 */     GIR_EraseRootFromParent_Done,
     /*  530694 */   // Label 8085: @530694
     /*  530694 */   GIM_Try, /*On fail goto*//*Label 8086*/ GIMT_Encode4(530746), // Rule ID 30157 //
     /*  530699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  530702 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  530706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530722 */     // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
     /*  530725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530730 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530737 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530744 */     GIR_RootConstrainSelectedInstOperands,
     /*  530745 */     // GIR_Coverage, 30157,
     /*  530745 */     GIR_EraseRootFromParent_Done,
     /*  530746 */   // Label 8086: @530746
     /*  530746 */   GIM_Try, /*On fail goto*//*Label 8087*/ GIMT_Encode4(530798), // Rule ID 29798 //
     /*  530751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  530754 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530759 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530774 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  530777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530782 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530796 */     GIR_RootConstrainSelectedInstOperands,
     /*  530797 */     // GIR_Coverage, 29798,
     /*  530797 */     GIR_EraseRootFromParent_Done,
     /*  530798 */   // Label 8087: @530798
     /*  530798 */   GIM_Try, /*On fail goto*//*Label 8088*/ GIMT_Encode4(530850), // Rule ID 29799 //
     /*  530803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  530806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530811 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530826 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  530829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530834 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530848 */     GIR_RootConstrainSelectedInstOperands,
     /*  530849 */     // GIR_Coverage, 29799,
     /*  530849 */     GIR_EraseRootFromParent_Done,
     /*  530850 */   // Label 8088: @530850
     /*  530850 */   GIM_Try, /*On fail goto*//*Label 8089*/ GIMT_Encode4(530902), // Rule ID 29800 //
     /*  530855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  530858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530863 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530878 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  530881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530886 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530900 */     GIR_RootConstrainSelectedInstOperands,
     /*  530901 */     // GIR_Coverage, 29800,
     /*  530901 */     GIR_EraseRootFromParent_Done,
     /*  530902 */   // Label 8089: @530902
     /*  530902 */   GIM_Try, /*On fail goto*//*Label 8090*/ GIMT_Encode4(530954), // Rule ID 29801 //
     /*  530907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  530910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530915 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530930 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  530933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530938 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  530948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  530952 */     GIR_RootConstrainSelectedInstOperands,
     /*  530953 */     // GIR_Coverage, 29801,
     /*  530953 */     GIR_EraseRootFromParent_Done,
     /*  530954 */   // Label 8090: @530954
     /*  530954 */   GIM_Try, /*On fail goto*//*Label 8091*/ GIMT_Encode4(531006), // Rule ID 29802 //
     /*  530959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  530962 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  530967 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  530971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  530975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  530982 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  530982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  530985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  530990 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  530992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  530997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531004 */     GIR_RootConstrainSelectedInstOperands,
     /*  531005 */     // GIR_Coverage, 29802,
     /*  531005 */     GIR_EraseRootFromParent_Done,
     /*  531006 */   // Label 8091: @531006
     /*  531006 */   GIM_Try, /*On fail goto*//*Label 8092*/ GIMT_Encode4(531058), // Rule ID 29818 //
     /*  531011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  531014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531019 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  531023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531034 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531042 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531056 */     GIR_RootConstrainSelectedInstOperands,
     /*  531057 */     // GIR_Coverage, 29818,
     /*  531057 */     GIR_EraseRootFromParent_Done,
     /*  531058 */   // Label 8092: @531058
     /*  531058 */   GIM_Try, /*On fail goto*//*Label 8093*/ GIMT_Encode4(531110), // Rule ID 29819 //
     /*  531063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  531066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531071 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  531075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531086 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531094 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531104 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531108 */     GIR_RootConstrainSelectedInstOperands,
     /*  531109 */     // GIR_Coverage, 29819,
     /*  531109 */     GIR_EraseRootFromParent_Done,
     /*  531110 */   // Label 8093: @531110
     /*  531110 */   GIM_Try, /*On fail goto*//*Label 8094*/ GIMT_Encode4(531162), // Rule ID 29820 //
     /*  531115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  531118 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531123 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  531127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531138 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531146 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531160 */     GIR_RootConstrainSelectedInstOperands,
     /*  531161 */     // GIR_Coverage, 29820,
     /*  531161 */     GIR_EraseRootFromParent_Done,
     /*  531162 */   // Label 8094: @531162
     /*  531162 */   GIM_Try, /*On fail goto*//*Label 8095*/ GIMT_Encode4(531214), // Rule ID 29821 //
     /*  531167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  531170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531175 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  531179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531190 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531198 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531212 */     GIR_RootConstrainSelectedInstOperands,
     /*  531213 */     // GIR_Coverage, 29821,
     /*  531213 */     GIR_EraseRootFromParent_Done,
     /*  531214 */   // Label 8095: @531214
     /*  531214 */   GIM_Try, /*On fail goto*//*Label 8096*/ GIMT_Encode4(531266), // Rule ID 29822 //
     /*  531219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  531222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531227 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  531231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531242 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531250 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531264 */     GIR_RootConstrainSelectedInstOperands,
     /*  531265 */     // GIR_Coverage, 29822,
     /*  531265 */     GIR_EraseRootFromParent_Done,
     /*  531266 */   // Label 8096: @531266
     /*  531266 */   GIM_Try, /*On fail goto*//*Label 8097*/ GIMT_Encode4(531314), // Rule ID 30138 //
     /*  531271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  531274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531279 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531290 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531298 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531312 */     GIR_RootConstrainSelectedInstOperands,
     /*  531313 */     // GIR_Coverage, 30138,
     /*  531313 */     GIR_EraseRootFromParent_Done,
     /*  531314 */   // Label 8097: @531314
     /*  531314 */   GIM_Try, /*On fail goto*//*Label 8098*/ GIMT_Encode4(531362), // Rule ID 30139 //
     /*  531319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  531322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531338 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531346 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531360 */     GIR_RootConstrainSelectedInstOperands,
     /*  531361 */     // GIR_Coverage, 30139,
     /*  531361 */     GIR_EraseRootFromParent_Done,
     /*  531362 */   // Label 8098: @531362
     /*  531362 */   GIM_Try, /*On fail goto*//*Label 8099*/ GIMT_Encode4(531410), // Rule ID 30140 //
     /*  531367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  531370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531386 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531394 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531408 */     GIR_RootConstrainSelectedInstOperands,
     /*  531409 */     // GIR_Coverage, 30140,
     /*  531409 */     GIR_EraseRootFromParent_Done,
     /*  531410 */   // Label 8099: @531410
     /*  531410 */   GIM_Try, /*On fail goto*//*Label 8100*/ GIMT_Encode4(531458), // Rule ID 30141 //
     /*  531415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  531418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531427 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531434 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531442 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531456 */     GIR_RootConstrainSelectedInstOperands,
     /*  531457 */     // GIR_Coverage, 30141,
     /*  531457 */     GIR_EraseRootFromParent_Done,
     /*  531458 */   // Label 8100: @531458
     /*  531458 */   GIM_Try, /*On fail goto*//*Label 8101*/ GIMT_Encode4(531506), // Rule ID 30142 //
     /*  531463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  531466 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531482 */     // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531490 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531504 */     GIR_RootConstrainSelectedInstOperands,
     /*  531505 */     // GIR_Coverage, 30142,
     /*  531505 */     GIR_EraseRootFromParent_Done,
     /*  531506 */   // Label 8101: @531506
     /*  531506 */   GIM_Try, /*On fail goto*//*Label 8102*/ GIMT_Encode4(531554), // Rule ID 30158 //
     /*  531511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  531514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531530 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531538 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531552 */     GIR_RootConstrainSelectedInstOperands,
     /*  531553 */     // GIR_Coverage, 30158,
     /*  531553 */     GIR_EraseRootFromParent_Done,
     /*  531554 */   // Label 8102: @531554
     /*  531554 */   GIM_Try, /*On fail goto*//*Label 8103*/ GIMT_Encode4(531602), // Rule ID 30159 //
     /*  531559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  531562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531578 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531586 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531600 */     GIR_RootConstrainSelectedInstOperands,
     /*  531601 */     // GIR_Coverage, 30159,
     /*  531601 */     GIR_EraseRootFromParent_Done,
     /*  531602 */   // Label 8103: @531602
     /*  531602 */   GIM_Try, /*On fail goto*//*Label 8104*/ GIMT_Encode4(531650), // Rule ID 30160 //
     /*  531607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  531610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531626 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531634 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531644 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531648 */     GIR_RootConstrainSelectedInstOperands,
     /*  531649 */     // GIR_Coverage, 30160,
     /*  531649 */     GIR_EraseRootFromParent_Done,
     /*  531650 */   // Label 8104: @531650
     /*  531650 */   GIM_Try, /*On fail goto*//*Label 8105*/ GIMT_Encode4(531698), // Rule ID 30161 //
     /*  531655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  531658 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531674 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531682 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531696 */     GIR_RootConstrainSelectedInstOperands,
     /*  531697 */     // GIR_Coverage, 30161,
     /*  531697 */     GIR_EraseRootFromParent_Done,
     /*  531698 */   // Label 8105: @531698
     /*  531698 */   GIM_Try, /*On fail goto*//*Label 8106*/ GIMT_Encode4(531746), // Rule ID 30162 //
     /*  531703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  531706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  531711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  531722 */     // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15622:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  531722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
     /*  531725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  531730 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  531737 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531744 */     GIR_RootConstrainSelectedInstOperands,
     /*  531745 */     // GIR_Coverage, 30162,
     /*  531745 */     GIR_EraseRootFromParent_Done,
     /*  531746 */   // Label 8106: @531746
     /*  531746 */   GIM_Try, /*On fail goto*//*Label 8107*/ GIMT_Encode4(531802), // Rule ID 25966 //
     /*  531751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  531754 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  531759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  531770 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  531770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  531773 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  531780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  531785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  531790 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531800 */     GIR_RootConstrainSelectedInstOperands,
     /*  531801 */     // GIR_Coverage, 25966,
     /*  531801 */     GIR_EraseRootFromParent_Done,
     /*  531802 */   // Label 8107: @531802
     /*  531802 */   GIM_Try, /*On fail goto*//*Label 8108*/ GIMT_Encode4(531858), // Rule ID 25967 //
     /*  531807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  531810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  531815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  531826 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  531826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  531829 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  531836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  531841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  531846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531856 */     GIR_RootConstrainSelectedInstOperands,
     /*  531857 */     // GIR_Coverage, 25967,
     /*  531857 */     GIR_EraseRootFromParent_Done,
     /*  531858 */   // Label 8108: @531858
     /*  531858 */   GIM_Try, /*On fail goto*//*Label 8109*/ GIMT_Encode4(531914), // Rule ID 25968 //
     /*  531863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  531866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  531871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  531882 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  531882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  531885 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  531892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  531897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  531902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531912 */     GIR_RootConstrainSelectedInstOperands,
     /*  531913 */     // GIR_Coverage, 25968,
     /*  531913 */     GIR_EraseRootFromParent_Done,
     /*  531914 */   // Label 8109: @531914
     /*  531914 */   GIM_Try, /*On fail goto*//*Label 8110*/ GIMT_Encode4(531970), // Rule ID 25969 //
     /*  531919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  531922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  531927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  531938 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  531938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  531941 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  531948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  531953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  531958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  531964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  531968 */     GIR_RootConstrainSelectedInstOperands,
     /*  531969 */     // GIR_Coverage, 25969,
     /*  531969 */     GIR_EraseRootFromParent_Done,
     /*  531970 */   // Label 8110: @531970
     /*  531970 */   GIM_Try, /*On fail goto*//*Label 8111*/ GIMT_Encode4(532026), // Rule ID 25970 //
     /*  531975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  531978 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  531983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  531987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  531994 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  531994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  531997 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  531999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  532004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  532009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532024 */     GIR_RootConstrainSelectedInstOperands,
     /*  532025 */     // GIR_Coverage, 25970,
     /*  532025 */     GIR_EraseRootFromParent_Done,
     /*  532026 */   // Label 8111: @532026
     /*  532026 */   GIM_Try, /*On fail goto*//*Label 8112*/ GIMT_Encode4(532082), // Rule ID 25976 //
     /*  532031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  532034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  532050 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  532050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  532053 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  532055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  532060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  532065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532080 */     GIR_RootConstrainSelectedInstOperands,
     /*  532081 */     // GIR_Coverage, 25976,
     /*  532081 */     GIR_EraseRootFromParent_Done,
     /*  532082 */   // Label 8112: @532082
     /*  532082 */   GIM_Try, /*On fail goto*//*Label 8113*/ GIMT_Encode4(532138), // Rule ID 25977 //
     /*  532087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  532090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  532106 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  532106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  532109 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  532111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  532116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  532121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532136 */     GIR_RootConstrainSelectedInstOperands,
     /*  532137 */     // GIR_Coverage, 25977,
     /*  532137 */     GIR_EraseRootFromParent_Done,
     /*  532138 */   // Label 8113: @532138
     /*  532138 */   GIM_Try, /*On fail goto*//*Label 8114*/ GIMT_Encode4(532194), // Rule ID 25978 //
     /*  532143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  532146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  532162 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  532162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  532165 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  532167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  532172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  532177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532192 */     GIR_RootConstrainSelectedInstOperands,
     /*  532193 */     // GIR_Coverage, 25978,
     /*  532193 */     GIR_EraseRootFromParent_Done,
     /*  532194 */   // Label 8114: @532194
     /*  532194 */   GIM_Try, /*On fail goto*//*Label 8115*/ GIMT_Encode4(532250), // Rule ID 25979 //
     /*  532199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  532202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  532218 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  532218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  532221 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  532223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  532228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  532233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532248 */     GIR_RootConstrainSelectedInstOperands,
     /*  532249 */     // GIR_Coverage, 25979,
     /*  532249 */     GIR_EraseRootFromParent_Done,
     /*  532250 */   // Label 8115: @532250
     /*  532250 */   GIM_Try, /*On fail goto*//*Label 8116*/ GIMT_Encode4(532306), // Rule ID 25980 //
     /*  532255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  532258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  532274 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  532274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  532277 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  532279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  532284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  532289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532304 */     GIR_RootConstrainSelectedInstOperands,
     /*  532305 */     // GIR_Coverage, 25980,
     /*  532305 */     GIR_EraseRootFromParent_Done,
     /*  532306 */   // Label 8116: @532306
     /*  532306 */   GIM_Try, /*On fail goto*//*Label 8117*/ GIMT_Encode4(532361), // Rule ID 14797 //
     /*  532311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  532314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  532330 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SVS anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  532330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS),
     /*  532333 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  532345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  532355 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532359 */     GIR_RootConstrainSelectedInstOperands,
     /*  532360 */     // GIR_Coverage, 14797,
     /*  532360 */     GIR_EraseRootFromParent_Done,
     /*  532361 */   // Label 8117: @532361
     /*  532361 */   GIM_Try, /*On fail goto*//*Label 8118*/ GIMT_Encode4(532416), // Rule ID 14798 //
     /*  532366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  532369 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  532385 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SVS anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  532385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS),
     /*  532388 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  532400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  532410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532414 */     GIR_RootConstrainSelectedInstOperands,
     /*  532415 */     // GIR_Coverage, 14798,
     /*  532415 */     GIR_EraseRootFromParent_Done,
     /*  532416 */   // Label 8118: @532416
     /*  532416 */   GIM_Try, /*On fail goto*//*Label 8119*/ GIMT_Encode4(532471), // Rule ID 14799 //
     /*  532421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  532424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  532440 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SVS anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  532440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS),
     /*  532443 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  532455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  532465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532469 */     GIR_RootConstrainSelectedInstOperands,
     /*  532470 */     // GIR_Coverage, 14799,
     /*  532470 */     GIR_EraseRootFromParent_Done,
     /*  532471 */   // Label 8119: @532471
     /*  532471 */   GIM_Try, /*On fail goto*//*Label 8120*/ GIMT_Encode4(532526), // Rule ID 14800 //
     /*  532476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  532479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  532495 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SVS anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  532495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS),
     /*  532498 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  532510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  532520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532524 */     GIR_RootConstrainSelectedInstOperands,
     /*  532525 */     // GIR_Coverage, 14800,
     /*  532525 */     GIR_EraseRootFromParent_Done,
     /*  532526 */   // Label 8120: @532526
     /*  532526 */   GIM_Try, /*On fail goto*//*Label 8121*/ GIMT_Encode4(532581), // Rule ID 14801 //
     /*  532531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  532534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  532550 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SVS anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  532550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS),
     /*  532553 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  532565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  532570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  532575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532579 */     GIR_RootConstrainSelectedInstOperands,
     /*  532580 */     // GIR_Coverage, 14801,
     /*  532580 */     GIR_EraseRootFromParent_Done,
     /*  532581 */   // Label 8121: @532581
     /*  532581 */   GIM_Try, /*On fail goto*//*Label 8122*/ GIMT_Encode4(532629), // Rule ID 14792 //
     /*  532586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  532589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  532605 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SADDR anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  532605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR),
     /*  532608 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  532615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532627 */     GIR_RootConstrainSelectedInstOperands,
     /*  532628 */     // GIR_Coverage, 14792,
     /*  532628 */     GIR_EraseRootFromParent_Done,
     /*  532629 */   // Label 8122: @532629
     /*  532629 */   GIM_Try, /*On fail goto*//*Label 8123*/ GIMT_Encode4(532677), // Rule ID 14793 //
     /*  532634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  532637 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  532653 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SADDR anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  532653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR),
     /*  532656 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  532663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532675 */     GIR_RootConstrainSelectedInstOperands,
     /*  532676 */     // GIR_Coverage, 14793,
     /*  532676 */     GIR_EraseRootFromParent_Done,
     /*  532677 */   // Label 8123: @532677
     /*  532677 */   GIM_Try, /*On fail goto*//*Label 8124*/ GIMT_Encode4(532725), // Rule ID 14794 //
     /*  532682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  532685 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532690 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  532701 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SADDR anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  532701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR),
     /*  532704 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  532711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532723 */     GIR_RootConstrainSelectedInstOperands,
     /*  532724 */     // GIR_Coverage, 14794,
     /*  532724 */     GIR_EraseRootFromParent_Done,
     /*  532725 */   // Label 8124: @532725
     /*  532725 */   GIM_Try, /*On fail goto*//*Label 8125*/ GIMT_Encode4(532773), // Rule ID 14795 //
     /*  532730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  532733 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  532749 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SADDR anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  532749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR),
     /*  532752 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  532759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532771 */     GIR_RootConstrainSelectedInstOperands,
     /*  532772 */     // GIR_Coverage, 14795,
     /*  532772 */     GIR_EraseRootFromParent_Done,
     /*  532773 */   // Label 8125: @532773
     /*  532773 */   GIM_Try, /*On fail goto*//*Label 8126*/ GIMT_Encode4(532821), // Rule ID 14796 //
     /*  532778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  532781 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  532797 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SADDR anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  532797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR),
     /*  532800 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  532807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532819 */     GIR_RootConstrainSelectedInstOperands,
     /*  532820 */     // GIR_Coverage, 14796,
     /*  532820 */     GIR_EraseRootFromParent_Done,
     /*  532821 */   // Label 8126: @532821
     /*  532821 */   GIM_Try, /*On fail goto*//*Label 8127*/ GIMT_Encode4(532869), // Rule ID 14787 //
     /*  532826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  532829 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  532845 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3 anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  532845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3),
     /*  532848 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532867 */     GIR_RootConstrainSelectedInstOperands,
     /*  532868 */     // GIR_Coverage, 14787,
     /*  532868 */     GIR_EraseRootFromParent_Done,
     /*  532869 */   // Label 8127: @532869
     /*  532869 */   GIM_Try, /*On fail goto*//*Label 8128*/ GIMT_Encode4(532917), // Rule ID 14788 //
     /*  532874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  532877 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532882 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532886 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  532893 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3 anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  532893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3),
     /*  532896 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532915 */     GIR_RootConstrainSelectedInstOperands,
     /*  532916 */     // GIR_Coverage, 14788,
     /*  532916 */     GIR_EraseRootFromParent_Done,
     /*  532917 */   // Label 8128: @532917
     /*  532917 */   GIM_Try, /*On fail goto*//*Label 8129*/ GIMT_Encode4(532965), // Rule ID 14789 //
     /*  532922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  532925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  532941 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3 anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  532941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3),
     /*  532944 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  532956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  532959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  532963 */     GIR_RootConstrainSelectedInstOperands,
     /*  532964 */     // GIR_Coverage, 14789,
     /*  532964 */     GIR_EraseRootFromParent_Done,
     /*  532965 */   // Label 8129: @532965
     /*  532965 */   GIM_Try, /*On fail goto*//*Label 8130*/ GIMT_Encode4(533013), // Rule ID 14790 //
     /*  532970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  532973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  532978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  532982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  532989 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3 anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  532989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3),
     /*  532992 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  532994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  532999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  533004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533011 */     GIR_RootConstrainSelectedInstOperands,
     /*  533012 */     // GIR_Coverage, 14790,
     /*  533012 */     GIR_EraseRootFromParent_Done,
     /*  533013 */   // Label 8130: @533013
     /*  533013 */   GIM_Try, /*On fail goto*//*Label 8131*/ GIMT_Encode4(533061), // Rule ID 14791 //
     /*  533018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  533021 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  533026 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533030 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  533037 */     // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3 anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  533037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3),
     /*  533040 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  533042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  533047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  533052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533055 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533059 */     GIR_RootConstrainSelectedInstOperands,
     /*  533060 */     // GIR_Coverage, 14791,
     /*  533060 */     GIR_EraseRootFromParent_Done,
     /*  533061 */   // Label 8131: @533061
     /*  533061 */   GIM_Try, /*On fail goto*//*Label 8132*/ GIMT_Encode4(533124), // Rule ID 16238 //
     /*  533066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  533069 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533087 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533090 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533122 */     GIR_RootConstrainSelectedInstOperands,
     /*  533123 */     // GIR_Coverage, 16238,
     /*  533123 */     GIR_EraseRootFromParent_Done,
     /*  533124 */   // Label 8132: @533124
     /*  533124 */   GIM_Try, /*On fail goto*//*Label 8133*/ GIMT_Encode4(533187), // Rule ID 16239 //
     /*  533129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  533132 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533150 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533153 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533185 */     GIR_RootConstrainSelectedInstOperands,
     /*  533186 */     // GIR_Coverage, 16239,
     /*  533186 */     GIR_EraseRootFromParent_Done,
     /*  533187 */   // Label 8133: @533187
     /*  533187 */   GIM_Try, /*On fail goto*//*Label 8134*/ GIMT_Encode4(533250), // Rule ID 16240 //
     /*  533192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  533195 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533206 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533213 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533216 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533248 */     GIR_RootConstrainSelectedInstOperands,
     /*  533249 */     // GIR_Coverage, 16240,
     /*  533249 */     GIR_EraseRootFromParent_Done,
     /*  533250 */   // Label 8134: @533250
     /*  533250 */   GIM_Try, /*On fail goto*//*Label 8135*/ GIMT_Encode4(533313), // Rule ID 16241 //
     /*  533255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  533258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533276 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533279 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533311 */     GIR_RootConstrainSelectedInstOperands,
     /*  533312 */     // GIR_Coverage, 16241,
     /*  533312 */     GIR_EraseRootFromParent_Done,
     /*  533313 */   // Label 8135: @533313
     /*  533313 */   GIM_Try, /*On fail goto*//*Label 8136*/ GIMT_Encode4(533376), // Rule ID 16242 //
     /*  533318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  533321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533339 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533342 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533374 */     GIR_RootConstrainSelectedInstOperands,
     /*  533375 */     // GIR_Coverage, 16242,
     /*  533375 */     GIR_EraseRootFromParent_Done,
     /*  533376 */   // Label 8136: @533376
     /*  533376 */   GIM_Try, /*On fail goto*//*Label 8137*/ GIMT_Encode4(533439), // Rule ID 16248 //
     /*  533381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  533384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533402 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  533405 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533437 */     GIR_RootConstrainSelectedInstOperands,
     /*  533438 */     // GIR_Coverage, 16248,
     /*  533438 */     GIR_EraseRootFromParent_Done,
     /*  533439 */   // Label 8137: @533439
     /*  533439 */   GIM_Try, /*On fail goto*//*Label 8138*/ GIMT_Encode4(533502), // Rule ID 16249 //
     /*  533444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  533447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533465 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  533468 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533500 */     GIR_RootConstrainSelectedInstOperands,
     /*  533501 */     // GIR_Coverage, 16249,
     /*  533501 */     GIR_EraseRootFromParent_Done,
     /*  533502 */   // Label 8138: @533502
     /*  533502 */   GIM_Try, /*On fail goto*//*Label 8139*/ GIMT_Encode4(533565), // Rule ID 16250 //
     /*  533507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  533510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533528 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  533531 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533563 */     GIR_RootConstrainSelectedInstOperands,
     /*  533564 */     // GIR_Coverage, 16250,
     /*  533564 */     GIR_EraseRootFromParent_Done,
     /*  533565 */   // Label 8139: @533565
     /*  533565 */   GIM_Try, /*On fail goto*//*Label 8140*/ GIMT_Encode4(533628), // Rule ID 16251 //
     /*  533570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  533573 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533591 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  533594 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533626 */     GIR_RootConstrainSelectedInstOperands,
     /*  533627 */     // GIR_Coverage, 16251,
     /*  533627 */     GIR_EraseRootFromParent_Done,
     /*  533628 */   // Label 8140: @533628
     /*  533628 */   GIM_Try, /*On fail goto*//*Label 8141*/ GIMT_Encode4(533691), // Rule ID 16252 //
     /*  533633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  533636 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533654 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  533657 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533689 */     GIR_RootConstrainSelectedInstOperands,
     /*  533690 */     // GIR_Coverage, 16252,
     /*  533690 */     GIR_EraseRootFromParent_Done,
     /*  533691 */   // Label 8141: @533691
     /*  533691 */   GIM_Try, /*On fail goto*//*Label 8142*/ GIMT_Encode4(533754), // Rule ID 16258 //
     /*  533696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  533699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533717 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533720 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533752 */     GIR_RootConstrainSelectedInstOperands,
     /*  533753 */     // GIR_Coverage, 16258,
     /*  533753 */     GIR_EraseRootFromParent_Done,
     /*  533754 */   // Label 8142: @533754
     /*  533754 */   GIM_Try, /*On fail goto*//*Label 8143*/ GIMT_Encode4(533817), // Rule ID 16259 //
     /*  533759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  533762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533780 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533783 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533815 */     GIR_RootConstrainSelectedInstOperands,
     /*  533816 */     // GIR_Coverage, 16259,
     /*  533816 */     GIR_EraseRootFromParent_Done,
     /*  533817 */   // Label 8143: @533817
     /*  533817 */   GIM_Try, /*On fail goto*//*Label 8144*/ GIMT_Encode4(533880), // Rule ID 16260 //
     /*  533822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  533825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533843 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533846 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533878 */     GIR_RootConstrainSelectedInstOperands,
     /*  533879 */     // GIR_Coverage, 16260,
     /*  533879 */     GIR_EraseRootFromParent_Done,
     /*  533880 */   // Label 8144: @533880
     /*  533880 */   GIM_Try, /*On fail goto*//*Label 8145*/ GIMT_Encode4(533943), // Rule ID 16261 //
     /*  533885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  533888 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533899 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533906 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533909 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  533941 */     GIR_RootConstrainSelectedInstOperands,
     /*  533942 */     // GIR_Coverage, 16261,
     /*  533942 */     GIR_EraseRootFromParent_Done,
     /*  533943 */   // Label 8145: @533943
     /*  533943 */   GIM_Try, /*On fail goto*//*Label 8146*/ GIMT_Encode4(534006), // Rule ID 16262 //
     /*  533948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  533951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  533958 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  533962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  533969 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  533969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
     /*  533972 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  533974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  533979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  533984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  533989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  533994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  533997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534004 */     GIR_RootConstrainSelectedInstOperands,
     /*  534005 */     // GIR_Coverage, 16262,
     /*  534005 */     GIR_EraseRootFromParent_Done,
     /*  534006 */   // Label 8146: @534006
     /*  534006 */   GIM_Try, /*On fail goto*//*Label 8147*/ GIMT_Encode4(534069), // Rule ID 16268 //
     /*  534011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  534014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  534021 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534025 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  534032 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  534032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  534035 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  534037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534067 */     GIR_RootConstrainSelectedInstOperands,
     /*  534068 */     // GIR_Coverage, 16268,
     /*  534068 */     GIR_EraseRootFromParent_Done,
     /*  534069 */   // Label 8147: @534069
     /*  534069 */   GIM_Try, /*On fail goto*//*Label 8148*/ GIMT_Encode4(534132), // Rule ID 16269 //
     /*  534074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  534077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  534084 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534088 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  534095 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  534095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  534098 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  534100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534130 */     GIR_RootConstrainSelectedInstOperands,
     /*  534131 */     // GIR_Coverage, 16269,
     /*  534131 */     GIR_EraseRootFromParent_Done,
     /*  534132 */   // Label 8148: @534132
     /*  534132 */   GIM_Try, /*On fail goto*//*Label 8149*/ GIMT_Encode4(534195), // Rule ID 16270 //
     /*  534137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  534140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  534147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  534158 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  534158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  534161 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  534163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534189 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534193 */     GIR_RootConstrainSelectedInstOperands,
     /*  534194 */     // GIR_Coverage, 16270,
     /*  534194 */     GIR_EraseRootFromParent_Done,
     /*  534195 */   // Label 8149: @534195
     /*  534195 */   GIM_Try, /*On fail goto*//*Label 8150*/ GIMT_Encode4(534258), // Rule ID 16271 //
     /*  534200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  534203 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  534210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  534221 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  534221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  534224 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  534226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534249 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534252 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534256 */     GIR_RootConstrainSelectedInstOperands,
     /*  534257 */     // GIR_Coverage, 16271,
     /*  534257 */     GIR_EraseRootFromParent_Done,
     /*  534258 */   // Label 8150: @534258
     /*  534258 */   GIM_Try, /*On fail goto*//*Label 8151*/ GIMT_Encode4(534321), // Rule ID 16272 //
     /*  534263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  534266 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  534273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  534284 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  534284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
     /*  534287 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  534289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534315 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534319 */     GIR_RootConstrainSelectedInstOperands,
     /*  534320 */     // GIR_Coverage, 16272,
     /*  534320 */     GIR_EraseRootFromParent_Done,
     /*  534321 */   // Label 8151: @534321
     /*  534321 */   GIM_Try, /*On fail goto*//*Label 8152*/ GIMT_Encode4(534382), // Rule ID 25961 //
     /*  534326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  534329 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534345 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN),
     /*  534348 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534380 */     GIR_RootConstrainSelectedInstOperands,
     /*  534381 */     // GIR_Coverage, 25961,
     /*  534381 */     GIR_EraseRootFromParent_Done,
     /*  534382 */   // Label 8152: @534382
     /*  534382 */   GIM_Try, /*On fail goto*//*Label 8153*/ GIMT_Encode4(534443), // Rule ID 25962 //
     /*  534387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  534390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534406 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN),
     /*  534409 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534441 */     GIR_RootConstrainSelectedInstOperands,
     /*  534442 */     // GIR_Coverage, 25962,
     /*  534442 */     GIR_EraseRootFromParent_Done,
     /*  534443 */   // Label 8153: @534443
     /*  534443 */   GIM_Try, /*On fail goto*//*Label 8154*/ GIMT_Encode4(534504), // Rule ID 25963 //
     /*  534448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  534451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534467 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN),
     /*  534470 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534502 */     GIR_RootConstrainSelectedInstOperands,
     /*  534503 */     // GIR_Coverage, 25963,
     /*  534503 */     GIR_EraseRootFromParent_Done,
     /*  534504 */   // Label 8154: @534504
     /*  534504 */   GIM_Try, /*On fail goto*//*Label 8155*/ GIMT_Encode4(534565), // Rule ID 25964 //
     /*  534509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  534512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534528 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN),
     /*  534531 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534563 */     GIR_RootConstrainSelectedInstOperands,
     /*  534564 */     // GIR_Coverage, 25964,
     /*  534564 */     GIR_EraseRootFromParent_Done,
     /*  534565 */   // Label 8155: @534565
     /*  534565 */   GIM_Try, /*On fail goto*//*Label 8156*/ GIMT_Encode4(534626), // Rule ID 25965 //
     /*  534570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  534573 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534589 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN),
     /*  534592 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534624 */     GIR_RootConstrainSelectedInstOperands,
     /*  534625 */     // GIR_Coverage, 25965,
     /*  534625 */     GIR_EraseRootFromParent_Done,
     /*  534626 */   // Label 8156: @534626
     /*  534626 */   GIM_Try, /*On fail goto*//*Label 8157*/ GIMT_Encode4(534687), // Rule ID 25971 //
     /*  534631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  534634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534650 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN),
     /*  534653 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534681 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534685 */     GIR_RootConstrainSelectedInstOperands,
     /*  534686 */     // GIR_Coverage, 25971,
     /*  534686 */     GIR_EraseRootFromParent_Done,
     /*  534687 */   // Label 8157: @534687
     /*  534687 */   GIM_Try, /*On fail goto*//*Label 8158*/ GIMT_Encode4(534748), // Rule ID 25972 //
     /*  534692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  534695 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534711 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN),
     /*  534714 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534746 */     GIR_RootConstrainSelectedInstOperands,
     /*  534747 */     // GIR_Coverage, 25972,
     /*  534747 */     GIR_EraseRootFromParent_Done,
     /*  534748 */   // Label 8158: @534748
     /*  534748 */   GIM_Try, /*On fail goto*//*Label 8159*/ GIMT_Encode4(534809), // Rule ID 25973 //
     /*  534753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  534756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534772 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN),
     /*  534775 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534807 */     GIR_RootConstrainSelectedInstOperands,
     /*  534808 */     // GIR_Coverage, 25973,
     /*  534808 */     GIR_EraseRootFromParent_Done,
     /*  534809 */   // Label 8159: @534809
     /*  534809 */   GIM_Try, /*On fail goto*//*Label 8160*/ GIMT_Encode4(534870), // Rule ID 25974 //
     /*  534814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  534817 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534833 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN),
     /*  534836 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534868 */     GIR_RootConstrainSelectedInstOperands,
     /*  534869 */     // GIR_Coverage, 25974,
     /*  534869 */     GIR_EraseRootFromParent_Done,
     /*  534870 */   // Label 8160: @534870
     /*  534870 */   GIM_Try, /*On fail goto*//*Label 8161*/ GIMT_Encode4(534931), // Rule ID 25975 //
     /*  534875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  534878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  534883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  534894 */     // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  534894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN),
     /*  534897 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  534899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  534904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  534914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  534919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534929 */     GIR_RootConstrainSelectedInstOperands,
     /*  534930 */     // GIR_Coverage, 25975,
     /*  534930 */     GIR_EraseRootFromParent_Done,
     /*  534931 */   // Label 8161: @534931
     /*  534931 */   GIM_Try, /*On fail goto*//*Label 8162*/ GIMT_Encode4(534989), // Rule ID 16233 //
     /*  534936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  534939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  534946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  534950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  534957 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  534957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  534960 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  534962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  534967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  534972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  534977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  534983 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  534987 */     GIR_RootConstrainSelectedInstOperands,
     /*  534988 */     // GIR_Coverage, 16233,
     /*  534988 */     GIR_EraseRootFromParent_Done,
     /*  534989 */   // Label 8162: @534989
     /*  534989 */   GIM_Try, /*On fail goto*//*Label 8163*/ GIMT_Encode4(535047), // Rule ID 16234 //
     /*  534994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  534997 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535004 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535008 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535015 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535018 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535045 */     GIR_RootConstrainSelectedInstOperands,
     /*  535046 */     // GIR_Coverage, 16234,
     /*  535046 */     GIR_EraseRootFromParent_Done,
     /*  535047 */   // Label 8163: @535047
     /*  535047 */   GIM_Try, /*On fail goto*//*Label 8164*/ GIMT_Encode4(535105), // Rule ID 16235 //
     /*  535052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  535055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535073 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535076 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535103 */     GIR_RootConstrainSelectedInstOperands,
     /*  535104 */     // GIR_Coverage, 16235,
     /*  535104 */     GIR_EraseRootFromParent_Done,
     /*  535105 */   // Label 8164: @535105
     /*  535105 */   GIM_Try, /*On fail goto*//*Label 8165*/ GIMT_Encode4(535163), // Rule ID 16236 //
     /*  535110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  535113 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535131 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535134 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535161 */     GIR_RootConstrainSelectedInstOperands,
     /*  535162 */     // GIR_Coverage, 16236,
     /*  535162 */     GIR_EraseRootFromParent_Done,
     /*  535163 */   // Label 8165: @535163
     /*  535163 */   GIM_Try, /*On fail goto*//*Label 8166*/ GIMT_Encode4(535221), // Rule ID 16237 //
     /*  535168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  535171 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535182 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535189 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535192 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535209 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535212 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535215 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535219 */     GIR_RootConstrainSelectedInstOperands,
     /*  535220 */     // GIR_Coverage, 16237,
     /*  535220 */     GIR_EraseRootFromParent_Done,
     /*  535221 */   // Label 8166: @535221
     /*  535221 */   GIM_Try, /*On fail goto*//*Label 8167*/ GIMT_Encode4(535279), // Rule ID 16243 //
     /*  535226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  535229 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535236 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535240 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535247 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535250 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535277 */     GIR_RootConstrainSelectedInstOperands,
     /*  535278 */     // GIR_Coverage, 16243,
     /*  535278 */     GIR_EraseRootFromParent_Done,
     /*  535279 */   // Label 8167: @535279
     /*  535279 */   GIM_Try, /*On fail goto*//*Label 8168*/ GIMT_Encode4(535337), // Rule ID 16244 //
     /*  535284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  535287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535305 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535308 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535335 */     GIR_RootConstrainSelectedInstOperands,
     /*  535336 */     // GIR_Coverage, 16244,
     /*  535336 */     GIR_EraseRootFromParent_Done,
     /*  535337 */   // Label 8168: @535337
     /*  535337 */   GIM_Try, /*On fail goto*//*Label 8169*/ GIMT_Encode4(535395), // Rule ID 16245 //
     /*  535342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  535345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535352 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535363 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535366 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535389 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535393 */     GIR_RootConstrainSelectedInstOperands,
     /*  535394 */     // GIR_Coverage, 16245,
     /*  535394 */     GIR_EraseRootFromParent_Done,
     /*  535395 */   // Label 8169: @535395
     /*  535395 */   GIM_Try, /*On fail goto*//*Label 8170*/ GIMT_Encode4(535453), // Rule ID 16246 //
     /*  535400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  535403 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535421 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535424 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535451 */     GIR_RootConstrainSelectedInstOperands,
     /*  535452 */     // GIR_Coverage, 16246,
     /*  535452 */     GIR_EraseRootFromParent_Done,
     /*  535453 */   // Label 8170: @535453
     /*  535453 */   GIM_Try, /*On fail goto*//*Label 8171*/ GIMT_Encode4(535511), // Rule ID 16247 //
     /*  535458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  535461 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535479 */     // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535482 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535509 */     GIR_RootConstrainSelectedInstOperands,
     /*  535510 */     // GIR_Coverage, 16247,
     /*  535510 */     GIR_EraseRootFromParent_Done,
     /*  535511 */   // Label 8171: @535511
     /*  535511 */   GIM_Try, /*On fail goto*//*Label 8172*/ GIMT_Encode4(535569), // Rule ID 16253 //
     /*  535516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  535519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535537 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535540 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535567 */     GIR_RootConstrainSelectedInstOperands,
     /*  535568 */     // GIR_Coverage, 16253,
     /*  535568 */     GIR_EraseRootFromParent_Done,
     /*  535569 */   // Label 8172: @535569
     /*  535569 */   GIM_Try, /*On fail goto*//*Label 8173*/ GIMT_Encode4(535627), // Rule ID 16254 //
     /*  535574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  535577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535595 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535598 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535621 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535625 */     GIR_RootConstrainSelectedInstOperands,
     /*  535626 */     // GIR_Coverage, 16254,
     /*  535626 */     GIR_EraseRootFromParent_Done,
     /*  535627 */   // Label 8173: @535627
     /*  535627 */   GIM_Try, /*On fail goto*//*Label 8174*/ GIMT_Encode4(535685), // Rule ID 16255 //
     /*  535632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  535635 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535653 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535656 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535673 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535683 */     GIR_RootConstrainSelectedInstOperands,
     /*  535684 */     // GIR_Coverage, 16255,
     /*  535684 */     GIR_EraseRootFromParent_Done,
     /*  535685 */   // Label 8174: @535685
     /*  535685 */   GIM_Try, /*On fail goto*//*Label 8175*/ GIMT_Encode4(535743), // Rule ID 16256 //
     /*  535690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  535693 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535711 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535714 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535741 */     GIR_RootConstrainSelectedInstOperands,
     /*  535742 */     // GIR_Coverage, 16256,
     /*  535742 */     GIR_EraseRootFromParent_Done,
     /*  535743 */   // Label 8175: @535743
     /*  535743 */   GIM_Try, /*On fail goto*//*Label 8176*/ GIMT_Encode4(535801), // Rule ID 16257 //
     /*  535748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  535751 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535769 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
     /*  535772 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535799 */     GIR_RootConstrainSelectedInstOperands,
     /*  535800 */     // GIR_Coverage, 16257,
     /*  535800 */     GIR_EraseRootFromParent_Done,
     /*  535801 */   // Label 8176: @535801
     /*  535801 */   GIM_Try, /*On fail goto*//*Label 8177*/ GIMT_Encode4(535859), // Rule ID 16263 //
     /*  535806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  535809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535816 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535820 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535827 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535830 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535853 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535857 */     GIR_RootConstrainSelectedInstOperands,
     /*  535858 */     // GIR_Coverage, 16263,
     /*  535858 */     GIR_EraseRootFromParent_Done,
     /*  535859 */   // Label 8177: @535859
     /*  535859 */   GIM_Try, /*On fail goto*//*Label 8178*/ GIMT_Encode4(535917), // Rule ID 16264 //
     /*  535864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  535867 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535885 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535888 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535915 */     GIR_RootConstrainSelectedInstOperands,
     /*  535916 */     // GIR_Coverage, 16264,
     /*  535916 */     GIR_EraseRootFromParent_Done,
     /*  535917 */   // Label 8178: @535917
     /*  535917 */   GIM_Try, /*On fail goto*//*Label 8179*/ GIMT_Encode4(535975), // Rule ID 16265 //
     /*  535922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  535925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535932 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535936 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  535943 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  535943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  535946 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  535948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  535953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  535958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  535963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  535969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  535973 */     GIR_RootConstrainSelectedInstOperands,
     /*  535974 */     // GIR_Coverage, 16265,
     /*  535974 */     GIR_EraseRootFromParent_Done,
     /*  535975 */   // Label 8179: @535975
     /*  535975 */   GIM_Try, /*On fail goto*//*Label 8180*/ GIMT_Encode4(536033), // Rule ID 16266 //
     /*  535980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  535983 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  535990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  535994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  536001 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  536001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  536004 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  536006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  536011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  536016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536031 */     GIR_RootConstrainSelectedInstOperands,
     /*  536032 */     // GIR_Coverage, 16266,
     /*  536032 */     GIR_EraseRootFromParent_Done,
     /*  536033 */   // Label 8180: @536033
     /*  536033 */   GIM_Try, /*On fail goto*//*Label 8181*/ GIMT_Encode4(536091), // Rule ID 16267 //
     /*  536038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  536041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  536059 */     // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  536059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
     /*  536062 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  536064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  536069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  536074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536089 */     GIR_RootConstrainSelectedInstOperands,
     /*  536090 */     // GIR_Coverage, 16267,
     /*  536090 */     GIR_EraseRootFromParent_Done,
     /*  536091 */   // Label 8181: @536091
     /*  536091 */   GIM_Try, /*On fail goto*//*Label 8182*/ GIMT_Encode4(536148), // Rule ID 12633 //
     /*  536096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  536099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536117 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR),
     /*  536120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536125 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536146 */     GIR_RootConstrainSelectedInstOperands,
     /*  536147 */     // GIR_Coverage, 12633,
     /*  536147 */     GIR_EraseRootFromParent_Done,
     /*  536148 */   // Label 8182: @536148
     /*  536148 */   GIM_Try, /*On fail goto*//*Label 8183*/ GIMT_Encode4(536205), // Rule ID 12634 //
     /*  536153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  536156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536174 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR),
     /*  536177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536182 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536203 */     GIR_RootConstrainSelectedInstOperands,
     /*  536204 */     // GIR_Coverage, 12634,
     /*  536204 */     GIR_EraseRootFromParent_Done,
     /*  536205 */   // Label 8183: @536205
     /*  536205 */   GIM_Try, /*On fail goto*//*Label 8184*/ GIMT_Encode4(536262), // Rule ID 12635 //
     /*  536210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  536213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536231 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR),
     /*  536234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536239 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536260 */     GIR_RootConstrainSelectedInstOperands,
     /*  536261 */     // GIR_Coverage, 12635,
     /*  536261 */     GIR_EraseRootFromParent_Done,
     /*  536262 */   // Label 8184: @536262
     /*  536262 */   GIM_Try, /*On fail goto*//*Label 8185*/ GIMT_Encode4(536319), // Rule ID 12636 //
     /*  536267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  536270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536288 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR),
     /*  536291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536296 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536317 */     GIR_RootConstrainSelectedInstOperands,
     /*  536318 */     // GIR_Coverage, 12636,
     /*  536318 */     GIR_EraseRootFromParent_Done,
     /*  536319 */   // Label 8185: @536319
     /*  536319 */   GIM_Try, /*On fail goto*//*Label 8186*/ GIMT_Encode4(536376), // Rule ID 12637 //
     /*  536324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  536327 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536345 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR),
     /*  536348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536353 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536374 */     GIR_RootConstrainSelectedInstOperands,
     /*  536375 */     // GIR_Coverage, 12637,
     /*  536375 */     GIR_EraseRootFromParent_Done,
     /*  536376 */   // Label 8186: @536376
     /*  536376 */   GIM_Try, /*On fail goto*//*Label 8187*/ GIMT_Encode4(536426), // Rule ID 12628 //
     /*  536381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  536384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  536402 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3),
     /*  536405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536410 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536420 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536424 */     GIR_RootConstrainSelectedInstOperands,
     /*  536425 */     // GIR_Coverage, 12628,
     /*  536425 */     GIR_EraseRootFromParent_Done,
     /*  536426 */   // Label 8187: @536426
     /*  536426 */   GIM_Try, /*On fail goto*//*Label 8188*/ GIMT_Encode4(536476), // Rule ID 12629 //
     /*  536431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  536434 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  536452 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3),
     /*  536455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536460 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536474 */     GIR_RootConstrainSelectedInstOperands,
     /*  536475 */     // GIR_Coverage, 12629,
     /*  536475 */     GIR_EraseRootFromParent_Done,
     /*  536476 */   // Label 8188: @536476
     /*  536476 */   GIM_Try, /*On fail goto*//*Label 8189*/ GIMT_Encode4(536526), // Rule ID 12630 //
     /*  536481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  536484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  536502 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3),
     /*  536505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536510 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536524 */     GIR_RootConstrainSelectedInstOperands,
     /*  536525 */     // GIR_Coverage, 12630,
     /*  536525 */     GIR_EraseRootFromParent_Done,
     /*  536526 */   // Label 8189: @536526
     /*  536526 */   GIM_Try, /*On fail goto*//*Label 8190*/ GIMT_Encode4(536576), // Rule ID 12631 //
     /*  536531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  536534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  536552 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3),
     /*  536555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536560 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536574 */     GIR_RootConstrainSelectedInstOperands,
     /*  536575 */     // GIR_Coverage, 12631,
     /*  536575 */     GIR_EraseRootFromParent_Done,
     /*  536576 */   // Label 8190: @536576
     /*  536576 */   GIM_Try, /*On fail goto*//*Label 8191*/ GIMT_Encode4(536626), // Rule ID 12632 //
     /*  536581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  536584 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  536591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  536602 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3),
     /*  536605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536610 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536624 */     GIR_RootConstrainSelectedInstOperands,
     /*  536625 */     // GIR_Coverage, 12632,
     /*  536625 */     GIR_EraseRootFromParent_Done,
     /*  536626 */   // Label 8191: @536626
     /*  536626 */   GIM_Try, /*On fail goto*//*Label 8192*/ GIMT_Encode4(536682), // Rule ID 10301 //
     /*  536631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  536634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536640 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536651 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3_SADDR),
     /*  536654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536659 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536676 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536680 */     GIR_RootConstrainSelectedInstOperands,
     /*  536681 */     // GIR_Coverage, 10301,
     /*  536681 */     GIR_EraseRootFromParent_Done,
     /*  536682 */   // Label 8192: @536682
     /*  536682 */   GIM_Try, /*On fail goto*//*Label 8193*/ GIMT_Encode4(536738), // Rule ID 10302 //
     /*  536687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  536690 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536707 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3_SADDR),
     /*  536710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536715 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536732 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536736 */     GIR_RootConstrainSelectedInstOperands,
     /*  536737 */     // GIR_Coverage, 10302,
     /*  536737 */     GIR_EraseRootFromParent_Done,
     /*  536738 */   // Label 8193: @536738
     /*  536738 */   GIM_Try, /*On fail goto*//*Label 8194*/ GIMT_Encode4(536794), // Rule ID 10303 //
     /*  536743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  536746 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536763 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3_SADDR),
     /*  536766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536771 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536792 */     GIR_RootConstrainSelectedInstOperands,
     /*  536793 */     // GIR_Coverage, 10303,
     /*  536793 */     GIR_EraseRootFromParent_Done,
     /*  536794 */   // Label 8194: @536794
     /*  536794 */   GIM_Try, /*On fail goto*//*Label 8195*/ GIMT_Encode4(536850), // Rule ID 10304 //
     /*  536799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  536802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536808 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536812 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536819 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3_SADDR),
     /*  536822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536827 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536848 */     GIR_RootConstrainSelectedInstOperands,
     /*  536849 */     // GIR_Coverage, 10304,
     /*  536849 */     GIR_EraseRootFromParent_Done,
     /*  536850 */   // Label 8195: @536850
     /*  536850 */   GIM_Try, /*On fail goto*//*Label 8196*/ GIMT_Encode4(536906), // Rule ID 10305 //
     /*  536855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  536858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  536875 */     // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  536875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3_SADDR),
     /*  536878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  536883 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  536890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  536895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  536900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536904 */     GIR_RootConstrainSelectedInstOperands,
     /*  536905 */     // GIR_Coverage, 10305,
     /*  536905 */     GIR_EraseRootFromParent_Done,
     /*  536906 */   // Label 8196: @536906
     /*  536906 */   GIM_Try, /*On fail goto*//*Label 8197*/ GIMT_Encode4(536955), // Rule ID 10296 //
     /*  536911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  536914 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536920 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  536931 */     // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3),
     /*  536934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536939 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  536953 */     GIR_RootConstrainSelectedInstOperands,
     /*  536954 */     // GIR_Coverage, 10296,
     /*  536954 */     GIR_EraseRootFromParent_Done,
     /*  536955 */   // Label 8197: @536955
     /*  536955 */   GIM_Try, /*On fail goto*//*Label 8198*/ GIMT_Encode4(537004), // Rule ID 10297 //
     /*  536960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  536963 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  536969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  536973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  536980 */     // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  536980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3),
     /*  536983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  536988 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  536990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  536995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  536998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537002 */     GIR_RootConstrainSelectedInstOperands,
     /*  537003 */     // GIR_Coverage, 10297,
     /*  537003 */     GIR_EraseRootFromParent_Done,
     /*  537004 */   // Label 8198: @537004
     /*  537004 */   GIM_Try, /*On fail goto*//*Label 8199*/ GIMT_Encode4(537053), // Rule ID 10298 //
     /*  537009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  537012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  537018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  537029 */     // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  537029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3),
     /*  537032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  537037 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  537039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537051 */     GIR_RootConstrainSelectedInstOperands,
     /*  537052 */     // GIR_Coverage, 10298,
     /*  537052 */     GIR_EraseRootFromParent_Done,
     /*  537053 */   // Label 8199: @537053
     /*  537053 */   GIM_Try, /*On fail goto*//*Label 8200*/ GIMT_Encode4(537102), // Rule ID 10299 //
     /*  537058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  537061 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  537067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  537078 */     // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  537078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3),
     /*  537081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  537086 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  537088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537100 */     GIR_RootConstrainSelectedInstOperands,
     /*  537101 */     // GIR_Coverage, 10299,
     /*  537101 */     GIR_EraseRootFromParent_Done,
     /*  537102 */   // Label 8200: @537102
     /*  537102 */   GIM_Try, /*On fail goto*//*Label 8201*/ GIMT_Encode4(537151), // Rule ID 10300 //
     /*  537107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  537110 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  537116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537120 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  537127 */     // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15622:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  537127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3),
     /*  537130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  537135 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  537137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537149 */     GIR_RootConstrainSelectedInstOperands,
     /*  537150 */     // GIR_Coverage, 10300,
     /*  537150 */     GIR_EraseRootFromParent_Done,
     /*  537151 */   // Label 8201: @537151
     /*  537151 */   GIM_Reject,
     /*  537152 */ // Label 8066: @537152
     /*  537152 */ GIM_Reject,
     /*  537153 */ // Label 5872: @537153
     /*  537153 */ GIM_Try, /*On fail goto*//*Label 8202*/ GIMT_Encode4(545932),
     /*  537158 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  537161 */   GIM_Try, /*On fail goto*//*Label 8203*/ GIMT_Encode4(537222), // Rule ID 30033 //
     /*  537166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  537169 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537173 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537178 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537187 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537198 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537206 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537220 */     GIR_RootConstrainSelectedInstOperands,
     /*  537221 */     // GIR_Coverage, 30033,
     /*  537221 */     GIR_EraseRootFromParent_Done,
     /*  537222 */   // Label 8203: @537222
     /*  537222 */   GIM_Try, /*On fail goto*//*Label 8204*/ GIMT_Encode4(537283), // Rule ID 30034 //
     /*  537227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  537230 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537239 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537248 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537259 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537267 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537281 */     GIR_RootConstrainSelectedInstOperands,
     /*  537282 */     // GIR_Coverage, 30034,
     /*  537282 */     GIR_EraseRootFromParent_Done,
     /*  537283 */   // Label 8204: @537283
     /*  537283 */   GIM_Try, /*On fail goto*//*Label 8205*/ GIMT_Encode4(537344), // Rule ID 30035 //
     /*  537288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  537291 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537295 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537300 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537309 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537320 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537328 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537342 */     GIR_RootConstrainSelectedInstOperands,
     /*  537343 */     // GIR_Coverage, 30035,
     /*  537343 */     GIR_EraseRootFromParent_Done,
     /*  537344 */   // Label 8205: @537344
     /*  537344 */   GIM_Try, /*On fail goto*//*Label 8206*/ GIMT_Encode4(537405), // Rule ID 30036 //
     /*  537349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  537352 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537356 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537370 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537374 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537381 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537389 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537399 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537403 */     GIR_RootConstrainSelectedInstOperands,
     /*  537404 */     // GIR_Coverage, 30036,
     /*  537404 */     GIR_EraseRootFromParent_Done,
     /*  537405 */   // Label 8206: @537405
     /*  537405 */   GIM_Try, /*On fail goto*//*Label 8207*/ GIMT_Encode4(537466), // Rule ID 30037 //
     /*  537410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  537413 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537417 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537431 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537442 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537450 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537464 */     GIR_RootConstrainSelectedInstOperands,
     /*  537465 */     // GIR_Coverage, 30037,
     /*  537465 */     GIR_EraseRootFromParent_Done,
     /*  537466 */   // Label 8207: @537466
     /*  537466 */   GIM_Try, /*On fail goto*//*Label 8208*/ GIMT_Encode4(537527), // Rule ID 30053 //
     /*  537471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  537474 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537478 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537492 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537503 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537511 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537525 */     GIR_RootConstrainSelectedInstOperands,
     /*  537526 */     // GIR_Coverage, 30053,
     /*  537526 */     GIR_EraseRootFromParent_Done,
     /*  537527 */   // Label 8208: @537527
     /*  537527 */   GIM_Try, /*On fail goto*//*Label 8209*/ GIMT_Encode4(537588), // Rule ID 30054 //
     /*  537532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  537535 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537553 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537564 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537572 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537586 */     GIR_RootConstrainSelectedInstOperands,
     /*  537587 */     // GIR_Coverage, 30054,
     /*  537587 */     GIR_EraseRootFromParent_Done,
     /*  537588 */   // Label 8209: @537588
     /*  537588 */   GIM_Try, /*On fail goto*//*Label 8210*/ GIMT_Encode4(537649), // Rule ID 30055 //
     /*  537593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  537596 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537605 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537614 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537625 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537633 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537647 */     GIR_RootConstrainSelectedInstOperands,
     /*  537648 */     // GIR_Coverage, 30055,
     /*  537648 */     GIR_EraseRootFromParent_Done,
     /*  537649 */   // Label 8210: @537649
     /*  537649 */   GIM_Try, /*On fail goto*//*Label 8211*/ GIMT_Encode4(537710), // Rule ID 30056 //
     /*  537654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  537657 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537675 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537686 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537694 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537708 */     GIR_RootConstrainSelectedInstOperands,
     /*  537709 */     // GIR_Coverage, 30056,
     /*  537709 */     GIR_EraseRootFromParent_Done,
     /*  537710 */   // Label 8211: @537710
     /*  537710 */   GIM_Try, /*On fail goto*//*Label 8212*/ GIMT_Encode4(537771), // Rule ID 30057 //
     /*  537715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  537718 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537722 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537736 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  537740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537747 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537755 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537769 */     GIR_RootConstrainSelectedInstOperands,
     /*  537770 */     // GIR_Coverage, 30057,
     /*  537770 */     GIR_EraseRootFromParent_Done,
     /*  537771 */   // Label 8212: @537771
     /*  537771 */   GIM_Try, /*On fail goto*//*Label 8213*/ GIMT_Encode4(537827), // Rule ID 29693 //
     /*  537776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  537779 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537788 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  537792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537803 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537811 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537825 */     GIR_RootConstrainSelectedInstOperands,
     /*  537826 */     // GIR_Coverage, 29693,
     /*  537826 */     GIR_EraseRootFromParent_Done,
     /*  537827 */   // Label 8213: @537827
     /*  537827 */   GIM_Try, /*On fail goto*//*Label 8214*/ GIMT_Encode4(537883), // Rule ID 29694 //
     /*  537832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  537835 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537844 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  537848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537859 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537867 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537881 */     GIR_RootConstrainSelectedInstOperands,
     /*  537882 */     // GIR_Coverage, 29694,
     /*  537882 */     GIR_EraseRootFromParent_Done,
     /*  537883 */   // Label 8214: @537883
     /*  537883 */   GIM_Try, /*On fail goto*//*Label 8215*/ GIMT_Encode4(537939), // Rule ID 29695 //
     /*  537888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  537891 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537900 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  537904 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537915 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537923 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537937 */     GIR_RootConstrainSelectedInstOperands,
     /*  537938 */     // GIR_Coverage, 29695,
     /*  537938 */     GIR_EraseRootFromParent_Done,
     /*  537939 */   // Label 8215: @537939
     /*  537939 */   GIM_Try, /*On fail goto*//*Label 8216*/ GIMT_Encode4(537995), // Rule ID 29696 //
     /*  537944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  537947 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  537951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  537956 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  537960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  537964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  537971 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  537971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  537974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  537979 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  537981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  537986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  537989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  537993 */     GIR_RootConstrainSelectedInstOperands,
     /*  537994 */     // GIR_Coverage, 29696,
     /*  537994 */     GIR_EraseRootFromParent_Done,
     /*  537995 */   // Label 8216: @537995
     /*  537995 */   GIM_Try, /*On fail goto*//*Label 8217*/ GIMT_Encode4(538051), // Rule ID 29697 //
     /*  538000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  538003 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  538007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538012 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538027 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  538030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538035 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538049 */     GIR_RootConstrainSelectedInstOperands,
     /*  538050 */     // GIR_Coverage, 29697,
     /*  538050 */     GIR_EraseRootFromParent_Done,
     /*  538051 */   // Label 8217: @538051
     /*  538051 */   GIM_Try, /*On fail goto*//*Label 8218*/ GIMT_Encode4(538107), // Rule ID 29713 //
     /*  538056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  538059 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  538063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538068 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538083 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  538086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538091 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538105 */     GIR_RootConstrainSelectedInstOperands,
     /*  538106 */     // GIR_Coverage, 29713,
     /*  538106 */     GIR_EraseRootFromParent_Done,
     /*  538107 */   // Label 8218: @538107
     /*  538107 */   GIM_Try, /*On fail goto*//*Label 8219*/ GIMT_Encode4(538163), // Rule ID 29714 //
     /*  538112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  538115 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  538119 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538124 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538139 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  538142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538147 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538161 */     GIR_RootConstrainSelectedInstOperands,
     /*  538162 */     // GIR_Coverage, 29714,
     /*  538162 */     GIR_EraseRootFromParent_Done,
     /*  538163 */   // Label 8219: @538163
     /*  538163 */   GIM_Try, /*On fail goto*//*Label 8220*/ GIMT_Encode4(538219), // Rule ID 29715 //
     /*  538168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  538171 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  538175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538180 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538195 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  538198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538203 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538213 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538217 */     GIR_RootConstrainSelectedInstOperands,
     /*  538218 */     // GIR_Coverage, 29715,
     /*  538218 */     GIR_EraseRootFromParent_Done,
     /*  538219 */   // Label 8220: @538219
     /*  538219 */   GIM_Try, /*On fail goto*//*Label 8221*/ GIMT_Encode4(538275), // Rule ID 29716 //
     /*  538224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  538227 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  538231 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538236 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538244 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538251 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  538254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538259 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538269 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538273 */     GIR_RootConstrainSelectedInstOperands,
     /*  538274 */     // GIR_Coverage, 29716,
     /*  538274 */     GIR_EraseRootFromParent_Done,
     /*  538275 */   // Label 8221: @538275
     /*  538275 */   GIM_Try, /*On fail goto*//*Label 8222*/ GIMT_Encode4(538331), // Rule ID 29717 //
     /*  538280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  538283 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  538287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538292 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538307 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
     /*  538310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538315 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538329 */     GIR_RootConstrainSelectedInstOperands,
     /*  538330 */     // GIR_Coverage, 29717,
     /*  538330 */     GIR_EraseRootFromParent_Done,
     /*  538331 */   // Label 8222: @538331
     /*  538331 */   GIM_Try, /*On fail goto*//*Label 8223*/ GIMT_Encode4(538388), // Rule ID 30038 //
     /*  538336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  538339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538353 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538364 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538372 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538386 */     GIR_RootConstrainSelectedInstOperands,
     /*  538387 */     // GIR_Coverage, 30038,
     /*  538387 */     GIR_EraseRootFromParent_Done,
     /*  538388 */   // Label 8223: @538388
     /*  538388 */   GIM_Try, /*On fail goto*//*Label 8224*/ GIMT_Encode4(538445), // Rule ID 30039 //
     /*  538393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  538396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538410 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538421 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538429 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538443 */     GIR_RootConstrainSelectedInstOperands,
     /*  538444 */     // GIR_Coverage, 30039,
     /*  538444 */     GIR_EraseRootFromParent_Done,
     /*  538445 */   // Label 8224: @538445
     /*  538445 */   GIM_Try, /*On fail goto*//*Label 8225*/ GIMT_Encode4(538502), // Rule ID 30040 //
     /*  538450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  538453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538467 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538478 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538486 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538500 */     GIR_RootConstrainSelectedInstOperands,
     /*  538501 */     // GIR_Coverage, 30040,
     /*  538501 */     GIR_EraseRootFromParent_Done,
     /*  538502 */   // Label 8225: @538502
     /*  538502 */   GIM_Try, /*On fail goto*//*Label 8226*/ GIMT_Encode4(538559), // Rule ID 30041 //
     /*  538507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  538510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538524 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538535 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538543 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538553 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538557 */     GIR_RootConstrainSelectedInstOperands,
     /*  538558 */     // GIR_Coverage, 30041,
     /*  538558 */     GIR_EraseRootFromParent_Done,
     /*  538559 */   // Label 8226: @538559
     /*  538559 */   GIM_Try, /*On fail goto*//*Label 8227*/ GIMT_Encode4(538616), // Rule ID 30042 //
     /*  538564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  538567 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538581 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538592 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538600 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538614 */     GIR_RootConstrainSelectedInstOperands,
     /*  538615 */     // GIR_Coverage, 30042,
     /*  538615 */     GIR_EraseRootFromParent_Done,
     /*  538616 */   // Label 8227: @538616
     /*  538616 */   GIM_Try, /*On fail goto*//*Label 8228*/ GIMT_Encode4(538673), // Rule ID 30058 //
     /*  538621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  538624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538629 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538638 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538642 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538649 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538657 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538671 */     GIR_RootConstrainSelectedInstOperands,
     /*  538672 */     // GIR_Coverage, 30058,
     /*  538672 */     GIR_EraseRootFromParent_Done,
     /*  538673 */   // Label 8228: @538673
     /*  538673 */   GIM_Try, /*On fail goto*//*Label 8229*/ GIMT_Encode4(538730), // Rule ID 30059 //
     /*  538678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  538681 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538686 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538695 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538706 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538714 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538728 */     GIR_RootConstrainSelectedInstOperands,
     /*  538729 */     // GIR_Coverage, 30059,
     /*  538729 */     GIR_EraseRootFromParent_Done,
     /*  538730 */   // Label 8229: @538730
     /*  538730 */   GIM_Try, /*On fail goto*//*Label 8230*/ GIMT_Encode4(538787), // Rule ID 30060 //
     /*  538735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  538738 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538752 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538763 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538771 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538785 */     GIR_RootConstrainSelectedInstOperands,
     /*  538786 */     // GIR_Coverage, 30060,
     /*  538786 */     GIR_EraseRootFromParent_Done,
     /*  538787 */   // Label 8230: @538787
     /*  538787 */   GIM_Try, /*On fail goto*//*Label 8231*/ GIMT_Encode4(538844), // Rule ID 30061 //
     /*  538792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  538795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538809 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538820 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538828 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538842 */     GIR_RootConstrainSelectedInstOperands,
     /*  538843 */     // GIR_Coverage, 30061,
     /*  538843 */     GIR_EraseRootFromParent_Done,
     /*  538844 */   // Label 8231: @538844
     /*  538844 */   GIM_Try, /*On fail goto*//*Label 8232*/ GIMT_Encode4(538901), // Rule ID 30062 //
     /*  538849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  538852 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538857 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538866 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  538870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538877 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538885 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538899 */     GIR_RootConstrainSelectedInstOperands,
     /*  538900 */     // GIR_Coverage, 30062,
     /*  538900 */     GIR_EraseRootFromParent_Done,
     /*  538901 */   // Label 8232: @538901
     /*  538901 */   GIM_Try, /*On fail goto*//*Label 8233*/ GIMT_Encode4(538953), // Rule ID 29698 //
     /*  538906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  538909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538914 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538929 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538937 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  538951 */     GIR_RootConstrainSelectedInstOperands,
     /*  538952 */     // GIR_Coverage, 29698,
     /*  538952 */     GIR_EraseRootFromParent_Done,
     /*  538953 */   // Label 8233: @538953
     /*  538953 */   GIM_Try, /*On fail goto*//*Label 8234*/ GIMT_Encode4(539005), // Rule ID 29699 //
     /*  538958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  538961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  538966 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  538970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  538974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  538981 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  538981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  538984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  538989 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  538991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  538996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  538999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539003 */     GIR_RootConstrainSelectedInstOperands,
     /*  539004 */     // GIR_Coverage, 29699,
     /*  539004 */     GIR_EraseRootFromParent_Done,
     /*  539005 */   // Label 8234: @539005
     /*  539005 */   GIM_Try, /*On fail goto*//*Label 8235*/ GIMT_Encode4(539057), // Rule ID 29700 //
     /*  539010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  539013 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539018 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539026 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539033 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539041 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539055 */     GIR_RootConstrainSelectedInstOperands,
     /*  539056 */     // GIR_Coverage, 29700,
     /*  539056 */     GIR_EraseRootFromParent_Done,
     /*  539057 */   // Label 8235: @539057
     /*  539057 */   GIM_Try, /*On fail goto*//*Label 8236*/ GIMT_Encode4(539109), // Rule ID 29701 //
     /*  539062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  539065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539070 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539074 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539078 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539085 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539093 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539107 */     GIR_RootConstrainSelectedInstOperands,
     /*  539108 */     // GIR_Coverage, 29701,
     /*  539108 */     GIR_EraseRootFromParent_Done,
     /*  539109 */   // Label 8236: @539109
     /*  539109 */   GIM_Try, /*On fail goto*//*Label 8237*/ GIMT_Encode4(539161), // Rule ID 29702 //
     /*  539114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  539117 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539122 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539137 */     // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539145 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539152 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539155 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539159 */     GIR_RootConstrainSelectedInstOperands,
     /*  539160 */     // GIR_Coverage, 29702,
     /*  539160 */     GIR_EraseRootFromParent_Done,
     /*  539161 */   // Label 8237: @539161
     /*  539161 */   GIM_Try, /*On fail goto*//*Label 8238*/ GIMT_Encode4(539213), // Rule ID 29718 //
     /*  539166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  539169 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539174 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539182 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539189 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539197 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539211 */     GIR_RootConstrainSelectedInstOperands,
     /*  539212 */     // GIR_Coverage, 29718,
     /*  539212 */     GIR_EraseRootFromParent_Done,
     /*  539213 */   // Label 8238: @539213
     /*  539213 */   GIM_Try, /*On fail goto*//*Label 8239*/ GIMT_Encode4(539265), // Rule ID 29719 //
     /*  539218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  539221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539226 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539241 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539249 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539263 */     GIR_RootConstrainSelectedInstOperands,
     /*  539264 */     // GIR_Coverage, 29719,
     /*  539264 */     GIR_EraseRootFromParent_Done,
     /*  539265 */   // Label 8239: @539265
     /*  539265 */   GIM_Try, /*On fail goto*//*Label 8240*/ GIMT_Encode4(539317), // Rule ID 29720 //
     /*  539270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  539273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539278 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539293 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539301 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539315 */     GIR_RootConstrainSelectedInstOperands,
     /*  539316 */     // GIR_Coverage, 29720,
     /*  539316 */     GIR_EraseRootFromParent_Done,
     /*  539317 */   // Label 8240: @539317
     /*  539317 */   GIM_Try, /*On fail goto*//*Label 8241*/ GIMT_Encode4(539369), // Rule ID 29721 //
     /*  539322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  539325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539330 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539345 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539353 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539367 */     GIR_RootConstrainSelectedInstOperands,
     /*  539368 */     // GIR_Coverage, 29721,
     /*  539368 */     GIR_EraseRootFromParent_Done,
     /*  539369 */   // Label 8241: @539369
     /*  539369 */   GIM_Try, /*On fail goto*//*Label 8242*/ GIMT_Encode4(539421), // Rule ID 29722 //
     /*  539374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  539377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  539382 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
     /*  539386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  539397 */     // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  539397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
     /*  539400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  539405 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  539407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  539412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  539415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539419 */     GIR_RootConstrainSelectedInstOperands,
     /*  539420 */     // GIR_Coverage, 29722,
     /*  539420 */     GIR_EraseRootFromParent_Done,
     /*  539421 */   // Label 8242: @539421
     /*  539421 */   GIM_Try, /*On fail goto*//*Label 8243*/ GIMT_Encode4(539476), // Rule ID 14437 //
     /*  539426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  539429 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539445 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539448 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539474 */     GIR_RootConstrainSelectedInstOperands,
     /*  539475 */     // GIR_Coverage, 14437,
     /*  539475 */     GIR_EraseRootFromParent_Done,
     /*  539476 */   // Label 8243: @539476
     /*  539476 */   GIM_Try, /*On fail goto*//*Label 8244*/ GIMT_Encode4(539531), // Rule ID 14438 //
     /*  539481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  539484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539500 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539503 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539529 */     GIR_RootConstrainSelectedInstOperands,
     /*  539530 */     // GIR_Coverage, 14438,
     /*  539530 */     GIR_EraseRootFromParent_Done,
     /*  539531 */   // Label 8244: @539531
     /*  539531 */   GIM_Try, /*On fail goto*//*Label 8245*/ GIMT_Encode4(539586), // Rule ID 14439 //
     /*  539536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  539539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539544 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539548 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539555 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539558 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539580 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539584 */     GIR_RootConstrainSelectedInstOperands,
     /*  539585 */     // GIR_Coverage, 14439,
     /*  539585 */     GIR_EraseRootFromParent_Done,
     /*  539586 */   // Label 8245: @539586
     /*  539586 */   GIM_Try, /*On fail goto*//*Label 8246*/ GIMT_Encode4(539641), // Rule ID 14440 //
     /*  539591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  539594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539610 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539613 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539639 */     GIR_RootConstrainSelectedInstOperands,
     /*  539640 */     // GIR_Coverage, 14440,
     /*  539640 */     GIR_EraseRootFromParent_Done,
     /*  539641 */   // Label 8246: @539641
     /*  539641 */   GIM_Try, /*On fail goto*//*Label 8247*/ GIMT_Encode4(539696), // Rule ID 14441 //
     /*  539646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  539649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539665 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539668 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539694 */     GIR_RootConstrainSelectedInstOperands,
     /*  539695 */     // GIR_Coverage, 14441,
     /*  539695 */     GIR_EraseRootFromParent_Done,
     /*  539696 */   // Label 8247: @539696
     /*  539696 */   GIM_Try, /*On fail goto*//*Label 8248*/ GIMT_Encode4(539751), // Rule ID 14467 //
     /*  539701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  539704 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539720 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539723 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539749 */     GIR_RootConstrainSelectedInstOperands,
     /*  539750 */     // GIR_Coverage, 14467,
     /*  539750 */     GIR_EraseRootFromParent_Done,
     /*  539751 */   // Label 8248: @539751
     /*  539751 */   GIM_Try, /*On fail goto*//*Label 8249*/ GIMT_Encode4(539806), // Rule ID 14468 //
     /*  539756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  539759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539764 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539768 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539775 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539778 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539804 */     GIR_RootConstrainSelectedInstOperands,
     /*  539805 */     // GIR_Coverage, 14468,
     /*  539805 */     GIR_EraseRootFromParent_Done,
     /*  539806 */   // Label 8249: @539806
     /*  539806 */   GIM_Try, /*On fail goto*//*Label 8250*/ GIMT_Encode4(539861), // Rule ID 14469 //
     /*  539811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  539814 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539830 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539833 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539859 */     GIR_RootConstrainSelectedInstOperands,
     /*  539860 */     // GIR_Coverage, 14469,
     /*  539860 */     GIR_EraseRootFromParent_Done,
     /*  539861 */   // Label 8250: @539861
     /*  539861 */   GIM_Try, /*On fail goto*//*Label 8251*/ GIMT_Encode4(539916), // Rule ID 14470 //
     /*  539866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  539869 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539885 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539888 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539914 */     GIR_RootConstrainSelectedInstOperands,
     /*  539915 */     // GIR_Coverage, 14470,
     /*  539915 */     GIR_EraseRootFromParent_Done,
     /*  539916 */   // Label 8251: @539916
     /*  539916 */   GIM_Try, /*On fail goto*//*Label 8252*/ GIMT_Encode4(539971), // Rule ID 14471 //
     /*  539921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  539924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  539940 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  539940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
     /*  539943 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  539945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  539950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  539955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  539960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  539965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  539969 */     GIR_RootConstrainSelectedInstOperands,
     /*  539970 */     // GIR_Coverage, 14471,
     /*  539970 */     GIR_EraseRootFromParent_Done,
     /*  539971 */   // Label 8252: @539971
     /*  539971 */   GIM_Try, /*On fail goto*//*Label 8253*/ GIMT_Encode4(540019), // Rule ID 14432 //
     /*  539976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  539979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  539984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  539988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  539995 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  539995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  539998 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540017 */     GIR_RootConstrainSelectedInstOperands,
     /*  540018 */     // GIR_Coverage, 14432,
     /*  540018 */     GIR_EraseRootFromParent_Done,
     /*  540019 */   // Label 8253: @540019
     /*  540019 */   GIM_Try, /*On fail goto*//*Label 8254*/ GIMT_Encode4(540067), // Rule ID 14433 //
     /*  540024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  540027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540032 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540043 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540046 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540065 */     GIR_RootConstrainSelectedInstOperands,
     /*  540066 */     // GIR_Coverage, 14433,
     /*  540066 */     GIR_EraseRootFromParent_Done,
     /*  540067 */   // Label 8254: @540067
     /*  540067 */   GIM_Try, /*On fail goto*//*Label 8255*/ GIMT_Encode4(540115), // Rule ID 14434 //
     /*  540072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  540075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540091 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540094 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540113 */     GIR_RootConstrainSelectedInstOperands,
     /*  540114 */     // GIR_Coverage, 14434,
     /*  540114 */     GIR_EraseRootFromParent_Done,
     /*  540115 */   // Label 8255: @540115
     /*  540115 */   GIM_Try, /*On fail goto*//*Label 8256*/ GIMT_Encode4(540163), // Rule ID 14435 //
     /*  540120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  540123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540139 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540142 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540161 */     GIR_RootConstrainSelectedInstOperands,
     /*  540162 */     // GIR_Coverage, 14435,
     /*  540162 */     GIR_EraseRootFromParent_Done,
     /*  540163 */   // Label 8256: @540163
     /*  540163 */   GIM_Try, /*On fail goto*//*Label 8257*/ GIMT_Encode4(540211), // Rule ID 14436 //
     /*  540168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  540171 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540180 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540187 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540190 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540209 */     GIR_RootConstrainSelectedInstOperands,
     /*  540210 */     // GIR_Coverage, 14436,
     /*  540210 */     GIR_EraseRootFromParent_Done,
     /*  540211 */   // Label 8257: @540211
     /*  540211 */   GIM_Try, /*On fail goto*//*Label 8258*/ GIMT_Encode4(540259), // Rule ID 14462 //
     /*  540216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  540219 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540235 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540238 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540257 */     GIR_RootConstrainSelectedInstOperands,
     /*  540258 */     // GIR_Coverage, 14462,
     /*  540258 */     GIR_EraseRootFromParent_Done,
     /*  540259 */   // Label 8258: @540259
     /*  540259 */   GIM_Try, /*On fail goto*//*Label 8259*/ GIMT_Encode4(540307), // Rule ID 14463 //
     /*  540264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  540267 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540283 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540286 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540305 */     GIR_RootConstrainSelectedInstOperands,
     /*  540306 */     // GIR_Coverage, 14463,
     /*  540306 */     GIR_EraseRootFromParent_Done,
     /*  540307 */   // Label 8259: @540307
     /*  540307 */   GIM_Try, /*On fail goto*//*Label 8260*/ GIMT_Encode4(540355), // Rule ID 14464 //
     /*  540312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  540315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540320 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540324 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540331 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540334 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540353 */     GIR_RootConstrainSelectedInstOperands,
     /*  540354 */     // GIR_Coverage, 14464,
     /*  540354 */     GIR_EraseRootFromParent_Done,
     /*  540355 */   // Label 8260: @540355
     /*  540355 */   GIM_Try, /*On fail goto*//*Label 8261*/ GIMT_Encode4(540403), // Rule ID 14465 //
     /*  540360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  540363 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540372 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540379 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540382 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540401 */     GIR_RootConstrainSelectedInstOperands,
     /*  540402 */     // GIR_Coverage, 14465,
     /*  540402 */     GIR_EraseRootFromParent_Done,
     /*  540403 */   // Label 8261: @540403
     /*  540403 */   GIM_Try, /*On fail goto*//*Label 8262*/ GIMT_Encode4(540451), // Rule ID 14466 //
     /*  540408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  540411 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  540427 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  540427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
     /*  540430 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  540437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540449 */     GIR_RootConstrainSelectedInstOperands,
     /*  540450 */     // GIR_Coverage, 14466,
     /*  540450 */     GIR_EraseRootFromParent_Done,
     /*  540451 */   // Label 8262: @540451
     /*  540451 */   GIM_Try, /*On fail goto*//*Label 8263*/ GIMT_Encode4(540499), // Rule ID 14427 //
     /*  540456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  540459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540475 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540478 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540497 */     GIR_RootConstrainSelectedInstOperands,
     /*  540498 */     // GIR_Coverage, 14427,
     /*  540498 */     GIR_EraseRootFromParent_Done,
     /*  540499 */   // Label 8263: @540499
     /*  540499 */   GIM_Try, /*On fail goto*//*Label 8264*/ GIMT_Encode4(540547), // Rule ID 14428 //
     /*  540504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  540507 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540512 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540516 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540523 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540526 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540545 */     GIR_RootConstrainSelectedInstOperands,
     /*  540546 */     // GIR_Coverage, 14428,
     /*  540546 */     GIR_EraseRootFromParent_Done,
     /*  540547 */   // Label 8264: @540547
     /*  540547 */   GIM_Try, /*On fail goto*//*Label 8265*/ GIMT_Encode4(540595), // Rule ID 14429 //
     /*  540552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  540555 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540571 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540574 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540593 */     GIR_RootConstrainSelectedInstOperands,
     /*  540594 */     // GIR_Coverage, 14429,
     /*  540594 */     GIR_EraseRootFromParent_Done,
     /*  540595 */   // Label 8265: @540595
     /*  540595 */   GIM_Try, /*On fail goto*//*Label 8266*/ GIMT_Encode4(540643), // Rule ID 14430 //
     /*  540600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  540603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540608 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540612 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540619 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540622 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540637 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540641 */     GIR_RootConstrainSelectedInstOperands,
     /*  540642 */     // GIR_Coverage, 14430,
     /*  540642 */     GIR_EraseRootFromParent_Done,
     /*  540643 */   // Label 8266: @540643
     /*  540643 */   GIM_Try, /*On fail goto*//*Label 8267*/ GIMT_Encode4(540691), // Rule ID 14431 //
     /*  540648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  540651 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540667 */     // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540670 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540689 */     GIR_RootConstrainSelectedInstOperands,
     /*  540690 */     // GIR_Coverage, 14431,
     /*  540690 */     GIR_EraseRootFromParent_Done,
     /*  540691 */   // Label 8267: @540691
     /*  540691 */   GIM_Try, /*On fail goto*//*Label 8268*/ GIMT_Encode4(540739), // Rule ID 14457 //
     /*  540696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  540699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540715 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540718 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540737 */     GIR_RootConstrainSelectedInstOperands,
     /*  540738 */     // GIR_Coverage, 14457,
     /*  540738 */     GIR_EraseRootFromParent_Done,
     /*  540739 */   // Label 8268: @540739
     /*  540739 */   GIM_Try, /*On fail goto*//*Label 8269*/ GIMT_Encode4(540787), // Rule ID 14458 //
     /*  540744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  540747 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540763 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540766 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540785 */     GIR_RootConstrainSelectedInstOperands,
     /*  540786 */     // GIR_Coverage, 14458,
     /*  540786 */     GIR_EraseRootFromParent_Done,
     /*  540787 */   // Label 8269: @540787
     /*  540787 */   GIM_Try, /*On fail goto*//*Label 8270*/ GIMT_Encode4(540835), // Rule ID 14459 //
     /*  540792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  540795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540804 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540811 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540814 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540833 */     GIR_RootConstrainSelectedInstOperands,
     /*  540834 */     // GIR_Coverage, 14459,
     /*  540834 */     GIR_EraseRootFromParent_Done,
     /*  540835 */   // Label 8270: @540835
     /*  540835 */   GIM_Try, /*On fail goto*//*Label 8271*/ GIMT_Encode4(540883), // Rule ID 14460 //
     /*  540840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  540843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540859 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540862 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540881 */     GIR_RootConstrainSelectedInstOperands,
     /*  540882 */     // GIR_Coverage, 14460,
     /*  540882 */     GIR_EraseRootFromParent_Done,
     /*  540883 */   // Label 8271: @540883
     /*  540883 */   GIM_Try, /*On fail goto*//*Label 8272*/ GIMT_Encode4(540931), // Rule ID 14461 //
     /*  540888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  540891 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  540896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  540907 */     // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  540907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
     /*  540910 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  540912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  540917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  540922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540929 */     GIR_RootConstrainSelectedInstOperands,
     /*  540930 */     // GIR_Coverage, 14461,
     /*  540930 */     GIR_EraseRootFromParent_Done,
     /*  540931 */   // Label 8272: @540931
     /*  540931 */   GIM_Try, /*On fail goto*//*Label 8273*/ GIMT_Encode4(540994), // Rule ID 16138 //
     /*  540936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  540939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  540946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  540950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  540957 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  540957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  540960 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  540962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  540967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  540972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  540977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  540982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  540988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  540992 */     GIR_RootConstrainSelectedInstOperands,
     /*  540993 */     // GIR_Coverage, 16138,
     /*  540993 */     GIR_EraseRootFromParent_Done,
     /*  540994 */   // Label 8273: @540994
     /*  540994 */   GIM_Try, /*On fail goto*//*Label 8274*/ GIMT_Encode4(541057), // Rule ID 16139 //
     /*  540999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  541002 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541020 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541023 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541055 */     GIR_RootConstrainSelectedInstOperands,
     /*  541056 */     // GIR_Coverage, 16139,
     /*  541056 */     GIR_EraseRootFromParent_Done,
     /*  541057 */   // Label 8274: @541057
     /*  541057 */   GIM_Try, /*On fail goto*//*Label 8275*/ GIMT_Encode4(541120), // Rule ID 16140 //
     /*  541062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  541065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541083 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541086 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541118 */     GIR_RootConstrainSelectedInstOperands,
     /*  541119 */     // GIR_Coverage, 16140,
     /*  541119 */     GIR_EraseRootFromParent_Done,
     /*  541120 */   // Label 8275: @541120
     /*  541120 */   GIM_Try, /*On fail goto*//*Label 8276*/ GIMT_Encode4(541183), // Rule ID 16141 //
     /*  541125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  541128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541146 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541149 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541181 */     GIR_RootConstrainSelectedInstOperands,
     /*  541182 */     // GIR_Coverage, 16141,
     /*  541182 */     GIR_EraseRootFromParent_Done,
     /*  541183 */   // Label 8276: @541183
     /*  541183 */   GIM_Try, /*On fail goto*//*Label 8277*/ GIMT_Encode4(541246), // Rule ID 16142 //
     /*  541188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  541191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541202 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541209 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541212 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541244 */     GIR_RootConstrainSelectedInstOperands,
     /*  541245 */     // GIR_Coverage, 16142,
     /*  541245 */     GIR_EraseRootFromParent_Done,
     /*  541246 */   // Label 8277: @541246
     /*  541246 */   GIM_Try, /*On fail goto*//*Label 8278*/ GIMT_Encode4(541309), // Rule ID 16148 //
     /*  541251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  541254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541265 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541272 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541275 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541307 */     GIR_RootConstrainSelectedInstOperands,
     /*  541308 */     // GIR_Coverage, 16148,
     /*  541308 */     GIR_EraseRootFromParent_Done,
     /*  541309 */   // Label 8278: @541309
     /*  541309 */   GIM_Try, /*On fail goto*//*Label 8279*/ GIMT_Encode4(541372), // Rule ID 16149 //
     /*  541314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  541317 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541335 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541338 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541370 */     GIR_RootConstrainSelectedInstOperands,
     /*  541371 */     // GIR_Coverage, 16149,
     /*  541371 */     GIR_EraseRootFromParent_Done,
     /*  541372 */   // Label 8279: @541372
     /*  541372 */   GIM_Try, /*On fail goto*//*Label 8280*/ GIMT_Encode4(541435), // Rule ID 16150 //
     /*  541377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  541380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541398 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541401 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541433 */     GIR_RootConstrainSelectedInstOperands,
     /*  541434 */     // GIR_Coverage, 16150,
     /*  541434 */     GIR_EraseRootFromParent_Done,
     /*  541435 */   // Label 8280: @541435
     /*  541435 */   GIM_Try, /*On fail goto*//*Label 8281*/ GIMT_Encode4(541498), // Rule ID 16151 //
     /*  541440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  541443 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541461 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541464 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541492 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541496 */     GIR_RootConstrainSelectedInstOperands,
     /*  541497 */     // GIR_Coverage, 16151,
     /*  541497 */     GIR_EraseRootFromParent_Done,
     /*  541498 */   // Label 8281: @541498
     /*  541498 */   GIM_Try, /*On fail goto*//*Label 8282*/ GIMT_Encode4(541561), // Rule ID 16152 //
     /*  541503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  541506 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541524 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541527 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541559 */     GIR_RootConstrainSelectedInstOperands,
     /*  541560 */     // GIR_Coverage, 16152,
     /*  541560 */     GIR_EraseRootFromParent_Done,
     /*  541561 */   // Label 8282: @541561
     /*  541561 */   GIM_Try, /*On fail goto*//*Label 8283*/ GIMT_Encode4(541624), // Rule ID 16158 //
     /*  541566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  541569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541576 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541580 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541587 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541590 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541622 */     GIR_RootConstrainSelectedInstOperands,
     /*  541623 */     // GIR_Coverage, 16158,
     /*  541623 */     GIR_EraseRootFromParent_Done,
     /*  541624 */   // Label 8283: @541624
     /*  541624 */   GIM_Try, /*On fail goto*//*Label 8284*/ GIMT_Encode4(541687), // Rule ID 16159 //
     /*  541629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  541632 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541650 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541653 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541681 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541685 */     GIR_RootConstrainSelectedInstOperands,
     /*  541686 */     // GIR_Coverage, 16159,
     /*  541686 */     GIR_EraseRootFromParent_Done,
     /*  541687 */   // Label 8284: @541687
     /*  541687 */   GIM_Try, /*On fail goto*//*Label 8285*/ GIMT_Encode4(541750), // Rule ID 16160 //
     /*  541692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  541695 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541706 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541713 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541716 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541748 */     GIR_RootConstrainSelectedInstOperands,
     /*  541749 */     // GIR_Coverage, 16160,
     /*  541749 */     GIR_EraseRootFromParent_Done,
     /*  541750 */   // Label 8285: @541750
     /*  541750 */   GIM_Try, /*On fail goto*//*Label 8286*/ GIMT_Encode4(541813), // Rule ID 16161 //
     /*  541755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  541758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541776 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541779 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541811 */     GIR_RootConstrainSelectedInstOperands,
     /*  541812 */     // GIR_Coverage, 16161,
     /*  541812 */     GIR_EraseRootFromParent_Done,
     /*  541813 */   // Label 8286: @541813
     /*  541813 */   GIM_Try, /*On fail goto*//*Label 8287*/ GIMT_Encode4(541876), // Rule ID 16162 //
     /*  541818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  541821 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541839 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
     /*  541842 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541874 */     GIR_RootConstrainSelectedInstOperands,
     /*  541875 */     // GIR_Coverage, 16162,
     /*  541875 */     GIR_EraseRootFromParent_Done,
     /*  541876 */   // Label 8287: @541876
     /*  541876 */   GIM_Try, /*On fail goto*//*Label 8288*/ GIMT_Encode4(541939), // Rule ID 16168 //
     /*  541881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  541884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541902 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541905 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  541937 */     GIR_RootConstrainSelectedInstOperands,
     /*  541938 */     // GIR_Coverage, 16168,
     /*  541938 */     GIR_EraseRootFromParent_Done,
     /*  541939 */   // Label 8288: @541939
     /*  541939 */   GIM_Try, /*On fail goto*//*Label 8289*/ GIMT_Encode4(542002), // Rule ID 16169 //
     /*  541944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  541947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  541954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  541958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  541965 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  541965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  541968 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  541970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  541975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  541980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  541985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  541990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  541996 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542000 */     GIR_RootConstrainSelectedInstOperands,
     /*  542001 */     // GIR_Coverage, 16169,
     /*  542001 */     GIR_EraseRootFromParent_Done,
     /*  542002 */   // Label 8289: @542002
     /*  542002 */   GIM_Try, /*On fail goto*//*Label 8290*/ GIMT_Encode4(542065), // Rule ID 16170 //
     /*  542007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  542010 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542017 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  542028 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  542031 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  542038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  542048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  542053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542063 */     GIR_RootConstrainSelectedInstOperands,
     /*  542064 */     // GIR_Coverage, 16170,
     /*  542064 */     GIR_EraseRootFromParent_Done,
     /*  542065 */   // Label 8290: @542065
     /*  542065 */   GIM_Try, /*On fail goto*//*Label 8291*/ GIMT_Encode4(542128), // Rule ID 16171 //
     /*  542070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  542073 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  542091 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  542094 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  542101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  542111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  542116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542126 */     GIR_RootConstrainSelectedInstOperands,
     /*  542127 */     // GIR_Coverage, 16171,
     /*  542127 */     GIR_EraseRootFromParent_Done,
     /*  542128 */   // Label 8291: @542128
     /*  542128 */   GIM_Try, /*On fail goto*//*Label 8292*/ GIMT_Encode4(542191), // Rule ID 16172 //
     /*  542133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  542136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  542154 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
     /*  542157 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  542164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  542174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  542179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542185 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542189 */     GIR_RootConstrainSelectedInstOperands,
     /*  542190 */     // GIR_Coverage, 16172,
     /*  542190 */     GIR_EraseRootFromParent_Done,
     /*  542191 */   // Label 8292: @542191
     /*  542191 */   GIM_Try, /*On fail goto*//*Label 8293*/ GIMT_Encode4(542308), // Rule ID 29448 //
     /*  542196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  542199 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  542203 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  542208 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  542219 */     // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  542219 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  542222 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  542226 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  542231 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  542237 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  542242 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  542247 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  542250 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  542254 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  542259 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  542265 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  542270 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  542275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  542278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  542283 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  542286 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  542289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  542294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  542299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542306 */     GIR_RootConstrainSelectedInstOperands,
     /*  542307 */     // GIR_Coverage, 29448,
     /*  542307 */     GIR_EraseRootFromParent_Done,
     /*  542308 */   // Label 8293: @542308
     /*  542308 */   GIM_Try, /*On fail goto*//*Label 8294*/ GIMT_Encode4(542425), // Rule ID 29460 //
     /*  542313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
     /*  542316 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  542320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  542325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  542336 */     // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  542336 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  542339 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  542343 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  542348 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  542354 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  542359 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  542364 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  542367 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  542371 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  542376 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  542382 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  542387 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  542392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
     /*  542395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  542400 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  542403 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  542406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  542411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  542416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542423 */     GIR_RootConstrainSelectedInstOperands,
     /*  542424 */     // GIR_Coverage, 29460,
     /*  542424 */     GIR_EraseRootFromParent_Done,
     /*  542425 */   // Label 8294: @542425
     /*  542425 */   GIM_Try, /*On fail goto*//*Label 8295*/ GIMT_Encode4(542483), // Rule ID 16133 //
     /*  542430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  542433 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542451 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  542454 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542481 */     GIR_RootConstrainSelectedInstOperands,
     /*  542482 */     // GIR_Coverage, 16133,
     /*  542482 */     GIR_EraseRootFromParent_Done,
     /*  542483 */   // Label 8295: @542483
     /*  542483 */   GIM_Try, /*On fail goto*//*Label 8296*/ GIMT_Encode4(542541), // Rule ID 16134 //
     /*  542488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  542491 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542509 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  542512 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542539 */     GIR_RootConstrainSelectedInstOperands,
     /*  542540 */     // GIR_Coverage, 16134,
     /*  542540 */     GIR_EraseRootFromParent_Done,
     /*  542541 */   // Label 8296: @542541
     /*  542541 */   GIM_Try, /*On fail goto*//*Label 8297*/ GIMT_Encode4(542599), // Rule ID 16135 //
     /*  542546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  542549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542556 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542560 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542567 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  542570 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542597 */     GIR_RootConstrainSelectedInstOperands,
     /*  542598 */     // GIR_Coverage, 16135,
     /*  542598 */     GIR_EraseRootFromParent_Done,
     /*  542599 */   // Label 8297: @542599
     /*  542599 */   GIM_Try, /*On fail goto*//*Label 8298*/ GIMT_Encode4(542657), // Rule ID 16136 //
     /*  542604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  542607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542625 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  542628 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542655 */     GIR_RootConstrainSelectedInstOperands,
     /*  542656 */     // GIR_Coverage, 16136,
     /*  542656 */     GIR_EraseRootFromParent_Done,
     /*  542657 */   // Label 8298: @542657
     /*  542657 */   GIM_Try, /*On fail goto*//*Label 8299*/ GIMT_Encode4(542715), // Rule ID 16137 //
     /*  542662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  542665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542683 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  542686 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542713 */     GIR_RootConstrainSelectedInstOperands,
     /*  542714 */     // GIR_Coverage, 16137,
     /*  542714 */     GIR_EraseRootFromParent_Done,
     /*  542715 */   // Label 8299: @542715
     /*  542715 */   GIM_Try, /*On fail goto*//*Label 8300*/ GIMT_Encode4(542773), // Rule ID 16143 //
     /*  542720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  542723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542741 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  542744 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542771 */     GIR_RootConstrainSelectedInstOperands,
     /*  542772 */     // GIR_Coverage, 16143,
     /*  542772 */     GIR_EraseRootFromParent_Done,
     /*  542773 */   // Label 8300: @542773
     /*  542773 */   GIM_Try, /*On fail goto*//*Label 8301*/ GIMT_Encode4(542831), // Rule ID 16144 //
     /*  542778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  542781 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542799 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  542802 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542829 */     GIR_RootConstrainSelectedInstOperands,
     /*  542830 */     // GIR_Coverage, 16144,
     /*  542830 */     GIR_EraseRootFromParent_Done,
     /*  542831 */   // Label 8301: @542831
     /*  542831 */   GIM_Try, /*On fail goto*//*Label 8302*/ GIMT_Encode4(542889), // Rule ID 16145 //
     /*  542836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  542839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542857 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  542860 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542887 */     GIR_RootConstrainSelectedInstOperands,
     /*  542888 */     // GIR_Coverage, 16145,
     /*  542888 */     GIR_EraseRootFromParent_Done,
     /*  542889 */   // Label 8302: @542889
     /*  542889 */   GIM_Try, /*On fail goto*//*Label 8303*/ GIMT_Encode4(542947), // Rule ID 16146 //
     /*  542894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  542897 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542904 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542915 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  542918 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542941 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  542945 */     GIR_RootConstrainSelectedInstOperands,
     /*  542946 */     // GIR_Coverage, 16146,
     /*  542946 */     GIR_EraseRootFromParent_Done,
     /*  542947 */   // Label 8303: @542947
     /*  542947 */   GIM_Try, /*On fail goto*//*Label 8304*/ GIMT_Encode4(543005), // Rule ID 16147 //
     /*  542952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  542955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  542962 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  542966 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  542973 */     // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  542973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  542976 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  542978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  542983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  542988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  542993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  542999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543003 */     GIR_RootConstrainSelectedInstOperands,
     /*  543004 */     // GIR_Coverage, 16147,
     /*  543004 */     GIR_EraseRootFromParent_Done,
     /*  543005 */   // Label 8304: @543005
     /*  543005 */   GIM_Try, /*On fail goto*//*Label 8305*/ GIMT_Encode4(543063), // Rule ID 16153 //
     /*  543010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  543013 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543031 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  543034 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543061 */     GIR_RootConstrainSelectedInstOperands,
     /*  543062 */     // GIR_Coverage, 16153,
     /*  543062 */     GIR_EraseRootFromParent_Done,
     /*  543063 */   // Label 8305: @543063
     /*  543063 */   GIM_Try, /*On fail goto*//*Label 8306*/ GIMT_Encode4(543121), // Rule ID 16154 //
     /*  543068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  543071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543089 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  543092 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543119 */     GIR_RootConstrainSelectedInstOperands,
     /*  543120 */     // GIR_Coverage, 16154,
     /*  543120 */     GIR_EraseRootFromParent_Done,
     /*  543121 */   // Label 8306: @543121
     /*  543121 */   GIM_Try, /*On fail goto*//*Label 8307*/ GIMT_Encode4(543179), // Rule ID 16155 //
     /*  543126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  543129 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543147 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  543150 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543177 */     GIR_RootConstrainSelectedInstOperands,
     /*  543178 */     // GIR_Coverage, 16155,
     /*  543178 */     GIR_EraseRootFromParent_Done,
     /*  543179 */   // Label 8307: @543179
     /*  543179 */   GIM_Try, /*On fail goto*//*Label 8308*/ GIMT_Encode4(543237), // Rule ID 16156 //
     /*  543184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  543187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543194 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543205 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  543208 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543231 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543235 */     GIR_RootConstrainSelectedInstOperands,
     /*  543236 */     // GIR_Coverage, 16156,
     /*  543236 */     GIR_EraseRootFromParent_Done,
     /*  543237 */   // Label 8308: @543237
     /*  543237 */   GIM_Try, /*On fail goto*//*Label 8309*/ GIMT_Encode4(543295), // Rule ID 16157 //
     /*  543242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  543245 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543263 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
     /*  543266 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543283 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543293 */     GIR_RootConstrainSelectedInstOperands,
     /*  543294 */     // GIR_Coverage, 16157,
     /*  543294 */     GIR_EraseRootFromParent_Done,
     /*  543295 */   // Label 8309: @543295
     /*  543295 */   GIM_Try, /*On fail goto*//*Label 8310*/ GIMT_Encode4(543353), // Rule ID 16163 //
     /*  543300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  543303 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543321 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  543324 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543347 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543351 */     GIR_RootConstrainSelectedInstOperands,
     /*  543352 */     // GIR_Coverage, 16163,
     /*  543352 */     GIR_EraseRootFromParent_Done,
     /*  543353 */   // Label 8310: @543353
     /*  543353 */   GIM_Try, /*On fail goto*//*Label 8311*/ GIMT_Encode4(543411), // Rule ID 16164 //
     /*  543358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  543361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543372 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543379 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  543382 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543402 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543409 */     GIR_RootConstrainSelectedInstOperands,
     /*  543410 */     // GIR_Coverage, 16164,
     /*  543410 */     GIR_EraseRootFromParent_Done,
     /*  543411 */   // Label 8311: @543411
     /*  543411 */   GIM_Try, /*On fail goto*//*Label 8312*/ GIMT_Encode4(543469), // Rule ID 16165 //
     /*  543416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  543419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543437 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  543440 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543467 */     GIR_RootConstrainSelectedInstOperands,
     /*  543468 */     // GIR_Coverage, 16165,
     /*  543468 */     GIR_EraseRootFromParent_Done,
     /*  543469 */   // Label 8312: @543469
     /*  543469 */   GIM_Try, /*On fail goto*//*Label 8313*/ GIMT_Encode4(543527), // Rule ID 16166 //
     /*  543474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  543477 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543495 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  543498 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543525 */     GIR_RootConstrainSelectedInstOperands,
     /*  543526 */     // GIR_Coverage, 16166,
     /*  543526 */     GIR_EraseRootFromParent_Done,
     /*  543527 */   // Label 8313: @543527
     /*  543527 */   GIM_Try, /*On fail goto*//*Label 8314*/ GIMT_Encode4(543585), // Rule ID 16167 //
     /*  543532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  543535 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  543553 */     // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  543553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
     /*  543556 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  543558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  543563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  543568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543583 */     GIR_RootConstrainSelectedInstOperands,
     /*  543584 */     // GIR_Coverage, 16167,
     /*  543584 */     GIR_EraseRootFromParent_Done,
     /*  543585 */   // Label 8314: @543585
     /*  543585 */   GIM_Try, /*On fail goto*//*Label 8315*/ GIMT_Encode4(543698), // Rule ID 29454 //
     /*  543590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  543593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  543598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  543609 */     // (st v4i16:{ *:[v4i16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  543609 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  543612 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  543616 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  543621 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  543627 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  543632 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  543637 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  543640 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  543644 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  543649 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  543655 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  543660 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  543665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  543668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  543673 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  543676 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  543679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  543684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  543689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543696 */     GIR_RootConstrainSelectedInstOperands,
     /*  543697 */     // GIR_Coverage, 29454,
     /*  543697 */     GIR_EraseRootFromParent_Done,
     /*  543698 */   // Label 8315: @543698
     /*  543698 */   GIM_Try, /*On fail goto*//*Label 8316*/ GIMT_Encode4(543811), // Rule ID 29466 //
     /*  543703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  543706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  543711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
     /*  543722 */     // (st v4f16:{ *:[v4f16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  543722 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  543725 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  543729 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  543734 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
     /*  543740 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  543745 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  543750 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  543753 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  543757 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  543762 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
     /*  543768 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  543773 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  543778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
     /*  543781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  543786 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  543789 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  543792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  543797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  543802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  543805 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543809 */     GIR_RootConstrainSelectedInstOperands,
     /*  543810 */     // GIR_Coverage, 29466,
     /*  543810 */     GIR_EraseRootFromParent_Done,
     /*  543811 */   // Label 8316: @543811
     /*  543811 */   GIM_Try, /*On fail goto*//*Label 8317*/ GIMT_Encode4(543868), // Rule ID 12353 //
     /*  543816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  543819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  543837 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  543837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  543840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  543845 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  543847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  543852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  543862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543866 */     GIR_RootConstrainSelectedInstOperands,
     /*  543867 */     // GIR_Coverage, 12353,
     /*  543867 */     GIR_EraseRootFromParent_Done,
     /*  543868 */   // Label 8317: @543868
     /*  543868 */   GIM_Try, /*On fail goto*//*Label 8318*/ GIMT_Encode4(543925), // Rule ID 12354 //
     /*  543873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  543876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  543894 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  543894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  543897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  543902 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  543904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  543909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  543919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543923 */     GIR_RootConstrainSelectedInstOperands,
     /*  543924 */     // GIR_Coverage, 12354,
     /*  543924 */     GIR_EraseRootFromParent_Done,
     /*  543925 */   // Label 8318: @543925
     /*  543925 */   GIM_Try, /*On fail goto*//*Label 8319*/ GIMT_Encode4(543982), // Rule ID 12355 //
     /*  543930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  543933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543940 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  543944 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  543951 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  543951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  543954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  543959 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  543961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  543966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  543971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  543976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  543980 */     GIR_RootConstrainSelectedInstOperands,
     /*  543981 */     // GIR_Coverage, 12355,
     /*  543981 */     GIR_EraseRootFromParent_Done,
     /*  543982 */   // Label 8319: @543982
     /*  543982 */   GIM_Try, /*On fail goto*//*Label 8320*/ GIMT_Encode4(544039), // Rule ID 12356 //
     /*  543987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  543990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  543997 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544008 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544016 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544033 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544037 */     GIR_RootConstrainSelectedInstOperands,
     /*  544038 */     // GIR_Coverage, 12356,
     /*  544038 */     GIR_EraseRootFromParent_Done,
     /*  544039 */   // Label 8320: @544039
     /*  544039 */   GIM_Try, /*On fail goto*//*Label 8321*/ GIMT_Encode4(544096), // Rule ID 12357 //
     /*  544044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  544047 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544065 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544073 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544094 */     GIR_RootConstrainSelectedInstOperands,
     /*  544095 */     // GIR_Coverage, 12357,
     /*  544095 */     GIR_EraseRootFromParent_Done,
     /*  544096 */   // Label 8321: @544096
     /*  544096 */   GIM_Try, /*On fail goto*//*Label 8322*/ GIMT_Encode4(544153), // Rule ID 12373 //
     /*  544101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  544104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544122 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544130 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544151 */     GIR_RootConstrainSelectedInstOperands,
     /*  544152 */     // GIR_Coverage, 12373,
     /*  544152 */     GIR_EraseRootFromParent_Done,
     /*  544153 */   // Label 8322: @544153
     /*  544153 */   GIM_Try, /*On fail goto*//*Label 8323*/ GIMT_Encode4(544210), // Rule ID 12374 //
     /*  544158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  544161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544179 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544187 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544208 */     GIR_RootConstrainSelectedInstOperands,
     /*  544209 */     // GIR_Coverage, 12374,
     /*  544209 */     GIR_EraseRootFromParent_Done,
     /*  544210 */   // Label 8323: @544210
     /*  544210 */   GIM_Try, /*On fail goto*//*Label 8324*/ GIMT_Encode4(544267), // Rule ID 12375 //
     /*  544215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  544218 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544236 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544244 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544265 */     GIR_RootConstrainSelectedInstOperands,
     /*  544266 */     // GIR_Coverage, 12375,
     /*  544266 */     GIR_EraseRootFromParent_Done,
     /*  544267 */   // Label 8324: @544267
     /*  544267 */   GIM_Try, /*On fail goto*//*Label 8325*/ GIMT_Encode4(544324), // Rule ID 12376 //
     /*  544272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  544275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544293 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544301 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544322 */     GIR_RootConstrainSelectedInstOperands,
     /*  544323 */     // GIR_Coverage, 12376,
     /*  544323 */     GIR_EraseRootFromParent_Done,
     /*  544324 */   // Label 8325: @544324
     /*  544324 */   GIM_Try, /*On fail goto*//*Label 8326*/ GIMT_Encode4(544381), // Rule ID 12377 //
     /*  544329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  544332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544339 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544350 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
     /*  544353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544358 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544375 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544379 */     GIR_RootConstrainSelectedInstOperands,
     /*  544380 */     // GIR_Coverage, 12377,
     /*  544380 */     GIR_EraseRootFromParent_Done,
     /*  544381 */   // Label 8326: @544381
     /*  544381 */   GIM_Try, /*On fail goto*//*Label 8327*/ GIMT_Encode4(544431), // Rule ID 12348 //
     /*  544386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  544389 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544407 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544415 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544429 */     GIR_RootConstrainSelectedInstOperands,
     /*  544430 */     // GIR_Coverage, 12348,
     /*  544430 */     GIR_EraseRootFromParent_Done,
     /*  544431 */   // Label 8327: @544431
     /*  544431 */   GIM_Try, /*On fail goto*//*Label 8328*/ GIMT_Encode4(544481), // Rule ID 12349 //
     /*  544436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  544439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544446 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544450 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544457 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544465 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544475 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544479 */     GIR_RootConstrainSelectedInstOperands,
     /*  544480 */     // GIR_Coverage, 12349,
     /*  544480 */     GIR_EraseRootFromParent_Done,
     /*  544481 */   // Label 8328: @544481
     /*  544481 */   GIM_Try, /*On fail goto*//*Label 8329*/ GIMT_Encode4(544531), // Rule ID 12350 //
     /*  544486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  544489 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544507 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544515 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544529 */     GIR_RootConstrainSelectedInstOperands,
     /*  544530 */     // GIR_Coverage, 12350,
     /*  544530 */     GIR_EraseRootFromParent_Done,
     /*  544531 */   // Label 8329: @544531
     /*  544531 */   GIM_Try, /*On fail goto*//*Label 8330*/ GIMT_Encode4(544581), // Rule ID 12351 //
     /*  544536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  544539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544557 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544565 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544579 */     GIR_RootConstrainSelectedInstOperands,
     /*  544580 */     // GIR_Coverage, 12351,
     /*  544580 */     GIR_EraseRootFromParent_Done,
     /*  544581 */   // Label 8330: @544581
     /*  544581 */   GIM_Try, /*On fail goto*//*Label 8331*/ GIMT_Encode4(544631), // Rule ID 12352 //
     /*  544586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  544589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544607 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544615 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544629 */     GIR_RootConstrainSelectedInstOperands,
     /*  544630 */     // GIR_Coverage, 12352,
     /*  544630 */     GIR_EraseRootFromParent_Done,
     /*  544631 */   // Label 8331: @544631
     /*  544631 */   GIM_Try, /*On fail goto*//*Label 8332*/ GIMT_Encode4(544681), // Rule ID 12368 //
     /*  544636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  544639 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544657 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544665 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544679 */     GIR_RootConstrainSelectedInstOperands,
     /*  544680 */     // GIR_Coverage, 12368,
     /*  544680 */     GIR_EraseRootFromParent_Done,
     /*  544681 */   // Label 8332: @544681
     /*  544681 */   GIM_Try, /*On fail goto*//*Label 8333*/ GIMT_Encode4(544731), // Rule ID 12369 //
     /*  544686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  544689 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544707 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544715 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544729 */     GIR_RootConstrainSelectedInstOperands,
     /*  544730 */     // GIR_Coverage, 12369,
     /*  544730 */     GIR_EraseRootFromParent_Done,
     /*  544731 */   // Label 8333: @544731
     /*  544731 */   GIM_Try, /*On fail goto*//*Label 8334*/ GIMT_Encode4(544781), // Rule ID 12370 //
     /*  544736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  544739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544757 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544765 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544779 */     GIR_RootConstrainSelectedInstOperands,
     /*  544780 */     // GIR_Coverage, 12370,
     /*  544780 */     GIR_EraseRootFromParent_Done,
     /*  544781 */   // Label 8334: @544781
     /*  544781 */   GIM_Try, /*On fail goto*//*Label 8335*/ GIMT_Encode4(544831), // Rule ID 12371 //
     /*  544786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  544789 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544807 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544815 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544829 */     GIR_RootConstrainSelectedInstOperands,
     /*  544830 */     // GIR_Coverage, 12371,
     /*  544830 */     GIR_EraseRootFromParent_Done,
     /*  544831 */   // Label 8335: @544831
     /*  544831 */   GIM_Try, /*On fail goto*//*Label 8336*/ GIMT_Encode4(544881), // Rule ID 12372 //
     /*  544836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  544839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  544846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  544857 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  544857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
     /*  544860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  544865 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  544872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  544875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544879 */     GIR_RootConstrainSelectedInstOperands,
     /*  544880 */     // GIR_Coverage, 12372,
     /*  544880 */     GIR_EraseRootFromParent_Done,
     /*  544881 */   // Label 8336: @544881
     /*  544881 */   GIM_Try, /*On fail goto*//*Label 8337*/ GIMT_Encode4(544937), // Rule ID 10201 //
     /*  544886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  544889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  544895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544899 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544906 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  544909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544914 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544931 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544935 */     GIR_RootConstrainSelectedInstOperands,
     /*  544936 */     // GIR_Coverage, 10201,
     /*  544936 */     GIR_EraseRootFromParent_Done,
     /*  544937 */   // Label 8337: @544937
     /*  544937 */   GIM_Try, /*On fail goto*//*Label 8338*/ GIMT_Encode4(544993), // Rule ID 10202 //
     /*  544942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  544945 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  544951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  544955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  544962 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  544962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  544965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  544970 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  544972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  544977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  544982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  544987 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  544991 */     GIR_RootConstrainSelectedInstOperands,
     /*  544992 */     // GIR_Coverage, 10202,
     /*  544992 */     GIR_EraseRootFromParent_Done,
     /*  544993 */   // Label 8338: @544993
     /*  544993 */   GIM_Try, /*On fail goto*//*Label 8339*/ GIMT_Encode4(545049), // Rule ID 10203 //
     /*  544998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  545001 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545018 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545026 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545047 */     GIR_RootConstrainSelectedInstOperands,
     /*  545048 */     // GIR_Coverage, 10203,
     /*  545048 */     GIR_EraseRootFromParent_Done,
     /*  545049 */   // Label 8339: @545049
     /*  545049 */   GIM_Try, /*On fail goto*//*Label 8340*/ GIMT_Encode4(545105), // Rule ID 10204 //
     /*  545054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  545057 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545074 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545082 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545103 */     GIR_RootConstrainSelectedInstOperands,
     /*  545104 */     // GIR_Coverage, 10204,
     /*  545104 */     GIR_EraseRootFromParent_Done,
     /*  545105 */   // Label 8340: @545105
     /*  545105 */   GIM_Try, /*On fail goto*//*Label 8341*/ GIMT_Encode4(545161), // Rule ID 10205 //
     /*  545110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  545113 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545119 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545123 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545130 */     // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545138 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545155 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545159 */     GIR_RootConstrainSelectedInstOperands,
     /*  545160 */     // GIR_Coverage, 10205,
     /*  545160 */     GIR_EraseRootFromParent_Done,
     /*  545161 */   // Label 8341: @545161
     /*  545161 */   GIM_Try, /*On fail goto*//*Label 8342*/ GIMT_Encode4(545217), // Rule ID 10221 //
     /*  545166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  545169 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545175 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545186 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545194 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545215 */     GIR_RootConstrainSelectedInstOperands,
     /*  545216 */     // GIR_Coverage, 10221,
     /*  545216 */     GIR_EraseRootFromParent_Done,
     /*  545217 */   // Label 8342: @545217
     /*  545217 */   GIM_Try, /*On fail goto*//*Label 8343*/ GIMT_Encode4(545273), // Rule ID 10222 //
     /*  545222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  545225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545242 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545250 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545267 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545271 */     GIR_RootConstrainSelectedInstOperands,
     /*  545272 */     // GIR_Coverage, 10222,
     /*  545272 */     GIR_EraseRootFromParent_Done,
     /*  545273 */   // Label 8343: @545273
     /*  545273 */   GIM_Try, /*On fail goto*//*Label 8344*/ GIMT_Encode4(545329), // Rule ID 10223 //
     /*  545278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  545281 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545298 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545306 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545327 */     GIR_RootConstrainSelectedInstOperands,
     /*  545328 */     // GIR_Coverage, 10223,
     /*  545328 */     GIR_EraseRootFromParent_Done,
     /*  545329 */   // Label 8344: @545329
     /*  545329 */   GIM_Try, /*On fail goto*//*Label 8345*/ GIMT_Encode4(545385), // Rule ID 10224 //
     /*  545334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  545337 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545354 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545362 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545383 */     GIR_RootConstrainSelectedInstOperands,
     /*  545384 */     // GIR_Coverage, 10224,
     /*  545384 */     GIR_EraseRootFromParent_Done,
     /*  545385 */   // Label 8345: @545385
     /*  545385 */   GIM_Try, /*On fail goto*//*Label 8346*/ GIMT_Encode4(545441), // Rule ID 10225 //
     /*  545390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  545393 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  545410 */     // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  545410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2_SADDR),
     /*  545413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  545418 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  545425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  545430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  545435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545439 */     GIR_RootConstrainSelectedInstOperands,
     /*  545440 */     // GIR_Coverage, 10225,
     /*  545440 */     GIR_EraseRootFromParent_Done,
     /*  545441 */   // Label 8346: @545441
     /*  545441 */   GIM_Try, /*On fail goto*//*Label 8347*/ GIMT_Encode4(545490), // Rule ID 10196 //
     /*  545446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  545449 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545466 */     // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545474 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545488 */     GIR_RootConstrainSelectedInstOperands,
     /*  545489 */     // GIR_Coverage, 10196,
     /*  545489 */     GIR_EraseRootFromParent_Done,
     /*  545490 */   // Label 8347: @545490
     /*  545490 */   GIM_Try, /*On fail goto*//*Label 8348*/ GIMT_Encode4(545539), // Rule ID 10197 //
     /*  545495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  545498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545515 */     // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545523 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545537 */     GIR_RootConstrainSelectedInstOperands,
     /*  545538 */     // GIR_Coverage, 10197,
     /*  545538 */     GIR_EraseRootFromParent_Done,
     /*  545539 */   // Label 8348: @545539
     /*  545539 */   GIM_Try, /*On fail goto*//*Label 8349*/ GIMT_Encode4(545588), // Rule ID 10198 //
     /*  545544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  545547 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545564 */     // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545572 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545586 */     GIR_RootConstrainSelectedInstOperands,
     /*  545587 */     // GIR_Coverage, 10198,
     /*  545587 */     GIR_EraseRootFromParent_Done,
     /*  545588 */   // Label 8349: @545588
     /*  545588 */   GIM_Try, /*On fail goto*//*Label 8350*/ GIMT_Encode4(545637), // Rule ID 10199 //
     /*  545593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  545596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545613 */     // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545621 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545635 */     GIR_RootConstrainSelectedInstOperands,
     /*  545636 */     // GIR_Coverage, 10199,
     /*  545636 */     GIR_EraseRootFromParent_Done,
     /*  545637 */   // Label 8350: @545637
     /*  545637 */   GIM_Try, /*On fail goto*//*Label 8351*/ GIMT_Encode4(545686), // Rule ID 10200 //
     /*  545642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  545645 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545662 */     // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545670 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545677 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545680 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545684 */     GIR_RootConstrainSelectedInstOperands,
     /*  545685 */     // GIR_Coverage, 10200,
     /*  545685 */     GIR_EraseRootFromParent_Done,
     /*  545686 */   // Label 8351: @545686
     /*  545686 */   GIM_Try, /*On fail goto*//*Label 8352*/ GIMT_Encode4(545735), // Rule ID 10216 //
     /*  545691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  545694 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545711 */     // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545719 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545733 */     GIR_RootConstrainSelectedInstOperands,
     /*  545734 */     // GIR_Coverage, 10216,
     /*  545734 */     GIR_EraseRootFromParent_Done,
     /*  545735 */   // Label 8352: @545735
     /*  545735 */   GIM_Try, /*On fail goto*//*Label 8353*/ GIMT_Encode4(545784), // Rule ID 10217 //
     /*  545740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  545743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545749 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545760 */     // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545768 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545782 */     GIR_RootConstrainSelectedInstOperands,
     /*  545783 */     // GIR_Coverage, 10217,
     /*  545783 */     GIR_EraseRootFromParent_Done,
     /*  545784 */   // Label 8353: @545784
     /*  545784 */   GIM_Try, /*On fail goto*//*Label 8354*/ GIMT_Encode4(545833), // Rule ID 10218 //
     /*  545789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  545792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545809 */     // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545817 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545831 */     GIR_RootConstrainSelectedInstOperands,
     /*  545832 */     // GIR_Coverage, 10218,
     /*  545832 */     GIR_EraseRootFromParent_Done,
     /*  545833 */   // Label 8354: @545833
     /*  545833 */   GIM_Try, /*On fail goto*//*Label 8355*/ GIMT_Encode4(545882), // Rule ID 10219 //
     /*  545838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  545841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545858 */     // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545866 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545880 */     GIR_RootConstrainSelectedInstOperands,
     /*  545881 */     // GIR_Coverage, 10219,
     /*  545881 */     GIR_EraseRootFromParent_Done,
     /*  545882 */   // Label 8355: @545882
     /*  545882 */   GIM_Try, /*On fail goto*//*Label 8356*/ GIMT_Encode4(545931), // Rule ID 10220 //
     /*  545887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  545890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  545896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  545907 */     // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  545907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
     /*  545910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  545915 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  545917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545929 */     GIR_RootConstrainSelectedInstOperands,
     /*  545930 */     // GIR_Coverage, 10220,
     /*  545930 */     GIR_EraseRootFromParent_Done,
     /*  545931 */   // Label 8356: @545931
     /*  545931 */   GIM_Reject,
     /*  545932 */ // Label 8202: @545932
     /*  545932 */ GIM_Reject,
     /*  545933 */ // Label 5873: @545933
     /*  545933 */ GIM_Try, /*On fail goto*//*Label 8357*/ GIMT_Encode4(545992), // Rule ID 29833 //
     /*  545938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  545941 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  545944 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  545948 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  545953 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  545957 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  545961 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  545968 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  545968 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  545971 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  545976 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  545978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  545983 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  545986 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  545990 */   GIR_RootConstrainSelectedInstOperands,
     /*  545991 */   // GIR_Coverage, 29833,
     /*  545991 */   GIR_EraseRootFromParent_Done,
     /*  545992 */ // Label 8357: @545992
     /*  545992 */ GIM_Try, /*On fail goto*//*Label 8358*/ GIMT_Encode4(546051), // Rule ID 29834 //
     /*  545997 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  546000 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546003 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546007 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546012 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546016 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546020 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546027 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546035 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546037 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546042 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546045 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546049 */   GIR_RootConstrainSelectedInstOperands,
     /*  546050 */   // GIR_Coverage, 29834,
     /*  546050 */   GIR_EraseRootFromParent_Done,
     /*  546051 */ // Label 8358: @546051
     /*  546051 */ GIM_Try, /*On fail goto*//*Label 8359*/ GIMT_Encode4(546110), // Rule ID 29835 //
     /*  546056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  546059 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546062 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546066 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546071 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546075 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546079 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546086 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546086 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546094 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546101 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546104 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546108 */   GIR_RootConstrainSelectedInstOperands,
     /*  546109 */   // GIR_Coverage, 29835,
     /*  546109 */   GIR_EraseRootFromParent_Done,
     /*  546110 */ // Label 8359: @546110
     /*  546110 */ GIM_Try, /*On fail goto*//*Label 8360*/ GIMT_Encode4(546169), // Rule ID 29836 //
     /*  546115 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  546118 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546121 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546125 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546130 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546134 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546138 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546145 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546145 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546153 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546155 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546160 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546163 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546167 */   GIR_RootConstrainSelectedInstOperands,
     /*  546168 */   // GIR_Coverage, 29836,
     /*  546168 */   GIR_EraseRootFromParent_Done,
     /*  546169 */ // Label 8360: @546169
     /*  546169 */ GIM_Try, /*On fail goto*//*Label 8361*/ GIMT_Encode4(546228), // Rule ID 29837 //
     /*  546174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  546177 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546180 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546184 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546189 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546197 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546204 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546204 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546212 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546222 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546226 */   GIR_RootConstrainSelectedInstOperands,
     /*  546227 */   // GIR_Coverage, 29837,
     /*  546227 */   GIR_EraseRootFromParent_Done,
     /*  546228 */ // Label 8361: @546228
     /*  546228 */ GIM_Try, /*On fail goto*//*Label 8362*/ GIMT_Encode4(546287), // Rule ID 29853 //
     /*  546233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  546236 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546239 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546243 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546248 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546252 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546256 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546263 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546266 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546271 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546278 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546281 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546285 */   GIR_RootConstrainSelectedInstOperands,
     /*  546286 */   // GIR_Coverage, 29853,
     /*  546286 */   GIR_EraseRootFromParent_Done,
     /*  546287 */ // Label 8362: @546287
     /*  546287 */ GIM_Try, /*On fail goto*//*Label 8363*/ GIMT_Encode4(546346), // Rule ID 29854 //
     /*  546292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  546295 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546298 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546302 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546307 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546311 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546315 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546322 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546322 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546325 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546330 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546332 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546337 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546340 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546344 */   GIR_RootConstrainSelectedInstOperands,
     /*  546345 */   // GIR_Coverage, 29854,
     /*  546345 */   GIR_EraseRootFromParent_Done,
     /*  546346 */ // Label 8363: @546346
     /*  546346 */ GIM_Try, /*On fail goto*//*Label 8364*/ GIMT_Encode4(546405), // Rule ID 29855 //
     /*  546351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  546354 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546357 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546361 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546366 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546370 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546374 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546381 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546389 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546391 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546396 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546399 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546403 */   GIR_RootConstrainSelectedInstOperands,
     /*  546404 */   // GIR_Coverage, 29855,
     /*  546404 */   GIR_EraseRootFromParent_Done,
     /*  546405 */ // Label 8364: @546405
     /*  546405 */ GIM_Try, /*On fail goto*//*Label 8365*/ GIMT_Encode4(546464), // Rule ID 29856 //
     /*  546410 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  546413 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546416 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546420 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546425 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546429 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546433 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546440 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546440 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546448 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546450 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546455 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546458 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546462 */   GIR_RootConstrainSelectedInstOperands,
     /*  546463 */   // GIR_Coverage, 29856,
     /*  546463 */   GIR_EraseRootFromParent_Done,
     /*  546464 */ // Label 8365: @546464
     /*  546464 */ GIM_Try, /*On fail goto*//*Label 8366*/ GIMT_Encode4(546523), // Rule ID 29857 //
     /*  546469 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  546472 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546475 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546479 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546484 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  546488 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546492 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546499 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546499 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546502 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546507 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546509 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546514 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546517 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546521 */   GIR_RootConstrainSelectedInstOperands,
     /*  546522 */   // GIR_Coverage, 29857,
     /*  546522 */   GIR_EraseRootFromParent_Done,
     /*  546523 */ // Label 8366: @546523
     /*  546523 */ GIM_Try, /*On fail goto*//*Label 8367*/ GIMT_Encode4(546587), // Rule ID 30173 //
     /*  546528 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  546531 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546534 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546538 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546543 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546548 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546552 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546556 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546563 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546563 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546571 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546578 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546581 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546585 */   GIR_RootConstrainSelectedInstOperands,
     /*  546586 */   // GIR_Coverage, 30173,
     /*  546586 */   GIR_EraseRootFromParent_Done,
     /*  546587 */ // Label 8367: @546587
     /*  546587 */ GIM_Try, /*On fail goto*//*Label 8368*/ GIMT_Encode4(546651), // Rule ID 30174 //
     /*  546592 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  546595 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546598 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546602 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546607 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546612 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546616 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546620 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546627 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546627 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546635 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546642 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546645 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546649 */   GIR_RootConstrainSelectedInstOperands,
     /*  546650 */   // GIR_Coverage, 30174,
     /*  546650 */   GIR_EraseRootFromParent_Done,
     /*  546651 */ // Label 8368: @546651
     /*  546651 */ GIM_Try, /*On fail goto*//*Label 8369*/ GIMT_Encode4(546715), // Rule ID 30175 //
     /*  546656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  546659 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546662 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546666 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546671 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546676 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546680 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546684 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546691 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546691 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546694 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546699 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546706 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546709 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546713 */   GIR_RootConstrainSelectedInstOperands,
     /*  546714 */   // GIR_Coverage, 30175,
     /*  546714 */   GIR_EraseRootFromParent_Done,
     /*  546715 */ // Label 8369: @546715
     /*  546715 */ GIM_Try, /*On fail goto*//*Label 8370*/ GIMT_Encode4(546779), // Rule ID 30176 //
     /*  546720 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  546723 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546726 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546730 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546740 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546744 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546748 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546755 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546763 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546765 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546770 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546773 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546777 */   GIR_RootConstrainSelectedInstOperands,
     /*  546778 */   // GIR_Coverage, 30176,
     /*  546778 */   GIR_EraseRootFromParent_Done,
     /*  546779 */ // Label 8370: @546779
     /*  546779 */ GIM_Try, /*On fail goto*//*Label 8371*/ GIMT_Encode4(546843), // Rule ID 30177 //
     /*  546784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  546787 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546790 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546794 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546799 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546804 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546808 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546812 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546819 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546827 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546834 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546837 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546841 */   GIR_RootConstrainSelectedInstOperands,
     /*  546842 */   // GIR_Coverage, 30177,
     /*  546842 */   GIR_EraseRootFromParent_Done,
     /*  546843 */ // Label 8371: @546843
     /*  546843 */ GIM_Try, /*On fail goto*//*Label 8372*/ GIMT_Encode4(546907), // Rule ID 30193 //
     /*  546848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  546851 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546854 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546858 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546863 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546868 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546872 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546876 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546883 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546883 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546891 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546898 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546901 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546905 */   GIR_RootConstrainSelectedInstOperands,
     /*  546906 */   // GIR_Coverage, 30193,
     /*  546906 */   GIR_EraseRootFromParent_Done,
     /*  546907 */ // Label 8372: @546907
     /*  546907 */ GIM_Try, /*On fail goto*//*Label 8373*/ GIMT_Encode4(546971), // Rule ID 30194 //
     /*  546912 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  546915 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546918 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546922 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546927 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546932 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  546936 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  546940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  546947 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  546947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  546950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  546955 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  546957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  546962 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  546965 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  546969 */   GIR_RootConstrainSelectedInstOperands,
     /*  546970 */   // GIR_Coverage, 30194,
     /*  546970 */   GIR_EraseRootFromParent_Done,
     /*  546971 */ // Label 8373: @546971
     /*  546971 */ GIM_Try, /*On fail goto*//*Label 8374*/ GIMT_Encode4(547035), // Rule ID 30195 //
     /*  546976 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  546979 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  546982 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  546986 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546991 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  546996 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547000 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  547004 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547011 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  547014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547019 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547021 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547026 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547029 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547033 */   GIR_RootConstrainSelectedInstOperands,
     /*  547034 */   // GIR_Coverage, 30195,
     /*  547034 */   GIR_EraseRootFromParent_Done,
     /*  547035 */ // Label 8374: @547035
     /*  547035 */ GIM_Try, /*On fail goto*//*Label 8375*/ GIMT_Encode4(547099), // Rule ID 30196 //
     /*  547040 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  547043 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547046 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  547050 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547055 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547060 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547064 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  547068 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547075 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547075 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  547078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547083 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547090 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547093 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547097 */   GIR_RootConstrainSelectedInstOperands,
     /*  547098 */   // GIR_Coverage, 30196,
     /*  547098 */   GIR_EraseRootFromParent_Done,
     /*  547099 */ // Label 8375: @547099
     /*  547099 */ GIM_Try, /*On fail goto*//*Label 8376*/ GIMT_Encode4(547163), // Rule ID 30197 //
     /*  547104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  547107 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547110 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  547114 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547119 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547128 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  547132 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547139 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  547142 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547147 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547154 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547161 */   GIR_RootConstrainSelectedInstOperands,
     /*  547162 */   // GIR_Coverage, 30197,
     /*  547162 */   GIR_EraseRootFromParent_Done,
     /*  547163 */ // Label 8376: @547163
     /*  547163 */ GIM_Try, /*On fail goto*//*Label 8377*/ GIMT_Encode4(547218), // Rule ID 29838 //
     /*  547168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  547171 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547174 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547179 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547183 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547187 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547194 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547202 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547216 */   GIR_RootConstrainSelectedInstOperands,
     /*  547217 */   // GIR_Coverage, 29838,
     /*  547217 */   GIR_EraseRootFromParent_Done,
     /*  547218 */ // Label 8377: @547218
     /*  547218 */ GIM_Try, /*On fail goto*//*Label 8378*/ GIMT_Encode4(547273), // Rule ID 29839 //
     /*  547223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  547226 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547229 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547234 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547238 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547242 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547249 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547252 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547257 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547259 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547271 */   GIR_RootConstrainSelectedInstOperands,
     /*  547272 */   // GIR_Coverage, 29839,
     /*  547272 */   GIR_EraseRootFromParent_Done,
     /*  547273 */ // Label 8378: @547273
     /*  547273 */ GIM_Try, /*On fail goto*//*Label 8379*/ GIMT_Encode4(547328), // Rule ID 29840 //
     /*  547278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  547281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547289 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547293 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547297 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547304 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547304 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547312 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547319 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547322 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547326 */   GIR_RootConstrainSelectedInstOperands,
     /*  547327 */   // GIR_Coverage, 29840,
     /*  547327 */   GIR_EraseRootFromParent_Done,
     /*  547328 */ // Label 8379: @547328
     /*  547328 */ GIM_Try, /*On fail goto*//*Label 8380*/ GIMT_Encode4(547383), // Rule ID 29841 //
     /*  547333 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  547336 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547339 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547344 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547348 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547352 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547359 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547359 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547367 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547369 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547374 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547377 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547381 */   GIR_RootConstrainSelectedInstOperands,
     /*  547382 */   // GIR_Coverage, 29841,
     /*  547382 */   GIR_EraseRootFromParent_Done,
     /*  547383 */ // Label 8380: @547383
     /*  547383 */ GIM_Try, /*On fail goto*//*Label 8381*/ GIMT_Encode4(547438), // Rule ID 29842 //
     /*  547388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  547391 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547394 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547399 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547403 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547407 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547414 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547422 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547424 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547429 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547436 */   GIR_RootConstrainSelectedInstOperands,
     /*  547437 */   // GIR_Coverage, 29842,
     /*  547437 */   GIR_EraseRootFromParent_Done,
     /*  547438 */ // Label 8381: @547438
     /*  547438 */ GIM_Try, /*On fail goto*//*Label 8382*/ GIMT_Encode4(547493), // Rule ID 29858 //
     /*  547443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  547446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547454 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547458 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547462 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547469 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547477 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547479 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547487 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547491 */   GIR_RootConstrainSelectedInstOperands,
     /*  547492 */   // GIR_Coverage, 29858,
     /*  547492 */   GIR_EraseRootFromParent_Done,
     /*  547493 */ // Label 8382: @547493
     /*  547493 */ GIM_Try, /*On fail goto*//*Label 8383*/ GIMT_Encode4(547548), // Rule ID 29859 //
     /*  547498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  547501 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547504 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547509 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547513 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547517 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547524 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547524 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547532 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547539 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547542 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547546 */   GIR_RootConstrainSelectedInstOperands,
     /*  547547 */   // GIR_Coverage, 29859,
     /*  547547 */   GIR_EraseRootFromParent_Done,
     /*  547548 */ // Label 8383: @547548
     /*  547548 */ GIM_Try, /*On fail goto*//*Label 8384*/ GIMT_Encode4(547603), // Rule ID 29860 //
     /*  547553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  547556 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547559 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547564 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547568 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547572 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547579 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547587 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547594 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547597 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547601 */   GIR_RootConstrainSelectedInstOperands,
     /*  547602 */   // GIR_Coverage, 29860,
     /*  547602 */   GIR_EraseRootFromParent_Done,
     /*  547603 */ // Label 8384: @547603
     /*  547603 */ GIM_Try, /*On fail goto*//*Label 8385*/ GIMT_Encode4(547658), // Rule ID 29861 //
     /*  547608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  547611 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547614 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547619 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547623 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547627 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547634 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547642 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547649 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547652 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547656 */   GIR_RootConstrainSelectedInstOperands,
     /*  547657 */   // GIR_Coverage, 29861,
     /*  547657 */   GIR_EraseRootFromParent_Done,
     /*  547658 */ // Label 8385: @547658
     /*  547658 */ GIM_Try, /*On fail goto*//*Label 8386*/ GIMT_Encode4(547713), // Rule ID 29862 //
     /*  547663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  547666 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547669 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547674 */   GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  547678 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547682 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547689 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547689 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547697 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547704 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547707 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547711 */   GIR_RootConstrainSelectedInstOperands,
     /*  547712 */   // GIR_Coverage, 29862,
     /*  547712 */   GIR_EraseRootFromParent_Done,
     /*  547713 */ // Label 8386: @547713
     /*  547713 */ GIM_Try, /*On fail goto*//*Label 8387*/ GIMT_Encode4(547773), // Rule ID 30178 //
     /*  547718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  547721 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547724 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547729 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547734 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547738 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  547742 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547749 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547749 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547757 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547759 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547764 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547767 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547771 */   GIR_RootConstrainSelectedInstOperands,
     /*  547772 */   // GIR_Coverage, 30178,
     /*  547772 */   GIR_EraseRootFromParent_Done,
     /*  547773 */ // Label 8387: @547773
     /*  547773 */ GIM_Try, /*On fail goto*//*Label 8388*/ GIMT_Encode4(547833), // Rule ID 30179 //
     /*  547778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  547781 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547784 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547789 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547794 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547798 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  547802 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547809 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547809 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547812 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547817 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547831 */   GIR_RootConstrainSelectedInstOperands,
     /*  547832 */   // GIR_Coverage, 30179,
     /*  547832 */   GIR_EraseRootFromParent_Done,
     /*  547833 */ // Label 8388: @547833
     /*  547833 */ GIM_Try, /*On fail goto*//*Label 8389*/ GIMT_Encode4(547893), // Rule ID 30180 //
     /*  547838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  547841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547849 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547854 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547858 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  547862 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547869 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547877 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547879 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547884 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547887 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547891 */   GIR_RootConstrainSelectedInstOperands,
     /*  547892 */   // GIR_Coverage, 30180,
     /*  547892 */   GIR_EraseRootFromParent_Done,
     /*  547893 */ // Label 8389: @547893
     /*  547893 */ GIM_Try, /*On fail goto*//*Label 8390*/ GIMT_Encode4(547953), // Rule ID 30181 //
     /*  547898 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  547901 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547904 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547909 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547914 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547918 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  547922 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547929 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547929 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547932 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547937 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547939 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  547944 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  547947 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  547951 */   GIR_RootConstrainSelectedInstOperands,
     /*  547952 */   // GIR_Coverage, 30181,
     /*  547952 */   GIR_EraseRootFromParent_Done,
     /*  547953 */ // Label 8390: @547953
     /*  547953 */ GIM_Try, /*On fail goto*//*Label 8391*/ GIMT_Encode4(548013), // Rule ID 30182 //
     /*  547958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  547961 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  547964 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547969 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  547974 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  547978 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  547982 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  547989 */   // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  547989 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  547992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  547997 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  547999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  548004 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548007 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548011 */   GIR_RootConstrainSelectedInstOperands,
     /*  548012 */   // GIR_Coverage, 30182,
     /*  548012 */   GIR_EraseRootFromParent_Done,
     /*  548013 */ // Label 8391: @548013
     /*  548013 */ GIM_Try, /*On fail goto*//*Label 8392*/ GIMT_Encode4(548073), // Rule ID 30198 //
     /*  548018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  548021 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548024 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548029 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548034 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548038 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  548042 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  548049 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  548049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  548052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  548057 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  548064 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548067 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548071 */   GIR_RootConstrainSelectedInstOperands,
     /*  548072 */   // GIR_Coverage, 30198,
     /*  548072 */   GIR_EraseRootFromParent_Done,
     /*  548073 */ // Label 8392: @548073
     /*  548073 */ GIM_Try, /*On fail goto*//*Label 8393*/ GIMT_Encode4(548133), // Rule ID 30199 //
     /*  548078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  548081 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548084 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548089 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548094 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548098 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  548102 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  548109 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  548109 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  548112 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  548117 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  548124 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548127 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548131 */   GIR_RootConstrainSelectedInstOperands,
     /*  548132 */   // GIR_Coverage, 30199,
     /*  548132 */   GIR_EraseRootFromParent_Done,
     /*  548133 */ // Label 8393: @548133
     /*  548133 */ GIM_Try, /*On fail goto*//*Label 8394*/ GIMT_Encode4(548193), // Rule ID 30200 //
     /*  548138 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  548141 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548144 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548149 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548154 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548158 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  548162 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  548169 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  548169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  548172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  548177 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  548184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548191 */   GIR_RootConstrainSelectedInstOperands,
     /*  548192 */   // GIR_Coverage, 30200,
     /*  548192 */   GIR_EraseRootFromParent_Done,
     /*  548193 */ // Label 8394: @548193
     /*  548193 */ GIM_Try, /*On fail goto*//*Label 8395*/ GIMT_Encode4(548253), // Rule ID 30201 //
     /*  548198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  548201 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548204 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548209 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548214 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548218 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  548222 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  548229 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  548229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  548232 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  548237 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  548244 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548247 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548251 */   GIR_RootConstrainSelectedInstOperands,
     /*  548252 */   // GIR_Coverage, 30201,
     /*  548252 */   GIR_EraseRootFromParent_Done,
     /*  548253 */ // Label 8395: @548253
     /*  548253 */ GIM_Try, /*On fail goto*//*Label 8396*/ GIMT_Encode4(548313), // Rule ID 30202 //
     /*  548258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  548261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548264 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548269 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  548274 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548278 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  548282 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  548289 */   // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  548289 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  548292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  548297 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  548304 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548307 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548311 */   GIR_RootConstrainSelectedInstOperands,
     /*  548312 */   // GIR_Coverage, 30202,
     /*  548312 */   GIR_EraseRootFromParent_Done,
     /*  548313 */ // Label 8396: @548313
     /*  548313 */ GIM_Try, /*On fail goto*//*Label 8397*/ GIMT_Encode4(548372), // Rule ID 25986 //
     /*  548318 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  548321 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548324 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548329 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548333 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548340 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548340 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  548343 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548360 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548370 */   GIR_RootConstrainSelectedInstOperands,
     /*  548371 */   // GIR_Coverage, 25986,
     /*  548371 */   GIR_EraseRootFromParent_Done,
     /*  548372 */ // Label 8397: @548372
     /*  548372 */ GIM_Try, /*On fail goto*//*Label 8398*/ GIMT_Encode4(548431), // Rule ID 25987 //
     /*  548377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  548380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548383 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548388 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548392 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548399 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548399 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  548402 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548419 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548422 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548425 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548429 */   GIR_RootConstrainSelectedInstOperands,
     /*  548430 */   // GIR_Coverage, 25987,
     /*  548430 */   GIR_EraseRootFromParent_Done,
     /*  548431 */ // Label 8398: @548431
     /*  548431 */ GIM_Try, /*On fail goto*//*Label 8399*/ GIMT_Encode4(548490), // Rule ID 25988 //
     /*  548436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  548439 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548442 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548447 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548451 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548458 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548458 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  548461 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548478 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548484 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548488 */   GIR_RootConstrainSelectedInstOperands,
     /*  548489 */   // GIR_Coverage, 25988,
     /*  548489 */   GIR_EraseRootFromParent_Done,
     /*  548490 */ // Label 8399: @548490
     /*  548490 */ GIM_Try, /*On fail goto*//*Label 8400*/ GIMT_Encode4(548549), // Rule ID 25989 //
     /*  548495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  548498 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548501 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548506 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548510 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548517 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548517 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  548520 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548537 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548540 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548543 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548547 */   GIR_RootConstrainSelectedInstOperands,
     /*  548548 */   // GIR_Coverage, 25989,
     /*  548548 */   GIR_EraseRootFromParent_Done,
     /*  548549 */ // Label 8400: @548549
     /*  548549 */ GIM_Try, /*On fail goto*//*Label 8401*/ GIMT_Encode4(548608), // Rule ID 25990 //
     /*  548554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  548557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548560 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548565 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548569 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548576 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548576 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  548579 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548581 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548586 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548591 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548596 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548602 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548606 */   GIR_RootConstrainSelectedInstOperands,
     /*  548607 */   // GIR_Coverage, 25990,
     /*  548607 */   GIR_EraseRootFromParent_Done,
     /*  548608 */ // Label 8401: @548608
     /*  548608 */ GIM_Try, /*On fail goto*//*Label 8402*/ GIMT_Encode4(548667), // Rule ID 25996 //
     /*  548613 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  548616 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548619 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548624 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548628 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548635 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  548638 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548640 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548645 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548655 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548658 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548661 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548665 */   GIR_RootConstrainSelectedInstOperands,
     /*  548666 */   // GIR_Coverage, 25996,
     /*  548666 */   GIR_EraseRootFromParent_Done,
     /*  548667 */ // Label 8402: @548667
     /*  548667 */ GIM_Try, /*On fail goto*//*Label 8403*/ GIMT_Encode4(548726), // Rule ID 25997 //
     /*  548672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  548675 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548678 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548683 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548687 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548694 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  548697 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548699 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548704 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548709 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548714 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548717 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548720 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548724 */   GIR_RootConstrainSelectedInstOperands,
     /*  548725 */   // GIR_Coverage, 25997,
     /*  548725 */   GIR_EraseRootFromParent_Done,
     /*  548726 */ // Label 8403: @548726
     /*  548726 */ GIM_Try, /*On fail goto*//*Label 8404*/ GIMT_Encode4(548785), // Rule ID 25998 //
     /*  548731 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  548734 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548737 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548742 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548746 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548753 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  548756 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548783 */   GIR_RootConstrainSelectedInstOperands,
     /*  548784 */   // GIR_Coverage, 25998,
     /*  548784 */   GIR_EraseRootFromParent_Done,
     /*  548785 */ // Label 8404: @548785
     /*  548785 */ GIM_Try, /*On fail goto*//*Label 8405*/ GIMT_Encode4(548844), // Rule ID 25999 //
     /*  548790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  548793 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548796 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548801 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548805 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548812 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548812 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  548815 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548817 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548822 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548827 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548835 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548838 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548842 */   GIR_RootConstrainSelectedInstOperands,
     /*  548843 */   // GIR_Coverage, 25999,
     /*  548843 */   GIR_EraseRootFromParent_Done,
     /*  548844 */ // Label 8405: @548844
     /*  548844 */ GIM_Try, /*On fail goto*//*Label 8406*/ GIMT_Encode4(548903), // Rule ID 26000 //
     /*  548849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  548852 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548855 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548860 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548864 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
     /*  548871 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  548871 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  548874 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  548876 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  548881 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  548886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548891 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548894 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  548897 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548901 */   GIR_RootConstrainSelectedInstOperands,
     /*  548902 */   // GIR_Coverage, 26000,
     /*  548902 */   GIR_EraseRootFromParent_Done,
     /*  548903 */ // Label 8406: @548903
     /*  548903 */ GIM_Try, /*On fail goto*//*Label 8407*/ GIMT_Encode4(548961), // Rule ID 14602 //
     /*  548908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  548911 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548914 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548919 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548923 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  548930 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  548930 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  548933 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  548935 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  548940 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  548945 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  548950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  548955 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  548959 */   GIR_RootConstrainSelectedInstOperands,
     /*  548960 */   // GIR_Coverage, 14602,
     /*  548960 */   GIR_EraseRootFromParent_Done,
     /*  548961 */ // Label 8407: @548961
     /*  548961 */ GIM_Try, /*On fail goto*//*Label 8408*/ GIMT_Encode4(549019), // Rule ID 14603 //
     /*  548966 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  548969 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  548972 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  548977 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  548981 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  548988 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  548988 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  548991 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  548993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  548998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549013 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549017 */   GIR_RootConstrainSelectedInstOperands,
     /*  549018 */   // GIR_Coverage, 14603,
     /*  549018 */   GIR_EraseRootFromParent_Done,
     /*  549019 */ // Label 8408: @549019
     /*  549019 */ GIM_Try, /*On fail goto*//*Label 8409*/ GIMT_Encode4(549077), // Rule ID 14604 //
     /*  549024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  549027 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549030 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549046 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549049 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549066 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549071 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549075 */   GIR_RootConstrainSelectedInstOperands,
     /*  549076 */   // GIR_Coverage, 14604,
     /*  549076 */   GIR_EraseRootFromParent_Done,
     /*  549077 */ // Label 8409: @549077
     /*  549077 */ GIM_Try, /*On fail goto*//*Label 8410*/ GIMT_Encode4(549135), // Rule ID 14605 //
     /*  549082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  549085 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549088 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549093 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549097 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549104 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549107 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549114 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549119 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549129 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549133 */   GIR_RootConstrainSelectedInstOperands,
     /*  549134 */   // GIR_Coverage, 14605,
     /*  549134 */   GIR_EraseRootFromParent_Done,
     /*  549135 */ // Label 8410: @549135
     /*  549135 */ GIM_Try, /*On fail goto*//*Label 8411*/ GIMT_Encode4(549193), // Rule ID 14606 //
     /*  549140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  549143 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549146 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549151 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549155 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549162 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549162 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549165 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549172 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549177 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549182 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549187 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549191 */   GIR_RootConstrainSelectedInstOperands,
     /*  549192 */   // GIR_Coverage, 14606,
     /*  549192 */   GIR_EraseRootFromParent_Done,
     /*  549193 */ // Label 8411: @549193
     /*  549193 */ GIM_Try, /*On fail goto*//*Label 8412*/ GIMT_Encode4(549251), // Rule ID 14632 //
     /*  549198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  549201 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549204 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549209 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549213 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549220 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549223 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549225 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549230 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549245 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549249 */   GIR_RootConstrainSelectedInstOperands,
     /*  549250 */   // GIR_Coverage, 14632,
     /*  549250 */   GIR_EraseRootFromParent_Done,
     /*  549251 */ // Label 8412: @549251
     /*  549251 */ GIM_Try, /*On fail goto*//*Label 8413*/ GIMT_Encode4(549309), // Rule ID 14633 //
     /*  549256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  549259 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549262 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549271 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549278 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549281 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549288 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549293 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549303 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549307 */   GIR_RootConstrainSelectedInstOperands,
     /*  549308 */   // GIR_Coverage, 14633,
     /*  549308 */   GIR_EraseRootFromParent_Done,
     /*  549309 */ // Label 8413: @549309
     /*  549309 */ GIM_Try, /*On fail goto*//*Label 8414*/ GIMT_Encode4(549367), // Rule ID 14634 //
     /*  549314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  549317 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549320 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549325 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549329 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549336 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549336 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549339 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549361 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549365 */   GIR_RootConstrainSelectedInstOperands,
     /*  549366 */   // GIR_Coverage, 14634,
     /*  549366 */   GIR_EraseRootFromParent_Done,
     /*  549367 */ // Label 8414: @549367
     /*  549367 */ GIM_Try, /*On fail goto*//*Label 8415*/ GIMT_Encode4(549425), // Rule ID 14635 //
     /*  549372 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  549375 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549378 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549383 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549387 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549394 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549394 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549397 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549399 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549414 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549419 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549423 */   GIR_RootConstrainSelectedInstOperands,
     /*  549424 */   // GIR_Coverage, 14635,
     /*  549424 */   GIR_EraseRootFromParent_Done,
     /*  549425 */ // Label 8415: @549425
     /*  549425 */ GIM_Try, /*On fail goto*//*Label 8416*/ GIMT_Encode4(549483), // Rule ID 14636 //
     /*  549430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  549433 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549436 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549441 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549445 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  549452 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  549452 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  549455 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  549462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  549467 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  549472 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  549477 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549481 */   GIR_RootConstrainSelectedInstOperands,
     /*  549482 */   // GIR_Coverage, 14636,
     /*  549482 */   GIR_EraseRootFromParent_Done,
     /*  549483 */ // Label 8416: @549483
     /*  549483 */ GIM_Try, /*On fail goto*//*Label 8417*/ GIMT_Encode4(549534), // Rule ID 14597 //
     /*  549488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  549491 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549494 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549499 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549503 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549510 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549513 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549515 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549520 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549525 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549532 */   GIR_RootConstrainSelectedInstOperands,
     /*  549533 */   // GIR_Coverage, 14597,
     /*  549533 */   GIR_EraseRootFromParent_Done,
     /*  549534 */ // Label 8417: @549534
     /*  549534 */ GIM_Try, /*On fail goto*//*Label 8418*/ GIMT_Encode4(549585), // Rule ID 14598 //
     /*  549539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  549542 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549545 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549550 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549554 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549561 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549564 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549576 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549579 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549583 */   GIR_RootConstrainSelectedInstOperands,
     /*  549584 */   // GIR_Coverage, 14598,
     /*  549584 */   GIR_EraseRootFromParent_Done,
     /*  549585 */ // Label 8418: @549585
     /*  549585 */ GIM_Try, /*On fail goto*//*Label 8419*/ GIMT_Encode4(549636), // Rule ID 14599 //
     /*  549590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  549593 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549596 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549601 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549605 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549612 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549612 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549615 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549627 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549630 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549634 */   GIR_RootConstrainSelectedInstOperands,
     /*  549635 */   // GIR_Coverage, 14599,
     /*  549635 */   GIR_EraseRootFromParent_Done,
     /*  549636 */ // Label 8419: @549636
     /*  549636 */ GIM_Try, /*On fail goto*//*Label 8420*/ GIMT_Encode4(549687), // Rule ID 14600 //
     /*  549641 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  549644 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549647 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549652 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549656 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549663 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549666 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549678 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549681 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549685 */   GIR_RootConstrainSelectedInstOperands,
     /*  549686 */   // GIR_Coverage, 14600,
     /*  549686 */   GIR_EraseRootFromParent_Done,
     /*  549687 */ // Label 8420: @549687
     /*  549687 */ GIM_Try, /*On fail goto*//*Label 8421*/ GIMT_Encode4(549738), // Rule ID 14601 //
     /*  549692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  549695 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549698 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549707 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549714 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549717 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549729 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549736 */   GIR_RootConstrainSelectedInstOperands,
     /*  549737 */   // GIR_Coverage, 14601,
     /*  549737 */   GIR_EraseRootFromParent_Done,
     /*  549738 */ // Label 8421: @549738
     /*  549738 */ GIM_Try, /*On fail goto*//*Label 8422*/ GIMT_Encode4(549789), // Rule ID 14627 //
     /*  549743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  549746 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549754 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549758 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549765 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549765 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549768 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549775 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549783 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549787 */   GIR_RootConstrainSelectedInstOperands,
     /*  549788 */   // GIR_Coverage, 14627,
     /*  549788 */   GIR_EraseRootFromParent_Done,
     /*  549789 */ // Label 8422: @549789
     /*  549789 */ GIM_Try, /*On fail goto*//*Label 8423*/ GIMT_Encode4(549840), // Rule ID 14628 //
     /*  549794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  549797 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549800 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549805 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549809 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549816 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549816 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549819 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549821 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549826 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549831 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549834 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549838 */   GIR_RootConstrainSelectedInstOperands,
     /*  549839 */   // GIR_Coverage, 14628,
     /*  549839 */   GIR_EraseRootFromParent_Done,
     /*  549840 */ // Label 8423: @549840
     /*  549840 */ GIM_Try, /*On fail goto*//*Label 8424*/ GIMT_Encode4(549891), // Rule ID 14629 //
     /*  549845 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  549848 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549851 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549856 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549860 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549867 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549870 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549885 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549889 */   GIR_RootConstrainSelectedInstOperands,
     /*  549890 */   // GIR_Coverage, 14629,
     /*  549890 */   GIR_EraseRootFromParent_Done,
     /*  549891 */ // Label 8424: @549891
     /*  549891 */ GIM_Try, /*On fail goto*//*Label 8425*/ GIMT_Encode4(549942), // Rule ID 14630 //
     /*  549896 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  549899 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549902 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549907 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549911 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549918 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549918 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549921 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549923 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549928 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549933 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549936 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549940 */   GIR_RootConstrainSelectedInstOperands,
     /*  549941 */   // GIR_Coverage, 14630,
     /*  549941 */   GIR_EraseRootFromParent_Done,
     /*  549942 */ // Label 8425: @549942
     /*  549942 */ GIM_Try, /*On fail goto*//*Label 8426*/ GIMT_Encode4(549993), // Rule ID 14631 //
     /*  549947 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  549950 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  549953 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  549958 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  549962 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  549969 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  549969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  549972 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  549974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  549979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  549984 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  549987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  549991 */   GIR_RootConstrainSelectedInstOperands,
     /*  549992 */   // GIR_Coverage, 14631,
     /*  549992 */   GIR_EraseRootFromParent_Done,
     /*  549993 */ // Label 8426: @549993
     /*  549993 */ GIM_Try, /*On fail goto*//*Label 8427*/ GIMT_Encode4(550044), // Rule ID 14592 //
     /*  549998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  550001 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550004 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550009 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550013 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550020 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550020 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550023 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550025 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550030 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550035 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550038 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550042 */   GIR_RootConstrainSelectedInstOperands,
     /*  550043 */   // GIR_Coverage, 14592,
     /*  550043 */   GIR_EraseRootFromParent_Done,
     /*  550044 */ // Label 8427: @550044
     /*  550044 */ GIM_Try, /*On fail goto*//*Label 8428*/ GIMT_Encode4(550095), // Rule ID 14593 //
     /*  550049 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  550052 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550055 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550060 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550064 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550071 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550074 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550076 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550086 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550089 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550093 */   GIR_RootConstrainSelectedInstOperands,
     /*  550094 */   // GIR_Coverage, 14593,
     /*  550094 */   GIR_EraseRootFromParent_Done,
     /*  550095 */ // Label 8428: @550095
     /*  550095 */ GIM_Try, /*On fail goto*//*Label 8429*/ GIMT_Encode4(550146), // Rule ID 14594 //
     /*  550100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  550103 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550106 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550111 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550115 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550122 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550122 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550125 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550132 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550137 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550140 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550144 */   GIR_RootConstrainSelectedInstOperands,
     /*  550145 */   // GIR_Coverage, 14594,
     /*  550145 */   GIR_EraseRootFromParent_Done,
     /*  550146 */ // Label 8429: @550146
     /*  550146 */ GIM_Try, /*On fail goto*//*Label 8430*/ GIMT_Encode4(550197), // Rule ID 14595 //
     /*  550151 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  550154 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550157 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550162 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550166 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550173 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550176 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550178 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550183 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550191 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550195 */   GIR_RootConstrainSelectedInstOperands,
     /*  550196 */   // GIR_Coverage, 14595,
     /*  550196 */   GIR_EraseRootFromParent_Done,
     /*  550197 */ // Label 8430: @550197
     /*  550197 */ GIM_Try, /*On fail goto*//*Label 8431*/ GIMT_Encode4(550248), // Rule ID 14596 //
     /*  550202 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  550205 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550208 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550213 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550217 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550224 */   // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550227 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550239 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550246 */   GIR_RootConstrainSelectedInstOperands,
     /*  550247 */   // GIR_Coverage, 14596,
     /*  550247 */   GIR_EraseRootFromParent_Done,
     /*  550248 */ // Label 8431: @550248
     /*  550248 */ GIM_Try, /*On fail goto*//*Label 8432*/ GIMT_Encode4(550299), // Rule ID 14622 //
     /*  550253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  550256 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550259 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550264 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550268 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550275 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550275 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550278 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550290 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550293 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550297 */   GIR_RootConstrainSelectedInstOperands,
     /*  550298 */   // GIR_Coverage, 14622,
     /*  550298 */   GIR_EraseRootFromParent_Done,
     /*  550299 */ // Label 8432: @550299
     /*  550299 */ GIM_Try, /*On fail goto*//*Label 8433*/ GIMT_Encode4(550350), // Rule ID 14623 //
     /*  550304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  550307 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550310 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550315 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550319 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550326 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550329 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550331 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550341 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550344 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550348 */   GIR_RootConstrainSelectedInstOperands,
     /*  550349 */   // GIR_Coverage, 14623,
     /*  550349 */   GIR_EraseRootFromParent_Done,
     /*  550350 */ // Label 8433: @550350
     /*  550350 */ GIM_Try, /*On fail goto*//*Label 8434*/ GIMT_Encode4(550401), // Rule ID 14624 //
     /*  550355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  550358 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550361 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550366 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550370 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550377 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550380 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550387 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550392 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550395 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550399 */   GIR_RootConstrainSelectedInstOperands,
     /*  550400 */   // GIR_Coverage, 14624,
     /*  550400 */   GIR_EraseRootFromParent_Done,
     /*  550401 */ // Label 8434: @550401
     /*  550401 */ GIM_Try, /*On fail goto*//*Label 8435*/ GIMT_Encode4(550452), // Rule ID 14625 //
     /*  550406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  550409 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550412 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550417 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550421 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550428 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550431 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550443 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550446 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550450 */   GIR_RootConstrainSelectedInstOperands,
     /*  550451 */   // GIR_Coverage, 14625,
     /*  550451 */   GIR_EraseRootFromParent_Done,
     /*  550452 */ // Label 8435: @550452
     /*  550452 */ GIM_Try, /*On fail goto*//*Label 8436*/ GIMT_Encode4(550503), // Rule ID 14626 //
     /*  550457 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  550460 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550463 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  550468 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550472 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  550479 */   // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  550479 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  550482 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  550484 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  550489 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  550494 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550497 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550501 */   GIR_RootConstrainSelectedInstOperands,
     /*  550502 */   // GIR_Coverage, 14626,
     /*  550502 */   GIR_EraseRootFromParent_Done,
     /*  550503 */ // Label 8436: @550503
     /*  550503 */ GIM_Try, /*On fail goto*//*Label 8437*/ GIMT_Encode4(550569), // Rule ID 16278 //
     /*  550508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  550511 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550514 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550521 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550525 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550532 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550532 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  550535 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550557 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550560 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550563 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550567 */   GIR_RootConstrainSelectedInstOperands,
     /*  550568 */   // GIR_Coverage, 16278,
     /*  550568 */   GIR_EraseRootFromParent_Done,
     /*  550569 */ // Label 8437: @550569
     /*  550569 */ GIM_Try, /*On fail goto*//*Label 8438*/ GIMT_Encode4(550635), // Rule ID 16279 //
     /*  550574 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  550577 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550580 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550587 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550591 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550598 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550598 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  550601 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550613 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550618 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550623 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550633 */   GIR_RootConstrainSelectedInstOperands,
     /*  550634 */   // GIR_Coverage, 16279,
     /*  550634 */   GIR_EraseRootFromParent_Done,
     /*  550635 */ // Label 8438: @550635
     /*  550635 */ GIM_Try, /*On fail goto*//*Label 8439*/ GIMT_Encode4(550701), // Rule ID 16280 //
     /*  550640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  550643 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550646 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550653 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550657 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550664 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  550667 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550689 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550692 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550695 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550699 */   GIR_RootConstrainSelectedInstOperands,
     /*  550700 */   // GIR_Coverage, 16280,
     /*  550700 */   GIR_EraseRootFromParent_Done,
     /*  550701 */ // Label 8439: @550701
     /*  550701 */ GIM_Try, /*On fail goto*//*Label 8440*/ GIMT_Encode4(550767), // Rule ID 16281 //
     /*  550706 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  550709 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550712 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550719 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550723 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550730 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550730 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  550733 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550758 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550765 */   GIR_RootConstrainSelectedInstOperands,
     /*  550766 */   // GIR_Coverage, 16281,
     /*  550766 */   GIR_EraseRootFromParent_Done,
     /*  550767 */ // Label 8440: @550767
     /*  550767 */ GIM_Try, /*On fail goto*//*Label 8441*/ GIMT_Encode4(550833), // Rule ID 16282 //
     /*  550772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  550775 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550778 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550789 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550796 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  550799 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550821 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550824 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550827 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550831 */   GIR_RootConstrainSelectedInstOperands,
     /*  550832 */   // GIR_Coverage, 16282,
     /*  550832 */   GIR_EraseRootFromParent_Done,
     /*  550833 */ // Label 8441: @550833
     /*  550833 */ GIM_Try, /*On fail goto*//*Label 8442*/ GIMT_Encode4(550899), // Rule ID 16288 //
     /*  550838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  550841 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550844 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550851 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550855 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550862 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  550865 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550867 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550872 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550877 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550882 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550890 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550893 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550897 */   GIR_RootConstrainSelectedInstOperands,
     /*  550898 */   // GIR_Coverage, 16288,
     /*  550898 */   GIR_EraseRootFromParent_Done,
     /*  550899 */ // Label 8442: @550899
     /*  550899 */ GIM_Try, /*On fail goto*//*Label 8443*/ GIMT_Encode4(550965), // Rule ID 16289 //
     /*  550904 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  550907 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550910 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550917 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550921 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550928 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  550931 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550933 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  550938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  550943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  550948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  550953 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  550959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  550963 */   GIR_RootConstrainSelectedInstOperands,
     /*  550964 */   // GIR_Coverage, 16289,
     /*  550964 */   GIR_EraseRootFromParent_Done,
     /*  550965 */ // Label 8443: @550965
     /*  550965 */ GIM_Try, /*On fail goto*//*Label 8444*/ GIMT_Encode4(551031), // Rule ID 16290 //
     /*  550970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  550973 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  550976 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  550983 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  550987 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  550994 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  550994 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  550997 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  550999 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551004 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551014 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551019 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551022 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551025 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551029 */   GIR_RootConstrainSelectedInstOperands,
     /*  551030 */   // GIR_Coverage, 16290,
     /*  551030 */   GIR_EraseRootFromParent_Done,
     /*  551031 */ // Label 8444: @551031
     /*  551031 */ GIM_Try, /*On fail goto*//*Label 8445*/ GIMT_Encode4(551097), // Rule ID 16291 //
     /*  551036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  551039 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551042 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551049 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551053 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551060 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551060 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551063 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551075 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551080 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551085 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551088 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551091 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551095 */   GIR_RootConstrainSelectedInstOperands,
     /*  551096 */   // GIR_Coverage, 16291,
     /*  551096 */   GIR_EraseRootFromParent_Done,
     /*  551097 */ // Label 8445: @551097
     /*  551097 */ GIM_Try, /*On fail goto*//*Label 8446*/ GIMT_Encode4(551163), // Rule ID 16292 //
     /*  551102 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  551105 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551108 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551115 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551119 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551126 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551126 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551129 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551131 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551136 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551141 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551146 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551151 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551154 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551157 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551161 */   GIR_RootConstrainSelectedInstOperands,
     /*  551162 */   // GIR_Coverage, 16292,
     /*  551162 */   GIR_EraseRootFromParent_Done,
     /*  551163 */ // Label 8446: @551163
     /*  551163 */ GIM_Try, /*On fail goto*//*Label 8447*/ GIMT_Encode4(551229), // Rule ID 16298 //
     /*  551168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  551171 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551174 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551181 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551185 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551192 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  551195 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551202 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551207 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551217 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551220 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551223 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551227 */   GIR_RootConstrainSelectedInstOperands,
     /*  551228 */   // GIR_Coverage, 16298,
     /*  551228 */   GIR_EraseRootFromParent_Done,
     /*  551229 */ // Label 8447: @551229
     /*  551229 */ GIM_Try, /*On fail goto*//*Label 8448*/ GIMT_Encode4(551295), // Rule ID 16299 //
     /*  551234 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  551237 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551240 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551258 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  551261 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551263 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551283 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551286 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551293 */   GIR_RootConstrainSelectedInstOperands,
     /*  551294 */   // GIR_Coverage, 16299,
     /*  551294 */   GIR_EraseRootFromParent_Done,
     /*  551295 */ // Label 8448: @551295
     /*  551295 */ GIM_Try, /*On fail goto*//*Label 8449*/ GIMT_Encode4(551361), // Rule ID 16300 //
     /*  551300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  551303 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551306 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551317 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551324 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  551327 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551349 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551352 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551355 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551359 */   GIR_RootConstrainSelectedInstOperands,
     /*  551360 */   // GIR_Coverage, 16300,
     /*  551360 */   GIR_EraseRootFromParent_Done,
     /*  551361 */ // Label 8449: @551361
     /*  551361 */ GIM_Try, /*On fail goto*//*Label 8450*/ GIMT_Encode4(551427), // Rule ID 16301 //
     /*  551366 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  551369 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551372 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551379 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551383 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551390 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551390 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  551393 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551395 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551400 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551415 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551421 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551425 */   GIR_RootConstrainSelectedInstOperands,
     /*  551426 */   // GIR_Coverage, 16301,
     /*  551426 */   GIR_EraseRootFromParent_Done,
     /*  551427 */ // Label 8450: @551427
     /*  551427 */ GIM_Try, /*On fail goto*//*Label 8451*/ GIMT_Encode4(551493), // Rule ID 16302 //
     /*  551432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  551435 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551438 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551445 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551449 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551456 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551456 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  551459 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551484 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551487 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551491 */   GIR_RootConstrainSelectedInstOperands,
     /*  551492 */   // GIR_Coverage, 16302,
     /*  551492 */   GIR_EraseRootFromParent_Done,
     /*  551493 */ // Label 8451: @551493
     /*  551493 */ GIM_Try, /*On fail goto*//*Label 8452*/ GIMT_Encode4(551559), // Rule ID 16308 //
     /*  551498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  551501 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551504 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551511 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551515 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551522 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551522 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551525 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551527 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551532 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551547 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551550 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551557 */   GIR_RootConstrainSelectedInstOperands,
     /*  551558 */   // GIR_Coverage, 16308,
     /*  551558 */   GIR_EraseRootFromParent_Done,
     /*  551559 */ // Label 8452: @551559
     /*  551559 */ GIM_Try, /*On fail goto*//*Label 8453*/ GIMT_Encode4(551625), // Rule ID 16309 //
     /*  551564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  551567 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551570 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551577 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551581 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551588 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551588 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551591 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551613 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551616 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551619 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551623 */   GIR_RootConstrainSelectedInstOperands,
     /*  551624 */   // GIR_Coverage, 16309,
     /*  551624 */   GIR_EraseRootFromParent_Done,
     /*  551625 */ // Label 8453: @551625
     /*  551625 */ GIM_Try, /*On fail goto*//*Label 8454*/ GIMT_Encode4(551691), // Rule ID 16310 //
     /*  551630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  551633 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551636 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551643 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551647 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551654 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551657 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551664 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551679 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551682 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551689 */   GIR_RootConstrainSelectedInstOperands,
     /*  551690 */   // GIR_Coverage, 16310,
     /*  551690 */   GIR_EraseRootFromParent_Done,
     /*  551691 */ // Label 8454: @551691
     /*  551691 */ GIM_Try, /*On fail goto*//*Label 8455*/ GIMT_Encode4(551757), // Rule ID 16311 //
     /*  551696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  551699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551702 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551709 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551713 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551720 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551720 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551723 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551725 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551745 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551748 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551751 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551755 */   GIR_RootConstrainSelectedInstOperands,
     /*  551756 */   // GIR_Coverage, 16311,
     /*  551756 */   GIR_EraseRootFromParent_Done,
     /*  551757 */ // Label 8455: @551757
     /*  551757 */ GIM_Try, /*On fail goto*//*Label 8456*/ GIMT_Encode4(551823), // Rule ID 16312 //
     /*  551762 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  551765 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551768 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  551775 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551779 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  551786 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  551786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  551789 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  551791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551817 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551821 */   GIR_RootConstrainSelectedInstOperands,
     /*  551822 */   // GIR_Coverage, 16312,
     /*  551822 */   GIR_EraseRootFromParent_Done,
     /*  551823 */ // Label 8456: @551823
     /*  551823 */ GIM_Try, /*On fail goto*//*Label 8457*/ GIMT_Encode4(551887), // Rule ID 25981 //
     /*  551828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode0),
     /*  551831 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551834 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  551839 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551843 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  551850 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  551850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN),
     /*  551853 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  551855 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551860 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551878 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551881 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551885 */   GIR_RootConstrainSelectedInstOperands,
     /*  551886 */   // GIR_Coverage, 25981,
     /*  551886 */   GIR_EraseRootFromParent_Done,
     /*  551887 */ // Label 8457: @551887
     /*  551887 */ GIM_Try, /*On fail goto*//*Label 8458*/ GIMT_Encode4(551951), // Rule ID 25982 //
     /*  551892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode1),
     /*  551895 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551898 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  551903 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551907 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  551914 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  551914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN),
     /*  551917 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  551919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551934 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  551939 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551942 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  551945 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  551949 */   GIR_RootConstrainSelectedInstOperands,
     /*  551950 */   // GIR_Coverage, 25982,
     /*  551950 */   GIR_EraseRootFromParent_Done,
     /*  551951 */ // Label 8458: @551951
     /*  551951 */ GIM_Try, /*On fail goto*//*Label 8459*/ GIMT_Encode4(552015), // Rule ID 25983 //
     /*  551956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode2),
     /*  551959 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  551962 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  551967 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  551971 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  551978 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  551978 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN),
     /*  551981 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  551983 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  551988 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  551993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  551998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552003 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552009 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552013 */   GIR_RootConstrainSelectedInstOperands,
     /*  552014 */   // GIR_Coverage, 25983,
     /*  552014 */   GIR_EraseRootFromParent_Done,
     /*  552015 */ // Label 8459: @552015
     /*  552015 */ GIM_Try, /*On fail goto*//*Label 8460*/ GIMT_Encode4(552079), // Rule ID 25984 //
     /*  552020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode3),
     /*  552023 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552026 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552031 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552035 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552042 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN),
     /*  552045 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552047 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552052 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552057 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552062 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552067 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552070 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552073 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552077 */   GIR_RootConstrainSelectedInstOperands,
     /*  552078 */   // GIR_Coverage, 25984,
     /*  552078 */   GIR_EraseRootFromParent_Done,
     /*  552079 */ // Label 8460: @552079
     /*  552079 */ GIM_Try, /*On fail goto*//*Label 8461*/ GIMT_Encode4(552143), // Rule ID 25985 //
     /*  552084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset_HwMode4),
     /*  552087 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552090 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552095 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552099 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552106 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552106 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN),
     /*  552109 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552121 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552126 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552131 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552134 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552137 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552141 */   GIR_RootConstrainSelectedInstOperands,
     /*  552142 */   // GIR_Coverage, 25985,
     /*  552142 */   GIR_EraseRootFromParent_Done,
     /*  552143 */ // Label 8461: @552143
     /*  552143 */ GIM_Try, /*On fail goto*//*Label 8462*/ GIMT_Encode4(552207), // Rule ID 25991 //
     /*  552148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode0),
     /*  552151 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552154 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552159 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552163 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552170 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN),
     /*  552173 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552175 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552180 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552195 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552198 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552201 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552205 */   GIR_RootConstrainSelectedInstOperands,
     /*  552206 */   // GIR_Coverage, 25991,
     /*  552206 */   GIR_EraseRootFromParent_Done,
     /*  552207 */ // Label 8462: @552207
     /*  552207 */ GIM_Try, /*On fail goto*//*Label 8463*/ GIMT_Encode4(552271), // Rule ID 25992 //
     /*  552212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode1),
     /*  552215 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552218 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552223 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552227 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552234 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN),
     /*  552237 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552239 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552244 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552249 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552254 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552259 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552262 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552265 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552269 */   GIR_RootConstrainSelectedInstOperands,
     /*  552270 */   // GIR_Coverage, 25992,
     /*  552270 */   GIR_EraseRootFromParent_Done,
     /*  552271 */ // Label 8463: @552271
     /*  552271 */ GIM_Try, /*On fail goto*//*Label 8464*/ GIMT_Encode4(552335), // Rule ID 25993 //
     /*  552276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode2),
     /*  552279 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552282 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552287 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552291 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552298 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN),
     /*  552301 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552313 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552318 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552333 */   GIR_RootConstrainSelectedInstOperands,
     /*  552334 */   // GIR_Coverage, 25993,
     /*  552334 */   GIR_EraseRootFromParent_Done,
     /*  552335 */ // Label 8464: @552335
     /*  552335 */ GIM_Try, /*On fail goto*//*Label 8465*/ GIMT_Encode4(552399), // Rule ID 25994 //
     /*  552340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode3),
     /*  552343 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552351 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552355 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552362 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN),
     /*  552365 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552372 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552377 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552382 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552387 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552390 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552397 */   GIR_RootConstrainSelectedInstOperands,
     /*  552398 */   // GIR_Coverage, 25994,
     /*  552398 */   GIR_EraseRootFromParent_Done,
     /*  552399 */ // Label 8465: @552399
     /*  552399 */ GIM_Try, /*On fail goto*//*Label 8466*/ GIMT_Encode4(552463), // Rule ID 25995 //
     /*  552404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HwMode4),
     /*  552407 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552410 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  552415 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552419 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
     /*  552426 */   // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
     /*  552426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN),
     /*  552429 */   GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  552431 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  552436 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  552441 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  552446 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  552451 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552457 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552461 */   GIR_RootConstrainSelectedInstOperands,
     /*  552462 */   // GIR_Coverage, 25995,
     /*  552462 */   GIR_EraseRootFromParent_Done,
     /*  552463 */ // Label 8466: @552463
     /*  552463 */ GIM_Try, /*On fail goto*//*Label 8467*/ GIMT_Encode4(552583), // Rule ID 29392 //
     /*  552468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  552471 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552474 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  552478 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  552483 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552487 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  552494 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  552494 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  552497 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552501 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552506 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  552512 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552517 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552522 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  552525 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552529 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552534 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  552540 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552545 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  552553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  552558 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  552561 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  552564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  552569 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  552574 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552577 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552581 */   GIR_RootConstrainSelectedInstOperands,
     /*  552582 */   // GIR_Coverage, 29392,
     /*  552582 */   GIR_EraseRootFromParent_Done,
     /*  552583 */ // Label 8467: @552583
     /*  552583 */ GIM_Try, /*On fail goto*//*Label 8468*/ GIMT_Encode4(552703), // Rule ID 29393 //
     /*  552588 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  552591 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552594 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  552598 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  552603 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552607 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  552614 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  552614 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  552617 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552621 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552626 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  552632 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552637 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552642 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  552645 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552649 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552654 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  552660 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552665 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552670 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  552673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  552678 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  552681 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  552684 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  552689 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  552694 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552697 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552701 */   GIR_RootConstrainSelectedInstOperands,
     /*  552702 */   // GIR_Coverage, 29393,
     /*  552702 */   GIR_EraseRootFromParent_Done,
     /*  552703 */ // Label 8468: @552703
     /*  552703 */ GIM_Try, /*On fail goto*//*Label 8469*/ GIMT_Encode4(552823), // Rule ID 29394 //
     /*  552708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  552711 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552714 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  552718 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  552723 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552727 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  552734 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  552734 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  552737 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552741 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552746 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  552752 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552757 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552762 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  552765 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552769 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552774 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  552780 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552785 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  552793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  552798 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  552801 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  552804 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  552809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  552814 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552817 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552821 */   GIR_RootConstrainSelectedInstOperands,
     /*  552822 */   // GIR_Coverage, 29394,
     /*  552822 */   GIR_EraseRootFromParent_Done,
     /*  552823 */ // Label 8469: @552823
     /*  552823 */ GIM_Try, /*On fail goto*//*Label 8470*/ GIMT_Encode4(552943), // Rule ID 29395 //
     /*  552828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  552831 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552834 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  552838 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  552843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552847 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  552854 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  552854 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  552857 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552861 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552866 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  552872 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552877 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552882 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  552885 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552889 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552894 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  552900 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552905 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  552910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  552913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  552918 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  552921 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  552924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  552929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  552934 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  552937 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  552941 */   GIR_RootConstrainSelectedInstOperands,
     /*  552942 */   // GIR_Coverage, 29395,
     /*  552942 */   GIR_EraseRootFromParent_Done,
     /*  552943 */ // Label 8470: @552943
     /*  552943 */ GIM_Try, /*On fail goto*//*Label 8471*/ GIMT_Encode4(553063), // Rule ID 29396 //
     /*  552948 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  552951 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  552954 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  552958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  552963 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  552967 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  552974 */   // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  552974 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  552977 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  552981 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  552986 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  552992 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  552997 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553002 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  553005 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553009 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553014 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  553020 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553025 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553030 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  553033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  553038 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  553041 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  553044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  553049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  553054 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553057 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553061 */   GIR_RootConstrainSelectedInstOperands,
     /*  553062 */   // GIR_Coverage, 29396,
     /*  553062 */   GIR_EraseRootFromParent_Done,
     /*  553063 */ // Label 8471: @553063
     /*  553063 */ GIM_Try, /*On fail goto*//*Label 8472*/ GIMT_Encode4(553183), // Rule ID 29508 //
     /*  553068 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  553071 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553074 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  553078 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  553083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  553094 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  553094 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  553097 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553101 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553106 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  553112 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553117 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553122 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  553125 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553129 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553134 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  553140 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553145 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553150 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  553153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  553158 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  553161 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  553164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  553169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  553174 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553177 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553181 */   GIR_RootConstrainSelectedInstOperands,
     /*  553182 */   // GIR_Coverage, 29508,
     /*  553182 */   GIR_EraseRootFromParent_Done,
     /*  553183 */ // Label 8472: @553183
     /*  553183 */ GIM_Try, /*On fail goto*//*Label 8473*/ GIMT_Encode4(553303), // Rule ID 29509 //
     /*  553188 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  553191 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553194 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  553198 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  553203 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553207 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  553214 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  553214 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  553217 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553221 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553226 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  553232 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553237 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553242 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  553245 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553249 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553254 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  553260 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553265 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  553273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  553278 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  553281 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  553284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  553289 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  553294 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553297 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553301 */   GIR_RootConstrainSelectedInstOperands,
     /*  553302 */   // GIR_Coverage, 29509,
     /*  553302 */   GIR_EraseRootFromParent_Done,
     /*  553303 */ // Label 8473: @553303
     /*  553303 */ GIM_Try, /*On fail goto*//*Label 8474*/ GIMT_Encode4(553423), // Rule ID 29510 //
     /*  553308 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  553311 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553314 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  553318 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  553323 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553327 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  553334 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  553334 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  553337 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553341 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553346 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  553352 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553357 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553362 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  553365 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553369 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553374 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  553380 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553385 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553390 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  553393 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  553398 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  553401 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  553404 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  553409 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  553414 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553417 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553421 */   GIR_RootConstrainSelectedInstOperands,
     /*  553422 */   // GIR_Coverage, 29510,
     /*  553422 */   GIR_EraseRootFromParent_Done,
     /*  553423 */ // Label 8474: @553423
     /*  553423 */ GIM_Try, /*On fail goto*//*Label 8475*/ GIMT_Encode4(553543), // Rule ID 29511 //
     /*  553428 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  553431 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553434 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  553438 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  553443 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553447 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  553454 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  553454 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  553457 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553461 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553466 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  553472 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553477 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553482 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  553485 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553489 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553494 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  553500 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553505 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553510 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  553513 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  553518 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  553521 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  553524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  553529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  553534 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553541 */   GIR_RootConstrainSelectedInstOperands,
     /*  553542 */   // GIR_Coverage, 29511,
     /*  553542 */   GIR_EraseRootFromParent_Done,
     /*  553543 */ // Label 8475: @553543
     /*  553543 */ GIM_Try, /*On fail goto*//*Label 8476*/ GIMT_Encode4(553663), // Rule ID 29512 //
     /*  553548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  553551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553554 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  553558 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  553563 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553567 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  553574 */   // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  553574 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  553577 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553581 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553586 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  553592 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553597 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553602 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  553605 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  553609 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  553614 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  553620 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  553625 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  553630 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  553633 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  553638 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  553641 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  553644 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  553649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  553654 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553661 */   GIR_RootConstrainSelectedInstOperands,
     /*  553662 */   // GIR_Coverage, 29512,
     /*  553662 */   GIR_EraseRootFromParent_Done,
     /*  553663 */ // Label 8476: @553663
     /*  553663 */ GIM_Try, /*On fail goto*//*Label 8477*/ GIMT_Encode4(553724), // Rule ID 16273 //
     /*  553668 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  553671 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553674 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  553681 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553685 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  553692 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  553692 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  553695 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  553697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  553702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  553707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  553712 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553715 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553718 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553722 */   GIR_RootConstrainSelectedInstOperands,
     /*  553723 */   // GIR_Coverage, 16273,
     /*  553723 */   GIR_EraseRootFromParent_Done,
     /*  553724 */ // Label 8477: @553724
     /*  553724 */ GIM_Try, /*On fail goto*//*Label 8478*/ GIMT_Encode4(553785), // Rule ID 16274 //
     /*  553729 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  553732 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553735 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  553742 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553746 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  553753 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  553753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  553756 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  553758 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  553763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  553768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  553773 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553776 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553779 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553783 */   GIR_RootConstrainSelectedInstOperands,
     /*  553784 */   // GIR_Coverage, 16274,
     /*  553784 */   GIR_EraseRootFromParent_Done,
     /*  553785 */ // Label 8478: @553785
     /*  553785 */ GIM_Try, /*On fail goto*//*Label 8479*/ GIMT_Encode4(553846), // Rule ID 16275 //
     /*  553790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  553793 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553796 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  553803 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553807 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  553814 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  553814 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  553817 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  553819 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  553824 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  553829 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  553834 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553837 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553840 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553844 */   GIR_RootConstrainSelectedInstOperands,
     /*  553845 */   // GIR_Coverage, 16275,
     /*  553845 */   GIR_EraseRootFromParent_Done,
     /*  553846 */ // Label 8479: @553846
     /*  553846 */ GIM_Try, /*On fail goto*//*Label 8480*/ GIMT_Encode4(553907), // Rule ID 16276 //
     /*  553851 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  553854 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553857 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  553864 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553868 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  553875 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  553875 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  553878 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  553880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  553885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  553890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  553895 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553898 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553901 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553905 */   GIR_RootConstrainSelectedInstOperands,
     /*  553906 */   // GIR_Coverage, 16276,
     /*  553906 */   GIR_EraseRootFromParent_Done,
     /*  553907 */ // Label 8480: @553907
     /*  553907 */ GIM_Try, /*On fail goto*//*Label 8481*/ GIMT_Encode4(553968), // Rule ID 16277 //
     /*  553912 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  553915 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553918 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  553925 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553929 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  553936 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  553936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  553939 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  553941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  553946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  553951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  553956 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553959 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  553962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  553966 */   GIR_RootConstrainSelectedInstOperands,
     /*  553967 */   // GIR_Coverage, 16277,
     /*  553967 */   GIR_EraseRootFromParent_Done,
     /*  553968 */ // Label 8481: @553968
     /*  553968 */ GIM_Try, /*On fail goto*//*Label 8482*/ GIMT_Encode4(554029), // Rule ID 16283 //
     /*  553973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  553976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  553979 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  553986 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  553990 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  553997 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  553997 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554000 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554017 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554020 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554027 */   GIR_RootConstrainSelectedInstOperands,
     /*  554028 */   // GIR_Coverage, 16283,
     /*  554028 */   GIR_EraseRootFromParent_Done,
     /*  554029 */ // Label 8482: @554029
     /*  554029 */ GIM_Try, /*On fail goto*//*Label 8483*/ GIMT_Encode4(554090), // Rule ID 16284 //
     /*  554034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  554037 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554040 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554047 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554051 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554058 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554061 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554063 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554078 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554081 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554088 */   GIR_RootConstrainSelectedInstOperands,
     /*  554089 */   // GIR_Coverage, 16284,
     /*  554089 */   GIR_EraseRootFromParent_Done,
     /*  554090 */ // Label 8483: @554090
     /*  554090 */ GIM_Try, /*On fail goto*//*Label 8484*/ GIMT_Encode4(554151), // Rule ID 16285 //
     /*  554095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  554098 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554101 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554108 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554112 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554119 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554119 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554122 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554124 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554129 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554139 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554142 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554145 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554149 */   GIR_RootConstrainSelectedInstOperands,
     /*  554150 */   // GIR_Coverage, 16285,
     /*  554150 */   GIR_EraseRootFromParent_Done,
     /*  554151 */ // Label 8484: @554151
     /*  554151 */ GIM_Try, /*On fail goto*//*Label 8485*/ GIMT_Encode4(554212), // Rule ID 16286 //
     /*  554156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  554159 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554162 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554173 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554180 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554180 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554183 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554195 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554203 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554206 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554210 */   GIR_RootConstrainSelectedInstOperands,
     /*  554211 */   // GIR_Coverage, 16286,
     /*  554211 */   GIR_EraseRootFromParent_Done,
     /*  554212 */ // Label 8485: @554212
     /*  554212 */ GIM_Try, /*On fail goto*//*Label 8486*/ GIMT_Encode4(554273), // Rule ID 16287 //
     /*  554217 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  554220 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554223 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554230 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554234 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554241 */   // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554241 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554244 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554246 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554251 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554256 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554267 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554271 */   GIR_RootConstrainSelectedInstOperands,
     /*  554272 */   // GIR_Coverage, 16287,
     /*  554272 */   GIR_EraseRootFromParent_Done,
     /*  554273 */ // Label 8486: @554273
     /*  554273 */ GIM_Try, /*On fail goto*//*Label 8487*/ GIMT_Encode4(554334), // Rule ID 16293 //
     /*  554278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  554281 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554284 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554291 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554295 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554302 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554302 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  554305 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554307 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554312 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554325 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554328 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554332 */   GIR_RootConstrainSelectedInstOperands,
     /*  554333 */   // GIR_Coverage, 16293,
     /*  554333 */   GIR_EraseRootFromParent_Done,
     /*  554334 */ // Label 8487: @554334
     /*  554334 */ GIM_Try, /*On fail goto*//*Label 8488*/ GIMT_Encode4(554395), // Rule ID 16294 //
     /*  554339 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  554342 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554345 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554363 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  554366 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554368 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554383 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554386 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554389 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554393 */   GIR_RootConstrainSelectedInstOperands,
     /*  554394 */   // GIR_Coverage, 16294,
     /*  554394 */   GIR_EraseRootFromParent_Done,
     /*  554395 */ // Label 8488: @554395
     /*  554395 */ GIM_Try, /*On fail goto*//*Label 8489*/ GIMT_Encode4(554456), // Rule ID 16295 //
     /*  554400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  554403 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554406 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554413 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554417 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554424 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  554427 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554429 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554434 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554439 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554444 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554447 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554450 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554454 */   GIR_RootConstrainSelectedInstOperands,
     /*  554455 */   // GIR_Coverage, 16295,
     /*  554455 */   GIR_EraseRootFromParent_Done,
     /*  554456 */ // Label 8489: @554456
     /*  554456 */ GIM_Try, /*On fail goto*//*Label 8490*/ GIMT_Encode4(554517), // Rule ID 16296 //
     /*  554461 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  554464 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554467 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554474 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554478 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554485 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  554488 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554490 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554505 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554508 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554511 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554515 */   GIR_RootConstrainSelectedInstOperands,
     /*  554516 */   // GIR_Coverage, 16296,
     /*  554516 */   GIR_EraseRootFromParent_Done,
     /*  554517 */ // Label 8490: @554517
     /*  554517 */ GIM_Try, /*On fail goto*//*Label 8491*/ GIMT_Encode4(554578), // Rule ID 16297 //
     /*  554522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  554525 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554528 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554535 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554539 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554546 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  554549 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554551 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554556 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554566 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554569 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554572 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554576 */   GIR_RootConstrainSelectedInstOperands,
     /*  554577 */   // GIR_Coverage, 16297,
     /*  554577 */   GIR_EraseRootFromParent_Done,
     /*  554578 */ // Label 8491: @554578
     /*  554578 */ GIM_Try, /*On fail goto*//*Label 8492*/ GIMT_Encode4(554639), // Rule ID 16303 //
     /*  554583 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  554586 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554589 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554600 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554607 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554607 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554610 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554612 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554617 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554622 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554627 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554630 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554633 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554637 */   GIR_RootConstrainSelectedInstOperands,
     /*  554638 */   // GIR_Coverage, 16303,
     /*  554638 */   GIR_EraseRootFromParent_Done,
     /*  554639 */ // Label 8492: @554639
     /*  554639 */ GIM_Try, /*On fail goto*//*Label 8493*/ GIMT_Encode4(554700), // Rule ID 16304 //
     /*  554644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  554647 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554650 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554657 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554661 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554668 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554671 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554688 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554691 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554694 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554698 */   GIR_RootConstrainSelectedInstOperands,
     /*  554699 */   // GIR_Coverage, 16304,
     /*  554699 */   GIR_EraseRootFromParent_Done,
     /*  554700 */ // Label 8493: @554700
     /*  554700 */ GIM_Try, /*On fail goto*//*Label 8494*/ GIMT_Encode4(554761), // Rule ID 16305 //
     /*  554705 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  554708 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554711 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554718 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554722 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554729 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554732 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554739 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554744 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554749 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554752 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554759 */   GIR_RootConstrainSelectedInstOperands,
     /*  554760 */   // GIR_Coverage, 16305,
     /*  554760 */   GIR_EraseRootFromParent_Done,
     /*  554761 */ // Label 8494: @554761
     /*  554761 */ GIM_Try, /*On fail goto*//*Label 8495*/ GIMT_Encode4(554822), // Rule ID 16306 //
     /*  554766 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  554769 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554772 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554779 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554783 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554790 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554793 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554800 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554805 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554810 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554813 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554816 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554820 */   GIR_RootConstrainSelectedInstOperands,
     /*  554821 */   // GIR_Coverage, 16306,
     /*  554821 */   GIR_EraseRootFromParent_Done,
     /*  554822 */ // Label 8495: @554822
     /*  554822 */ GIM_Try, /*On fail goto*//*Label 8496*/ GIMT_Encode4(554883), // Rule ID 16307 //
     /*  554827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  554830 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554833 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  554840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554844 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  554851 */   // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  554851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  554854 */   GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  554856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  554861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  554866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  554871 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554874 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554877 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554881 */   GIR_RootConstrainSelectedInstOperands,
     /*  554882 */   // GIR_Coverage, 16307,
     /*  554882 */   GIR_EraseRootFromParent_Done,
     /*  554883 */ // Label 8496: @554883
     /*  554883 */ GIM_Try, /*On fail goto*//*Label 8497*/ GIMT_Encode4(554999), // Rule ID 29402 //
     /*  554888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  554891 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  554894 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  554899 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  554903 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  554910 */   // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  554910 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  554913 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  554917 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  554922 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  554928 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  554933 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  554938 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  554941 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  554945 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  554950 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  554956 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  554961 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  554966 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  554969 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  554974 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  554977 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  554980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  554985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  554990 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  554993 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  554997 */   GIR_RootConstrainSelectedInstOperands,
     /*  554998 */   // GIR_Coverage, 29402,
     /*  554998 */   GIR_EraseRootFromParent_Done,
     /*  554999 */ // Label 8497: @554999
     /*  554999 */ GIM_Try, /*On fail goto*//*Label 8498*/ GIMT_Encode4(555115), // Rule ID 29403 //
     /*  555004 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  555007 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555010 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555026 */   // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555026 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555029 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555033 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555038 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555044 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555049 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555054 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555057 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555061 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555066 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555072 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555077 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555085 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555090 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555093 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555096 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555101 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555106 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555109 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555113 */   GIR_RootConstrainSelectedInstOperands,
     /*  555114 */   // GIR_Coverage, 29403,
     /*  555114 */   GIR_EraseRootFromParent_Done,
     /*  555115 */ // Label 8498: @555115
     /*  555115 */ GIM_Try, /*On fail goto*//*Label 8499*/ GIMT_Encode4(555231), // Rule ID 29404 //
     /*  555120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  555123 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555126 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555131 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555135 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555142 */   // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555142 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555145 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555149 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555154 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555160 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555165 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555170 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555173 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555177 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555182 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555188 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555193 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555206 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555209 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555212 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555222 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555225 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555229 */   GIR_RootConstrainSelectedInstOperands,
     /*  555230 */   // GIR_Coverage, 29404,
     /*  555230 */   GIR_EraseRootFromParent_Done,
     /*  555231 */ // Label 8499: @555231
     /*  555231 */ GIM_Try, /*On fail goto*//*Label 8500*/ GIMT_Encode4(555347), // Rule ID 29405 //
     /*  555236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  555239 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555242 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555247 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555251 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555258 */   // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555258 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555261 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555265 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555270 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555276 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555281 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555286 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555289 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555293 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555298 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555304 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555309 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555314 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555322 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555325 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555338 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555341 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555345 */   GIR_RootConstrainSelectedInstOperands,
     /*  555346 */   // GIR_Coverage, 29405,
     /*  555346 */   GIR_EraseRootFromParent_Done,
     /*  555347 */ // Label 8500: @555347
     /*  555347 */ GIM_Try, /*On fail goto*//*Label 8501*/ GIMT_Encode4(555463), // Rule ID 29406 //
     /*  555352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  555355 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555358 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555367 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555374 */   // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555374 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555377 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555381 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555386 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555392 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555397 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555402 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555405 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555409 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555414 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555420 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555425 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555438 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555441 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555444 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555449 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555454 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555457 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555461 */   GIR_RootConstrainSelectedInstOperands,
     /*  555462 */   // GIR_Coverage, 29406,
     /*  555462 */   GIR_EraseRootFromParent_Done,
     /*  555463 */ // Label 8501: @555463
     /*  555463 */ GIM_Try, /*On fail goto*//*Label 8502*/ GIMT_Encode4(555579), // Rule ID 29518 //
     /*  555468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  555471 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555474 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555479 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555483 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555490 */   // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555490 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555493 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555497 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555502 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555508 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555513 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555518 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555521 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555525 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555530 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555536 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555541 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555549 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555554 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555557 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555570 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555573 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555577 */   GIR_RootConstrainSelectedInstOperands,
     /*  555578 */   // GIR_Coverage, 29518,
     /*  555578 */   GIR_EraseRootFromParent_Done,
     /*  555579 */ // Label 8502: @555579
     /*  555579 */ GIM_Try, /*On fail goto*//*Label 8503*/ GIMT_Encode4(555695), // Rule ID 29519 //
     /*  555584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  555587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555590 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555599 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555606 */   // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555606 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555609 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555613 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555618 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555624 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555629 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555634 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555637 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555641 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555646 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555652 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555657 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555662 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555665 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555670 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555673 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555676 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555686 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555689 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555693 */   GIR_RootConstrainSelectedInstOperands,
     /*  555694 */   // GIR_Coverage, 29519,
     /*  555694 */   GIR_EraseRootFromParent_Done,
     /*  555695 */ // Label 8503: @555695
     /*  555695 */ GIM_Try, /*On fail goto*//*Label 8504*/ GIMT_Encode4(555811), // Rule ID 29520 //
     /*  555700 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  555703 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555706 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555711 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555715 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555722 */   // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555722 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555725 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555729 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555734 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555740 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555745 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555750 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555753 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555757 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555762 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555768 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555773 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555781 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555786 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555789 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555802 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555805 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555809 */   GIR_RootConstrainSelectedInstOperands,
     /*  555810 */   // GIR_Coverage, 29520,
     /*  555810 */   GIR_EraseRootFromParent_Done,
     /*  555811 */ // Label 8504: @555811
     /*  555811 */ GIM_Try, /*On fail goto*//*Label 8505*/ GIMT_Encode4(555927), // Rule ID 29521 //
     /*  555816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  555819 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555822 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555827 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555831 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555838 */   // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555838 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555841 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555845 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555850 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555856 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555861 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555866 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555869 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555873 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555878 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  555884 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555889 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555894 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  555897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  555902 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  555905 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  555908 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  555913 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  555918 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  555921 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  555925 */   GIR_RootConstrainSelectedInstOperands,
     /*  555926 */   // GIR_Coverage, 29521,
     /*  555926 */   GIR_EraseRootFromParent_Done,
     /*  555927 */ // Label 8505: @555927
     /*  555927 */ GIM_Try, /*On fail goto*//*Label 8506*/ GIMT_Encode4(556043), // Rule ID 29522 //
     /*  555932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  555935 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  555938 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  555943 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  555947 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  555954 */   // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  555954 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  555957 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555961 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555966 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  555972 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  555977 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  555982 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  555985 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  555989 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  555994 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  556000 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  556005 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  556010 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  556013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  556018 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  556021 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  556024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  556029 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  556034 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  556037 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556041 */   GIR_RootConstrainSelectedInstOperands,
     /*  556042 */   // GIR_Coverage, 29522,
     /*  556042 */   GIR_EraseRootFromParent_Done,
     /*  556043 */ // Label 8506: @556043
     /*  556043 */ GIM_Try, /*On fail goto*//*Label 8507*/ GIMT_Encode4(556110), // Rule ID 12887 //
     /*  556048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  556051 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  556054 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  556061 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556079 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556082 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556087 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556104 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556108 */   GIR_RootConstrainSelectedInstOperands,
     /*  556109 */   // GIR_Coverage, 12887,
     /*  556109 */   GIR_EraseRootFromParent_Done,
     /*  556110 */ // Label 8507: @556110
     /*  556110 */ GIM_Try, /*On fail goto*//*Label 8508*/ GIMT_Encode4(556177), // Rule ID 12888 //
     /*  556115 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  556118 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  556121 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  556128 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556135 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556139 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556146 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556149 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556154 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556171 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556175 */   GIR_RootConstrainSelectedInstOperands,
     /*  556176 */   // GIR_Coverage, 12888,
     /*  556176 */   GIR_EraseRootFromParent_Done,
     /*  556177 */ // Label 8508: @556177
     /*  556177 */ GIM_Try, /*On fail goto*//*Label 8509*/ GIMT_Encode4(556244), // Rule ID 12889 //
     /*  556182 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  556185 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  556188 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  556195 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556213 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556216 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556221 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556233 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556238 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556242 */   GIR_RootConstrainSelectedInstOperands,
     /*  556243 */   // GIR_Coverage, 12889,
     /*  556243 */   GIR_EraseRootFromParent_Done,
     /*  556244 */ // Label 8509: @556244
     /*  556244 */ GIM_Try, /*On fail goto*//*Label 8510*/ GIMT_Encode4(556311), // Rule ID 12890 //
     /*  556249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  556252 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  556255 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  556262 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556269 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556273 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556280 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556288 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556300 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556305 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556309 */   GIR_RootConstrainSelectedInstOperands,
     /*  556310 */   // GIR_Coverage, 12890,
     /*  556310 */   GIR_EraseRootFromParent_Done,
     /*  556311 */ // Label 8510: @556311
     /*  556311 */ GIM_Try, /*On fail goto*//*Label 8511*/ GIMT_Encode4(556378), // Rule ID 12891 //
     /*  556316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  556319 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  556322 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  556329 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556336 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556340 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556347 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556355 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556357 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556362 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556367 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556372 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556376 */   GIR_RootConstrainSelectedInstOperands,
     /*  556377 */   // GIR_Coverage, 12891,
     /*  556377 */   GIR_EraseRootFromParent_Done,
     /*  556378 */ // Label 8511: @556378
     /*  556378 */ GIM_Try, /*On fail goto*//*Label 8512*/ GIMT_Encode4(556438), // Rule ID 12463 //
     /*  556383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  556386 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556389 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556396 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556400 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556407 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556410 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556415 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556436 */   GIR_RootConstrainSelectedInstOperands,
     /*  556437 */   // GIR_Coverage, 12463,
     /*  556437 */   GIR_EraseRootFromParent_Done,
     /*  556438 */ // Label 8512: @556438
     /*  556438 */ GIM_Try, /*On fail goto*//*Label 8513*/ GIMT_Encode4(556498), // Rule ID 12464 //
     /*  556443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  556446 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556449 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556456 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556460 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556467 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556475 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556482 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556487 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556492 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556496 */   GIR_RootConstrainSelectedInstOperands,
     /*  556497 */   // GIR_Coverage, 12464,
     /*  556497 */   GIR_EraseRootFromParent_Done,
     /*  556498 */ // Label 8513: @556498
     /*  556498 */ GIM_Try, /*On fail goto*//*Label 8514*/ GIMT_Encode4(556558), // Rule ID 12465 //
     /*  556503 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  556506 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556509 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556516 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556520 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556527 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556527 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556535 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556537 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556542 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556547 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556552 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556556 */   GIR_RootConstrainSelectedInstOperands,
     /*  556557 */   // GIR_Coverage, 12465,
     /*  556557 */   GIR_EraseRootFromParent_Done,
     /*  556558 */ // Label 8514: @556558
     /*  556558 */ GIM_Try, /*On fail goto*//*Label 8515*/ GIMT_Encode4(556618), // Rule ID 12466 //
     /*  556563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  556566 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556569 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556576 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556580 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556587 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556590 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556595 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556597 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556602 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556607 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556612 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556616 */   GIR_RootConstrainSelectedInstOperands,
     /*  556617 */   // GIR_Coverage, 12466,
     /*  556617 */   GIR_EraseRootFromParent_Done,
     /*  556618 */ // Label 8515: @556618
     /*  556618 */ GIM_Try, /*On fail goto*//*Label 8516*/ GIMT_Encode4(556678), // Rule ID 12467 //
     /*  556623 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  556626 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556629 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556636 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556640 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556647 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556647 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556650 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556655 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556657 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556662 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556667 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556672 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556676 */   GIR_RootConstrainSelectedInstOperands,
     /*  556677 */   // GIR_Coverage, 12467,
     /*  556677 */   GIR_EraseRootFromParent_Done,
     /*  556678 */ // Label 8516: @556678
     /*  556678 */ GIM_Try, /*On fail goto*//*Label 8517*/ GIMT_Encode4(556738), // Rule ID 12483 //
     /*  556683 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  556686 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556689 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556696 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556700 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556707 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556707 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556710 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556715 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556736 */   GIR_RootConstrainSelectedInstOperands,
     /*  556737 */   // GIR_Coverage, 12483,
     /*  556737 */   GIR_EraseRootFromParent_Done,
     /*  556738 */ // Label 8517: @556738
     /*  556738 */ GIM_Try, /*On fail goto*//*Label 8518*/ GIMT_Encode4(556798), // Rule ID 12484 //
     /*  556743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  556746 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556749 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556767 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556767 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556770 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556775 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556792 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556796 */   GIR_RootConstrainSelectedInstOperands,
     /*  556797 */   // GIR_Coverage, 12484,
     /*  556797 */   GIR_EraseRootFromParent_Done,
     /*  556798 */ // Label 8518: @556798
     /*  556798 */ GIM_Try, /*On fail goto*//*Label 8519*/ GIMT_Encode4(556858), // Rule ID 12485 //
     /*  556803 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  556806 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556809 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556816 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556820 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556827 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556827 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556835 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556847 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556852 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556856 */   GIR_RootConstrainSelectedInstOperands,
     /*  556857 */   // GIR_Coverage, 12485,
     /*  556857 */   GIR_EraseRootFromParent_Done,
     /*  556858 */ // Label 8519: @556858
     /*  556858 */ GIM_Try, /*On fail goto*//*Label 8520*/ GIMT_Encode4(556918), // Rule ID 12486 //
     /*  556863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  556866 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556869 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556876 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556880 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556887 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556895 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556902 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556907 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556912 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556916 */   GIR_RootConstrainSelectedInstOperands,
     /*  556917 */   // GIR_Coverage, 12486,
     /*  556917 */   GIR_EraseRootFromParent_Done,
     /*  556918 */ // Label 8520: @556918
     /*  556918 */ GIM_Try, /*On fail goto*//*Label 8521*/ GIMT_Encode4(556978), // Rule ID 12487 //
     /*  556923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  556926 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  556929 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  556936 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  556940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  556947 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  556947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  556950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  556955 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  556957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  556962 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  556967 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  556972 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  556976 */   GIR_RootConstrainSelectedInstOperands,
     /*  556977 */   // GIR_Coverage, 12487,
     /*  556977 */   GIR_EraseRootFromParent_Done,
     /*  556978 */ // Label 8521: @556978
     /*  556978 */ GIM_Try, /*On fail goto*//*Label 8522*/ GIMT_Encode4(557038), // Rule ID 12882 //
     /*  556983 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  556986 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  556989 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  556996 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557003 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557007 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557014 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557014 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557022 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557024 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557029 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557032 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557036 */   GIR_RootConstrainSelectedInstOperands,
     /*  557037 */   // GIR_Coverage, 12882,
     /*  557037 */   GIR_EraseRootFromParent_Done,
     /*  557038 */ // Label 8522: @557038
     /*  557038 */ GIM_Try, /*On fail goto*//*Label 8523*/ GIMT_Encode4(557098), // Rule ID 12883 //
     /*  557043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  557046 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557049 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557056 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557063 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557067 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557074 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557074 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557077 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557082 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557089 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557092 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557096 */   GIR_RootConstrainSelectedInstOperands,
     /*  557097 */   // GIR_Coverage, 12883,
     /*  557097 */   GIR_EraseRootFromParent_Done,
     /*  557098 */ // Label 8523: @557098
     /*  557098 */ GIM_Try, /*On fail goto*//*Label 8524*/ GIMT_Encode4(557158), // Rule ID 12884 //
     /*  557103 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  557106 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557109 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557116 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557123 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557127 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557134 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557134 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557137 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557142 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557144 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557149 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557152 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557156 */   GIR_RootConstrainSelectedInstOperands,
     /*  557157 */   // GIR_Coverage, 12884,
     /*  557157 */   GIR_EraseRootFromParent_Done,
     /*  557158 */ // Label 8524: @557158
     /*  557158 */ GIM_Try, /*On fail goto*//*Label 8525*/ GIMT_Encode4(557218), // Rule ID 12885 //
     /*  557163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  557166 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557169 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557176 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557183 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557187 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557194 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557197 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557202 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557209 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557212 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557216 */   GIR_RootConstrainSelectedInstOperands,
     /*  557217 */   // GIR_Coverage, 12885,
     /*  557217 */   GIR_EraseRootFromParent_Done,
     /*  557218 */ // Label 8525: @557218
     /*  557218 */ GIM_Try, /*On fail goto*//*Label 8526*/ GIMT_Encode4(557278), // Rule ID 12886 //
     /*  557223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  557226 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557229 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557236 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557243 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557247 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557254 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557257 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557262 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557264 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557272 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557276 */   GIR_RootConstrainSelectedInstOperands,
     /*  557277 */   // GIR_Coverage, 12886,
     /*  557277 */   GIR_EraseRootFromParent_Done,
     /*  557278 */ // Label 8526: @557278
     /*  557278 */ GIM_Try, /*On fail goto*//*Label 8527*/ GIMT_Encode4(557331), // Rule ID 12458 //
     /*  557283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  557286 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557289 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557296 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557300 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557307 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557310 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557315 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557322 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557325 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557329 */   GIR_RootConstrainSelectedInstOperands,
     /*  557330 */   // GIR_Coverage, 12458,
     /*  557330 */   GIR_EraseRootFromParent_Done,
     /*  557331 */ // Label 8527: @557331
     /*  557331 */ GIM_Try, /*On fail goto*//*Label 8528*/ GIMT_Encode4(557384), // Rule ID 12459 //
     /*  557336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  557339 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557342 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557349 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557353 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557360 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557368 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557370 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557375 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557378 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557382 */   GIR_RootConstrainSelectedInstOperands,
     /*  557383 */   // GIR_Coverage, 12459,
     /*  557383 */   GIR_EraseRootFromParent_Done,
     /*  557384 */ // Label 8528: @557384
     /*  557384 */ GIM_Try, /*On fail goto*//*Label 8529*/ GIMT_Encode4(557437), // Rule ID 12460 //
     /*  557389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  557392 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557395 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557402 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557406 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557413 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557416 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557421 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557428 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557431 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557435 */   GIR_RootConstrainSelectedInstOperands,
     /*  557436 */   // GIR_Coverage, 12460,
     /*  557436 */   GIR_EraseRootFromParent_Done,
     /*  557437 */ // Label 8529: @557437
     /*  557437 */ GIM_Try, /*On fail goto*//*Label 8530*/ GIMT_Encode4(557490), // Rule ID 12461 //
     /*  557442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  557445 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557448 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557455 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557459 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557466 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557466 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557469 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557474 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557481 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557484 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557488 */   GIR_RootConstrainSelectedInstOperands,
     /*  557489 */   // GIR_Coverage, 12461,
     /*  557489 */   GIR_EraseRootFromParent_Done,
     /*  557490 */ // Label 8530: @557490
     /*  557490 */ GIM_Try, /*On fail goto*//*Label 8531*/ GIMT_Encode4(557543), // Rule ID 12462 //
     /*  557495 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  557498 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557501 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557519 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557527 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557534 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557541 */   GIR_RootConstrainSelectedInstOperands,
     /*  557542 */   // GIR_Coverage, 12462,
     /*  557542 */   GIR_EraseRootFromParent_Done,
     /*  557543 */ // Label 8531: @557543
     /*  557543 */ GIM_Try, /*On fail goto*//*Label 8532*/ GIMT_Encode4(557596), // Rule ID 12478 //
     /*  557548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  557551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557554 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557561 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557565 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557572 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557575 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557580 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557587 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557590 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557594 */   GIR_RootConstrainSelectedInstOperands,
     /*  557595 */   // GIR_Coverage, 12478,
     /*  557595 */   GIR_EraseRootFromParent_Done,
     /*  557596 */ // Label 8532: @557596
     /*  557596 */ GIM_Try, /*On fail goto*//*Label 8533*/ GIMT_Encode4(557649), // Rule ID 12479 //
     /*  557601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  557604 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557607 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557614 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557618 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557625 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557628 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557633 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557640 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557643 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557647 */   GIR_RootConstrainSelectedInstOperands,
     /*  557648 */   // GIR_Coverage, 12479,
     /*  557648 */   GIR_EraseRootFromParent_Done,
     /*  557649 */ // Label 8533: @557649
     /*  557649 */ GIM_Try, /*On fail goto*//*Label 8534*/ GIMT_Encode4(557702), // Rule ID 12480 //
     /*  557654 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  557657 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557660 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557667 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557671 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557678 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557678 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557686 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557688 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557693 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557696 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557700 */   GIR_RootConstrainSelectedInstOperands,
     /*  557701 */   // GIR_Coverage, 12480,
     /*  557701 */   GIR_EraseRootFromParent_Done,
     /*  557702 */ // Label 8534: @557702
     /*  557702 */ GIM_Try, /*On fail goto*//*Label 8535*/ GIMT_Encode4(557755), // Rule ID 12481 //
     /*  557707 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  557710 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557713 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557720 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557724 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557731 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557731 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557734 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557739 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557741 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557746 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557749 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557753 */   GIR_RootConstrainSelectedInstOperands,
     /*  557754 */   // GIR_Coverage, 12481,
     /*  557754 */   GIR_EraseRootFromParent_Done,
     /*  557755 */ // Label 8535: @557755
     /*  557755 */ GIM_Try, /*On fail goto*//*Label 8536*/ GIMT_Encode4(557808), // Rule ID 12482 //
     /*  557760 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  557763 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  557766 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  557773 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557777 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  557784 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  557784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  557787 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  557792 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557794 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  557799 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  557802 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557806 */   GIR_RootConstrainSelectedInstOperands,
     /*  557807 */   // GIR_Coverage, 12482,
     /*  557807 */   GIR_EraseRootFromParent_Done,
     /*  557808 */ // Label 8536: @557808
     /*  557808 */ GIM_Try, /*On fail goto*//*Label 8537*/ GIMT_Encode4(557874), // Rule ID 10461 //
     /*  557813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  557816 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557819 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557826 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  557832 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557836 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  557843 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  557843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  557846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  557851 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  557858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  557863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  557868 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557872 */   GIR_RootConstrainSelectedInstOperands,
     /*  557873 */   // GIR_Coverage, 10461,
     /*  557873 */   GIR_EraseRootFromParent_Done,
     /*  557874 */ // Label 8537: @557874
     /*  557874 */ GIM_Try, /*On fail goto*//*Label 8538*/ GIMT_Encode4(557940), // Rule ID 10462 //
     /*  557879 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  557882 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557885 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557892 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  557898 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557902 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  557909 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  557909 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  557912 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  557917 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  557924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  557929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  557934 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  557938 */   GIR_RootConstrainSelectedInstOperands,
     /*  557939 */   // GIR_Coverage, 10462,
     /*  557939 */   GIR_EraseRootFromParent_Done,
     /*  557940 */ // Label 8538: @557940
     /*  557940 */ GIM_Try, /*On fail goto*//*Label 8539*/ GIMT_Encode4(558006), // Rule ID 10463 //
     /*  557945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  557948 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  557951 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  557958 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  557964 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  557968 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  557975 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  557975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  557978 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  557983 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  557985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  557990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  557995 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558000 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558004 */   GIR_RootConstrainSelectedInstOperands,
     /*  558005 */   // GIR_Coverage, 10463,
     /*  558005 */   GIR_EraseRootFromParent_Done,
     /*  558006 */ // Label 8539: @558006
     /*  558006 */ GIM_Try, /*On fail goto*//*Label 8540*/ GIMT_Encode4(558072), // Rule ID 10464 //
     /*  558011 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  558014 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558017 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558024 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558030 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558034 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558041 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558041 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558049 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558066 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558070 */   GIR_RootConstrainSelectedInstOperands,
     /*  558071 */   // GIR_Coverage, 10464,
     /*  558071 */   GIR_EraseRootFromParent_Done,
     /*  558072 */ // Label 8540: @558072
     /*  558072 */ GIM_Try, /*On fail goto*//*Label 8541*/ GIMT_Encode4(558138), // Rule ID 10465 //
     /*  558077 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  558080 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558083 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558090 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558096 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558100 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558107 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558115 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558117 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558122 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558127 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558132 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558136 */   GIR_RootConstrainSelectedInstOperands,
     /*  558137 */   // GIR_Coverage, 10465,
     /*  558137 */   GIR_EraseRootFromParent_Done,
     /*  558138 */ // Label 8541: @558138
     /*  558138 */ GIM_Try, /*On fail goto*//*Label 8542*/ GIMT_Encode4(558197), // Rule ID 10321 //
     /*  558143 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  558146 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558149 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558155 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558159 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558166 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558166 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558174 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558191 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558195 */   GIR_RootConstrainSelectedInstOperands,
     /*  558196 */   // GIR_Coverage, 10321,
     /*  558196 */   GIR_EraseRootFromParent_Done,
     /*  558197 */ // Label 8542: @558197
     /*  558197 */ GIM_Try, /*On fail goto*//*Label 8543*/ GIMT_Encode4(558256), // Rule ID 10322 //
     /*  558202 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  558205 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558208 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558214 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558218 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558225 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558225 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558233 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558235 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558240 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558245 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558250 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558254 */   GIR_RootConstrainSelectedInstOperands,
     /*  558255 */   // GIR_Coverage, 10322,
     /*  558255 */   GIR_EraseRootFromParent_Done,
     /*  558256 */ // Label 8543: @558256
     /*  558256 */ GIM_Try, /*On fail goto*//*Label 8544*/ GIMT_Encode4(558315), // Rule ID 10323 //
     /*  558261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  558264 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558267 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558273 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558277 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558284 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558292 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558294 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558299 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558304 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558309 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558313 */   GIR_RootConstrainSelectedInstOperands,
     /*  558314 */   // GIR_Coverage, 10323,
     /*  558314 */   GIR_EraseRootFromParent_Done,
     /*  558315 */ // Label 8544: @558315
     /*  558315 */ GIM_Try, /*On fail goto*//*Label 8545*/ GIMT_Encode4(558374), // Rule ID 10324 //
     /*  558320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  558323 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558326 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558332 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558336 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558343 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558351 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558353 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558358 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558363 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558368 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558372 */   GIR_RootConstrainSelectedInstOperands,
     /*  558373 */   // GIR_Coverage, 10324,
     /*  558373 */   GIR_EraseRootFromParent_Done,
     /*  558374 */ // Label 8545: @558374
     /*  558374 */ GIM_Try, /*On fail goto*//*Label 8546*/ GIMT_Encode4(558433), // Rule ID 10325 //
     /*  558379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  558382 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558385 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558391 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558395 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558402 */   // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558405 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558410 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558427 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558431 */   GIR_RootConstrainSelectedInstOperands,
     /*  558432 */   // GIR_Coverage, 10325,
     /*  558432 */   GIR_EraseRootFromParent_Done,
     /*  558433 */ // Label 8546: @558433
     /*  558433 */ GIM_Try, /*On fail goto*//*Label 8547*/ GIMT_Encode4(558492), // Rule ID 10341 //
     /*  558438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  558441 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558444 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558450 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558454 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558461 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558464 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558469 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558476 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558486 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558490 */   GIR_RootConstrainSelectedInstOperands,
     /*  558491 */   // GIR_Coverage, 10341,
     /*  558491 */   GIR_EraseRootFromParent_Done,
     /*  558492 */ // Label 8547: @558492
     /*  558492 */ GIM_Try, /*On fail goto*//*Label 8548*/ GIMT_Encode4(558551), // Rule ID 10342 //
     /*  558497 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  558500 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558503 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558509 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558513 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558520 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558523 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558528 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558549 */   GIR_RootConstrainSelectedInstOperands,
     /*  558550 */   // GIR_Coverage, 10342,
     /*  558550 */   GIR_EraseRootFromParent_Done,
     /*  558551 */ // Label 8548: @558551
     /*  558551 */ GIM_Try, /*On fail goto*//*Label 8549*/ GIMT_Encode4(558610), // Rule ID 10343 //
     /*  558556 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  558559 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558562 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558568 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558572 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558579 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558587 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558599 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558604 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558608 */   GIR_RootConstrainSelectedInstOperands,
     /*  558609 */   // GIR_Coverage, 10343,
     /*  558609 */   GIR_EraseRootFromParent_Done,
     /*  558610 */ // Label 8549: @558610
     /*  558610 */ GIM_Try, /*On fail goto*//*Label 8550*/ GIMT_Encode4(558669), // Rule ID 10344 //
     /*  558615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  558618 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558621 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558627 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558631 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558638 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558638 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558646 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558653 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558658 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558663 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558667 */   GIR_RootConstrainSelectedInstOperands,
     /*  558668 */   // GIR_Coverage, 10344,
     /*  558668 */   GIR_EraseRootFromParent_Done,
     /*  558669 */ // Label 8550: @558669
     /*  558669 */ GIM_Try, /*On fail goto*//*Label 8551*/ GIMT_Encode4(558728), // Rule ID 10345 //
     /*  558674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  558677 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  558680 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558686 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  558697 */   // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  558697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  558700 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  558705 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558707 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  558712 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  558717 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  558722 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558726 */   GIR_RootConstrainSelectedInstOperands,
     /*  558727 */   // GIR_Coverage, 10345,
     /*  558727 */   GIR_EraseRootFromParent_Done,
     /*  558728 */ // Label 8551: @558728
     /*  558728 */ GIM_Try, /*On fail goto*//*Label 8552*/ GIMT_Encode4(558787), // Rule ID 10456 //
     /*  558733 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  558736 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558739 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558746 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558752 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558756 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  558763 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  558763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  558766 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  558771 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  558778 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  558781 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558785 */   GIR_RootConstrainSelectedInstOperands,
     /*  558786 */   // GIR_Coverage, 10456,
     /*  558786 */   GIR_EraseRootFromParent_Done,
     /*  558787 */ // Label 8552: @558787
     /*  558787 */ GIM_Try, /*On fail goto*//*Label 8553*/ GIMT_Encode4(558846), // Rule ID 10457 //
     /*  558792 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  558795 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558798 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558805 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558811 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558815 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  558822 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  558822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  558825 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  558830 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  558837 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  558840 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558844 */   GIR_RootConstrainSelectedInstOperands,
     /*  558845 */   // GIR_Coverage, 10457,
     /*  558845 */   GIR_EraseRootFromParent_Done,
     /*  558846 */ // Label 8553: @558846
     /*  558846 */ GIM_Try, /*On fail goto*//*Label 8554*/ GIMT_Encode4(558905), // Rule ID 10458 //
     /*  558851 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  558854 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558857 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558864 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  558881 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  558881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  558884 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  558889 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  558896 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  558899 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558903 */   GIR_RootConstrainSelectedInstOperands,
     /*  558904 */   // GIR_Coverage, 10458,
     /*  558904 */   GIR_EraseRootFromParent_Done,
     /*  558905 */ // Label 8554: @558905
     /*  558905 */ GIM_Try, /*On fail goto*//*Label 8555*/ GIMT_Encode4(558964), // Rule ID 10459 //
     /*  558910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  558913 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558916 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558923 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558929 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558933 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  558940 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  558940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  558943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  558948 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  558950 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  558955 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  558958 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  558962 */   GIR_RootConstrainSelectedInstOperands,
     /*  558963 */   // GIR_Coverage, 10459,
     /*  558963 */   GIR_EraseRootFromParent_Done,
     /*  558964 */ // Label 8555: @558964
     /*  558964 */ GIM_Try, /*On fail goto*//*Label 8556*/ GIMT_Encode4(559023), // Rule ID 10460 //
     /*  558969 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  558972 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /*  558975 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(16),
     /*  558982 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  558988 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  558992 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  558999 */   // (atomic_store v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_128>><<P:Predicate_atomic_store_128_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  558999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559002 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559007 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559009 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559014 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559017 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559021 */   GIR_RootConstrainSelectedInstOperands,
     /*  559022 */   // GIR_Coverage, 10460,
     /*  559022 */   GIR_EraseRootFromParent_Done,
     /*  559023 */ // Label 8556: @559023
     /*  559023 */ GIM_Try, /*On fail goto*//*Label 8557*/ GIMT_Encode4(559075), // Rule ID 10316 //
     /*  559028 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  559031 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559034 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559040 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559044 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559051 */   // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559059 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559061 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559066 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559069 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559073 */   GIR_RootConstrainSelectedInstOperands,
     /*  559074 */   // GIR_Coverage, 10316,
     /*  559074 */   GIR_EraseRootFromParent_Done,
     /*  559075 */ // Label 8557: @559075
     /*  559075 */ GIM_Try, /*On fail goto*//*Label 8558*/ GIMT_Encode4(559127), // Rule ID 10317 //
     /*  559080 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  559083 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559086 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559092 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559096 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559103 */   // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559111 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559113 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559118 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559121 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559125 */   GIR_RootConstrainSelectedInstOperands,
     /*  559126 */   // GIR_Coverage, 10317,
     /*  559126 */   GIR_EraseRootFromParent_Done,
     /*  559127 */ // Label 8558: @559127
     /*  559127 */ GIM_Try, /*On fail goto*//*Label 8559*/ GIMT_Encode4(559179), // Rule ID 10318 //
     /*  559132 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  559135 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559138 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559148 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559155 */   // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559158 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559163 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559165 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559170 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559173 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559177 */   GIR_RootConstrainSelectedInstOperands,
     /*  559178 */   // GIR_Coverage, 10318,
     /*  559178 */   GIR_EraseRootFromParent_Done,
     /*  559179 */ // Label 8559: @559179
     /*  559179 */ GIM_Try, /*On fail goto*//*Label 8560*/ GIMT_Encode4(559231), // Rule ID 10319 //
     /*  559184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  559187 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559190 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559196 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559200 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559207 */   // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559207 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559210 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559215 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559217 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559222 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559225 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559229 */   GIR_RootConstrainSelectedInstOperands,
     /*  559230 */   // GIR_Coverage, 10319,
     /*  559230 */   GIR_EraseRootFromParent_Done,
     /*  559231 */ // Label 8560: @559231
     /*  559231 */ GIM_Try, /*On fail goto*//*Label 8561*/ GIMT_Encode4(559283), // Rule ID 10320 //
     /*  559236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  559239 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559242 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559248 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559252 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559259 */   // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559259 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559262 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559267 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559269 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559274 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559277 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559281 */   GIR_RootConstrainSelectedInstOperands,
     /*  559282 */   // GIR_Coverage, 10320,
     /*  559282 */   GIR_EraseRootFromParent_Done,
     /*  559283 */ // Label 8561: @559283
     /*  559283 */ GIM_Try, /*On fail goto*//*Label 8562*/ GIMT_Encode4(559335), // Rule ID 10336 //
     /*  559288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  559291 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559294 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559300 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559304 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559311 */   // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559314 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559319 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559321 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559329 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559333 */   GIR_RootConstrainSelectedInstOperands,
     /*  559334 */   // GIR_Coverage, 10336,
     /*  559334 */   GIR_EraseRootFromParent_Done,
     /*  559335 */ // Label 8562: @559335
     /*  559335 */ GIM_Try, /*On fail goto*//*Label 8563*/ GIMT_Encode4(559387), // Rule ID 10337 //
     /*  559340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  559343 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559346 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559352 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559356 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559363 */   // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559363 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559366 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559371 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559378 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559381 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559385 */   GIR_RootConstrainSelectedInstOperands,
     /*  559386 */   // GIR_Coverage, 10337,
     /*  559386 */   GIR_EraseRootFromParent_Done,
     /*  559387 */ // Label 8563: @559387
     /*  559387 */ GIM_Try, /*On fail goto*//*Label 8564*/ GIMT_Encode4(559439), // Rule ID 10338 //
     /*  559392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  559395 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559398 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559404 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559408 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559415 */   // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559415 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559423 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559425 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559430 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559433 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559437 */   GIR_RootConstrainSelectedInstOperands,
     /*  559438 */   // GIR_Coverage, 10338,
     /*  559438 */   GIR_EraseRootFromParent_Done,
     /*  559439 */ // Label 8564: @559439
     /*  559439 */ GIM_Try, /*On fail goto*//*Label 8565*/ GIMT_Encode4(559491), // Rule ID 10339 //
     /*  559444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  559447 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559450 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559456 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559460 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559467 */   // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559475 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559477 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559482 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559485 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559489 */   GIR_RootConstrainSelectedInstOperands,
     /*  559490 */   // GIR_Coverage, 10339,
     /*  559490 */   GIR_EraseRootFromParent_Done,
     /*  559491 */ // Label 8565: @559491
     /*  559491 */ GIM_Try, /*On fail goto*//*Label 8566*/ GIMT_Encode4(559543), // Rule ID 10340 //
     /*  559496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  559499 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559502 */   GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  559508 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559512 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  559519 */   // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  559519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  559522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  559527 */   GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  559529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559534 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559537 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559541 */   GIR_RootConstrainSelectedInstOperands,
     /*  559542 */   // GIR_Coverage, 10340,
     /*  559542 */   GIR_EraseRootFromParent_Done,
     /*  559543 */ // Label 8566: @559543
     /*  559543 */ GIM_Reject,
     /*  559544 */ // Label 5874: @559544
     /*  559544 */ GIM_Try, /*On fail goto*//*Label 8567*/ GIMT_Encode4(570163),
     /*  559549 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /*  559552 */   GIM_Try, /*On fail goto*//*Label 8568*/ GIMT_Encode4(559608), // Rule ID 29913 //
     /*  559557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  559560 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559564 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559569 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559584 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559592 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559606 */     GIR_RootConstrainSelectedInstOperands,
     /*  559607 */     // GIR_Coverage, 29913,
     /*  559607 */     GIR_EraseRootFromParent_Done,
     /*  559608 */   // Label 8568: @559608
     /*  559608 */   GIM_Try, /*On fail goto*//*Label 8569*/ GIMT_Encode4(559664), // Rule ID 29914 //
     /*  559613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  559616 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559625 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559640 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559648 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559662 */     GIR_RootConstrainSelectedInstOperands,
     /*  559663 */     // GIR_Coverage, 29914,
     /*  559663 */     GIR_EraseRootFromParent_Done,
     /*  559664 */   // Label 8569: @559664
     /*  559664 */   GIM_Try, /*On fail goto*//*Label 8570*/ GIMT_Encode4(559720), // Rule ID 29915 //
     /*  559669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  559672 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559676 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559681 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559696 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559704 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559718 */     GIR_RootConstrainSelectedInstOperands,
     /*  559719 */     // GIR_Coverage, 29915,
     /*  559719 */     GIR_EraseRootFromParent_Done,
     /*  559720 */   // Label 8570: @559720
     /*  559720 */   GIM_Try, /*On fail goto*//*Label 8571*/ GIMT_Encode4(559776), // Rule ID 29916 //
     /*  559725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  559728 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559737 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559752 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559760 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559774 */     GIR_RootConstrainSelectedInstOperands,
     /*  559775 */     // GIR_Coverage, 29916,
     /*  559775 */     GIR_EraseRootFromParent_Done,
     /*  559776 */   // Label 8571: @559776
     /*  559776 */   GIM_Try, /*On fail goto*//*Label 8572*/ GIMT_Encode4(559832), // Rule ID 29917 //
     /*  559781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  559784 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559788 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559793 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559797 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559808 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559816 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559830 */     GIR_RootConstrainSelectedInstOperands,
     /*  559831 */     // GIR_Coverage, 29917,
     /*  559831 */     GIR_EraseRootFromParent_Done,
     /*  559832 */   // Label 8572: @559832
     /*  559832 */   GIM_Try, /*On fail goto*//*Label 8573*/ GIMT_Encode4(559888), // Rule ID 29933 //
     /*  559837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  559840 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559849 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559864 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559872 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559886 */     GIR_RootConstrainSelectedInstOperands,
     /*  559887 */     // GIR_Coverage, 29933,
     /*  559887 */     GIR_EraseRootFromParent_Done,
     /*  559888 */   // Label 8573: @559888
     /*  559888 */   GIM_Try, /*On fail goto*//*Label 8574*/ GIMT_Encode4(559944), // Rule ID 29934 //
     /*  559893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  559896 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559900 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559905 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559909 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559920 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559928 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559942 */     GIR_RootConstrainSelectedInstOperands,
     /*  559943 */     // GIR_Coverage, 29934,
     /*  559943 */     GIR_EraseRootFromParent_Done,
     /*  559944 */   // Label 8574: @559944
     /*  559944 */   GIM_Try, /*On fail goto*//*Label 8575*/ GIMT_Encode4(560000), // Rule ID 29935 //
     /*  559949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  559952 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  559956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  559961 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  559965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  559969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  559976 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  559976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  559979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  559984 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  559986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  559991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  559994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  559998 */     GIR_RootConstrainSelectedInstOperands,
     /*  559999 */     // GIR_Coverage, 29935,
     /*  559999 */     GIR_EraseRootFromParent_Done,
     /*  560000 */   // Label 8575: @560000
     /*  560000 */   GIM_Try, /*On fail goto*//*Label 8576*/ GIMT_Encode4(560056), // Rule ID 29936 //
     /*  560005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  560008 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560017 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560021 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560025 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560032 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560040 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560047 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560050 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560054 */     GIR_RootConstrainSelectedInstOperands,
     /*  560055 */     // GIR_Coverage, 29936,
     /*  560055 */     GIR_EraseRootFromParent_Done,
     /*  560056 */   // Label 8576: @560056
     /*  560056 */   GIM_Try, /*On fail goto*//*Label 8577*/ GIMT_Encode4(560112), // Rule ID 29937 //
     /*  560061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  560064 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560073 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560088 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560096 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560110 */     GIR_RootConstrainSelectedInstOperands,
     /*  560111 */     // GIR_Coverage, 29937,
     /*  560111 */     GIR_EraseRootFromParent_Done,
     /*  560112 */   // Label 8577: @560112
     /*  560112 */   GIM_Try, /*On fail goto*//*Label 8578*/ GIMT_Encode4(560173), // Rule ID 30253 //
     /*  560117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  560120 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560129 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560138 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560149 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560157 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560171 */     GIR_RootConstrainSelectedInstOperands,
     /*  560172 */     // GIR_Coverage, 30253,
     /*  560172 */     GIR_EraseRootFromParent_Done,
     /*  560173 */   // Label 8578: @560173
     /*  560173 */   GIM_Try, /*On fail goto*//*Label 8579*/ GIMT_Encode4(560234), // Rule ID 30254 //
     /*  560178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  560181 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560185 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560190 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560199 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560210 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560218 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560232 */     GIR_RootConstrainSelectedInstOperands,
     /*  560233 */     // GIR_Coverage, 30254,
     /*  560233 */     GIR_EraseRootFromParent_Done,
     /*  560234 */   // Label 8579: @560234
     /*  560234 */   GIM_Try, /*On fail goto*//*Label 8580*/ GIMT_Encode4(560295), // Rule ID 30255 //
     /*  560239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  560242 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560246 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560251 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560260 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560271 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560279 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560293 */     GIR_RootConstrainSelectedInstOperands,
     /*  560294 */     // GIR_Coverage, 30255,
     /*  560294 */     GIR_EraseRootFromParent_Done,
     /*  560295 */   // Label 8580: @560295
     /*  560295 */   GIM_Try, /*On fail goto*//*Label 8581*/ GIMT_Encode4(560356), // Rule ID 30256 //
     /*  560300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  560303 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560321 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560332 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560340 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560354 */     GIR_RootConstrainSelectedInstOperands,
     /*  560355 */     // GIR_Coverage, 30256,
     /*  560355 */     GIR_EraseRootFromParent_Done,
     /*  560356 */   // Label 8581: @560356
     /*  560356 */   GIM_Try, /*On fail goto*//*Label 8582*/ GIMT_Encode4(560417), // Rule ID 30257 //
     /*  560361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  560364 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560382 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560393 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560401 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560415 */     GIR_RootConstrainSelectedInstOperands,
     /*  560416 */     // GIR_Coverage, 30257,
     /*  560416 */     GIR_EraseRootFromParent_Done,
     /*  560417 */   // Label 8582: @560417
     /*  560417 */   GIM_Try, /*On fail goto*//*Label 8583*/ GIMT_Encode4(560478), // Rule ID 30273 //
     /*  560422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode0),
     /*  560425 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560429 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560434 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560443 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560447 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560454 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560462 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560476 */     GIR_RootConstrainSelectedInstOperands,
     /*  560477 */     // GIR_Coverage, 30273,
     /*  560477 */     GIR_EraseRootFromParent_Done,
     /*  560478 */   // Label 8583: @560478
     /*  560478 */   GIM_Try, /*On fail goto*//*Label 8584*/ GIMT_Encode4(560539), // Rule ID 30274 //
     /*  560483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode1),
     /*  560486 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560490 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560495 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560500 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560504 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560515 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560523 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560537 */     GIR_RootConstrainSelectedInstOperands,
     /*  560538 */     // GIR_Coverage, 30274,
     /*  560538 */     GIR_EraseRootFromParent_Done,
     /*  560539 */   // Label 8584: @560539
     /*  560539 */   GIM_Try, /*On fail goto*//*Label 8585*/ GIMT_Encode4(560600), // Rule ID 30275 //
     /*  560544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode2),
     /*  560547 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560551 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560565 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560576 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560584 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560598 */     GIR_RootConstrainSelectedInstOperands,
     /*  560599 */     // GIR_Coverage, 30275,
     /*  560599 */     GIR_EraseRootFromParent_Done,
     /*  560600 */   // Label 8585: @560600
     /*  560600 */   GIM_Try, /*On fail goto*//*Label 8586*/ GIMT_Encode4(560661), // Rule ID 30276 //
     /*  560605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode3),
     /*  560608 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560617 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560626 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560637 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560645 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560659 */     GIR_RootConstrainSelectedInstOperands,
     /*  560660 */     // GIR_Coverage, 30276,
     /*  560660 */     GIR_EraseRootFromParent_Done,
     /*  560661 */   // Label 8586: @560661
     /*  560661 */   GIM_Try, /*On fail goto*//*Label 8587*/ GIMT_Encode4(560722), // Rule ID 30277 //
     /*  560666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init_HwMode4),
     /*  560669 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  560673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560678 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560687 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
     /*  560691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560698 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
     /*  560701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560706 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560716 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560720 */     GIR_RootConstrainSelectedInstOperands,
     /*  560721 */     // GIR_Coverage, 30277,
     /*  560721 */     GIR_EraseRootFromParent_Done,
     /*  560722 */   // Label 8587: @560722
     /*  560722 */   GIM_Try, /*On fail goto*//*Label 8588*/ GIMT_Encode4(560774), // Rule ID 29918 //
     /*  560727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  560730 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560735 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560739 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560743 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560750 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  560753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560758 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560772 */     GIR_RootConstrainSelectedInstOperands,
     /*  560773 */     // GIR_Coverage, 29918,
     /*  560773 */     GIR_EraseRootFromParent_Done,
     /*  560774 */   // Label 8588: @560774
     /*  560774 */   GIM_Try, /*On fail goto*//*Label 8589*/ GIMT_Encode4(560826), // Rule ID 29919 //
     /*  560779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  560782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560787 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560802 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  560805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560810 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560824 */     GIR_RootConstrainSelectedInstOperands,
     /*  560825 */     // GIR_Coverage, 29919,
     /*  560825 */     GIR_EraseRootFromParent_Done,
     /*  560826 */   // Label 8589: @560826
     /*  560826 */   GIM_Try, /*On fail goto*//*Label 8590*/ GIMT_Encode4(560878), // Rule ID 29920 //
     /*  560831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  560834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560839 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560854 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  560857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560862 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560876 */     GIR_RootConstrainSelectedInstOperands,
     /*  560877 */     // GIR_Coverage, 29920,
     /*  560877 */     GIR_EraseRootFromParent_Done,
     /*  560878 */   // Label 8590: @560878
     /*  560878 */   GIM_Try, /*On fail goto*//*Label 8591*/ GIMT_Encode4(560930), // Rule ID 29921 //
     /*  560883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  560886 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560891 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560899 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560906 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  560909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560914 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560924 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560928 */     GIR_RootConstrainSelectedInstOperands,
     /*  560929 */     // GIR_Coverage, 29921,
     /*  560929 */     GIR_EraseRootFromParent_Done,
     /*  560930 */   // Label 8591: @560930
     /*  560930 */   GIM_Try, /*On fail goto*//*Label 8592*/ GIMT_Encode4(560982), // Rule ID 29922 //
     /*  560935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  560938 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560943 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  560951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  560958 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  560958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  560961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  560966 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  560968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  560973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  560976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  560980 */     GIR_RootConstrainSelectedInstOperands,
     /*  560981 */     // GIR_Coverage, 29922,
     /*  560981 */     GIR_EraseRootFromParent_Done,
     /*  560982 */   // Label 8592: @560982
     /*  560982 */   GIM_Try, /*On fail goto*//*Label 8593*/ GIMT_Encode4(561034), // Rule ID 29938 //
     /*  560987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  560990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  560995 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  560999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561010 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561018 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561032 */     GIR_RootConstrainSelectedInstOperands,
     /*  561033 */     // GIR_Coverage, 29938,
     /*  561033 */     GIR_EraseRootFromParent_Done,
     /*  561034 */   // Label 8593: @561034
     /*  561034 */   GIM_Try, /*On fail goto*//*Label 8594*/ GIMT_Encode4(561086), // Rule ID 29939 //
     /*  561039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  561042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561047 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  561051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561062 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561070 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561084 */     GIR_RootConstrainSelectedInstOperands,
     /*  561085 */     // GIR_Coverage, 29939,
     /*  561085 */     GIR_EraseRootFromParent_Done,
     /*  561086 */   // Label 8594: @561086
     /*  561086 */   GIM_Try, /*On fail goto*//*Label 8595*/ GIMT_Encode4(561138), // Rule ID 29940 //
     /*  561091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  561094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561099 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  561103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561114 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561122 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561136 */     GIR_RootConstrainSelectedInstOperands,
     /*  561137 */     // GIR_Coverage, 29940,
     /*  561137 */     GIR_EraseRootFromParent_Done,
     /*  561138 */   // Label 8595: @561138
     /*  561138 */   GIM_Try, /*On fail goto*//*Label 8596*/ GIMT_Encode4(561190), // Rule ID 29941 //
     /*  561143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  561146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561151 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  561155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561166 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561174 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561188 */     GIR_RootConstrainSelectedInstOperands,
     /*  561189 */     // GIR_Coverage, 29941,
     /*  561189 */     GIR_EraseRootFromParent_Done,
     /*  561190 */   // Label 8596: @561190
     /*  561190 */   GIM_Try, /*On fail goto*//*Label 8597*/ GIMT_Encode4(561242), // Rule ID 29942 //
     /*  561195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  561198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561203 */     GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
     /*  561207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561218 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561226 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561240 */     GIR_RootConstrainSelectedInstOperands,
     /*  561241 */     // GIR_Coverage, 29942,
     /*  561241 */     GIR_EraseRootFromParent_Done,
     /*  561242 */   // Label 8597: @561242
     /*  561242 */   GIM_Try, /*On fail goto*//*Label 8598*/ GIMT_Encode4(561299), // Rule ID 30258 //
     /*  561247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  561250 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561255 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561264 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561275 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561283 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561293 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561297 */     GIR_RootConstrainSelectedInstOperands,
     /*  561298 */     // GIR_Coverage, 30258,
     /*  561298 */     GIR_EraseRootFromParent_Done,
     /*  561299 */   // Label 8598: @561299
     /*  561299 */   GIM_Try, /*On fail goto*//*Label 8599*/ GIMT_Encode4(561356), // Rule ID 30259 //
     /*  561304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  561307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561321 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561332 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561340 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561354 */     GIR_RootConstrainSelectedInstOperands,
     /*  561355 */     // GIR_Coverage, 30259,
     /*  561355 */     GIR_EraseRootFromParent_Done,
     /*  561356 */   // Label 8599: @561356
     /*  561356 */   GIM_Try, /*On fail goto*//*Label 8600*/ GIMT_Encode4(561413), // Rule ID 30260 //
     /*  561361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  561364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561369 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561378 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561389 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561397 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561407 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561411 */     GIR_RootConstrainSelectedInstOperands,
     /*  561412 */     // GIR_Coverage, 30260,
     /*  561412 */     GIR_EraseRootFromParent_Done,
     /*  561413 */   // Label 8600: @561413
     /*  561413 */   GIM_Try, /*On fail goto*//*Label 8601*/ GIMT_Encode4(561470), // Rule ID 30261 //
     /*  561418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  561421 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561435 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561446 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561454 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561461 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561464 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561468 */     GIR_RootConstrainSelectedInstOperands,
     /*  561469 */     // GIR_Coverage, 30261,
     /*  561469 */     GIR_EraseRootFromParent_Done,
     /*  561470 */   // Label 8601: @561470
     /*  561470 */   GIM_Try, /*On fail goto*//*Label 8602*/ GIMT_Encode4(561527), // Rule ID 30262 //
     /*  561475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  561478 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561492 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561503 */     // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561511 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561525 */     GIR_RootConstrainSelectedInstOperands,
     /*  561526 */     // GIR_Coverage, 30262,
     /*  561526 */     GIR_EraseRootFromParent_Done,
     /*  561527 */   // Label 8602: @561527
     /*  561527 */   GIM_Try, /*On fail goto*//*Label 8603*/ GIMT_Encode4(561584), // Rule ID 30278 //
     /*  561532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode0),
     /*  561535 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561549 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561560 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561568 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561582 */     GIR_RootConstrainSelectedInstOperands,
     /*  561583 */     // GIR_Coverage, 30278,
     /*  561583 */     GIR_EraseRootFromParent_Done,
     /*  561584 */   // Label 8603: @561584
     /*  561584 */   GIM_Try, /*On fail goto*//*Label 8604*/ GIMT_Encode4(561641), // Rule ID 30279 //
     /*  561589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode1),
     /*  561592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561597 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561606 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561617 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561625 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561639 */     GIR_RootConstrainSelectedInstOperands,
     /*  561640 */     // GIR_Coverage, 30279,
     /*  561640 */     GIR_EraseRootFromParent_Done,
     /*  561641 */   // Label 8604: @561641
     /*  561641 */   GIM_Try, /*On fail goto*//*Label 8605*/ GIMT_Encode4(561698), // Rule ID 30280 //
     /*  561646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode2),
     /*  561649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561654 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561663 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561674 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561682 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561696 */     GIR_RootConstrainSelectedInstOperands,
     /*  561697 */     // GIR_Coverage, 30280,
     /*  561697 */     GIR_EraseRootFromParent_Done,
     /*  561698 */   // Label 8605: @561698
     /*  561698 */   GIM_Try, /*On fail goto*//*Label 8606*/ GIMT_Encode4(561755), // Rule ID 30281 //
     /*  561703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode3),
     /*  561706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561720 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561731 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561739 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561749 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561753 */     GIR_RootConstrainSelectedInstOperands,
     /*  561754 */     // GIR_Coverage, 30281,
     /*  561754 */     GIR_EraseRootFromParent_Done,
     /*  561755 */   // Label 8606: @561755
     /*  561755 */   GIM_Try, /*On fail goto*//*Label 8607*/ GIMT_Encode4(561812), // Rule ID 30282 //
     /*  561760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init_HwMode4),
     /*  561763 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  561773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561777 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
     /*  561781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  561788 */     // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15621:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  561788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
     /*  561791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  561796 */     GIR_RootToRootCopy, /*OpIdx*/0, // value
     /*  561798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  561803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  561806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561810 */     GIR_RootConstrainSelectedInstOperands,
     /*  561811 */     // GIR_Coverage, 30282,
     /*  561811 */     GIR_EraseRootFromParent_Done,
     /*  561812 */   // Label 8607: @561812
     /*  561812 */   GIM_Try, /*On fail goto*//*Label 8608*/ GIMT_Encode4(561867), // Rule ID 14722 //
     /*  561817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  561820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  561825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  561836 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  561836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  561839 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  561841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  561846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  561851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  561856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  561861 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561865 */     GIR_RootConstrainSelectedInstOperands,
     /*  561866 */     // GIR_Coverage, 14722,
     /*  561866 */     GIR_EraseRootFromParent_Done,
     /*  561867 */   // Label 8608: @561867
     /*  561867 */   GIM_Try, /*On fail goto*//*Label 8609*/ GIMT_Encode4(561922), // Rule ID 14723 //
     /*  561872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  561875 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  561880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  561891 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  561891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  561894 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  561896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  561901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  561906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  561911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  561916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561920 */     GIR_RootConstrainSelectedInstOperands,
     /*  561921 */     // GIR_Coverage, 14723,
     /*  561921 */     GIR_EraseRootFromParent_Done,
     /*  561922 */   // Label 8609: @561922
     /*  561922 */   GIM_Try, /*On fail goto*//*Label 8610*/ GIMT_Encode4(561977), // Rule ID 14724 //
     /*  561927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  561930 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  561935 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  561946 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  561946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  561949 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  561951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  561956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  561961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  561966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  561971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  561975 */     GIR_RootConstrainSelectedInstOperands,
     /*  561976 */     // GIR_Coverage, 14724,
     /*  561976 */     GIR_EraseRootFromParent_Done,
     /*  561977 */   // Label 8610: @561977
     /*  561977 */   GIM_Try, /*On fail goto*//*Label 8611*/ GIMT_Encode4(562032), // Rule ID 14725 //
     /*  561982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  561985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  561990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  561994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562001 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562004 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562030 */     GIR_RootConstrainSelectedInstOperands,
     /*  562031 */     // GIR_Coverage, 14725,
     /*  562031 */     GIR_EraseRootFromParent_Done,
     /*  562032 */   // Label 8611: @562032
     /*  562032 */   GIM_Try, /*On fail goto*//*Label 8612*/ GIMT_Encode4(562087), // Rule ID 14726 //
     /*  562037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  562040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562056 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562059 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562085 */     GIR_RootConstrainSelectedInstOperands,
     /*  562086 */     // GIR_Coverage, 14726,
     /*  562086 */     GIR_EraseRootFromParent_Done,
     /*  562087 */   // Label 8612: @562087
     /*  562087 */   GIM_Try, /*On fail goto*//*Label 8613*/ GIMT_Encode4(562142), // Rule ID 14752 //
     /*  562092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode0),
     /*  562095 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562111 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562114 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562140 */     GIR_RootConstrainSelectedInstOperands,
     /*  562141 */     // GIR_Coverage, 14752,
     /*  562141 */     GIR_EraseRootFromParent_Done,
     /*  562142 */   // Label 8613: @562142
     /*  562142 */   GIM_Try, /*On fail goto*//*Label 8614*/ GIMT_Encode4(562197), // Rule ID 14753 //
     /*  562147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode1),
     /*  562150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562166 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562169 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562195 */     GIR_RootConstrainSelectedInstOperands,
     /*  562196 */     // GIR_Coverage, 14753,
     /*  562196 */     GIR_EraseRootFromParent_Done,
     /*  562197 */   // Label 8614: @562197
     /*  562197 */   GIM_Try, /*On fail goto*//*Label 8615*/ GIMT_Encode4(562252), // Rule ID 14754 //
     /*  562202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode2),
     /*  562205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562221 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562224 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562250 */     GIR_RootConstrainSelectedInstOperands,
     /*  562251 */     // GIR_Coverage, 14754,
     /*  562251 */     GIR_EraseRootFromParent_Done,
     /*  562252 */   // Label 8615: @562252
     /*  562252 */   GIM_Try, /*On fail goto*//*Label 8616*/ GIMT_Encode4(562307), // Rule ID 14755 //
     /*  562257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode3),
     /*  562260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562276 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562279 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562305 */     GIR_RootConstrainSelectedInstOperands,
     /*  562306 */     // GIR_Coverage, 14755,
     /*  562306 */     GIR_EraseRootFromParent_Done,
     /*  562307 */   // Label 8616: @562307
     /*  562307 */   GIM_Try, /*On fail goto*//*Label 8617*/ GIMT_Encode4(562362), // Rule ID 14756 //
     /*  562312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode_HwMode4),
     /*  562315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562320 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562324 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
     /*  562331 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  562331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
     /*  562334 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
     /*  562346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  562351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  562356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562360 */     GIR_RootConstrainSelectedInstOperands,
     /*  562361 */     // GIR_Coverage, 14756,
     /*  562361 */     GIR_EraseRootFromParent_Done,
     /*  562362 */   // Label 8617: @562362
     /*  562362 */   GIM_Try, /*On fail goto*//*Label 8618*/ GIMT_Encode4(562410), // Rule ID 14717 //
     /*  562367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  562370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562386 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562389 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562408 */     GIR_RootConstrainSelectedInstOperands,
     /*  562409 */     // GIR_Coverage, 14717,
     /*  562409 */     GIR_EraseRootFromParent_Done,
     /*  562410 */   // Label 8618: @562410
     /*  562410 */   GIM_Try, /*On fail goto*//*Label 8619*/ GIMT_Encode4(562458), // Rule ID 14718 //
     /*  562415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  562418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562427 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562434 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562437 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562456 */     GIR_RootConstrainSelectedInstOperands,
     /*  562457 */     // GIR_Coverage, 14718,
     /*  562457 */     GIR_EraseRootFromParent_Done,
     /*  562458 */   // Label 8619: @562458
     /*  562458 */   GIM_Try, /*On fail goto*//*Label 8620*/ GIMT_Encode4(562506), // Rule ID 14719 //
     /*  562463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  562466 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562482 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562485 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562504 */     GIR_RootConstrainSelectedInstOperands,
     /*  562505 */     // GIR_Coverage, 14719,
     /*  562505 */     GIR_EraseRootFromParent_Done,
     /*  562506 */   // Label 8620: @562506
     /*  562506 */   GIM_Try, /*On fail goto*//*Label 8621*/ GIMT_Encode4(562554), // Rule ID 14720 //
     /*  562511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  562514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562530 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562533 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562552 */     GIR_RootConstrainSelectedInstOperands,
     /*  562553 */     // GIR_Coverage, 14720,
     /*  562553 */     GIR_EraseRootFromParent_Done,
     /*  562554 */   // Label 8621: @562554
     /*  562554 */   GIM_Try, /*On fail goto*//*Label 8622*/ GIMT_Encode4(562602), // Rule ID 14721 //
     /*  562559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  562562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562578 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562581 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562600 */     GIR_RootConstrainSelectedInstOperands,
     /*  562601 */     // GIR_Coverage, 14721,
     /*  562601 */     GIR_EraseRootFromParent_Done,
     /*  562602 */   // Label 8622: @562602
     /*  562602 */   GIM_Try, /*On fail goto*//*Label 8623*/ GIMT_Encode4(562650), // Rule ID 14747 //
     /*  562607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  562610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562626 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562629 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562644 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562648 */     GIR_RootConstrainSelectedInstOperands,
     /*  562649 */     // GIR_Coverage, 14747,
     /*  562649 */     GIR_EraseRootFromParent_Done,
     /*  562650 */   // Label 8623: @562650
     /*  562650 */   GIM_Try, /*On fail goto*//*Label 8624*/ GIMT_Encode4(562698), // Rule ID 14748 //
     /*  562655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  562658 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562674 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562677 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562696 */     GIR_RootConstrainSelectedInstOperands,
     /*  562697 */     // GIR_Coverage, 14748,
     /*  562697 */     GIR_EraseRootFromParent_Done,
     /*  562698 */   // Label 8624: @562698
     /*  562698 */   GIM_Try, /*On fail goto*//*Label 8625*/ GIMT_Encode4(562746), // Rule ID 14749 //
     /*  562703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  562706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562722 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562725 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562737 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562744 */     GIR_RootConstrainSelectedInstOperands,
     /*  562745 */     // GIR_Coverage, 14749,
     /*  562745 */     GIR_EraseRootFromParent_Done,
     /*  562746 */   // Label 8625: @562746
     /*  562746 */   GIM_Try, /*On fail goto*//*Label 8626*/ GIMT_Encode4(562794), // Rule ID 14750 //
     /*  562751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  562754 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562770 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562773 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562792 */     GIR_RootConstrainSelectedInstOperands,
     /*  562793 */     // GIR_Coverage, 14750,
     /*  562793 */     GIR_EraseRootFromParent_Done,
     /*  562794 */   // Label 8626: @562794
     /*  562794 */   GIM_Try, /*On fail goto*//*Label 8627*/ GIMT_Encode4(562842), // Rule ID 14751 //
     /*  562799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  562802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
     /*  562818 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
     /*  562818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
     /*  562821 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  562828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562840 */     GIR_RootConstrainSelectedInstOperands,
     /*  562841 */     // GIR_Coverage, 14751,
     /*  562841 */     GIR_EraseRootFromParent_Done,
     /*  562842 */   // Label 8627: @562842
     /*  562842 */   GIM_Try, /*On fail goto*//*Label 8628*/ GIMT_Encode4(562890), // Rule ID 14712 //
     /*  562847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  562850 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  562866 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  562866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  562869 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562888 */     GIR_RootConstrainSelectedInstOperands,
     /*  562889 */     // GIR_Coverage, 14712,
     /*  562889 */     GIR_EraseRootFromParent_Done,
     /*  562890 */   // Label 8628: @562890
     /*  562890 */   GIM_Try, /*On fail goto*//*Label 8629*/ GIMT_Encode4(562938), // Rule ID 14713 //
     /*  562895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  562898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562903 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  562914 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  562914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  562917 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562936 */     GIR_RootConstrainSelectedInstOperands,
     /*  562937 */     // GIR_Coverage, 14713,
     /*  562937 */     GIR_EraseRootFromParent_Done,
     /*  562938 */   // Label 8629: @562938
     /*  562938 */   GIM_Try, /*On fail goto*//*Label 8630*/ GIMT_Encode4(562986), // Rule ID 14714 //
     /*  562943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  562946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  562955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  562962 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  562962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  562965 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  562967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  562972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  562977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  562980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  562984 */     GIR_RootConstrainSelectedInstOperands,
     /*  562985 */     // GIR_Coverage, 14714,
     /*  562985 */     GIR_EraseRootFromParent_Done,
     /*  562986 */   // Label 8630: @562986
     /*  562986 */   GIM_Try, /*On fail goto*//*Label 8631*/ GIMT_Encode4(563034), // Rule ID 14715 //
     /*  562991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  562994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  562999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563010 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563013 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563032 */     GIR_RootConstrainSelectedInstOperands,
     /*  563033 */     // GIR_Coverage, 14715,
     /*  563033 */     GIR_EraseRootFromParent_Done,
     /*  563034 */   // Label 8631: @563034
     /*  563034 */   GIM_Try, /*On fail goto*//*Label 8632*/ GIMT_Encode4(563082), // Rule ID 14716 //
     /*  563039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  563042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  563047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563058 */     // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563061 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563080 */     GIR_RootConstrainSelectedInstOperands,
     /*  563081 */     // GIR_Coverage, 14716,
     /*  563081 */     GIR_EraseRootFromParent_Done,
     /*  563082 */   // Label 8632: @563082
     /*  563082 */   GIM_Try, /*On fail goto*//*Label 8633*/ GIMT_Encode4(563130), // Rule ID 14742 //
     /*  563087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode0),
     /*  563090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  563095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563106 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563109 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563128 */     GIR_RootConstrainSelectedInstOperands,
     /*  563129 */     // GIR_Coverage, 14742,
     /*  563129 */     GIR_EraseRootFromParent_Done,
     /*  563130 */   // Label 8633: @563130
     /*  563130 */   GIM_Try, /*On fail goto*//*Label 8634*/ GIMT_Encode4(563178), // Rule ID 14743 //
     /*  563135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode1),
     /*  563138 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  563143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563154 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563157 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563176 */     GIR_RootConstrainSelectedInstOperands,
     /*  563177 */     // GIR_Coverage, 14743,
     /*  563177 */     GIR_EraseRootFromParent_Done,
     /*  563178 */   // Label 8634: @563178
     /*  563178 */   GIM_Try, /*On fail goto*//*Label 8635*/ GIMT_Encode4(563226), // Rule ID 14744 //
     /*  563183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode2),
     /*  563186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  563191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563202 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563205 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563224 */     GIR_RootConstrainSelectedInstOperands,
     /*  563225 */     // GIR_Coverage, 14744,
     /*  563225 */     GIR_EraseRootFromParent_Done,
     /*  563226 */   // Label 8635: @563226
     /*  563226 */   GIM_Try, /*On fail goto*//*Label 8636*/ GIMT_Encode4(563274), // Rule ID 14745 //
     /*  563231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode3),
     /*  563234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  563239 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563250 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563253 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563272 */     GIR_RootConstrainSelectedInstOperands,
     /*  563273 */     // GIR_Coverage, 14745,
     /*  563273 */     GIR_EraseRootFromParent_Done,
     /*  563274 */   // Label 8636: @563274
     /*  563274 */   GIM_Try, /*On fail goto*//*Label 8637*/ GIMT_Encode4(563322), // Rule ID 14746 //
     /*  563279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HwMode4),
     /*  563282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
     /*  563287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
     /*  563298 */     // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  563298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
     /*  563301 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  563303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  563308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  563313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563320 */     GIR_RootConstrainSelectedInstOperands,
     /*  563321 */     // GIR_Coverage, 14746,
     /*  563321 */     GIR_EraseRootFromParent_Done,
     /*  563322 */   // Label 8637: @563322
     /*  563322 */   GIM_Try, /*On fail goto*//*Label 8638*/ GIMT_Encode4(563385), // Rule ID 16358 //
     /*  563327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  563330 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563348 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  563351 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563383 */     GIR_RootConstrainSelectedInstOperands,
     /*  563384 */     // GIR_Coverage, 16358,
     /*  563384 */     GIR_EraseRootFromParent_Done,
     /*  563385 */   // Label 8638: @563385
     /*  563385 */   GIM_Try, /*On fail goto*//*Label 8639*/ GIMT_Encode4(563448), // Rule ID 16359 //
     /*  563390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  563393 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563411 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  563414 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563446 */     GIR_RootConstrainSelectedInstOperands,
     /*  563447 */     // GIR_Coverage, 16359,
     /*  563447 */     GIR_EraseRootFromParent_Done,
     /*  563448 */   // Label 8639: @563448
     /*  563448 */   GIM_Try, /*On fail goto*//*Label 8640*/ GIMT_Encode4(563511), // Rule ID 16360 //
     /*  563453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  563456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563474 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  563477 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563509 */     GIR_RootConstrainSelectedInstOperands,
     /*  563510 */     // GIR_Coverage, 16360,
     /*  563510 */     GIR_EraseRootFromParent_Done,
     /*  563511 */   // Label 8640: @563511
     /*  563511 */   GIM_Try, /*On fail goto*//*Label 8641*/ GIMT_Encode4(563574), // Rule ID 16361 //
     /*  563516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  563519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563537 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  563540 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563572 */     GIR_RootConstrainSelectedInstOperands,
     /*  563573 */     // GIR_Coverage, 16361,
     /*  563573 */     GIR_EraseRootFromParent_Done,
     /*  563574 */   // Label 8641: @563574
     /*  563574 */   GIM_Try, /*On fail goto*//*Label 8642*/ GIMT_Encode4(563637), // Rule ID 16362 //
     /*  563579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  563582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563600 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  563603 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563635 */     GIR_RootConstrainSelectedInstOperands,
     /*  563636 */     // GIR_Coverage, 16362,
     /*  563636 */     GIR_EraseRootFromParent_Done,
     /*  563637 */   // Label 8642: @563637
     /*  563637 */   GIM_Try, /*On fail goto*//*Label 8643*/ GIMT_Encode4(563700), // Rule ID 16368 //
     /*  563642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  563645 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563663 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  563666 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563688 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563698 */     GIR_RootConstrainSelectedInstOperands,
     /*  563699 */     // GIR_Coverage, 16368,
     /*  563699 */     GIR_EraseRootFromParent_Done,
     /*  563700 */   // Label 8643: @563700
     /*  563700 */   GIM_Try, /*On fail goto*//*Label 8644*/ GIMT_Encode4(563763), // Rule ID 16369 //
     /*  563705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  563708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563726 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  563729 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563761 */     GIR_RootConstrainSelectedInstOperands,
     /*  563762 */     // GIR_Coverage, 16369,
     /*  563762 */     GIR_EraseRootFromParent_Done,
     /*  563763 */   // Label 8644: @563763
     /*  563763 */   GIM_Try, /*On fail goto*//*Label 8645*/ GIMT_Encode4(563826), // Rule ID 16370 //
     /*  563768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  563771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563782 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563789 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  563792 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563824 */     GIR_RootConstrainSelectedInstOperands,
     /*  563825 */     // GIR_Coverage, 16370,
     /*  563825 */     GIR_EraseRootFromParent_Done,
     /*  563826 */   // Label 8645: @563826
     /*  563826 */   GIM_Try, /*On fail goto*//*Label 8646*/ GIMT_Encode4(563889), // Rule ID 16371 //
     /*  563831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  563834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563852 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  563855 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563887 */     GIR_RootConstrainSelectedInstOperands,
     /*  563888 */     // GIR_Coverage, 16371,
     /*  563888 */     GIR_EraseRootFromParent_Done,
     /*  563889 */   // Label 8646: @563889
     /*  563889 */   GIM_Try, /*On fail goto*//*Label 8647*/ GIMT_Encode4(563952), // Rule ID 16372 //
     /*  563894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  563897 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563904 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563915 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  563918 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  563940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  563946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  563950 */     GIR_RootConstrainSelectedInstOperands,
     /*  563951 */     // GIR_Coverage, 16372,
     /*  563951 */     GIR_EraseRootFromParent_Done,
     /*  563952 */   // Label 8647: @563952
     /*  563952 */   GIM_Try, /*On fail goto*//*Label 8648*/ GIMT_Encode4(564015), // Rule ID 16378 //
     /*  563957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  563960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  563967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  563971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  563978 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  563978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  563981 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  563983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  563988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  563993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  563998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564013 */     GIR_RootConstrainSelectedInstOperands,
     /*  564014 */     // GIR_Coverage, 16378,
     /*  564014 */     GIR_EraseRootFromParent_Done,
     /*  564015 */   // Label 8648: @564015
     /*  564015 */   GIM_Try, /*On fail goto*//*Label 8649*/ GIMT_Encode4(564078), // Rule ID 16379 //
     /*  564020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  564023 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564030 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564034 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564041 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  564044 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564076 */     GIR_RootConstrainSelectedInstOperands,
     /*  564077 */     // GIR_Coverage, 16379,
     /*  564077 */     GIR_EraseRootFromParent_Done,
     /*  564078 */   // Label 8649: @564078
     /*  564078 */   GIM_Try, /*On fail goto*//*Label 8650*/ GIMT_Encode4(564141), // Rule ID 16380 //
     /*  564083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  564086 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564104 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  564107 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564139 */     GIR_RootConstrainSelectedInstOperands,
     /*  564140 */     // GIR_Coverage, 16380,
     /*  564140 */     GIR_EraseRootFromParent_Done,
     /*  564141 */   // Label 8650: @564141
     /*  564141 */   GIM_Try, /*On fail goto*//*Label 8651*/ GIMT_Encode4(564204), // Rule ID 16381 //
     /*  564146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  564149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564156 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564160 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564167 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  564170 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564202 */     GIR_RootConstrainSelectedInstOperands,
     /*  564203 */     // GIR_Coverage, 16381,
     /*  564203 */     GIR_EraseRootFromParent_Done,
     /*  564204 */   // Label 8651: @564204
     /*  564204 */   GIM_Try, /*On fail goto*//*Label 8652*/ GIMT_Encode4(564267), // Rule ID 16382 //
     /*  564209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  564212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564223 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564230 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
     /*  564233 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564265 */     GIR_RootConstrainSelectedInstOperands,
     /*  564266 */     // GIR_Coverage, 16382,
     /*  564266 */     GIR_EraseRootFromParent_Done,
     /*  564267 */   // Label 8652: @564267
     /*  564267 */   GIM_Try, /*On fail goto*//*Label 8653*/ GIMT_Encode4(564330), // Rule ID 16388 //
     /*  564272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  564275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564293 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  564296 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564328 */     GIR_RootConstrainSelectedInstOperands,
     /*  564329 */     // GIR_Coverage, 16388,
     /*  564329 */     GIR_EraseRootFromParent_Done,
     /*  564330 */   // Label 8653: @564330
     /*  564330 */   GIM_Try, /*On fail goto*//*Label 8654*/ GIMT_Encode4(564393), // Rule ID 16389 //
     /*  564335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  564338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564356 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  564359 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564391 */     GIR_RootConstrainSelectedInstOperands,
     /*  564392 */     // GIR_Coverage, 16389,
     /*  564392 */     GIR_EraseRootFromParent_Done,
     /*  564393 */   // Label 8654: @564393
     /*  564393 */   GIM_Try, /*On fail goto*//*Label 8655*/ GIMT_Encode4(564456), // Rule ID 16390 //
     /*  564398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  564401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564419 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  564422 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564454 */     GIR_RootConstrainSelectedInstOperands,
     /*  564455 */     // GIR_Coverage, 16390,
     /*  564455 */     GIR_EraseRootFromParent_Done,
     /*  564456 */   // Label 8655: @564456
     /*  564456 */   GIM_Try, /*On fail goto*//*Label 8656*/ GIMT_Encode4(564519), // Rule ID 16391 //
     /*  564461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  564464 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564482 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  564485 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564517 */     GIR_RootConstrainSelectedInstOperands,
     /*  564518 */     // GIR_Coverage, 16391,
     /*  564518 */     GIR_EraseRootFromParent_Done,
     /*  564519 */   // Label 8656: @564519
     /*  564519 */   GIM_Try, /*On fail goto*//*Label 8657*/ GIMT_Encode4(564582), // Rule ID 16392 //
     /*  564524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  564527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  564534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  564545 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  564545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
     /*  564548 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  564550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  564555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  564560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  564565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  564570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564576 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564580 */     GIR_RootConstrainSelectedInstOperands,
     /*  564581 */     // GIR_Coverage, 16392,
     /*  564581 */     GIR_EraseRootFromParent_Done,
     /*  564582 */   // Label 8657: @564582
     /*  564582 */   GIM_Try, /*On fail goto*//*Label 8658*/ GIMT_Encode4(564699), // Rule ID 29568 //
     /*  564587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  564590 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  564594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  564599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  564610 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  564610 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  564613 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564617 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564622 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  564628 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564633 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564638 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  564641 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564645 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564650 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  564656 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564661 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  564669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  564674 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  564677 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  564680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  564685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  564690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564697 */     GIR_RootConstrainSelectedInstOperands,
     /*  564698 */     // GIR_Coverage, 29568,
     /*  564698 */     GIR_EraseRootFromParent_Done,
     /*  564699 */   // Label 8658: @564699
     /*  564699 */   GIM_Try, /*On fail goto*//*Label 8659*/ GIMT_Encode4(564816), // Rule ID 29569 //
     /*  564704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  564707 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  564711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  564716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  564727 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  564727 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  564730 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564734 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564739 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  564745 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564750 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564755 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  564758 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564762 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564767 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  564773 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564778 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  564786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  564791 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  564794 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  564797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  564802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  564807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564814 */     GIR_RootConstrainSelectedInstOperands,
     /*  564815 */     // GIR_Coverage, 29569,
     /*  564815 */     GIR_EraseRootFromParent_Done,
     /*  564816 */   // Label 8659: @564816
     /*  564816 */   GIM_Try, /*On fail goto*//*Label 8660*/ GIMT_Encode4(564933), // Rule ID 29570 //
     /*  564821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  564824 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  564828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  564833 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564837 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  564844 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  564844 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  564847 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564851 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564856 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  564862 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564867 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564872 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  564875 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564879 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564884 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  564890 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564895 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  564903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  564908 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  564911 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  564914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  564919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  564924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  564927 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  564931 */     GIR_RootConstrainSelectedInstOperands,
     /*  564932 */     // GIR_Coverage, 29570,
     /*  564932 */     GIR_EraseRootFromParent_Done,
     /*  564933 */   // Label 8660: @564933
     /*  564933 */   GIM_Try, /*On fail goto*//*Label 8661*/ GIMT_Encode4(565050), // Rule ID 29571 //
     /*  564938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  564941 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  564945 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  564950 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  564954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  564961 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  564961 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  564964 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564968 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  564973 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  564979 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  564984 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  564989 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  564992 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  564996 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565001 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565007 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565012 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565025 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565028 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565044 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565048 */     GIR_RootConstrainSelectedInstOperands,
     /*  565049 */     // GIR_Coverage, 29571,
     /*  565049 */     GIR_EraseRootFromParent_Done,
     /*  565050 */   // Label 8661: @565050
     /*  565050 */   GIM_Try, /*On fail goto*//*Label 8662*/ GIMT_Encode4(565167), // Rule ID 29572 //
     /*  565055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  565058 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  565062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  565067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  565078 */     // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  565078 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  565081 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565085 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565090 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  565096 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565101 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565106 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  565109 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565113 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565118 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565124 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565129 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565142 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565145 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565165 */     GIR_RootConstrainSelectedInstOperands,
     /*  565166 */     // GIR_Coverage, 29572,
     /*  565166 */     GIR_EraseRootFromParent_Done,
     /*  565167 */   // Label 8662: @565167
     /*  565167 */   GIM_Try, /*On fail goto*//*Label 8663*/ GIMT_Encode4(565284), // Rule ID 29588 //
     /*  565172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode0),
     /*  565175 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  565179 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  565184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  565195 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  565195 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  565198 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565202 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565207 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  565213 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565218 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565223 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  565226 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565230 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565235 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565241 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565246 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565259 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565262 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565282 */     GIR_RootConstrainSelectedInstOperands,
     /*  565283 */     // GIR_Coverage, 29588,
     /*  565283 */     GIR_EraseRootFromParent_Done,
     /*  565284 */   // Label 8663: @565284
     /*  565284 */   GIM_Try, /*On fail goto*//*Label 8664*/ GIMT_Encode4(565401), // Rule ID 29589 //
     /*  565289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode1),
     /*  565292 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  565296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  565301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  565312 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  565312 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  565315 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565319 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565324 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  565330 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565335 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  565343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565352 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565358 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565363 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565376 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565379 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565399 */     GIR_RootConstrainSelectedInstOperands,
     /*  565400 */     // GIR_Coverage, 29589,
     /*  565400 */     GIR_EraseRootFromParent_Done,
     /*  565401 */   // Label 8664: @565401
     /*  565401 */   GIM_Try, /*On fail goto*//*Label 8665*/ GIMT_Encode4(565518), // Rule ID 29590 //
     /*  565406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode2),
     /*  565409 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  565413 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  565418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  565429 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  565429 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  565432 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565436 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565441 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  565447 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565452 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565457 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  565460 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565464 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565469 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565475 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565480 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565493 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565496 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565512 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565516 */     GIR_RootConstrainSelectedInstOperands,
     /*  565517 */     // GIR_Coverage, 29590,
     /*  565517 */     GIR_EraseRootFromParent_Done,
     /*  565518 */   // Label 8665: @565518
     /*  565518 */   GIM_Try, /*On fail goto*//*Label 8666*/ GIMT_Encode4(565635), // Rule ID 29591 //
     /*  565523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode3),
     /*  565526 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  565530 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  565535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  565546 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  565546 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  565549 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565553 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565558 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  565564 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565569 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565574 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  565577 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565581 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565586 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565592 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565597 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565610 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565613 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565633 */     GIR_RootConstrainSelectedInstOperands,
     /*  565634 */     // GIR_Coverage, 29591,
     /*  565634 */     GIR_EraseRootFromParent_Done,
     /*  565635 */   // Label 8666: @565635
     /*  565635 */   GIM_Try, /*On fail goto*//*Label 8667*/ GIMT_Encode4(565752), // Rule ID 29592 //
     /*  565640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus_HwMode4),
     /*  565643 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /*  565647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  565652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  565663 */     // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  565663 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  565666 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565670 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565675 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  565681 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565686 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565691 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  565694 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  565698 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  565703 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  565709 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  565714 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  565719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
     /*  565722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  565727 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  565730 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  565733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  565738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  565743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565750 */     GIR_RootConstrainSelectedInstOperands,
     /*  565751 */     // GIR_Coverage, 29592,
     /*  565751 */     GIR_EraseRootFromParent_Done,
     /*  565752 */   // Label 8667: @565752
     /*  565752 */   GIM_Try, /*On fail goto*//*Label 8668*/ GIMT_Encode4(565810), // Rule ID 16353 //
     /*  565757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  565760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  565767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  565778 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  565778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  565781 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  565783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  565788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  565793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  565798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565808 */     GIR_RootConstrainSelectedInstOperands,
     /*  565809 */     // GIR_Coverage, 16353,
     /*  565809 */     GIR_EraseRootFromParent_Done,
     /*  565810 */   // Label 8668: @565810
     /*  565810 */   GIM_Try, /*On fail goto*//*Label 8669*/ GIMT_Encode4(565868), // Rule ID 16354 //
     /*  565815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  565818 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  565825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  565836 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  565836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  565839 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  565841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  565846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  565851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  565856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565866 */     GIR_RootConstrainSelectedInstOperands,
     /*  565867 */     // GIR_Coverage, 16354,
     /*  565867 */     GIR_EraseRootFromParent_Done,
     /*  565868 */   // Label 8669: @565868
     /*  565868 */   GIM_Try, /*On fail goto*//*Label 8670*/ GIMT_Encode4(565926), // Rule ID 16355 //
     /*  565873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  565876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  565883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  565894 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  565894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  565897 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  565899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  565904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  565909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  565914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565920 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565924 */     GIR_RootConstrainSelectedInstOperands,
     /*  565925 */     // GIR_Coverage, 16355,
     /*  565925 */     GIR_EraseRootFromParent_Done,
     /*  565926 */   // Label 8670: @565926
     /*  565926 */   GIM_Try, /*On fail goto*//*Label 8671*/ GIMT_Encode4(565984), // Rule ID 16356 //
     /*  565931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  565934 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  565941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  565945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  565952 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  565952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  565955 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  565957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  565962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  565967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  565972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  565978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  565982 */     GIR_RootConstrainSelectedInstOperands,
     /*  565983 */     // GIR_Coverage, 16356,
     /*  565983 */     GIR_EraseRootFromParent_Done,
     /*  565984 */   // Label 8671: @565984
     /*  565984 */   GIM_Try, /*On fail goto*//*Label 8672*/ GIMT_Encode4(566042), // Rule ID 16357 //
     /*  565989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  565992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  565999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566010 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  566013 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566040 */     GIR_RootConstrainSelectedInstOperands,
     /*  566041 */     // GIR_Coverage, 16357,
     /*  566041 */     GIR_EraseRootFromParent_Done,
     /*  566042 */   // Label 8672: @566042
     /*  566042 */   GIM_Try, /*On fail goto*//*Label 8673*/ GIMT_Encode4(566100), // Rule ID 16363 //
     /*  566047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  566050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566057 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566068 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566071 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566098 */     GIR_RootConstrainSelectedInstOperands,
     /*  566099 */     // GIR_Coverage, 16363,
     /*  566099 */     GIR_EraseRootFromParent_Done,
     /*  566100 */   // Label 8673: @566100
     /*  566100 */   GIM_Try, /*On fail goto*//*Label 8674*/ GIMT_Encode4(566158), // Rule ID 16364 //
     /*  566105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  566108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566126 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566129 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566156 */     GIR_RootConstrainSelectedInstOperands,
     /*  566157 */     // GIR_Coverage, 16364,
     /*  566157 */     GIR_EraseRootFromParent_Done,
     /*  566158 */   // Label 8674: @566158
     /*  566158 */   GIM_Try, /*On fail goto*//*Label 8675*/ GIMT_Encode4(566216), // Rule ID 16365 //
     /*  566163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  566166 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566184 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566187 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566214 */     GIR_RootConstrainSelectedInstOperands,
     /*  566215 */     // GIR_Coverage, 16365,
     /*  566215 */     GIR_EraseRootFromParent_Done,
     /*  566216 */   // Label 8675: @566216
     /*  566216 */   GIM_Try, /*On fail goto*//*Label 8676*/ GIMT_Encode4(566274), // Rule ID 16366 //
     /*  566221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  566224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566242 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566245 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566272 */     GIR_RootConstrainSelectedInstOperands,
     /*  566273 */     // GIR_Coverage, 16366,
     /*  566273 */     GIR_EraseRootFromParent_Done,
     /*  566274 */   // Label 8676: @566274
     /*  566274 */   GIM_Try, /*On fail goto*//*Label 8677*/ GIMT_Encode4(566332), // Rule ID 16367 //
     /*  566279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  566282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566300 */     // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566303 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566330 */     GIR_RootConstrainSelectedInstOperands,
     /*  566331 */     // GIR_Coverage, 16367,
     /*  566331 */     GIR_EraseRootFromParent_Done,
     /*  566332 */   // Label 8677: @566332
     /*  566332 */   GIM_Try, /*On fail goto*//*Label 8678*/ GIMT_Encode4(566390), // Rule ID 16373 //
     /*  566337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  566340 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566358 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  566361 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566384 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566388 */     GIR_RootConstrainSelectedInstOperands,
     /*  566389 */     // GIR_Coverage, 16373,
     /*  566389 */     GIR_EraseRootFromParent_Done,
     /*  566390 */   // Label 8678: @566390
     /*  566390 */   GIM_Try, /*On fail goto*//*Label 8679*/ GIMT_Encode4(566448), // Rule ID 16374 //
     /*  566395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  566398 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566416 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  566419 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566446 */     GIR_RootConstrainSelectedInstOperands,
     /*  566447 */     // GIR_Coverage, 16374,
     /*  566447 */     GIR_EraseRootFromParent_Done,
     /*  566448 */   // Label 8679: @566448
     /*  566448 */   GIM_Try, /*On fail goto*//*Label 8680*/ GIMT_Encode4(566506), // Rule ID 16375 //
     /*  566453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  566456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566474 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  566477 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566504 */     GIR_RootConstrainSelectedInstOperands,
     /*  566505 */     // GIR_Coverage, 16375,
     /*  566505 */     GIR_EraseRootFromParent_Done,
     /*  566506 */   // Label 8680: @566506
     /*  566506 */   GIM_Try, /*On fail goto*//*Label 8681*/ GIMT_Encode4(566564), // Rule ID 16376 //
     /*  566511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  566514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566532 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  566535 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566562 */     GIR_RootConstrainSelectedInstOperands,
     /*  566563 */     // GIR_Coverage, 16376,
     /*  566563 */     GIR_EraseRootFromParent_Done,
     /*  566564 */   // Label 8681: @566564
     /*  566564 */   GIM_Try, /*On fail goto*//*Label 8682*/ GIMT_Encode4(566622), // Rule ID 16377 //
     /*  566569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  566572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566590 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
     /*  566593 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566616 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566620 */     GIR_RootConstrainSelectedInstOperands,
     /*  566621 */     // GIR_Coverage, 16377,
     /*  566621 */     GIR_EraseRootFromParent_Done,
     /*  566622 */   // Label 8682: @566622
     /*  566622 */   GIM_Try, /*On fail goto*//*Label 8683*/ GIMT_Encode4(566680), // Rule ID 16383 //
     /*  566627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  566630 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566648 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566651 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566678 */     GIR_RootConstrainSelectedInstOperands,
     /*  566679 */     // GIR_Coverage, 16383,
     /*  566679 */     GIR_EraseRootFromParent_Done,
     /*  566680 */   // Label 8683: @566680
     /*  566680 */   GIM_Try, /*On fail goto*//*Label 8684*/ GIMT_Encode4(566738), // Rule ID 16384 //
     /*  566685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  566688 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566706 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566709 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566732 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566736 */     GIR_RootConstrainSelectedInstOperands,
     /*  566737 */     // GIR_Coverage, 16384,
     /*  566737 */     GIR_EraseRootFromParent_Done,
     /*  566738 */   // Label 8684: @566738
     /*  566738 */   GIM_Try, /*On fail goto*//*Label 8685*/ GIMT_Encode4(566796), // Rule ID 16385 //
     /*  566743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  566746 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566764 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566767 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566794 */     GIR_RootConstrainSelectedInstOperands,
     /*  566795 */     // GIR_Coverage, 16385,
     /*  566795 */     GIR_EraseRootFromParent_Done,
     /*  566796 */   // Label 8685: @566796
     /*  566796 */   GIM_Try, /*On fail goto*//*Label 8686*/ GIMT_Encode4(566854), // Rule ID 16386 //
     /*  566801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  566804 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566822 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566825 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566848 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566852 */     GIR_RootConstrainSelectedInstOperands,
     /*  566853 */     // GIR_Coverage, 16386,
     /*  566853 */     GIR_EraseRootFromParent_Done,
     /*  566854 */   // Label 8686: @566854
     /*  566854 */   GIM_Try, /*On fail goto*//*Label 8687*/ GIMT_Encode4(566912), // Rule ID 16387 //
     /*  566859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  566862 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  566869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  566880 */     // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
     /*  566880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
     /*  566883 */     GIR_RootToRootCopy, /*OpIdx*/0, // vdata
     /*  566885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  566890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  566895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  566900 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  566906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  566910 */     GIR_RootConstrainSelectedInstOperands,
     /*  566911 */     // GIR_Coverage, 16387,
     /*  566911 */     GIR_EraseRootFromParent_Done,
     /*  566912 */   // Label 8687: @566912
     /*  566912 */   GIM_Try, /*On fail goto*//*Label 8688*/ GIMT_Encode4(567025), // Rule ID 29578 //
     /*  566917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  566920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  566925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  566929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  566936 */     // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  566936 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  566939 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  566943 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  566948 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  566954 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  566959 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  566964 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  566967 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  566971 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  566976 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  566982 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  566987 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  566992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  566995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567000 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567003 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567023 */     GIR_RootConstrainSelectedInstOperands,
     /*  567024 */     // GIR_Coverage, 29578,
     /*  567024 */     GIR_EraseRootFromParent_Done,
     /*  567025 */   // Label 8688: @567025
     /*  567025 */   GIM_Try, /*On fail goto*//*Label 8689*/ GIMT_Encode4(567138), // Rule ID 29579 //
     /*  567030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  567033 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567049 */     // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567049 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567052 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567056 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567061 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567067 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567072 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567077 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567080 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567084 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567089 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567095 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567100 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567113 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567116 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567136 */     GIR_RootConstrainSelectedInstOperands,
     /*  567137 */     // GIR_Coverage, 29579,
     /*  567137 */     GIR_EraseRootFromParent_Done,
     /*  567138 */   // Label 8689: @567138
     /*  567138 */   GIM_Try, /*On fail goto*//*Label 8690*/ GIMT_Encode4(567251), // Rule ID 29580 //
     /*  567143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  567146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567162 */     // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567162 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567165 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567169 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567174 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567180 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567185 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567190 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567193 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567197 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567202 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567208 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567213 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567226 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567229 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567245 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567249 */     GIR_RootConstrainSelectedInstOperands,
     /*  567250 */     // GIR_Coverage, 29580,
     /*  567250 */     GIR_EraseRootFromParent_Done,
     /*  567251 */   // Label 8690: @567251
     /*  567251 */   GIM_Try, /*On fail goto*//*Label 8691*/ GIMT_Encode4(567364), // Rule ID 29581 //
     /*  567256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  567259 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567264 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567275 */     // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567275 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567278 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567282 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567287 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567293 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567298 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567303 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567306 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567310 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567315 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567321 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567326 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567339 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567342 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567362 */     GIR_RootConstrainSelectedInstOperands,
     /*  567363 */     // GIR_Coverage, 29581,
     /*  567363 */     GIR_EraseRootFromParent_Done,
     /*  567364 */   // Label 8691: @567364
     /*  567364 */   GIM_Try, /*On fail goto*//*Label 8692*/ GIMT_Encode4(567477), // Rule ID 29582 //
     /*  567369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  567372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567388 */     // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567388 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567391 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567395 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567400 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567406 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567411 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567416 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567419 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567423 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567428 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567434 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567439 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567452 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567455 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567471 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567475 */     GIR_RootConstrainSelectedInstOperands,
     /*  567476 */     // GIR_Coverage, 29582,
     /*  567476 */     GIR_EraseRootFromParent_Done,
     /*  567477 */   // Label 8692: @567477
     /*  567477 */   GIM_Try, /*On fail goto*//*Label 8693*/ GIMT_Encode4(567590), // Rule ID 29598 //
     /*  567482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  567485 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567501 */     // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567501 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567504 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567508 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567513 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567519 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567524 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567529 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567532 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567536 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567541 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567547 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567552 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567565 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567568 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567588 */     GIR_RootConstrainSelectedInstOperands,
     /*  567589 */     // GIR_Coverage, 29598,
     /*  567589 */     GIR_EraseRootFromParent_Done,
     /*  567590 */   // Label 8693: @567590
     /*  567590 */   GIM_Try, /*On fail goto*//*Label 8694*/ GIMT_Encode4(567703), // Rule ID 29599 //
     /*  567595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  567598 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567603 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567614 */     // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567614 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567617 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567621 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567626 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567632 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567637 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567642 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567645 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567649 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567654 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567660 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567665 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567678 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567681 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567701 */     GIR_RootConstrainSelectedInstOperands,
     /*  567702 */     // GIR_Coverage, 29599,
     /*  567702 */     GIR_EraseRootFromParent_Done,
     /*  567703 */   // Label 8694: @567703
     /*  567703 */   GIM_Try, /*On fail goto*//*Label 8695*/ GIMT_Encode4(567816), // Rule ID 29600 //
     /*  567708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  567711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567727 */     // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567727 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567730 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567734 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567739 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567745 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567750 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567755 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567758 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567762 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567767 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567773 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567778 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567791 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567794 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567814 */     GIR_RootConstrainSelectedInstOperands,
     /*  567815 */     // GIR_Coverage, 29600,
     /*  567815 */     GIR_EraseRootFromParent_Done,
     /*  567816 */   // Label 8695: @567816
     /*  567816 */   GIM_Try, /*On fail goto*//*Label 8696*/ GIMT_Encode4(567929), // Rule ID 29601 //
     /*  567821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  567824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567840 */     // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567840 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567843 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567847 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567852 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567858 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567863 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567868 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567871 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567875 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567880 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567886 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567891 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  567899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  567904 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  567907 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  567910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  567915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  567920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  567923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  567927 */     GIR_RootConstrainSelectedInstOperands,
     /*  567928 */     // GIR_Coverage, 29601,
     /*  567928 */     GIR_EraseRootFromParent_Done,
     /*  567929 */   // Label 8696: @567929
     /*  567929 */   GIM_Try, /*On fail goto*//*Label 8697*/ GIMT_Encode4(568042), // Rule ID 29602 //
     /*  567934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  567937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  567942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  567946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
     /*  567953 */     // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset0, i32:{ *:[i32] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i32] }:$offset0, ?:{ *:[i32] }:$offset1, 0:{ *:[i1] })
     /*  567953 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  567956 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567960 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567965 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
     /*  567971 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  567976 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  567981 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  567984 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  567988 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  567993 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
     /*  567999 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  568004 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  568009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
     /*  568012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  568017 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  568020 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  568023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
     /*  568028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
     /*  568033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568040 */     GIR_RootConstrainSelectedInstOperands,
     /*  568041 */     // GIR_Coverage, 29602,
     /*  568041 */     GIR_EraseRootFromParent_Done,
     /*  568042 */   // Label 8697: @568042
     /*  568042 */   GIM_Try, /*On fail goto*//*Label 8698*/ GIMT_Encode4(568099), // Rule ID 12543 //
     /*  568047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  568050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568057 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568068 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568076 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568093 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568097 */     GIR_RootConstrainSelectedInstOperands,
     /*  568098 */     // GIR_Coverage, 12543,
     /*  568098 */     GIR_EraseRootFromParent_Done,
     /*  568099 */   // Label 8698: @568099
     /*  568099 */   GIM_Try, /*On fail goto*//*Label 8699*/ GIMT_Encode4(568156), // Rule ID 12544 //
     /*  568104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  568107 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568114 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568125 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568133 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568154 */     GIR_RootConstrainSelectedInstOperands,
     /*  568155 */     // GIR_Coverage, 12544,
     /*  568155 */     GIR_EraseRootFromParent_Done,
     /*  568156 */   // Label 8699: @568156
     /*  568156 */   GIM_Try, /*On fail goto*//*Label 8700*/ GIMT_Encode4(568213), // Rule ID 12545 //
     /*  568161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  568164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568182 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568190 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568211 */     GIR_RootConstrainSelectedInstOperands,
     /*  568212 */     // GIR_Coverage, 12545,
     /*  568212 */     GIR_EraseRootFromParent_Done,
     /*  568213 */   // Label 8700: @568213
     /*  568213 */   GIM_Try, /*On fail goto*//*Label 8701*/ GIMT_Encode4(568270), // Rule ID 12546 //
     /*  568218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  568221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568239 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568247 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568268 */     GIR_RootConstrainSelectedInstOperands,
     /*  568269 */     // GIR_Coverage, 12546,
     /*  568269 */     GIR_EraseRootFromParent_Done,
     /*  568270 */   // Label 8701: @568270
     /*  568270 */   GIM_Try, /*On fail goto*//*Label 8702*/ GIMT_Encode4(568327), // Rule ID 12547 //
     /*  568275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  568278 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568296 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568304 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568325 */     GIR_RootConstrainSelectedInstOperands,
     /*  568326 */     // GIR_Coverage, 12547,
     /*  568326 */     GIR_EraseRootFromParent_Done,
     /*  568327 */   // Label 8702: @568327
     /*  568327 */   GIM_Try, /*On fail goto*//*Label 8703*/ GIMT_Encode4(568384), // Rule ID 12563 //
     /*  568332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  568335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568353 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568361 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568382 */     GIR_RootConstrainSelectedInstOperands,
     /*  568383 */     // GIR_Coverage, 12563,
     /*  568383 */     GIR_EraseRootFromParent_Done,
     /*  568384 */   // Label 8703: @568384
     /*  568384 */   GIM_Try, /*On fail goto*//*Label 8704*/ GIMT_Encode4(568441), // Rule ID 12564 //
     /*  568389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  568392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568410 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568418 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568439 */     GIR_RootConstrainSelectedInstOperands,
     /*  568440 */     // GIR_Coverage, 12564,
     /*  568440 */     GIR_EraseRootFromParent_Done,
     /*  568441 */   // Label 8704: @568441
     /*  568441 */   GIM_Try, /*On fail goto*//*Label 8705*/ GIMT_Encode4(568498), // Rule ID 12565 //
     /*  568446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  568449 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568467 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568475 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568492 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568496 */     GIR_RootConstrainSelectedInstOperands,
     /*  568497 */     // GIR_Coverage, 12565,
     /*  568497 */     GIR_EraseRootFromParent_Done,
     /*  568498 */   // Label 8705: @568498
     /*  568498 */   GIM_Try, /*On fail goto*//*Label 8706*/ GIMT_Encode4(568555), // Rule ID 12566 //
     /*  568503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  568506 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568524 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568532 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568553 */     GIR_RootConstrainSelectedInstOperands,
     /*  568554 */     // GIR_Coverage, 12566,
     /*  568554 */     GIR_EraseRootFromParent_Done,
     /*  568555 */   // Label 8706: @568555
     /*  568555 */   GIM_Try, /*On fail goto*//*Label 8707*/ GIMT_Encode4(568612), // Rule ID 12567 //
     /*  568560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  568563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  568581 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  568581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
     /*  568584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  568589 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  568596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  568601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  568606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568610 */     GIR_RootConstrainSelectedInstOperands,
     /*  568611 */     // GIR_Coverage, 12567,
     /*  568611 */     GIR_EraseRootFromParent_Done,
     /*  568612 */   // Label 8707: @568612
     /*  568612 */   GIM_Try, /*On fail goto*//*Label 8708*/ GIMT_Encode4(568662), // Rule ID 12538 //
     /*  568617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  568620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568638 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568646 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568656 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568660 */     GIR_RootConstrainSelectedInstOperands,
     /*  568661 */     // GIR_Coverage, 12538,
     /*  568661 */     GIR_EraseRootFromParent_Done,
     /*  568662 */   // Label 8708: @568662
     /*  568662 */   GIM_Try, /*On fail goto*//*Label 8709*/ GIMT_Encode4(568712), // Rule ID 12539 //
     /*  568667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  568670 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568688 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568696 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568710 */     GIR_RootConstrainSelectedInstOperands,
     /*  568711 */     // GIR_Coverage, 12539,
     /*  568711 */     GIR_EraseRootFromParent_Done,
     /*  568712 */   // Label 8709: @568712
     /*  568712 */   GIM_Try, /*On fail goto*//*Label 8710*/ GIMT_Encode4(568762), // Rule ID 12540 //
     /*  568717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  568720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568738 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568746 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568760 */     GIR_RootConstrainSelectedInstOperands,
     /*  568761 */     // GIR_Coverage, 12540,
     /*  568761 */     GIR_EraseRootFromParent_Done,
     /*  568762 */   // Label 8710: @568762
     /*  568762 */   GIM_Try, /*On fail goto*//*Label 8711*/ GIMT_Encode4(568812), // Rule ID 12541 //
     /*  568767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  568770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568788 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568796 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568810 */     GIR_RootConstrainSelectedInstOperands,
     /*  568811 */     // GIR_Coverage, 12541,
     /*  568811 */     GIR_EraseRootFromParent_Done,
     /*  568812 */   // Label 8711: @568812
     /*  568812 */   GIM_Try, /*On fail goto*//*Label 8712*/ GIMT_Encode4(568862), // Rule ID 12542 //
     /*  568817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  568820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568838 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568846 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568860 */     GIR_RootConstrainSelectedInstOperands,
     /*  568861 */     // GIR_Coverage, 12542,
     /*  568861 */     GIR_EraseRootFromParent_Done,
     /*  568862 */   // Label 8712: @568862
     /*  568862 */   GIM_Try, /*On fail goto*//*Label 8713*/ GIMT_Encode4(568912), // Rule ID 12558 //
     /*  568867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  568870 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568888 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568896 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568910 */     GIR_RootConstrainSelectedInstOperands,
     /*  568911 */     // GIR_Coverage, 12558,
     /*  568911 */     GIR_EraseRootFromParent_Done,
     /*  568912 */   // Label 8713: @568912
     /*  568912 */   GIM_Try, /*On fail goto*//*Label 8714*/ GIMT_Encode4(568962), // Rule ID 12559 //
     /*  568917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  568920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568938 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568946 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  568953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  568956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  568960 */     GIR_RootConstrainSelectedInstOperands,
     /*  568961 */     // GIR_Coverage, 12559,
     /*  568961 */     GIR_EraseRootFromParent_Done,
     /*  568962 */   // Label 8714: @568962
     /*  568962 */   GIM_Try, /*On fail goto*//*Label 8715*/ GIMT_Encode4(569012), // Rule ID 12560 //
     /*  568967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  568970 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  568977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  568981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  568988 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  568988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  568991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  568996 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  568998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569010 */     GIR_RootConstrainSelectedInstOperands,
     /*  569011 */     // GIR_Coverage, 12560,
     /*  569011 */     GIR_EraseRootFromParent_Done,
     /*  569012 */   // Label 8715: @569012
     /*  569012 */   GIM_Try, /*On fail goto*//*Label 8716*/ GIMT_Encode4(569062), // Rule ID 12561 //
     /*  569017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  569020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  569027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  569038 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  569041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569046 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569060 */     GIR_RootConstrainSelectedInstOperands,
     /*  569061 */     // GIR_Coverage, 12561,
     /*  569061 */     GIR_EraseRootFromParent_Done,
     /*  569062 */   // Label 8716: @569062
     /*  569062 */   GIM_Try, /*On fail goto*//*Label 8717*/ GIMT_Encode4(569112), // Rule ID 12562 //
     /*  569067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  569070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  569077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  569088 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
     /*  569091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569096 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569110 */     GIR_RootConstrainSelectedInstOperands,
     /*  569111 */     // GIR_Coverage, 12562,
     /*  569111 */     GIR_EraseRootFromParent_Done,
     /*  569112 */   // Label 8717: @569112
     /*  569112 */   GIM_Try, /*On fail goto*//*Label 8718*/ GIMT_Encode4(569168), // Rule ID 10401 //
     /*  569117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  569120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569137 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569145 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569162 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569166 */     GIR_RootConstrainSelectedInstOperands,
     /*  569167 */     // GIR_Coverage, 10401,
     /*  569167 */     GIR_EraseRootFromParent_Done,
     /*  569168 */   // Label 8718: @569168
     /*  569168 */   GIM_Try, /*On fail goto*//*Label 8719*/ GIMT_Encode4(569224), // Rule ID 10402 //
     /*  569173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  569176 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569193 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569201 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569222 */     GIR_RootConstrainSelectedInstOperands,
     /*  569223 */     // GIR_Coverage, 10402,
     /*  569223 */     GIR_EraseRootFromParent_Done,
     /*  569224 */   // Label 8719: @569224
     /*  569224 */   GIM_Try, /*On fail goto*//*Label 8720*/ GIMT_Encode4(569280), // Rule ID 10403 //
     /*  569229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  569232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569238 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569242 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569249 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569257 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569278 */     GIR_RootConstrainSelectedInstOperands,
     /*  569279 */     // GIR_Coverage, 10403,
     /*  569279 */     GIR_EraseRootFromParent_Done,
     /*  569280 */   // Label 8720: @569280
     /*  569280 */   GIM_Try, /*On fail goto*//*Label 8721*/ GIMT_Encode4(569336), // Rule ID 10404 //
     /*  569285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  569288 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569305 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569313 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569334 */     GIR_RootConstrainSelectedInstOperands,
     /*  569335 */     // GIR_Coverage, 10404,
     /*  569335 */     GIR_EraseRootFromParent_Done,
     /*  569336 */   // Label 8721: @569336
     /*  569336 */   GIM_Try, /*On fail goto*//*Label 8722*/ GIMT_Encode4(569392), // Rule ID 10405 //
     /*  569341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  569344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569361 */     // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569369 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569390 */     GIR_RootConstrainSelectedInstOperands,
     /*  569391 */     // GIR_Coverage, 10405,
     /*  569391 */     GIR_EraseRootFromParent_Done,
     /*  569392 */   // Label 8722: @569392
     /*  569392 */   GIM_Try, /*On fail goto*//*Label 8723*/ GIMT_Encode4(569448), // Rule ID 10421 //
     /*  569397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode0),
     /*  569400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569417 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569425 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569446 */     GIR_RootConstrainSelectedInstOperands,
     /*  569447 */     // GIR_Coverage, 10421,
     /*  569447 */     GIR_EraseRootFromParent_Done,
     /*  569448 */   // Label 8723: @569448
     /*  569448 */   GIM_Try, /*On fail goto*//*Label 8724*/ GIMT_Encode4(569504), // Rule ID 10422 //
     /*  569453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode1),
     /*  569456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569466 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569473 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569481 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569502 */     GIR_RootConstrainSelectedInstOperands,
     /*  569503 */     // GIR_Coverage, 10422,
     /*  569503 */     GIR_EraseRootFromParent_Done,
     /*  569504 */   // Label 8724: @569504
     /*  569504 */   GIM_Try, /*On fail goto*//*Label 8725*/ GIMT_Encode4(569560), // Rule ID 10423 //
     /*  569509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode2),
     /*  569512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569529 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569537 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569558 */     GIR_RootConstrainSelectedInstOperands,
     /*  569559 */     // GIR_Coverage, 10423,
     /*  569559 */     GIR_EraseRootFromParent_Done,
     /*  569560 */   // Label 8725: @569560
     /*  569560 */   GIM_Try, /*On fail goto*//*Label 8726*/ GIMT_Encode4(569616), // Rule ID 10424 //
     /*  569565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode3),
     /*  569568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569574 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569578 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569585 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569593 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569614 */     GIR_RootConstrainSelectedInstOperands,
     /*  569615 */     // GIR_Coverage, 10424,
     /*  569615 */     GIR_EraseRootFromParent_Done,
     /*  569616 */   // Label 8726: @569616
     /*  569616 */   GIM_Try, /*On fail goto*//*Label 8727*/ GIMT_Encode4(569672), // Rule ID 10425 //
     /*  569621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_HwMode4),
     /*  569624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569630 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  569641 */     // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  569641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4_SADDR),
     /*  569644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  569649 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  569656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  569661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  569666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569670 */     GIR_RootConstrainSelectedInstOperands,
     /*  569671 */     // GIR_Coverage, 10425,
     /*  569671 */     GIR_EraseRootFromParent_Done,
     /*  569672 */   // Label 8727: @569672
     /*  569672 */   GIM_Try, /*On fail goto*//*Label 8728*/ GIMT_Encode4(569721), // Rule ID 10396 //
     /*  569677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  569680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569697 */     // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569705 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569719 */     GIR_RootConstrainSelectedInstOperands,
     /*  569720 */     // GIR_Coverage, 10396,
     /*  569720 */     GIR_EraseRootFromParent_Done,
     /*  569721 */   // Label 8728: @569721
     /*  569721 */   GIM_Try, /*On fail goto*//*Label 8729*/ GIMT_Encode4(569770), // Rule ID 10397 //
     /*  569726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  569729 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569735 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569746 */     // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569754 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569764 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569768 */     GIR_RootConstrainSelectedInstOperands,
     /*  569769 */     // GIR_Coverage, 10397,
     /*  569769 */     GIR_EraseRootFromParent_Done,
     /*  569770 */   // Label 8729: @569770
     /*  569770 */   GIM_Try, /*On fail goto*//*Label 8730*/ GIMT_Encode4(569819), // Rule ID 10398 //
     /*  569775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  569778 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569795 */     // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569803 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569817 */     GIR_RootConstrainSelectedInstOperands,
     /*  569818 */     // GIR_Coverage, 10398,
     /*  569818 */     GIR_EraseRootFromParent_Done,
     /*  569819 */   // Label 8730: @569819
     /*  569819 */   GIM_Try, /*On fail goto*//*Label 8731*/ GIMT_Encode4(569868), // Rule ID 10399 //
     /*  569824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  569827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569833 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569837 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569844 */     // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569852 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569866 */     GIR_RootConstrainSelectedInstOperands,
     /*  569867 */     // GIR_Coverage, 10399,
     /*  569867 */     GIR_EraseRootFromParent_Done,
     /*  569868 */   // Label 8731: @569868
     /*  569868 */   GIM_Try, /*On fail goto*//*Label 8732*/ GIMT_Encode4(569917), // Rule ID 10400 //
     /*  569873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  569876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569882 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569886 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569893 */     // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569901 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569915 */     GIR_RootConstrainSelectedInstOperands,
     /*  569916 */     // GIR_Coverage, 10400,
     /*  569916 */     GIR_EraseRootFromParent_Done,
     /*  569917 */   // Label 8732: @569917
     /*  569917 */   GIM_Try, /*On fail goto*//*Label 8733*/ GIMT_Encode4(569966), // Rule ID 10416 //
     /*  569922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  569925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569942 */     // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569950 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  569952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  569957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  569960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  569964 */     GIR_RootConstrainSelectedInstOperands,
     /*  569965 */     // GIR_Coverage, 10416,
     /*  569965 */     GIR_EraseRootFromParent_Done,
     /*  569966 */   // Label 8733: @569966
     /*  569966 */   GIM_Try, /*On fail goto*//*Label 8734*/ GIMT_Encode4(570015), // Rule ID 10417 //
     /*  569971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  569974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  569980 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  569984 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  569991 */     // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  569991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  569994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  569999 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  570001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570013 */     GIR_RootConstrainSelectedInstOperands,
     /*  570014 */     // GIR_Coverage, 10417,
     /*  570014 */     GIR_EraseRootFromParent_Done,
     /*  570015 */   // Label 8734: @570015
     /*  570015 */   GIM_Try, /*On fail goto*//*Label 8735*/ GIMT_Encode4(570064), // Rule ID 10418 //
     /*  570020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  570023 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  570029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  570040 */     // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  570040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  570043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  570048 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  570050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570062 */     GIR_RootConstrainSelectedInstOperands,
     /*  570063 */     // GIR_Coverage, 10418,
     /*  570063 */     GIR_EraseRootFromParent_Done,
     /*  570064 */   // Label 8735: @570064
     /*  570064 */   GIM_Try, /*On fail goto*//*Label 8736*/ GIMT_Encode4(570113), // Rule ID 10419 //
     /*  570069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  570072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  570078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  570089 */     // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  570089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  570092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  570097 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  570099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570111 */     GIR_RootConstrainSelectedInstOperands,
     /*  570112 */     // GIR_Coverage, 10419,
     /*  570112 */     GIR_EraseRootFromParent_Done,
     /*  570113 */   // Label 8736: @570113
     /*  570113 */   GIM_Try, /*On fail goto*//*Label 8737*/ GIMT_Encode4(570162), // Rule ID 10420 //
     /*  570118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  570121 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
     /*  570127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  570138 */     // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15621:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  570138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
     /*  570141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  570146 */     GIR_RootToRootCopy, /*OpIdx*/0, // data
     /*  570148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570160 */     GIR_RootConstrainSelectedInstOperands,
     /*  570161 */     // GIR_Coverage, 10420,
     /*  570161 */     GIR_EraseRootFromParent_Done,
     /*  570162 */   // Label 8737: @570162
     /*  570162 */   GIM_Reject,
     /*  570163 */ // Label 8567: @570163
     /*  570163 */ GIM_Reject,
     /*  570164 */ // Label 5875: @570164
     /*  570164 */ GIM_Reject,
     /*  570165 */ // Label 18: @570165
     /*  570165 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 8740*/ GIMT_Encode4(573450),
     /*  570176 */ /*GILLT_s32*//*Label 8738*/ GIMT_Encode4(570184),
     /*  570180 */ /*GILLT_s64*//*Label 8739*/ GIMT_Encode4(570737),
     /*  570184 */ // Label 8738: @570184
     /*  570184 */ GIM_Try, /*On fail goto*//*Label 8741*/ GIMT_Encode4(570736),
     /*  570189 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  570192 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  570195 */   GIM_Try, /*On fail goto*//*Label 8742*/ GIMT_Encode4(570247), // Rule ID 30284 //
     /*  570200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
     /*  570203 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570208 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570221 */     // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i32>>  =>  (DS_CMPST_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$cmp, anonymous_15624:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32),
     /*  570224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570229 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570231 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570241 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570245 */     GIR_RootConstrainSelectedInstOperands,
     /*  570246 */     // GIR_Coverage, 30284,
     /*  570246 */     GIR_EraseRootFromParent_Done,
     /*  570247 */   // Label 8742: @570247
     /*  570247 */   GIM_Try, /*On fail goto*//*Label 8743*/ GIMT_Encode4(570299), // Rule ID 30286 //
     /*  570252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
     /*  570255 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570260 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570266 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570273 */     // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i32>>  =>  (DS_CMPST_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$cmp, anonymous_15624:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32_gfx9),
     /*  570276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570281 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570283 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570293 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570297 */     GIR_RootConstrainSelectedInstOperands,
     /*  570298 */     // GIR_Coverage, 30286,
     /*  570298 */     GIR_EraseRootFromParent_Done,
     /*  570299 */   // Label 8743: @570299
     /*  570299 */   GIM_Try, /*On fail goto*//*Label 8744*/ GIMT_Encode4(570351), // Rule ID 30288 //
     /*  570304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10),
     /*  570307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  570312 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570314 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570318 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570325 */     // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i32>>  =>  (DS_CMPST_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$cmp, anonymous_15624:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  570325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32),
     /*  570328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570333 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570335 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  570345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570349 */     GIR_RootConstrainSelectedInstOperands,
     /*  570350 */     // GIR_Coverage, 30288,
     /*  570350 */     GIR_EraseRootFromParent_Done,
     /*  570351 */   // Label 8744: @570351
     /*  570351 */   GIM_Try, /*On fail goto*//*Label 8745*/ GIMT_Encode4(570403), // Rule ID 30290 //
     /*  570356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*  570359 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570364 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570377 */     // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i32>>  =>  (DS_CMPSTORE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$swap, anonymous_15624:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B32_gfx9),
     /*  570380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570385 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570387 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570401 */     GIR_RootConstrainSelectedInstOperands,
     /*  570402 */     // GIR_Coverage, 30290,
     /*  570402 */     GIR_EraseRootFromParent_Done,
     /*  570403 */   // Label 8745: @570403
     /*  570403 */   GIM_Try, /*On fail goto*//*Label 8746*/ GIMT_Encode4(570455), // Rule ID 30292 //
     /*  570408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus),
     /*  570411 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  570416 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570429 */     // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i32>>  =>  (DS_CMPSTORE_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$swap, anonymous_15624:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  570429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B32),
     /*  570432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570437 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570439 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570446 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  570449 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570453 */     GIR_RootConstrainSelectedInstOperands,
     /*  570454 */     // GIR_Coverage, 30292,
     /*  570454 */     GIR_EraseRootFromParent_Done,
     /*  570455 */   // Label 8746: @570455
     /*  570455 */   GIM_Try, /*On fail goto*//*Label 8747*/ GIMT_Encode4(570511), // Rule ID 30283 //
     /*  570460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
     /*  570463 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  570472 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570476 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570483 */     // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i32>>  =>  (DS_CMPST_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$cmp, anonymous_15624:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32),
     /*  570486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  570488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570493 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570495 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570509 */     GIR_RootConstrainSelectedInstOperands,
     /*  570510 */     // GIR_Coverage, 30283,
     /*  570510 */     GIR_EraseRootFromParent_Done,
     /*  570511 */   // Label 8747: @570511
     /*  570511 */   GIM_Try, /*On fail goto*//*Label 8748*/ GIMT_Encode4(570567), // Rule ID 30285 //
     /*  570516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
     /*  570519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  570528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570539 */     // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i32>>  =>  (DS_CMPST_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$cmp, anonymous_15624:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32_gfx9),
     /*  570542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  570544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570549 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570551 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570561 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570565 */     GIR_RootConstrainSelectedInstOperands,
     /*  570566 */     // GIR_Coverage, 30285,
     /*  570566 */     GIR_EraseRootFromParent_Done,
     /*  570567 */   // Label 8748: @570567
     /*  570567 */   GIM_Try, /*On fail goto*//*Label 8749*/ GIMT_Encode4(570623), // Rule ID 30287 //
     /*  570572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10),
     /*  570575 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  570580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  570584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570595 */     // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i32>>  =>  (DS_CMPST_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$cmp, anonymous_15624:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  570595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32),
     /*  570598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  570600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570605 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570607 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  570617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570621 */     GIR_RootConstrainSelectedInstOperands,
     /*  570622 */     // GIR_Coverage, 30287,
     /*  570622 */     GIR_EraseRootFromParent_Done,
     /*  570623 */   // Label 8749: @570623
     /*  570623 */   GIM_Try, /*On fail goto*//*Label 8750*/ GIMT_Encode4(570679), // Rule ID 30289 //
     /*  570628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*  570631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  570640 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570651 */     // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i32>>  =>  (DS_CMPSTORE_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$swap, anonymous_15624:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B32_gfx9),
     /*  570654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  570656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570661 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570663 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570677 */     GIR_RootConstrainSelectedInstOperands,
     /*  570678 */     // GIR_Coverage, 30289,
     /*  570678 */     GIR_EraseRootFromParent_Done,
     /*  570679 */   // Label 8750: @570679
     /*  570679 */   GIM_Try, /*On fail goto*//*Label 8751*/ GIMT_Encode4(570735), // Rule ID 30291 //
     /*  570684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus),
     /*  570687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  570692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  570696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570707 */     // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i32>>  =>  (DS_CMPSTORE_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$swap, anonymous_15624:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  570707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B32),
     /*  570710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  570712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570717 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570719 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  570729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570733 */     GIR_RootConstrainSelectedInstOperands,
     /*  570734 */     // GIR_Coverage, 30291,
     /*  570734 */     GIR_EraseRootFromParent_Done,
     /*  570735 */   // Label 8751: @570735
     /*  570735 */   GIM_Reject,
     /*  570736 */ // Label 8741: @570736
     /*  570736 */ GIM_Reject,
     /*  570737 */ // Label 8739: @570737
     /*  570737 */ GIM_Try, /*On fail goto*//*Label 8752*/ GIMT_Encode4(573449),
     /*  570742 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  570745 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  570748 */   GIM_Try, /*On fail goto*//*Label 8753*/ GIMT_Encode4(570800), // Rule ID 30955 //
     /*  570753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode0),
     /*  570756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570761 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570774 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  570777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570782 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570784 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570798 */     GIR_RootConstrainSelectedInstOperands,
     /*  570799 */     // GIR_Coverage, 30955,
     /*  570799 */     GIR_EraseRootFromParent_Done,
     /*  570800 */   // Label 8753: @570800
     /*  570800 */   GIM_Try, /*On fail goto*//*Label 8754*/ GIMT_Encode4(570852), // Rule ID 30956 //
     /*  570805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode1),
     /*  570808 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570813 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570826 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  570829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570834 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570836 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570850 */     GIR_RootConstrainSelectedInstOperands,
     /*  570851 */     // GIR_Coverage, 30956,
     /*  570851 */     GIR_EraseRootFromParent_Done,
     /*  570852 */   // Label 8754: @570852
     /*  570852 */   GIM_Try, /*On fail goto*//*Label 8755*/ GIMT_Encode4(570904), // Rule ID 30957 //
     /*  570857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode2),
     /*  570860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570865 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570878 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  570881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570886 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570888 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570902 */     GIR_RootConstrainSelectedInstOperands,
     /*  570903 */     // GIR_Coverage, 30957,
     /*  570903 */     GIR_EraseRootFromParent_Done,
     /*  570904 */   // Label 8755: @570904
     /*  570904 */   GIM_Try, /*On fail goto*//*Label 8756*/ GIMT_Encode4(570956), // Rule ID 30958 //
     /*  570909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode3),
     /*  570912 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570917 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570930 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  570933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570938 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570940 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  570950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  570954 */     GIR_RootConstrainSelectedInstOperands,
     /*  570955 */     // GIR_Coverage, 30958,
     /*  570955 */     GIR_EraseRootFromParent_Done,
     /*  570956 */   // Label 8756: @570956
     /*  570956 */   GIM_Try, /*On fail goto*//*Label 8757*/ GIMT_Encode4(571008), // Rule ID 30959 //
     /*  570961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode4),
     /*  570964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  570969 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  570971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  570975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  570982 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  570982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  570985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  570990 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  570992 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  570994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  570999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571006 */     GIR_RootConstrainSelectedInstOperands,
     /*  571007 */     // GIR_Coverage, 30959,
     /*  571007 */     GIR_EraseRootFromParent_Done,
     /*  571008 */   // Label 8757: @571008
     /*  571008 */   GIM_Try, /*On fail goto*//*Label 8758*/ GIMT_Encode4(571060), // Rule ID 30965 //
     /*  571013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode0),
     /*  571016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571021 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571034 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9),
     /*  571037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571042 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571044 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571058 */     GIR_RootConstrainSelectedInstOperands,
     /*  571059 */     // GIR_Coverage, 30965,
     /*  571059 */     GIR_EraseRootFromParent_Done,
     /*  571060 */   // Label 8758: @571060
     /*  571060 */   GIM_Try, /*On fail goto*//*Label 8759*/ GIMT_Encode4(571112), // Rule ID 30966 //
     /*  571065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode1),
     /*  571068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571073 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571086 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9),
     /*  571089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571094 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571096 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571110 */     GIR_RootConstrainSelectedInstOperands,
     /*  571111 */     // GIR_Coverage, 30966,
     /*  571111 */     GIR_EraseRootFromParent_Done,
     /*  571112 */   // Label 8759: @571112
     /*  571112 */   GIM_Try, /*On fail goto*//*Label 8760*/ GIMT_Encode4(571164), // Rule ID 30967 //
     /*  571117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode2),
     /*  571120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571125 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571138 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9),
     /*  571141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571146 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571148 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571162 */     GIR_RootConstrainSelectedInstOperands,
     /*  571163 */     // GIR_Coverage, 30967,
     /*  571163 */     GIR_EraseRootFromParent_Done,
     /*  571164 */   // Label 8760: @571164
     /*  571164 */   GIM_Try, /*On fail goto*//*Label 8761*/ GIMT_Encode4(571216), // Rule ID 30968 //
     /*  571169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode3),
     /*  571172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571177 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571190 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9),
     /*  571193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571198 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571200 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571214 */     GIR_RootConstrainSelectedInstOperands,
     /*  571215 */     // GIR_Coverage, 30968,
     /*  571215 */     GIR_EraseRootFromParent_Done,
     /*  571216 */   // Label 8761: @571216
     /*  571216 */   GIM_Try, /*On fail goto*//*Label 8762*/ GIMT_Encode4(571268), // Rule ID 30969 //
     /*  571221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode4),
     /*  571224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571229 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571242 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9),
     /*  571245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571250 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571252 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571266 */     GIR_RootConstrainSelectedInstOperands,
     /*  571267 */     // GIR_Coverage, 30969,
     /*  571267 */     GIR_EraseRootFromParent_Done,
     /*  571268 */   // Label 8762: @571268
     /*  571268 */   GIM_Try, /*On fail goto*//*Label 8763*/ GIMT_Encode4(571320), // Rule ID 30975 //
     /*  571273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode0),
     /*  571276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571281 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571294 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  571297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571302 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571304 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571318 */     GIR_RootConstrainSelectedInstOperands,
     /*  571319 */     // GIR_Coverage, 30975,
     /*  571319 */     GIR_EraseRootFromParent_Done,
     /*  571320 */   // Label 8763: @571320
     /*  571320 */   GIM_Try, /*On fail goto*//*Label 8764*/ GIMT_Encode4(571372), // Rule ID 30976 //
     /*  571325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode1),
     /*  571328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571333 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571346 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  571349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571354 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571356 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571370 */     GIR_RootConstrainSelectedInstOperands,
     /*  571371 */     // GIR_Coverage, 30976,
     /*  571371 */     GIR_EraseRootFromParent_Done,
     /*  571372 */   // Label 8764: @571372
     /*  571372 */   GIM_Try, /*On fail goto*//*Label 8765*/ GIMT_Encode4(571424), // Rule ID 30977 //
     /*  571377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode2),
     /*  571380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571385 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571398 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  571401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571406 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571408 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571422 */     GIR_RootConstrainSelectedInstOperands,
     /*  571423 */     // GIR_Coverage, 30977,
     /*  571423 */     GIR_EraseRootFromParent_Done,
     /*  571424 */   // Label 8765: @571424
     /*  571424 */   GIM_Try, /*On fail goto*//*Label 8766*/ GIMT_Encode4(571476), // Rule ID 30978 //
     /*  571429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode3),
     /*  571432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571437 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571443 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571450 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  571453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571458 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571460 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571474 */     GIR_RootConstrainSelectedInstOperands,
     /*  571475 */     // GIR_Coverage, 30978,
     /*  571475 */     GIR_EraseRootFromParent_Done,
     /*  571476 */   // Label 8766: @571476
     /*  571476 */   GIM_Try, /*On fail goto*//*Label 8767*/ GIMT_Encode4(571528), // Rule ID 30979 //
     /*  571481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode4),
     /*  571484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571489 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571502 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
     /*  571505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571510 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571512 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571526 */     GIR_RootConstrainSelectedInstOperands,
     /*  571527 */     // GIR_Coverage, 30979,
     /*  571527 */     GIR_EraseRootFromParent_Done,
     /*  571528 */   // Label 8767: @571528
     /*  571528 */   GIM_Try, /*On fail goto*//*Label 8768*/ GIMT_Encode4(571580), // Rule ID 30985 //
     /*  571533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode0),
     /*  571536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571541 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571554 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9),
     /*  571557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571562 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571564 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571578 */     GIR_RootConstrainSelectedInstOperands,
     /*  571579 */     // GIR_Coverage, 30985,
     /*  571579 */     GIR_EraseRootFromParent_Done,
     /*  571580 */   // Label 8768: @571580
     /*  571580 */   GIM_Try, /*On fail goto*//*Label 8769*/ GIMT_Encode4(571632), // Rule ID 30986 //
     /*  571585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode1),
     /*  571588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571593 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571606 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9),
     /*  571609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571614 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571616 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571630 */     GIR_RootConstrainSelectedInstOperands,
     /*  571631 */     // GIR_Coverage, 30986,
     /*  571631 */     GIR_EraseRootFromParent_Done,
     /*  571632 */   // Label 8769: @571632
     /*  571632 */   GIM_Try, /*On fail goto*//*Label 8770*/ GIMT_Encode4(571684), // Rule ID 30987 //
     /*  571637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode2),
     /*  571640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571645 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571658 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9),
     /*  571661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571666 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571668 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571682 */     GIR_RootConstrainSelectedInstOperands,
     /*  571683 */     // GIR_Coverage, 30987,
     /*  571683 */     GIR_EraseRootFromParent_Done,
     /*  571684 */   // Label 8770: @571684
     /*  571684 */   GIM_Try, /*On fail goto*//*Label 8771*/ GIMT_Encode4(571736), // Rule ID 30988 //
     /*  571689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode3),
     /*  571692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571697 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571710 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9),
     /*  571713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571718 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571720 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571734 */     GIR_RootConstrainSelectedInstOperands,
     /*  571735 */     // GIR_Coverage, 30988,
     /*  571735 */     GIR_EraseRootFromParent_Done,
     /*  571736 */   // Label 8771: @571736
     /*  571736 */   GIM_Try, /*On fail goto*//*Label 8772*/ GIMT_Encode4(571788), // Rule ID 30989 //
     /*  571741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode4),
     /*  571744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  571749 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571762 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>>  =>  (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  571762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9),
     /*  571765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571770 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571772 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  571782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571786 */     GIR_RootConstrainSelectedInstOperands,
     /*  571787 */     // GIR_Coverage, 30989,
     /*  571787 */     GIR_EraseRootFromParent_Done,
     /*  571788 */   // Label 8772: @571788
     /*  571788 */   GIM_Try, /*On fail goto*//*Label 8773*/ GIMT_Encode4(571840), // Rule ID 30995 //
     /*  571793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode0),
     /*  571796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571801 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571814 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64),
     /*  571817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571822 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571824 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571838 */     GIR_RootConstrainSelectedInstOperands,
     /*  571839 */     // GIR_Coverage, 30995,
     /*  571839 */     GIR_EraseRootFromParent_Done,
     /*  571840 */   // Label 8773: @571840
     /*  571840 */   GIM_Try, /*On fail goto*//*Label 8774*/ GIMT_Encode4(571892), // Rule ID 30996 //
     /*  571845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode1),
     /*  571848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571853 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571866 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64),
     /*  571869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571874 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571876 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571886 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571890 */     GIR_RootConstrainSelectedInstOperands,
     /*  571891 */     // GIR_Coverage, 30996,
     /*  571891 */     GIR_EraseRootFromParent_Done,
     /*  571892 */   // Label 8774: @571892
     /*  571892 */   GIM_Try, /*On fail goto*//*Label 8775*/ GIMT_Encode4(571944), // Rule ID 30997 //
     /*  571897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode2),
     /*  571900 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571905 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571918 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64),
     /*  571921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571926 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571928 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571942 */     GIR_RootConstrainSelectedInstOperands,
     /*  571943 */     // GIR_Coverage, 30997,
     /*  571943 */     GIR_EraseRootFromParent_Done,
     /*  571944 */   // Label 8775: @571944
     /*  571944 */   GIM_Try, /*On fail goto*//*Label 8776*/ GIMT_Encode4(571996), // Rule ID 30998 //
     /*  571949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode3),
     /*  571952 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  571957 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  571959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  571963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  571970 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  571970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64),
     /*  571973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  571978 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  571980 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  571982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  571987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  571990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  571994 */     GIR_RootConstrainSelectedInstOperands,
     /*  571995 */     // GIR_Coverage, 30998,
     /*  571995 */     GIR_EraseRootFromParent_Done,
     /*  571996 */   // Label 8776: @571996
     /*  571996 */   GIM_Try, /*On fail goto*//*Label 8777*/ GIMT_Encode4(572048), // Rule ID 30999 //
     /*  572001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode4),
     /*  572004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  572009 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  572011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572022 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>>  =>  (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  572022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64),
     /*  572025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572030 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572032 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  572042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572046 */     GIR_RootConstrainSelectedInstOperands,
     /*  572047 */     // GIR_Coverage, 30999,
     /*  572047 */     GIR_EraseRootFromParent_Done,
     /*  572048 */   // Label 8777: @572048
     /*  572048 */   GIM_Try, /*On fail goto*//*Label 8778*/ GIMT_Encode4(572104), // Rule ID 30950 //
     /*  572053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode0),
     /*  572056 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572076 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572086 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572088 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572102 */     GIR_RootConstrainSelectedInstOperands,
     /*  572103 */     // GIR_Coverage, 30950,
     /*  572103 */     GIR_EraseRootFromParent_Done,
     /*  572104 */   // Label 8778: @572104
     /*  572104 */   GIM_Try, /*On fail goto*//*Label 8779*/ GIMT_Encode4(572160), // Rule ID 30951 //
     /*  572109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode1),
     /*  572112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572132 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572142 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572144 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572158 */     GIR_RootConstrainSelectedInstOperands,
     /*  572159 */     // GIR_Coverage, 30951,
     /*  572159 */     GIR_EraseRootFromParent_Done,
     /*  572160 */   // Label 8779: @572160
     /*  572160 */   GIM_Try, /*On fail goto*//*Label 8780*/ GIMT_Encode4(572216), // Rule ID 30952 //
     /*  572165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode2),
     /*  572168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572188 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572198 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572200 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572214 */     GIR_RootConstrainSelectedInstOperands,
     /*  572215 */     // GIR_Coverage, 30952,
     /*  572215 */     GIR_EraseRootFromParent_Done,
     /*  572216 */   // Label 8780: @572216
     /*  572216 */   GIM_Try, /*On fail goto*//*Label 8781*/ GIMT_Encode4(572272), // Rule ID 30953 //
     /*  572221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode3),
     /*  572224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572244 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572254 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572256 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572270 */     GIR_RootConstrainSelectedInstOperands,
     /*  572271 */     // GIR_Coverage, 30953,
     /*  572271 */     GIR_EraseRootFromParent_Done,
     /*  572272 */   // Label 8781: @572272
     /*  572272 */   GIM_Try, /*On fail goto*//*Label 8782*/ GIMT_Encode4(572328), // Rule ID 30954 //
     /*  572277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode4),
     /*  572280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572300 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572310 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572312 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572326 */     GIR_RootConstrainSelectedInstOperands,
     /*  572327 */     // GIR_Coverage, 30954,
     /*  572327 */     GIR_EraseRootFromParent_Done,
     /*  572328 */   // Label 8782: @572328
     /*  572328 */   GIM_Try, /*On fail goto*//*Label 8783*/ GIMT_Encode4(572384), // Rule ID 30960 //
     /*  572333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode0),
     /*  572336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572356 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9),
     /*  572359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572366 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572368 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572382 */     GIR_RootConstrainSelectedInstOperands,
     /*  572383 */     // GIR_Coverage, 30960,
     /*  572383 */     GIR_EraseRootFromParent_Done,
     /*  572384 */   // Label 8783: @572384
     /*  572384 */   GIM_Try, /*On fail goto*//*Label 8784*/ GIMT_Encode4(572440), // Rule ID 30961 //
     /*  572389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode1),
     /*  572392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572412 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9),
     /*  572415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572422 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572424 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572438 */     GIR_RootConstrainSelectedInstOperands,
     /*  572439 */     // GIR_Coverage, 30961,
     /*  572439 */     GIR_EraseRootFromParent_Done,
     /*  572440 */   // Label 8784: @572440
     /*  572440 */   GIM_Try, /*On fail goto*//*Label 8785*/ GIMT_Encode4(572496), // Rule ID 30962 //
     /*  572445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode2),
     /*  572448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572468 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9),
     /*  572471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572478 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572480 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572494 */     GIR_RootConstrainSelectedInstOperands,
     /*  572495 */     // GIR_Coverage, 30962,
     /*  572495 */     GIR_EraseRootFromParent_Done,
     /*  572496 */   // Label 8785: @572496
     /*  572496 */   GIM_Try, /*On fail goto*//*Label 8786*/ GIMT_Encode4(572552), // Rule ID 30963 //
     /*  572501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode3),
     /*  572504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572524 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9),
     /*  572527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572534 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572536 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572550 */     GIR_RootConstrainSelectedInstOperands,
     /*  572551 */     // GIR_Coverage, 30963,
     /*  572551 */     GIR_EraseRootFromParent_Done,
     /*  572552 */   // Label 8786: @572552
     /*  572552 */   GIM_Try, /*On fail goto*//*Label 8787*/ GIMT_Encode4(572608), // Rule ID 30964 //
     /*  572557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10_HwMode4),
     /*  572560 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572573 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572580 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9),
     /*  572583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572590 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572592 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572606 */     GIR_RootConstrainSelectedInstOperands,
     /*  572607 */     // GIR_Coverage, 30964,
     /*  572607 */     GIR_EraseRootFromParent_Done,
     /*  572608 */   // Label 8787: @572608
     /*  572608 */   GIM_Try, /*On fail goto*//*Label 8788*/ GIMT_Encode4(572664), // Rule ID 30970 //
     /*  572613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode0),
     /*  572616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  572621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572636 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  572636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572646 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572648 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  572658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572662 */     GIR_RootConstrainSelectedInstOperands,
     /*  572663 */     // GIR_Coverage, 30970,
     /*  572663 */     GIR_EraseRootFromParent_Done,
     /*  572664 */   // Label 8788: @572664
     /*  572664 */   GIM_Try, /*On fail goto*//*Label 8789*/ GIMT_Encode4(572720), // Rule ID 30971 //
     /*  572669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode1),
     /*  572672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  572677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572692 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  572692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572702 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572704 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  572714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572718 */     GIR_RootConstrainSelectedInstOperands,
     /*  572719 */     // GIR_Coverage, 30971,
     /*  572719 */     GIR_EraseRootFromParent_Done,
     /*  572720 */   // Label 8789: @572720
     /*  572720 */   GIM_Try, /*On fail goto*//*Label 8790*/ GIMT_Encode4(572776), // Rule ID 30972 //
     /*  572725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode2),
     /*  572728 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  572733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572748 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  572748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572758 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572760 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  572770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572774 */     GIR_RootConstrainSelectedInstOperands,
     /*  572775 */     // GIR_Coverage, 30972,
     /*  572775 */     GIR_EraseRootFromParent_Done,
     /*  572776 */   // Label 8790: @572776
     /*  572776 */   GIM_Try, /*On fail goto*//*Label 8791*/ GIMT_Encode4(572832), // Rule ID 30973 //
     /*  572781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode3),
     /*  572784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  572789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572804 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  572804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572814 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572816 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  572826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572830 */     GIR_RootConstrainSelectedInstOperands,
     /*  572831 */     // GIR_Coverage, 30973,
     /*  572831 */     GIR_EraseRootFromParent_Done,
     /*  572832 */   // Label 8791: @572832
     /*  572832 */   GIM_Try, /*On fail goto*//*Label 8792*/ GIMT_Encode4(572888), // Rule ID 30974 //
     /*  572837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10_HwMode4),
     /*  572840 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  572845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572860 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$cmp, anonymous_15623:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  572860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
     /*  572863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572870 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572872 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  572882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572886 */     GIR_RootConstrainSelectedInstOperands,
     /*  572887 */     // GIR_Coverage, 30974,
     /*  572887 */     GIR_EraseRootFromParent_Done,
     /*  572888 */   // Label 8792: @572888
     /*  572888 */   GIM_Try, /*On fail goto*//*Label 8793*/ GIMT_Encode4(572944), // Rule ID 30980 //
     /*  572893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode0),
     /*  572896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572916 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9),
     /*  572919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572926 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572928 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572942 */     GIR_RootConstrainSelectedInstOperands,
     /*  572943 */     // GIR_Coverage, 30980,
     /*  572943 */     GIR_EraseRootFromParent_Done,
     /*  572944 */   // Label 8793: @572944
     /*  572944 */   GIM_Try, /*On fail goto*//*Label 8794*/ GIMT_Encode4(573000), // Rule ID 30981 //
     /*  572949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode1),
     /*  572952 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  572957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  572961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  572965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  572972 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  572972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9),
     /*  572975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  572977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  572982 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  572984 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  572986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  572991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  572994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  572998 */     GIR_RootConstrainSelectedInstOperands,
     /*  572999 */     // GIR_Coverage, 30981,
     /*  572999 */     GIR_EraseRootFromParent_Done,
     /*  573000 */   // Label 8794: @573000
     /*  573000 */   GIM_Try, /*On fail goto*//*Label 8795*/ GIMT_Encode4(573056), // Rule ID 30982 //
     /*  573005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode2),
     /*  573008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  573013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573017 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573028 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  573028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9),
     /*  573031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573038 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573040 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573047 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573050 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573054 */     GIR_RootConstrainSelectedInstOperands,
     /*  573055 */     // GIR_Coverage, 30982,
     /*  573055 */     GIR_EraseRootFromParent_Done,
     /*  573056 */   // Label 8795: @573056
     /*  573056 */   GIM_Try, /*On fail goto*//*Label 8796*/ GIMT_Encode4(573112), // Rule ID 30983 //
     /*  573061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode3),
     /*  573064 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  573069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573084 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  573084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9),
     /*  573087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573094 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573096 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573110 */     GIR_RootConstrainSelectedInstOperands,
     /*  573111 */     // GIR_Coverage, 30983,
     /*  573111 */     GIR_EraseRootFromParent_Done,
     /*  573112 */   // Label 8796: @573112
     /*  573112 */   GIM_Try, /*On fail goto*//*Label 8797*/ GIMT_Encode4(573168), // Rule ID 30984 //
     /*  573117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus_HwMode4),
     /*  573120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  573125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573133 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573140 */     // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>>  =>  (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  573140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9),
     /*  573143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573150 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573152 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573159 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573162 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573166 */     GIR_RootConstrainSelectedInstOperands,
     /*  573167 */     // GIR_Coverage, 30984,
     /*  573167 */     GIR_EraseRootFromParent_Done,
     /*  573168 */   // Label 8797: @573168
     /*  573168 */   GIM_Try, /*On fail goto*//*Label 8798*/ GIMT_Encode4(573224), // Rule ID 30990 //
     /*  573173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode0),
     /*  573176 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  573181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573196 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  573196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64),
     /*  573199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573206 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573208 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  573218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573222 */     GIR_RootConstrainSelectedInstOperands,
     /*  573223 */     // GIR_Coverage, 30990,
     /*  573223 */     GIR_EraseRootFromParent_Done,
     /*  573224 */   // Label 8798: @573224
     /*  573224 */   GIM_Try, /*On fail goto*//*Label 8799*/ GIMT_Encode4(573280), // Rule ID 30991 //
     /*  573229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode1),
     /*  573232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  573237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573241 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573252 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  573252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64),
     /*  573255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573262 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573264 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  573274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573278 */     GIR_RootConstrainSelectedInstOperands,
     /*  573279 */     // GIR_Coverage, 30991,
     /*  573279 */     GIR_EraseRootFromParent_Done,
     /*  573280 */   // Label 8799: @573280
     /*  573280 */   GIM_Try, /*On fail goto*//*Label 8800*/ GIMT_Encode4(573336), // Rule ID 30992 //
     /*  573285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode2),
     /*  573288 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  573293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573301 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573308 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  573308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64),
     /*  573311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573318 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573320 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  573330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573334 */     GIR_RootConstrainSelectedInstOperands,
     /*  573335 */     // GIR_Coverage, 30992,
     /*  573335 */     GIR_EraseRootFromParent_Done,
     /*  573336 */   // Label 8800: @573336
     /*  573336 */   GIM_Try, /*On fail goto*//*Label 8801*/ GIMT_Encode4(573392), // Rule ID 30993 //
     /*  573341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode3),
     /*  573344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  573349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573353 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573364 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  573364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64),
     /*  573367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573374 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573376 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  573386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573390 */     GIR_RootConstrainSelectedInstOperands,
     /*  573391 */     // GIR_Coverage, 30993,
     /*  573391 */     GIR_EraseRootFromParent_Done,
     /*  573392 */   // Label 8801: @573392
     /*  573392 */   GIM_Try, /*On fail goto*//*Label 8802*/ GIMT_Encode4(573448), // Rule ID 30994 //
     /*  573397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus_HwMode4),
     /*  573400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  573405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  573409 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  573420 */     // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>>  =>  (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$swap, anonymous_15623:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  573420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64),
     /*  573423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  573425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  573430 */     GIR_RootToRootCopy, /*OpIdx*/3, // swap
     /*  573432 */     GIR_RootToRootCopy, /*OpIdx*/2, // cmp
     /*  573434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  573439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  573442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573446 */     GIR_RootConstrainSelectedInstOperands,
     /*  573447 */     // GIR_Coverage, 30994,
     /*  573447 */     GIR_EraseRootFromParent_Done,
     /*  573448 */   // Label 8802: @573448
     /*  573448 */   GIM_Reject,
     /*  573449 */ // Label 8752: @573449
     /*  573449 */ GIM_Reject,
     /*  573450 */ // Label 8740: @573450
     /*  573450 */ GIM_Reject,
     /*  573451 */ // Label 19: @573451
     /*  573451 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 8805*/ GIMT_Encode4(585562),
     /*  573462 */ /*GILLT_s32*//*Label 8803*/ GIMT_Encode4(573470),
     /*  573466 */ /*GILLT_s64*//*Label 8804*/ GIMT_Encode4(578812),
     /*  573470 */ // Label 8803: @573470
     /*  573470 */ GIM_Try, /*On fail goto*//*Label 8806*/ GIMT_Encode4(578811),
     /*  573475 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  573478 */   GIM_Try, /*On fail goto*//*Label 8807*/ GIMT_Encode4(573540), // Rule ID 20738 //
     /*  573483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  573486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573493 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573506 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64),
     /*  573509 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573538 */     GIR_RootConstrainSelectedInstOperands,
     /*  573539 */     // GIR_Coverage, 20738,
     /*  573539 */     GIR_EraseRootFromParent_Done,
     /*  573540 */   // Label 8807: @573540
     /*  573540 */   GIM_Try, /*On fail goto*//*Label 8808*/ GIMT_Encode4(573602), // Rule ID 20739 //
     /*  573545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  573548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573555 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573568 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64),
     /*  573571 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573600 */     GIR_RootConstrainSelectedInstOperands,
     /*  573601 */     // GIR_Coverage, 20739,
     /*  573601 */     GIR_EraseRootFromParent_Done,
     /*  573602 */   // Label 8808: @573602
     /*  573602 */   GIM_Try, /*On fail goto*//*Label 8809*/ GIMT_Encode4(573664), // Rule ID 20740 //
     /*  573607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  573610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573617 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573630 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64),
     /*  573633 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573662 */     GIR_RootConstrainSelectedInstOperands,
     /*  573663 */     // GIR_Coverage, 20740,
     /*  573663 */     GIR_EraseRootFromParent_Done,
     /*  573664 */   // Label 8809: @573664
     /*  573664 */   GIM_Try, /*On fail goto*//*Label 8810*/ GIMT_Encode4(573726), // Rule ID 20741 //
     /*  573669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  573672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573679 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573692 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64),
     /*  573695 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573724 */     GIR_RootConstrainSelectedInstOperands,
     /*  573725 */     // GIR_Coverage, 20741,
     /*  573725 */     GIR_EraseRootFromParent_Done,
     /*  573726 */   // Label 8810: @573726
     /*  573726 */   GIM_Try, /*On fail goto*//*Label 8811*/ GIMT_Encode4(573788), // Rule ID 20742 //
     /*  573731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  573734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573741 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573754 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64),
     /*  573757 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573786 */     GIR_RootConstrainSelectedInstOperands,
     /*  573787 */     // GIR_Coverage, 20742,
     /*  573787 */     GIR_EraseRootFromParent_Done,
     /*  573788 */   // Label 8811: @573788
     /*  573788 */   GIM_Try, /*On fail goto*//*Label 8812*/ GIMT_Encode4(573850), // Rule ID 20758 //
     /*  573793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  573796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573803 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573816 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64),
     /*  573819 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573848 */     GIR_RootConstrainSelectedInstOperands,
     /*  573849 */     // GIR_Coverage, 20758,
     /*  573849 */     GIR_EraseRootFromParent_Done,
     /*  573850 */   // Label 8812: @573850
     /*  573850 */   GIM_Try, /*On fail goto*//*Label 8813*/ GIMT_Encode4(573912), // Rule ID 20759 //
     /*  573855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  573858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573865 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573878 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64),
     /*  573881 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573910 */     GIR_RootConstrainSelectedInstOperands,
     /*  573911 */     // GIR_Coverage, 20759,
     /*  573911 */     GIR_EraseRootFromParent_Done,
     /*  573912 */   // Label 8813: @573912
     /*  573912 */   GIM_Try, /*On fail goto*//*Label 8814*/ GIMT_Encode4(573974), // Rule ID 20760 //
     /*  573917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  573920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573927 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  573940 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  573940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64),
     /*  573943 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  573945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  573950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  573955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  573960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  573965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  573968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  573972 */     GIR_RootConstrainSelectedInstOperands,
     /*  573973 */     // GIR_Coverage, 20760,
     /*  573973 */     GIR_EraseRootFromParent_Done,
     /*  573974 */   // Label 8814: @573974
     /*  573974 */   GIM_Try, /*On fail goto*//*Label 8815*/ GIMT_Encode4(574036), // Rule ID 20761 //
     /*  573979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  573982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  573989 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  573991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  573995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574002 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64),
     /*  574005 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  574030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574034 */     GIR_RootConstrainSelectedInstOperands,
     /*  574035 */     // GIR_Coverage, 20761,
     /*  574035 */     GIR_EraseRootFromParent_Done,
     /*  574036 */   // Label 8815: @574036
     /*  574036 */   GIM_Try, /*On fail goto*//*Label 8816*/ GIMT_Encode4(574098), // Rule ID 20762 //
     /*  574041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  574044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574051 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  574053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574064 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64),
     /*  574067 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  574092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574096 */     GIR_RootConstrainSelectedInstOperands,
     /*  574097 */     // GIR_Coverage, 20762,
     /*  574097 */     GIR_EraseRootFromParent_Done,
     /*  574098 */   // Label 8816: @574098
     /*  574098 */   GIM_Try, /*On fail goto*//*Label 8817*/ GIMT_Encode4(574164), // Rule ID 20718 //
     /*  574103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  574106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574128 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN),
     /*  574131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574133 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574162 */     GIR_RootConstrainSelectedInstOperands,
     /*  574163 */     // GIR_Coverage, 20718,
     /*  574163 */     GIR_EraseRootFromParent_Done,
     /*  574164 */   // Label 8817: @574164
     /*  574164 */   GIM_Try, /*On fail goto*//*Label 8818*/ GIMT_Encode4(574230), // Rule ID 20719 //
     /*  574169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  574172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574194 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN),
     /*  574197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574199 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574228 */     GIR_RootConstrainSelectedInstOperands,
     /*  574229 */     // GIR_Coverage, 20719,
     /*  574229 */     GIR_EraseRootFromParent_Done,
     /*  574230 */   // Label 8818: @574230
     /*  574230 */   GIM_Try, /*On fail goto*//*Label 8819*/ GIMT_Encode4(574296), // Rule ID 20720 //
     /*  574235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  574238 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574249 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574253 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574260 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN),
     /*  574263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574265 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574294 */     GIR_RootConstrainSelectedInstOperands,
     /*  574295 */     // GIR_Coverage, 20720,
     /*  574295 */     GIR_EraseRootFromParent_Done,
     /*  574296 */   // Label 8819: @574296
     /*  574296 */   GIM_Try, /*On fail goto*//*Label 8820*/ GIMT_Encode4(574362), // Rule ID 20721 //
     /*  574301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  574304 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574326 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN),
     /*  574329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574331 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574360 */     GIR_RootConstrainSelectedInstOperands,
     /*  574361 */     // GIR_Coverage, 20721,
     /*  574361 */     GIR_EraseRootFromParent_Done,
     /*  574362 */   // Label 8820: @574362
     /*  574362 */   GIM_Try, /*On fail goto*//*Label 8821*/ GIMT_Encode4(574428), // Rule ID 20722 //
     /*  574367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  574370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574392 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN),
     /*  574395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574397 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574426 */     GIR_RootConstrainSelectedInstOperands,
     /*  574427 */     // GIR_Coverage, 20722,
     /*  574427 */     GIR_EraseRootFromParent_Done,
     /*  574428 */   // Label 8821: @574428
     /*  574428 */   GIM_Try, /*On fail goto*//*Label 8822*/ GIMT_Encode4(574494), // Rule ID 20748 //
     /*  574433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  574436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574447 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574451 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574458 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN),
     /*  574461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574463 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574492 */     GIR_RootConstrainSelectedInstOperands,
     /*  574493 */     // GIR_Coverage, 20748,
     /*  574493 */     GIR_EraseRootFromParent_Done,
     /*  574494 */   // Label 8822: @574494
     /*  574494 */   GIM_Try, /*On fail goto*//*Label 8823*/ GIMT_Encode4(574560), // Rule ID 20749 //
     /*  574499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  574502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574524 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN),
     /*  574527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574529 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574558 */     GIR_RootConstrainSelectedInstOperands,
     /*  574559 */     // GIR_Coverage, 20749,
     /*  574559 */     GIR_EraseRootFromParent_Done,
     /*  574560 */   // Label 8823: @574560
     /*  574560 */   GIM_Try, /*On fail goto*//*Label 8824*/ GIMT_Encode4(574626), // Rule ID 20750 //
     /*  574565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  574568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574590 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN),
     /*  574593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574595 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574624 */     GIR_RootConstrainSelectedInstOperands,
     /*  574625 */     // GIR_Coverage, 20750,
     /*  574625 */     GIR_EraseRootFromParent_Done,
     /*  574626 */   // Label 8824: @574626
     /*  574626 */   GIM_Try, /*On fail goto*//*Label 8825*/ GIMT_Encode4(574692), // Rule ID 20751 //
     /*  574631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  574634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574656 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN),
     /*  574659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574661 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574690 */     GIR_RootConstrainSelectedInstOperands,
     /*  574691 */     // GIR_Coverage, 20751,
     /*  574691 */     GIR_EraseRootFromParent_Done,
     /*  574692 */   // Label 8825: @574692
     /*  574692 */   GIM_Try, /*On fail goto*//*Label 8826*/ GIMT_Encode4(574758), // Rule ID 20752 //
     /*  574697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  574700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  574711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  574722 */     // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN),
     /*  574725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  574727 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  574734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  574744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  574749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  574752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574756 */     GIR_RootConstrainSelectedInstOperands,
     /*  574757 */     // GIR_Coverage, 20752,
     /*  574757 */     GIR_EraseRootFromParent_Done,
     /*  574758 */   // Label 8826: @574758
     /*  574758 */   GIM_Try, /*On fail goto*//*Label 8827*/ GIMT_Encode4(574815), // Rule ID 20733 //
     /*  574763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  574766 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574773 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  574775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  574786 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
     /*  574789 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  574801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  574806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  574809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574813 */     GIR_RootConstrainSelectedInstOperands,
     /*  574814 */     // GIR_Coverage, 20733,
     /*  574814 */     GIR_EraseRootFromParent_Done,
     /*  574815 */   // Label 8827: @574815
     /*  574815 */   GIM_Try, /*On fail goto*//*Label 8828*/ GIMT_Encode4(574872), // Rule ID 20734 //
     /*  574820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  574823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574830 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  574832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  574843 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
     /*  574846 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  574858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  574863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  574866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574870 */     GIR_RootConstrainSelectedInstOperands,
     /*  574871 */     // GIR_Coverage, 20734,
     /*  574871 */     GIR_EraseRootFromParent_Done,
     /*  574872 */   // Label 8828: @574872
     /*  574872 */   GIM_Try, /*On fail goto*//*Label 8829*/ GIMT_Encode4(574929), // Rule ID 20735 //
     /*  574877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  574880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574887 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  574889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  574900 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
     /*  574903 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  574915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  574920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  574923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574927 */     GIR_RootConstrainSelectedInstOperands,
     /*  574928 */     // GIR_Coverage, 20735,
     /*  574928 */     GIR_EraseRootFromParent_Done,
     /*  574929 */   // Label 8829: @574929
     /*  574929 */   GIM_Try, /*On fail goto*//*Label 8830*/ GIMT_Encode4(574986), // Rule ID 20736 //
     /*  574934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  574937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  574944 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  574946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  574950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  574957 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  574957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
     /*  574960 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  574962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  574967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  574972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  574977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  574980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  574984 */     GIR_RootConstrainSelectedInstOperands,
     /*  574985 */     // GIR_Coverage, 20736,
     /*  574985 */     GIR_EraseRootFromParent_Done,
     /*  574986 */   // Label 8830: @574986
     /*  574986 */   GIM_Try, /*On fail goto*//*Label 8831*/ GIMT_Encode4(575043), // Rule ID 20737 //
     /*  574991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  574994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575001 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  575003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575014 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
     /*  575017 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575041 */     GIR_RootConstrainSelectedInstOperands,
     /*  575042 */     // GIR_Coverage, 20737,
     /*  575042 */     GIR_EraseRootFromParent_Done,
     /*  575043 */   // Label 8831: @575043
     /*  575043 */   GIM_Try, /*On fail goto*//*Label 8832*/ GIMT_Encode4(575100), // Rule ID 20753 //
     /*  575048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  575051 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575058 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  575060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575071 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
     /*  575074 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575098 */     GIR_RootConstrainSelectedInstOperands,
     /*  575099 */     // GIR_Coverage, 20753,
     /*  575099 */     GIR_EraseRootFromParent_Done,
     /*  575100 */   // Label 8832: @575100
     /*  575100 */   GIM_Try, /*On fail goto*//*Label 8833*/ GIMT_Encode4(575157), // Rule ID 20754 //
     /*  575105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  575108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575115 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  575117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575128 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
     /*  575131 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575155 */     GIR_RootConstrainSelectedInstOperands,
     /*  575156 */     // GIR_Coverage, 20754,
     /*  575156 */     GIR_EraseRootFromParent_Done,
     /*  575157 */   // Label 8833: @575157
     /*  575157 */   GIM_Try, /*On fail goto*//*Label 8834*/ GIMT_Encode4(575214), // Rule ID 20755 //
     /*  575162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  575165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575172 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  575174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575185 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
     /*  575188 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575212 */     GIR_RootConstrainSelectedInstOperands,
     /*  575213 */     // GIR_Coverage, 20755,
     /*  575213 */     GIR_EraseRootFromParent_Done,
     /*  575214 */   // Label 8834: @575214
     /*  575214 */   GIM_Try, /*On fail goto*//*Label 8835*/ GIMT_Encode4(575271), // Rule ID 20756 //
     /*  575219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  575222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575229 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  575231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575242 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
     /*  575245 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575269 */     GIR_RootConstrainSelectedInstOperands,
     /*  575270 */     // GIR_Coverage, 20756,
     /*  575270 */     GIR_EraseRootFromParent_Done,
     /*  575271 */   // Label 8835: @575271
     /*  575271 */   GIM_Try, /*On fail goto*//*Label 8836*/ GIMT_Encode4(575328), // Rule ID 20757 //
     /*  575276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  575279 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575286 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  575288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575299 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
     /*  575302 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575326 */     GIR_RootConstrainSelectedInstOperands,
     /*  575327 */     // GIR_Coverage, 20757,
     /*  575327 */     GIR_EraseRootFromParent_Done,
     /*  575328 */   // Label 8836: @575328
     /*  575328 */   GIM_Try, /*On fail goto*//*Label 8837*/ GIMT_Encode4(575389), // Rule ID 20713 //
     /*  575333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  575336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575358 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
     /*  575361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575363 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575383 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575387 */     GIR_RootConstrainSelectedInstOperands,
     /*  575388 */     // GIR_Coverage, 20713,
     /*  575388 */     GIR_EraseRootFromParent_Done,
     /*  575389 */   // Label 8837: @575389
     /*  575389 */   GIM_Try, /*On fail goto*//*Label 8838*/ GIMT_Encode4(575450), // Rule ID 20714 //
     /*  575394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  575397 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575419 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
     /*  575422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575424 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575448 */     GIR_RootConstrainSelectedInstOperands,
     /*  575449 */     // GIR_Coverage, 20714,
     /*  575449 */     GIR_EraseRootFromParent_Done,
     /*  575450 */   // Label 8838: @575450
     /*  575450 */   GIM_Try, /*On fail goto*//*Label 8839*/ GIMT_Encode4(575511), // Rule ID 20715 //
     /*  575455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  575458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575469 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575480 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
     /*  575483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575485 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575509 */     GIR_RootConstrainSelectedInstOperands,
     /*  575510 */     // GIR_Coverage, 20715,
     /*  575510 */     GIR_EraseRootFromParent_Done,
     /*  575511 */   // Label 8839: @575511
     /*  575511 */   GIM_Try, /*On fail goto*//*Label 8840*/ GIMT_Encode4(575572), // Rule ID 20716 //
     /*  575516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  575519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575541 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
     /*  575544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575546 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575566 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575570 */     GIR_RootConstrainSelectedInstOperands,
     /*  575571 */     // GIR_Coverage, 20716,
     /*  575571 */     GIR_EraseRootFromParent_Done,
     /*  575572 */   // Label 8840: @575572
     /*  575572 */   GIM_Try, /*On fail goto*//*Label 8841*/ GIMT_Encode4(575633), // Rule ID 20717 //
     /*  575577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  575580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575602 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
     /*  575605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575607 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575627 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575631 */     GIR_RootConstrainSelectedInstOperands,
     /*  575632 */     // GIR_Coverage, 20717,
     /*  575632 */     GIR_EraseRootFromParent_Done,
     /*  575633 */   // Label 8841: @575633
     /*  575633 */   GIM_Try, /*On fail goto*//*Label 8842*/ GIMT_Encode4(575694), // Rule ID 20743 //
     /*  575638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  575641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575663 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
     /*  575666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575668 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575685 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575692 */     GIR_RootConstrainSelectedInstOperands,
     /*  575693 */     // GIR_Coverage, 20743,
     /*  575693 */     GIR_EraseRootFromParent_Done,
     /*  575694 */   // Label 8842: @575694
     /*  575694 */   GIM_Try, /*On fail goto*//*Label 8843*/ GIMT_Encode4(575755), // Rule ID 20744 //
     /*  575699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  575702 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575724 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
     /*  575727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575729 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575749 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575753 */     GIR_RootConstrainSelectedInstOperands,
     /*  575754 */     // GIR_Coverage, 20744,
     /*  575754 */     GIR_EraseRootFromParent_Done,
     /*  575755 */   // Label 8843: @575755
     /*  575755 */   GIM_Try, /*On fail goto*//*Label 8844*/ GIMT_Encode4(575816), // Rule ID 20745 //
     /*  575760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  575763 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575785 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
     /*  575788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575790 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575814 */     GIR_RootConstrainSelectedInstOperands,
     /*  575815 */     // GIR_Coverage, 20745,
     /*  575815 */     GIR_EraseRootFromParent_Done,
     /*  575816 */   // Label 8844: @575816
     /*  575816 */   GIM_Try, /*On fail goto*//*Label 8845*/ GIMT_Encode4(575877), // Rule ID 20746 //
     /*  575821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  575824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575846 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
     /*  575849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575851 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575871 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575875 */     GIR_RootConstrainSelectedInstOperands,
     /*  575876 */     // GIR_Coverage, 20746,
     /*  575876 */     GIR_EraseRootFromParent_Done,
     /*  575877 */   // Label 8845: @575877
     /*  575877 */   GIM_Try, /*On fail goto*//*Label 8846*/ GIMT_Encode4(575938), // Rule ID 20747 //
     /*  575882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  575885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  575892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  575907 */     // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  575907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
     /*  575910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  575912 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  575914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  575919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  575924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  575929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  575932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575936 */     GIR_RootConstrainSelectedInstOperands,
     /*  575937 */     // GIR_Coverage, 20747,
     /*  575937 */     GIR_EraseRootFromParent_Done,
     /*  575938 */   // Label 8846: @575938
     /*  575938 */   GIM_Try, /*On fail goto*//*Label 8847*/ GIMT_Encode4(575992), // Rule ID 28741 //
     /*  575943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  575946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  575951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  575955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  575959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  575966 */     // (atomic_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_local_m0_i32>>  =>  (DS_WRXCHG_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  575966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32),
     /*  575969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  575971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  575976 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  575978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  575983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  575986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  575990 */     GIR_RootConstrainSelectedInstOperands,
     /*  575991 */     // GIR_Coverage, 28741,
     /*  575991 */     GIR_EraseRootFromParent_Done,
     /*  575992 */   // Label 8847: @575992
     /*  575992 */   GIM_Try, /*On fail goto*//*Label 8848*/ GIMT_Encode4(576046), // Rule ID 28742 //
     /*  575997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  576000 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  576005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  576020 */     // (atomic_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_local_i32>>  =>  (DS_WRXCHG_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  576020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32_gfx9),
     /*  576023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  576030 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  576032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  576040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576044 */     GIR_RootConstrainSelectedInstOperands,
     /*  576045 */     // GIR_Coverage, 28742,
     /*  576045 */     GIR_EraseRootFromParent_Done,
     /*  576046 */   // Label 8848: @576046
     /*  576046 */   GIM_Try, /*On fail goto*//*Label 8849*/ GIMT_Encode4(576100), // Rule ID 28743 //
     /*  576051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  576054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  576059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  576074 */     // (atomic_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_region_m0_i32>>  =>  (DS_WRXCHG_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  576074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32),
     /*  576077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  576084 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  576086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  576094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576098 */     GIR_RootConstrainSelectedInstOperands,
     /*  576099 */     // GIR_Coverage, 28743,
     /*  576099 */     GIR_EraseRootFromParent_Done,
     /*  576100 */   // Label 8849: @576100
     /*  576100 */   GIM_Try, /*On fail goto*//*Label 8850*/ GIMT_Encode4(576159), // Rule ID 13041 //
     /*  576105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  576108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576115 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  576128 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  576128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR),
     /*  576131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  576136 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  576143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  576148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  576153 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576157 */     GIR_RootConstrainSelectedInstOperands,
     /*  576158 */     // GIR_Coverage, 13041,
     /*  576158 */     GIR_EraseRootFromParent_Done,
     /*  576159 */   // Label 8850: @576159
     /*  576159 */   GIM_Try, /*On fail goto*//*Label 8851*/ GIMT_Encode4(576218), // Rule ID 13042 //
     /*  576164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  576167 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576174 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576180 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  576187 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  576187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR),
     /*  576190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  576195 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  576202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  576207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  576212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576216 */     GIR_RootConstrainSelectedInstOperands,
     /*  576217 */     // GIR_Coverage, 13042,
     /*  576217 */     GIR_EraseRootFromParent_Done,
     /*  576218 */   // Label 8851: @576218
     /*  576218 */   GIM_Try, /*On fail goto*//*Label 8852*/ GIMT_Encode4(576277), // Rule ID 13043 //
     /*  576223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  576226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576233 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576235 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576239 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  576246 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  576246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR),
     /*  576249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  576254 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  576261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  576266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  576271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576275 */     GIR_RootConstrainSelectedInstOperands,
     /*  576276 */     // GIR_Coverage, 13043,
     /*  576276 */     GIR_EraseRootFromParent_Done,
     /*  576277 */   // Label 8852: @576277
     /*  576277 */   GIM_Try, /*On fail goto*//*Label 8853*/ GIMT_Encode4(576336), // Rule ID 13044 //
     /*  576282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  576285 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576292 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  576305 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  576305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR),
     /*  576308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  576313 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  576320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  576325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  576330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576334 */     GIR_RootConstrainSelectedInstOperands,
     /*  576335 */     // GIR_Coverage, 13044,
     /*  576335 */     GIR_EraseRootFromParent_Done,
     /*  576336 */   // Label 8853: @576336
     /*  576336 */   GIM_Try, /*On fail goto*//*Label 8854*/ GIMT_Encode4(576395), // Rule ID 13045 //
     /*  576341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  576344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576351 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576353 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  576364 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  576364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR),
     /*  576367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  576372 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  576379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  576384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  576389 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576393 */     GIR_RootConstrainSelectedInstOperands,
     /*  576394 */     // GIR_Coverage, 13045,
     /*  576394 */     GIR_EraseRootFromParent_Done,
     /*  576395 */   // Label 8854: @576395
     /*  576395 */   GIM_Try, /*On fail goto*//*Label 8855*/ GIMT_Encode4(576458), // Rule ID 13051 //
     /*  576400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  576403 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576418 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  576425 */     // (atomic_swap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  576425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN),
     /*  576428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  576435 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  576442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  576447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  576452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576456 */     GIR_RootConstrainSelectedInstOperands,
     /*  576457 */     // GIR_Coverage, 13051,
     /*  576457 */     GIR_EraseRootFromParent_Done,
     /*  576458 */   // Label 8855: @576458
     /*  576458 */   GIM_Try, /*On fail goto*//*Label 8856*/ GIMT_Encode4(576510), // Rule ID 13036 //
     /*  576463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  576466 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576473 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576486 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP),
     /*  576489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576494 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  576504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576508 */     GIR_RootConstrainSelectedInstOperands,
     /*  576509 */     // GIR_Coverage, 13036,
     /*  576509 */     GIR_EraseRootFromParent_Done,
     /*  576510 */   // Label 8856: @576510
     /*  576510 */   GIM_Try, /*On fail goto*//*Label 8857*/ GIMT_Encode4(576562), // Rule ID 13037 //
     /*  576515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  576518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576525 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576538 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP),
     /*  576541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576546 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  576556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576560 */     GIR_RootConstrainSelectedInstOperands,
     /*  576561 */     // GIR_Coverage, 13037,
     /*  576561 */     GIR_EraseRootFromParent_Done,
     /*  576562 */   // Label 8857: @576562
     /*  576562 */   GIM_Try, /*On fail goto*//*Label 8858*/ GIMT_Encode4(576614), // Rule ID 13038 //
     /*  576567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  576570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576577 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576590 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP),
     /*  576593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576598 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576605 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  576608 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576612 */     GIR_RootConstrainSelectedInstOperands,
     /*  576613 */     // GIR_Coverage, 13038,
     /*  576613 */     GIR_EraseRootFromParent_Done,
     /*  576614 */   // Label 8858: @576614
     /*  576614 */   GIM_Try, /*On fail goto*//*Label 8859*/ GIMT_Encode4(576666), // Rule ID 13039 //
     /*  576619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  576622 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576629 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576642 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP),
     /*  576645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576650 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  576660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576664 */     GIR_RootConstrainSelectedInstOperands,
     /*  576665 */     // GIR_Coverage, 13039,
     /*  576665 */     GIR_EraseRootFromParent_Done,
     /*  576666 */   // Label 8859: @576666
     /*  576666 */   GIM_Try, /*On fail goto*//*Label 8860*/ GIMT_Encode4(576718), // Rule ID 13040 //
     /*  576671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  576674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576681 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  576683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576694 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP),
     /*  576697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576702 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  576712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576716 */     GIR_RootConstrainSelectedInstOperands,
     /*  576717 */     // GIR_Coverage, 13040,
     /*  576717 */     GIR_EraseRootFromParent_Done,
     /*  576718 */   // Label 8860: @576718
     /*  576718 */   GIM_Try, /*On fail goto*//*Label 8861*/ GIMT_Encode4(576774), // Rule ID 13046 //
     /*  576723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  576726 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576748 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN),
     /*  576751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576758 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  576768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576772 */     GIR_RootConstrainSelectedInstOperands,
     /*  576773 */     // GIR_Coverage, 13046,
     /*  576773 */     GIR_EraseRootFromParent_Done,
     /*  576774 */   // Label 8861: @576774
     /*  576774 */   GIM_Try, /*On fail goto*//*Label 8862*/ GIMT_Encode4(576830), // Rule ID 13047 //
     /*  576779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  576782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576804 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN),
     /*  576807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576814 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  576824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576828 */     GIR_RootConstrainSelectedInstOperands,
     /*  576829 */     // GIR_Coverage, 13047,
     /*  576829 */     GIR_EraseRootFromParent_Done,
     /*  576830 */   // Label 8862: @576830
     /*  576830 */   GIM_Try, /*On fail goto*//*Label 8863*/ GIMT_Encode4(576886), // Rule ID 13048 //
     /*  576835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  576838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576860 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN),
     /*  576863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576870 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  576880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576884 */     GIR_RootConstrainSelectedInstOperands,
     /*  576885 */     // GIR_Coverage, 13048,
     /*  576885 */     GIR_EraseRootFromParent_Done,
     /*  576886 */   // Label 8863: @576886
     /*  576886 */   GIM_Try, /*On fail goto*//*Label 8864*/ GIMT_Encode4(576942), // Rule ID 13049 //
     /*  576891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  576894 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576916 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN),
     /*  576919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576926 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  576936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576940 */     GIR_RootConstrainSelectedInstOperands,
     /*  576941 */     // GIR_Coverage, 13049,
     /*  576941 */     GIR_EraseRootFromParent_Done,
     /*  576942 */   // Label 8864: @576942
     /*  576942 */   GIM_Try, /*On fail goto*//*Label 8865*/ GIMT_Encode4(576998), // Rule ID 13050 //
     /*  576947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  576950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  576957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  576961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  576965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  576972 */     // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  576972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN),
     /*  576975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  576977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  576982 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  576984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  576989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  576992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  576996 */     GIR_RootConstrainSelectedInstOperands,
     /*  576997 */     // GIR_Coverage, 13050,
     /*  576997 */     GIR_EraseRootFromParent_Done,
     /*  576998 */   // Label 8865: @576998
     /*  576998 */   GIM_Try, /*On fail goto*//*Label 8866*/ GIMT_Encode4(577058), // Rule ID 10641 //
     /*  577003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  577006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577014 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577027 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577035 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577056 */     GIR_RootConstrainSelectedInstOperands,
     /*  577057 */     // GIR_Coverage, 10641,
     /*  577057 */     GIR_EraseRootFromParent_Done,
     /*  577058 */   // Label 8866: @577058
     /*  577058 */   GIM_Try, /*On fail goto*//*Label 8867*/ GIMT_Encode4(577118), // Rule ID 10642 //
     /*  577063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  577066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577074 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577087 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577095 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577112 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577116 */     GIR_RootConstrainSelectedInstOperands,
     /*  577117 */     // GIR_Coverage, 10642,
     /*  577117 */     GIR_EraseRootFromParent_Done,
     /*  577118 */   // Label 8867: @577118
     /*  577118 */   GIM_Try, /*On fail goto*//*Label 8868*/ GIMT_Encode4(577178), // Rule ID 10643 //
     /*  577123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  577126 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577134 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577147 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577155 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577176 */     GIR_RootConstrainSelectedInstOperands,
     /*  577177 */     // GIR_Coverage, 10643,
     /*  577177 */     GIR_EraseRootFromParent_Done,
     /*  577178 */   // Label 8868: @577178
     /*  577178 */   GIM_Try, /*On fail goto*//*Label 8869*/ GIMT_Encode4(577238), // Rule ID 10644 //
     /*  577183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  577186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577194 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577200 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577207 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577215 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577236 */     GIR_RootConstrainSelectedInstOperands,
     /*  577237 */     // GIR_Coverage, 10644,
     /*  577237 */     GIR_EraseRootFromParent_Done,
     /*  577238 */   // Label 8869: @577238
     /*  577238 */   GIM_Try, /*On fail goto*//*Label 8870*/ GIMT_Encode4(577298), // Rule ID 10645 //
     /*  577243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  577246 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577254 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577267 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577275 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577292 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577296 */     GIR_RootConstrainSelectedInstOperands,
     /*  577297 */     // GIR_Coverage, 10645,
     /*  577297 */     GIR_EraseRootFromParent_Done,
     /*  577298 */   // Label 8870: @577298
     /*  577298 */   GIM_Try, /*On fail goto*//*Label 8871*/ GIMT_Encode4(577357), // Rule ID 11197 //
     /*  577303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  577306 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577313 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577326 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577334 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577355 */     GIR_RootConstrainSelectedInstOperands,
     /*  577356 */     // GIR_Coverage, 11197,
     /*  577356 */     GIR_EraseRootFromParent_Done,
     /*  577357 */   // Label 8871: @577357
     /*  577357 */   GIM_Try, /*On fail goto*//*Label 8872*/ GIMT_Encode4(577416), // Rule ID 11198 //
     /*  577362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  577365 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577372 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577385 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577393 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577414 */     GIR_RootConstrainSelectedInstOperands,
     /*  577415 */     // GIR_Coverage, 11198,
     /*  577415 */     GIR_EraseRootFromParent_Done,
     /*  577416 */   // Label 8872: @577416
     /*  577416 */   GIM_Try, /*On fail goto*//*Label 8873*/ GIMT_Encode4(577475), // Rule ID 11199 //
     /*  577421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  577424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577431 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577444 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577452 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577473 */     GIR_RootConstrainSelectedInstOperands,
     /*  577474 */     // GIR_Coverage, 11199,
     /*  577474 */     GIR_EraseRootFromParent_Done,
     /*  577475 */   // Label 8873: @577475
     /*  577475 */   GIM_Try, /*On fail goto*//*Label 8874*/ GIMT_Encode4(577534), // Rule ID 11200 //
     /*  577480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  577483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577490 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577492 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577503 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577511 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577532 */     GIR_RootConstrainSelectedInstOperands,
     /*  577533 */     // GIR_Coverage, 11200,
     /*  577533 */     GIR_EraseRootFromParent_Done,
     /*  577534 */   // Label 8874: @577534
     /*  577534 */   GIM_Try, /*On fail goto*//*Label 8875*/ GIMT_Encode4(577593), // Rule ID 11201 //
     /*  577539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  577542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577549 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  577562 */     // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR),
     /*  577565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577570 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577591 */     GIR_RootConstrainSelectedInstOperands,
     /*  577592 */     // GIR_Coverage, 11201,
     /*  577592 */     GIR_EraseRootFromParent_Done,
     /*  577593 */   // Label 8875: @577593
     /*  577593 */   GIM_Try, /*On fail goto*//*Label 8876*/ GIMT_Encode4(577657), // Rule ID 10635 //
     /*  577598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  577601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  577613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  577624 */     // (atomic_swap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR_RTN),
     /*  577627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  577629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577634 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577655 */     GIR_RootConstrainSelectedInstOperands,
     /*  577656 */     // GIR_Coverage, 10635,
     /*  577656 */     GIR_EraseRootFromParent_Done,
     /*  577657 */   // Label 8876: @577657
     /*  577657 */   GIM_Try, /*On fail goto*//*Label 8877*/ GIMT_Encode4(577720), // Rule ID 11191 //
     /*  577662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  577665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  577676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  577687 */     // (atomic_swap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (FLAT_ATOMIC_SWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  577687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_SADDR_RTN),
     /*  577690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  577692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  577697 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  577704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  577709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  577714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577718 */     GIR_RootConstrainSelectedInstOperands,
     /*  577719 */     // GIR_Coverage, 11191,
     /*  577719 */     GIR_EraseRootFromParent_Done,
     /*  577720 */   // Label 8877: @577720
     /*  577720 */   GIM_Try, /*On fail goto*//*Label 8878*/ GIMT_Encode4(577773), // Rule ID 10636 //
     /*  577725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  577728 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577736 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  577749 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  577749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  577752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  577757 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  577764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  577767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577771 */     GIR_RootConstrainSelectedInstOperands,
     /*  577772 */     // GIR_Coverage, 10636,
     /*  577772 */     GIR_EraseRootFromParent_Done,
     /*  577773 */   // Label 8878: @577773
     /*  577773 */   GIM_Try, /*On fail goto*//*Label 8879*/ GIMT_Encode4(577826), // Rule ID 10637 //
     /*  577778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  577781 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577789 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  577802 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  577802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  577805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  577810 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  577817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  577820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577824 */     GIR_RootConstrainSelectedInstOperands,
     /*  577825 */     // GIR_Coverage, 10637,
     /*  577825 */     GIR_EraseRootFromParent_Done,
     /*  577826 */   // Label 8879: @577826
     /*  577826 */   GIM_Try, /*On fail goto*//*Label 8880*/ GIMT_Encode4(577879), // Rule ID 10638 //
     /*  577831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  577834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577842 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  577855 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  577855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  577858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  577863 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  577870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  577873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577877 */     GIR_RootConstrainSelectedInstOperands,
     /*  577878 */     // GIR_Coverage, 10638,
     /*  577878 */     GIR_EraseRootFromParent_Done,
     /*  577879 */   // Label 8880: @577879
     /*  577879 */   GIM_Try, /*On fail goto*//*Label 8881*/ GIMT_Encode4(577932), // Rule ID 10639 //
     /*  577884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  577887 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577895 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  577908 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  577908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  577911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  577916 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  577923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  577926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577930 */     GIR_RootConstrainSelectedInstOperands,
     /*  577931 */     // GIR_Coverage, 10639,
     /*  577931 */     GIR_EraseRootFromParent_Done,
     /*  577932 */   // Label 8881: @577932
     /*  577932 */   GIM_Try, /*On fail goto*//*Label 8882*/ GIMT_Encode4(577985), // Rule ID 10640 //
     /*  577937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  577940 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  577948 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  577950 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  577954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  577961 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  577961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  577964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  577969 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  577971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  577976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  577979 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  577983 */     GIR_RootConstrainSelectedInstOperands,
     /*  577984 */     // GIR_Coverage, 10640,
     /*  577984 */     GIR_EraseRootFromParent_Done,
     /*  577985 */   // Label 8882: @577985
     /*  577985 */   GIM_Try, /*On fail goto*//*Label 8883*/ GIMT_Encode4(578037), // Rule ID 11192 //
     /*  577990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  577993 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578000 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578013 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  578016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578021 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578031 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578035 */     GIR_RootConstrainSelectedInstOperands,
     /*  578036 */     // GIR_Coverage, 11192,
     /*  578036 */     GIR_EraseRootFromParent_Done,
     /*  578037 */   // Label 8883: @578037
     /*  578037 */   GIM_Try, /*On fail goto*//*Label 8884*/ GIMT_Encode4(578089), // Rule ID 11193 //
     /*  578042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  578045 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578052 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578065 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  578068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578073 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578080 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578083 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578087 */     GIR_RootConstrainSelectedInstOperands,
     /*  578088 */     // GIR_Coverage, 11193,
     /*  578088 */     GIR_EraseRootFromParent_Done,
     /*  578089 */   // Label 8884: @578089
     /*  578089 */   GIM_Try, /*On fail goto*//*Label 8885*/ GIMT_Encode4(578141), // Rule ID 11194 //
     /*  578094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  578097 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578104 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578117 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  578120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578125 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578139 */     GIR_RootConstrainSelectedInstOperands,
     /*  578140 */     // GIR_Coverage, 11194,
     /*  578140 */     GIR_EraseRootFromParent_Done,
     /*  578141 */   // Label 8885: @578141
     /*  578141 */   GIM_Try, /*On fail goto*//*Label 8886*/ GIMT_Encode4(578193), // Rule ID 11195 //
     /*  578146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  578149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578156 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578158 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578162 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578169 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  578172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578177 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578191 */     GIR_RootConstrainSelectedInstOperands,
     /*  578192 */     // GIR_Coverage, 11195,
     /*  578192 */     GIR_EraseRootFromParent_Done,
     /*  578193 */   // Label 8886: @578193
     /*  578193 */   GIM_Try, /*On fail goto*//*Label 8887*/ GIMT_Encode4(578245), // Rule ID 11196 //
     /*  578198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  578201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578208 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578221 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>>  =>  (FLAT_ATOMIC_SWAP VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
     /*  578224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578229 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578243 */     GIR_RootConstrainSelectedInstOperands,
     /*  578244 */     // GIR_Coverage, 11196,
     /*  578244 */     GIR_EraseRootFromParent_Done,
     /*  578245 */   // Label 8887: @578245
     /*  578245 */   GIM_Try, /*On fail goto*//*Label 8888*/ GIMT_Encode4(578302), // Rule ID 10630 //
     /*  578250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  578253 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578276 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578286 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578300 */     GIR_RootConstrainSelectedInstOperands,
     /*  578301 */     // GIR_Coverage, 10630,
     /*  578301 */     GIR_EraseRootFromParent_Done,
     /*  578302 */   // Label 8888: @578302
     /*  578302 */   GIM_Try, /*On fail goto*//*Label 8889*/ GIMT_Encode4(578359), // Rule ID 10631 //
     /*  578307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  578310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578333 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578343 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578353 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578357 */     GIR_RootConstrainSelectedInstOperands,
     /*  578358 */     // GIR_Coverage, 10631,
     /*  578358 */     GIR_EraseRootFromParent_Done,
     /*  578359 */   // Label 8889: @578359
     /*  578359 */   GIM_Try, /*On fail goto*//*Label 8890*/ GIMT_Encode4(578416), // Rule ID 10632 //
     /*  578364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  578367 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578390 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578414 */     GIR_RootConstrainSelectedInstOperands,
     /*  578415 */     // GIR_Coverage, 10632,
     /*  578415 */     GIR_EraseRootFromParent_Done,
     /*  578416 */   // Label 8890: @578416
     /*  578416 */   GIM_Try, /*On fail goto*//*Label 8891*/ GIMT_Encode4(578473), // Rule ID 10633 //
     /*  578421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  578424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578447 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578457 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578471 */     GIR_RootConstrainSelectedInstOperands,
     /*  578472 */     // GIR_Coverage, 10633,
     /*  578472 */     GIR_EraseRootFromParent_Done,
     /*  578473 */   // Label 8891: @578473
     /*  578473 */   GIM_Try, /*On fail goto*//*Label 8892*/ GIMT_Encode4(578530), // Rule ID 10634 //
     /*  578478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  578481 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578504 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578514 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578528 */     GIR_RootConstrainSelectedInstOperands,
     /*  578529 */     // GIR_Coverage, 10634,
     /*  578529 */     GIR_EraseRootFromParent_Done,
     /*  578530 */   // Label 8892: @578530
     /*  578530 */   GIM_Try, /*On fail goto*//*Label 8893*/ GIMT_Encode4(578586), // Rule ID 11186 //
     /*  578535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  578538 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578560 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578570 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578580 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578584 */     GIR_RootConstrainSelectedInstOperands,
     /*  578585 */     // GIR_Coverage, 11186,
     /*  578585 */     GIR_EraseRootFromParent_Done,
     /*  578586 */   // Label 8893: @578586
     /*  578586 */   GIM_Try, /*On fail goto*//*Label 8894*/ GIMT_Encode4(578642), // Rule ID 11187 //
     /*  578591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  578594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578616 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578626 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578640 */     GIR_RootConstrainSelectedInstOperands,
     /*  578641 */     // GIR_Coverage, 11187,
     /*  578641 */     GIR_EraseRootFromParent_Done,
     /*  578642 */   // Label 8894: @578642
     /*  578642 */   GIM_Try, /*On fail goto*//*Label 8895*/ GIMT_Encode4(578698), // Rule ID 11188 //
     /*  578647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  578650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578672 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578682 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578696 */     GIR_RootConstrainSelectedInstOperands,
     /*  578697 */     // GIR_Coverage, 11188,
     /*  578697 */     GIR_EraseRootFromParent_Done,
     /*  578698 */   // Label 8895: @578698
     /*  578698 */   GIM_Try, /*On fail goto*//*Label 8896*/ GIMT_Encode4(578754), // Rule ID 11189 //
     /*  578703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  578706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578728 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578738 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578752 */     GIR_RootConstrainSelectedInstOperands,
     /*  578753 */     // GIR_Coverage, 11189,
     /*  578753 */     GIR_EraseRootFromParent_Done,
     /*  578754 */   // Label 8896: @578754
     /*  578754 */   GIM_Try, /*On fail goto*//*Label 8897*/ GIMT_Encode4(578810), // Rule ID 11190 //
     /*  578759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  578762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  578773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  578784 */     // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  578784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
     /*  578787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  578789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  578794 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  578796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  578801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  578804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578808 */     GIR_RootConstrainSelectedInstOperands,
     /*  578809 */     // GIR_Coverage, 11190,
     /*  578809 */     GIR_EraseRootFromParent_Done,
     /*  578810 */   // Label 8897: @578810
     /*  578810 */   GIM_Reject,
     /*  578811 */ // Label 8806: @578811
     /*  578811 */ GIM_Reject,
     /*  578812 */ // Label 8804: @578812
     /*  578812 */ GIM_Try, /*On fail goto*//*Label 8898*/ GIMT_Encode4(585561),
     /*  578817 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  578820 */   GIM_Try, /*On fail goto*//*Label 8899*/ GIMT_Encode4(578882), // Rule ID 21218 //
     /*  578825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  578828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  578848 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  578848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64),
     /*  578851 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  578853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  578858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  578863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  578868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  578873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578880 */     GIR_RootConstrainSelectedInstOperands,
     /*  578881 */     // GIR_Coverage, 21218,
     /*  578881 */     GIR_EraseRootFromParent_Done,
     /*  578882 */   // Label 8899: @578882
     /*  578882 */   GIM_Try, /*On fail goto*//*Label 8900*/ GIMT_Encode4(578944), // Rule ID 21219 //
     /*  578887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  578890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578897 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  578910 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  578910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64),
     /*  578913 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  578915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  578920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  578925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  578930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  578935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  578938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  578942 */     GIR_RootConstrainSelectedInstOperands,
     /*  578943 */     // GIR_Coverage, 21219,
     /*  578943 */     GIR_EraseRootFromParent_Done,
     /*  578944 */   // Label 8900: @578944
     /*  578944 */   GIM_Try, /*On fail goto*//*Label 8901*/ GIMT_Encode4(579006), // Rule ID 21220 //
     /*  578949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  578952 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  578959 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  578961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  578965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  578972 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  578972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64),
     /*  578975 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  578977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  578982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  578987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  578992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  578997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579004 */     GIR_RootConstrainSelectedInstOperands,
     /*  579005 */     // GIR_Coverage, 21220,
     /*  579005 */     GIR_EraseRootFromParent_Done,
     /*  579006 */   // Label 8901: @579006
     /*  579006 */   GIM_Try, /*On fail goto*//*Label 8902*/ GIMT_Encode4(579068), // Rule ID 21221 //
     /*  579011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  579014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579021 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579034 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64),
     /*  579037 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579066 */     GIR_RootConstrainSelectedInstOperands,
     /*  579067 */     // GIR_Coverage, 21221,
     /*  579067 */     GIR_EraseRootFromParent_Done,
     /*  579068 */   // Label 8902: @579068
     /*  579068 */   GIM_Try, /*On fail goto*//*Label 8903*/ GIMT_Encode4(579130), // Rule ID 21222 //
     /*  579073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  579076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579083 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579085 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579096 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64),
     /*  579099 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579128 */     GIR_RootConstrainSelectedInstOperands,
     /*  579129 */     // GIR_Coverage, 21222,
     /*  579129 */     GIR_EraseRootFromParent_Done,
     /*  579130 */   // Label 8903: @579130
     /*  579130 */   GIM_Try, /*On fail goto*//*Label 8904*/ GIMT_Encode4(579192), // Rule ID 21238 //
     /*  579135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  579138 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579145 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579158 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64),
     /*  579161 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579190 */     GIR_RootConstrainSelectedInstOperands,
     /*  579191 */     // GIR_Coverage, 21238,
     /*  579191 */     GIR_EraseRootFromParent_Done,
     /*  579192 */   // Label 8904: @579192
     /*  579192 */   GIM_Try, /*On fail goto*//*Label 8905*/ GIMT_Encode4(579254), // Rule ID 21239 //
     /*  579197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  579200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579207 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579209 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579220 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64),
     /*  579223 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579252 */     GIR_RootConstrainSelectedInstOperands,
     /*  579253 */     // GIR_Coverage, 21239,
     /*  579253 */     GIR_EraseRootFromParent_Done,
     /*  579254 */   // Label 8905: @579254
     /*  579254 */   GIM_Try, /*On fail goto*//*Label 8906*/ GIMT_Encode4(579316), // Rule ID 21240 //
     /*  579259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  579262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579269 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579282 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64),
     /*  579285 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579310 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579314 */     GIR_RootConstrainSelectedInstOperands,
     /*  579315 */     // GIR_Coverage, 21240,
     /*  579315 */     GIR_EraseRootFromParent_Done,
     /*  579316 */   // Label 8906: @579316
     /*  579316 */   GIM_Try, /*On fail goto*//*Label 8907*/ GIMT_Encode4(579378), // Rule ID 21241 //
     /*  579321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  579324 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579331 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579337 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579344 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64),
     /*  579347 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579376 */     GIR_RootConstrainSelectedInstOperands,
     /*  579377 */     // GIR_Coverage, 21241,
     /*  579377 */     GIR_EraseRootFromParent_Done,
     /*  579378 */   // Label 8907: @579378
     /*  579378 */   GIM_Try, /*On fail goto*//*Label 8908*/ GIMT_Encode4(579440), // Rule ID 21242 //
     /*  579383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  579386 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579393 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  579395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579406 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64),
     /*  579409 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  579434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579438 */     GIR_RootConstrainSelectedInstOperands,
     /*  579439 */     // GIR_Coverage, 21242,
     /*  579439 */     GIR_EraseRootFromParent_Done,
     /*  579440 */   // Label 8908: @579440
     /*  579440 */   GIM_Try, /*On fail goto*//*Label 8909*/ GIMT_Encode4(579506), // Rule ID 21208 //
     /*  579445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  579448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579459 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579470 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN),
     /*  579473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579475 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579504 */     GIR_RootConstrainSelectedInstOperands,
     /*  579505 */     // GIR_Coverage, 21208,
     /*  579505 */     GIR_EraseRootFromParent_Done,
     /*  579506 */   // Label 8909: @579506
     /*  579506 */   GIM_Try, /*On fail goto*//*Label 8910*/ GIMT_Encode4(579572), // Rule ID 21209 //
     /*  579511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  579514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579525 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579529 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579536 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN),
     /*  579539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579541 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579566 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579570 */     GIR_RootConstrainSelectedInstOperands,
     /*  579571 */     // GIR_Coverage, 21209,
     /*  579571 */     GIR_EraseRootFromParent_Done,
     /*  579572 */   // Label 8910: @579572
     /*  579572 */   GIM_Try, /*On fail goto*//*Label 8911*/ GIMT_Encode4(579638), // Rule ID 21210 //
     /*  579577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  579580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579602 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN),
     /*  579605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579607 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579632 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579636 */     GIR_RootConstrainSelectedInstOperands,
     /*  579637 */     // GIR_Coverage, 21210,
     /*  579637 */     GIR_EraseRootFromParent_Done,
     /*  579638 */   // Label 8911: @579638
     /*  579638 */   GIM_Try, /*On fail goto*//*Label 8912*/ GIMT_Encode4(579704), // Rule ID 21211 //
     /*  579643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  579646 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579668 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN),
     /*  579671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579673 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579702 */     GIR_RootConstrainSelectedInstOperands,
     /*  579703 */     // GIR_Coverage, 21211,
     /*  579703 */     GIR_EraseRootFromParent_Done,
     /*  579704 */   // Label 8912: @579704
     /*  579704 */   GIM_Try, /*On fail goto*//*Label 8913*/ GIMT_Encode4(579770), // Rule ID 21212 //
     /*  579709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  579712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579723 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579734 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN),
     /*  579737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579739 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579764 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579768 */     GIR_RootConstrainSelectedInstOperands,
     /*  579769 */     // GIR_Coverage, 21212,
     /*  579769 */     GIR_EraseRootFromParent_Done,
     /*  579770 */   // Label 8913: @579770
     /*  579770 */   GIM_Try, /*On fail goto*//*Label 8914*/ GIMT_Encode4(579836), // Rule ID 21228 //
     /*  579775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  579778 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579800 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN),
     /*  579803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579805 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579834 */     GIR_RootConstrainSelectedInstOperands,
     /*  579835 */     // GIR_Coverage, 21228,
     /*  579835 */     GIR_EraseRootFromParent_Done,
     /*  579836 */   // Label 8914: @579836
     /*  579836 */   GIM_Try, /*On fail goto*//*Label 8915*/ GIMT_Encode4(579902), // Rule ID 21229 //
     /*  579841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  579844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579866 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN),
     /*  579869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579871 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579900 */     GIR_RootConstrainSelectedInstOperands,
     /*  579901 */     // GIR_Coverage, 21229,
     /*  579901 */     GIR_EraseRootFromParent_Done,
     /*  579902 */   // Label 8915: @579902
     /*  579902 */   GIM_Try, /*On fail goto*//*Label 8916*/ GIMT_Encode4(579968), // Rule ID 21230 //
     /*  579907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  579910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579932 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN),
     /*  579935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  579937 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  579939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  579944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  579949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  579954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  579959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  579962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  579966 */     GIR_RootConstrainSelectedInstOperands,
     /*  579967 */     // GIR_Coverage, 21230,
     /*  579967 */     GIR_EraseRootFromParent_Done,
     /*  579968 */   // Label 8916: @579968
     /*  579968 */   GIM_Try, /*On fail goto*//*Label 8917*/ GIMT_Encode4(580034), // Rule ID 21231 //
     /*  579973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  579976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  579983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  579987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  579991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  579998 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  579998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN),
     /*  580001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580003 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  580010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  580020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  580025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580032 */     GIR_RootConstrainSelectedInstOperands,
     /*  580033 */     // GIR_Coverage, 21231,
     /*  580033 */     GIR_EraseRootFromParent_Done,
     /*  580034 */   // Label 8917: @580034
     /*  580034 */   GIM_Try, /*On fail goto*//*Label 8918*/ GIMT_Encode4(580100), // Rule ID 21232 //
     /*  580039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  580042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  580064 */     // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN),
     /*  580067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580069 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  580076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  580086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  580091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580098 */     GIR_RootConstrainSelectedInstOperands,
     /*  580099 */     // GIR_Coverage, 21232,
     /*  580099 */     GIR_EraseRootFromParent_Done,
     /*  580100 */   // Label 8918: @580100
     /*  580100 */   GIM_Try, /*On fail goto*//*Label 8919*/ GIMT_Encode4(580157), // Rule ID 21213 //
     /*  580105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  580108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580115 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580128 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
     /*  580131 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580155 */     GIR_RootConstrainSelectedInstOperands,
     /*  580156 */     // GIR_Coverage, 21213,
     /*  580156 */     GIR_EraseRootFromParent_Done,
     /*  580157 */   // Label 8919: @580157
     /*  580157 */   GIM_Try, /*On fail goto*//*Label 8920*/ GIMT_Encode4(580214), // Rule ID 21214 //
     /*  580162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  580165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580172 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580185 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
     /*  580188 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580212 */     GIR_RootConstrainSelectedInstOperands,
     /*  580213 */     // GIR_Coverage, 21214,
     /*  580213 */     GIR_EraseRootFromParent_Done,
     /*  580214 */   // Label 8920: @580214
     /*  580214 */   GIM_Try, /*On fail goto*//*Label 8921*/ GIMT_Encode4(580271), // Rule ID 21215 //
     /*  580219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  580222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580229 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580242 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
     /*  580245 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580269 */     GIR_RootConstrainSelectedInstOperands,
     /*  580270 */     // GIR_Coverage, 21215,
     /*  580270 */     GIR_EraseRootFromParent_Done,
     /*  580271 */   // Label 8921: @580271
     /*  580271 */   GIM_Try, /*On fail goto*//*Label 8922*/ GIMT_Encode4(580328), // Rule ID 21216 //
     /*  580276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  580279 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580286 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580299 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
     /*  580302 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580326 */     GIR_RootConstrainSelectedInstOperands,
     /*  580327 */     // GIR_Coverage, 21216,
     /*  580327 */     GIR_EraseRootFromParent_Done,
     /*  580328 */   // Label 8922: @580328
     /*  580328 */   GIM_Try, /*On fail goto*//*Label 8923*/ GIMT_Encode4(580385), // Rule ID 21217 //
     /*  580333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  580336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580343 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580356 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
     /*  580359 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580383 */     GIR_RootConstrainSelectedInstOperands,
     /*  580384 */     // GIR_Coverage, 21217,
     /*  580384 */     GIR_EraseRootFromParent_Done,
     /*  580385 */   // Label 8923: @580385
     /*  580385 */   GIM_Try, /*On fail goto*//*Label 8924*/ GIMT_Encode4(580442), // Rule ID 21233 //
     /*  580390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  580393 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580400 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580413 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
     /*  580416 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580440 */     GIR_RootConstrainSelectedInstOperands,
     /*  580441 */     // GIR_Coverage, 21233,
     /*  580441 */     GIR_EraseRootFromParent_Done,
     /*  580442 */   // Label 8924: @580442
     /*  580442 */   GIM_Try, /*On fail goto*//*Label 8925*/ GIMT_Encode4(580499), // Rule ID 21234 //
     /*  580447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  580450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580457 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580459 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580470 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
     /*  580473 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580493 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580497 */     GIR_RootConstrainSelectedInstOperands,
     /*  580498 */     // GIR_Coverage, 21234,
     /*  580498 */     GIR_EraseRootFromParent_Done,
     /*  580499 */   // Label 8925: @580499
     /*  580499 */   GIM_Try, /*On fail goto*//*Label 8926*/ GIMT_Encode4(580556), // Rule ID 21235 //
     /*  580504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  580507 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580514 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580527 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
     /*  580530 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580550 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580554 */     GIR_RootConstrainSelectedInstOperands,
     /*  580555 */     // GIR_Coverage, 21235,
     /*  580555 */     GIR_EraseRootFromParent_Done,
     /*  580556 */   // Label 8926: @580556
     /*  580556 */   GIM_Try, /*On fail goto*//*Label 8927*/ GIMT_Encode4(580613), // Rule ID 21236 //
     /*  580561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  580564 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580571 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580584 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
     /*  580587 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580611 */     GIR_RootConstrainSelectedInstOperands,
     /*  580612 */     // GIR_Coverage, 21236,
     /*  580612 */     GIR_EraseRootFromParent_Done,
     /*  580613 */   // Label 8927: @580613
     /*  580613 */   GIM_Try, /*On fail goto*//*Label 8928*/ GIMT_Encode4(580670), // Rule ID 21237 //
     /*  580618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  580621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580628 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  580630 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580641 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
     /*  580644 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  580664 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580668 */     GIR_RootConstrainSelectedInstOperands,
     /*  580669 */     // GIR_Coverage, 21237,
     /*  580669 */     GIR_EraseRootFromParent_Done,
     /*  580670 */   // Label 8928: @580670
     /*  580670 */   GIM_Try, /*On fail goto*//*Label 8929*/ GIMT_Encode4(580731), // Rule ID 21203 //
     /*  580675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  580678 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580700 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
     /*  580703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580705 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580729 */     GIR_RootConstrainSelectedInstOperands,
     /*  580730 */     // GIR_Coverage, 21203,
     /*  580730 */     GIR_EraseRootFromParent_Done,
     /*  580731 */   // Label 8929: @580731
     /*  580731 */   GIM_Try, /*On fail goto*//*Label 8930*/ GIMT_Encode4(580792), // Rule ID 21204 //
     /*  580736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  580739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580754 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580761 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
     /*  580764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580766 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580783 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580790 */     GIR_RootConstrainSelectedInstOperands,
     /*  580791 */     // GIR_Coverage, 21204,
     /*  580791 */     GIR_EraseRootFromParent_Done,
     /*  580792 */   // Label 8930: @580792
     /*  580792 */   GIM_Try, /*On fail goto*//*Label 8931*/ GIMT_Encode4(580853), // Rule ID 21205 //
     /*  580797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  580800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580822 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
     /*  580825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580827 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580851 */     GIR_RootConstrainSelectedInstOperands,
     /*  580852 */     // GIR_Coverage, 21205,
     /*  580852 */     GIR_EraseRootFromParent_Done,
     /*  580853 */   // Label 8931: @580853
     /*  580853 */   GIM_Try, /*On fail goto*//*Label 8932*/ GIMT_Encode4(580914), // Rule ID 21206 //
     /*  580858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  580861 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580883 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
     /*  580886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580888 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580912 */     GIR_RootConstrainSelectedInstOperands,
     /*  580913 */     // GIR_Coverage, 21206,
     /*  580913 */     GIR_EraseRootFromParent_Done,
     /*  580914 */   // Label 8932: @580914
     /*  580914 */   GIM_Try, /*On fail goto*//*Label 8933*/ GIMT_Encode4(580975), // Rule ID 21207 //
     /*  580919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  580922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  580944 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  580944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
     /*  580947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  580949 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  580951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  580956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  580961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  580966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  580969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  580973 */     GIR_RootConstrainSelectedInstOperands,
     /*  580974 */     // GIR_Coverage, 21207,
     /*  580974 */     GIR_EraseRootFromParent_Done,
     /*  580975 */   // Label 8933: @580975
     /*  580975 */   GIM_Try, /*On fail goto*//*Label 8934*/ GIMT_Encode4(581036), // Rule ID 21223 //
     /*  580980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  580983 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  580990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  580994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  580998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  581005 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  581005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
     /*  581008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  581010 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  581012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  581017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  581022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  581027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581034 */     GIR_RootConstrainSelectedInstOperands,
     /*  581035 */     // GIR_Coverage, 21223,
     /*  581035 */     GIR_EraseRootFromParent_Done,
     /*  581036 */   // Label 8934: @581036
     /*  581036 */   GIM_Try, /*On fail goto*//*Label 8935*/ GIMT_Encode4(581097), // Rule ID 21224 //
     /*  581041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  581044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  581051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  581066 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  581066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
     /*  581069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  581071 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  581073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  581078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  581083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  581088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581095 */     GIR_RootConstrainSelectedInstOperands,
     /*  581096 */     // GIR_Coverage, 21224,
     /*  581096 */     GIR_EraseRootFromParent_Done,
     /*  581097 */   // Label 8935: @581097
     /*  581097 */   GIM_Try, /*On fail goto*//*Label 8936*/ GIMT_Encode4(581158), // Rule ID 21225 //
     /*  581102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  581105 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  581112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581120 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  581127 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  581127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
     /*  581130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  581132 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  581134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  581139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  581144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  581149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581156 */     GIR_RootConstrainSelectedInstOperands,
     /*  581157 */     // GIR_Coverage, 21225,
     /*  581157 */     GIR_EraseRootFromParent_Done,
     /*  581158 */   // Label 8936: @581158
     /*  581158 */   GIM_Try, /*On fail goto*//*Label 8937*/ GIMT_Encode4(581219), // Rule ID 21226 //
     /*  581163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  581166 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  581173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  581188 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  581188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
     /*  581191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  581193 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  581195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  581200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  581205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  581210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581213 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581217 */     GIR_RootConstrainSelectedInstOperands,
     /*  581218 */     // GIR_Coverage, 21226,
     /*  581218 */     GIR_EraseRootFromParent_Done,
     /*  581219 */   // Label 8937: @581219
     /*  581219 */   GIM_Try, /*On fail goto*//*Label 8938*/ GIMT_Encode4(581280), // Rule ID 21227 //
     /*  581224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  581227 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  581234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581238 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581242 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  581249 */     // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  581249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
     /*  581252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  581254 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  581256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  581261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  581266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  581271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581278 */     GIR_RootConstrainSelectedInstOperands,
     /*  581279 */     // GIR_Coverage, 21227,
     /*  581279 */     GIR_EraseRootFromParent_Done,
     /*  581280 */   // Label 8938: @581280
     /*  581280 */   GIM_Try, /*On fail goto*//*Label 8939*/ GIMT_Encode4(581334), // Rule ID 30545 //
     /*  581285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  581288 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581301 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581308 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581318 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581328 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581332 */     GIR_RootConstrainSelectedInstOperands,
     /*  581333 */     // GIR_Coverage, 30545,
     /*  581333 */     GIR_EraseRootFromParent_Done,
     /*  581334 */   // Label 8939: @581334
     /*  581334 */   GIM_Try, /*On fail goto*//*Label 8940*/ GIMT_Encode4(581388), // Rule ID 30546 //
     /*  581339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  581342 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581351 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581362 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581372 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581386 */     GIR_RootConstrainSelectedInstOperands,
     /*  581387 */     // GIR_Coverage, 30546,
     /*  581387 */     GIR_EraseRootFromParent_Done,
     /*  581388 */   // Label 8940: @581388
     /*  581388 */   GIM_Try, /*On fail goto*//*Label 8941*/ GIMT_Encode4(581442), // Rule ID 30547 //
     /*  581393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  581396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581416 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581426 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581440 */     GIR_RootConstrainSelectedInstOperands,
     /*  581441 */     // GIR_Coverage, 30547,
     /*  581441 */     GIR_EraseRootFromParent_Done,
     /*  581442 */   // Label 8941: @581442
     /*  581442 */   GIM_Try, /*On fail goto*//*Label 8942*/ GIMT_Encode4(581496), // Rule ID 30548 //
     /*  581447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  581450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581459 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581470 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581480 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581494 */     GIR_RootConstrainSelectedInstOperands,
     /*  581495 */     // GIR_Coverage, 30548,
     /*  581495 */     GIR_EraseRootFromParent_Done,
     /*  581496 */   // Label 8942: @581496
     /*  581496 */   GIM_Try, /*On fail goto*//*Label 8943*/ GIMT_Encode4(581550), // Rule ID 30549 //
     /*  581501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  581504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581524 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581534 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581548 */     GIR_RootConstrainSelectedInstOperands,
     /*  581549 */     // GIR_Coverage, 30549,
     /*  581549 */     GIR_EraseRootFromParent_Done,
     /*  581550 */   // Label 8943: @581550
     /*  581550 */   GIM_Try, /*On fail goto*//*Label 8944*/ GIMT_Encode4(581604), // Rule ID 30550 //
     /*  581555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  581558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581578 */     // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_i64>>  =>  (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9),
     /*  581581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581588 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581602 */     GIR_RootConstrainSelectedInstOperands,
     /*  581603 */     // GIR_Coverage, 30550,
     /*  581603 */     GIR_EraseRootFromParent_Done,
     /*  581604 */   // Label 8944: @581604
     /*  581604 */   GIM_Try, /*On fail goto*//*Label 8945*/ GIMT_Encode4(581658), // Rule ID 30551 //
     /*  581609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  581612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581632 */     // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_i64>>  =>  (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9),
     /*  581635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581642 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581656 */     GIR_RootConstrainSelectedInstOperands,
     /*  581657 */     // GIR_Coverage, 30551,
     /*  581657 */     GIR_EraseRootFromParent_Done,
     /*  581658 */   // Label 8945: @581658
     /*  581658 */   GIM_Try, /*On fail goto*//*Label 8946*/ GIMT_Encode4(581712), // Rule ID 30552 //
     /*  581663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  581666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581686 */     // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_i64>>  =>  (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9),
     /*  581689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581696 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581710 */     GIR_RootConstrainSelectedInstOperands,
     /*  581711 */     // GIR_Coverage, 30552,
     /*  581711 */     GIR_EraseRootFromParent_Done,
     /*  581712 */   // Label 8946: @581712
     /*  581712 */   GIM_Try, /*On fail goto*//*Label 8947*/ GIMT_Encode4(581766), // Rule ID 30553 //
     /*  581717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  581720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581740 */     // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_i64>>  =>  (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9),
     /*  581743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581750 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581760 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581764 */     GIR_RootConstrainSelectedInstOperands,
     /*  581765 */     // GIR_Coverage, 30553,
     /*  581765 */     GIR_EraseRootFromParent_Done,
     /*  581766 */   // Label 8947: @581766
     /*  581766 */   GIM_Try, /*On fail goto*//*Label 8948*/ GIMT_Encode4(581820), // Rule ID 30554 //
     /*  581771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  581774 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  581779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581794 */     // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_i64>>  =>  (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  581794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9),
     /*  581797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581804 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  581814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581818 */     GIR_RootConstrainSelectedInstOperands,
     /*  581819 */     // GIR_Coverage, 30554,
     /*  581819 */     GIR_EraseRootFromParent_Done,
     /*  581820 */   // Label 8948: @581820
     /*  581820 */   GIM_Try, /*On fail goto*//*Label 8949*/ GIMT_Encode4(581874), // Rule ID 30555 //
     /*  581825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  581828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  581833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581848 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  581848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581858 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581872 */     GIR_RootConstrainSelectedInstOperands,
     /*  581873 */     // GIR_Coverage, 30555,
     /*  581873 */     GIR_EraseRootFromParent_Done,
     /*  581874 */   // Label 8949: @581874
     /*  581874 */   GIM_Try, /*On fail goto*//*Label 8950*/ GIMT_Encode4(581928), // Rule ID 30556 //
     /*  581879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  581882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  581887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581902 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  581902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581912 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581926 */     GIR_RootConstrainSelectedInstOperands,
     /*  581927 */     // GIR_Coverage, 30556,
     /*  581927 */     GIR_EraseRootFromParent_Done,
     /*  581928 */   // Label 8950: @581928
     /*  581928 */   GIM_Try, /*On fail goto*//*Label 8951*/ GIMT_Encode4(581982), // Rule ID 30557 //
     /*  581933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  581936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  581941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  581949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  581956 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  581956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  581959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  581961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  581966 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  581968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  581973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  581976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  581980 */     GIR_RootConstrainSelectedInstOperands,
     /*  581981 */     // GIR_Coverage, 30557,
     /*  581981 */     GIR_EraseRootFromParent_Done,
     /*  581982 */   // Label 8951: @581982
     /*  581982 */   GIM_Try, /*On fail goto*//*Label 8952*/ GIMT_Encode4(582036), // Rule ID 30558 //
     /*  581987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  581990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  581995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  581999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  582010 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  582010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  582013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  582020 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  582022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  582030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582034 */     GIR_RootConstrainSelectedInstOperands,
     /*  582035 */     // GIR_Coverage, 30558,
     /*  582035 */     GIR_EraseRootFromParent_Done,
     /*  582036 */   // Label 8952: @582036
     /*  582036 */   GIM_Try, /*On fail goto*//*Label 8953*/ GIMT_Encode4(582090), // Rule ID 30559 //
     /*  582041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  582044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  582049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  582064 */     // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_i64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  582064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
     /*  582067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  582074 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  582076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  582084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582088 */     GIR_RootConstrainSelectedInstOperands,
     /*  582089 */     // GIR_Coverage, 30559,
     /*  582089 */     GIR_EraseRootFromParent_Done,
     /*  582090 */   // Label 8953: @582090
     /*  582090 */   GIM_Try, /*On fail goto*//*Label 8954*/ GIMT_Encode4(582149), // Rule ID 13305 //
     /*  582095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  582098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582105 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  582118 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR),
     /*  582121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582126 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582147 */     GIR_RootConstrainSelectedInstOperands,
     /*  582148 */     // GIR_Coverage, 13305,
     /*  582148 */     GIR_EraseRootFromParent_Done,
     /*  582149 */   // Label 8954: @582149
     /*  582149 */   GIM_Try, /*On fail goto*//*Label 8955*/ GIMT_Encode4(582208), // Rule ID 13306 //
     /*  582154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  582157 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582164 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  582177 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR),
     /*  582180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582185 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582206 */     GIR_RootConstrainSelectedInstOperands,
     /*  582207 */     // GIR_Coverage, 13306,
     /*  582207 */     GIR_EraseRootFromParent_Done,
     /*  582208 */   // Label 8955: @582208
     /*  582208 */   GIM_Try, /*On fail goto*//*Label 8956*/ GIMT_Encode4(582267), // Rule ID 13307 //
     /*  582213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  582216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  582236 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR),
     /*  582239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582244 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582265 */     GIR_RootConstrainSelectedInstOperands,
     /*  582266 */     // GIR_Coverage, 13307,
     /*  582266 */     GIR_EraseRootFromParent_Done,
     /*  582267 */   // Label 8956: @582267
     /*  582267 */   GIM_Try, /*On fail goto*//*Label 8957*/ GIMT_Encode4(582326), // Rule ID 13308 //
     /*  582272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  582275 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582282 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582284 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582288 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  582295 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR),
     /*  582298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582303 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582324 */     GIR_RootConstrainSelectedInstOperands,
     /*  582325 */     // GIR_Coverage, 13308,
     /*  582325 */     GIR_EraseRootFromParent_Done,
     /*  582326 */   // Label 8957: @582326
     /*  582326 */   GIM_Try, /*On fail goto*//*Label 8958*/ GIMT_Encode4(582385), // Rule ID 13309 //
     /*  582331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  582334 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582341 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  582354 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR),
     /*  582357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582362 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582383 */     GIR_RootConstrainSelectedInstOperands,
     /*  582384 */     // GIR_Coverage, 13309,
     /*  582384 */     GIR_EraseRootFromParent_Done,
     /*  582385 */   // Label 8958: @582385
     /*  582385 */   GIM_Try, /*On fail goto*//*Label 8959*/ GIMT_Encode4(582448), // Rule ID 13315 //
     /*  582390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  582393 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  582415 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  582418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582425 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582446 */     GIR_RootConstrainSelectedInstOperands,
     /*  582447 */     // GIR_Coverage, 13315,
     /*  582447 */     GIR_EraseRootFromParent_Done,
     /*  582448 */   // Label 8959: @582448
     /*  582448 */   GIM_Try, /*On fail goto*//*Label 8960*/ GIMT_Encode4(582511), // Rule ID 13316 //
     /*  582453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  582456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  582478 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  582481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582488 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582509 */     GIR_RootConstrainSelectedInstOperands,
     /*  582510 */     // GIR_Coverage, 13316,
     /*  582510 */     GIR_EraseRootFromParent_Done,
     /*  582511 */   // Label 8960: @582511
     /*  582511 */   GIM_Try, /*On fail goto*//*Label 8961*/ GIMT_Encode4(582574), // Rule ID 13317 //
     /*  582516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  582519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  582541 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  582544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582551 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582572 */     GIR_RootConstrainSelectedInstOperands,
     /*  582573 */     // GIR_Coverage, 13317,
     /*  582573 */     GIR_EraseRootFromParent_Done,
     /*  582574 */   // Label 8961: @582574
     /*  582574 */   GIM_Try, /*On fail goto*//*Label 8962*/ GIMT_Encode4(582637), // Rule ID 13318 //
     /*  582579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  582582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582593 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  582604 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  582607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582614 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582635 */     GIR_RootConstrainSelectedInstOperands,
     /*  582636 */     // GIR_Coverage, 13318,
     /*  582636 */     GIR_EraseRootFromParent_Done,
     /*  582637 */   // Label 8962: @582637
     /*  582637 */   GIM_Try, /*On fail goto*//*Label 8963*/ GIMT_Encode4(582700), // Rule ID 13319 //
     /*  582642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  582645 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  582667 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  582667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  582670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  582677 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  582684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  582689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  582694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582698 */     GIR_RootConstrainSelectedInstOperands,
     /*  582699 */     // GIR_Coverage, 13319,
     /*  582699 */     GIR_EraseRootFromParent_Done,
     /*  582700 */   // Label 8963: @582700
     /*  582700 */   GIM_Try, /*On fail goto*//*Label 8964*/ GIMT_Encode4(582752), // Rule ID 13300 //
     /*  582705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  582708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582715 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  582728 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  582728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2),
     /*  582731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  582736 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  582746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582750 */     GIR_RootConstrainSelectedInstOperands,
     /*  582751 */     // GIR_Coverage, 13300,
     /*  582751 */     GIR_EraseRootFromParent_Done,
     /*  582752 */   // Label 8964: @582752
     /*  582752 */   GIM_Try, /*On fail goto*//*Label 8965*/ GIMT_Encode4(582804), // Rule ID 13301 //
     /*  582757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  582760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  582780 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  582780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2),
     /*  582783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  582788 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  582798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582802 */     GIR_RootConstrainSelectedInstOperands,
     /*  582803 */     // GIR_Coverage, 13301,
     /*  582803 */     GIR_EraseRootFromParent_Done,
     /*  582804 */   // Label 8965: @582804
     /*  582804 */   GIM_Try, /*On fail goto*//*Label 8966*/ GIMT_Encode4(582856), // Rule ID 13302 //
     /*  582809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  582812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582819 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  582832 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  582832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2),
     /*  582835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  582840 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  582850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582854 */     GIR_RootConstrainSelectedInstOperands,
     /*  582855 */     // GIR_Coverage, 13302,
     /*  582855 */     GIR_EraseRootFromParent_Done,
     /*  582856 */   // Label 8966: @582856
     /*  582856 */   GIM_Try, /*On fail goto*//*Label 8967*/ GIMT_Encode4(582908), // Rule ID 13303 //
     /*  582861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  582864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582871 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  582884 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  582884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2),
     /*  582887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  582892 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  582902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582906 */     GIR_RootConstrainSelectedInstOperands,
     /*  582907 */     // GIR_Coverage, 13303,
     /*  582907 */     GIR_EraseRootFromParent_Done,
     /*  582908 */   // Label 8967: @582908
     /*  582908 */   GIM_Try, /*On fail goto*//*Label 8968*/ GIMT_Encode4(582960), // Rule ID 13304 //
     /*  582913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  582916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582923 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  582925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  582936 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  582936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2),
     /*  582939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  582944 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  582946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  582951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  582954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  582958 */     GIR_RootConstrainSelectedInstOperands,
     /*  582959 */     // GIR_Coverage, 13304,
     /*  582959 */     GIR_EraseRootFromParent_Done,
     /*  582960 */   // Label 8968: @582960
     /*  582960 */   GIM_Try, /*On fail goto*//*Label 8969*/ GIMT_Encode4(583016), // Rule ID 13310 //
     /*  582965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  582968 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  582975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  582979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  582983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  582990 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  582990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN),
     /*  582993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  582995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  583000 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  583007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  583010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583014 */     GIR_RootConstrainSelectedInstOperands,
     /*  583015 */     // GIR_Coverage, 13310,
     /*  583015 */     GIR_EraseRootFromParent_Done,
     /*  583016 */   // Label 8969: @583016
     /*  583016 */   GIM_Try, /*On fail goto*//*Label 8970*/ GIMT_Encode4(583072), // Rule ID 13311 //
     /*  583021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  583024 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  583046 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  583046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN),
     /*  583049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  583056 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  583063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  583066 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583070 */     GIR_RootConstrainSelectedInstOperands,
     /*  583071 */     // GIR_Coverage, 13311,
     /*  583071 */     GIR_EraseRootFromParent_Done,
     /*  583072 */   // Label 8970: @583072
     /*  583072 */   GIM_Try, /*On fail goto*//*Label 8971*/ GIMT_Encode4(583128), // Rule ID 13312 //
     /*  583077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  583080 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583091 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  583102 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  583102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN),
     /*  583105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  583112 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  583119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  583122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583126 */     GIR_RootConstrainSelectedInstOperands,
     /*  583127 */     // GIR_Coverage, 13312,
     /*  583127 */     GIR_EraseRootFromParent_Done,
     /*  583128 */   // Label 8971: @583128
     /*  583128 */   GIM_Try, /*On fail goto*//*Label 8972*/ GIMT_Encode4(583184), // Rule ID 13313 //
     /*  583133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  583136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  583158 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  583158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN),
     /*  583161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  583168 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  583175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  583178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583182 */     GIR_RootConstrainSelectedInstOperands,
     /*  583183 */     // GIR_Coverage, 13313,
     /*  583183 */     GIR_EraseRootFromParent_Done,
     /*  583184 */   // Label 8972: @583184
     /*  583184 */   GIM_Try, /*On fail goto*//*Label 8973*/ GIMT_Encode4(583240), // Rule ID 13314 //
     /*  583189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  583192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  583214 */     // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  583214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN),
     /*  583217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  583224 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  583231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  583234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583238 */     GIR_RootConstrainSelectedInstOperands,
     /*  583239 */     // GIR_Coverage, 13314,
     /*  583239 */     GIR_EraseRootFromParent_Done,
     /*  583240 */   // Label 8973: @583240
     /*  583240 */   GIM_Try, /*On fail goto*//*Label 8974*/ GIMT_Encode4(583300), // Rule ID 10897 //
     /*  583245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  583248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583256 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583269 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583277 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583298 */     GIR_RootConstrainSelectedInstOperands,
     /*  583299 */     // GIR_Coverage, 10897,
     /*  583299 */     GIR_EraseRootFromParent_Done,
     /*  583300 */   // Label 8974: @583300
     /*  583300 */   GIM_Try, /*On fail goto*//*Label 8975*/ GIMT_Encode4(583360), // Rule ID 10898 //
     /*  583305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  583308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583316 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583329 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583337 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583358 */     GIR_RootConstrainSelectedInstOperands,
     /*  583359 */     // GIR_Coverage, 10898,
     /*  583359 */     GIR_EraseRootFromParent_Done,
     /*  583360 */   // Label 8975: @583360
     /*  583360 */   GIM_Try, /*On fail goto*//*Label 8976*/ GIMT_Encode4(583420), // Rule ID 10899 //
     /*  583365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  583368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583376 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583389 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583397 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583418 */     GIR_RootConstrainSelectedInstOperands,
     /*  583419 */     // GIR_Coverage, 10899,
     /*  583419 */     GIR_EraseRootFromParent_Done,
     /*  583420 */   // Label 8976: @583420
     /*  583420 */   GIM_Try, /*On fail goto*//*Label 8977*/ GIMT_Encode4(583480), // Rule ID 10900 //
     /*  583425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  583428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583436 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583449 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583457 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583478 */     GIR_RootConstrainSelectedInstOperands,
     /*  583479 */     // GIR_Coverage, 10900,
     /*  583479 */     GIR_EraseRootFromParent_Done,
     /*  583480 */   // Label 8977: @583480
     /*  583480 */   GIM_Try, /*On fail goto*//*Label 8978*/ GIMT_Encode4(583540), // Rule ID 10901 //
     /*  583485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  583488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583496 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583509 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583517 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583538 */     GIR_RootConstrainSelectedInstOperands,
     /*  583539 */     // GIR_Coverage, 10901,
     /*  583539 */     GIR_EraseRootFromParent_Done,
     /*  583540 */   // Label 8978: @583540
     /*  583540 */   GIM_Try, /*On fail goto*//*Label 8979*/ GIMT_Encode4(583599), // Rule ID 11453 //
     /*  583545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  583548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583555 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583568 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583576 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583597 */     GIR_RootConstrainSelectedInstOperands,
     /*  583598 */     // GIR_Coverage, 11453,
     /*  583598 */     GIR_EraseRootFromParent_Done,
     /*  583599 */   // Label 8979: @583599
     /*  583599 */   GIM_Try, /*On fail goto*//*Label 8980*/ GIMT_Encode4(583658), // Rule ID 11454 //
     /*  583604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  583607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583614 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583627 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583635 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583656 */     GIR_RootConstrainSelectedInstOperands,
     /*  583657 */     // GIR_Coverage, 11454,
     /*  583657 */     GIR_EraseRootFromParent_Done,
     /*  583658 */   // Label 8980: @583658
     /*  583658 */   GIM_Try, /*On fail goto*//*Label 8981*/ GIMT_Encode4(583717), // Rule ID 11455 //
     /*  583663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  583666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583673 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583686 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583694 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583715 */     GIR_RootConstrainSelectedInstOperands,
     /*  583716 */     // GIR_Coverage, 11455,
     /*  583716 */     GIR_EraseRootFromParent_Done,
     /*  583717 */   // Label 8981: @583717
     /*  583717 */   GIM_Try, /*On fail goto*//*Label 8982*/ GIMT_Encode4(583776), // Rule ID 11456 //
     /*  583722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  583725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583732 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583745 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583753 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583774 */     GIR_RootConstrainSelectedInstOperands,
     /*  583775 */     // GIR_Coverage, 11456,
     /*  583775 */     GIR_EraseRootFromParent_Done,
     /*  583776 */   // Label 8982: @583776
     /*  583776 */   GIM_Try, /*On fail goto*//*Label 8983*/ GIMT_Encode4(583835), // Rule ID 11457 //
     /*  583781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  583784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583791 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  583793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  583804 */     // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR),
     /*  583807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583812 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583833 */     GIR_RootConstrainSelectedInstOperands,
     /*  583834 */     // GIR_Coverage, 11457,
     /*  583834 */     GIR_EraseRootFromParent_Done,
     /*  583835 */   // Label 8983: @583835
     /*  583835 */   GIM_Try, /*On fail goto*//*Label 8984*/ GIMT_Encode4(583899), // Rule ID 10887 //
     /*  583840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  583843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  583866 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  583869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583876 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583897 */     GIR_RootConstrainSelectedInstOperands,
     /*  583898 */     // GIR_Coverage, 10887,
     /*  583898 */     GIR_EraseRootFromParent_Done,
     /*  583899 */   // Label 8984: @583899
     /*  583899 */   GIM_Try, /*On fail goto*//*Label 8985*/ GIMT_Encode4(583963), // Rule ID 10888 //
     /*  583904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  583907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  583930 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  583933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  583940 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  583942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  583947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  583952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  583957 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  583961 */     GIR_RootConstrainSelectedInstOperands,
     /*  583962 */     // GIR_Coverage, 10888,
     /*  583962 */     GIR_EraseRootFromParent_Done,
     /*  583963 */   // Label 8985: @583963
     /*  583963 */   GIM_Try, /*On fail goto*//*Label 8986*/ GIMT_Encode4(584027), // Rule ID 10889 //
     /*  583968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  583971 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  583979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  583983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  583987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  583994 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  583994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  583997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  583999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584004 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584025 */     GIR_RootConstrainSelectedInstOperands,
     /*  584026 */     // GIR_Coverage, 10889,
     /*  584026 */     GIR_EraseRootFromParent_Done,
     /*  584027 */   // Label 8986: @584027
     /*  584027 */   GIM_Try, /*On fail goto*//*Label 8987*/ GIMT_Encode4(584091), // Rule ID 10890 //
     /*  584032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  584035 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584058 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584068 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584089 */     GIR_RootConstrainSelectedInstOperands,
     /*  584090 */     // GIR_Coverage, 10890,
     /*  584090 */     GIR_EraseRootFromParent_Done,
     /*  584091 */   // Label 8987: @584091
     /*  584091 */   GIM_Try, /*On fail goto*//*Label 8988*/ GIMT_Encode4(584155), // Rule ID 10891 //
     /*  584096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  584099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584122 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584132 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584153 */     GIR_RootConstrainSelectedInstOperands,
     /*  584154 */     // GIR_Coverage, 10891,
     /*  584154 */     GIR_EraseRootFromParent_Done,
     /*  584155 */   // Label 8988: @584155
     /*  584155 */   GIM_Try, /*On fail goto*//*Label 8989*/ GIMT_Encode4(584218), // Rule ID 11443 //
     /*  584160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  584163 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584185 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584195 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584216 */     GIR_RootConstrainSelectedInstOperands,
     /*  584217 */     // GIR_Coverage, 11443,
     /*  584217 */     GIR_EraseRootFromParent_Done,
     /*  584218 */   // Label 8989: @584218
     /*  584218 */   GIM_Try, /*On fail goto*//*Label 8990*/ GIMT_Encode4(584281), // Rule ID 11444 //
     /*  584223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  584226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584248 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584258 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584279 */     GIR_RootConstrainSelectedInstOperands,
     /*  584280 */     // GIR_Coverage, 11444,
     /*  584280 */     GIR_EraseRootFromParent_Done,
     /*  584281 */   // Label 8990: @584281
     /*  584281 */   GIM_Try, /*On fail goto*//*Label 8991*/ GIMT_Encode4(584344), // Rule ID 11445 //
     /*  584286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  584289 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584311 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584321 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584342 */     GIR_RootConstrainSelectedInstOperands,
     /*  584343 */     // GIR_Coverage, 11445,
     /*  584343 */     GIR_EraseRootFromParent_Done,
     /*  584344 */   // Label 8991: @584344
     /*  584344 */   GIM_Try, /*On fail goto*//*Label 8992*/ GIMT_Encode4(584407), // Rule ID 11446 //
     /*  584349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  584352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584374 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584384 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584405 */     GIR_RootConstrainSelectedInstOperands,
     /*  584406 */     // GIR_Coverage, 11446,
     /*  584406 */     GIR_EraseRootFromParent_Done,
     /*  584407 */   // Label 8992: @584407
     /*  584407 */   GIM_Try, /*On fail goto*//*Label 8993*/ GIMT_Encode4(584470), // Rule ID 11447 //
     /*  584412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  584415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  584426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  584437 */     // (atomic_swap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  584437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_SADDR_RTN),
     /*  584440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  584442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  584447 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  584454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  584459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  584464 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584468 */     GIR_RootConstrainSelectedInstOperands,
     /*  584469 */     // GIR_Coverage, 11447,
     /*  584469 */     GIR_EraseRootFromParent_Done,
     /*  584470 */   // Label 8993: @584470
     /*  584470 */   GIM_Try, /*On fail goto*//*Label 8994*/ GIMT_Encode4(584523), // Rule ID 10892 //
     /*  584475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  584478 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584486 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584499 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584507 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584521 */     GIR_RootConstrainSelectedInstOperands,
     /*  584522 */     // GIR_Coverage, 10892,
     /*  584522 */     GIR_EraseRootFromParent_Done,
     /*  584523 */   // Label 8994: @584523
     /*  584523 */   GIM_Try, /*On fail goto*//*Label 8995*/ GIMT_Encode4(584576), // Rule ID 10893 //
     /*  584528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  584531 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584539 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584552 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584560 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584574 */     GIR_RootConstrainSelectedInstOperands,
     /*  584575 */     // GIR_Coverage, 10893,
     /*  584575 */     GIR_EraseRootFromParent_Done,
     /*  584576 */   // Label 8995: @584576
     /*  584576 */   GIM_Try, /*On fail goto*//*Label 8996*/ GIMT_Encode4(584629), // Rule ID 10894 //
     /*  584581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  584584 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584592 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584605 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584613 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584627 */     GIR_RootConstrainSelectedInstOperands,
     /*  584628 */     // GIR_Coverage, 10894,
     /*  584628 */     GIR_EraseRootFromParent_Done,
     /*  584629 */   // Label 8996: @584629
     /*  584629 */   GIM_Try, /*On fail goto*//*Label 8997*/ GIMT_Encode4(584682), // Rule ID 10895 //
     /*  584634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  584637 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584645 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584658 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584666 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584673 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584676 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584680 */     GIR_RootConstrainSelectedInstOperands,
     /*  584681 */     // GIR_Coverage, 10895,
     /*  584681 */     GIR_EraseRootFromParent_Done,
     /*  584682 */   // Label 8997: @584682
     /*  584682 */   GIM_Try, /*On fail goto*//*Label 8998*/ GIMT_Encode4(584735), // Rule ID 10896 //
     /*  584687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  584690 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584698 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584711 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584719 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584733 */     GIR_RootConstrainSelectedInstOperands,
     /*  584734 */     // GIR_Coverage, 10896,
     /*  584734 */     GIR_EraseRootFromParent_Done,
     /*  584735 */   // Label 8998: @584735
     /*  584735 */   GIM_Try, /*On fail goto*//*Label 8999*/ GIMT_Encode4(584787), // Rule ID 11448 //
     /*  584740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  584743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584750 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584763 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584771 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584785 */     GIR_RootConstrainSelectedInstOperands,
     /*  584786 */     // GIR_Coverage, 11448,
     /*  584786 */     GIR_EraseRootFromParent_Done,
     /*  584787 */   // Label 8999: @584787
     /*  584787 */   GIM_Try, /*On fail goto*//*Label 9000*/ GIMT_Encode4(584839), // Rule ID 11449 //
     /*  584792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  584795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584802 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584815 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584823 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584837 */     GIR_RootConstrainSelectedInstOperands,
     /*  584838 */     // GIR_Coverage, 11449,
     /*  584838 */     GIR_EraseRootFromParent_Done,
     /*  584839 */   // Label 9000: @584839
     /*  584839 */   GIM_Try, /*On fail goto*//*Label 9001*/ GIMT_Encode4(584891), // Rule ID 11450 //
     /*  584844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  584847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584854 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584867 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584875 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584889 */     GIR_RootConstrainSelectedInstOperands,
     /*  584890 */     // GIR_Coverage, 11450,
     /*  584890 */     GIR_EraseRootFromParent_Done,
     /*  584891 */   // Label 9001: @584891
     /*  584891 */   GIM_Try, /*On fail goto*//*Label 9002*/ GIMT_Encode4(584943), // Rule ID 11451 //
     /*  584896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  584899 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584906 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584919 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584927 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584941 */     GIR_RootConstrainSelectedInstOperands,
     /*  584942 */     // GIR_Coverage, 11451,
     /*  584942 */     GIR_EraseRootFromParent_Done,
     /*  584943 */   // Label 9002: @584943
     /*  584943 */   GIM_Try, /*On fail goto*//*Label 9003*/ GIMT_Encode4(584995), // Rule ID 11452 //
     /*  584948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  584951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  584958 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  584960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  584964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  584971 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  584971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
     /*  584974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  584979 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  584981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  584986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  584989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  584993 */     GIR_RootConstrainSelectedInstOperands,
     /*  584994 */     // GIR_Coverage, 11452,
     /*  584994 */     GIR_EraseRootFromParent_Done,
     /*  584995 */   // Label 9003: @584995
     /*  584995 */   GIM_Try, /*On fail goto*//*Label 9004*/ GIMT_Encode4(585052), // Rule ID 10882 //
     /*  585000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  585003 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585026 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585036 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585050 */     GIR_RootConstrainSelectedInstOperands,
     /*  585051 */     // GIR_Coverage, 10882,
     /*  585051 */     GIR_EraseRootFromParent_Done,
     /*  585052 */   // Label 9004: @585052
     /*  585052 */   GIM_Try, /*On fail goto*//*Label 9005*/ GIMT_Encode4(585109), // Rule ID 10883 //
     /*  585057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  585060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585083 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585093 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585107 */     GIR_RootConstrainSelectedInstOperands,
     /*  585108 */     // GIR_Coverage, 10883,
     /*  585108 */     GIR_EraseRootFromParent_Done,
     /*  585109 */   // Label 9005: @585109
     /*  585109 */   GIM_Try, /*On fail goto*//*Label 9006*/ GIMT_Encode4(585166), // Rule ID 10884 //
     /*  585114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  585117 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585133 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585140 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585150 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585164 */     GIR_RootConstrainSelectedInstOperands,
     /*  585165 */     // GIR_Coverage, 10884,
     /*  585165 */     GIR_EraseRootFromParent_Done,
     /*  585166 */   // Label 9006: @585166
     /*  585166 */   GIM_Try, /*On fail goto*//*Label 9007*/ GIMT_Encode4(585223), // Rule ID 10885 //
     /*  585171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  585174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585186 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585190 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585197 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585207 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585217 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585221 */     GIR_RootConstrainSelectedInstOperands,
     /*  585222 */     // GIR_Coverage, 10885,
     /*  585222 */     GIR_EraseRootFromParent_Done,
     /*  585223 */   // Label 9007: @585223
     /*  585223 */   GIM_Try, /*On fail goto*//*Label 9008*/ GIMT_Encode4(585280), // Rule ID 10886 //
     /*  585228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  585231 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585254 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585264 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585278 */     GIR_RootConstrainSelectedInstOperands,
     /*  585279 */     // GIR_Coverage, 10886,
     /*  585279 */     GIR_EraseRootFromParent_Done,
     /*  585280 */   // Label 9008: @585280
     /*  585280 */   GIM_Try, /*On fail goto*//*Label 9009*/ GIMT_Encode4(585336), // Rule ID 11438 //
     /*  585285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  585288 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585299 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585303 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585310 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585320 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585334 */     GIR_RootConstrainSelectedInstOperands,
     /*  585335 */     // GIR_Coverage, 11438,
     /*  585335 */     GIR_EraseRootFromParent_Done,
     /*  585336 */   // Label 9009: @585336
     /*  585336 */   GIM_Try, /*On fail goto*//*Label 9010*/ GIMT_Encode4(585392), // Rule ID 11439 //
     /*  585341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  585344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585366 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585376 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585390 */     GIR_RootConstrainSelectedInstOperands,
     /*  585391 */     // GIR_Coverage, 11439,
     /*  585391 */     GIR_EraseRootFromParent_Done,
     /*  585392 */   // Label 9010: @585392
     /*  585392 */   GIM_Try, /*On fail goto*//*Label 9011*/ GIMT_Encode4(585448), // Rule ID 11440 //
     /*  585397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  585400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585422 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585432 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585446 */     GIR_RootConstrainSelectedInstOperands,
     /*  585447 */     // GIR_Coverage, 11440,
     /*  585447 */     GIR_EraseRootFromParent_Done,
     /*  585448 */   // Label 9011: @585448
     /*  585448 */   GIM_Try, /*On fail goto*//*Label 9012*/ GIMT_Encode4(585504), // Rule ID 11441 //
     /*  585453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  585456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585478 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585488 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585502 */     GIR_RootConstrainSelectedInstOperands,
     /*  585503 */     // GIR_Coverage, 11441,
     /*  585503 */     GIR_EraseRootFromParent_Done,
     /*  585504 */   // Label 9012: @585504
     /*  585504 */   GIM_Try, /*On fail goto*//*Label 9013*/ GIMT_Encode4(585560), // Rule ID 11442 //
     /*  585509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  585512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  585523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  585534 */     // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  585534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
     /*  585537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  585539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  585544 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  585546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  585551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  585554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585558 */     GIR_RootConstrainSelectedInstOperands,
     /*  585559 */     // GIR_Coverage, 11442,
     /*  585559 */     GIR_EraseRootFromParent_Done,
     /*  585560 */   // Label 9013: @585560
     /*  585560 */   GIM_Reject,
     /*  585561 */ // Label 8898: @585561
     /*  585561 */ GIM_Reject,
     /*  585562 */ // Label 8805: @585562
     /*  585562 */ GIM_Reject,
     /*  585563 */ // Label 20: @585563
     /*  585563 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 9016*/ GIMT_Encode4(599174),
     /*  585574 */ /*GILLT_s32*//*Label 9014*/ GIMT_Encode4(585582),
     /*  585578 */ /*GILLT_s64*//*Label 9015*/ GIMT_Encode4(591674),
     /*  585582 */ // Label 9014: @585582
     /*  585582 */ GIM_Try, /*On fail goto*//*Label 9017*/ GIMT_Encode4(591673),
     /*  585587 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  585590 */   GIM_Try, /*On fail goto*//*Label 9018*/ GIMT_Encode4(585652), // Rule ID 20778 //
     /*  585595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  585598 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585605 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585618 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64),
     /*  585621 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  585628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  585633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  585638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  585643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  585646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585650 */     GIR_RootConstrainSelectedInstOperands,
     /*  585651 */     // GIR_Coverage, 20778,
     /*  585651 */     GIR_EraseRootFromParent_Done,
     /*  585652 */   // Label 9018: @585652
     /*  585652 */   GIM_Try, /*On fail goto*//*Label 9019*/ GIMT_Encode4(585714), // Rule ID 20779 //
     /*  585657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  585660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585667 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585673 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585680 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64),
     /*  585683 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  585690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  585695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  585700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  585705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  585708 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585712 */     GIR_RootConstrainSelectedInstOperands,
     /*  585713 */     // GIR_Coverage, 20779,
     /*  585713 */     GIR_EraseRootFromParent_Done,
     /*  585714 */   // Label 9019: @585714
     /*  585714 */   GIM_Try, /*On fail goto*//*Label 9020*/ GIMT_Encode4(585776), // Rule ID 20780 //
     /*  585719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  585722 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585729 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585731 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585735 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585742 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64),
     /*  585745 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  585752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  585757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  585762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  585767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  585770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585774 */     GIR_RootConstrainSelectedInstOperands,
     /*  585775 */     // GIR_Coverage, 20780,
     /*  585775 */     GIR_EraseRootFromParent_Done,
     /*  585776 */   // Label 9020: @585776
     /*  585776 */   GIM_Try, /*On fail goto*//*Label 9021*/ GIMT_Encode4(585838), // Rule ID 20781 //
     /*  585781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  585784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585791 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585804 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64),
     /*  585807 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  585814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  585819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  585824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  585829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  585832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585836 */     GIR_RootConstrainSelectedInstOperands,
     /*  585837 */     // GIR_Coverage, 20781,
     /*  585837 */     GIR_EraseRootFromParent_Done,
     /*  585838 */   // Label 9021: @585838
     /*  585838 */   GIM_Try, /*On fail goto*//*Label 9022*/ GIMT_Encode4(585900), // Rule ID 20782 //
     /*  585843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  585846 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585853 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585866 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64),
     /*  585869 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  585876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  585881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  585886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  585891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  585894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585898 */     GIR_RootConstrainSelectedInstOperands,
     /*  585899 */     // GIR_Coverage, 20782,
     /*  585899 */     GIR_EraseRootFromParent_Done,
     /*  585900 */   // Label 9022: @585900
     /*  585900 */   GIM_Try, /*On fail goto*//*Label 9023*/ GIMT_Encode4(585962), // Rule ID 20798 //
     /*  585905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  585908 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585915 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585928 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64),
     /*  585931 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  585938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  585943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  585948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  585953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  585956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  585960 */     GIR_RootConstrainSelectedInstOperands,
     /*  585961 */     // GIR_Coverage, 20798,
     /*  585961 */     GIR_EraseRootFromParent_Done,
     /*  585962 */   // Label 9023: @585962
     /*  585962 */   GIM_Try, /*On fail goto*//*Label 9024*/ GIMT_Encode4(586024), // Rule ID 20799 //
     /*  585967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  585970 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  585977 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  585979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  585983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  585990 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  585990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64),
     /*  585993 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  585995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  586018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586022 */     GIR_RootConstrainSelectedInstOperands,
     /*  586023 */     // GIR_Coverage, 20799,
     /*  586023 */     GIR_EraseRootFromParent_Done,
     /*  586024 */   // Label 9024: @586024
     /*  586024 */   GIM_Try, /*On fail goto*//*Label 9025*/ GIMT_Encode4(586086), // Rule ID 20800 //
     /*  586029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  586032 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586039 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  586041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586052 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64),
     /*  586055 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  586080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586084 */     GIR_RootConstrainSelectedInstOperands,
     /*  586085 */     // GIR_Coverage, 20800,
     /*  586085 */     GIR_EraseRootFromParent_Done,
     /*  586086 */   // Label 9025: @586086
     /*  586086 */   GIM_Try, /*On fail goto*//*Label 9026*/ GIMT_Encode4(586148), // Rule ID 20801 //
     /*  586091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  586094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586101 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  586103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586114 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64),
     /*  586117 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  586142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586146 */     GIR_RootConstrainSelectedInstOperands,
     /*  586147 */     // GIR_Coverage, 20801,
     /*  586147 */     GIR_EraseRootFromParent_Done,
     /*  586148 */   // Label 9026: @586148
     /*  586148 */   GIM_Try, /*On fail goto*//*Label 9027*/ GIMT_Encode4(586210), // Rule ID 20802 //
     /*  586153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  586156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586163 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  586165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586176 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64),
     /*  586179 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  586204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586208 */     GIR_RootConstrainSelectedInstOperands,
     /*  586209 */     // GIR_Coverage, 20802,
     /*  586209 */     GIR_EraseRootFromParent_Done,
     /*  586210 */   // Label 9027: @586210
     /*  586210 */   GIM_Try, /*On fail goto*//*Label 9028*/ GIMT_Encode4(586276), // Rule ID 20768 //
     /*  586215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  586218 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586240 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN),
     /*  586243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586245 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586274 */     GIR_RootConstrainSelectedInstOperands,
     /*  586275 */     // GIR_Coverage, 20768,
     /*  586275 */     GIR_EraseRootFromParent_Done,
     /*  586276 */   // Label 9028: @586276
     /*  586276 */   GIM_Try, /*On fail goto*//*Label 9029*/ GIMT_Encode4(586342), // Rule ID 20769 //
     /*  586281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  586284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586306 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN),
     /*  586309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586311 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586340 */     GIR_RootConstrainSelectedInstOperands,
     /*  586341 */     // GIR_Coverage, 20769,
     /*  586341 */     GIR_EraseRootFromParent_Done,
     /*  586342 */   // Label 9029: @586342
     /*  586342 */   GIM_Try, /*On fail goto*//*Label 9030*/ GIMT_Encode4(586408), // Rule ID 20770 //
     /*  586347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  586350 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586365 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586372 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN),
     /*  586375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586377 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586402 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586406 */     GIR_RootConstrainSelectedInstOperands,
     /*  586407 */     // GIR_Coverage, 20770,
     /*  586407 */     GIR_EraseRootFromParent_Done,
     /*  586408 */   // Label 9030: @586408
     /*  586408 */   GIM_Try, /*On fail goto*//*Label 9031*/ GIMT_Encode4(586474), // Rule ID 20771 //
     /*  586413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  586416 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586438 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN),
     /*  586441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586443 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586472 */     GIR_RootConstrainSelectedInstOperands,
     /*  586473 */     // GIR_Coverage, 20771,
     /*  586473 */     GIR_EraseRootFromParent_Done,
     /*  586474 */   // Label 9031: @586474
     /*  586474 */   GIM_Try, /*On fail goto*//*Label 9032*/ GIMT_Encode4(586540), // Rule ID 20772 //
     /*  586479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  586482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586504 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN),
     /*  586507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586509 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586538 */     GIR_RootConstrainSelectedInstOperands,
     /*  586539 */     // GIR_Coverage, 20772,
     /*  586539 */     GIR_EraseRootFromParent_Done,
     /*  586540 */   // Label 9032: @586540
     /*  586540 */   GIM_Try, /*On fail goto*//*Label 9033*/ GIMT_Encode4(586606), // Rule ID 20788 //
     /*  586545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  586548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586570 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN),
     /*  586573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586575 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586604 */     GIR_RootConstrainSelectedInstOperands,
     /*  586605 */     // GIR_Coverage, 20788,
     /*  586605 */     GIR_EraseRootFromParent_Done,
     /*  586606 */   // Label 9033: @586606
     /*  586606 */   GIM_Try, /*On fail goto*//*Label 9034*/ GIMT_Encode4(586672), // Rule ID 20789 //
     /*  586611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  586614 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586636 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN),
     /*  586639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586641 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586670 */     GIR_RootConstrainSelectedInstOperands,
     /*  586671 */     // GIR_Coverage, 20789,
     /*  586671 */     GIR_EraseRootFromParent_Done,
     /*  586672 */   // Label 9034: @586672
     /*  586672 */   GIM_Try, /*On fail goto*//*Label 9035*/ GIMT_Encode4(586738), // Rule ID 20790 //
     /*  586677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  586680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586702 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN),
     /*  586705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586707 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586732 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586736 */     GIR_RootConstrainSelectedInstOperands,
     /*  586737 */     // GIR_Coverage, 20790,
     /*  586737 */     GIR_EraseRootFromParent_Done,
     /*  586738 */   // Label 9035: @586738
     /*  586738 */   GIM_Try, /*On fail goto*//*Label 9036*/ GIMT_Encode4(586804), // Rule ID 20791 //
     /*  586743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  586746 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586757 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586768 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN),
     /*  586771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586773 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586802 */     GIR_RootConstrainSelectedInstOperands,
     /*  586803 */     // GIR_Coverage, 20791,
     /*  586803 */     GIR_EraseRootFromParent_Done,
     /*  586804 */   // Label 9036: @586804
     /*  586804 */   GIM_Try, /*On fail goto*//*Label 9037*/ GIMT_Encode4(586870), // Rule ID 20792 //
     /*  586809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  586812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  586823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  586834 */     // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN),
     /*  586837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  586839 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  586846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  586856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  586861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  586864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586868 */     GIR_RootConstrainSelectedInstOperands,
     /*  586869 */     // GIR_Coverage, 20792,
     /*  586869 */     GIR_EraseRootFromParent_Done,
     /*  586870 */   // Label 9037: @586870
     /*  586870 */   GIM_Try, /*On fail goto*//*Label 9038*/ GIMT_Encode4(586927), // Rule ID 20773 //
     /*  586875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  586878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586885 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  586887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  586898 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
     /*  586901 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  586913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  586918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  586921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586925 */     GIR_RootConstrainSelectedInstOperands,
     /*  586926 */     // GIR_Coverage, 20773,
     /*  586926 */     GIR_EraseRootFromParent_Done,
     /*  586927 */   // Label 9038: @586927
     /*  586927 */   GIM_Try, /*On fail goto*//*Label 9039*/ GIMT_Encode4(586984), // Rule ID 20774 //
     /*  586932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  586935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586942 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  586944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  586948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  586955 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  586955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
     /*  586958 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  586960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  586965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  586970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  586975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  586978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  586982 */     GIR_RootConstrainSelectedInstOperands,
     /*  586983 */     // GIR_Coverage, 20774,
     /*  586983 */     GIR_EraseRootFromParent_Done,
     /*  586984 */   // Label 9039: @586984
     /*  586984 */   GIM_Try, /*On fail goto*//*Label 9040*/ GIMT_Encode4(587041), // Rule ID 20775 //
     /*  586989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  586992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  586999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587012 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
     /*  587015 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587035 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587039 */     GIR_RootConstrainSelectedInstOperands,
     /*  587040 */     // GIR_Coverage, 20775,
     /*  587040 */     GIR_EraseRootFromParent_Done,
     /*  587041 */   // Label 9040: @587041
     /*  587041 */   GIM_Try, /*On fail goto*//*Label 9041*/ GIMT_Encode4(587098), // Rule ID 20776 //
     /*  587046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  587049 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587056 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587058 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587062 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587069 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
     /*  587072 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587096 */     GIR_RootConstrainSelectedInstOperands,
     /*  587097 */     // GIR_Coverage, 20776,
     /*  587097 */     GIR_EraseRootFromParent_Done,
     /*  587098 */   // Label 9041: @587098
     /*  587098 */   GIM_Try, /*On fail goto*//*Label 9042*/ GIMT_Encode4(587155), // Rule ID 20777 //
     /*  587103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  587106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587113 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587126 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
     /*  587129 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587153 */     GIR_RootConstrainSelectedInstOperands,
     /*  587154 */     // GIR_Coverage, 20777,
     /*  587154 */     GIR_EraseRootFromParent_Done,
     /*  587155 */   // Label 9042: @587155
     /*  587155 */   GIM_Try, /*On fail goto*//*Label 9043*/ GIMT_Encode4(587212), // Rule ID 20793 //
     /*  587160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  587163 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587170 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587183 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
     /*  587186 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587210 */     GIR_RootConstrainSelectedInstOperands,
     /*  587211 */     // GIR_Coverage, 20793,
     /*  587211 */     GIR_EraseRootFromParent_Done,
     /*  587212 */   // Label 9043: @587212
     /*  587212 */   GIM_Try, /*On fail goto*//*Label 9044*/ GIMT_Encode4(587269), // Rule ID 20794 //
     /*  587217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  587220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587227 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587240 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
     /*  587243 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587263 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587267 */     GIR_RootConstrainSelectedInstOperands,
     /*  587268 */     // GIR_Coverage, 20794,
     /*  587268 */     GIR_EraseRootFromParent_Done,
     /*  587269 */   // Label 9044: @587269
     /*  587269 */   GIM_Try, /*On fail goto*//*Label 9045*/ GIMT_Encode4(587326), // Rule ID 20795 //
     /*  587274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  587277 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587284 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587286 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587290 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587297 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
     /*  587300 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587324 */     GIR_RootConstrainSelectedInstOperands,
     /*  587325 */     // GIR_Coverage, 20795,
     /*  587325 */     GIR_EraseRootFromParent_Done,
     /*  587326 */   // Label 9045: @587326
     /*  587326 */   GIM_Try, /*On fail goto*//*Label 9046*/ GIMT_Encode4(587383), // Rule ID 20796 //
     /*  587331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  587334 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587341 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587354 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
     /*  587357 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587381 */     GIR_RootConstrainSelectedInstOperands,
     /*  587382 */     // GIR_Coverage, 20796,
     /*  587382 */     GIR_EraseRootFromParent_Done,
     /*  587383 */   // Label 9046: @587383
     /*  587383 */   GIM_Try, /*On fail goto*//*Label 9047*/ GIMT_Encode4(587440), // Rule ID 20797 //
     /*  587388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  587391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587398 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  587400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587411 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
     /*  587414 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  587434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587438 */     GIR_RootConstrainSelectedInstOperands,
     /*  587439 */     // GIR_Coverage, 20797,
     /*  587439 */     GIR_EraseRootFromParent_Done,
     /*  587440 */   // Label 9047: @587440
     /*  587440 */   GIM_Try, /*On fail goto*//*Label 9048*/ GIMT_Encode4(587501), // Rule ID 20763 //
     /*  587445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  587448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587459 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587470 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
     /*  587473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587475 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587499 */     GIR_RootConstrainSelectedInstOperands,
     /*  587500 */     // GIR_Coverage, 20763,
     /*  587500 */     GIR_EraseRootFromParent_Done,
     /*  587501 */   // Label 9048: @587501
     /*  587501 */   GIM_Try, /*On fail goto*//*Label 9049*/ GIMT_Encode4(587562), // Rule ID 20764 //
     /*  587506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  587509 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587531 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
     /*  587534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587536 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587560 */     GIR_RootConstrainSelectedInstOperands,
     /*  587561 */     // GIR_Coverage, 20764,
     /*  587561 */     GIR_EraseRootFromParent_Done,
     /*  587562 */   // Label 9049: @587562
     /*  587562 */   GIM_Try, /*On fail goto*//*Label 9050*/ GIMT_Encode4(587623), // Rule ID 20765 //
     /*  587567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  587570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587592 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
     /*  587595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587597 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587621 */     GIR_RootConstrainSelectedInstOperands,
     /*  587622 */     // GIR_Coverage, 20765,
     /*  587622 */     GIR_EraseRootFromParent_Done,
     /*  587623 */   // Label 9050: @587623
     /*  587623 */   GIM_Try, /*On fail goto*//*Label 9051*/ GIMT_Encode4(587684), // Rule ID 20766 //
     /*  587628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  587631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587653 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
     /*  587656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587658 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587682 */     GIR_RootConstrainSelectedInstOperands,
     /*  587683 */     // GIR_Coverage, 20766,
     /*  587683 */     GIR_EraseRootFromParent_Done,
     /*  587684 */   // Label 9051: @587684
     /*  587684 */   GIM_Try, /*On fail goto*//*Label 9052*/ GIMT_Encode4(587745), // Rule ID 20767 //
     /*  587689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  587692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587703 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587714 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
     /*  587717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587719 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587743 */     GIR_RootConstrainSelectedInstOperands,
     /*  587744 */     // GIR_Coverage, 20767,
     /*  587744 */     GIR_EraseRootFromParent_Done,
     /*  587745 */   // Label 9052: @587745
     /*  587745 */   GIM_Try, /*On fail goto*//*Label 9053*/ GIMT_Encode4(587806), // Rule ID 20783 //
     /*  587750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  587753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587764 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587768 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587775 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
     /*  587778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587780 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587804 */     GIR_RootConstrainSelectedInstOperands,
     /*  587805 */     // GIR_Coverage, 20783,
     /*  587805 */     GIR_EraseRootFromParent_Done,
     /*  587806 */   // Label 9053: @587806
     /*  587806 */   GIM_Try, /*On fail goto*//*Label 9054*/ GIMT_Encode4(587867), // Rule ID 20784 //
     /*  587811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  587814 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587836 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
     /*  587839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587841 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587861 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587865 */     GIR_RootConstrainSelectedInstOperands,
     /*  587866 */     // GIR_Coverage, 20784,
     /*  587866 */     GIR_EraseRootFromParent_Done,
     /*  587867 */   // Label 9054: @587867
     /*  587867 */   GIM_Try, /*On fail goto*//*Label 9055*/ GIMT_Encode4(587928), // Rule ID 20785 //
     /*  587872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  587875 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587897 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
     /*  587900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587902 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587926 */     GIR_RootConstrainSelectedInstOperands,
     /*  587927 */     // GIR_Coverage, 20785,
     /*  587927 */     GIR_EraseRootFromParent_Done,
     /*  587928 */   // Label 9055: @587928
     /*  587928 */   GIM_Try, /*On fail goto*//*Label 9056*/ GIMT_Encode4(587989), // Rule ID 20786 //
     /*  587933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  587936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  587943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  587947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  587951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  587958 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  587958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
     /*  587961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  587963 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  587965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  587970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  587975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  587980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  587983 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  587987 */     GIR_RootConstrainSelectedInstOperands,
     /*  587988 */     // GIR_Coverage, 20786,
     /*  587988 */     GIR_EraseRootFromParent_Done,
     /*  587989 */   // Label 9056: @587989
     /*  587989 */   GIM_Try, /*On fail goto*//*Label 9057*/ GIMT_Encode4(588050), // Rule ID 20787 //
     /*  587994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  587997 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  588004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  588008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  588019 */     // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  588019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
     /*  588022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  588024 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  588026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  588031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  588036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  588041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588044 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588048 */     GIR_RootConstrainSelectedInstOperands,
     /*  588049 */     // GIR_Coverage, 20787,
     /*  588049 */     GIR_EraseRootFromParent_Done,
     /*  588050 */   // Label 9057: @588050
     /*  588050 */   GIM_Try, /*On fail goto*//*Label 9058*/ GIMT_Encode4(588100), // Rule ID 28745 //
     /*  588055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  588058 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588063 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588076 */     // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_i32>>  =>  (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9),
     /*  588079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588084 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588098 */     GIR_RootConstrainSelectedInstOperands,
     /*  588099 */     // GIR_Coverage, 28745,
     /*  588099 */     GIR_EraseRootFromParent_Done,
     /*  588100 */   // Label 9058: @588100
     /*  588100 */   GIM_Try, /*On fail goto*//*Label 9059*/ GIMT_Encode4(588150), // Rule ID 28746 //
     /*  588105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  588108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588113 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588126 */     // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_i32>>  =>  (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9),
     /*  588129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588134 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588148 */     GIR_RootConstrainSelectedInstOperands,
     /*  588149 */     // GIR_Coverage, 28746,
     /*  588149 */     GIR_EraseRootFromParent_Done,
     /*  588150 */   // Label 9059: @588150
     /*  588150 */   GIM_Try, /*On fail goto*//*Label 9060*/ GIMT_Encode4(588200), // Rule ID 28747 //
     /*  588155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  588158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588163 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588176 */     // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_i32>>  =>  (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9),
     /*  588179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588184 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588198 */     GIR_RootConstrainSelectedInstOperands,
     /*  588199 */     // GIR_Coverage, 28747,
     /*  588199 */     GIR_EraseRootFromParent_Done,
     /*  588200 */   // Label 9060: @588200
     /*  588200 */   GIM_Try, /*On fail goto*//*Label 9061*/ GIMT_Encode4(588250), // Rule ID 28748 //
     /*  588205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  588208 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588213 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588215 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588226 */     // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_i32>>  =>  (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9),
     /*  588229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588234 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588248 */     GIR_RootConstrainSelectedInstOperands,
     /*  588249 */     // GIR_Coverage, 28748,
     /*  588249 */     GIR_EraseRootFromParent_Done,
     /*  588250 */   // Label 9061: @588250
     /*  588250 */   GIM_Try, /*On fail goto*//*Label 9062*/ GIMT_Encode4(588300), // Rule ID 28749 //
     /*  588255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  588258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588263 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588276 */     // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_i32>>  =>  (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9),
     /*  588279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588284 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588298 */     GIR_RootConstrainSelectedInstOperands,
     /*  588299 */     // GIR_Coverage, 28749,
     /*  588299 */     GIR_EraseRootFromParent_Done,
     /*  588300 */   // Label 9062: @588300
     /*  588300 */   GIM_Try, /*On fail goto*//*Label 9063*/ GIMT_Encode4(588350), // Rule ID 28751 //
     /*  588305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  588308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588313 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588326 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588334 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588348 */     GIR_RootConstrainSelectedInstOperands,
     /*  588349 */     // GIR_Coverage, 28751,
     /*  588349 */     GIR_EraseRootFromParent_Done,
     /*  588350 */   // Label 9063: @588350
     /*  588350 */   GIM_Try, /*On fail goto*//*Label 9064*/ GIMT_Encode4(588400), // Rule ID 28752 //
     /*  588355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  588358 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588363 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588376 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588384 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588398 */     GIR_RootConstrainSelectedInstOperands,
     /*  588399 */     // GIR_Coverage, 28752,
     /*  588399 */     GIR_EraseRootFromParent_Done,
     /*  588400 */   // Label 9064: @588400
     /*  588400 */   GIM_Try, /*On fail goto*//*Label 9065*/ GIMT_Encode4(588450), // Rule ID 28753 //
     /*  588405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  588408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588413 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588426 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588434 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588448 */     GIR_RootConstrainSelectedInstOperands,
     /*  588449 */     // GIR_Coverage, 28753,
     /*  588449 */     GIR_EraseRootFromParent_Done,
     /*  588450 */   // Label 9065: @588450
     /*  588450 */   GIM_Try, /*On fail goto*//*Label 9066*/ GIMT_Encode4(588500), // Rule ID 28754 //
     /*  588455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  588458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588463 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588476 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588484 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588498 */     GIR_RootConstrainSelectedInstOperands,
     /*  588499 */     // GIR_Coverage, 28754,
     /*  588499 */     GIR_EraseRootFromParent_Done,
     /*  588500 */   // Label 9066: @588500
     /*  588500 */   GIM_Try, /*On fail goto*//*Label 9067*/ GIMT_Encode4(588550), // Rule ID 28755 //
     /*  588505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  588508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588513 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588515 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588519 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588526 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588534 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588548 */     GIR_RootConstrainSelectedInstOperands,
     /*  588549 */     // GIR_Coverage, 28755,
     /*  588549 */     GIR_EraseRootFromParent_Done,
     /*  588550 */   // Label 9067: @588550
     /*  588550 */   GIM_Try, /*On fail goto*//*Label 9068*/ GIMT_Encode4(588600), // Rule ID 28757 //
     /*  588555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  588558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  588563 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588576 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  588576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588584 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588598 */     GIR_RootConstrainSelectedInstOperands,
     /*  588599 */     // GIR_Coverage, 28757,
     /*  588599 */     GIR_EraseRootFromParent_Done,
     /*  588600 */   // Label 9068: @588600
     /*  588600 */   GIM_Try, /*On fail goto*//*Label 9069*/ GIMT_Encode4(588650), // Rule ID 28758 //
     /*  588605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  588608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  588613 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588626 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  588626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588634 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588644 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588648 */     GIR_RootConstrainSelectedInstOperands,
     /*  588649 */     // GIR_Coverage, 28758,
     /*  588649 */     GIR_EraseRootFromParent_Done,
     /*  588650 */   // Label 9069: @588650
     /*  588650 */   GIM_Try, /*On fail goto*//*Label 9070*/ GIMT_Encode4(588700), // Rule ID 28759 //
     /*  588655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  588658 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  588663 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588676 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  588676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588684 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588698 */     GIR_RootConstrainSelectedInstOperands,
     /*  588699 */     // GIR_Coverage, 28759,
     /*  588699 */     GIR_EraseRootFromParent_Done,
     /*  588700 */   // Label 9070: @588700
     /*  588700 */   GIM_Try, /*On fail goto*//*Label 9071*/ GIMT_Encode4(588750), // Rule ID 28760 //
     /*  588705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  588708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  588713 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588726 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  588726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588734 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588748 */     GIR_RootConstrainSelectedInstOperands,
     /*  588749 */     // GIR_Coverage, 28760,
     /*  588749 */     GIR_EraseRootFromParent_Done,
     /*  588750 */   // Label 9071: @588750
     /*  588750 */   GIM_Try, /*On fail goto*//*Label 9072*/ GIMT_Encode4(588800), // Rule ID 28761 //
     /*  588755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  588758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  588763 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588776 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  588776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
     /*  588779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588784 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588798 */     GIR_RootConstrainSelectedInstOperands,
     /*  588799 */     // GIR_Coverage, 28761,
     /*  588799 */     GIR_EraseRootFromParent_Done,
     /*  588800 */   // Label 9072: @588800
     /*  588800 */   GIM_Try, /*On fail goto*//*Label 9073*/ GIMT_Encode4(588854), // Rule ID 28744 //
     /*  588805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  588808 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  588817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588828 */     // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_i32>>  =>  (DS_ADD_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32_gfx9),
     /*  588831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  588833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588838 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588848 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588852 */     GIR_RootConstrainSelectedInstOperands,
     /*  588853 */     // GIR_Coverage, 28744,
     /*  588853 */     GIR_EraseRootFromParent_Done,
     /*  588854 */   // Label 9073: @588854
     /*  588854 */   GIM_Try, /*On fail goto*//*Label 9074*/ GIMT_Encode4(588908), // Rule ID 28750 //
     /*  588859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  588862 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  588867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  588871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588882 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_i32>>  =>  (DS_ADD_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  588882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32),
     /*  588885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  588887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588892 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  588902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588906 */     GIR_RootConstrainSelectedInstOperands,
     /*  588907 */     // GIR_Coverage, 28750,
     /*  588907 */     GIR_EraseRootFromParent_Done,
     /*  588908 */   // Label 9074: @588908
     /*  588908 */   GIM_Try, /*On fail goto*//*Label 9075*/ GIMT_Encode4(588962), // Rule ID 28756 //
     /*  588913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  588916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  588921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  588925 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  588936 */     // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_i32>>  =>  (DS_ADD_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  588936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32),
     /*  588939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  588941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  588946 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  588948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  588953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  588956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  588960 */     GIR_RootConstrainSelectedInstOperands,
     /*  588961 */     // GIR_Coverage, 28756,
     /*  588961 */     GIR_EraseRootFromParent_Done,
     /*  588962 */   // Label 9075: @588962
     /*  588962 */   GIM_Try, /*On fail goto*//*Label 9076*/ GIMT_Encode4(589021), // Rule ID 9397 //
     /*  588967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  588970 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  588977 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  588979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  588983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  588990 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  588990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR),
     /*  588993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  588998 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589015 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589019 */     GIR_RootConstrainSelectedInstOperands,
     /*  589020 */     // GIR_Coverage, 9397,
     /*  589020 */     GIR_EraseRootFromParent_Done,
     /*  589021 */   // Label 9076: @589021
     /*  589021 */   GIM_Try, /*On fail goto*//*Label 9077*/ GIMT_Encode4(589080), // Rule ID 9398 //
     /*  589026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  589029 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589036 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  589049 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR),
     /*  589052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589057 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589078 */     GIR_RootConstrainSelectedInstOperands,
     /*  589079 */     // GIR_Coverage, 9398,
     /*  589079 */     GIR_EraseRootFromParent_Done,
     /*  589080 */   // Label 9077: @589080
     /*  589080 */   GIM_Try, /*On fail goto*//*Label 9078*/ GIMT_Encode4(589139), // Rule ID 9399 //
     /*  589085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  589088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589095 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589101 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  589108 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR),
     /*  589111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589116 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589133 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589137 */     GIR_RootConstrainSelectedInstOperands,
     /*  589138 */     // GIR_Coverage, 9399,
     /*  589138 */     GIR_EraseRootFromParent_Done,
     /*  589139 */   // Label 9078: @589139
     /*  589139 */   GIM_Try, /*On fail goto*//*Label 9079*/ GIMT_Encode4(589198), // Rule ID 9400 //
     /*  589144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  589147 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589154 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589156 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589160 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  589167 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR),
     /*  589170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589175 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589196 */     GIR_RootConstrainSelectedInstOperands,
     /*  589197 */     // GIR_Coverage, 9400,
     /*  589197 */     GIR_EraseRootFromParent_Done,
     /*  589198 */   // Label 9079: @589198
     /*  589198 */   GIM_Try, /*On fail goto*//*Label 9080*/ GIMT_Encode4(589257), // Rule ID 9401 //
     /*  589203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  589206 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589213 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589215 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  589226 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR),
     /*  589229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589234 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589255 */     GIR_RootConstrainSelectedInstOperands,
     /*  589256 */     // GIR_Coverage, 9401,
     /*  589256 */     GIR_EraseRootFromParent_Done,
     /*  589257 */   // Label 9080: @589257
     /*  589257 */   GIM_Try, /*On fail goto*//*Label 9081*/ GIMT_Encode4(589320), // Rule ID 9407 //
     /*  589262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  589265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  589276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589280 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  589287 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN),
     /*  589290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  589292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589297 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589318 */     GIR_RootConstrainSelectedInstOperands,
     /*  589319 */     // GIR_Coverage, 9407,
     /*  589319 */     GIR_EraseRootFromParent_Done,
     /*  589320 */   // Label 9081: @589320
     /*  589320 */   GIM_Try, /*On fail goto*//*Label 9082*/ GIMT_Encode4(589372), // Rule ID 9392 //
     /*  589325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  589328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589335 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589348 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD),
     /*  589351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589356 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  589366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589370 */     GIR_RootConstrainSelectedInstOperands,
     /*  589371 */     // GIR_Coverage, 9392,
     /*  589371 */     GIR_EraseRootFromParent_Done,
     /*  589372 */   // Label 9082: @589372
     /*  589372 */   GIM_Try, /*On fail goto*//*Label 9083*/ GIMT_Encode4(589424), // Rule ID 9393 //
     /*  589377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  589380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589400 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD),
     /*  589403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589408 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  589418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589422 */     GIR_RootConstrainSelectedInstOperands,
     /*  589423 */     // GIR_Coverage, 9393,
     /*  589423 */     GIR_EraseRootFromParent_Done,
     /*  589424 */   // Label 9083: @589424
     /*  589424 */   GIM_Try, /*On fail goto*//*Label 9084*/ GIMT_Encode4(589476), // Rule ID 9394 //
     /*  589429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  589432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589439 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589452 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD),
     /*  589455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589460 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  589470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589474 */     GIR_RootConstrainSelectedInstOperands,
     /*  589475 */     // GIR_Coverage, 9394,
     /*  589475 */     GIR_EraseRootFromParent_Done,
     /*  589476 */   // Label 9084: @589476
     /*  589476 */   GIM_Try, /*On fail goto*//*Label 9085*/ GIMT_Encode4(589528), // Rule ID 9395 //
     /*  589481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  589484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589491 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589504 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD),
     /*  589507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589512 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  589522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589526 */     GIR_RootConstrainSelectedInstOperands,
     /*  589527 */     // GIR_Coverage, 9395,
     /*  589527 */     GIR_EraseRootFromParent_Done,
     /*  589528 */   // Label 9085: @589528
     /*  589528 */   GIM_Try, /*On fail goto*//*Label 9086*/ GIMT_Encode4(589580), // Rule ID 9396 //
     /*  589533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  589536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589543 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589556 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (GLOBAL_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD),
     /*  589559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589564 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  589574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589578 */     GIR_RootConstrainSelectedInstOperands,
     /*  589579 */     // GIR_Coverage, 9396,
     /*  589579 */     GIR_EraseRootFromParent_Done,
     /*  589580 */   // Label 9086: @589580
     /*  589580 */   GIM_Try, /*On fail goto*//*Label 9087*/ GIMT_Encode4(589636), // Rule ID 9402 //
     /*  589585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  589588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  589599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589610 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN),
     /*  589613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  589615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589620 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  589630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589634 */     GIR_RootConstrainSelectedInstOperands,
     /*  589635 */     // GIR_Coverage, 9402,
     /*  589635 */     GIR_EraseRootFromParent_Done,
     /*  589636 */   // Label 9087: @589636
     /*  589636 */   GIM_Try, /*On fail goto*//*Label 9088*/ GIMT_Encode4(589692), // Rule ID 9403 //
     /*  589641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  589644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  589655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589666 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN),
     /*  589669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  589671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589676 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  589686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589690 */     GIR_RootConstrainSelectedInstOperands,
     /*  589691 */     // GIR_Coverage, 9403,
     /*  589691 */     GIR_EraseRootFromParent_Done,
     /*  589692 */   // Label 9088: @589692
     /*  589692 */   GIM_Try, /*On fail goto*//*Label 9089*/ GIMT_Encode4(589748), // Rule ID 9404 //
     /*  589697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  589700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  589711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589722 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN),
     /*  589725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  589727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589732 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  589742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589746 */     GIR_RootConstrainSelectedInstOperands,
     /*  589747 */     // GIR_Coverage, 9404,
     /*  589747 */     GIR_EraseRootFromParent_Done,
     /*  589748 */   // Label 9089: @589748
     /*  589748 */   GIM_Try, /*On fail goto*//*Label 9090*/ GIMT_Encode4(589804), // Rule ID 9405 //
     /*  589753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  589756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  589767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589778 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN),
     /*  589781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  589783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589788 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  589798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589802 */     GIR_RootConstrainSelectedInstOperands,
     /*  589803 */     // GIR_Coverage, 9405,
     /*  589803 */     GIR_EraseRootFromParent_Done,
     /*  589804 */   // Label 9090: @589804
     /*  589804 */   GIM_Try, /*On fail goto*//*Label 9091*/ GIMT_Encode4(589860), // Rule ID 9406 //
     /*  589809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  589812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  589823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  589834 */     // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  589834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN),
     /*  589837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  589839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  589844 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  589851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  589854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589858 */     GIR_RootConstrainSelectedInstOperands,
     /*  589859 */     // GIR_Coverage, 9406,
     /*  589859 */     GIR_EraseRootFromParent_Done,
     /*  589860 */   // Label 9091: @589860
     /*  589860 */   GIM_Try, /*On fail goto*//*Label 9092*/ GIMT_Encode4(589920), // Rule ID 9299 //
     /*  589865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  589868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589876 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589878 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  589889 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  589892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589897 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589918 */     GIR_RootConstrainSelectedInstOperands,
     /*  589919 */     // GIR_Coverage, 9299,
     /*  589919 */     GIR_EraseRootFromParent_Done,
     /*  589920 */   // Label 9092: @589920
     /*  589920 */   GIM_Try, /*On fail goto*//*Label 9093*/ GIMT_Encode4(589980), // Rule ID 9300 //
     /*  589925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  589928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589936 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  589942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  589949 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  589949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  589952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  589957 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  589959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  589964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  589969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  589974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  589978 */     GIR_RootConstrainSelectedInstOperands,
     /*  589979 */     // GIR_Coverage, 9300,
     /*  589979 */     GIR_EraseRootFromParent_Done,
     /*  589980 */   // Label 9093: @589980
     /*  589980 */   GIM_Try, /*On fail goto*//*Label 9094*/ GIMT_Encode4(590040), // Rule ID 9301 //
     /*  589985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  589988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  589996 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  589998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590009 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590017 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590038 */     GIR_RootConstrainSelectedInstOperands,
     /*  590039 */     // GIR_Coverage, 9301,
     /*  590039 */     GIR_EraseRootFromParent_Done,
     /*  590040 */   // Label 9094: @590040
     /*  590040 */   GIM_Try, /*On fail goto*//*Label 9095*/ GIMT_Encode4(590100), // Rule ID 9302 //
     /*  590045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  590048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590056 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590058 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590062 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590069 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590077 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590098 */     GIR_RootConstrainSelectedInstOperands,
     /*  590099 */     // GIR_Coverage, 9302,
     /*  590099 */     GIR_EraseRootFromParent_Done,
     /*  590100 */   // Label 9095: @590100
     /*  590100 */   GIM_Try, /*On fail goto*//*Label 9096*/ GIMT_Encode4(590160), // Rule ID 9303 //
     /*  590105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  590108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590116 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590118 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590122 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590129 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590137 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590158 */     GIR_RootConstrainSelectedInstOperands,
     /*  590159 */     // GIR_Coverage, 9303,
     /*  590159 */     GIR_EraseRootFromParent_Done,
     /*  590160 */   // Label 9096: @590160
     /*  590160 */   GIM_Try, /*On fail goto*//*Label 9097*/ GIMT_Encode4(590219), // Rule ID 11037 //
     /*  590165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  590168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590175 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590188 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590196 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590213 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590217 */     GIR_RootConstrainSelectedInstOperands,
     /*  590218 */     // GIR_Coverage, 11037,
     /*  590218 */     GIR_EraseRootFromParent_Done,
     /*  590219 */   // Label 9097: @590219
     /*  590219 */   GIM_Try, /*On fail goto*//*Label 9098*/ GIMT_Encode4(590278), // Rule ID 11038 //
     /*  590224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  590227 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590234 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590236 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590240 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590247 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590255 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590276 */     GIR_RootConstrainSelectedInstOperands,
     /*  590277 */     // GIR_Coverage, 11038,
     /*  590277 */     GIR_EraseRootFromParent_Done,
     /*  590278 */   // Label 9098: @590278
     /*  590278 */   GIM_Try, /*On fail goto*//*Label 9099*/ GIMT_Encode4(590337), // Rule ID 11039 //
     /*  590283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  590286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590293 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590306 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590314 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590335 */     GIR_RootConstrainSelectedInstOperands,
     /*  590336 */     // GIR_Coverage, 11039,
     /*  590336 */     GIR_EraseRootFromParent_Done,
     /*  590337 */   // Label 9099: @590337
     /*  590337 */   GIM_Try, /*On fail goto*//*Label 9100*/ GIMT_Encode4(590396), // Rule ID 11040 //
     /*  590342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  590345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590352 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590354 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590358 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590365 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590373 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590394 */     GIR_RootConstrainSelectedInstOperands,
     /*  590395 */     // GIR_Coverage, 11040,
     /*  590395 */     GIR_EraseRootFromParent_Done,
     /*  590396 */   // Label 9100: @590396
     /*  590396 */   GIM_Try, /*On fail goto*//*Label 9101*/ GIMT_Encode4(590455), // Rule ID 11041 //
     /*  590401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  590404 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590411 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590413 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590417 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  590424 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR),
     /*  590427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590432 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590449 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590453 */     GIR_RootConstrainSelectedInstOperands,
     /*  590454 */     // GIR_Coverage, 11041,
     /*  590454 */     GIR_EraseRootFromParent_Done,
     /*  590455 */   // Label 9101: @590455
     /*  590455 */   GIM_Try, /*On fail goto*//*Label 9102*/ GIMT_Encode4(590519), // Rule ID 9309 //
     /*  590460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  590463 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  590475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  590486 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR_RTN),
     /*  590489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  590491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590496 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590517 */     GIR_RootConstrainSelectedInstOperands,
     /*  590518 */     // GIR_Coverage, 9309,
     /*  590518 */     GIR_EraseRootFromParent_Done,
     /*  590519 */   // Label 9102: @590519
     /*  590519 */   GIM_Try, /*On fail goto*//*Label 9103*/ GIMT_Encode4(590582), // Rule ID 11031 //
     /*  590524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  590527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  590538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590542 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  590549 */     // (atomic_load_add:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (FLAT_ATOMIC_ADD_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  590549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_SADDR_RTN),
     /*  590552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  590554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  590559 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  590566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  590571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  590576 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590580 */     GIR_RootConstrainSelectedInstOperands,
     /*  590581 */     // GIR_Coverage, 11031,
     /*  590581 */     GIR_EraseRootFromParent_Done,
     /*  590582 */   // Label 9103: @590582
     /*  590582 */   GIM_Try, /*On fail goto*//*Label 9104*/ GIMT_Encode4(590635), // Rule ID 9294 //
     /*  590587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  590590 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590598 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590611 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590619 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590633 */     GIR_RootConstrainSelectedInstOperands,
     /*  590634 */     // GIR_Coverage, 9294,
     /*  590634 */     GIR_EraseRootFromParent_Done,
     /*  590635 */   // Label 9104: @590635
     /*  590635 */   GIM_Try, /*On fail goto*//*Label 9105*/ GIMT_Encode4(590688), // Rule ID 9295 //
     /*  590640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  590643 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590651 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590664 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590672 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590686 */     GIR_RootConstrainSelectedInstOperands,
     /*  590687 */     // GIR_Coverage, 9295,
     /*  590687 */     GIR_EraseRootFromParent_Done,
     /*  590688 */   // Label 9105: @590688
     /*  590688 */   GIM_Try, /*On fail goto*//*Label 9106*/ GIMT_Encode4(590741), // Rule ID 9296 //
     /*  590693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  590696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590704 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590717 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590725 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590735 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590739 */     GIR_RootConstrainSelectedInstOperands,
     /*  590740 */     // GIR_Coverage, 9296,
     /*  590740 */     GIR_EraseRootFromParent_Done,
     /*  590741 */   // Label 9106: @590741
     /*  590741 */   GIM_Try, /*On fail goto*//*Label 9107*/ GIMT_Encode4(590794), // Rule ID 9297 //
     /*  590746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  590749 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590757 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590770 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590778 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590792 */     GIR_RootConstrainSelectedInstOperands,
     /*  590793 */     // GIR_Coverage, 9297,
     /*  590793 */     GIR_EraseRootFromParent_Done,
     /*  590794 */   // Label 9107: @590794
     /*  590794 */   GIM_Try, /*On fail goto*//*Label 9108*/ GIMT_Encode4(590847), // Rule ID 9298 //
     /*  590799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  590802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590810 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590816 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590823 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590831 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590845 */     GIR_RootConstrainSelectedInstOperands,
     /*  590846 */     // GIR_Coverage, 9298,
     /*  590846 */     GIR_EraseRootFromParent_Done,
     /*  590847 */   // Label 9108: @590847
     /*  590847 */   GIM_Try, /*On fail goto*//*Label 9109*/ GIMT_Encode4(590899), // Rule ID 11032 //
     /*  590852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  590855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590862 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590875 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590883 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590897 */     GIR_RootConstrainSelectedInstOperands,
     /*  590898 */     // GIR_Coverage, 11032,
     /*  590898 */     GIR_EraseRootFromParent_Done,
     /*  590899 */   // Label 9109: @590899
     /*  590899 */   GIM_Try, /*On fail goto*//*Label 9110*/ GIMT_Encode4(590951), // Rule ID 11033 //
     /*  590904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  590907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590914 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590927 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590935 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  590949 */     GIR_RootConstrainSelectedInstOperands,
     /*  590950 */     // GIR_Coverage, 11033,
     /*  590950 */     GIR_EraseRootFromParent_Done,
     /*  590951 */   // Label 9110: @590951
     /*  590951 */   GIM_Try, /*On fail goto*//*Label 9111*/ GIMT_Encode4(591003), // Rule ID 11034 //
     /*  590956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  590959 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  590966 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  590968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  590972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  590979 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  590979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  590982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  590987 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  590989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  590994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  590997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591001 */     GIR_RootConstrainSelectedInstOperands,
     /*  591002 */     // GIR_Coverage, 11034,
     /*  591002 */     GIR_EraseRootFromParent_Done,
     /*  591003 */   // Label 9111: @591003
     /*  591003 */   GIM_Try, /*On fail goto*//*Label 9112*/ GIMT_Encode4(591055), // Rule ID 11035 //
     /*  591008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  591011 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591018 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591031 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  591034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591039 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591053 */     GIR_RootConstrainSelectedInstOperands,
     /*  591054 */     // GIR_Coverage, 11035,
     /*  591054 */     GIR_EraseRootFromParent_Done,
     /*  591055 */   // Label 9112: @591055
     /*  591055 */   GIM_Try, /*On fail goto*//*Label 9113*/ GIMT_Encode4(591107), // Rule ID 11036 //
     /*  591060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  591063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591070 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591083 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>>  =>  (FLAT_ATOMIC_ADD VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
     /*  591086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591091 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591105 */     GIR_RootConstrainSelectedInstOperands,
     /*  591106 */     // GIR_Coverage, 11036,
     /*  591106 */     GIR_EraseRootFromParent_Done,
     /*  591107 */   // Label 9113: @591107
     /*  591107 */   GIM_Try, /*On fail goto*//*Label 9114*/ GIMT_Encode4(591164), // Rule ID 9304 //
     /*  591112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  591115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591138 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591148 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591162 */     GIR_RootConstrainSelectedInstOperands,
     /*  591163 */     // GIR_Coverage, 9304,
     /*  591163 */     GIR_EraseRootFromParent_Done,
     /*  591164 */   // Label 9114: @591164
     /*  591164 */   GIM_Try, /*On fail goto*//*Label 9115*/ GIMT_Encode4(591221), // Rule ID 9305 //
     /*  591169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  591172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591195 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591205 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591212 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591215 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591219 */     GIR_RootConstrainSelectedInstOperands,
     /*  591220 */     // GIR_Coverage, 9305,
     /*  591220 */     GIR_EraseRootFromParent_Done,
     /*  591221 */   // Label 9115: @591221
     /*  591221 */   GIM_Try, /*On fail goto*//*Label 9116*/ GIMT_Encode4(591278), // Rule ID 9306 //
     /*  591226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  591229 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591241 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591252 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591262 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591276 */     GIR_RootConstrainSelectedInstOperands,
     /*  591277 */     // GIR_Coverage, 9306,
     /*  591277 */     GIR_EraseRootFromParent_Done,
     /*  591278 */   // Label 9116: @591278
     /*  591278 */   GIM_Try, /*On fail goto*//*Label 9117*/ GIMT_Encode4(591335), // Rule ID 9307 //
     /*  591283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  591286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591298 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591302 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591309 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591319 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591333 */     GIR_RootConstrainSelectedInstOperands,
     /*  591334 */     // GIR_Coverage, 9307,
     /*  591334 */     GIR_EraseRootFromParent_Done,
     /*  591335 */   // Label 9117: @591335
     /*  591335 */   GIM_Try, /*On fail goto*//*Label 9118*/ GIMT_Encode4(591392), // Rule ID 9308 //
     /*  591340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  591343 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591366 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591376 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591390 */     GIR_RootConstrainSelectedInstOperands,
     /*  591391 */     // GIR_Coverage, 9308,
     /*  591391 */     GIR_EraseRootFromParent_Done,
     /*  591392 */   // Label 9118: @591392
     /*  591392 */   GIM_Try, /*On fail goto*//*Label 9119*/ GIMT_Encode4(591448), // Rule ID 11026 //
     /*  591397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  591400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591422 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591432 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591446 */     GIR_RootConstrainSelectedInstOperands,
     /*  591447 */     // GIR_Coverage, 11026,
     /*  591447 */     GIR_EraseRootFromParent_Done,
     /*  591448 */   // Label 9119: @591448
     /*  591448 */   GIM_Try, /*On fail goto*//*Label 9120*/ GIMT_Encode4(591504), // Rule ID 11027 //
     /*  591453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  591456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591478 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591488 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591502 */     GIR_RootConstrainSelectedInstOperands,
     /*  591503 */     // GIR_Coverage, 11027,
     /*  591503 */     GIR_EraseRootFromParent_Done,
     /*  591504 */   // Label 9120: @591504
     /*  591504 */   GIM_Try, /*On fail goto*//*Label 9121*/ GIMT_Encode4(591560), // Rule ID 11028 //
     /*  591509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  591512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591534 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591544 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591558 */     GIR_RootConstrainSelectedInstOperands,
     /*  591559 */     // GIR_Coverage, 11028,
     /*  591559 */     GIR_EraseRootFromParent_Done,
     /*  591560 */   // Label 9121: @591560
     /*  591560 */   GIM_Try, /*On fail goto*//*Label 9122*/ GIMT_Encode4(591616), // Rule ID 11029 //
     /*  591565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  591568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591590 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591600 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591614 */     GIR_RootConstrainSelectedInstOperands,
     /*  591615 */     // GIR_Coverage, 11029,
     /*  591615 */     GIR_EraseRootFromParent_Done,
     /*  591616 */   // Label 9122: @591616
     /*  591616 */   GIM_Try, /*On fail goto*//*Label 9123*/ GIMT_Encode4(591672), // Rule ID 11030 //
     /*  591621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  591624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  591635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  591646 */     // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  591646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
     /*  591649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  591651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  591656 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  591658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  591663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  591666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591670 */     GIR_RootConstrainSelectedInstOperands,
     /*  591671 */     // GIR_Coverage, 11030,
     /*  591671 */     GIR_EraseRootFromParent_Done,
     /*  591672 */   // Label 9123: @591672
     /*  591672 */   GIM_Reject,
     /*  591673 */ // Label 9017: @591673
     /*  591673 */ GIM_Reject,
     /*  591674 */ // Label 9015: @591674
     /*  591674 */ GIM_Try, /*On fail goto*//*Label 9124*/ GIMT_Encode4(599173),
     /*  591679 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  591682 */   GIM_Try, /*On fail goto*//*Label 9125*/ GIMT_Encode4(591744), // Rule ID 21258 //
     /*  591687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  591690 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591697 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  591710 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  591710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64),
     /*  591713 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  591715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  591720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  591725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  591730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  591735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591742 */     GIR_RootConstrainSelectedInstOperands,
     /*  591743 */     // GIR_Coverage, 21258,
     /*  591743 */     GIR_EraseRootFromParent_Done,
     /*  591744 */   // Label 9125: @591744
     /*  591744 */   GIM_Try, /*On fail goto*//*Label 9126*/ GIMT_Encode4(591806), // Rule ID 21259 //
     /*  591749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  591752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591759 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  591772 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  591772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64),
     /*  591775 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  591777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  591782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  591787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  591792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  591797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591804 */     GIR_RootConstrainSelectedInstOperands,
     /*  591805 */     // GIR_Coverage, 21259,
     /*  591805 */     GIR_EraseRootFromParent_Done,
     /*  591806 */   // Label 9126: @591806
     /*  591806 */   GIM_Try, /*On fail goto*//*Label 9127*/ GIMT_Encode4(591868), // Rule ID 21260 //
     /*  591811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  591814 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591821 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  591834 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  591834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64),
     /*  591837 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  591839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  591844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  591849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  591854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  591859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591866 */     GIR_RootConstrainSelectedInstOperands,
     /*  591867 */     // GIR_Coverage, 21260,
     /*  591867 */     GIR_EraseRootFromParent_Done,
     /*  591868 */   // Label 9127: @591868
     /*  591868 */   GIM_Try, /*On fail goto*//*Label 9128*/ GIMT_Encode4(591930), // Rule ID 21261 //
     /*  591873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  591876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591883 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  591896 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  591896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64),
     /*  591899 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  591901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  591906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  591911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  591916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  591921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591924 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591928 */     GIR_RootConstrainSelectedInstOperands,
     /*  591929 */     // GIR_Coverage, 21261,
     /*  591929 */     GIR_EraseRootFromParent_Done,
     /*  591930 */   // Label 9128: @591930
     /*  591930 */   GIM_Try, /*On fail goto*//*Label 9129*/ GIMT_Encode4(591992), // Rule ID 21262 //
     /*  591935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  591938 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  591945 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  591947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  591951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  591958 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  591958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64),
     /*  591961 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  591963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  591968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  591973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  591978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  591983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  591986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  591990 */     GIR_RootConstrainSelectedInstOperands,
     /*  591991 */     // GIR_Coverage, 21262,
     /*  591991 */     GIR_EraseRootFromParent_Done,
     /*  591992 */   // Label 9129: @591992
     /*  591992 */   GIM_Try, /*On fail goto*//*Label 9130*/ GIMT_Encode4(592054), // Rule ID 21278 //
     /*  591997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  592000 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592007 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  592009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592020 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64),
     /*  592023 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  592048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592052 */     GIR_RootConstrainSelectedInstOperands,
     /*  592053 */     // GIR_Coverage, 21278,
     /*  592053 */     GIR_EraseRootFromParent_Done,
     /*  592054 */   // Label 9130: @592054
     /*  592054 */   GIM_Try, /*On fail goto*//*Label 9131*/ GIMT_Encode4(592116), // Rule ID 21279 //
     /*  592059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  592062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592069 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  592071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592082 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64),
     /*  592085 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  592110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592114 */     GIR_RootConstrainSelectedInstOperands,
     /*  592115 */     // GIR_Coverage, 21279,
     /*  592115 */     GIR_EraseRootFromParent_Done,
     /*  592116 */   // Label 9131: @592116
     /*  592116 */   GIM_Try, /*On fail goto*//*Label 9132*/ GIMT_Encode4(592178), // Rule ID 21280 //
     /*  592121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  592124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592131 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  592133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592144 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64),
     /*  592147 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  592172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592176 */     GIR_RootConstrainSelectedInstOperands,
     /*  592177 */     // GIR_Coverage, 21280,
     /*  592177 */     GIR_EraseRootFromParent_Done,
     /*  592178 */   // Label 9132: @592178
     /*  592178 */   GIM_Try, /*On fail goto*//*Label 9133*/ GIMT_Encode4(592240), // Rule ID 21281 //
     /*  592183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  592186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592193 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  592195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592206 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64),
     /*  592209 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  592234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592238 */     GIR_RootConstrainSelectedInstOperands,
     /*  592239 */     // GIR_Coverage, 21281,
     /*  592239 */     GIR_EraseRootFromParent_Done,
     /*  592240 */   // Label 9133: @592240
     /*  592240 */   GIM_Try, /*On fail goto*//*Label 9134*/ GIMT_Encode4(592302), // Rule ID 21282 //
     /*  592245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  592248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592255 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  592257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592268 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64),
     /*  592271 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  592296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592300 */     GIR_RootConstrainSelectedInstOperands,
     /*  592301 */     // GIR_Coverage, 21282,
     /*  592301 */     GIR_EraseRootFromParent_Done,
     /*  592302 */   // Label 9134: @592302
     /*  592302 */   GIM_Try, /*On fail goto*//*Label 9135*/ GIMT_Encode4(592368), // Rule ID 21248 //
     /*  592307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  592310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592332 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN),
     /*  592335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592337 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592362 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592366 */     GIR_RootConstrainSelectedInstOperands,
     /*  592367 */     // GIR_Coverage, 21248,
     /*  592367 */     GIR_EraseRootFromParent_Done,
     /*  592368 */   // Label 9135: @592368
     /*  592368 */   GIM_Try, /*On fail goto*//*Label 9136*/ GIMT_Encode4(592434), // Rule ID 21249 //
     /*  592373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  592376 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592398 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN),
     /*  592401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592403 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592432 */     GIR_RootConstrainSelectedInstOperands,
     /*  592433 */     // GIR_Coverage, 21249,
     /*  592433 */     GIR_EraseRootFromParent_Done,
     /*  592434 */   // Label 9136: @592434
     /*  592434 */   GIM_Try, /*On fail goto*//*Label 9137*/ GIMT_Encode4(592500), // Rule ID 21250 //
     /*  592439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  592442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592464 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN),
     /*  592467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592469 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592498 */     GIR_RootConstrainSelectedInstOperands,
     /*  592499 */     // GIR_Coverage, 21250,
     /*  592499 */     GIR_EraseRootFromParent_Done,
     /*  592500 */   // Label 9137: @592500
     /*  592500 */   GIM_Try, /*On fail goto*//*Label 9138*/ GIMT_Encode4(592566), // Rule ID 21251 //
     /*  592505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  592508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592530 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN),
     /*  592533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592535 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592560 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592564 */     GIR_RootConstrainSelectedInstOperands,
     /*  592565 */     // GIR_Coverage, 21251,
     /*  592565 */     GIR_EraseRootFromParent_Done,
     /*  592566 */   // Label 9138: @592566
     /*  592566 */   GIM_Try, /*On fail goto*//*Label 9139*/ GIMT_Encode4(592632), // Rule ID 21252 //
     /*  592571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  592574 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592589 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592596 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN),
     /*  592599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592601 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592630 */     GIR_RootConstrainSelectedInstOperands,
     /*  592631 */     // GIR_Coverage, 21252,
     /*  592631 */     GIR_EraseRootFromParent_Done,
     /*  592632 */   // Label 9139: @592632
     /*  592632 */   GIM_Try, /*On fail goto*//*Label 9140*/ GIMT_Encode4(592698), // Rule ID 21268 //
     /*  592637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  592640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592662 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN),
     /*  592665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592667 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592696 */     GIR_RootConstrainSelectedInstOperands,
     /*  592697 */     // GIR_Coverage, 21268,
     /*  592697 */     GIR_EraseRootFromParent_Done,
     /*  592698 */   // Label 9140: @592698
     /*  592698 */   GIM_Try, /*On fail goto*//*Label 9141*/ GIMT_Encode4(592764), // Rule ID 21269 //
     /*  592703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  592706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592728 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN),
     /*  592731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592733 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592762 */     GIR_RootConstrainSelectedInstOperands,
     /*  592763 */     // GIR_Coverage, 21269,
     /*  592763 */     GIR_EraseRootFromParent_Done,
     /*  592764 */   // Label 9141: @592764
     /*  592764 */   GIM_Try, /*On fail goto*//*Label 9142*/ GIMT_Encode4(592830), // Rule ID 21270 //
     /*  592769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  592772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592794 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN),
     /*  592797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592799 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592828 */     GIR_RootConstrainSelectedInstOperands,
     /*  592829 */     // GIR_Coverage, 21270,
     /*  592829 */     GIR_EraseRootFromParent_Done,
     /*  592830 */   // Label 9142: @592830
     /*  592830 */   GIM_Try, /*On fail goto*//*Label 9143*/ GIMT_Encode4(592896), // Rule ID 21271 //
     /*  592835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  592838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592860 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN),
     /*  592863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592865 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592894 */     GIR_RootConstrainSelectedInstOperands,
     /*  592895 */     // GIR_Coverage, 21271,
     /*  592895 */     GIR_EraseRootFromParent_Done,
     /*  592896 */   // Label 9143: @592896
     /*  592896 */   GIM_Try, /*On fail goto*//*Label 9144*/ GIMT_Encode4(592962), // Rule ID 21272 //
     /*  592901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  592904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  592915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  592926 */     // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN),
     /*  592929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  592931 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  592938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  592943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  592948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  592953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  592956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  592960 */     GIR_RootConstrainSelectedInstOperands,
     /*  592961 */     // GIR_Coverage, 21272,
     /*  592961 */     GIR_EraseRootFromParent_Done,
     /*  592962 */   // Label 9144: @592962
     /*  592962 */   GIM_Try, /*On fail goto*//*Label 9145*/ GIMT_Encode4(593019), // Rule ID 21253 //
     /*  592967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  592970 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  592977 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  592979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  592983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  592990 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  592990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
     /*  592993 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  592995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593017 */     GIR_RootConstrainSelectedInstOperands,
     /*  593018 */     // GIR_Coverage, 21253,
     /*  593018 */     GIR_EraseRootFromParent_Done,
     /*  593019 */   // Label 9145: @593019
     /*  593019 */   GIM_Try, /*On fail goto*//*Label 9146*/ GIMT_Encode4(593076), // Rule ID 21254 //
     /*  593024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  593027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593034 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593047 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
     /*  593050 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593074 */     GIR_RootConstrainSelectedInstOperands,
     /*  593075 */     // GIR_Coverage, 21254,
     /*  593075 */     GIR_EraseRootFromParent_Done,
     /*  593076 */   // Label 9146: @593076
     /*  593076 */   GIM_Try, /*On fail goto*//*Label 9147*/ GIMT_Encode4(593133), // Rule ID 21255 //
     /*  593081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  593084 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593091 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593104 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
     /*  593107 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593131 */     GIR_RootConstrainSelectedInstOperands,
     /*  593132 */     // GIR_Coverage, 21255,
     /*  593132 */     GIR_EraseRootFromParent_Done,
     /*  593133 */   // Label 9147: @593133
     /*  593133 */   GIM_Try, /*On fail goto*//*Label 9148*/ GIMT_Encode4(593190), // Rule ID 21256 //
     /*  593138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  593141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593148 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593161 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
     /*  593164 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593188 */     GIR_RootConstrainSelectedInstOperands,
     /*  593189 */     // GIR_Coverage, 21256,
     /*  593189 */     GIR_EraseRootFromParent_Done,
     /*  593190 */   // Label 9148: @593190
     /*  593190 */   GIM_Try, /*On fail goto*//*Label 9149*/ GIMT_Encode4(593247), // Rule ID 21257 //
     /*  593195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  593198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593205 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593218 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
     /*  593221 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593241 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593245 */     GIR_RootConstrainSelectedInstOperands,
     /*  593246 */     // GIR_Coverage, 21257,
     /*  593246 */     GIR_EraseRootFromParent_Done,
     /*  593247 */   // Label 9149: @593247
     /*  593247 */   GIM_Try, /*On fail goto*//*Label 9150*/ GIMT_Encode4(593304), // Rule ID 21273 //
     /*  593252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  593255 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593262 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593264 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593275 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
     /*  593278 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593302 */     GIR_RootConstrainSelectedInstOperands,
     /*  593303 */     // GIR_Coverage, 21273,
     /*  593303 */     GIR_EraseRootFromParent_Done,
     /*  593304 */   // Label 9150: @593304
     /*  593304 */   GIM_Try, /*On fail goto*//*Label 9151*/ GIMT_Encode4(593361), // Rule ID 21274 //
     /*  593309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  593312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593319 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593332 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
     /*  593335 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593352 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593355 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593359 */     GIR_RootConstrainSelectedInstOperands,
     /*  593360 */     // GIR_Coverage, 21274,
     /*  593360 */     GIR_EraseRootFromParent_Done,
     /*  593361 */   // Label 9151: @593361
     /*  593361 */   GIM_Try, /*On fail goto*//*Label 9152*/ GIMT_Encode4(593418), // Rule ID 21275 //
     /*  593366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  593369 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593376 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593389 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
     /*  593392 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593416 */     GIR_RootConstrainSelectedInstOperands,
     /*  593417 */     // GIR_Coverage, 21275,
     /*  593417 */     GIR_EraseRootFromParent_Done,
     /*  593418 */   // Label 9152: @593418
     /*  593418 */   GIM_Try, /*On fail goto*//*Label 9153*/ GIMT_Encode4(593475), // Rule ID 21276 //
     /*  593423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  593426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593433 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593446 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
     /*  593449 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593473 */     GIR_RootConstrainSelectedInstOperands,
     /*  593474 */     // GIR_Coverage, 21276,
     /*  593474 */     GIR_EraseRootFromParent_Done,
     /*  593475 */   // Label 9153: @593475
     /*  593475 */   GIM_Try, /*On fail goto*//*Label 9154*/ GIMT_Encode4(593532), // Rule ID 21277 //
     /*  593480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  593483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593490 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  593492 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593503 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
     /*  593506 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  593526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593530 */     GIR_RootConstrainSelectedInstOperands,
     /*  593531 */     // GIR_Coverage, 21277,
     /*  593531 */     GIR_EraseRootFromParent_Done,
     /*  593532 */   // Label 9154: @593532
     /*  593532 */   GIM_Try, /*On fail goto*//*Label 9155*/ GIMT_Encode4(593593), // Rule ID 21243 //
     /*  593537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  593540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593562 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
     /*  593565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593567 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593591 */     GIR_RootConstrainSelectedInstOperands,
     /*  593592 */     // GIR_Coverage, 21243,
     /*  593592 */     GIR_EraseRootFromParent_Done,
     /*  593593 */   // Label 9155: @593593
     /*  593593 */   GIM_Try, /*On fail goto*//*Label 9156*/ GIMT_Encode4(593654), // Rule ID 21244 //
     /*  593598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  593601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593623 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
     /*  593626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593628 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593652 */     GIR_RootConstrainSelectedInstOperands,
     /*  593653 */     // GIR_Coverage, 21244,
     /*  593653 */     GIR_EraseRootFromParent_Done,
     /*  593654 */   // Label 9156: @593654
     /*  593654 */   GIM_Try, /*On fail goto*//*Label 9157*/ GIMT_Encode4(593715), // Rule ID 21245 //
     /*  593659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  593662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593684 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
     /*  593687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593689 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593713 */     GIR_RootConstrainSelectedInstOperands,
     /*  593714 */     // GIR_Coverage, 21245,
     /*  593714 */     GIR_EraseRootFromParent_Done,
     /*  593715 */   // Label 9157: @593715
     /*  593715 */   GIM_Try, /*On fail goto*//*Label 9158*/ GIMT_Encode4(593776), // Rule ID 21246 //
     /*  593720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  593723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593745 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
     /*  593748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593750 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593774 */     GIR_RootConstrainSelectedInstOperands,
     /*  593775 */     // GIR_Coverage, 21246,
     /*  593775 */     GIR_EraseRootFromParent_Done,
     /*  593776 */   // Label 9158: @593776
     /*  593776 */   GIM_Try, /*On fail goto*//*Label 9159*/ GIMT_Encode4(593837), // Rule ID 21247 //
     /*  593781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  593784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593799 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593806 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
     /*  593809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593811 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593835 */     GIR_RootConstrainSelectedInstOperands,
     /*  593836 */     // GIR_Coverage, 21247,
     /*  593836 */     GIR_EraseRootFromParent_Done,
     /*  593837 */   // Label 9159: @593837
     /*  593837 */   GIM_Try, /*On fail goto*//*Label 9160*/ GIMT_Encode4(593898), // Rule ID 21263 //
     /*  593842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  593845 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593867 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
     /*  593870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593872 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593896 */     GIR_RootConstrainSelectedInstOperands,
     /*  593897 */     // GIR_Coverage, 21263,
     /*  593897 */     GIR_EraseRootFromParent_Done,
     /*  593898 */   // Label 9160: @593898
     /*  593898 */   GIM_Try, /*On fail goto*//*Label 9161*/ GIMT_Encode4(593959), // Rule ID 21264 //
     /*  593903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  593906 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593928 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
     /*  593931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593933 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  593940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  593945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  593950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  593953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  593957 */     GIR_RootConstrainSelectedInstOperands,
     /*  593958 */     // GIR_Coverage, 21264,
     /*  593958 */     GIR_EraseRootFromParent_Done,
     /*  593959 */   // Label 9161: @593959
     /*  593959 */   GIM_Try, /*On fail goto*//*Label 9162*/ GIMT_Encode4(594020), // Rule ID 21265 //
     /*  593964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  593967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  593974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  593978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  593982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  593989 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  593989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
     /*  593992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  593994 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  593996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  594001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  594006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  594011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594018 */     GIR_RootConstrainSelectedInstOperands,
     /*  594019 */     // GIR_Coverage, 21265,
     /*  594019 */     GIR_EraseRootFromParent_Done,
     /*  594020 */   // Label 9162: @594020
     /*  594020 */   GIM_Try, /*On fail goto*//*Label 9163*/ GIMT_Encode4(594081), // Rule ID 21266 //
     /*  594025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  594028 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  594035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  594039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  594050 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  594050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
     /*  594053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  594055 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  594057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  594062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  594067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  594072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594079 */     GIR_RootConstrainSelectedInstOperands,
     /*  594080 */     // GIR_Coverage, 21266,
     /*  594080 */     GIR_EraseRootFromParent_Done,
     /*  594081 */   // Label 9163: @594081
     /*  594081 */   GIM_Try, /*On fail goto*//*Label 9164*/ GIMT_Encode4(594142), // Rule ID 21267 //
     /*  594086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  594089 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  594096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  594100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  594111 */     // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  594111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
     /*  594114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  594116 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  594118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  594123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  594128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  594133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594140 */     GIR_RootConstrainSelectedInstOperands,
     /*  594141 */     // GIR_Coverage, 21267,
     /*  594141 */     GIR_EraseRootFromParent_Done,
     /*  594142 */   // Label 9164: @594142
     /*  594142 */   GIM_Try, /*On fail goto*//*Label 9165*/ GIMT_Encode4(594192), // Rule ID 30565 //
     /*  594147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  594150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594155 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594168 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594176 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594190 */     GIR_RootConstrainSelectedInstOperands,
     /*  594191 */     // GIR_Coverage, 30565,
     /*  594191 */     GIR_EraseRootFromParent_Done,
     /*  594192 */   // Label 9165: @594192
     /*  594192 */   GIM_Try, /*On fail goto*//*Label 9166*/ GIMT_Encode4(594242), // Rule ID 30566 //
     /*  594197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  594200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594205 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594218 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594226 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594240 */     GIR_RootConstrainSelectedInstOperands,
     /*  594241 */     // GIR_Coverage, 30566,
     /*  594241 */     GIR_EraseRootFromParent_Done,
     /*  594242 */   // Label 9166: @594242
     /*  594242 */   GIM_Try, /*On fail goto*//*Label 9167*/ GIMT_Encode4(594292), // Rule ID 30567 //
     /*  594247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  594250 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594255 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594268 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594276 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594283 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594286 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594290 */     GIR_RootConstrainSelectedInstOperands,
     /*  594291 */     // GIR_Coverage, 30567,
     /*  594291 */     GIR_EraseRootFromParent_Done,
     /*  594292 */   // Label 9167: @594292
     /*  594292 */   GIM_Try, /*On fail goto*//*Label 9168*/ GIMT_Encode4(594342), // Rule ID 30568 //
     /*  594297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  594300 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594305 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594318 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594326 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594340 */     GIR_RootConstrainSelectedInstOperands,
     /*  594341 */     // GIR_Coverage, 30568,
     /*  594341 */     GIR_EraseRootFromParent_Done,
     /*  594342 */   // Label 9168: @594342
     /*  594342 */   GIM_Try, /*On fail goto*//*Label 9169*/ GIMT_Encode4(594392), // Rule ID 30569 //
     /*  594347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  594350 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594355 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594368 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594376 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594390 */     GIR_RootConstrainSelectedInstOperands,
     /*  594391 */     // GIR_Coverage, 30569,
     /*  594391 */     GIR_EraseRootFromParent_Done,
     /*  594392 */   // Label 9169: @594392
     /*  594392 */   GIM_Try, /*On fail goto*//*Label 9170*/ GIMT_Encode4(594442), // Rule ID 30575 //
     /*  594397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  594400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594405 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594407 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594411 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594418 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_i64>>  =>  (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9),
     /*  594421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594426 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594440 */     GIR_RootConstrainSelectedInstOperands,
     /*  594441 */     // GIR_Coverage, 30575,
     /*  594441 */     GIR_EraseRootFromParent_Done,
     /*  594442 */   // Label 9170: @594442
     /*  594442 */   GIM_Try, /*On fail goto*//*Label 9171*/ GIMT_Encode4(594492), // Rule ID 30576 //
     /*  594447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  594450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594455 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594468 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_i64>>  =>  (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9),
     /*  594471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594476 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594490 */     GIR_RootConstrainSelectedInstOperands,
     /*  594491 */     // GIR_Coverage, 30576,
     /*  594491 */     GIR_EraseRootFromParent_Done,
     /*  594492 */   // Label 9171: @594492
     /*  594492 */   GIM_Try, /*On fail goto*//*Label 9172*/ GIMT_Encode4(594542), // Rule ID 30577 //
     /*  594497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  594500 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594505 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594507 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594518 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_i64>>  =>  (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9),
     /*  594521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594526 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594533 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594536 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594540 */     GIR_RootConstrainSelectedInstOperands,
     /*  594541 */     // GIR_Coverage, 30577,
     /*  594541 */     GIR_EraseRootFromParent_Done,
     /*  594542 */   // Label 9172: @594542
     /*  594542 */   GIM_Try, /*On fail goto*//*Label 9173*/ GIMT_Encode4(594592), // Rule ID 30578 //
     /*  594547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  594550 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594555 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594568 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_i64>>  =>  (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9),
     /*  594571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594576 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594590 */     GIR_RootConstrainSelectedInstOperands,
     /*  594591 */     // GIR_Coverage, 30578,
     /*  594591 */     GIR_EraseRootFromParent_Done,
     /*  594592 */   // Label 9173: @594592
     /*  594592 */   GIM_Try, /*On fail goto*//*Label 9174*/ GIMT_Encode4(594642), // Rule ID 30579 //
     /*  594597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  594600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594605 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594618 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_i64>>  =>  (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9),
     /*  594621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594626 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594640 */     GIR_RootConstrainSelectedInstOperands,
     /*  594641 */     // GIR_Coverage, 30579,
     /*  594641 */     GIR_EraseRootFromParent_Done,
     /*  594642 */   // Label 9174: @594642
     /*  594642 */   GIM_Try, /*On fail goto*//*Label 9175*/ GIMT_Encode4(594692), // Rule ID 30585 //
     /*  594647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  594650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  594655 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594668 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  594668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594676 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594690 */     GIR_RootConstrainSelectedInstOperands,
     /*  594691 */     // GIR_Coverage, 30585,
     /*  594691 */     GIR_EraseRootFromParent_Done,
     /*  594692 */   // Label 9175: @594692
     /*  594692 */   GIM_Try, /*On fail goto*//*Label 9176*/ GIMT_Encode4(594742), // Rule ID 30586 //
     /*  594697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  594700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  594705 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594718 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  594718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594726 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594740 */     GIR_RootConstrainSelectedInstOperands,
     /*  594741 */     // GIR_Coverage, 30586,
     /*  594741 */     GIR_EraseRootFromParent_Done,
     /*  594742 */   // Label 9176: @594742
     /*  594742 */   GIM_Try, /*On fail goto*//*Label 9177*/ GIMT_Encode4(594792), // Rule ID 30587 //
     /*  594747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  594750 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  594755 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594757 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594768 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  594768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594776 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594783 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594790 */     GIR_RootConstrainSelectedInstOperands,
     /*  594791 */     // GIR_Coverage, 30587,
     /*  594791 */     GIR_EraseRootFromParent_Done,
     /*  594792 */   // Label 9177: @594792
     /*  594792 */   GIM_Try, /*On fail goto*//*Label 9178*/ GIMT_Encode4(594842), // Rule ID 30588 //
     /*  594797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  594800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  594805 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594818 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  594818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594826 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594840 */     GIR_RootConstrainSelectedInstOperands,
     /*  594841 */     // GIR_Coverage, 30588,
     /*  594841 */     GIR_EraseRootFromParent_Done,
     /*  594842 */   // Label 9178: @594842
     /*  594842 */   GIM_Try, /*On fail goto*//*Label 9179*/ GIMT_Encode4(594892), // Rule ID 30589 //
     /*  594847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  594850 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  594855 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  594857 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594861 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594868 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  594868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
     /*  594871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594876 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  594886 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594890 */     GIR_RootConstrainSelectedInstOperands,
     /*  594891 */     // GIR_Coverage, 30589,
     /*  594891 */     GIR_EraseRootFromParent_Done,
     /*  594892 */   // Label 9179: @594892
     /*  594892 */   GIM_Try, /*On fail goto*//*Label 9180*/ GIMT_Encode4(594946), // Rule ID 30560 //
     /*  594897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  594900 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  594909 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594920 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  594923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  594925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594930 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594944 */     GIR_RootConstrainSelectedInstOperands,
     /*  594945 */     // GIR_Coverage, 30560,
     /*  594945 */     GIR_EraseRootFromParent_Done,
     /*  594946 */   // Label 9180: @594946
     /*  594946 */   GIM_Try, /*On fail goto*//*Label 9181*/ GIMT_Encode4(595000), // Rule ID 30561 //
     /*  594951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  594954 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  594959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  594963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  594967 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  594974 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  594974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  594977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  594979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  594984 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  594986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  594991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  594994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  594998 */     GIR_RootConstrainSelectedInstOperands,
     /*  594999 */     // GIR_Coverage, 30561,
     /*  594999 */     GIR_EraseRootFromParent_Done,
     /*  595000 */   // Label 9181: @595000
     /*  595000 */   GIM_Try, /*On fail goto*//*Label 9182*/ GIMT_Encode4(595054), // Rule ID 30562 //
     /*  595005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  595008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595017 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595028 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595038 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595052 */     GIR_RootConstrainSelectedInstOperands,
     /*  595053 */     // GIR_Coverage, 30562,
     /*  595053 */     GIR_EraseRootFromParent_Done,
     /*  595054 */   // Label 9182: @595054
     /*  595054 */   GIM_Try, /*On fail goto*//*Label 9183*/ GIMT_Encode4(595108), // Rule ID 30563 //
     /*  595059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  595062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595082 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595092 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595106 */     GIR_RootConstrainSelectedInstOperands,
     /*  595107 */     // GIR_Coverage, 30563,
     /*  595107 */     GIR_EraseRootFromParent_Done,
     /*  595108 */   // Label 9183: @595108
     /*  595108 */   GIM_Try, /*On fail goto*//*Label 9184*/ GIMT_Encode4(595162), // Rule ID 30564 //
     /*  595113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  595116 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595136 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595146 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595160 */     GIR_RootConstrainSelectedInstOperands,
     /*  595161 */     // GIR_Coverage, 30564,
     /*  595161 */     GIR_EraseRootFromParent_Done,
     /*  595162 */   // Label 9184: @595162
     /*  595162 */   GIM_Try, /*On fail goto*//*Label 9185*/ GIMT_Encode4(595216), // Rule ID 30570 //
     /*  595167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  595170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595190 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_i64>>  =>  (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9),
     /*  595193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595200 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595214 */     GIR_RootConstrainSelectedInstOperands,
     /*  595215 */     // GIR_Coverage, 30570,
     /*  595215 */     GIR_EraseRootFromParent_Done,
     /*  595216 */   // Label 9185: @595216
     /*  595216 */   GIM_Try, /*On fail goto*//*Label 9186*/ GIMT_Encode4(595270), // Rule ID 30571 //
     /*  595221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  595224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595244 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_i64>>  =>  (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9),
     /*  595247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595254 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595268 */     GIR_RootConstrainSelectedInstOperands,
     /*  595269 */     // GIR_Coverage, 30571,
     /*  595269 */     GIR_EraseRootFromParent_Done,
     /*  595270 */   // Label 9186: @595270
     /*  595270 */   GIM_Try, /*On fail goto*//*Label 9187*/ GIMT_Encode4(595324), // Rule ID 30572 //
     /*  595275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  595278 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595298 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_i64>>  =>  (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9),
     /*  595301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595308 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595322 */     GIR_RootConstrainSelectedInstOperands,
     /*  595323 */     // GIR_Coverage, 30572,
     /*  595323 */     GIR_EraseRootFromParent_Done,
     /*  595324 */   // Label 9187: @595324
     /*  595324 */   GIM_Try, /*On fail goto*//*Label 9188*/ GIMT_Encode4(595378), // Rule ID 30573 //
     /*  595329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  595332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595341 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595352 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_i64>>  =>  (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9),
     /*  595355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595362 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595376 */     GIR_RootConstrainSelectedInstOperands,
     /*  595377 */     // GIR_Coverage, 30573,
     /*  595377 */     GIR_EraseRootFromParent_Done,
     /*  595378 */   // Label 9188: @595378
     /*  595378 */   GIM_Try, /*On fail goto*//*Label 9189*/ GIMT_Encode4(595432), // Rule ID 30574 //
     /*  595383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  595386 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  595391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595406 */     // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_i64>>  =>  (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  595406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9),
     /*  595409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595416 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  595426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595430 */     GIR_RootConstrainSelectedInstOperands,
     /*  595431 */     // GIR_Coverage, 30574,
     /*  595431 */     GIR_EraseRootFromParent_Done,
     /*  595432 */   // Label 9189: @595432
     /*  595432 */   GIM_Try, /*On fail goto*//*Label 9190*/ GIMT_Encode4(595486), // Rule ID 30580 //
     /*  595437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  595440 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  595445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595460 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  595460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595470 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  595480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595484 */     GIR_RootConstrainSelectedInstOperands,
     /*  595485 */     // GIR_Coverage, 30580,
     /*  595485 */     GIR_EraseRootFromParent_Done,
     /*  595486 */   // Label 9190: @595486
     /*  595486 */   GIM_Try, /*On fail goto*//*Label 9191*/ GIMT_Encode4(595540), // Rule ID 30581 //
     /*  595491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  595494 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  595499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595514 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  595514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595524 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  595534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595538 */     GIR_RootConstrainSelectedInstOperands,
     /*  595539 */     // GIR_Coverage, 30581,
     /*  595539 */     GIR_EraseRootFromParent_Done,
     /*  595540 */   // Label 9191: @595540
     /*  595540 */   GIM_Try, /*On fail goto*//*Label 9192*/ GIMT_Encode4(595594), // Rule ID 30582 //
     /*  595545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  595548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  595553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595568 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  595568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595578 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  595588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595592 */     GIR_RootConstrainSelectedInstOperands,
     /*  595593 */     // GIR_Coverage, 30582,
     /*  595593 */     GIR_EraseRootFromParent_Done,
     /*  595594 */   // Label 9192: @595594
     /*  595594 */   GIM_Try, /*On fail goto*//*Label 9193*/ GIMT_Encode4(595648), // Rule ID 30583 //
     /*  595599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  595602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  595607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595622 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  595622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595632 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  595642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595646 */     GIR_RootConstrainSelectedInstOperands,
     /*  595647 */     // GIR_Coverage, 30583,
     /*  595647 */     GIR_EraseRootFromParent_Done,
     /*  595648 */   // Label 9193: @595648
     /*  595648 */   GIM_Try, /*On fail goto*//*Label 9194*/ GIMT_Encode4(595702), // Rule ID 30584 //
     /*  595653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  595656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  595661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  595665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  595676 */     // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_i64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  595676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
     /*  595679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  595681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  595686 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  595688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  595693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  595696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595700 */     GIR_RootConstrainSelectedInstOperands,
     /*  595701 */     // GIR_Coverage, 30584,
     /*  595701 */     GIR_EraseRootFromParent_Done,
     /*  595702 */   // Label 9194: @595702
     /*  595702 */   GIM_Try, /*On fail goto*//*Label 9195*/ GIMT_Encode4(595761), // Rule ID 13105 //
     /*  595707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  595710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  595717 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  595719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  595730 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  595730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR),
     /*  595733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  595738 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  595740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  595745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  595750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  595755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595759 */     GIR_RootConstrainSelectedInstOperands,
     /*  595760 */     // GIR_Coverage, 13105,
     /*  595760 */     GIR_EraseRootFromParent_Done,
     /*  595761 */   // Label 9195: @595761
     /*  595761 */   GIM_Try, /*On fail goto*//*Label 9196*/ GIMT_Encode4(595820), // Rule ID 13106 //
     /*  595766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  595769 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  595776 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  595778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595782 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  595789 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  595789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR),
     /*  595792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  595797 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  595799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  595804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  595809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  595814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595818 */     GIR_RootConstrainSelectedInstOperands,
     /*  595819 */     // GIR_Coverage, 13106,
     /*  595819 */     GIR_EraseRootFromParent_Done,
     /*  595820 */   // Label 9196: @595820
     /*  595820 */   GIM_Try, /*On fail goto*//*Label 9197*/ GIMT_Encode4(595879), // Rule ID 13107 //
     /*  595825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  595828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  595835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  595837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  595848 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  595848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR),
     /*  595851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  595856 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  595858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  595863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  595868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  595873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595877 */     GIR_RootConstrainSelectedInstOperands,
     /*  595878 */     // GIR_Coverage, 13107,
     /*  595878 */     GIR_EraseRootFromParent_Done,
     /*  595879 */   // Label 9197: @595879
     /*  595879 */   GIM_Try, /*On fail goto*//*Label 9198*/ GIMT_Encode4(595938), // Rule ID 13108 //
     /*  595884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  595887 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  595894 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  595896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  595907 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  595907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR),
     /*  595910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  595915 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  595917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  595922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  595927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  595932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595936 */     GIR_RootConstrainSelectedInstOperands,
     /*  595937 */     // GIR_Coverage, 13108,
     /*  595937 */     GIR_EraseRootFromParent_Done,
     /*  595938 */   // Label 9198: @595938
     /*  595938 */   GIM_Try, /*On fail goto*//*Label 9199*/ GIMT_Encode4(595997), // Rule ID 13109 //
     /*  595943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  595946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  595953 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  595955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  595959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  595966 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  595966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR),
     /*  595969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  595974 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  595976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  595981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  595986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  595991 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  595995 */     GIR_RootConstrainSelectedInstOperands,
     /*  595996 */     // GIR_Coverage, 13109,
     /*  595996 */     GIR_EraseRootFromParent_Done,
     /*  595997 */   // Label 9199: @595997
     /*  595997 */   GIM_Try, /*On fail goto*//*Label 9200*/ GIMT_Encode4(596060), // Rule ID 13115 //
     /*  596002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  596005 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  596027 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN),
     /*  596030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596037 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596058 */     GIR_RootConstrainSelectedInstOperands,
     /*  596059 */     // GIR_Coverage, 13115,
     /*  596059 */     GIR_EraseRootFromParent_Done,
     /*  596060 */   // Label 9200: @596060
     /*  596060 */   GIM_Try, /*On fail goto*//*Label 9201*/ GIMT_Encode4(596123), // Rule ID 13116 //
     /*  596065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  596068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  596090 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN),
     /*  596093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596100 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596121 */     GIR_RootConstrainSelectedInstOperands,
     /*  596122 */     // GIR_Coverage, 13116,
     /*  596122 */     GIR_EraseRootFromParent_Done,
     /*  596123 */   // Label 9201: @596123
     /*  596123 */   GIM_Try, /*On fail goto*//*Label 9202*/ GIMT_Encode4(596186), // Rule ID 13117 //
     /*  596128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  596131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596142 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  596153 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN),
     /*  596156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596163 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596184 */     GIR_RootConstrainSelectedInstOperands,
     /*  596185 */     // GIR_Coverage, 13117,
     /*  596185 */     GIR_EraseRootFromParent_Done,
     /*  596186 */   // Label 9202: @596186
     /*  596186 */   GIM_Try, /*On fail goto*//*Label 9203*/ GIMT_Encode4(596249), // Rule ID 13118 //
     /*  596191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  596194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  596216 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN),
     /*  596219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596226 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596247 */     GIR_RootConstrainSelectedInstOperands,
     /*  596248 */     // GIR_Coverage, 13118,
     /*  596248 */     GIR_EraseRootFromParent_Done,
     /*  596249 */   // Label 9203: @596249
     /*  596249 */   GIM_Try, /*On fail goto*//*Label 9204*/ GIMT_Encode4(596312), // Rule ID 13119 //
     /*  596254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  596257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  596279 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN),
     /*  596282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596289 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596306 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596310 */     GIR_RootConstrainSelectedInstOperands,
     /*  596311 */     // GIR_Coverage, 13119,
     /*  596311 */     GIR_EraseRootFromParent_Done,
     /*  596312 */   // Label 9204: @596312
     /*  596312 */   GIM_Try, /*On fail goto*//*Label 9205*/ GIMT_Encode4(596364), // Rule ID 13100 //
     /*  596317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  596320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596327 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596340 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2),
     /*  596343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596348 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  596358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596362 */     GIR_RootConstrainSelectedInstOperands,
     /*  596363 */     // GIR_Coverage, 13100,
     /*  596363 */     GIR_EraseRootFromParent_Done,
     /*  596364 */   // Label 9205: @596364
     /*  596364 */   GIM_Try, /*On fail goto*//*Label 9206*/ GIMT_Encode4(596416), // Rule ID 13101 //
     /*  596369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  596372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596392 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2),
     /*  596395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  596410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596414 */     GIR_RootConstrainSelectedInstOperands,
     /*  596415 */     // GIR_Coverage, 13101,
     /*  596415 */     GIR_EraseRootFromParent_Done,
     /*  596416 */   // Label 9206: @596416
     /*  596416 */   GIM_Try, /*On fail goto*//*Label 9207*/ GIMT_Encode4(596468), // Rule ID 13102 //
     /*  596421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  596424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596431 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596444 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2),
     /*  596447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596452 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  596462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596466 */     GIR_RootConstrainSelectedInstOperands,
     /*  596467 */     // GIR_Coverage, 13102,
     /*  596467 */     GIR_EraseRootFromParent_Done,
     /*  596468 */   // Label 9207: @596468
     /*  596468 */   GIM_Try, /*On fail goto*//*Label 9208*/ GIMT_Encode4(596520), // Rule ID 13103 //
     /*  596473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  596476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596483 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596496 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2),
     /*  596499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596504 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  596514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596518 */     GIR_RootConstrainSelectedInstOperands,
     /*  596519 */     // GIR_Coverage, 13103,
     /*  596519 */     GIR_EraseRootFromParent_Done,
     /*  596520 */   // Label 9208: @596520
     /*  596520 */   GIM_Try, /*On fail goto*//*Label 9209*/ GIMT_Encode4(596572), // Rule ID 13104 //
     /*  596525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  596528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596535 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596537 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596541 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596548 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2),
     /*  596551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596556 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  596566 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596570 */     GIR_RootConstrainSelectedInstOperands,
     /*  596571 */     // GIR_Coverage, 13104,
     /*  596571 */     GIR_EraseRootFromParent_Done,
     /*  596572 */   // Label 9209: @596572
     /*  596572 */   GIM_Try, /*On fail goto*//*Label 9210*/ GIMT_Encode4(596628), // Rule ID 13110 //
     /*  596577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  596580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596602 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN),
     /*  596605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596612 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  596622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596626 */     GIR_RootConstrainSelectedInstOperands,
     /*  596627 */     // GIR_Coverage, 13110,
     /*  596627 */     GIR_EraseRootFromParent_Done,
     /*  596628 */   // Label 9210: @596628
     /*  596628 */   GIM_Try, /*On fail goto*//*Label 9211*/ GIMT_Encode4(596684), // Rule ID 13111 //
     /*  596633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  596636 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596658 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN),
     /*  596661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596668 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  596678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596682 */     GIR_RootConstrainSelectedInstOperands,
     /*  596683 */     // GIR_Coverage, 13111,
     /*  596683 */     GIR_EraseRootFromParent_Done,
     /*  596684 */   // Label 9211: @596684
     /*  596684 */   GIM_Try, /*On fail goto*//*Label 9212*/ GIMT_Encode4(596740), // Rule ID 13112 //
     /*  596689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  596692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596703 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596714 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN),
     /*  596717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596724 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  596734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596738 */     GIR_RootConstrainSelectedInstOperands,
     /*  596739 */     // GIR_Coverage, 13112,
     /*  596739 */     GIR_EraseRootFromParent_Done,
     /*  596740 */   // Label 9212: @596740
     /*  596740 */   GIM_Try, /*On fail goto*//*Label 9213*/ GIMT_Encode4(596796), // Rule ID 13113 //
     /*  596745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  596748 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596770 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN),
     /*  596773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596780 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  596790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596794 */     GIR_RootConstrainSelectedInstOperands,
     /*  596795 */     // GIR_Coverage, 13113,
     /*  596795 */     GIR_EraseRootFromParent_Done,
     /*  596796 */   // Label 9213: @596796
     /*  596796 */   GIM_Try, /*On fail goto*//*Label 9214*/ GIMT_Encode4(596852), // Rule ID 13114 //
     /*  596801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  596804 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  596815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  596826 */     // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  596826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN),
     /*  596829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  596831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  596836 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  596843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  596846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596850 */     GIR_RootConstrainSelectedInstOperands,
     /*  596851 */     // GIR_Coverage, 13114,
     /*  596851 */     GIR_EraseRootFromParent_Done,
     /*  596852 */   // Label 9214: @596852
     /*  596852 */   GIM_Try, /*On fail goto*//*Label 9215*/ GIMT_Encode4(596912), // Rule ID 10697 //
     /*  596857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  596860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596868 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596874 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  596881 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  596884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596889 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596910 */     GIR_RootConstrainSelectedInstOperands,
     /*  596911 */     // GIR_Coverage, 10697,
     /*  596911 */     GIR_EraseRootFromParent_Done,
     /*  596912 */   // Label 9215: @596912
     /*  596912 */   GIM_Try, /*On fail goto*//*Label 9216*/ GIMT_Encode4(596972), // Rule ID 10698 //
     /*  596917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  596920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596928 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  596941 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  596941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  596944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  596949 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  596951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  596956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  596961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  596966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  596970 */     GIR_RootConstrainSelectedInstOperands,
     /*  596971 */     // GIR_Coverage, 10698,
     /*  596971 */     GIR_EraseRootFromParent_Done,
     /*  596972 */   // Label 9216: @596972
     /*  596972 */   GIM_Try, /*On fail goto*//*Label 9217*/ GIMT_Encode4(597032), // Rule ID 10699 //
     /*  596977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  596980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  596988 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  596990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  596994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597001 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597009 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597030 */     GIR_RootConstrainSelectedInstOperands,
     /*  597031 */     // GIR_Coverage, 10699,
     /*  597031 */     GIR_EraseRootFromParent_Done,
     /*  597032 */   // Label 9217: @597032
     /*  597032 */   GIM_Try, /*On fail goto*//*Label 9218*/ GIMT_Encode4(597092), // Rule ID 10700 //
     /*  597037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  597040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597048 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597061 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597069 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597090 */     GIR_RootConstrainSelectedInstOperands,
     /*  597091 */     // GIR_Coverage, 10700,
     /*  597091 */     GIR_EraseRootFromParent_Done,
     /*  597092 */   // Label 9218: @597092
     /*  597092 */   GIM_Try, /*On fail goto*//*Label 9219*/ GIMT_Encode4(597152), // Rule ID 10701 //
     /*  597097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  597100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597108 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597121 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597129 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597150 */     GIR_RootConstrainSelectedInstOperands,
     /*  597151 */     // GIR_Coverage, 10701,
     /*  597151 */     GIR_EraseRootFromParent_Done,
     /*  597152 */   // Label 9219: @597152
     /*  597152 */   GIM_Try, /*On fail goto*//*Label 9220*/ GIMT_Encode4(597211), // Rule ID 11253 //
     /*  597157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  597160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597167 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597180 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597188 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597209 */     GIR_RootConstrainSelectedInstOperands,
     /*  597210 */     // GIR_Coverage, 11253,
     /*  597210 */     GIR_EraseRootFromParent_Done,
     /*  597211 */   // Label 9220: @597211
     /*  597211 */   GIM_Try, /*On fail goto*//*Label 9221*/ GIMT_Encode4(597270), // Rule ID 11254 //
     /*  597216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  597219 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597226 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597239 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597247 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597268 */     GIR_RootConstrainSelectedInstOperands,
     /*  597269 */     // GIR_Coverage, 11254,
     /*  597269 */     GIR_EraseRootFromParent_Done,
     /*  597270 */   // Label 9221: @597270
     /*  597270 */   GIM_Try, /*On fail goto*//*Label 9222*/ GIMT_Encode4(597329), // Rule ID 11255 //
     /*  597275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  597278 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597285 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597298 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597306 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597327 */     GIR_RootConstrainSelectedInstOperands,
     /*  597328 */     // GIR_Coverage, 11255,
     /*  597328 */     GIR_EraseRootFromParent_Done,
     /*  597329 */   // Label 9222: @597329
     /*  597329 */   GIM_Try, /*On fail goto*//*Label 9223*/ GIMT_Encode4(597388), // Rule ID 11256 //
     /*  597334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  597337 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597344 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597346 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597350 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597357 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597365 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597386 */     GIR_RootConstrainSelectedInstOperands,
     /*  597387 */     // GIR_Coverage, 11256,
     /*  597387 */     GIR_EraseRootFromParent_Done,
     /*  597388 */   // Label 9223: @597388
     /*  597388 */   GIM_Try, /*On fail goto*//*Label 9224*/ GIMT_Encode4(597447), // Rule ID 11257 //
     /*  597393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  597396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597403 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  597405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  597416 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR),
     /*  597419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597424 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597445 */     GIR_RootConstrainSelectedInstOperands,
     /*  597446 */     // GIR_Coverage, 11257,
     /*  597446 */     GIR_EraseRootFromParent_Done,
     /*  597447 */   // Label 9224: @597447
     /*  597447 */   GIM_Try, /*On fail goto*//*Label 9225*/ GIMT_Encode4(597511), // Rule ID 10687 //
     /*  597452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  597455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597478 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597488 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597509 */     GIR_RootConstrainSelectedInstOperands,
     /*  597510 */     // GIR_Coverage, 10687,
     /*  597510 */     GIR_EraseRootFromParent_Done,
     /*  597511 */   // Label 9225: @597511
     /*  597511 */   GIM_Try, /*On fail goto*//*Label 9226*/ GIMT_Encode4(597575), // Rule ID 10688 //
     /*  597516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  597519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597542 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597552 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597569 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597573 */     GIR_RootConstrainSelectedInstOperands,
     /*  597574 */     // GIR_Coverage, 10688,
     /*  597574 */     GIR_EraseRootFromParent_Done,
     /*  597575 */   // Label 9226: @597575
     /*  597575 */   GIM_Try, /*On fail goto*//*Label 9227*/ GIMT_Encode4(597639), // Rule ID 10689 //
     /*  597580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  597583 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597606 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597616 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597637 */     GIR_RootConstrainSelectedInstOperands,
     /*  597638 */     // GIR_Coverage, 10689,
     /*  597638 */     GIR_EraseRootFromParent_Done,
     /*  597639 */   // Label 9227: @597639
     /*  597639 */   GIM_Try, /*On fail goto*//*Label 9228*/ GIMT_Encode4(597703), // Rule ID 10690 //
     /*  597644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  597647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597670 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597680 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597701 */     GIR_RootConstrainSelectedInstOperands,
     /*  597702 */     // GIR_Coverage, 10690,
     /*  597702 */     GIR_EraseRootFromParent_Done,
     /*  597703 */   // Label 9228: @597703
     /*  597703 */   GIM_Try, /*On fail goto*//*Label 9229*/ GIMT_Encode4(597767), // Rule ID 10691 //
     /*  597708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  597711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597723 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597734 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597744 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597765 */     GIR_RootConstrainSelectedInstOperands,
     /*  597766 */     // GIR_Coverage, 10691,
     /*  597766 */     GIR_EraseRootFromParent_Done,
     /*  597767 */   // Label 9229: @597767
     /*  597767 */   GIM_Try, /*On fail goto*//*Label 9230*/ GIMT_Encode4(597830), // Rule ID 11243 //
     /*  597772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  597775 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597790 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597797 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597807 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597828 */     GIR_RootConstrainSelectedInstOperands,
     /*  597829 */     // GIR_Coverage, 11243,
     /*  597829 */     GIR_EraseRootFromParent_Done,
     /*  597830 */   // Label 9230: @597830
     /*  597830 */   GIM_Try, /*On fail goto*//*Label 9231*/ GIMT_Encode4(597893), // Rule ID 11244 //
     /*  597835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  597838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597860 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597870 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597891 */     GIR_RootConstrainSelectedInstOperands,
     /*  597892 */     // GIR_Coverage, 11244,
     /*  597892 */     GIR_EraseRootFromParent_Done,
     /*  597893 */   // Label 9231: @597893
     /*  597893 */   GIM_Try, /*On fail goto*//*Label 9232*/ GIMT_Encode4(597956), // Rule ID 11245 //
     /*  597898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  597901 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597923 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597933 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  597940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  597945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  597950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  597954 */     GIR_RootConstrainSelectedInstOperands,
     /*  597955 */     // GIR_Coverage, 11245,
     /*  597955 */     GIR_EraseRootFromParent_Done,
     /*  597956 */   // Label 9232: @597956
     /*  597956 */   GIM_Try, /*On fail goto*//*Label 9233*/ GIMT_Encode4(598019), // Rule ID 11246 //
     /*  597961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  597964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  597971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  597975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  597979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  597986 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  597986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  597989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  597991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  597996 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  597998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  598003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  598008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  598013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598017 */     GIR_RootConstrainSelectedInstOperands,
     /*  598018 */     // GIR_Coverage, 11246,
     /*  598018 */     GIR_EraseRootFromParent_Done,
     /*  598019 */   // Label 9233: @598019
     /*  598019 */   GIM_Try, /*On fail goto*//*Label 9234*/ GIMT_Encode4(598082), // Rule ID 11247 //
     /*  598024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  598027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  598049 */     // (atomic_load_add:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  598049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_SADDR_RTN),
     /*  598052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  598059 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  598066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  598071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  598076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598080 */     GIR_RootConstrainSelectedInstOperands,
     /*  598081 */     // GIR_Coverage, 11247,
     /*  598081 */     GIR_EraseRootFromParent_Done,
     /*  598082 */   // Label 9234: @598082
     /*  598082 */   GIM_Try, /*On fail goto*//*Label 9235*/ GIMT_Encode4(598135), // Rule ID 10692 //
     /*  598087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  598090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598098 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598111 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598119 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598133 */     GIR_RootConstrainSelectedInstOperands,
     /*  598134 */     // GIR_Coverage, 10692,
     /*  598134 */     GIR_EraseRootFromParent_Done,
     /*  598135 */   // Label 9235: @598135
     /*  598135 */   GIM_Try, /*On fail goto*//*Label 9236*/ GIMT_Encode4(598188), // Rule ID 10693 //
     /*  598140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  598143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598151 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598164 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598172 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598186 */     GIR_RootConstrainSelectedInstOperands,
     /*  598187 */     // GIR_Coverage, 10693,
     /*  598187 */     GIR_EraseRootFromParent_Done,
     /*  598188 */   // Label 9236: @598188
     /*  598188 */   GIM_Try, /*On fail goto*//*Label 9237*/ GIMT_Encode4(598241), // Rule ID 10694 //
     /*  598193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  598196 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598204 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598217 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598225 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598235 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598239 */     GIR_RootConstrainSelectedInstOperands,
     /*  598240 */     // GIR_Coverage, 10694,
     /*  598240 */     GIR_EraseRootFromParent_Done,
     /*  598241 */   // Label 9237: @598241
     /*  598241 */   GIM_Try, /*On fail goto*//*Label 9238*/ GIMT_Encode4(598294), // Rule ID 10695 //
     /*  598246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  598249 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598257 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598270 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598278 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598292 */     GIR_RootConstrainSelectedInstOperands,
     /*  598293 */     // GIR_Coverage, 10695,
     /*  598293 */     GIR_EraseRootFromParent_Done,
     /*  598294 */   // Label 9238: @598294
     /*  598294 */   GIM_Try, /*On fail goto*//*Label 9239*/ GIMT_Encode4(598347), // Rule ID 10696 //
     /*  598299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  598302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598310 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598312 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598316 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598323 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598331 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598345 */     GIR_RootConstrainSelectedInstOperands,
     /*  598346 */     // GIR_Coverage, 10696,
     /*  598346 */     GIR_EraseRootFromParent_Done,
     /*  598347 */   // Label 9239: @598347
     /*  598347 */   GIM_Try, /*On fail goto*//*Label 9240*/ GIMT_Encode4(598399), // Rule ID 11248 //
     /*  598352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  598355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598362 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598375 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598383 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598397 */     GIR_RootConstrainSelectedInstOperands,
     /*  598398 */     // GIR_Coverage, 11248,
     /*  598398 */     GIR_EraseRootFromParent_Done,
     /*  598399 */   // Label 9240: @598399
     /*  598399 */   GIM_Try, /*On fail goto*//*Label 9241*/ GIMT_Encode4(598451), // Rule ID 11249 //
     /*  598404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  598407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598414 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598427 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598435 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598449 */     GIR_RootConstrainSelectedInstOperands,
     /*  598450 */     // GIR_Coverage, 11249,
     /*  598450 */     GIR_EraseRootFromParent_Done,
     /*  598451 */   // Label 9241: @598451
     /*  598451 */   GIM_Try, /*On fail goto*//*Label 9242*/ GIMT_Encode4(598503), // Rule ID 11250 //
     /*  598456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  598459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598466 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598479 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598487 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598501 */     GIR_RootConstrainSelectedInstOperands,
     /*  598502 */     // GIR_Coverage, 11250,
     /*  598502 */     GIR_EraseRootFromParent_Done,
     /*  598503 */   // Label 9242: @598503
     /*  598503 */   GIM_Try, /*On fail goto*//*Label 9243*/ GIMT_Encode4(598555), // Rule ID 11251 //
     /*  598508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  598511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598518 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598531 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598539 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598553 */     GIR_RootConstrainSelectedInstOperands,
     /*  598554 */     // GIR_Coverage, 11251,
     /*  598554 */     GIR_EraseRootFromParent_Done,
     /*  598555 */   // Label 9243: @598555
     /*  598555 */   GIM_Try, /*On fail goto*//*Label 9244*/ GIMT_Encode4(598607), // Rule ID 11252 //
     /*  598560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  598563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598570 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  598572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598583 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
     /*  598586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598591 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  598601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598605 */     GIR_RootConstrainSelectedInstOperands,
     /*  598606 */     // GIR_Coverage, 11252,
     /*  598606 */     GIR_EraseRootFromParent_Done,
     /*  598607 */   // Label 9244: @598607
     /*  598607 */   GIM_Try, /*On fail goto*//*Label 9245*/ GIMT_Encode4(598664), // Rule ID 10682 //
     /*  598612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  598615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598638 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598648 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598662 */     GIR_RootConstrainSelectedInstOperands,
     /*  598663 */     // GIR_Coverage, 10682,
     /*  598663 */     GIR_EraseRootFromParent_Done,
     /*  598664 */   // Label 9245: @598664
     /*  598664 */   GIM_Try, /*On fail goto*//*Label 9246*/ GIMT_Encode4(598721), // Rule ID 10683 //
     /*  598669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  598672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598695 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598705 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598719 */     GIR_RootConstrainSelectedInstOperands,
     /*  598720 */     // GIR_Coverage, 10683,
     /*  598720 */     GIR_EraseRootFromParent_Done,
     /*  598721 */   // Label 9246: @598721
     /*  598721 */   GIM_Try, /*On fail goto*//*Label 9247*/ GIMT_Encode4(598778), // Rule ID 10684 //
     /*  598726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  598729 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598752 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598762 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598776 */     GIR_RootConstrainSelectedInstOperands,
     /*  598777 */     // GIR_Coverage, 10684,
     /*  598777 */     GIR_EraseRootFromParent_Done,
     /*  598778 */   // Label 9247: @598778
     /*  598778 */   GIM_Try, /*On fail goto*//*Label 9248*/ GIMT_Encode4(598835), // Rule ID 10685 //
     /*  598783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  598786 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598809 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598819 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598833 */     GIR_RootConstrainSelectedInstOperands,
     /*  598834 */     // GIR_Coverage, 10685,
     /*  598834 */     GIR_EraseRootFromParent_Done,
     /*  598835 */   // Label 9248: @598835
     /*  598835 */   GIM_Try, /*On fail goto*//*Label 9249*/ GIMT_Encode4(598892), // Rule ID 10686 //
     /*  598840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  598843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598866 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598876 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598886 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598890 */     GIR_RootConstrainSelectedInstOperands,
     /*  598891 */     // GIR_Coverage, 10686,
     /*  598891 */     GIR_EraseRootFromParent_Done,
     /*  598892 */   // Label 9249: @598892
     /*  598892 */   GIM_Try, /*On fail goto*//*Label 9250*/ GIMT_Encode4(598948), // Rule ID 11238 //
     /*  598897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  598900 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598922 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598932 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  598946 */     GIR_RootConstrainSelectedInstOperands,
     /*  598947 */     // GIR_Coverage, 11238,
     /*  598947 */     GIR_EraseRootFromParent_Done,
     /*  598948 */   // Label 9250: @598948
     /*  598948 */   GIM_Try, /*On fail goto*//*Label 9251*/ GIMT_Encode4(599004), // Rule ID 11239 //
     /*  598953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  598956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  598963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  598967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  598971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  598978 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  598978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  598981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  598983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  598988 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  598990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  598995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  598998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599002 */     GIR_RootConstrainSelectedInstOperands,
     /*  599003 */     // GIR_Coverage, 11239,
     /*  599003 */     GIR_EraseRootFromParent_Done,
     /*  599004 */   // Label 9251: @599004
     /*  599004 */   GIM_Try, /*On fail goto*//*Label 9252*/ GIMT_Encode4(599060), // Rule ID 11240 //
     /*  599009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  599012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  599023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  599034 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  599034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  599037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  599039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  599044 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  599046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  599051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  599054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599058 */     GIR_RootConstrainSelectedInstOperands,
     /*  599059 */     // GIR_Coverage, 11240,
     /*  599059 */     GIR_EraseRootFromParent_Done,
     /*  599060 */   // Label 9252: @599060
     /*  599060 */   GIM_Try, /*On fail goto*//*Label 9253*/ GIMT_Encode4(599116), // Rule ID 11241 //
     /*  599065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  599068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  599079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  599090 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  599090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  599093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  599095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  599100 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  599102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  599107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  599110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599114 */     GIR_RootConstrainSelectedInstOperands,
     /*  599115 */     // GIR_Coverage, 11241,
     /*  599115 */     GIR_EraseRootFromParent_Done,
     /*  599116 */   // Label 9253: @599116
     /*  599116 */   GIM_Try, /*On fail goto*//*Label 9254*/ GIMT_Encode4(599172), // Rule ID 11242 //
     /*  599121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  599124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  599135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  599146 */     // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  599146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
     /*  599149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  599151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  599156 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  599158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  599163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  599166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599170 */     GIR_RootConstrainSelectedInstOperands,
     /*  599171 */     // GIR_Coverage, 11242,
     /*  599171 */     GIR_EraseRootFromParent_Done,
     /*  599172 */   // Label 9254: @599172
     /*  599172 */   GIM_Reject,
     /*  599173 */ // Label 9124: @599173
     /*  599173 */ GIM_Reject,
     /*  599174 */ // Label 9016: @599174
     /*  599174 */ GIM_Reject,
     /*  599175 */ // Label 21: @599175
     /*  599175 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 9257*/ GIMT_Encode4(612786),
     /*  599186 */ /*GILLT_s32*//*Label 9255*/ GIMT_Encode4(599194),
     /*  599190 */ /*GILLT_s64*//*Label 9256*/ GIMT_Encode4(605286),
     /*  599194 */ // Label 9255: @599194
     /*  599194 */ GIM_Try, /*On fail goto*//*Label 9258*/ GIMT_Encode4(605285),
     /*  599199 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  599202 */   GIM_Try, /*On fail goto*//*Label 9259*/ GIMT_Encode4(599264), // Rule ID 20818 //
     /*  599207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  599210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599217 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599223 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599230 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64),
     /*  599233 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599262 */     GIR_RootConstrainSelectedInstOperands,
     /*  599263 */     // GIR_Coverage, 20818,
     /*  599263 */     GIR_EraseRootFromParent_Done,
     /*  599264 */   // Label 9259: @599264
     /*  599264 */   GIM_Try, /*On fail goto*//*Label 9260*/ GIMT_Encode4(599326), // Rule ID 20819 //
     /*  599269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  599272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599279 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599281 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599285 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599292 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64),
     /*  599295 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599324 */     GIR_RootConstrainSelectedInstOperands,
     /*  599325 */     // GIR_Coverage, 20819,
     /*  599325 */     GIR_EraseRootFromParent_Done,
     /*  599326 */   // Label 9260: @599326
     /*  599326 */   GIM_Try, /*On fail goto*//*Label 9261*/ GIMT_Encode4(599388), // Rule ID 20820 //
     /*  599331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  599334 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599341 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599354 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64),
     /*  599357 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599386 */     GIR_RootConstrainSelectedInstOperands,
     /*  599387 */     // GIR_Coverage, 20820,
     /*  599387 */     GIR_EraseRootFromParent_Done,
     /*  599388 */   // Label 9261: @599388
     /*  599388 */   GIM_Try, /*On fail goto*//*Label 9262*/ GIMT_Encode4(599450), // Rule ID 20821 //
     /*  599393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  599396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599403 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599416 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64),
     /*  599419 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599448 */     GIR_RootConstrainSelectedInstOperands,
     /*  599449 */     // GIR_Coverage, 20821,
     /*  599449 */     GIR_EraseRootFromParent_Done,
     /*  599450 */   // Label 9262: @599450
     /*  599450 */   GIM_Try, /*On fail goto*//*Label 9263*/ GIMT_Encode4(599512), // Rule ID 20822 //
     /*  599455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  599458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599465 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599478 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64),
     /*  599481 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599506 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599510 */     GIR_RootConstrainSelectedInstOperands,
     /*  599511 */     // GIR_Coverage, 20822,
     /*  599511 */     GIR_EraseRootFromParent_Done,
     /*  599512 */   // Label 9263: @599512
     /*  599512 */   GIM_Try, /*On fail goto*//*Label 9264*/ GIMT_Encode4(599574), // Rule ID 20838 //
     /*  599517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  599520 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599527 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599533 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599540 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64),
     /*  599543 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599572 */     GIR_RootConstrainSelectedInstOperands,
     /*  599573 */     // GIR_Coverage, 20838,
     /*  599573 */     GIR_EraseRootFromParent_Done,
     /*  599574 */   // Label 9264: @599574
     /*  599574 */   GIM_Try, /*On fail goto*//*Label 9265*/ GIMT_Encode4(599636), // Rule ID 20839 //
     /*  599579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  599582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599589 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599602 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64),
     /*  599605 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599634 */     GIR_RootConstrainSelectedInstOperands,
     /*  599635 */     // GIR_Coverage, 20839,
     /*  599635 */     GIR_EraseRootFromParent_Done,
     /*  599636 */   // Label 9265: @599636
     /*  599636 */   GIM_Try, /*On fail goto*//*Label 9266*/ GIMT_Encode4(599698), // Rule ID 20840 //
     /*  599641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  599644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599651 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599664 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64),
     /*  599667 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599696 */     GIR_RootConstrainSelectedInstOperands,
     /*  599697 */     // GIR_Coverage, 20840,
     /*  599697 */     GIR_EraseRootFromParent_Done,
     /*  599698 */   // Label 9266: @599698
     /*  599698 */   GIM_Try, /*On fail goto*//*Label 9267*/ GIMT_Encode4(599760), // Rule ID 20841 //
     /*  599703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  599706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599713 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599726 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64),
     /*  599729 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599758 */     GIR_RootConstrainSelectedInstOperands,
     /*  599759 */     // GIR_Coverage, 20841,
     /*  599759 */     GIR_EraseRootFromParent_Done,
     /*  599760 */   // Label 9267: @599760
     /*  599760 */   GIM_Try, /*On fail goto*//*Label 9268*/ GIMT_Encode4(599822), // Rule ID 20842 //
     /*  599765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  599768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599775 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  599777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599788 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64),
     /*  599791 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  599816 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599820 */     GIR_RootConstrainSelectedInstOperands,
     /*  599821 */     // GIR_Coverage, 20842,
     /*  599821 */     GIR_EraseRootFromParent_Done,
     /*  599822 */   // Label 9268: @599822
     /*  599822 */   GIM_Try, /*On fail goto*//*Label 9269*/ GIMT_Encode4(599888), // Rule ID 20808 //
     /*  599827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  599830 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  599841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599852 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN),
     /*  599855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  599857 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  599882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599886 */     GIR_RootConstrainSelectedInstOperands,
     /*  599887 */     // GIR_Coverage, 20808,
     /*  599887 */     GIR_EraseRootFromParent_Done,
     /*  599888 */   // Label 9269: @599888
     /*  599888 */   GIM_Try, /*On fail goto*//*Label 9270*/ GIMT_Encode4(599954), // Rule ID 20809 //
     /*  599893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  599896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  599907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599918 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN),
     /*  599921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  599923 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  599935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  599940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  599945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  599948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  599952 */     GIR_RootConstrainSelectedInstOperands,
     /*  599953 */     // GIR_Coverage, 20809,
     /*  599953 */     GIR_EraseRootFromParent_Done,
     /*  599954 */   // Label 9270: @599954
     /*  599954 */   GIM_Try, /*On fail goto*//*Label 9271*/ GIMT_Encode4(600020), // Rule ID 20810 //
     /*  599959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  599962 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  599969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  599973 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  599977 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  599984 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  599984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN),
     /*  599987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  599989 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  599991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  599996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600018 */     GIR_RootConstrainSelectedInstOperands,
     /*  600019 */     // GIR_Coverage, 20810,
     /*  600019 */     GIR_EraseRootFromParent_Done,
     /*  600020 */   // Label 9271: @600020
     /*  600020 */   GIM_Try, /*On fail goto*//*Label 9272*/ GIMT_Encode4(600086), // Rule ID 20811 //
     /*  600025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  600028 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600050 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN),
     /*  600053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600055 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600084 */     GIR_RootConstrainSelectedInstOperands,
     /*  600085 */     // GIR_Coverage, 20811,
     /*  600085 */     GIR_EraseRootFromParent_Done,
     /*  600086 */   // Label 9272: @600086
     /*  600086 */   GIM_Try, /*On fail goto*//*Label 9273*/ GIMT_Encode4(600152), // Rule ID 20812 //
     /*  600091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  600094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600116 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN),
     /*  600119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600121 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600150 */     GIR_RootConstrainSelectedInstOperands,
     /*  600151 */     // GIR_Coverage, 20812,
     /*  600151 */     GIR_EraseRootFromParent_Done,
     /*  600152 */   // Label 9273: @600152
     /*  600152 */   GIM_Try, /*On fail goto*//*Label 9274*/ GIMT_Encode4(600218), // Rule ID 20828 //
     /*  600157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  600160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600182 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN),
     /*  600185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600187 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600209 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600216 */     GIR_RootConstrainSelectedInstOperands,
     /*  600217 */     // GIR_Coverage, 20828,
     /*  600217 */     GIR_EraseRootFromParent_Done,
     /*  600218 */   // Label 9274: @600218
     /*  600218 */   GIM_Try, /*On fail goto*//*Label 9275*/ GIMT_Encode4(600284), // Rule ID 20829 //
     /*  600223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  600226 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600248 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN),
     /*  600251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600253 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600282 */     GIR_RootConstrainSelectedInstOperands,
     /*  600283 */     // GIR_Coverage, 20829,
     /*  600283 */     GIR_EraseRootFromParent_Done,
     /*  600284 */   // Label 9275: @600284
     /*  600284 */   GIM_Try, /*On fail goto*//*Label 9276*/ GIMT_Encode4(600350), // Rule ID 20830 //
     /*  600289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  600292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600314 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN),
     /*  600317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600319 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600348 */     GIR_RootConstrainSelectedInstOperands,
     /*  600349 */     // GIR_Coverage, 20830,
     /*  600349 */     GIR_EraseRootFromParent_Done,
     /*  600350 */   // Label 9276: @600350
     /*  600350 */   GIM_Try, /*On fail goto*//*Label 9277*/ GIMT_Encode4(600416), // Rule ID 20831 //
     /*  600355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  600358 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600369 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600380 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN),
     /*  600383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600385 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600414 */     GIR_RootConstrainSelectedInstOperands,
     /*  600415 */     // GIR_Coverage, 20831,
     /*  600415 */     GIR_EraseRootFromParent_Done,
     /*  600416 */   // Label 9277: @600416
     /*  600416 */   GIM_Try, /*On fail goto*//*Label 9278*/ GIMT_Encode4(600482), // Rule ID 20832 //
     /*  600421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  600424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  600435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  600446 */     // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN),
     /*  600449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  600451 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  600458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  600468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  600473 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  600476 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600480 */     GIR_RootConstrainSelectedInstOperands,
     /*  600481 */     // GIR_Coverage, 20832,
     /*  600481 */     GIR_EraseRootFromParent_Done,
     /*  600482 */   // Label 9278: @600482
     /*  600482 */   GIM_Try, /*On fail goto*//*Label 9279*/ GIMT_Encode4(600539), // Rule ID 20813 //
     /*  600487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  600490 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600497 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600503 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600510 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
     /*  600513 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600537 */     GIR_RootConstrainSelectedInstOperands,
     /*  600538 */     // GIR_Coverage, 20813,
     /*  600538 */     GIR_EraseRootFromParent_Done,
     /*  600539 */   // Label 9279: @600539
     /*  600539 */   GIM_Try, /*On fail goto*//*Label 9280*/ GIMT_Encode4(600596), // Rule ID 20814 //
     /*  600544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  600547 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600554 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600556 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600560 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600567 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
     /*  600570 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600594 */     GIR_RootConstrainSelectedInstOperands,
     /*  600595 */     // GIR_Coverage, 20814,
     /*  600595 */     GIR_EraseRootFromParent_Done,
     /*  600596 */   // Label 9280: @600596
     /*  600596 */   GIM_Try, /*On fail goto*//*Label 9281*/ GIMT_Encode4(600653), // Rule ID 20815 //
     /*  600601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  600604 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600611 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600624 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
     /*  600627 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600651 */     GIR_RootConstrainSelectedInstOperands,
     /*  600652 */     // GIR_Coverage, 20815,
     /*  600652 */     GIR_EraseRootFromParent_Done,
     /*  600653 */   // Label 9281: @600653
     /*  600653 */   GIM_Try, /*On fail goto*//*Label 9282*/ GIMT_Encode4(600710), // Rule ID 20816 //
     /*  600658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  600661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600668 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600674 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600681 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
     /*  600684 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600708 */     GIR_RootConstrainSelectedInstOperands,
     /*  600709 */     // GIR_Coverage, 20816,
     /*  600709 */     GIR_EraseRootFromParent_Done,
     /*  600710 */   // Label 9282: @600710
     /*  600710 */   GIM_Try, /*On fail goto*//*Label 9283*/ GIMT_Encode4(600767), // Rule ID 20817 //
     /*  600715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  600718 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600725 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600738 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
     /*  600741 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600758 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600765 */     GIR_RootConstrainSelectedInstOperands,
     /*  600766 */     // GIR_Coverage, 20817,
     /*  600766 */     GIR_EraseRootFromParent_Done,
     /*  600767 */   // Label 9283: @600767
     /*  600767 */   GIM_Try, /*On fail goto*//*Label 9284*/ GIMT_Encode4(600824), // Rule ID 20833 //
     /*  600772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  600775 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600782 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600795 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
     /*  600798 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600822 */     GIR_RootConstrainSelectedInstOperands,
     /*  600823 */     // GIR_Coverage, 20833,
     /*  600823 */     GIR_EraseRootFromParent_Done,
     /*  600824 */   // Label 9284: @600824
     /*  600824 */   GIM_Try, /*On fail goto*//*Label 9285*/ GIMT_Encode4(600881), // Rule ID 20834 //
     /*  600829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  600832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600839 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600852 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
     /*  600855 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600879 */     GIR_RootConstrainSelectedInstOperands,
     /*  600880 */     // GIR_Coverage, 20834,
     /*  600880 */     GIR_EraseRootFromParent_Done,
     /*  600881 */   // Label 9285: @600881
     /*  600881 */   GIM_Try, /*On fail goto*//*Label 9286*/ GIMT_Encode4(600938), // Rule ID 20835 //
     /*  600886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  600889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600896 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600909 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
     /*  600912 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600936 */     GIR_RootConstrainSelectedInstOperands,
     /*  600937 */     // GIR_Coverage, 20835,
     /*  600937 */     GIR_EraseRootFromParent_Done,
     /*  600938 */   // Label 9286: @600938
     /*  600938 */   GIM_Try, /*On fail goto*//*Label 9287*/ GIMT_Encode4(600995), // Rule ID 20836 //
     /*  600943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  600946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  600953 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  600955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  600959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  600966 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  600966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
     /*  600969 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  600971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  600976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  600981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  600986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  600989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  600993 */     GIR_RootConstrainSelectedInstOperands,
     /*  600994 */     // GIR_Coverage, 20836,
     /*  600994 */     GIR_EraseRootFromParent_Done,
     /*  600995 */   // Label 9287: @600995
     /*  600995 */   GIM_Try, /*On fail goto*//*Label 9288*/ GIMT_Encode4(601052), // Rule ID 20837 //
     /*  601000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  601003 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601010 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601012 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601016 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601023 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
     /*  601026 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601050 */     GIR_RootConstrainSelectedInstOperands,
     /*  601051 */     // GIR_Coverage, 20837,
     /*  601051 */     GIR_EraseRootFromParent_Done,
     /*  601052 */   // Label 9288: @601052
     /*  601052 */   GIM_Try, /*On fail goto*//*Label 9289*/ GIMT_Encode4(601113), // Rule ID 20803 //
     /*  601057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  601060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601082 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
     /*  601085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601087 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601111 */     GIR_RootConstrainSelectedInstOperands,
     /*  601112 */     // GIR_Coverage, 20803,
     /*  601112 */     GIR_EraseRootFromParent_Done,
     /*  601113 */   // Label 9289: @601113
     /*  601113 */   GIM_Try, /*On fail goto*//*Label 9290*/ GIMT_Encode4(601174), // Rule ID 20804 //
     /*  601118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  601121 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601143 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
     /*  601146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601148 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601172 */     GIR_RootConstrainSelectedInstOperands,
     /*  601173 */     // GIR_Coverage, 20804,
     /*  601173 */     GIR_EraseRootFromParent_Done,
     /*  601174 */   // Label 9290: @601174
     /*  601174 */   GIM_Try, /*On fail goto*//*Label 9291*/ GIMT_Encode4(601235), // Rule ID 20805 //
     /*  601179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  601182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601204 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
     /*  601207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601209 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601233 */     GIR_RootConstrainSelectedInstOperands,
     /*  601234 */     // GIR_Coverage, 20805,
     /*  601234 */     GIR_EraseRootFromParent_Done,
     /*  601235 */   // Label 9291: @601235
     /*  601235 */   GIM_Try, /*On fail goto*//*Label 9292*/ GIMT_Encode4(601296), // Rule ID 20806 //
     /*  601240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  601243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601254 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601265 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
     /*  601268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601270 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601294 */     GIR_RootConstrainSelectedInstOperands,
     /*  601295 */     // GIR_Coverage, 20806,
     /*  601295 */     GIR_EraseRootFromParent_Done,
     /*  601296 */   // Label 9292: @601296
     /*  601296 */   GIM_Try, /*On fail goto*//*Label 9293*/ GIMT_Encode4(601357), // Rule ID 20807 //
     /*  601301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  601304 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601326 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
     /*  601329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601331 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601355 */     GIR_RootConstrainSelectedInstOperands,
     /*  601356 */     // GIR_Coverage, 20807,
     /*  601356 */     GIR_EraseRootFromParent_Done,
     /*  601357 */   // Label 9293: @601357
     /*  601357 */   GIM_Try, /*On fail goto*//*Label 9294*/ GIMT_Encode4(601418), // Rule ID 20823 //
     /*  601362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  601365 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601387 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
     /*  601390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601392 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601416 */     GIR_RootConstrainSelectedInstOperands,
     /*  601417 */     // GIR_Coverage, 20823,
     /*  601417 */     GIR_EraseRootFromParent_Done,
     /*  601418 */   // Label 9294: @601418
     /*  601418 */   GIM_Try, /*On fail goto*//*Label 9295*/ GIMT_Encode4(601479), // Rule ID 20824 //
     /*  601423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  601426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601448 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
     /*  601451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601453 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601477 */     GIR_RootConstrainSelectedInstOperands,
     /*  601478 */     // GIR_Coverage, 20824,
     /*  601478 */     GIR_EraseRootFromParent_Done,
     /*  601479 */   // Label 9295: @601479
     /*  601479 */   GIM_Try, /*On fail goto*//*Label 9296*/ GIMT_Encode4(601540), // Rule ID 20825 //
     /*  601484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  601487 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601509 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
     /*  601512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601514 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601538 */     GIR_RootConstrainSelectedInstOperands,
     /*  601539 */     // GIR_Coverage, 20825,
     /*  601539 */     GIR_EraseRootFromParent_Done,
     /*  601540 */   // Label 9296: @601540
     /*  601540 */   GIM_Try, /*On fail goto*//*Label 9297*/ GIMT_Encode4(601601), // Rule ID 20826 //
     /*  601545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  601548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601570 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
     /*  601573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601575 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601599 */     GIR_RootConstrainSelectedInstOperands,
     /*  601600 */     // GIR_Coverage, 20826,
     /*  601600 */     GIR_EraseRootFromParent_Done,
     /*  601601 */   // Label 9297: @601601
     /*  601601 */   GIM_Try, /*On fail goto*//*Label 9298*/ GIMT_Encode4(601662), // Rule ID 20827 //
     /*  601606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  601609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  601616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  601620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  601631 */     // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  601631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
     /*  601634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  601636 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  601638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  601643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  601648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  601653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  601656 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601660 */     GIR_RootConstrainSelectedInstOperands,
     /*  601661 */     // GIR_Coverage, 20827,
     /*  601661 */     GIR_EraseRootFromParent_Done,
     /*  601662 */   // Label 9298: @601662
     /*  601662 */   GIM_Try, /*On fail goto*//*Label 9299*/ GIMT_Encode4(601712), // Rule ID 30294 //
     /*  601667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  601670 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601675 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601688 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  601691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601696 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  601703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601710 */     GIR_RootConstrainSelectedInstOperands,
     /*  601711 */     // GIR_Coverage, 30294,
     /*  601711 */     GIR_EraseRootFromParent_Done,
     /*  601712 */   // Label 9299: @601712
     /*  601712 */   GIM_Try, /*On fail goto*//*Label 9300*/ GIMT_Encode4(601762), // Rule ID 30295 //
     /*  601717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  601720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601725 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601738 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  601741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601746 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  601753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601760 */     GIR_RootConstrainSelectedInstOperands,
     /*  601761 */     // GIR_Coverage, 30295,
     /*  601761 */     GIR_EraseRootFromParent_Done,
     /*  601762 */   // Label 9300: @601762
     /*  601762 */   GIM_Try, /*On fail goto*//*Label 9301*/ GIMT_Encode4(601812), // Rule ID 30296 //
     /*  601767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  601770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601775 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601788 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  601791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601796 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  601803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601810 */     GIR_RootConstrainSelectedInstOperands,
     /*  601811 */     // GIR_Coverage, 30296,
     /*  601811 */     GIR_EraseRootFromParent_Done,
     /*  601812 */   // Label 9301: @601812
     /*  601812 */   GIM_Try, /*On fail goto*//*Label 9302*/ GIMT_Encode4(601862), // Rule ID 30297 //
     /*  601817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  601820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601825 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601838 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  601841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601846 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  601853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601860 */     GIR_RootConstrainSelectedInstOperands,
     /*  601861 */     // GIR_Coverage, 30297,
     /*  601861 */     GIR_EraseRootFromParent_Done,
     /*  601862 */   // Label 9302: @601862
     /*  601862 */   GIM_Try, /*On fail goto*//*Label 9303*/ GIMT_Encode4(601912), // Rule ID 30298 //
     /*  601867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  601870 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601875 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601888 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  601891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601896 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  601903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601910 */     GIR_RootConstrainSelectedInstOperands,
     /*  601911 */     // GIR_Coverage, 30298,
     /*  601911 */     GIR_EraseRootFromParent_Done,
     /*  601912 */   // Label 9303: @601912
     /*  601912 */   GIM_Try, /*On fail goto*//*Label 9304*/ GIMT_Encode4(601962), // Rule ID 30300 //
     /*  601917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  601920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601925 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601938 */     // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i32>>  =>  (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9),
     /*  601941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601946 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  601953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  601956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  601960 */     GIR_RootConstrainSelectedInstOperands,
     /*  601961 */     // GIR_Coverage, 30300,
     /*  601961 */     GIR_EraseRootFromParent_Done,
     /*  601962 */   // Label 9304: @601962
     /*  601962 */   GIM_Try, /*On fail goto*//*Label 9305*/ GIMT_Encode4(602012), // Rule ID 30301 //
     /*  601967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  601970 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  601975 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  601977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  601981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  601988 */     // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i32>>  =>  (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  601988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9),
     /*  601991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  601996 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  601998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602010 */     GIR_RootConstrainSelectedInstOperands,
     /*  602011 */     // GIR_Coverage, 30301,
     /*  602011 */     GIR_EraseRootFromParent_Done,
     /*  602012 */   // Label 9305: @602012
     /*  602012 */   GIM_Try, /*On fail goto*//*Label 9306*/ GIMT_Encode4(602062), // Rule ID 30302 //
     /*  602017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  602020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  602025 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602038 */     // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i32>>  =>  (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  602038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9),
     /*  602041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602046 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602060 */     GIR_RootConstrainSelectedInstOperands,
     /*  602061 */     // GIR_Coverage, 30302,
     /*  602061 */     GIR_EraseRootFromParent_Done,
     /*  602062 */   // Label 9306: @602062
     /*  602062 */   GIM_Try, /*On fail goto*//*Label 9307*/ GIMT_Encode4(602112), // Rule ID 30303 //
     /*  602067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  602070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  602075 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602088 */     // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i32>>  =>  (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  602088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9),
     /*  602091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602096 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602110 */     GIR_RootConstrainSelectedInstOperands,
     /*  602111 */     // GIR_Coverage, 30303,
     /*  602111 */     GIR_EraseRootFromParent_Done,
     /*  602112 */   // Label 9307: @602112
     /*  602112 */   GIM_Try, /*On fail goto*//*Label 9308*/ GIMT_Encode4(602162), // Rule ID 30304 //
     /*  602117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  602120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  602125 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602138 */     // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i32>>  =>  (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  602138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9),
     /*  602141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602146 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602160 */     GIR_RootConstrainSelectedInstOperands,
     /*  602161 */     // GIR_Coverage, 30304,
     /*  602161 */     GIR_EraseRootFromParent_Done,
     /*  602162 */   // Label 9308: @602162
     /*  602162 */   GIM_Try, /*On fail goto*//*Label 9309*/ GIMT_Encode4(602212), // Rule ID 30306 //
     /*  602167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  602170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  602175 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602188 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  602188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  602191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602196 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  602206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602210 */     GIR_RootConstrainSelectedInstOperands,
     /*  602211 */     // GIR_Coverage, 30306,
     /*  602211 */     GIR_EraseRootFromParent_Done,
     /*  602212 */   // Label 9309: @602212
     /*  602212 */   GIM_Try, /*On fail goto*//*Label 9310*/ GIMT_Encode4(602262), // Rule ID 30307 //
     /*  602217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  602220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  602225 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602227 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602231 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602238 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  602238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  602241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602246 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  602256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602260 */     GIR_RootConstrainSelectedInstOperands,
     /*  602261 */     // GIR_Coverage, 30307,
     /*  602261 */     GIR_EraseRootFromParent_Done,
     /*  602262 */   // Label 9310: @602262
     /*  602262 */   GIM_Try, /*On fail goto*//*Label 9311*/ GIMT_Encode4(602312), // Rule ID 30308 //
     /*  602267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  602270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  602275 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602288 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  602288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  602291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602296 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  602306 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602310 */     GIR_RootConstrainSelectedInstOperands,
     /*  602311 */     // GIR_Coverage, 30308,
     /*  602311 */     GIR_EraseRootFromParent_Done,
     /*  602312 */   // Label 9311: @602312
     /*  602312 */   GIM_Try, /*On fail goto*//*Label 9312*/ GIMT_Encode4(602362), // Rule ID 30309 //
     /*  602317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  602320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  602325 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602338 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  602338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  602341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602346 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  602356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602360 */     GIR_RootConstrainSelectedInstOperands,
     /*  602361 */     // GIR_Coverage, 30309,
     /*  602361 */     GIR_EraseRootFromParent_Done,
     /*  602362 */   // Label 9312: @602362
     /*  602362 */   GIM_Try, /*On fail goto*//*Label 9313*/ GIMT_Encode4(602412), // Rule ID 30310 //
     /*  602367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  602370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  602375 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602388 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  602388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
     /*  602391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602396 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  602406 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602410 */     GIR_RootConstrainSelectedInstOperands,
     /*  602411 */     // GIR_Coverage, 30310,
     /*  602411 */     GIR_EraseRootFromParent_Done,
     /*  602412 */   // Label 9313: @602412
     /*  602412 */   GIM_Try, /*On fail goto*//*Label 9314*/ GIMT_Encode4(602466), // Rule ID 30293 //
     /*  602417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  602420 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  602425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  602429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602440 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i32>>  =>  (DS_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  602440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32),
     /*  602443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  602445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602450 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602464 */     GIR_RootConstrainSelectedInstOperands,
     /*  602465 */     // GIR_Coverage, 30293,
     /*  602465 */     GIR_EraseRootFromParent_Done,
     /*  602466 */   // Label 9314: @602466
     /*  602466 */   GIM_Try, /*On fail goto*//*Label 9315*/ GIMT_Encode4(602520), // Rule ID 30299 //
     /*  602471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  602474 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  602479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  602483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602494 */     // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_i32>>  =>  (DS_SUB_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  602494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32_gfx9),
     /*  602497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  602499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602504 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602518 */     GIR_RootConstrainSelectedInstOperands,
     /*  602519 */     // GIR_Coverage, 30299,
     /*  602519 */     GIR_EraseRootFromParent_Done,
     /*  602520 */   // Label 9315: @602520
     /*  602520 */   GIM_Try, /*On fail goto*//*Label 9316*/ GIMT_Encode4(602574), // Rule ID 30305 //
     /*  602525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  602528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  602533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  602537 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602541 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  602548 */     // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i32>>  =>  (DS_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  602548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32),
     /*  602551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  602553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  602558 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  602560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  602568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602572 */     GIR_RootConstrainSelectedInstOperands,
     /*  602573 */     // GIR_Coverage, 30305,
     /*  602573 */     GIR_EraseRootFromParent_Done,
     /*  602574 */   // Label 9316: @602574
     /*  602574 */   GIM_Try, /*On fail goto*//*Label 9317*/ GIMT_Encode4(602633), // Rule ID 12897 //
     /*  602579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  602582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602589 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  602602 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  602602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR),
     /*  602605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  602610 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  602617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  602622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  602627 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602631 */     GIR_RootConstrainSelectedInstOperands,
     /*  602632 */     // GIR_Coverage, 12897,
     /*  602632 */     GIR_EraseRootFromParent_Done,
     /*  602633 */   // Label 9317: @602633
     /*  602633 */   GIM_Try, /*On fail goto*//*Label 9318*/ GIMT_Encode4(602692), // Rule ID 12898 //
     /*  602638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  602641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602648 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  602661 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  602661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR),
     /*  602664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  602669 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  602676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  602681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  602686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602690 */     GIR_RootConstrainSelectedInstOperands,
     /*  602691 */     // GIR_Coverage, 12898,
     /*  602691 */     GIR_EraseRootFromParent_Done,
     /*  602692 */   // Label 9318: @602692
     /*  602692 */   GIM_Try, /*On fail goto*//*Label 9319*/ GIMT_Encode4(602751), // Rule ID 12899 //
     /*  602697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  602700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602707 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  602720 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  602720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR),
     /*  602723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  602728 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  602735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  602740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  602745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602749 */     GIR_RootConstrainSelectedInstOperands,
     /*  602750 */     // GIR_Coverage, 12899,
     /*  602750 */     GIR_EraseRootFromParent_Done,
     /*  602751 */   // Label 9319: @602751
     /*  602751 */   GIM_Try, /*On fail goto*//*Label 9320*/ GIMT_Encode4(602810), // Rule ID 12900 //
     /*  602756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  602759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602766 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602768 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  602779 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  602779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR),
     /*  602782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  602787 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  602794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  602799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  602804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602808 */     GIR_RootConstrainSelectedInstOperands,
     /*  602809 */     // GIR_Coverage, 12900,
     /*  602809 */     GIR_EraseRootFromParent_Done,
     /*  602810 */   // Label 9320: @602810
     /*  602810 */   GIM_Try, /*On fail goto*//*Label 9321*/ GIMT_Encode4(602869), // Rule ID 12901 //
     /*  602815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  602818 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602825 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  602838 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  602838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR),
     /*  602841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  602846 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  602853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  602858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  602863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602867 */     GIR_RootConstrainSelectedInstOperands,
     /*  602868 */     // GIR_Coverage, 12901,
     /*  602868 */     GIR_EraseRootFromParent_Done,
     /*  602869 */   // Label 9321: @602869
     /*  602869 */   GIM_Try, /*On fail goto*//*Label 9322*/ GIMT_Encode4(602932), // Rule ID 12907 //
     /*  602874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  602877 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  602888 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  602899 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  602899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN),
     /*  602902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  602904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  602909 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  602916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  602921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  602926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602930 */     GIR_RootConstrainSelectedInstOperands,
     /*  602931 */     // GIR_Coverage, 12907,
     /*  602931 */     GIR_EraseRootFromParent_Done,
     /*  602932 */   // Label 9322: @602932
     /*  602932 */   GIM_Try, /*On fail goto*//*Label 9323*/ GIMT_Encode4(602984), // Rule ID 12892 //
     /*  602937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  602940 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602947 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  602949 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  602953 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  602960 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  602960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB),
     /*  602963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  602968 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  602970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  602975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  602978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  602982 */     GIR_RootConstrainSelectedInstOperands,
     /*  602983 */     // GIR_Coverage, 12892,
     /*  602983 */     GIR_EraseRootFromParent_Done,
     /*  602984 */   // Label 9323: @602984
     /*  602984 */   GIM_Try, /*On fail goto*//*Label 9324*/ GIMT_Encode4(603036), // Rule ID 12893 //
     /*  602989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  602992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  602999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603012 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB),
     /*  603015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603020 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  603030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603034 */     GIR_RootConstrainSelectedInstOperands,
     /*  603035 */     // GIR_Coverage, 12893,
     /*  603035 */     GIR_EraseRootFromParent_Done,
     /*  603036 */   // Label 9324: @603036
     /*  603036 */   GIM_Try, /*On fail goto*//*Label 9325*/ GIMT_Encode4(603088), // Rule ID 12894 //
     /*  603041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  603044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603051 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603064 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB),
     /*  603067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603072 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  603082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603086 */     GIR_RootConstrainSelectedInstOperands,
     /*  603087 */     // GIR_Coverage, 12894,
     /*  603087 */     GIR_EraseRootFromParent_Done,
     /*  603088 */   // Label 9325: @603088
     /*  603088 */   GIM_Try, /*On fail goto*//*Label 9326*/ GIMT_Encode4(603140), // Rule ID 12895 //
     /*  603093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  603096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603103 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603116 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB),
     /*  603119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603124 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  603134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603138 */     GIR_RootConstrainSelectedInstOperands,
     /*  603139 */     // GIR_Coverage, 12895,
     /*  603139 */     GIR_EraseRootFromParent_Done,
     /*  603140 */   // Label 9326: @603140
     /*  603140 */   GIM_Try, /*On fail goto*//*Label 9327*/ GIMT_Encode4(603192), // Rule ID 12896 //
     /*  603145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  603148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603155 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603168 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB),
     /*  603171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603176 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  603186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603190 */     GIR_RootConstrainSelectedInstOperands,
     /*  603191 */     // GIR_Coverage, 12896,
     /*  603191 */     GIR_EraseRootFromParent_Done,
     /*  603192 */   // Label 9327: @603192
     /*  603192 */   GIM_Try, /*On fail goto*//*Label 9328*/ GIMT_Encode4(603248), // Rule ID 12902 //
     /*  603197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  603200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  603211 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603222 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN),
     /*  603225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  603227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603232 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  603242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603246 */     GIR_RootConstrainSelectedInstOperands,
     /*  603247 */     // GIR_Coverage, 12902,
     /*  603247 */     GIR_EraseRootFromParent_Done,
     /*  603248 */   // Label 9328: @603248
     /*  603248 */   GIM_Try, /*On fail goto*//*Label 9329*/ GIMT_Encode4(603304), // Rule ID 12903 //
     /*  603253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  603256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  603267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603278 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN),
     /*  603281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  603283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603288 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  603298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603302 */     GIR_RootConstrainSelectedInstOperands,
     /*  603303 */     // GIR_Coverage, 12903,
     /*  603303 */     GIR_EraseRootFromParent_Done,
     /*  603304 */   // Label 9329: @603304
     /*  603304 */   GIM_Try, /*On fail goto*//*Label 9330*/ GIMT_Encode4(603360), // Rule ID 12904 //
     /*  603309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  603312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  603323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603334 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN),
     /*  603337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  603339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603344 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  603354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603358 */     GIR_RootConstrainSelectedInstOperands,
     /*  603359 */     // GIR_Coverage, 12904,
     /*  603359 */     GIR_EraseRootFromParent_Done,
     /*  603360 */   // Label 9330: @603360
     /*  603360 */   GIM_Try, /*On fail goto*//*Label 9331*/ GIMT_Encode4(603416), // Rule ID 12905 //
     /*  603365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  603368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  603379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603390 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN),
     /*  603393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  603395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  603410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603414 */     GIR_RootConstrainSelectedInstOperands,
     /*  603415 */     // GIR_Coverage, 12905,
     /*  603415 */     GIR_EraseRootFromParent_Done,
     /*  603416 */   // Label 9331: @603416
     /*  603416 */   GIM_Try, /*On fail goto*//*Label 9332*/ GIMT_Encode4(603472), // Rule ID 12906 //
     /*  603421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  603424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  603435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  603446 */     // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  603446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN),
     /*  603449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  603451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  603456 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  603463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  603466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603470 */     GIR_RootConstrainSelectedInstOperands,
     /*  603471 */     // GIR_Coverage, 12906,
     /*  603471 */     GIR_EraseRootFromParent_Done,
     /*  603472 */   // Label 9332: @603472
     /*  603472 */   GIM_Try, /*On fail goto*//*Label 9333*/ GIMT_Encode4(603532), // Rule ID 10497 //
     /*  603477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  603480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603488 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603501 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603509 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603530 */     GIR_RootConstrainSelectedInstOperands,
     /*  603531 */     // GIR_Coverage, 10497,
     /*  603531 */     GIR_EraseRootFromParent_Done,
     /*  603532 */   // Label 9333: @603532
     /*  603532 */   GIM_Try, /*On fail goto*//*Label 9334*/ GIMT_Encode4(603592), // Rule ID 10498 //
     /*  603537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  603540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603548 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603561 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603569 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603590 */     GIR_RootConstrainSelectedInstOperands,
     /*  603591 */     // GIR_Coverage, 10498,
     /*  603591 */     GIR_EraseRootFromParent_Done,
     /*  603592 */   // Label 9334: @603592
     /*  603592 */   GIM_Try, /*On fail goto*//*Label 9335*/ GIMT_Encode4(603652), // Rule ID 10499 //
     /*  603597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  603600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603608 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603621 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603629 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603650 */     GIR_RootConstrainSelectedInstOperands,
     /*  603651 */     // GIR_Coverage, 10499,
     /*  603651 */     GIR_EraseRootFromParent_Done,
     /*  603652 */   // Label 9335: @603652
     /*  603652 */   GIM_Try, /*On fail goto*//*Label 9336*/ GIMT_Encode4(603712), // Rule ID 10500 //
     /*  603657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  603660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603668 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603674 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603681 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603689 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603710 */     GIR_RootConstrainSelectedInstOperands,
     /*  603711 */     // GIR_Coverage, 10500,
     /*  603711 */     GIR_EraseRootFromParent_Done,
     /*  603712 */   // Label 9336: @603712
     /*  603712 */   GIM_Try, /*On fail goto*//*Label 9337*/ GIMT_Encode4(603772), // Rule ID 10501 //
     /*  603717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  603720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603728 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603741 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603749 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603770 */     GIR_RootConstrainSelectedInstOperands,
     /*  603771 */     // GIR_Coverage, 10501,
     /*  603771 */     GIR_EraseRootFromParent_Done,
     /*  603772 */   // Label 9337: @603772
     /*  603772 */   GIM_Try, /*On fail goto*//*Label 9338*/ GIMT_Encode4(603831), // Rule ID 11053 //
     /*  603777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  603780 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603787 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603800 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603808 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603829 */     GIR_RootConstrainSelectedInstOperands,
     /*  603830 */     // GIR_Coverage, 11053,
     /*  603830 */     GIR_EraseRootFromParent_Done,
     /*  603831 */   // Label 9338: @603831
     /*  603831 */   GIM_Try, /*On fail goto*//*Label 9339*/ GIMT_Encode4(603890), // Rule ID 11054 //
     /*  603836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  603839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603846 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603859 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603867 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603888 */     GIR_RootConstrainSelectedInstOperands,
     /*  603889 */     // GIR_Coverage, 11054,
     /*  603889 */     GIR_EraseRootFromParent_Done,
     /*  603890 */   // Label 9339: @603890
     /*  603890 */   GIM_Try, /*On fail goto*//*Label 9340*/ GIMT_Encode4(603949), // Rule ID 11055 //
     /*  603895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  603898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603905 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603918 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603926 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  603943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  603947 */     GIR_RootConstrainSelectedInstOperands,
     /*  603948 */     // GIR_Coverage, 11055,
     /*  603948 */     GIR_EraseRootFromParent_Done,
     /*  603949 */   // Label 9340: @603949
     /*  603949 */   GIM_Try, /*On fail goto*//*Label 9341*/ GIMT_Encode4(604008), // Rule ID 11056 //
     /*  603954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  603957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  603964 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  603966 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  603970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  603977 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  603977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  603980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  603985 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  603987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  603992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  603997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  604002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604006 */     GIR_RootConstrainSelectedInstOperands,
     /*  604007 */     // GIR_Coverage, 11056,
     /*  604007 */     GIR_EraseRootFromParent_Done,
     /*  604008 */   // Label 9341: @604008
     /*  604008 */   GIM_Try, /*On fail goto*//*Label 9342*/ GIMT_Encode4(604067), // Rule ID 11057 //
     /*  604013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  604016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604023 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604025 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604029 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  604036 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  604036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR),
     /*  604039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  604044 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  604051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  604056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  604061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604065 */     GIR_RootConstrainSelectedInstOperands,
     /*  604066 */     // GIR_Coverage, 11057,
     /*  604066 */     GIR_EraseRootFromParent_Done,
     /*  604067 */   // Label 9342: @604067
     /*  604067 */   GIM_Try, /*On fail goto*//*Label 9343*/ GIMT_Encode4(604131), // Rule ID 10491 //
     /*  604072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  604075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604087 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  604098 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  604098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR_RTN),
     /*  604101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  604108 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  604115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  604120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  604125 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604129 */     GIR_RootConstrainSelectedInstOperands,
     /*  604130 */     // GIR_Coverage, 10491,
     /*  604130 */     GIR_EraseRootFromParent_Done,
     /*  604131 */   // Label 9343: @604131
     /*  604131 */   GIM_Try, /*On fail goto*//*Label 9344*/ GIMT_Encode4(604194), // Rule ID 11047 //
     /*  604136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  604139 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  604161 */     // (atomic_load_sub:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (FLAT_ATOMIC_SUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  604161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_SADDR_RTN),
     /*  604164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  604171 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  604178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  604183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  604188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604192 */     GIR_RootConstrainSelectedInstOperands,
     /*  604193 */     // GIR_Coverage, 11047,
     /*  604193 */     GIR_EraseRootFromParent_Done,
     /*  604194 */   // Label 9344: @604194
     /*  604194 */   GIM_Try, /*On fail goto*//*Label 9345*/ GIMT_Encode4(604247), // Rule ID 10492 //
     /*  604199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  604202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604210 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604212 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604216 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604223 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604231 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604241 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604245 */     GIR_RootConstrainSelectedInstOperands,
     /*  604246 */     // GIR_Coverage, 10492,
     /*  604246 */     GIR_EraseRootFromParent_Done,
     /*  604247 */   // Label 9345: @604247
     /*  604247 */   GIM_Try, /*On fail goto*//*Label 9346*/ GIMT_Encode4(604300), // Rule ID 10493 //
     /*  604252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  604255 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604263 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604276 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604284 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604298 */     GIR_RootConstrainSelectedInstOperands,
     /*  604299 */     // GIR_Coverage, 10493,
     /*  604299 */     GIR_EraseRootFromParent_Done,
     /*  604300 */   // Label 9346: @604300
     /*  604300 */   GIM_Try, /*On fail goto*//*Label 9347*/ GIMT_Encode4(604353), // Rule ID 10494 //
     /*  604305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  604308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604316 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604329 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604337 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604347 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604351 */     GIR_RootConstrainSelectedInstOperands,
     /*  604352 */     // GIR_Coverage, 10494,
     /*  604352 */     GIR_EraseRootFromParent_Done,
     /*  604353 */   // Label 9347: @604353
     /*  604353 */   GIM_Try, /*On fail goto*//*Label 9348*/ GIMT_Encode4(604406), // Rule ID 10495 //
     /*  604358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  604361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604369 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604382 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604390 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604404 */     GIR_RootConstrainSelectedInstOperands,
     /*  604405 */     // GIR_Coverage, 10495,
     /*  604405 */     GIR_EraseRootFromParent_Done,
     /*  604406 */   // Label 9348: @604406
     /*  604406 */   GIM_Try, /*On fail goto*//*Label 9349*/ GIMT_Encode4(604459), // Rule ID 10496 //
     /*  604411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  604414 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604422 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604424 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604435 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604443 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604457 */     GIR_RootConstrainSelectedInstOperands,
     /*  604458 */     // GIR_Coverage, 10496,
     /*  604458 */     GIR_EraseRootFromParent_Done,
     /*  604459 */   // Label 9349: @604459
     /*  604459 */   GIM_Try, /*On fail goto*//*Label 9350*/ GIMT_Encode4(604511), // Rule ID 11048 //
     /*  604464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  604467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604474 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604476 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604480 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604487 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604495 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604509 */     GIR_RootConstrainSelectedInstOperands,
     /*  604510 */     // GIR_Coverage, 11048,
     /*  604510 */     GIR_EraseRootFromParent_Done,
     /*  604511 */   // Label 9350: @604511
     /*  604511 */   GIM_Try, /*On fail goto*//*Label 9351*/ GIMT_Encode4(604563), // Rule ID 11049 //
     /*  604516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  604519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604526 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604539 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604547 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604554 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604557 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604561 */     GIR_RootConstrainSelectedInstOperands,
     /*  604562 */     // GIR_Coverage, 11049,
     /*  604562 */     GIR_EraseRootFromParent_Done,
     /*  604563 */   // Label 9351: @604563
     /*  604563 */   GIM_Try, /*On fail goto*//*Label 9352*/ GIMT_Encode4(604615), // Rule ID 11050 //
     /*  604568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  604571 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604578 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604591 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604599 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604613 */     GIR_RootConstrainSelectedInstOperands,
     /*  604614 */     // GIR_Coverage, 11050,
     /*  604614 */     GIR_EraseRootFromParent_Done,
     /*  604615 */   // Label 9352: @604615
     /*  604615 */   GIM_Try, /*On fail goto*//*Label 9353*/ GIMT_Encode4(604667), // Rule ID 11051 //
     /*  604620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  604623 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604630 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604643 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604651 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604665 */     GIR_RootConstrainSelectedInstOperands,
     /*  604666 */     // GIR_Coverage, 11051,
     /*  604666 */     GIR_EraseRootFromParent_Done,
     /*  604667 */   // Label 9353: @604667
     /*  604667 */   GIM_Try, /*On fail goto*//*Label 9354*/ GIMT_Encode4(604719), // Rule ID 11052 //
     /*  604672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  604675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604682 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  604684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604695 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>>  =>  (FLAT_ATOMIC_SUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
     /*  604698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604703 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  604713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604717 */     GIR_RootConstrainSelectedInstOperands,
     /*  604718 */     // GIR_Coverage, 11052,
     /*  604718 */     GIR_EraseRootFromParent_Done,
     /*  604719 */   // Label 9354: @604719
     /*  604719 */   GIM_Try, /*On fail goto*//*Label 9355*/ GIMT_Encode4(604776), // Rule ID 10486 //
     /*  604724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  604727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604739 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604743 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604750 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  604753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604760 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  604770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604774 */     GIR_RootConstrainSelectedInstOperands,
     /*  604775 */     // GIR_Coverage, 10486,
     /*  604775 */     GIR_EraseRootFromParent_Done,
     /*  604776 */   // Label 9355: @604776
     /*  604776 */   GIM_Try, /*On fail goto*//*Label 9356*/ GIMT_Encode4(604833), // Rule ID 10487 //
     /*  604781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  604784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604807 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  604810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604817 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  604827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604831 */     GIR_RootConstrainSelectedInstOperands,
     /*  604832 */     // GIR_Coverage, 10487,
     /*  604832 */     GIR_EraseRootFromParent_Done,
     /*  604833 */   // Label 9356: @604833
     /*  604833 */   GIM_Try, /*On fail goto*//*Label 9357*/ GIMT_Encode4(604890), // Rule ID 10488 //
     /*  604838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  604841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604864 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  604867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604874 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  604884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604888 */     GIR_RootConstrainSelectedInstOperands,
     /*  604889 */     // GIR_Coverage, 10488,
     /*  604889 */     GIR_EraseRootFromParent_Done,
     /*  604890 */   // Label 9357: @604890
     /*  604890 */   GIM_Try, /*On fail goto*//*Label 9358*/ GIMT_Encode4(604947), // Rule ID 10489 //
     /*  604895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  604898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604921 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  604924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604931 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  604941 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  604945 */     GIR_RootConstrainSelectedInstOperands,
     /*  604946 */     // GIR_Coverage, 10489,
     /*  604946 */     GIR_EraseRootFromParent_Done,
     /*  604947 */   // Label 9358: @604947
     /*  604947 */   GIM_Try, /*On fail goto*//*Label 9359*/ GIMT_Encode4(605004), // Rule ID 10490 //
     /*  604952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  604955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  604963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  604967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  604971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  604978 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  604978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  604981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  604983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  604988 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  604990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  604995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  604998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605002 */     GIR_RootConstrainSelectedInstOperands,
     /*  605003 */     // GIR_Coverage, 10490,
     /*  605003 */     GIR_EraseRootFromParent_Done,
     /*  605004 */   // Label 9359: @605004
     /*  605004 */   GIM_Try, /*On fail goto*//*Label 9360*/ GIMT_Encode4(605060), // Rule ID 11042 //
     /*  605009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  605012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  605023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  605034 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  605034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  605037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  605039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  605044 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  605046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  605051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  605054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605058 */     GIR_RootConstrainSelectedInstOperands,
     /*  605059 */     // GIR_Coverage, 11042,
     /*  605059 */     GIR_EraseRootFromParent_Done,
     /*  605060 */   // Label 9360: @605060
     /*  605060 */   GIM_Try, /*On fail goto*//*Label 9361*/ GIMT_Encode4(605116), // Rule ID 11043 //
     /*  605065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  605068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  605079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  605090 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  605090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  605093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  605095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  605100 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  605102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  605107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  605110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605114 */     GIR_RootConstrainSelectedInstOperands,
     /*  605115 */     // GIR_Coverage, 11043,
     /*  605115 */     GIR_EraseRootFromParent_Done,
     /*  605116 */   // Label 9361: @605116
     /*  605116 */   GIM_Try, /*On fail goto*//*Label 9362*/ GIMT_Encode4(605172), // Rule ID 11044 //
     /*  605121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  605124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  605135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  605146 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  605146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  605149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  605151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  605156 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  605158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  605163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  605166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605170 */     GIR_RootConstrainSelectedInstOperands,
     /*  605171 */     // GIR_Coverage, 11044,
     /*  605171 */     GIR_EraseRootFromParent_Done,
     /*  605172 */   // Label 9362: @605172
     /*  605172 */   GIM_Try, /*On fail goto*//*Label 9363*/ GIMT_Encode4(605228), // Rule ID 11045 //
     /*  605177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  605180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  605191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  605202 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  605202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  605205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  605207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  605212 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  605214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  605219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  605222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605226 */     GIR_RootConstrainSelectedInstOperands,
     /*  605227 */     // GIR_Coverage, 11045,
     /*  605227 */     GIR_EraseRootFromParent_Done,
     /*  605228 */   // Label 9363: @605228
     /*  605228 */   GIM_Try, /*On fail goto*//*Label 9364*/ GIMT_Encode4(605284), // Rule ID 11046 //
     /*  605233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  605236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  605247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  605258 */     // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  605258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
     /*  605261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  605263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  605268 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  605270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  605275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  605278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605282 */     GIR_RootConstrainSelectedInstOperands,
     /*  605283 */     // GIR_Coverage, 11046,
     /*  605283 */     GIR_EraseRootFromParent_Done,
     /*  605284 */   // Label 9364: @605284
     /*  605284 */   GIM_Reject,
     /*  605285 */ // Label 9258: @605285
     /*  605285 */ GIM_Reject,
     /*  605286 */ // Label 9256: @605286
     /*  605286 */ GIM_Try, /*On fail goto*//*Label 9365*/ GIMT_Encode4(612785),
     /*  605291 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  605294 */   GIM_Try, /*On fail goto*//*Label 9366*/ GIMT_Encode4(605356), // Rule ID 21298 //
     /*  605299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  605302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605309 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605322 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64),
     /*  605325 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605354 */     GIR_RootConstrainSelectedInstOperands,
     /*  605355 */     // GIR_Coverage, 21298,
     /*  605355 */     GIR_EraseRootFromParent_Done,
     /*  605356 */   // Label 9366: @605356
     /*  605356 */   GIM_Try, /*On fail goto*//*Label 9367*/ GIMT_Encode4(605418), // Rule ID 21299 //
     /*  605361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  605364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605371 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605373 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605384 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64),
     /*  605387 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605416 */     GIR_RootConstrainSelectedInstOperands,
     /*  605417 */     // GIR_Coverage, 21299,
     /*  605417 */     GIR_EraseRootFromParent_Done,
     /*  605418 */   // Label 9367: @605418
     /*  605418 */   GIM_Try, /*On fail goto*//*Label 9368*/ GIMT_Encode4(605480), // Rule ID 21300 //
     /*  605423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  605426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605433 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605446 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64),
     /*  605449 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605478 */     GIR_RootConstrainSelectedInstOperands,
     /*  605479 */     // GIR_Coverage, 21300,
     /*  605479 */     GIR_EraseRootFromParent_Done,
     /*  605480 */   // Label 9368: @605480
     /*  605480 */   GIM_Try, /*On fail goto*//*Label 9369*/ GIMT_Encode4(605542), // Rule ID 21301 //
     /*  605485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  605488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605495 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605508 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64),
     /*  605511 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605533 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605536 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605540 */     GIR_RootConstrainSelectedInstOperands,
     /*  605541 */     // GIR_Coverage, 21301,
     /*  605541 */     GIR_EraseRootFromParent_Done,
     /*  605542 */   // Label 9369: @605542
     /*  605542 */   GIM_Try, /*On fail goto*//*Label 9370*/ GIMT_Encode4(605604), // Rule ID 21302 //
     /*  605547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  605550 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605557 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605570 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64),
     /*  605573 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605602 */     GIR_RootConstrainSelectedInstOperands,
     /*  605603 */     // GIR_Coverage, 21302,
     /*  605603 */     GIR_EraseRootFromParent_Done,
     /*  605604 */   // Label 9370: @605604
     /*  605604 */   GIM_Try, /*On fail goto*//*Label 9371*/ GIMT_Encode4(605666), // Rule ID 21318 //
     /*  605609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  605612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605619 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605632 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64),
     /*  605635 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605664 */     GIR_RootConstrainSelectedInstOperands,
     /*  605665 */     // GIR_Coverage, 21318,
     /*  605665 */     GIR_EraseRootFromParent_Done,
     /*  605666 */   // Label 9371: @605666
     /*  605666 */   GIM_Try, /*On fail goto*//*Label 9372*/ GIMT_Encode4(605728), // Rule ID 21319 //
     /*  605671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  605674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605681 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605694 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64),
     /*  605697 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605726 */     GIR_RootConstrainSelectedInstOperands,
     /*  605727 */     // GIR_Coverage, 21319,
     /*  605727 */     GIR_EraseRootFromParent_Done,
     /*  605728 */   // Label 9372: @605728
     /*  605728 */   GIM_Try, /*On fail goto*//*Label 9373*/ GIMT_Encode4(605790), // Rule ID 21320 //
     /*  605733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  605736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605743 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605756 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64),
     /*  605759 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605788 */     GIR_RootConstrainSelectedInstOperands,
     /*  605789 */     // GIR_Coverage, 21320,
     /*  605789 */     GIR_EraseRootFromParent_Done,
     /*  605790 */   // Label 9373: @605790
     /*  605790 */   GIM_Try, /*On fail goto*//*Label 9374*/ GIMT_Encode4(605852), // Rule ID 21321 //
     /*  605795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  605798 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605805 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605818 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64),
     /*  605821 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605850 */     GIR_RootConstrainSelectedInstOperands,
     /*  605851 */     // GIR_Coverage, 21321,
     /*  605851 */     GIR_EraseRootFromParent_Done,
     /*  605852 */   // Label 9374: @605852
     /*  605852 */   GIM_Try, /*On fail goto*//*Label 9375*/ GIMT_Encode4(605914), // Rule ID 21322 //
     /*  605857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  605860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605867 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  605869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605880 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64),
     /*  605883 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  605908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605912 */     GIR_RootConstrainSelectedInstOperands,
     /*  605913 */     // GIR_Coverage, 21322,
     /*  605913 */     GIR_EraseRootFromParent_Done,
     /*  605914 */   // Label 9375: @605914
     /*  605914 */   GIM_Try, /*On fail goto*//*Label 9376*/ GIMT_Encode4(605980), // Rule ID 21288 //
     /*  605919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  605922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  605933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  605937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  605944 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  605944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN),
     /*  605947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  605949 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  605951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  605956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  605961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  605966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  605971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  605974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  605978 */     GIR_RootConstrainSelectedInstOperands,
     /*  605979 */     // GIR_Coverage, 21288,
     /*  605979 */     GIR_EraseRootFromParent_Done,
     /*  605980 */   // Label 9376: @605980
     /*  605980 */   GIM_Try, /*On fail goto*//*Label 9377*/ GIMT_Encode4(606046), // Rule ID 21289 //
     /*  605985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  605988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  605995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  605999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606010 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN),
     /*  606013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606015 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606044 */     GIR_RootConstrainSelectedInstOperands,
     /*  606045 */     // GIR_Coverage, 21289,
     /*  606045 */     GIR_EraseRootFromParent_Done,
     /*  606046 */   // Label 9377: @606046
     /*  606046 */   GIM_Try, /*On fail goto*//*Label 9378*/ GIMT_Encode4(606112), // Rule ID 21290 //
     /*  606051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  606054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606076 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN),
     /*  606079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606081 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606110 */     GIR_RootConstrainSelectedInstOperands,
     /*  606111 */     // GIR_Coverage, 21290,
     /*  606111 */     GIR_EraseRootFromParent_Done,
     /*  606112 */   // Label 9378: @606112
     /*  606112 */   GIM_Try, /*On fail goto*//*Label 9379*/ GIMT_Encode4(606178), // Rule ID 21291 //
     /*  606117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  606120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606142 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN),
     /*  606145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606147 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606176 */     GIR_RootConstrainSelectedInstOperands,
     /*  606177 */     // GIR_Coverage, 21291,
     /*  606177 */     GIR_EraseRootFromParent_Done,
     /*  606178 */   // Label 9379: @606178
     /*  606178 */   GIM_Try, /*On fail goto*//*Label 9380*/ GIMT_Encode4(606244), // Rule ID 21292 //
     /*  606183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  606186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606197 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606208 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN),
     /*  606211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606213 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606242 */     GIR_RootConstrainSelectedInstOperands,
     /*  606243 */     // GIR_Coverage, 21292,
     /*  606243 */     GIR_EraseRootFromParent_Done,
     /*  606244 */   // Label 9380: @606244
     /*  606244 */   GIM_Try, /*On fail goto*//*Label 9381*/ GIMT_Encode4(606310), // Rule ID 21308 //
     /*  606249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  606252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606274 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN),
     /*  606277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606279 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606308 */     GIR_RootConstrainSelectedInstOperands,
     /*  606309 */     // GIR_Coverage, 21308,
     /*  606309 */     GIR_EraseRootFromParent_Done,
     /*  606310 */   // Label 9381: @606310
     /*  606310 */   GIM_Try, /*On fail goto*//*Label 9382*/ GIMT_Encode4(606376), // Rule ID 21309 //
     /*  606315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  606318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606340 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN),
     /*  606343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606345 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606374 */     GIR_RootConstrainSelectedInstOperands,
     /*  606375 */     // GIR_Coverage, 21309,
     /*  606375 */     GIR_EraseRootFromParent_Done,
     /*  606376 */   // Label 9382: @606376
     /*  606376 */   GIM_Try, /*On fail goto*//*Label 9383*/ GIMT_Encode4(606442), // Rule ID 21310 //
     /*  606381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  606384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606406 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN),
     /*  606409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606411 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606440 */     GIR_RootConstrainSelectedInstOperands,
     /*  606441 */     // GIR_Coverage, 21310,
     /*  606441 */     GIR_EraseRootFromParent_Done,
     /*  606442 */   // Label 9383: @606442
     /*  606442 */   GIM_Try, /*On fail goto*//*Label 9384*/ GIMT_Encode4(606508), // Rule ID 21311 //
     /*  606447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  606450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606472 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN),
     /*  606475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606477 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606506 */     GIR_RootConstrainSelectedInstOperands,
     /*  606507 */     // GIR_Coverage, 21311,
     /*  606507 */     GIR_EraseRootFromParent_Done,
     /*  606508 */   // Label 9384: @606508
     /*  606508 */   GIM_Try, /*On fail goto*//*Label 9385*/ GIMT_Encode4(606574), // Rule ID 21312 //
     /*  606513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  606516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  606527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  606538 */     // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN),
     /*  606541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  606543 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  606550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  606560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  606565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  606568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606572 */     GIR_RootConstrainSelectedInstOperands,
     /*  606573 */     // GIR_Coverage, 21312,
     /*  606573 */     GIR_EraseRootFromParent_Done,
     /*  606574 */   // Label 9385: @606574
     /*  606574 */   GIM_Try, /*On fail goto*//*Label 9386*/ GIMT_Encode4(606631), // Rule ID 21293 //
     /*  606579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  606582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606589 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606602 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
     /*  606605 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606629 */     GIR_RootConstrainSelectedInstOperands,
     /*  606630 */     // GIR_Coverage, 21293,
     /*  606630 */     GIR_EraseRootFromParent_Done,
     /*  606631 */   // Label 9386: @606631
     /*  606631 */   GIM_Try, /*On fail goto*//*Label 9387*/ GIMT_Encode4(606688), // Rule ID 21294 //
     /*  606636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  606639 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606646 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606648 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606659 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
     /*  606662 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606686 */     GIR_RootConstrainSelectedInstOperands,
     /*  606687 */     // GIR_Coverage, 21294,
     /*  606687 */     GIR_EraseRootFromParent_Done,
     /*  606688 */   // Label 9387: @606688
     /*  606688 */   GIM_Try, /*On fail goto*//*Label 9388*/ GIMT_Encode4(606745), // Rule ID 21295 //
     /*  606693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  606696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606703 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606705 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606716 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
     /*  606719 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606743 */     GIR_RootConstrainSelectedInstOperands,
     /*  606744 */     // GIR_Coverage, 21295,
     /*  606744 */     GIR_EraseRootFromParent_Done,
     /*  606745 */   // Label 9388: @606745
     /*  606745 */   GIM_Try, /*On fail goto*//*Label 9389*/ GIMT_Encode4(606802), // Rule ID 21296 //
     /*  606750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  606753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606760 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606773 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
     /*  606776 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606800 */     GIR_RootConstrainSelectedInstOperands,
     /*  606801 */     // GIR_Coverage, 21296,
     /*  606801 */     GIR_EraseRootFromParent_Done,
     /*  606802 */   // Label 9389: @606802
     /*  606802 */   GIM_Try, /*On fail goto*//*Label 9390*/ GIMT_Encode4(606859), // Rule ID 21297 //
     /*  606807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  606810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606817 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606830 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
     /*  606833 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606853 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606857 */     GIR_RootConstrainSelectedInstOperands,
     /*  606858 */     // GIR_Coverage, 21297,
     /*  606858 */     GIR_EraseRootFromParent_Done,
     /*  606859 */   // Label 9390: @606859
     /*  606859 */   GIM_Try, /*On fail goto*//*Label 9391*/ GIMT_Encode4(606916), // Rule ID 21313 //
     /*  606864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  606867 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606874 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606887 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
     /*  606890 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606914 */     GIR_RootConstrainSelectedInstOperands,
     /*  606915 */     // GIR_Coverage, 21313,
     /*  606915 */     GIR_EraseRootFromParent_Done,
     /*  606916 */   // Label 9391: @606916
     /*  606916 */   GIM_Try, /*On fail goto*//*Label 9392*/ GIMT_Encode4(606973), // Rule ID 21314 //
     /*  606921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  606924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606931 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  606944 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  606944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
     /*  606947 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  606949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  606954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  606959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  606964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  606967 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  606971 */     GIR_RootConstrainSelectedInstOperands,
     /*  606972 */     // GIR_Coverage, 21314,
     /*  606972 */     GIR_EraseRootFromParent_Done,
     /*  606973 */   // Label 9392: @606973
     /*  606973 */   GIM_Try, /*On fail goto*//*Label 9393*/ GIMT_Encode4(607030), // Rule ID 21315 //
     /*  606978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  606981 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  606988 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  606990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  606994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607001 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
     /*  607004 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607028 */     GIR_RootConstrainSelectedInstOperands,
     /*  607029 */     // GIR_Coverage, 21315,
     /*  607029 */     GIR_EraseRootFromParent_Done,
     /*  607030 */   // Label 9393: @607030
     /*  607030 */   GIM_Try, /*On fail goto*//*Label 9394*/ GIMT_Encode4(607087), // Rule ID 21316 //
     /*  607035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  607038 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607045 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607058 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
     /*  607061 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607085 */     GIR_RootConstrainSelectedInstOperands,
     /*  607086 */     // GIR_Coverage, 21316,
     /*  607086 */     GIR_EraseRootFromParent_Done,
     /*  607087 */   // Label 9394: @607087
     /*  607087 */   GIM_Try, /*On fail goto*//*Label 9395*/ GIMT_Encode4(607144), // Rule ID 21317 //
     /*  607092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  607095 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607102 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607104 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607115 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
     /*  607118 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607142 */     GIR_RootConstrainSelectedInstOperands,
     /*  607143 */     // GIR_Coverage, 21317,
     /*  607143 */     GIR_EraseRootFromParent_Done,
     /*  607144 */   // Label 9395: @607144
     /*  607144 */   GIM_Try, /*On fail goto*//*Label 9396*/ GIMT_Encode4(607205), // Rule ID 21283 //
     /*  607149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  607152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607174 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
     /*  607177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607179 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607203 */     GIR_RootConstrainSelectedInstOperands,
     /*  607204 */     // GIR_Coverage, 21283,
     /*  607204 */     GIR_EraseRootFromParent_Done,
     /*  607205 */   // Label 9396: @607205
     /*  607205 */   GIM_Try, /*On fail goto*//*Label 9397*/ GIMT_Encode4(607266), // Rule ID 21284 //
     /*  607210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  607213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607235 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
     /*  607238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607240 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607264 */     GIR_RootConstrainSelectedInstOperands,
     /*  607265 */     // GIR_Coverage, 21284,
     /*  607265 */     GIR_EraseRootFromParent_Done,
     /*  607266 */   // Label 9397: @607266
     /*  607266 */   GIM_Try, /*On fail goto*//*Label 9398*/ GIMT_Encode4(607327), // Rule ID 21285 //
     /*  607271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  607274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607296 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
     /*  607299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607301 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607325 */     GIR_RootConstrainSelectedInstOperands,
     /*  607326 */     // GIR_Coverage, 21285,
     /*  607326 */     GIR_EraseRootFromParent_Done,
     /*  607327 */   // Label 9398: @607327
     /*  607327 */   GIM_Try, /*On fail goto*//*Label 9399*/ GIMT_Encode4(607388), // Rule ID 21286 //
     /*  607332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  607335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607346 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607350 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607357 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
     /*  607360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607362 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607386 */     GIR_RootConstrainSelectedInstOperands,
     /*  607387 */     // GIR_Coverage, 21286,
     /*  607387 */     GIR_EraseRootFromParent_Done,
     /*  607388 */   // Label 9399: @607388
     /*  607388 */   GIM_Try, /*On fail goto*//*Label 9400*/ GIMT_Encode4(607449), // Rule ID 21287 //
     /*  607393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  607396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607407 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607411 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607418 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
     /*  607421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607423 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607447 */     GIR_RootConstrainSelectedInstOperands,
     /*  607448 */     // GIR_Coverage, 21287,
     /*  607448 */     GIR_EraseRootFromParent_Done,
     /*  607449 */   // Label 9400: @607449
     /*  607449 */   GIM_Try, /*On fail goto*//*Label 9401*/ GIMT_Encode4(607510), // Rule ID 21303 //
     /*  607454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  607457 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607479 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
     /*  607482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607484 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607508 */     GIR_RootConstrainSelectedInstOperands,
     /*  607509 */     // GIR_Coverage, 21303,
     /*  607509 */     GIR_EraseRootFromParent_Done,
     /*  607510 */   // Label 9401: @607510
     /*  607510 */   GIM_Try, /*On fail goto*//*Label 9402*/ GIMT_Encode4(607571), // Rule ID 21304 //
     /*  607515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  607518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607533 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607540 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
     /*  607543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607545 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607569 */     GIR_RootConstrainSelectedInstOperands,
     /*  607570 */     // GIR_Coverage, 21304,
     /*  607570 */     GIR_EraseRootFromParent_Done,
     /*  607571 */   // Label 9402: @607571
     /*  607571 */   GIM_Try, /*On fail goto*//*Label 9403*/ GIMT_Encode4(607632), // Rule ID 21305 //
     /*  607576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  607579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607601 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
     /*  607604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607606 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607630 */     GIR_RootConstrainSelectedInstOperands,
     /*  607631 */     // GIR_Coverage, 21305,
     /*  607631 */     GIR_EraseRootFromParent_Done,
     /*  607632 */   // Label 9403: @607632
     /*  607632 */   GIM_Try, /*On fail goto*//*Label 9404*/ GIMT_Encode4(607693), // Rule ID 21306 //
     /*  607637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  607640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607662 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
     /*  607665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607667 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607691 */     GIR_RootConstrainSelectedInstOperands,
     /*  607692 */     // GIR_Coverage, 21306,
     /*  607692 */     GIR_EraseRootFromParent_Done,
     /*  607693 */   // Label 9404: @607693
     /*  607693 */   GIM_Try, /*On fail goto*//*Label 9405*/ GIMT_Encode4(607754), // Rule ID 21307 //
     /*  607698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  607701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  607708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  607712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  607723 */     // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  607723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
     /*  607726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  607728 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  607730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  607735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  607740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  607745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  607748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607752 */     GIR_RootConstrainSelectedInstOperands,
     /*  607753 */     // GIR_Coverage, 21307,
     /*  607753 */     GIR_EraseRootFromParent_Done,
     /*  607754 */   // Label 9405: @607754
     /*  607754 */   GIM_Try, /*On fail goto*//*Label 9406*/ GIMT_Encode4(607804), // Rule ID 30595 //
     /*  607759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  607762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  607767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  607780 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  607780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  607783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  607788 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  607790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  607795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607802 */     GIR_RootConstrainSelectedInstOperands,
     /*  607803 */     // GIR_Coverage, 30595,
     /*  607803 */     GIR_EraseRootFromParent_Done,
     /*  607804 */   // Label 9406: @607804
     /*  607804 */   GIM_Try, /*On fail goto*//*Label 9407*/ GIMT_Encode4(607854), // Rule ID 30596 //
     /*  607809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  607812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  607817 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  607830 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  607830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  607833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  607838 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  607840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  607845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607848 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607852 */     GIR_RootConstrainSelectedInstOperands,
     /*  607853 */     // GIR_Coverage, 30596,
     /*  607853 */     GIR_EraseRootFromParent_Done,
     /*  607854 */   // Label 9407: @607854
     /*  607854 */   GIM_Try, /*On fail goto*//*Label 9408*/ GIMT_Encode4(607904), // Rule ID 30597 //
     /*  607859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  607862 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  607867 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  607880 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  607880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  607883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  607888 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  607890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  607895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607902 */     GIR_RootConstrainSelectedInstOperands,
     /*  607903 */     // GIR_Coverage, 30597,
     /*  607903 */     GIR_EraseRootFromParent_Done,
     /*  607904 */   // Label 9408: @607904
     /*  607904 */   GIM_Try, /*On fail goto*//*Label 9409*/ GIMT_Encode4(607954), // Rule ID 30598 //
     /*  607909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  607912 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  607917 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  607930 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  607930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  607933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  607938 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  607940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  607945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  607952 */     GIR_RootConstrainSelectedInstOperands,
     /*  607953 */     // GIR_Coverage, 30598,
     /*  607953 */     GIR_EraseRootFromParent_Done,
     /*  607954 */   // Label 9409: @607954
     /*  607954 */   GIM_Try, /*On fail goto*//*Label 9410*/ GIMT_Encode4(608004), // Rule ID 30599 //
     /*  607959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  607962 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  607967 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  607969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  607973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  607980 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  607980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  607983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  607988 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  607990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  607995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  607998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608002 */     GIR_RootConstrainSelectedInstOperands,
     /*  608003 */     // GIR_Coverage, 30599,
     /*  608003 */     GIR_EraseRootFromParent_Done,
     /*  608004 */   // Label 9410: @608004
     /*  608004 */   GIM_Try, /*On fail goto*//*Label 9411*/ GIMT_Encode4(608054), // Rule ID 30605 //
     /*  608009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  608012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608017 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608019 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608023 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608030 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i64>>  =>  (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9),
     /*  608033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608038 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608052 */     GIR_RootConstrainSelectedInstOperands,
     /*  608053 */     // GIR_Coverage, 30605,
     /*  608053 */     GIR_EraseRootFromParent_Done,
     /*  608054 */   // Label 9411: @608054
     /*  608054 */   GIM_Try, /*On fail goto*//*Label 9412*/ GIMT_Encode4(608104), // Rule ID 30606 //
     /*  608059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  608062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608067 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608080 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i64>>  =>  (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9),
     /*  608083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608088 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608102 */     GIR_RootConstrainSelectedInstOperands,
     /*  608103 */     // GIR_Coverage, 30606,
     /*  608103 */     GIR_EraseRootFromParent_Done,
     /*  608104 */   // Label 9412: @608104
     /*  608104 */   GIM_Try, /*On fail goto*//*Label 9413*/ GIMT_Encode4(608154), // Rule ID 30607 //
     /*  608109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  608112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608117 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608119 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608123 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608130 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i64>>  =>  (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9),
     /*  608133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608138 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608148 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608152 */     GIR_RootConstrainSelectedInstOperands,
     /*  608153 */     // GIR_Coverage, 30607,
     /*  608153 */     GIR_EraseRootFromParent_Done,
     /*  608154 */   // Label 9413: @608154
     /*  608154 */   GIM_Try, /*On fail goto*//*Label 9414*/ GIMT_Encode4(608204), // Rule ID 30608 //
     /*  608159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  608162 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608167 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608180 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i64>>  =>  (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9),
     /*  608183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608188 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608202 */     GIR_RootConstrainSelectedInstOperands,
     /*  608203 */     // GIR_Coverage, 30608,
     /*  608203 */     GIR_EraseRootFromParent_Done,
     /*  608204 */   // Label 9414: @608204
     /*  608204 */   GIM_Try, /*On fail goto*//*Label 9415*/ GIMT_Encode4(608254), // Rule ID 30609 //
     /*  608209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  608212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608217 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608223 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608230 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i64>>  =>  (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9),
     /*  608233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608238 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608252 */     GIR_RootConstrainSelectedInstOperands,
     /*  608253 */     // GIR_Coverage, 30609,
     /*  608253 */     GIR_EraseRootFromParent_Done,
     /*  608254 */   // Label 9415: @608254
     /*  608254 */   GIM_Try, /*On fail goto*//*Label 9416*/ GIMT_Encode4(608304), // Rule ID 30615 //
     /*  608259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  608262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  608267 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608280 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  608280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  608283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608288 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  608298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608302 */     GIR_RootConstrainSelectedInstOperands,
     /*  608303 */     // GIR_Coverage, 30615,
     /*  608303 */     GIR_EraseRootFromParent_Done,
     /*  608304 */   // Label 9416: @608304
     /*  608304 */   GIM_Try, /*On fail goto*//*Label 9417*/ GIMT_Encode4(608354), // Rule ID 30616 //
     /*  608309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  608312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  608317 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608330 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  608330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  608333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608338 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  608348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608352 */     GIR_RootConstrainSelectedInstOperands,
     /*  608353 */     // GIR_Coverage, 30616,
     /*  608353 */     GIR_EraseRootFromParent_Done,
     /*  608354 */   // Label 9417: @608354
     /*  608354 */   GIM_Try, /*On fail goto*//*Label 9418*/ GIMT_Encode4(608404), // Rule ID 30617 //
     /*  608359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  608362 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  608367 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608369 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608380 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  608380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  608383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608388 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  608398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608402 */     GIR_RootConstrainSelectedInstOperands,
     /*  608403 */     // GIR_Coverage, 30617,
     /*  608403 */     GIR_EraseRootFromParent_Done,
     /*  608404 */   // Label 9418: @608404
     /*  608404 */   GIM_Try, /*On fail goto*//*Label 9419*/ GIMT_Encode4(608454), // Rule ID 30618 //
     /*  608409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  608412 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  608417 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608430 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  608430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  608433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608438 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  608448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608452 */     GIR_RootConstrainSelectedInstOperands,
     /*  608453 */     // GIR_Coverage, 30618,
     /*  608453 */     GIR_EraseRootFromParent_Done,
     /*  608454 */   // Label 9419: @608454
     /*  608454 */   GIM_Try, /*On fail goto*//*Label 9420*/ GIMT_Encode4(608504), // Rule ID 30619 //
     /*  608459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  608462 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  608467 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  608469 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608480 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  608480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
     /*  608483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608488 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  608498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608502 */     GIR_RootConstrainSelectedInstOperands,
     /*  608503 */     // GIR_Coverage, 30619,
     /*  608503 */     GIR_EraseRootFromParent_Done,
     /*  608504 */   // Label 9420: @608504
     /*  608504 */   GIM_Try, /*On fail goto*//*Label 9421*/ GIMT_Encode4(608558), // Rule ID 30590 //
     /*  608509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  608512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608532 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  608535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608542 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608552 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608556 */     GIR_RootConstrainSelectedInstOperands,
     /*  608557 */     // GIR_Coverage, 30590,
     /*  608557 */     GIR_EraseRootFromParent_Done,
     /*  608558 */   // Label 9421: @608558
     /*  608558 */   GIM_Try, /*On fail goto*//*Label 9422*/ GIMT_Encode4(608612), // Rule ID 30591 //
     /*  608563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  608566 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608575 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608586 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  608589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608596 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608610 */     GIR_RootConstrainSelectedInstOperands,
     /*  608611 */     // GIR_Coverage, 30591,
     /*  608611 */     GIR_EraseRootFromParent_Done,
     /*  608612 */   // Label 9422: @608612
     /*  608612 */   GIM_Try, /*On fail goto*//*Label 9423*/ GIMT_Encode4(608666), // Rule ID 30592 //
     /*  608617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  608620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608640 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  608643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608650 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608664 */     GIR_RootConstrainSelectedInstOperands,
     /*  608665 */     // GIR_Coverage, 30592,
     /*  608665 */     GIR_EraseRootFromParent_Done,
     /*  608666 */   // Label 9423: @608666
     /*  608666 */   GIM_Try, /*On fail goto*//*Label 9424*/ GIMT_Encode4(608720), // Rule ID 30593 //
     /*  608671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  608674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608694 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  608697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608704 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608714 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608718 */     GIR_RootConstrainSelectedInstOperands,
     /*  608719 */     // GIR_Coverage, 30593,
     /*  608719 */     GIR_EraseRootFromParent_Done,
     /*  608720 */   // Label 9424: @608720
     /*  608720 */   GIM_Try, /*On fail goto*//*Label 9425*/ GIMT_Encode4(608774), // Rule ID 30594 //
     /*  608725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  608728 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608748 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  608751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608758 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608772 */     GIR_RootConstrainSelectedInstOperands,
     /*  608773 */     // GIR_Coverage, 30594,
     /*  608773 */     GIR_EraseRootFromParent_Done,
     /*  608774 */   // Label 9425: @608774
     /*  608774 */   GIM_Try, /*On fail goto*//*Label 9426*/ GIMT_Encode4(608828), // Rule ID 30600 //
     /*  608779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  608782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608802 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_i64>>  =>  (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9),
     /*  608805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608812 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608822 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608826 */     GIR_RootConstrainSelectedInstOperands,
     /*  608827 */     // GIR_Coverage, 30600,
     /*  608827 */     GIR_EraseRootFromParent_Done,
     /*  608828 */   // Label 9426: @608828
     /*  608828 */   GIM_Try, /*On fail goto*//*Label 9427*/ GIMT_Encode4(608882), // Rule ID 30601 //
     /*  608833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  608836 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608856 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_i64>>  =>  (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9),
     /*  608859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608866 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608880 */     GIR_RootConstrainSelectedInstOperands,
     /*  608881 */     // GIR_Coverage, 30601,
     /*  608881 */     GIR_EraseRootFromParent_Done,
     /*  608882 */   // Label 9427: @608882
     /*  608882 */   GIM_Try, /*On fail goto*//*Label 9428*/ GIMT_Encode4(608936), // Rule ID 30602 //
     /*  608887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  608890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608910 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_i64>>  =>  (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9),
     /*  608913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608920 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608934 */     GIR_RootConstrainSelectedInstOperands,
     /*  608935 */     // GIR_Coverage, 30602,
     /*  608935 */     GIR_EraseRootFromParent_Done,
     /*  608936 */   // Label 9428: @608936
     /*  608936 */   GIM_Try, /*On fail goto*//*Label 9429*/ GIMT_Encode4(608990), // Rule ID 30603 //
     /*  608941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  608944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  608949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  608953 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  608957 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  608964 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_i64>>  =>  (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  608964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9),
     /*  608967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  608969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  608974 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  608976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  608981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  608984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  608988 */     GIR_RootConstrainSelectedInstOperands,
     /*  608989 */     // GIR_Coverage, 30603,
     /*  608989 */     GIR_EraseRootFromParent_Done,
     /*  608990 */   // Label 9429: @608990
     /*  608990 */   GIM_Try, /*On fail goto*//*Label 9430*/ GIMT_Encode4(609044), // Rule ID 30604 //
     /*  608995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  608998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  609003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  609018 */     // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_i64>>  =>  (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  609018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9),
     /*  609021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  609028 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  609030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  609038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609042 */     GIR_RootConstrainSelectedInstOperands,
     /*  609043 */     // GIR_Coverage, 30604,
     /*  609043 */     GIR_EraseRootFromParent_Done,
     /*  609044 */   // Label 9430: @609044
     /*  609044 */   GIM_Try, /*On fail goto*//*Label 9431*/ GIMT_Encode4(609098), // Rule ID 30610 //
     /*  609049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  609052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  609057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  609072 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  609072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  609075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  609082 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  609084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  609092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609096 */     GIR_RootConstrainSelectedInstOperands,
     /*  609097 */     // GIR_Coverage, 30610,
     /*  609097 */     GIR_EraseRootFromParent_Done,
     /*  609098 */   // Label 9431: @609098
     /*  609098 */   GIM_Try, /*On fail goto*//*Label 9432*/ GIMT_Encode4(609152), // Rule ID 30611 //
     /*  609103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  609106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  609111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  609126 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  609126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  609129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  609136 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  609138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  609146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609150 */     GIR_RootConstrainSelectedInstOperands,
     /*  609151 */     // GIR_Coverage, 30611,
     /*  609151 */     GIR_EraseRootFromParent_Done,
     /*  609152 */   // Label 9432: @609152
     /*  609152 */   GIM_Try, /*On fail goto*//*Label 9433*/ GIMT_Encode4(609206), // Rule ID 30612 //
     /*  609157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  609160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  609165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  609180 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  609180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  609183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  609190 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  609192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  609200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609204 */     GIR_RootConstrainSelectedInstOperands,
     /*  609205 */     // GIR_Coverage, 30612,
     /*  609205 */     GIR_EraseRootFromParent_Done,
     /*  609206 */   // Label 9433: @609206
     /*  609206 */   GIM_Try, /*On fail goto*//*Label 9434*/ GIMT_Encode4(609260), // Rule ID 30613 //
     /*  609211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  609214 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  609219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  609234 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  609234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  609237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  609244 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  609246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  609254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609258 */     GIR_RootConstrainSelectedInstOperands,
     /*  609259 */     // GIR_Coverage, 30613,
     /*  609259 */     GIR_EraseRootFromParent_Done,
     /*  609260 */   // Label 9434: @609260
     /*  609260 */   GIM_Try, /*On fail goto*//*Label 9435*/ GIMT_Encode4(609314), // Rule ID 30614 //
     /*  609265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  609268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  609273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  609288 */     // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  609288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
     /*  609291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  609298 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  609300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  609308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609312 */     GIR_RootConstrainSelectedInstOperands,
     /*  609313 */     // GIR_Coverage, 30614,
     /*  609313 */     GIR_EraseRootFromParent_Done,
     /*  609314 */   // Label 9435: @609314
     /*  609314 */   GIM_Try, /*On fail goto*//*Label 9436*/ GIMT_Encode4(609373), // Rule ID 13125 //
     /*  609319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  609322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609329 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  609342 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR),
     /*  609345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609350 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609367 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609371 */     GIR_RootConstrainSelectedInstOperands,
     /*  609372 */     // GIR_Coverage, 13125,
     /*  609372 */     GIR_EraseRootFromParent_Done,
     /*  609373 */   // Label 9436: @609373
     /*  609373 */   GIM_Try, /*On fail goto*//*Label 9437*/ GIMT_Encode4(609432), // Rule ID 13126 //
     /*  609378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  609381 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609388 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609394 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  609401 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR),
     /*  609404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609409 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609430 */     GIR_RootConstrainSelectedInstOperands,
     /*  609431 */     // GIR_Coverage, 13126,
     /*  609431 */     GIR_EraseRootFromParent_Done,
     /*  609432 */   // Label 9437: @609432
     /*  609432 */   GIM_Try, /*On fail goto*//*Label 9438*/ GIMT_Encode4(609491), // Rule ID 13127 //
     /*  609437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  609440 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609447 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  609460 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR),
     /*  609463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609468 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609485 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609489 */     GIR_RootConstrainSelectedInstOperands,
     /*  609490 */     // GIR_Coverage, 13127,
     /*  609490 */     GIR_EraseRootFromParent_Done,
     /*  609491 */   // Label 9438: @609491
     /*  609491 */   GIM_Try, /*On fail goto*//*Label 9439*/ GIMT_Encode4(609550), // Rule ID 13128 //
     /*  609496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  609499 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609506 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609512 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  609519 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR),
     /*  609522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609527 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609548 */     GIR_RootConstrainSelectedInstOperands,
     /*  609549 */     // GIR_Coverage, 13128,
     /*  609549 */     GIR_EraseRootFromParent_Done,
     /*  609550 */   // Label 9439: @609550
     /*  609550 */   GIM_Try, /*On fail goto*//*Label 9440*/ GIMT_Encode4(609609), // Rule ID 13129 //
     /*  609555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  609558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609565 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  609578 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR),
     /*  609581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609586 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609607 */     GIR_RootConstrainSelectedInstOperands,
     /*  609608 */     // GIR_Coverage, 13129,
     /*  609608 */     GIR_EraseRootFromParent_Done,
     /*  609609 */   // Label 9440: @609609
     /*  609609 */   GIM_Try, /*On fail goto*//*Label 9441*/ GIMT_Encode4(609672), // Rule ID 13135 //
     /*  609614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  609617 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  609639 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN),
     /*  609642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609649 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609670 */     GIR_RootConstrainSelectedInstOperands,
     /*  609671 */     // GIR_Coverage, 13135,
     /*  609671 */     GIR_EraseRootFromParent_Done,
     /*  609672 */   // Label 9441: @609672
     /*  609672 */   GIM_Try, /*On fail goto*//*Label 9442*/ GIMT_Encode4(609735), // Rule ID 13136 //
     /*  609677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  609680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  609702 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN),
     /*  609705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609712 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609733 */     GIR_RootConstrainSelectedInstOperands,
     /*  609734 */     // GIR_Coverage, 13136,
     /*  609734 */     GIR_EraseRootFromParent_Done,
     /*  609735 */   // Label 9442: @609735
     /*  609735 */   GIM_Try, /*On fail goto*//*Label 9443*/ GIMT_Encode4(609798), // Rule ID 13137 //
     /*  609740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  609743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609754 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609758 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  609765 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN),
     /*  609768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609775 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609796 */     GIR_RootConstrainSelectedInstOperands,
     /*  609797 */     // GIR_Coverage, 13137,
     /*  609797 */     GIR_EraseRootFromParent_Done,
     /*  609798 */   // Label 9443: @609798
     /*  609798 */   GIM_Try, /*On fail goto*//*Label 9444*/ GIMT_Encode4(609861), // Rule ID 13138 //
     /*  609803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  609806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  609828 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN),
     /*  609831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609838 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609859 */     GIR_RootConstrainSelectedInstOperands,
     /*  609860 */     // GIR_Coverage, 13138,
     /*  609860 */     GIR_EraseRootFromParent_Done,
     /*  609861 */   // Label 9444: @609861
     /*  609861 */   GIM_Try, /*On fail goto*//*Label 9445*/ GIMT_Encode4(609924), // Rule ID 13139 //
     /*  609866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  609869 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  609880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  609891 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  609891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN),
     /*  609894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  609896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  609901 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  609908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  609913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  609918 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609922 */     GIR_RootConstrainSelectedInstOperands,
     /*  609923 */     // GIR_Coverage, 13139,
     /*  609923 */     GIR_EraseRootFromParent_Done,
     /*  609924 */   // Label 9445: @609924
     /*  609924 */   GIM_Try, /*On fail goto*//*Label 9446*/ GIMT_Encode4(609976), // Rule ID 13120 //
     /*  609929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  609932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609939 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  609952 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  609952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2),
     /*  609955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  609960 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  609962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  609967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  609970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  609974 */     GIR_RootConstrainSelectedInstOperands,
     /*  609975 */     // GIR_Coverage, 13120,
     /*  609975 */     GIR_EraseRootFromParent_Done,
     /*  609976 */   // Label 9446: @609976
     /*  609976 */   GIM_Try, /*On fail goto*//*Label 9447*/ GIMT_Encode4(610028), // Rule ID 13121 //
     /*  609981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  609984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  609991 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  609993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  609997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610004 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2),
     /*  610007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610012 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  610022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610026 */     GIR_RootConstrainSelectedInstOperands,
     /*  610027 */     // GIR_Coverage, 13121,
     /*  610027 */     GIR_EraseRootFromParent_Done,
     /*  610028 */   // Label 9447: @610028
     /*  610028 */   GIM_Try, /*On fail goto*//*Label 9448*/ GIMT_Encode4(610080), // Rule ID 13122 //
     /*  610033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  610036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610043 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610056 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2),
     /*  610059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610064 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  610074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610078 */     GIR_RootConstrainSelectedInstOperands,
     /*  610079 */     // GIR_Coverage, 13122,
     /*  610079 */     GIR_EraseRootFromParent_Done,
     /*  610080 */   // Label 9448: @610080
     /*  610080 */   GIM_Try, /*On fail goto*//*Label 9449*/ GIMT_Encode4(610132), // Rule ID 13123 //
     /*  610085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  610088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610095 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610101 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610108 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2),
     /*  610111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610116 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  610126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610130 */     GIR_RootConstrainSelectedInstOperands,
     /*  610131 */     // GIR_Coverage, 13123,
     /*  610131 */     GIR_EraseRootFromParent_Done,
     /*  610132 */   // Label 9449: @610132
     /*  610132 */   GIM_Try, /*On fail goto*//*Label 9450*/ GIMT_Encode4(610184), // Rule ID 13124 //
     /*  610137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  610140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610147 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610160 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2),
     /*  610163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610168 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  610178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610182 */     GIR_RootConstrainSelectedInstOperands,
     /*  610183 */     // GIR_Coverage, 13124,
     /*  610183 */     GIR_EraseRootFromParent_Done,
     /*  610184 */   // Label 9450: @610184
     /*  610184 */   GIM_Try, /*On fail goto*//*Label 9451*/ GIMT_Encode4(610240), // Rule ID 13130 //
     /*  610189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  610192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  610203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610214 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN),
     /*  610217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  610219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610224 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  610234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610238 */     GIR_RootConstrainSelectedInstOperands,
     /*  610239 */     // GIR_Coverage, 13130,
     /*  610239 */     GIR_EraseRootFromParent_Done,
     /*  610240 */   // Label 9451: @610240
     /*  610240 */   GIM_Try, /*On fail goto*//*Label 9452*/ GIMT_Encode4(610296), // Rule ID 13131 //
     /*  610245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  610248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  610259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610270 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN),
     /*  610273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  610275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610280 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  610290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610294 */     GIR_RootConstrainSelectedInstOperands,
     /*  610295 */     // GIR_Coverage, 13131,
     /*  610295 */     GIR_EraseRootFromParent_Done,
     /*  610296 */   // Label 9452: @610296
     /*  610296 */   GIM_Try, /*On fail goto*//*Label 9453*/ GIMT_Encode4(610352), // Rule ID 13132 //
     /*  610301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  610304 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  610315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610326 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN),
     /*  610329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  610331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610336 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  610346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610350 */     GIR_RootConstrainSelectedInstOperands,
     /*  610351 */     // GIR_Coverage, 13132,
     /*  610351 */     GIR_EraseRootFromParent_Done,
     /*  610352 */   // Label 9453: @610352
     /*  610352 */   GIM_Try, /*On fail goto*//*Label 9454*/ GIMT_Encode4(610408), // Rule ID 13133 //
     /*  610357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  610360 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  610371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610382 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN),
     /*  610385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  610387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610392 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  610402 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610406 */     GIR_RootConstrainSelectedInstOperands,
     /*  610407 */     // GIR_Coverage, 13133,
     /*  610407 */     GIR_EraseRootFromParent_Done,
     /*  610408 */   // Label 9454: @610408
     /*  610408 */   GIM_Try, /*On fail goto*//*Label 9455*/ GIMT_Encode4(610464), // Rule ID 13134 //
     /*  610413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  610416 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  610427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  610438 */     // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  610438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN),
     /*  610441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  610443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  610448 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  610455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  610458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610462 */     GIR_RootConstrainSelectedInstOperands,
     /*  610463 */     // GIR_Coverage, 13134,
     /*  610463 */     GIR_EraseRootFromParent_Done,
     /*  610464 */   // Label 9455: @610464
     /*  610464 */   GIM_Try, /*On fail goto*//*Label 9456*/ GIMT_Encode4(610524), // Rule ID 10717 //
     /*  610469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  610472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610480 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610493 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610501 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610522 */     GIR_RootConstrainSelectedInstOperands,
     /*  610523 */     // GIR_Coverage, 10717,
     /*  610523 */     GIR_EraseRootFromParent_Done,
     /*  610524 */   // Label 9456: @610524
     /*  610524 */   GIM_Try, /*On fail goto*//*Label 9457*/ GIMT_Encode4(610584), // Rule ID 10718 //
     /*  610529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  610532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610540 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610553 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610561 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610582 */     GIR_RootConstrainSelectedInstOperands,
     /*  610583 */     // GIR_Coverage, 10718,
     /*  610583 */     GIR_EraseRootFromParent_Done,
     /*  610584 */   // Label 9457: @610584
     /*  610584 */   GIM_Try, /*On fail goto*//*Label 9458*/ GIMT_Encode4(610644), // Rule ID 10719 //
     /*  610589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  610592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610600 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610613 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610621 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610642 */     GIR_RootConstrainSelectedInstOperands,
     /*  610643 */     // GIR_Coverage, 10719,
     /*  610643 */     GIR_EraseRootFromParent_Done,
     /*  610644 */   // Label 9458: @610644
     /*  610644 */   GIM_Try, /*On fail goto*//*Label 9459*/ GIMT_Encode4(610704), // Rule ID 10720 //
     /*  610649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  610652 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610660 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610673 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610681 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610702 */     GIR_RootConstrainSelectedInstOperands,
     /*  610703 */     // GIR_Coverage, 10720,
     /*  610703 */     GIR_EraseRootFromParent_Done,
     /*  610704 */   // Label 9459: @610704
     /*  610704 */   GIM_Try, /*On fail goto*//*Label 9460*/ GIMT_Encode4(610764), // Rule ID 10721 //
     /*  610709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  610712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610720 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610733 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610741 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610762 */     GIR_RootConstrainSelectedInstOperands,
     /*  610763 */     // GIR_Coverage, 10721,
     /*  610763 */     GIR_EraseRootFromParent_Done,
     /*  610764 */   // Label 9460: @610764
     /*  610764 */   GIM_Try, /*On fail goto*//*Label 9461*/ GIMT_Encode4(610823), // Rule ID 11273 //
     /*  610769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  610772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610779 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610792 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610800 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610821 */     GIR_RootConstrainSelectedInstOperands,
     /*  610822 */     // GIR_Coverage, 11273,
     /*  610822 */     GIR_EraseRootFromParent_Done,
     /*  610823 */   // Label 9461: @610823
     /*  610823 */   GIM_Try, /*On fail goto*//*Label 9462*/ GIMT_Encode4(610882), // Rule ID 11274 //
     /*  610828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  610831 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610838 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610851 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610859 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610880 */     GIR_RootConstrainSelectedInstOperands,
     /*  610881 */     // GIR_Coverage, 11274,
     /*  610881 */     GIR_EraseRootFromParent_Done,
     /*  610882 */   // Label 9462: @610882
     /*  610882 */   GIM_Try, /*On fail goto*//*Label 9463*/ GIMT_Encode4(610941), // Rule ID 11275 //
     /*  610887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  610890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610897 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610910 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610918 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610935 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610939 */     GIR_RootConstrainSelectedInstOperands,
     /*  610940 */     // GIR_Coverage, 11275,
     /*  610940 */     GIR_EraseRootFromParent_Done,
     /*  610941 */   // Label 9463: @610941
     /*  610941 */   GIM_Try, /*On fail goto*//*Label 9464*/ GIMT_Encode4(611000), // Rule ID 11276 //
     /*  610946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  610949 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  610956 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  610958 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  610962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  610969 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  610969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  610972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  610977 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  610979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  610984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  610989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  610994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  610998 */     GIR_RootConstrainSelectedInstOperands,
     /*  610999 */     // GIR_Coverage, 11276,
     /*  610999 */     GIR_EraseRootFromParent_Done,
     /*  611000 */   // Label 9464: @611000
     /*  611000 */   GIM_Try, /*On fail goto*//*Label 9465*/ GIMT_Encode4(611059), // Rule ID 11277 //
     /*  611005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  611008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611015 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611017 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  611028 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR),
     /*  611031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611036 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611057 */     GIR_RootConstrainSelectedInstOperands,
     /*  611058 */     // GIR_Coverage, 11277,
     /*  611058 */     GIR_EraseRootFromParent_Done,
     /*  611059 */   // Label 9465: @611059
     /*  611059 */   GIM_Try, /*On fail goto*//*Label 9466*/ GIMT_Encode4(611123), // Rule ID 10707 //
     /*  611064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  611067 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611090 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611100 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611121 */     GIR_RootConstrainSelectedInstOperands,
     /*  611122 */     // GIR_Coverage, 10707,
     /*  611122 */     GIR_EraseRootFromParent_Done,
     /*  611123 */   // Label 9466: @611123
     /*  611123 */   GIM_Try, /*On fail goto*//*Label 9467*/ GIMT_Encode4(611187), // Rule ID 10708 //
     /*  611128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  611131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611154 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611164 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611185 */     GIR_RootConstrainSelectedInstOperands,
     /*  611186 */     // GIR_Coverage, 10708,
     /*  611186 */     GIR_EraseRootFromParent_Done,
     /*  611187 */   // Label 9467: @611187
     /*  611187 */   GIM_Try, /*On fail goto*//*Label 9468*/ GIMT_Encode4(611251), // Rule ID 10709 //
     /*  611192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  611195 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611218 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611228 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611245 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611249 */     GIR_RootConstrainSelectedInstOperands,
     /*  611250 */     // GIR_Coverage, 10709,
     /*  611250 */     GIR_EraseRootFromParent_Done,
     /*  611251 */   // Label 9468: @611251
     /*  611251 */   GIM_Try, /*On fail goto*//*Label 9469*/ GIMT_Encode4(611315), // Rule ID 10710 //
     /*  611256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  611259 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611282 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611292 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611313 */     GIR_RootConstrainSelectedInstOperands,
     /*  611314 */     // GIR_Coverage, 10710,
     /*  611314 */     GIR_EraseRootFromParent_Done,
     /*  611315 */   // Label 9469: @611315
     /*  611315 */   GIM_Try, /*On fail goto*//*Label 9470*/ GIMT_Encode4(611379), // Rule ID 10711 //
     /*  611320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  611323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611346 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611356 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611377 */     GIR_RootConstrainSelectedInstOperands,
     /*  611378 */     // GIR_Coverage, 10711,
     /*  611378 */     GIR_EraseRootFromParent_Done,
     /*  611379 */   // Label 9470: @611379
     /*  611379 */   GIM_Try, /*On fail goto*//*Label 9471*/ GIMT_Encode4(611442), // Rule ID 11263 //
     /*  611384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  611387 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611398 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611409 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611419 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611440 */     GIR_RootConstrainSelectedInstOperands,
     /*  611441 */     // GIR_Coverage, 11263,
     /*  611441 */     GIR_EraseRootFromParent_Done,
     /*  611442 */   // Label 9471: @611442
     /*  611442 */   GIM_Try, /*On fail goto*//*Label 9472*/ GIMT_Encode4(611505), // Rule ID 11264 //
     /*  611447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  611450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611472 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611482 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611503 */     GIR_RootConstrainSelectedInstOperands,
     /*  611504 */     // GIR_Coverage, 11264,
     /*  611504 */     GIR_EraseRootFromParent_Done,
     /*  611505 */   // Label 9472: @611505
     /*  611505 */   GIM_Try, /*On fail goto*//*Label 9473*/ GIMT_Encode4(611568), // Rule ID 11265 //
     /*  611510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  611513 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611535 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611545 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611566 */     GIR_RootConstrainSelectedInstOperands,
     /*  611567 */     // GIR_Coverage, 11265,
     /*  611567 */     GIR_EraseRootFromParent_Done,
     /*  611568 */   // Label 9473: @611568
     /*  611568 */   GIM_Try, /*On fail goto*//*Label 9474*/ GIMT_Encode4(611631), // Rule ID 11266 //
     /*  611573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  611576 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611598 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611608 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611629 */     GIR_RootConstrainSelectedInstOperands,
     /*  611630 */     // GIR_Coverage, 11266,
     /*  611630 */     GIR_EraseRootFromParent_Done,
     /*  611631 */   // Label 9474: @611631
     /*  611631 */   GIM_Try, /*On fail goto*//*Label 9475*/ GIMT_Encode4(611694), // Rule ID 11267 //
     /*  611636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  611639 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  611650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  611661 */     // (atomic_load_sub:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  611661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_SADDR_RTN),
     /*  611664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  611666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  611671 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  611678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  611683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  611688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611692 */     GIR_RootConstrainSelectedInstOperands,
     /*  611693 */     // GIR_Coverage, 11267,
     /*  611693 */     GIR_EraseRootFromParent_Done,
     /*  611694 */   // Label 9475: @611694
     /*  611694 */   GIM_Try, /*On fail goto*//*Label 9476*/ GIMT_Encode4(611747), // Rule ID 10712 //
     /*  611699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  611702 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611710 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  611723 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  611723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  611726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  611731 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  611738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  611741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611745 */     GIR_RootConstrainSelectedInstOperands,
     /*  611746 */     // GIR_Coverage, 10712,
     /*  611746 */     GIR_EraseRootFromParent_Done,
     /*  611747 */   // Label 9476: @611747
     /*  611747 */   GIM_Try, /*On fail goto*//*Label 9477*/ GIMT_Encode4(611800), // Rule ID 10713 //
     /*  611752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  611755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611763 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  611776 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  611776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  611779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  611784 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  611791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  611794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611798 */     GIR_RootConstrainSelectedInstOperands,
     /*  611799 */     // GIR_Coverage, 10713,
     /*  611799 */     GIR_EraseRootFromParent_Done,
     /*  611800 */   // Label 9477: @611800
     /*  611800 */   GIM_Try, /*On fail goto*//*Label 9478*/ GIMT_Encode4(611853), // Rule ID 10714 //
     /*  611805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  611808 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611816 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  611829 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  611829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  611832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  611837 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  611844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  611847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611851 */     GIR_RootConstrainSelectedInstOperands,
     /*  611852 */     // GIR_Coverage, 10714,
     /*  611852 */     GIR_EraseRootFromParent_Done,
     /*  611853 */   // Label 9478: @611853
     /*  611853 */   GIM_Try, /*On fail goto*//*Label 9479*/ GIMT_Encode4(611906), // Rule ID 10715 //
     /*  611858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  611861 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611869 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  611882 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  611882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  611885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  611890 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  611897 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  611900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611904 */     GIR_RootConstrainSelectedInstOperands,
     /*  611905 */     // GIR_Coverage, 10715,
     /*  611905 */     GIR_EraseRootFromParent_Done,
     /*  611906 */   // Label 9479: @611906
     /*  611906 */   GIM_Try, /*On fail goto*//*Label 9480*/ GIMT_Encode4(611959), // Rule ID 10716 //
     /*  611911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  611914 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611922 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  611935 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  611935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  611938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  611943 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  611950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  611953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  611957 */     GIR_RootConstrainSelectedInstOperands,
     /*  611958 */     // GIR_Coverage, 10716,
     /*  611958 */     GIR_EraseRootFromParent_Done,
     /*  611959 */   // Label 9480: @611959
     /*  611959 */   GIM_Try, /*On fail goto*//*Label 9481*/ GIMT_Encode4(612011), // Rule ID 11268 //
     /*  611964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  611967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  611974 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  611976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  611980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  611987 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  611987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  611990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  611995 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  611997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612009 */     GIR_RootConstrainSelectedInstOperands,
     /*  612010 */     // GIR_Coverage, 11268,
     /*  612010 */     GIR_EraseRootFromParent_Done,
     /*  612011 */   // Label 9481: @612011
     /*  612011 */   GIM_Try, /*On fail goto*//*Label 9482*/ GIMT_Encode4(612063), // Rule ID 11269 //
     /*  612016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  612019 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612026 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612028 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612032 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612039 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  612042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612047 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612061 */     GIR_RootConstrainSelectedInstOperands,
     /*  612062 */     // GIR_Coverage, 11269,
     /*  612062 */     GIR_EraseRootFromParent_Done,
     /*  612063 */   // Label 9482: @612063
     /*  612063 */   GIM_Try, /*On fail goto*//*Label 9483*/ GIMT_Encode4(612115), // Rule ID 11270 //
     /*  612068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  612071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612078 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612091 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  612094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612099 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612113 */     GIR_RootConstrainSelectedInstOperands,
     /*  612114 */     // GIR_Coverage, 11270,
     /*  612114 */     GIR_EraseRootFromParent_Done,
     /*  612115 */   // Label 9483: @612115
     /*  612115 */   GIM_Try, /*On fail goto*//*Label 9484*/ GIMT_Encode4(612167), // Rule ID 11271 //
     /*  612120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  612123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612130 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612143 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  612146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612151 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612165 */     GIR_RootConstrainSelectedInstOperands,
     /*  612166 */     // GIR_Coverage, 11271,
     /*  612166 */     GIR_EraseRootFromParent_Done,
     /*  612167 */   // Label 9484: @612167
     /*  612167 */   GIM_Try, /*On fail goto*//*Label 9485*/ GIMT_Encode4(612219), // Rule ID 11272 //
     /*  612172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  612175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612182 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612195 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
     /*  612198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612203 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612213 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612217 */     GIR_RootConstrainSelectedInstOperands,
     /*  612218 */     // GIR_Coverage, 11272,
     /*  612218 */     GIR_EraseRootFromParent_Done,
     /*  612219 */   // Label 9485: @612219
     /*  612219 */   GIM_Try, /*On fail goto*//*Label 9486*/ GIMT_Encode4(612276), // Rule ID 10702 //
     /*  612224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  612227 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612239 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612250 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612260 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612274 */     GIR_RootConstrainSelectedInstOperands,
     /*  612275 */     // GIR_Coverage, 10702,
     /*  612275 */     GIR_EraseRootFromParent_Done,
     /*  612276 */   // Label 9486: @612276
     /*  612276 */   GIM_Try, /*On fail goto*//*Label 9487*/ GIMT_Encode4(612333), // Rule ID 10703 //
     /*  612281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  612284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612307 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612317 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612324 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612327 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612331 */     GIR_RootConstrainSelectedInstOperands,
     /*  612332 */     // GIR_Coverage, 10703,
     /*  612332 */     GIR_EraseRootFromParent_Done,
     /*  612333 */   // Label 9487: @612333
     /*  612333 */   GIM_Try, /*On fail goto*//*Label 9488*/ GIMT_Encode4(612390), // Rule ID 10704 //
     /*  612338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  612341 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612353 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612364 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612374 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612384 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612388 */     GIR_RootConstrainSelectedInstOperands,
     /*  612389 */     // GIR_Coverage, 10704,
     /*  612389 */     GIR_EraseRootFromParent_Done,
     /*  612390 */   // Label 9488: @612390
     /*  612390 */   GIM_Try, /*On fail goto*//*Label 9489*/ GIMT_Encode4(612447), // Rule ID 10705 //
     /*  612395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  612398 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612421 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612431 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612445 */     GIR_RootConstrainSelectedInstOperands,
     /*  612446 */     // GIR_Coverage, 10705,
     /*  612446 */     GIR_EraseRootFromParent_Done,
     /*  612447 */   // Label 9489: @612447
     /*  612447 */   GIM_Try, /*On fail goto*//*Label 9490*/ GIMT_Encode4(612504), // Rule ID 10706 //
     /*  612452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  612455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612478 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612488 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612502 */     GIR_RootConstrainSelectedInstOperands,
     /*  612503 */     // GIR_Coverage, 10706,
     /*  612503 */     GIR_EraseRootFromParent_Done,
     /*  612504 */   // Label 9490: @612504
     /*  612504 */   GIM_Try, /*On fail goto*//*Label 9491*/ GIMT_Encode4(612560), // Rule ID 11258 //
     /*  612509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  612512 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612534 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612544 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612558 */     GIR_RootConstrainSelectedInstOperands,
     /*  612559 */     // GIR_Coverage, 11258,
     /*  612559 */     GIR_EraseRootFromParent_Done,
     /*  612560 */   // Label 9491: @612560
     /*  612560 */   GIM_Try, /*On fail goto*//*Label 9492*/ GIMT_Encode4(612616), // Rule ID 11259 //
     /*  612565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  612568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612590 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612600 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612614 */     GIR_RootConstrainSelectedInstOperands,
     /*  612615 */     // GIR_Coverage, 11259,
     /*  612615 */     GIR_EraseRootFromParent_Done,
     /*  612616 */   // Label 9492: @612616
     /*  612616 */   GIM_Try, /*On fail goto*//*Label 9493*/ GIMT_Encode4(612672), // Rule ID 11260 //
     /*  612621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  612624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612646 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612656 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612670 */     GIR_RootConstrainSelectedInstOperands,
     /*  612671 */     // GIR_Coverage, 11260,
     /*  612671 */     GIR_EraseRootFromParent_Done,
     /*  612672 */   // Label 9493: @612672
     /*  612672 */   GIM_Try, /*On fail goto*//*Label 9494*/ GIMT_Encode4(612728), // Rule ID 11261 //
     /*  612677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  612680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612702 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612712 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612726 */     GIR_RootConstrainSelectedInstOperands,
     /*  612727 */     // GIR_Coverage, 11261,
     /*  612727 */     GIR_EraseRootFromParent_Done,
     /*  612728 */   // Label 9494: @612728
     /*  612728 */   GIM_Try, /*On fail goto*//*Label 9495*/ GIMT_Encode4(612784), // Rule ID 11262 //
     /*  612733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  612736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  612747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  612758 */     // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  612758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
     /*  612761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  612763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  612768 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  612770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  612775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  612778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612782 */     GIR_RootConstrainSelectedInstOperands,
     /*  612783 */     // GIR_Coverage, 11262,
     /*  612783 */     GIR_EraseRootFromParent_Done,
     /*  612784 */   // Label 9495: @612784
     /*  612784 */   GIM_Reject,
     /*  612785 */ // Label 9365: @612785
     /*  612785 */ GIM_Reject,
     /*  612786 */ // Label 9257: @612786
     /*  612786 */ GIM_Reject,
     /*  612787 */ // Label 22: @612787
     /*  612787 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 9498*/ GIMT_Encode4(626398),
     /*  612798 */ /*GILLT_s32*//*Label 9496*/ GIMT_Encode4(612806),
     /*  612802 */ /*GILLT_s64*//*Label 9497*/ GIMT_Encode4(618898),
     /*  612806 */ // Label 9496: @612806
     /*  612806 */ GIM_Try, /*On fail goto*//*Label 9499*/ GIMT_Encode4(618897),
     /*  612811 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  612814 */   GIM_Try, /*On fail goto*//*Label 9500*/ GIMT_Encode4(612876), // Rule ID 21018 //
     /*  612819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  612822 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612829 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612831 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612835 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  612842 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  612842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64),
     /*  612845 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  612847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  612852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  612857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  612862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  612867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612874 */     GIR_RootConstrainSelectedInstOperands,
     /*  612875 */     // GIR_Coverage, 21018,
     /*  612875 */     GIR_EraseRootFromParent_Done,
     /*  612876 */   // Label 9500: @612876
     /*  612876 */   GIM_Try, /*On fail goto*//*Label 9501*/ GIMT_Encode4(612938), // Rule ID 21019 //
     /*  612881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  612884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612891 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612893 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612897 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  612904 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  612904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64),
     /*  612907 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  612909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  612914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  612919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  612924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  612929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612936 */     GIR_RootConstrainSelectedInstOperands,
     /*  612937 */     // GIR_Coverage, 21019,
     /*  612937 */     GIR_EraseRootFromParent_Done,
     /*  612938 */   // Label 9501: @612938
     /*  612938 */   GIM_Try, /*On fail goto*//*Label 9502*/ GIMT_Encode4(613000), // Rule ID 21020 //
     /*  612943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  612946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  612953 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  612955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  612959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  612966 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  612966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64),
     /*  612969 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  612971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  612976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  612981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  612986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  612991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  612994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  612998 */     GIR_RootConstrainSelectedInstOperands,
     /*  612999 */     // GIR_Coverage, 21020,
     /*  612999 */     GIR_EraseRootFromParent_Done,
     /*  613000 */   // Label 9502: @613000
     /*  613000 */   GIM_Try, /*On fail goto*//*Label 9503*/ GIMT_Encode4(613062), // Rule ID 21021 //
     /*  613005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  613008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613015 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613017 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613028 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64),
     /*  613031 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613060 */     GIR_RootConstrainSelectedInstOperands,
     /*  613061 */     // GIR_Coverage, 21021,
     /*  613061 */     GIR_EraseRootFromParent_Done,
     /*  613062 */   // Label 9503: @613062
     /*  613062 */   GIM_Try, /*On fail goto*//*Label 9504*/ GIMT_Encode4(613124), // Rule ID 21022 //
     /*  613067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  613070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613077 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613090 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64),
     /*  613093 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613122 */     GIR_RootConstrainSelectedInstOperands,
     /*  613123 */     // GIR_Coverage, 21022,
     /*  613123 */     GIR_EraseRootFromParent_Done,
     /*  613124 */   // Label 9504: @613124
     /*  613124 */   GIM_Try, /*On fail goto*//*Label 9505*/ GIMT_Encode4(613186), // Rule ID 21038 //
     /*  613129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  613132 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613139 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613152 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64),
     /*  613155 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613184 */     GIR_RootConstrainSelectedInstOperands,
     /*  613185 */     // GIR_Coverage, 21038,
     /*  613185 */     GIR_EraseRootFromParent_Done,
     /*  613186 */   // Label 9505: @613186
     /*  613186 */   GIM_Try, /*On fail goto*//*Label 9506*/ GIMT_Encode4(613248), // Rule ID 21039 //
     /*  613191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  613194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613201 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613214 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64),
     /*  613217 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613246 */     GIR_RootConstrainSelectedInstOperands,
     /*  613247 */     // GIR_Coverage, 21039,
     /*  613247 */     GIR_EraseRootFromParent_Done,
     /*  613248 */   // Label 9506: @613248
     /*  613248 */   GIM_Try, /*On fail goto*//*Label 9507*/ GIMT_Encode4(613310), // Rule ID 21040 //
     /*  613253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  613256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613263 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613276 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64),
     /*  613279 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613308 */     GIR_RootConstrainSelectedInstOperands,
     /*  613309 */     // GIR_Coverage, 21040,
     /*  613309 */     GIR_EraseRootFromParent_Done,
     /*  613310 */   // Label 9507: @613310
     /*  613310 */   GIM_Try, /*On fail goto*//*Label 9508*/ GIMT_Encode4(613372), // Rule ID 21041 //
     /*  613315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  613318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613325 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613338 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64),
     /*  613341 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613370 */     GIR_RootConstrainSelectedInstOperands,
     /*  613371 */     // GIR_Coverage, 21041,
     /*  613371 */     GIR_EraseRootFromParent_Done,
     /*  613372 */   // Label 9508: @613372
     /*  613372 */   GIM_Try, /*On fail goto*//*Label 9509*/ GIMT_Encode4(613434), // Rule ID 21042 //
     /*  613377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  613380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  613389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613400 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64),
     /*  613403 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  613428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613432 */     GIR_RootConstrainSelectedInstOperands,
     /*  613433 */     // GIR_Coverage, 21042,
     /*  613433 */     GIR_EraseRootFromParent_Done,
     /*  613434 */   // Label 9509: @613434
     /*  613434 */   GIM_Try, /*On fail goto*//*Label 9510*/ GIMT_Encode4(613500), // Rule ID 21008 //
     /*  613439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  613442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613464 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN),
     /*  613467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613469 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613498 */     GIR_RootConstrainSelectedInstOperands,
     /*  613499 */     // GIR_Coverage, 21008,
     /*  613499 */     GIR_EraseRootFromParent_Done,
     /*  613500 */   // Label 9510: @613500
     /*  613500 */   GIM_Try, /*On fail goto*//*Label 9511*/ GIMT_Encode4(613566), // Rule ID 21009 //
     /*  613505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  613508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613530 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN),
     /*  613533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613535 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613560 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613564 */     GIR_RootConstrainSelectedInstOperands,
     /*  613565 */     // GIR_Coverage, 21009,
     /*  613565 */     GIR_EraseRootFromParent_Done,
     /*  613566 */   // Label 9511: @613566
     /*  613566 */   GIM_Try, /*On fail goto*//*Label 9512*/ GIMT_Encode4(613632), // Rule ID 21010 //
     /*  613571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  613574 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613589 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613596 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN),
     /*  613599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613601 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613630 */     GIR_RootConstrainSelectedInstOperands,
     /*  613631 */     // GIR_Coverage, 21010,
     /*  613631 */     GIR_EraseRootFromParent_Done,
     /*  613632 */   // Label 9512: @613632
     /*  613632 */   GIM_Try, /*On fail goto*//*Label 9513*/ GIMT_Encode4(613698), // Rule ID 21011 //
     /*  613637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  613640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613662 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN),
     /*  613665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613667 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613696 */     GIR_RootConstrainSelectedInstOperands,
     /*  613697 */     // GIR_Coverage, 21011,
     /*  613697 */     GIR_EraseRootFromParent_Done,
     /*  613698 */   // Label 9513: @613698
     /*  613698 */   GIM_Try, /*On fail goto*//*Label 9514*/ GIMT_Encode4(613764), // Rule ID 21012 //
     /*  613703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  613706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613728 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN),
     /*  613731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613733 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613762 */     GIR_RootConstrainSelectedInstOperands,
     /*  613763 */     // GIR_Coverage, 21012,
     /*  613763 */     GIR_EraseRootFromParent_Done,
     /*  613764 */   // Label 9514: @613764
     /*  613764 */   GIM_Try, /*On fail goto*//*Label 9515*/ GIMT_Encode4(613830), // Rule ID 21028 //
     /*  613769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  613772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613794 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN),
     /*  613797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613799 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613828 */     GIR_RootConstrainSelectedInstOperands,
     /*  613829 */     // GIR_Coverage, 21028,
     /*  613829 */     GIR_EraseRootFromParent_Done,
     /*  613830 */   // Label 9515: @613830
     /*  613830 */   GIM_Try, /*On fail goto*//*Label 9516*/ GIMT_Encode4(613896), // Rule ID 21029 //
     /*  613835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  613838 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613860 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN),
     /*  613863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613865 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613894 */     GIR_RootConstrainSelectedInstOperands,
     /*  613895 */     // GIR_Coverage, 21029,
     /*  613895 */     GIR_EraseRootFromParent_Done,
     /*  613896 */   // Label 9516: @613896
     /*  613896 */   GIM_Try, /*On fail goto*//*Label 9517*/ GIMT_Encode4(613962), // Rule ID 21030 //
     /*  613901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  613904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613926 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN),
     /*  613929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613931 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  613938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  613943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  613948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  613953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  613956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  613960 */     GIR_RootConstrainSelectedInstOperands,
     /*  613961 */     // GIR_Coverage, 21030,
     /*  613961 */     GIR_EraseRootFromParent_Done,
     /*  613962 */   // Label 9517: @613962
     /*  613962 */   GIM_Try, /*On fail goto*//*Label 9518*/ GIMT_Encode4(614028), // Rule ID 21031 //
     /*  613967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  613970 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  613977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  613981 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  613985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  613992 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  613992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN),
     /*  613995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  613997 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  613999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  614004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  614014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  614019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614026 */     GIR_RootConstrainSelectedInstOperands,
     /*  614027 */     // GIR_Coverage, 21031,
     /*  614027 */     GIR_EraseRootFromParent_Done,
     /*  614028 */   // Label 9518: @614028
     /*  614028 */   GIM_Try, /*On fail goto*//*Label 9519*/ GIMT_Encode4(614094), // Rule ID 21032 //
     /*  614033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  614036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  614058 */     // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN),
     /*  614061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  614063 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  614070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  614080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  614085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614088 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614092 */     GIR_RootConstrainSelectedInstOperands,
     /*  614093 */     // GIR_Coverage, 21032,
     /*  614093 */     GIR_EraseRootFromParent_Done,
     /*  614094 */   // Label 9519: @614094
     /*  614094 */   GIM_Try, /*On fail goto*//*Label 9520*/ GIMT_Encode4(614151), // Rule ID 21013 //
     /*  614099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  614102 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614109 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614122 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
     /*  614125 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614149 */     GIR_RootConstrainSelectedInstOperands,
     /*  614150 */     // GIR_Coverage, 21013,
     /*  614150 */     GIR_EraseRootFromParent_Done,
     /*  614151 */   // Label 9520: @614151
     /*  614151 */   GIM_Try, /*On fail goto*//*Label 9521*/ GIMT_Encode4(614208), // Rule ID 21014 //
     /*  614156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  614159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614166 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614179 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
     /*  614182 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614206 */     GIR_RootConstrainSelectedInstOperands,
     /*  614207 */     // GIR_Coverage, 21014,
     /*  614207 */     GIR_EraseRootFromParent_Done,
     /*  614208 */   // Label 9521: @614208
     /*  614208 */   GIM_Try, /*On fail goto*//*Label 9522*/ GIMT_Encode4(614265), // Rule ID 21015 //
     /*  614213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  614216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614236 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
     /*  614239 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614263 */     GIR_RootConstrainSelectedInstOperands,
     /*  614264 */     // GIR_Coverage, 21015,
     /*  614264 */     GIR_EraseRootFromParent_Done,
     /*  614265 */   // Label 9522: @614265
     /*  614265 */   GIM_Try, /*On fail goto*//*Label 9523*/ GIMT_Encode4(614322), // Rule ID 21016 //
     /*  614270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  614273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614280 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614293 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
     /*  614296 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614320 */     GIR_RootConstrainSelectedInstOperands,
     /*  614321 */     // GIR_Coverage, 21016,
     /*  614321 */     GIR_EraseRootFromParent_Done,
     /*  614322 */   // Label 9523: @614322
     /*  614322 */   GIM_Try, /*On fail goto*//*Label 9524*/ GIMT_Encode4(614379), // Rule ID 21017 //
     /*  614327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  614330 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614337 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614339 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614350 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
     /*  614353 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614377 */     GIR_RootConstrainSelectedInstOperands,
     /*  614378 */     // GIR_Coverage, 21017,
     /*  614378 */     GIR_EraseRootFromParent_Done,
     /*  614379 */   // Label 9524: @614379
     /*  614379 */   GIM_Try, /*On fail goto*//*Label 9525*/ GIMT_Encode4(614436), // Rule ID 21033 //
     /*  614384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  614387 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614394 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614407 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
     /*  614410 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614434 */     GIR_RootConstrainSelectedInstOperands,
     /*  614435 */     // GIR_Coverage, 21033,
     /*  614435 */     GIR_EraseRootFromParent_Done,
     /*  614436 */   // Label 9525: @614436
     /*  614436 */   GIM_Try, /*On fail goto*//*Label 9526*/ GIMT_Encode4(614493), // Rule ID 21034 //
     /*  614441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  614444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614451 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614464 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
     /*  614467 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614484 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614487 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614491 */     GIR_RootConstrainSelectedInstOperands,
     /*  614492 */     // GIR_Coverage, 21034,
     /*  614492 */     GIR_EraseRootFromParent_Done,
     /*  614493 */   // Label 9526: @614493
     /*  614493 */   GIM_Try, /*On fail goto*//*Label 9527*/ GIMT_Encode4(614550), // Rule ID 21035 //
     /*  614498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  614501 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614508 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614510 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614521 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
     /*  614524 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614548 */     GIR_RootConstrainSelectedInstOperands,
     /*  614549 */     // GIR_Coverage, 21035,
     /*  614549 */     GIR_EraseRootFromParent_Done,
     /*  614550 */   // Label 9527: @614550
     /*  614550 */   GIM_Try, /*On fail goto*//*Label 9528*/ GIMT_Encode4(614607), // Rule ID 21036 //
     /*  614555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  614558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614565 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614578 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
     /*  614581 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614605 */     GIR_RootConstrainSelectedInstOperands,
     /*  614606 */     // GIR_Coverage, 21036,
     /*  614606 */     GIR_EraseRootFromParent_Done,
     /*  614607 */   // Label 9528: @614607
     /*  614607 */   GIM_Try, /*On fail goto*//*Label 9529*/ GIMT_Encode4(614664), // Rule ID 21037 //
     /*  614612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  614615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614622 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  614624 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614635 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
     /*  614638 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  614658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614662 */     GIR_RootConstrainSelectedInstOperands,
     /*  614663 */     // GIR_Coverage, 21037,
     /*  614663 */     GIR_EraseRootFromParent_Done,
     /*  614664 */   // Label 9529: @614664
     /*  614664 */   GIM_Try, /*On fail goto*//*Label 9530*/ GIMT_Encode4(614725), // Rule ID 21003 //
     /*  614669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  614672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614694 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
     /*  614697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  614699 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614723 */     GIR_RootConstrainSelectedInstOperands,
     /*  614724 */     // GIR_Coverage, 21003,
     /*  614724 */     GIR_EraseRootFromParent_Done,
     /*  614725 */   // Label 9530: @614725
     /*  614725 */   GIM_Try, /*On fail goto*//*Label 9531*/ GIMT_Encode4(614786), // Rule ID 21004 //
     /*  614730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  614733 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614755 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
     /*  614758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  614760 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614784 */     GIR_RootConstrainSelectedInstOperands,
     /*  614785 */     // GIR_Coverage, 21004,
     /*  614785 */     GIR_EraseRootFromParent_Done,
     /*  614786 */   // Label 9531: @614786
     /*  614786 */   GIM_Try, /*On fail goto*//*Label 9532*/ GIMT_Encode4(614847), // Rule ID 21005 //
     /*  614791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  614794 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614816 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
     /*  614819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  614821 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614845 */     GIR_RootConstrainSelectedInstOperands,
     /*  614846 */     // GIR_Coverage, 21005,
     /*  614846 */     GIR_EraseRootFromParent_Done,
     /*  614847 */   // Label 9532: @614847
     /*  614847 */   GIM_Try, /*On fail goto*//*Label 9533*/ GIMT_Encode4(614908), // Rule ID 21006 //
     /*  614852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  614855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614877 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
     /*  614880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  614882 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614906 */     GIR_RootConstrainSelectedInstOperands,
     /*  614907 */     // GIR_Coverage, 21006,
     /*  614907 */     GIR_EraseRootFromParent_Done,
     /*  614908 */   // Label 9533: @614908
     /*  614908 */   GIM_Try, /*On fail goto*//*Label 9534*/ GIMT_Encode4(614969), // Rule ID 21007 //
     /*  614913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  614916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614938 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
     /*  614941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  614943 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  614945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  614950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  614955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  614960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  614963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  614967 */     GIR_RootConstrainSelectedInstOperands,
     /*  614968 */     // GIR_Coverage, 21007,
     /*  614968 */     GIR_EraseRootFromParent_Done,
     /*  614969 */   // Label 9534: @614969
     /*  614969 */   GIM_Try, /*On fail goto*//*Label 9535*/ GIMT_Encode4(615030), // Rule ID 21023 //
     /*  614974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  614977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  614984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  614988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  614992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  614999 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  614999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
     /*  615002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  615004 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  615006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  615011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  615016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  615021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615028 */     GIR_RootConstrainSelectedInstOperands,
     /*  615029 */     // GIR_Coverage, 21023,
     /*  615029 */     GIR_EraseRootFromParent_Done,
     /*  615030 */   // Label 9535: @615030
     /*  615030 */   GIM_Try, /*On fail goto*//*Label 9536*/ GIMT_Encode4(615091), // Rule ID 21024 //
     /*  615035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  615038 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  615045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  615049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  615060 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  615060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
     /*  615063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  615065 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  615067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  615072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  615077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  615082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615089 */     GIR_RootConstrainSelectedInstOperands,
     /*  615090 */     // GIR_Coverage, 21024,
     /*  615090 */     GIR_EraseRootFromParent_Done,
     /*  615091 */   // Label 9536: @615091
     /*  615091 */   GIM_Try, /*On fail goto*//*Label 9537*/ GIMT_Encode4(615152), // Rule ID 21025 //
     /*  615096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  615099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  615106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  615110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  615121 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  615121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
     /*  615124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  615126 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  615128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  615133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  615138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  615143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615150 */     GIR_RootConstrainSelectedInstOperands,
     /*  615151 */     // GIR_Coverage, 21025,
     /*  615151 */     GIR_EraseRootFromParent_Done,
     /*  615152 */   // Label 9537: @615152
     /*  615152 */   GIM_Try, /*On fail goto*//*Label 9538*/ GIMT_Encode4(615213), // Rule ID 21026 //
     /*  615157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  615160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  615167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  615171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  615182 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  615182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
     /*  615185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  615187 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  615189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  615194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  615199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  615204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615211 */     GIR_RootConstrainSelectedInstOperands,
     /*  615212 */     // GIR_Coverage, 21026,
     /*  615212 */     GIR_EraseRootFromParent_Done,
     /*  615213 */   // Label 9538: @615213
     /*  615213 */   GIM_Try, /*On fail goto*//*Label 9539*/ GIMT_Encode4(615274), // Rule ID 21027 //
     /*  615218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  615221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  615228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  615232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  615243 */     // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  615243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
     /*  615246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  615248 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  615250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  615255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  615260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  615265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615272 */     GIR_RootConstrainSelectedInstOperands,
     /*  615273 */     // GIR_Coverage, 21027,
     /*  615273 */     GIR_EraseRootFromParent_Done,
     /*  615274 */   // Label 9539: @615274
     /*  615274 */   GIM_Try, /*On fail goto*//*Label 9540*/ GIMT_Encode4(615324), // Rule ID 30348 //
     /*  615279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  615282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615287 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615300 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615308 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615322 */     GIR_RootConstrainSelectedInstOperands,
     /*  615323 */     // GIR_Coverage, 30348,
     /*  615323 */     GIR_EraseRootFromParent_Done,
     /*  615324 */   // Label 9540: @615324
     /*  615324 */   GIM_Try, /*On fail goto*//*Label 9541*/ GIMT_Encode4(615374), // Rule ID 30349 //
     /*  615329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  615332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615337 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615339 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615350 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615358 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615372 */     GIR_RootConstrainSelectedInstOperands,
     /*  615373 */     // GIR_Coverage, 30349,
     /*  615373 */     GIR_EraseRootFromParent_Done,
     /*  615374 */   // Label 9541: @615374
     /*  615374 */   GIM_Try, /*On fail goto*//*Label 9542*/ GIMT_Encode4(615424), // Rule ID 30350 //
     /*  615379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  615382 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615400 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615408 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615422 */     GIR_RootConstrainSelectedInstOperands,
     /*  615423 */     // GIR_Coverage, 30350,
     /*  615423 */     GIR_EraseRootFromParent_Done,
     /*  615424 */   // Label 9542: @615424
     /*  615424 */   GIM_Try, /*On fail goto*//*Label 9543*/ GIMT_Encode4(615474), // Rule ID 30351 //
     /*  615429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  615432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615437 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615443 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615450 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615458 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615472 */     GIR_RootConstrainSelectedInstOperands,
     /*  615473 */     // GIR_Coverage, 30351,
     /*  615473 */     GIR_EraseRootFromParent_Done,
     /*  615474 */   // Label 9543: @615474
     /*  615474 */   GIM_Try, /*On fail goto*//*Label 9544*/ GIMT_Encode4(615524), // Rule ID 30352 //
     /*  615479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  615482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615487 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615500 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615508 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615522 */     GIR_RootConstrainSelectedInstOperands,
     /*  615523 */     // GIR_Coverage, 30352,
     /*  615523 */     GIR_EraseRootFromParent_Done,
     /*  615524 */   // Label 9544: @615524
     /*  615524 */   GIM_Try, /*On fail goto*//*Label 9545*/ GIMT_Encode4(615574), // Rule ID 30354 //
     /*  615529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  615532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615537 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615550 */     // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_i32>>  =>  (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9),
     /*  615553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615558 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615572 */     GIR_RootConstrainSelectedInstOperands,
     /*  615573 */     // GIR_Coverage, 30354,
     /*  615573 */     GIR_EraseRootFromParent_Done,
     /*  615574 */   // Label 9545: @615574
     /*  615574 */   GIM_Try, /*On fail goto*//*Label 9546*/ GIMT_Encode4(615624), // Rule ID 30355 //
     /*  615579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  615582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615587 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615600 */     // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_i32>>  =>  (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9),
     /*  615603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615608 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615622 */     GIR_RootConstrainSelectedInstOperands,
     /*  615623 */     // GIR_Coverage, 30355,
     /*  615623 */     GIR_EraseRootFromParent_Done,
     /*  615624 */   // Label 9546: @615624
     /*  615624 */   GIM_Try, /*On fail goto*//*Label 9547*/ GIMT_Encode4(615674), // Rule ID 30356 //
     /*  615629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  615632 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615637 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615650 */     // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_i32>>  =>  (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9),
     /*  615653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615658 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615668 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615672 */     GIR_RootConstrainSelectedInstOperands,
     /*  615673 */     // GIR_Coverage, 30356,
     /*  615673 */     GIR_EraseRootFromParent_Done,
     /*  615674 */   // Label 9547: @615674
     /*  615674 */   GIM_Try, /*On fail goto*//*Label 9548*/ GIMT_Encode4(615724), // Rule ID 30357 //
     /*  615679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  615682 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615687 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615700 */     // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_i32>>  =>  (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9),
     /*  615703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615708 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615722 */     GIR_RootConstrainSelectedInstOperands,
     /*  615723 */     // GIR_Coverage, 30357,
     /*  615723 */     GIR_EraseRootFromParent_Done,
     /*  615724 */   // Label 9548: @615724
     /*  615724 */   GIM_Try, /*On fail goto*//*Label 9549*/ GIMT_Encode4(615774), // Rule ID 30358 //
     /*  615729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  615732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  615737 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615739 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615743 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615750 */     // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_i32>>  =>  (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  615750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9),
     /*  615753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615758 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  615768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615772 */     GIR_RootConstrainSelectedInstOperands,
     /*  615773 */     // GIR_Coverage, 30358,
     /*  615773 */     GIR_EraseRootFromParent_Done,
     /*  615774 */   // Label 9549: @615774
     /*  615774 */   GIM_Try, /*On fail goto*//*Label 9550*/ GIMT_Encode4(615824), // Rule ID 30360 //
     /*  615779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  615782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  615787 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615800 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  615800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615808 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615822 */     GIR_RootConstrainSelectedInstOperands,
     /*  615823 */     // GIR_Coverage, 30360,
     /*  615823 */     GIR_EraseRootFromParent_Done,
     /*  615824 */   // Label 9550: @615824
     /*  615824 */   GIM_Try, /*On fail goto*//*Label 9551*/ GIMT_Encode4(615874), // Rule ID 30361 //
     /*  615829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  615832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  615837 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615839 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615850 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  615850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615858 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615872 */     GIR_RootConstrainSelectedInstOperands,
     /*  615873 */     // GIR_Coverage, 30361,
     /*  615873 */     GIR_EraseRootFromParent_Done,
     /*  615874 */   // Label 9551: @615874
     /*  615874 */   GIM_Try, /*On fail goto*//*Label 9552*/ GIMT_Encode4(615924), // Rule ID 30362 //
     /*  615879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  615882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  615887 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615900 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  615900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615908 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615918 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615922 */     GIR_RootConstrainSelectedInstOperands,
     /*  615923 */     // GIR_Coverage, 30362,
     /*  615923 */     GIR_EraseRootFromParent_Done,
     /*  615924 */   // Label 9552: @615924
     /*  615924 */   GIM_Try, /*On fail goto*//*Label 9553*/ GIMT_Encode4(615974), // Rule ID 30363 //
     /*  615929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  615932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  615937 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  615950 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  615950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  615953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  615958 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  615960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  615965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  615968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  615972 */     GIR_RootConstrainSelectedInstOperands,
     /*  615973 */     // GIR_Coverage, 30363,
     /*  615973 */     GIR_EraseRootFromParent_Done,
     /*  615974 */   // Label 9553: @615974
     /*  615974 */   GIM_Try, /*On fail goto*//*Label 9554*/ GIMT_Encode4(616024), // Rule ID 30364 //
     /*  615979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  615982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  615987 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  615989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  615993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  616000 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  616000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
     /*  616003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  616008 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  616010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  616018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616022 */     GIR_RootConstrainSelectedInstOperands,
     /*  616023 */     // GIR_Coverage, 30364,
     /*  616023 */     GIR_EraseRootFromParent_Done,
     /*  616024 */   // Label 9554: @616024
     /*  616024 */   GIM_Try, /*On fail goto*//*Label 9555*/ GIMT_Encode4(616078), // Rule ID 30347 //
     /*  616029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  616032 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  616037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  616052 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_i32>>  =>  (DS_AND_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  616052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32),
     /*  616055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  616062 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  616064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616076 */     GIR_RootConstrainSelectedInstOperands,
     /*  616077 */     // GIR_Coverage, 30347,
     /*  616077 */     GIR_EraseRootFromParent_Done,
     /*  616078 */   // Label 9555: @616078
     /*  616078 */   GIM_Try, /*On fail goto*//*Label 9556*/ GIMT_Encode4(616132), // Rule ID 30353 //
     /*  616083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  616086 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  616091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  616106 */     // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_i32>>  =>  (DS_AND_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  616106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32_gfx9),
     /*  616109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  616116 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  616118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616130 */     GIR_RootConstrainSelectedInstOperands,
     /*  616131 */     // GIR_Coverage, 30353,
     /*  616131 */     GIR_EraseRootFromParent_Done,
     /*  616132 */   // Label 9556: @616132
     /*  616132 */   GIM_Try, /*On fail goto*//*Label 9557*/ GIMT_Encode4(616186), // Rule ID 30359 //
     /*  616137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  616140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  616145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  616160 */     // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_i32>>  =>  (DS_AND_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  616160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32),
     /*  616163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  616170 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  616172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  616180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616184 */     GIR_RootConstrainSelectedInstOperands,
     /*  616185 */     // GIR_Coverage, 30359,
     /*  616185 */     GIR_EraseRootFromParent_Done,
     /*  616186 */   // Label 9557: @616186
     /*  616186 */   GIM_Try, /*On fail goto*//*Label 9558*/ GIMT_Encode4(616245), // Rule ID 12945 //
     /*  616191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  616194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616201 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  616214 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  616214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR),
     /*  616217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  616222 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  616229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  616234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  616239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616243 */     GIR_RootConstrainSelectedInstOperands,
     /*  616244 */     // GIR_Coverage, 12945,
     /*  616244 */     GIR_EraseRootFromParent_Done,
     /*  616245 */   // Label 9558: @616245
     /*  616245 */   GIM_Try, /*On fail goto*//*Label 9559*/ GIMT_Encode4(616304), // Rule ID 12946 //
     /*  616250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  616253 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616260 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616266 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  616273 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  616273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR),
     /*  616276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  616281 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  616288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  616293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  616298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616302 */     GIR_RootConstrainSelectedInstOperands,
     /*  616303 */     // GIR_Coverage, 12946,
     /*  616303 */     GIR_EraseRootFromParent_Done,
     /*  616304 */   // Label 9559: @616304
     /*  616304 */   GIM_Try, /*On fail goto*//*Label 9560*/ GIMT_Encode4(616363), // Rule ID 12947 //
     /*  616309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  616312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616319 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  616332 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  616332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR),
     /*  616335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  616340 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  616347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  616352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  616357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616361 */     GIR_RootConstrainSelectedInstOperands,
     /*  616362 */     // GIR_Coverage, 12947,
     /*  616362 */     GIR_EraseRootFromParent_Done,
     /*  616363 */   // Label 9560: @616363
     /*  616363 */   GIM_Try, /*On fail goto*//*Label 9561*/ GIMT_Encode4(616422), // Rule ID 12948 //
     /*  616368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  616371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616378 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616380 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  616391 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  616391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR),
     /*  616394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  616399 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  616406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  616411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  616416 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616420 */     GIR_RootConstrainSelectedInstOperands,
     /*  616421 */     // GIR_Coverage, 12948,
     /*  616421 */     GIR_EraseRootFromParent_Done,
     /*  616422 */   // Label 9561: @616422
     /*  616422 */   GIM_Try, /*On fail goto*//*Label 9562*/ GIMT_Encode4(616481), // Rule ID 12949 //
     /*  616427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  616430 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616437 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616443 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  616450 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  616450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR),
     /*  616453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  616458 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  616465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  616470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  616475 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616479 */     GIR_RootConstrainSelectedInstOperands,
     /*  616480 */     // GIR_Coverage, 12949,
     /*  616480 */     GIR_EraseRootFromParent_Done,
     /*  616481 */   // Label 9562: @616481
     /*  616481 */   GIM_Try, /*On fail goto*//*Label 9563*/ GIMT_Encode4(616544), // Rule ID 12955 //
     /*  616486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  616489 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616500 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616504 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  616511 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (GLOBAL_ATOMIC_AND_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  616511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN),
     /*  616514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  616521 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  616528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  616533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  616538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616542 */     GIR_RootConstrainSelectedInstOperands,
     /*  616543 */     // GIR_Coverage, 12955,
     /*  616543 */     GIR_EraseRootFromParent_Done,
     /*  616544 */   // Label 9563: @616544
     /*  616544 */   GIM_Try, /*On fail goto*//*Label 9564*/ GIMT_Encode4(616596), // Rule ID 12940 //
     /*  616549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  616552 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616559 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616572 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND),
     /*  616575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616580 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616594 */     GIR_RootConstrainSelectedInstOperands,
     /*  616595 */     // GIR_Coverage, 12940,
     /*  616595 */     GIR_EraseRootFromParent_Done,
     /*  616596 */   // Label 9564: @616596
     /*  616596 */   GIM_Try, /*On fail goto*//*Label 9565*/ GIMT_Encode4(616648), // Rule ID 12941 //
     /*  616601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  616604 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616611 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616624 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND),
     /*  616627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616632 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616646 */     GIR_RootConstrainSelectedInstOperands,
     /*  616647 */     // GIR_Coverage, 12941,
     /*  616647 */     GIR_EraseRootFromParent_Done,
     /*  616648 */   // Label 9565: @616648
     /*  616648 */   GIM_Try, /*On fail goto*//*Label 9566*/ GIMT_Encode4(616700), // Rule ID 12942 //
     /*  616653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  616656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616663 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616676 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND),
     /*  616679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616684 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616698 */     GIR_RootConstrainSelectedInstOperands,
     /*  616699 */     // GIR_Coverage, 12942,
     /*  616699 */     GIR_EraseRootFromParent_Done,
     /*  616700 */   // Label 9566: @616700
     /*  616700 */   GIM_Try, /*On fail goto*//*Label 9567*/ GIMT_Encode4(616752), // Rule ID 12943 //
     /*  616705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  616708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616715 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616728 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND),
     /*  616731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616736 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616750 */     GIR_RootConstrainSelectedInstOperands,
     /*  616751 */     // GIR_Coverage, 12943,
     /*  616751 */     GIR_EraseRootFromParent_Done,
     /*  616752 */   // Label 9567: @616752
     /*  616752 */   GIM_Try, /*On fail goto*//*Label 9568*/ GIMT_Encode4(616804), // Rule ID 12944 //
     /*  616757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  616760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  616769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616780 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (GLOBAL_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND),
     /*  616783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616788 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  616798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616802 */     GIR_RootConstrainSelectedInstOperands,
     /*  616803 */     // GIR_Coverage, 12944,
     /*  616803 */     GIR_EraseRootFromParent_Done,
     /*  616804 */   // Label 9568: @616804
     /*  616804 */   GIM_Try, /*On fail goto*//*Label 9569*/ GIMT_Encode4(616860), // Rule ID 12950 //
     /*  616809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  616812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616834 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN),
     /*  616837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616844 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  616854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616858 */     GIR_RootConstrainSelectedInstOperands,
     /*  616859 */     // GIR_Coverage, 12950,
     /*  616859 */     GIR_EraseRootFromParent_Done,
     /*  616860 */   // Label 9569: @616860
     /*  616860 */   GIM_Try, /*On fail goto*//*Label 9570*/ GIMT_Encode4(616916), // Rule ID 12951 //
     /*  616865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  616868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616883 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616890 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN),
     /*  616893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616900 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  616910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616914 */     GIR_RootConstrainSelectedInstOperands,
     /*  616915 */     // GIR_Coverage, 12951,
     /*  616915 */     GIR_EraseRootFromParent_Done,
     /*  616916 */   // Label 9570: @616916
     /*  616916 */   GIM_Try, /*On fail goto*//*Label 9571*/ GIMT_Encode4(616972), // Rule ID 12952 //
     /*  616921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  616924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616935 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  616946 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  616946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN),
     /*  616949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  616951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  616956 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  616958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  616963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  616966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  616970 */     GIR_RootConstrainSelectedInstOperands,
     /*  616971 */     // GIR_Coverage, 12952,
     /*  616971 */     GIR_EraseRootFromParent_Done,
     /*  616972 */   // Label 9571: @616972
     /*  616972 */   GIM_Try, /*On fail goto*//*Label 9572*/ GIMT_Encode4(617028), // Rule ID 12953 //
     /*  616977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  616980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  616987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  616991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  616995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  617002 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  617002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN),
     /*  617005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  617007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  617012 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  617019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  617022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617026 */     GIR_RootConstrainSelectedInstOperands,
     /*  617027 */     // GIR_Coverage, 12953,
     /*  617027 */     GIR_EraseRootFromParent_Done,
     /*  617028 */   // Label 9572: @617028
     /*  617028 */   GIM_Try, /*On fail goto*//*Label 9573*/ GIMT_Encode4(617084), // Rule ID 12954 //
     /*  617033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  617036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  617047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  617058 */     // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  617058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN),
     /*  617061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  617063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  617068 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  617075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  617078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617082 */     GIR_RootConstrainSelectedInstOperands,
     /*  617083 */     // GIR_Coverage, 12954,
     /*  617083 */     GIR_EraseRootFromParent_Done,
     /*  617084 */   // Label 9573: @617084
     /*  617084 */   GIM_Try, /*On fail goto*//*Label 9574*/ GIMT_Encode4(617144), // Rule ID 10545 //
     /*  617089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  617092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617100 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617102 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617113 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617121 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617142 */     GIR_RootConstrainSelectedInstOperands,
     /*  617143 */     // GIR_Coverage, 10545,
     /*  617143 */     GIR_EraseRootFromParent_Done,
     /*  617144 */   // Label 9574: @617144
     /*  617144 */   GIM_Try, /*On fail goto*//*Label 9575*/ GIMT_Encode4(617204), // Rule ID 10546 //
     /*  617149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  617152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617160 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617162 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617166 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617173 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617181 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617202 */     GIR_RootConstrainSelectedInstOperands,
     /*  617203 */     // GIR_Coverage, 10546,
     /*  617203 */     GIR_EraseRootFromParent_Done,
     /*  617204 */   // Label 9575: @617204
     /*  617204 */   GIM_Try, /*On fail goto*//*Label 9576*/ GIMT_Encode4(617264), // Rule ID 10547 //
     /*  617209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  617212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617220 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617233 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617241 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617262 */     GIR_RootConstrainSelectedInstOperands,
     /*  617263 */     // GIR_Coverage, 10547,
     /*  617263 */     GIR_EraseRootFromParent_Done,
     /*  617264 */   // Label 9576: @617264
     /*  617264 */   GIM_Try, /*On fail goto*//*Label 9577*/ GIMT_Encode4(617324), // Rule ID 10548 //
     /*  617269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  617272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617280 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617293 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617301 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617322 */     GIR_RootConstrainSelectedInstOperands,
     /*  617323 */     // GIR_Coverage, 10548,
     /*  617323 */     GIR_EraseRootFromParent_Done,
     /*  617324 */   // Label 9577: @617324
     /*  617324 */   GIM_Try, /*On fail goto*//*Label 9578*/ GIMT_Encode4(617384), // Rule ID 10549 //
     /*  617329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  617332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617340 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617353 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617361 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617382 */     GIR_RootConstrainSelectedInstOperands,
     /*  617383 */     // GIR_Coverage, 10549,
     /*  617383 */     GIR_EraseRootFromParent_Done,
     /*  617384 */   // Label 9578: @617384
     /*  617384 */   GIM_Try, /*On fail goto*//*Label 9579*/ GIMT_Encode4(617443), // Rule ID 11101 //
     /*  617389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  617392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617399 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617412 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617420 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617441 */     GIR_RootConstrainSelectedInstOperands,
     /*  617442 */     // GIR_Coverage, 11101,
     /*  617442 */     GIR_EraseRootFromParent_Done,
     /*  617443 */   // Label 9579: @617443
     /*  617443 */   GIM_Try, /*On fail goto*//*Label 9580*/ GIMT_Encode4(617502), // Rule ID 11102 //
     /*  617448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  617451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617458 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617460 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617471 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617479 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617500 */     GIR_RootConstrainSelectedInstOperands,
     /*  617501 */     // GIR_Coverage, 11102,
     /*  617501 */     GIR_EraseRootFromParent_Done,
     /*  617502 */   // Label 9580: @617502
     /*  617502 */   GIM_Try, /*On fail goto*//*Label 9581*/ GIMT_Encode4(617561), // Rule ID 11103 //
     /*  617507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  617510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617517 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617530 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617538 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617559 */     GIR_RootConstrainSelectedInstOperands,
     /*  617560 */     // GIR_Coverage, 11103,
     /*  617560 */     GIR_EraseRootFromParent_Done,
     /*  617561 */   // Label 9581: @617561
     /*  617561 */   GIM_Try, /*On fail goto*//*Label 9582*/ GIMT_Encode4(617620), // Rule ID 11104 //
     /*  617566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  617569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617576 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617589 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617597 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617618 */     GIR_RootConstrainSelectedInstOperands,
     /*  617619 */     // GIR_Coverage, 11104,
     /*  617619 */     GIR_EraseRootFromParent_Done,
     /*  617620 */   // Label 9582: @617620
     /*  617620 */   GIM_Try, /*On fail goto*//*Label 9583*/ GIMT_Encode4(617679), // Rule ID 11105 //
     /*  617625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  617628 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617635 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  617648 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR),
     /*  617651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617656 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617677 */     GIR_RootConstrainSelectedInstOperands,
     /*  617678 */     // GIR_Coverage, 11105,
     /*  617678 */     GIR_EraseRootFromParent_Done,
     /*  617679 */   // Label 9583: @617679
     /*  617679 */   GIM_Try, /*On fail goto*//*Label 9584*/ GIMT_Encode4(617743), // Rule ID 10539 //
     /*  617684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  617687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  617699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  617710 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>>  =>  (FLAT_ATOMIC_AND_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR_RTN),
     /*  617713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  617715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617720 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617741 */     GIR_RootConstrainSelectedInstOperands,
     /*  617742 */     // GIR_Coverage, 10539,
     /*  617742 */     GIR_EraseRootFromParent_Done,
     /*  617743 */   // Label 9584: @617743
     /*  617743 */   GIM_Try, /*On fail goto*//*Label 9585*/ GIMT_Encode4(617806), // Rule ID 11095 //
     /*  617748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  617751 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  617762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  617773 */     // (atomic_load_and:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (FLAT_ATOMIC_AND_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  617773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_SADDR_RTN),
     /*  617776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  617778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  617783 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  617790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  617795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  617800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617804 */     GIR_RootConstrainSelectedInstOperands,
     /*  617805 */     // GIR_Coverage, 11095,
     /*  617805 */     GIR_EraseRootFromParent_Done,
     /*  617806 */   // Label 9585: @617806
     /*  617806 */   GIM_Try, /*On fail goto*//*Label 9586*/ GIMT_Encode4(617859), // Rule ID 10540 //
     /*  617811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  617814 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617822 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617824 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617828 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  617835 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  617835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  617838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  617843 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  617850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  617853 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617857 */     GIR_RootConstrainSelectedInstOperands,
     /*  617858 */     // GIR_Coverage, 10540,
     /*  617858 */     GIR_EraseRootFromParent_Done,
     /*  617859 */   // Label 9586: @617859
     /*  617859 */   GIM_Try, /*On fail goto*//*Label 9587*/ GIMT_Encode4(617912), // Rule ID 10541 //
     /*  617864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  617867 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617875 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  617888 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  617888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  617891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  617896 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  617903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  617906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617910 */     GIR_RootConstrainSelectedInstOperands,
     /*  617911 */     // GIR_Coverage, 10541,
     /*  617911 */     GIR_EraseRootFromParent_Done,
     /*  617912 */   // Label 9587: @617912
     /*  617912 */   GIM_Try, /*On fail goto*//*Label 9588*/ GIMT_Encode4(617965), // Rule ID 10542 //
     /*  617917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  617920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617928 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  617941 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  617941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  617944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  617949 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  617951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  617956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  617959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  617963 */     GIR_RootConstrainSelectedInstOperands,
     /*  617964 */     // GIR_Coverage, 10542,
     /*  617964 */     GIR_EraseRootFromParent_Done,
     /*  617965 */   // Label 9588: @617965
     /*  617965 */   GIM_Try, /*On fail goto*//*Label 9589*/ GIMT_Encode4(618018), // Rule ID 10543 //
     /*  617970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  617973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  617981 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  617983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  617987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  617994 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  617994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  617997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618002 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618012 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618016 */     GIR_RootConstrainSelectedInstOperands,
     /*  618017 */     // GIR_Coverage, 10543,
     /*  618017 */     GIR_EraseRootFromParent_Done,
     /*  618018 */   // Label 9589: @618018
     /*  618018 */   GIM_Try, /*On fail goto*//*Label 9590*/ GIMT_Encode4(618071), // Rule ID 10544 //
     /*  618023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  618026 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618034 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618047 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  618050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618055 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618069 */     GIR_RootConstrainSelectedInstOperands,
     /*  618070 */     // GIR_Coverage, 10544,
     /*  618070 */     GIR_EraseRootFromParent_Done,
     /*  618071 */   // Label 9590: @618071
     /*  618071 */   GIM_Try, /*On fail goto*//*Label 9591*/ GIMT_Encode4(618123), // Rule ID 11096 //
     /*  618076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  618079 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618086 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618088 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618092 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618099 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  618102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618107 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618121 */     GIR_RootConstrainSelectedInstOperands,
     /*  618122 */     // GIR_Coverage, 11096,
     /*  618122 */     GIR_EraseRootFromParent_Done,
     /*  618123 */   // Label 9591: @618123
     /*  618123 */   GIM_Try, /*On fail goto*//*Label 9592*/ GIMT_Encode4(618175), // Rule ID 11097 //
     /*  618128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  618131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618138 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618151 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  618154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618159 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618166 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618173 */     GIR_RootConstrainSelectedInstOperands,
     /*  618174 */     // GIR_Coverage, 11097,
     /*  618174 */     GIR_EraseRootFromParent_Done,
     /*  618175 */   // Label 9592: @618175
     /*  618175 */   GIM_Try, /*On fail goto*//*Label 9593*/ GIMT_Encode4(618227), // Rule ID 11098 //
     /*  618180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  618183 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618190 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618203 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  618206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618211 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618221 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618225 */     GIR_RootConstrainSelectedInstOperands,
     /*  618226 */     // GIR_Coverage, 11098,
     /*  618226 */     GIR_EraseRootFromParent_Done,
     /*  618227 */   // Label 9593: @618227
     /*  618227 */   GIM_Try, /*On fail goto*//*Label 9594*/ GIMT_Encode4(618279), // Rule ID 11099 //
     /*  618232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  618235 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618242 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618255 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  618258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618263 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618277 */     GIR_RootConstrainSelectedInstOperands,
     /*  618278 */     // GIR_Coverage, 11099,
     /*  618278 */     GIR_EraseRootFromParent_Done,
     /*  618279 */   // Label 9594: @618279
     /*  618279 */   GIM_Try, /*On fail goto*//*Label 9595*/ GIMT_Encode4(618331), // Rule ID 11100 //
     /*  618284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  618287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618294 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618307 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>>  =>  (FLAT_ATOMIC_AND VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
     /*  618310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618315 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618329 */     GIR_RootConstrainSelectedInstOperands,
     /*  618330 */     // GIR_Coverage, 11100,
     /*  618330 */     GIR_EraseRootFromParent_Done,
     /*  618331 */   // Label 9595: @618331
     /*  618331 */   GIM_Try, /*On fail goto*//*Label 9596*/ GIMT_Encode4(618388), // Rule ID 10534 //
     /*  618336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  618339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618351 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618362 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618372 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618386 */     GIR_RootConstrainSelectedInstOperands,
     /*  618387 */     // GIR_Coverage, 10534,
     /*  618387 */     GIR_EraseRootFromParent_Done,
     /*  618388 */   // Label 9596: @618388
     /*  618388 */   GIM_Try, /*On fail goto*//*Label 9597*/ GIMT_Encode4(618445), // Rule ID 10535 //
     /*  618393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  618396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618419 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618429 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618443 */     GIR_RootConstrainSelectedInstOperands,
     /*  618444 */     // GIR_Coverage, 10535,
     /*  618444 */     GIR_EraseRootFromParent_Done,
     /*  618445 */   // Label 9597: @618445
     /*  618445 */   GIM_Try, /*On fail goto*//*Label 9598*/ GIMT_Encode4(618502), // Rule ID 10536 //
     /*  618450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  618453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618476 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618486 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618500 */     GIR_RootConstrainSelectedInstOperands,
     /*  618501 */     // GIR_Coverage, 10536,
     /*  618501 */     GIR_EraseRootFromParent_Done,
     /*  618502 */   // Label 9598: @618502
     /*  618502 */   GIM_Try, /*On fail goto*//*Label 9599*/ GIMT_Encode4(618559), // Rule ID 10537 //
     /*  618507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  618510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618533 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618543 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618553 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618557 */     GIR_RootConstrainSelectedInstOperands,
     /*  618558 */     // GIR_Coverage, 10537,
     /*  618558 */     GIR_EraseRootFromParent_Done,
     /*  618559 */   // Label 9599: @618559
     /*  618559 */   GIM_Try, /*On fail goto*//*Label 9600*/ GIMT_Encode4(618616), // Rule ID 10538 //
     /*  618564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  618567 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618590 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618600 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618614 */     GIR_RootConstrainSelectedInstOperands,
     /*  618615 */     // GIR_Coverage, 10538,
     /*  618615 */     GIR_EraseRootFromParent_Done,
     /*  618616 */   // Label 9600: @618616
     /*  618616 */   GIM_Try, /*On fail goto*//*Label 9601*/ GIMT_Encode4(618672), // Rule ID 11090 //
     /*  618621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  618624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618646 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618656 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618670 */     GIR_RootConstrainSelectedInstOperands,
     /*  618671 */     // GIR_Coverage, 11090,
     /*  618671 */     GIR_EraseRootFromParent_Done,
     /*  618672 */   // Label 9601: @618672
     /*  618672 */   GIM_Try, /*On fail goto*//*Label 9602*/ GIMT_Encode4(618728), // Rule ID 11091 //
     /*  618677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  618680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618702 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618712 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618726 */     GIR_RootConstrainSelectedInstOperands,
     /*  618727 */     // GIR_Coverage, 11091,
     /*  618727 */     GIR_EraseRootFromParent_Done,
     /*  618728 */   // Label 9602: @618728
     /*  618728 */   GIM_Try, /*On fail goto*//*Label 9603*/ GIMT_Encode4(618784), // Rule ID 11092 //
     /*  618733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  618736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618758 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618768 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618782 */     GIR_RootConstrainSelectedInstOperands,
     /*  618783 */     // GIR_Coverage, 11092,
     /*  618783 */     GIR_EraseRootFromParent_Done,
     /*  618784 */   // Label 9603: @618784
     /*  618784 */   GIM_Try, /*On fail goto*//*Label 9604*/ GIMT_Encode4(618840), // Rule ID 11093 //
     /*  618789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  618792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618814 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618824 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618838 */     GIR_RootConstrainSelectedInstOperands,
     /*  618839 */     // GIR_Coverage, 11093,
     /*  618839 */     GIR_EraseRootFromParent_Done,
     /*  618840 */   // Label 9604: @618840
     /*  618840 */   GIM_Try, /*On fail goto*//*Label 9605*/ GIMT_Encode4(618896), // Rule ID 11094 //
     /*  618845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  618848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  618859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  618870 */     // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  618870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
     /*  618873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  618875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  618880 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  618882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  618887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  618890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618894 */     GIR_RootConstrainSelectedInstOperands,
     /*  618895 */     // GIR_Coverage, 11094,
     /*  618895 */     GIR_EraseRootFromParent_Done,
     /*  618896 */   // Label 9605: @618896
     /*  618896 */   GIM_Reject,
     /*  618897 */ // Label 9499: @618897
     /*  618897 */ GIM_Reject,
     /*  618898 */ // Label 9497: @618898
     /*  618898 */ GIM_Try, /*On fail goto*//*Label 9606*/ GIMT_Encode4(626397),
     /*  618903 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  618906 */   GIM_Try, /*On fail goto*//*Label 9607*/ GIMT_Encode4(618968), // Rule ID 21498 //
     /*  618911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  618914 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618921 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618923 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618927 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  618934 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  618934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64),
     /*  618937 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  618939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  618944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  618949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  618954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  618959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  618962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  618966 */     GIR_RootConstrainSelectedInstOperands,
     /*  618967 */     // GIR_Coverage, 21498,
     /*  618967 */     GIR_EraseRootFromParent_Done,
     /*  618968 */   // Label 9607: @618968
     /*  618968 */   GIM_Try, /*On fail goto*//*Label 9608*/ GIMT_Encode4(619030), // Rule ID 21499 //
     /*  618973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  618976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  618983 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  618985 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  618989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  618996 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  618996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64),
     /*  618999 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619028 */     GIR_RootConstrainSelectedInstOperands,
     /*  619029 */     // GIR_Coverage, 21499,
     /*  619029 */     GIR_EraseRootFromParent_Done,
     /*  619030 */   // Label 9608: @619030
     /*  619030 */   GIM_Try, /*On fail goto*//*Label 9609*/ GIMT_Encode4(619092), // Rule ID 21500 //
     /*  619035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  619038 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619045 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619058 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64),
     /*  619061 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619083 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619090 */     GIR_RootConstrainSelectedInstOperands,
     /*  619091 */     // GIR_Coverage, 21500,
     /*  619091 */     GIR_EraseRootFromParent_Done,
     /*  619092 */   // Label 9609: @619092
     /*  619092 */   GIM_Try, /*On fail goto*//*Label 9610*/ GIMT_Encode4(619154), // Rule ID 21501 //
     /*  619097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  619100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619107 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619109 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619120 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64),
     /*  619123 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619148 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619152 */     GIR_RootConstrainSelectedInstOperands,
     /*  619153 */     // GIR_Coverage, 21501,
     /*  619153 */     GIR_EraseRootFromParent_Done,
     /*  619154 */   // Label 9610: @619154
     /*  619154 */   GIM_Try, /*On fail goto*//*Label 9611*/ GIMT_Encode4(619216), // Rule ID 21502 //
     /*  619159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  619162 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619169 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619182 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64),
     /*  619185 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619214 */     GIR_RootConstrainSelectedInstOperands,
     /*  619215 */     // GIR_Coverage, 21502,
     /*  619215 */     GIR_EraseRootFromParent_Done,
     /*  619216 */   // Label 9611: @619216
     /*  619216 */   GIM_Try, /*On fail goto*//*Label 9612*/ GIMT_Encode4(619278), // Rule ID 21518 //
     /*  619221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  619224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619231 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619244 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64),
     /*  619247 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619276 */     GIR_RootConstrainSelectedInstOperands,
     /*  619277 */     // GIR_Coverage, 21518,
     /*  619277 */     GIR_EraseRootFromParent_Done,
     /*  619278 */   // Label 9612: @619278
     /*  619278 */   GIM_Try, /*On fail goto*//*Label 9613*/ GIMT_Encode4(619340), // Rule ID 21519 //
     /*  619283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  619286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619293 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619306 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64),
     /*  619309 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619338 */     GIR_RootConstrainSelectedInstOperands,
     /*  619339 */     // GIR_Coverage, 21519,
     /*  619339 */     GIR_EraseRootFromParent_Done,
     /*  619340 */   // Label 9613: @619340
     /*  619340 */   GIM_Try, /*On fail goto*//*Label 9614*/ GIMT_Encode4(619402), // Rule ID 21520 //
     /*  619345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  619348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619355 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619368 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64),
     /*  619371 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619400 */     GIR_RootConstrainSelectedInstOperands,
     /*  619401 */     // GIR_Coverage, 21520,
     /*  619401 */     GIR_EraseRootFromParent_Done,
     /*  619402 */   // Label 9614: @619402
     /*  619402 */   GIM_Try, /*On fail goto*//*Label 9615*/ GIMT_Encode4(619464), // Rule ID 21521 //
     /*  619407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  619410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619417 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619430 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64),
     /*  619433 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619462 */     GIR_RootConstrainSelectedInstOperands,
     /*  619463 */     // GIR_Coverage, 21521,
     /*  619463 */     GIR_EraseRootFromParent_Done,
     /*  619464 */   // Label 9615: @619464
     /*  619464 */   GIM_Try, /*On fail goto*//*Label 9616*/ GIMT_Encode4(619526), // Rule ID 21522 //
     /*  619469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  619472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619479 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  619481 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619492 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64),
     /*  619495 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  619520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619524 */     GIR_RootConstrainSelectedInstOperands,
     /*  619525 */     // GIR_Coverage, 21522,
     /*  619525 */     GIR_EraseRootFromParent_Done,
     /*  619526 */   // Label 9616: @619526
     /*  619526 */   GIM_Try, /*On fail goto*//*Label 9617*/ GIMT_Encode4(619592), // Rule ID 21488 //
     /*  619531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  619534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619556 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN),
     /*  619559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619561 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619590 */     GIR_RootConstrainSelectedInstOperands,
     /*  619591 */     // GIR_Coverage, 21488,
     /*  619591 */     GIR_EraseRootFromParent_Done,
     /*  619592 */   // Label 9617: @619592
     /*  619592 */   GIM_Try, /*On fail goto*//*Label 9618*/ GIMT_Encode4(619658), // Rule ID 21489 //
     /*  619597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  619600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619622 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN),
     /*  619625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619627 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619656 */     GIR_RootConstrainSelectedInstOperands,
     /*  619657 */     // GIR_Coverage, 21489,
     /*  619657 */     GIR_EraseRootFromParent_Done,
     /*  619658 */   // Label 9618: @619658
     /*  619658 */   GIM_Try, /*On fail goto*//*Label 9619*/ GIMT_Encode4(619724), // Rule ID 21490 //
     /*  619663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  619666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619688 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN),
     /*  619691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619693 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619722 */     GIR_RootConstrainSelectedInstOperands,
     /*  619723 */     // GIR_Coverage, 21490,
     /*  619723 */     GIR_EraseRootFromParent_Done,
     /*  619724 */   // Label 9619: @619724
     /*  619724 */   GIM_Try, /*On fail goto*//*Label 9620*/ GIMT_Encode4(619790), // Rule ID 21491 //
     /*  619729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  619732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619754 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN),
     /*  619757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619759 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619788 */     GIR_RootConstrainSelectedInstOperands,
     /*  619789 */     // GIR_Coverage, 21491,
     /*  619789 */     GIR_EraseRootFromParent_Done,
     /*  619790 */   // Label 9620: @619790
     /*  619790 */   GIM_Try, /*On fail goto*//*Label 9621*/ GIMT_Encode4(619856), // Rule ID 21492 //
     /*  619795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  619798 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619820 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN),
     /*  619823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619825 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619854 */     GIR_RootConstrainSelectedInstOperands,
     /*  619855 */     // GIR_Coverage, 21492,
     /*  619855 */     GIR_EraseRootFromParent_Done,
     /*  619856 */   // Label 9621: @619856
     /*  619856 */   GIM_Try, /*On fail goto*//*Label 9622*/ GIMT_Encode4(619922), // Rule ID 21508 //
     /*  619861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  619864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619886 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN),
     /*  619889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619891 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619920 */     GIR_RootConstrainSelectedInstOperands,
     /*  619921 */     // GIR_Coverage, 21508,
     /*  619921 */     GIR_EraseRootFromParent_Done,
     /*  619922 */   // Label 9622: @619922
     /*  619922 */   GIM_Try, /*On fail goto*//*Label 9623*/ GIMT_Encode4(619988), // Rule ID 21509 //
     /*  619927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  619930 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  619937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  619941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  619945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  619952 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  619952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN),
     /*  619955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  619957 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  619959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  619964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  619969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  619974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  619979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  619982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  619986 */     GIR_RootConstrainSelectedInstOperands,
     /*  619987 */     // GIR_Coverage, 21509,
     /*  619987 */     GIR_EraseRootFromParent_Done,
     /*  619988 */   // Label 9623: @619988
     /*  619988 */   GIM_Try, /*On fail goto*//*Label 9624*/ GIMT_Encode4(620054), // Rule ID 21510 //
     /*  619993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  619996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  620018 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN),
     /*  620021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620023 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  620030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  620040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  620045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620052 */     GIR_RootConstrainSelectedInstOperands,
     /*  620053 */     // GIR_Coverage, 21510,
     /*  620053 */     GIR_EraseRootFromParent_Done,
     /*  620054 */   // Label 9624: @620054
     /*  620054 */   GIM_Try, /*On fail goto*//*Label 9625*/ GIMT_Encode4(620120), // Rule ID 21511 //
     /*  620059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  620062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  620084 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN),
     /*  620087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620089 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  620096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  620106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  620111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620118 */     GIR_RootConstrainSelectedInstOperands,
     /*  620119 */     // GIR_Coverage, 21511,
     /*  620119 */     GIR_EraseRootFromParent_Done,
     /*  620120 */   // Label 9625: @620120
     /*  620120 */   GIM_Try, /*On fail goto*//*Label 9626*/ GIMT_Encode4(620186), // Rule ID 21512 //
     /*  620125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  620128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  620150 */     // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN),
     /*  620153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620155 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  620162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  620172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  620177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620184 */     GIR_RootConstrainSelectedInstOperands,
     /*  620185 */     // GIR_Coverage, 21512,
     /*  620185 */     GIR_EraseRootFromParent_Done,
     /*  620186 */   // Label 9626: @620186
     /*  620186 */   GIM_Try, /*On fail goto*//*Label 9627*/ GIMT_Encode4(620243), // Rule ID 21493 //
     /*  620191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  620194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620201 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620214 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
     /*  620217 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620241 */     GIR_RootConstrainSelectedInstOperands,
     /*  620242 */     // GIR_Coverage, 21493,
     /*  620242 */     GIR_EraseRootFromParent_Done,
     /*  620243 */   // Label 9627: @620243
     /*  620243 */   GIM_Try, /*On fail goto*//*Label 9628*/ GIMT_Encode4(620300), // Rule ID 21494 //
     /*  620248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  620251 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620258 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620271 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
     /*  620274 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620298 */     GIR_RootConstrainSelectedInstOperands,
     /*  620299 */     // GIR_Coverage, 21494,
     /*  620299 */     GIR_EraseRootFromParent_Done,
     /*  620300 */   // Label 9628: @620300
     /*  620300 */   GIM_Try, /*On fail goto*//*Label 9629*/ GIMT_Encode4(620357), // Rule ID 21495 //
     /*  620305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  620308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620315 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620328 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
     /*  620331 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620355 */     GIR_RootConstrainSelectedInstOperands,
     /*  620356 */     // GIR_Coverage, 21495,
     /*  620356 */     GIR_EraseRootFromParent_Done,
     /*  620357 */   // Label 9629: @620357
     /*  620357 */   GIM_Try, /*On fail goto*//*Label 9630*/ GIMT_Encode4(620414), // Rule ID 21496 //
     /*  620362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  620365 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620372 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620385 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
     /*  620388 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620412 */     GIR_RootConstrainSelectedInstOperands,
     /*  620413 */     // GIR_Coverage, 21496,
     /*  620413 */     GIR_EraseRootFromParent_Done,
     /*  620414 */   // Label 9630: @620414
     /*  620414 */   GIM_Try, /*On fail goto*//*Label 9631*/ GIMT_Encode4(620471), // Rule ID 21497 //
     /*  620419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  620422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620429 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620442 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
     /*  620445 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620469 */     GIR_RootConstrainSelectedInstOperands,
     /*  620470 */     // GIR_Coverage, 21497,
     /*  620470 */     GIR_EraseRootFromParent_Done,
     /*  620471 */   // Label 9631: @620471
     /*  620471 */   GIM_Try, /*On fail goto*//*Label 9632*/ GIMT_Encode4(620528), // Rule ID 21513 //
     /*  620476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  620479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620486 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620499 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
     /*  620502 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620526 */     GIR_RootConstrainSelectedInstOperands,
     /*  620527 */     // GIR_Coverage, 21513,
     /*  620527 */     GIR_EraseRootFromParent_Done,
     /*  620528 */   // Label 9632: @620528
     /*  620528 */   GIM_Try, /*On fail goto*//*Label 9633*/ GIMT_Encode4(620585), // Rule ID 21514 //
     /*  620533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  620536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620543 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620556 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
     /*  620559 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620583 */     GIR_RootConstrainSelectedInstOperands,
     /*  620584 */     // GIR_Coverage, 21514,
     /*  620584 */     GIR_EraseRootFromParent_Done,
     /*  620585 */   // Label 9633: @620585
     /*  620585 */   GIM_Try, /*On fail goto*//*Label 9634*/ GIMT_Encode4(620642), // Rule ID 21515 //
     /*  620590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  620593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620600 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620613 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
     /*  620616 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620640 */     GIR_RootConstrainSelectedInstOperands,
     /*  620641 */     // GIR_Coverage, 21515,
     /*  620641 */     GIR_EraseRootFromParent_Done,
     /*  620642 */   // Label 9634: @620642
     /*  620642 */   GIM_Try, /*On fail goto*//*Label 9635*/ GIMT_Encode4(620699), // Rule ID 21516 //
     /*  620647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  620650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620657 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620670 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
     /*  620673 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620697 */     GIR_RootConstrainSelectedInstOperands,
     /*  620698 */     // GIR_Coverage, 21516,
     /*  620698 */     GIR_EraseRootFromParent_Done,
     /*  620699 */   // Label 9635: @620699
     /*  620699 */   GIM_Try, /*On fail goto*//*Label 9636*/ GIMT_Encode4(620756), // Rule ID 21517 //
     /*  620704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  620707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620714 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  620716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620727 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
     /*  620730 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  620750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620754 */     GIR_RootConstrainSelectedInstOperands,
     /*  620755 */     // GIR_Coverage, 21517,
     /*  620755 */     GIR_EraseRootFromParent_Done,
     /*  620756 */   // Label 9636: @620756
     /*  620756 */   GIM_Try, /*On fail goto*//*Label 9637*/ GIMT_Encode4(620817), // Rule ID 21483 //
     /*  620761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  620764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620786 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
     /*  620789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620791 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620815 */     GIR_RootConstrainSelectedInstOperands,
     /*  620816 */     // GIR_Coverage, 21483,
     /*  620816 */     GIR_EraseRootFromParent_Done,
     /*  620817 */   // Label 9637: @620817
     /*  620817 */   GIM_Try, /*On fail goto*//*Label 9638*/ GIMT_Encode4(620878), // Rule ID 21484 //
     /*  620822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  620825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620847 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
     /*  620850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620852 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620876 */     GIR_RootConstrainSelectedInstOperands,
     /*  620877 */     // GIR_Coverage, 21484,
     /*  620877 */     GIR_EraseRootFromParent_Done,
     /*  620878 */   // Label 9638: @620878
     /*  620878 */   GIM_Try, /*On fail goto*//*Label 9639*/ GIMT_Encode4(620939), // Rule ID 21485 //
     /*  620883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  620886 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620908 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
     /*  620911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620913 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620937 */     GIR_RootConstrainSelectedInstOperands,
     /*  620938 */     // GIR_Coverage, 21485,
     /*  620938 */     GIR_EraseRootFromParent_Done,
     /*  620939 */   // Label 9639: @620939
     /*  620939 */   GIM_Try, /*On fail goto*//*Label 9640*/ GIMT_Encode4(621000), // Rule ID 21486 //
     /*  620944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  620947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  620954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  620958 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  620962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  620969 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  620969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
     /*  620972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  620974 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  620976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  620981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  620986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  620991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  620994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  620998 */     GIR_RootConstrainSelectedInstOperands,
     /*  620999 */     // GIR_Coverage, 21486,
     /*  620999 */     GIR_EraseRootFromParent_Done,
     /*  621000 */   // Label 9640: @621000
     /*  621000 */   GIM_Try, /*On fail goto*//*Label 9641*/ GIMT_Encode4(621061), // Rule ID 21487 //
     /*  621005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  621008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  621015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  621019 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621023 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  621030 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  621030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
     /*  621033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  621035 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  621037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  621042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  621047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  621052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621055 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621059 */     GIR_RootConstrainSelectedInstOperands,
     /*  621060 */     // GIR_Coverage, 21487,
     /*  621060 */     GIR_EraseRootFromParent_Done,
     /*  621061 */   // Label 9641: @621061
     /*  621061 */   GIM_Try, /*On fail goto*//*Label 9642*/ GIMT_Encode4(621122), // Rule ID 21503 //
     /*  621066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  621069 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  621076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  621080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  621091 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  621091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
     /*  621094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  621096 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  621098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  621103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  621108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  621113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621120 */     GIR_RootConstrainSelectedInstOperands,
     /*  621121 */     // GIR_Coverage, 21503,
     /*  621121 */     GIR_EraseRootFromParent_Done,
     /*  621122 */   // Label 9642: @621122
     /*  621122 */   GIM_Try, /*On fail goto*//*Label 9643*/ GIMT_Encode4(621183), // Rule ID 21504 //
     /*  621127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  621130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  621137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  621141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  621152 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  621152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
     /*  621155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  621157 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  621159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  621164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  621169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  621174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621181 */     GIR_RootConstrainSelectedInstOperands,
     /*  621182 */     // GIR_Coverage, 21504,
     /*  621182 */     GIR_EraseRootFromParent_Done,
     /*  621183 */   // Label 9643: @621183
     /*  621183 */   GIM_Try, /*On fail goto*//*Label 9644*/ GIMT_Encode4(621244), // Rule ID 21505 //
     /*  621188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  621191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  621198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  621202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621206 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  621213 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  621213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
     /*  621216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  621218 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  621220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  621225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  621230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  621235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621242 */     GIR_RootConstrainSelectedInstOperands,
     /*  621243 */     // GIR_Coverage, 21505,
     /*  621243 */     GIR_EraseRootFromParent_Done,
     /*  621244 */   // Label 9644: @621244
     /*  621244 */   GIM_Try, /*On fail goto*//*Label 9645*/ GIMT_Encode4(621305), // Rule ID 21506 //
     /*  621249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  621252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  621259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  621263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  621274 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  621274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
     /*  621277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  621279 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  621281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  621286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  621291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  621296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621303 */     GIR_RootConstrainSelectedInstOperands,
     /*  621304 */     // GIR_Coverage, 21506,
     /*  621304 */     GIR_EraseRootFromParent_Done,
     /*  621305 */   // Label 9645: @621305
     /*  621305 */   GIM_Try, /*On fail goto*//*Label 9646*/ GIMT_Encode4(621366), // Rule ID 21507 //
     /*  621310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  621313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  621320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  621324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  621335 */     // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  621335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
     /*  621338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  621340 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  621342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  621347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  621352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  621357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621360 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621364 */     GIR_RootConstrainSelectedInstOperands,
     /*  621365 */     // GIR_Coverage, 21507,
     /*  621365 */     GIR_EraseRootFromParent_Done,
     /*  621366 */   // Label 9646: @621366
     /*  621366 */   GIM_Try, /*On fail goto*//*Label 9647*/ GIMT_Encode4(621416), // Rule ID 30685 //
     /*  621371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  621374 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621392 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621400 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621414 */     GIR_RootConstrainSelectedInstOperands,
     /*  621415 */     // GIR_Coverage, 30685,
     /*  621415 */     GIR_EraseRootFromParent_Done,
     /*  621416 */   // Label 9647: @621416
     /*  621416 */   GIM_Try, /*On fail goto*//*Label 9648*/ GIMT_Encode4(621466), // Rule ID 30686 //
     /*  621421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  621424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621429 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621442 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621450 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621464 */     GIR_RootConstrainSelectedInstOperands,
     /*  621465 */     // GIR_Coverage, 30686,
     /*  621465 */     GIR_EraseRootFromParent_Done,
     /*  621466 */   // Label 9648: @621466
     /*  621466 */   GIM_Try, /*On fail goto*//*Label 9649*/ GIMT_Encode4(621516), // Rule ID 30687 //
     /*  621471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  621474 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621479 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621481 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621492 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621500 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621514 */     GIR_RootConstrainSelectedInstOperands,
     /*  621515 */     // GIR_Coverage, 30687,
     /*  621515 */     GIR_EraseRootFromParent_Done,
     /*  621516 */   // Label 9649: @621516
     /*  621516 */   GIM_Try, /*On fail goto*//*Label 9650*/ GIMT_Encode4(621566), // Rule ID 30688 //
     /*  621521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  621524 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621529 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621542 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621550 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621560 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621564 */     GIR_RootConstrainSelectedInstOperands,
     /*  621565 */     // GIR_Coverage, 30688,
     /*  621565 */     GIR_EraseRootFromParent_Done,
     /*  621566 */   // Label 9650: @621566
     /*  621566 */   GIM_Try, /*On fail goto*//*Label 9651*/ GIMT_Encode4(621616), // Rule ID 30689 //
     /*  621571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  621574 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621579 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621592 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621600 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621614 */     GIR_RootConstrainSelectedInstOperands,
     /*  621615 */     // GIR_Coverage, 30689,
     /*  621615 */     GIR_EraseRootFromParent_Done,
     /*  621616 */   // Label 9651: @621616
     /*  621616 */   GIM_Try, /*On fail goto*//*Label 9652*/ GIMT_Encode4(621666), // Rule ID 30695 //
     /*  621621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  621624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621629 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621642 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_i64>>  =>  (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9),
     /*  621645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621650 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621664 */     GIR_RootConstrainSelectedInstOperands,
     /*  621665 */     // GIR_Coverage, 30695,
     /*  621665 */     GIR_EraseRootFromParent_Done,
     /*  621666 */   // Label 9652: @621666
     /*  621666 */   GIM_Try, /*On fail goto*//*Label 9653*/ GIMT_Encode4(621716), // Rule ID 30696 //
     /*  621671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  621674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621679 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621692 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_i64>>  =>  (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9),
     /*  621695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621700 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621714 */     GIR_RootConstrainSelectedInstOperands,
     /*  621715 */     // GIR_Coverage, 30696,
     /*  621715 */     GIR_EraseRootFromParent_Done,
     /*  621716 */   // Label 9653: @621716
     /*  621716 */   GIM_Try, /*On fail goto*//*Label 9654*/ GIMT_Encode4(621766), // Rule ID 30697 //
     /*  621721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  621724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621729 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621731 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621735 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621742 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_i64>>  =>  (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9),
     /*  621745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621750 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621760 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621764 */     GIR_RootConstrainSelectedInstOperands,
     /*  621765 */     // GIR_Coverage, 30697,
     /*  621765 */     GIR_EraseRootFromParent_Done,
     /*  621766 */   // Label 9654: @621766
     /*  621766 */   GIM_Try, /*On fail goto*//*Label 9655*/ GIMT_Encode4(621816), // Rule ID 30698 //
     /*  621771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  621774 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621779 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621792 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_i64>>  =>  (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9),
     /*  621795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621800 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621814 */     GIR_RootConstrainSelectedInstOperands,
     /*  621815 */     // GIR_Coverage, 30698,
     /*  621815 */     GIR_EraseRootFromParent_Done,
     /*  621816 */   // Label 9655: @621816
     /*  621816 */   GIM_Try, /*On fail goto*//*Label 9656*/ GIMT_Encode4(621866), // Rule ID 30699 //
     /*  621821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  621824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  621829 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621831 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621835 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621842 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_i64>>  =>  (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  621842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9),
     /*  621845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621850 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  621860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621864 */     GIR_RootConstrainSelectedInstOperands,
     /*  621865 */     // GIR_Coverage, 30699,
     /*  621865 */     GIR_EraseRootFromParent_Done,
     /*  621866 */   // Label 9656: @621866
     /*  621866 */   GIM_Try, /*On fail goto*//*Label 9657*/ GIMT_Encode4(621916), // Rule ID 30705 //
     /*  621871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  621874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  621879 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621881 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621892 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  621892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621900 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621914 */     GIR_RootConstrainSelectedInstOperands,
     /*  621915 */     // GIR_Coverage, 30705,
     /*  621915 */     GIR_EraseRootFromParent_Done,
     /*  621916 */   // Label 9657: @621916
     /*  621916 */   GIM_Try, /*On fail goto*//*Label 9658*/ GIMT_Encode4(621966), // Rule ID 30706 //
     /*  621921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  621924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  621929 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621942 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  621942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  621950 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  621952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  621957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  621960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  621964 */     GIR_RootConstrainSelectedInstOperands,
     /*  621965 */     // GIR_Coverage, 30706,
     /*  621965 */     GIR_EraseRootFromParent_Done,
     /*  621966 */   // Label 9658: @621966
     /*  621966 */   GIM_Try, /*On fail goto*//*Label 9659*/ GIMT_Encode4(622016), // Rule ID 30707 //
     /*  621971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  621974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  621979 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  621981 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  621985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  621992 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  621992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  621995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622000 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622014 */     GIR_RootConstrainSelectedInstOperands,
     /*  622015 */     // GIR_Coverage, 30707,
     /*  622015 */     GIR_EraseRootFromParent_Done,
     /*  622016 */   // Label 9659: @622016
     /*  622016 */   GIM_Try, /*On fail goto*//*Label 9660*/ GIMT_Encode4(622066), // Rule ID 30708 //
     /*  622021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  622024 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622029 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  622031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622042 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  622045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622050 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622060 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622064 */     GIR_RootConstrainSelectedInstOperands,
     /*  622065 */     // GIR_Coverage, 30708,
     /*  622065 */     GIR_EraseRootFromParent_Done,
     /*  622066 */   // Label 9660: @622066
     /*  622066 */   GIM_Try, /*On fail goto*//*Label 9661*/ GIMT_Encode4(622116), // Rule ID 30709 //
     /*  622071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  622074 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622079 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  622081 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622085 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622092 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
     /*  622095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622100 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622114 */     GIR_RootConstrainSelectedInstOperands,
     /*  622115 */     // GIR_Coverage, 30709,
     /*  622115 */     GIR_EraseRootFromParent_Done,
     /*  622116 */   // Label 9661: @622116
     /*  622116 */   GIM_Try, /*On fail goto*//*Label 9662*/ GIMT_Encode4(622170), // Rule ID 30680 //
     /*  622121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  622124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622144 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622154 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622164 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622168 */     GIR_RootConstrainSelectedInstOperands,
     /*  622169 */     // GIR_Coverage, 30680,
     /*  622169 */     GIR_EraseRootFromParent_Done,
     /*  622170 */   // Label 9662: @622170
     /*  622170 */   GIM_Try, /*On fail goto*//*Label 9663*/ GIMT_Encode4(622224), // Rule ID 30681 //
     /*  622175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  622178 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622198 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622208 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622222 */     GIR_RootConstrainSelectedInstOperands,
     /*  622223 */     // GIR_Coverage, 30681,
     /*  622223 */     GIR_EraseRootFromParent_Done,
     /*  622224 */   // Label 9663: @622224
     /*  622224 */   GIM_Try, /*On fail goto*//*Label 9664*/ GIMT_Encode4(622278), // Rule ID 30682 //
     /*  622229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  622232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622241 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622252 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622262 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622276 */     GIR_RootConstrainSelectedInstOperands,
     /*  622277 */     // GIR_Coverage, 30682,
     /*  622277 */     GIR_EraseRootFromParent_Done,
     /*  622278 */   // Label 9664: @622278
     /*  622278 */   GIM_Try, /*On fail goto*//*Label 9665*/ GIMT_Encode4(622332), // Rule ID 30683 //
     /*  622283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  622286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622306 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622316 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622330 */     GIR_RootConstrainSelectedInstOperands,
     /*  622331 */     // GIR_Coverage, 30683,
     /*  622331 */     GIR_EraseRootFromParent_Done,
     /*  622332 */   // Label 9665: @622332
     /*  622332 */   GIM_Try, /*On fail goto*//*Label 9666*/ GIMT_Encode4(622386), // Rule ID 30684 //
     /*  622337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  622340 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622360 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622370 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622384 */     GIR_RootConstrainSelectedInstOperands,
     /*  622385 */     // GIR_Coverage, 30684,
     /*  622385 */     GIR_EraseRootFromParent_Done,
     /*  622386 */   // Label 9666: @622386
     /*  622386 */   GIM_Try, /*On fail goto*//*Label 9667*/ GIMT_Encode4(622440), // Rule ID 30690 //
     /*  622391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  622394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622414 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_i64>>  =>  (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9),
     /*  622417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622424 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622438 */     GIR_RootConstrainSelectedInstOperands,
     /*  622439 */     // GIR_Coverage, 30690,
     /*  622439 */     GIR_EraseRootFromParent_Done,
     /*  622440 */   // Label 9667: @622440
     /*  622440 */   GIM_Try, /*On fail goto*//*Label 9668*/ GIMT_Encode4(622494), // Rule ID 30691 //
     /*  622445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  622448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622468 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_i64>>  =>  (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9),
     /*  622471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622478 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622492 */     GIR_RootConstrainSelectedInstOperands,
     /*  622493 */     // GIR_Coverage, 30691,
     /*  622493 */     GIR_EraseRootFromParent_Done,
     /*  622494 */   // Label 9668: @622494
     /*  622494 */   GIM_Try, /*On fail goto*//*Label 9669*/ GIMT_Encode4(622548), // Rule ID 30692 //
     /*  622499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  622502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622522 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_i64>>  =>  (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9),
     /*  622525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622532 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622546 */     GIR_RootConstrainSelectedInstOperands,
     /*  622547 */     // GIR_Coverage, 30692,
     /*  622547 */     GIR_EraseRootFromParent_Done,
     /*  622548 */   // Label 9669: @622548
     /*  622548 */   GIM_Try, /*On fail goto*//*Label 9670*/ GIMT_Encode4(622602), // Rule ID 30693 //
     /*  622553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  622556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622576 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_i64>>  =>  (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9),
     /*  622579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622586 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622600 */     GIR_RootConstrainSelectedInstOperands,
     /*  622601 */     // GIR_Coverage, 30693,
     /*  622601 */     GIR_EraseRootFromParent_Done,
     /*  622602 */   // Label 9670: @622602
     /*  622602 */   GIM_Try, /*On fail goto*//*Label 9671*/ GIMT_Encode4(622656), // Rule ID 30694 //
     /*  622607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  622610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  622615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622630 */     // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_i64>>  =>  (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  622630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9),
     /*  622633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622640 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  622650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622654 */     GIR_RootConstrainSelectedInstOperands,
     /*  622655 */     // GIR_Coverage, 30694,
     /*  622655 */     GIR_EraseRootFromParent_Done,
     /*  622656 */   // Label 9671: @622656
     /*  622656 */   GIM_Try, /*On fail goto*//*Label 9672*/ GIMT_Encode4(622710), // Rule ID 30700 //
     /*  622661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  622664 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622684 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622694 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622708 */     GIR_RootConstrainSelectedInstOperands,
     /*  622709 */     // GIR_Coverage, 30700,
     /*  622709 */     GIR_EraseRootFromParent_Done,
     /*  622710 */   // Label 9672: @622710
     /*  622710 */   GIM_Try, /*On fail goto*//*Label 9673*/ GIMT_Encode4(622764), // Rule ID 30701 //
     /*  622715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  622718 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622738 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622748 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622762 */     GIR_RootConstrainSelectedInstOperands,
     /*  622763 */     // GIR_Coverage, 30701,
     /*  622763 */     GIR_EraseRootFromParent_Done,
     /*  622764 */   // Label 9673: @622764
     /*  622764 */   GIM_Try, /*On fail goto*//*Label 9674*/ GIMT_Encode4(622818), // Rule ID 30702 //
     /*  622769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  622772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622792 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622802 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622812 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622816 */     GIR_RootConstrainSelectedInstOperands,
     /*  622817 */     // GIR_Coverage, 30702,
     /*  622817 */     GIR_EraseRootFromParent_Done,
     /*  622818 */   // Label 9674: @622818
     /*  622818 */   GIM_Try, /*On fail goto*//*Label 9675*/ GIMT_Encode4(622872), // Rule ID 30703 //
     /*  622823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  622826 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622846 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622856 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622870 */     GIR_RootConstrainSelectedInstOperands,
     /*  622871 */     // GIR_Coverage, 30703,
     /*  622871 */     GIR_EraseRootFromParent_Done,
     /*  622872 */   // Label 9675: @622872
     /*  622872 */   GIM_Try, /*On fail goto*//*Label 9676*/ GIMT_Encode4(622926), // Rule ID 30704 //
     /*  622877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  622880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  622885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  622889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  622900 */     // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_i64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  622900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
     /*  622903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  622905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  622910 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  622912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  622917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  622920 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622924 */     GIR_RootConstrainSelectedInstOperands,
     /*  622925 */     // GIR_Coverage, 30704,
     /*  622925 */     GIR_EraseRootFromParent_Done,
     /*  622926 */   // Label 9676: @622926
     /*  622926 */   GIM_Try, /*On fail goto*//*Label 9677*/ GIMT_Encode4(622985), // Rule ID 13185 //
     /*  622931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  622934 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  622941 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  622943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  622947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  622954 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  622954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR),
     /*  622957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  622962 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  622964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  622969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  622974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  622979 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  622983 */     GIR_RootConstrainSelectedInstOperands,
     /*  622984 */     // GIR_Coverage, 13185,
     /*  622984 */     GIR_EraseRootFromParent_Done,
     /*  622985 */   // Label 9677: @622985
     /*  622985 */   GIM_Try, /*On fail goto*//*Label 9678*/ GIMT_Encode4(623044), // Rule ID 13186 //
     /*  622990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  622993 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623000 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  623013 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR),
     /*  623016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623021 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623042 */     GIR_RootConstrainSelectedInstOperands,
     /*  623043 */     // GIR_Coverage, 13186,
     /*  623043 */     GIR_EraseRootFromParent_Done,
     /*  623044 */   // Label 9678: @623044
     /*  623044 */   GIM_Try, /*On fail goto*//*Label 9679*/ GIMT_Encode4(623103), // Rule ID 13187 //
     /*  623049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  623052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623059 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  623072 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR),
     /*  623075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623080 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623097 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623101 */     GIR_RootConstrainSelectedInstOperands,
     /*  623102 */     // GIR_Coverage, 13187,
     /*  623102 */     GIR_EraseRootFromParent_Done,
     /*  623103 */   // Label 9679: @623103
     /*  623103 */   GIM_Try, /*On fail goto*//*Label 9680*/ GIMT_Encode4(623162), // Rule ID 13188 //
     /*  623108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  623111 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623118 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  623131 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR),
     /*  623134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623139 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623160 */     GIR_RootConstrainSelectedInstOperands,
     /*  623161 */     // GIR_Coverage, 13188,
     /*  623161 */     GIR_EraseRootFromParent_Done,
     /*  623162 */   // Label 9680: @623162
     /*  623162 */   GIM_Try, /*On fail goto*//*Label 9681*/ GIMT_Encode4(623221), // Rule ID 13189 //
     /*  623167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  623170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623177 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  623190 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR),
     /*  623193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623198 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623215 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623219 */     GIR_RootConstrainSelectedInstOperands,
     /*  623220 */     // GIR_Coverage, 13189,
     /*  623220 */     GIR_EraseRootFromParent_Done,
     /*  623221 */   // Label 9681: @623221
     /*  623221 */   GIM_Try, /*On fail goto*//*Label 9682*/ GIMT_Encode4(623284), // Rule ID 13195 //
     /*  623226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  623229 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623244 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  623251 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN),
     /*  623254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623261 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623282 */     GIR_RootConstrainSelectedInstOperands,
     /*  623283 */     // GIR_Coverage, 13195,
     /*  623283 */     GIR_EraseRootFromParent_Done,
     /*  623284 */   // Label 9682: @623284
     /*  623284 */   GIM_Try, /*On fail goto*//*Label 9683*/ GIMT_Encode4(623347), // Rule ID 13196 //
     /*  623289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  623292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  623314 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN),
     /*  623317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623324 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623345 */     GIR_RootConstrainSelectedInstOperands,
     /*  623346 */     // GIR_Coverage, 13196,
     /*  623346 */     GIR_EraseRootFromParent_Done,
     /*  623347 */   // Label 9683: @623347
     /*  623347 */   GIM_Try, /*On fail goto*//*Label 9684*/ GIMT_Encode4(623410), // Rule ID 13197 //
     /*  623352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  623355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  623377 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN),
     /*  623380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623387 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623408 */     GIR_RootConstrainSelectedInstOperands,
     /*  623409 */     // GIR_Coverage, 13197,
     /*  623409 */     GIR_EraseRootFromParent_Done,
     /*  623410 */   // Label 9684: @623410
     /*  623410 */   GIM_Try, /*On fail goto*//*Label 9685*/ GIMT_Encode4(623473), // Rule ID 13198 //
     /*  623415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  623418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  623440 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN),
     /*  623443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623450 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623471 */     GIR_RootConstrainSelectedInstOperands,
     /*  623472 */     // GIR_Coverage, 13198,
     /*  623472 */     GIR_EraseRootFromParent_Done,
     /*  623473 */   // Label 9685: @623473
     /*  623473 */   GIM_Try, /*On fail goto*//*Label 9686*/ GIMT_Encode4(623536), // Rule ID 13199 //
     /*  623478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  623481 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623492 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  623503 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  623503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN),
     /*  623506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  623513 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  623520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  623525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  623530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623534 */     GIR_RootConstrainSelectedInstOperands,
     /*  623535 */     // GIR_Coverage, 13199,
     /*  623535 */     GIR_EraseRootFromParent_Done,
     /*  623536 */   // Label 9686: @623536
     /*  623536 */   GIM_Try, /*On fail goto*//*Label 9687*/ GIMT_Encode4(623588), // Rule ID 13180 //
     /*  623541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  623544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623551 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623564 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2),
     /*  623567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623572 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  623582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623586 */     GIR_RootConstrainSelectedInstOperands,
     /*  623587 */     // GIR_Coverage, 13180,
     /*  623587 */     GIR_EraseRootFromParent_Done,
     /*  623588 */   // Label 9687: @623588
     /*  623588 */   GIM_Try, /*On fail goto*//*Label 9688*/ GIMT_Encode4(623640), // Rule ID 13181 //
     /*  623593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  623596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623603 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623616 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2),
     /*  623619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623624 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  623634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623638 */     GIR_RootConstrainSelectedInstOperands,
     /*  623639 */     // GIR_Coverage, 13181,
     /*  623639 */     GIR_EraseRootFromParent_Done,
     /*  623640 */   // Label 9688: @623640
     /*  623640 */   GIM_Try, /*On fail goto*//*Label 9689*/ GIMT_Encode4(623692), // Rule ID 13182 //
     /*  623645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  623648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623655 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623668 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2),
     /*  623671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623676 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  623686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623690 */     GIR_RootConstrainSelectedInstOperands,
     /*  623691 */     // GIR_Coverage, 13182,
     /*  623691 */     GIR_EraseRootFromParent_Done,
     /*  623692 */   // Label 9689: @623692
     /*  623692 */   GIM_Try, /*On fail goto*//*Label 9690*/ GIMT_Encode4(623744), // Rule ID 13183 //
     /*  623697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  623700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623707 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623720 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2),
     /*  623723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623728 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  623738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623742 */     GIR_RootConstrainSelectedInstOperands,
     /*  623743 */     // GIR_Coverage, 13183,
     /*  623743 */     GIR_EraseRootFromParent_Done,
     /*  623744 */   // Label 9690: @623744
     /*  623744 */   GIM_Try, /*On fail goto*//*Label 9691*/ GIMT_Encode4(623796), // Rule ID 13184 //
     /*  623749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  623752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623759 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  623761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623772 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (GLOBAL_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2),
     /*  623775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623780 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  623790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623794 */     GIR_RootConstrainSelectedInstOperands,
     /*  623795 */     // GIR_Coverage, 13184,
     /*  623795 */     GIR_EraseRootFromParent_Done,
     /*  623796 */   // Label 9691: @623796
     /*  623796 */   GIM_Try, /*On fail goto*//*Label 9692*/ GIMT_Encode4(623852), // Rule ID 13190 //
     /*  623801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  623804 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623826 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN),
     /*  623829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623836 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  623846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623850 */     GIR_RootConstrainSelectedInstOperands,
     /*  623851 */     // GIR_Coverage, 13190,
     /*  623851 */     GIR_EraseRootFromParent_Done,
     /*  623852 */   // Label 9692: @623852
     /*  623852 */   GIM_Try, /*On fail goto*//*Label 9693*/ GIMT_Encode4(623908), // Rule ID 13191 //
     /*  623857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  623860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623882 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN),
     /*  623885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623892 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  623902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623906 */     GIR_RootConstrainSelectedInstOperands,
     /*  623907 */     // GIR_Coverage, 13191,
     /*  623907 */     GIR_EraseRootFromParent_Done,
     /*  623908 */   // Label 9693: @623908
     /*  623908 */   GIM_Try, /*On fail goto*//*Label 9694*/ GIMT_Encode4(623964), // Rule ID 13192 //
     /*  623913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  623916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623938 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN),
     /*  623941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  623948 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  623950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  623955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  623958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  623962 */     GIR_RootConstrainSelectedInstOperands,
     /*  623963 */     // GIR_Coverage, 13192,
     /*  623963 */     GIR_EraseRootFromParent_Done,
     /*  623964 */   // Label 9694: @623964
     /*  623964 */   GIM_Try, /*On fail goto*//*Label 9695*/ GIMT_Encode4(624020), // Rule ID 13193 //
     /*  623969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  623972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  623979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  623983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  623987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  623994 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  623994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN),
     /*  623997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  623999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  624004 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  624011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  624014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624018 */     GIR_RootConstrainSelectedInstOperands,
     /*  624019 */     // GIR_Coverage, 13193,
     /*  624019 */     GIR_EraseRootFromParent_Done,
     /*  624020 */   // Label 9695: @624020
     /*  624020 */   GIM_Try, /*On fail goto*//*Label 9696*/ GIMT_Encode4(624076), // Rule ID 13194 //
     /*  624025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  624028 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  624039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  624050 */     // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  624050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN),
     /*  624053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  624055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  624060 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  624067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  624070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624074 */     GIR_RootConstrainSelectedInstOperands,
     /*  624075 */     // GIR_Coverage, 13194,
     /*  624075 */     GIR_EraseRootFromParent_Done,
     /*  624076 */   // Label 9696: @624076
     /*  624076 */   GIM_Try, /*On fail goto*//*Label 9697*/ GIMT_Encode4(624136), // Rule ID 10777 //
     /*  624081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  624084 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624092 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624094 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624105 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624113 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624134 */     GIR_RootConstrainSelectedInstOperands,
     /*  624135 */     // GIR_Coverage, 10777,
     /*  624135 */     GIR_EraseRootFromParent_Done,
     /*  624136 */   // Label 9697: @624136
     /*  624136 */   GIM_Try, /*On fail goto*//*Label 9698*/ GIMT_Encode4(624196), // Rule ID 10778 //
     /*  624141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  624144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624152 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624165 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624173 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624194 */     GIR_RootConstrainSelectedInstOperands,
     /*  624195 */     // GIR_Coverage, 10778,
     /*  624195 */     GIR_EraseRootFromParent_Done,
     /*  624196 */   // Label 9698: @624196
     /*  624196 */   GIM_Try, /*On fail goto*//*Label 9699*/ GIMT_Encode4(624256), // Rule ID 10779 //
     /*  624201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  624204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624212 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624225 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624233 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624254 */     GIR_RootConstrainSelectedInstOperands,
     /*  624255 */     // GIR_Coverage, 10779,
     /*  624255 */     GIR_EraseRootFromParent_Done,
     /*  624256 */   // Label 9699: @624256
     /*  624256 */   GIM_Try, /*On fail goto*//*Label 9700*/ GIMT_Encode4(624316), // Rule ID 10780 //
     /*  624261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  624264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624272 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624285 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624293 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624310 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624314 */     GIR_RootConstrainSelectedInstOperands,
     /*  624315 */     // GIR_Coverage, 10780,
     /*  624315 */     GIR_EraseRootFromParent_Done,
     /*  624316 */   // Label 9700: @624316
     /*  624316 */   GIM_Try, /*On fail goto*//*Label 9701*/ GIMT_Encode4(624376), // Rule ID 10781 //
     /*  624321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  624324 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624332 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624345 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624353 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624374 */     GIR_RootConstrainSelectedInstOperands,
     /*  624375 */     // GIR_Coverage, 10781,
     /*  624375 */     GIR_EraseRootFromParent_Done,
     /*  624376 */   // Label 9701: @624376
     /*  624376 */   GIM_Try, /*On fail goto*//*Label 9702*/ GIMT_Encode4(624435), // Rule ID 11333 //
     /*  624381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  624384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624391 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624404 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624412 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624433 */     GIR_RootConstrainSelectedInstOperands,
     /*  624434 */     // GIR_Coverage, 11333,
     /*  624434 */     GIR_EraseRootFromParent_Done,
     /*  624435 */   // Label 9702: @624435
     /*  624435 */   GIM_Try, /*On fail goto*//*Label 9703*/ GIMT_Encode4(624494), // Rule ID 11334 //
     /*  624440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  624443 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624450 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624452 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624463 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624471 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624492 */     GIR_RootConstrainSelectedInstOperands,
     /*  624493 */     // GIR_Coverage, 11334,
     /*  624493 */     GIR_EraseRootFromParent_Done,
     /*  624494 */   // Label 9703: @624494
     /*  624494 */   GIM_Try, /*On fail goto*//*Label 9704*/ GIMT_Encode4(624553), // Rule ID 11335 //
     /*  624499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  624502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624509 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624522 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624530 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624551 */     GIR_RootConstrainSelectedInstOperands,
     /*  624552 */     // GIR_Coverage, 11335,
     /*  624552 */     GIR_EraseRootFromParent_Done,
     /*  624553 */   // Label 9704: @624553
     /*  624553 */   GIM_Try, /*On fail goto*//*Label 9705*/ GIMT_Encode4(624612), // Rule ID 11336 //
     /*  624558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  624561 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624568 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624581 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624589 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624610 */     GIR_RootConstrainSelectedInstOperands,
     /*  624611 */     // GIR_Coverage, 11336,
     /*  624611 */     GIR_EraseRootFromParent_Done,
     /*  624612 */   // Label 9705: @624612
     /*  624612 */   GIM_Try, /*On fail goto*//*Label 9706*/ GIMT_Encode4(624671), // Rule ID 11337 //
     /*  624617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  624620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624627 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  624629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  624640 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR),
     /*  624643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624648 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624669 */     GIR_RootConstrainSelectedInstOperands,
     /*  624670 */     // GIR_Coverage, 11337,
     /*  624670 */     GIR_EraseRootFromParent_Done,
     /*  624671 */   // Label 9706: @624671
     /*  624671 */   GIM_Try, /*On fail goto*//*Label 9707*/ GIMT_Encode4(624735), // Rule ID 10767 //
     /*  624676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  624679 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  624691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  624702 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  624705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  624707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624712 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624733 */     GIR_RootConstrainSelectedInstOperands,
     /*  624734 */     // GIR_Coverage, 10767,
     /*  624734 */     GIR_EraseRootFromParent_Done,
     /*  624735 */   // Label 9707: @624735
     /*  624735 */   GIM_Try, /*On fail goto*//*Label 9708*/ GIMT_Encode4(624799), // Rule ID 10768 //
     /*  624740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  624743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  624755 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  624766 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  624769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  624771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624776 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624793 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624797 */     GIR_RootConstrainSelectedInstOperands,
     /*  624798 */     // GIR_Coverage, 10768,
     /*  624798 */     GIR_EraseRootFromParent_Done,
     /*  624799 */   // Label 9708: @624799
     /*  624799 */   GIM_Try, /*On fail goto*//*Label 9709*/ GIMT_Encode4(624863), // Rule ID 10769 //
     /*  624804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  624807 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  624819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  624830 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  624833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  624835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624840 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624861 */     GIR_RootConstrainSelectedInstOperands,
     /*  624862 */     // GIR_Coverage, 10769,
     /*  624862 */     GIR_EraseRootFromParent_Done,
     /*  624863 */   // Label 9709: @624863
     /*  624863 */   GIM_Try, /*On fail goto*//*Label 9710*/ GIMT_Encode4(624927), // Rule ID 10770 //
     /*  624868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  624871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  624883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  624894 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  624897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  624899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624904 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624925 */     GIR_RootConstrainSelectedInstOperands,
     /*  624926 */     // GIR_Coverage, 10770,
     /*  624926 */     GIR_EraseRootFromParent_Done,
     /*  624927 */   // Label 9710: @624927
     /*  624927 */   GIM_Try, /*On fail goto*//*Label 9711*/ GIMT_Encode4(624991), // Rule ID 10771 //
     /*  624932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  624935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  624943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  624947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  624951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  624958 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  624958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  624961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  624963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  624968 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  624970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  624975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  624980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  624985 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  624989 */     GIR_RootConstrainSelectedInstOperands,
     /*  624990 */     // GIR_Coverage, 10771,
     /*  624990 */     GIR_EraseRootFromParent_Done,
     /*  624991 */   // Label 9711: @624991
     /*  624991 */   GIM_Try, /*On fail goto*//*Label 9712*/ GIMT_Encode4(625054), // Rule ID 11323 //
     /*  624996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  624999 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625010 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625014 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  625021 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  625021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  625024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  625031 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  625038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  625043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  625048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625052 */     GIR_RootConstrainSelectedInstOperands,
     /*  625053 */     // GIR_Coverage, 11323,
     /*  625053 */     GIR_EraseRootFromParent_Done,
     /*  625054 */   // Label 9712: @625054
     /*  625054 */   GIM_Try, /*On fail goto*//*Label 9713*/ GIMT_Encode4(625117), // Rule ID 11324 //
     /*  625059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  625062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  625084 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  625084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  625087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  625094 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  625101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  625106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  625111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625115 */     GIR_RootConstrainSelectedInstOperands,
     /*  625116 */     // GIR_Coverage, 11324,
     /*  625116 */     GIR_EraseRootFromParent_Done,
     /*  625117 */   // Label 9713: @625117
     /*  625117 */   GIM_Try, /*On fail goto*//*Label 9714*/ GIMT_Encode4(625180), // Rule ID 11325 //
     /*  625122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  625125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  625147 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  625147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  625150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  625157 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  625164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  625169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  625174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625178 */     GIR_RootConstrainSelectedInstOperands,
     /*  625179 */     // GIR_Coverage, 11325,
     /*  625179 */     GIR_EraseRootFromParent_Done,
     /*  625180 */   // Label 9714: @625180
     /*  625180 */   GIM_Try, /*On fail goto*//*Label 9715*/ GIMT_Encode4(625243), // Rule ID 11326 //
     /*  625185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  625188 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  625210 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  625210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  625213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  625220 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  625227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  625232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  625237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625241 */     GIR_RootConstrainSelectedInstOperands,
     /*  625242 */     // GIR_Coverage, 11326,
     /*  625242 */     GIR_EraseRootFromParent_Done,
     /*  625243 */   // Label 9715: @625243
     /*  625243 */   GIM_Try, /*On fail goto*//*Label 9716*/ GIMT_Encode4(625306), // Rule ID 11327 //
     /*  625248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  625251 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625266 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  625273 */     // (atomic_load_and:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  625273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_SADDR_RTN),
     /*  625276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  625283 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  625290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  625295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  625300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625304 */     GIR_RootConstrainSelectedInstOperands,
     /*  625305 */     // GIR_Coverage, 11327,
     /*  625305 */     GIR_EraseRootFromParent_Done,
     /*  625306 */   // Label 9716: @625306
     /*  625306 */   GIM_Try, /*On fail goto*//*Label 9717*/ GIMT_Encode4(625359), // Rule ID 10772 //
     /*  625311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  625314 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625322 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625335 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625343 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625353 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625357 */     GIR_RootConstrainSelectedInstOperands,
     /*  625358 */     // GIR_Coverage, 10772,
     /*  625358 */     GIR_EraseRootFromParent_Done,
     /*  625359 */   // Label 9717: @625359
     /*  625359 */   GIM_Try, /*On fail goto*//*Label 9718*/ GIMT_Encode4(625412), // Rule ID 10773 //
     /*  625364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  625367 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625375 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625388 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625396 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625406 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625410 */     GIR_RootConstrainSelectedInstOperands,
     /*  625411 */     // GIR_Coverage, 10773,
     /*  625411 */     GIR_EraseRootFromParent_Done,
     /*  625412 */   // Label 9718: @625412
     /*  625412 */   GIM_Try, /*On fail goto*//*Label 9719*/ GIMT_Encode4(625465), // Rule ID 10774 //
     /*  625417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  625420 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625428 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625434 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625441 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625449 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625463 */     GIR_RootConstrainSelectedInstOperands,
     /*  625464 */     // GIR_Coverage, 10774,
     /*  625464 */     GIR_EraseRootFromParent_Done,
     /*  625465 */   // Label 9719: @625465
     /*  625465 */   GIM_Try, /*On fail goto*//*Label 9720*/ GIMT_Encode4(625518), // Rule ID 10775 //
     /*  625470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  625473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625481 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625494 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625502 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625512 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625516 */     GIR_RootConstrainSelectedInstOperands,
     /*  625517 */     // GIR_Coverage, 10775,
     /*  625517 */     GIR_EraseRootFromParent_Done,
     /*  625518 */   // Label 9720: @625518
     /*  625518 */   GIM_Try, /*On fail goto*//*Label 9721*/ GIMT_Encode4(625571), // Rule ID 10776 //
     /*  625523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  625526 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625534 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625547 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625555 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625569 */     GIR_RootConstrainSelectedInstOperands,
     /*  625570 */     // GIR_Coverage, 10776,
     /*  625570 */     GIR_EraseRootFromParent_Done,
     /*  625571 */   // Label 9721: @625571
     /*  625571 */   GIM_Try, /*On fail goto*//*Label 9722*/ GIMT_Encode4(625623), // Rule ID 11328 //
     /*  625576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  625579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625586 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625599 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625607 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625621 */     GIR_RootConstrainSelectedInstOperands,
     /*  625622 */     // GIR_Coverage, 11328,
     /*  625622 */     GIR_EraseRootFromParent_Done,
     /*  625623 */   // Label 9722: @625623
     /*  625623 */   GIM_Try, /*On fail goto*//*Label 9723*/ GIMT_Encode4(625675), // Rule ID 11329 //
     /*  625628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  625631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625638 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625640 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625651 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625659 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625669 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625673 */     GIR_RootConstrainSelectedInstOperands,
     /*  625674 */     // GIR_Coverage, 11329,
     /*  625674 */     GIR_EraseRootFromParent_Done,
     /*  625675 */   // Label 9723: @625675
     /*  625675 */   GIM_Try, /*On fail goto*//*Label 9724*/ GIMT_Encode4(625727), // Rule ID 11330 //
     /*  625680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  625683 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625690 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625692 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625703 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625711 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625725 */     GIR_RootConstrainSelectedInstOperands,
     /*  625726 */     // GIR_Coverage, 11330,
     /*  625726 */     GIR_EraseRootFromParent_Done,
     /*  625727 */   // Label 9724: @625727
     /*  625727 */   GIM_Try, /*On fail goto*//*Label 9725*/ GIMT_Encode4(625779), // Rule ID 11331 //
     /*  625732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  625735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625742 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625755 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625763 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625773 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625777 */     GIR_RootConstrainSelectedInstOperands,
     /*  625778 */     // GIR_Coverage, 11331,
     /*  625778 */     GIR_EraseRootFromParent_Done,
     /*  625779 */   // Label 9725: @625779
     /*  625779 */   GIM_Try, /*On fail goto*//*Label 9726*/ GIMT_Encode4(625831), // Rule ID 11332 //
     /*  625784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  625787 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625794 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  625796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625807 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
     /*  625810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625815 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  625825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625829 */     GIR_RootConstrainSelectedInstOperands,
     /*  625830 */     // GIR_Coverage, 11332,
     /*  625830 */     GIR_EraseRootFromParent_Done,
     /*  625831 */   // Label 9726: @625831
     /*  625831 */   GIM_Try, /*On fail goto*//*Label 9727*/ GIMT_Encode4(625888), // Rule ID 10762 //
     /*  625836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  625839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625862 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  625865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625872 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  625882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625886 */     GIR_RootConstrainSelectedInstOperands,
     /*  625887 */     // GIR_Coverage, 10762,
     /*  625887 */     GIR_EraseRootFromParent_Done,
     /*  625888 */   // Label 9727: @625888
     /*  625888 */   GIM_Try, /*On fail goto*//*Label 9728*/ GIMT_Encode4(625945), // Rule ID 10763 //
     /*  625893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  625896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625919 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  625922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625929 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  625939 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  625943 */     GIR_RootConstrainSelectedInstOperands,
     /*  625944 */     // GIR_Coverage, 10763,
     /*  625944 */     GIR_EraseRootFromParent_Done,
     /*  625945 */   // Label 9728: @625945
     /*  625945 */   GIM_Try, /*On fail goto*//*Label 9729*/ GIMT_Encode4(626002), // Rule ID 10764 //
     /*  625950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  625953 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  625961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  625965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  625969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  625976 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  625976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  625979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  625981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  625986 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  625988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  625993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  625996 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626000 */     GIR_RootConstrainSelectedInstOperands,
     /*  626001 */     // GIR_Coverage, 10764,
     /*  626001 */     GIR_EraseRootFromParent_Done,
     /*  626002 */   // Label 9729: @626002
     /*  626002 */   GIM_Try, /*On fail goto*//*Label 9730*/ GIMT_Encode4(626059), // Rule ID 10765 //
     /*  626007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  626010 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626026 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626033 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626043 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626057 */     GIR_RootConstrainSelectedInstOperands,
     /*  626058 */     // GIR_Coverage, 10765,
     /*  626058 */     GIR_EraseRootFromParent_Done,
     /*  626059 */   // Label 9730: @626059
     /*  626059 */   GIM_Try, /*On fail goto*//*Label 9731*/ GIMT_Encode4(626116), // Rule ID 10766 //
     /*  626064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  626067 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626090 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626100 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626114 */     GIR_RootConstrainSelectedInstOperands,
     /*  626115 */     // GIR_Coverage, 10766,
     /*  626115 */     GIR_EraseRootFromParent_Done,
     /*  626116 */   // Label 9731: @626116
     /*  626116 */   GIM_Try, /*On fail goto*//*Label 9732*/ GIMT_Encode4(626172), // Rule ID 11318 //
     /*  626121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  626124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626146 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626156 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626170 */     GIR_RootConstrainSelectedInstOperands,
     /*  626171 */     // GIR_Coverage, 11318,
     /*  626171 */     GIR_EraseRootFromParent_Done,
     /*  626172 */   // Label 9732: @626172
     /*  626172 */   GIM_Try, /*On fail goto*//*Label 9733*/ GIMT_Encode4(626228), // Rule ID 11319 //
     /*  626177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  626180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626202 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626212 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626226 */     GIR_RootConstrainSelectedInstOperands,
     /*  626227 */     // GIR_Coverage, 11319,
     /*  626227 */     GIR_EraseRootFromParent_Done,
     /*  626228 */   // Label 9733: @626228
     /*  626228 */   GIM_Try, /*On fail goto*//*Label 9734*/ GIMT_Encode4(626284), // Rule ID 11320 //
     /*  626233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  626236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626258 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626268 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626282 */     GIR_RootConstrainSelectedInstOperands,
     /*  626283 */     // GIR_Coverage, 11320,
     /*  626283 */     GIR_EraseRootFromParent_Done,
     /*  626284 */   // Label 9734: @626284
     /*  626284 */   GIM_Try, /*On fail goto*//*Label 9735*/ GIMT_Encode4(626340), // Rule ID 11321 //
     /*  626289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  626292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626314 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626324 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626338 */     GIR_RootConstrainSelectedInstOperands,
     /*  626339 */     // GIR_Coverage, 11321,
     /*  626339 */     GIR_EraseRootFromParent_Done,
     /*  626340 */   // Label 9735: @626340
     /*  626340 */   GIM_Try, /*On fail goto*//*Label 9736*/ GIMT_Encode4(626396), // Rule ID 11322 //
     /*  626345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  626348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  626359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626363 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  626370 */     // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  626370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
     /*  626373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  626375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  626380 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  626382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  626387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  626390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626394 */     GIR_RootConstrainSelectedInstOperands,
     /*  626395 */     // GIR_Coverage, 11322,
     /*  626395 */     GIR_EraseRootFromParent_Done,
     /*  626396 */   // Label 9736: @626396
     /*  626396 */   GIM_Reject,
     /*  626397 */ // Label 9606: @626397
     /*  626397 */ GIM_Reject,
     /*  626398 */ // Label 9498: @626398
     /*  626398 */ GIM_Reject,
     /*  626399 */ // Label 23: @626399
     /*  626399 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 9739*/ GIMT_Encode4(640010),
     /*  626410 */ /*GILLT_s32*//*Label 9737*/ GIMT_Encode4(626418),
     /*  626414 */ /*GILLT_s64*//*Label 9738*/ GIMT_Encode4(632510),
     /*  626418 */ // Label 9737: @626418
     /*  626418 */ GIM_Try, /*On fail goto*//*Label 9740*/ GIMT_Encode4(632509),
     /*  626423 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  626426 */   GIM_Try, /*On fail goto*//*Label 9741*/ GIMT_Encode4(626488), // Rule ID 21058 //
     /*  626431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  626434 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626441 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626443 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626447 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626454 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64),
     /*  626457 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626482 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626486 */     GIR_RootConstrainSelectedInstOperands,
     /*  626487 */     // GIR_Coverage, 21058,
     /*  626487 */     GIR_EraseRootFromParent_Done,
     /*  626488 */   // Label 9741: @626488
     /*  626488 */   GIM_Try, /*On fail goto*//*Label 9742*/ GIMT_Encode4(626550), // Rule ID 21059 //
     /*  626493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  626496 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626503 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626505 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626509 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626516 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64),
     /*  626519 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626548 */     GIR_RootConstrainSelectedInstOperands,
     /*  626549 */     // GIR_Coverage, 21059,
     /*  626549 */     GIR_EraseRootFromParent_Done,
     /*  626550 */   // Label 9742: @626550
     /*  626550 */   GIM_Try, /*On fail goto*//*Label 9743*/ GIMT_Encode4(626612), // Rule ID 21060 //
     /*  626555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  626558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626565 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626578 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64),
     /*  626581 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626610 */     GIR_RootConstrainSelectedInstOperands,
     /*  626611 */     // GIR_Coverage, 21060,
     /*  626611 */     GIR_EraseRootFromParent_Done,
     /*  626612 */   // Label 9743: @626612
     /*  626612 */   GIM_Try, /*On fail goto*//*Label 9744*/ GIMT_Encode4(626674), // Rule ID 21061 //
     /*  626617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  626620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626627 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626640 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64),
     /*  626643 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626668 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626672 */     GIR_RootConstrainSelectedInstOperands,
     /*  626673 */     // GIR_Coverage, 21061,
     /*  626673 */     GIR_EraseRootFromParent_Done,
     /*  626674 */   // Label 9744: @626674
     /*  626674 */   GIM_Try, /*On fail goto*//*Label 9745*/ GIMT_Encode4(626736), // Rule ID 21062 //
     /*  626679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  626682 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626689 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626702 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64),
     /*  626705 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626734 */     GIR_RootConstrainSelectedInstOperands,
     /*  626735 */     // GIR_Coverage, 21062,
     /*  626735 */     GIR_EraseRootFromParent_Done,
     /*  626736 */   // Label 9745: @626736
     /*  626736 */   GIM_Try, /*On fail goto*//*Label 9746*/ GIMT_Encode4(626798), // Rule ID 21078 //
     /*  626741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  626744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626751 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626764 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64),
     /*  626767 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626796 */     GIR_RootConstrainSelectedInstOperands,
     /*  626797 */     // GIR_Coverage, 21078,
     /*  626797 */     GIR_EraseRootFromParent_Done,
     /*  626798 */   // Label 9746: @626798
     /*  626798 */   GIM_Try, /*On fail goto*//*Label 9747*/ GIMT_Encode4(626860), // Rule ID 21079 //
     /*  626803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  626806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626813 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626826 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64),
     /*  626829 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626858 */     GIR_RootConstrainSelectedInstOperands,
     /*  626859 */     // GIR_Coverage, 21079,
     /*  626859 */     GIR_EraseRootFromParent_Done,
     /*  626860 */   // Label 9747: @626860
     /*  626860 */   GIM_Try, /*On fail goto*//*Label 9748*/ GIMT_Encode4(626922), // Rule ID 21080 //
     /*  626865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  626868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626875 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626888 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64),
     /*  626891 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626920 */     GIR_RootConstrainSelectedInstOperands,
     /*  626921 */     // GIR_Coverage, 21080,
     /*  626921 */     GIR_EraseRootFromParent_Done,
     /*  626922 */   // Label 9748: @626922
     /*  626922 */   GIM_Try, /*On fail goto*//*Label 9749*/ GIMT_Encode4(626984), // Rule ID 21081 //
     /*  626927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  626930 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626937 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  626939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  626943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  626950 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  626950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64),
     /*  626953 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  626955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  626960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  626965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  626970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  626975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  626978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  626982 */     GIR_RootConstrainSelectedInstOperands,
     /*  626983 */     // GIR_Coverage, 21081,
     /*  626983 */     GIR_EraseRootFromParent_Done,
     /*  626984 */   // Label 9749: @626984
     /*  626984 */   GIM_Try, /*On fail goto*//*Label 9750*/ GIMT_Encode4(627046), // Rule ID 21082 //
     /*  626989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  626992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  626999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  627001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627012 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64),
     /*  627015 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  627040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627044 */     GIR_RootConstrainSelectedInstOperands,
     /*  627045 */     // GIR_Coverage, 21082,
     /*  627045 */     GIR_EraseRootFromParent_Done,
     /*  627046 */   // Label 9750: @627046
     /*  627046 */   GIM_Try, /*On fail goto*//*Label 9751*/ GIMT_Encode4(627112), // Rule ID 21048 //
     /*  627051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  627054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627076 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN),
     /*  627079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627081 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627110 */     GIR_RootConstrainSelectedInstOperands,
     /*  627111 */     // GIR_Coverage, 21048,
     /*  627111 */     GIR_EraseRootFromParent_Done,
     /*  627112 */   // Label 9751: @627112
     /*  627112 */   GIM_Try, /*On fail goto*//*Label 9752*/ GIMT_Encode4(627178), // Rule ID 21049 //
     /*  627117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  627120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627142 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN),
     /*  627145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627147 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627176 */     GIR_RootConstrainSelectedInstOperands,
     /*  627177 */     // GIR_Coverage, 21049,
     /*  627177 */     GIR_EraseRootFromParent_Done,
     /*  627178 */   // Label 9752: @627178
     /*  627178 */   GIM_Try, /*On fail goto*//*Label 9753*/ GIMT_Encode4(627244), // Rule ID 21050 //
     /*  627183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  627186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627197 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627208 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN),
     /*  627211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627213 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627242 */     GIR_RootConstrainSelectedInstOperands,
     /*  627243 */     // GIR_Coverage, 21050,
     /*  627243 */     GIR_EraseRootFromParent_Done,
     /*  627244 */   // Label 9753: @627244
     /*  627244 */   GIM_Try, /*On fail goto*//*Label 9754*/ GIMT_Encode4(627310), // Rule ID 21051 //
     /*  627249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  627252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627274 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN),
     /*  627277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627279 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627308 */     GIR_RootConstrainSelectedInstOperands,
     /*  627309 */     // GIR_Coverage, 21051,
     /*  627309 */     GIR_EraseRootFromParent_Done,
     /*  627310 */   // Label 9754: @627310
     /*  627310 */   GIM_Try, /*On fail goto*//*Label 9755*/ GIMT_Encode4(627376), // Rule ID 21052 //
     /*  627315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  627318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627340 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN),
     /*  627343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627345 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627374 */     GIR_RootConstrainSelectedInstOperands,
     /*  627375 */     // GIR_Coverage, 21052,
     /*  627375 */     GIR_EraseRootFromParent_Done,
     /*  627376 */   // Label 9755: @627376
     /*  627376 */   GIM_Try, /*On fail goto*//*Label 9756*/ GIMT_Encode4(627442), // Rule ID 21068 //
     /*  627381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  627384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627406 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN),
     /*  627409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627411 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627436 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627440 */     GIR_RootConstrainSelectedInstOperands,
     /*  627441 */     // GIR_Coverage, 21068,
     /*  627441 */     GIR_EraseRootFromParent_Done,
     /*  627442 */   // Label 9756: @627442
     /*  627442 */   GIM_Try, /*On fail goto*//*Label 9757*/ GIMT_Encode4(627508), // Rule ID 21069 //
     /*  627447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  627450 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627472 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN),
     /*  627475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627477 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627506 */     GIR_RootConstrainSelectedInstOperands,
     /*  627507 */     // GIR_Coverage, 21069,
     /*  627507 */     GIR_EraseRootFromParent_Done,
     /*  627508 */   // Label 9757: @627508
     /*  627508 */   GIM_Try, /*On fail goto*//*Label 9758*/ GIMT_Encode4(627574), // Rule ID 21070 //
     /*  627513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  627516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627538 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN),
     /*  627541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627543 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627572 */     GIR_RootConstrainSelectedInstOperands,
     /*  627573 */     // GIR_Coverage, 21070,
     /*  627573 */     GIR_EraseRootFromParent_Done,
     /*  627574 */   // Label 9758: @627574
     /*  627574 */   GIM_Try, /*On fail goto*//*Label 9759*/ GIMT_Encode4(627640), // Rule ID 21071 //
     /*  627579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  627582 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627593 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627604 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN),
     /*  627607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627609 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627638 */     GIR_RootConstrainSelectedInstOperands,
     /*  627639 */     // GIR_Coverage, 21071,
     /*  627639 */     GIR_EraseRootFromParent_Done,
     /*  627640 */   // Label 9759: @627640
     /*  627640 */   GIM_Try, /*On fail goto*//*Label 9760*/ GIMT_Encode4(627706), // Rule ID 21072 //
     /*  627645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  627648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  627659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  627670 */     // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN),
     /*  627673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  627675 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  627682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  627692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  627697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  627700 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627704 */     GIR_RootConstrainSelectedInstOperands,
     /*  627705 */     // GIR_Coverage, 21072,
     /*  627705 */     GIR_EraseRootFromParent_Done,
     /*  627706 */   // Label 9760: @627706
     /*  627706 */   GIM_Try, /*On fail goto*//*Label 9761*/ GIMT_Encode4(627763), // Rule ID 21053 //
     /*  627711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  627714 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627721 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  627723 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  627734 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
     /*  627737 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  627749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  627754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  627757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627761 */     GIR_RootConstrainSelectedInstOperands,
     /*  627762 */     // GIR_Coverage, 21053,
     /*  627762 */     GIR_EraseRootFromParent_Done,
     /*  627763 */   // Label 9761: @627763
     /*  627763 */   GIM_Try, /*On fail goto*//*Label 9762*/ GIMT_Encode4(627820), // Rule ID 21054 //
     /*  627768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  627771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627778 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  627780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627784 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  627791 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
     /*  627794 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  627806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  627811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  627814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627818 */     GIR_RootConstrainSelectedInstOperands,
     /*  627819 */     // GIR_Coverage, 21054,
     /*  627819 */     GIR_EraseRootFromParent_Done,
     /*  627820 */   // Label 9762: @627820
     /*  627820 */   GIM_Try, /*On fail goto*//*Label 9763*/ GIMT_Encode4(627877), // Rule ID 21055 //
     /*  627825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  627828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  627837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  627848 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
     /*  627851 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  627863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  627868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  627871 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627875 */     GIR_RootConstrainSelectedInstOperands,
     /*  627876 */     // GIR_Coverage, 21055,
     /*  627876 */     GIR_EraseRootFromParent_Done,
     /*  627877 */   // Label 9763: @627877
     /*  627877 */   GIM_Try, /*On fail goto*//*Label 9764*/ GIMT_Encode4(627934), // Rule ID 21056 //
     /*  627882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  627885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627892 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  627894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  627905 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
     /*  627908 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  627920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  627925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  627928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627932 */     GIR_RootConstrainSelectedInstOperands,
     /*  627933 */     // GIR_Coverage, 21056,
     /*  627933 */     GIR_EraseRootFromParent_Done,
     /*  627934 */   // Label 9764: @627934
     /*  627934 */   GIM_Try, /*On fail goto*//*Label 9765*/ GIMT_Encode4(627991), // Rule ID 21057 //
     /*  627939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  627942 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  627949 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  627951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  627955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  627962 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  627962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
     /*  627965 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  627967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  627972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  627977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  627982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  627985 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  627989 */     GIR_RootConstrainSelectedInstOperands,
     /*  627990 */     // GIR_Coverage, 21057,
     /*  627990 */     GIR_EraseRootFromParent_Done,
     /*  627991 */   // Label 9765: @627991
     /*  627991 */   GIM_Try, /*On fail goto*//*Label 9766*/ GIMT_Encode4(628048), // Rule ID 21073 //
     /*  627996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  627999 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628006 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628019 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
     /*  628022 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628046 */     GIR_RootConstrainSelectedInstOperands,
     /*  628047 */     // GIR_Coverage, 21073,
     /*  628047 */     GIR_EraseRootFromParent_Done,
     /*  628048 */   // Label 9766: @628048
     /*  628048 */   GIM_Try, /*On fail goto*//*Label 9767*/ GIMT_Encode4(628105), // Rule ID 21074 //
     /*  628053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  628056 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628063 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628076 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
     /*  628079 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628103 */     GIR_RootConstrainSelectedInstOperands,
     /*  628104 */     // GIR_Coverage, 21074,
     /*  628104 */     GIR_EraseRootFromParent_Done,
     /*  628105 */   // Label 9767: @628105
     /*  628105 */   GIM_Try, /*On fail goto*//*Label 9768*/ GIMT_Encode4(628162), // Rule ID 21075 //
     /*  628110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  628113 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628120 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628133 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
     /*  628136 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628160 */     GIR_RootConstrainSelectedInstOperands,
     /*  628161 */     // GIR_Coverage, 21075,
     /*  628161 */     GIR_EraseRootFromParent_Done,
     /*  628162 */   // Label 9768: @628162
     /*  628162 */   GIM_Try, /*On fail goto*//*Label 9769*/ GIMT_Encode4(628219), // Rule ID 21076 //
     /*  628167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  628170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628177 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628190 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
     /*  628193 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628213 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628217 */     GIR_RootConstrainSelectedInstOperands,
     /*  628218 */     // GIR_Coverage, 21076,
     /*  628218 */     GIR_EraseRootFromParent_Done,
     /*  628219 */   // Label 9769: @628219
     /*  628219 */   GIM_Try, /*On fail goto*//*Label 9770*/ GIMT_Encode4(628276), // Rule ID 21077 //
     /*  628224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  628227 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628234 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628236 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628240 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628247 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
     /*  628250 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628274 */     GIR_RootConstrainSelectedInstOperands,
     /*  628275 */     // GIR_Coverage, 21077,
     /*  628275 */     GIR_EraseRootFromParent_Done,
     /*  628276 */   // Label 9770: @628276
     /*  628276 */   GIM_Try, /*On fail goto*//*Label 9771*/ GIMT_Encode4(628337), // Rule ID 21043 //
     /*  628281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  628284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628306 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
     /*  628309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628311 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628335 */     GIR_RootConstrainSelectedInstOperands,
     /*  628336 */     // GIR_Coverage, 21043,
     /*  628336 */     GIR_EraseRootFromParent_Done,
     /*  628337 */   // Label 9771: @628337
     /*  628337 */   GIM_Try, /*On fail goto*//*Label 9772*/ GIMT_Encode4(628398), // Rule ID 21044 //
     /*  628342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  628345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628367 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
     /*  628370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628372 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628396 */     GIR_RootConstrainSelectedInstOperands,
     /*  628397 */     // GIR_Coverage, 21044,
     /*  628397 */     GIR_EraseRootFromParent_Done,
     /*  628398 */   // Label 9772: @628398
     /*  628398 */   GIM_Try, /*On fail goto*//*Label 9773*/ GIMT_Encode4(628459), // Rule ID 21045 //
     /*  628403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  628406 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628428 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
     /*  628431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628433 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628457 */     GIR_RootConstrainSelectedInstOperands,
     /*  628458 */     // GIR_Coverage, 21045,
     /*  628458 */     GIR_EraseRootFromParent_Done,
     /*  628459 */   // Label 9773: @628459
     /*  628459 */   GIM_Try, /*On fail goto*//*Label 9774*/ GIMT_Encode4(628520), // Rule ID 21046 //
     /*  628464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  628467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628478 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628482 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628489 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
     /*  628492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628494 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628518 */     GIR_RootConstrainSelectedInstOperands,
     /*  628519 */     // GIR_Coverage, 21046,
     /*  628519 */     GIR_EraseRootFromParent_Done,
     /*  628520 */   // Label 9774: @628520
     /*  628520 */   GIM_Try, /*On fail goto*//*Label 9775*/ GIMT_Encode4(628581), // Rule ID 21047 //
     /*  628525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  628528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628550 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
     /*  628553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628555 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628579 */     GIR_RootConstrainSelectedInstOperands,
     /*  628580 */     // GIR_Coverage, 21047,
     /*  628580 */     GIR_EraseRootFromParent_Done,
     /*  628581 */   // Label 9775: @628581
     /*  628581 */   GIM_Try, /*On fail goto*//*Label 9776*/ GIMT_Encode4(628642), // Rule ID 21063 //
     /*  628586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  628589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628611 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
     /*  628614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628616 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628640 */     GIR_RootConstrainSelectedInstOperands,
     /*  628641 */     // GIR_Coverage, 21063,
     /*  628641 */     GIR_EraseRootFromParent_Done,
     /*  628642 */   // Label 9776: @628642
     /*  628642 */   GIM_Try, /*On fail goto*//*Label 9777*/ GIMT_Encode4(628703), // Rule ID 21064 //
     /*  628647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  628650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628672 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
     /*  628675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628677 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628701 */     GIR_RootConstrainSelectedInstOperands,
     /*  628702 */     // GIR_Coverage, 21064,
     /*  628702 */     GIR_EraseRootFromParent_Done,
     /*  628703 */   // Label 9777: @628703
     /*  628703 */   GIM_Try, /*On fail goto*//*Label 9778*/ GIMT_Encode4(628764), // Rule ID 21065 //
     /*  628708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  628711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628733 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
     /*  628736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628738 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628762 */     GIR_RootConstrainSelectedInstOperands,
     /*  628763 */     // GIR_Coverage, 21065,
     /*  628763 */     GIR_EraseRootFromParent_Done,
     /*  628764 */   // Label 9778: @628764
     /*  628764 */   GIM_Try, /*On fail goto*//*Label 9779*/ GIMT_Encode4(628825), // Rule ID 21066 //
     /*  628769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  628772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628794 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
     /*  628797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628799 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628823 */     GIR_RootConstrainSelectedInstOperands,
     /*  628824 */     // GIR_Coverage, 21066,
     /*  628824 */     GIR_EraseRootFromParent_Done,
     /*  628825 */   // Label 9779: @628825
     /*  628825 */   GIM_Try, /*On fail goto*//*Label 9780*/ GIMT_Encode4(628886), // Rule ID 21067 //
     /*  628830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  628833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  628840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  628844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  628855 */     // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  628855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
     /*  628858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  628860 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  628862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  628867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  628872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  628877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  628880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628884 */     GIR_RootConstrainSelectedInstOperands,
     /*  628885 */     // GIR_Coverage, 21067,
     /*  628885 */     GIR_EraseRootFromParent_Done,
     /*  628886 */   // Label 9780: @628886
     /*  628886 */   GIM_Try, /*On fail goto*//*Label 9781*/ GIMT_Encode4(628936), // Rule ID 30366 //
     /*  628891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  628894 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  628899 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  628912 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  628912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  628915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  628920 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  628922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  628927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628934 */     GIR_RootConstrainSelectedInstOperands,
     /*  628935 */     // GIR_Coverage, 30366,
     /*  628935 */     GIR_EraseRootFromParent_Done,
     /*  628936 */   // Label 9781: @628936
     /*  628936 */   GIM_Try, /*On fail goto*//*Label 9782*/ GIMT_Encode4(628986), // Rule ID 30367 //
     /*  628941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  628944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  628949 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  628951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  628955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  628962 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  628962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  628965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  628970 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  628972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  628977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  628980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  628984 */     GIR_RootConstrainSelectedInstOperands,
     /*  628985 */     // GIR_Coverage, 30367,
     /*  628985 */     GIR_EraseRootFromParent_Done,
     /*  628986 */   // Label 9782: @628986
     /*  628986 */   GIM_Try, /*On fail goto*//*Label 9783*/ GIMT_Encode4(629036), // Rule ID 30368 //
     /*  628991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  628994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  628999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629012 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629020 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629034 */     GIR_RootConstrainSelectedInstOperands,
     /*  629035 */     // GIR_Coverage, 30368,
     /*  629035 */     GIR_EraseRootFromParent_Done,
     /*  629036 */   // Label 9783: @629036
     /*  629036 */   GIM_Try, /*On fail goto*//*Label 9784*/ GIMT_Encode4(629086), // Rule ID 30369 //
     /*  629041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  629044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629049 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629062 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629070 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629084 */     GIR_RootConstrainSelectedInstOperands,
     /*  629085 */     // GIR_Coverage, 30369,
     /*  629085 */     GIR_EraseRootFromParent_Done,
     /*  629086 */   // Label 9784: @629086
     /*  629086 */   GIM_Try, /*On fail goto*//*Label 9785*/ GIMT_Encode4(629136), // Rule ID 30370 //
     /*  629091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  629094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629099 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629112 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629120 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629134 */     GIR_RootConstrainSelectedInstOperands,
     /*  629135 */     // GIR_Coverage, 30370,
     /*  629135 */     GIR_EraseRootFromParent_Done,
     /*  629136 */   // Label 9785: @629136
     /*  629136 */   GIM_Try, /*On fail goto*//*Label 9786*/ GIMT_Encode4(629186), // Rule ID 30372 //
     /*  629141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  629144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629149 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629162 */     // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_i32>>  =>  (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9),
     /*  629165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629170 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629184 */     GIR_RootConstrainSelectedInstOperands,
     /*  629185 */     // GIR_Coverage, 30372,
     /*  629185 */     GIR_EraseRootFromParent_Done,
     /*  629186 */   // Label 9786: @629186
     /*  629186 */   GIM_Try, /*On fail goto*//*Label 9787*/ GIMT_Encode4(629236), // Rule ID 30373 //
     /*  629191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  629194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629199 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629212 */     // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_i32>>  =>  (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9),
     /*  629215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629220 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629234 */     GIR_RootConstrainSelectedInstOperands,
     /*  629235 */     // GIR_Coverage, 30373,
     /*  629235 */     GIR_EraseRootFromParent_Done,
     /*  629236 */   // Label 9787: @629236
     /*  629236 */   GIM_Try, /*On fail goto*//*Label 9788*/ GIMT_Encode4(629286), // Rule ID 30374 //
     /*  629241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  629244 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629249 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629262 */     // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_i32>>  =>  (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9),
     /*  629265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629270 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629284 */     GIR_RootConstrainSelectedInstOperands,
     /*  629285 */     // GIR_Coverage, 30374,
     /*  629285 */     GIR_EraseRootFromParent_Done,
     /*  629286 */   // Label 9788: @629286
     /*  629286 */   GIM_Try, /*On fail goto*//*Label 9789*/ GIMT_Encode4(629336), // Rule ID 30375 //
     /*  629291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  629294 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629299 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629312 */     // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_i32>>  =>  (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9),
     /*  629315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629320 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629334 */     GIR_RootConstrainSelectedInstOperands,
     /*  629335 */     // GIR_Coverage, 30375,
     /*  629335 */     GIR_EraseRootFromParent_Done,
     /*  629336 */   // Label 9789: @629336
     /*  629336 */   GIM_Try, /*On fail goto*//*Label 9790*/ GIMT_Encode4(629386), // Rule ID 30376 //
     /*  629341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  629344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629349 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629351 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629362 */     // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_i32>>  =>  (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9),
     /*  629365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629370 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629384 */     GIR_RootConstrainSelectedInstOperands,
     /*  629385 */     // GIR_Coverage, 30376,
     /*  629385 */     GIR_EraseRootFromParent_Done,
     /*  629386 */   // Label 9790: @629386
     /*  629386 */   GIM_Try, /*On fail goto*//*Label 9791*/ GIMT_Encode4(629436), // Rule ID 30378 //
     /*  629391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  629394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  629399 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629412 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  629412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629420 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  629430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629434 */     GIR_RootConstrainSelectedInstOperands,
     /*  629435 */     // GIR_Coverage, 30378,
     /*  629435 */     GIR_EraseRootFromParent_Done,
     /*  629436 */   // Label 9791: @629436
     /*  629436 */   GIM_Try, /*On fail goto*//*Label 9792*/ GIMT_Encode4(629486), // Rule ID 30379 //
     /*  629441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  629444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  629449 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629462 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  629462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629470 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  629480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629484 */     GIR_RootConstrainSelectedInstOperands,
     /*  629485 */     // GIR_Coverage, 30379,
     /*  629485 */     GIR_EraseRootFromParent_Done,
     /*  629486 */   // Label 9792: @629486
     /*  629486 */   GIM_Try, /*On fail goto*//*Label 9793*/ GIMT_Encode4(629536), // Rule ID 30380 //
     /*  629491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  629494 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  629499 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629512 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  629512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629520 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  629530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629534 */     GIR_RootConstrainSelectedInstOperands,
     /*  629535 */     // GIR_Coverage, 30380,
     /*  629535 */     GIR_EraseRootFromParent_Done,
     /*  629536 */   // Label 9793: @629536
     /*  629536 */   GIM_Try, /*On fail goto*//*Label 9794*/ GIMT_Encode4(629586), // Rule ID 30381 //
     /*  629541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  629544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  629549 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629562 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  629562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629570 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  629580 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629584 */     GIR_RootConstrainSelectedInstOperands,
     /*  629585 */     // GIR_Coverage, 30381,
     /*  629585 */     GIR_EraseRootFromParent_Done,
     /*  629586 */   // Label 9794: @629586
     /*  629586 */   GIM_Try, /*On fail goto*//*Label 9795*/ GIMT_Encode4(629636), // Rule ID 30382 //
     /*  629591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  629594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  629599 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629601 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629612 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  629612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
     /*  629615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629620 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  629630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629634 */     GIR_RootConstrainSelectedInstOperands,
     /*  629635 */     // GIR_Coverage, 30382,
     /*  629635 */     GIR_EraseRootFromParent_Done,
     /*  629636 */   // Label 9795: @629636
     /*  629636 */   GIM_Try, /*On fail goto*//*Label 9796*/ GIMT_Encode4(629690), // Rule ID 30365 //
     /*  629641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  629644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  629653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629664 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_i32>>  =>  (DS_OR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32),
     /*  629667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  629669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629674 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629684 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629688 */     GIR_RootConstrainSelectedInstOperands,
     /*  629689 */     // GIR_Coverage, 30365,
     /*  629689 */     GIR_EraseRootFromParent_Done,
     /*  629690 */   // Label 9796: @629690
     /*  629690 */   GIM_Try, /*On fail goto*//*Label 9797*/ GIMT_Encode4(629744), // Rule ID 30371 //
     /*  629695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  629698 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  629703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  629707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629718 */     // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_i32>>  =>  (DS_OR_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  629718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32_gfx9),
     /*  629721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  629723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629728 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  629738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629742 */     GIR_RootConstrainSelectedInstOperands,
     /*  629743 */     // GIR_Coverage, 30371,
     /*  629743 */     GIR_EraseRootFromParent_Done,
     /*  629744 */   // Label 9797: @629744
     /*  629744 */   GIM_Try, /*On fail goto*//*Label 9798*/ GIMT_Encode4(629798), // Rule ID 30377 //
     /*  629749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  629752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  629757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  629761 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  629772 */     // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_i32>>  =>  (DS_OR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  629772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32),
     /*  629775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  629777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  629782 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  629784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  629789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  629792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629796 */     GIR_RootConstrainSelectedInstOperands,
     /*  629797 */     // GIR_Coverage, 30377,
     /*  629797 */     GIR_EraseRootFromParent_Done,
     /*  629798 */   // Label 9798: @629798
     /*  629798 */   GIM_Try, /*On fail goto*//*Label 9799*/ GIMT_Encode4(629857), // Rule ID 13025 //
     /*  629803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  629806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  629813 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  629826 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  629826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR),
     /*  629829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  629834 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  629836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  629841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  629846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  629851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629855 */     GIR_RootConstrainSelectedInstOperands,
     /*  629856 */     // GIR_Coverage, 13025,
     /*  629856 */     GIR_EraseRootFromParent_Done,
     /*  629857 */   // Label 9799: @629857
     /*  629857 */   GIM_Try, /*On fail goto*//*Label 9800*/ GIMT_Encode4(629916), // Rule ID 13026 //
     /*  629862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  629865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  629872 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  629885 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  629885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR),
     /*  629888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  629893 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  629895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  629900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  629905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  629910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629914 */     GIR_RootConstrainSelectedInstOperands,
     /*  629915 */     // GIR_Coverage, 13026,
     /*  629915 */     GIR_EraseRootFromParent_Done,
     /*  629916 */   // Label 9800: @629916
     /*  629916 */   GIM_Try, /*On fail goto*//*Label 9801*/ GIMT_Encode4(629975), // Rule ID 13027 //
     /*  629921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  629924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  629931 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  629944 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  629944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR),
     /*  629947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  629952 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  629954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  629959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  629964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  629969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  629973 */     GIR_RootConstrainSelectedInstOperands,
     /*  629974 */     // GIR_Coverage, 13027,
     /*  629974 */     GIR_EraseRootFromParent_Done,
     /*  629975 */   // Label 9801: @629975
     /*  629975 */   GIM_Try, /*On fail goto*//*Label 9802*/ GIMT_Encode4(630034), // Rule ID 13028 //
     /*  629980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  629983 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  629990 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  629992 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  629996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630003 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR),
     /*  630006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630011 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630032 */     GIR_RootConstrainSelectedInstOperands,
     /*  630033 */     // GIR_Coverage, 13028,
     /*  630033 */     GIR_EraseRootFromParent_Done,
     /*  630034 */   // Label 9802: @630034
     /*  630034 */   GIM_Try, /*On fail goto*//*Label 9803*/ GIMT_Encode4(630093), // Rule ID 13029 //
     /*  630039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  630042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630049 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630062 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR),
     /*  630065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630070 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630087 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630091 */     GIR_RootConstrainSelectedInstOperands,
     /*  630092 */     // GIR_Coverage, 13029,
     /*  630092 */     GIR_EraseRootFromParent_Done,
     /*  630093 */   // Label 9803: @630093
     /*  630093 */   GIM_Try, /*On fail goto*//*Label 9804*/ GIMT_Encode4(630156), // Rule ID 13035 //
     /*  630098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  630101 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  630112 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630116 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  630123 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (GLOBAL_ATOMIC_OR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN),
     /*  630126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  630128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630133 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630154 */     GIR_RootConstrainSelectedInstOperands,
     /*  630155 */     // GIR_Coverage, 13035,
     /*  630155 */     GIR_EraseRootFromParent_Done,
     /*  630156 */   // Label 9804: @630156
     /*  630156 */   GIM_Try, /*On fail goto*//*Label 9805*/ GIMT_Encode4(630208), // Rule ID 13020 //
     /*  630161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  630164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630171 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630184 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR),
     /*  630187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630192 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  630202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630206 */     GIR_RootConstrainSelectedInstOperands,
     /*  630207 */     // GIR_Coverage, 13020,
     /*  630207 */     GIR_EraseRootFromParent_Done,
     /*  630208 */   // Label 9805: @630208
     /*  630208 */   GIM_Try, /*On fail goto*//*Label 9806*/ GIMT_Encode4(630260), // Rule ID 13021 //
     /*  630213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  630216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630236 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR),
     /*  630239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630244 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  630254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630258 */     GIR_RootConstrainSelectedInstOperands,
     /*  630259 */     // GIR_Coverage, 13021,
     /*  630259 */     GIR_EraseRootFromParent_Done,
     /*  630260 */   // Label 9806: @630260
     /*  630260 */   GIM_Try, /*On fail goto*//*Label 9807*/ GIMT_Encode4(630312), // Rule ID 13022 //
     /*  630265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  630268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630275 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630288 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR),
     /*  630291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630296 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  630306 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630310 */     GIR_RootConstrainSelectedInstOperands,
     /*  630311 */     // GIR_Coverage, 13022,
     /*  630311 */     GIR_EraseRootFromParent_Done,
     /*  630312 */   // Label 9807: @630312
     /*  630312 */   GIM_Try, /*On fail goto*//*Label 9808*/ GIMT_Encode4(630364), // Rule ID 13023 //
     /*  630317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  630320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630327 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630340 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR),
     /*  630343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630348 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  630358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630362 */     GIR_RootConstrainSelectedInstOperands,
     /*  630363 */     // GIR_Coverage, 13023,
     /*  630363 */     GIR_EraseRootFromParent_Done,
     /*  630364 */   // Label 9808: @630364
     /*  630364 */   GIM_Try, /*On fail goto*//*Label 9809*/ GIMT_Encode4(630416), // Rule ID 13024 //
     /*  630369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  630372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630392 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (GLOBAL_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR),
     /*  630395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  630410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630414 */     GIR_RootConstrainSelectedInstOperands,
     /*  630415 */     // GIR_Coverage, 13024,
     /*  630415 */     GIR_EraseRootFromParent_Done,
     /*  630416 */   // Label 9809: @630416
     /*  630416 */   GIM_Try, /*On fail goto*//*Label 9810*/ GIMT_Encode4(630472), // Rule ID 13030 //
     /*  630421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  630424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  630435 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630446 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN),
     /*  630449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  630451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630456 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  630466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630470 */     GIR_RootConstrainSelectedInstOperands,
     /*  630471 */     // GIR_Coverage, 13030,
     /*  630471 */     GIR_EraseRootFromParent_Done,
     /*  630472 */   // Label 9810: @630472
     /*  630472 */   GIM_Try, /*On fail goto*//*Label 9811*/ GIMT_Encode4(630528), // Rule ID 13031 //
     /*  630477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  630480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  630491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630502 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN),
     /*  630505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  630507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630512 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  630522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630526 */     GIR_RootConstrainSelectedInstOperands,
     /*  630527 */     // GIR_Coverage, 13031,
     /*  630527 */     GIR_EraseRootFromParent_Done,
     /*  630528 */   // Label 9811: @630528
     /*  630528 */   GIM_Try, /*On fail goto*//*Label 9812*/ GIMT_Encode4(630584), // Rule ID 13032 //
     /*  630533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  630536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  630547 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630551 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630558 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN),
     /*  630561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  630563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630568 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  630578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630582 */     GIR_RootConstrainSelectedInstOperands,
     /*  630583 */     // GIR_Coverage, 13032,
     /*  630583 */     GIR_EraseRootFromParent_Done,
     /*  630584 */   // Label 9812: @630584
     /*  630584 */   GIM_Try, /*On fail goto*//*Label 9813*/ GIMT_Encode4(630640), // Rule ID 13033 //
     /*  630589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  630592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  630603 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630614 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN),
     /*  630617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  630619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630624 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  630634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630638 */     GIR_RootConstrainSelectedInstOperands,
     /*  630639 */     // GIR_Coverage, 13033,
     /*  630639 */     GIR_EraseRootFromParent_Done,
     /*  630640 */   // Label 9813: @630640
     /*  630640 */   GIM_Try, /*On fail goto*//*Label 9814*/ GIMT_Encode4(630696), // Rule ID 13034 //
     /*  630645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  630648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  630659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  630670 */     // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  630670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN),
     /*  630673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  630675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  630680 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  630687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  630690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630694 */     GIR_RootConstrainSelectedInstOperands,
     /*  630695 */     // GIR_Coverage, 13034,
     /*  630695 */     GIR_EraseRootFromParent_Done,
     /*  630696 */   // Label 9814: @630696
     /*  630696 */   GIM_Try, /*On fail goto*//*Label 9815*/ GIMT_Encode4(630756), // Rule ID 10625 //
     /*  630701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  630704 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630712 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630714 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630718 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630725 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  630728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630733 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630754 */     GIR_RootConstrainSelectedInstOperands,
     /*  630755 */     // GIR_Coverage, 10625,
     /*  630755 */     GIR_EraseRootFromParent_Done,
     /*  630756 */   // Label 9815: @630756
     /*  630756 */   GIM_Try, /*On fail goto*//*Label 9816*/ GIMT_Encode4(630816), // Rule ID 10626 //
     /*  630761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  630764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630772 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630785 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  630788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630793 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630814 */     GIR_RootConstrainSelectedInstOperands,
     /*  630815 */     // GIR_Coverage, 10626,
     /*  630815 */     GIR_EraseRootFromParent_Done,
     /*  630816 */   // Label 9816: @630816
     /*  630816 */   GIM_Try, /*On fail goto*//*Label 9817*/ GIMT_Encode4(630876), // Rule ID 10627 //
     /*  630821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  630824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630832 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630845 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  630848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630853 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630874 */     GIR_RootConstrainSelectedInstOperands,
     /*  630875 */     // GIR_Coverage, 10627,
     /*  630875 */     GIR_EraseRootFromParent_Done,
     /*  630876 */   // Label 9817: @630876
     /*  630876 */   GIM_Try, /*On fail goto*//*Label 9818*/ GIMT_Encode4(630936), // Rule ID 10628 //
     /*  630881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  630884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630892 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630905 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  630908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630913 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630934 */     GIR_RootConstrainSelectedInstOperands,
     /*  630935 */     // GIR_Coverage, 10628,
     /*  630935 */     GIR_EraseRootFromParent_Done,
     /*  630936 */   // Label 9818: @630936
     /*  630936 */   GIM_Try, /*On fail goto*//*Label 9819*/ GIMT_Encode4(630996), // Rule ID 10629 //
     /*  630941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  630944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  630952 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  630954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  630958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  630965 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  630965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  630968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  630973 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  630975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  630980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  630985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  630990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  630994 */     GIR_RootConstrainSelectedInstOperands,
     /*  630995 */     // GIR_Coverage, 10629,
     /*  630995 */     GIR_EraseRootFromParent_Done,
     /*  630996 */   // Label 9819: @630996
     /*  630996 */   GIM_Try, /*On fail goto*//*Label 9820*/ GIMT_Encode4(631055), // Rule ID 11181 //
     /*  631001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  631004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631011 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  631024 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  631027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631032 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631053 */     GIR_RootConstrainSelectedInstOperands,
     /*  631054 */     // GIR_Coverage, 11181,
     /*  631054 */     GIR_EraseRootFromParent_Done,
     /*  631055 */   // Label 9820: @631055
     /*  631055 */   GIM_Try, /*On fail goto*//*Label 9821*/ GIMT_Encode4(631114), // Rule ID 11182 //
     /*  631060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  631063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631070 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  631083 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  631086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631091 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631112 */     GIR_RootConstrainSelectedInstOperands,
     /*  631113 */     // GIR_Coverage, 11182,
     /*  631113 */     GIR_EraseRootFromParent_Done,
     /*  631114 */   // Label 9821: @631114
     /*  631114 */   GIM_Try, /*On fail goto*//*Label 9822*/ GIMT_Encode4(631173), // Rule ID 11183 //
     /*  631119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  631122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631129 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  631142 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  631145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631150 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631171 */     GIR_RootConstrainSelectedInstOperands,
     /*  631172 */     // GIR_Coverage, 11183,
     /*  631172 */     GIR_EraseRootFromParent_Done,
     /*  631173 */   // Label 9822: @631173
     /*  631173 */   GIM_Try, /*On fail goto*//*Label 9823*/ GIMT_Encode4(631232), // Rule ID 11184 //
     /*  631178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  631181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631188 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631190 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631194 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  631201 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  631204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631209 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631230 */     GIR_RootConstrainSelectedInstOperands,
     /*  631231 */     // GIR_Coverage, 11184,
     /*  631231 */     GIR_EraseRootFromParent_Done,
     /*  631232 */   // Label 9823: @631232
     /*  631232 */   GIM_Try, /*On fail goto*//*Label 9824*/ GIMT_Encode4(631291), // Rule ID 11185 //
     /*  631237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  631240 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631247 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631249 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631253 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  631260 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR),
     /*  631263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631268 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631285 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631289 */     GIR_RootConstrainSelectedInstOperands,
     /*  631290 */     // GIR_Coverage, 11185,
     /*  631290 */     GIR_EraseRootFromParent_Done,
     /*  631291 */   // Label 9824: @631291
     /*  631291 */   GIM_Try, /*On fail goto*//*Label 9825*/ GIMT_Encode4(631355), // Rule ID 10619 //
     /*  631296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  631299 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  631311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  631322 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>>  =>  (FLAT_ATOMIC_OR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR_RTN),
     /*  631325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  631327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631332 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631353 */     GIR_RootConstrainSelectedInstOperands,
     /*  631354 */     // GIR_Coverage, 10619,
     /*  631354 */     GIR_EraseRootFromParent_Done,
     /*  631355 */   // Label 9825: @631355
     /*  631355 */   GIM_Try, /*On fail goto*//*Label 9826*/ GIMT_Encode4(631418), // Rule ID 11175 //
     /*  631360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  631363 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  631374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  631385 */     // (atomic_load_or:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (FLAT_ATOMIC_OR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  631385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_SADDR_RTN),
     /*  631388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  631390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  631395 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  631402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  631407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  631412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631416 */     GIR_RootConstrainSelectedInstOperands,
     /*  631417 */     // GIR_Coverage, 11175,
     /*  631417 */     GIR_EraseRootFromParent_Done,
     /*  631418 */   // Label 9826: @631418
     /*  631418 */   GIM_Try, /*On fail goto*//*Label 9827*/ GIMT_Encode4(631471), // Rule ID 10620 //
     /*  631423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  631426 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631434 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631447 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631455 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631469 */     GIR_RootConstrainSelectedInstOperands,
     /*  631470 */     // GIR_Coverage, 10620,
     /*  631470 */     GIR_EraseRootFromParent_Done,
     /*  631471 */   // Label 9827: @631471
     /*  631471 */   GIM_Try, /*On fail goto*//*Label 9828*/ GIMT_Encode4(631524), // Rule ID 10621 //
     /*  631476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  631479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631487 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631500 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631508 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631522 */     GIR_RootConstrainSelectedInstOperands,
     /*  631523 */     // GIR_Coverage, 10621,
     /*  631523 */     GIR_EraseRootFromParent_Done,
     /*  631524 */   // Label 9828: @631524
     /*  631524 */   GIM_Try, /*On fail goto*//*Label 9829*/ GIMT_Encode4(631577), // Rule ID 10622 //
     /*  631529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  631532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631540 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631553 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631561 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631571 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631575 */     GIR_RootConstrainSelectedInstOperands,
     /*  631576 */     // GIR_Coverage, 10622,
     /*  631576 */     GIR_EraseRootFromParent_Done,
     /*  631577 */   // Label 9829: @631577
     /*  631577 */   GIM_Try, /*On fail goto*//*Label 9830*/ GIMT_Encode4(631630), // Rule ID 10623 //
     /*  631582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  631585 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631593 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631606 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631614 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631624 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631628 */     GIR_RootConstrainSelectedInstOperands,
     /*  631629 */     // GIR_Coverage, 10623,
     /*  631629 */     GIR_EraseRootFromParent_Done,
     /*  631630 */   // Label 9830: @631630
     /*  631630 */   GIM_Try, /*On fail goto*//*Label 9831*/ GIMT_Encode4(631683), // Rule ID 10624 //
     /*  631635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  631638 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631646 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631648 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631659 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631667 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631681 */     GIR_RootConstrainSelectedInstOperands,
     /*  631682 */     // GIR_Coverage, 10624,
     /*  631682 */     GIR_EraseRootFromParent_Done,
     /*  631683 */   // Label 9831: @631683
     /*  631683 */   GIM_Try, /*On fail goto*//*Label 9832*/ GIMT_Encode4(631735), // Rule ID 11176 //
     /*  631688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  631691 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631698 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631711 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631719 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631733 */     GIR_RootConstrainSelectedInstOperands,
     /*  631734 */     // GIR_Coverage, 11176,
     /*  631734 */     GIR_EraseRootFromParent_Done,
     /*  631735 */   // Label 9832: @631735
     /*  631735 */   GIM_Try, /*On fail goto*//*Label 9833*/ GIMT_Encode4(631787), // Rule ID 11177 //
     /*  631740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  631743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631750 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631763 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631771 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631785 */     GIR_RootConstrainSelectedInstOperands,
     /*  631786 */     // GIR_Coverage, 11177,
     /*  631786 */     GIR_EraseRootFromParent_Done,
     /*  631787 */   // Label 9833: @631787
     /*  631787 */   GIM_Try, /*On fail goto*//*Label 9834*/ GIMT_Encode4(631839), // Rule ID 11178 //
     /*  631792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  631795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631802 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631815 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631823 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631837 */     GIR_RootConstrainSelectedInstOperands,
     /*  631838 */     // GIR_Coverage, 11178,
     /*  631838 */     GIR_EraseRootFromParent_Done,
     /*  631839 */   // Label 9834: @631839
     /*  631839 */   GIM_Try, /*On fail goto*//*Label 9835*/ GIMT_Encode4(631891), // Rule ID 11179 //
     /*  631844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  631847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631854 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631867 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631875 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631889 */     GIR_RootConstrainSelectedInstOperands,
     /*  631890 */     // GIR_Coverage, 11179,
     /*  631890 */     GIR_EraseRootFromParent_Done,
     /*  631891 */   // Label 9835: @631891
     /*  631891 */   GIM_Try, /*On fail goto*//*Label 9836*/ GIMT_Encode4(631943), // Rule ID 11180 //
     /*  631896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  631899 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631906 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  631908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631919 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>>  =>  (FLAT_ATOMIC_OR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
     /*  631922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631927 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  631937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631941 */     GIR_RootConstrainSelectedInstOperands,
     /*  631942 */     // GIR_Coverage, 11180,
     /*  631942 */     GIR_EraseRootFromParent_Done,
     /*  631943 */   // Label 9836: @631943
     /*  631943 */   GIM_Try, /*On fail goto*//*Label 9837*/ GIMT_Encode4(632000), // Rule ID 10614 //
     /*  631948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  631951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  631959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  631963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  631967 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  631974 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  631974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  631977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  631979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  631984 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  631986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  631991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  631994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  631998 */     GIR_RootConstrainSelectedInstOperands,
     /*  631999 */     // GIR_Coverage, 10614,
     /*  631999 */     GIR_EraseRootFromParent_Done,
     /*  632000 */   // Label 9837: @632000
     /*  632000 */   GIM_Try, /*On fail goto*//*Label 9838*/ GIMT_Encode4(632057), // Rule ID 10615 //
     /*  632005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  632008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632031 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632041 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632055 */     GIR_RootConstrainSelectedInstOperands,
     /*  632056 */     // GIR_Coverage, 10615,
     /*  632056 */     GIR_EraseRootFromParent_Done,
     /*  632057 */   // Label 9838: @632057
     /*  632057 */   GIM_Try, /*On fail goto*//*Label 9839*/ GIMT_Encode4(632114), // Rule ID 10616 //
     /*  632062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  632065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632088 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632098 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632112 */     GIR_RootConstrainSelectedInstOperands,
     /*  632113 */     // GIR_Coverage, 10616,
     /*  632113 */     GIR_EraseRootFromParent_Done,
     /*  632114 */   // Label 9839: @632114
     /*  632114 */   GIM_Try, /*On fail goto*//*Label 9840*/ GIMT_Encode4(632171), // Rule ID 10617 //
     /*  632119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  632122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632145 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632155 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632165 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632169 */     GIR_RootConstrainSelectedInstOperands,
     /*  632170 */     // GIR_Coverage, 10617,
     /*  632170 */     GIR_EraseRootFromParent_Done,
     /*  632171 */   // Label 9840: @632171
     /*  632171 */   GIM_Try, /*On fail goto*//*Label 9841*/ GIMT_Encode4(632228), // Rule ID 10618 //
     /*  632176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  632179 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632202 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632212 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632226 */     GIR_RootConstrainSelectedInstOperands,
     /*  632227 */     // GIR_Coverage, 10618,
     /*  632227 */     GIR_EraseRootFromParent_Done,
     /*  632228 */   // Label 9841: @632228
     /*  632228 */   GIM_Try, /*On fail goto*//*Label 9842*/ GIMT_Encode4(632284), // Rule ID 11170 //
     /*  632233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  632236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632258 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632268 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632282 */     GIR_RootConstrainSelectedInstOperands,
     /*  632283 */     // GIR_Coverage, 11170,
     /*  632283 */     GIR_EraseRootFromParent_Done,
     /*  632284 */   // Label 9842: @632284
     /*  632284 */   GIM_Try, /*On fail goto*//*Label 9843*/ GIMT_Encode4(632340), // Rule ID 11171 //
     /*  632289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  632292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632314 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632324 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632338 */     GIR_RootConstrainSelectedInstOperands,
     /*  632339 */     // GIR_Coverage, 11171,
     /*  632339 */     GIR_EraseRootFromParent_Done,
     /*  632340 */   // Label 9843: @632340
     /*  632340 */   GIM_Try, /*On fail goto*//*Label 9844*/ GIMT_Encode4(632396), // Rule ID 11172 //
     /*  632345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  632348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632363 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632370 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632380 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632394 */     GIR_RootConstrainSelectedInstOperands,
     /*  632395 */     // GIR_Coverage, 11172,
     /*  632395 */     GIR_EraseRootFromParent_Done,
     /*  632396 */   // Label 9844: @632396
     /*  632396 */   GIM_Try, /*On fail goto*//*Label 9845*/ GIMT_Encode4(632452), // Rule ID 11173 //
     /*  632401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  632404 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632426 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632436 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632450 */     GIR_RootConstrainSelectedInstOperands,
     /*  632451 */     // GIR_Coverage, 11173,
     /*  632451 */     GIR_EraseRootFromParent_Done,
     /*  632452 */   // Label 9845: @632452
     /*  632452 */   GIM_Try, /*On fail goto*//*Label 9846*/ GIMT_Encode4(632508), // Rule ID 11174 //
     /*  632457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  632460 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  632471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  632482 */     // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  632482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
     /*  632485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  632487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  632492 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  632494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  632499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  632502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632506 */     GIR_RootConstrainSelectedInstOperands,
     /*  632507 */     // GIR_Coverage, 11174,
     /*  632507 */     GIR_EraseRootFromParent_Done,
     /*  632508 */   // Label 9846: @632508
     /*  632508 */   GIM_Reject,
     /*  632509 */ // Label 9740: @632509
     /*  632509 */ GIM_Reject,
     /*  632510 */ // Label 9738: @632510
     /*  632510 */ GIM_Try, /*On fail goto*//*Label 9847*/ GIMT_Encode4(640009),
     /*  632515 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  632518 */   GIM_Try, /*On fail goto*//*Label 9848*/ GIMT_Encode4(632580), // Rule ID 21538 //
     /*  632523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  632526 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632533 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632546 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64),
     /*  632549 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632578 */     GIR_RootConstrainSelectedInstOperands,
     /*  632579 */     // GIR_Coverage, 21538,
     /*  632579 */     GIR_EraseRootFromParent_Done,
     /*  632580 */   // Label 9848: @632580
     /*  632580 */   GIM_Try, /*On fail goto*//*Label 9849*/ GIMT_Encode4(632642), // Rule ID 21539 //
     /*  632585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  632588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632595 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632608 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64),
     /*  632611 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632640 */     GIR_RootConstrainSelectedInstOperands,
     /*  632641 */     // GIR_Coverage, 21539,
     /*  632641 */     GIR_EraseRootFromParent_Done,
     /*  632642 */   // Label 9849: @632642
     /*  632642 */   GIM_Try, /*On fail goto*//*Label 9850*/ GIMT_Encode4(632704), // Rule ID 21540 //
     /*  632647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  632650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632657 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632670 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64),
     /*  632673 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632702 */     GIR_RootConstrainSelectedInstOperands,
     /*  632703 */     // GIR_Coverage, 21540,
     /*  632703 */     GIR_EraseRootFromParent_Done,
     /*  632704 */   // Label 9850: @632704
     /*  632704 */   GIM_Try, /*On fail goto*//*Label 9851*/ GIMT_Encode4(632766), // Rule ID 21541 //
     /*  632709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  632712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632719 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632732 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64),
     /*  632735 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632760 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632764 */     GIR_RootConstrainSelectedInstOperands,
     /*  632765 */     // GIR_Coverage, 21541,
     /*  632765 */     GIR_EraseRootFromParent_Done,
     /*  632766 */   // Label 9851: @632766
     /*  632766 */   GIM_Try, /*On fail goto*//*Label 9852*/ GIMT_Encode4(632828), // Rule ID 21542 //
     /*  632771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  632774 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632781 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632794 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64),
     /*  632797 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632819 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632822 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632826 */     GIR_RootConstrainSelectedInstOperands,
     /*  632827 */     // GIR_Coverage, 21542,
     /*  632827 */     GIR_EraseRootFromParent_Done,
     /*  632828 */   // Label 9852: @632828
     /*  632828 */   GIM_Try, /*On fail goto*//*Label 9853*/ GIMT_Encode4(632890), // Rule ID 21558 //
     /*  632833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  632836 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632843 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632856 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64),
     /*  632859 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632888 */     GIR_RootConstrainSelectedInstOperands,
     /*  632889 */     // GIR_Coverage, 21558,
     /*  632889 */     GIR_EraseRootFromParent_Done,
     /*  632890 */   // Label 9853: @632890
     /*  632890 */   GIM_Try, /*On fail goto*//*Label 9854*/ GIMT_Encode4(632952), // Rule ID 21559 //
     /*  632895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  632898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632905 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632918 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64),
     /*  632921 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  632938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  632943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  632946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  632950 */     GIR_RootConstrainSelectedInstOperands,
     /*  632951 */     // GIR_Coverage, 21559,
     /*  632951 */     GIR_EraseRootFromParent_Done,
     /*  632952 */   // Label 9854: @632952
     /*  632952 */   GIM_Try, /*On fail goto*//*Label 9855*/ GIMT_Encode4(633014), // Rule ID 21560 //
     /*  632957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  632960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  632967 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  632969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  632973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  632980 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  632980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64),
     /*  632983 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  632985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  632990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  632995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  633008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633012 */     GIR_RootConstrainSelectedInstOperands,
     /*  633013 */     // GIR_Coverage, 21560,
     /*  633013 */     GIR_EraseRootFromParent_Done,
     /*  633014 */   // Label 9855: @633014
     /*  633014 */   GIM_Try, /*On fail goto*//*Label 9856*/ GIMT_Encode4(633076), // Rule ID 21561 //
     /*  633019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  633022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633029 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  633031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633042 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64),
     /*  633045 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  633070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633074 */     GIR_RootConstrainSelectedInstOperands,
     /*  633075 */     // GIR_Coverage, 21561,
     /*  633075 */     GIR_EraseRootFromParent_Done,
     /*  633076 */   // Label 9856: @633076
     /*  633076 */   GIM_Try, /*On fail goto*//*Label 9857*/ GIMT_Encode4(633138), // Rule ID 21562 //
     /*  633081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  633084 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633091 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  633093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633104 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64),
     /*  633107 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  633132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633136 */     GIR_RootConstrainSelectedInstOperands,
     /*  633137 */     // GIR_Coverage, 21562,
     /*  633137 */     GIR_EraseRootFromParent_Done,
     /*  633138 */   // Label 9857: @633138
     /*  633138 */   GIM_Try, /*On fail goto*//*Label 9858*/ GIMT_Encode4(633204), // Rule ID 21528 //
     /*  633143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  633146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633168 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN),
     /*  633171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633173 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633202 */     GIR_RootConstrainSelectedInstOperands,
     /*  633203 */     // GIR_Coverage, 21528,
     /*  633203 */     GIR_EraseRootFromParent_Done,
     /*  633204 */   // Label 9858: @633204
     /*  633204 */   GIM_Try, /*On fail goto*//*Label 9859*/ GIMT_Encode4(633270), // Rule ID 21529 //
     /*  633209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  633212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633234 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN),
     /*  633237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633239 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633268 */     GIR_RootConstrainSelectedInstOperands,
     /*  633269 */     // GIR_Coverage, 21529,
     /*  633269 */     GIR_EraseRootFromParent_Done,
     /*  633270 */   // Label 9859: @633270
     /*  633270 */   GIM_Try, /*On fail goto*//*Label 9860*/ GIMT_Encode4(633336), // Rule ID 21530 //
     /*  633275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  633278 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633300 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN),
     /*  633303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633305 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633334 */     GIR_RootConstrainSelectedInstOperands,
     /*  633335 */     // GIR_Coverage, 21530,
     /*  633335 */     GIR_EraseRootFromParent_Done,
     /*  633336 */   // Label 9860: @633336
     /*  633336 */   GIM_Try, /*On fail goto*//*Label 9861*/ GIMT_Encode4(633402), // Rule ID 21531 //
     /*  633341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  633344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633366 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN),
     /*  633369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633371 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633400 */     GIR_RootConstrainSelectedInstOperands,
     /*  633401 */     // GIR_Coverage, 21531,
     /*  633401 */     GIR_EraseRootFromParent_Done,
     /*  633402 */   // Label 9861: @633402
     /*  633402 */   GIM_Try, /*On fail goto*//*Label 9862*/ GIMT_Encode4(633468), // Rule ID 21532 //
     /*  633407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  633410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633432 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN),
     /*  633435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633437 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633466 */     GIR_RootConstrainSelectedInstOperands,
     /*  633467 */     // GIR_Coverage, 21532,
     /*  633467 */     GIR_EraseRootFromParent_Done,
     /*  633468 */   // Label 9862: @633468
     /*  633468 */   GIM_Try, /*On fail goto*//*Label 9863*/ GIMT_Encode4(633534), // Rule ID 21548 //
     /*  633473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  633476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633498 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN),
     /*  633501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633503 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633532 */     GIR_RootConstrainSelectedInstOperands,
     /*  633533 */     // GIR_Coverage, 21548,
     /*  633533 */     GIR_EraseRootFromParent_Done,
     /*  633534 */   // Label 9863: @633534
     /*  633534 */   GIM_Try, /*On fail goto*//*Label 9864*/ GIMT_Encode4(633600), // Rule ID 21549 //
     /*  633539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  633542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633564 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN),
     /*  633567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633569 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633598 */     GIR_RootConstrainSelectedInstOperands,
     /*  633599 */     // GIR_Coverage, 21549,
     /*  633599 */     GIR_EraseRootFromParent_Done,
     /*  633600 */   // Label 9864: @633600
     /*  633600 */   GIM_Try, /*On fail goto*//*Label 9865*/ GIMT_Encode4(633666), // Rule ID 21550 //
     /*  633605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  633608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633630 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN),
     /*  633633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633635 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633664 */     GIR_RootConstrainSelectedInstOperands,
     /*  633665 */     // GIR_Coverage, 21550,
     /*  633665 */     GIR_EraseRootFromParent_Done,
     /*  633666 */   // Label 9865: @633666
     /*  633666 */   GIM_Try, /*On fail goto*//*Label 9866*/ GIMT_Encode4(633732), // Rule ID 21551 //
     /*  633671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  633674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633696 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN),
     /*  633699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633701 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633730 */     GIR_RootConstrainSelectedInstOperands,
     /*  633731 */     // GIR_Coverage, 21551,
     /*  633731 */     GIR_EraseRootFromParent_Done,
     /*  633732 */   // Label 9866: @633732
     /*  633732 */   GIM_Try, /*On fail goto*//*Label 9867*/ GIMT_Encode4(633798), // Rule ID 21552 //
     /*  633737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  633740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  633751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  633762 */     // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN),
     /*  633765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  633767 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  633774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  633784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  633789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  633792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633796 */     GIR_RootConstrainSelectedInstOperands,
     /*  633797 */     // GIR_Coverage, 21552,
     /*  633797 */     GIR_EraseRootFromParent_Done,
     /*  633798 */   // Label 9867: @633798
     /*  633798 */   GIM_Try, /*On fail goto*//*Label 9868*/ GIMT_Encode4(633855), // Rule ID 21533 //
     /*  633803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  633806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633813 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  633815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  633826 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
     /*  633829 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  633841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  633846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  633849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633853 */     GIR_RootConstrainSelectedInstOperands,
     /*  633854 */     // GIR_Coverage, 21533,
     /*  633854 */     GIR_EraseRootFromParent_Done,
     /*  633855 */   // Label 9868: @633855
     /*  633855 */   GIM_Try, /*On fail goto*//*Label 9869*/ GIMT_Encode4(633912), // Rule ID 21534 //
     /*  633860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  633863 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633870 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  633872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  633883 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
     /*  633886 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  633898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  633903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  633906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633910 */     GIR_RootConstrainSelectedInstOperands,
     /*  633911 */     // GIR_Coverage, 21534,
     /*  633911 */     GIR_EraseRootFromParent_Done,
     /*  633912 */   // Label 9869: @633912
     /*  633912 */   GIM_Try, /*On fail goto*//*Label 9870*/ GIMT_Encode4(633969), // Rule ID 21535 //
     /*  633917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  633920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633927 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  633929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  633940 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
     /*  633943 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  633945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  633950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  633955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  633960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  633963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  633967 */     GIR_RootConstrainSelectedInstOperands,
     /*  633968 */     // GIR_Coverage, 21535,
     /*  633968 */     GIR_EraseRootFromParent_Done,
     /*  633969 */   // Label 9870: @633969
     /*  633969 */   GIM_Try, /*On fail goto*//*Label 9871*/ GIMT_Encode4(634026), // Rule ID 21536 //
     /*  633974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  633977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  633984 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  633986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  633990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  633997 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  633997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
     /*  634000 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634024 */     GIR_RootConstrainSelectedInstOperands,
     /*  634025 */     // GIR_Coverage, 21536,
     /*  634025 */     GIR_EraseRootFromParent_Done,
     /*  634026 */   // Label 9871: @634026
     /*  634026 */   GIM_Try, /*On fail goto*//*Label 9872*/ GIMT_Encode4(634083), // Rule ID 21537 //
     /*  634031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  634034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634041 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634043 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634054 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
     /*  634057 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634074 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634077 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634081 */     GIR_RootConstrainSelectedInstOperands,
     /*  634082 */     // GIR_Coverage, 21537,
     /*  634082 */     GIR_EraseRootFromParent_Done,
     /*  634083 */   // Label 9872: @634083
     /*  634083 */   GIM_Try, /*On fail goto*//*Label 9873*/ GIMT_Encode4(634140), // Rule ID 21553 //
     /*  634088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  634091 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634098 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634111 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
     /*  634114 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634138 */     GIR_RootConstrainSelectedInstOperands,
     /*  634139 */     // GIR_Coverage, 21553,
     /*  634139 */     GIR_EraseRootFromParent_Done,
     /*  634140 */   // Label 9873: @634140
     /*  634140 */   GIM_Try, /*On fail goto*//*Label 9874*/ GIMT_Encode4(634197), // Rule ID 21554 //
     /*  634145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  634148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634155 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634168 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
     /*  634171 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634195 */     GIR_RootConstrainSelectedInstOperands,
     /*  634196 */     // GIR_Coverage, 21554,
     /*  634196 */     GIR_EraseRootFromParent_Done,
     /*  634197 */   // Label 9874: @634197
     /*  634197 */   GIM_Try, /*On fail goto*//*Label 9875*/ GIMT_Encode4(634254), // Rule ID 21555 //
     /*  634202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  634205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634212 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634225 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
     /*  634228 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634252 */     GIR_RootConstrainSelectedInstOperands,
     /*  634253 */     // GIR_Coverage, 21555,
     /*  634253 */     GIR_EraseRootFromParent_Done,
     /*  634254 */   // Label 9875: @634254
     /*  634254 */   GIM_Try, /*On fail goto*//*Label 9876*/ GIMT_Encode4(634311), // Rule ID 21556 //
     /*  634259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  634262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634269 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634282 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
     /*  634285 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634309 */     GIR_RootConstrainSelectedInstOperands,
     /*  634310 */     // GIR_Coverage, 21556,
     /*  634310 */     GIR_EraseRootFromParent_Done,
     /*  634311 */   // Label 9876: @634311
     /*  634311 */   GIM_Try, /*On fail goto*//*Label 9877*/ GIMT_Encode4(634368), // Rule ID 21557 //
     /*  634316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  634319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634326 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634339 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
     /*  634342 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  634362 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634366 */     GIR_RootConstrainSelectedInstOperands,
     /*  634367 */     // GIR_Coverage, 21557,
     /*  634367 */     GIR_EraseRootFromParent_Done,
     /*  634368 */   // Label 9877: @634368
     /*  634368 */   GIM_Try, /*On fail goto*//*Label 9878*/ GIMT_Encode4(634429), // Rule ID 21523 //
     /*  634373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  634376 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634398 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
     /*  634401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634403 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634427 */     GIR_RootConstrainSelectedInstOperands,
     /*  634428 */     // GIR_Coverage, 21523,
     /*  634428 */     GIR_EraseRootFromParent_Done,
     /*  634429 */   // Label 9878: @634429
     /*  634429 */   GIM_Try, /*On fail goto*//*Label 9879*/ GIMT_Encode4(634490), // Rule ID 21524 //
     /*  634434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  634437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634459 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
     /*  634462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634464 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634488 */     GIR_RootConstrainSelectedInstOperands,
     /*  634489 */     // GIR_Coverage, 21524,
     /*  634489 */     GIR_EraseRootFromParent_Done,
     /*  634490 */   // Label 9879: @634490
     /*  634490 */   GIM_Try, /*On fail goto*//*Label 9880*/ GIMT_Encode4(634551), // Rule ID 21525 //
     /*  634495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  634498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634520 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
     /*  634523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634525 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634545 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634549 */     GIR_RootConstrainSelectedInstOperands,
     /*  634550 */     // GIR_Coverage, 21525,
     /*  634550 */     GIR_EraseRootFromParent_Done,
     /*  634551 */   // Label 9880: @634551
     /*  634551 */   GIM_Try, /*On fail goto*//*Label 9881*/ GIMT_Encode4(634612), // Rule ID 21526 //
     /*  634556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  634559 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634581 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
     /*  634584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634586 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634610 */     GIR_RootConstrainSelectedInstOperands,
     /*  634611 */     // GIR_Coverage, 21526,
     /*  634611 */     GIR_EraseRootFromParent_Done,
     /*  634612 */   // Label 9881: @634612
     /*  634612 */   GIM_Try, /*On fail goto*//*Label 9882*/ GIMT_Encode4(634673), // Rule ID 21527 //
     /*  634617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  634620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634631 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634642 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
     /*  634645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634647 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634671 */     GIR_RootConstrainSelectedInstOperands,
     /*  634672 */     // GIR_Coverage, 21527,
     /*  634672 */     GIR_EraseRootFromParent_Done,
     /*  634673 */   // Label 9882: @634673
     /*  634673 */   GIM_Try, /*On fail goto*//*Label 9883*/ GIMT_Encode4(634734), // Rule ID 21543 //
     /*  634678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  634681 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634692 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634703 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
     /*  634706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634708 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634728 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634732 */     GIR_RootConstrainSelectedInstOperands,
     /*  634733 */     // GIR_Coverage, 21543,
     /*  634733 */     GIR_EraseRootFromParent_Done,
     /*  634734 */   // Label 9883: @634734
     /*  634734 */   GIM_Try, /*On fail goto*//*Label 9884*/ GIMT_Encode4(634795), // Rule ID 21544 //
     /*  634739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  634742 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634764 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
     /*  634767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634769 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634793 */     GIR_RootConstrainSelectedInstOperands,
     /*  634794 */     // GIR_Coverage, 21544,
     /*  634794 */     GIR_EraseRootFromParent_Done,
     /*  634795 */   // Label 9884: @634795
     /*  634795 */   GIM_Try, /*On fail goto*//*Label 9885*/ GIMT_Encode4(634856), // Rule ID 21545 //
     /*  634800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  634803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634814 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634818 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634825 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
     /*  634828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634830 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634854 */     GIR_RootConstrainSelectedInstOperands,
     /*  634855 */     // GIR_Coverage, 21545,
     /*  634855 */     GIR_EraseRootFromParent_Done,
     /*  634856 */   // Label 9885: @634856
     /*  634856 */   GIM_Try, /*On fail goto*//*Label 9886*/ GIMT_Encode4(634917), // Rule ID 21546 //
     /*  634861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  634864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634886 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
     /*  634889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634891 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634915 */     GIR_RootConstrainSelectedInstOperands,
     /*  634916 */     // GIR_Coverage, 21546,
     /*  634916 */     GIR_EraseRootFromParent_Done,
     /*  634917 */   // Label 9886: @634917
     /*  634917 */   GIM_Try, /*On fail goto*//*Label 9887*/ GIMT_Encode4(634978), // Rule ID 21547 //
     /*  634922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  634925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  634932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  634936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  634947 */     // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  634947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
     /*  634950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  634952 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  634954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  634959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  634964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  634969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  634972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  634976 */     GIR_RootConstrainSelectedInstOperands,
     /*  634977 */     // GIR_Coverage, 21547,
     /*  634977 */     GIR_EraseRootFromParent_Done,
     /*  634978 */   // Label 9887: @634978
     /*  634978 */   GIM_Try, /*On fail goto*//*Label 9888*/ GIMT_Encode4(635028), // Rule ID 30715 //
     /*  634983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  634986 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  634991 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  634993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  634997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635004 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635012 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635026 */     GIR_RootConstrainSelectedInstOperands,
     /*  635027 */     // GIR_Coverage, 30715,
     /*  635027 */     GIR_EraseRootFromParent_Done,
     /*  635028 */   // Label 9888: @635028
     /*  635028 */   GIM_Try, /*On fail goto*//*Label 9889*/ GIMT_Encode4(635078), // Rule ID 30716 //
     /*  635033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  635036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635041 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635043 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635054 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635062 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635076 */     GIR_RootConstrainSelectedInstOperands,
     /*  635077 */     // GIR_Coverage, 30716,
     /*  635077 */     GIR_EraseRootFromParent_Done,
     /*  635078 */   // Label 9889: @635078
     /*  635078 */   GIM_Try, /*On fail goto*//*Label 9890*/ GIMT_Encode4(635128), // Rule ID 30717 //
     /*  635083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  635086 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635091 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635104 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635112 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635126 */     GIR_RootConstrainSelectedInstOperands,
     /*  635127 */     // GIR_Coverage, 30717,
     /*  635127 */     GIR_EraseRootFromParent_Done,
     /*  635128 */   // Label 9890: @635128
     /*  635128 */   GIM_Try, /*On fail goto*//*Label 9891*/ GIMT_Encode4(635178), // Rule ID 30718 //
     /*  635133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  635136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635141 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635154 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635162 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635176 */     GIR_RootConstrainSelectedInstOperands,
     /*  635177 */     // GIR_Coverage, 30718,
     /*  635177 */     GIR_EraseRootFromParent_Done,
     /*  635178 */   // Label 9891: @635178
     /*  635178 */   GIM_Try, /*On fail goto*//*Label 9892*/ GIMT_Encode4(635228), // Rule ID 30719 //
     /*  635183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  635186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635191 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635204 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635212 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635226 */     GIR_RootConstrainSelectedInstOperands,
     /*  635227 */     // GIR_Coverage, 30719,
     /*  635227 */     GIR_EraseRootFromParent_Done,
     /*  635228 */   // Label 9892: @635228
     /*  635228 */   GIM_Try, /*On fail goto*//*Label 9893*/ GIMT_Encode4(635278), // Rule ID 30725 //
     /*  635233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  635236 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635241 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635254 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_i64>>  =>  (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9),
     /*  635257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635262 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635276 */     GIR_RootConstrainSelectedInstOperands,
     /*  635277 */     // GIR_Coverage, 30725,
     /*  635277 */     GIR_EraseRootFromParent_Done,
     /*  635278 */   // Label 9893: @635278
     /*  635278 */   GIM_Try, /*On fail goto*//*Label 9894*/ GIMT_Encode4(635328), // Rule ID 30726 //
     /*  635283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  635286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635291 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635304 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_i64>>  =>  (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9),
     /*  635307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635312 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635326 */     GIR_RootConstrainSelectedInstOperands,
     /*  635327 */     // GIR_Coverage, 30726,
     /*  635327 */     GIR_EraseRootFromParent_Done,
     /*  635328 */   // Label 9894: @635328
     /*  635328 */   GIM_Try, /*On fail goto*//*Label 9895*/ GIMT_Encode4(635378), // Rule ID 30727 //
     /*  635333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  635336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635341 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635354 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_i64>>  =>  (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9),
     /*  635357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635362 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635376 */     GIR_RootConstrainSelectedInstOperands,
     /*  635377 */     // GIR_Coverage, 30727,
     /*  635377 */     GIR_EraseRootFromParent_Done,
     /*  635378 */   // Label 9895: @635378
     /*  635378 */   GIM_Try, /*On fail goto*//*Label 9896*/ GIMT_Encode4(635428), // Rule ID 30728 //
     /*  635383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  635386 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635391 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635404 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_i64>>  =>  (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9),
     /*  635407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635412 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635426 */     GIR_RootConstrainSelectedInstOperands,
     /*  635427 */     // GIR_Coverage, 30728,
     /*  635427 */     GIR_EraseRootFromParent_Done,
     /*  635428 */   // Label 9896: @635428
     /*  635428 */   GIM_Try, /*On fail goto*//*Label 9897*/ GIMT_Encode4(635478), // Rule ID 30729 //
     /*  635433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  635436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635441 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635443 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635447 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635454 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_i64>>  =>  (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9),
     /*  635457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635462 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635476 */     GIR_RootConstrainSelectedInstOperands,
     /*  635477 */     // GIR_Coverage, 30729,
     /*  635477 */     GIR_EraseRootFromParent_Done,
     /*  635478 */   // Label 9897: @635478
     /*  635478 */   GIM_Try, /*On fail goto*//*Label 9898*/ GIMT_Encode4(635528), // Rule ID 30735 //
     /*  635483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  635486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  635491 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635504 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  635504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635512 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  635522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635526 */     GIR_RootConstrainSelectedInstOperands,
     /*  635527 */     // GIR_Coverage, 30735,
     /*  635527 */     GIR_EraseRootFromParent_Done,
     /*  635528 */   // Label 9898: @635528
     /*  635528 */   GIM_Try, /*On fail goto*//*Label 9899*/ GIMT_Encode4(635578), // Rule ID 30736 //
     /*  635533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  635536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  635541 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635554 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  635554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635562 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  635572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635576 */     GIR_RootConstrainSelectedInstOperands,
     /*  635577 */     // GIR_Coverage, 30736,
     /*  635577 */     GIR_EraseRootFromParent_Done,
     /*  635578 */   // Label 9899: @635578
     /*  635578 */   GIM_Try, /*On fail goto*//*Label 9900*/ GIMT_Encode4(635628), // Rule ID 30737 //
     /*  635583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  635586 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  635591 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635593 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635604 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  635604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635612 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  635622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635626 */     GIR_RootConstrainSelectedInstOperands,
     /*  635627 */     // GIR_Coverage, 30737,
     /*  635627 */     GIR_EraseRootFromParent_Done,
     /*  635628 */   // Label 9900: @635628
     /*  635628 */   GIM_Try, /*On fail goto*//*Label 9901*/ GIMT_Encode4(635678), // Rule ID 30738 //
     /*  635633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  635636 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  635641 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635654 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  635654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635662 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  635672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635676 */     GIR_RootConstrainSelectedInstOperands,
     /*  635677 */     // GIR_Coverage, 30738,
     /*  635677 */     GIR_EraseRootFromParent_Done,
     /*  635678 */   // Label 9901: @635678
     /*  635678 */   GIM_Try, /*On fail goto*//*Label 9902*/ GIMT_Encode4(635728), // Rule ID 30739 //
     /*  635683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  635686 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  635691 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  635693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635704 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  635704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
     /*  635707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635712 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  635722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635726 */     GIR_RootConstrainSelectedInstOperands,
     /*  635727 */     // GIR_Coverage, 30739,
     /*  635727 */     GIR_EraseRootFromParent_Done,
     /*  635728 */   // Label 9902: @635728
     /*  635728 */   GIM_Try, /*On fail goto*//*Label 9903*/ GIMT_Encode4(635782), // Rule ID 30710 //
     /*  635733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  635736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  635745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635756 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  635759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  635761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635766 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635780 */     GIR_RootConstrainSelectedInstOperands,
     /*  635781 */     // GIR_Coverage, 30710,
     /*  635781 */     GIR_EraseRootFromParent_Done,
     /*  635782 */   // Label 9903: @635782
     /*  635782 */   GIM_Try, /*On fail goto*//*Label 9904*/ GIMT_Encode4(635836), // Rule ID 30711 //
     /*  635787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  635790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  635799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635810 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  635813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  635815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635820 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635834 */     GIR_RootConstrainSelectedInstOperands,
     /*  635835 */     // GIR_Coverage, 30711,
     /*  635835 */     GIR_EraseRootFromParent_Done,
     /*  635836 */   // Label 9904: @635836
     /*  635836 */   GIM_Try, /*On fail goto*//*Label 9905*/ GIMT_Encode4(635890), // Rule ID 30712 //
     /*  635841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  635844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  635853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635864 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  635867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  635869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635874 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635888 */     GIR_RootConstrainSelectedInstOperands,
     /*  635889 */     // GIR_Coverage, 30712,
     /*  635889 */     GIR_EraseRootFromParent_Done,
     /*  635890 */   // Label 9905: @635890
     /*  635890 */   GIM_Try, /*On fail goto*//*Label 9906*/ GIMT_Encode4(635944), // Rule ID 30713 //
     /*  635895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  635898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  635907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635918 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  635921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  635923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635928 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635942 */     GIR_RootConstrainSelectedInstOperands,
     /*  635943 */     // GIR_Coverage, 30713,
     /*  635943 */     GIR_EraseRootFromParent_Done,
     /*  635944 */   // Label 9906: @635944
     /*  635944 */   GIM_Try, /*On fail goto*//*Label 9907*/ GIMT_Encode4(635998), // Rule ID 30714 //
     /*  635949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  635952 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  635957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  635961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  635965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  635972 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  635972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  635975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  635977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  635982 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  635984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  635989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  635992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  635996 */     GIR_RootConstrainSelectedInstOperands,
     /*  635997 */     // GIR_Coverage, 30714,
     /*  635997 */     GIR_EraseRootFromParent_Done,
     /*  635998 */   // Label 9907: @635998
     /*  635998 */   GIM_Try, /*On fail goto*//*Label 9908*/ GIMT_Encode4(636052), // Rule ID 30720 //
     /*  636003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  636006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  636011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636026 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_i64>>  =>  (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  636026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9),
     /*  636029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636036 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  636046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636050 */     GIR_RootConstrainSelectedInstOperands,
     /*  636051 */     // GIR_Coverage, 30720,
     /*  636051 */     GIR_EraseRootFromParent_Done,
     /*  636052 */   // Label 9908: @636052
     /*  636052 */   GIM_Try, /*On fail goto*//*Label 9909*/ GIMT_Encode4(636106), // Rule ID 30721 //
     /*  636057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  636060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  636065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636080 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_i64>>  =>  (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  636080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9),
     /*  636083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636090 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  636100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636104 */     GIR_RootConstrainSelectedInstOperands,
     /*  636105 */     // GIR_Coverage, 30721,
     /*  636105 */     GIR_EraseRootFromParent_Done,
     /*  636106 */   // Label 9909: @636106
     /*  636106 */   GIM_Try, /*On fail goto*//*Label 9910*/ GIMT_Encode4(636160), // Rule ID 30722 //
     /*  636111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  636114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  636119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636127 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636134 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_i64>>  =>  (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  636134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9),
     /*  636137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636144 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  636154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636158 */     GIR_RootConstrainSelectedInstOperands,
     /*  636159 */     // GIR_Coverage, 30722,
     /*  636159 */     GIR_EraseRootFromParent_Done,
     /*  636160 */   // Label 9910: @636160
     /*  636160 */   GIM_Try, /*On fail goto*//*Label 9911*/ GIMT_Encode4(636214), // Rule ID 30723 //
     /*  636165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  636168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  636173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636188 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_i64>>  =>  (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  636188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9),
     /*  636191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636198 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  636208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636212 */     GIR_RootConstrainSelectedInstOperands,
     /*  636213 */     // GIR_Coverage, 30723,
     /*  636213 */     GIR_EraseRootFromParent_Done,
     /*  636214 */   // Label 9911: @636214
     /*  636214 */   GIM_Try, /*On fail goto*//*Label 9912*/ GIMT_Encode4(636268), // Rule ID 30724 //
     /*  636219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  636222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  636227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636242 */     // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_i64>>  =>  (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  636242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9),
     /*  636245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636252 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  636262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636266 */     GIR_RootConstrainSelectedInstOperands,
     /*  636267 */     // GIR_Coverage, 30724,
     /*  636267 */     GIR_EraseRootFromParent_Done,
     /*  636268 */   // Label 9912: @636268
     /*  636268 */   GIM_Try, /*On fail goto*//*Label 9913*/ GIMT_Encode4(636322), // Rule ID 30730 //
     /*  636273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  636276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  636281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636296 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  636296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  636299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636306 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  636316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636320 */     GIR_RootConstrainSelectedInstOperands,
     /*  636321 */     // GIR_Coverage, 30730,
     /*  636321 */     GIR_EraseRootFromParent_Done,
     /*  636322 */   // Label 9913: @636322
     /*  636322 */   GIM_Try, /*On fail goto*//*Label 9914*/ GIMT_Encode4(636376), // Rule ID 30731 //
     /*  636327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  636330 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  636335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636339 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636350 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  636350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  636353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636360 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  636370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636374 */     GIR_RootConstrainSelectedInstOperands,
     /*  636375 */     // GIR_Coverage, 30731,
     /*  636375 */     GIR_EraseRootFromParent_Done,
     /*  636376 */   // Label 9914: @636376
     /*  636376 */   GIM_Try, /*On fail goto*//*Label 9915*/ GIMT_Encode4(636430), // Rule ID 30732 //
     /*  636381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  636384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  636389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636404 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  636404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  636407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636414 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  636424 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636428 */     GIR_RootConstrainSelectedInstOperands,
     /*  636429 */     // GIR_Coverage, 30732,
     /*  636429 */     GIR_EraseRootFromParent_Done,
     /*  636430 */   // Label 9915: @636430
     /*  636430 */   GIM_Try, /*On fail goto*//*Label 9916*/ GIMT_Encode4(636484), // Rule ID 30733 //
     /*  636435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  636438 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  636443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636447 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636451 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636458 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  636458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  636461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636468 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  636478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636482 */     GIR_RootConstrainSelectedInstOperands,
     /*  636483 */     // GIR_Coverage, 30733,
     /*  636483 */     GIR_EraseRootFromParent_Done,
     /*  636484 */   // Label 9916: @636484
     /*  636484 */   GIM_Try, /*On fail goto*//*Label 9917*/ GIMT_Encode4(636538), // Rule ID 30734 //
     /*  636489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  636492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  636497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  636512 */     // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_i64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  636512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
     /*  636515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  636522 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  636524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  636529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  636532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636536 */     GIR_RootConstrainSelectedInstOperands,
     /*  636537 */     // GIR_Coverage, 30734,
     /*  636537 */     GIR_EraseRootFromParent_Done,
     /*  636538 */   // Label 9917: @636538
     /*  636538 */   GIM_Try, /*On fail goto*//*Label 9918*/ GIMT_Encode4(636597), // Rule ID 13285 //
     /*  636543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  636546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636553 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  636555 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636559 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  636566 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR),
     /*  636569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636574 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636591 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636595 */     GIR_RootConstrainSelectedInstOperands,
     /*  636596 */     // GIR_Coverage, 13285,
     /*  636596 */     GIR_EraseRootFromParent_Done,
     /*  636597 */   // Label 9918: @636597
     /*  636597 */   GIM_Try, /*On fail goto*//*Label 9919*/ GIMT_Encode4(636656), // Rule ID 13286 //
     /*  636602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  636605 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636612 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  636614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  636625 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR),
     /*  636628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636633 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636654 */     GIR_RootConstrainSelectedInstOperands,
     /*  636655 */     // GIR_Coverage, 13286,
     /*  636655 */     GIR_EraseRootFromParent_Done,
     /*  636656 */   // Label 9919: @636656
     /*  636656 */   GIM_Try, /*On fail goto*//*Label 9920*/ GIMT_Encode4(636715), // Rule ID 13287 //
     /*  636661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  636664 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636671 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  636673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  636684 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR),
     /*  636687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636692 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636713 */     GIR_RootConstrainSelectedInstOperands,
     /*  636714 */     // GIR_Coverage, 13287,
     /*  636714 */     GIR_EraseRootFromParent_Done,
     /*  636715 */   // Label 9920: @636715
     /*  636715 */   GIM_Try, /*On fail goto*//*Label 9921*/ GIMT_Encode4(636774), // Rule ID 13288 //
     /*  636720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  636723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636730 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  636732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  636743 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR),
     /*  636746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636751 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636772 */     GIR_RootConstrainSelectedInstOperands,
     /*  636773 */     // GIR_Coverage, 13288,
     /*  636773 */     GIR_EraseRootFromParent_Done,
     /*  636774 */   // Label 9921: @636774
     /*  636774 */   GIM_Try, /*On fail goto*//*Label 9922*/ GIMT_Encode4(636833), // Rule ID 13289 //
     /*  636779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  636782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636789 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  636791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  636802 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR),
     /*  636805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636810 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636831 */     GIR_RootConstrainSelectedInstOperands,
     /*  636832 */     // GIR_Coverage, 13289,
     /*  636832 */     GIR_EraseRootFromParent_Done,
     /*  636833 */   // Label 9922: @636833
     /*  636833 */   GIM_Try, /*On fail goto*//*Label 9923*/ GIMT_Encode4(636896), // Rule ID 13295 //
     /*  636838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  636841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  636863 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN),
     /*  636866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636873 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636894 */     GIR_RootConstrainSelectedInstOperands,
     /*  636895 */     // GIR_Coverage, 13295,
     /*  636895 */     GIR_EraseRootFromParent_Done,
     /*  636896 */   // Label 9923: @636896
     /*  636896 */   GIM_Try, /*On fail goto*//*Label 9924*/ GIMT_Encode4(636959), // Rule ID 13296 //
     /*  636901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  636904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  636926 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN),
     /*  636929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636936 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  636938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  636943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  636948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  636953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  636957 */     GIR_RootConstrainSelectedInstOperands,
     /*  636958 */     // GIR_Coverage, 13296,
     /*  636958 */     GIR_EraseRootFromParent_Done,
     /*  636959 */   // Label 9924: @636959
     /*  636959 */   GIM_Try, /*On fail goto*//*Label 9925*/ GIMT_Encode4(637022), // Rule ID 13297 //
     /*  636964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  636967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  636974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  636978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  636982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  636989 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  636989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN),
     /*  636992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  636994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  636999 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637020 */     GIR_RootConstrainSelectedInstOperands,
     /*  637021 */     // GIR_Coverage, 13297,
     /*  637021 */     GIR_EraseRootFromParent_Done,
     /*  637022 */   // Label 9925: @637022
     /*  637022 */   GIM_Try, /*On fail goto*//*Label 9926*/ GIMT_Encode4(637085), // Rule ID 13298 //
     /*  637027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  637030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  637052 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN),
     /*  637055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637062 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637079 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637083 */     GIR_RootConstrainSelectedInstOperands,
     /*  637084 */     // GIR_Coverage, 13298,
     /*  637084 */     GIR_EraseRootFromParent_Done,
     /*  637085 */   // Label 9926: @637085
     /*  637085 */   GIM_Try, /*On fail goto*//*Label 9927*/ GIMT_Encode4(637148), // Rule ID 13299 //
     /*  637090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  637093 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637104 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  637115 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN),
     /*  637118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637125 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637146 */     GIR_RootConstrainSelectedInstOperands,
     /*  637147 */     // GIR_Coverage, 13299,
     /*  637147 */     GIR_EraseRootFromParent_Done,
     /*  637148 */   // Label 9927: @637148
     /*  637148 */   GIM_Try, /*On fail goto*//*Label 9928*/ GIMT_Encode4(637200), // Rule ID 13280 //
     /*  637153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  637156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637163 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637176 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2),
     /*  637179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637184 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  637194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637198 */     GIR_RootConstrainSelectedInstOperands,
     /*  637199 */     // GIR_Coverage, 13280,
     /*  637199 */     GIR_EraseRootFromParent_Done,
     /*  637200 */   // Label 9928: @637200
     /*  637200 */   GIM_Try, /*On fail goto*//*Label 9929*/ GIMT_Encode4(637252), // Rule ID 13281 //
     /*  637205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  637208 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637215 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637228 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2),
     /*  637231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637236 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  637246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637250 */     GIR_RootConstrainSelectedInstOperands,
     /*  637251 */     // GIR_Coverage, 13281,
     /*  637251 */     GIR_EraseRootFromParent_Done,
     /*  637252 */   // Label 9929: @637252
     /*  637252 */   GIM_Try, /*On fail goto*//*Label 9930*/ GIMT_Encode4(637304), // Rule ID 13282 //
     /*  637257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  637260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637267 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637280 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2),
     /*  637283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637288 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  637298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637302 */     GIR_RootConstrainSelectedInstOperands,
     /*  637303 */     // GIR_Coverage, 13282,
     /*  637303 */     GIR_EraseRootFromParent_Done,
     /*  637304 */   // Label 9930: @637304
     /*  637304 */   GIM_Try, /*On fail goto*//*Label 9931*/ GIMT_Encode4(637356), // Rule ID 13283 //
     /*  637309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  637312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637319 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637332 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2),
     /*  637335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637340 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  637350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637354 */     GIR_RootConstrainSelectedInstOperands,
     /*  637355 */     // GIR_Coverage, 13283,
     /*  637355 */     GIR_EraseRootFromParent_Done,
     /*  637356 */   // Label 9931: @637356
     /*  637356 */   GIM_Try, /*On fail goto*//*Label 9932*/ GIMT_Encode4(637408), // Rule ID 13284 //
     /*  637361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  637364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637371 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637373 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637384 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (GLOBAL_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2),
     /*  637387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637392 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  637402 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637406 */     GIR_RootConstrainSelectedInstOperands,
     /*  637407 */     // GIR_Coverage, 13284,
     /*  637407 */     GIR_EraseRootFromParent_Done,
     /*  637408 */   // Label 9932: @637408
     /*  637408 */   GIM_Try, /*On fail goto*//*Label 9933*/ GIMT_Encode4(637464), // Rule ID 13290 //
     /*  637413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  637416 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637438 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN),
     /*  637441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637448 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  637458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637462 */     GIR_RootConstrainSelectedInstOperands,
     /*  637463 */     // GIR_Coverage, 13290,
     /*  637463 */     GIR_EraseRootFromParent_Done,
     /*  637464 */   // Label 9933: @637464
     /*  637464 */   GIM_Try, /*On fail goto*//*Label 9934*/ GIMT_Encode4(637520), // Rule ID 13291 //
     /*  637469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  637472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637494 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN),
     /*  637497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637504 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  637514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637518 */     GIR_RootConstrainSelectedInstOperands,
     /*  637519 */     // GIR_Coverage, 13291,
     /*  637519 */     GIR_EraseRootFromParent_Done,
     /*  637520 */   // Label 9934: @637520
     /*  637520 */   GIM_Try, /*On fail goto*//*Label 9935*/ GIMT_Encode4(637576), // Rule ID 13292 //
     /*  637525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  637528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637539 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637550 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN),
     /*  637553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637560 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  637570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637574 */     GIR_RootConstrainSelectedInstOperands,
     /*  637575 */     // GIR_Coverage, 13292,
     /*  637575 */     GIR_EraseRootFromParent_Done,
     /*  637576 */   // Label 9935: @637576
     /*  637576 */   GIM_Try, /*On fail goto*//*Label 9936*/ GIMT_Encode4(637632), // Rule ID 13293 //
     /*  637581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  637584 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637606 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN),
     /*  637609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637616 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  637626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637630 */     GIR_RootConstrainSelectedInstOperands,
     /*  637631 */     // GIR_Coverage, 13293,
     /*  637631 */     GIR_EraseRootFromParent_Done,
     /*  637632 */   // Label 9936: @637632
     /*  637632 */   GIM_Try, /*On fail goto*//*Label 9937*/ GIMT_Encode4(637688), // Rule ID 13294 //
     /*  637637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  637640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  637651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  637662 */     // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  637662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN),
     /*  637665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  637667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  637672 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  637679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  637682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637686 */     GIR_RootConstrainSelectedInstOperands,
     /*  637687 */     // GIR_Coverage, 13294,
     /*  637687 */     GIR_EraseRootFromParent_Done,
     /*  637688 */   // Label 9937: @637688
     /*  637688 */   GIM_Try, /*On fail goto*//*Label 9938*/ GIMT_Encode4(637748), // Rule ID 10877 //
     /*  637693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  637696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637704 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  637717 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  637720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637725 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637746 */     GIR_RootConstrainSelectedInstOperands,
     /*  637747 */     // GIR_Coverage, 10877,
     /*  637747 */     GIR_EraseRootFromParent_Done,
     /*  637748 */   // Label 9938: @637748
     /*  637748 */   GIM_Try, /*On fail goto*//*Label 9939*/ GIMT_Encode4(637808), // Rule ID 10878 //
     /*  637753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  637756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637764 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  637777 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  637780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637785 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637806 */     GIR_RootConstrainSelectedInstOperands,
     /*  637807 */     // GIR_Coverage, 10878,
     /*  637807 */     GIR_EraseRootFromParent_Done,
     /*  637808 */   // Label 9939: @637808
     /*  637808 */   GIM_Try, /*On fail goto*//*Label 9940*/ GIMT_Encode4(637868), // Rule ID 10879 //
     /*  637813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  637816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637824 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  637837 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  637840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637845 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637866 */     GIR_RootConstrainSelectedInstOperands,
     /*  637867 */     // GIR_Coverage, 10879,
     /*  637867 */     GIR_EraseRootFromParent_Done,
     /*  637868 */   // Label 9940: @637868
     /*  637868 */   GIM_Try, /*On fail goto*//*Label 9941*/ GIMT_Encode4(637928), // Rule ID 10880 //
     /*  637873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  637876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637884 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  637897 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  637900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637905 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637926 */     GIR_RootConstrainSelectedInstOperands,
     /*  637927 */     // GIR_Coverage, 10880,
     /*  637927 */     GIR_EraseRootFromParent_Done,
     /*  637928 */   // Label 9941: @637928
     /*  637928 */   GIM_Try, /*On fail goto*//*Label 9942*/ GIMT_Encode4(637988), // Rule ID 10881 //
     /*  637933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  637936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  637944 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  637946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  637950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  637957 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  637957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  637960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  637965 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  637967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  637972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  637977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  637982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  637986 */     GIR_RootConstrainSelectedInstOperands,
     /*  637987 */     // GIR_Coverage, 10881,
     /*  637987 */     GIR_EraseRootFromParent_Done,
     /*  637988 */   // Label 9942: @637988
     /*  637988 */   GIM_Try, /*On fail goto*//*Label 9943*/ GIMT_Encode4(638047), // Rule ID 11433 //
     /*  637993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  637996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638003 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  638016 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  638019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638024 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638045 */     GIR_RootConstrainSelectedInstOperands,
     /*  638046 */     // GIR_Coverage, 11433,
     /*  638046 */     GIR_EraseRootFromParent_Done,
     /*  638047 */   // Label 9943: @638047
     /*  638047 */   GIM_Try, /*On fail goto*//*Label 9944*/ GIMT_Encode4(638106), // Rule ID 11434 //
     /*  638052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  638055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638062 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  638075 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  638078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638083 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638104 */     GIR_RootConstrainSelectedInstOperands,
     /*  638105 */     // GIR_Coverage, 11434,
     /*  638105 */     GIR_EraseRootFromParent_Done,
     /*  638106 */   // Label 9944: @638106
     /*  638106 */   GIM_Try, /*On fail goto*//*Label 9945*/ GIMT_Encode4(638165), // Rule ID 11435 //
     /*  638111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  638114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638121 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638127 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  638134 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  638137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638142 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638163 */     GIR_RootConstrainSelectedInstOperands,
     /*  638164 */     // GIR_Coverage, 11435,
     /*  638164 */     GIR_EraseRootFromParent_Done,
     /*  638165 */   // Label 9945: @638165
     /*  638165 */   GIM_Try, /*On fail goto*//*Label 9946*/ GIMT_Encode4(638224), // Rule ID 11436 //
     /*  638170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  638173 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638180 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  638193 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  638196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638201 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638222 */     GIR_RootConstrainSelectedInstOperands,
     /*  638223 */     // GIR_Coverage, 11436,
     /*  638223 */     GIR_EraseRootFromParent_Done,
     /*  638224 */   // Label 9946: @638224
     /*  638224 */   GIM_Try, /*On fail goto*//*Label 9947*/ GIMT_Encode4(638283), // Rule ID 11437 //
     /*  638229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  638232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638239 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638241 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  638252 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR),
     /*  638255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638260 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638281 */     GIR_RootConstrainSelectedInstOperands,
     /*  638282 */     // GIR_Coverage, 11437,
     /*  638282 */     GIR_EraseRootFromParent_Done,
     /*  638283 */   // Label 9947: @638283
     /*  638283 */   GIM_Try, /*On fail goto*//*Label 9948*/ GIMT_Encode4(638347), // Rule ID 10867 //
     /*  638288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  638291 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638314 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638324 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638345 */     GIR_RootConstrainSelectedInstOperands,
     /*  638346 */     // GIR_Coverage, 10867,
     /*  638346 */     GIR_EraseRootFromParent_Done,
     /*  638347 */   // Label 9948: @638347
     /*  638347 */   GIM_Try, /*On fail goto*//*Label 9949*/ GIMT_Encode4(638411), // Rule ID 10868 //
     /*  638352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  638355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638371 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638378 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638388 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638405 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638409 */     GIR_RootConstrainSelectedInstOperands,
     /*  638410 */     // GIR_Coverage, 10868,
     /*  638410 */     GIR_EraseRootFromParent_Done,
     /*  638411 */   // Label 9949: @638411
     /*  638411 */   GIM_Try, /*On fail goto*//*Label 9950*/ GIMT_Encode4(638475), // Rule ID 10869 //
     /*  638416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  638419 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638442 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638452 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638469 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638473 */     GIR_RootConstrainSelectedInstOperands,
     /*  638474 */     // GIR_Coverage, 10869,
     /*  638474 */     GIR_EraseRootFromParent_Done,
     /*  638475 */   // Label 9950: @638475
     /*  638475 */   GIM_Try, /*On fail goto*//*Label 9951*/ GIMT_Encode4(638539), // Rule ID 10870 //
     /*  638480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  638483 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638506 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638516 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638537 */     GIR_RootConstrainSelectedInstOperands,
     /*  638538 */     // GIR_Coverage, 10870,
     /*  638538 */     GIR_EraseRootFromParent_Done,
     /*  638539 */   // Label 9951: @638539
     /*  638539 */   GIM_Try, /*On fail goto*//*Label 9952*/ GIMT_Encode4(638603), // Rule ID 10871 //
     /*  638544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  638547 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638570 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638580 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638601 */     GIR_RootConstrainSelectedInstOperands,
     /*  638602 */     // GIR_Coverage, 10871,
     /*  638602 */     GIR_EraseRootFromParent_Done,
     /*  638603 */   // Label 9952: @638603
     /*  638603 */   GIM_Try, /*On fail goto*//*Label 9953*/ GIMT_Encode4(638666), // Rule ID 11423 //
     /*  638608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  638611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638626 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638633 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638643 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638664 */     GIR_RootConstrainSelectedInstOperands,
     /*  638665 */     // GIR_Coverage, 11423,
     /*  638665 */     GIR_EraseRootFromParent_Done,
     /*  638666 */   // Label 9953: @638666
     /*  638666 */   GIM_Try, /*On fail goto*//*Label 9954*/ GIMT_Encode4(638729), // Rule ID 11424 //
     /*  638671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  638674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638696 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638706 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638727 */     GIR_RootConstrainSelectedInstOperands,
     /*  638728 */     // GIR_Coverage, 11424,
     /*  638728 */     GIR_EraseRootFromParent_Done,
     /*  638729 */   // Label 9954: @638729
     /*  638729 */   GIM_Try, /*On fail goto*//*Label 9955*/ GIMT_Encode4(638792), // Rule ID 11425 //
     /*  638734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  638737 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638759 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638769 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638790 */     GIR_RootConstrainSelectedInstOperands,
     /*  638791 */     // GIR_Coverage, 11425,
     /*  638791 */     GIR_EraseRootFromParent_Done,
     /*  638792 */   // Label 9955: @638792
     /*  638792 */   GIM_Try, /*On fail goto*//*Label 9956*/ GIMT_Encode4(638855), // Rule ID 11426 //
     /*  638797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  638800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638822 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638832 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638853 */     GIR_RootConstrainSelectedInstOperands,
     /*  638854 */     // GIR_Coverage, 11426,
     /*  638854 */     GIR_EraseRootFromParent_Done,
     /*  638855 */   // Label 9956: @638855
     /*  638855 */   GIM_Try, /*On fail goto*//*Label 9957*/ GIMT_Encode4(638918), // Rule ID 11427 //
     /*  638860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  638863 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  638874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  638885 */     // (atomic_load_or:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  638885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_SADDR_RTN),
     /*  638888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  638890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  638895 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  638902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  638907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  638912 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638916 */     GIR_RootConstrainSelectedInstOperands,
     /*  638917 */     // GIR_Coverage, 11427,
     /*  638917 */     GIR_EraseRootFromParent_Done,
     /*  638918 */   // Label 9957: @638918
     /*  638918 */   GIM_Try, /*On fail goto*//*Label 9958*/ GIMT_Encode4(638971), // Rule ID 10872 //
     /*  638923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  638926 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638934 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  638947 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  638947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  638950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  638955 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  638957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  638962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  638965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  638969 */     GIR_RootConstrainSelectedInstOperands,
     /*  638970 */     // GIR_Coverage, 10872,
     /*  638970 */     GIR_EraseRootFromParent_Done,
     /*  638971 */   // Label 9958: @638971
     /*  638971 */   GIM_Try, /*On fail goto*//*Label 9959*/ GIMT_Encode4(639024), // Rule ID 10873 //
     /*  638976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  638979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  638987 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  638989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  638993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639000 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639008 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639022 */     GIR_RootConstrainSelectedInstOperands,
     /*  639023 */     // GIR_Coverage, 10873,
     /*  639023 */     GIR_EraseRootFromParent_Done,
     /*  639024 */   // Label 9959: @639024
     /*  639024 */   GIM_Try, /*On fail goto*//*Label 9960*/ GIMT_Encode4(639077), // Rule ID 10874 //
     /*  639029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  639032 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639040 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639042 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639046 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639053 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639061 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639075 */     GIR_RootConstrainSelectedInstOperands,
     /*  639076 */     // GIR_Coverage, 10874,
     /*  639076 */     GIR_EraseRootFromParent_Done,
     /*  639077 */   // Label 9960: @639077
     /*  639077 */   GIM_Try, /*On fail goto*//*Label 9961*/ GIMT_Encode4(639130), // Rule ID 10875 //
     /*  639082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  639085 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639093 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639106 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639114 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639128 */     GIR_RootConstrainSelectedInstOperands,
     /*  639129 */     // GIR_Coverage, 10875,
     /*  639129 */     GIR_EraseRootFromParent_Done,
     /*  639130 */   // Label 9961: @639130
     /*  639130 */   GIM_Try, /*On fail goto*//*Label 9962*/ GIMT_Encode4(639183), // Rule ID 10876 //
     /*  639135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  639138 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639146 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639152 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639159 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639167 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639181 */     GIR_RootConstrainSelectedInstOperands,
     /*  639182 */     // GIR_Coverage, 10876,
     /*  639182 */     GIR_EraseRootFromParent_Done,
     /*  639183 */   // Label 9962: @639183
     /*  639183 */   GIM_Try, /*On fail goto*//*Label 9963*/ GIMT_Encode4(639235), // Rule ID 11428 //
     /*  639188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  639191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639198 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639200 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639211 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639219 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639233 */     GIR_RootConstrainSelectedInstOperands,
     /*  639234 */     // GIR_Coverage, 11428,
     /*  639234 */     GIR_EraseRootFromParent_Done,
     /*  639235 */   // Label 9963: @639235
     /*  639235 */   GIM_Try, /*On fail goto*//*Label 9964*/ GIMT_Encode4(639287), // Rule ID 11429 //
     /*  639240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  639243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639250 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639263 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639271 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639281 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639285 */     GIR_RootConstrainSelectedInstOperands,
     /*  639286 */     // GIR_Coverage, 11429,
     /*  639286 */     GIR_EraseRootFromParent_Done,
     /*  639287 */   // Label 9964: @639287
     /*  639287 */   GIM_Try, /*On fail goto*//*Label 9965*/ GIMT_Encode4(639339), // Rule ID 11430 //
     /*  639292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  639295 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639302 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639304 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639308 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639315 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639323 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639337 */     GIR_RootConstrainSelectedInstOperands,
     /*  639338 */     // GIR_Coverage, 11430,
     /*  639338 */     GIR_EraseRootFromParent_Done,
     /*  639339 */   // Label 9965: @639339
     /*  639339 */   GIM_Try, /*On fail goto*//*Label 9966*/ GIMT_Encode4(639391), // Rule ID 11431 //
     /*  639344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  639347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639354 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639367 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639375 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639389 */     GIR_RootConstrainSelectedInstOperands,
     /*  639390 */     // GIR_Coverage, 11431,
     /*  639390 */     GIR_EraseRootFromParent_Done,
     /*  639391 */   // Label 9966: @639391
     /*  639391 */   GIM_Try, /*On fail goto*//*Label 9967*/ GIMT_Encode4(639443), // Rule ID 11432 //
     /*  639396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  639399 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639406 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  639408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639419 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
     /*  639422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639427 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  639437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639441 */     GIR_RootConstrainSelectedInstOperands,
     /*  639442 */     // GIR_Coverage, 11432,
     /*  639442 */     GIR_EraseRootFromParent_Done,
     /*  639443 */   // Label 9967: @639443
     /*  639443 */   GIM_Try, /*On fail goto*//*Label 9968*/ GIMT_Encode4(639500), // Rule ID 10862 //
     /*  639448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  639451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639474 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639484 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639498 */     GIR_RootConstrainSelectedInstOperands,
     /*  639499 */     // GIR_Coverage, 10862,
     /*  639499 */     GIR_EraseRootFromParent_Done,
     /*  639500 */   // Label 9968: @639500
     /*  639500 */   GIM_Try, /*On fail goto*//*Label 9969*/ GIMT_Encode4(639557), // Rule ID 10863 //
     /*  639505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  639508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639531 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639541 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639555 */     GIR_RootConstrainSelectedInstOperands,
     /*  639556 */     // GIR_Coverage, 10863,
     /*  639556 */     GIR_EraseRootFromParent_Done,
     /*  639557 */   // Label 9969: @639557
     /*  639557 */   GIM_Try, /*On fail goto*//*Label 9970*/ GIMT_Encode4(639614), // Rule ID 10864 //
     /*  639562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  639565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639588 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639598 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639605 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639608 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639612 */     GIR_RootConstrainSelectedInstOperands,
     /*  639613 */     // GIR_Coverage, 10864,
     /*  639613 */     GIR_EraseRootFromParent_Done,
     /*  639614 */   // Label 9970: @639614
     /*  639614 */   GIM_Try, /*On fail goto*//*Label 9971*/ GIMT_Encode4(639671), // Rule ID 10865 //
     /*  639619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  639622 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639638 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639645 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639655 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639662 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639669 */     GIR_RootConstrainSelectedInstOperands,
     /*  639670 */     // GIR_Coverage, 10865,
     /*  639670 */     GIR_EraseRootFromParent_Done,
     /*  639671 */   // Label 9971: @639671
     /*  639671 */   GIM_Try, /*On fail goto*//*Label 9972*/ GIMT_Encode4(639728), // Rule ID 10866 //
     /*  639676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  639679 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639702 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639712 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639726 */     GIR_RootConstrainSelectedInstOperands,
     /*  639727 */     // GIR_Coverage, 10866,
     /*  639727 */     GIR_EraseRootFromParent_Done,
     /*  639728 */   // Label 9972: @639728
     /*  639728 */   GIM_Try, /*On fail goto*//*Label 9973*/ GIMT_Encode4(639784), // Rule ID 11418 //
     /*  639733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  639736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639758 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639768 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639782 */     GIR_RootConstrainSelectedInstOperands,
     /*  639783 */     // GIR_Coverage, 11418,
     /*  639783 */     GIR_EraseRootFromParent_Done,
     /*  639784 */   // Label 9973: @639784
     /*  639784 */   GIM_Try, /*On fail goto*//*Label 9974*/ GIMT_Encode4(639840), // Rule ID 11419 //
     /*  639789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  639792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639814 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639824 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639838 */     GIR_RootConstrainSelectedInstOperands,
     /*  639839 */     // GIR_Coverage, 11419,
     /*  639839 */     GIR_EraseRootFromParent_Done,
     /*  639840 */   // Label 9974: @639840
     /*  639840 */   GIM_Try, /*On fail goto*//*Label 9975*/ GIMT_Encode4(639896), // Rule ID 11420 //
     /*  639845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  639848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639870 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639880 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639894 */     GIR_RootConstrainSelectedInstOperands,
     /*  639895 */     // GIR_Coverage, 11420,
     /*  639895 */     GIR_EraseRootFromParent_Done,
     /*  639896 */   // Label 9975: @639896
     /*  639896 */   GIM_Try, /*On fail goto*//*Label 9976*/ GIMT_Encode4(639952), // Rule ID 11421 //
     /*  639901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  639904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639926 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639936 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  639946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  639950 */     GIR_RootConstrainSelectedInstOperands,
     /*  639951 */     // GIR_Coverage, 11421,
     /*  639951 */     GIR_EraseRootFromParent_Done,
     /*  639952 */   // Label 9976: @639952
     /*  639952 */   GIM_Try, /*On fail goto*//*Label 9977*/ GIMT_Encode4(640008), // Rule ID 11422 //
     /*  639957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  639960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  639967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  639971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  639975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  639982 */     // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  639982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
     /*  639985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  639987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  639992 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  639994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  639999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  640002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640006 */     GIR_RootConstrainSelectedInstOperands,
     /*  640007 */     // GIR_Coverage, 11422,
     /*  640007 */     GIR_EraseRootFromParent_Done,
     /*  640008 */   // Label 9977: @640008
     /*  640008 */   GIM_Reject,
     /*  640009 */ // Label 9847: @640009
     /*  640009 */ GIM_Reject,
     /*  640010 */ // Label 9739: @640010
     /*  640010 */ GIM_Reject,
     /*  640011 */ // Label 24: @640011
     /*  640011 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 9980*/ GIMT_Encode4(653622),
     /*  640022 */ /*GILLT_s32*//*Label 9978*/ GIMT_Encode4(640030),
     /*  640026 */ /*GILLT_s64*//*Label 9979*/ GIMT_Encode4(646122),
     /*  640030 */ // Label 9978: @640030
     /*  640030 */ GIM_Try, /*On fail goto*//*Label 9981*/ GIMT_Encode4(646121),
     /*  640035 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  640038 */   GIM_Try, /*On fail goto*//*Label 9982*/ GIMT_Encode4(640100), // Rule ID 21098 //
     /*  640043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  640046 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640053 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640066 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64),
     /*  640069 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640098 */     GIR_RootConstrainSelectedInstOperands,
     /*  640099 */     // GIR_Coverage, 21098,
     /*  640099 */     GIR_EraseRootFromParent_Done,
     /*  640100 */   // Label 9982: @640100
     /*  640100 */   GIM_Try, /*On fail goto*//*Label 9983*/ GIMT_Encode4(640162), // Rule ID 21099 //
     /*  640105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  640108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640115 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640128 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64),
     /*  640131 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640160 */     GIR_RootConstrainSelectedInstOperands,
     /*  640161 */     // GIR_Coverage, 21099,
     /*  640161 */     GIR_EraseRootFromParent_Done,
     /*  640162 */   // Label 9983: @640162
     /*  640162 */   GIM_Try, /*On fail goto*//*Label 9984*/ GIMT_Encode4(640224), // Rule ID 21100 //
     /*  640167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  640170 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640177 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640190 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64),
     /*  640193 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640222 */     GIR_RootConstrainSelectedInstOperands,
     /*  640223 */     // GIR_Coverage, 21100,
     /*  640223 */     GIR_EraseRootFromParent_Done,
     /*  640224 */   // Label 9984: @640224
     /*  640224 */   GIM_Try, /*On fail goto*//*Label 9985*/ GIMT_Encode4(640286), // Rule ID 21101 //
     /*  640229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  640232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640239 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640241 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640252 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64),
     /*  640255 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640284 */     GIR_RootConstrainSelectedInstOperands,
     /*  640285 */     // GIR_Coverage, 21101,
     /*  640285 */     GIR_EraseRootFromParent_Done,
     /*  640286 */   // Label 9985: @640286
     /*  640286 */   GIM_Try, /*On fail goto*//*Label 9986*/ GIMT_Encode4(640348), // Rule ID 21102 //
     /*  640291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  640294 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640301 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640314 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64),
     /*  640317 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640342 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640346 */     GIR_RootConstrainSelectedInstOperands,
     /*  640347 */     // GIR_Coverage, 21102,
     /*  640347 */     GIR_EraseRootFromParent_Done,
     /*  640348 */   // Label 9986: @640348
     /*  640348 */   GIM_Try, /*On fail goto*//*Label 9987*/ GIMT_Encode4(640410), // Rule ID 21118 //
     /*  640353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  640356 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640363 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640376 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64),
     /*  640379 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640408 */     GIR_RootConstrainSelectedInstOperands,
     /*  640409 */     // GIR_Coverage, 21118,
     /*  640409 */     GIR_EraseRootFromParent_Done,
     /*  640410 */   // Label 9987: @640410
     /*  640410 */   GIM_Try, /*On fail goto*//*Label 9988*/ GIMT_Encode4(640472), // Rule ID 21119 //
     /*  640415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  640418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640425 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640438 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64),
     /*  640441 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640470 */     GIR_RootConstrainSelectedInstOperands,
     /*  640471 */     // GIR_Coverage, 21119,
     /*  640471 */     GIR_EraseRootFromParent_Done,
     /*  640472 */   // Label 9988: @640472
     /*  640472 */   GIM_Try, /*On fail goto*//*Label 9989*/ GIMT_Encode4(640534), // Rule ID 21120 //
     /*  640477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  640480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640487 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640500 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64),
     /*  640503 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640532 */     GIR_RootConstrainSelectedInstOperands,
     /*  640533 */     // GIR_Coverage, 21120,
     /*  640533 */     GIR_EraseRootFromParent_Done,
     /*  640534 */   // Label 9989: @640534
     /*  640534 */   GIM_Try, /*On fail goto*//*Label 9990*/ GIMT_Encode4(640596), // Rule ID 21121 //
     /*  640539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  640542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640549 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640562 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64),
     /*  640565 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640594 */     GIR_RootConstrainSelectedInstOperands,
     /*  640595 */     // GIR_Coverage, 21121,
     /*  640595 */     GIR_EraseRootFromParent_Done,
     /*  640596 */   // Label 9990: @640596
     /*  640596 */   GIM_Try, /*On fail goto*//*Label 9991*/ GIMT_Encode4(640658), // Rule ID 21122 //
     /*  640601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  640604 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640611 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  640613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640624 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64),
     /*  640627 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  640652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640656 */     GIR_RootConstrainSelectedInstOperands,
     /*  640657 */     // GIR_Coverage, 21122,
     /*  640657 */     GIR_EraseRootFromParent_Done,
     /*  640658 */   // Label 9991: @640658
     /*  640658 */   GIM_Try, /*On fail goto*//*Label 9992*/ GIMT_Encode4(640724), // Rule ID 21088 //
     /*  640663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  640666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  640677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640688 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN),
     /*  640691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  640693 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  640718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640722 */     GIR_RootConstrainSelectedInstOperands,
     /*  640723 */     // GIR_Coverage, 21088,
     /*  640723 */     GIR_EraseRootFromParent_Done,
     /*  640724 */   // Label 9992: @640724
     /*  640724 */   GIM_Try, /*On fail goto*//*Label 9993*/ GIMT_Encode4(640790), // Rule ID 21089 //
     /*  640729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  640732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  640743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640754 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN),
     /*  640757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  640759 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  640784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640788 */     GIR_RootConstrainSelectedInstOperands,
     /*  640789 */     // GIR_Coverage, 21089,
     /*  640789 */     GIR_EraseRootFromParent_Done,
     /*  640790 */   // Label 9993: @640790
     /*  640790 */   GIM_Try, /*On fail goto*//*Label 9994*/ GIMT_Encode4(640856), // Rule ID 21090 //
     /*  640795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  640798 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  640809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640820 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN),
     /*  640823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  640825 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  640850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640854 */     GIR_RootConstrainSelectedInstOperands,
     /*  640855 */     // GIR_Coverage, 21090,
     /*  640855 */     GIR_EraseRootFromParent_Done,
     /*  640856 */   // Label 9994: @640856
     /*  640856 */   GIM_Try, /*On fail goto*//*Label 9995*/ GIMT_Encode4(640922), // Rule ID 21091 //
     /*  640861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  640864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  640875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640886 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN),
     /*  640889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  640891 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  640916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640920 */     GIR_RootConstrainSelectedInstOperands,
     /*  640921 */     // GIR_Coverage, 21091,
     /*  640921 */     GIR_EraseRootFromParent_Done,
     /*  640922 */   // Label 9995: @640922
     /*  640922 */   GIM_Try, /*On fail goto*//*Label 9996*/ GIMT_Encode4(640988), // Rule ID 21092 //
     /*  640927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  640930 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  640937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  640941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  640945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  640952 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  640952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN),
     /*  640955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  640957 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  640959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  640964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  640969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  640974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  640979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  640982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  640986 */     GIR_RootConstrainSelectedInstOperands,
     /*  640987 */     // GIR_Coverage, 21092,
     /*  640987 */     GIR_EraseRootFromParent_Done,
     /*  640988 */   // Label 9996: @640988
     /*  640988 */   GIM_Try, /*On fail goto*//*Label 9997*/ GIMT_Encode4(641054), // Rule ID 21108 //
     /*  640993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  640996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  641018 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN),
     /*  641021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641023 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  641030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  641040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  641045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  641048 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641052 */     GIR_RootConstrainSelectedInstOperands,
     /*  641053 */     // GIR_Coverage, 21108,
     /*  641053 */     GIR_EraseRootFromParent_Done,
     /*  641054 */   // Label 9997: @641054
     /*  641054 */   GIM_Try, /*On fail goto*//*Label 9998*/ GIMT_Encode4(641120), // Rule ID 21109 //
     /*  641059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  641062 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  641084 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN),
     /*  641087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641089 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  641096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  641106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  641111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  641114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641118 */     GIR_RootConstrainSelectedInstOperands,
     /*  641119 */     // GIR_Coverage, 21109,
     /*  641119 */     GIR_EraseRootFromParent_Done,
     /*  641120 */   // Label 9998: @641120
     /*  641120 */   GIM_Try, /*On fail goto*//*Label 9999*/ GIMT_Encode4(641186), // Rule ID 21110 //
     /*  641125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  641128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  641150 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN),
     /*  641153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641155 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  641162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  641172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  641177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  641180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641184 */     GIR_RootConstrainSelectedInstOperands,
     /*  641185 */     // GIR_Coverage, 21110,
     /*  641185 */     GIR_EraseRootFromParent_Done,
     /*  641186 */   // Label 9999: @641186
     /*  641186 */   GIM_Try, /*On fail goto*//*Label 10000*/ GIMT_Encode4(641252), // Rule ID 21111 //
     /*  641191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  641194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  641216 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN),
     /*  641219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641221 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  641228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  641238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  641243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  641246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641250 */     GIR_RootConstrainSelectedInstOperands,
     /*  641251 */     // GIR_Coverage, 21111,
     /*  641251 */     GIR_EraseRootFromParent_Done,
     /*  641252 */   // Label 10000: @641252
     /*  641252 */   GIM_Try, /*On fail goto*//*Label 10001*/ GIMT_Encode4(641318), // Rule ID 21112 //
     /*  641257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  641260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  641282 */     // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN),
     /*  641285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641287 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  641294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  641304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  641309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  641312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641316 */     GIR_RootConstrainSelectedInstOperands,
     /*  641317 */     // GIR_Coverage, 21112,
     /*  641317 */     GIR_EraseRootFromParent_Done,
     /*  641318 */   // Label 10001: @641318
     /*  641318 */   GIM_Try, /*On fail goto*//*Label 10002*/ GIMT_Encode4(641375), // Rule ID 21093 //
     /*  641323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  641326 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641333 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641335 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641346 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
     /*  641349 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641369 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641373 */     GIR_RootConstrainSelectedInstOperands,
     /*  641374 */     // GIR_Coverage, 21093,
     /*  641374 */     GIR_EraseRootFromParent_Done,
     /*  641375 */   // Label 10002: @641375
     /*  641375 */   GIM_Try, /*On fail goto*//*Label 10003*/ GIMT_Encode4(641432), // Rule ID 21094 //
     /*  641380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  641383 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641390 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641396 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641403 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
     /*  641406 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641430 */     GIR_RootConstrainSelectedInstOperands,
     /*  641431 */     // GIR_Coverage, 21094,
     /*  641431 */     GIR_EraseRootFromParent_Done,
     /*  641432 */   // Label 10003: @641432
     /*  641432 */   GIM_Try, /*On fail goto*//*Label 10004*/ GIMT_Encode4(641489), // Rule ID 21095 //
     /*  641437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  641440 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641447 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641460 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
     /*  641463 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641487 */     GIR_RootConstrainSelectedInstOperands,
     /*  641488 */     // GIR_Coverage, 21095,
     /*  641488 */     GIR_EraseRootFromParent_Done,
     /*  641489 */   // Label 10004: @641489
     /*  641489 */   GIM_Try, /*On fail goto*//*Label 10005*/ GIMT_Encode4(641546), // Rule ID 21096 //
     /*  641494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  641497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641504 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641517 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
     /*  641520 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641544 */     GIR_RootConstrainSelectedInstOperands,
     /*  641545 */     // GIR_Coverage, 21096,
     /*  641545 */     GIR_EraseRootFromParent_Done,
     /*  641546 */   // Label 10005: @641546
     /*  641546 */   GIM_Try, /*On fail goto*//*Label 10006*/ GIMT_Encode4(641603), // Rule ID 21097 //
     /*  641551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  641554 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641561 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641574 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
     /*  641577 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641601 */     GIR_RootConstrainSelectedInstOperands,
     /*  641602 */     // GIR_Coverage, 21097,
     /*  641602 */     GIR_EraseRootFromParent_Done,
     /*  641603 */   // Label 10006: @641603
     /*  641603 */   GIM_Try, /*On fail goto*//*Label 10007*/ GIMT_Encode4(641660), // Rule ID 21113 //
     /*  641608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  641611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641618 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641631 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
     /*  641634 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641654 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641658 */     GIR_RootConstrainSelectedInstOperands,
     /*  641659 */     // GIR_Coverage, 21113,
     /*  641659 */     GIR_EraseRootFromParent_Done,
     /*  641660 */   // Label 10007: @641660
     /*  641660 */   GIM_Try, /*On fail goto*//*Label 10008*/ GIMT_Encode4(641717), // Rule ID 21114 //
     /*  641665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  641668 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641675 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641688 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
     /*  641691 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641715 */     GIR_RootConstrainSelectedInstOperands,
     /*  641716 */     // GIR_Coverage, 21114,
     /*  641716 */     GIR_EraseRootFromParent_Done,
     /*  641717 */   // Label 10008: @641717
     /*  641717 */   GIM_Try, /*On fail goto*//*Label 10009*/ GIMT_Encode4(641774), // Rule ID 21115 //
     /*  641722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  641725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641732 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641745 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
     /*  641748 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641772 */     GIR_RootConstrainSelectedInstOperands,
     /*  641773 */     // GIR_Coverage, 21115,
     /*  641773 */     GIR_EraseRootFromParent_Done,
     /*  641774 */   // Label 10009: @641774
     /*  641774 */   GIM_Try, /*On fail goto*//*Label 10010*/ GIMT_Encode4(641831), // Rule ID 21116 //
     /*  641779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  641782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641789 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641802 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
     /*  641805 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641829 */     GIR_RootConstrainSelectedInstOperands,
     /*  641830 */     // GIR_Coverage, 21116,
     /*  641830 */     GIR_EraseRootFromParent_Done,
     /*  641831 */   // Label 10010: @641831
     /*  641831 */   GIM_Try, /*On fail goto*//*Label 10011*/ GIMT_Encode4(641888), // Rule ID 21117 //
     /*  641836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  641839 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641846 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  641848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641859 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
     /*  641862 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  641882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641886 */     GIR_RootConstrainSelectedInstOperands,
     /*  641887 */     // GIR_Coverage, 21117,
     /*  641887 */     GIR_EraseRootFromParent_Done,
     /*  641888 */   // Label 10011: @641888
     /*  641888 */   GIM_Try, /*On fail goto*//*Label 10012*/ GIMT_Encode4(641949), // Rule ID 21083 //
     /*  641893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  641896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641918 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
     /*  641921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641923 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  641940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  641943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  641947 */     GIR_RootConstrainSelectedInstOperands,
     /*  641948 */     // GIR_Coverage, 21083,
     /*  641948 */     GIR_EraseRootFromParent_Done,
     /*  641949 */   // Label 10012: @641949
     /*  641949 */   GIM_Try, /*On fail goto*//*Label 10013*/ GIMT_Encode4(642010), // Rule ID 21084 //
     /*  641954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  641957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  641964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  641968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  641972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  641979 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  641979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
     /*  641982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  641984 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  641986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  641991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  641996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642004 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642008 */     GIR_RootConstrainSelectedInstOperands,
     /*  642009 */     // GIR_Coverage, 21084,
     /*  642009 */     GIR_EraseRootFromParent_Done,
     /*  642010 */   // Label 10013: @642010
     /*  642010 */   GIM_Try, /*On fail goto*//*Label 10014*/ GIMT_Encode4(642071), // Rule ID 21085 //
     /*  642015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  642018 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642040 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
     /*  642043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642045 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642069 */     GIR_RootConstrainSelectedInstOperands,
     /*  642070 */     // GIR_Coverage, 21085,
     /*  642070 */     GIR_EraseRootFromParent_Done,
     /*  642071 */   // Label 10014: @642071
     /*  642071 */   GIM_Try, /*On fail goto*//*Label 10015*/ GIMT_Encode4(642132), // Rule ID 21086 //
     /*  642076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  642079 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642090 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642094 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642101 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
     /*  642104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642106 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642130 */     GIR_RootConstrainSelectedInstOperands,
     /*  642131 */     // GIR_Coverage, 21086,
     /*  642131 */     GIR_EraseRootFromParent_Done,
     /*  642132 */   // Label 10015: @642132
     /*  642132 */   GIM_Try, /*On fail goto*//*Label 10016*/ GIMT_Encode4(642193), // Rule ID 21087 //
     /*  642137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  642140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642162 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
     /*  642165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642167 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642191 */     GIR_RootConstrainSelectedInstOperands,
     /*  642192 */     // GIR_Coverage, 21087,
     /*  642192 */     GIR_EraseRootFromParent_Done,
     /*  642193 */   // Label 10016: @642193
     /*  642193 */   GIM_Try, /*On fail goto*//*Label 10017*/ GIMT_Encode4(642254), // Rule ID 21103 //
     /*  642198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  642201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642212 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642216 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642223 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
     /*  642226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642228 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642252 */     GIR_RootConstrainSelectedInstOperands,
     /*  642253 */     // GIR_Coverage, 21103,
     /*  642253 */     GIR_EraseRootFromParent_Done,
     /*  642254 */   // Label 10017: @642254
     /*  642254 */   GIM_Try, /*On fail goto*//*Label 10018*/ GIMT_Encode4(642315), // Rule ID 21104 //
     /*  642259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  642262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642284 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
     /*  642287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642289 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642313 */     GIR_RootConstrainSelectedInstOperands,
     /*  642314 */     // GIR_Coverage, 21104,
     /*  642314 */     GIR_EraseRootFromParent_Done,
     /*  642315 */   // Label 10018: @642315
     /*  642315 */   GIM_Try, /*On fail goto*//*Label 10019*/ GIMT_Encode4(642376), // Rule ID 21105 //
     /*  642320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  642323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642345 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
     /*  642348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642350 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642374 */     GIR_RootConstrainSelectedInstOperands,
     /*  642375 */     // GIR_Coverage, 21105,
     /*  642375 */     GIR_EraseRootFromParent_Done,
     /*  642376 */   // Label 10019: @642376
     /*  642376 */   GIM_Try, /*On fail goto*//*Label 10020*/ GIMT_Encode4(642437), // Rule ID 21106 //
     /*  642381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  642384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642406 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
     /*  642409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642411 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642435 */     GIR_RootConstrainSelectedInstOperands,
     /*  642436 */     // GIR_Coverage, 21106,
     /*  642436 */     GIR_EraseRootFromParent_Done,
     /*  642437 */   // Label 10020: @642437
     /*  642437 */   GIM_Try, /*On fail goto*//*Label 10021*/ GIMT_Encode4(642498), // Rule ID 21107 //
     /*  642442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  642445 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  642452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  642456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  642467 */     // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  642467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
     /*  642470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  642472 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  642474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  642479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  642484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  642489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  642492 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642496 */     GIR_RootConstrainSelectedInstOperands,
     /*  642497 */     // GIR_Coverage, 21107,
     /*  642497 */     GIR_EraseRootFromParent_Done,
     /*  642498 */   // Label 10021: @642498
     /*  642498 */   GIM_Try, /*On fail goto*//*Label 10022*/ GIMT_Encode4(642548), // Rule ID 30384 //
     /*  642503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  642506 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642511 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642524 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  642527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642532 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642546 */     GIR_RootConstrainSelectedInstOperands,
     /*  642547 */     // GIR_Coverage, 30384,
     /*  642547 */     GIR_EraseRootFromParent_Done,
     /*  642548 */   // Label 10022: @642548
     /*  642548 */   GIM_Try, /*On fail goto*//*Label 10023*/ GIMT_Encode4(642598), // Rule ID 30385 //
     /*  642553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  642556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642561 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642574 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  642577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642582 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642596 */     GIR_RootConstrainSelectedInstOperands,
     /*  642597 */     // GIR_Coverage, 30385,
     /*  642597 */     GIR_EraseRootFromParent_Done,
     /*  642598 */   // Label 10023: @642598
     /*  642598 */   GIM_Try, /*On fail goto*//*Label 10024*/ GIMT_Encode4(642648), // Rule ID 30386 //
     /*  642603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  642606 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642611 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642624 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  642627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642632 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642646 */     GIR_RootConstrainSelectedInstOperands,
     /*  642647 */     // GIR_Coverage, 30386,
     /*  642647 */     GIR_EraseRootFromParent_Done,
     /*  642648 */   // Label 10024: @642648
     /*  642648 */   GIM_Try, /*On fail goto*//*Label 10025*/ GIMT_Encode4(642698), // Rule ID 30387 //
     /*  642653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  642656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642661 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642674 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  642677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642682 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642692 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642696 */     GIR_RootConstrainSelectedInstOperands,
     /*  642697 */     // GIR_Coverage, 30387,
     /*  642697 */     GIR_EraseRootFromParent_Done,
     /*  642698 */   // Label 10025: @642698
     /*  642698 */   GIM_Try, /*On fail goto*//*Label 10026*/ GIMT_Encode4(642748), // Rule ID 30388 //
     /*  642703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  642706 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642711 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642724 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  642727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642732 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642746 */     GIR_RootConstrainSelectedInstOperands,
     /*  642747 */     // GIR_Coverage, 30388,
     /*  642747 */     GIR_EraseRootFromParent_Done,
     /*  642748 */   // Label 10026: @642748
     /*  642748 */   GIM_Try, /*On fail goto*//*Label 10027*/ GIMT_Encode4(642798), // Rule ID 30390 //
     /*  642753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  642756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642761 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642774 */     // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i32>>  =>  (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9),
     /*  642777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642782 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642796 */     GIR_RootConstrainSelectedInstOperands,
     /*  642797 */     // GIR_Coverage, 30390,
     /*  642797 */     GIR_EraseRootFromParent_Done,
     /*  642798 */   // Label 10027: @642798
     /*  642798 */   GIM_Try, /*On fail goto*//*Label 10028*/ GIMT_Encode4(642848), // Rule ID 30391 //
     /*  642803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  642806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642811 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642817 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642824 */     // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i32>>  =>  (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9),
     /*  642827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642832 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642839 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642842 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642846 */     GIR_RootConstrainSelectedInstOperands,
     /*  642847 */     // GIR_Coverage, 30391,
     /*  642847 */     GIR_EraseRootFromParent_Done,
     /*  642848 */   // Label 10028: @642848
     /*  642848 */   GIM_Try, /*On fail goto*//*Label 10029*/ GIMT_Encode4(642898), // Rule ID 30392 //
     /*  642853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  642856 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642861 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642874 */     // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i32>>  =>  (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9),
     /*  642877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642882 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642896 */     GIR_RootConstrainSelectedInstOperands,
     /*  642897 */     // GIR_Coverage, 30392,
     /*  642897 */     GIR_EraseRootFromParent_Done,
     /*  642898 */   // Label 10029: @642898
     /*  642898 */   GIM_Try, /*On fail goto*//*Label 10030*/ GIMT_Encode4(642948), // Rule ID 30393 //
     /*  642903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  642906 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642911 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642924 */     // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i32>>  =>  (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9),
     /*  642927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642932 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642946 */     GIR_RootConstrainSelectedInstOperands,
     /*  642947 */     // GIR_Coverage, 30393,
     /*  642947 */     GIR_EraseRootFromParent_Done,
     /*  642948 */   // Label 10030: @642948
     /*  642948 */   GIM_Try, /*On fail goto*//*Label 10031*/ GIMT_Encode4(642998), // Rule ID 30394 //
     /*  642953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  642956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  642961 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  642963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  642967 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  642974 */     // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i32>>  =>  (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  642974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9),
     /*  642977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  642982 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  642984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  642989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  642992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  642996 */     GIR_RootConstrainSelectedInstOperands,
     /*  642997 */     // GIR_Coverage, 30394,
     /*  642997 */     GIR_EraseRootFromParent_Done,
     /*  642998 */   // Label 10031: @642998
     /*  642998 */   GIM_Try, /*On fail goto*//*Label 10032*/ GIMT_Encode4(643048), // Rule ID 30396 //
     /*  643003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  643006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  643011 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643024 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  643024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  643027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643032 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  643042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643046 */     GIR_RootConstrainSelectedInstOperands,
     /*  643047 */     // GIR_Coverage, 30396,
     /*  643047 */     GIR_EraseRootFromParent_Done,
     /*  643048 */   // Label 10032: @643048
     /*  643048 */   GIM_Try, /*On fail goto*//*Label 10033*/ GIMT_Encode4(643098), // Rule ID 30397 //
     /*  643053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  643056 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  643061 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643074 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  643074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  643077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643082 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  643092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643096 */     GIR_RootConstrainSelectedInstOperands,
     /*  643097 */     // GIR_Coverage, 30397,
     /*  643097 */     GIR_EraseRootFromParent_Done,
     /*  643098 */   // Label 10033: @643098
     /*  643098 */   GIM_Try, /*On fail goto*//*Label 10034*/ GIMT_Encode4(643148), // Rule ID 30398 //
     /*  643103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  643106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  643111 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643124 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  643124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  643127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643132 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  643142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643146 */     GIR_RootConstrainSelectedInstOperands,
     /*  643147 */     // GIR_Coverage, 30398,
     /*  643147 */     GIR_EraseRootFromParent_Done,
     /*  643148 */   // Label 10034: @643148
     /*  643148 */   GIM_Try, /*On fail goto*//*Label 10035*/ GIMT_Encode4(643198), // Rule ID 30399 //
     /*  643153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  643156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  643161 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643174 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  643174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  643177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643182 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  643192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643196 */     GIR_RootConstrainSelectedInstOperands,
     /*  643197 */     // GIR_Coverage, 30399,
     /*  643197 */     GIR_EraseRootFromParent_Done,
     /*  643198 */   // Label 10035: @643198
     /*  643198 */   GIM_Try, /*On fail goto*//*Label 10036*/ GIMT_Encode4(643248), // Rule ID 30400 //
     /*  643203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  643206 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  643211 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643213 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643224 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  643224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
     /*  643227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643232 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  643242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643246 */     GIR_RootConstrainSelectedInstOperands,
     /*  643247 */     // GIR_Coverage, 30400,
     /*  643247 */     GIR_EraseRootFromParent_Done,
     /*  643248 */   // Label 10036: @643248
     /*  643248 */   GIM_Try, /*On fail goto*//*Label 10037*/ GIMT_Encode4(643302), // Rule ID 30383 //
     /*  643253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  643256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  643261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  643265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643276 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i32>>  =>  (DS_XOR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  643276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32),
     /*  643279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  643281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643286 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  643296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643300 */     GIR_RootConstrainSelectedInstOperands,
     /*  643301 */     // GIR_Coverage, 30383,
     /*  643301 */     GIR_EraseRootFromParent_Done,
     /*  643302 */   // Label 10037: @643302
     /*  643302 */   GIM_Try, /*On fail goto*//*Label 10038*/ GIMT_Encode4(643356), // Rule ID 30389 //
     /*  643307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  643310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  643315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  643319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643330 */     // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_i32>>  =>  (DS_XOR_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  643330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32_gfx9),
     /*  643333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  643335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643340 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  643350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643354 */     GIR_RootConstrainSelectedInstOperands,
     /*  643355 */     // GIR_Coverage, 30389,
     /*  643355 */     GIR_EraseRootFromParent_Done,
     /*  643356 */   // Label 10038: @643356
     /*  643356 */   GIM_Try, /*On fail goto*//*Label 10039*/ GIMT_Encode4(643410), // Rule ID 30395 //
     /*  643361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  643364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  643369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  643373 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  643384 */     // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i32>>  =>  (DS_XOR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  643384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32),
     /*  643387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  643389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  643394 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  643396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  643404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643408 */     GIR_RootConstrainSelectedInstOperands,
     /*  643409 */     // GIR_Coverage, 30395,
     /*  643409 */     GIR_EraseRootFromParent_Done,
     /*  643410 */   // Label 10039: @643410
     /*  643410 */   GIM_Try, /*On fail goto*//*Label 10040*/ GIMT_Encode4(643469), // Rule ID 13077 //
     /*  643415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  643418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643425 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  643438 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  643438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR),
     /*  643441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  643446 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  643453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  643458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  643463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643467 */     GIR_RootConstrainSelectedInstOperands,
     /*  643468 */     // GIR_Coverage, 13077,
     /*  643468 */     GIR_EraseRootFromParent_Done,
     /*  643469 */   // Label 10040: @643469
     /*  643469 */   GIM_Try, /*On fail goto*//*Label 10041*/ GIMT_Encode4(643528), // Rule ID 13078 //
     /*  643474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  643477 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643484 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643486 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  643497 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  643497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR),
     /*  643500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  643505 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  643512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  643517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  643522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643526 */     GIR_RootConstrainSelectedInstOperands,
     /*  643527 */     // GIR_Coverage, 13078,
     /*  643527 */     GIR_EraseRootFromParent_Done,
     /*  643528 */   // Label 10041: @643528
     /*  643528 */   GIM_Try, /*On fail goto*//*Label 10042*/ GIMT_Encode4(643587), // Rule ID 13079 //
     /*  643533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  643536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643543 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  643556 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  643556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR),
     /*  643559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  643564 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  643571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  643576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  643581 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643585 */     GIR_RootConstrainSelectedInstOperands,
     /*  643586 */     // GIR_Coverage, 13079,
     /*  643586 */     GIR_EraseRootFromParent_Done,
     /*  643587 */   // Label 10042: @643587
     /*  643587 */   GIM_Try, /*On fail goto*//*Label 10043*/ GIMT_Encode4(643646), // Rule ID 13080 //
     /*  643592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  643595 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643602 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643604 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643608 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  643615 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  643615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR),
     /*  643618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  643623 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  643630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  643635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  643640 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643644 */     GIR_RootConstrainSelectedInstOperands,
     /*  643645 */     // GIR_Coverage, 13080,
     /*  643645 */     GIR_EraseRootFromParent_Done,
     /*  643646 */   // Label 10043: @643646
     /*  643646 */   GIM_Try, /*On fail goto*//*Label 10044*/ GIMT_Encode4(643705), // Rule ID 13081 //
     /*  643651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  643654 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643661 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  643674 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  643674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR),
     /*  643677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  643682 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  643689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  643694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  643699 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643703 */     GIR_RootConstrainSelectedInstOperands,
     /*  643704 */     // GIR_Coverage, 13081,
     /*  643704 */     GIR_EraseRootFromParent_Done,
     /*  643705 */   // Label 10044: @643705
     /*  643705 */   GIM_Try, /*On fail goto*//*Label 10045*/ GIMT_Encode4(643768), // Rule ID 13087 //
     /*  643710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  643713 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  643724 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  643735 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  643735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN),
     /*  643738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  643740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  643745 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  643752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  643757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  643762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643766 */     GIR_RootConstrainSelectedInstOperands,
     /*  643767 */     // GIR_Coverage, 13087,
     /*  643767 */     GIR_EraseRootFromParent_Done,
     /*  643768 */   // Label 10045: @643768
     /*  643768 */   GIM_Try, /*On fail goto*//*Label 10046*/ GIMT_Encode4(643820), // Rule ID 13072 //
     /*  643773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  643776 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643783 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643785 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643789 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  643796 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  643796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR),
     /*  643799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  643804 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  643814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643818 */     GIR_RootConstrainSelectedInstOperands,
     /*  643819 */     // GIR_Coverage, 13072,
     /*  643819 */     GIR_EraseRootFromParent_Done,
     /*  643820 */   // Label 10046: @643820
     /*  643820 */   GIM_Try, /*On fail goto*//*Label 10047*/ GIMT_Encode4(643872), // Rule ID 13073 //
     /*  643825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  643828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  643848 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  643848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR),
     /*  643851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  643856 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  643866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643870 */     GIR_RootConstrainSelectedInstOperands,
     /*  643871 */     // GIR_Coverage, 13073,
     /*  643871 */     GIR_EraseRootFromParent_Done,
     /*  643872 */   // Label 10047: @643872
     /*  643872 */   GIM_Try, /*On fail goto*//*Label 10048*/ GIMT_Encode4(643924), // Rule ID 13074 //
     /*  643877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  643880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643887 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643889 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  643900 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  643900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR),
     /*  643903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  643908 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  643918 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643922 */     GIR_RootConstrainSelectedInstOperands,
     /*  643923 */     // GIR_Coverage, 13074,
     /*  643923 */     GIR_EraseRootFromParent_Done,
     /*  643924 */   // Label 10048: @643924
     /*  643924 */   GIM_Try, /*On fail goto*//*Label 10049*/ GIMT_Encode4(643976), // Rule ID 13075 //
     /*  643929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  643932 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643939 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  643952 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  643952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR),
     /*  643955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  643960 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  643962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  643967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  643970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  643974 */     GIR_RootConstrainSelectedInstOperands,
     /*  643975 */     // GIR_Coverage, 13075,
     /*  643975 */     GIR_EraseRootFromParent_Done,
     /*  643976 */   // Label 10049: @643976
     /*  643976 */   GIM_Try, /*On fail goto*//*Label 10050*/ GIMT_Encode4(644028), // Rule ID 13076 //
     /*  643981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  643984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  643991 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  643993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  643997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  644004 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (GLOBAL_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  644004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR),
     /*  644007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  644012 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  644019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  644022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644026 */     GIR_RootConstrainSelectedInstOperands,
     /*  644027 */     // GIR_Coverage, 13076,
     /*  644027 */     GIR_EraseRootFromParent_Done,
     /*  644028 */   // Label 10050: @644028
     /*  644028 */   GIM_Try, /*On fail goto*//*Label 10051*/ GIMT_Encode4(644084), // Rule ID 13082 //
     /*  644033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  644036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  644058 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  644058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN),
     /*  644061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  644063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  644068 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  644075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  644078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644082 */     GIR_RootConstrainSelectedInstOperands,
     /*  644083 */     // GIR_Coverage, 13082,
     /*  644083 */     GIR_EraseRootFromParent_Done,
     /*  644084 */   // Label 10051: @644084
     /*  644084 */   GIM_Try, /*On fail goto*//*Label 10052*/ GIMT_Encode4(644140), // Rule ID 13083 //
     /*  644089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  644092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  644114 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  644114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN),
     /*  644117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  644119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  644124 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  644131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  644134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644138 */     GIR_RootConstrainSelectedInstOperands,
     /*  644139 */     // GIR_Coverage, 13083,
     /*  644139 */     GIR_EraseRootFromParent_Done,
     /*  644140 */   // Label 10052: @644140
     /*  644140 */   GIM_Try, /*On fail goto*//*Label 10053*/ GIMT_Encode4(644196), // Rule ID 13084 //
     /*  644145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  644148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644159 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644163 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  644170 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  644170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN),
     /*  644173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  644175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  644180 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  644187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  644190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644194 */     GIR_RootConstrainSelectedInstOperands,
     /*  644195 */     // GIR_Coverage, 13084,
     /*  644195 */     GIR_EraseRootFromParent_Done,
     /*  644196 */   // Label 10053: @644196
     /*  644196 */   GIM_Try, /*On fail goto*//*Label 10054*/ GIMT_Encode4(644252), // Rule ID 13085 //
     /*  644201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  644204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644215 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  644226 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  644226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN),
     /*  644229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  644231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  644236 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  644243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  644246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644250 */     GIR_RootConstrainSelectedInstOperands,
     /*  644251 */     // GIR_Coverage, 13085,
     /*  644251 */     GIR_EraseRootFromParent_Done,
     /*  644252 */   // Label 10054: @644252
     /*  644252 */   GIM_Try, /*On fail goto*//*Label 10055*/ GIMT_Encode4(644308), // Rule ID 13086 //
     /*  644257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  644260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  644282 */     // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  644282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN),
     /*  644285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  644287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  644292 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  644299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  644302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644306 */     GIR_RootConstrainSelectedInstOperands,
     /*  644307 */     // GIR_Coverage, 13086,
     /*  644307 */     GIR_EraseRootFromParent_Done,
     /*  644308 */   // Label 10055: @644308
     /*  644308 */   GIM_Try, /*On fail goto*//*Label 10056*/ GIMT_Encode4(644368), // Rule ID 10677 //
     /*  644313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  644316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644324 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644326 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644337 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644345 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644362 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644366 */     GIR_RootConstrainSelectedInstOperands,
     /*  644367 */     // GIR_Coverage, 10677,
     /*  644367 */     GIR_EraseRootFromParent_Done,
     /*  644368 */   // Label 10056: @644368
     /*  644368 */   GIM_Try, /*On fail goto*//*Label 10057*/ GIMT_Encode4(644428), // Rule ID 10678 //
     /*  644373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  644376 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644384 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644397 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644405 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644426 */     GIR_RootConstrainSelectedInstOperands,
     /*  644427 */     // GIR_Coverage, 10678,
     /*  644427 */     GIR_EraseRootFromParent_Done,
     /*  644428 */   // Label 10057: @644428
     /*  644428 */   GIM_Try, /*On fail goto*//*Label 10058*/ GIMT_Encode4(644488), // Rule ID 10679 //
     /*  644433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  644436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644444 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644446 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644450 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644457 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644465 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644482 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644486 */     GIR_RootConstrainSelectedInstOperands,
     /*  644487 */     // GIR_Coverage, 10679,
     /*  644487 */     GIR_EraseRootFromParent_Done,
     /*  644488 */   // Label 10058: @644488
     /*  644488 */   GIM_Try, /*On fail goto*//*Label 10059*/ GIMT_Encode4(644548), // Rule ID 10680 //
     /*  644493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  644496 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644504 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644517 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644525 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644546 */     GIR_RootConstrainSelectedInstOperands,
     /*  644547 */     // GIR_Coverage, 10680,
     /*  644547 */     GIR_EraseRootFromParent_Done,
     /*  644548 */   // Label 10059: @644548
     /*  644548 */   GIM_Try, /*On fail goto*//*Label 10060*/ GIMT_Encode4(644608), // Rule ID 10681 //
     /*  644553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  644556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644564 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644577 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644585 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644606 */     GIR_RootConstrainSelectedInstOperands,
     /*  644607 */     // GIR_Coverage, 10681,
     /*  644607 */     GIR_EraseRootFromParent_Done,
     /*  644608 */   // Label 10060: @644608
     /*  644608 */   GIM_Try, /*On fail goto*//*Label 10061*/ GIMT_Encode4(644667), // Rule ID 11233 //
     /*  644613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  644616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644623 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644636 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644644 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644665 */     GIR_RootConstrainSelectedInstOperands,
     /*  644666 */     // GIR_Coverage, 11233,
     /*  644666 */     GIR_EraseRootFromParent_Done,
     /*  644667 */   // Label 10061: @644667
     /*  644667 */   GIM_Try, /*On fail goto*//*Label 10062*/ GIMT_Encode4(644726), // Rule ID 11234 //
     /*  644672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  644675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644682 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644695 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644703 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644724 */     GIR_RootConstrainSelectedInstOperands,
     /*  644725 */     // GIR_Coverage, 11234,
     /*  644725 */     GIR_EraseRootFromParent_Done,
     /*  644726 */   // Label 10062: @644726
     /*  644726 */   GIM_Try, /*On fail goto*//*Label 10063*/ GIMT_Encode4(644785), // Rule ID 11235 //
     /*  644731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  644734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644741 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644754 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644762 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644783 */     GIR_RootConstrainSelectedInstOperands,
     /*  644784 */     // GIR_Coverage, 11235,
     /*  644784 */     GIR_EraseRootFromParent_Done,
     /*  644785 */   // Label 10063: @644785
     /*  644785 */   GIM_Try, /*On fail goto*//*Label 10064*/ GIMT_Encode4(644844), // Rule ID 11236 //
     /*  644790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  644793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644800 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644813 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644821 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644842 */     GIR_RootConstrainSelectedInstOperands,
     /*  644843 */     // GIR_Coverage, 11236,
     /*  644843 */     GIR_EraseRootFromParent_Done,
     /*  644844 */   // Label 10064: @644844
     /*  644844 */   GIM_Try, /*On fail goto*//*Label 10065*/ GIMT_Encode4(644903), // Rule ID 11237 //
     /*  644849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  644852 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644859 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  644861 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644865 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  644872 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR),
     /*  644875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644880 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644901 */     GIR_RootConstrainSelectedInstOperands,
     /*  644902 */     // GIR_Coverage, 11237,
     /*  644902 */     GIR_EraseRootFromParent_Done,
     /*  644903 */   // Label 10065: @644903
     /*  644903 */   GIM_Try, /*On fail goto*//*Label 10066*/ GIMT_Encode4(644967), // Rule ID 10671 //
     /*  644908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  644911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644923 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644927 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  644934 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR_RTN),
     /*  644937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  644939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  644944 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  644946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  644951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  644956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  644961 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  644965 */     GIR_RootConstrainSelectedInstOperands,
     /*  644966 */     // GIR_Coverage, 10671,
     /*  644966 */     GIR_EraseRootFromParent_Done,
     /*  644967 */   // Label 10066: @644967
     /*  644967 */   GIM_Try, /*On fail goto*//*Label 10067*/ GIMT_Encode4(645030), // Rule ID 11227 //
     /*  644972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  644975 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  644982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  644986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  644990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  644997 */     // (atomic_load_xor:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (FLAT_ATOMIC_XOR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  644997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_SADDR_RTN),
     /*  645000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  645007 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  645014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  645019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  645024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645028 */     GIR_RootConstrainSelectedInstOperands,
     /*  645029 */     // GIR_Coverage, 11227,
     /*  645029 */     GIR_EraseRootFromParent_Done,
     /*  645030 */   // Label 10067: @645030
     /*  645030 */   GIM_Try, /*On fail goto*//*Label 10068*/ GIMT_Encode4(645083), // Rule ID 10672 //
     /*  645035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  645038 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645046 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645059 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645067 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645074 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645077 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645081 */     GIR_RootConstrainSelectedInstOperands,
     /*  645082 */     // GIR_Coverage, 10672,
     /*  645082 */     GIR_EraseRootFromParent_Done,
     /*  645083 */   // Label 10068: @645083
     /*  645083 */   GIM_Try, /*On fail goto*//*Label 10069*/ GIMT_Encode4(645136), // Rule ID 10673 //
     /*  645088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  645091 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645099 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645112 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645120 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645134 */     GIR_RootConstrainSelectedInstOperands,
     /*  645135 */     // GIR_Coverage, 10673,
     /*  645135 */     GIR_EraseRootFromParent_Done,
     /*  645136 */   // Label 10069: @645136
     /*  645136 */   GIM_Try, /*On fail goto*//*Label 10070*/ GIMT_Encode4(645189), // Rule ID 10674 //
     /*  645141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  645144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645152 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645165 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645173 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645187 */     GIR_RootConstrainSelectedInstOperands,
     /*  645188 */     // GIR_Coverage, 10674,
     /*  645188 */     GIR_EraseRootFromParent_Done,
     /*  645189 */   // Label 10070: @645189
     /*  645189 */   GIM_Try, /*On fail goto*//*Label 10071*/ GIMT_Encode4(645242), // Rule ID 10675 //
     /*  645194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  645197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645205 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645218 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645226 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645236 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645240 */     GIR_RootConstrainSelectedInstOperands,
     /*  645241 */     // GIR_Coverage, 10675,
     /*  645241 */     GIR_EraseRootFromParent_Done,
     /*  645242 */   // Label 10071: @645242
     /*  645242 */   GIM_Try, /*On fail goto*//*Label 10072*/ GIMT_Encode4(645295), // Rule ID 10676 //
     /*  645247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  645250 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645258 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645271 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645279 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645293 */     GIR_RootConstrainSelectedInstOperands,
     /*  645294 */     // GIR_Coverage, 10676,
     /*  645294 */     GIR_EraseRootFromParent_Done,
     /*  645295 */   // Label 10072: @645295
     /*  645295 */   GIM_Try, /*On fail goto*//*Label 10073*/ GIMT_Encode4(645347), // Rule ID 11228 //
     /*  645300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  645303 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645310 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645312 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645316 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645323 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645331 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645345 */     GIR_RootConstrainSelectedInstOperands,
     /*  645346 */     // GIR_Coverage, 11228,
     /*  645346 */     GIR_EraseRootFromParent_Done,
     /*  645347 */   // Label 10073: @645347
     /*  645347 */   GIM_Try, /*On fail goto*//*Label 10074*/ GIMT_Encode4(645399), // Rule ID 11229 //
     /*  645352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  645355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645362 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645375 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645383 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645397 */     GIR_RootConstrainSelectedInstOperands,
     /*  645398 */     // GIR_Coverage, 11229,
     /*  645398 */     GIR_EraseRootFromParent_Done,
     /*  645399 */   // Label 10074: @645399
     /*  645399 */   GIM_Try, /*On fail goto*//*Label 10075*/ GIMT_Encode4(645451), // Rule ID 11230 //
     /*  645404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  645407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645414 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645427 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645435 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645449 */     GIR_RootConstrainSelectedInstOperands,
     /*  645450 */     // GIR_Coverage, 11230,
     /*  645450 */     GIR_EraseRootFromParent_Done,
     /*  645451 */   // Label 10075: @645451
     /*  645451 */   GIM_Try, /*On fail goto*//*Label 10076*/ GIMT_Encode4(645503), // Rule ID 11231 //
     /*  645456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  645459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645466 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645479 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645487 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645501 */     GIR_RootConstrainSelectedInstOperands,
     /*  645502 */     // GIR_Coverage, 11231,
     /*  645502 */     GIR_EraseRootFromParent_Done,
     /*  645503 */   // Label 10076: @645503
     /*  645503 */   GIM_Try, /*On fail goto*//*Label 10077*/ GIMT_Encode4(645555), // Rule ID 11232 //
     /*  645508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  645511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645518 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  645520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645531 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>>  =>  (FLAT_ATOMIC_XOR VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
     /*  645534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645539 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  645549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645553 */     GIR_RootConstrainSelectedInstOperands,
     /*  645554 */     // GIR_Coverage, 11232,
     /*  645554 */     GIR_EraseRootFromParent_Done,
     /*  645555 */   // Label 10077: @645555
     /*  645555 */   GIM_Try, /*On fail goto*//*Label 10078*/ GIMT_Encode4(645612), // Rule ID 10666 //
     /*  645560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  645563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645575 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645586 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645596 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645610 */     GIR_RootConstrainSelectedInstOperands,
     /*  645611 */     // GIR_Coverage, 10666,
     /*  645611 */     GIR_EraseRootFromParent_Done,
     /*  645612 */   // Label 10078: @645612
     /*  645612 */   GIM_Try, /*On fail goto*//*Label 10079*/ GIMT_Encode4(645669), // Rule ID 10667 //
     /*  645617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  645620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645643 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645653 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645667 */     GIR_RootConstrainSelectedInstOperands,
     /*  645668 */     // GIR_Coverage, 10667,
     /*  645668 */     GIR_EraseRootFromParent_Done,
     /*  645669 */   // Label 10079: @645669
     /*  645669 */   GIM_Try, /*On fail goto*//*Label 10080*/ GIMT_Encode4(645726), // Rule ID 10668 //
     /*  645674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  645677 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645700 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645710 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645724 */     GIR_RootConstrainSelectedInstOperands,
     /*  645725 */     // GIR_Coverage, 10668,
     /*  645725 */     GIR_EraseRootFromParent_Done,
     /*  645726 */   // Label 10080: @645726
     /*  645726 */   GIM_Try, /*On fail goto*//*Label 10081*/ GIMT_Encode4(645783), // Rule ID 10669 //
     /*  645731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  645734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645757 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645767 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645777 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645781 */     GIR_RootConstrainSelectedInstOperands,
     /*  645782 */     // GIR_Coverage, 10669,
     /*  645782 */     GIR_EraseRootFromParent_Done,
     /*  645783 */   // Label 10081: @645783
     /*  645783 */   GIM_Try, /*On fail goto*//*Label 10082*/ GIMT_Encode4(645840), // Rule ID 10670 //
     /*  645788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  645791 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645814 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645824 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645838 */     GIR_RootConstrainSelectedInstOperands,
     /*  645839 */     // GIR_Coverage, 10670,
     /*  645839 */     GIR_EraseRootFromParent_Done,
     /*  645840 */   // Label 10082: @645840
     /*  645840 */   GIM_Try, /*On fail goto*//*Label 10083*/ GIMT_Encode4(645896), // Rule ID 11222 //
     /*  645845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  645848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645870 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645880 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645894 */     GIR_RootConstrainSelectedInstOperands,
     /*  645895 */     // GIR_Coverage, 11222,
     /*  645895 */     GIR_EraseRootFromParent_Done,
     /*  645896 */   // Label 10083: @645896
     /*  645896 */   GIM_Try, /*On fail goto*//*Label 10084*/ GIMT_Encode4(645952), // Rule ID 11223 //
     /*  645901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  645904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645926 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645936 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  645946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  645950 */     GIR_RootConstrainSelectedInstOperands,
     /*  645951 */     // GIR_Coverage, 11223,
     /*  645951 */     GIR_EraseRootFromParent_Done,
     /*  645952 */   // Label 10084: @645952
     /*  645952 */   GIM_Try, /*On fail goto*//*Label 10085*/ GIMT_Encode4(646008), // Rule ID 11224 //
     /*  645957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  645960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  645967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  645971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  645975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  645982 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  645982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  645985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  645987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  645992 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  645994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  645999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  646002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646006 */     GIR_RootConstrainSelectedInstOperands,
     /*  646007 */     // GIR_Coverage, 11224,
     /*  646007 */     GIR_EraseRootFromParent_Done,
     /*  646008 */   // Label 10085: @646008
     /*  646008 */   GIM_Try, /*On fail goto*//*Label 10086*/ GIMT_Encode4(646064), // Rule ID 11225 //
     /*  646013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  646016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  646027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  646038 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  646038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  646041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  646043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  646048 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  646050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  646055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  646058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646062 */     GIR_RootConstrainSelectedInstOperands,
     /*  646063 */     // GIR_Coverage, 11225,
     /*  646063 */     GIR_EraseRootFromParent_Done,
     /*  646064 */   // Label 10086: @646064
     /*  646064 */   GIM_Try, /*On fail goto*//*Label 10087*/ GIMT_Encode4(646120), // Rule ID 11226 //
     /*  646069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  646072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  646083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  646094 */     // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  646094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
     /*  646097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  646099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  646104 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  646106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  646111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  646114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646118 */     GIR_RootConstrainSelectedInstOperands,
     /*  646119 */     // GIR_Coverage, 11226,
     /*  646119 */     GIR_EraseRootFromParent_Done,
     /*  646120 */   // Label 10087: @646120
     /*  646120 */   GIM_Reject,
     /*  646121 */ // Label 9981: @646121
     /*  646121 */ GIM_Reject,
     /*  646122 */ // Label 9979: @646122
     /*  646122 */ GIM_Try, /*On fail goto*//*Label 10088*/ GIMT_Encode4(653621),
     /*  646127 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  646130 */   GIM_Try, /*On fail goto*//*Label 10089*/ GIMT_Encode4(646192), // Rule ID 21578 //
     /*  646135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  646138 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646145 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646158 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64),
     /*  646161 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646190 */     GIR_RootConstrainSelectedInstOperands,
     /*  646191 */     // GIR_Coverage, 21578,
     /*  646191 */     GIR_EraseRootFromParent_Done,
     /*  646192 */   // Label 10089: @646192
     /*  646192 */   GIM_Try, /*On fail goto*//*Label 10090*/ GIMT_Encode4(646254), // Rule ID 21579 //
     /*  646197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  646200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646207 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646209 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646220 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64),
     /*  646223 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646252 */     GIR_RootConstrainSelectedInstOperands,
     /*  646253 */     // GIR_Coverage, 21579,
     /*  646253 */     GIR_EraseRootFromParent_Done,
     /*  646254 */   // Label 10090: @646254
     /*  646254 */   GIM_Try, /*On fail goto*//*Label 10091*/ GIMT_Encode4(646316), // Rule ID 21580 //
     /*  646259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  646262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646269 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646282 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64),
     /*  646285 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646310 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646314 */     GIR_RootConstrainSelectedInstOperands,
     /*  646315 */     // GIR_Coverage, 21580,
     /*  646315 */     GIR_EraseRootFromParent_Done,
     /*  646316 */   // Label 10091: @646316
     /*  646316 */   GIM_Try, /*On fail goto*//*Label 10092*/ GIMT_Encode4(646378), // Rule ID 21581 //
     /*  646321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  646324 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646331 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646337 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646344 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64),
     /*  646347 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646376 */     GIR_RootConstrainSelectedInstOperands,
     /*  646377 */     // GIR_Coverage, 21581,
     /*  646377 */     GIR_EraseRootFromParent_Done,
     /*  646378 */   // Label 10092: @646378
     /*  646378 */   GIM_Try, /*On fail goto*//*Label 10093*/ GIMT_Encode4(646440), // Rule ID 21582 //
     /*  646383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  646386 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646393 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646406 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64),
     /*  646409 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646438 */     GIR_RootConstrainSelectedInstOperands,
     /*  646439 */     // GIR_Coverage, 21582,
     /*  646439 */     GIR_EraseRootFromParent_Done,
     /*  646440 */   // Label 10093: @646440
     /*  646440 */   GIM_Try, /*On fail goto*//*Label 10094*/ GIMT_Encode4(646502), // Rule ID 21598 //
     /*  646445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  646448 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646455 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646457 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646468 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64),
     /*  646471 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646500 */     GIR_RootConstrainSelectedInstOperands,
     /*  646501 */     // GIR_Coverage, 21598,
     /*  646501 */     GIR_EraseRootFromParent_Done,
     /*  646502 */   // Label 10094: @646502
     /*  646502 */   GIM_Try, /*On fail goto*//*Label 10095*/ GIMT_Encode4(646564), // Rule ID 21599 //
     /*  646507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  646510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646517 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646530 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64),
     /*  646533 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646562 */     GIR_RootConstrainSelectedInstOperands,
     /*  646563 */     // GIR_Coverage, 21599,
     /*  646563 */     GIR_EraseRootFromParent_Done,
     /*  646564 */   // Label 10095: @646564
     /*  646564 */   GIM_Try, /*On fail goto*//*Label 10096*/ GIMT_Encode4(646626), // Rule ID 21600 //
     /*  646569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  646572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646579 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646592 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64),
     /*  646595 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646624 */     GIR_RootConstrainSelectedInstOperands,
     /*  646625 */     // GIR_Coverage, 21600,
     /*  646625 */     GIR_EraseRootFromParent_Done,
     /*  646626 */   // Label 10096: @646626
     /*  646626 */   GIM_Try, /*On fail goto*//*Label 10097*/ GIMT_Encode4(646688), // Rule ID 21601 //
     /*  646631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  646634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646641 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646654 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64),
     /*  646657 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646686 */     GIR_RootConstrainSelectedInstOperands,
     /*  646687 */     // GIR_Coverage, 21601,
     /*  646687 */     GIR_EraseRootFromParent_Done,
     /*  646688 */   // Label 10097: @646688
     /*  646688 */   GIM_Try, /*On fail goto*//*Label 10098*/ GIMT_Encode4(646750), // Rule ID 21602 //
     /*  646693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  646696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646703 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  646705 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646716 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64),
     /*  646719 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  646744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646748 */     GIR_RootConstrainSelectedInstOperands,
     /*  646749 */     // GIR_Coverage, 21602,
     /*  646749 */     GIR_EraseRootFromParent_Done,
     /*  646750 */   // Label 10098: @646750
     /*  646750 */   GIM_Try, /*On fail goto*//*Label 10099*/ GIMT_Encode4(646816), // Rule ID 21568 //
     /*  646755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  646758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  646769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646780 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN),
     /*  646783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  646785 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  646810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646814 */     GIR_RootConstrainSelectedInstOperands,
     /*  646815 */     // GIR_Coverage, 21568,
     /*  646815 */     GIR_EraseRootFromParent_Done,
     /*  646816 */   // Label 10099: @646816
     /*  646816 */   GIM_Try, /*On fail goto*//*Label 10100*/ GIMT_Encode4(646882), // Rule ID 21569 //
     /*  646821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  646824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  646835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646846 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN),
     /*  646849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  646851 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  646876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646880 */     GIR_RootConstrainSelectedInstOperands,
     /*  646881 */     // GIR_Coverage, 21569,
     /*  646881 */     GIR_EraseRootFromParent_Done,
     /*  646882 */   // Label 10100: @646882
     /*  646882 */   GIM_Try, /*On fail goto*//*Label 10101*/ GIMT_Encode4(646948), // Rule ID 21570 //
     /*  646887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  646890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  646901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646912 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN),
     /*  646915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  646917 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  646934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  646939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  646942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  646946 */     GIR_RootConstrainSelectedInstOperands,
     /*  646947 */     // GIR_Coverage, 21570,
     /*  646947 */     GIR_EraseRootFromParent_Done,
     /*  646948 */   // Label 10101: @646948
     /*  646948 */   GIM_Try, /*On fail goto*//*Label 10102*/ GIMT_Encode4(647014), // Rule ID 21571 //
     /*  646953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  646956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  646963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  646967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  646971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  646978 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  646978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN),
     /*  646981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  646983 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  646985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  646990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  646995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647012 */     GIR_RootConstrainSelectedInstOperands,
     /*  647013 */     // GIR_Coverage, 21571,
     /*  647013 */     GIR_EraseRootFromParent_Done,
     /*  647014 */   // Label 10102: @647014
     /*  647014 */   GIM_Try, /*On fail goto*//*Label 10103*/ GIMT_Encode4(647080), // Rule ID 21572 //
     /*  647019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  647022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  647044 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN),
     /*  647047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  647049 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  647056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647078 */     GIR_RootConstrainSelectedInstOperands,
     /*  647079 */     // GIR_Coverage, 21572,
     /*  647079 */     GIR_EraseRootFromParent_Done,
     /*  647080 */   // Label 10103: @647080
     /*  647080 */   GIM_Try, /*On fail goto*//*Label 10104*/ GIMT_Encode4(647146), // Rule ID 21588 //
     /*  647085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  647088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  647110 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN),
     /*  647113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  647115 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  647122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647140 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647144 */     GIR_RootConstrainSelectedInstOperands,
     /*  647145 */     // GIR_Coverage, 21588,
     /*  647145 */     GIR_EraseRootFromParent_Done,
     /*  647146 */   // Label 10104: @647146
     /*  647146 */   GIM_Try, /*On fail goto*//*Label 10105*/ GIMT_Encode4(647212), // Rule ID 21589 //
     /*  647151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  647154 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  647176 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN),
     /*  647179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  647181 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  647188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647210 */     GIR_RootConstrainSelectedInstOperands,
     /*  647211 */     // GIR_Coverage, 21589,
     /*  647211 */     GIR_EraseRootFromParent_Done,
     /*  647212 */   // Label 10105: @647212
     /*  647212 */   GIM_Try, /*On fail goto*//*Label 10106*/ GIMT_Encode4(647278), // Rule ID 21590 //
     /*  647217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  647220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  647242 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN),
     /*  647245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  647247 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  647254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647276 */     GIR_RootConstrainSelectedInstOperands,
     /*  647277 */     // GIR_Coverage, 21590,
     /*  647277 */     GIR_EraseRootFromParent_Done,
     /*  647278 */   // Label 10106: @647278
     /*  647278 */   GIM_Try, /*On fail goto*//*Label 10107*/ GIMT_Encode4(647344), // Rule ID 21591 //
     /*  647283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  647286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647301 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  647308 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN),
     /*  647311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  647313 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  647320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647342 */     GIR_RootConstrainSelectedInstOperands,
     /*  647343 */     // GIR_Coverage, 21591,
     /*  647343 */     GIR_EraseRootFromParent_Done,
     /*  647344 */   // Label 10107: @647344
     /*  647344 */   GIM_Try, /*On fail goto*//*Label 10108*/ GIMT_Encode4(647410), // Rule ID 21592 //
     /*  647349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  647352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  647374 */     // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN),
     /*  647377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  647379 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  647386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  647396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  647401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  647404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647408 */     GIR_RootConstrainSelectedInstOperands,
     /*  647409 */     // GIR_Coverage, 21592,
     /*  647409 */     GIR_EraseRootFromParent_Done,
     /*  647410 */   // Label 10108: @647410
     /*  647410 */   GIM_Try, /*On fail goto*//*Label 10109*/ GIMT_Encode4(647467), // Rule ID 21573 //
     /*  647415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  647418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647425 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647438 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
     /*  647441 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647465 */     GIR_RootConstrainSelectedInstOperands,
     /*  647466 */     // GIR_Coverage, 21573,
     /*  647466 */     GIR_EraseRootFromParent_Done,
     /*  647467 */   // Label 10109: @647467
     /*  647467 */   GIM_Try, /*On fail goto*//*Label 10110*/ GIMT_Encode4(647524), // Rule ID 21574 //
     /*  647472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  647475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647482 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647495 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
     /*  647498 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647522 */     GIR_RootConstrainSelectedInstOperands,
     /*  647523 */     // GIR_Coverage, 21574,
     /*  647523 */     GIR_EraseRootFromParent_Done,
     /*  647524 */   // Label 10110: @647524
     /*  647524 */   GIM_Try, /*On fail goto*//*Label 10111*/ GIMT_Encode4(647581), // Rule ID 21575 //
     /*  647529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  647532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647539 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647552 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
     /*  647555 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647579 */     GIR_RootConstrainSelectedInstOperands,
     /*  647580 */     // GIR_Coverage, 21575,
     /*  647580 */     GIR_EraseRootFromParent_Done,
     /*  647581 */   // Label 10111: @647581
     /*  647581 */   GIM_Try, /*On fail goto*//*Label 10112*/ GIMT_Encode4(647638), // Rule ID 21576 //
     /*  647586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  647589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647596 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647609 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
     /*  647612 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647632 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647636 */     GIR_RootConstrainSelectedInstOperands,
     /*  647637 */     // GIR_Coverage, 21576,
     /*  647637 */     GIR_EraseRootFromParent_Done,
     /*  647638 */   // Label 10112: @647638
     /*  647638 */   GIM_Try, /*On fail goto*//*Label 10113*/ GIMT_Encode4(647695), // Rule ID 21577 //
     /*  647643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  647646 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647653 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647666 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
     /*  647669 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647693 */     GIR_RootConstrainSelectedInstOperands,
     /*  647694 */     // GIR_Coverage, 21577,
     /*  647694 */     GIR_EraseRootFromParent_Done,
     /*  647695 */   // Label 10113: @647695
     /*  647695 */   GIM_Try, /*On fail goto*//*Label 10114*/ GIMT_Encode4(647752), // Rule ID 21593 //
     /*  647700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  647703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647710 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647723 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
     /*  647726 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647750 */     GIR_RootConstrainSelectedInstOperands,
     /*  647751 */     // GIR_Coverage, 21593,
     /*  647751 */     GIR_EraseRootFromParent_Done,
     /*  647752 */   // Label 10114: @647752
     /*  647752 */   GIM_Try, /*On fail goto*//*Label 10115*/ GIMT_Encode4(647809), // Rule ID 21594 //
     /*  647757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  647760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647780 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
     /*  647783 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647807 */     GIR_RootConstrainSelectedInstOperands,
     /*  647808 */     // GIR_Coverage, 21594,
     /*  647808 */     GIR_EraseRootFromParent_Done,
     /*  647809 */   // Label 10115: @647809
     /*  647809 */   GIM_Try, /*On fail goto*//*Label 10116*/ GIMT_Encode4(647866), // Rule ID 21595 //
     /*  647814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  647817 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647824 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647837 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
     /*  647840 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647864 */     GIR_RootConstrainSelectedInstOperands,
     /*  647865 */     // GIR_Coverage, 21595,
     /*  647865 */     GIR_EraseRootFromParent_Done,
     /*  647866 */   // Label 10116: @647866
     /*  647866 */   GIM_Try, /*On fail goto*//*Label 10117*/ GIMT_Encode4(647923), // Rule ID 21596 //
     /*  647871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  647874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647881 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647894 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
     /*  647897 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647917 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647921 */     GIR_RootConstrainSelectedInstOperands,
     /*  647922 */     // GIR_Coverage, 21596,
     /*  647922 */     GIR_EraseRootFromParent_Done,
     /*  647923 */   // Label 10117: @647923
     /*  647923 */   GIM_Try, /*On fail goto*//*Label 10118*/ GIMT_Encode4(647980), // Rule ID 21597 //
     /*  647928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  647931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647938 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  647940 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  647944 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  647951 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  647951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
     /*  647954 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  647956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  647961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  647966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  647971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  647974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  647978 */     GIR_RootConstrainSelectedInstOperands,
     /*  647979 */     // GIR_Coverage, 21597,
     /*  647979 */     GIR_EraseRootFromParent_Done,
     /*  647980 */   // Label 10118: @647980
     /*  647980 */   GIM_Try, /*On fail goto*//*Label 10119*/ GIMT_Encode4(648041), // Rule ID 21563 //
     /*  647985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  647988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  647995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  647999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648010 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
     /*  648013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648015 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648035 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648039 */     GIR_RootConstrainSelectedInstOperands,
     /*  648040 */     // GIR_Coverage, 21563,
     /*  648040 */     GIR_EraseRootFromParent_Done,
     /*  648041 */   // Label 10119: @648041
     /*  648041 */   GIM_Try, /*On fail goto*//*Label 10120*/ GIMT_Encode4(648102), // Rule ID 21564 //
     /*  648046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  648049 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648071 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
     /*  648074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648076 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648100 */     GIR_RootConstrainSelectedInstOperands,
     /*  648101 */     // GIR_Coverage, 21564,
     /*  648101 */     GIR_EraseRootFromParent_Done,
     /*  648102 */   // Label 10120: @648102
     /*  648102 */   GIM_Try, /*On fail goto*//*Label 10121*/ GIMT_Encode4(648163), // Rule ID 21565 //
     /*  648107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  648110 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648132 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
     /*  648135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648137 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648161 */     GIR_RootConstrainSelectedInstOperands,
     /*  648162 */     // GIR_Coverage, 21565,
     /*  648162 */     GIR_EraseRootFromParent_Done,
     /*  648163 */   // Label 10121: @648163
     /*  648163 */   GIM_Try, /*On fail goto*//*Label 10122*/ GIMT_Encode4(648224), // Rule ID 21566 //
     /*  648168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  648171 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648193 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
     /*  648196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648198 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648222 */     GIR_RootConstrainSelectedInstOperands,
     /*  648223 */     // GIR_Coverage, 21566,
     /*  648223 */     GIR_EraseRootFromParent_Done,
     /*  648224 */   // Label 10122: @648224
     /*  648224 */   GIM_Try, /*On fail goto*//*Label 10123*/ GIMT_Encode4(648285), // Rule ID 21567 //
     /*  648229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  648232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648254 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
     /*  648257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648259 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648283 */     GIR_RootConstrainSelectedInstOperands,
     /*  648284 */     // GIR_Coverage, 21567,
     /*  648284 */     GIR_EraseRootFromParent_Done,
     /*  648285 */   // Label 10123: @648285
     /*  648285 */   GIM_Try, /*On fail goto*//*Label 10124*/ GIMT_Encode4(648346), // Rule ID 21583 //
     /*  648290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  648293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648304 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648308 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648315 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
     /*  648318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648320 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648344 */     GIR_RootConstrainSelectedInstOperands,
     /*  648345 */     // GIR_Coverage, 21583,
     /*  648345 */     GIR_EraseRootFromParent_Done,
     /*  648346 */   // Label 10124: @648346
     /*  648346 */   GIM_Try, /*On fail goto*//*Label 10125*/ GIMT_Encode4(648407), // Rule ID 21584 //
     /*  648351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  648354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648376 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
     /*  648379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648381 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648405 */     GIR_RootConstrainSelectedInstOperands,
     /*  648406 */     // GIR_Coverage, 21584,
     /*  648406 */     GIR_EraseRootFromParent_Done,
     /*  648407 */   // Label 10125: @648407
     /*  648407 */   GIM_Try, /*On fail goto*//*Label 10126*/ GIMT_Encode4(648468), // Rule ID 21585 //
     /*  648412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  648415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648437 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
     /*  648440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648442 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648466 */     GIR_RootConstrainSelectedInstOperands,
     /*  648467 */     // GIR_Coverage, 21585,
     /*  648467 */     GIR_EraseRootFromParent_Done,
     /*  648468 */   // Label 10126: @648468
     /*  648468 */   GIM_Try, /*On fail goto*//*Label 10127*/ GIMT_Encode4(648529), // Rule ID 21586 //
     /*  648473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  648476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648498 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
     /*  648501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648503 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648523 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648527 */     GIR_RootConstrainSelectedInstOperands,
     /*  648528 */     // GIR_Coverage, 21586,
     /*  648528 */     GIR_EraseRootFromParent_Done,
     /*  648529 */   // Label 10127: @648529
     /*  648529 */   GIM_Try, /*On fail goto*//*Label 10128*/ GIMT_Encode4(648590), // Rule ID 21587 //
     /*  648534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  648537 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  648544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  648548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  648559 */     // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  648559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
     /*  648562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  648564 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  648566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  648571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  648576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  648581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  648584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648588 */     GIR_RootConstrainSelectedInstOperands,
     /*  648589 */     // GIR_Coverage, 21587,
     /*  648589 */     GIR_EraseRootFromParent_Done,
     /*  648590 */   // Label 10128: @648590
     /*  648590 */   GIM_Try, /*On fail goto*//*Label 10129*/ GIMT_Encode4(648640), // Rule ID 30745 //
     /*  648595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  648598 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648603 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648616 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  648619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648624 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648638 */     GIR_RootConstrainSelectedInstOperands,
     /*  648639 */     // GIR_Coverage, 30745,
     /*  648639 */     GIR_EraseRootFromParent_Done,
     /*  648640 */   // Label 10129: @648640
     /*  648640 */   GIM_Try, /*On fail goto*//*Label 10130*/ GIMT_Encode4(648690), // Rule ID 30746 //
     /*  648645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  648648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648653 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648666 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  648669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648674 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648684 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648688 */     GIR_RootConstrainSelectedInstOperands,
     /*  648689 */     // GIR_Coverage, 30746,
     /*  648689 */     GIR_EraseRootFromParent_Done,
     /*  648690 */   // Label 10130: @648690
     /*  648690 */   GIM_Try, /*On fail goto*//*Label 10131*/ GIMT_Encode4(648740), // Rule ID 30747 //
     /*  648695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  648698 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648703 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648705 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648716 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  648719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648724 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648738 */     GIR_RootConstrainSelectedInstOperands,
     /*  648739 */     // GIR_Coverage, 30747,
     /*  648739 */     GIR_EraseRootFromParent_Done,
     /*  648740 */   // Label 10131: @648740
     /*  648740 */   GIM_Try, /*On fail goto*//*Label 10132*/ GIMT_Encode4(648790), // Rule ID 30748 //
     /*  648745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  648748 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648753 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648755 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648766 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  648769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648774 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648788 */     GIR_RootConstrainSelectedInstOperands,
     /*  648789 */     // GIR_Coverage, 30748,
     /*  648789 */     GIR_EraseRootFromParent_Done,
     /*  648790 */   // Label 10132: @648790
     /*  648790 */   GIM_Try, /*On fail goto*//*Label 10133*/ GIMT_Encode4(648840), // Rule ID 30749 //
     /*  648795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  648798 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648803 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648816 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  648819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648824 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648838 */     GIR_RootConstrainSelectedInstOperands,
     /*  648839 */     // GIR_Coverage, 30749,
     /*  648839 */     GIR_EraseRootFromParent_Done,
     /*  648840 */   // Label 10133: @648840
     /*  648840 */   GIM_Try, /*On fail goto*//*Label 10134*/ GIMT_Encode4(648890), // Rule ID 30755 //
     /*  648845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  648848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648853 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648866 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i64>>  =>  (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9),
     /*  648869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648874 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648888 */     GIR_RootConstrainSelectedInstOperands,
     /*  648889 */     // GIR_Coverage, 30755,
     /*  648889 */     GIR_EraseRootFromParent_Done,
     /*  648890 */   // Label 10134: @648890
     /*  648890 */   GIM_Try, /*On fail goto*//*Label 10135*/ GIMT_Encode4(648940), // Rule ID 30756 //
     /*  648895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  648898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648903 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648916 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i64>>  =>  (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9),
     /*  648919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648924 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648938 */     GIR_RootConstrainSelectedInstOperands,
     /*  648939 */     // GIR_Coverage, 30756,
     /*  648939 */     GIR_EraseRootFromParent_Done,
     /*  648940 */   // Label 10135: @648940
     /*  648940 */   GIM_Try, /*On fail goto*//*Label 10136*/ GIMT_Encode4(648990), // Rule ID 30757 //
     /*  648945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  648948 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  648953 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  648955 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  648959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  648966 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i64>>  =>  (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  648966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9),
     /*  648969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  648974 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  648976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  648981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  648984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  648988 */     GIR_RootConstrainSelectedInstOperands,
     /*  648989 */     // GIR_Coverage, 30757,
     /*  648989 */     GIR_EraseRootFromParent_Done,
     /*  648990 */   // Label 10136: @648990
     /*  648990 */   GIM_Try, /*On fail goto*//*Label 10137*/ GIMT_Encode4(649040), // Rule ID 30758 //
     /*  648995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  648998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649003 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649016 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i64>>  =>  (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9),
     /*  649019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649024 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649038 */     GIR_RootConstrainSelectedInstOperands,
     /*  649039 */     // GIR_Coverage, 30758,
     /*  649039 */     GIR_EraseRootFromParent_Done,
     /*  649040 */   // Label 10137: @649040
     /*  649040 */   GIM_Try, /*On fail goto*//*Label 10138*/ GIMT_Encode4(649090), // Rule ID 30759 //
     /*  649045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  649048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649053 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649066 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i64>>  =>  (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9),
     /*  649069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649074 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649088 */     GIR_RootConstrainSelectedInstOperands,
     /*  649089 */     // GIR_Coverage, 30759,
     /*  649089 */     GIR_EraseRootFromParent_Done,
     /*  649090 */   // Label 10138: @649090
     /*  649090 */   GIM_Try, /*On fail goto*//*Label 10139*/ GIMT_Encode4(649140), // Rule ID 30765 //
     /*  649095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  649098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649103 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649116 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  649119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649124 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649138 */     GIR_RootConstrainSelectedInstOperands,
     /*  649139 */     // GIR_Coverage, 30765,
     /*  649139 */     GIR_EraseRootFromParent_Done,
     /*  649140 */   // Label 10139: @649140
     /*  649140 */   GIM_Try, /*On fail goto*//*Label 10140*/ GIMT_Encode4(649190), // Rule ID 30766 //
     /*  649145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  649148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649153 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649166 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  649169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649174 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649188 */     GIR_RootConstrainSelectedInstOperands,
     /*  649189 */     // GIR_Coverage, 30766,
     /*  649189 */     GIR_EraseRootFromParent_Done,
     /*  649190 */   // Label 10140: @649190
     /*  649190 */   GIM_Try, /*On fail goto*//*Label 10141*/ GIMT_Encode4(649240), // Rule ID 30767 //
     /*  649195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  649198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649203 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649216 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  649219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649224 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649238 */     GIR_RootConstrainSelectedInstOperands,
     /*  649239 */     // GIR_Coverage, 30767,
     /*  649239 */     GIR_EraseRootFromParent_Done,
     /*  649240 */   // Label 10141: @649240
     /*  649240 */   GIM_Try, /*On fail goto*//*Label 10142*/ GIMT_Encode4(649290), // Rule ID 30768 //
     /*  649245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  649248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649253 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649255 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649259 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649266 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  649269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649274 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649281 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649288 */     GIR_RootConstrainSelectedInstOperands,
     /*  649289 */     // GIR_Coverage, 30768,
     /*  649289 */     GIR_EraseRootFromParent_Done,
     /*  649290 */   // Label 10142: @649290
     /*  649290 */   GIM_Try, /*On fail goto*//*Label 10143*/ GIMT_Encode4(649340), // Rule ID 30769 //
     /*  649295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  649298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649303 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  649305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649316 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
     /*  649319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649324 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649338 */     GIR_RootConstrainSelectedInstOperands,
     /*  649339 */     // GIR_Coverage, 30769,
     /*  649339 */     GIR_EraseRootFromParent_Done,
     /*  649340 */   // Label 10143: @649340
     /*  649340 */   GIM_Try, /*On fail goto*//*Label 10144*/ GIMT_Encode4(649394), // Rule ID 30740 //
     /*  649345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  649348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649368 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649378 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649388 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649392 */     GIR_RootConstrainSelectedInstOperands,
     /*  649393 */     // GIR_Coverage, 30740,
     /*  649393 */     GIR_EraseRootFromParent_Done,
     /*  649394 */   // Label 10144: @649394
     /*  649394 */   GIM_Try, /*On fail goto*//*Label 10145*/ GIMT_Encode4(649448), // Rule ID 30741 //
     /*  649399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  649402 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649422 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649432 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649446 */     GIR_RootConstrainSelectedInstOperands,
     /*  649447 */     // GIR_Coverage, 30741,
     /*  649447 */     GIR_EraseRootFromParent_Done,
     /*  649448 */   // Label 10145: @649448
     /*  649448 */   GIM_Try, /*On fail goto*//*Label 10146*/ GIMT_Encode4(649502), // Rule ID 30742 //
     /*  649453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  649456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649476 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649486 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649500 */     GIR_RootConstrainSelectedInstOperands,
     /*  649501 */     // GIR_Coverage, 30742,
     /*  649501 */     GIR_EraseRootFromParent_Done,
     /*  649502 */   // Label 10146: @649502
     /*  649502 */   GIM_Try, /*On fail goto*//*Label 10147*/ GIMT_Encode4(649556), // Rule ID 30743 //
     /*  649507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  649510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649530 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649540 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649550 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649554 */     GIR_RootConstrainSelectedInstOperands,
     /*  649555 */     // GIR_Coverage, 30743,
     /*  649555 */     GIR_EraseRootFromParent_Done,
     /*  649556 */   // Label 10147: @649556
     /*  649556 */   GIM_Try, /*On fail goto*//*Label 10148*/ GIMT_Encode4(649610), // Rule ID 30744 //
     /*  649561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  649564 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649584 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649594 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649608 */     GIR_RootConstrainSelectedInstOperands,
     /*  649609 */     // GIR_Coverage, 30744,
     /*  649609 */     GIR_EraseRootFromParent_Done,
     /*  649610 */   // Label 10148: @649610
     /*  649610 */   GIM_Try, /*On fail goto*//*Label 10149*/ GIMT_Encode4(649664), // Rule ID 30750 //
     /*  649615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  649618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649638 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_i64>>  =>  (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9),
     /*  649641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649648 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649662 */     GIR_RootConstrainSelectedInstOperands,
     /*  649663 */     // GIR_Coverage, 30750,
     /*  649663 */     GIR_EraseRootFromParent_Done,
     /*  649664 */   // Label 10149: @649664
     /*  649664 */   GIM_Try, /*On fail goto*//*Label 10150*/ GIMT_Encode4(649718), // Rule ID 30751 //
     /*  649669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  649672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649692 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_i64>>  =>  (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9),
     /*  649695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649702 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649716 */     GIR_RootConstrainSelectedInstOperands,
     /*  649717 */     // GIR_Coverage, 30751,
     /*  649717 */     GIR_EraseRootFromParent_Done,
     /*  649718 */   // Label 10150: @649718
     /*  649718 */   GIM_Try, /*On fail goto*//*Label 10151*/ GIMT_Encode4(649772), // Rule ID 30752 //
     /*  649723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  649726 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649735 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649746 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_i64>>  =>  (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9),
     /*  649749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649756 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649763 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649770 */     GIR_RootConstrainSelectedInstOperands,
     /*  649771 */     // GIR_Coverage, 30752,
     /*  649771 */     GIR_EraseRootFromParent_Done,
     /*  649772 */   // Label 10151: @649772
     /*  649772 */   GIM_Try, /*On fail goto*//*Label 10152*/ GIMT_Encode4(649826), // Rule ID 30753 //
     /*  649777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  649780 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649800 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_i64>>  =>  (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9),
     /*  649803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649810 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649824 */     GIR_RootConstrainSelectedInstOperands,
     /*  649825 */     // GIR_Coverage, 30753,
     /*  649825 */     GIR_EraseRootFromParent_Done,
     /*  649826 */   // Label 10152: @649826
     /*  649826 */   GIM_Try, /*On fail goto*//*Label 10153*/ GIMT_Encode4(649880), // Rule ID 30754 //
     /*  649831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  649834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  649839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649854 */     // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_i64>>  =>  (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  649854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9),
     /*  649857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649864 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  649874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649878 */     GIR_RootConstrainSelectedInstOperands,
     /*  649879 */     // GIR_Coverage, 30754,
     /*  649879 */     GIR_EraseRootFromParent_Done,
     /*  649880 */   // Label 10153: @649880
     /*  649880 */   GIM_Try, /*On fail goto*//*Label 10154*/ GIMT_Encode4(649934), // Rule ID 30760 //
     /*  649885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  649888 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649908 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649918 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649932 */     GIR_RootConstrainSelectedInstOperands,
     /*  649933 */     // GIR_Coverage, 30760,
     /*  649933 */     GIR_EraseRootFromParent_Done,
     /*  649934 */   // Label 10154: @649934
     /*  649934 */   GIM_Try, /*On fail goto*//*Label 10155*/ GIMT_Encode4(649988), // Rule ID 30761 //
     /*  649939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  649942 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  649947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  649951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  649955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  649962 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  649962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  649965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  649967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  649972 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  649974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  649979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  649982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  649986 */     GIR_RootConstrainSelectedInstOperands,
     /*  649987 */     // GIR_Coverage, 30761,
     /*  649987 */     GIR_EraseRootFromParent_Done,
     /*  649988 */   // Label 10155: @649988
     /*  649988 */   GIM_Try, /*On fail goto*//*Label 10156*/ GIMT_Encode4(650042), // Rule ID 30762 //
     /*  649993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  649996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  650001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  650016 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  650016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  650019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  650026 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  650028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  650036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650040 */     GIR_RootConstrainSelectedInstOperands,
     /*  650041 */     // GIR_Coverage, 30762,
     /*  650041 */     GIR_EraseRootFromParent_Done,
     /*  650042 */   // Label 10156: @650042
     /*  650042 */   GIM_Try, /*On fail goto*//*Label 10157*/ GIMT_Encode4(650096), // Rule ID 30763 //
     /*  650047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  650050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  650055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650059 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650063 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  650070 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  650070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  650073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  650080 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  650082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  650090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650094 */     GIR_RootConstrainSelectedInstOperands,
     /*  650095 */     // GIR_Coverage, 30763,
     /*  650095 */     GIR_EraseRootFromParent_Done,
     /*  650096 */   // Label 10157: @650096
     /*  650096 */   GIM_Try, /*On fail goto*//*Label 10158*/ GIMT_Encode4(650150), // Rule ID 30764 //
     /*  650101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  650104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  650109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  650124 */     // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  650124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
     /*  650127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  650134 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  650136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  650144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650148 */     GIR_RootConstrainSelectedInstOperands,
     /*  650149 */     // GIR_Coverage, 30764,
     /*  650149 */     GIR_EraseRootFromParent_Done,
     /*  650150 */   // Label 10158: @650150
     /*  650150 */   GIM_Try, /*On fail goto*//*Label 10159*/ GIMT_Encode4(650209), // Rule ID 13345 //
     /*  650155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  650158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650165 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650167 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650171 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  650178 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR),
     /*  650181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650186 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650203 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650207 */     GIR_RootConstrainSelectedInstOperands,
     /*  650208 */     // GIR_Coverage, 13345,
     /*  650208 */     GIR_EraseRootFromParent_Done,
     /*  650209 */   // Label 10159: @650209
     /*  650209 */   GIM_Try, /*On fail goto*//*Label 10160*/ GIMT_Encode4(650268), // Rule ID 13346 //
     /*  650214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  650217 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650224 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  650237 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR),
     /*  650240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650245 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650266 */     GIR_RootConstrainSelectedInstOperands,
     /*  650267 */     // GIR_Coverage, 13346,
     /*  650267 */     GIR_EraseRootFromParent_Done,
     /*  650268 */   // Label 10160: @650268
     /*  650268 */   GIM_Try, /*On fail goto*//*Label 10161*/ GIMT_Encode4(650327), // Rule ID 13347 //
     /*  650273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  650276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650283 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  650296 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR),
     /*  650299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650304 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650325 */     GIR_RootConstrainSelectedInstOperands,
     /*  650326 */     // GIR_Coverage, 13347,
     /*  650326 */     GIR_EraseRootFromParent_Done,
     /*  650327 */   // Label 10161: @650327
     /*  650327 */   GIM_Try, /*On fail goto*//*Label 10162*/ GIMT_Encode4(650386), // Rule ID 13348 //
     /*  650332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  650335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650342 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650344 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  650355 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR),
     /*  650358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650363 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650384 */     GIR_RootConstrainSelectedInstOperands,
     /*  650385 */     // GIR_Coverage, 13348,
     /*  650385 */     GIR_EraseRootFromParent_Done,
     /*  650386 */   // Label 10162: @650386
     /*  650386 */   GIM_Try, /*On fail goto*//*Label 10163*/ GIMT_Encode4(650445), // Rule ID 13349 //
     /*  650391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  650394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650401 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  650414 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR),
     /*  650417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650422 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650443 */     GIR_RootConstrainSelectedInstOperands,
     /*  650444 */     // GIR_Coverage, 13349,
     /*  650444 */     GIR_EraseRootFromParent_Done,
     /*  650445 */   // Label 10163: @650445
     /*  650445 */   GIM_Try, /*On fail goto*//*Label 10164*/ GIMT_Encode4(650508), // Rule ID 13355 //
     /*  650450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  650453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  650475 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN),
     /*  650478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650485 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650506 */     GIR_RootConstrainSelectedInstOperands,
     /*  650507 */     // GIR_Coverage, 13355,
     /*  650507 */     GIR_EraseRootFromParent_Done,
     /*  650508 */   // Label 10164: @650508
     /*  650508 */   GIM_Try, /*On fail goto*//*Label 10165*/ GIMT_Encode4(650571), // Rule ID 13356 //
     /*  650513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  650516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  650538 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN),
     /*  650541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650548 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650569 */     GIR_RootConstrainSelectedInstOperands,
     /*  650570 */     // GIR_Coverage, 13356,
     /*  650570 */     GIR_EraseRootFromParent_Done,
     /*  650571 */   // Label 10165: @650571
     /*  650571 */   GIM_Try, /*On fail goto*//*Label 10166*/ GIMT_Encode4(650634), // Rule ID 13357 //
     /*  650576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  650579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  650601 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN),
     /*  650604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650611 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650632 */     GIR_RootConstrainSelectedInstOperands,
     /*  650633 */     // GIR_Coverage, 13357,
     /*  650633 */     GIR_EraseRootFromParent_Done,
     /*  650634 */   // Label 10166: @650634
     /*  650634 */   GIM_Try, /*On fail goto*//*Label 10167*/ GIMT_Encode4(650697), // Rule ID 13358 //
     /*  650639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  650642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  650664 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN),
     /*  650667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650674 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650695 */     GIR_RootConstrainSelectedInstOperands,
     /*  650696 */     // GIR_Coverage, 13358,
     /*  650696 */     GIR_EraseRootFromParent_Done,
     /*  650697 */   // Label 10167: @650697
     /*  650697 */   GIM_Try, /*On fail goto*//*Label 10168*/ GIMT_Encode4(650760), // Rule ID 13359 //
     /*  650702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  650705 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  650716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  650727 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  650727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN),
     /*  650730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  650732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  650737 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  650744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  650749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  650754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650758 */     GIR_RootConstrainSelectedInstOperands,
     /*  650759 */     // GIR_Coverage, 13359,
     /*  650759 */     GIR_EraseRootFromParent_Done,
     /*  650760 */   // Label 10168: @650760
     /*  650760 */   GIM_Try, /*On fail goto*//*Label 10169*/ GIMT_Encode4(650812), // Rule ID 13340 //
     /*  650765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  650768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650775 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  650788 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  650788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2),
     /*  650791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  650796 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  650806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650810 */     GIR_RootConstrainSelectedInstOperands,
     /*  650811 */     // GIR_Coverage, 13340,
     /*  650811 */     GIR_EraseRootFromParent_Done,
     /*  650812 */   // Label 10169: @650812
     /*  650812 */   GIM_Try, /*On fail goto*//*Label 10170*/ GIMT_Encode4(650864), // Rule ID 13341 //
     /*  650817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  650820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650827 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  650840 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  650840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2),
     /*  650843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  650848 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  650858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650862 */     GIR_RootConstrainSelectedInstOperands,
     /*  650863 */     // GIR_Coverage, 13341,
     /*  650863 */     GIR_EraseRootFromParent_Done,
     /*  650864 */   // Label 10170: @650864
     /*  650864 */   GIM_Try, /*On fail goto*//*Label 10171*/ GIMT_Encode4(650916), // Rule ID 13342 //
     /*  650869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  650872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650879 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650881 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  650892 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  650892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2),
     /*  650895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  650900 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  650910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650914 */     GIR_RootConstrainSelectedInstOperands,
     /*  650915 */     // GIR_Coverage, 13342,
     /*  650915 */     GIR_EraseRootFromParent_Done,
     /*  650916 */   // Label 10171: @650916
     /*  650916 */   GIM_Try, /*On fail goto*//*Label 10172*/ GIMT_Encode4(650968), // Rule ID 13343 //
     /*  650921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  650924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650931 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  650944 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  650944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2),
     /*  650947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  650952 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  650954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  650959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  650962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  650966 */     GIR_RootConstrainSelectedInstOperands,
     /*  650967 */     // GIR_Coverage, 13343,
     /*  650967 */     GIR_EraseRootFromParent_Done,
     /*  650968 */   // Label 10172: @650968
     /*  650968 */   GIM_Try, /*On fail goto*//*Label 10173*/ GIMT_Encode4(651020), // Rule ID 13344 //
     /*  650973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  650976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  650983 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  650985 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  650989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  650996 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  650996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2),
     /*  650999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  651004 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  651011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  651014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651018 */     GIR_RootConstrainSelectedInstOperands,
     /*  651019 */     // GIR_Coverage, 13344,
     /*  651019 */     GIR_EraseRootFromParent_Done,
     /*  651020 */   // Label 10173: @651020
     /*  651020 */   GIM_Try, /*On fail goto*//*Label 10174*/ GIMT_Encode4(651076), // Rule ID 13350 //
     /*  651025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  651028 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  651050 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  651050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN),
     /*  651053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  651060 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  651067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  651070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651074 */     GIR_RootConstrainSelectedInstOperands,
     /*  651075 */     // GIR_Coverage, 13350,
     /*  651075 */     GIR_EraseRootFromParent_Done,
     /*  651076 */   // Label 10174: @651076
     /*  651076 */   GIM_Try, /*On fail goto*//*Label 10175*/ GIMT_Encode4(651132), // Rule ID 13351 //
     /*  651081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  651084 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  651106 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  651106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN),
     /*  651109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  651116 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  651123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  651126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651130 */     GIR_RootConstrainSelectedInstOperands,
     /*  651131 */     // GIR_Coverage, 13351,
     /*  651131 */     GIR_EraseRootFromParent_Done,
     /*  651132 */   // Label 10175: @651132
     /*  651132 */   GIM_Try, /*On fail goto*//*Label 10176*/ GIMT_Encode4(651188), // Rule ID 13352 //
     /*  651137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  651140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  651162 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  651162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN),
     /*  651165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  651172 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  651179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  651182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651186 */     GIR_RootConstrainSelectedInstOperands,
     /*  651187 */     // GIR_Coverage, 13352,
     /*  651187 */     GIR_EraseRootFromParent_Done,
     /*  651188 */   // Label 10176: @651188
     /*  651188 */   GIM_Try, /*On fail goto*//*Label 10177*/ GIMT_Encode4(651244), // Rule ID 13353 //
     /*  651193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  651196 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651207 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  651218 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  651218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN),
     /*  651221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  651228 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  651235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  651238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651242 */     GIR_RootConstrainSelectedInstOperands,
     /*  651243 */     // GIR_Coverage, 13353,
     /*  651243 */     GIR_EraseRootFromParent_Done,
     /*  651244 */   // Label 10177: @651244
     /*  651244 */   GIM_Try, /*On fail goto*//*Label 10178*/ GIMT_Encode4(651300), // Rule ID 13354 //
     /*  651249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  651252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  651274 */     // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  651274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN),
     /*  651277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  651284 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  651291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  651294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651298 */     GIR_RootConstrainSelectedInstOperands,
     /*  651299 */     // GIR_Coverage, 13354,
     /*  651299 */     GIR_EraseRootFromParent_Done,
     /*  651300 */   // Label 10178: @651300
     /*  651300 */   GIM_Try, /*On fail goto*//*Label 10179*/ GIMT_Encode4(651360), // Rule ID 10937 //
     /*  651305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  651308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651316 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651329 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651337 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651358 */     GIR_RootConstrainSelectedInstOperands,
     /*  651359 */     // GIR_Coverage, 10937,
     /*  651359 */     GIR_EraseRootFromParent_Done,
     /*  651360 */   // Label 10179: @651360
     /*  651360 */   GIM_Try, /*On fail goto*//*Label 10180*/ GIMT_Encode4(651420), // Rule ID 10938 //
     /*  651365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  651368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651376 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651389 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651397 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651418 */     GIR_RootConstrainSelectedInstOperands,
     /*  651419 */     // GIR_Coverage, 10938,
     /*  651419 */     GIR_EraseRootFromParent_Done,
     /*  651420 */   // Label 10180: @651420
     /*  651420 */   GIM_Try, /*On fail goto*//*Label 10181*/ GIMT_Encode4(651480), // Rule ID 10939 //
     /*  651425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  651428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651436 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651449 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651457 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651478 */     GIR_RootConstrainSelectedInstOperands,
     /*  651479 */     // GIR_Coverage, 10939,
     /*  651479 */     GIR_EraseRootFromParent_Done,
     /*  651480 */   // Label 10181: @651480
     /*  651480 */   GIM_Try, /*On fail goto*//*Label 10182*/ GIMT_Encode4(651540), // Rule ID 10940 //
     /*  651485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  651488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651496 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651509 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651517 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651538 */     GIR_RootConstrainSelectedInstOperands,
     /*  651539 */     // GIR_Coverage, 10940,
     /*  651539 */     GIR_EraseRootFromParent_Done,
     /*  651540 */   // Label 10182: @651540
     /*  651540 */   GIM_Try, /*On fail goto*//*Label 10183*/ GIMT_Encode4(651600), // Rule ID 10941 //
     /*  651545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  651548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651556 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651569 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651577 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651598 */     GIR_RootConstrainSelectedInstOperands,
     /*  651599 */     // GIR_Coverage, 10941,
     /*  651599 */     GIR_EraseRootFromParent_Done,
     /*  651600 */   // Label 10183: @651600
     /*  651600 */   GIM_Try, /*On fail goto*//*Label 10184*/ GIMT_Encode4(651659), // Rule ID 11493 //
     /*  651605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  651608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651615 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651628 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651636 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651653 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651657 */     GIR_RootConstrainSelectedInstOperands,
     /*  651658 */     // GIR_Coverage, 11493,
     /*  651658 */     GIR_EraseRootFromParent_Done,
     /*  651659 */   // Label 10184: @651659
     /*  651659 */   GIM_Try, /*On fail goto*//*Label 10185*/ GIMT_Encode4(651718), // Rule ID 11494 //
     /*  651664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  651667 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651674 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651687 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651695 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651716 */     GIR_RootConstrainSelectedInstOperands,
     /*  651717 */     // GIR_Coverage, 11494,
     /*  651717 */     GIR_EraseRootFromParent_Done,
     /*  651718 */   // Label 10185: @651718
     /*  651718 */   GIM_Try, /*On fail goto*//*Label 10186*/ GIMT_Encode4(651777), // Rule ID 11495 //
     /*  651723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  651726 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651733 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651735 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651746 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651754 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651775 */     GIR_RootConstrainSelectedInstOperands,
     /*  651776 */     // GIR_Coverage, 11495,
     /*  651776 */     GIR_EraseRootFromParent_Done,
     /*  651777 */   // Label 10186: @651777
     /*  651777 */   GIM_Try, /*On fail goto*//*Label 10187*/ GIMT_Encode4(651836), // Rule ID 11496 //
     /*  651782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  651785 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651792 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651794 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651798 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651805 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651813 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651834 */     GIR_RootConstrainSelectedInstOperands,
     /*  651835 */     // GIR_Coverage, 11496,
     /*  651835 */     GIR_EraseRootFromParent_Done,
     /*  651836 */   // Label 10187: @651836
     /*  651836 */   GIM_Try, /*On fail goto*//*Label 10188*/ GIMT_Encode4(651895), // Rule ID 11497 //
     /*  651841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  651844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651851 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  651853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  651864 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR),
     /*  651867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651872 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651889 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651893 */     GIR_RootConstrainSelectedInstOperands,
     /*  651894 */     // GIR_Coverage, 11497,
     /*  651894 */     GIR_EraseRootFromParent_Done,
     /*  651895 */   // Label 10188: @651895
     /*  651895 */   GIM_Try, /*On fail goto*//*Label 10189*/ GIMT_Encode4(651959), // Rule ID 10927 //
     /*  651900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  651903 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  651926 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  651929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  651936 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  651938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  651943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  651948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  651953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  651957 */     GIR_RootConstrainSelectedInstOperands,
     /*  651958 */     // GIR_Coverage, 10927,
     /*  651958 */     GIR_EraseRootFromParent_Done,
     /*  651959 */   // Label 10189: @651959
     /*  651959 */   GIM_Try, /*On fail goto*//*Label 10190*/ GIMT_Encode4(652023), // Rule ID 10928 //
     /*  651964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  651967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  651975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  651979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  651983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  651990 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  651990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  651993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  651995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652000 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652021 */     GIR_RootConstrainSelectedInstOperands,
     /*  652022 */     // GIR_Coverage, 10928,
     /*  652022 */     GIR_EraseRootFromParent_Done,
     /*  652023 */   // Label 10190: @652023
     /*  652023 */   GIM_Try, /*On fail goto*//*Label 10191*/ GIMT_Encode4(652087), // Rule ID 10929 //
     /*  652028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  652031 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652043 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652054 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652064 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652081 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652085 */     GIR_RootConstrainSelectedInstOperands,
     /*  652086 */     // GIR_Coverage, 10929,
     /*  652086 */     GIR_EraseRootFromParent_Done,
     /*  652087 */   // Label 10191: @652087
     /*  652087 */   GIM_Try, /*On fail goto*//*Label 10192*/ GIMT_Encode4(652151), // Rule ID 10930 //
     /*  652092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  652095 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652118 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652128 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652149 */     GIR_RootConstrainSelectedInstOperands,
     /*  652150 */     // GIR_Coverage, 10930,
     /*  652150 */     GIR_EraseRootFromParent_Done,
     /*  652151 */   // Label 10192: @652151
     /*  652151 */   GIM_Try, /*On fail goto*//*Label 10193*/ GIMT_Encode4(652215), // Rule ID 10931 //
     /*  652156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  652159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652182 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652192 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652213 */     GIR_RootConstrainSelectedInstOperands,
     /*  652214 */     // GIR_Coverage, 10931,
     /*  652214 */     GIR_EraseRootFromParent_Done,
     /*  652215 */   // Label 10193: @652215
     /*  652215 */   GIM_Try, /*On fail goto*//*Label 10194*/ GIMT_Encode4(652278), // Rule ID 11483 //
     /*  652220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  652223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652245 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652255 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652276 */     GIR_RootConstrainSelectedInstOperands,
     /*  652277 */     // GIR_Coverage, 11483,
     /*  652277 */     GIR_EraseRootFromParent_Done,
     /*  652278 */   // Label 10194: @652278
     /*  652278 */   GIM_Try, /*On fail goto*//*Label 10195*/ GIMT_Encode4(652341), // Rule ID 11484 //
     /*  652283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  652286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652301 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652308 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652318 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652335 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652339 */     GIR_RootConstrainSelectedInstOperands,
     /*  652340 */     // GIR_Coverage, 11484,
     /*  652340 */     GIR_EraseRootFromParent_Done,
     /*  652341 */   // Label 10195: @652341
     /*  652341 */   GIM_Try, /*On fail goto*//*Label 10196*/ GIMT_Encode4(652404), // Rule ID 11485 //
     /*  652346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  652349 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652371 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652381 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652402 */     GIR_RootConstrainSelectedInstOperands,
     /*  652403 */     // GIR_Coverage, 11485,
     /*  652403 */     GIR_EraseRootFromParent_Done,
     /*  652404 */   // Label 10196: @652404
     /*  652404 */   GIM_Try, /*On fail goto*//*Label 10197*/ GIMT_Encode4(652467), // Rule ID 11486 //
     /*  652409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  652412 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652423 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652427 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652434 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652444 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652465 */     GIR_RootConstrainSelectedInstOperands,
     /*  652466 */     // GIR_Coverage, 11486,
     /*  652466 */     GIR_EraseRootFromParent_Done,
     /*  652467 */   // Label 10197: @652467
     /*  652467 */   GIM_Try, /*On fail goto*//*Label 10198*/ GIMT_Encode4(652530), // Rule ID 11487 //
     /*  652472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  652475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  652486 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  652497 */     // (atomic_load_xor:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  652497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_SADDR_RTN),
     /*  652500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  652502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  652507 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  652514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  652519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  652524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652528 */     GIR_RootConstrainSelectedInstOperands,
     /*  652529 */     // GIR_Coverage, 11487,
     /*  652529 */     GIR_EraseRootFromParent_Done,
     /*  652530 */   // Label 10198: @652530
     /*  652530 */   GIM_Try, /*On fail goto*//*Label 10199*/ GIMT_Encode4(652583), // Rule ID 10932 //
     /*  652535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  652538 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652546 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652559 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652567 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652581 */     GIR_RootConstrainSelectedInstOperands,
     /*  652582 */     // GIR_Coverage, 10932,
     /*  652582 */     GIR_EraseRootFromParent_Done,
     /*  652583 */   // Label 10199: @652583
     /*  652583 */   GIM_Try, /*On fail goto*//*Label 10200*/ GIMT_Encode4(652636), // Rule ID 10933 //
     /*  652588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  652591 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652599 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652601 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652612 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652620 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652634 */     GIR_RootConstrainSelectedInstOperands,
     /*  652635 */     // GIR_Coverage, 10933,
     /*  652635 */     GIR_EraseRootFromParent_Done,
     /*  652636 */   // Label 10200: @652636
     /*  652636 */   GIM_Try, /*On fail goto*//*Label 10201*/ GIMT_Encode4(652689), // Rule ID 10934 //
     /*  652641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  652644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652652 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652665 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652673 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652683 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652687 */     GIR_RootConstrainSelectedInstOperands,
     /*  652688 */     // GIR_Coverage, 10934,
     /*  652688 */     GIR_EraseRootFromParent_Done,
     /*  652689 */   // Label 10201: @652689
     /*  652689 */   GIM_Try, /*On fail goto*//*Label 10202*/ GIMT_Encode4(652742), // Rule ID 10935 //
     /*  652694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  652697 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652705 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652718 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652726 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652740 */     GIR_RootConstrainSelectedInstOperands,
     /*  652741 */     // GIR_Coverage, 10935,
     /*  652741 */     GIR_EraseRootFromParent_Done,
     /*  652742 */   // Label 10202: @652742
     /*  652742 */   GIM_Try, /*On fail goto*//*Label 10203*/ GIMT_Encode4(652795), // Rule ID 10936 //
     /*  652747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  652750 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652758 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652771 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652779 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652793 */     GIR_RootConstrainSelectedInstOperands,
     /*  652794 */     // GIR_Coverage, 10936,
     /*  652794 */     GIR_EraseRootFromParent_Done,
     /*  652795 */   // Label 10203: @652795
     /*  652795 */   GIM_Try, /*On fail goto*//*Label 10204*/ GIMT_Encode4(652847), // Rule ID 11488 //
     /*  652800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  652803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652810 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652816 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652823 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652831 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652845 */     GIR_RootConstrainSelectedInstOperands,
     /*  652846 */     // GIR_Coverage, 11488,
     /*  652846 */     GIR_EraseRootFromParent_Done,
     /*  652847 */   // Label 10204: @652847
     /*  652847 */   GIM_Try, /*On fail goto*//*Label 10205*/ GIMT_Encode4(652899), // Rule ID 11489 //
     /*  652852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  652855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652862 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652875 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652883 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652897 */     GIR_RootConstrainSelectedInstOperands,
     /*  652898 */     // GIR_Coverage, 11489,
     /*  652898 */     GIR_EraseRootFromParent_Done,
     /*  652899 */   // Label 10205: @652899
     /*  652899 */   GIM_Try, /*On fail goto*//*Label 10206*/ GIMT_Encode4(652951), // Rule ID 11490 //
     /*  652904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  652907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652914 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652927 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652935 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  652949 */     GIR_RootConstrainSelectedInstOperands,
     /*  652950 */     // GIR_Coverage, 11490,
     /*  652950 */     GIR_EraseRootFromParent_Done,
     /*  652951 */   // Label 10206: @652951
     /*  652951 */   GIM_Try, /*On fail goto*//*Label 10207*/ GIMT_Encode4(653003), // Rule ID 11491 //
     /*  652956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  652959 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  652966 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  652968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  652972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  652979 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  652979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  652982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  652987 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  652989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  652994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  652997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653001 */     GIR_RootConstrainSelectedInstOperands,
     /*  653002 */     // GIR_Coverage, 11491,
     /*  653002 */     GIR_EraseRootFromParent_Done,
     /*  653003 */   // Label 10207: @653003
     /*  653003 */   GIM_Try, /*On fail goto*//*Label 10208*/ GIMT_Encode4(653055), // Rule ID 11492 //
     /*  653008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  653011 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653018 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653024 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653031 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
     /*  653034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653039 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  653049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653053 */     GIR_RootConstrainSelectedInstOperands,
     /*  653054 */     // GIR_Coverage, 11492,
     /*  653054 */     GIR_EraseRootFromParent_Done,
     /*  653055 */   // Label 10208: @653055
     /*  653055 */   GIM_Try, /*On fail goto*//*Label 10209*/ GIMT_Encode4(653112), // Rule ID 10922 //
     /*  653060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  653063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653086 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653096 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653110 */     GIR_RootConstrainSelectedInstOperands,
     /*  653111 */     // GIR_Coverage, 10922,
     /*  653111 */     GIR_EraseRootFromParent_Done,
     /*  653112 */   // Label 10209: @653112
     /*  653112 */   GIM_Try, /*On fail goto*//*Label 10210*/ GIMT_Encode4(653169), // Rule ID 10923 //
     /*  653117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  653120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653143 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653153 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653167 */     GIR_RootConstrainSelectedInstOperands,
     /*  653168 */     // GIR_Coverage, 10923,
     /*  653168 */     GIR_EraseRootFromParent_Done,
     /*  653169 */   // Label 10210: @653169
     /*  653169 */   GIM_Try, /*On fail goto*//*Label 10211*/ GIMT_Encode4(653226), // Rule ID 10924 //
     /*  653174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  653177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653189 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653200 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653210 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653224 */     GIR_RootConstrainSelectedInstOperands,
     /*  653225 */     // GIR_Coverage, 10924,
     /*  653225 */     GIR_EraseRootFromParent_Done,
     /*  653226 */   // Label 10211: @653226
     /*  653226 */   GIM_Try, /*On fail goto*//*Label 10212*/ GIMT_Encode4(653283), // Rule ID 10925 //
     /*  653231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  653234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653257 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653267 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653281 */     GIR_RootConstrainSelectedInstOperands,
     /*  653282 */     // GIR_Coverage, 10925,
     /*  653282 */     GIR_EraseRootFromParent_Done,
     /*  653283 */   // Label 10212: @653283
     /*  653283 */   GIM_Try, /*On fail goto*//*Label 10213*/ GIMT_Encode4(653340), // Rule ID 10926 //
     /*  653288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  653291 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653314 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653324 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653338 */     GIR_RootConstrainSelectedInstOperands,
     /*  653339 */     // GIR_Coverage, 10926,
     /*  653339 */     GIR_EraseRootFromParent_Done,
     /*  653340 */   // Label 10213: @653340
     /*  653340 */   GIM_Try, /*On fail goto*//*Label 10214*/ GIMT_Encode4(653396), // Rule ID 11478 //
     /*  653345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  653348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653363 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653370 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653380 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653394 */     GIR_RootConstrainSelectedInstOperands,
     /*  653395 */     // GIR_Coverage, 11478,
     /*  653395 */     GIR_EraseRootFromParent_Done,
     /*  653396 */   // Label 10214: @653396
     /*  653396 */   GIM_Try, /*On fail goto*//*Label 10215*/ GIMT_Encode4(653452), // Rule ID 11479 //
     /*  653401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  653404 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653426 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653436 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653450 */     GIR_RootConstrainSelectedInstOperands,
     /*  653451 */     // GIR_Coverage, 11479,
     /*  653451 */     GIR_EraseRootFromParent_Done,
     /*  653452 */   // Label 10215: @653452
     /*  653452 */   GIM_Try, /*On fail goto*//*Label 10216*/ GIMT_Encode4(653508), // Rule ID 11480 //
     /*  653457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  653460 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653482 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653492 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653506 */     GIR_RootConstrainSelectedInstOperands,
     /*  653507 */     // GIR_Coverage, 11480,
     /*  653507 */     GIR_EraseRootFromParent_Done,
     /*  653508 */   // Label 10216: @653508
     /*  653508 */   GIM_Try, /*On fail goto*//*Label 10217*/ GIMT_Encode4(653564), // Rule ID 11481 //
     /*  653513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  653516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653538 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653548 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653562 */     GIR_RootConstrainSelectedInstOperands,
     /*  653563 */     // GIR_Coverage, 11481,
     /*  653563 */     GIR_EraseRootFromParent_Done,
     /*  653564 */   // Label 10217: @653564
     /*  653564 */   GIM_Try, /*On fail goto*//*Label 10218*/ GIMT_Encode4(653620), // Rule ID 11482 //
     /*  653569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  653572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  653583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  653594 */     // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  653594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
     /*  653597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  653599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  653604 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  653606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  653611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  653614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653618 */     GIR_RootConstrainSelectedInstOperands,
     /*  653619 */     // GIR_Coverage, 11482,
     /*  653619 */     GIR_EraseRootFromParent_Done,
     /*  653620 */   // Label 10218: @653620
     /*  653620 */   GIM_Reject,
     /*  653621 */ // Label 10088: @653621
     /*  653621 */ GIM_Reject,
     /*  653622 */ // Label 9980: @653622
     /*  653622 */ GIM_Reject,
     /*  653623 */ // Label 25: @653623
     /*  653623 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 10221*/ GIMT_Encode4(667234),
     /*  653634 */ /*GILLT_s32*//*Label 10219*/ GIMT_Encode4(653642),
     /*  653638 */ /*GILLT_s64*//*Label 10220*/ GIMT_Encode4(659734),
     /*  653642 */ // Label 10219: @653642
     /*  653642 */ GIM_Try, /*On fail goto*//*Label 10222*/ GIMT_Encode4(659733),
     /*  653647 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  653650 */   GIM_Try, /*On fail goto*//*Label 10223*/ GIMT_Encode4(653712), // Rule ID 20938 //
     /*  653655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  653658 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653665 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  653678 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  653678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64),
     /*  653681 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  653683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  653688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  653693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  653698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  653703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  653706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653710 */     GIR_RootConstrainSelectedInstOperands,
     /*  653711 */     // GIR_Coverage, 20938,
     /*  653711 */     GIR_EraseRootFromParent_Done,
     /*  653712 */   // Label 10223: @653712
     /*  653712 */   GIM_Try, /*On fail goto*//*Label 10224*/ GIMT_Encode4(653774), // Rule ID 20939 //
     /*  653717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  653720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653727 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653729 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  653740 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  653740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64),
     /*  653743 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  653745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  653750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  653755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  653760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  653765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  653768 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653772 */     GIR_RootConstrainSelectedInstOperands,
     /*  653773 */     // GIR_Coverage, 20939,
     /*  653773 */     GIR_EraseRootFromParent_Done,
     /*  653774 */   // Label 10224: @653774
     /*  653774 */   GIM_Try, /*On fail goto*//*Label 10225*/ GIMT_Encode4(653836), // Rule ID 20940 //
     /*  653779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  653782 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653789 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  653802 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  653802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64),
     /*  653805 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  653807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  653812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  653817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  653822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  653827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  653830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653834 */     GIR_RootConstrainSelectedInstOperands,
     /*  653835 */     // GIR_Coverage, 20940,
     /*  653835 */     GIR_EraseRootFromParent_Done,
     /*  653836 */   // Label 10225: @653836
     /*  653836 */   GIM_Try, /*On fail goto*//*Label 10226*/ GIMT_Encode4(653898), // Rule ID 20941 //
     /*  653841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  653844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653851 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  653864 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  653864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64),
     /*  653867 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  653869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  653874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  653879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  653884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  653889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  653892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653896 */     GIR_RootConstrainSelectedInstOperands,
     /*  653897 */     // GIR_Coverage, 20941,
     /*  653897 */     GIR_EraseRootFromParent_Done,
     /*  653898 */   // Label 10226: @653898
     /*  653898 */   GIM_Try, /*On fail goto*//*Label 10227*/ GIMT_Encode4(653960), // Rule ID 20942 //
     /*  653903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  653906 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653913 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  653926 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  653926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64),
     /*  653929 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  653931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  653936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  653941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  653946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  653951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  653954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  653958 */     GIR_RootConstrainSelectedInstOperands,
     /*  653959 */     // GIR_Coverage, 20942,
     /*  653959 */     GIR_EraseRootFromParent_Done,
     /*  653960 */   // Label 10227: @653960
     /*  653960 */   GIM_Try, /*On fail goto*//*Label 10228*/ GIMT_Encode4(654022), // Rule ID 20958 //
     /*  653965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  653968 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  653975 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  653977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  653981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  653988 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  653988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64),
     /*  653991 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  653993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  653998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  654016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654020 */     GIR_RootConstrainSelectedInstOperands,
     /*  654021 */     // GIR_Coverage, 20958,
     /*  654021 */     GIR_EraseRootFromParent_Done,
     /*  654022 */   // Label 10228: @654022
     /*  654022 */   GIM_Try, /*On fail goto*//*Label 10229*/ GIMT_Encode4(654084), // Rule ID 20959 //
     /*  654027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  654030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654037 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  654039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654050 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64),
     /*  654053 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  654078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654082 */     GIR_RootConstrainSelectedInstOperands,
     /*  654083 */     // GIR_Coverage, 20959,
     /*  654083 */     GIR_EraseRootFromParent_Done,
     /*  654084 */   // Label 10229: @654084
     /*  654084 */   GIM_Try, /*On fail goto*//*Label 10230*/ GIMT_Encode4(654146), // Rule ID 20960 //
     /*  654089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  654092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654099 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  654101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654112 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64),
     /*  654115 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  654140 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654144 */     GIR_RootConstrainSelectedInstOperands,
     /*  654145 */     // GIR_Coverage, 20960,
     /*  654145 */     GIR_EraseRootFromParent_Done,
     /*  654146 */   // Label 10230: @654146
     /*  654146 */   GIM_Try, /*On fail goto*//*Label 10231*/ GIMT_Encode4(654208), // Rule ID 20961 //
     /*  654151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  654154 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654161 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  654163 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654174 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64),
     /*  654177 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  654202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654206 */     GIR_RootConstrainSelectedInstOperands,
     /*  654207 */     // GIR_Coverage, 20961,
     /*  654207 */     GIR_EraseRootFromParent_Done,
     /*  654208 */   // Label 10231: @654208
     /*  654208 */   GIM_Try, /*On fail goto*//*Label 10232*/ GIMT_Encode4(654270), // Rule ID 20962 //
     /*  654213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  654216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  654225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654236 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64),
     /*  654239 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  654264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654268 */     GIR_RootConstrainSelectedInstOperands,
     /*  654269 */     // GIR_Coverage, 20962,
     /*  654269 */     GIR_EraseRootFromParent_Done,
     /*  654270 */   // Label 10232: @654270
     /*  654270 */   GIM_Try, /*On fail goto*//*Label 10233*/ GIMT_Encode4(654336), // Rule ID 20928 //
     /*  654275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  654278 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654300 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN),
     /*  654303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654305 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654334 */     GIR_RootConstrainSelectedInstOperands,
     /*  654335 */     // GIR_Coverage, 20928,
     /*  654335 */     GIR_EraseRootFromParent_Done,
     /*  654336 */   // Label 10233: @654336
     /*  654336 */   GIM_Try, /*On fail goto*//*Label 10234*/ GIMT_Encode4(654402), // Rule ID 20929 //
     /*  654341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  654344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654366 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN),
     /*  654369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654371 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654400 */     GIR_RootConstrainSelectedInstOperands,
     /*  654401 */     // GIR_Coverage, 20929,
     /*  654401 */     GIR_EraseRootFromParent_Done,
     /*  654402 */   // Label 10234: @654402
     /*  654402 */   GIM_Try, /*On fail goto*//*Label 10235*/ GIMT_Encode4(654468), // Rule ID 20930 //
     /*  654407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  654410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654432 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN),
     /*  654435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654437 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654466 */     GIR_RootConstrainSelectedInstOperands,
     /*  654467 */     // GIR_Coverage, 20930,
     /*  654467 */     GIR_EraseRootFromParent_Done,
     /*  654468 */   // Label 10235: @654468
     /*  654468 */   GIM_Try, /*On fail goto*//*Label 10236*/ GIMT_Encode4(654534), // Rule ID 20931 //
     /*  654473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  654476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654498 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN),
     /*  654501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654503 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654532 */     GIR_RootConstrainSelectedInstOperands,
     /*  654533 */     // GIR_Coverage, 20931,
     /*  654533 */     GIR_EraseRootFromParent_Done,
     /*  654534 */   // Label 10236: @654534
     /*  654534 */   GIM_Try, /*On fail goto*//*Label 10237*/ GIMT_Encode4(654600), // Rule ID 20932 //
     /*  654539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  654542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654564 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN),
     /*  654567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654569 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654598 */     GIR_RootConstrainSelectedInstOperands,
     /*  654599 */     // GIR_Coverage, 20932,
     /*  654599 */     GIR_EraseRootFromParent_Done,
     /*  654600 */   // Label 10237: @654600
     /*  654600 */   GIM_Try, /*On fail goto*//*Label 10238*/ GIMT_Encode4(654666), // Rule ID 20948 //
     /*  654605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  654608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654630 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN),
     /*  654633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654635 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654664 */     GIR_RootConstrainSelectedInstOperands,
     /*  654665 */     // GIR_Coverage, 20948,
     /*  654665 */     GIR_EraseRootFromParent_Done,
     /*  654666 */   // Label 10238: @654666
     /*  654666 */   GIM_Try, /*On fail goto*//*Label 10239*/ GIMT_Encode4(654732), // Rule ID 20949 //
     /*  654671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  654674 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654696 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN),
     /*  654699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654701 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654730 */     GIR_RootConstrainSelectedInstOperands,
     /*  654731 */     // GIR_Coverage, 20949,
     /*  654731 */     GIR_EraseRootFromParent_Done,
     /*  654732 */   // Label 10239: @654732
     /*  654732 */   GIM_Try, /*On fail goto*//*Label 10240*/ GIMT_Encode4(654798), // Rule ID 20950 //
     /*  654737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  654740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654762 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN),
     /*  654765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654767 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654796 */     GIR_RootConstrainSelectedInstOperands,
     /*  654797 */     // GIR_Coverage, 20950,
     /*  654797 */     GIR_EraseRootFromParent_Done,
     /*  654798 */   // Label 10240: @654798
     /*  654798 */   GIM_Try, /*On fail goto*//*Label 10241*/ GIMT_Encode4(654864), // Rule ID 20951 //
     /*  654803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  654806 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654828 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN),
     /*  654831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654833 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654862 */     GIR_RootConstrainSelectedInstOperands,
     /*  654863 */     // GIR_Coverage, 20951,
     /*  654863 */     GIR_EraseRootFromParent_Done,
     /*  654864 */   // Label 10241: @654864
     /*  654864 */   GIM_Try, /*On fail goto*//*Label 10242*/ GIMT_Encode4(654930), // Rule ID 20952 //
     /*  654869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  654872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  654883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  654894 */     // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN),
     /*  654897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  654899 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  654906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  654916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  654921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  654924 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654928 */     GIR_RootConstrainSelectedInstOperands,
     /*  654929 */     // GIR_Coverage, 20952,
     /*  654929 */     GIR_EraseRootFromParent_Done,
     /*  654930 */   // Label 10242: @654930
     /*  654930 */   GIM_Try, /*On fail goto*//*Label 10243*/ GIMT_Encode4(654987), // Rule ID 20933 //
     /*  654935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  654938 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  654945 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  654947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  654951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  654958 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  654958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
     /*  654961 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  654963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  654968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  654973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  654978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  654981 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  654985 */     GIR_RootConstrainSelectedInstOperands,
     /*  654986 */     // GIR_Coverage, 20933,
     /*  654986 */     GIR_EraseRootFromParent_Done,
     /*  654987 */   // Label 10243: @654987
     /*  654987 */   GIM_Try, /*On fail goto*//*Label 10244*/ GIMT_Encode4(655044), // Rule ID 20934 //
     /*  654992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  654995 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655002 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655004 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655008 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655015 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
     /*  655018 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655042 */     GIR_RootConstrainSelectedInstOperands,
     /*  655043 */     // GIR_Coverage, 20934,
     /*  655043 */     GIR_EraseRootFromParent_Done,
     /*  655044 */   // Label 10244: @655044
     /*  655044 */   GIM_Try, /*On fail goto*//*Label 10245*/ GIMT_Encode4(655101), // Rule ID 20935 //
     /*  655049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  655052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655059 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655072 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
     /*  655075 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655099 */     GIR_RootConstrainSelectedInstOperands,
     /*  655100 */     // GIR_Coverage, 20935,
     /*  655100 */     GIR_EraseRootFromParent_Done,
     /*  655101 */   // Label 10245: @655101
     /*  655101 */   GIM_Try, /*On fail goto*//*Label 10246*/ GIMT_Encode4(655158), // Rule ID 20936 //
     /*  655106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  655109 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655116 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655118 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655122 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655129 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
     /*  655132 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655156 */     GIR_RootConstrainSelectedInstOperands,
     /*  655157 */     // GIR_Coverage, 20936,
     /*  655157 */     GIR_EraseRootFromParent_Done,
     /*  655158 */   // Label 10246: @655158
     /*  655158 */   GIM_Try, /*On fail goto*//*Label 10247*/ GIMT_Encode4(655215), // Rule ID 20937 //
     /*  655163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  655166 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655173 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655175 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655186 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
     /*  655189 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655213 */     GIR_RootConstrainSelectedInstOperands,
     /*  655214 */     // GIR_Coverage, 20937,
     /*  655214 */     GIR_EraseRootFromParent_Done,
     /*  655215 */   // Label 10247: @655215
     /*  655215 */   GIM_Try, /*On fail goto*//*Label 10248*/ GIMT_Encode4(655272), // Rule ID 20953 //
     /*  655220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  655223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655230 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655243 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
     /*  655246 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655270 */     GIR_RootConstrainSelectedInstOperands,
     /*  655271 */     // GIR_Coverage, 20953,
     /*  655271 */     GIR_EraseRootFromParent_Done,
     /*  655272 */   // Label 10248: @655272
     /*  655272 */   GIM_Try, /*On fail goto*//*Label 10249*/ GIMT_Encode4(655329), // Rule ID 20954 //
     /*  655277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  655280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655287 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655300 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
     /*  655303 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655327 */     GIR_RootConstrainSelectedInstOperands,
     /*  655328 */     // GIR_Coverage, 20954,
     /*  655328 */     GIR_EraseRootFromParent_Done,
     /*  655329 */   // Label 10249: @655329
     /*  655329 */   GIM_Try, /*On fail goto*//*Label 10250*/ GIMT_Encode4(655386), // Rule ID 20955 //
     /*  655334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  655337 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655344 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655346 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655350 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655357 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
     /*  655360 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655384 */     GIR_RootConstrainSelectedInstOperands,
     /*  655385 */     // GIR_Coverage, 20955,
     /*  655385 */     GIR_EraseRootFromParent_Done,
     /*  655386 */   // Label 10250: @655386
     /*  655386 */   GIM_Try, /*On fail goto*//*Label 10251*/ GIMT_Encode4(655443), // Rule ID 20956 //
     /*  655391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  655394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655401 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655414 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
     /*  655417 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655441 */     GIR_RootConstrainSelectedInstOperands,
     /*  655442 */     // GIR_Coverage, 20956,
     /*  655442 */     GIR_EraseRootFromParent_Done,
     /*  655443 */   // Label 10251: @655443
     /*  655443 */   GIM_Try, /*On fail goto*//*Label 10252*/ GIMT_Encode4(655500), // Rule ID 20957 //
     /*  655448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  655451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655458 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  655460 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655471 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
     /*  655474 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  655494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655498 */     GIR_RootConstrainSelectedInstOperands,
     /*  655499 */     // GIR_Coverage, 20957,
     /*  655499 */     GIR_EraseRootFromParent_Done,
     /*  655500 */   // Label 10252: @655500
     /*  655500 */   GIM_Try, /*On fail goto*//*Label 10253*/ GIMT_Encode4(655561), // Rule ID 20923 //
     /*  655505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  655508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655530 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
     /*  655533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655535 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655559 */     GIR_RootConstrainSelectedInstOperands,
     /*  655560 */     // GIR_Coverage, 20923,
     /*  655560 */     GIR_EraseRootFromParent_Done,
     /*  655561 */   // Label 10253: @655561
     /*  655561 */   GIM_Try, /*On fail goto*//*Label 10254*/ GIMT_Encode4(655622), // Rule ID 20924 //
     /*  655566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  655569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655591 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
     /*  655594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655596 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655616 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655620 */     GIR_RootConstrainSelectedInstOperands,
     /*  655621 */     // GIR_Coverage, 20924,
     /*  655621 */     GIR_EraseRootFromParent_Done,
     /*  655622 */   // Label 10254: @655622
     /*  655622 */   GIM_Try, /*On fail goto*//*Label 10255*/ GIMT_Encode4(655683), // Rule ID 20925 //
     /*  655627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  655630 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655641 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655645 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655652 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
     /*  655655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655657 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655681 */     GIR_RootConstrainSelectedInstOperands,
     /*  655682 */     // GIR_Coverage, 20925,
     /*  655682 */     GIR_EraseRootFromParent_Done,
     /*  655683 */   // Label 10255: @655683
     /*  655683 */   GIM_Try, /*On fail goto*//*Label 10256*/ GIMT_Encode4(655744), // Rule ID 20926 //
     /*  655688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  655691 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655706 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655713 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
     /*  655716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655718 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655742 */     GIR_RootConstrainSelectedInstOperands,
     /*  655743 */     // GIR_Coverage, 20926,
     /*  655743 */     GIR_EraseRootFromParent_Done,
     /*  655744 */   // Label 10256: @655744
     /*  655744 */   GIM_Try, /*On fail goto*//*Label 10257*/ GIMT_Encode4(655805), // Rule ID 20927 //
     /*  655749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  655752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655774 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
     /*  655777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655779 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655803 */     GIR_RootConstrainSelectedInstOperands,
     /*  655804 */     // GIR_Coverage, 20927,
     /*  655804 */     GIR_EraseRootFromParent_Done,
     /*  655805 */   // Label 10257: @655805
     /*  655805 */   GIM_Try, /*On fail goto*//*Label 10258*/ GIMT_Encode4(655866), // Rule ID 20943 //
     /*  655810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  655813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655824 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655828 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655835 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
     /*  655838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655840 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655864 */     GIR_RootConstrainSelectedInstOperands,
     /*  655865 */     // GIR_Coverage, 20943,
     /*  655865 */     GIR_EraseRootFromParent_Done,
     /*  655866 */   // Label 10258: @655866
     /*  655866 */   GIM_Try, /*On fail goto*//*Label 10259*/ GIMT_Encode4(655927), // Rule ID 20944 //
     /*  655871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  655874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655896 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
     /*  655899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655901 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655925 */     GIR_RootConstrainSelectedInstOperands,
     /*  655926 */     // GIR_Coverage, 20944,
     /*  655926 */     GIR_EraseRootFromParent_Done,
     /*  655927 */   // Label 10259: @655927
     /*  655927 */   GIM_Try, /*On fail goto*//*Label 10260*/ GIMT_Encode4(655988), // Rule ID 20945 //
     /*  655932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  655935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  655942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  655946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  655950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  655957 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  655957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
     /*  655960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  655962 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  655964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  655969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  655974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  655979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  655982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  655986 */     GIR_RootConstrainSelectedInstOperands,
     /*  655987 */     // GIR_Coverage, 20945,
     /*  655987 */     GIR_EraseRootFromParent_Done,
     /*  655988 */   // Label 10260: @655988
     /*  655988 */   GIM_Try, /*On fail goto*//*Label 10261*/ GIMT_Encode4(656049), // Rule ID 20946 //
     /*  655993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  655996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  656003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  656007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  656018 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  656018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
     /*  656021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  656023 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  656025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  656030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  656035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  656040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656047 */     GIR_RootConstrainSelectedInstOperands,
     /*  656048 */     // GIR_Coverage, 20946,
     /*  656048 */     GIR_EraseRootFromParent_Done,
     /*  656049 */   // Label 10261: @656049
     /*  656049 */   GIM_Try, /*On fail goto*//*Label 10262*/ GIMT_Encode4(656110), // Rule ID 20947 //
     /*  656054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  656057 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  656064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  656068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  656079 */     // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  656079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
     /*  656082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  656084 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  656086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  656091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  656096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  656101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656104 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656108 */     GIR_RootConstrainSelectedInstOperands,
     /*  656109 */     // GIR_Coverage, 20947,
     /*  656109 */     GIR_EraseRootFromParent_Done,
     /*  656110 */   // Label 10262: @656110
     /*  656110 */   GIM_Try, /*On fail goto*//*Label 10263*/ GIMT_Encode4(656160), // Rule ID 30420 //
     /*  656115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  656118 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656123 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656136 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656144 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656158 */     GIR_RootConstrainSelectedInstOperands,
     /*  656159 */     // GIR_Coverage, 30420,
     /*  656159 */     GIR_EraseRootFromParent_Done,
     /*  656160 */   // Label 10263: @656160
     /*  656160 */   GIM_Try, /*On fail goto*//*Label 10264*/ GIMT_Encode4(656210), // Rule ID 30421 //
     /*  656165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  656168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656173 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656175 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656186 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656194 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656208 */     GIR_RootConstrainSelectedInstOperands,
     /*  656209 */     // GIR_Coverage, 30421,
     /*  656209 */     GIR_EraseRootFromParent_Done,
     /*  656210 */   // Label 10264: @656210
     /*  656210 */   GIM_Try, /*On fail goto*//*Label 10265*/ GIMT_Encode4(656260), // Rule ID 30422 //
     /*  656215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  656218 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656236 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656244 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656258 */     GIR_RootConstrainSelectedInstOperands,
     /*  656259 */     // GIR_Coverage, 30422,
     /*  656259 */     GIR_EraseRootFromParent_Done,
     /*  656260 */   // Label 10265: @656260
     /*  656260 */   GIM_Try, /*On fail goto*//*Label 10266*/ GIMT_Encode4(656310), // Rule ID 30423 //
     /*  656265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  656268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656273 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656286 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656294 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656308 */     GIR_RootConstrainSelectedInstOperands,
     /*  656309 */     // GIR_Coverage, 30423,
     /*  656309 */     GIR_EraseRootFromParent_Done,
     /*  656310 */   // Label 10266: @656310
     /*  656310 */   GIM_Try, /*On fail goto*//*Label 10267*/ GIMT_Encode4(656360), // Rule ID 30424 //
     /*  656315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  656318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656323 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656336 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656344 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656358 */     GIR_RootConstrainSelectedInstOperands,
     /*  656359 */     // GIR_Coverage, 30424,
     /*  656359 */     GIR_EraseRootFromParent_Done,
     /*  656360 */   // Label 10267: @656360
     /*  656360 */   GIM_Try, /*On fail goto*//*Label 10268*/ GIMT_Encode4(656410), // Rule ID 30426 //
     /*  656365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  656368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656373 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656386 */     // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_i32>>  =>  (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9),
     /*  656389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656394 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656408 */     GIR_RootConstrainSelectedInstOperands,
     /*  656409 */     // GIR_Coverage, 30426,
     /*  656409 */     GIR_EraseRootFromParent_Done,
     /*  656410 */   // Label 10268: @656410
     /*  656410 */   GIM_Try, /*On fail goto*//*Label 10269*/ GIMT_Encode4(656460), // Rule ID 30427 //
     /*  656415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  656418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656423 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656425 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656436 */     // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_i32>>  =>  (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9),
     /*  656439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656444 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656458 */     GIR_RootConstrainSelectedInstOperands,
     /*  656459 */     // GIR_Coverage, 30427,
     /*  656459 */     GIR_EraseRootFromParent_Done,
     /*  656460 */   // Label 10269: @656460
     /*  656460 */   GIM_Try, /*On fail goto*//*Label 10270*/ GIMT_Encode4(656510), // Rule ID 30428 //
     /*  656465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  656468 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656473 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656486 */     // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_i32>>  =>  (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9),
     /*  656489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656494 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656508 */     GIR_RootConstrainSelectedInstOperands,
     /*  656509 */     // GIR_Coverage, 30428,
     /*  656509 */     GIR_EraseRootFromParent_Done,
     /*  656510 */   // Label 10270: @656510
     /*  656510 */   GIM_Try, /*On fail goto*//*Label 10271*/ GIMT_Encode4(656560), // Rule ID 30429 //
     /*  656515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  656518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656523 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656525 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656529 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656536 */     // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_i32>>  =>  (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9),
     /*  656539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656544 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656558 */     GIR_RootConstrainSelectedInstOperands,
     /*  656559 */     // GIR_Coverage, 30429,
     /*  656559 */     GIR_EraseRootFromParent_Done,
     /*  656560 */   // Label 10271: @656560
     /*  656560 */   GIM_Try, /*On fail goto*//*Label 10272*/ GIMT_Encode4(656610), // Rule ID 30430 //
     /*  656565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  656568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656573 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656575 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656586 */     // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_i32>>  =>  (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9),
     /*  656589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656594 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656608 */     GIR_RootConstrainSelectedInstOperands,
     /*  656609 */     // GIR_Coverage, 30430,
     /*  656609 */     GIR_EraseRootFromParent_Done,
     /*  656610 */   // Label 10272: @656610
     /*  656610 */   GIM_Try, /*On fail goto*//*Label 10273*/ GIMT_Encode4(656660), // Rule ID 30432 //
     /*  656615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  656618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  656623 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656636 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  656636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656644 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656654 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656658 */     GIR_RootConstrainSelectedInstOperands,
     /*  656659 */     // GIR_Coverage, 30432,
     /*  656659 */     GIR_EraseRootFromParent_Done,
     /*  656660 */   // Label 10273: @656660
     /*  656660 */   GIM_Try, /*On fail goto*//*Label 10274*/ GIMT_Encode4(656710), // Rule ID 30433 //
     /*  656665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  656668 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  656673 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656686 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  656686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656694 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656708 */     GIR_RootConstrainSelectedInstOperands,
     /*  656709 */     // GIR_Coverage, 30433,
     /*  656709 */     GIR_EraseRootFromParent_Done,
     /*  656710 */   // Label 10274: @656710
     /*  656710 */   GIM_Try, /*On fail goto*//*Label 10275*/ GIMT_Encode4(656760), // Rule ID 30434 //
     /*  656715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  656718 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  656723 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656736 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  656736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656744 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656758 */     GIR_RootConstrainSelectedInstOperands,
     /*  656759 */     // GIR_Coverage, 30434,
     /*  656759 */     GIR_EraseRootFromParent_Done,
     /*  656760 */   // Label 10275: @656760
     /*  656760 */   GIM_Try, /*On fail goto*//*Label 10276*/ GIMT_Encode4(656810), // Rule ID 30435 //
     /*  656765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  656768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  656773 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656786 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  656786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656794 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656808 */     GIR_RootConstrainSelectedInstOperands,
     /*  656809 */     // GIR_Coverage, 30435,
     /*  656809 */     GIR_EraseRootFromParent_Done,
     /*  656810 */   // Label 10276: @656810
     /*  656810 */   GIM_Try, /*On fail goto*//*Label 10277*/ GIMT_Encode4(656860), // Rule ID 30436 //
     /*  656815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  656818 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  656823 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  656825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656836 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  656836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
     /*  656839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656844 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  656854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656858 */     GIR_RootConstrainSelectedInstOperands,
     /*  656859 */     // GIR_Coverage, 30436,
     /*  656859 */     GIR_EraseRootFromParent_Done,
     /*  656860 */   // Label 10277: @656860
     /*  656860 */   GIM_Try, /*On fail goto*//*Label 10278*/ GIMT_Encode4(656914), // Rule ID 30419 //
     /*  656865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  656868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  656877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656888 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_i32>>  =>  (DS_MAX_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32),
     /*  656891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  656893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656898 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656912 */     GIR_RootConstrainSelectedInstOperands,
     /*  656913 */     // GIR_Coverage, 30419,
     /*  656913 */     GIR_EraseRootFromParent_Done,
     /*  656914 */   // Label 10278: @656914
     /*  656914 */   GIM_Try, /*On fail goto*//*Label 10279*/ GIMT_Encode4(656968), // Rule ID 30425 //
     /*  656919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  656922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  656927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  656931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656942 */     // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_i32>>  =>  (DS_MAX_RTN_I32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  656942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32_gfx9),
     /*  656945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  656947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  656952 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  656954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  656959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  656962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  656966 */     GIR_RootConstrainSelectedInstOperands,
     /*  656967 */     // GIR_Coverage, 30425,
     /*  656967 */     GIR_EraseRootFromParent_Done,
     /*  656968 */   // Label 10279: @656968
     /*  656968 */   GIM_Try, /*On fail goto*//*Label 10280*/ GIMT_Encode4(657022), // Rule ID 30431 //
     /*  656973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  656976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  656981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  656985 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  656989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  656996 */     // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_i32>>  =>  (DS_MAX_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  656996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32),
     /*  656999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  657006 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  657008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  657016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657020 */     GIR_RootConstrainSelectedInstOperands,
     /*  657021 */     // GIR_Coverage, 30431,
     /*  657021 */     GIR_EraseRootFromParent_Done,
     /*  657022 */   // Label 10280: @657022
     /*  657022 */   GIM_Try, /*On fail goto*//*Label 10281*/ GIMT_Encode4(657081), // Rule ID 12961 //
     /*  657027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  657030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657037 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  657050 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR),
     /*  657053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657058 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657079 */     GIR_RootConstrainSelectedInstOperands,
     /*  657080 */     // GIR_Coverage, 12961,
     /*  657080 */     GIR_EraseRootFromParent_Done,
     /*  657081 */   // Label 10281: @657081
     /*  657081 */   GIM_Try, /*On fail goto*//*Label 10282*/ GIMT_Encode4(657140), // Rule ID 12962 //
     /*  657086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  657089 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657096 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657102 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  657109 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR),
     /*  657112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657117 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657138 */     GIR_RootConstrainSelectedInstOperands,
     /*  657139 */     // GIR_Coverage, 12962,
     /*  657139 */     GIR_EraseRootFromParent_Done,
     /*  657140 */   // Label 10282: @657140
     /*  657140 */   GIM_Try, /*On fail goto*//*Label 10283*/ GIMT_Encode4(657199), // Rule ID 12963 //
     /*  657145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  657148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657155 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  657168 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR),
     /*  657171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657176 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657197 */     GIR_RootConstrainSelectedInstOperands,
     /*  657198 */     // GIR_Coverage, 12963,
     /*  657198 */     GIR_EraseRootFromParent_Done,
     /*  657199 */   // Label 10283: @657199
     /*  657199 */   GIM_Try, /*On fail goto*//*Label 10284*/ GIMT_Encode4(657258), // Rule ID 12964 //
     /*  657204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  657207 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657214 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  657227 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR),
     /*  657230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657235 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657252 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657256 */     GIR_RootConstrainSelectedInstOperands,
     /*  657257 */     // GIR_Coverage, 12964,
     /*  657257 */     GIR_EraseRootFromParent_Done,
     /*  657258 */   // Label 10284: @657258
     /*  657258 */   GIM_Try, /*On fail goto*//*Label 10285*/ GIMT_Encode4(657317), // Rule ID 12965 //
     /*  657263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  657266 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657273 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  657286 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR),
     /*  657289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657294 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657315 */     GIR_RootConstrainSelectedInstOperands,
     /*  657316 */     // GIR_Coverage, 12965,
     /*  657316 */     GIR_EraseRootFromParent_Done,
     /*  657317 */   // Label 10285: @657317
     /*  657317 */   GIM_Try, /*On fail goto*//*Label 10286*/ GIMT_Encode4(657380), // Rule ID 12971 //
     /*  657322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  657325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  657336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  657347 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN),
     /*  657350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657357 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657378 */     GIR_RootConstrainSelectedInstOperands,
     /*  657379 */     // GIR_Coverage, 12971,
     /*  657379 */     GIR_EraseRootFromParent_Done,
     /*  657380 */   // Label 10286: @657380
     /*  657380 */   GIM_Try, /*On fail goto*//*Label 10287*/ GIMT_Encode4(657432), // Rule ID 12956 //
     /*  657385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  657388 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657395 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657397 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657401 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657408 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX),
     /*  657411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657416 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  657426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657430 */     GIR_RootConstrainSelectedInstOperands,
     /*  657431 */     // GIR_Coverage, 12956,
     /*  657431 */     GIR_EraseRootFromParent_Done,
     /*  657432 */   // Label 10287: @657432
     /*  657432 */   GIM_Try, /*On fail goto*//*Label 10288*/ GIMT_Encode4(657484), // Rule ID 12957 //
     /*  657437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  657440 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657447 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657460 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX),
     /*  657463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657468 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  657478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657482 */     GIR_RootConstrainSelectedInstOperands,
     /*  657483 */     // GIR_Coverage, 12957,
     /*  657483 */     GIR_EraseRootFromParent_Done,
     /*  657484 */   // Label 10288: @657484
     /*  657484 */   GIM_Try, /*On fail goto*//*Label 10289*/ GIMT_Encode4(657536), // Rule ID 12958 //
     /*  657489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  657492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657499 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657512 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX),
     /*  657515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657520 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  657530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657534 */     GIR_RootConstrainSelectedInstOperands,
     /*  657535 */     // GIR_Coverage, 12958,
     /*  657535 */     GIR_EraseRootFromParent_Done,
     /*  657536 */   // Label 10289: @657536
     /*  657536 */   GIM_Try, /*On fail goto*//*Label 10290*/ GIMT_Encode4(657588), // Rule ID 12959 //
     /*  657541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  657544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657551 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657564 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX),
     /*  657567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657572 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  657582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657586 */     GIR_RootConstrainSelectedInstOperands,
     /*  657587 */     // GIR_Coverage, 12959,
     /*  657587 */     GIR_EraseRootFromParent_Done,
     /*  657588 */   // Label 10290: @657588
     /*  657588 */   GIM_Try, /*On fail goto*//*Label 10291*/ GIMT_Encode4(657640), // Rule ID 12960 //
     /*  657593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  657596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657603 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657616 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX),
     /*  657619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657624 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  657634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657638 */     GIR_RootConstrainSelectedInstOperands,
     /*  657639 */     // GIR_Coverage, 12960,
     /*  657639 */     GIR_EraseRootFromParent_Done,
     /*  657640 */   // Label 10291: @657640
     /*  657640 */   GIM_Try, /*On fail goto*//*Label 10292*/ GIMT_Encode4(657696), // Rule ID 12966 //
     /*  657645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  657648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  657659 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657670 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN),
     /*  657673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657680 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  657690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657694 */     GIR_RootConstrainSelectedInstOperands,
     /*  657695 */     // GIR_Coverage, 12966,
     /*  657695 */     GIR_EraseRootFromParent_Done,
     /*  657696 */   // Label 10292: @657696
     /*  657696 */   GIM_Try, /*On fail goto*//*Label 10293*/ GIMT_Encode4(657752), // Rule ID 12967 //
     /*  657701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  657704 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  657715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657726 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN),
     /*  657729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657736 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  657746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657750 */     GIR_RootConstrainSelectedInstOperands,
     /*  657751 */     // GIR_Coverage, 12967,
     /*  657751 */     GIR_EraseRootFromParent_Done,
     /*  657752 */   // Label 10293: @657752
     /*  657752 */   GIM_Try, /*On fail goto*//*Label 10294*/ GIMT_Encode4(657808), // Rule ID 12968 //
     /*  657757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  657760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  657771 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657782 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN),
     /*  657785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657792 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  657802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657806 */     GIR_RootConstrainSelectedInstOperands,
     /*  657807 */     // GIR_Coverage, 12968,
     /*  657807 */     GIR_EraseRootFromParent_Done,
     /*  657808 */   // Label 10294: @657808
     /*  657808 */   GIM_Try, /*On fail goto*//*Label 10295*/ GIMT_Encode4(657864), // Rule ID 12969 //
     /*  657813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  657816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  657827 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657838 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN),
     /*  657841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657848 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  657858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657862 */     GIR_RootConstrainSelectedInstOperands,
     /*  657863 */     // GIR_Coverage, 12969,
     /*  657863 */     GIR_EraseRootFromParent_Done,
     /*  657864 */   // Label 10295: @657864
     /*  657864 */   GIM_Try, /*On fail goto*//*Label 10296*/ GIMT_Encode4(657920), // Rule ID 12970 //
     /*  657869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  657872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  657883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  657894 */     // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  657894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN),
     /*  657897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  657899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  657904 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  657911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  657914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657918 */     GIR_RootConstrainSelectedInstOperands,
     /*  657919 */     // GIR_Coverage, 12970,
     /*  657919 */     GIR_EraseRootFromParent_Done,
     /*  657920 */   // Label 10296: @657920
     /*  657920 */   GIM_Try, /*On fail goto*//*Label 10297*/ GIMT_Encode4(657980), // Rule ID 10561 //
     /*  657925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  657928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657936 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  657942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  657949 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  657949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  657952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  657957 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  657959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  657964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  657969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  657974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  657978 */     GIR_RootConstrainSelectedInstOperands,
     /*  657979 */     // GIR_Coverage, 10561,
     /*  657979 */     GIR_EraseRootFromParent_Done,
     /*  657980 */   // Label 10297: @657980
     /*  657980 */   GIM_Try, /*On fail goto*//*Label 10298*/ GIMT_Encode4(658040), // Rule ID 10562 //
     /*  657985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  657988 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  657996 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  657998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658009 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658017 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658038 */     GIR_RootConstrainSelectedInstOperands,
     /*  658039 */     // GIR_Coverage, 10562,
     /*  658039 */     GIR_EraseRootFromParent_Done,
     /*  658040 */   // Label 10298: @658040
     /*  658040 */   GIM_Try, /*On fail goto*//*Label 10299*/ GIMT_Encode4(658100), // Rule ID 10563 //
     /*  658045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  658048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658056 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658058 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658062 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658069 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658077 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658098 */     GIR_RootConstrainSelectedInstOperands,
     /*  658099 */     // GIR_Coverage, 10563,
     /*  658099 */     GIR_EraseRootFromParent_Done,
     /*  658100 */   // Label 10299: @658100
     /*  658100 */   GIM_Try, /*On fail goto*//*Label 10300*/ GIMT_Encode4(658160), // Rule ID 10564 //
     /*  658105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  658108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658116 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658118 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658122 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658129 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658137 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658158 */     GIR_RootConstrainSelectedInstOperands,
     /*  658159 */     // GIR_Coverage, 10564,
     /*  658159 */     GIR_EraseRootFromParent_Done,
     /*  658160 */   // Label 10300: @658160
     /*  658160 */   GIM_Try, /*On fail goto*//*Label 10301*/ GIMT_Encode4(658220), // Rule ID 10565 //
     /*  658165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  658168 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658176 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658182 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658189 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658197 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658218 */     GIR_RootConstrainSelectedInstOperands,
     /*  658219 */     // GIR_Coverage, 10565,
     /*  658219 */     GIR_EraseRootFromParent_Done,
     /*  658220 */   // Label 10301: @658220
     /*  658220 */   GIM_Try, /*On fail goto*//*Label 10302*/ GIMT_Encode4(658279), // Rule ID 11117 //
     /*  658225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  658228 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658235 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658248 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658256 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658277 */     GIR_RootConstrainSelectedInstOperands,
     /*  658278 */     // GIR_Coverage, 11117,
     /*  658278 */     GIR_EraseRootFromParent_Done,
     /*  658279 */   // Label 10302: @658279
     /*  658279 */   GIM_Try, /*On fail goto*//*Label 10303*/ GIMT_Encode4(658338), // Rule ID 11118 //
     /*  658284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  658287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658294 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658307 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658315 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658336 */     GIR_RootConstrainSelectedInstOperands,
     /*  658337 */     // GIR_Coverage, 11118,
     /*  658337 */     GIR_EraseRootFromParent_Done,
     /*  658338 */   // Label 10303: @658338
     /*  658338 */   GIM_Try, /*On fail goto*//*Label 10304*/ GIMT_Encode4(658397), // Rule ID 11119 //
     /*  658343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  658346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658353 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658366 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658374 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658395 */     GIR_RootConstrainSelectedInstOperands,
     /*  658396 */     // GIR_Coverage, 11119,
     /*  658396 */     GIR_EraseRootFromParent_Done,
     /*  658397 */   // Label 10304: @658397
     /*  658397 */   GIM_Try, /*On fail goto*//*Label 10305*/ GIMT_Encode4(658456), // Rule ID 11120 //
     /*  658402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  658405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658412 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658418 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658425 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658433 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658454 */     GIR_RootConstrainSelectedInstOperands,
     /*  658455 */     // GIR_Coverage, 11120,
     /*  658455 */     GIR_EraseRootFromParent_Done,
     /*  658456 */   // Label 10305: @658456
     /*  658456 */   GIM_Try, /*On fail goto*//*Label 10306*/ GIMT_Encode4(658515), // Rule ID 11121 //
     /*  658461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  658464 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658471 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  658484 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR),
     /*  658487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658492 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658513 */     GIR_RootConstrainSelectedInstOperands,
     /*  658514 */     // GIR_Coverage, 11121,
     /*  658514 */     GIR_EraseRootFromParent_Done,
     /*  658515 */   // Label 10306: @658515
     /*  658515 */   GIM_Try, /*On fail goto*//*Label 10307*/ GIMT_Encode4(658579), // Rule ID 10555 //
     /*  658520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  658523 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  658535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  658546 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR_RTN),
     /*  658549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  658551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658556 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658573 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658577 */     GIR_RootConstrainSelectedInstOperands,
     /*  658578 */     // GIR_Coverage, 10555,
     /*  658578 */     GIR_EraseRootFromParent_Done,
     /*  658579 */   // Label 10307: @658579
     /*  658579 */   GIM_Try, /*On fail goto*//*Label 10308*/ GIMT_Encode4(658642), // Rule ID 11111 //
     /*  658584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  658587 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  658598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  658609 */     // (atomic_load_max:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (FLAT_ATOMIC_SMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  658609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_SADDR_RTN),
     /*  658612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  658614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  658619 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  658626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  658631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  658636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658640 */     GIR_RootConstrainSelectedInstOperands,
     /*  658641 */     // GIR_Coverage, 11111,
     /*  658641 */     GIR_EraseRootFromParent_Done,
     /*  658642 */   // Label 10308: @658642
     /*  658642 */   GIM_Try, /*On fail goto*//*Label 10309*/ GIMT_Encode4(658695), // Rule ID 10556 //
     /*  658647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  658650 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658658 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658671 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658679 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  658686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  658689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658693 */     GIR_RootConstrainSelectedInstOperands,
     /*  658694 */     // GIR_Coverage, 10556,
     /*  658694 */     GIR_EraseRootFromParent_Done,
     /*  658695 */   // Label 10309: @658695
     /*  658695 */   GIM_Try, /*On fail goto*//*Label 10310*/ GIMT_Encode4(658748), // Rule ID 10557 //
     /*  658700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  658703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658711 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658724 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658732 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  658739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  658742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658746 */     GIR_RootConstrainSelectedInstOperands,
     /*  658747 */     // GIR_Coverage, 10557,
     /*  658747 */     GIR_EraseRootFromParent_Done,
     /*  658748 */   // Label 10310: @658748
     /*  658748 */   GIM_Try, /*On fail goto*//*Label 10311*/ GIMT_Encode4(658801), // Rule ID 10558 //
     /*  658753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  658756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658764 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658777 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658785 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  658792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  658795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658799 */     GIR_RootConstrainSelectedInstOperands,
     /*  658800 */     // GIR_Coverage, 10558,
     /*  658800 */     GIR_EraseRootFromParent_Done,
     /*  658801 */   // Label 10311: @658801
     /*  658801 */   GIM_Try, /*On fail goto*//*Label 10312*/ GIMT_Encode4(658854), // Rule ID 10559 //
     /*  658806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  658809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658817 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658830 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658838 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  658845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  658848 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658852 */     GIR_RootConstrainSelectedInstOperands,
     /*  658853 */     // GIR_Coverage, 10559,
     /*  658853 */     GIR_EraseRootFromParent_Done,
     /*  658854 */   // Label 10312: @658854
     /*  658854 */   GIM_Try, /*On fail goto*//*Label 10313*/ GIMT_Encode4(658907), // Rule ID 10560 //
     /*  658859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  658862 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658870 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658883 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658891 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  658898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  658901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658905 */     GIR_RootConstrainSelectedInstOperands,
     /*  658906 */     // GIR_Coverage, 10560,
     /*  658906 */     GIR_EraseRootFromParent_Done,
     /*  658907 */   // Label 10313: @658907
     /*  658907 */   GIM_Try, /*On fail goto*//*Label 10314*/ GIMT_Encode4(658959), // Rule ID 11112 //
     /*  658912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  658915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658922 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658935 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658943 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  658950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  658953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  658957 */     GIR_RootConstrainSelectedInstOperands,
     /*  658958 */     // GIR_Coverage, 11112,
     /*  658958 */     GIR_EraseRootFromParent_Done,
     /*  658959 */   // Label 10314: @658959
     /*  658959 */   GIM_Try, /*On fail goto*//*Label 10315*/ GIMT_Encode4(659011), // Rule ID 11113 //
     /*  658964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  658967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  658974 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  658976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  658980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  658987 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  658987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  658990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  658995 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  658997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659009 */     GIR_RootConstrainSelectedInstOperands,
     /*  659010 */     // GIR_Coverage, 11113,
     /*  659010 */     GIR_EraseRootFromParent_Done,
     /*  659011 */   // Label 10315: @659011
     /*  659011 */   GIM_Try, /*On fail goto*//*Label 10316*/ GIMT_Encode4(659063), // Rule ID 11114 //
     /*  659016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  659019 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659026 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659028 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659032 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659039 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  659042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659047 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659061 */     GIR_RootConstrainSelectedInstOperands,
     /*  659062 */     // GIR_Coverage, 11114,
     /*  659062 */     GIR_EraseRootFromParent_Done,
     /*  659063 */   // Label 10316: @659063
     /*  659063 */   GIM_Try, /*On fail goto*//*Label 10317*/ GIMT_Encode4(659115), // Rule ID 11115 //
     /*  659068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  659071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659078 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659091 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  659094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659099 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659113 */     GIR_RootConstrainSelectedInstOperands,
     /*  659114 */     // GIR_Coverage, 11115,
     /*  659114 */     GIR_EraseRootFromParent_Done,
     /*  659115 */   // Label 10317: @659115
     /*  659115 */   GIM_Try, /*On fail goto*//*Label 10318*/ GIMT_Encode4(659167), // Rule ID 11116 //
     /*  659120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  659123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659130 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659143 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>>  =>  (FLAT_ATOMIC_SMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
     /*  659146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659151 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659165 */     GIR_RootConstrainSelectedInstOperands,
     /*  659166 */     // GIR_Coverage, 11116,
     /*  659166 */     GIR_EraseRootFromParent_Done,
     /*  659167 */   // Label 10318: @659167
     /*  659167 */   GIM_Try, /*On fail goto*//*Label 10319*/ GIMT_Encode4(659224), // Rule ID 10550 //
     /*  659172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  659175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659198 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659208 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659222 */     GIR_RootConstrainSelectedInstOperands,
     /*  659223 */     // GIR_Coverage, 10550,
     /*  659223 */     GIR_EraseRootFromParent_Done,
     /*  659224 */   // Label 10319: @659224
     /*  659224 */   GIM_Try, /*On fail goto*//*Label 10320*/ GIMT_Encode4(659281), // Rule ID 10551 //
     /*  659229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  659232 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659255 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659265 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659279 */     GIR_RootConstrainSelectedInstOperands,
     /*  659280 */     // GIR_Coverage, 10551,
     /*  659280 */     GIR_EraseRootFromParent_Done,
     /*  659281 */   // Label 10320: @659281
     /*  659281 */   GIM_Try, /*On fail goto*//*Label 10321*/ GIMT_Encode4(659338), // Rule ID 10552 //
     /*  659286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  659289 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659312 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659322 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659336 */     GIR_RootConstrainSelectedInstOperands,
     /*  659337 */     // GIR_Coverage, 10552,
     /*  659337 */     GIR_EraseRootFromParent_Done,
     /*  659338 */   // Label 10321: @659338
     /*  659338 */   GIM_Try, /*On fail goto*//*Label 10322*/ GIMT_Encode4(659395), // Rule ID 10553 //
     /*  659343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  659346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659369 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659379 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659389 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659393 */     GIR_RootConstrainSelectedInstOperands,
     /*  659394 */     // GIR_Coverage, 10553,
     /*  659394 */     GIR_EraseRootFromParent_Done,
     /*  659395 */   // Label 10322: @659395
     /*  659395 */   GIM_Try, /*On fail goto*//*Label 10323*/ GIMT_Encode4(659452), // Rule ID 10554 //
     /*  659400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  659403 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659426 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659436 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659450 */     GIR_RootConstrainSelectedInstOperands,
     /*  659451 */     // GIR_Coverage, 10554,
     /*  659451 */     GIR_EraseRootFromParent_Done,
     /*  659452 */   // Label 10323: @659452
     /*  659452 */   GIM_Try, /*On fail goto*//*Label 10324*/ GIMT_Encode4(659508), // Rule ID 11106 //
     /*  659457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  659460 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659482 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659492 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659506 */     GIR_RootConstrainSelectedInstOperands,
     /*  659507 */     // GIR_Coverage, 11106,
     /*  659507 */     GIR_EraseRootFromParent_Done,
     /*  659508 */   // Label 10324: @659508
     /*  659508 */   GIM_Try, /*On fail goto*//*Label 10325*/ GIMT_Encode4(659564), // Rule ID 11107 //
     /*  659513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  659516 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659538 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659548 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659562 */     GIR_RootConstrainSelectedInstOperands,
     /*  659563 */     // GIR_Coverage, 11107,
     /*  659563 */     GIR_EraseRootFromParent_Done,
     /*  659564 */   // Label 10325: @659564
     /*  659564 */   GIM_Try, /*On fail goto*//*Label 10326*/ GIMT_Encode4(659620), // Rule ID 11108 //
     /*  659569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  659572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659594 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659604 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659618 */     GIR_RootConstrainSelectedInstOperands,
     /*  659619 */     // GIR_Coverage, 11108,
     /*  659619 */     GIR_EraseRootFromParent_Done,
     /*  659620 */   // Label 10326: @659620
     /*  659620 */   GIM_Try, /*On fail goto*//*Label 10327*/ GIMT_Encode4(659676), // Rule ID 11109 //
     /*  659625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  659628 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659650 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659660 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659674 */     GIR_RootConstrainSelectedInstOperands,
     /*  659675 */     // GIR_Coverage, 11109,
     /*  659675 */     GIR_EraseRootFromParent_Done,
     /*  659676 */   // Label 10327: @659676
     /*  659676 */   GIM_Try, /*On fail goto*//*Label 10328*/ GIMT_Encode4(659732), // Rule ID 11110 //
     /*  659681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  659684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  659695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  659706 */     // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  659706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
     /*  659709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  659711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  659716 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  659718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  659723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  659726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659730 */     GIR_RootConstrainSelectedInstOperands,
     /*  659731 */     // GIR_Coverage, 11110,
     /*  659731 */     GIR_EraseRootFromParent_Done,
     /*  659732 */   // Label 10328: @659732
     /*  659732 */   GIM_Reject,
     /*  659733 */ // Label 10222: @659733
     /*  659733 */ GIM_Reject,
     /*  659734 */ // Label 10220: @659734
     /*  659734 */ GIM_Try, /*On fail goto*//*Label 10329*/ GIMT_Encode4(667233),
     /*  659739 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  659742 */   GIM_Try, /*On fail goto*//*Label 10330*/ GIMT_Encode4(659804), // Rule ID 21418 //
     /*  659747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  659750 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659757 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  659770 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  659770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64),
     /*  659773 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  659775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  659780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  659785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  659790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  659795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659802 */     GIR_RootConstrainSelectedInstOperands,
     /*  659803 */     // GIR_Coverage, 21418,
     /*  659803 */     GIR_EraseRootFromParent_Done,
     /*  659804 */   // Label 10330: @659804
     /*  659804 */   GIM_Try, /*On fail goto*//*Label 10331*/ GIMT_Encode4(659866), // Rule ID 21419 //
     /*  659809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  659812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659819 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  659832 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  659832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64),
     /*  659835 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  659837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  659842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  659847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  659852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  659857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659864 */     GIR_RootConstrainSelectedInstOperands,
     /*  659865 */     // GIR_Coverage, 21419,
     /*  659865 */     GIR_EraseRootFromParent_Done,
     /*  659866 */   // Label 10331: @659866
     /*  659866 */   GIM_Try, /*On fail goto*//*Label 10332*/ GIMT_Encode4(659928), // Rule ID 21420 //
     /*  659871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  659874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659881 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  659894 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  659894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64),
     /*  659897 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  659899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  659904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  659909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  659914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  659919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659926 */     GIR_RootConstrainSelectedInstOperands,
     /*  659927 */     // GIR_Coverage, 21420,
     /*  659927 */     GIR_EraseRootFromParent_Done,
     /*  659928 */   // Label 10332: @659928
     /*  659928 */   GIM_Try, /*On fail goto*//*Label 10333*/ GIMT_Encode4(659990), // Rule ID 21421 //
     /*  659933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  659936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  659943 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  659945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  659949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  659956 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  659956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64),
     /*  659959 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  659961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  659966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  659971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  659976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  659981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  659984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  659988 */     GIR_RootConstrainSelectedInstOperands,
     /*  659989 */     // GIR_Coverage, 21421,
     /*  659989 */     GIR_EraseRootFromParent_Done,
     /*  659990 */   // Label 10333: @659990
     /*  659990 */   GIM_Try, /*On fail goto*//*Label 10334*/ GIMT_Encode4(660052), // Rule ID 21422 //
     /*  659995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  659998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660005 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  660007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660018 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64),
     /*  660021 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  660046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660050 */     GIR_RootConstrainSelectedInstOperands,
     /*  660051 */     // GIR_Coverage, 21422,
     /*  660051 */     GIR_EraseRootFromParent_Done,
     /*  660052 */   // Label 10334: @660052
     /*  660052 */   GIM_Try, /*On fail goto*//*Label 10335*/ GIMT_Encode4(660114), // Rule ID 21438 //
     /*  660057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  660060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660067 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  660069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660080 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64),
     /*  660083 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  660108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660112 */     GIR_RootConstrainSelectedInstOperands,
     /*  660113 */     // GIR_Coverage, 21438,
     /*  660113 */     GIR_EraseRootFromParent_Done,
     /*  660114 */   // Label 10335: @660114
     /*  660114 */   GIM_Try, /*On fail goto*//*Label 10336*/ GIMT_Encode4(660176), // Rule ID 21439 //
     /*  660119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  660122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660129 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  660131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660142 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64),
     /*  660145 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  660170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660174 */     GIR_RootConstrainSelectedInstOperands,
     /*  660175 */     // GIR_Coverage, 21439,
     /*  660175 */     GIR_EraseRootFromParent_Done,
     /*  660176 */   // Label 10336: @660176
     /*  660176 */   GIM_Try, /*On fail goto*//*Label 10337*/ GIMT_Encode4(660238), // Rule ID 21440 //
     /*  660181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  660184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660191 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  660193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660204 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64),
     /*  660207 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  660232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660236 */     GIR_RootConstrainSelectedInstOperands,
     /*  660237 */     // GIR_Coverage, 21440,
     /*  660237 */     GIR_EraseRootFromParent_Done,
     /*  660238 */   // Label 10337: @660238
     /*  660238 */   GIM_Try, /*On fail goto*//*Label 10338*/ GIMT_Encode4(660300), // Rule ID 21441 //
     /*  660243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  660246 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660253 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  660255 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660259 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660266 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64),
     /*  660269 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  660294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660298 */     GIR_RootConstrainSelectedInstOperands,
     /*  660299 */     // GIR_Coverage, 21441,
     /*  660299 */     GIR_EraseRootFromParent_Done,
     /*  660300 */   // Label 10338: @660300
     /*  660300 */   GIM_Try, /*On fail goto*//*Label 10339*/ GIMT_Encode4(660362), // Rule ID 21442 //
     /*  660305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  660308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660315 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  660317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660328 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64),
     /*  660331 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  660356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660360 */     GIR_RootConstrainSelectedInstOperands,
     /*  660361 */     // GIR_Coverage, 21442,
     /*  660361 */     GIR_EraseRootFromParent_Done,
     /*  660362 */   // Label 10339: @660362
     /*  660362 */   GIM_Try, /*On fail goto*//*Label 10340*/ GIMT_Encode4(660428), // Rule ID 21408 //
     /*  660367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  660370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660392 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN),
     /*  660395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660397 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660426 */     GIR_RootConstrainSelectedInstOperands,
     /*  660427 */     // GIR_Coverage, 21408,
     /*  660427 */     GIR_EraseRootFromParent_Done,
     /*  660428 */   // Label 10340: @660428
     /*  660428 */   GIM_Try, /*On fail goto*//*Label 10341*/ GIMT_Encode4(660494), // Rule ID 21409 //
     /*  660433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  660436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660447 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660451 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660458 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN),
     /*  660461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660463 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660492 */     GIR_RootConstrainSelectedInstOperands,
     /*  660493 */     // GIR_Coverage, 21409,
     /*  660493 */     GIR_EraseRootFromParent_Done,
     /*  660494 */   // Label 10341: @660494
     /*  660494 */   GIM_Try, /*On fail goto*//*Label 10342*/ GIMT_Encode4(660560), // Rule ID 21410 //
     /*  660499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  660502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660524 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN),
     /*  660527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660529 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660558 */     GIR_RootConstrainSelectedInstOperands,
     /*  660559 */     // GIR_Coverage, 21410,
     /*  660559 */     GIR_EraseRootFromParent_Done,
     /*  660560 */   // Label 10342: @660560
     /*  660560 */   GIM_Try, /*On fail goto*//*Label 10343*/ GIMT_Encode4(660626), // Rule ID 21411 //
     /*  660565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  660568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660590 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN),
     /*  660593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660595 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660624 */     GIR_RootConstrainSelectedInstOperands,
     /*  660625 */     // GIR_Coverage, 21411,
     /*  660625 */     GIR_EraseRootFromParent_Done,
     /*  660626 */   // Label 10343: @660626
     /*  660626 */   GIM_Try, /*On fail goto*//*Label 10344*/ GIMT_Encode4(660692), // Rule ID 21412 //
     /*  660631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  660634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660656 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN),
     /*  660659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660661 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660690 */     GIR_RootConstrainSelectedInstOperands,
     /*  660691 */     // GIR_Coverage, 21412,
     /*  660691 */     GIR_EraseRootFromParent_Done,
     /*  660692 */   // Label 10344: @660692
     /*  660692 */   GIM_Try, /*On fail goto*//*Label 10345*/ GIMT_Encode4(660758), // Rule ID 21428 //
     /*  660697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  660700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660722 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN),
     /*  660725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660727 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660756 */     GIR_RootConstrainSelectedInstOperands,
     /*  660757 */     // GIR_Coverage, 21428,
     /*  660757 */     GIR_EraseRootFromParent_Done,
     /*  660758 */   // Label 10345: @660758
     /*  660758 */   GIM_Try, /*On fail goto*//*Label 10346*/ GIMT_Encode4(660824), // Rule ID 21429 //
     /*  660763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  660766 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660788 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN),
     /*  660791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660793 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660822 */     GIR_RootConstrainSelectedInstOperands,
     /*  660823 */     // GIR_Coverage, 21429,
     /*  660823 */     GIR_EraseRootFromParent_Done,
     /*  660824 */   // Label 10346: @660824
     /*  660824 */   GIM_Try, /*On fail goto*//*Label 10347*/ GIMT_Encode4(660890), // Rule ID 21430 //
     /*  660829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  660832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660854 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN),
     /*  660857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660859 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660888 */     GIR_RootConstrainSelectedInstOperands,
     /*  660889 */     // GIR_Coverage, 21430,
     /*  660889 */     GIR_EraseRootFromParent_Done,
     /*  660890 */   // Label 10347: @660890
     /*  660890 */   GIM_Try, /*On fail goto*//*Label 10348*/ GIMT_Encode4(660956), // Rule ID 21431 //
     /*  660895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  660898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660909 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660920 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN),
     /*  660923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660925 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  660937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  660942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  660947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  660950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  660954 */     GIR_RootConstrainSelectedInstOperands,
     /*  660955 */     // GIR_Coverage, 21431,
     /*  660955 */     GIR_EraseRootFromParent_Done,
     /*  660956 */   // Label 10348: @660956
     /*  660956 */   GIM_Try, /*On fail goto*//*Label 10349*/ GIMT_Encode4(661022), // Rule ID 21432 //
     /*  660961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  660964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  660971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  660975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  660979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  660986 */     // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  660986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN),
     /*  660989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  660991 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  660993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  660998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  661008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  661013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661020 */     GIR_RootConstrainSelectedInstOperands,
     /*  661021 */     // GIR_Coverage, 21432,
     /*  661021 */     GIR_EraseRootFromParent_Done,
     /*  661022 */   // Label 10349: @661022
     /*  661022 */   GIM_Try, /*On fail goto*//*Label 10350*/ GIMT_Encode4(661079), // Rule ID 21413 //
     /*  661027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  661030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661037 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661050 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
     /*  661053 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661073 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661077 */     GIR_RootConstrainSelectedInstOperands,
     /*  661078 */     // GIR_Coverage, 21413,
     /*  661078 */     GIR_EraseRootFromParent_Done,
     /*  661079 */   // Label 10350: @661079
     /*  661079 */   GIM_Try, /*On fail goto*//*Label 10351*/ GIMT_Encode4(661136), // Rule ID 21414 //
     /*  661084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  661087 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661094 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661096 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661100 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661107 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
     /*  661110 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661134 */     GIR_RootConstrainSelectedInstOperands,
     /*  661135 */     // GIR_Coverage, 21414,
     /*  661135 */     GIR_EraseRootFromParent_Done,
     /*  661136 */   // Label 10351: @661136
     /*  661136 */   GIM_Try, /*On fail goto*//*Label 10352*/ GIMT_Encode4(661193), // Rule ID 21415 //
     /*  661141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  661144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661151 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661164 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
     /*  661167 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661191 */     GIR_RootConstrainSelectedInstOperands,
     /*  661192 */     // GIR_Coverage, 21415,
     /*  661192 */     GIR_EraseRootFromParent_Done,
     /*  661193 */   // Label 10352: @661193
     /*  661193 */   GIM_Try, /*On fail goto*//*Label 10353*/ GIMT_Encode4(661250), // Rule ID 21416 //
     /*  661198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  661201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661208 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661221 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
     /*  661224 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661248 */     GIR_RootConstrainSelectedInstOperands,
     /*  661249 */     // GIR_Coverage, 21416,
     /*  661249 */     GIR_EraseRootFromParent_Done,
     /*  661250 */   // Label 10353: @661250
     /*  661250 */   GIM_Try, /*On fail goto*//*Label 10354*/ GIMT_Encode4(661307), // Rule ID 21417 //
     /*  661255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  661258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661265 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661278 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
     /*  661281 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661305 */     GIR_RootConstrainSelectedInstOperands,
     /*  661306 */     // GIR_Coverage, 21417,
     /*  661306 */     GIR_EraseRootFromParent_Done,
     /*  661307 */   // Label 10354: @661307
     /*  661307 */   GIM_Try, /*On fail goto*//*Label 10355*/ GIMT_Encode4(661364), // Rule ID 21433 //
     /*  661312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  661315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661322 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661335 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
     /*  661338 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661362 */     GIR_RootConstrainSelectedInstOperands,
     /*  661363 */     // GIR_Coverage, 21433,
     /*  661363 */     GIR_EraseRootFromParent_Done,
     /*  661364 */   // Label 10355: @661364
     /*  661364 */   GIM_Try, /*On fail goto*//*Label 10356*/ GIMT_Encode4(661421), // Rule ID 21434 //
     /*  661369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  661372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661392 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
     /*  661395 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661419 */     GIR_RootConstrainSelectedInstOperands,
     /*  661420 */     // GIR_Coverage, 21434,
     /*  661420 */     GIR_EraseRootFromParent_Done,
     /*  661421 */   // Label 10356: @661421
     /*  661421 */   GIM_Try, /*On fail goto*//*Label 10357*/ GIMT_Encode4(661478), // Rule ID 21435 //
     /*  661426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  661429 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661436 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661449 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
     /*  661452 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661476 */     GIR_RootConstrainSelectedInstOperands,
     /*  661477 */     // GIR_Coverage, 21435,
     /*  661477 */     GIR_EraseRootFromParent_Done,
     /*  661478 */   // Label 10357: @661478
     /*  661478 */   GIM_Try, /*On fail goto*//*Label 10358*/ GIMT_Encode4(661535), // Rule ID 21436 //
     /*  661483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  661486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661493 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661506 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
     /*  661509 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661529 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661533 */     GIR_RootConstrainSelectedInstOperands,
     /*  661534 */     // GIR_Coverage, 21436,
     /*  661534 */     GIR_EraseRootFromParent_Done,
     /*  661535 */   // Label 10358: @661535
     /*  661535 */   GIM_Try, /*On fail goto*//*Label 10359*/ GIMT_Encode4(661592), // Rule ID 21437 //
     /*  661540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  661543 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661550 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  661552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661563 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
     /*  661566 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  661586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661590 */     GIR_RootConstrainSelectedInstOperands,
     /*  661591 */     // GIR_Coverage, 21437,
     /*  661591 */     GIR_EraseRootFromParent_Done,
     /*  661592 */   // Label 10359: @661592
     /*  661592 */   GIM_Try, /*On fail goto*//*Label 10360*/ GIMT_Encode4(661653), // Rule ID 21403 //
     /*  661597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  661600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661622 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
     /*  661625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661627 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661651 */     GIR_RootConstrainSelectedInstOperands,
     /*  661652 */     // GIR_Coverage, 21403,
     /*  661652 */     GIR_EraseRootFromParent_Done,
     /*  661653 */   // Label 10360: @661653
     /*  661653 */   GIM_Try, /*On fail goto*//*Label 10361*/ GIMT_Encode4(661714), // Rule ID 21404 //
     /*  661658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  661661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661683 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
     /*  661686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661688 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661708 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661712 */     GIR_RootConstrainSelectedInstOperands,
     /*  661713 */     // GIR_Coverage, 21404,
     /*  661713 */     GIR_EraseRootFromParent_Done,
     /*  661714 */   // Label 10361: @661714
     /*  661714 */   GIM_Try, /*On fail goto*//*Label 10362*/ GIMT_Encode4(661775), // Rule ID 21405 //
     /*  661719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  661722 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661744 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
     /*  661747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661749 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661766 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661773 */     GIR_RootConstrainSelectedInstOperands,
     /*  661774 */     // GIR_Coverage, 21405,
     /*  661774 */     GIR_EraseRootFromParent_Done,
     /*  661775 */   // Label 10362: @661775
     /*  661775 */   GIM_Try, /*On fail goto*//*Label 10363*/ GIMT_Encode4(661836), // Rule ID 21406 //
     /*  661780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  661783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661794 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661798 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661805 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
     /*  661808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661810 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661834 */     GIR_RootConstrainSelectedInstOperands,
     /*  661835 */     // GIR_Coverage, 21406,
     /*  661835 */     GIR_EraseRootFromParent_Done,
     /*  661836 */   // Label 10363: @661836
     /*  661836 */   GIM_Try, /*On fail goto*//*Label 10364*/ GIMT_Encode4(661897), // Rule ID 21407 //
     /*  661841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  661844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661866 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
     /*  661869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661871 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661895 */     GIR_RootConstrainSelectedInstOperands,
     /*  661896 */     // GIR_Coverage, 21407,
     /*  661896 */     GIR_EraseRootFromParent_Done,
     /*  661897 */   // Label 10364: @661897
     /*  661897 */   GIM_Try, /*On fail goto*//*Label 10365*/ GIMT_Encode4(661958), // Rule ID 21423 //
     /*  661902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  661905 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661927 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
     /*  661930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661932 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  661939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  661944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  661949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  661952 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  661956 */     GIR_RootConstrainSelectedInstOperands,
     /*  661957 */     // GIR_Coverage, 21423,
     /*  661957 */     GIR_EraseRootFromParent_Done,
     /*  661958 */   // Label 10365: @661958
     /*  661958 */   GIM_Try, /*On fail goto*//*Label 10366*/ GIMT_Encode4(662019), // Rule ID 21424 //
     /*  661963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  661966 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  661973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  661977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  661981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  661988 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  661988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
     /*  661991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  661993 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  661995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  662000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  662005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  662010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662017 */     GIR_RootConstrainSelectedInstOperands,
     /*  662018 */     // GIR_Coverage, 21424,
     /*  662018 */     GIR_EraseRootFromParent_Done,
     /*  662019 */   // Label 10366: @662019
     /*  662019 */   GIM_Try, /*On fail goto*//*Label 10367*/ GIMT_Encode4(662080), // Rule ID 21425 //
     /*  662024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  662027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  662034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  662038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  662049 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  662049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
     /*  662052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  662054 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  662056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  662061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  662066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  662071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662078 */     GIR_RootConstrainSelectedInstOperands,
     /*  662079 */     // GIR_Coverage, 21425,
     /*  662079 */     GIR_EraseRootFromParent_Done,
     /*  662080 */   // Label 10367: @662080
     /*  662080 */   GIM_Try, /*On fail goto*//*Label 10368*/ GIMT_Encode4(662141), // Rule ID 21426 //
     /*  662085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  662088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  662095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  662099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  662110 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  662110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
     /*  662113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  662115 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  662117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  662122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  662127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  662132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662139 */     GIR_RootConstrainSelectedInstOperands,
     /*  662140 */     // GIR_Coverage, 21426,
     /*  662140 */     GIR_EraseRootFromParent_Done,
     /*  662141 */   // Label 10368: @662141
     /*  662141 */   GIM_Try, /*On fail goto*//*Label 10369*/ GIMT_Encode4(662202), // Rule ID 21427 //
     /*  662146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  662149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  662156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  662160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  662171 */     // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  662171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
     /*  662174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  662176 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  662178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  662183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  662188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  662193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662196 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662200 */     GIR_RootConstrainSelectedInstOperands,
     /*  662201 */     // GIR_Coverage, 21427,
     /*  662201 */     GIR_EraseRootFromParent_Done,
     /*  662202 */   // Label 10369: @662202
     /*  662202 */   GIM_Try, /*On fail goto*//*Label 10370*/ GIMT_Encode4(662252), // Rule ID 30805 //
     /*  662207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  662210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662215 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662228 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662236 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662250 */     GIR_RootConstrainSelectedInstOperands,
     /*  662251 */     // GIR_Coverage, 30805,
     /*  662251 */     GIR_EraseRootFromParent_Done,
     /*  662252 */   // Label 10370: @662252
     /*  662252 */   GIM_Try, /*On fail goto*//*Label 10371*/ GIMT_Encode4(662302), // Rule ID 30806 //
     /*  662257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  662260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662265 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662278 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662286 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662300 */     GIR_RootConstrainSelectedInstOperands,
     /*  662301 */     // GIR_Coverage, 30806,
     /*  662301 */     GIR_EraseRootFromParent_Done,
     /*  662302 */   // Label 10371: @662302
     /*  662302 */   GIM_Try, /*On fail goto*//*Label 10372*/ GIMT_Encode4(662352), // Rule ID 30807 //
     /*  662307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  662310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662315 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662328 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662336 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662350 */     GIR_RootConstrainSelectedInstOperands,
     /*  662351 */     // GIR_Coverage, 30807,
     /*  662351 */     GIR_EraseRootFromParent_Done,
     /*  662352 */   // Label 10372: @662352
     /*  662352 */   GIM_Try, /*On fail goto*//*Label 10373*/ GIMT_Encode4(662402), // Rule ID 30808 //
     /*  662357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  662360 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662365 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662371 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662378 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662386 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662400 */     GIR_RootConstrainSelectedInstOperands,
     /*  662401 */     // GIR_Coverage, 30808,
     /*  662401 */     GIR_EraseRootFromParent_Done,
     /*  662402 */   // Label 10373: @662402
     /*  662402 */   GIM_Try, /*On fail goto*//*Label 10374*/ GIMT_Encode4(662452), // Rule ID 30809 //
     /*  662407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  662410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662415 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662428 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662436 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662450 */     GIR_RootConstrainSelectedInstOperands,
     /*  662451 */     // GIR_Coverage, 30809,
     /*  662451 */     GIR_EraseRootFromParent_Done,
     /*  662452 */   // Label 10374: @662452
     /*  662452 */   GIM_Try, /*On fail goto*//*Label 10375*/ GIMT_Encode4(662502), // Rule ID 30815 //
     /*  662457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  662460 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662465 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662478 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_i64>>  =>  (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9),
     /*  662481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662486 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662500 */     GIR_RootConstrainSelectedInstOperands,
     /*  662501 */     // GIR_Coverage, 30815,
     /*  662501 */     GIR_EraseRootFromParent_Done,
     /*  662502 */   // Label 10375: @662502
     /*  662502 */   GIM_Try, /*On fail goto*//*Label 10376*/ GIMT_Encode4(662552), // Rule ID 30816 //
     /*  662507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  662510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662515 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662528 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_i64>>  =>  (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9),
     /*  662531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662536 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662550 */     GIR_RootConstrainSelectedInstOperands,
     /*  662551 */     // GIR_Coverage, 30816,
     /*  662551 */     GIR_EraseRootFromParent_Done,
     /*  662552 */   // Label 10376: @662552
     /*  662552 */   GIM_Try, /*On fail goto*//*Label 10377*/ GIMT_Encode4(662602), // Rule ID 30817 //
     /*  662557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  662560 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662565 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662578 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_i64>>  =>  (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9),
     /*  662581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662586 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662600 */     GIR_RootConstrainSelectedInstOperands,
     /*  662601 */     // GIR_Coverage, 30817,
     /*  662601 */     GIR_EraseRootFromParent_Done,
     /*  662602 */   // Label 10377: @662602
     /*  662602 */   GIM_Try, /*On fail goto*//*Label 10378*/ GIMT_Encode4(662652), // Rule ID 30818 //
     /*  662607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  662610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662615 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662628 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_i64>>  =>  (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9),
     /*  662631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662636 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662650 */     GIR_RootConstrainSelectedInstOperands,
     /*  662651 */     // GIR_Coverage, 30818,
     /*  662651 */     GIR_EraseRootFromParent_Done,
     /*  662652 */   // Label 10378: @662652
     /*  662652 */   GIM_Try, /*On fail goto*//*Label 10379*/ GIMT_Encode4(662702), // Rule ID 30819 //
     /*  662657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  662660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662665 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662678 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_i64>>  =>  (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9),
     /*  662681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662686 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  662696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662700 */     GIR_RootConstrainSelectedInstOperands,
     /*  662701 */     // GIR_Coverage, 30819,
     /*  662701 */     GIR_EraseRootFromParent_Done,
     /*  662702 */   // Label 10379: @662702
     /*  662702 */   GIM_Try, /*On fail goto*//*Label 10380*/ GIMT_Encode4(662752), // Rule ID 30825 //
     /*  662707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  662710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  662715 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662728 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  662728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662736 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662750 */     GIR_RootConstrainSelectedInstOperands,
     /*  662751 */     // GIR_Coverage, 30825,
     /*  662751 */     GIR_EraseRootFromParent_Done,
     /*  662752 */   // Label 10380: @662752
     /*  662752 */   GIM_Try, /*On fail goto*//*Label 10381*/ GIMT_Encode4(662802), // Rule ID 30826 //
     /*  662757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  662760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  662765 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662778 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  662778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662786 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662800 */     GIR_RootConstrainSelectedInstOperands,
     /*  662801 */     // GIR_Coverage, 30826,
     /*  662801 */     GIR_EraseRootFromParent_Done,
     /*  662802 */   // Label 10381: @662802
     /*  662802 */   GIM_Try, /*On fail goto*//*Label 10382*/ GIMT_Encode4(662852), // Rule ID 30827 //
     /*  662807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  662810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  662815 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662828 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  662828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662836 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662850 */     GIR_RootConstrainSelectedInstOperands,
     /*  662851 */     // GIR_Coverage, 30827,
     /*  662851 */     GIR_EraseRootFromParent_Done,
     /*  662852 */   // Label 10382: @662852
     /*  662852 */   GIM_Try, /*On fail goto*//*Label 10383*/ GIMT_Encode4(662902), // Rule ID 30828 //
     /*  662857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  662860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  662865 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662878 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  662878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662886 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662900 */     GIR_RootConstrainSelectedInstOperands,
     /*  662901 */     // GIR_Coverage, 30828,
     /*  662901 */     GIR_EraseRootFromParent_Done,
     /*  662902 */   // Label 10383: @662902
     /*  662902 */   GIM_Try, /*On fail goto*//*Label 10384*/ GIMT_Encode4(662952), // Rule ID 30829 //
     /*  662907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  662910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  662915 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  662917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662928 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  662928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
     /*  662931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662936 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  662946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  662950 */     GIR_RootConstrainSelectedInstOperands,
     /*  662951 */     // GIR_Coverage, 30829,
     /*  662951 */     GIR_EraseRootFromParent_Done,
     /*  662952 */   // Label 10384: @662952
     /*  662952 */   GIM_Try, /*On fail goto*//*Label 10385*/ GIMT_Encode4(663006), // Rule ID 30800 //
     /*  662957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  662960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  662965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  662969 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  662973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  662980 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  662980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  662983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  662985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  662990 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  662992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  662997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663004 */     GIR_RootConstrainSelectedInstOperands,
     /*  663005 */     // GIR_Coverage, 30800,
     /*  663005 */     GIR_EraseRootFromParent_Done,
     /*  663006 */   // Label 10385: @663006
     /*  663006 */   GIM_Try, /*On fail goto*//*Label 10386*/ GIMT_Encode4(663060), // Rule ID 30801 //
     /*  663011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  663014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663034 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663044 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663058 */     GIR_RootConstrainSelectedInstOperands,
     /*  663059 */     // GIR_Coverage, 30801,
     /*  663059 */     GIR_EraseRootFromParent_Done,
     /*  663060 */   // Label 10386: @663060
     /*  663060 */   GIM_Try, /*On fail goto*//*Label 10387*/ GIMT_Encode4(663114), // Rule ID 30802 //
     /*  663065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  663068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663088 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663098 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663112 */     GIR_RootConstrainSelectedInstOperands,
     /*  663113 */     // GIR_Coverage, 30802,
     /*  663113 */     GIR_EraseRootFromParent_Done,
     /*  663114 */   // Label 10387: @663114
     /*  663114 */   GIM_Try, /*On fail goto*//*Label 10388*/ GIMT_Encode4(663168), // Rule ID 30803 //
     /*  663119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  663122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663142 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663152 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663159 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663162 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663166 */     GIR_RootConstrainSelectedInstOperands,
     /*  663167 */     // GIR_Coverage, 30803,
     /*  663167 */     GIR_EraseRootFromParent_Done,
     /*  663168 */   // Label 10388: @663168
     /*  663168 */   GIM_Try, /*On fail goto*//*Label 10389*/ GIMT_Encode4(663222), // Rule ID 30804 //
     /*  663173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  663176 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663196 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663206 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663220 */     GIR_RootConstrainSelectedInstOperands,
     /*  663221 */     // GIR_Coverage, 30804,
     /*  663221 */     GIR_EraseRootFromParent_Done,
     /*  663222 */   // Label 10389: @663222
     /*  663222 */   GIM_Try, /*On fail goto*//*Label 10390*/ GIMT_Encode4(663276), // Rule ID 30810 //
     /*  663227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  663230 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663239 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663250 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_i64>>  =>  (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9),
     /*  663253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663260 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663274 */     GIR_RootConstrainSelectedInstOperands,
     /*  663275 */     // GIR_Coverage, 30810,
     /*  663275 */     GIR_EraseRootFromParent_Done,
     /*  663276 */   // Label 10390: @663276
     /*  663276 */   GIM_Try, /*On fail goto*//*Label 10391*/ GIMT_Encode4(663330), // Rule ID 30811 //
     /*  663281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  663284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663304 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_i64>>  =>  (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9),
     /*  663307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663314 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663328 */     GIR_RootConstrainSelectedInstOperands,
     /*  663329 */     // GIR_Coverage, 30811,
     /*  663329 */     GIR_EraseRootFromParent_Done,
     /*  663330 */   // Label 10391: @663330
     /*  663330 */   GIM_Try, /*On fail goto*//*Label 10392*/ GIMT_Encode4(663384), // Rule ID 30812 //
     /*  663335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  663338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663358 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_i64>>  =>  (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9),
     /*  663361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663368 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663382 */     GIR_RootConstrainSelectedInstOperands,
     /*  663383 */     // GIR_Coverage, 30812,
     /*  663383 */     GIR_EraseRootFromParent_Done,
     /*  663384 */   // Label 10392: @663384
     /*  663384 */   GIM_Try, /*On fail goto*//*Label 10393*/ GIMT_Encode4(663438), // Rule ID 30813 //
     /*  663389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  663392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663405 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663412 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_i64>>  =>  (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9),
     /*  663415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663422 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663436 */     GIR_RootConstrainSelectedInstOperands,
     /*  663437 */     // GIR_Coverage, 30813,
     /*  663437 */     GIR_EraseRootFromParent_Done,
     /*  663438 */   // Label 10393: @663438
     /*  663438 */   GIM_Try, /*On fail goto*//*Label 10394*/ GIMT_Encode4(663492), // Rule ID 30814 //
     /*  663443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  663446 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  663451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663466 */     // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_i64>>  =>  (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  663466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9),
     /*  663469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663476 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  663486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663490 */     GIR_RootConstrainSelectedInstOperands,
     /*  663491 */     // GIR_Coverage, 30814,
     /*  663491 */     GIR_EraseRootFromParent_Done,
     /*  663492 */   // Label 10394: @663492
     /*  663492 */   GIM_Try, /*On fail goto*//*Label 10395*/ GIMT_Encode4(663546), // Rule ID 30820 //
     /*  663497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  663500 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  663505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663520 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  663520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663530 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  663540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663544 */     GIR_RootConstrainSelectedInstOperands,
     /*  663545 */     // GIR_Coverage, 30820,
     /*  663545 */     GIR_EraseRootFromParent_Done,
     /*  663546 */   // Label 10395: @663546
     /*  663546 */   GIM_Try, /*On fail goto*//*Label 10396*/ GIMT_Encode4(663600), // Rule ID 30821 //
     /*  663551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  663554 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  663559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663574 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  663574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663584 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  663594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663598 */     GIR_RootConstrainSelectedInstOperands,
     /*  663599 */     // GIR_Coverage, 30821,
     /*  663599 */     GIR_EraseRootFromParent_Done,
     /*  663600 */   // Label 10396: @663600
     /*  663600 */   GIM_Try, /*On fail goto*//*Label 10397*/ GIMT_Encode4(663654), // Rule ID 30822 //
     /*  663605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  663608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  663613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663628 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  663628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663638 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  663648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663652 */     GIR_RootConstrainSelectedInstOperands,
     /*  663653 */     // GIR_Coverage, 30822,
     /*  663653 */     GIR_EraseRootFromParent_Done,
     /*  663654 */   // Label 10397: @663654
     /*  663654 */   GIM_Try, /*On fail goto*//*Label 10398*/ GIMT_Encode4(663708), // Rule ID 30823 //
     /*  663659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  663662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  663667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663682 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  663682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663692 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  663702 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663706 */     GIR_RootConstrainSelectedInstOperands,
     /*  663707 */     // GIR_Coverage, 30823,
     /*  663707 */     GIR_EraseRootFromParent_Done,
     /*  663708 */   // Label 10398: @663708
     /*  663708 */   GIM_Try, /*On fail goto*//*Label 10399*/ GIMT_Encode4(663762), // Rule ID 30824 //
     /*  663713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  663716 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  663721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  663725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  663736 */     // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_i64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  663736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
     /*  663739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  663741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  663746 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  663748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  663753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  663756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663760 */     GIR_RootConstrainSelectedInstOperands,
     /*  663761 */     // GIR_Coverage, 30824,
     /*  663761 */     GIR_EraseRootFromParent_Done,
     /*  663762 */   // Label 10399: @663762
     /*  663762 */   GIM_Try, /*On fail goto*//*Label 10400*/ GIMT_Encode4(663821), // Rule ID 13205 //
     /*  663767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  663770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  663777 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  663779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663783 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  663790 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  663790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR),
     /*  663793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  663798 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  663800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  663805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  663810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  663815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663819 */     GIR_RootConstrainSelectedInstOperands,
     /*  663820 */     // GIR_Coverage, 13205,
     /*  663820 */     GIR_EraseRootFromParent_Done,
     /*  663821 */   // Label 10400: @663821
     /*  663821 */   GIM_Try, /*On fail goto*//*Label 10401*/ GIMT_Encode4(663880), // Rule ID 13206 //
     /*  663826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  663829 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  663836 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  663838 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  663849 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  663849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR),
     /*  663852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  663857 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  663859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  663864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  663869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  663874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663878 */     GIR_RootConstrainSelectedInstOperands,
     /*  663879 */     // GIR_Coverage, 13206,
     /*  663879 */     GIR_EraseRootFromParent_Done,
     /*  663880 */   // Label 10401: @663880
     /*  663880 */   GIM_Try, /*On fail goto*//*Label 10402*/ GIMT_Encode4(663939), // Rule ID 13207 //
     /*  663885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  663888 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  663895 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  663897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  663908 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  663908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR),
     /*  663911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  663916 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  663918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  663923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  663928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  663933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663937 */     GIR_RootConstrainSelectedInstOperands,
     /*  663938 */     // GIR_Coverage, 13207,
     /*  663938 */     GIR_EraseRootFromParent_Done,
     /*  663939 */   // Label 10402: @663939
     /*  663939 */   GIM_Try, /*On fail goto*//*Label 10403*/ GIMT_Encode4(663998), // Rule ID 13208 //
     /*  663944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  663947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  663954 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  663956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  663960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  663967 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  663967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR),
     /*  663970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  663975 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  663977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  663982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  663987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  663992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  663996 */     GIR_RootConstrainSelectedInstOperands,
     /*  663997 */     // GIR_Coverage, 13208,
     /*  663997 */     GIR_EraseRootFromParent_Done,
     /*  663998 */   // Label 10403: @663998
     /*  663998 */   GIM_Try, /*On fail goto*//*Label 10404*/ GIMT_Encode4(664057), // Rule ID 13209 //
     /*  664003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  664006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664013 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  664026 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR),
     /*  664029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664034 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664055 */     GIR_RootConstrainSelectedInstOperands,
     /*  664056 */     // GIR_Coverage, 13209,
     /*  664056 */     GIR_EraseRootFromParent_Done,
     /*  664057 */   // Label 10404: @664057
     /*  664057 */   GIM_Try, /*On fail goto*//*Label 10405*/ GIMT_Encode4(664120), // Rule ID 13215 //
     /*  664062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  664065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  664087 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  664090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664097 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664118 */     GIR_RootConstrainSelectedInstOperands,
     /*  664119 */     // GIR_Coverage, 13215,
     /*  664119 */     GIR_EraseRootFromParent_Done,
     /*  664120 */   // Label 10405: @664120
     /*  664120 */   GIM_Try, /*On fail goto*//*Label 10406*/ GIMT_Encode4(664183), // Rule ID 13216 //
     /*  664125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  664128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  664150 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  664153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664160 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664181 */     GIR_RootConstrainSelectedInstOperands,
     /*  664182 */     // GIR_Coverage, 13216,
     /*  664182 */     GIR_EraseRootFromParent_Done,
     /*  664183 */   // Label 10406: @664183
     /*  664183 */   GIM_Try, /*On fail goto*//*Label 10407*/ GIMT_Encode4(664246), // Rule ID 13217 //
     /*  664188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  664191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664206 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  664213 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  664216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664223 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664244 */     GIR_RootConstrainSelectedInstOperands,
     /*  664245 */     // GIR_Coverage, 13217,
     /*  664245 */     GIR_EraseRootFromParent_Done,
     /*  664246 */   // Label 10407: @664246
     /*  664246 */   GIM_Try, /*On fail goto*//*Label 10408*/ GIMT_Encode4(664309), // Rule ID 13218 //
     /*  664251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  664254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  664276 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  664279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664286 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664307 */     GIR_RootConstrainSelectedInstOperands,
     /*  664308 */     // GIR_Coverage, 13218,
     /*  664308 */     GIR_EraseRootFromParent_Done,
     /*  664309 */   // Label 10408: @664309
     /*  664309 */   GIM_Try, /*On fail goto*//*Label 10409*/ GIMT_Encode4(664372), // Rule ID 13219 //
     /*  664314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  664317 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  664339 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  664342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664349 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664370 */     GIR_RootConstrainSelectedInstOperands,
     /*  664371 */     // GIR_Coverage, 13219,
     /*  664371 */     GIR_EraseRootFromParent_Done,
     /*  664372 */   // Label 10409: @664372
     /*  664372 */   GIM_Try, /*On fail goto*//*Label 10410*/ GIMT_Encode4(664424), // Rule ID 13200 //
     /*  664377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  664380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664400 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2),
     /*  664403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664408 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  664418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664422 */     GIR_RootConstrainSelectedInstOperands,
     /*  664423 */     // GIR_Coverage, 13200,
     /*  664423 */     GIR_EraseRootFromParent_Done,
     /*  664424 */   // Label 10410: @664424
     /*  664424 */   GIM_Try, /*On fail goto*//*Label 10411*/ GIMT_Encode4(664476), // Rule ID 13201 //
     /*  664429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  664432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664439 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664452 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2),
     /*  664455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664460 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  664470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664474 */     GIR_RootConstrainSelectedInstOperands,
     /*  664475 */     // GIR_Coverage, 13201,
     /*  664475 */     GIR_EraseRootFromParent_Done,
     /*  664476 */   // Label 10411: @664476
     /*  664476 */   GIM_Try, /*On fail goto*//*Label 10412*/ GIMT_Encode4(664528), // Rule ID 13202 //
     /*  664481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  664484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664491 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664504 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2),
     /*  664507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664512 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  664522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664526 */     GIR_RootConstrainSelectedInstOperands,
     /*  664527 */     // GIR_Coverage, 13202,
     /*  664527 */     GIR_EraseRootFromParent_Done,
     /*  664528 */   // Label 10412: @664528
     /*  664528 */   GIM_Try, /*On fail goto*//*Label 10413*/ GIMT_Encode4(664580), // Rule ID 13203 //
     /*  664533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  664536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664543 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664556 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2),
     /*  664559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664564 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  664574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664578 */     GIR_RootConstrainSelectedInstOperands,
     /*  664579 */     // GIR_Coverage, 13203,
     /*  664579 */     GIR_EraseRootFromParent_Done,
     /*  664580 */   // Label 10413: @664580
     /*  664580 */   GIM_Try, /*On fail goto*//*Label 10414*/ GIMT_Encode4(664632), // Rule ID 13204 //
     /*  664585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  664588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664595 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664608 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2),
     /*  664611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664616 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  664626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664630 */     GIR_RootConstrainSelectedInstOperands,
     /*  664631 */     // GIR_Coverage, 13204,
     /*  664631 */     GIR_EraseRootFromParent_Done,
     /*  664632 */   // Label 10414: @664632
     /*  664632 */   GIM_Try, /*On fail goto*//*Label 10415*/ GIMT_Encode4(664688), // Rule ID 13210 //
     /*  664637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  664640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664662 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN),
     /*  664665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664672 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  664682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664686 */     GIR_RootConstrainSelectedInstOperands,
     /*  664687 */     // GIR_Coverage, 13210,
     /*  664687 */     GIR_EraseRootFromParent_Done,
     /*  664688 */   // Label 10415: @664688
     /*  664688 */   GIM_Try, /*On fail goto*//*Label 10416*/ GIMT_Encode4(664744), // Rule ID 13211 //
     /*  664693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  664696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664718 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN),
     /*  664721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664728 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  664738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664742 */     GIR_RootConstrainSelectedInstOperands,
     /*  664743 */     // GIR_Coverage, 13211,
     /*  664743 */     GIR_EraseRootFromParent_Done,
     /*  664744 */   // Label 10416: @664744
     /*  664744 */   GIM_Try, /*On fail goto*//*Label 10417*/ GIMT_Encode4(664800), // Rule ID 13212 //
     /*  664749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  664752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664774 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN),
     /*  664777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664784 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  664794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664798 */     GIR_RootConstrainSelectedInstOperands,
     /*  664799 */     // GIR_Coverage, 13212,
     /*  664799 */     GIR_EraseRootFromParent_Done,
     /*  664800 */   // Label 10417: @664800
     /*  664800 */   GIM_Try, /*On fail goto*//*Label 10418*/ GIMT_Encode4(664856), // Rule ID 13213 //
     /*  664805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  664808 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664830 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN),
     /*  664833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664840 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  664850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664854 */     GIR_RootConstrainSelectedInstOperands,
     /*  664855 */     // GIR_Coverage, 13213,
     /*  664855 */     GIR_EraseRootFromParent_Done,
     /*  664856 */   // Label 10418: @664856
     /*  664856 */   GIM_Try, /*On fail goto*//*Label 10419*/ GIMT_Encode4(664912), // Rule ID 13214 //
     /*  664861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  664864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  664875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  664886 */     // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  664886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN),
     /*  664889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  664891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  664896 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  664903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  664906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664910 */     GIR_RootConstrainSelectedInstOperands,
     /*  664911 */     // GIR_Coverage, 13214,
     /*  664911 */     GIR_EraseRootFromParent_Done,
     /*  664912 */   // Label 10419: @664912
     /*  664912 */   GIM_Try, /*On fail goto*//*Label 10420*/ GIMT_Encode4(664972), // Rule ID 10797 //
     /*  664917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  664920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664928 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  664941 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  664941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  664944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  664949 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  664951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  664956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  664961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  664966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  664970 */     GIR_RootConstrainSelectedInstOperands,
     /*  664971 */     // GIR_Coverage, 10797,
     /*  664971 */     GIR_EraseRootFromParent_Done,
     /*  664972 */   // Label 10420: @664972
     /*  664972 */   GIM_Try, /*On fail goto*//*Label 10421*/ GIMT_Encode4(665032), // Rule ID 10798 //
     /*  664977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  664980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  664988 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  664990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  664994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665001 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665009 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665030 */     GIR_RootConstrainSelectedInstOperands,
     /*  665031 */     // GIR_Coverage, 10798,
     /*  665031 */     GIR_EraseRootFromParent_Done,
     /*  665032 */   // Label 10421: @665032
     /*  665032 */   GIM_Try, /*On fail goto*//*Label 10422*/ GIMT_Encode4(665092), // Rule ID 10799 //
     /*  665037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  665040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665048 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665061 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665069 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665090 */     GIR_RootConstrainSelectedInstOperands,
     /*  665091 */     // GIR_Coverage, 10799,
     /*  665091 */     GIR_EraseRootFromParent_Done,
     /*  665092 */   // Label 10422: @665092
     /*  665092 */   GIM_Try, /*On fail goto*//*Label 10423*/ GIMT_Encode4(665152), // Rule ID 10800 //
     /*  665097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  665100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665108 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665121 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665129 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665150 */     GIR_RootConstrainSelectedInstOperands,
     /*  665151 */     // GIR_Coverage, 10800,
     /*  665151 */     GIR_EraseRootFromParent_Done,
     /*  665152 */   // Label 10423: @665152
     /*  665152 */   GIM_Try, /*On fail goto*//*Label 10424*/ GIMT_Encode4(665212), // Rule ID 10801 //
     /*  665157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  665160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665168 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665181 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665189 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665210 */     GIR_RootConstrainSelectedInstOperands,
     /*  665211 */     // GIR_Coverage, 10801,
     /*  665211 */     GIR_EraseRootFromParent_Done,
     /*  665212 */   // Label 10424: @665212
     /*  665212 */   GIM_Try, /*On fail goto*//*Label 10425*/ GIMT_Encode4(665271), // Rule ID 11353 //
     /*  665217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  665220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665227 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665240 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665248 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665269 */     GIR_RootConstrainSelectedInstOperands,
     /*  665270 */     // GIR_Coverage, 11353,
     /*  665270 */     GIR_EraseRootFromParent_Done,
     /*  665271 */   // Label 10425: @665271
     /*  665271 */   GIM_Try, /*On fail goto*//*Label 10426*/ GIMT_Encode4(665330), // Rule ID 11354 //
     /*  665276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  665279 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665286 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665299 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665307 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665328 */     GIR_RootConstrainSelectedInstOperands,
     /*  665329 */     // GIR_Coverage, 11354,
     /*  665329 */     GIR_EraseRootFromParent_Done,
     /*  665330 */   // Label 10426: @665330
     /*  665330 */   GIM_Try, /*On fail goto*//*Label 10427*/ GIMT_Encode4(665389), // Rule ID 11355 //
     /*  665335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  665338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665345 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665358 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665366 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665383 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665387 */     GIR_RootConstrainSelectedInstOperands,
     /*  665388 */     // GIR_Coverage, 11355,
     /*  665388 */     GIR_EraseRootFromParent_Done,
     /*  665389 */   // Label 10427: @665389
     /*  665389 */   GIM_Try, /*On fail goto*//*Label 10428*/ GIMT_Encode4(665448), // Rule ID 11356 //
     /*  665394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  665397 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665404 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665417 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665425 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665446 */     GIR_RootConstrainSelectedInstOperands,
     /*  665447 */     // GIR_Coverage, 11356,
     /*  665447 */     GIR_EraseRootFromParent_Done,
     /*  665448 */   // Label 10428: @665448
     /*  665448 */   GIM_Try, /*On fail goto*//*Label 10429*/ GIMT_Encode4(665507), // Rule ID 11357 //
     /*  665453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  665456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665463 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  665465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  665476 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR),
     /*  665479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665484 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665505 */     GIR_RootConstrainSelectedInstOperands,
     /*  665506 */     // GIR_Coverage, 11357,
     /*  665506 */     GIR_EraseRootFromParent_Done,
     /*  665507 */   // Label 10429: @665507
     /*  665507 */   GIM_Try, /*On fail goto*//*Label 10430*/ GIMT_Encode4(665571), // Rule ID 10787 //
     /*  665512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  665515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665538 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665548 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665569 */     GIR_RootConstrainSelectedInstOperands,
     /*  665570 */     // GIR_Coverage, 10787,
     /*  665570 */     GIR_EraseRootFromParent_Done,
     /*  665571 */   // Label 10430: @665571
     /*  665571 */   GIM_Try, /*On fail goto*//*Label 10431*/ GIMT_Encode4(665635), // Rule ID 10788 //
     /*  665576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  665579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665602 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665612 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665633 */     GIR_RootConstrainSelectedInstOperands,
     /*  665634 */     // GIR_Coverage, 10788,
     /*  665634 */     GIR_EraseRootFromParent_Done,
     /*  665635 */   // Label 10431: @665635
     /*  665635 */   GIM_Try, /*On fail goto*//*Label 10432*/ GIMT_Encode4(665699), // Rule ID 10789 //
     /*  665640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  665643 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665666 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665676 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665697 */     GIR_RootConstrainSelectedInstOperands,
     /*  665698 */     // GIR_Coverage, 10789,
     /*  665698 */     GIR_EraseRootFromParent_Done,
     /*  665699 */   // Label 10432: @665699
     /*  665699 */   GIM_Try, /*On fail goto*//*Label 10433*/ GIMT_Encode4(665763), // Rule ID 10790 //
     /*  665704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  665707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665730 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665740 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665761 */     GIR_RootConstrainSelectedInstOperands,
     /*  665762 */     // GIR_Coverage, 10790,
     /*  665762 */     GIR_EraseRootFromParent_Done,
     /*  665763 */   // Label 10433: @665763
     /*  665763 */   GIM_Try, /*On fail goto*//*Label 10434*/ GIMT_Encode4(665827), // Rule ID 10791 //
     /*  665768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  665771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665794 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665804 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665825 */     GIR_RootConstrainSelectedInstOperands,
     /*  665826 */     // GIR_Coverage, 10791,
     /*  665826 */     GIR_EraseRootFromParent_Done,
     /*  665827 */   // Label 10434: @665827
     /*  665827 */   GIM_Try, /*On fail goto*//*Label 10435*/ GIMT_Encode4(665890), // Rule ID 11343 //
     /*  665832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  665835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665857 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665867 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665888 */     GIR_RootConstrainSelectedInstOperands,
     /*  665889 */     // GIR_Coverage, 11343,
     /*  665889 */     GIR_EraseRootFromParent_Done,
     /*  665890 */   // Label 10435: @665890
     /*  665890 */   GIM_Try, /*On fail goto*//*Label 10436*/ GIMT_Encode4(665953), // Rule ID 11344 //
     /*  665895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  665898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665909 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665920 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665930 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  665937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  665942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  665947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  665951 */     GIR_RootConstrainSelectedInstOperands,
     /*  665952 */     // GIR_Coverage, 11344,
     /*  665952 */     GIR_EraseRootFromParent_Done,
     /*  665953 */   // Label 10436: @665953
     /*  665953 */   GIM_Try, /*On fail goto*//*Label 10437*/ GIMT_Encode4(666016), // Rule ID 11345 //
     /*  665958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  665961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  665968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  665972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  665976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  665983 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  665983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  665986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  665988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  665993 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  665995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  666000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  666005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  666010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666014 */     GIR_RootConstrainSelectedInstOperands,
     /*  666015 */     // GIR_Coverage, 11345,
     /*  666015 */     GIR_EraseRootFromParent_Done,
     /*  666016 */   // Label 10437: @666016
     /*  666016 */   GIM_Try, /*On fail goto*//*Label 10438*/ GIMT_Encode4(666079), // Rule ID 11346 //
     /*  666021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  666024 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  666046 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  666046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  666049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  666056 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  666063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  666068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  666073 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666077 */     GIR_RootConstrainSelectedInstOperands,
     /*  666078 */     // GIR_Coverage, 11346,
     /*  666078 */     GIR_EraseRootFromParent_Done,
     /*  666079 */   // Label 10438: @666079
     /*  666079 */   GIM_Try, /*On fail goto*//*Label 10439*/ GIMT_Encode4(666142), // Rule ID 11347 //
     /*  666084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  666087 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666102 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  666109 */     // (atomic_load_max:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  666109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_SADDR_RTN),
     /*  666112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  666119 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  666126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  666131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  666136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666140 */     GIR_RootConstrainSelectedInstOperands,
     /*  666141 */     // GIR_Coverage, 11347,
     /*  666141 */     GIR_EraseRootFromParent_Done,
     /*  666142 */   // Label 10439: @666142
     /*  666142 */   GIM_Try, /*On fail goto*//*Label 10440*/ GIMT_Encode4(666195), // Rule ID 10792 //
     /*  666147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  666150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666158 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666171 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666179 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666189 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666193 */     GIR_RootConstrainSelectedInstOperands,
     /*  666194 */     // GIR_Coverage, 10792,
     /*  666194 */     GIR_EraseRootFromParent_Done,
     /*  666195 */   // Label 10440: @666195
     /*  666195 */   GIM_Try, /*On fail goto*//*Label 10441*/ GIMT_Encode4(666248), // Rule ID 10793 //
     /*  666200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  666203 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666211 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666213 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666224 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666232 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666246 */     GIR_RootConstrainSelectedInstOperands,
     /*  666247 */     // GIR_Coverage, 10793,
     /*  666247 */     GIR_EraseRootFromParent_Done,
     /*  666248 */   // Label 10441: @666248
     /*  666248 */   GIM_Try, /*On fail goto*//*Label 10442*/ GIMT_Encode4(666301), // Rule ID 10794 //
     /*  666253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  666256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666264 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666266 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666277 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666285 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666295 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666299 */     GIR_RootConstrainSelectedInstOperands,
     /*  666300 */     // GIR_Coverage, 10794,
     /*  666300 */     GIR_EraseRootFromParent_Done,
     /*  666301 */   // Label 10442: @666301
     /*  666301 */   GIM_Try, /*On fail goto*//*Label 10443*/ GIMT_Encode4(666354), // Rule ID 10795 //
     /*  666306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  666309 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666317 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666330 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666338 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666348 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666352 */     GIR_RootConstrainSelectedInstOperands,
     /*  666353 */     // GIR_Coverage, 10795,
     /*  666353 */     GIR_EraseRootFromParent_Done,
     /*  666354 */   // Label 10443: @666354
     /*  666354 */   GIM_Try, /*On fail goto*//*Label 10444*/ GIMT_Encode4(666407), // Rule ID 10796 //
     /*  666359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  666362 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666370 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666383 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666391 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666405 */     GIR_RootConstrainSelectedInstOperands,
     /*  666406 */     // GIR_Coverage, 10796,
     /*  666406 */     GIR_EraseRootFromParent_Done,
     /*  666407 */   // Label 10444: @666407
     /*  666407 */   GIM_Try, /*On fail goto*//*Label 10445*/ GIMT_Encode4(666459), // Rule ID 11348 //
     /*  666412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  666415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666422 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666424 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666435 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666443 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666457 */     GIR_RootConstrainSelectedInstOperands,
     /*  666458 */     // GIR_Coverage, 11348,
     /*  666458 */     GIR_EraseRootFromParent_Done,
     /*  666459 */   // Label 10445: @666459
     /*  666459 */   GIM_Try, /*On fail goto*//*Label 10446*/ GIMT_Encode4(666511), // Rule ID 11349 //
     /*  666464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  666467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666474 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666476 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666480 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666487 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666495 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666509 */     GIR_RootConstrainSelectedInstOperands,
     /*  666510 */     // GIR_Coverage, 11349,
     /*  666510 */     GIR_EraseRootFromParent_Done,
     /*  666511 */   // Label 10446: @666511
     /*  666511 */   GIM_Try, /*On fail goto*//*Label 10447*/ GIMT_Encode4(666563), // Rule ID 11350 //
     /*  666516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  666519 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666526 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666539 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666547 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666554 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666557 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666561 */     GIR_RootConstrainSelectedInstOperands,
     /*  666562 */     // GIR_Coverage, 11350,
     /*  666562 */     GIR_EraseRootFromParent_Done,
     /*  666563 */   // Label 10447: @666563
     /*  666563 */   GIM_Try, /*On fail goto*//*Label 10448*/ GIMT_Encode4(666615), // Rule ID 11351 //
     /*  666568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  666571 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666578 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666591 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666599 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666613 */     GIR_RootConstrainSelectedInstOperands,
     /*  666614 */     // GIR_Coverage, 11351,
     /*  666614 */     GIR_EraseRootFromParent_Done,
     /*  666615 */   // Label 10448: @666615
     /*  666615 */   GIM_Try, /*On fail goto*//*Label 10449*/ GIMT_Encode4(666667), // Rule ID 11352 //
     /*  666620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  666623 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666630 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  666632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666643 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
     /*  666646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666651 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  666661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666665 */     GIR_RootConstrainSelectedInstOperands,
     /*  666666 */     // GIR_Coverage, 11352,
     /*  666666 */     GIR_EraseRootFromParent_Done,
     /*  666667 */   // Label 10449: @666667
     /*  666667 */   GIM_Try, /*On fail goto*//*Label 10450*/ GIMT_Encode4(666724), // Rule ID 10782 //
     /*  666672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  666675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666687 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666698 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  666701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666708 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  666718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666722 */     GIR_RootConstrainSelectedInstOperands,
     /*  666723 */     // GIR_Coverage, 10782,
     /*  666723 */     GIR_EraseRootFromParent_Done,
     /*  666724 */   // Label 10450: @666724
     /*  666724 */   GIM_Try, /*On fail goto*//*Label 10451*/ GIMT_Encode4(666781), // Rule ID 10783 //
     /*  666729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  666732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666755 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  666758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666765 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  666775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666779 */     GIR_RootConstrainSelectedInstOperands,
     /*  666780 */     // GIR_Coverage, 10783,
     /*  666780 */     GIR_EraseRootFromParent_Done,
     /*  666781 */   // Label 10451: @666781
     /*  666781 */   GIM_Try, /*On fail goto*//*Label 10452*/ GIMT_Encode4(666838), // Rule ID 10784 //
     /*  666786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  666789 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666812 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  666815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666822 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  666832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666836 */     GIR_RootConstrainSelectedInstOperands,
     /*  666837 */     // GIR_Coverage, 10784,
     /*  666837 */     GIR_EraseRootFromParent_Done,
     /*  666838 */   // Label 10452: @666838
     /*  666838 */   GIM_Try, /*On fail goto*//*Label 10453*/ GIMT_Encode4(666895), // Rule ID 10785 //
     /*  666843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  666846 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666862 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666869 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  666872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666879 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  666889 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666893 */     GIR_RootConstrainSelectedInstOperands,
     /*  666894 */     // GIR_Coverage, 10785,
     /*  666894 */     GIR_EraseRootFromParent_Done,
     /*  666895 */   // Label 10453: @666895
     /*  666895 */   GIM_Try, /*On fail goto*//*Label 10454*/ GIMT_Encode4(666952), // Rule ID 10786 //
     /*  666900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  666903 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666926 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  666929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666936 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  666946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  666950 */     GIR_RootConstrainSelectedInstOperands,
     /*  666951 */     // GIR_Coverage, 10786,
     /*  666951 */     GIR_EraseRootFromParent_Done,
     /*  666952 */   // Label 10454: @666952
     /*  666952 */   GIM_Try, /*On fail goto*//*Label 10455*/ GIMT_Encode4(667008), // Rule ID 11338 //
     /*  666957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  666960 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  666967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  666971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  666975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  666982 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  666982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  666985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  666987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  666992 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  666994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  666999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  667002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667006 */     GIR_RootConstrainSelectedInstOperands,
     /*  667007 */     // GIR_Coverage, 11338,
     /*  667007 */     GIR_EraseRootFromParent_Done,
     /*  667008 */   // Label 10455: @667008
     /*  667008 */   GIM_Try, /*On fail goto*//*Label 10456*/ GIMT_Encode4(667064), // Rule ID 11339 //
     /*  667013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  667016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  667027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  667038 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  667038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  667041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  667043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  667048 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  667050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  667055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  667058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667062 */     GIR_RootConstrainSelectedInstOperands,
     /*  667063 */     // GIR_Coverage, 11339,
     /*  667063 */     GIR_EraseRootFromParent_Done,
     /*  667064 */   // Label 10456: @667064
     /*  667064 */   GIM_Try, /*On fail goto*//*Label 10457*/ GIMT_Encode4(667120), // Rule ID 11340 //
     /*  667069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  667072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  667083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  667094 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  667094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  667097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  667099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  667104 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  667106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  667111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  667114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667118 */     GIR_RootConstrainSelectedInstOperands,
     /*  667119 */     // GIR_Coverage, 11340,
     /*  667119 */     GIR_EraseRootFromParent_Done,
     /*  667120 */   // Label 10457: @667120
     /*  667120 */   GIM_Try, /*On fail goto*//*Label 10458*/ GIMT_Encode4(667176), // Rule ID 11341 //
     /*  667125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  667128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  667139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  667150 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  667150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  667153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  667155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  667160 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  667162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  667167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  667170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667174 */     GIR_RootConstrainSelectedInstOperands,
     /*  667175 */     // GIR_Coverage, 11341,
     /*  667175 */     GIR_EraseRootFromParent_Done,
     /*  667176 */   // Label 10458: @667176
     /*  667176 */   GIM_Try, /*On fail goto*//*Label 10459*/ GIMT_Encode4(667232), // Rule ID 11342 //
     /*  667181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  667184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  667195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  667206 */     // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  667206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
     /*  667209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  667211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  667216 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  667218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  667223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  667226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667230 */     GIR_RootConstrainSelectedInstOperands,
     /*  667231 */     // GIR_Coverage, 11342,
     /*  667231 */     GIR_EraseRootFromParent_Done,
     /*  667232 */   // Label 10459: @667232
     /*  667232 */   GIM_Reject,
     /*  667233 */ // Label 10329: @667233
     /*  667233 */ GIM_Reject,
     /*  667234 */ // Label 10221: @667234
     /*  667234 */ GIM_Reject,
     /*  667235 */ // Label 26: @667235
     /*  667235 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 10462*/ GIMT_Encode4(680846),
     /*  667246 */ /*GILLT_s32*//*Label 10460*/ GIMT_Encode4(667254),
     /*  667250 */ /*GILLT_s64*//*Label 10461*/ GIMT_Encode4(673346),
     /*  667254 */ // Label 10460: @667254
     /*  667254 */ GIM_Try, /*On fail goto*//*Label 10463*/ GIMT_Encode4(673345),
     /*  667259 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  667262 */   GIM_Try, /*On fail goto*//*Label 10464*/ GIMT_Encode4(667324), // Rule ID 20858 //
     /*  667267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  667270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667277 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667279 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667290 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64),
     /*  667293 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667322 */     GIR_RootConstrainSelectedInstOperands,
     /*  667323 */     // GIR_Coverage, 20858,
     /*  667323 */     GIR_EraseRootFromParent_Done,
     /*  667324 */   // Label 10464: @667324
     /*  667324 */   GIM_Try, /*On fail goto*//*Label 10465*/ GIMT_Encode4(667386), // Rule ID 20859 //
     /*  667329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  667332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667339 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667341 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667352 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64),
     /*  667355 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667384 */     GIR_RootConstrainSelectedInstOperands,
     /*  667385 */     // GIR_Coverage, 20859,
     /*  667385 */     GIR_EraseRootFromParent_Done,
     /*  667386 */   // Label 10465: @667386
     /*  667386 */   GIM_Try, /*On fail goto*//*Label 10466*/ GIMT_Encode4(667448), // Rule ID 20860 //
     /*  667391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  667394 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667401 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667414 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64),
     /*  667417 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667446 */     GIR_RootConstrainSelectedInstOperands,
     /*  667447 */     // GIR_Coverage, 20860,
     /*  667447 */     GIR_EraseRootFromParent_Done,
     /*  667448 */   // Label 10466: @667448
     /*  667448 */   GIM_Try, /*On fail goto*//*Label 10467*/ GIMT_Encode4(667510), // Rule ID 20861 //
     /*  667453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  667456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667463 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667476 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64),
     /*  667479 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667508 */     GIR_RootConstrainSelectedInstOperands,
     /*  667509 */     // GIR_Coverage, 20861,
     /*  667509 */     GIR_EraseRootFromParent_Done,
     /*  667510 */   // Label 10467: @667510
     /*  667510 */   GIM_Try, /*On fail goto*//*Label 10468*/ GIMT_Encode4(667572), // Rule ID 20862 //
     /*  667515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  667518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667525 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667538 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64),
     /*  667541 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667566 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667570 */     GIR_RootConstrainSelectedInstOperands,
     /*  667571 */     // GIR_Coverage, 20862,
     /*  667571 */     GIR_EraseRootFromParent_Done,
     /*  667572 */   // Label 10468: @667572
     /*  667572 */   GIM_Try, /*On fail goto*//*Label 10469*/ GIMT_Encode4(667634), // Rule ID 20878 //
     /*  667577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  667580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667587 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667600 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64),
     /*  667603 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667632 */     GIR_RootConstrainSelectedInstOperands,
     /*  667633 */     // GIR_Coverage, 20878,
     /*  667633 */     GIR_EraseRootFromParent_Done,
     /*  667634 */   // Label 10469: @667634
     /*  667634 */   GIM_Try, /*On fail goto*//*Label 10470*/ GIMT_Encode4(667696), // Rule ID 20879 //
     /*  667639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  667642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667649 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667662 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64),
     /*  667665 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667694 */     GIR_RootConstrainSelectedInstOperands,
     /*  667695 */     // GIR_Coverage, 20879,
     /*  667695 */     GIR_EraseRootFromParent_Done,
     /*  667696 */   // Label 10470: @667696
     /*  667696 */   GIM_Try, /*On fail goto*//*Label 10471*/ GIMT_Encode4(667758), // Rule ID 20880 //
     /*  667701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  667704 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667711 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667724 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64),
     /*  667727 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667756 */     GIR_RootConstrainSelectedInstOperands,
     /*  667757 */     // GIR_Coverage, 20880,
     /*  667757 */     GIR_EraseRootFromParent_Done,
     /*  667758 */   // Label 10471: @667758
     /*  667758 */   GIM_Try, /*On fail goto*//*Label 10472*/ GIMT_Encode4(667820), // Rule ID 20881 //
     /*  667763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  667766 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667773 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667786 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64),
     /*  667789 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667818 */     GIR_RootConstrainSelectedInstOperands,
     /*  667819 */     // GIR_Coverage, 20881,
     /*  667819 */     GIR_EraseRootFromParent_Done,
     /*  667820 */   // Label 10472: @667820
     /*  667820 */   GIM_Try, /*On fail goto*//*Label 10473*/ GIMT_Encode4(667882), // Rule ID 20882 //
     /*  667825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  667828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  667837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667848 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64),
     /*  667851 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  667876 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667880 */     GIR_RootConstrainSelectedInstOperands,
     /*  667881 */     // GIR_Coverage, 20882,
     /*  667881 */     GIR_EraseRootFromParent_Done,
     /*  667882 */   // Label 10473: @667882
     /*  667882 */   GIM_Try, /*On fail goto*//*Label 10474*/ GIMT_Encode4(667948), // Rule ID 20848 //
     /*  667887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  667890 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  667901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667912 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN),
     /*  667915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  667917 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  667934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  667939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  667942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  667946 */     GIR_RootConstrainSelectedInstOperands,
     /*  667947 */     // GIR_Coverage, 20848,
     /*  667947 */     GIR_EraseRootFromParent_Done,
     /*  667948 */   // Label 10474: @667948
     /*  667948 */   GIM_Try, /*On fail goto*//*Label 10475*/ GIMT_Encode4(668014), // Rule ID 20849 //
     /*  667953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  667956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  667963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  667967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  667971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  667978 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  667978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN),
     /*  667981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  667983 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  667985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  667990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  667995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668012 */     GIR_RootConstrainSelectedInstOperands,
     /*  668013 */     // GIR_Coverage, 20849,
     /*  668013 */     GIR_EraseRootFromParent_Done,
     /*  668014 */   // Label 10475: @668014
     /*  668014 */   GIM_Try, /*On fail goto*//*Label 10476*/ GIMT_Encode4(668080), // Rule ID 20850 //
     /*  668019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  668022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668044 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN),
     /*  668047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668049 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668078 */     GIR_RootConstrainSelectedInstOperands,
     /*  668079 */     // GIR_Coverage, 20850,
     /*  668079 */     GIR_EraseRootFromParent_Done,
     /*  668080 */   // Label 10476: @668080
     /*  668080 */   GIM_Try, /*On fail goto*//*Label 10477*/ GIMT_Encode4(668146), // Rule ID 20851 //
     /*  668085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  668088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668110 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN),
     /*  668113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668115 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668140 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668144 */     GIR_RootConstrainSelectedInstOperands,
     /*  668145 */     // GIR_Coverage, 20851,
     /*  668145 */     GIR_EraseRootFromParent_Done,
     /*  668146 */   // Label 10477: @668146
     /*  668146 */   GIM_Try, /*On fail goto*//*Label 10478*/ GIMT_Encode4(668212), // Rule ID 20852 //
     /*  668151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  668154 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668176 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN),
     /*  668179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668181 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668210 */     GIR_RootConstrainSelectedInstOperands,
     /*  668211 */     // GIR_Coverage, 20852,
     /*  668211 */     GIR_EraseRootFromParent_Done,
     /*  668212 */   // Label 10478: @668212
     /*  668212 */   GIM_Try, /*On fail goto*//*Label 10479*/ GIMT_Encode4(668278), // Rule ID 20868 //
     /*  668217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  668220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668242 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN),
     /*  668245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668247 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668272 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668276 */     GIR_RootConstrainSelectedInstOperands,
     /*  668277 */     // GIR_Coverage, 20868,
     /*  668277 */     GIR_EraseRootFromParent_Done,
     /*  668278 */   // Label 10479: @668278
     /*  668278 */   GIM_Try, /*On fail goto*//*Label 10480*/ GIMT_Encode4(668344), // Rule ID 20869 //
     /*  668283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  668286 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668301 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668308 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN),
     /*  668311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668313 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668342 */     GIR_RootConstrainSelectedInstOperands,
     /*  668343 */     // GIR_Coverage, 20869,
     /*  668343 */     GIR_EraseRootFromParent_Done,
     /*  668344 */   // Label 10480: @668344
     /*  668344 */   GIM_Try, /*On fail goto*//*Label 10481*/ GIMT_Encode4(668410), // Rule ID 20870 //
     /*  668349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  668352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668374 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN),
     /*  668377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668379 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668408 */     GIR_RootConstrainSelectedInstOperands,
     /*  668409 */     // GIR_Coverage, 20870,
     /*  668409 */     GIR_EraseRootFromParent_Done,
     /*  668410 */   // Label 10481: @668410
     /*  668410 */   GIM_Try, /*On fail goto*//*Label 10482*/ GIMT_Encode4(668476), // Rule ID 20871 //
     /*  668415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  668418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668440 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN),
     /*  668443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668445 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668474 */     GIR_RootConstrainSelectedInstOperands,
     /*  668475 */     // GIR_Coverage, 20871,
     /*  668475 */     GIR_EraseRootFromParent_Done,
     /*  668476 */   // Label 10482: @668476
     /*  668476 */   GIM_Try, /*On fail goto*//*Label 10483*/ GIMT_Encode4(668542), // Rule ID 20872 //
     /*  668481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  668484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  668495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  668506 */     // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN),
     /*  668509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  668511 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  668518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  668528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  668533 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  668536 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668540 */     GIR_RootConstrainSelectedInstOperands,
     /*  668541 */     // GIR_Coverage, 20872,
     /*  668541 */     GIR_EraseRootFromParent_Done,
     /*  668542 */   // Label 10483: @668542
     /*  668542 */   GIM_Try, /*On fail goto*//*Label 10484*/ GIMT_Encode4(668599), // Rule ID 20853 //
     /*  668547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  668550 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668557 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668570 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
     /*  668573 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668597 */     GIR_RootConstrainSelectedInstOperands,
     /*  668598 */     // GIR_Coverage, 20853,
     /*  668598 */     GIR_EraseRootFromParent_Done,
     /*  668599 */   // Label 10484: @668599
     /*  668599 */   GIM_Try, /*On fail goto*//*Label 10485*/ GIMT_Encode4(668656), // Rule ID 20854 //
     /*  668604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  668607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668614 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668627 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
     /*  668630 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668654 */     GIR_RootConstrainSelectedInstOperands,
     /*  668655 */     // GIR_Coverage, 20854,
     /*  668655 */     GIR_EraseRootFromParent_Done,
     /*  668656 */   // Label 10485: @668656
     /*  668656 */   GIM_Try, /*On fail goto*//*Label 10486*/ GIMT_Encode4(668713), // Rule ID 20855 //
     /*  668661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  668664 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668671 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668684 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
     /*  668687 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668711 */     GIR_RootConstrainSelectedInstOperands,
     /*  668712 */     // GIR_Coverage, 20855,
     /*  668712 */     GIR_EraseRootFromParent_Done,
     /*  668713 */   // Label 10486: @668713
     /*  668713 */   GIM_Try, /*On fail goto*//*Label 10487*/ GIMT_Encode4(668770), // Rule ID 20856 //
     /*  668718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  668721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668728 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668741 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
     /*  668744 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668764 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668768 */     GIR_RootConstrainSelectedInstOperands,
     /*  668769 */     // GIR_Coverage, 20856,
     /*  668769 */     GIR_EraseRootFromParent_Done,
     /*  668770 */   // Label 10487: @668770
     /*  668770 */   GIM_Try, /*On fail goto*//*Label 10488*/ GIMT_Encode4(668827), // Rule ID 20857 //
     /*  668775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  668778 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668785 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668787 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668791 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668798 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
     /*  668801 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668825 */     GIR_RootConstrainSelectedInstOperands,
     /*  668826 */     // GIR_Coverage, 20857,
     /*  668826 */     GIR_EraseRootFromParent_Done,
     /*  668827 */   // Label 10488: @668827
     /*  668827 */   GIM_Try, /*On fail goto*//*Label 10489*/ GIMT_Encode4(668884), // Rule ID 20873 //
     /*  668832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  668835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668842 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668855 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
     /*  668858 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668878 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668882 */     GIR_RootConstrainSelectedInstOperands,
     /*  668883 */     // GIR_Coverage, 20873,
     /*  668883 */     GIR_EraseRootFromParent_Done,
     /*  668884 */   // Label 10489: @668884
     /*  668884 */   GIM_Try, /*On fail goto*//*Label 10490*/ GIMT_Encode4(668941), // Rule ID 20874 //
     /*  668889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  668892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668899 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668912 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
     /*  668915 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668932 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668935 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668939 */     GIR_RootConstrainSelectedInstOperands,
     /*  668940 */     // GIR_Coverage, 20874,
     /*  668940 */     GIR_EraseRootFromParent_Done,
     /*  668941 */   // Label 10490: @668941
     /*  668941 */   GIM_Try, /*On fail goto*//*Label 10491*/ GIMT_Encode4(668998), // Rule ID 20875 //
     /*  668946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  668949 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  668956 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  668958 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  668962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  668969 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  668969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
     /*  668972 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  668974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  668979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  668984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  668989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  668992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  668996 */     GIR_RootConstrainSelectedInstOperands,
     /*  668997 */     // GIR_Coverage, 20875,
     /*  668997 */     GIR_EraseRootFromParent_Done,
     /*  668998 */   // Label 10491: @668998
     /*  668998 */   GIM_Try, /*On fail goto*//*Label 10492*/ GIMT_Encode4(669055), // Rule ID 20876 //
     /*  669003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  669006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669013 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669026 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
     /*  669029 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669053 */     GIR_RootConstrainSelectedInstOperands,
     /*  669054 */     // GIR_Coverage, 20876,
     /*  669054 */     GIR_EraseRootFromParent_Done,
     /*  669055 */   // Label 10492: @669055
     /*  669055 */   GIM_Try, /*On fail goto*//*Label 10493*/ GIMT_Encode4(669112), // Rule ID 20877 //
     /*  669060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  669063 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669070 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669083 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
     /*  669086 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669110 */     GIR_RootConstrainSelectedInstOperands,
     /*  669111 */     // GIR_Coverage, 20877,
     /*  669111 */     GIR_EraseRootFromParent_Done,
     /*  669112 */   // Label 10493: @669112
     /*  669112 */   GIM_Try, /*On fail goto*//*Label 10494*/ GIMT_Encode4(669173), // Rule ID 20843 //
     /*  669117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  669120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669142 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
     /*  669145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669147 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669171 */     GIR_RootConstrainSelectedInstOperands,
     /*  669172 */     // GIR_Coverage, 20843,
     /*  669172 */     GIR_EraseRootFromParent_Done,
     /*  669173 */   // Label 10494: @669173
     /*  669173 */   GIM_Try, /*On fail goto*//*Label 10495*/ GIMT_Encode4(669234), // Rule ID 20844 //
     /*  669178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  669181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669203 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
     /*  669206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669208 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669232 */     GIR_RootConstrainSelectedInstOperands,
     /*  669233 */     // GIR_Coverage, 20844,
     /*  669233 */     GIR_EraseRootFromParent_Done,
     /*  669234 */   // Label 10495: @669234
     /*  669234 */   GIM_Try, /*On fail goto*//*Label 10496*/ GIMT_Encode4(669295), // Rule ID 20845 //
     /*  669239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  669242 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669264 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
     /*  669267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669269 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669293 */     GIR_RootConstrainSelectedInstOperands,
     /*  669294 */     // GIR_Coverage, 20845,
     /*  669294 */     GIR_EraseRootFromParent_Done,
     /*  669295 */   // Label 10496: @669295
     /*  669295 */   GIM_Try, /*On fail goto*//*Label 10497*/ GIMT_Encode4(669356), // Rule ID 20846 //
     /*  669300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  669303 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669314 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669318 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669325 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
     /*  669328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669330 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669354 */     GIR_RootConstrainSelectedInstOperands,
     /*  669355 */     // GIR_Coverage, 20846,
     /*  669355 */     GIR_EraseRootFromParent_Done,
     /*  669356 */   // Label 10497: @669356
     /*  669356 */   GIM_Try, /*On fail goto*//*Label 10498*/ GIMT_Encode4(669417), // Rule ID 20847 //
     /*  669361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  669364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669386 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
     /*  669389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669391 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669415 */     GIR_RootConstrainSelectedInstOperands,
     /*  669416 */     // GIR_Coverage, 20847,
     /*  669416 */     GIR_EraseRootFromParent_Done,
     /*  669417 */   // Label 10498: @669417
     /*  669417 */   GIM_Try, /*On fail goto*//*Label 10499*/ GIMT_Encode4(669478), // Rule ID 20863 //
     /*  669422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  669425 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669447 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
     /*  669450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669452 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669476 */     GIR_RootConstrainSelectedInstOperands,
     /*  669477 */     // GIR_Coverage, 20863,
     /*  669477 */     GIR_EraseRootFromParent_Done,
     /*  669478 */   // Label 10499: @669478
     /*  669478 */   GIM_Try, /*On fail goto*//*Label 10500*/ GIMT_Encode4(669539), // Rule ID 20864 //
     /*  669483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  669486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669508 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
     /*  669511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669513 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669537 */     GIR_RootConstrainSelectedInstOperands,
     /*  669538 */     // GIR_Coverage, 20864,
     /*  669538 */     GIR_EraseRootFromParent_Done,
     /*  669539 */   // Label 10500: @669539
     /*  669539 */   GIM_Try, /*On fail goto*//*Label 10501*/ GIMT_Encode4(669600), // Rule ID 20865 //
     /*  669544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  669547 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669569 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
     /*  669572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669574 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669598 */     GIR_RootConstrainSelectedInstOperands,
     /*  669599 */     // GIR_Coverage, 20865,
     /*  669599 */     GIR_EraseRootFromParent_Done,
     /*  669600 */   // Label 10501: @669600
     /*  669600 */   GIM_Try, /*On fail goto*//*Label 10502*/ GIMT_Encode4(669661), // Rule ID 20866 //
     /*  669605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  669608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669630 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
     /*  669633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669635 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669659 */     GIR_RootConstrainSelectedInstOperands,
     /*  669660 */     // GIR_Coverage, 20866,
     /*  669660 */     GIR_EraseRootFromParent_Done,
     /*  669661 */   // Label 10502: @669661
     /*  669661 */   GIM_Try, /*On fail goto*//*Label 10503*/ GIMT_Encode4(669722), // Rule ID 20867 //
     /*  669666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  669669 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  669676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  669680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  669691 */     // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  669691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
     /*  669694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  669696 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  669698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  669703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  669708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  669713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  669716 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669720 */     GIR_RootConstrainSelectedInstOperands,
     /*  669721 */     // GIR_Coverage, 20867,
     /*  669721 */     GIR_EraseRootFromParent_Done,
     /*  669722 */   // Label 10503: @669722
     /*  669722 */   GIM_Try, /*On fail goto*//*Label 10504*/ GIMT_Encode4(669772), // Rule ID 30402 //
     /*  669727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  669730 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  669735 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  669748 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  669748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  669751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  669756 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  669758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  669763 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669770 */     GIR_RootConstrainSelectedInstOperands,
     /*  669771 */     // GIR_Coverage, 30402,
     /*  669771 */     GIR_EraseRootFromParent_Done,
     /*  669772 */   // Label 10504: @669772
     /*  669772 */   GIM_Try, /*On fail goto*//*Label 10505*/ GIMT_Encode4(669822), // Rule ID 30403 //
     /*  669777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  669780 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  669785 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669787 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669791 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  669798 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  669798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  669801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  669806 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  669808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  669813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669816 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669820 */     GIR_RootConstrainSelectedInstOperands,
     /*  669821 */     // GIR_Coverage, 30403,
     /*  669821 */     GIR_EraseRootFromParent_Done,
     /*  669822 */   // Label 10505: @669822
     /*  669822 */   GIM_Try, /*On fail goto*//*Label 10506*/ GIMT_Encode4(669872), // Rule ID 30404 //
     /*  669827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  669830 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  669835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  669848 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  669848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  669851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  669856 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  669858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  669863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669870 */     GIR_RootConstrainSelectedInstOperands,
     /*  669871 */     // GIR_Coverage, 30404,
     /*  669871 */     GIR_EraseRootFromParent_Done,
     /*  669872 */   // Label 10506: @669872
     /*  669872 */   GIM_Try, /*On fail goto*//*Label 10507*/ GIMT_Encode4(669922), // Rule ID 30405 //
     /*  669877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  669880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  669885 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  669898 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  669898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  669901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  669906 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  669908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  669913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669920 */     GIR_RootConstrainSelectedInstOperands,
     /*  669921 */     // GIR_Coverage, 30405,
     /*  669921 */     GIR_EraseRootFromParent_Done,
     /*  669922 */   // Label 10507: @669922
     /*  669922 */   GIM_Try, /*On fail goto*//*Label 10508*/ GIMT_Encode4(669972), // Rule ID 30406 //
     /*  669927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  669930 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  669935 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  669948 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  669948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  669951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  669956 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  669958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  669963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  669966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  669970 */     GIR_RootConstrainSelectedInstOperands,
     /*  669971 */     // GIR_Coverage, 30406,
     /*  669971 */     GIR_EraseRootFromParent_Done,
     /*  669972 */   // Label 10508: @669972
     /*  669972 */   GIM_Try, /*On fail goto*//*Label 10509*/ GIMT_Encode4(670022), // Rule ID 30408 //
     /*  669977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  669980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  669985 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  669987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  669991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  669998 */     // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_i32>>  =>  (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  669998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9),
     /*  670001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670006 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670020 */     GIR_RootConstrainSelectedInstOperands,
     /*  670021 */     // GIR_Coverage, 30408,
     /*  670021 */     GIR_EraseRootFromParent_Done,
     /*  670022 */   // Label 10509: @670022
     /*  670022 */   GIM_Try, /*On fail goto*//*Label 10510*/ GIMT_Encode4(670072), // Rule ID 30409 //
     /*  670027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  670030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  670035 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670037 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670041 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670048 */     // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_i32>>  =>  (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  670048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9),
     /*  670051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670056 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670066 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670070 */     GIR_RootConstrainSelectedInstOperands,
     /*  670071 */     // GIR_Coverage, 30409,
     /*  670071 */     GIR_EraseRootFromParent_Done,
     /*  670072 */   // Label 10510: @670072
     /*  670072 */   GIM_Try, /*On fail goto*//*Label 10511*/ GIMT_Encode4(670122), // Rule ID 30410 //
     /*  670077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  670080 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  670085 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670087 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670098 */     // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_i32>>  =>  (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  670098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9),
     /*  670101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670106 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670120 */     GIR_RootConstrainSelectedInstOperands,
     /*  670121 */     // GIR_Coverage, 30410,
     /*  670121 */     GIR_EraseRootFromParent_Done,
     /*  670122 */   // Label 10511: @670122
     /*  670122 */   GIM_Try, /*On fail goto*//*Label 10512*/ GIMT_Encode4(670172), // Rule ID 30411 //
     /*  670127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  670130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  670135 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670148 */     // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_i32>>  =>  (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  670148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9),
     /*  670151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670156 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670170 */     GIR_RootConstrainSelectedInstOperands,
     /*  670171 */     // GIR_Coverage, 30411,
     /*  670171 */     GIR_EraseRootFromParent_Done,
     /*  670172 */   // Label 10512: @670172
     /*  670172 */   GIM_Try, /*On fail goto*//*Label 10513*/ GIMT_Encode4(670222), // Rule ID 30412 //
     /*  670177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  670180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  670185 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670187 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670198 */     // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_i32>>  =>  (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  670198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9),
     /*  670201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670206 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670220 */     GIR_RootConstrainSelectedInstOperands,
     /*  670221 */     // GIR_Coverage, 30412,
     /*  670221 */     GIR_EraseRootFromParent_Done,
     /*  670222 */   // Label 10513: @670222
     /*  670222 */   GIM_Try, /*On fail goto*//*Label 10514*/ GIMT_Encode4(670272), // Rule ID 30414 //
     /*  670227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  670230 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  670235 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670248 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  670248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  670251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670256 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  670266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670270 */     GIR_RootConstrainSelectedInstOperands,
     /*  670271 */     // GIR_Coverage, 30414,
     /*  670271 */     GIR_EraseRootFromParent_Done,
     /*  670272 */   // Label 10514: @670272
     /*  670272 */   GIM_Try, /*On fail goto*//*Label 10515*/ GIMT_Encode4(670322), // Rule ID 30415 //
     /*  670277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  670280 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  670285 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670298 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  670298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  670301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670306 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  670316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670320 */     GIR_RootConstrainSelectedInstOperands,
     /*  670321 */     // GIR_Coverage, 30415,
     /*  670321 */     GIR_EraseRootFromParent_Done,
     /*  670322 */   // Label 10515: @670322
     /*  670322 */   GIM_Try, /*On fail goto*//*Label 10516*/ GIMT_Encode4(670372), // Rule ID 30416 //
     /*  670327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  670330 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  670335 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670348 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  670348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  670351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670356 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  670366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670370 */     GIR_RootConstrainSelectedInstOperands,
     /*  670371 */     // GIR_Coverage, 30416,
     /*  670371 */     GIR_EraseRootFromParent_Done,
     /*  670372 */   // Label 10516: @670372
     /*  670372 */   GIM_Try, /*On fail goto*//*Label 10517*/ GIMT_Encode4(670422), // Rule ID 30417 //
     /*  670377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  670380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  670385 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670398 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  670398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  670401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670406 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  670416 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670420 */     GIR_RootConstrainSelectedInstOperands,
     /*  670421 */     // GIR_Coverage, 30417,
     /*  670421 */     GIR_EraseRootFromParent_Done,
     /*  670422 */   // Label 10517: @670422
     /*  670422 */   GIM_Try, /*On fail goto*//*Label 10518*/ GIMT_Encode4(670472), // Rule ID 30418 //
     /*  670427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  670430 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  670435 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670448 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  670448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
     /*  670451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670456 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  670466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670470 */     GIR_RootConstrainSelectedInstOperands,
     /*  670471 */     // GIR_Coverage, 30418,
     /*  670471 */     GIR_EraseRootFromParent_Done,
     /*  670472 */   // Label 10518: @670472
     /*  670472 */   GIM_Try, /*On fail goto*//*Label 10519*/ GIMT_Encode4(670526), // Rule ID 30401 //
     /*  670477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  670480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  670485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  670489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670500 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_i32>>  =>  (DS_MIN_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  670500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32),
     /*  670503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  670505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670510 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670524 */     GIR_RootConstrainSelectedInstOperands,
     /*  670525 */     // GIR_Coverage, 30401,
     /*  670525 */     GIR_EraseRootFromParent_Done,
     /*  670526 */   // Label 10519: @670526
     /*  670526 */   GIM_Try, /*On fail goto*//*Label 10520*/ GIMT_Encode4(670580), // Rule ID 30407 //
     /*  670531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  670534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  670539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  670543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670554 */     // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_i32>>  =>  (DS_MIN_RTN_I32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  670554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32_gfx9),
     /*  670557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  670559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670564 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  670574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670578 */     GIR_RootConstrainSelectedInstOperands,
     /*  670579 */     // GIR_Coverage, 30407,
     /*  670579 */     GIR_EraseRootFromParent_Done,
     /*  670580 */   // Label 10520: @670580
     /*  670580 */   GIM_Try, /*On fail goto*//*Label 10521*/ GIMT_Encode4(670634), // Rule ID 30413 //
     /*  670585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  670588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  670593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  670597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  670608 */     // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_i32>>  =>  (DS_MIN_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  670608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32),
     /*  670611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  670613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  670618 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  670620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  670625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  670628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670632 */     GIR_RootConstrainSelectedInstOperands,
     /*  670633 */     // GIR_Coverage, 30413,
     /*  670633 */     GIR_EraseRootFromParent_Done,
     /*  670634 */   // Label 10521: @670634
     /*  670634 */   GIM_Try, /*On fail goto*//*Label 10522*/ GIMT_Encode4(670693), // Rule ID 12993 //
     /*  670639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  670642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  670649 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  670662 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  670662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR),
     /*  670665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  670670 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  670672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  670677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  670682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  670687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670691 */     GIR_RootConstrainSelectedInstOperands,
     /*  670692 */     // GIR_Coverage, 12993,
     /*  670692 */     GIR_EraseRootFromParent_Done,
     /*  670693 */   // Label 10522: @670693
     /*  670693 */   GIM_Try, /*On fail goto*//*Label 10523*/ GIMT_Encode4(670752), // Rule ID 12994 //
     /*  670698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  670701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  670708 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  670721 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  670721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR),
     /*  670724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  670729 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  670731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  670736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  670741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  670746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670750 */     GIR_RootConstrainSelectedInstOperands,
     /*  670751 */     // GIR_Coverage, 12994,
     /*  670751 */     GIR_EraseRootFromParent_Done,
     /*  670752 */   // Label 10523: @670752
     /*  670752 */   GIM_Try, /*On fail goto*//*Label 10524*/ GIMT_Encode4(670811), // Rule ID 12995 //
     /*  670757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  670760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  670767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  670780 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  670780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR),
     /*  670783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  670788 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  670790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  670795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  670800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  670805 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670809 */     GIR_RootConstrainSelectedInstOperands,
     /*  670810 */     // GIR_Coverage, 12995,
     /*  670810 */     GIR_EraseRootFromParent_Done,
     /*  670811 */   // Label 10524: @670811
     /*  670811 */   GIM_Try, /*On fail goto*//*Label 10525*/ GIMT_Encode4(670870), // Rule ID 12996 //
     /*  670816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  670819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  670826 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  670839 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  670839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR),
     /*  670842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  670847 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  670849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  670854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  670859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  670864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670868 */     GIR_RootConstrainSelectedInstOperands,
     /*  670869 */     // GIR_Coverage, 12996,
     /*  670869 */     GIR_EraseRootFromParent_Done,
     /*  670870 */   // Label 10525: @670870
     /*  670870 */   GIM_Try, /*On fail goto*//*Label 10526*/ GIMT_Encode4(670929), // Rule ID 12997 //
     /*  670875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  670878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  670885 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  670887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  670898 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  670898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR),
     /*  670901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  670906 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  670908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  670913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  670918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  670923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670927 */     GIR_RootConstrainSelectedInstOperands,
     /*  670928 */     // GIR_Coverage, 12997,
     /*  670928 */     GIR_EraseRootFromParent_Done,
     /*  670929 */   // Label 10526: @670929
     /*  670929 */   GIM_Try, /*On fail goto*//*Label 10527*/ GIMT_Encode4(670992), // Rule ID 13003 //
     /*  670934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  670937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  670944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  670948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  670952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  670959 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  670959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN),
     /*  670962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  670964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  670969 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  670971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  670976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  670981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  670986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  670990 */     GIR_RootConstrainSelectedInstOperands,
     /*  670991 */     // GIR_Coverage, 13003,
     /*  670991 */     GIR_EraseRootFromParent_Done,
     /*  670992 */   // Label 10527: @670992
     /*  670992 */   GIM_Try, /*On fail goto*//*Label 10528*/ GIMT_Encode4(671044), // Rule ID 12988 //
     /*  670997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  671000 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671007 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671020 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN),
     /*  671023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671028 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  671038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671042 */     GIR_RootConstrainSelectedInstOperands,
     /*  671043 */     // GIR_Coverage, 12988,
     /*  671043 */     GIR_EraseRootFromParent_Done,
     /*  671044 */   // Label 10528: @671044
     /*  671044 */   GIM_Try, /*On fail goto*//*Label 10529*/ GIMT_Encode4(671096), // Rule ID 12989 //
     /*  671049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  671052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671059 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671072 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN),
     /*  671075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671080 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  671090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671094 */     GIR_RootConstrainSelectedInstOperands,
     /*  671095 */     // GIR_Coverage, 12989,
     /*  671095 */     GIR_EraseRootFromParent_Done,
     /*  671096 */   // Label 10529: @671096
     /*  671096 */   GIM_Try, /*On fail goto*//*Label 10530*/ GIMT_Encode4(671148), // Rule ID 12990 //
     /*  671101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  671104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671111 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671124 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN),
     /*  671127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671132 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  671142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671146 */     GIR_RootConstrainSelectedInstOperands,
     /*  671147 */     // GIR_Coverage, 12990,
     /*  671147 */     GIR_EraseRootFromParent_Done,
     /*  671148 */   // Label 10530: @671148
     /*  671148 */   GIM_Try, /*On fail goto*//*Label 10531*/ GIMT_Encode4(671200), // Rule ID 12991 //
     /*  671153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  671156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671163 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671176 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN),
     /*  671179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671184 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  671194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671198 */     GIR_RootConstrainSelectedInstOperands,
     /*  671199 */     // GIR_Coverage, 12991,
     /*  671199 */     GIR_EraseRootFromParent_Done,
     /*  671200 */   // Label 10531: @671200
     /*  671200 */   GIM_Try, /*On fail goto*//*Label 10532*/ GIMT_Encode4(671252), // Rule ID 12992 //
     /*  671205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  671208 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671215 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671228 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (GLOBAL_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN),
     /*  671231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671236 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  671246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671250 */     GIR_RootConstrainSelectedInstOperands,
     /*  671251 */     // GIR_Coverage, 12992,
     /*  671251 */     GIR_EraseRootFromParent_Done,
     /*  671252 */   // Label 10532: @671252
     /*  671252 */   GIM_Try, /*On fail goto*//*Label 10533*/ GIMT_Encode4(671308), // Rule ID 12998 //
     /*  671257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  671260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  671271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671282 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN),
     /*  671285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  671287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671292 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  671302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671306 */     GIR_RootConstrainSelectedInstOperands,
     /*  671307 */     // GIR_Coverage, 12998,
     /*  671307 */     GIR_EraseRootFromParent_Done,
     /*  671308 */   // Label 10533: @671308
     /*  671308 */   GIM_Try, /*On fail goto*//*Label 10534*/ GIMT_Encode4(671364), // Rule ID 12999 //
     /*  671313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  671316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  671327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671338 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN),
     /*  671341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  671343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671348 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  671358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671362 */     GIR_RootConstrainSelectedInstOperands,
     /*  671363 */     // GIR_Coverage, 12999,
     /*  671363 */     GIR_EraseRootFromParent_Done,
     /*  671364 */   // Label 10534: @671364
     /*  671364 */   GIM_Try, /*On fail goto*//*Label 10535*/ GIMT_Encode4(671420), // Rule ID 13000 //
     /*  671369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  671372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  671383 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671394 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN),
     /*  671397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  671399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671404 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  671414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671418 */     GIR_RootConstrainSelectedInstOperands,
     /*  671419 */     // GIR_Coverage, 13000,
     /*  671419 */     GIR_EraseRootFromParent_Done,
     /*  671420 */   // Label 10535: @671420
     /*  671420 */   GIM_Try, /*On fail goto*//*Label 10536*/ GIMT_Encode4(671476), // Rule ID 13001 //
     /*  671425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  671428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  671439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671443 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671450 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN),
     /*  671453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  671455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671460 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  671470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671474 */     GIR_RootConstrainSelectedInstOperands,
     /*  671475 */     // GIR_Coverage, 13001,
     /*  671475 */     GIR_EraseRootFromParent_Done,
     /*  671476 */   // Label 10536: @671476
     /*  671476 */   GIM_Try, /*On fail goto*//*Label 10537*/ GIMT_Encode4(671532), // Rule ID 13002 //
     /*  671481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  671484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  671495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  671506 */     // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  671506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN),
     /*  671509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  671511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  671516 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  671523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  671526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671530 */     GIR_RootConstrainSelectedInstOperands,
     /*  671531 */     // GIR_Coverage, 13002,
     /*  671531 */     GIR_EraseRootFromParent_Done,
     /*  671532 */   // Label 10537: @671532
     /*  671532 */   GIM_Try, /*On fail goto*//*Label 10538*/ GIMT_Encode4(671592), // Rule ID 10593 //
     /*  671537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  671540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671548 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671561 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671569 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671590 */     GIR_RootConstrainSelectedInstOperands,
     /*  671591 */     // GIR_Coverage, 10593,
     /*  671591 */     GIR_EraseRootFromParent_Done,
     /*  671592 */   // Label 10538: @671592
     /*  671592 */   GIM_Try, /*On fail goto*//*Label 10539*/ GIMT_Encode4(671652), // Rule ID 10594 //
     /*  671597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  671600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671608 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671621 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671629 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671650 */     GIR_RootConstrainSelectedInstOperands,
     /*  671651 */     // GIR_Coverage, 10594,
     /*  671651 */     GIR_EraseRootFromParent_Done,
     /*  671652 */   // Label 10539: @671652
     /*  671652 */   GIM_Try, /*On fail goto*//*Label 10540*/ GIMT_Encode4(671712), // Rule ID 10595 //
     /*  671657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  671660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671668 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671674 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671681 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671689 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671710 */     GIR_RootConstrainSelectedInstOperands,
     /*  671711 */     // GIR_Coverage, 10595,
     /*  671711 */     GIR_EraseRootFromParent_Done,
     /*  671712 */   // Label 10540: @671712
     /*  671712 */   GIM_Try, /*On fail goto*//*Label 10541*/ GIMT_Encode4(671772), // Rule ID 10596 //
     /*  671717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  671720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671728 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671741 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671749 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671770 */     GIR_RootConstrainSelectedInstOperands,
     /*  671771 */     // GIR_Coverage, 10596,
     /*  671771 */     GIR_EraseRootFromParent_Done,
     /*  671772 */   // Label 10541: @671772
     /*  671772 */   GIM_Try, /*On fail goto*//*Label 10542*/ GIMT_Encode4(671832), // Rule ID 10597 //
     /*  671777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  671780 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671788 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671790 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671801 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671809 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671830 */     GIR_RootConstrainSelectedInstOperands,
     /*  671831 */     // GIR_Coverage, 10597,
     /*  671831 */     GIR_EraseRootFromParent_Done,
     /*  671832 */   // Label 10542: @671832
     /*  671832 */   GIM_Try, /*On fail goto*//*Label 10543*/ GIMT_Encode4(671891), // Rule ID 11149 //
     /*  671837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  671840 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671847 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671860 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671868 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671889 */     GIR_RootConstrainSelectedInstOperands,
     /*  671890 */     // GIR_Coverage, 11149,
     /*  671890 */     GIR_EraseRootFromParent_Done,
     /*  671891 */   // Label 10543: @671891
     /*  671891 */   GIM_Try, /*On fail goto*//*Label 10544*/ GIMT_Encode4(671950), // Rule ID 11150 //
     /*  671896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  671899 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671906 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671919 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671927 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  671944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  671948 */     GIR_RootConstrainSelectedInstOperands,
     /*  671949 */     // GIR_Coverage, 11150,
     /*  671949 */     GIR_EraseRootFromParent_Done,
     /*  671950 */   // Label 10544: @671950
     /*  671950 */   GIM_Try, /*On fail goto*//*Label 10545*/ GIMT_Encode4(672009), // Rule ID 11151 //
     /*  671955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  671958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  671965 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  671967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  671971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  671978 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  671978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  671981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  671986 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  671988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  671993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  671998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  672003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672007 */     GIR_RootConstrainSelectedInstOperands,
     /*  672008 */     // GIR_Coverage, 11151,
     /*  672008 */     GIR_EraseRootFromParent_Done,
     /*  672009 */   // Label 10545: @672009
     /*  672009 */   GIM_Try, /*On fail goto*//*Label 10546*/ GIMT_Encode4(672068), // Rule ID 11152 //
     /*  672014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  672017 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672024 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672026 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672030 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  672037 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  672037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  672040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  672045 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  672052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  672057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  672062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672066 */     GIR_RootConstrainSelectedInstOperands,
     /*  672067 */     // GIR_Coverage, 11152,
     /*  672067 */     GIR_EraseRootFromParent_Done,
     /*  672068 */   // Label 10546: @672068
     /*  672068 */   GIM_Try, /*On fail goto*//*Label 10547*/ GIMT_Encode4(672127), // Rule ID 11153 //
     /*  672073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  672076 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672083 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672085 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  672096 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  672096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR),
     /*  672099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  672104 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  672111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  672116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  672121 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672125 */     GIR_RootConstrainSelectedInstOperands,
     /*  672126 */     // GIR_Coverage, 11153,
     /*  672126 */     GIR_EraseRootFromParent_Done,
     /*  672127 */   // Label 10547: @672127
     /*  672127 */   GIM_Try, /*On fail goto*//*Label 10548*/ GIMT_Encode4(672191), // Rule ID 10587 //
     /*  672132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  672135 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  672147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  672158 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  672158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR_RTN),
     /*  672161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  672163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  672168 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  672175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  672180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  672185 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672189 */     GIR_RootConstrainSelectedInstOperands,
     /*  672190 */     // GIR_Coverage, 10587,
     /*  672190 */     GIR_EraseRootFromParent_Done,
     /*  672191 */   // Label 10548: @672191
     /*  672191 */   GIM_Try, /*On fail goto*//*Label 10549*/ GIMT_Encode4(672254), // Rule ID 11143 //
     /*  672196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  672199 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  672210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  672221 */     // (atomic_load_min:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (FLAT_ATOMIC_SMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  672221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_SADDR_RTN),
     /*  672224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  672226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  672231 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  672238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  672243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  672248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672252 */     GIR_RootConstrainSelectedInstOperands,
     /*  672253 */     // GIR_Coverage, 11143,
     /*  672253 */     GIR_EraseRootFromParent_Done,
     /*  672254 */   // Label 10549: @672254
     /*  672254 */   GIM_Try, /*On fail goto*//*Label 10550*/ GIMT_Encode4(672307), // Rule ID 10588 //
     /*  672259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  672262 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672270 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672283 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672291 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672305 */     GIR_RootConstrainSelectedInstOperands,
     /*  672306 */     // GIR_Coverage, 10588,
     /*  672306 */     GIR_EraseRootFromParent_Done,
     /*  672307 */   // Label 10550: @672307
     /*  672307 */   GIM_Try, /*On fail goto*//*Label 10551*/ GIMT_Encode4(672360), // Rule ID 10589 //
     /*  672312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  672315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672323 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672336 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672344 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672358 */     GIR_RootConstrainSelectedInstOperands,
     /*  672359 */     // GIR_Coverage, 10589,
     /*  672359 */     GIR_EraseRootFromParent_Done,
     /*  672360 */   // Label 10551: @672360
     /*  672360 */   GIM_Try, /*On fail goto*//*Label 10552*/ GIMT_Encode4(672413), // Rule ID 10590 //
     /*  672365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  672368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672376 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672389 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672397 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672407 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672411 */     GIR_RootConstrainSelectedInstOperands,
     /*  672412 */     // GIR_Coverage, 10590,
     /*  672412 */     GIR_EraseRootFromParent_Done,
     /*  672413 */   // Label 10552: @672413
     /*  672413 */   GIM_Try, /*On fail goto*//*Label 10553*/ GIMT_Encode4(672466), // Rule ID 10591 //
     /*  672418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  672421 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672429 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672442 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672450 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672464 */     GIR_RootConstrainSelectedInstOperands,
     /*  672465 */     // GIR_Coverage, 10591,
     /*  672465 */     GIR_EraseRootFromParent_Done,
     /*  672466 */   // Label 10553: @672466
     /*  672466 */   GIM_Try, /*On fail goto*//*Label 10554*/ GIMT_Encode4(672519), // Rule ID 10592 //
     /*  672471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  672474 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672482 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672495 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672503 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672517 */     GIR_RootConstrainSelectedInstOperands,
     /*  672518 */     // GIR_Coverage, 10592,
     /*  672518 */     GIR_EraseRootFromParent_Done,
     /*  672519 */   // Label 10554: @672519
     /*  672519 */   GIM_Try, /*On fail goto*//*Label 10555*/ GIMT_Encode4(672571), // Rule ID 11144 //
     /*  672524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  672527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672534 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672547 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672555 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672569 */     GIR_RootConstrainSelectedInstOperands,
     /*  672570 */     // GIR_Coverage, 11144,
     /*  672570 */     GIR_EraseRootFromParent_Done,
     /*  672571 */   // Label 10555: @672571
     /*  672571 */   GIM_Try, /*On fail goto*//*Label 10556*/ GIMT_Encode4(672623), // Rule ID 11145 //
     /*  672576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  672579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672586 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672599 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672607 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672621 */     GIR_RootConstrainSelectedInstOperands,
     /*  672622 */     // GIR_Coverage, 11145,
     /*  672622 */     GIR_EraseRootFromParent_Done,
     /*  672623 */   // Label 10556: @672623
     /*  672623 */   GIM_Try, /*On fail goto*//*Label 10557*/ GIMT_Encode4(672675), // Rule ID 11146 //
     /*  672628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  672631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672638 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672640 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672651 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672659 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672669 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672673 */     GIR_RootConstrainSelectedInstOperands,
     /*  672674 */     // GIR_Coverage, 11146,
     /*  672674 */     GIR_EraseRootFromParent_Done,
     /*  672675 */   // Label 10557: @672675
     /*  672675 */   GIM_Try, /*On fail goto*//*Label 10558*/ GIMT_Encode4(672727), // Rule ID 11147 //
     /*  672680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  672683 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672690 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672692 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672703 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672711 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672725 */     GIR_RootConstrainSelectedInstOperands,
     /*  672726 */     // GIR_Coverage, 11147,
     /*  672726 */     GIR_EraseRootFromParent_Done,
     /*  672727 */   // Label 10558: @672727
     /*  672727 */   GIM_Try, /*On fail goto*//*Label 10559*/ GIMT_Encode4(672779), // Rule ID 11148 //
     /*  672732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  672735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672742 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  672744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672755 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>>  =>  (FLAT_ATOMIC_SMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
     /*  672758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672763 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  672773 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672777 */     GIR_RootConstrainSelectedInstOperands,
     /*  672778 */     // GIR_Coverage, 11148,
     /*  672778 */     GIR_EraseRootFromParent_Done,
     /*  672779 */   // Label 10559: @672779
     /*  672779 */   GIM_Try, /*On fail goto*//*Label 10560*/ GIMT_Encode4(672836), // Rule ID 10582 //
     /*  672784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  672787 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  672799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672810 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  672813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  672815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672820 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  672830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672834 */     GIR_RootConstrainSelectedInstOperands,
     /*  672835 */     // GIR_Coverage, 10582,
     /*  672835 */     GIR_EraseRootFromParent_Done,
     /*  672836 */   // Label 10560: @672836
     /*  672836 */   GIM_Try, /*On fail goto*//*Label 10561*/ GIMT_Encode4(672893), // Rule ID 10583 //
     /*  672841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  672844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  672856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672867 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  672870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  672872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672877 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  672887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672891 */     GIR_RootConstrainSelectedInstOperands,
     /*  672892 */     // GIR_Coverage, 10583,
     /*  672892 */     GIR_EraseRootFromParent_Done,
     /*  672893 */   // Label 10561: @672893
     /*  672893 */   GIM_Try, /*On fail goto*//*Label 10562*/ GIMT_Encode4(672950), // Rule ID 10584 //
     /*  672898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  672901 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  672913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672924 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  672927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  672929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672934 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  672944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  672948 */     GIR_RootConstrainSelectedInstOperands,
     /*  672949 */     // GIR_Coverage, 10584,
     /*  672949 */     GIR_EraseRootFromParent_Done,
     /*  672950 */   // Label 10562: @672950
     /*  672950 */   GIM_Try, /*On fail goto*//*Label 10563*/ GIMT_Encode4(673007), // Rule ID 10585 //
     /*  672955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  672958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  672966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  672970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  672974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  672981 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  672981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  672984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  672986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  672991 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  672993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  672998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673005 */     GIR_RootConstrainSelectedInstOperands,
     /*  673006 */     // GIR_Coverage, 10585,
     /*  673006 */     GIR_EraseRootFromParent_Done,
     /*  673007 */   // Label 10563: @673007
     /*  673007 */   GIM_Try, /*On fail goto*//*Label 10564*/ GIMT_Encode4(673064), // Rule ID 10586 //
     /*  673012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  673015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  673027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  673038 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  673038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  673041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  673043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  673048 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  673050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  673055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673062 */     GIR_RootConstrainSelectedInstOperands,
     /*  673063 */     // GIR_Coverage, 10586,
     /*  673063 */     GIR_EraseRootFromParent_Done,
     /*  673064 */   // Label 10564: @673064
     /*  673064 */   GIM_Try, /*On fail goto*//*Label 10565*/ GIMT_Encode4(673120), // Rule ID 11138 //
     /*  673069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  673072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  673083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  673094 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  673094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  673097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  673099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  673104 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  673106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  673111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673118 */     GIR_RootConstrainSelectedInstOperands,
     /*  673119 */     // GIR_Coverage, 11138,
     /*  673119 */     GIR_EraseRootFromParent_Done,
     /*  673120 */   // Label 10565: @673120
     /*  673120 */   GIM_Try, /*On fail goto*//*Label 10566*/ GIMT_Encode4(673176), // Rule ID 11139 //
     /*  673125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  673128 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  673139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  673150 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  673150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  673153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  673155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  673160 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  673162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  673167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673174 */     GIR_RootConstrainSelectedInstOperands,
     /*  673175 */     // GIR_Coverage, 11139,
     /*  673175 */     GIR_EraseRootFromParent_Done,
     /*  673176 */   // Label 10566: @673176
     /*  673176 */   GIM_Try, /*On fail goto*//*Label 10567*/ GIMT_Encode4(673232), // Rule ID 11140 //
     /*  673181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  673184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  673195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  673206 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  673206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  673209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  673211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  673216 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  673218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  673223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673230 */     GIR_RootConstrainSelectedInstOperands,
     /*  673231 */     // GIR_Coverage, 11140,
     /*  673231 */     GIR_EraseRootFromParent_Done,
     /*  673232 */   // Label 10567: @673232
     /*  673232 */   GIM_Try, /*On fail goto*//*Label 10568*/ GIMT_Encode4(673288), // Rule ID 11141 //
     /*  673237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  673240 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  673251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  673262 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  673262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  673265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  673267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  673272 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  673274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  673279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673286 */     GIR_RootConstrainSelectedInstOperands,
     /*  673287 */     // GIR_Coverage, 11141,
     /*  673287 */     GIR_EraseRootFromParent_Done,
     /*  673288 */   // Label 10568: @673288
     /*  673288 */   GIM_Try, /*On fail goto*//*Label 10569*/ GIMT_Encode4(673344), // Rule ID 11142 //
     /*  673293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  673296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  673307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  673318 */     // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  673318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
     /*  673321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  673323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  673328 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  673330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  673335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  673338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673342 */     GIR_RootConstrainSelectedInstOperands,
     /*  673343 */     // GIR_Coverage, 11142,
     /*  673343 */     GIR_EraseRootFromParent_Done,
     /*  673344 */   // Label 10569: @673344
     /*  673344 */   GIM_Reject,
     /*  673345 */ // Label 10463: @673345
     /*  673345 */ GIM_Reject,
     /*  673346 */ // Label 10461: @673346
     /*  673346 */ GIM_Try, /*On fail goto*//*Label 10570*/ GIMT_Encode4(680845),
     /*  673351 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  673354 */   GIM_Try, /*On fail goto*//*Label 10571*/ GIMT_Encode4(673416), // Rule ID 21338 //
     /*  673359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  673362 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673369 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673382 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64),
     /*  673385 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673414 */     GIR_RootConstrainSelectedInstOperands,
     /*  673415 */     // GIR_Coverage, 21338,
     /*  673415 */     GIR_EraseRootFromParent_Done,
     /*  673416 */   // Label 10571: @673416
     /*  673416 */   GIM_Try, /*On fail goto*//*Label 10572*/ GIMT_Encode4(673478), // Rule ID 21339 //
     /*  673421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  673424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673431 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673444 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64),
     /*  673447 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673476 */     GIR_RootConstrainSelectedInstOperands,
     /*  673477 */     // GIR_Coverage, 21339,
     /*  673477 */     GIR_EraseRootFromParent_Done,
     /*  673478 */   // Label 10572: @673478
     /*  673478 */   GIM_Try, /*On fail goto*//*Label 10573*/ GIMT_Encode4(673540), // Rule ID 21340 //
     /*  673483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  673486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673493 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673506 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64),
     /*  673509 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673538 */     GIR_RootConstrainSelectedInstOperands,
     /*  673539 */     // GIR_Coverage, 21340,
     /*  673539 */     GIR_EraseRootFromParent_Done,
     /*  673540 */   // Label 10573: @673540
     /*  673540 */   GIM_Try, /*On fail goto*//*Label 10574*/ GIMT_Encode4(673602), // Rule ID 21341 //
     /*  673545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  673548 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673555 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673568 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64),
     /*  673571 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673600 */     GIR_RootConstrainSelectedInstOperands,
     /*  673601 */     // GIR_Coverage, 21341,
     /*  673601 */     GIR_EraseRootFromParent_Done,
     /*  673602 */   // Label 10574: @673602
     /*  673602 */   GIM_Try, /*On fail goto*//*Label 10575*/ GIMT_Encode4(673664), // Rule ID 21342 //
     /*  673607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  673610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673617 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673630 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64),
     /*  673633 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673662 */     GIR_RootConstrainSelectedInstOperands,
     /*  673663 */     // GIR_Coverage, 21342,
     /*  673663 */     GIR_EraseRootFromParent_Done,
     /*  673664 */   // Label 10575: @673664
     /*  673664 */   GIM_Try, /*On fail goto*//*Label 10576*/ GIMT_Encode4(673726), // Rule ID 21358 //
     /*  673669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  673672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673679 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673692 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64),
     /*  673695 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673724 */     GIR_RootConstrainSelectedInstOperands,
     /*  673725 */     // GIR_Coverage, 21358,
     /*  673725 */     GIR_EraseRootFromParent_Done,
     /*  673726 */   // Label 10576: @673726
     /*  673726 */   GIM_Try, /*On fail goto*//*Label 10577*/ GIMT_Encode4(673788), // Rule ID 21359 //
     /*  673731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  673734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673741 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673754 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64),
     /*  673757 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673786 */     GIR_RootConstrainSelectedInstOperands,
     /*  673787 */     // GIR_Coverage, 21359,
     /*  673787 */     GIR_EraseRootFromParent_Done,
     /*  673788 */   // Label 10577: @673788
     /*  673788 */   GIM_Try, /*On fail goto*//*Label 10578*/ GIMT_Encode4(673850), // Rule ID 21360 //
     /*  673793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  673796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673803 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673816 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64),
     /*  673819 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673848 */     GIR_RootConstrainSelectedInstOperands,
     /*  673849 */     // GIR_Coverage, 21360,
     /*  673849 */     GIR_EraseRootFromParent_Done,
     /*  673850 */   // Label 10578: @673850
     /*  673850 */   GIM_Try, /*On fail goto*//*Label 10579*/ GIMT_Encode4(673912), // Rule ID 21361 //
     /*  673855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  673858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673865 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673878 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64),
     /*  673881 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673910 */     GIR_RootConstrainSelectedInstOperands,
     /*  673911 */     // GIR_Coverage, 21361,
     /*  673911 */     GIR_EraseRootFromParent_Done,
     /*  673912 */   // Label 10579: @673912
     /*  673912 */   GIM_Try, /*On fail goto*//*Label 10580*/ GIMT_Encode4(673974), // Rule ID 21362 //
     /*  673917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  673920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673927 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  673929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  673940 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  673940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64),
     /*  673943 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  673945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  673950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  673955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  673960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  673965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  673968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  673972 */     GIR_RootConstrainSelectedInstOperands,
     /*  673973 */     // GIR_Coverage, 21362,
     /*  673973 */     GIR_EraseRootFromParent_Done,
     /*  673974 */   // Label 10580: @673974
     /*  673974 */   GIM_Try, /*On fail goto*//*Label 10581*/ GIMT_Encode4(674040), // Rule ID 21328 //
     /*  673979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  673982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  673989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  673993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  673997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674004 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN),
     /*  674007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674009 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674038 */     GIR_RootConstrainSelectedInstOperands,
     /*  674039 */     // GIR_Coverage, 21328,
     /*  674039 */     GIR_EraseRootFromParent_Done,
     /*  674040 */   // Label 10581: @674040
     /*  674040 */   GIM_Try, /*On fail goto*//*Label 10582*/ GIMT_Encode4(674106), // Rule ID 21329 //
     /*  674045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  674048 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674059 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674063 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674070 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN),
     /*  674073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674075 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674104 */     GIR_RootConstrainSelectedInstOperands,
     /*  674105 */     // GIR_Coverage, 21329,
     /*  674105 */     GIR_EraseRootFromParent_Done,
     /*  674106 */   // Label 10582: @674106
     /*  674106 */   GIM_Try, /*On fail goto*//*Label 10583*/ GIMT_Encode4(674172), // Rule ID 21330 //
     /*  674111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  674114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674136 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN),
     /*  674139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674141 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674170 */     GIR_RootConstrainSelectedInstOperands,
     /*  674171 */     // GIR_Coverage, 21330,
     /*  674171 */     GIR_EraseRootFromParent_Done,
     /*  674172 */   // Label 10583: @674172
     /*  674172 */   GIM_Try, /*On fail goto*//*Label 10584*/ GIMT_Encode4(674238), // Rule ID 21331 //
     /*  674177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  674180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674202 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN),
     /*  674205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674207 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674236 */     GIR_RootConstrainSelectedInstOperands,
     /*  674237 */     // GIR_Coverage, 21331,
     /*  674237 */     GIR_EraseRootFromParent_Done,
     /*  674238 */   // Label 10584: @674238
     /*  674238 */   GIM_Try, /*On fail goto*//*Label 10585*/ GIMT_Encode4(674304), // Rule ID 21332 //
     /*  674243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  674246 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674268 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN),
     /*  674271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674273 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674302 */     GIR_RootConstrainSelectedInstOperands,
     /*  674303 */     // GIR_Coverage, 21332,
     /*  674303 */     GIR_EraseRootFromParent_Done,
     /*  674304 */   // Label 10585: @674304
     /*  674304 */   GIM_Try, /*On fail goto*//*Label 10586*/ GIMT_Encode4(674370), // Rule ID 21348 //
     /*  674309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  674312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674334 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN),
     /*  674337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674339 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674368 */     GIR_RootConstrainSelectedInstOperands,
     /*  674369 */     // GIR_Coverage, 21348,
     /*  674369 */     GIR_EraseRootFromParent_Done,
     /*  674370 */   // Label 10586: @674370
     /*  674370 */   GIM_Try, /*On fail goto*//*Label 10587*/ GIMT_Encode4(674436), // Rule ID 21349 //
     /*  674375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  674378 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674400 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN),
     /*  674403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674405 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674434 */     GIR_RootConstrainSelectedInstOperands,
     /*  674435 */     // GIR_Coverage, 21349,
     /*  674435 */     GIR_EraseRootFromParent_Done,
     /*  674436 */   // Label 10587: @674436
     /*  674436 */   GIM_Try, /*On fail goto*//*Label 10588*/ GIMT_Encode4(674502), // Rule ID 21350 //
     /*  674441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  674444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674466 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN),
     /*  674469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674471 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674500 */     GIR_RootConstrainSelectedInstOperands,
     /*  674501 */     // GIR_Coverage, 21350,
     /*  674501 */     GIR_EraseRootFromParent_Done,
     /*  674502 */   // Label 10588: @674502
     /*  674502 */   GIM_Try, /*On fail goto*//*Label 10589*/ GIMT_Encode4(674568), // Rule ID 21351 //
     /*  674507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  674510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674532 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN),
     /*  674535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674537 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674566 */     GIR_RootConstrainSelectedInstOperands,
     /*  674567 */     // GIR_Coverage, 21351,
     /*  674567 */     GIR_EraseRootFromParent_Done,
     /*  674568 */   // Label 10589: @674568
     /*  674568 */   GIM_Try, /*On fail goto*//*Label 10590*/ GIMT_Encode4(674634), // Rule ID 21352 //
     /*  674573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  674576 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  674587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  674598 */     // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN),
     /*  674601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  674603 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  674610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  674620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  674625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  674628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674632 */     GIR_RootConstrainSelectedInstOperands,
     /*  674633 */     // GIR_Coverage, 21352,
     /*  674633 */     GIR_EraseRootFromParent_Done,
     /*  674634 */   // Label 10590: @674634
     /*  674634 */   GIM_Try, /*On fail goto*//*Label 10591*/ GIMT_Encode4(674691), // Rule ID 21333 //
     /*  674639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  674642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674649 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  674662 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
     /*  674665 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  674677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  674682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  674685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674689 */     GIR_RootConstrainSelectedInstOperands,
     /*  674690 */     // GIR_Coverage, 21333,
     /*  674690 */     GIR_EraseRootFromParent_Done,
     /*  674691 */   // Label 10591: @674691
     /*  674691 */   GIM_Try, /*On fail goto*//*Label 10592*/ GIMT_Encode4(674748), // Rule ID 21334 //
     /*  674696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  674699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674706 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674708 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  674719 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
     /*  674722 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  674734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  674739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  674742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674746 */     GIR_RootConstrainSelectedInstOperands,
     /*  674747 */     // GIR_Coverage, 21334,
     /*  674747 */     GIR_EraseRootFromParent_Done,
     /*  674748 */   // Label 10592: @674748
     /*  674748 */   GIM_Try, /*On fail goto*//*Label 10593*/ GIMT_Encode4(674805), // Rule ID 21335 //
     /*  674753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  674756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674763 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  674776 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
     /*  674779 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  674791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  674796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  674799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674803 */     GIR_RootConstrainSelectedInstOperands,
     /*  674804 */     // GIR_Coverage, 21335,
     /*  674804 */     GIR_EraseRootFromParent_Done,
     /*  674805 */   // Label 10593: @674805
     /*  674805 */   GIM_Try, /*On fail goto*//*Label 10594*/ GIMT_Encode4(674862), // Rule ID 21336 //
     /*  674810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  674813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674820 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  674833 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
     /*  674836 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  674848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  674853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  674856 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674860 */     GIR_RootConstrainSelectedInstOperands,
     /*  674861 */     // GIR_Coverage, 21336,
     /*  674861 */     GIR_EraseRootFromParent_Done,
     /*  674862 */   // Label 10594: @674862
     /*  674862 */   GIM_Try, /*On fail goto*//*Label 10595*/ GIMT_Encode4(674919), // Rule ID 21337 //
     /*  674867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  674870 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674877 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674883 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  674890 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
     /*  674893 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  674905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  674910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  674913 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674917 */     GIR_RootConstrainSelectedInstOperands,
     /*  674918 */     // GIR_Coverage, 21337,
     /*  674918 */     GIR_EraseRootFromParent_Done,
     /*  674919 */   // Label 10595: @674919
     /*  674919 */   GIM_Try, /*On fail goto*//*Label 10596*/ GIMT_Encode4(674976), // Rule ID 21353 //
     /*  674924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  674927 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674934 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  674947 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  674947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
     /*  674950 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  674952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  674957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  674962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  674967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  674970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  674974 */     GIR_RootConstrainSelectedInstOperands,
     /*  674975 */     // GIR_Coverage, 21353,
     /*  674975 */     GIR_EraseRootFromParent_Done,
     /*  674976 */   // Label 10596: @674976
     /*  674976 */   GIM_Try, /*On fail goto*//*Label 10597*/ GIMT_Encode4(675033), // Rule ID 21354 //
     /*  674981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  674984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  674991 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  674993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  674997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675004 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
     /*  675007 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675031 */     GIR_RootConstrainSelectedInstOperands,
     /*  675032 */     // GIR_Coverage, 21354,
     /*  675032 */     GIR_EraseRootFromParent_Done,
     /*  675033 */   // Label 10597: @675033
     /*  675033 */   GIM_Try, /*On fail goto*//*Label 10598*/ GIMT_Encode4(675090), // Rule ID 21355 //
     /*  675038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  675041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675048 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675061 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
     /*  675064 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675088 */     GIR_RootConstrainSelectedInstOperands,
     /*  675089 */     // GIR_Coverage, 21355,
     /*  675089 */     GIR_EraseRootFromParent_Done,
     /*  675090 */   // Label 10598: @675090
     /*  675090 */   GIM_Try, /*On fail goto*//*Label 10599*/ GIMT_Encode4(675147), // Rule ID 21356 //
     /*  675095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  675098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675105 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675118 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
     /*  675121 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675145 */     GIR_RootConstrainSelectedInstOperands,
     /*  675146 */     // GIR_Coverage, 21356,
     /*  675146 */     GIR_EraseRootFromParent_Done,
     /*  675147 */   // Label 10599: @675147
     /*  675147 */   GIM_Try, /*On fail goto*//*Label 10600*/ GIMT_Encode4(675204), // Rule ID 21357 //
     /*  675152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  675155 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675162 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675175 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
     /*  675178 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675202 */     GIR_RootConstrainSelectedInstOperands,
     /*  675203 */     // GIR_Coverage, 21357,
     /*  675203 */     GIR_EraseRootFromParent_Done,
     /*  675204 */   // Label 10600: @675204
     /*  675204 */   GIM_Try, /*On fail goto*//*Label 10601*/ GIMT_Encode4(675265), // Rule ID 21323 //
     /*  675209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  675212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675234 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
     /*  675237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675239 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675263 */     GIR_RootConstrainSelectedInstOperands,
     /*  675264 */     // GIR_Coverage, 21323,
     /*  675264 */     GIR_EraseRootFromParent_Done,
     /*  675265 */   // Label 10601: @675265
     /*  675265 */   GIM_Try, /*On fail goto*//*Label 10602*/ GIMT_Encode4(675326), // Rule ID 21324 //
     /*  675270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  675273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675284 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675288 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675295 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
     /*  675298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675300 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675324 */     GIR_RootConstrainSelectedInstOperands,
     /*  675325 */     // GIR_Coverage, 21324,
     /*  675325 */     GIR_EraseRootFromParent_Done,
     /*  675326 */   // Label 10602: @675326
     /*  675326 */   GIM_Try, /*On fail goto*//*Label 10603*/ GIMT_Encode4(675387), // Rule ID 21325 //
     /*  675331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  675334 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675356 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
     /*  675359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675361 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675381 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675385 */     GIR_RootConstrainSelectedInstOperands,
     /*  675386 */     // GIR_Coverage, 21325,
     /*  675386 */     GIR_EraseRootFromParent_Done,
     /*  675387 */   // Label 10603: @675387
     /*  675387 */   GIM_Try, /*On fail goto*//*Label 10604*/ GIMT_Encode4(675448), // Rule ID 21326 //
     /*  675392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  675395 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675417 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
     /*  675420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675422 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675446 */     GIR_RootConstrainSelectedInstOperands,
     /*  675447 */     // GIR_Coverage, 21326,
     /*  675447 */     GIR_EraseRootFromParent_Done,
     /*  675448 */   // Label 10604: @675448
     /*  675448 */   GIM_Try, /*On fail goto*//*Label 10605*/ GIMT_Encode4(675509), // Rule ID 21327 //
     /*  675453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  675456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675478 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
     /*  675481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675483 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675507 */     GIR_RootConstrainSelectedInstOperands,
     /*  675508 */     // GIR_Coverage, 21327,
     /*  675508 */     GIR_EraseRootFromParent_Done,
     /*  675509 */   // Label 10605: @675509
     /*  675509 */   GIM_Try, /*On fail goto*//*Label 10606*/ GIMT_Encode4(675570), // Rule ID 21343 //
     /*  675514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  675517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675539 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
     /*  675542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675544 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675564 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675568 */     GIR_RootConstrainSelectedInstOperands,
     /*  675569 */     // GIR_Coverage, 21343,
     /*  675569 */     GIR_EraseRootFromParent_Done,
     /*  675570 */   // Label 10606: @675570
     /*  675570 */   GIM_Try, /*On fail goto*//*Label 10607*/ GIMT_Encode4(675631), // Rule ID 21344 //
     /*  675575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  675578 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675600 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
     /*  675603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675605 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675629 */     GIR_RootConstrainSelectedInstOperands,
     /*  675630 */     // GIR_Coverage, 21344,
     /*  675630 */     GIR_EraseRootFromParent_Done,
     /*  675631 */   // Label 10607: @675631
     /*  675631 */   GIM_Try, /*On fail goto*//*Label 10608*/ GIMT_Encode4(675692), // Rule ID 21345 //
     /*  675636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  675639 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675661 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
     /*  675664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675666 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675690 */     GIR_RootConstrainSelectedInstOperands,
     /*  675691 */     // GIR_Coverage, 21345,
     /*  675691 */     GIR_EraseRootFromParent_Done,
     /*  675692 */   // Label 10608: @675692
     /*  675692 */   GIM_Try, /*On fail goto*//*Label 10609*/ GIMT_Encode4(675753), // Rule ID 21346 //
     /*  675697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  675700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675722 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
     /*  675725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675727 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675744 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675751 */     GIR_RootConstrainSelectedInstOperands,
     /*  675752 */     // GIR_Coverage, 21346,
     /*  675752 */     GIR_EraseRootFromParent_Done,
     /*  675753 */   // Label 10609: @675753
     /*  675753 */   GIM_Try, /*On fail goto*//*Label 10610*/ GIMT_Encode4(675814), // Rule ID 21347 //
     /*  675758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  675761 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  675768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  675772 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  675783 */     // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  675783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
     /*  675786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  675788 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  675790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  675795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  675800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  675805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  675808 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675812 */     GIR_RootConstrainSelectedInstOperands,
     /*  675813 */     // GIR_Coverage, 21347,
     /*  675813 */     GIR_EraseRootFromParent_Done,
     /*  675814 */   // Label 10610: @675814
     /*  675814 */   GIM_Try, /*On fail goto*//*Label 10611*/ GIMT_Encode4(675864), // Rule ID 30775 //
     /*  675819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  675822 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  675827 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  675840 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  675840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  675843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  675848 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  675850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  675855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675862 */     GIR_RootConstrainSelectedInstOperands,
     /*  675863 */     // GIR_Coverage, 30775,
     /*  675863 */     GIR_EraseRootFromParent_Done,
     /*  675864 */   // Label 10611: @675864
     /*  675864 */   GIM_Try, /*On fail goto*//*Label 10612*/ GIMT_Encode4(675914), // Rule ID 30776 //
     /*  675869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  675872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  675877 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675883 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  675890 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  675890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  675893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  675898 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  675900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  675905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675912 */     GIR_RootConstrainSelectedInstOperands,
     /*  675913 */     // GIR_Coverage, 30776,
     /*  675913 */     GIR_EraseRootFromParent_Done,
     /*  675914 */   // Label 10612: @675914
     /*  675914 */   GIM_Try, /*On fail goto*//*Label 10613*/ GIMT_Encode4(675964), // Rule ID 30777 //
     /*  675919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  675922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  675927 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675929 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  675940 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  675940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  675943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  675948 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  675950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  675955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  675958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  675962 */     GIR_RootConstrainSelectedInstOperands,
     /*  675963 */     // GIR_Coverage, 30777,
     /*  675963 */     GIR_EraseRootFromParent_Done,
     /*  675964 */   // Label 10613: @675964
     /*  675964 */   GIM_Try, /*On fail goto*//*Label 10614*/ GIMT_Encode4(676014), // Rule ID 30778 //
     /*  675969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  675972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  675977 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  675979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  675983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  675990 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  675990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  675993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  675998 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676012 */     GIR_RootConstrainSelectedInstOperands,
     /*  676013 */     // GIR_Coverage, 30778,
     /*  676013 */     GIR_EraseRootFromParent_Done,
     /*  676014 */   // Label 10614: @676014
     /*  676014 */   GIM_Try, /*On fail goto*//*Label 10615*/ GIMT_Encode4(676064), // Rule ID 30779 //
     /*  676019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  676022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676027 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676040 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  676043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676048 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676062 */     GIR_RootConstrainSelectedInstOperands,
     /*  676063 */     // GIR_Coverage, 30779,
     /*  676063 */     GIR_EraseRootFromParent_Done,
     /*  676064 */   // Label 10615: @676064
     /*  676064 */   GIM_Try, /*On fail goto*//*Label 10616*/ GIMT_Encode4(676114), // Rule ID 30785 //
     /*  676069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  676072 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676077 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676090 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_i64>>  =>  (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9),
     /*  676093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676098 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676112 */     GIR_RootConstrainSelectedInstOperands,
     /*  676113 */     // GIR_Coverage, 30785,
     /*  676113 */     GIR_EraseRootFromParent_Done,
     /*  676114 */   // Label 10616: @676114
     /*  676114 */   GIM_Try, /*On fail goto*//*Label 10617*/ GIMT_Encode4(676164), // Rule ID 30786 //
     /*  676119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  676122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676127 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676133 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676140 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_i64>>  =>  (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9),
     /*  676143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676148 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676162 */     GIR_RootConstrainSelectedInstOperands,
     /*  676163 */     // GIR_Coverage, 30786,
     /*  676163 */     GIR_EraseRootFromParent_Done,
     /*  676164 */   // Label 10617: @676164
     /*  676164 */   GIM_Try, /*On fail goto*//*Label 10618*/ GIMT_Encode4(676214), // Rule ID 30787 //
     /*  676169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  676172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676177 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676190 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_i64>>  =>  (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9),
     /*  676193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676198 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676212 */     GIR_RootConstrainSelectedInstOperands,
     /*  676213 */     // GIR_Coverage, 30787,
     /*  676213 */     GIR_EraseRootFromParent_Done,
     /*  676214 */   // Label 10618: @676214
     /*  676214 */   GIM_Try, /*On fail goto*//*Label 10619*/ GIMT_Encode4(676264), // Rule ID 30788 //
     /*  676219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  676222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676227 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676240 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_i64>>  =>  (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9),
     /*  676243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676248 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676262 */     GIR_RootConstrainSelectedInstOperands,
     /*  676263 */     // GIR_Coverage, 30788,
     /*  676263 */     GIR_EraseRootFromParent_Done,
     /*  676264 */   // Label 10619: @676264
     /*  676264 */   GIM_Try, /*On fail goto*//*Label 10620*/ GIMT_Encode4(676314), // Rule ID 30789 //
     /*  676269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  676272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676277 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676279 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676290 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_i64>>  =>  (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9),
     /*  676293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676298 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676312 */     GIR_RootConstrainSelectedInstOperands,
     /*  676313 */     // GIR_Coverage, 30789,
     /*  676313 */     GIR_EraseRootFromParent_Done,
     /*  676314 */   // Label 10620: @676314
     /*  676314 */   GIM_Try, /*On fail goto*//*Label 10621*/ GIMT_Encode4(676364), // Rule ID 30795 //
     /*  676319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  676322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  676327 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676340 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  676340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  676343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676348 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  676358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676362 */     GIR_RootConstrainSelectedInstOperands,
     /*  676363 */     // GIR_Coverage, 30795,
     /*  676363 */     GIR_EraseRootFromParent_Done,
     /*  676364 */   // Label 10621: @676364
     /*  676364 */   GIM_Try, /*On fail goto*//*Label 10622*/ GIMT_Encode4(676414), // Rule ID 30796 //
     /*  676369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  676372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  676377 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676390 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  676390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  676393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676398 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  676408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676412 */     GIR_RootConstrainSelectedInstOperands,
     /*  676413 */     // GIR_Coverage, 30796,
     /*  676413 */     GIR_EraseRootFromParent_Done,
     /*  676414 */   // Label 10622: @676414
     /*  676414 */   GIM_Try, /*On fail goto*//*Label 10623*/ GIMT_Encode4(676464), // Rule ID 30797 //
     /*  676419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  676422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  676427 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676440 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  676440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  676443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676448 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  676458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676462 */     GIR_RootConstrainSelectedInstOperands,
     /*  676463 */     // GIR_Coverage, 30797,
     /*  676463 */     GIR_EraseRootFromParent_Done,
     /*  676464 */   // Label 10623: @676464
     /*  676464 */   GIM_Try, /*On fail goto*//*Label 10624*/ GIMT_Encode4(676514), // Rule ID 30798 //
     /*  676469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  676472 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  676477 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676490 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  676490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  676493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676498 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  676508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676512 */     GIR_RootConstrainSelectedInstOperands,
     /*  676513 */     // GIR_Coverage, 30798,
     /*  676513 */     GIR_EraseRootFromParent_Done,
     /*  676514 */   // Label 10624: @676514
     /*  676514 */   GIM_Try, /*On fail goto*//*Label 10625*/ GIMT_Encode4(676564), // Rule ID 30799 //
     /*  676519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  676522 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  676527 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  676529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676533 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676540 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  676540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
     /*  676543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676548 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  676558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676562 */     GIR_RootConstrainSelectedInstOperands,
     /*  676563 */     // GIR_Coverage, 30799,
     /*  676563 */     GIR_EraseRootFromParent_Done,
     /*  676564 */   // Label 10625: @676564
     /*  676564 */   GIM_Try, /*On fail goto*//*Label 10626*/ GIMT_Encode4(676618), // Rule ID 30770 //
     /*  676569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  676572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676592 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  676595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676602 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676612 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676616 */     GIR_RootConstrainSelectedInstOperands,
     /*  676617 */     // GIR_Coverage, 30770,
     /*  676617 */     GIR_EraseRootFromParent_Done,
     /*  676618 */   // Label 10626: @676618
     /*  676618 */   GIM_Try, /*On fail goto*//*Label 10627*/ GIMT_Encode4(676672), // Rule ID 30771 //
     /*  676623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  676626 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676646 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  676649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676656 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676670 */     GIR_RootConstrainSelectedInstOperands,
     /*  676671 */     // GIR_Coverage, 30771,
     /*  676671 */     GIR_EraseRootFromParent_Done,
     /*  676672 */   // Label 10627: @676672
     /*  676672 */   GIM_Try, /*On fail goto*//*Label 10628*/ GIMT_Encode4(676726), // Rule ID 30772 //
     /*  676677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  676680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676700 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  676703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676710 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676724 */     GIR_RootConstrainSelectedInstOperands,
     /*  676725 */     // GIR_Coverage, 30772,
     /*  676725 */     GIR_EraseRootFromParent_Done,
     /*  676726 */   // Label 10628: @676726
     /*  676726 */   GIM_Try, /*On fail goto*//*Label 10629*/ GIMT_Encode4(676780), // Rule ID 30773 //
     /*  676731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  676734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676754 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  676757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676764 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676774 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676778 */     GIR_RootConstrainSelectedInstOperands,
     /*  676779 */     // GIR_Coverage, 30773,
     /*  676779 */     GIR_EraseRootFromParent_Done,
     /*  676780 */   // Label 10629: @676780
     /*  676780 */   GIM_Try, /*On fail goto*//*Label 10630*/ GIMT_Encode4(676834), // Rule ID 30774 //
     /*  676785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  676788 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676797 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676808 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  676811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676818 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676832 */     GIR_RootConstrainSelectedInstOperands,
     /*  676833 */     // GIR_Coverage, 30774,
     /*  676833 */     GIR_EraseRootFromParent_Done,
     /*  676834 */   // Label 10630: @676834
     /*  676834 */   GIM_Try, /*On fail goto*//*Label 10631*/ GIMT_Encode4(676888), // Rule ID 30780 //
     /*  676839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  676842 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676862 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_i64>>  =>  (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9),
     /*  676865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676872 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676886 */     GIR_RootConstrainSelectedInstOperands,
     /*  676887 */     // GIR_Coverage, 30780,
     /*  676887 */     GIR_EraseRootFromParent_Done,
     /*  676888 */   // Label 10631: @676888
     /*  676888 */   GIM_Try, /*On fail goto*//*Label 10632*/ GIMT_Encode4(676942), // Rule ID 30781 //
     /*  676893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  676896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676916 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_i64>>  =>  (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9),
     /*  676919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676926 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676940 */     GIR_RootConstrainSelectedInstOperands,
     /*  676941 */     // GIR_Coverage, 30781,
     /*  676941 */     GIR_EraseRootFromParent_Done,
     /*  676942 */   // Label 10632: @676942
     /*  676942 */   GIM_Try, /*On fail goto*//*Label 10633*/ GIMT_Encode4(676996), // Rule ID 30782 //
     /*  676947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  676950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  676955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  676959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  676963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  676970 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_i64>>  =>  (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  676970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9),
     /*  676973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  676975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  676980 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  676982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  676987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  676990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  676994 */     GIR_RootConstrainSelectedInstOperands,
     /*  676995 */     // GIR_Coverage, 30782,
     /*  676995 */     GIR_EraseRootFromParent_Done,
     /*  676996 */   // Label 10633: @676996
     /*  676996 */   GIM_Try, /*On fail goto*//*Label 10634*/ GIMT_Encode4(677050), // Rule ID 30783 //
     /*  677001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  677004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  677009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677024 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_i64>>  =>  (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  677024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9),
     /*  677027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677034 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  677044 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677048 */     GIR_RootConstrainSelectedInstOperands,
     /*  677049 */     // GIR_Coverage, 30783,
     /*  677049 */     GIR_EraseRootFromParent_Done,
     /*  677050 */   // Label 10634: @677050
     /*  677050 */   GIM_Try, /*On fail goto*//*Label 10635*/ GIMT_Encode4(677104), // Rule ID 30784 //
     /*  677055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  677058 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  677063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677078 */     // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_i64>>  =>  (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  677078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9),
     /*  677081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677088 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  677098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677102 */     GIR_RootConstrainSelectedInstOperands,
     /*  677103 */     // GIR_Coverage, 30784,
     /*  677103 */     GIR_EraseRootFromParent_Done,
     /*  677104 */   // Label 10635: @677104
     /*  677104 */   GIM_Try, /*On fail goto*//*Label 10636*/ GIMT_Encode4(677158), // Rule ID 30790 //
     /*  677109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  677112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  677117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677132 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  677132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  677135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677142 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  677152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677156 */     GIR_RootConstrainSelectedInstOperands,
     /*  677157 */     // GIR_Coverage, 30790,
     /*  677157 */     GIR_EraseRootFromParent_Done,
     /*  677158 */   // Label 10636: @677158
     /*  677158 */   GIM_Try, /*On fail goto*//*Label 10637*/ GIMT_Encode4(677212), // Rule ID 30791 //
     /*  677163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  677166 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  677171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677175 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677186 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  677186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  677189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677196 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  677206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677210 */     GIR_RootConstrainSelectedInstOperands,
     /*  677211 */     // GIR_Coverage, 30791,
     /*  677211 */     GIR_EraseRootFromParent_Done,
     /*  677212 */   // Label 10637: @677212
     /*  677212 */   GIM_Try, /*On fail goto*//*Label 10638*/ GIMT_Encode4(677266), // Rule ID 30792 //
     /*  677217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  677220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  677225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677240 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  677240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  677243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677250 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  677260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677264 */     GIR_RootConstrainSelectedInstOperands,
     /*  677265 */     // GIR_Coverage, 30792,
     /*  677265 */     GIR_EraseRootFromParent_Done,
     /*  677266 */   // Label 10638: @677266
     /*  677266 */   GIM_Try, /*On fail goto*//*Label 10639*/ GIMT_Encode4(677320), // Rule ID 30793 //
     /*  677271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  677274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  677279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677294 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  677294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  677297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677304 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  677314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677318 */     GIR_RootConstrainSelectedInstOperands,
     /*  677319 */     // GIR_Coverage, 30793,
     /*  677319 */     GIR_EraseRootFromParent_Done,
     /*  677320 */   // Label 10639: @677320
     /*  677320 */   GIM_Try, /*On fail goto*//*Label 10640*/ GIMT_Encode4(677374), // Rule ID 30794 //
     /*  677325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  677328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  677333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  677348 */     // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_i64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  677348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
     /*  677351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  677358 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  677360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  677365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  677368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677372 */     GIR_RootConstrainSelectedInstOperands,
     /*  677373 */     // GIR_Coverage, 30794,
     /*  677373 */     GIR_EraseRootFromParent_Done,
     /*  677374 */   // Label 10640: @677374
     /*  677374 */   GIM_Try, /*On fail goto*//*Label 10641*/ GIMT_Encode4(677433), // Rule ID 13245 //
     /*  677379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  677382 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677389 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  677391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  677402 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR),
     /*  677405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677410 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677431 */     GIR_RootConstrainSelectedInstOperands,
     /*  677432 */     // GIR_Coverage, 13245,
     /*  677432 */     GIR_EraseRootFromParent_Done,
     /*  677433 */   // Label 10641: @677433
     /*  677433 */   GIM_Try, /*On fail goto*//*Label 10642*/ GIMT_Encode4(677492), // Rule ID 13246 //
     /*  677438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  677441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677448 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  677450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  677461 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR),
     /*  677464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677469 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677490 */     GIR_RootConstrainSelectedInstOperands,
     /*  677491 */     // GIR_Coverage, 13246,
     /*  677491 */     GIR_EraseRootFromParent_Done,
     /*  677492 */   // Label 10642: @677492
     /*  677492 */   GIM_Try, /*On fail goto*//*Label 10643*/ GIMT_Encode4(677551), // Rule ID 13247 //
     /*  677497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  677500 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677507 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  677509 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  677520 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR),
     /*  677523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677528 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677545 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677549 */     GIR_RootConstrainSelectedInstOperands,
     /*  677550 */     // GIR_Coverage, 13247,
     /*  677550 */     GIR_EraseRootFromParent_Done,
     /*  677551 */   // Label 10643: @677551
     /*  677551 */   GIM_Try, /*On fail goto*//*Label 10644*/ GIMT_Encode4(677610), // Rule ID 13248 //
     /*  677556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  677559 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677566 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  677568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  677579 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR),
     /*  677582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677587 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677608 */     GIR_RootConstrainSelectedInstOperands,
     /*  677609 */     // GIR_Coverage, 13248,
     /*  677609 */     GIR_EraseRootFromParent_Done,
     /*  677610 */   // Label 10644: @677610
     /*  677610 */   GIM_Try, /*On fail goto*//*Label 10645*/ GIMT_Encode4(677669), // Rule ID 13249 //
     /*  677615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  677618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677625 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  677627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  677638 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR),
     /*  677641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677646 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677667 */     GIR_RootConstrainSelectedInstOperands,
     /*  677668 */     // GIR_Coverage, 13249,
     /*  677668 */     GIR_EraseRootFromParent_Done,
     /*  677669 */   // Label 10645: @677669
     /*  677669 */   GIM_Try, /*On fail goto*//*Label 10646*/ GIMT_Encode4(677732), // Rule ID 13255 //
     /*  677674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  677677 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677692 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  677699 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  677702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677709 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677730 */     GIR_RootConstrainSelectedInstOperands,
     /*  677731 */     // GIR_Coverage, 13255,
     /*  677731 */     GIR_EraseRootFromParent_Done,
     /*  677732 */   // Label 10646: @677732
     /*  677732 */   GIM_Try, /*On fail goto*//*Label 10647*/ GIMT_Encode4(677795), // Rule ID 13256 //
     /*  677737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  677740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  677762 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  677765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677772 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677793 */     GIR_RootConstrainSelectedInstOperands,
     /*  677794 */     // GIR_Coverage, 13256,
     /*  677794 */     GIR_EraseRootFromParent_Done,
     /*  677795 */   // Label 10647: @677795
     /*  677795 */   GIM_Try, /*On fail goto*//*Label 10648*/ GIMT_Encode4(677858), // Rule ID 13257 //
     /*  677800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  677803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677814 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677818 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  677825 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  677828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677835 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677856 */     GIR_RootConstrainSelectedInstOperands,
     /*  677857 */     // GIR_Coverage, 13257,
     /*  677857 */     GIR_EraseRootFromParent_Done,
     /*  677858 */   // Label 10648: @677858
     /*  677858 */   GIM_Try, /*On fail goto*//*Label 10649*/ GIMT_Encode4(677921), // Rule ID 13258 //
     /*  677863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  677866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  677888 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  677891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677898 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677915 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677919 */     GIR_RootConstrainSelectedInstOperands,
     /*  677920 */     // GIR_Coverage, 13258,
     /*  677920 */     GIR_EraseRootFromParent_Done,
     /*  677921 */   // Label 10649: @677921
     /*  677921 */   GIM_Try, /*On fail goto*//*Label 10650*/ GIMT_Encode4(677984), // Rule ID 13259 //
     /*  677926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  677929 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  677940 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  677944 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  677951 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  677951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  677954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  677956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  677961 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  677963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  677968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  677973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  677978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  677982 */     GIR_RootConstrainSelectedInstOperands,
     /*  677983 */     // GIR_Coverage, 13259,
     /*  677983 */     GIR_EraseRootFromParent_Done,
     /*  677984 */   // Label 10650: @677984
     /*  677984 */   GIM_Try, /*On fail goto*//*Label 10651*/ GIMT_Encode4(678036), // Rule ID 13240 //
     /*  677989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  677992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  677999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678012 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2),
     /*  678015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678020 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  678030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678034 */     GIR_RootConstrainSelectedInstOperands,
     /*  678035 */     // GIR_Coverage, 13240,
     /*  678035 */     GIR_EraseRootFromParent_Done,
     /*  678036 */   // Label 10651: @678036
     /*  678036 */   GIM_Try, /*On fail goto*//*Label 10652*/ GIMT_Encode4(678088), // Rule ID 13241 //
     /*  678041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  678044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678051 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678064 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2),
     /*  678067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678072 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  678082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678086 */     GIR_RootConstrainSelectedInstOperands,
     /*  678087 */     // GIR_Coverage, 13241,
     /*  678087 */     GIR_EraseRootFromParent_Done,
     /*  678088 */   // Label 10652: @678088
     /*  678088 */   GIM_Try, /*On fail goto*//*Label 10653*/ GIMT_Encode4(678140), // Rule ID 13242 //
     /*  678093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  678096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678103 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678116 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2),
     /*  678119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678124 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  678134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678138 */     GIR_RootConstrainSelectedInstOperands,
     /*  678139 */     // GIR_Coverage, 13242,
     /*  678139 */     GIR_EraseRootFromParent_Done,
     /*  678140 */   // Label 10653: @678140
     /*  678140 */   GIM_Try, /*On fail goto*//*Label 10654*/ GIMT_Encode4(678192), // Rule ID 13243 //
     /*  678145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  678148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678155 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678168 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2),
     /*  678171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678176 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  678186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678190 */     GIR_RootConstrainSelectedInstOperands,
     /*  678191 */     // GIR_Coverage, 13243,
     /*  678191 */     GIR_EraseRootFromParent_Done,
     /*  678192 */   // Label 10654: @678192
     /*  678192 */   GIM_Try, /*On fail goto*//*Label 10655*/ GIMT_Encode4(678244), // Rule ID 13244 //
     /*  678197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  678200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678207 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678209 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678220 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2),
     /*  678223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678228 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  678238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678242 */     GIR_RootConstrainSelectedInstOperands,
     /*  678243 */     // GIR_Coverage, 13244,
     /*  678243 */     GIR_EraseRootFromParent_Done,
     /*  678244 */   // Label 10655: @678244
     /*  678244 */   GIM_Try, /*On fail goto*//*Label 10656*/ GIMT_Encode4(678300), // Rule ID 13250 //
     /*  678249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  678252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  678263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678274 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN),
     /*  678277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  678279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678284 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  678294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678298 */     GIR_RootConstrainSelectedInstOperands,
     /*  678299 */     // GIR_Coverage, 13250,
     /*  678299 */     GIR_EraseRootFromParent_Done,
     /*  678300 */   // Label 10656: @678300
     /*  678300 */   GIM_Try, /*On fail goto*//*Label 10657*/ GIMT_Encode4(678356), // Rule ID 13251 //
     /*  678305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  678308 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  678319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678330 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN),
     /*  678333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  678335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678340 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  678350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678354 */     GIR_RootConstrainSelectedInstOperands,
     /*  678355 */     // GIR_Coverage, 13251,
     /*  678355 */     GIR_EraseRootFromParent_Done,
     /*  678356 */   // Label 10657: @678356
     /*  678356 */   GIM_Try, /*On fail goto*//*Label 10658*/ GIMT_Encode4(678412), // Rule ID 13252 //
     /*  678361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  678364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  678375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678386 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN),
     /*  678389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  678391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678396 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  678406 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678410 */     GIR_RootConstrainSelectedInstOperands,
     /*  678411 */     // GIR_Coverage, 13252,
     /*  678411 */     GIR_EraseRootFromParent_Done,
     /*  678412 */   // Label 10658: @678412
     /*  678412 */   GIM_Try, /*On fail goto*//*Label 10659*/ GIMT_Encode4(678468), // Rule ID 13253 //
     /*  678417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  678420 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  678431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678442 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN),
     /*  678445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  678447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678452 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  678462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678466 */     GIR_RootConstrainSelectedInstOperands,
     /*  678467 */     // GIR_Coverage, 13253,
     /*  678467 */     GIR_EraseRootFromParent_Done,
     /*  678468 */   // Label 10659: @678468
     /*  678468 */   GIM_Try, /*On fail goto*//*Label 10660*/ GIMT_Encode4(678524), // Rule ID 13254 //
     /*  678473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  678476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  678487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  678498 */     // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  678498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN),
     /*  678501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  678503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  678508 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  678515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  678518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678522 */     GIR_RootConstrainSelectedInstOperands,
     /*  678523 */     // GIR_Coverage, 13254,
     /*  678523 */     GIR_EraseRootFromParent_Done,
     /*  678524 */   // Label 10660: @678524
     /*  678524 */   GIM_Try, /*On fail goto*//*Label 10661*/ GIMT_Encode4(678584), // Rule ID 10837 //
     /*  678529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  678532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678540 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678553 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678561 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678582 */     GIR_RootConstrainSelectedInstOperands,
     /*  678583 */     // GIR_Coverage, 10837,
     /*  678583 */     GIR_EraseRootFromParent_Done,
     /*  678584 */   // Label 10661: @678584
     /*  678584 */   GIM_Try, /*On fail goto*//*Label 10662*/ GIMT_Encode4(678644), // Rule ID 10838 //
     /*  678589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  678592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678600 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678613 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678621 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678642 */     GIR_RootConstrainSelectedInstOperands,
     /*  678643 */     // GIR_Coverage, 10838,
     /*  678643 */     GIR_EraseRootFromParent_Done,
     /*  678644 */   // Label 10662: @678644
     /*  678644 */   GIM_Try, /*On fail goto*//*Label 10663*/ GIMT_Encode4(678704), // Rule ID 10839 //
     /*  678649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  678652 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678660 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678673 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678681 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678702 */     GIR_RootConstrainSelectedInstOperands,
     /*  678703 */     // GIR_Coverage, 10839,
     /*  678703 */     GIR_EraseRootFromParent_Done,
     /*  678704 */   // Label 10663: @678704
     /*  678704 */   GIM_Try, /*On fail goto*//*Label 10664*/ GIMT_Encode4(678764), // Rule ID 10840 //
     /*  678709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  678712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678720 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678733 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678741 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678762 */     GIR_RootConstrainSelectedInstOperands,
     /*  678763 */     // GIR_Coverage, 10840,
     /*  678763 */     GIR_EraseRootFromParent_Done,
     /*  678764 */   // Label 10664: @678764
     /*  678764 */   GIM_Try, /*On fail goto*//*Label 10665*/ GIMT_Encode4(678824), // Rule ID 10841 //
     /*  678769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  678772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678780 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678793 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678801 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678822 */     GIR_RootConstrainSelectedInstOperands,
     /*  678823 */     // GIR_Coverage, 10841,
     /*  678823 */     GIR_EraseRootFromParent_Done,
     /*  678824 */   // Label 10665: @678824
     /*  678824 */   GIM_Try, /*On fail goto*//*Label 10666*/ GIMT_Encode4(678883), // Rule ID 11393 //
     /*  678829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  678832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678839 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678852 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678860 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678881 */     GIR_RootConstrainSelectedInstOperands,
     /*  678882 */     // GIR_Coverage, 11393,
     /*  678882 */     GIR_EraseRootFromParent_Done,
     /*  678883 */   // Label 10666: @678883
     /*  678883 */   GIM_Try, /*On fail goto*//*Label 10667*/ GIMT_Encode4(678942), // Rule ID 11394 //
     /*  678888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  678891 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678898 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678911 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678919 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678940 */     GIR_RootConstrainSelectedInstOperands,
     /*  678941 */     // GIR_Coverage, 11394,
     /*  678941 */     GIR_EraseRootFromParent_Done,
     /*  678942 */   // Label 10667: @678942
     /*  678942 */   GIM_Try, /*On fail goto*//*Label 10668*/ GIMT_Encode4(679001), // Rule ID 11395 //
     /*  678947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  678950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  678957 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  678959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  678963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  678970 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  678970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  678973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  678978 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  678980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  678985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  678990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  678995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  678999 */     GIR_RootConstrainSelectedInstOperands,
     /*  679000 */     // GIR_Coverage, 11395,
     /*  679000 */     GIR_EraseRootFromParent_Done,
     /*  679001 */   // Label 10668: @679001
     /*  679001 */   GIM_Try, /*On fail goto*//*Label 10669*/ GIMT_Encode4(679060), // Rule ID 11396 //
     /*  679006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  679009 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679016 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  679029 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  679032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679037 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679058 */     GIR_RootConstrainSelectedInstOperands,
     /*  679059 */     // GIR_Coverage, 11396,
     /*  679059 */     GIR_EraseRootFromParent_Done,
     /*  679060 */   // Label 10669: @679060
     /*  679060 */   GIM_Try, /*On fail goto*//*Label 10670*/ GIMT_Encode4(679119), // Rule ID 11397 //
     /*  679065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  679068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679075 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  679088 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR),
     /*  679091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679096 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679113 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679117 */     GIR_RootConstrainSelectedInstOperands,
     /*  679118 */     // GIR_Coverage, 11397,
     /*  679118 */     GIR_EraseRootFromParent_Done,
     /*  679119 */   // Label 10670: @679119
     /*  679119 */   GIM_Try, /*On fail goto*//*Label 10671*/ GIMT_Encode4(679183), // Rule ID 10827 //
     /*  679124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  679127 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679150 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679160 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679181 */     GIR_RootConstrainSelectedInstOperands,
     /*  679182 */     // GIR_Coverage, 10827,
     /*  679182 */     GIR_EraseRootFromParent_Done,
     /*  679183 */   // Label 10671: @679183
     /*  679183 */   GIM_Try, /*On fail goto*//*Label 10672*/ GIMT_Encode4(679247), // Rule ID 10828 //
     /*  679188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  679191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679214 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679224 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679241 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679245 */     GIR_RootConstrainSelectedInstOperands,
     /*  679246 */     // GIR_Coverage, 10828,
     /*  679246 */     GIR_EraseRootFromParent_Done,
     /*  679247 */   // Label 10672: @679247
     /*  679247 */   GIM_Try, /*On fail goto*//*Label 10673*/ GIMT_Encode4(679311), // Rule ID 10829 //
     /*  679252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  679255 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679278 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679288 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679309 */     GIR_RootConstrainSelectedInstOperands,
     /*  679310 */     // GIR_Coverage, 10829,
     /*  679310 */     GIR_EraseRootFromParent_Done,
     /*  679311 */   // Label 10673: @679311
     /*  679311 */   GIM_Try, /*On fail goto*//*Label 10674*/ GIMT_Encode4(679375), // Rule ID 10830 //
     /*  679316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  679319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679342 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679352 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679369 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679373 */     GIR_RootConstrainSelectedInstOperands,
     /*  679374 */     // GIR_Coverage, 10830,
     /*  679374 */     GIR_EraseRootFromParent_Done,
     /*  679375 */   // Label 10674: @679375
     /*  679375 */   GIM_Try, /*On fail goto*//*Label 10675*/ GIMT_Encode4(679439), // Rule ID 10831 //
     /*  679380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  679383 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679395 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679406 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679416 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679437 */     GIR_RootConstrainSelectedInstOperands,
     /*  679438 */     // GIR_Coverage, 10831,
     /*  679438 */     GIR_EraseRootFromParent_Done,
     /*  679439 */   // Label 10675: @679439
     /*  679439 */   GIM_Try, /*On fail goto*//*Label 10676*/ GIMT_Encode4(679502), // Rule ID 11383 //
     /*  679444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  679447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679458 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679469 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679479 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679500 */     GIR_RootConstrainSelectedInstOperands,
     /*  679501 */     // GIR_Coverage, 11383,
     /*  679501 */     GIR_EraseRootFromParent_Done,
     /*  679502 */   // Label 10676: @679502
     /*  679502 */   GIM_Try, /*On fail goto*//*Label 10677*/ GIMT_Encode4(679565), // Rule ID 11384 //
     /*  679507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  679510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679532 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679542 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679563 */     GIR_RootConstrainSelectedInstOperands,
     /*  679564 */     // GIR_Coverage, 11384,
     /*  679564 */     GIR_EraseRootFromParent_Done,
     /*  679565 */   // Label 10677: @679565
     /*  679565 */   GIM_Try, /*On fail goto*//*Label 10678*/ GIMT_Encode4(679628), // Rule ID 11385 //
     /*  679570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  679573 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679595 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679605 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679626 */     GIR_RootConstrainSelectedInstOperands,
     /*  679627 */     // GIR_Coverage, 11385,
     /*  679627 */     GIR_EraseRootFromParent_Done,
     /*  679628 */   // Label 10678: @679628
     /*  679628 */   GIM_Try, /*On fail goto*//*Label 10679*/ GIMT_Encode4(679691), // Rule ID 11386 //
     /*  679633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  679636 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679647 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679658 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679668 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679689 */     GIR_RootConstrainSelectedInstOperands,
     /*  679690 */     // GIR_Coverage, 11386,
     /*  679690 */     GIR_EraseRootFromParent_Done,
     /*  679691 */   // Label 10679: @679691
     /*  679691 */   GIM_Try, /*On fail goto*//*Label 10680*/ GIMT_Encode4(679754), // Rule ID 11387 //
     /*  679696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  679699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  679710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  679721 */     // (atomic_load_min:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  679721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_SADDR_RTN),
     /*  679724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  679726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  679731 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  679738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  679743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  679748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679752 */     GIR_RootConstrainSelectedInstOperands,
     /*  679753 */     // GIR_Coverage, 11387,
     /*  679753 */     GIR_EraseRootFromParent_Done,
     /*  679754 */   // Label 10680: @679754
     /*  679754 */   GIM_Try, /*On fail goto*//*Label 10681*/ GIMT_Encode4(679807), // Rule ID 10832 //
     /*  679759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  679762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679770 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679772 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  679783 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  679783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  679786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  679791 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  679798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  679801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679805 */     GIR_RootConstrainSelectedInstOperands,
     /*  679806 */     // GIR_Coverage, 10832,
     /*  679806 */     GIR_EraseRootFromParent_Done,
     /*  679807 */   // Label 10681: @679807
     /*  679807 */   GIM_Try, /*On fail goto*//*Label 10682*/ GIMT_Encode4(679860), // Rule ID 10833 //
     /*  679812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  679815 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679823 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  679836 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  679836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  679839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  679844 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  679851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  679854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679858 */     GIR_RootConstrainSelectedInstOperands,
     /*  679859 */     // GIR_Coverage, 10833,
     /*  679859 */     GIR_EraseRootFromParent_Done,
     /*  679860 */   // Label 10682: @679860
     /*  679860 */   GIM_Try, /*On fail goto*//*Label 10683*/ GIMT_Encode4(679913), // Rule ID 10834 //
     /*  679865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  679868 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679876 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679878 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  679889 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  679889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  679892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  679897 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  679904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  679907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679911 */     GIR_RootConstrainSelectedInstOperands,
     /*  679912 */     // GIR_Coverage, 10834,
     /*  679912 */     GIR_EraseRootFromParent_Done,
     /*  679913 */   // Label 10683: @679913
     /*  679913 */   GIM_Try, /*On fail goto*//*Label 10684*/ GIMT_Encode4(679966), // Rule ID 10835 //
     /*  679918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  679921 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679929 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  679942 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  679942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  679945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  679950 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  679952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  679957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  679960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  679964 */     GIR_RootConstrainSelectedInstOperands,
     /*  679965 */     // GIR_Coverage, 10835,
     /*  679965 */     GIR_EraseRootFromParent_Done,
     /*  679966 */   // Label 10684: @679966
     /*  679966 */   GIM_Try, /*On fail goto*//*Label 10685*/ GIMT_Encode4(680019), // Rule ID 10836 //
     /*  679971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  679974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  679982 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  679984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  679988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  679995 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  679995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  679998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680003 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680017 */     GIR_RootConstrainSelectedInstOperands,
     /*  680018 */     // GIR_Coverage, 10836,
     /*  680018 */     GIR_EraseRootFromParent_Done,
     /*  680019 */   // Label 10685: @680019
     /*  680019 */   GIM_Try, /*On fail goto*//*Label 10686*/ GIMT_Encode4(680071), // Rule ID 11388 //
     /*  680024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  680027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680034 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680047 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  680050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680055 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680069 */     GIR_RootConstrainSelectedInstOperands,
     /*  680070 */     // GIR_Coverage, 11388,
     /*  680070 */     GIR_EraseRootFromParent_Done,
     /*  680071 */   // Label 10686: @680071
     /*  680071 */   GIM_Try, /*On fail goto*//*Label 10687*/ GIMT_Encode4(680123), // Rule ID 11389 //
     /*  680076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  680079 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680086 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680088 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680092 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680099 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  680102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680107 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680121 */     GIR_RootConstrainSelectedInstOperands,
     /*  680122 */     // GIR_Coverage, 11389,
     /*  680122 */     GIR_EraseRootFromParent_Done,
     /*  680123 */   // Label 10687: @680123
     /*  680123 */   GIM_Try, /*On fail goto*//*Label 10688*/ GIMT_Encode4(680175), // Rule ID 11390 //
     /*  680128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  680131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680138 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680151 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  680154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680159 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680166 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680173 */     GIR_RootConstrainSelectedInstOperands,
     /*  680174 */     // GIR_Coverage, 11390,
     /*  680174 */     GIR_EraseRootFromParent_Done,
     /*  680175 */   // Label 10688: @680175
     /*  680175 */   GIM_Try, /*On fail goto*//*Label 10689*/ GIMT_Encode4(680227), // Rule ID 11391 //
     /*  680180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  680183 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680190 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680203 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  680206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680211 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680221 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680225 */     GIR_RootConstrainSelectedInstOperands,
     /*  680226 */     // GIR_Coverage, 11391,
     /*  680226 */     GIR_EraseRootFromParent_Done,
     /*  680227 */   // Label 10689: @680227
     /*  680227 */   GIM_Try, /*On fail goto*//*Label 10690*/ GIMT_Encode4(680279), // Rule ID 11392 //
     /*  680232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  680235 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680242 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680255 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
     /*  680258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680263 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680277 */     GIR_RootConstrainSelectedInstOperands,
     /*  680278 */     // GIR_Coverage, 11392,
     /*  680278 */     GIR_EraseRootFromParent_Done,
     /*  680279 */   // Label 10690: @680279
     /*  680279 */   GIM_Try, /*On fail goto*//*Label 10691*/ GIMT_Encode4(680336), // Rule ID 10822 //
     /*  680284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  680287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680299 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680303 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680310 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680320 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680334 */     GIR_RootConstrainSelectedInstOperands,
     /*  680335 */     // GIR_Coverage, 10822,
     /*  680335 */     GIR_EraseRootFromParent_Done,
     /*  680336 */   // Label 10691: @680336
     /*  680336 */   GIM_Try, /*On fail goto*//*Label 10692*/ GIMT_Encode4(680393), // Rule ID 10823 //
     /*  680341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  680344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680367 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680377 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680391 */     GIR_RootConstrainSelectedInstOperands,
     /*  680392 */     // GIR_Coverage, 10823,
     /*  680392 */     GIR_EraseRootFromParent_Done,
     /*  680393 */   // Label 10692: @680393
     /*  680393 */   GIM_Try, /*On fail goto*//*Label 10693*/ GIMT_Encode4(680450), // Rule ID 10824 //
     /*  680398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  680401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680413 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680417 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680424 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680434 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680448 */     GIR_RootConstrainSelectedInstOperands,
     /*  680449 */     // GIR_Coverage, 10824,
     /*  680449 */     GIR_EraseRootFromParent_Done,
     /*  680450 */   // Label 10693: @680450
     /*  680450 */   GIM_Try, /*On fail goto*//*Label 10694*/ GIMT_Encode4(680507), // Rule ID 10825 //
     /*  680455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  680458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680470 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680474 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680481 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680491 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680505 */     GIR_RootConstrainSelectedInstOperands,
     /*  680506 */     // GIR_Coverage, 10825,
     /*  680506 */     GIR_EraseRootFromParent_Done,
     /*  680507 */   // Label 10694: @680507
     /*  680507 */   GIM_Try, /*On fail goto*//*Label 10695*/ GIMT_Encode4(680564), // Rule ID 10826 //
     /*  680512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  680515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680538 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680548 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680562 */     GIR_RootConstrainSelectedInstOperands,
     /*  680563 */     // GIR_Coverage, 10826,
     /*  680563 */     GIR_EraseRootFromParent_Done,
     /*  680564 */   // Label 10695: @680564
     /*  680564 */   GIM_Try, /*On fail goto*//*Label 10696*/ GIMT_Encode4(680620), // Rule ID 11378 //
     /*  680569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  680572 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680594 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680604 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680618 */     GIR_RootConstrainSelectedInstOperands,
     /*  680619 */     // GIR_Coverage, 11378,
     /*  680619 */     GIR_EraseRootFromParent_Done,
     /*  680620 */   // Label 10696: @680620
     /*  680620 */   GIM_Try, /*On fail goto*//*Label 10697*/ GIMT_Encode4(680676), // Rule ID 11379 //
     /*  680625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  680628 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680650 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680660 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680674 */     GIR_RootConstrainSelectedInstOperands,
     /*  680675 */     // GIR_Coverage, 11379,
     /*  680675 */     GIR_EraseRootFromParent_Done,
     /*  680676 */   // Label 10697: @680676
     /*  680676 */   GIM_Try, /*On fail goto*//*Label 10698*/ GIMT_Encode4(680732), // Rule ID 11380 //
     /*  680681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  680684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680706 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680716 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680730 */     GIR_RootConstrainSelectedInstOperands,
     /*  680731 */     // GIR_Coverage, 11380,
     /*  680731 */     GIR_EraseRootFromParent_Done,
     /*  680732 */   // Label 10698: @680732
     /*  680732 */   GIM_Try, /*On fail goto*//*Label 10699*/ GIMT_Encode4(680788), // Rule ID 11381 //
     /*  680737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  680740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680762 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680772 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680786 */     GIR_RootConstrainSelectedInstOperands,
     /*  680787 */     // GIR_Coverage, 11381,
     /*  680787 */     GIR_EraseRootFromParent_Done,
     /*  680788 */   // Label 10699: @680788
     /*  680788 */   GIM_Try, /*On fail goto*//*Label 10700*/ GIMT_Encode4(680844), // Rule ID 11382 //
     /*  680793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  680796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  680807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  680818 */     // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  680818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
     /*  680821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  680823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  680828 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  680830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  680835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  680838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680842 */     GIR_RootConstrainSelectedInstOperands,
     /*  680843 */     // GIR_Coverage, 11382,
     /*  680843 */     GIR_EraseRootFromParent_Done,
     /*  680844 */   // Label 10700: @680844
     /*  680844 */   GIM_Reject,
     /*  680845 */ // Label 10570: @680845
     /*  680845 */ GIM_Reject,
     /*  680846 */ // Label 10462: @680846
     /*  680846 */ GIM_Reject,
     /*  680847 */ // Label 27: @680847
     /*  680847 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 10703*/ GIMT_Encode4(694458),
     /*  680858 */ /*GILLT_s32*//*Label 10701*/ GIMT_Encode4(680866),
     /*  680862 */ /*GILLT_s64*//*Label 10702*/ GIMT_Encode4(686958),
     /*  680866 */ // Label 10701: @680866
     /*  680866 */ GIM_Try, /*On fail goto*//*Label 10704*/ GIMT_Encode4(686957),
     /*  680871 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  680874 */   GIM_Try, /*On fail goto*//*Label 10705*/ GIMT_Encode4(680936), // Rule ID 20978 //
     /*  680879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  680882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680889 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  680902 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  680902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64),
     /*  680905 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  680907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  680912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  680917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  680922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  680927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680934 */     GIR_RootConstrainSelectedInstOperands,
     /*  680935 */     // GIR_Coverage, 20978,
     /*  680935 */     GIR_EraseRootFromParent_Done,
     /*  680936 */   // Label 10705: @680936
     /*  680936 */   GIM_Try, /*On fail goto*//*Label 10706*/ GIMT_Encode4(680998), // Rule ID 20979 //
     /*  680941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  680944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  680951 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  680953 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  680957 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  680964 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  680964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64),
     /*  680967 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  680969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  680974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  680979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  680984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  680989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  680992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  680996 */     GIR_RootConstrainSelectedInstOperands,
     /*  680997 */     // GIR_Coverage, 20979,
     /*  680997 */     GIR_EraseRootFromParent_Done,
     /*  680998 */   // Label 10706: @680998
     /*  680998 */   GIM_Try, /*On fail goto*//*Label 10707*/ GIMT_Encode4(681060), // Rule ID 20980 //
     /*  681003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  681006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681013 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681015 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681026 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64),
     /*  681029 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681058 */     GIR_RootConstrainSelectedInstOperands,
     /*  681059 */     // GIR_Coverage, 20980,
     /*  681059 */     GIR_EraseRootFromParent_Done,
     /*  681060 */   // Label 10707: @681060
     /*  681060 */   GIM_Try, /*On fail goto*//*Label 10708*/ GIMT_Encode4(681122), // Rule ID 20981 //
     /*  681065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  681068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681075 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681088 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64),
     /*  681091 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681120 */     GIR_RootConstrainSelectedInstOperands,
     /*  681121 */     // GIR_Coverage, 20981,
     /*  681121 */     GIR_EraseRootFromParent_Done,
     /*  681122 */   // Label 10708: @681122
     /*  681122 */   GIM_Try, /*On fail goto*//*Label 10709*/ GIMT_Encode4(681184), // Rule ID 20982 //
     /*  681127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  681130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681137 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681150 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64),
     /*  681153 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681178 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681182 */     GIR_RootConstrainSelectedInstOperands,
     /*  681183 */     // GIR_Coverage, 20982,
     /*  681183 */     GIR_EraseRootFromParent_Done,
     /*  681184 */   // Label 10709: @681184
     /*  681184 */   GIM_Try, /*On fail goto*//*Label 10710*/ GIMT_Encode4(681246), // Rule ID 20998 //
     /*  681189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  681192 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681199 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681212 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64),
     /*  681215 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681244 */     GIR_RootConstrainSelectedInstOperands,
     /*  681245 */     // GIR_Coverage, 20998,
     /*  681245 */     GIR_EraseRootFromParent_Done,
     /*  681246 */   // Label 10710: @681246
     /*  681246 */   GIM_Try, /*On fail goto*//*Label 10711*/ GIMT_Encode4(681308), // Rule ID 20999 //
     /*  681251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  681254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681261 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681274 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64),
     /*  681277 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681306 */     GIR_RootConstrainSelectedInstOperands,
     /*  681307 */     // GIR_Coverage, 20999,
     /*  681307 */     GIR_EraseRootFromParent_Done,
     /*  681308 */   // Label 10711: @681308
     /*  681308 */   GIM_Try, /*On fail goto*//*Label 10712*/ GIMT_Encode4(681370), // Rule ID 21000 //
     /*  681313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  681316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681323 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681336 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64),
     /*  681339 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681368 */     GIR_RootConstrainSelectedInstOperands,
     /*  681369 */     // GIR_Coverage, 21000,
     /*  681369 */     GIR_EraseRootFromParent_Done,
     /*  681370 */   // Label 10712: @681370
     /*  681370 */   GIM_Try, /*On fail goto*//*Label 10713*/ GIMT_Encode4(681432), // Rule ID 21001 //
     /*  681375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  681378 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681385 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681398 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64),
     /*  681401 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681430 */     GIR_RootConstrainSelectedInstOperands,
     /*  681431 */     // GIR_Coverage, 21001,
     /*  681431 */     GIR_EraseRootFromParent_Done,
     /*  681432 */   // Label 10713: @681432
     /*  681432 */   GIM_Try, /*On fail goto*//*Label 10714*/ GIMT_Encode4(681494), // Rule ID 21002 //
     /*  681437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  681440 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681447 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  681449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681460 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64),
     /*  681463 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  681488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681492 */     GIR_RootConstrainSelectedInstOperands,
     /*  681493 */     // GIR_Coverage, 21002,
     /*  681493 */     GIR_EraseRootFromParent_Done,
     /*  681494 */   // Label 10714: @681494
     /*  681494 */   GIM_Try, /*On fail goto*//*Label 10715*/ GIMT_Encode4(681560), // Rule ID 20968 //
     /*  681499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  681502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681524 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN),
     /*  681527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681529 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681558 */     GIR_RootConstrainSelectedInstOperands,
     /*  681559 */     // GIR_Coverage, 20968,
     /*  681559 */     GIR_EraseRootFromParent_Done,
     /*  681560 */   // Label 10715: @681560
     /*  681560 */   GIM_Try, /*On fail goto*//*Label 10716*/ GIMT_Encode4(681626), // Rule ID 20969 //
     /*  681565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  681568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681590 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN),
     /*  681593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681595 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681624 */     GIR_RootConstrainSelectedInstOperands,
     /*  681625 */     // GIR_Coverage, 20969,
     /*  681625 */     GIR_EraseRootFromParent_Done,
     /*  681626 */   // Label 10716: @681626
     /*  681626 */   GIM_Try, /*On fail goto*//*Label 10717*/ GIMT_Encode4(681692), // Rule ID 20970 //
     /*  681631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  681634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681656 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN),
     /*  681659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681661 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681690 */     GIR_RootConstrainSelectedInstOperands,
     /*  681691 */     // GIR_Coverage, 20970,
     /*  681691 */     GIR_EraseRootFromParent_Done,
     /*  681692 */   // Label 10717: @681692
     /*  681692 */   GIM_Try, /*On fail goto*//*Label 10718*/ GIMT_Encode4(681758), // Rule ID 20971 //
     /*  681697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  681700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681722 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN),
     /*  681725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681727 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681756 */     GIR_RootConstrainSelectedInstOperands,
     /*  681757 */     // GIR_Coverage, 20971,
     /*  681757 */     GIR_EraseRootFromParent_Done,
     /*  681758 */   // Label 10718: @681758
     /*  681758 */   GIM_Try, /*On fail goto*//*Label 10719*/ GIMT_Encode4(681824), // Rule ID 20972 //
     /*  681763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  681766 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681788 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN),
     /*  681791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681793 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681822 */     GIR_RootConstrainSelectedInstOperands,
     /*  681823 */     // GIR_Coverage, 20972,
     /*  681823 */     GIR_EraseRootFromParent_Done,
     /*  681824 */   // Label 10719: @681824
     /*  681824 */   GIM_Try, /*On fail goto*//*Label 10720*/ GIMT_Encode4(681890), // Rule ID 20988 //
     /*  681829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  681832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681854 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN),
     /*  681857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681859 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681888 */     GIR_RootConstrainSelectedInstOperands,
     /*  681889 */     // GIR_Coverage, 20988,
     /*  681889 */     GIR_EraseRootFromParent_Done,
     /*  681890 */   // Label 10720: @681890
     /*  681890 */   GIM_Try, /*On fail goto*//*Label 10721*/ GIMT_Encode4(681956), // Rule ID 20989 //
     /*  681895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  681898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681909 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681920 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN),
     /*  681923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681925 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  681937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  681942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  681947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  681950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  681954 */     GIR_RootConstrainSelectedInstOperands,
     /*  681955 */     // GIR_Coverage, 20989,
     /*  681955 */     GIR_EraseRootFromParent_Done,
     /*  681956 */   // Label 10721: @681956
     /*  681956 */   GIM_Try, /*On fail goto*//*Label 10722*/ GIMT_Encode4(682022), // Rule ID 20990 //
     /*  681961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  681964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  681971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  681975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  681979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  681986 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  681986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN),
     /*  681989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  681991 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  681993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  681998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  682008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  682013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682020 */     GIR_RootConstrainSelectedInstOperands,
     /*  682021 */     // GIR_Coverage, 20990,
     /*  682021 */     GIR_EraseRootFromParent_Done,
     /*  682022 */   // Label 10722: @682022
     /*  682022 */   GIM_Try, /*On fail goto*//*Label 10723*/ GIMT_Encode4(682088), // Rule ID 20991 //
     /*  682027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  682030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  682052 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN),
     /*  682055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  682057 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  682064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  682074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  682079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682086 */     GIR_RootConstrainSelectedInstOperands,
     /*  682087 */     // GIR_Coverage, 20991,
     /*  682087 */     GIR_EraseRootFromParent_Done,
     /*  682088 */   // Label 10723: @682088
     /*  682088 */   GIM_Try, /*On fail goto*//*Label 10724*/ GIMT_Encode4(682154), // Rule ID 20992 //
     /*  682093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  682096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  682118 */     // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN),
     /*  682121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  682123 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  682130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  682140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  682145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682148 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682152 */     GIR_RootConstrainSelectedInstOperands,
     /*  682153 */     // GIR_Coverage, 20992,
     /*  682153 */     GIR_EraseRootFromParent_Done,
     /*  682154 */   // Label 10724: @682154
     /*  682154 */   GIM_Try, /*On fail goto*//*Label 10725*/ GIMT_Encode4(682211), // Rule ID 20973 //
     /*  682159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  682162 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682169 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682182 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
     /*  682185 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682209 */     GIR_RootConstrainSelectedInstOperands,
     /*  682210 */     // GIR_Coverage, 20973,
     /*  682210 */     GIR_EraseRootFromParent_Done,
     /*  682211 */   // Label 10725: @682211
     /*  682211 */   GIM_Try, /*On fail goto*//*Label 10726*/ GIMT_Encode4(682268), // Rule ID 20974 //
     /*  682216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  682219 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682226 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682239 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
     /*  682242 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682266 */     GIR_RootConstrainSelectedInstOperands,
     /*  682267 */     // GIR_Coverage, 20974,
     /*  682267 */     GIR_EraseRootFromParent_Done,
     /*  682268 */   // Label 10726: @682268
     /*  682268 */   GIM_Try, /*On fail goto*//*Label 10727*/ GIMT_Encode4(682325), // Rule ID 20975 //
     /*  682273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  682276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682283 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682296 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
     /*  682299 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682319 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682323 */     GIR_RootConstrainSelectedInstOperands,
     /*  682324 */     // GIR_Coverage, 20975,
     /*  682324 */     GIR_EraseRootFromParent_Done,
     /*  682325 */   // Label 10727: @682325
     /*  682325 */   GIM_Try, /*On fail goto*//*Label 10728*/ GIMT_Encode4(682382), // Rule ID 20976 //
     /*  682330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  682333 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682340 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682353 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
     /*  682356 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682380 */     GIR_RootConstrainSelectedInstOperands,
     /*  682381 */     // GIR_Coverage, 20976,
     /*  682381 */     GIR_EraseRootFromParent_Done,
     /*  682382 */   // Label 10728: @682382
     /*  682382 */   GIM_Try, /*On fail goto*//*Label 10729*/ GIMT_Encode4(682439), // Rule ID 20977 //
     /*  682387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  682390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682397 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682410 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
     /*  682413 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682437 */     GIR_RootConstrainSelectedInstOperands,
     /*  682438 */     // GIR_Coverage, 20977,
     /*  682438 */     GIR_EraseRootFromParent_Done,
     /*  682439 */   // Label 10729: @682439
     /*  682439 */   GIM_Try, /*On fail goto*//*Label 10730*/ GIMT_Encode4(682496), // Rule ID 20993 //
     /*  682444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  682447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682454 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682467 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
     /*  682470 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682494 */     GIR_RootConstrainSelectedInstOperands,
     /*  682495 */     // GIR_Coverage, 20993,
     /*  682495 */     GIR_EraseRootFromParent_Done,
     /*  682496 */   // Label 10730: @682496
     /*  682496 */   GIM_Try, /*On fail goto*//*Label 10731*/ GIMT_Encode4(682553), // Rule ID 20994 //
     /*  682501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  682504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682511 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682524 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
     /*  682527 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682551 */     GIR_RootConstrainSelectedInstOperands,
     /*  682552 */     // GIR_Coverage, 20994,
     /*  682552 */     GIR_EraseRootFromParent_Done,
     /*  682553 */   // Label 10731: @682553
     /*  682553 */   GIM_Try, /*On fail goto*//*Label 10732*/ GIMT_Encode4(682610), // Rule ID 20995 //
     /*  682558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  682561 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682568 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682581 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
     /*  682584 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682608 */     GIR_RootConstrainSelectedInstOperands,
     /*  682609 */     // GIR_Coverage, 20995,
     /*  682609 */     GIR_EraseRootFromParent_Done,
     /*  682610 */   // Label 10732: @682610
     /*  682610 */   GIM_Try, /*On fail goto*//*Label 10733*/ GIMT_Encode4(682667), // Rule ID 20996 //
     /*  682615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  682618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682625 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682638 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
     /*  682641 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682665 */     GIR_RootConstrainSelectedInstOperands,
     /*  682666 */     // GIR_Coverage, 20996,
     /*  682666 */     GIR_EraseRootFromParent_Done,
     /*  682667 */   // Label 10733: @682667
     /*  682667 */   GIM_Try, /*On fail goto*//*Label 10734*/ GIMT_Encode4(682724), // Rule ID 20997 //
     /*  682672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  682675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682682 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  682684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682695 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
     /*  682698 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  682718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682722 */     GIR_RootConstrainSelectedInstOperands,
     /*  682723 */     // GIR_Coverage, 20997,
     /*  682723 */     GIR_EraseRootFromParent_Done,
     /*  682724 */   // Label 10734: @682724
     /*  682724 */   GIM_Try, /*On fail goto*//*Label 10735*/ GIMT_Encode4(682785), // Rule ID 20963 //
     /*  682729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  682732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682754 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
     /*  682757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  682759 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682783 */     GIR_RootConstrainSelectedInstOperands,
     /*  682784 */     // GIR_Coverage, 20963,
     /*  682784 */     GIR_EraseRootFromParent_Done,
     /*  682785 */   // Label 10735: @682785
     /*  682785 */   GIM_Try, /*On fail goto*//*Label 10736*/ GIMT_Encode4(682846), // Rule ID 20964 //
     /*  682790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  682793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682815 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
     /*  682818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  682820 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682844 */     GIR_RootConstrainSelectedInstOperands,
     /*  682845 */     // GIR_Coverage, 20964,
     /*  682845 */     GIR_EraseRootFromParent_Done,
     /*  682846 */   // Label 10736: @682846
     /*  682846 */   GIM_Try, /*On fail goto*//*Label 10737*/ GIMT_Encode4(682907), // Rule ID 20965 //
     /*  682851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  682854 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682865 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682876 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
     /*  682879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  682881 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682905 */     GIR_RootConstrainSelectedInstOperands,
     /*  682906 */     // GIR_Coverage, 20965,
     /*  682906 */     GIR_EraseRootFromParent_Done,
     /*  682907 */   // Label 10737: @682907
     /*  682907 */   GIM_Try, /*On fail goto*//*Label 10738*/ GIMT_Encode4(682968), // Rule ID 20966 //
     /*  682912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  682915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682937 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
     /*  682940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  682942 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  682944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  682949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  682954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  682959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  682962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  682966 */     GIR_RootConstrainSelectedInstOperands,
     /*  682967 */     // GIR_Coverage, 20966,
     /*  682967 */     GIR_EraseRootFromParent_Done,
     /*  682968 */   // Label 10738: @682968
     /*  682968 */   GIM_Try, /*On fail goto*//*Label 10739*/ GIMT_Encode4(683029), // Rule ID 20967 //
     /*  682973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  682976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  682983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  682987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  682991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  682998 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  682998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
     /*  683001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  683003 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  683005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  683010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  683015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  683020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683027 */     GIR_RootConstrainSelectedInstOperands,
     /*  683028 */     // GIR_Coverage, 20967,
     /*  683028 */     GIR_EraseRootFromParent_Done,
     /*  683029 */   // Label 10739: @683029
     /*  683029 */   GIM_Try, /*On fail goto*//*Label 10740*/ GIMT_Encode4(683090), // Rule ID 20983 //
     /*  683034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  683037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  683044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  683048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  683059 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  683059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
     /*  683062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  683064 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  683066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  683071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  683076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  683081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683088 */     GIR_RootConstrainSelectedInstOperands,
     /*  683089 */     // GIR_Coverage, 20983,
     /*  683089 */     GIR_EraseRootFromParent_Done,
     /*  683090 */   // Label 10740: @683090
     /*  683090 */   GIM_Try, /*On fail goto*//*Label 10741*/ GIMT_Encode4(683151), // Rule ID 20984 //
     /*  683095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  683098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  683105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  683109 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  683120 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  683120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
     /*  683123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  683125 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  683127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  683132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  683137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  683142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683149 */     GIR_RootConstrainSelectedInstOperands,
     /*  683150 */     // GIR_Coverage, 20984,
     /*  683150 */     GIR_EraseRootFromParent_Done,
     /*  683151 */   // Label 10741: @683151
     /*  683151 */   GIM_Try, /*On fail goto*//*Label 10742*/ GIMT_Encode4(683212), // Rule ID 20985 //
     /*  683156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  683159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  683166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  683170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  683181 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  683181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
     /*  683184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  683186 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  683188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  683193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  683198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  683203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683210 */     GIR_RootConstrainSelectedInstOperands,
     /*  683211 */     // GIR_Coverage, 20985,
     /*  683211 */     GIR_EraseRootFromParent_Done,
     /*  683212 */   // Label 10742: @683212
     /*  683212 */   GIM_Try, /*On fail goto*//*Label 10743*/ GIMT_Encode4(683273), // Rule ID 20986 //
     /*  683217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  683220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  683227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  683231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  683242 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  683242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
     /*  683245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  683247 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  683249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  683254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  683259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  683264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683267 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683271 */     GIR_RootConstrainSelectedInstOperands,
     /*  683272 */     // GIR_Coverage, 20986,
     /*  683272 */     GIR_EraseRootFromParent_Done,
     /*  683273 */   // Label 10743: @683273
     /*  683273 */   GIM_Try, /*On fail goto*//*Label 10744*/ GIMT_Encode4(683334), // Rule ID 20987 //
     /*  683278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  683281 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  683288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  683292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  683303 */     // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  683303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
     /*  683306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  683308 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  683310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  683315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  683320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  683325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683328 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683332 */     GIR_RootConstrainSelectedInstOperands,
     /*  683333 */     // GIR_Coverage, 20987,
     /*  683333 */     GIR_EraseRootFromParent_Done,
     /*  683334 */   // Label 10744: @683334
     /*  683334 */   GIM_Try, /*On fail goto*//*Label 10745*/ GIMT_Encode4(683384), // Rule ID 30456 //
     /*  683339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  683342 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683347 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683360 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683368 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683382 */     GIR_RootConstrainSelectedInstOperands,
     /*  683383 */     // GIR_Coverage, 30456,
     /*  683383 */     GIR_EraseRootFromParent_Done,
     /*  683384 */   // Label 10745: @683384
     /*  683384 */   GIM_Try, /*On fail goto*//*Label 10746*/ GIMT_Encode4(683434), // Rule ID 30457 //
     /*  683389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  683392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683397 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683410 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683418 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683432 */     GIR_RootConstrainSelectedInstOperands,
     /*  683433 */     // GIR_Coverage, 30457,
     /*  683433 */     GIR_EraseRootFromParent_Done,
     /*  683434 */   // Label 10746: @683434
     /*  683434 */   GIM_Try, /*On fail goto*//*Label 10747*/ GIMT_Encode4(683484), // Rule ID 30458 //
     /*  683439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  683442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683447 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683460 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683468 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683482 */     GIR_RootConstrainSelectedInstOperands,
     /*  683483 */     // GIR_Coverage, 30458,
     /*  683483 */     GIR_EraseRootFromParent_Done,
     /*  683484 */   // Label 10747: @683484
     /*  683484 */   GIM_Try, /*On fail goto*//*Label 10748*/ GIMT_Encode4(683534), // Rule ID 30459 //
     /*  683489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  683492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683497 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683503 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683510 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683518 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683532 */     GIR_RootConstrainSelectedInstOperands,
     /*  683533 */     // GIR_Coverage, 30459,
     /*  683533 */     GIR_EraseRootFromParent_Done,
     /*  683534 */   // Label 10748: @683534
     /*  683534 */   GIM_Try, /*On fail goto*//*Label 10749*/ GIMT_Encode4(683584), // Rule ID 30460 //
     /*  683539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  683542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683547 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683560 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683568 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683582 */     GIR_RootConstrainSelectedInstOperands,
     /*  683583 */     // GIR_Coverage, 30460,
     /*  683583 */     GIR_EraseRootFromParent_Done,
     /*  683584 */   // Label 10749: @683584
     /*  683584 */   GIM_Try, /*On fail goto*//*Label 10750*/ GIMT_Encode4(683634), // Rule ID 30462 //
     /*  683589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  683592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683597 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683610 */     // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i32>>  =>  (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9),
     /*  683613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683618 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683632 */     GIR_RootConstrainSelectedInstOperands,
     /*  683633 */     // GIR_Coverage, 30462,
     /*  683633 */     GIR_EraseRootFromParent_Done,
     /*  683634 */   // Label 10750: @683634
     /*  683634 */   GIM_Try, /*On fail goto*//*Label 10751*/ GIMT_Encode4(683684), // Rule ID 30463 //
     /*  683639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  683642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683647 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683649 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683653 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683660 */     // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i32>>  =>  (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9),
     /*  683663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683668 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683682 */     GIR_RootConstrainSelectedInstOperands,
     /*  683683 */     // GIR_Coverage, 30463,
     /*  683683 */     GIR_EraseRootFromParent_Done,
     /*  683684 */   // Label 10751: @683684
     /*  683684 */   GIM_Try, /*On fail goto*//*Label 10752*/ GIMT_Encode4(683734), // Rule ID 30464 //
     /*  683689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  683692 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683697 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683710 */     // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i32>>  =>  (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9),
     /*  683713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683718 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683728 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683732 */     GIR_RootConstrainSelectedInstOperands,
     /*  683733 */     // GIR_Coverage, 30464,
     /*  683733 */     GIR_EraseRootFromParent_Done,
     /*  683734 */   // Label 10752: @683734
     /*  683734 */   GIM_Try, /*On fail goto*//*Label 10753*/ GIMT_Encode4(683784), // Rule ID 30465 //
     /*  683739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  683742 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683747 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683749 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683760 */     // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i32>>  =>  (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9),
     /*  683763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683768 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683782 */     GIR_RootConstrainSelectedInstOperands,
     /*  683783 */     // GIR_Coverage, 30465,
     /*  683783 */     GIR_EraseRootFromParent_Done,
     /*  683784 */   // Label 10753: @683784
     /*  683784 */   GIM_Try, /*On fail goto*//*Label 10754*/ GIMT_Encode4(683834), // Rule ID 30466 //
     /*  683789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  683792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  683797 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683810 */     // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i32>>  =>  (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  683810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9),
     /*  683813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683818 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  683828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683832 */     GIR_RootConstrainSelectedInstOperands,
     /*  683833 */     // GIR_Coverage, 30466,
     /*  683833 */     GIR_EraseRootFromParent_Done,
     /*  683834 */   // Label 10754: @683834
     /*  683834 */   GIM_Try, /*On fail goto*//*Label 10755*/ GIMT_Encode4(683884), // Rule ID 30468 //
     /*  683839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  683842 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  683847 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683849 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683860 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  683860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683868 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683878 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683882 */     GIR_RootConstrainSelectedInstOperands,
     /*  683883 */     // GIR_Coverage, 30468,
     /*  683883 */     GIR_EraseRootFromParent_Done,
     /*  683884 */   // Label 10755: @683884
     /*  683884 */   GIM_Try, /*On fail goto*//*Label 10756*/ GIMT_Encode4(683934), // Rule ID 30469 //
     /*  683889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  683892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  683897 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683910 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  683910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683918 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683932 */     GIR_RootConstrainSelectedInstOperands,
     /*  683933 */     // GIR_Coverage, 30469,
     /*  683933 */     GIR_EraseRootFromParent_Done,
     /*  683934 */   // Label 10756: @683934
     /*  683934 */   GIM_Try, /*On fail goto*//*Label 10757*/ GIMT_Encode4(683984), // Rule ID 30470 //
     /*  683939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  683942 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  683947 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683949 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  683953 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  683960 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  683960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  683963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  683968 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  683970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  683975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  683978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  683982 */     GIR_RootConstrainSelectedInstOperands,
     /*  683983 */     // GIR_Coverage, 30470,
     /*  683983 */     GIR_EraseRootFromParent_Done,
     /*  683984 */   // Label 10757: @683984
     /*  683984 */   GIM_Try, /*On fail goto*//*Label 10758*/ GIMT_Encode4(684034), // Rule ID 30471 //
     /*  683989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  683992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  683997 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  683999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  684010 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  684010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  684013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  684018 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  684020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  684028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684032 */     GIR_RootConstrainSelectedInstOperands,
     /*  684033 */     // GIR_Coverage, 30471,
     /*  684033 */     GIR_EraseRootFromParent_Done,
     /*  684034 */   // Label 10758: @684034
     /*  684034 */   GIM_Try, /*On fail goto*//*Label 10759*/ GIMT_Encode4(684084), // Rule ID 30472 //
     /*  684039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  684042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  684047 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  684060 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  684060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
     /*  684063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  684068 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  684070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  684078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684082 */     GIR_RootConstrainSelectedInstOperands,
     /*  684083 */     // GIR_Coverage, 30472,
     /*  684083 */     GIR_EraseRootFromParent_Done,
     /*  684084 */   // Label 10759: @684084
     /*  684084 */   GIM_Try, /*On fail goto*//*Label 10760*/ GIMT_Encode4(684138), // Rule ID 30455 //
     /*  684089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  684092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  684097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  684112 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i32>>  =>  (DS_MAX_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  684112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32),
     /*  684115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  684117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  684122 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  684124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684136 */     GIR_RootConstrainSelectedInstOperands,
     /*  684137 */     // GIR_Coverage, 30455,
     /*  684137 */     GIR_EraseRootFromParent_Done,
     /*  684138 */   // Label 10760: @684138
     /*  684138 */   GIM_Try, /*On fail goto*//*Label 10761*/ GIMT_Encode4(684192), // Rule ID 30461 //
     /*  684143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  684146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  684151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  684166 */     // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_i32>>  =>  (DS_MAX_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  684166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32_gfx9),
     /*  684169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  684171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  684176 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  684178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684186 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684190 */     GIR_RootConstrainSelectedInstOperands,
     /*  684191 */     // GIR_Coverage, 30461,
     /*  684191 */     GIR_EraseRootFromParent_Done,
     /*  684192 */   // Label 10761: @684192
     /*  684192 */   GIM_Try, /*On fail goto*//*Label 10762*/ GIMT_Encode4(684246), // Rule ID 30467 //
     /*  684197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  684200 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  684205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684209 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  684220 */     // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i32>>  =>  (DS_MAX_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  684220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32),
     /*  684223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  684225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  684230 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  684232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  684240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684244 */     GIR_RootConstrainSelectedInstOperands,
     /*  684245 */     // GIR_Coverage, 30467,
     /*  684245 */     GIR_EraseRootFromParent_Done,
     /*  684246 */   // Label 10762: @684246
     /*  684246 */   GIM_Try, /*On fail goto*//*Label 10763*/ GIMT_Encode4(684305), // Rule ID 12977 //
     /*  684251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  684254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684261 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  684274 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  684274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR),
     /*  684277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  684282 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  684289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  684294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  684299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684303 */     GIR_RootConstrainSelectedInstOperands,
     /*  684304 */     // GIR_Coverage, 12977,
     /*  684304 */     GIR_EraseRootFromParent_Done,
     /*  684305 */   // Label 10763: @684305
     /*  684305 */   GIM_Try, /*On fail goto*//*Label 10764*/ GIMT_Encode4(684364), // Rule ID 12978 //
     /*  684310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  684313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684320 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  684333 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  684333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR),
     /*  684336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  684341 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  684348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  684353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  684358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684362 */     GIR_RootConstrainSelectedInstOperands,
     /*  684363 */     // GIR_Coverage, 12978,
     /*  684363 */     GIR_EraseRootFromParent_Done,
     /*  684364 */   // Label 10764: @684364
     /*  684364 */   GIM_Try, /*On fail goto*//*Label 10765*/ GIMT_Encode4(684423), // Rule ID 12979 //
     /*  684369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  684372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  684392 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  684392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR),
     /*  684395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  684400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  684407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  684412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  684417 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684421 */     GIR_RootConstrainSelectedInstOperands,
     /*  684422 */     // GIR_Coverage, 12979,
     /*  684422 */     GIR_EraseRootFromParent_Done,
     /*  684423 */   // Label 10765: @684423
     /*  684423 */   GIM_Try, /*On fail goto*//*Label 10766*/ GIMT_Encode4(684482), // Rule ID 12980 //
     /*  684428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  684431 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684438 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  684451 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  684451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR),
     /*  684454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  684459 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  684466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  684471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  684476 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684480 */     GIR_RootConstrainSelectedInstOperands,
     /*  684481 */     // GIR_Coverage, 12980,
     /*  684481 */     GIR_EraseRootFromParent_Done,
     /*  684482 */   // Label 10766: @684482
     /*  684482 */   GIM_Try, /*On fail goto*//*Label 10767*/ GIMT_Encode4(684541), // Rule ID 12981 //
     /*  684487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  684490 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684497 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684503 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  684510 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  684510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR),
     /*  684513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  684518 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  684525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  684530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  684535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684539 */     GIR_RootConstrainSelectedInstOperands,
     /*  684540 */     // GIR_Coverage, 12981,
     /*  684540 */     GIR_EraseRootFromParent_Done,
     /*  684541 */   // Label 10767: @684541
     /*  684541 */   GIM_Try, /*On fail goto*//*Label 10768*/ GIMT_Encode4(684604), // Rule ID 12987 //
     /*  684546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  684549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  684571 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  684571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN),
     /*  684574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  684576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  684581 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  684588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  684593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  684598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684602 */     GIR_RootConstrainSelectedInstOperands,
     /*  684603 */     // GIR_Coverage, 12987,
     /*  684603 */     GIR_EraseRootFromParent_Done,
     /*  684604 */   // Label 10768: @684604
     /*  684604 */   GIM_Try, /*On fail goto*//*Label 10769*/ GIMT_Encode4(684656), // Rule ID 12972 //
     /*  684609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  684612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684619 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684632 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX),
     /*  684635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684640 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684654 */     GIR_RootConstrainSelectedInstOperands,
     /*  684655 */     // GIR_Coverage, 12972,
     /*  684655 */     GIR_EraseRootFromParent_Done,
     /*  684656 */   // Label 10769: @684656
     /*  684656 */   GIM_Try, /*On fail goto*//*Label 10770*/ GIMT_Encode4(684708), // Rule ID 12973 //
     /*  684661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  684664 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684671 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684684 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX),
     /*  684687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684692 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684702 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684706 */     GIR_RootConstrainSelectedInstOperands,
     /*  684707 */     // GIR_Coverage, 12973,
     /*  684707 */     GIR_EraseRootFromParent_Done,
     /*  684708 */   // Label 10770: @684708
     /*  684708 */   GIM_Try, /*On fail goto*//*Label 10771*/ GIMT_Encode4(684760), // Rule ID 12974 //
     /*  684713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  684716 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684723 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684736 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX),
     /*  684739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684744 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684758 */     GIR_RootConstrainSelectedInstOperands,
     /*  684759 */     // GIR_Coverage, 12974,
     /*  684759 */     GIR_EraseRootFromParent_Done,
     /*  684760 */   // Label 10771: @684760
     /*  684760 */   GIM_Try, /*On fail goto*//*Label 10772*/ GIMT_Encode4(684812), // Rule ID 12975 //
     /*  684765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  684768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684775 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684777 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684788 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX),
     /*  684791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684796 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684810 */     GIR_RootConstrainSelectedInstOperands,
     /*  684811 */     // GIR_Coverage, 12975,
     /*  684811 */     GIR_EraseRootFromParent_Done,
     /*  684812 */   // Label 10772: @684812
     /*  684812 */   GIM_Try, /*On fail goto*//*Label 10773*/ GIMT_Encode4(684864), // Rule ID 12976 //
     /*  684817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  684820 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684827 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  684829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684840 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX),
     /*  684843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684848 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  684858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684862 */     GIR_RootConstrainSelectedInstOperands,
     /*  684863 */     // GIR_Coverage, 12976,
     /*  684863 */     GIR_EraseRootFromParent_Done,
     /*  684864 */   // Label 10773: @684864
     /*  684864 */   GIM_Try, /*On fail goto*//*Label 10774*/ GIMT_Encode4(684920), // Rule ID 12982 //
     /*  684869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  684872 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684894 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN),
     /*  684897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  684899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684904 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  684914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684918 */     GIR_RootConstrainSelectedInstOperands,
     /*  684919 */     // GIR_Coverage, 12982,
     /*  684919 */     GIR_EraseRootFromParent_Done,
     /*  684920 */   // Label 10774: @684920
     /*  684920 */   GIM_Try, /*On fail goto*//*Label 10775*/ GIMT_Encode4(684976), // Rule ID 12983 //
     /*  684925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  684928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  684950 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  684950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN),
     /*  684953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  684955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  684960 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  684962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  684967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  684970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  684974 */     GIR_RootConstrainSelectedInstOperands,
     /*  684975 */     // GIR_Coverage, 12983,
     /*  684975 */     GIR_EraseRootFromParent_Done,
     /*  684976 */   // Label 10775: @684976
     /*  684976 */   GIM_Try, /*On fail goto*//*Label 10776*/ GIMT_Encode4(685032), // Rule ID 12984 //
     /*  684981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  684984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  684991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  684995 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  684999 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  685006 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  685006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN),
     /*  685009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  685011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  685016 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  685023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  685026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685030 */     GIR_RootConstrainSelectedInstOperands,
     /*  685031 */     // GIR_Coverage, 12984,
     /*  685031 */     GIR_EraseRootFromParent_Done,
     /*  685032 */   // Label 10776: @685032
     /*  685032 */   GIM_Try, /*On fail goto*//*Label 10777*/ GIMT_Encode4(685088), // Rule ID 12985 //
     /*  685037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  685040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  685051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  685062 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  685062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN),
     /*  685065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  685067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  685072 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  685079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  685082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685086 */     GIR_RootConstrainSelectedInstOperands,
     /*  685087 */     // GIR_Coverage, 12985,
     /*  685087 */     GIR_EraseRootFromParent_Done,
     /*  685088 */   // Label 10777: @685088
     /*  685088 */   GIM_Try, /*On fail goto*//*Label 10778*/ GIMT_Encode4(685144), // Rule ID 12986 //
     /*  685093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  685096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  685107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  685118 */     // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  685118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN),
     /*  685121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  685123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  685128 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  685135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  685138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685142 */     GIR_RootConstrainSelectedInstOperands,
     /*  685143 */     // GIR_Coverage, 12986,
     /*  685143 */     GIR_EraseRootFromParent_Done,
     /*  685144 */   // Label 10778: @685144
     /*  685144 */   GIM_Try, /*On fail goto*//*Label 10779*/ GIMT_Encode4(685204), // Rule ID 10577 //
     /*  685149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  685152 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685160 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685162 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685166 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685173 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685181 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685202 */     GIR_RootConstrainSelectedInstOperands,
     /*  685203 */     // GIR_Coverage, 10577,
     /*  685203 */     GIR_EraseRootFromParent_Done,
     /*  685204 */   // Label 10779: @685204
     /*  685204 */   GIM_Try, /*On fail goto*//*Label 10780*/ GIMT_Encode4(685264), // Rule ID 10578 //
     /*  685209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  685212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685220 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685233 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685241 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685262 */     GIR_RootConstrainSelectedInstOperands,
     /*  685263 */     // GIR_Coverage, 10578,
     /*  685263 */     GIR_EraseRootFromParent_Done,
     /*  685264 */   // Label 10780: @685264
     /*  685264 */   GIM_Try, /*On fail goto*//*Label 10781*/ GIMT_Encode4(685324), // Rule ID 10579 //
     /*  685269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  685272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685280 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685293 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685301 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685322 */     GIR_RootConstrainSelectedInstOperands,
     /*  685323 */     // GIR_Coverage, 10579,
     /*  685323 */     GIR_EraseRootFromParent_Done,
     /*  685324 */   // Label 10781: @685324
     /*  685324 */   GIM_Try, /*On fail goto*//*Label 10782*/ GIMT_Encode4(685384), // Rule ID 10580 //
     /*  685329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  685332 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685340 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685353 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685361 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685382 */     GIR_RootConstrainSelectedInstOperands,
     /*  685383 */     // GIR_Coverage, 10580,
     /*  685383 */     GIR_EraseRootFromParent_Done,
     /*  685384 */   // Label 10782: @685384
     /*  685384 */   GIM_Try, /*On fail goto*//*Label 10783*/ GIMT_Encode4(685444), // Rule ID 10581 //
     /*  685389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  685392 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685400 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685413 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685421 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685442 */     GIR_RootConstrainSelectedInstOperands,
     /*  685443 */     // GIR_Coverage, 10581,
     /*  685443 */     GIR_EraseRootFromParent_Done,
     /*  685444 */   // Label 10783: @685444
     /*  685444 */   GIM_Try, /*On fail goto*//*Label 10784*/ GIMT_Encode4(685503), // Rule ID 11133 //
     /*  685449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  685452 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685459 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685472 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685480 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685501 */     GIR_RootConstrainSelectedInstOperands,
     /*  685502 */     // GIR_Coverage, 11133,
     /*  685502 */     GIR_EraseRootFromParent_Done,
     /*  685503 */   // Label 10784: @685503
     /*  685503 */   GIM_Try, /*On fail goto*//*Label 10785*/ GIMT_Encode4(685562), // Rule ID 11134 //
     /*  685508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  685511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685518 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685531 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685539 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685560 */     GIR_RootConstrainSelectedInstOperands,
     /*  685561 */     // GIR_Coverage, 11134,
     /*  685561 */     GIR_EraseRootFromParent_Done,
     /*  685562 */   // Label 10785: @685562
     /*  685562 */   GIM_Try, /*On fail goto*//*Label 10786*/ GIMT_Encode4(685621), // Rule ID 11135 //
     /*  685567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  685570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685577 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685590 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685598 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685615 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685619 */     GIR_RootConstrainSelectedInstOperands,
     /*  685620 */     // GIR_Coverage, 11135,
     /*  685620 */     GIR_EraseRootFromParent_Done,
     /*  685621 */   // Label 10786: @685621
     /*  685621 */   GIM_Try, /*On fail goto*//*Label 10787*/ GIMT_Encode4(685680), // Rule ID 11136 //
     /*  685626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  685629 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685636 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685638 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685642 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685649 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685657 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685678 */     GIR_RootConstrainSelectedInstOperands,
     /*  685679 */     // GIR_Coverage, 11136,
     /*  685679 */     GIR_EraseRootFromParent_Done,
     /*  685680 */   // Label 10787: @685680
     /*  685680 */   GIM_Try, /*On fail goto*//*Label 10788*/ GIMT_Encode4(685739), // Rule ID 11137 //
     /*  685685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  685688 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685695 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685697 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  685708 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR),
     /*  685711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685716 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685737 */     GIR_RootConstrainSelectedInstOperands,
     /*  685738 */     // GIR_Coverage, 11137,
     /*  685738 */     GIR_EraseRootFromParent_Done,
     /*  685739 */   // Label 10788: @685739
     /*  685739 */   GIM_Try, /*On fail goto*//*Label 10789*/ GIMT_Encode4(685803), // Rule ID 10571 //
     /*  685744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  685747 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  685759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  685770 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR_RTN),
     /*  685773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  685775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685780 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685797 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685801 */     GIR_RootConstrainSelectedInstOperands,
     /*  685802 */     // GIR_Coverage, 10571,
     /*  685802 */     GIR_EraseRootFromParent_Done,
     /*  685803 */   // Label 10789: @685803
     /*  685803 */   GIM_Try, /*On fail goto*//*Label 10790*/ GIMT_Encode4(685866), // Rule ID 11127 //
     /*  685808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  685811 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  685822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  685833 */     // (atomic_load_umax:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (FLAT_ATOMIC_UMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  685833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_SADDR_RTN),
     /*  685836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  685838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  685843 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  685850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  685855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  685860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685864 */     GIR_RootConstrainSelectedInstOperands,
     /*  685865 */     // GIR_Coverage, 11127,
     /*  685865 */     GIR_EraseRootFromParent_Done,
     /*  685866 */   // Label 10790: @685866
     /*  685866 */   GIM_Try, /*On fail goto*//*Label 10791*/ GIMT_Encode4(685919), // Rule ID 10572 //
     /*  685871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  685874 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685882 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685884 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  685895 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  685895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  685898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  685903 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  685910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  685913 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685917 */     GIR_RootConstrainSelectedInstOperands,
     /*  685918 */     // GIR_Coverage, 10572,
     /*  685918 */     GIR_EraseRootFromParent_Done,
     /*  685919 */   // Label 10791: @685919
     /*  685919 */   GIM_Try, /*On fail goto*//*Label 10792*/ GIMT_Encode4(685972), // Rule ID 10573 //
     /*  685924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  685927 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685935 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  685948 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  685948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  685951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  685956 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  685958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  685963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  685966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  685970 */     GIR_RootConstrainSelectedInstOperands,
     /*  685971 */     // GIR_Coverage, 10573,
     /*  685971 */     GIR_EraseRootFromParent_Done,
     /*  685972 */   // Label 10792: @685972
     /*  685972 */   GIM_Try, /*On fail goto*//*Label 10793*/ GIMT_Encode4(686025), // Rule ID 10574 //
     /*  685977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  685980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  685988 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  685990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  685994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686001 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686009 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686023 */     GIR_RootConstrainSelectedInstOperands,
     /*  686024 */     // GIR_Coverage, 10574,
     /*  686024 */     GIR_EraseRootFromParent_Done,
     /*  686025 */   // Label 10793: @686025
     /*  686025 */   GIM_Try, /*On fail goto*//*Label 10794*/ GIMT_Encode4(686078), // Rule ID 10575 //
     /*  686030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  686033 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686041 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686043 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686054 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686062 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686076 */     GIR_RootConstrainSelectedInstOperands,
     /*  686077 */     // GIR_Coverage, 10575,
     /*  686077 */     GIR_EraseRootFromParent_Done,
     /*  686078 */   // Label 10794: @686078
     /*  686078 */   GIM_Try, /*On fail goto*//*Label 10795*/ GIMT_Encode4(686131), // Rule ID 10576 //
     /*  686083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  686086 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686094 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686096 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686100 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686107 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686115 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686125 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686129 */     GIR_RootConstrainSelectedInstOperands,
     /*  686130 */     // GIR_Coverage, 10576,
     /*  686130 */     GIR_EraseRootFromParent_Done,
     /*  686131 */   // Label 10795: @686131
     /*  686131 */   GIM_Try, /*On fail goto*//*Label 10796*/ GIMT_Encode4(686183), // Rule ID 11128 //
     /*  686136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  686139 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686146 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686152 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686159 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686167 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686181 */     GIR_RootConstrainSelectedInstOperands,
     /*  686182 */     // GIR_Coverage, 11128,
     /*  686182 */     GIR_EraseRootFromParent_Done,
     /*  686183 */   // Label 10796: @686183
     /*  686183 */   GIM_Try, /*On fail goto*//*Label 10797*/ GIMT_Encode4(686235), // Rule ID 11129 //
     /*  686188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  686191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686198 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686200 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686211 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686219 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686233 */     GIR_RootConstrainSelectedInstOperands,
     /*  686234 */     // GIR_Coverage, 11129,
     /*  686234 */     GIR_EraseRootFromParent_Done,
     /*  686235 */   // Label 10797: @686235
     /*  686235 */   GIM_Try, /*On fail goto*//*Label 10798*/ GIMT_Encode4(686287), // Rule ID 11130 //
     /*  686240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  686243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686250 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686263 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686271 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686281 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686285 */     GIR_RootConstrainSelectedInstOperands,
     /*  686286 */     // GIR_Coverage, 11130,
     /*  686286 */     GIR_EraseRootFromParent_Done,
     /*  686287 */   // Label 10798: @686287
     /*  686287 */   GIM_Try, /*On fail goto*//*Label 10799*/ GIMT_Encode4(686339), // Rule ID 11131 //
     /*  686292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  686295 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686302 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686304 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686308 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686315 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686323 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686337 */     GIR_RootConstrainSelectedInstOperands,
     /*  686338 */     // GIR_Coverage, 11131,
     /*  686338 */     GIR_EraseRootFromParent_Done,
     /*  686339 */   // Label 10799: @686339
     /*  686339 */   GIM_Try, /*On fail goto*//*Label 10800*/ GIMT_Encode4(686391), // Rule ID 11132 //
     /*  686344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  686347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686354 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686367 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>>  =>  (FLAT_ATOMIC_UMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
     /*  686370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686375 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  686385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686389 */     GIR_RootConstrainSelectedInstOperands,
     /*  686390 */     // GIR_Coverage, 11132,
     /*  686390 */     GIR_EraseRootFromParent_Done,
     /*  686391 */   // Label 10800: @686391
     /*  686391 */   GIM_Try, /*On fail goto*//*Label 10801*/ GIMT_Encode4(686448), // Rule ID 10566 //
     /*  686396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  686399 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686422 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686432 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686446 */     GIR_RootConstrainSelectedInstOperands,
     /*  686447 */     // GIR_Coverage, 10566,
     /*  686447 */     GIR_EraseRootFromParent_Done,
     /*  686448 */   // Label 10801: @686448
     /*  686448 */   GIM_Try, /*On fail goto*//*Label 10802*/ GIMT_Encode4(686505), // Rule ID 10567 //
     /*  686453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  686456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686479 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686489 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686503 */     GIR_RootConstrainSelectedInstOperands,
     /*  686504 */     // GIR_Coverage, 10567,
     /*  686504 */     GIR_EraseRootFromParent_Done,
     /*  686505 */   // Label 10802: @686505
     /*  686505 */   GIM_Try, /*On fail goto*//*Label 10803*/ GIMT_Encode4(686562), // Rule ID 10568 //
     /*  686510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  686513 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686525 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686529 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686536 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686546 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686560 */     GIR_RootConstrainSelectedInstOperands,
     /*  686561 */     // GIR_Coverage, 10568,
     /*  686561 */     GIR_EraseRootFromParent_Done,
     /*  686562 */   // Label 10803: @686562
     /*  686562 */   GIM_Try, /*On fail goto*//*Label 10804*/ GIMT_Encode4(686619), // Rule ID 10569 //
     /*  686567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  686570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686582 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686593 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686603 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686617 */     GIR_RootConstrainSelectedInstOperands,
     /*  686618 */     // GIR_Coverage, 10569,
     /*  686618 */     GIR_EraseRootFromParent_Done,
     /*  686619 */   // Label 10804: @686619
     /*  686619 */   GIM_Try, /*On fail goto*//*Label 10805*/ GIMT_Encode4(686676), // Rule ID 10570 //
     /*  686624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  686627 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686650 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686660 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686674 */     GIR_RootConstrainSelectedInstOperands,
     /*  686675 */     // GIR_Coverage, 10570,
     /*  686675 */     GIR_EraseRootFromParent_Done,
     /*  686676 */   // Label 10805: @686676
     /*  686676 */   GIM_Try, /*On fail goto*//*Label 10806*/ GIMT_Encode4(686732), // Rule ID 11122 //
     /*  686681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  686684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686706 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686716 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686730 */     GIR_RootConstrainSelectedInstOperands,
     /*  686731 */     // GIR_Coverage, 11122,
     /*  686731 */     GIR_EraseRootFromParent_Done,
     /*  686732 */   // Label 10806: @686732
     /*  686732 */   GIM_Try, /*On fail goto*//*Label 10807*/ GIMT_Encode4(686788), // Rule ID 11123 //
     /*  686737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  686740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686762 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686772 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686786 */     GIR_RootConstrainSelectedInstOperands,
     /*  686787 */     // GIR_Coverage, 11123,
     /*  686787 */     GIR_EraseRootFromParent_Done,
     /*  686788 */   // Label 10807: @686788
     /*  686788 */   GIM_Try, /*On fail goto*//*Label 10808*/ GIMT_Encode4(686844), // Rule ID 11124 //
     /*  686793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  686796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686818 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686828 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686842 */     GIR_RootConstrainSelectedInstOperands,
     /*  686843 */     // GIR_Coverage, 11124,
     /*  686843 */     GIR_EraseRootFromParent_Done,
     /*  686844 */   // Label 10808: @686844
     /*  686844 */   GIM_Try, /*On fail goto*//*Label 10809*/ GIMT_Encode4(686900), // Rule ID 11125 //
     /*  686849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  686852 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686874 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686884 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686898 */     GIR_RootConstrainSelectedInstOperands,
     /*  686899 */     // GIR_Coverage, 11125,
     /*  686899 */     GIR_EraseRootFromParent_Done,
     /*  686900 */   // Label 10809: @686900
     /*  686900 */   GIM_Try, /*On fail goto*//*Label 10810*/ GIMT_Encode4(686956), // Rule ID 11126 //
     /*  686905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  686908 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  686919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  686930 */     // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  686930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
     /*  686933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  686935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  686940 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  686942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  686947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  686950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  686954 */     GIR_RootConstrainSelectedInstOperands,
     /*  686955 */     // GIR_Coverage, 11126,
     /*  686955 */     GIR_EraseRootFromParent_Done,
     /*  686956 */   // Label 10810: @686956
     /*  686956 */   GIM_Reject,
     /*  686957 */ // Label 10704: @686957
     /*  686957 */ GIM_Reject,
     /*  686958 */ // Label 10702: @686958
     /*  686958 */ GIM_Try, /*On fail goto*//*Label 10811*/ GIMT_Encode4(694457),
     /*  686963 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  686966 */   GIM_Try, /*On fail goto*//*Label 10812*/ GIMT_Encode4(687028), // Rule ID 21458 //
     /*  686971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  686974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  686981 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  686983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  686987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  686994 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  686994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64),
     /*  686997 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  686999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687026 */     GIR_RootConstrainSelectedInstOperands,
     /*  687027 */     // GIR_Coverage, 21458,
     /*  687027 */     GIR_EraseRootFromParent_Done,
     /*  687028 */   // Label 10812: @687028
     /*  687028 */   GIM_Try, /*On fail goto*//*Label 10813*/ GIMT_Encode4(687090), // Rule ID 21459 //
     /*  687033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  687036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687043 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687056 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64),
     /*  687059 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687088 */     GIR_RootConstrainSelectedInstOperands,
     /*  687089 */     // GIR_Coverage, 21459,
     /*  687089 */     GIR_EraseRootFromParent_Done,
     /*  687090 */   // Label 10813: @687090
     /*  687090 */   GIM_Try, /*On fail goto*//*Label 10814*/ GIMT_Encode4(687152), // Rule ID 21460 //
     /*  687095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  687098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687105 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687118 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64),
     /*  687121 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687150 */     GIR_RootConstrainSelectedInstOperands,
     /*  687151 */     // GIR_Coverage, 21460,
     /*  687151 */     GIR_EraseRootFromParent_Done,
     /*  687152 */   // Label 10814: @687152
     /*  687152 */   GIM_Try, /*On fail goto*//*Label 10815*/ GIMT_Encode4(687214), // Rule ID 21461 //
     /*  687157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  687160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687167 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687180 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64),
     /*  687183 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687212 */     GIR_RootConstrainSelectedInstOperands,
     /*  687213 */     // GIR_Coverage, 21461,
     /*  687213 */     GIR_EraseRootFromParent_Done,
     /*  687214 */   // Label 10815: @687214
     /*  687214 */   GIM_Try, /*On fail goto*//*Label 10816*/ GIMT_Encode4(687276), // Rule ID 21462 //
     /*  687219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  687222 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687229 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687242 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64),
     /*  687245 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687274 */     GIR_RootConstrainSelectedInstOperands,
     /*  687275 */     // GIR_Coverage, 21462,
     /*  687275 */     GIR_EraseRootFromParent_Done,
     /*  687276 */   // Label 10816: @687276
     /*  687276 */   GIM_Try, /*On fail goto*//*Label 10817*/ GIMT_Encode4(687338), // Rule ID 21478 //
     /*  687281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  687284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687291 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687304 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64),
     /*  687307 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687336 */     GIR_RootConstrainSelectedInstOperands,
     /*  687337 */     // GIR_Coverage, 21478,
     /*  687337 */     GIR_EraseRootFromParent_Done,
     /*  687338 */   // Label 10817: @687338
     /*  687338 */   GIM_Try, /*On fail goto*//*Label 10818*/ GIMT_Encode4(687400), // Rule ID 21479 //
     /*  687343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  687346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687353 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687366 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64),
     /*  687369 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687398 */     GIR_RootConstrainSelectedInstOperands,
     /*  687399 */     // GIR_Coverage, 21479,
     /*  687399 */     GIR_EraseRootFromParent_Done,
     /*  687400 */   // Label 10818: @687400
     /*  687400 */   GIM_Try, /*On fail goto*//*Label 10819*/ GIMT_Encode4(687462), // Rule ID 21480 //
     /*  687405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  687408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687415 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687428 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64),
     /*  687431 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687460 */     GIR_RootConstrainSelectedInstOperands,
     /*  687461 */     // GIR_Coverage, 21480,
     /*  687461 */     GIR_EraseRootFromParent_Done,
     /*  687462 */   // Label 10819: @687462
     /*  687462 */   GIM_Try, /*On fail goto*//*Label 10820*/ GIMT_Encode4(687524), // Rule ID 21481 //
     /*  687467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  687470 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687477 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687490 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64),
     /*  687493 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687522 */     GIR_RootConstrainSelectedInstOperands,
     /*  687523 */     // GIR_Coverage, 21481,
     /*  687523 */     GIR_EraseRootFromParent_Done,
     /*  687524 */   // Label 10820: @687524
     /*  687524 */   GIM_Try, /*On fail goto*//*Label 10821*/ GIMT_Encode4(687586), // Rule ID 21482 //
     /*  687529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  687532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687539 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  687541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687552 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64),
     /*  687555 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  687580 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687584 */     GIR_RootConstrainSelectedInstOperands,
     /*  687585 */     // GIR_Coverage, 21482,
     /*  687585 */     GIR_EraseRootFromParent_Done,
     /*  687586 */   // Label 10821: @687586
     /*  687586 */   GIM_Try, /*On fail goto*//*Label 10822*/ GIMT_Encode4(687652), // Rule ID 21448 //
     /*  687591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  687594 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  687605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687616 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN),
     /*  687619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  687621 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  687646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687650 */     GIR_RootConstrainSelectedInstOperands,
     /*  687651 */     // GIR_Coverage, 21448,
     /*  687651 */     GIR_EraseRootFromParent_Done,
     /*  687652 */   // Label 10822: @687652
     /*  687652 */   GIM_Try, /*On fail goto*//*Label 10823*/ GIMT_Encode4(687718), // Rule ID 21449 //
     /*  687657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  687660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  687671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687682 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN),
     /*  687685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  687687 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  687712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687716 */     GIR_RootConstrainSelectedInstOperands,
     /*  687717 */     // GIR_Coverage, 21449,
     /*  687717 */     GIR_EraseRootFromParent_Done,
     /*  687718 */   // Label 10823: @687718
     /*  687718 */   GIM_Try, /*On fail goto*//*Label 10824*/ GIMT_Encode4(687784), // Rule ID 21450 //
     /*  687723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  687726 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  687737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687748 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN),
     /*  687751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  687753 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  687778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687782 */     GIR_RootConstrainSelectedInstOperands,
     /*  687783 */     // GIR_Coverage, 21450,
     /*  687783 */     GIR_EraseRootFromParent_Done,
     /*  687784 */   // Label 10824: @687784
     /*  687784 */   GIM_Try, /*On fail goto*//*Label 10825*/ GIMT_Encode4(687850), // Rule ID 21451 //
     /*  687789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  687792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  687803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687814 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN),
     /*  687817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  687819 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  687844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687848 */     GIR_RootConstrainSelectedInstOperands,
     /*  687849 */     // GIR_Coverage, 21451,
     /*  687849 */     GIR_EraseRootFromParent_Done,
     /*  687850 */   // Label 10825: @687850
     /*  687850 */   GIM_Try, /*On fail goto*//*Label 10826*/ GIMT_Encode4(687916), // Rule ID 21452 //
     /*  687855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  687858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  687869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687880 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN),
     /*  687883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  687885 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  687910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687914 */     GIR_RootConstrainSelectedInstOperands,
     /*  687915 */     // GIR_Coverage, 21452,
     /*  687915 */     GIR_EraseRootFromParent_Done,
     /*  687916 */   // Label 10826: @687916
     /*  687916 */   GIM_Try, /*On fail goto*//*Label 10827*/ GIMT_Encode4(687982), // Rule ID 21468 //
     /*  687921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  687924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  687935 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  687939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  687946 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  687946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN),
     /*  687949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  687951 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  687953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  687958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  687963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  687968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  687973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  687976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  687980 */     GIR_RootConstrainSelectedInstOperands,
     /*  687981 */     // GIR_Coverage, 21468,
     /*  687981 */     GIR_EraseRootFromParent_Done,
     /*  687982 */   // Label 10827: @687982
     /*  687982 */   GIM_Try, /*On fail goto*//*Label 10828*/ GIMT_Encode4(688048), // Rule ID 21469 //
     /*  687987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  687990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  687997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  688012 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN),
     /*  688015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688017 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  688024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  688034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  688039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688046 */     GIR_RootConstrainSelectedInstOperands,
     /*  688047 */     // GIR_Coverage, 21469,
     /*  688047 */     GIR_EraseRootFromParent_Done,
     /*  688048 */   // Label 10828: @688048
     /*  688048 */   GIM_Try, /*On fail goto*//*Label 10829*/ GIMT_Encode4(688114), // Rule ID 21470 //
     /*  688053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  688056 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  688078 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN),
     /*  688081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688083 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  688090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  688100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  688105 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688112 */     GIR_RootConstrainSelectedInstOperands,
     /*  688113 */     // GIR_Coverage, 21470,
     /*  688113 */     GIR_EraseRootFromParent_Done,
     /*  688114 */   // Label 10829: @688114
     /*  688114 */   GIM_Try, /*On fail goto*//*Label 10830*/ GIMT_Encode4(688180), // Rule ID 21471 //
     /*  688119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  688122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  688144 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN),
     /*  688147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688149 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  688156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  688166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  688171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688178 */     GIR_RootConstrainSelectedInstOperands,
     /*  688179 */     // GIR_Coverage, 21471,
     /*  688179 */     GIR_EraseRootFromParent_Done,
     /*  688180 */   // Label 10830: @688180
     /*  688180 */   GIM_Try, /*On fail goto*//*Label 10831*/ GIMT_Encode4(688246), // Rule ID 21472 //
     /*  688185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  688188 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  688210 */     // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN),
     /*  688213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688215 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  688222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  688232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  688237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688244 */     GIR_RootConstrainSelectedInstOperands,
     /*  688245 */     // GIR_Coverage, 21472,
     /*  688245 */     GIR_EraseRootFromParent_Done,
     /*  688246 */   // Label 10831: @688246
     /*  688246 */   GIM_Try, /*On fail goto*//*Label 10832*/ GIMT_Encode4(688303), // Rule ID 21453 //
     /*  688251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  688254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688261 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688274 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
     /*  688277 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688301 */     GIR_RootConstrainSelectedInstOperands,
     /*  688302 */     // GIR_Coverage, 21453,
     /*  688302 */     GIR_EraseRootFromParent_Done,
     /*  688303 */   // Label 10832: @688303
     /*  688303 */   GIM_Try, /*On fail goto*//*Label 10833*/ GIMT_Encode4(688360), // Rule ID 21454 //
     /*  688308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  688311 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688318 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688320 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688324 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688331 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
     /*  688334 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688354 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688358 */     GIR_RootConstrainSelectedInstOperands,
     /*  688359 */     // GIR_Coverage, 21454,
     /*  688359 */     GIR_EraseRootFromParent_Done,
     /*  688360 */   // Label 10833: @688360
     /*  688360 */   GIM_Try, /*On fail goto*//*Label 10834*/ GIMT_Encode4(688417), // Rule ID 21455 //
     /*  688365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  688368 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688375 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688388 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
     /*  688391 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688415 */     GIR_RootConstrainSelectedInstOperands,
     /*  688416 */     // GIR_Coverage, 21455,
     /*  688416 */     GIR_EraseRootFromParent_Done,
     /*  688417 */   // Label 10834: @688417
     /*  688417 */   GIM_Try, /*On fail goto*//*Label 10835*/ GIMT_Encode4(688474), // Rule ID 21456 //
     /*  688422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  688425 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688432 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688445 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
     /*  688448 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688472 */     GIR_RootConstrainSelectedInstOperands,
     /*  688473 */     // GIR_Coverage, 21456,
     /*  688473 */     GIR_EraseRootFromParent_Done,
     /*  688474 */   // Label 10835: @688474
     /*  688474 */   GIM_Try, /*On fail goto*//*Label 10836*/ GIMT_Encode4(688531), // Rule ID 21457 //
     /*  688479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  688482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688489 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688502 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
     /*  688505 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688529 */     GIR_RootConstrainSelectedInstOperands,
     /*  688530 */     // GIR_Coverage, 21457,
     /*  688530 */     GIR_EraseRootFromParent_Done,
     /*  688531 */   // Label 10836: @688531
     /*  688531 */   GIM_Try, /*On fail goto*//*Label 10837*/ GIMT_Encode4(688588), // Rule ID 21473 //
     /*  688536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  688539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688546 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688559 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
     /*  688562 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688586 */     GIR_RootConstrainSelectedInstOperands,
     /*  688587 */     // GIR_Coverage, 21473,
     /*  688587 */     GIR_EraseRootFromParent_Done,
     /*  688588 */   // Label 10837: @688588
     /*  688588 */   GIM_Try, /*On fail goto*//*Label 10838*/ GIMT_Encode4(688645), // Rule ID 21474 //
     /*  688593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  688596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688603 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688605 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688616 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
     /*  688619 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688639 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688643 */     GIR_RootConstrainSelectedInstOperands,
     /*  688644 */     // GIR_Coverage, 21474,
     /*  688644 */     GIR_EraseRootFromParent_Done,
     /*  688645 */   // Label 10838: @688645
     /*  688645 */   GIM_Try, /*On fail goto*//*Label 10839*/ GIMT_Encode4(688702), // Rule ID 21475 //
     /*  688650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  688653 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688660 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688673 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
     /*  688676 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688700 */     GIR_RootConstrainSelectedInstOperands,
     /*  688701 */     // GIR_Coverage, 21475,
     /*  688701 */     GIR_EraseRootFromParent_Done,
     /*  688702 */   // Label 10839: @688702
     /*  688702 */   GIM_Try, /*On fail goto*//*Label 10840*/ GIMT_Encode4(688759), // Rule ID 21476 //
     /*  688707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  688710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688717 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688730 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
     /*  688733 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688757 */     GIR_RootConstrainSelectedInstOperands,
     /*  688758 */     // GIR_Coverage, 21476,
     /*  688758 */     GIR_EraseRootFromParent_Done,
     /*  688759 */   // Label 10840: @688759
     /*  688759 */   GIM_Try, /*On fail goto*//*Label 10841*/ GIMT_Encode4(688816), // Rule ID 21477 //
     /*  688764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  688767 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688774 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  688776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688787 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
     /*  688790 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  688810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688814 */     GIR_RootConstrainSelectedInstOperands,
     /*  688815 */     // GIR_Coverage, 21477,
     /*  688815 */     GIR_EraseRootFromParent_Done,
     /*  688816 */   // Label 10841: @688816
     /*  688816 */   GIM_Try, /*On fail goto*//*Label 10842*/ GIMT_Encode4(688877), // Rule ID 21443 //
     /*  688821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  688824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688846 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
     /*  688849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688851 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688871 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688875 */     GIR_RootConstrainSelectedInstOperands,
     /*  688876 */     // GIR_Coverage, 21443,
     /*  688876 */     GIR_EraseRootFromParent_Done,
     /*  688877 */   // Label 10842: @688877
     /*  688877 */   GIM_Try, /*On fail goto*//*Label 10843*/ GIMT_Encode4(688938), // Rule ID 21444 //
     /*  688882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  688885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688900 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688907 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
     /*  688910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688912 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688936 */     GIR_RootConstrainSelectedInstOperands,
     /*  688937 */     // GIR_Coverage, 21444,
     /*  688937 */     GIR_EraseRootFromParent_Done,
     /*  688938 */   // Label 10843: @688938
     /*  688938 */   GIM_Try, /*On fail goto*//*Label 10844*/ GIMT_Encode4(688999), // Rule ID 21445 //
     /*  688943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  688946 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  688953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  688957 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  688961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  688968 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  688968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
     /*  688971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  688973 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  688975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  688980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  688985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  688990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  688993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  688997 */     GIR_RootConstrainSelectedInstOperands,
     /*  688998 */     // GIR_Coverage, 21445,
     /*  688998 */     GIR_EraseRootFromParent_Done,
     /*  688999 */   // Label 10844: @688999
     /*  688999 */   GIM_Try, /*On fail goto*//*Label 10845*/ GIMT_Encode4(689060), // Rule ID 21446 //
     /*  689004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  689007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689029 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
     /*  689032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689034 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689058 */     GIR_RootConstrainSelectedInstOperands,
     /*  689059 */     // GIR_Coverage, 21446,
     /*  689059 */     GIR_EraseRootFromParent_Done,
     /*  689060 */   // Label 10845: @689060
     /*  689060 */   GIM_Try, /*On fail goto*//*Label 10846*/ GIMT_Encode4(689121), // Rule ID 21447 //
     /*  689065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  689068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689090 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
     /*  689093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689095 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689115 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689119 */     GIR_RootConstrainSelectedInstOperands,
     /*  689120 */     // GIR_Coverage, 21447,
     /*  689120 */     GIR_EraseRootFromParent_Done,
     /*  689121 */   // Label 10846: @689121
     /*  689121 */   GIM_Try, /*On fail goto*//*Label 10847*/ GIMT_Encode4(689182), // Rule ID 21463 //
     /*  689126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  689129 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689151 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
     /*  689154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689156 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689173 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689176 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689180 */     GIR_RootConstrainSelectedInstOperands,
     /*  689181 */     // GIR_Coverage, 21463,
     /*  689181 */     GIR_EraseRootFromParent_Done,
     /*  689182 */   // Label 10847: @689182
     /*  689182 */   GIM_Try, /*On fail goto*//*Label 10848*/ GIMT_Encode4(689243), // Rule ID 21464 //
     /*  689187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  689190 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689212 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
     /*  689215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689217 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689241 */     GIR_RootConstrainSelectedInstOperands,
     /*  689242 */     // GIR_Coverage, 21464,
     /*  689242 */     GIR_EraseRootFromParent_Done,
     /*  689243 */   // Label 10848: @689243
     /*  689243 */   GIM_Try, /*On fail goto*//*Label 10849*/ GIMT_Encode4(689304), // Rule ID 21465 //
     /*  689248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  689251 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689262 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689266 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689273 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
     /*  689276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689278 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689302 */     GIR_RootConstrainSelectedInstOperands,
     /*  689303 */     // GIR_Coverage, 21465,
     /*  689303 */     GIR_EraseRootFromParent_Done,
     /*  689304 */   // Label 10849: @689304
     /*  689304 */   GIM_Try, /*On fail goto*//*Label 10850*/ GIMT_Encode4(689365), // Rule ID 21466 //
     /*  689309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  689312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689334 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
     /*  689337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689339 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689363 */     GIR_RootConstrainSelectedInstOperands,
     /*  689364 */     // GIR_Coverage, 21466,
     /*  689364 */     GIR_EraseRootFromParent_Done,
     /*  689365 */   // Label 10850: @689365
     /*  689365 */   GIM_Try, /*On fail goto*//*Label 10851*/ GIMT_Encode4(689426), // Rule ID 21467 //
     /*  689370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  689373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  689380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  689384 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  689395 */     // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  689395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
     /*  689398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  689400 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  689402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  689407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  689412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  689417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689420 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689424 */     GIR_RootConstrainSelectedInstOperands,
     /*  689425 */     // GIR_Coverage, 21467,
     /*  689425 */     GIR_EraseRootFromParent_Done,
     /*  689426 */   // Label 10851: @689426
     /*  689426 */   GIM_Try, /*On fail goto*//*Label 10852*/ GIMT_Encode4(689476), // Rule ID 30865 //
     /*  689431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  689434 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689439 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689452 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  689455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689460 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689474 */     GIR_RootConstrainSelectedInstOperands,
     /*  689475 */     // GIR_Coverage, 30865,
     /*  689475 */     GIR_EraseRootFromParent_Done,
     /*  689476 */   // Label 10852: @689476
     /*  689476 */   GIM_Try, /*On fail goto*//*Label 10853*/ GIMT_Encode4(689526), // Rule ID 30866 //
     /*  689481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  689484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689489 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689502 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  689505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689510 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689524 */     GIR_RootConstrainSelectedInstOperands,
     /*  689525 */     // GIR_Coverage, 30866,
     /*  689525 */     GIR_EraseRootFromParent_Done,
     /*  689526 */   // Label 10853: @689526
     /*  689526 */   GIM_Try, /*On fail goto*//*Label 10854*/ GIMT_Encode4(689576), // Rule ID 30867 //
     /*  689531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  689534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689539 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689552 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  689555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689560 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689574 */     GIR_RootConstrainSelectedInstOperands,
     /*  689575 */     // GIR_Coverage, 30867,
     /*  689575 */     GIR_EraseRootFromParent_Done,
     /*  689576 */   // Label 10854: @689576
     /*  689576 */   GIM_Try, /*On fail goto*//*Label 10855*/ GIMT_Encode4(689626), // Rule ID 30868 //
     /*  689581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  689584 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689589 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689602 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  689605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689610 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689624 */     GIR_RootConstrainSelectedInstOperands,
     /*  689625 */     // GIR_Coverage, 30868,
     /*  689625 */     GIR_EraseRootFromParent_Done,
     /*  689626 */   // Label 10855: @689626
     /*  689626 */   GIM_Try, /*On fail goto*//*Label 10856*/ GIMT_Encode4(689676), // Rule ID 30869 //
     /*  689631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  689634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689639 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689641 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689645 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689652 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  689655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689660 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689674 */     GIR_RootConstrainSelectedInstOperands,
     /*  689675 */     // GIR_Coverage, 30869,
     /*  689675 */     GIR_EraseRootFromParent_Done,
     /*  689676 */   // Label 10856: @689676
     /*  689676 */   GIM_Try, /*On fail goto*//*Label 10857*/ GIMT_Encode4(689726), // Rule ID 30875 //
     /*  689681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  689684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689689 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689702 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i64>>  =>  (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9),
     /*  689705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689710 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689724 */     GIR_RootConstrainSelectedInstOperands,
     /*  689725 */     // GIR_Coverage, 30875,
     /*  689725 */     GIR_EraseRootFromParent_Done,
     /*  689726 */   // Label 10857: @689726
     /*  689726 */   GIM_Try, /*On fail goto*//*Label 10858*/ GIMT_Encode4(689776), // Rule ID 30876 //
     /*  689731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  689734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689739 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689741 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689752 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i64>>  =>  (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9),
     /*  689755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689760 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689774 */     GIR_RootConstrainSelectedInstOperands,
     /*  689775 */     // GIR_Coverage, 30876,
     /*  689775 */     GIR_EraseRootFromParent_Done,
     /*  689776 */   // Label 10858: @689776
     /*  689776 */   GIM_Try, /*On fail goto*//*Label 10859*/ GIMT_Encode4(689826), // Rule ID 30877 //
     /*  689781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  689784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689789 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689791 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689802 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i64>>  =>  (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9),
     /*  689805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689810 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689824 */     GIR_RootConstrainSelectedInstOperands,
     /*  689825 */     // GIR_Coverage, 30877,
     /*  689825 */     GIR_EraseRootFromParent_Done,
     /*  689826 */   // Label 10859: @689826
     /*  689826 */   GIM_Try, /*On fail goto*//*Label 10860*/ GIMT_Encode4(689876), // Rule ID 30878 //
     /*  689831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  689834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689839 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689852 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i64>>  =>  (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9),
     /*  689855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689860 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689874 */     GIR_RootConstrainSelectedInstOperands,
     /*  689875 */     // GIR_Coverage, 30878,
     /*  689875 */     GIR_EraseRootFromParent_Done,
     /*  689876 */   // Label 10860: @689876
     /*  689876 */   GIM_Try, /*On fail goto*//*Label 10861*/ GIMT_Encode4(689926), // Rule ID 30879 //
     /*  689881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  689884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  689889 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689902 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i64>>  =>  (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  689902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9),
     /*  689905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689910 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  689920 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689924 */     GIR_RootConstrainSelectedInstOperands,
     /*  689925 */     // GIR_Coverage, 30879,
     /*  689925 */     GIR_EraseRootFromParent_Done,
     /*  689926 */   // Label 10861: @689926
     /*  689926 */   GIM_Try, /*On fail goto*//*Label 10862*/ GIMT_Encode4(689976), // Rule ID 30885 //
     /*  689931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  689934 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  689939 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689941 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  689952 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  689952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  689955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  689960 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  689962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  689967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  689970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  689974 */     GIR_RootConstrainSelectedInstOperands,
     /*  689975 */     // GIR_Coverage, 30885,
     /*  689975 */     GIR_EraseRootFromParent_Done,
     /*  689976 */   // Label 10862: @689976
     /*  689976 */   GIM_Try, /*On fail goto*//*Label 10863*/ GIMT_Encode4(690026), // Rule ID 30886 //
     /*  689981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  689984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  689989 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  689991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  689995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690002 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  690005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690010 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690024 */     GIR_RootConstrainSelectedInstOperands,
     /*  690025 */     // GIR_Coverage, 30886,
     /*  690025 */     GIR_EraseRootFromParent_Done,
     /*  690026 */   // Label 10863: @690026
     /*  690026 */   GIM_Try, /*On fail goto*//*Label 10864*/ GIMT_Encode4(690076), // Rule ID 30887 //
     /*  690031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  690034 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690039 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  690041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690052 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  690055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690060 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690074 */     GIR_RootConstrainSelectedInstOperands,
     /*  690075 */     // GIR_Coverage, 30887,
     /*  690075 */     GIR_EraseRootFromParent_Done,
     /*  690076 */   // Label 10864: @690076
     /*  690076 */   GIM_Try, /*On fail goto*//*Label 10865*/ GIMT_Encode4(690126), // Rule ID 30888 //
     /*  690081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  690084 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690089 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  690091 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690102 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  690105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690110 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690120 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690124 */     GIR_RootConstrainSelectedInstOperands,
     /*  690125 */     // GIR_Coverage, 30888,
     /*  690125 */     GIR_EraseRootFromParent_Done,
     /*  690126 */   // Label 10865: @690126
     /*  690126 */   GIM_Try, /*On fail goto*//*Label 10866*/ GIMT_Encode4(690176), // Rule ID 30889 //
     /*  690131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  690134 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690139 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  690141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690152 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
     /*  690155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690160 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690174 */     GIR_RootConstrainSelectedInstOperands,
     /*  690175 */     // GIR_Coverage, 30889,
     /*  690175 */     GIR_EraseRootFromParent_Done,
     /*  690176 */   // Label 10866: @690176
     /*  690176 */   GIM_Try, /*On fail goto*//*Label 10867*/ GIMT_Encode4(690230), // Rule ID 30860 //
     /*  690181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  690184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690204 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690214 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690228 */     GIR_RootConstrainSelectedInstOperands,
     /*  690229 */     // GIR_Coverage, 30860,
     /*  690229 */     GIR_EraseRootFromParent_Done,
     /*  690230 */   // Label 10867: @690230
     /*  690230 */   GIM_Try, /*On fail goto*//*Label 10868*/ GIMT_Encode4(690284), // Rule ID 30861 //
     /*  690235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  690238 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690258 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690268 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690282 */     GIR_RootConstrainSelectedInstOperands,
     /*  690283 */     // GIR_Coverage, 30861,
     /*  690283 */     GIR_EraseRootFromParent_Done,
     /*  690284 */   // Label 10868: @690284
     /*  690284 */   GIM_Try, /*On fail goto*//*Label 10869*/ GIMT_Encode4(690338), // Rule ID 30862 //
     /*  690289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  690292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690312 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690322 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690336 */     GIR_RootConstrainSelectedInstOperands,
     /*  690337 */     // GIR_Coverage, 30862,
     /*  690337 */     GIR_EraseRootFromParent_Done,
     /*  690338 */   // Label 10869: @690338
     /*  690338 */   GIM_Try, /*On fail goto*//*Label 10870*/ GIMT_Encode4(690392), // Rule ID 30863 //
     /*  690343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  690346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690366 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690376 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690390 */     GIR_RootConstrainSelectedInstOperands,
     /*  690391 */     // GIR_Coverage, 30863,
     /*  690391 */     GIR_EraseRootFromParent_Done,
     /*  690392 */   // Label 10870: @690392
     /*  690392 */   GIM_Try, /*On fail goto*//*Label 10871*/ GIMT_Encode4(690446), // Rule ID 30864 //
     /*  690397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  690400 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690409 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690420 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690430 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690444 */     GIR_RootConstrainSelectedInstOperands,
     /*  690445 */     // GIR_Coverage, 30864,
     /*  690445 */     GIR_EraseRootFromParent_Done,
     /*  690446 */   // Label 10871: @690446
     /*  690446 */   GIM_Try, /*On fail goto*//*Label 10872*/ GIMT_Encode4(690500), // Rule ID 30870 //
     /*  690451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  690454 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690474 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_i64>>  =>  (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9),
     /*  690477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690484 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690498 */     GIR_RootConstrainSelectedInstOperands,
     /*  690499 */     // GIR_Coverage, 30870,
     /*  690499 */     GIR_EraseRootFromParent_Done,
     /*  690500 */   // Label 10872: @690500
     /*  690500 */   GIM_Try, /*On fail goto*//*Label 10873*/ GIMT_Encode4(690554), // Rule ID 30871 //
     /*  690505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  690508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690528 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_i64>>  =>  (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9),
     /*  690531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690538 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690552 */     GIR_RootConstrainSelectedInstOperands,
     /*  690553 */     // GIR_Coverage, 30871,
     /*  690553 */     GIR_EraseRootFromParent_Done,
     /*  690554 */   // Label 10873: @690554
     /*  690554 */   GIM_Try, /*On fail goto*//*Label 10874*/ GIMT_Encode4(690608), // Rule ID 30872 //
     /*  690559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  690562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690582 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_i64>>  =>  (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9),
     /*  690585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690592 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690606 */     GIR_RootConstrainSelectedInstOperands,
     /*  690607 */     // GIR_Coverage, 30872,
     /*  690607 */     GIR_EraseRootFromParent_Done,
     /*  690608 */   // Label 10874: @690608
     /*  690608 */   GIM_Try, /*On fail goto*//*Label 10875*/ GIMT_Encode4(690662), // Rule ID 30873 //
     /*  690613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  690616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690636 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_i64>>  =>  (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9),
     /*  690639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690646 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690656 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690660 */     GIR_RootConstrainSelectedInstOperands,
     /*  690661 */     // GIR_Coverage, 30873,
     /*  690661 */     GIR_EraseRootFromParent_Done,
     /*  690662 */   // Label 10875: @690662
     /*  690662 */   GIM_Try, /*On fail goto*//*Label 10876*/ GIMT_Encode4(690716), // Rule ID 30874 //
     /*  690667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  690670 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  690675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690679 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690683 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690690 */     // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_i64>>  =>  (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  690690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9),
     /*  690693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690700 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  690710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690714 */     GIR_RootConstrainSelectedInstOperands,
     /*  690715 */     // GIR_Coverage, 30874,
     /*  690715 */     GIR_EraseRootFromParent_Done,
     /*  690716 */   // Label 10876: @690716
     /*  690716 */   GIM_Try, /*On fail goto*//*Label 10877*/ GIMT_Encode4(690770), // Rule ID 30880 //
     /*  690721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  690724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690744 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690754 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690764 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690768 */     GIR_RootConstrainSelectedInstOperands,
     /*  690769 */     // GIR_Coverage, 30880,
     /*  690769 */     GIR_EraseRootFromParent_Done,
     /*  690770 */   // Label 10877: @690770
     /*  690770 */   GIM_Try, /*On fail goto*//*Label 10878*/ GIMT_Encode4(690824), // Rule ID 30881 //
     /*  690775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  690778 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690787 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690791 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690798 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690808 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690822 */     GIR_RootConstrainSelectedInstOperands,
     /*  690823 */     // GIR_Coverage, 30881,
     /*  690823 */     GIR_EraseRootFromParent_Done,
     /*  690824 */   // Label 10878: @690824
     /*  690824 */   GIM_Try, /*On fail goto*//*Label 10879*/ GIMT_Encode4(690878), // Rule ID 30882 //
     /*  690829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  690832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690852 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690862 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690876 */     GIR_RootConstrainSelectedInstOperands,
     /*  690877 */     // GIR_Coverage, 30882,
     /*  690877 */     GIR_EraseRootFromParent_Done,
     /*  690878 */   // Label 10879: @690878
     /*  690878 */   GIM_Try, /*On fail goto*//*Label 10880*/ GIMT_Encode4(690932), // Rule ID 30883 //
     /*  690883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  690886 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690899 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690906 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690916 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690930 */     GIR_RootConstrainSelectedInstOperands,
     /*  690931 */     // GIR_Coverage, 30883,
     /*  690931 */     GIR_EraseRootFromParent_Done,
     /*  690932 */   // Label 10880: @690932
     /*  690932 */   GIM_Try, /*On fail goto*//*Label 10881*/ GIMT_Encode4(690986), // Rule ID 30884 //
     /*  690937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  690940 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  690945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  690949 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  690953 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  690960 */     // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  690960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
     /*  690963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  690965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  690970 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  690972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  690977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  690980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  690984 */     GIR_RootConstrainSelectedInstOperands,
     /*  690985 */     // GIR_Coverage, 30884,
     /*  690985 */     GIR_EraseRootFromParent_Done,
     /*  690986 */   // Label 10881: @690986
     /*  690986 */   GIM_Try, /*On fail goto*//*Label 10882*/ GIMT_Encode4(691045), // Rule ID 13225 //
     /*  690991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  690994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691001 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  691014 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR),
     /*  691017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691022 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691043 */     GIR_RootConstrainSelectedInstOperands,
     /*  691044 */     // GIR_Coverage, 13225,
     /*  691044 */     GIR_EraseRootFromParent_Done,
     /*  691045 */   // Label 10882: @691045
     /*  691045 */   GIM_Try, /*On fail goto*//*Label 10883*/ GIMT_Encode4(691104), // Rule ID 13226 //
     /*  691050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  691053 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691060 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  691073 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR),
     /*  691076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691081 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691102 */     GIR_RootConstrainSelectedInstOperands,
     /*  691103 */     // GIR_Coverage, 13226,
     /*  691103 */     GIR_EraseRootFromParent_Done,
     /*  691104 */   // Label 10883: @691104
     /*  691104 */   GIM_Try, /*On fail goto*//*Label 10884*/ GIMT_Encode4(691163), // Rule ID 13227 //
     /*  691109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  691112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691119 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  691132 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR),
     /*  691135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691140 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691161 */     GIR_RootConstrainSelectedInstOperands,
     /*  691162 */     // GIR_Coverage, 13227,
     /*  691162 */     GIR_EraseRootFromParent_Done,
     /*  691163 */   // Label 10884: @691163
     /*  691163 */   GIM_Try, /*On fail goto*//*Label 10885*/ GIMT_Encode4(691222), // Rule ID 13228 //
     /*  691168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  691171 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691178 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  691191 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR),
     /*  691194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691199 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691220 */     GIR_RootConstrainSelectedInstOperands,
     /*  691221 */     // GIR_Coverage, 13228,
     /*  691221 */     GIR_EraseRootFromParent_Done,
     /*  691222 */   // Label 10885: @691222
     /*  691222 */   GIM_Try, /*On fail goto*//*Label 10886*/ GIMT_Encode4(691281), // Rule ID 13229 //
     /*  691227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  691230 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691237 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691239 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  691250 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR),
     /*  691253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691258 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691279 */     GIR_RootConstrainSelectedInstOperands,
     /*  691280 */     // GIR_Coverage, 13229,
     /*  691280 */     GIR_EraseRootFromParent_Done,
     /*  691281 */   // Label 10886: @691281
     /*  691281 */   GIM_Try, /*On fail goto*//*Label 10887*/ GIMT_Encode4(691344), // Rule ID 13235 //
     /*  691286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  691289 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  691311 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  691314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691321 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691342 */     GIR_RootConstrainSelectedInstOperands,
     /*  691343 */     // GIR_Coverage, 13235,
     /*  691343 */     GIR_EraseRootFromParent_Done,
     /*  691344 */   // Label 10887: @691344
     /*  691344 */   GIM_Try, /*On fail goto*//*Label 10888*/ GIMT_Encode4(691407), // Rule ID 13236 //
     /*  691349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  691352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  691374 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  691377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691384 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691405 */     GIR_RootConstrainSelectedInstOperands,
     /*  691406 */     // GIR_Coverage, 13236,
     /*  691406 */     GIR_EraseRootFromParent_Done,
     /*  691407 */   // Label 10888: @691407
     /*  691407 */   GIM_Try, /*On fail goto*//*Label 10889*/ GIMT_Encode4(691470), // Rule ID 13237 //
     /*  691412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  691415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  691437 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  691440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691447 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691464 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691468 */     GIR_RootConstrainSelectedInstOperands,
     /*  691469 */     // GIR_Coverage, 13237,
     /*  691469 */     GIR_EraseRootFromParent_Done,
     /*  691470 */   // Label 10889: @691470
     /*  691470 */   GIM_Try, /*On fail goto*//*Label 10890*/ GIMT_Encode4(691533), // Rule ID 13238 //
     /*  691475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  691478 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  691500 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  691503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691510 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691531 */     GIR_RootConstrainSelectedInstOperands,
     /*  691532 */     // GIR_Coverage, 13238,
     /*  691532 */     GIR_EraseRootFromParent_Done,
     /*  691533 */   // Label 10890: @691533
     /*  691533 */   GIM_Try, /*On fail goto*//*Label 10891*/ GIMT_Encode4(691596), // Rule ID 13239 //
     /*  691538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  691541 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  691563 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  691563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  691566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  691573 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  691580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  691585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  691590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691594 */     GIR_RootConstrainSelectedInstOperands,
     /*  691595 */     // GIR_Coverage, 13239,
     /*  691595 */     GIR_EraseRootFromParent_Done,
     /*  691596 */   // Label 10891: @691596
     /*  691596 */   GIM_Try, /*On fail goto*//*Label 10892*/ GIMT_Encode4(691648), // Rule ID 13220 //
     /*  691601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  691604 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691611 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691624 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2),
     /*  691627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691632 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  691642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691646 */     GIR_RootConstrainSelectedInstOperands,
     /*  691647 */     // GIR_Coverage, 13220,
     /*  691647 */     GIR_EraseRootFromParent_Done,
     /*  691648 */   // Label 10892: @691648
     /*  691648 */   GIM_Try, /*On fail goto*//*Label 10893*/ GIMT_Encode4(691700), // Rule ID 13221 //
     /*  691653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  691656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691663 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691676 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2),
     /*  691679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691684 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  691694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691698 */     GIR_RootConstrainSelectedInstOperands,
     /*  691699 */     // GIR_Coverage, 13221,
     /*  691699 */     GIR_EraseRootFromParent_Done,
     /*  691700 */   // Label 10893: @691700
     /*  691700 */   GIM_Try, /*On fail goto*//*Label 10894*/ GIMT_Encode4(691752), // Rule ID 13222 //
     /*  691705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  691708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691715 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691728 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2),
     /*  691731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691736 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  691746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691750 */     GIR_RootConstrainSelectedInstOperands,
     /*  691751 */     // GIR_Coverage, 13222,
     /*  691751 */     GIR_EraseRootFromParent_Done,
     /*  691752 */   // Label 10894: @691752
     /*  691752 */   GIM_Try, /*On fail goto*//*Label 10895*/ GIMT_Encode4(691804), // Rule ID 13223 //
     /*  691757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  691760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691780 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2),
     /*  691783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691788 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  691798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691802 */     GIR_RootConstrainSelectedInstOperands,
     /*  691803 */     // GIR_Coverage, 13223,
     /*  691803 */     GIR_EraseRootFromParent_Done,
     /*  691804 */   // Label 10895: @691804
     /*  691804 */   GIM_Try, /*On fail goto*//*Label 10896*/ GIMT_Encode4(691856), // Rule ID 13224 //
     /*  691809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  691812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691819 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  691821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691832 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2),
     /*  691835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691840 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  691850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691854 */     GIR_RootConstrainSelectedInstOperands,
     /*  691855 */     // GIR_Coverage, 13224,
     /*  691855 */     GIR_EraseRootFromParent_Done,
     /*  691856 */   // Label 10896: @691856
     /*  691856 */   GIM_Try, /*On fail goto*//*Label 10897*/ GIMT_Encode4(691912), // Rule ID 13230 //
     /*  691861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  691864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691886 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN),
     /*  691889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691896 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  691906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691910 */     GIR_RootConstrainSelectedInstOperands,
     /*  691911 */     // GIR_Coverage, 13230,
     /*  691911 */     GIR_EraseRootFromParent_Done,
     /*  691912 */   // Label 10897: @691912
     /*  691912 */   GIM_Try, /*On fail goto*//*Label 10898*/ GIMT_Encode4(691968), // Rule ID 13231 //
     /*  691917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  691920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691942 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN),
     /*  691945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  691947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  691952 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  691954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  691959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  691962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  691966 */     GIR_RootConstrainSelectedInstOperands,
     /*  691967 */     // GIR_Coverage, 13231,
     /*  691967 */     GIR_EraseRootFromParent_Done,
     /*  691968 */   // Label 10898: @691968
     /*  691968 */   GIM_Try, /*On fail goto*//*Label 10899*/ GIMT_Encode4(692024), // Rule ID 13232 //
     /*  691973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  691976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  691983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  691987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  691991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  691998 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  691998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN),
     /*  692001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  692008 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  692015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  692018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692022 */     GIR_RootConstrainSelectedInstOperands,
     /*  692023 */     // GIR_Coverage, 13232,
     /*  692023 */     GIR_EraseRootFromParent_Done,
     /*  692024 */   // Label 10899: @692024
     /*  692024 */   GIM_Try, /*On fail goto*//*Label 10900*/ GIMT_Encode4(692080), // Rule ID 13233 //
     /*  692029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  692032 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  692043 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  692054 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  692054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN),
     /*  692057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  692064 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  692071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  692074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692078 */     GIR_RootConstrainSelectedInstOperands,
     /*  692079 */     // GIR_Coverage, 13233,
     /*  692079 */     GIR_EraseRootFromParent_Done,
     /*  692080 */   // Label 10900: @692080
     /*  692080 */   GIM_Try, /*On fail goto*//*Label 10901*/ GIMT_Encode4(692136), // Rule ID 13234 //
     /*  692085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  692088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  692099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  692110 */     // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  692110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN),
     /*  692113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  692120 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  692127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  692130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692134 */     GIR_RootConstrainSelectedInstOperands,
     /*  692135 */     // GIR_Coverage, 13234,
     /*  692135 */     GIR_EraseRootFromParent_Done,
     /*  692136 */   // Label 10901: @692136
     /*  692136 */   GIM_Try, /*On fail goto*//*Label 10902*/ GIMT_Encode4(692196), // Rule ID 10817 //
     /*  692141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  692144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692152 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692165 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692173 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692194 */     GIR_RootConstrainSelectedInstOperands,
     /*  692195 */     // GIR_Coverage, 10817,
     /*  692195 */     GIR_EraseRootFromParent_Done,
     /*  692196 */   // Label 10902: @692196
     /*  692196 */   GIM_Try, /*On fail goto*//*Label 10903*/ GIMT_Encode4(692256), // Rule ID 10818 //
     /*  692201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  692204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692212 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692225 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692233 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692254 */     GIR_RootConstrainSelectedInstOperands,
     /*  692255 */     // GIR_Coverage, 10818,
     /*  692255 */     GIR_EraseRootFromParent_Done,
     /*  692256 */   // Label 10903: @692256
     /*  692256 */   GIM_Try, /*On fail goto*//*Label 10904*/ GIMT_Encode4(692316), // Rule ID 10819 //
     /*  692261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  692264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692272 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692285 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692293 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692310 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692314 */     GIR_RootConstrainSelectedInstOperands,
     /*  692315 */     // GIR_Coverage, 10819,
     /*  692315 */     GIR_EraseRootFromParent_Done,
     /*  692316 */   // Label 10904: @692316
     /*  692316 */   GIM_Try, /*On fail goto*//*Label 10905*/ GIMT_Encode4(692376), // Rule ID 10820 //
     /*  692321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  692324 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692332 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692334 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692345 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692353 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692374 */     GIR_RootConstrainSelectedInstOperands,
     /*  692375 */     // GIR_Coverage, 10820,
     /*  692375 */     GIR_EraseRootFromParent_Done,
     /*  692376 */   // Label 10905: @692376
     /*  692376 */   GIM_Try, /*On fail goto*//*Label 10906*/ GIMT_Encode4(692436), // Rule ID 10821 //
     /*  692381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  692384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692392 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692394 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692398 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692405 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692413 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692434 */     GIR_RootConstrainSelectedInstOperands,
     /*  692435 */     // GIR_Coverage, 10821,
     /*  692435 */     GIR_EraseRootFromParent_Done,
     /*  692436 */   // Label 10906: @692436
     /*  692436 */   GIM_Try, /*On fail goto*//*Label 10907*/ GIMT_Encode4(692495), // Rule ID 11373 //
     /*  692441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  692444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692451 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692464 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692472 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692489 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692493 */     GIR_RootConstrainSelectedInstOperands,
     /*  692494 */     // GIR_Coverage, 11373,
     /*  692494 */     GIR_EraseRootFromParent_Done,
     /*  692495 */   // Label 10907: @692495
     /*  692495 */   GIM_Try, /*On fail goto*//*Label 10908*/ GIMT_Encode4(692554), // Rule ID 11374 //
     /*  692500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  692503 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692510 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692512 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692516 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692523 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692531 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692552 */     GIR_RootConstrainSelectedInstOperands,
     /*  692553 */     // GIR_Coverage, 11374,
     /*  692553 */     GIR_EraseRootFromParent_Done,
     /*  692554 */   // Label 10908: @692554
     /*  692554 */   GIM_Try, /*On fail goto*//*Label 10909*/ GIMT_Encode4(692613), // Rule ID 11375 //
     /*  692559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  692562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692569 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692582 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692590 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692611 */     GIR_RootConstrainSelectedInstOperands,
     /*  692612 */     // GIR_Coverage, 11375,
     /*  692612 */     GIR_EraseRootFromParent_Done,
     /*  692613 */   // Label 10909: @692613
     /*  692613 */   GIM_Try, /*On fail goto*//*Label 10910*/ GIMT_Encode4(692672), // Rule ID 11376 //
     /*  692618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  692621 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692628 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692630 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692641 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692649 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692670 */     GIR_RootConstrainSelectedInstOperands,
     /*  692671 */     // GIR_Coverage, 11376,
     /*  692671 */     GIR_EraseRootFromParent_Done,
     /*  692672 */   // Label 10910: @692672
     /*  692672 */   GIM_Try, /*On fail goto*//*Label 10911*/ GIMT_Encode4(692731), // Rule ID 11377 //
     /*  692677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  692680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692687 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  692689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  692700 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR),
     /*  692703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692708 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692729 */     GIR_RootConstrainSelectedInstOperands,
     /*  692730 */     // GIR_Coverage, 11377,
     /*  692730 */     GIR_EraseRootFromParent_Done,
     /*  692731 */   // Label 10911: @692731
     /*  692731 */   GIM_Try, /*On fail goto*//*Label 10912*/ GIMT_Encode4(692795), // Rule ID 10807 //
     /*  692736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  692739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  692751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  692762 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  692765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692772 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692793 */     GIR_RootConstrainSelectedInstOperands,
     /*  692794 */     // GIR_Coverage, 10807,
     /*  692794 */     GIR_EraseRootFromParent_Done,
     /*  692795 */   // Label 10912: @692795
     /*  692795 */   GIM_Try, /*On fail goto*//*Label 10913*/ GIMT_Encode4(692859), // Rule ID 10808 //
     /*  692800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  692803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  692815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  692826 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  692829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692836 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692853 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692857 */     GIR_RootConstrainSelectedInstOperands,
     /*  692858 */     // GIR_Coverage, 10808,
     /*  692858 */     GIR_EraseRootFromParent_Done,
     /*  692859 */   // Label 10913: @692859
     /*  692859 */   GIM_Try, /*On fail goto*//*Label 10914*/ GIMT_Encode4(692923), // Rule ID 10809 //
     /*  692864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  692867 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  692879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692883 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  692890 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  692893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692900 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692917 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692921 */     GIR_RootConstrainSelectedInstOperands,
     /*  692922 */     // GIR_Coverage, 10809,
     /*  692922 */     GIR_EraseRootFromParent_Done,
     /*  692923 */   // Label 10914: @692923
     /*  692923 */   GIM_Try, /*On fail goto*//*Label 10915*/ GIMT_Encode4(692987), // Rule ID 10810 //
     /*  692928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  692931 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  692939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  692943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  692947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  692954 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  692954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  692957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  692959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  692964 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  692966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  692971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  692976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  692981 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  692985 */     GIR_RootConstrainSelectedInstOperands,
     /*  692986 */     // GIR_Coverage, 10810,
     /*  692986 */     GIR_EraseRootFromParent_Done,
     /*  692987 */   // Label 10915: @692987
     /*  692987 */   GIM_Try, /*On fail goto*//*Label 10916*/ GIMT_Encode4(693051), // Rule ID 10811 //
     /*  692992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  692995 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  693018 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  693018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  693021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  693028 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  693035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  693040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  693045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693049 */     GIR_RootConstrainSelectedInstOperands,
     /*  693050 */     // GIR_Coverage, 10811,
     /*  693050 */     GIR_EraseRootFromParent_Done,
     /*  693051 */   // Label 10916: @693051
     /*  693051 */   GIM_Try, /*On fail goto*//*Label 10917*/ GIMT_Encode4(693114), // Rule ID 11363 //
     /*  693056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  693059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  693081 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  693081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  693084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  693091 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  693098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  693103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  693108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693112 */     GIR_RootConstrainSelectedInstOperands,
     /*  693113 */     // GIR_Coverage, 11363,
     /*  693113 */     GIR_EraseRootFromParent_Done,
     /*  693114 */   // Label 10917: @693114
     /*  693114 */   GIM_Try, /*On fail goto*//*Label 10918*/ GIMT_Encode4(693177), // Rule ID 11364 //
     /*  693119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  693122 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  693144 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  693144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  693147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  693154 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  693161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  693166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  693171 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693175 */     GIR_RootConstrainSelectedInstOperands,
     /*  693176 */     // GIR_Coverage, 11364,
     /*  693176 */     GIR_EraseRootFromParent_Done,
     /*  693177 */   // Label 10918: @693177
     /*  693177 */   GIM_Try, /*On fail goto*//*Label 10919*/ GIMT_Encode4(693240), // Rule ID 11365 //
     /*  693182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  693185 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693200 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  693207 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  693207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  693210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  693217 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  693224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  693229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  693234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693238 */     GIR_RootConstrainSelectedInstOperands,
     /*  693239 */     // GIR_Coverage, 11365,
     /*  693239 */     GIR_EraseRootFromParent_Done,
     /*  693240 */   // Label 10919: @693240
     /*  693240 */   GIM_Try, /*On fail goto*//*Label 10920*/ GIMT_Encode4(693303), // Rule ID 11366 //
     /*  693245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  693248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  693270 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  693270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  693273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  693280 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  693287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  693292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  693297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693301 */     GIR_RootConstrainSelectedInstOperands,
     /*  693302 */     // GIR_Coverage, 11366,
     /*  693302 */     GIR_EraseRootFromParent_Done,
     /*  693303 */   // Label 10920: @693303
     /*  693303 */   GIM_Try, /*On fail goto*//*Label 10921*/ GIMT_Encode4(693366), // Rule ID 11367 //
     /*  693308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  693311 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  693333 */     // (atomic_load_umax:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  693333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_SADDR_RTN),
     /*  693336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  693343 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  693350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  693355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  693360 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693364 */     GIR_RootConstrainSelectedInstOperands,
     /*  693365 */     // GIR_Coverage, 11367,
     /*  693365 */     GIR_EraseRootFromParent_Done,
     /*  693366 */   // Label 10921: @693366
     /*  693366 */   GIM_Try, /*On fail goto*//*Label 10922*/ GIMT_Encode4(693419), // Rule ID 10812 //
     /*  693371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  693374 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693382 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693384 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693395 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693403 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693413 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693417 */     GIR_RootConstrainSelectedInstOperands,
     /*  693418 */     // GIR_Coverage, 10812,
     /*  693418 */     GIR_EraseRootFromParent_Done,
     /*  693419 */   // Label 10922: @693419
     /*  693419 */   GIM_Try, /*On fail goto*//*Label 10923*/ GIMT_Encode4(693472), // Rule ID 10813 //
     /*  693424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  693427 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693435 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693448 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693456 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693470 */     GIR_RootConstrainSelectedInstOperands,
     /*  693471 */     // GIR_Coverage, 10813,
     /*  693471 */     GIR_EraseRootFromParent_Done,
     /*  693472 */   // Label 10923: @693472
     /*  693472 */   GIM_Try, /*On fail goto*//*Label 10924*/ GIMT_Encode4(693525), // Rule ID 10814 //
     /*  693477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  693480 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693488 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693501 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693509 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693523 */     GIR_RootConstrainSelectedInstOperands,
     /*  693524 */     // GIR_Coverage, 10814,
     /*  693524 */     GIR_EraseRootFromParent_Done,
     /*  693525 */   // Label 10924: @693525
     /*  693525 */   GIM_Try, /*On fail goto*//*Label 10925*/ GIMT_Encode4(693578), // Rule ID 10815 //
     /*  693530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  693533 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693541 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693554 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693562 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693576 */     GIR_RootConstrainSelectedInstOperands,
     /*  693577 */     // GIR_Coverage, 10815,
     /*  693577 */     GIR_EraseRootFromParent_Done,
     /*  693578 */   // Label 10925: @693578
     /*  693578 */   GIM_Try, /*On fail goto*//*Label 10926*/ GIMT_Encode4(693631), // Rule ID 10816 //
     /*  693583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  693586 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693594 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693596 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693607 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693615 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693625 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693629 */     GIR_RootConstrainSelectedInstOperands,
     /*  693630 */     // GIR_Coverage, 10816,
     /*  693630 */     GIR_EraseRootFromParent_Done,
     /*  693631 */   // Label 10926: @693631
     /*  693631 */   GIM_Try, /*On fail goto*//*Label 10927*/ GIMT_Encode4(693683), // Rule ID 11368 //
     /*  693636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  693639 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693646 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693648 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693659 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693667 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693681 */     GIR_RootConstrainSelectedInstOperands,
     /*  693682 */     // GIR_Coverage, 11368,
     /*  693682 */     GIR_EraseRootFromParent_Done,
     /*  693683 */   // Label 10927: @693683
     /*  693683 */   GIM_Try, /*On fail goto*//*Label 10928*/ GIMT_Encode4(693735), // Rule ID 11369 //
     /*  693688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  693691 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693698 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693711 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693719 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693733 */     GIR_RootConstrainSelectedInstOperands,
     /*  693734 */     // GIR_Coverage, 11369,
     /*  693734 */     GIR_EraseRootFromParent_Done,
     /*  693735 */   // Label 10928: @693735
     /*  693735 */   GIM_Try, /*On fail goto*//*Label 10929*/ GIMT_Encode4(693787), // Rule ID 11370 //
     /*  693740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  693743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693750 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693763 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693771 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693785 */     GIR_RootConstrainSelectedInstOperands,
     /*  693786 */     // GIR_Coverage, 11370,
     /*  693786 */     GIR_EraseRootFromParent_Done,
     /*  693787 */   // Label 10929: @693787
     /*  693787 */   GIM_Try, /*On fail goto*//*Label 10930*/ GIMT_Encode4(693839), // Rule ID 11371 //
     /*  693792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  693795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693802 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693815 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693823 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693837 */     GIR_RootConstrainSelectedInstOperands,
     /*  693838 */     // GIR_Coverage, 11371,
     /*  693838 */     GIR_EraseRootFromParent_Done,
     /*  693839 */   // Label 10930: @693839
     /*  693839 */   GIM_Try, /*On fail goto*//*Label 10931*/ GIMT_Encode4(693891), // Rule ID 11372 //
     /*  693844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  693847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693854 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  693856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693867 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
     /*  693870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693875 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  693885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693889 */     GIR_RootConstrainSelectedInstOperands,
     /*  693890 */     // GIR_Coverage, 11372,
     /*  693890 */     GIR_EraseRootFromParent_Done,
     /*  693891 */   // Label 10931: @693891
     /*  693891 */   GIM_Try, /*On fail goto*//*Label 10932*/ GIMT_Encode4(693948), // Rule ID 10802 //
     /*  693896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  693899 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693922 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  693925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693932 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  693942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  693946 */     GIR_RootConstrainSelectedInstOperands,
     /*  693947 */     // GIR_Coverage, 10802,
     /*  693947 */     GIR_EraseRootFromParent_Done,
     /*  693948 */   // Label 10932: @693948
     /*  693948 */   GIM_Try, /*On fail goto*//*Label 10933*/ GIMT_Encode4(694005), // Rule ID 10803 //
     /*  693953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  693956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  693964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  693968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  693972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  693979 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  693979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  693982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  693984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  693989 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  693991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  693996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  693999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694003 */     GIR_RootConstrainSelectedInstOperands,
     /*  694004 */     // GIR_Coverage, 10803,
     /*  694004 */     GIR_EraseRootFromParent_Done,
     /*  694005 */   // Label 10933: @694005
     /*  694005 */   GIM_Try, /*On fail goto*//*Label 10934*/ GIMT_Encode4(694062), // Rule ID 10804 //
     /*  694010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  694013 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694025 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694029 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694036 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694046 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694060 */     GIR_RootConstrainSelectedInstOperands,
     /*  694061 */     // GIR_Coverage, 10804,
     /*  694061 */     GIR_EraseRootFromParent_Done,
     /*  694062 */   // Label 10934: @694062
     /*  694062 */   GIM_Try, /*On fail goto*//*Label 10935*/ GIMT_Encode4(694119), // Rule ID 10805 //
     /*  694067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  694070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694093 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694103 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694113 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694117 */     GIR_RootConstrainSelectedInstOperands,
     /*  694118 */     // GIR_Coverage, 10805,
     /*  694118 */     GIR_EraseRootFromParent_Done,
     /*  694119 */   // Label 10935: @694119
     /*  694119 */   GIM_Try, /*On fail goto*//*Label 10936*/ GIMT_Encode4(694176), // Rule ID 10806 //
     /*  694124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  694127 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694150 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694160 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694170 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694174 */     GIR_RootConstrainSelectedInstOperands,
     /*  694175 */     // GIR_Coverage, 10806,
     /*  694175 */     GIR_EraseRootFromParent_Done,
     /*  694176 */   // Label 10936: @694176
     /*  694176 */   GIM_Try, /*On fail goto*//*Label 10937*/ GIMT_Encode4(694232), // Rule ID 11358 //
     /*  694181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  694184 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694206 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694216 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694230 */     GIR_RootConstrainSelectedInstOperands,
     /*  694231 */     // GIR_Coverage, 11358,
     /*  694231 */     GIR_EraseRootFromParent_Done,
     /*  694232 */   // Label 10937: @694232
     /*  694232 */   GIM_Try, /*On fail goto*//*Label 10938*/ GIMT_Encode4(694288), // Rule ID 11359 //
     /*  694237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  694240 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694262 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694272 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694286 */     GIR_RootConstrainSelectedInstOperands,
     /*  694287 */     // GIR_Coverage, 11359,
     /*  694287 */     GIR_EraseRootFromParent_Done,
     /*  694288 */   // Label 10938: @694288
     /*  694288 */   GIM_Try, /*On fail goto*//*Label 10939*/ GIMT_Encode4(694344), // Rule ID 11360 //
     /*  694293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  694296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694318 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694328 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694342 */     GIR_RootConstrainSelectedInstOperands,
     /*  694343 */     // GIR_Coverage, 11360,
     /*  694343 */     GIR_EraseRootFromParent_Done,
     /*  694344 */   // Label 10939: @694344
     /*  694344 */   GIM_Try, /*On fail goto*//*Label 10940*/ GIMT_Encode4(694400), // Rule ID 11361 //
     /*  694349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  694352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694374 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694384 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694398 */     GIR_RootConstrainSelectedInstOperands,
     /*  694399 */     // GIR_Coverage, 11361,
     /*  694399 */     GIR_EraseRootFromParent_Done,
     /*  694400 */   // Label 10940: @694400
     /*  694400 */   GIM_Try, /*On fail goto*//*Label 10941*/ GIMT_Encode4(694456), // Rule ID 11362 //
     /*  694405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  694408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  694419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  694430 */     // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  694430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
     /*  694433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  694435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  694440 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  694442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  694447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  694450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694454 */     GIR_RootConstrainSelectedInstOperands,
     /*  694455 */     // GIR_Coverage, 11362,
     /*  694455 */     GIR_EraseRootFromParent_Done,
     /*  694456 */   // Label 10941: @694456
     /*  694456 */   GIM_Reject,
     /*  694457 */ // Label 10811: @694457
     /*  694457 */ GIM_Reject,
     /*  694458 */ // Label 10703: @694458
     /*  694458 */ GIM_Reject,
     /*  694459 */ // Label 28: @694459
     /*  694459 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 10944*/ GIMT_Encode4(708070),
     /*  694470 */ /*GILLT_s32*//*Label 10942*/ GIMT_Encode4(694478),
     /*  694474 */ /*GILLT_s64*//*Label 10943*/ GIMT_Encode4(700570),
     /*  694478 */ // Label 10942: @694478
     /*  694478 */ GIM_Try, /*On fail goto*//*Label 10945*/ GIMT_Encode4(700569),
     /*  694483 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  694486 */   GIM_Try, /*On fail goto*//*Label 10946*/ GIMT_Encode4(694548), // Rule ID 20898 //
     /*  694491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  694494 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694501 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694514 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64),
     /*  694517 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694546 */     GIR_RootConstrainSelectedInstOperands,
     /*  694547 */     // GIR_Coverage, 20898,
     /*  694547 */     GIR_EraseRootFromParent_Done,
     /*  694548 */   // Label 10946: @694548
     /*  694548 */   GIM_Try, /*On fail goto*//*Label 10947*/ GIMT_Encode4(694610), // Rule ID 20899 //
     /*  694553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  694556 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694563 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694576 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64),
     /*  694579 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694608 */     GIR_RootConstrainSelectedInstOperands,
     /*  694609 */     // GIR_Coverage, 20899,
     /*  694609 */     GIR_EraseRootFromParent_Done,
     /*  694610 */   // Label 10947: @694610
     /*  694610 */   GIM_Try, /*On fail goto*//*Label 10948*/ GIMT_Encode4(694672), // Rule ID 20900 //
     /*  694615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  694618 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694625 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694638 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64),
     /*  694641 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694670 */     GIR_RootConstrainSelectedInstOperands,
     /*  694671 */     // GIR_Coverage, 20900,
     /*  694671 */     GIR_EraseRootFromParent_Done,
     /*  694672 */   // Label 10948: @694672
     /*  694672 */   GIM_Try, /*On fail goto*//*Label 10949*/ GIMT_Encode4(694734), // Rule ID 20901 //
     /*  694677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  694680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694687 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694689 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694700 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64),
     /*  694703 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694728 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694732 */     GIR_RootConstrainSelectedInstOperands,
     /*  694733 */     // GIR_Coverage, 20901,
     /*  694733 */     GIR_EraseRootFromParent_Done,
     /*  694734 */   // Label 10949: @694734
     /*  694734 */   GIM_Try, /*On fail goto*//*Label 10950*/ GIMT_Encode4(694796), // Rule ID 20902 //
     /*  694739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  694742 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694749 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694762 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64),
     /*  694765 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694794 */     GIR_RootConstrainSelectedInstOperands,
     /*  694795 */     // GIR_Coverage, 20902,
     /*  694795 */     GIR_EraseRootFromParent_Done,
     /*  694796 */   // Label 10950: @694796
     /*  694796 */   GIM_Try, /*On fail goto*//*Label 10951*/ GIMT_Encode4(694858), // Rule ID 20918 //
     /*  694801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  694804 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694811 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694817 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694824 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64),
     /*  694827 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694856 */     GIR_RootConstrainSelectedInstOperands,
     /*  694857 */     // GIR_Coverage, 20918,
     /*  694857 */     GIR_EraseRootFromParent_Done,
     /*  694858 */   // Label 10951: @694858
     /*  694858 */   GIM_Try, /*On fail goto*//*Label 10952*/ GIMT_Encode4(694920), // Rule ID 20919 //
     /*  694863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  694866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694873 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694886 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64),
     /*  694889 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694918 */     GIR_RootConstrainSelectedInstOperands,
     /*  694919 */     // GIR_Coverage, 20919,
     /*  694919 */     GIR_EraseRootFromParent_Done,
     /*  694920 */   // Label 10952: @694920
     /*  694920 */   GIM_Try, /*On fail goto*//*Label 10953*/ GIMT_Encode4(694982), // Rule ID 20920 //
     /*  694925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  694928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694935 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  694941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  694948 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  694948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64),
     /*  694951 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  694953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  694958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  694963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  694968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  694973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  694976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  694980 */     GIR_RootConstrainSelectedInstOperands,
     /*  694981 */     // GIR_Coverage, 20920,
     /*  694981 */     GIR_EraseRootFromParent_Done,
     /*  694982 */   // Label 10953: @694982
     /*  694982 */   GIM_Try, /*On fail goto*//*Label 10954*/ GIMT_Encode4(695044), // Rule ID 20921 //
     /*  694987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  694990 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  694997 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  694999 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695010 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64),
     /*  695013 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  695038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695042 */     GIR_RootConstrainSelectedInstOperands,
     /*  695043 */     // GIR_Coverage, 20921,
     /*  695043 */     GIR_EraseRootFromParent_Done,
     /*  695044 */   // Label 10954: @695044
     /*  695044 */   GIM_Try, /*On fail goto*//*Label 10955*/ GIMT_Encode4(695106), // Rule ID 20922 //
     /*  695049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  695052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695059 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  695061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695072 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64),
     /*  695075 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  695100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695104 */     GIR_RootConstrainSelectedInstOperands,
     /*  695105 */     // GIR_Coverage, 20922,
     /*  695105 */     GIR_EraseRootFromParent_Done,
     /*  695106 */   // Label 10955: @695106
     /*  695106 */   GIM_Try, /*On fail goto*//*Label 10956*/ GIMT_Encode4(695172), // Rule ID 20888 //
     /*  695111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  695114 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695136 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN),
     /*  695139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695141 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695170 */     GIR_RootConstrainSelectedInstOperands,
     /*  695171 */     // GIR_Coverage, 20888,
     /*  695171 */     GIR_EraseRootFromParent_Done,
     /*  695172 */   // Label 10956: @695172
     /*  695172 */   GIM_Try, /*On fail goto*//*Label 10957*/ GIMT_Encode4(695238), // Rule ID 20889 //
     /*  695177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  695180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695202 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN),
     /*  695205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695207 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695236 */     GIR_RootConstrainSelectedInstOperands,
     /*  695237 */     // GIR_Coverage, 20889,
     /*  695237 */     GIR_EraseRootFromParent_Done,
     /*  695238 */   // Label 10957: @695238
     /*  695238 */   GIM_Try, /*On fail goto*//*Label 10958*/ GIMT_Encode4(695304), // Rule ID 20890 //
     /*  695243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  695246 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695268 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN),
     /*  695271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695273 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695302 */     GIR_RootConstrainSelectedInstOperands,
     /*  695303 */     // GIR_Coverage, 20890,
     /*  695303 */     GIR_EraseRootFromParent_Done,
     /*  695304 */   // Label 10958: @695304
     /*  695304 */   GIM_Try, /*On fail goto*//*Label 10959*/ GIMT_Encode4(695370), // Rule ID 20891 //
     /*  695309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  695312 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695334 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN),
     /*  695337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695339 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695368 */     GIR_RootConstrainSelectedInstOperands,
     /*  695369 */     // GIR_Coverage, 20891,
     /*  695369 */     GIR_EraseRootFromParent_Done,
     /*  695370 */   // Label 10959: @695370
     /*  695370 */   GIM_Try, /*On fail goto*//*Label 10960*/ GIMT_Encode4(695436), // Rule ID 20892 //
     /*  695375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  695378 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695400 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN),
     /*  695403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695405 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695434 */     GIR_RootConstrainSelectedInstOperands,
     /*  695435 */     // GIR_Coverage, 20892,
     /*  695435 */     GIR_EraseRootFromParent_Done,
     /*  695436 */   // Label 10960: @695436
     /*  695436 */   GIM_Try, /*On fail goto*//*Label 10961*/ GIMT_Encode4(695502), // Rule ID 20908 //
     /*  695441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  695444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695466 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN),
     /*  695469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695471 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695500 */     GIR_RootConstrainSelectedInstOperands,
     /*  695501 */     // GIR_Coverage, 20908,
     /*  695501 */     GIR_EraseRootFromParent_Done,
     /*  695502 */   // Label 10961: @695502
     /*  695502 */   GIM_Try, /*On fail goto*//*Label 10962*/ GIMT_Encode4(695568), // Rule ID 20909 //
     /*  695507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  695510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695521 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695532 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN),
     /*  695535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695537 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695566 */     GIR_RootConstrainSelectedInstOperands,
     /*  695567 */     // GIR_Coverage, 20909,
     /*  695567 */     GIR_EraseRootFromParent_Done,
     /*  695568 */   // Label 10962: @695568
     /*  695568 */   GIM_Try, /*On fail goto*//*Label 10963*/ GIMT_Encode4(695634), // Rule ID 20910 //
     /*  695573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  695576 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695598 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN),
     /*  695601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695603 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695628 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695632 */     GIR_RootConstrainSelectedInstOperands,
     /*  695633 */     // GIR_Coverage, 20910,
     /*  695633 */     GIR_EraseRootFromParent_Done,
     /*  695634 */   // Label 10963: @695634
     /*  695634 */   GIM_Try, /*On fail goto*//*Label 10964*/ GIMT_Encode4(695700), // Rule ID 20911 //
     /*  695639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  695642 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695664 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN),
     /*  695667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695669 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695698 */     GIR_RootConstrainSelectedInstOperands,
     /*  695699 */     // GIR_Coverage, 20911,
     /*  695699 */     GIR_EraseRootFromParent_Done,
     /*  695700 */   // Label 10964: @695700
     /*  695700 */   GIM_Try, /*On fail goto*//*Label 10965*/ GIMT_Encode4(695766), // Rule ID 20912 //
     /*  695705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  695708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  695719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  695730 */     // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN),
     /*  695733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  695735 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  695742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  695752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  695757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  695760 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695764 */     GIR_RootConstrainSelectedInstOperands,
     /*  695765 */     // GIR_Coverage, 20912,
     /*  695765 */     GIR_EraseRootFromParent_Done,
     /*  695766 */   // Label 10965: @695766
     /*  695766 */   GIM_Try, /*On fail goto*//*Label 10966*/ GIMT_Encode4(695823), // Rule ID 20893 //
     /*  695771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  695774 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695781 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  695783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  695794 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
     /*  695797 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  695809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  695814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  695817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695821 */     GIR_RootConstrainSelectedInstOperands,
     /*  695822 */     // GIR_Coverage, 20893,
     /*  695822 */     GIR_EraseRootFromParent_Done,
     /*  695823 */   // Label 10966: @695823
     /*  695823 */   GIM_Try, /*On fail goto*//*Label 10967*/ GIMT_Encode4(695880), // Rule ID 20894 //
     /*  695828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  695831 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695838 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  695840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  695851 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
     /*  695854 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  695866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  695871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  695874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695878 */     GIR_RootConstrainSelectedInstOperands,
     /*  695879 */     // GIR_Coverage, 20894,
     /*  695879 */     GIR_EraseRootFromParent_Done,
     /*  695880 */   // Label 10967: @695880
     /*  695880 */   GIM_Try, /*On fail goto*//*Label 10968*/ GIMT_Encode4(695937), // Rule ID 20895 //
     /*  695885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  695888 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695895 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  695897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  695908 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
     /*  695911 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  695923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  695928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  695931 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695935 */     GIR_RootConstrainSelectedInstOperands,
     /*  695936 */     // GIR_Coverage, 20895,
     /*  695936 */     GIR_EraseRootFromParent_Done,
     /*  695937 */   // Label 10968: @695937
     /*  695937 */   GIM_Try, /*On fail goto*//*Label 10969*/ GIMT_Encode4(695994), // Rule ID 20896 //
     /*  695942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  695945 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  695952 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  695954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  695958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  695965 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  695965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
     /*  695968 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  695970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  695975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  695980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  695985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  695988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  695992 */     GIR_RootConstrainSelectedInstOperands,
     /*  695993 */     // GIR_Coverage, 20896,
     /*  695993 */     GIR_EraseRootFromParent_Done,
     /*  695994 */   // Label 10969: @695994
     /*  695994 */   GIM_Try, /*On fail goto*//*Label 10970*/ GIMT_Encode4(696051), // Rule ID 20897 //
     /*  695999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  696002 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696009 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696022 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
     /*  696025 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696049 */     GIR_RootConstrainSelectedInstOperands,
     /*  696050 */     // GIR_Coverage, 20897,
     /*  696050 */     GIR_EraseRootFromParent_Done,
     /*  696051 */   // Label 10970: @696051
     /*  696051 */   GIM_Try, /*On fail goto*//*Label 10971*/ GIMT_Encode4(696108), // Rule ID 20913 //
     /*  696056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  696059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696066 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696079 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
     /*  696082 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696106 */     GIR_RootConstrainSelectedInstOperands,
     /*  696107 */     // GIR_Coverage, 20913,
     /*  696107 */     GIR_EraseRootFromParent_Done,
     /*  696108 */   // Label 10971: @696108
     /*  696108 */   GIM_Try, /*On fail goto*//*Label 10972*/ GIMT_Encode4(696165), // Rule ID 20914 //
     /*  696113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  696116 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696123 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696136 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
     /*  696139 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696163 */     GIR_RootConstrainSelectedInstOperands,
     /*  696164 */     // GIR_Coverage, 20914,
     /*  696164 */     GIR_EraseRootFromParent_Done,
     /*  696165 */   // Label 10972: @696165
     /*  696165 */   GIM_Try, /*On fail goto*//*Label 10973*/ GIMT_Encode4(696222), // Rule ID 20915 //
     /*  696170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  696173 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696180 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696193 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
     /*  696196 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696216 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696220 */     GIR_RootConstrainSelectedInstOperands,
     /*  696221 */     // GIR_Coverage, 20915,
     /*  696221 */     GIR_EraseRootFromParent_Done,
     /*  696222 */   // Label 10973: @696222
     /*  696222 */   GIM_Try, /*On fail goto*//*Label 10974*/ GIMT_Encode4(696279), // Rule ID 20916 //
     /*  696227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  696230 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696237 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696239 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696250 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
     /*  696253 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696277 */     GIR_RootConstrainSelectedInstOperands,
     /*  696278 */     // GIR_Coverage, 20916,
     /*  696278 */     GIR_EraseRootFromParent_Done,
     /*  696279 */   // Label 10974: @696279
     /*  696279 */   GIM_Try, /*On fail goto*//*Label 10975*/ GIMT_Encode4(696336), // Rule ID 20917 //
     /*  696284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  696287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696294 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696307 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
     /*  696310 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696334 */     GIR_RootConstrainSelectedInstOperands,
     /*  696335 */     // GIR_Coverage, 20917,
     /*  696335 */     GIR_EraseRootFromParent_Done,
     /*  696336 */   // Label 10975: @696336
     /*  696336 */   GIM_Try, /*On fail goto*//*Label 10976*/ GIMT_Encode4(696397), // Rule ID 20883 //
     /*  696341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  696344 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696355 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696366 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
     /*  696369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696371 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696395 */     GIR_RootConstrainSelectedInstOperands,
     /*  696396 */     // GIR_Coverage, 20883,
     /*  696396 */     GIR_EraseRootFromParent_Done,
     /*  696397 */   // Label 10976: @696397
     /*  696397 */   GIM_Try, /*On fail goto*//*Label 10977*/ GIMT_Encode4(696458), // Rule ID 20884 //
     /*  696402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  696405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696427 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
     /*  696430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696432 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696456 */     GIR_RootConstrainSelectedInstOperands,
     /*  696457 */     // GIR_Coverage, 20884,
     /*  696457 */     GIR_EraseRootFromParent_Done,
     /*  696458 */   // Label 10977: @696458
     /*  696458 */   GIM_Try, /*On fail goto*//*Label 10978*/ GIMT_Encode4(696519), // Rule ID 20885 //
     /*  696463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  696466 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696488 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
     /*  696491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696493 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696517 */     GIR_RootConstrainSelectedInstOperands,
     /*  696518 */     // GIR_Coverage, 20885,
     /*  696518 */     GIR_EraseRootFromParent_Done,
     /*  696519 */   // Label 10978: @696519
     /*  696519 */   GIM_Try, /*On fail goto*//*Label 10979*/ GIMT_Encode4(696580), // Rule ID 20886 //
     /*  696524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  696527 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696542 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696549 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
     /*  696552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696554 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696578 */     GIR_RootConstrainSelectedInstOperands,
     /*  696579 */     // GIR_Coverage, 20886,
     /*  696579 */     GIR_EraseRootFromParent_Done,
     /*  696580 */   // Label 10979: @696580
     /*  696580 */   GIM_Try, /*On fail goto*//*Label 10980*/ GIMT_Encode4(696641), // Rule ID 20887 //
     /*  696585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  696588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696610 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
     /*  696613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696615 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696639 */     GIR_RootConstrainSelectedInstOperands,
     /*  696640 */     // GIR_Coverage, 20887,
     /*  696640 */     GIR_EraseRootFromParent_Done,
     /*  696641 */   // Label 10980: @696641
     /*  696641 */   GIM_Try, /*On fail goto*//*Label 10981*/ GIMT_Encode4(696702), // Rule ID 20903 //
     /*  696646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  696649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696671 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
     /*  696674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696676 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696700 */     GIR_RootConstrainSelectedInstOperands,
     /*  696701 */     // GIR_Coverage, 20903,
     /*  696701 */     GIR_EraseRootFromParent_Done,
     /*  696702 */   // Label 10981: @696702
     /*  696702 */   GIM_Try, /*On fail goto*//*Label 10982*/ GIMT_Encode4(696763), // Rule ID 20904 //
     /*  696707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  696710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696732 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
     /*  696735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696737 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696761 */     GIR_RootConstrainSelectedInstOperands,
     /*  696762 */     // GIR_Coverage, 20904,
     /*  696762 */     GIR_EraseRootFromParent_Done,
     /*  696763 */   // Label 10982: @696763
     /*  696763 */   GIM_Try, /*On fail goto*//*Label 10983*/ GIMT_Encode4(696824), // Rule ID 20905 //
     /*  696768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  696771 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696793 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
     /*  696796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696798 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696818 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696822 */     GIR_RootConstrainSelectedInstOperands,
     /*  696823 */     // GIR_Coverage, 20905,
     /*  696823 */     GIR_EraseRootFromParent_Done,
     /*  696824 */   // Label 10983: @696824
     /*  696824 */   GIM_Try, /*On fail goto*//*Label 10984*/ GIMT_Encode4(696885), // Rule ID 20906 //
     /*  696829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  696832 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696854 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
     /*  696857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696859 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696879 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696883 */     GIR_RootConstrainSelectedInstOperands,
     /*  696884 */     // GIR_Coverage, 20906,
     /*  696884 */     GIR_EraseRootFromParent_Done,
     /*  696885 */   // Label 10984: @696885
     /*  696885 */   GIM_Try, /*On fail goto*//*Label 10985*/ GIMT_Encode4(696946), // Rule ID 20907 //
     /*  696890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  696893 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  696900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  696904 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  696915 */     // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  696915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
     /*  696918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  696920 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  696922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  696927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  696932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  696937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  696940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696944 */     GIR_RootConstrainSelectedInstOperands,
     /*  696945 */     // GIR_Coverage, 20907,
     /*  696945 */     GIR_EraseRootFromParent_Done,
     /*  696946 */   // Label 10985: @696946
     /*  696946 */   GIM_Try, /*On fail goto*//*Label 10986*/ GIMT_Encode4(696996), // Rule ID 30438 //
     /*  696951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  696954 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  696959 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  696961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  696965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  696972 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  696972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  696975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  696980 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  696982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  696987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  696990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  696994 */     GIR_RootConstrainSelectedInstOperands,
     /*  696995 */     // GIR_Coverage, 30438,
     /*  696995 */     GIR_EraseRootFromParent_Done,
     /*  696996 */   // Label 10986: @696996
     /*  696996 */   GIM_Try, /*On fail goto*//*Label 10987*/ GIMT_Encode4(697046), // Rule ID 30439 //
     /*  697001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  697004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697009 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697022 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697030 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697044 */     GIR_RootConstrainSelectedInstOperands,
     /*  697045 */     // GIR_Coverage, 30439,
     /*  697045 */     GIR_EraseRootFromParent_Done,
     /*  697046 */   // Label 10987: @697046
     /*  697046 */   GIM_Try, /*On fail goto*//*Label 10988*/ GIMT_Encode4(697096), // Rule ID 30440 //
     /*  697051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  697054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697059 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697072 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697080 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697094 */     GIR_RootConstrainSelectedInstOperands,
     /*  697095 */     // GIR_Coverage, 30440,
     /*  697095 */     GIR_EraseRootFromParent_Done,
     /*  697096 */   // Label 10988: @697096
     /*  697096 */   GIM_Try, /*On fail goto*//*Label 10989*/ GIMT_Encode4(697146), // Rule ID 30441 //
     /*  697101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  697104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697109 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697122 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697130 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697137 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697140 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697144 */     GIR_RootConstrainSelectedInstOperands,
     /*  697145 */     // GIR_Coverage, 30441,
     /*  697145 */     GIR_EraseRootFromParent_Done,
     /*  697146 */   // Label 10989: @697146
     /*  697146 */   GIM_Try, /*On fail goto*//*Label 10990*/ GIMT_Encode4(697196), // Rule ID 30442 //
     /*  697151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  697154 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697159 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697161 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697172 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697180 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697194 */     GIR_RootConstrainSelectedInstOperands,
     /*  697195 */     // GIR_Coverage, 30442,
     /*  697195 */     GIR_EraseRootFromParent_Done,
     /*  697196 */   // Label 10990: @697196
     /*  697196 */   GIM_Try, /*On fail goto*//*Label 10991*/ GIMT_Encode4(697246), // Rule ID 30444 //
     /*  697201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  697204 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697209 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697211 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697222 */     // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i32>>  =>  (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9),
     /*  697225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697230 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697240 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697244 */     GIR_RootConstrainSelectedInstOperands,
     /*  697245 */     // GIR_Coverage, 30444,
     /*  697245 */     GIR_EraseRootFromParent_Done,
     /*  697246 */   // Label 10991: @697246
     /*  697246 */   GIM_Try, /*On fail goto*//*Label 10992*/ GIMT_Encode4(697296), // Rule ID 30445 //
     /*  697251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  697254 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697259 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697265 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697272 */     // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i32>>  =>  (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9),
     /*  697275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697280 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697294 */     GIR_RootConstrainSelectedInstOperands,
     /*  697295 */     // GIR_Coverage, 30445,
     /*  697295 */     GIR_EraseRootFromParent_Done,
     /*  697296 */   // Label 10992: @697296
     /*  697296 */   GIM_Try, /*On fail goto*//*Label 10993*/ GIMT_Encode4(697346), // Rule ID 30446 //
     /*  697301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  697304 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697309 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697322 */     // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i32>>  =>  (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9),
     /*  697325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697330 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697344 */     GIR_RootConstrainSelectedInstOperands,
     /*  697345 */     // GIR_Coverage, 30446,
     /*  697345 */     GIR_EraseRootFromParent_Done,
     /*  697346 */   // Label 10993: @697346
     /*  697346 */   GIM_Try, /*On fail goto*//*Label 10994*/ GIMT_Encode4(697396), // Rule ID 30447 //
     /*  697351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  697354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697359 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697365 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697372 */     // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i32>>  =>  (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9),
     /*  697375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697380 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697394 */     GIR_RootConstrainSelectedInstOperands,
     /*  697395 */     // GIR_Coverage, 30447,
     /*  697395 */     GIR_EraseRootFromParent_Done,
     /*  697396 */   // Label 10994: @697396
     /*  697396 */   GIM_Try, /*On fail goto*//*Label 10995*/ GIMT_Encode4(697446), // Rule ID 30448 //
     /*  697401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  697404 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697409 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697422 */     // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i32>>  =>  (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9),
     /*  697425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697430 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697444 */     GIR_RootConstrainSelectedInstOperands,
     /*  697445 */     // GIR_Coverage, 30448,
     /*  697445 */     GIR_EraseRootFromParent_Done,
     /*  697446 */   // Label 10995: @697446
     /*  697446 */   GIM_Try, /*On fail goto*//*Label 10996*/ GIMT_Encode4(697496), // Rule ID 30450 //
     /*  697451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  697454 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  697459 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697461 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697472 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  697472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697480 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  697490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697494 */     GIR_RootConstrainSelectedInstOperands,
     /*  697495 */     // GIR_Coverage, 30450,
     /*  697495 */     GIR_EraseRootFromParent_Done,
     /*  697496 */   // Label 10996: @697496
     /*  697496 */   GIM_Try, /*On fail goto*//*Label 10997*/ GIMT_Encode4(697546), // Rule ID 30451 //
     /*  697501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  697504 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  697509 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697511 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697522 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  697522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697530 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  697540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697544 */     GIR_RootConstrainSelectedInstOperands,
     /*  697545 */     // GIR_Coverage, 30451,
     /*  697545 */     GIR_EraseRootFromParent_Done,
     /*  697546 */   // Label 10997: @697546
     /*  697546 */   GIM_Try, /*On fail goto*//*Label 10998*/ GIMT_Encode4(697596), // Rule ID 30452 //
     /*  697551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  697554 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  697559 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697572 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  697572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697580 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  697590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697594 */     GIR_RootConstrainSelectedInstOperands,
     /*  697595 */     // GIR_Coverage, 30452,
     /*  697595 */     GIR_EraseRootFromParent_Done,
     /*  697596 */   // Label 10998: @697596
     /*  697596 */   GIM_Try, /*On fail goto*//*Label 10999*/ GIMT_Encode4(697646), // Rule ID 30453 //
     /*  697601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  697604 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  697609 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697622 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  697622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697630 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  697640 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697644 */     GIR_RootConstrainSelectedInstOperands,
     /*  697645 */     // GIR_Coverage, 30453,
     /*  697645 */     GIR_EraseRootFromParent_Done,
     /*  697646 */   // Label 10999: @697646
     /*  697646 */   GIM_Try, /*On fail goto*//*Label 11000*/ GIMT_Encode4(697696), // Rule ID 30454 //
     /*  697651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  697654 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  697659 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697672 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  697672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
     /*  697675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697680 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  697690 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697694 */     GIR_RootConstrainSelectedInstOperands,
     /*  697695 */     // GIR_Coverage, 30454,
     /*  697695 */     GIR_EraseRootFromParent_Done,
     /*  697696 */   // Label 11000: @697696
     /*  697696 */   GIM_Try, /*On fail goto*//*Label 11001*/ GIMT_Encode4(697750), // Rule ID 30437 //
     /*  697701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  697704 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  697713 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697724 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i32>>  =>  (DS_MIN_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32),
     /*  697727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  697729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697734 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697744 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697748 */     GIR_RootConstrainSelectedInstOperands,
     /*  697749 */     // GIR_Coverage, 30437,
     /*  697749 */     GIR_EraseRootFromParent_Done,
     /*  697750 */   // Label 11001: @697750
     /*  697750 */   GIM_Try, /*On fail goto*//*Label 11002*/ GIMT_Encode4(697804), // Rule ID 30443 //
     /*  697755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  697758 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  697763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  697767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697778 */     // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_i32>>  =>  (DS_MIN_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  697778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32_gfx9),
     /*  697781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  697783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697788 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  697798 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697802 */     GIR_RootConstrainSelectedInstOperands,
     /*  697803 */     // GIR_Coverage, 30443,
     /*  697803 */     GIR_EraseRootFromParent_Done,
     /*  697804 */   // Label 11002: @697804
     /*  697804 */   GIM_Try, /*On fail goto*//*Label 11003*/ GIMT_Encode4(697858), // Rule ID 30449 //
     /*  697809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  697812 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  697817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  697821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  697832 */     // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i32>>  =>  (DS_MIN_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  697832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32),
     /*  697835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  697837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  697842 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  697844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  697849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  697852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697856 */     GIR_RootConstrainSelectedInstOperands,
     /*  697857 */     // GIR_Coverage, 30449,
     /*  697857 */     GIR_EraseRootFromParent_Done,
     /*  697858 */   // Label 11003: @697858
     /*  697858 */   GIM_Try, /*On fail goto*//*Label 11004*/ GIMT_Encode4(697917), // Rule ID 13009 //
     /*  697863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  697866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  697873 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  697886 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  697886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR),
     /*  697889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  697894 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  697896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  697901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  697906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  697911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697915 */     GIR_RootConstrainSelectedInstOperands,
     /*  697916 */     // GIR_Coverage, 13009,
     /*  697916 */     GIR_EraseRootFromParent_Done,
     /*  697917 */   // Label 11004: @697917
     /*  697917 */   GIM_Try, /*On fail goto*//*Label 11005*/ GIMT_Encode4(697976), // Rule ID 13010 //
     /*  697922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  697925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  697932 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697934 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697938 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  697945 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  697945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR),
     /*  697948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  697953 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  697955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  697960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  697965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  697970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  697974 */     GIR_RootConstrainSelectedInstOperands,
     /*  697975 */     // GIR_Coverage, 13010,
     /*  697975 */     GIR_EraseRootFromParent_Done,
     /*  697976 */   // Label 11005: @697976
     /*  697976 */   GIM_Try, /*On fail goto*//*Label 11006*/ GIMT_Encode4(698035), // Rule ID 13011 //
     /*  697981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  697984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  697991 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  697993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  697997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698004 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR),
     /*  698007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698012 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698033 */     GIR_RootConstrainSelectedInstOperands,
     /*  698034 */     // GIR_Coverage, 13011,
     /*  698034 */     GIR_EraseRootFromParent_Done,
     /*  698035 */   // Label 11006: @698035
     /*  698035 */   GIM_Try, /*On fail goto*//*Label 11007*/ GIMT_Encode4(698094), // Rule ID 13012 //
     /*  698040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  698043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698050 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698052 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698056 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698063 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR),
     /*  698066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698071 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698088 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698092 */     GIR_RootConstrainSelectedInstOperands,
     /*  698093 */     // GIR_Coverage, 13012,
     /*  698093 */     GIR_EraseRootFromParent_Done,
     /*  698094 */   // Label 11007: @698094
     /*  698094 */   GIM_Try, /*On fail goto*//*Label 11008*/ GIMT_Encode4(698153), // Rule ID 13013 //
     /*  698099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  698102 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698109 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698122 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR),
     /*  698125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698130 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698151 */     GIR_RootConstrainSelectedInstOperands,
     /*  698152 */     // GIR_Coverage, 13013,
     /*  698152 */     GIR_EraseRootFromParent_Done,
     /*  698153 */   // Label 11008: @698153
     /*  698153 */   GIM_Try, /*On fail goto*//*Label 11009*/ GIMT_Encode4(698216), // Rule ID 13019 //
     /*  698158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  698161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  698172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  698183 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN),
     /*  698186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  698188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698193 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698214 */     GIR_RootConstrainSelectedInstOperands,
     /*  698215 */     // GIR_Coverage, 13019,
     /*  698215 */     GIR_EraseRootFromParent_Done,
     /*  698216 */   // Label 11009: @698216
     /*  698216 */   GIM_Try, /*On fail goto*//*Label 11010*/ GIMT_Encode4(698268), // Rule ID 13004 //
     /*  698221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  698224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698231 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698244 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN),
     /*  698247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698252 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  698262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698266 */     GIR_RootConstrainSelectedInstOperands,
     /*  698267 */     // GIR_Coverage, 13004,
     /*  698267 */     GIR_EraseRootFromParent_Done,
     /*  698268 */   // Label 11010: @698268
     /*  698268 */   GIM_Try, /*On fail goto*//*Label 11011*/ GIMT_Encode4(698320), // Rule ID 13005 //
     /*  698273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  698276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698283 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698296 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN),
     /*  698299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698304 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  698314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698318 */     GIR_RootConstrainSelectedInstOperands,
     /*  698319 */     // GIR_Coverage, 13005,
     /*  698319 */     GIR_EraseRootFromParent_Done,
     /*  698320 */   // Label 11011: @698320
     /*  698320 */   GIM_Try, /*On fail goto*//*Label 11012*/ GIMT_Encode4(698372), // Rule ID 13006 //
     /*  698325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  698328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698335 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698348 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN),
     /*  698351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698356 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  698366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698370 */     GIR_RootConstrainSelectedInstOperands,
     /*  698371 */     // GIR_Coverage, 13006,
     /*  698371 */     GIR_EraseRootFromParent_Done,
     /*  698372 */   // Label 11012: @698372
     /*  698372 */   GIM_Try, /*On fail goto*//*Label 11013*/ GIMT_Encode4(698424), // Rule ID 13007 //
     /*  698377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  698380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698400 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN),
     /*  698403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698408 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  698418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698422 */     GIR_RootConstrainSelectedInstOperands,
     /*  698423 */     // GIR_Coverage, 13007,
     /*  698423 */     GIR_EraseRootFromParent_Done,
     /*  698424 */   // Label 11013: @698424
     /*  698424 */   GIM_Try, /*On fail goto*//*Label 11014*/ GIMT_Encode4(698476), // Rule ID 13008 //
     /*  698429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  698432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698439 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698452 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (GLOBAL_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN),
     /*  698455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698460 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  698470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698474 */     GIR_RootConstrainSelectedInstOperands,
     /*  698475 */     // GIR_Coverage, 13008,
     /*  698475 */     GIR_EraseRootFromParent_Done,
     /*  698476 */   // Label 11014: @698476
     /*  698476 */   GIM_Try, /*On fail goto*//*Label 11015*/ GIMT_Encode4(698532), // Rule ID 13014 //
     /*  698481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  698484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  698495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698506 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN),
     /*  698509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  698511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698516 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  698526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698530 */     GIR_RootConstrainSelectedInstOperands,
     /*  698531 */     // GIR_Coverage, 13014,
     /*  698531 */     GIR_EraseRootFromParent_Done,
     /*  698532 */   // Label 11015: @698532
     /*  698532 */   GIM_Try, /*On fail goto*//*Label 11016*/ GIMT_Encode4(698588), // Rule ID 13015 //
     /*  698537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  698540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  698551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698562 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN),
     /*  698565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  698567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698572 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  698582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698586 */     GIR_RootConstrainSelectedInstOperands,
     /*  698587 */     // GIR_Coverage, 13015,
     /*  698587 */     GIR_EraseRootFromParent_Done,
     /*  698588 */   // Label 11016: @698588
     /*  698588 */   GIM_Try, /*On fail goto*//*Label 11017*/ GIMT_Encode4(698644), // Rule ID 13016 //
     /*  698593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  698596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698603 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  698607 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698618 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN),
     /*  698621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  698623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698628 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  698638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698642 */     GIR_RootConstrainSelectedInstOperands,
     /*  698643 */     // GIR_Coverage, 13016,
     /*  698643 */     GIR_EraseRootFromParent_Done,
     /*  698644 */   // Label 11017: @698644
     /*  698644 */   GIM_Try, /*On fail goto*//*Label 11018*/ GIMT_Encode4(698700), // Rule ID 13017 //
     /*  698649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  698652 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  698663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698674 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN),
     /*  698677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  698679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698684 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  698694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698698 */     GIR_RootConstrainSelectedInstOperands,
     /*  698699 */     // GIR_Coverage, 13017,
     /*  698699 */     GIR_EraseRootFromParent_Done,
     /*  698700 */   // Label 11018: @698700
     /*  698700 */   GIM_Try, /*On fail goto*//*Label 11019*/ GIMT_Encode4(698756), // Rule ID 13018 //
     /*  698705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  698708 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  698719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  698730 */     // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  698730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN),
     /*  698733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  698735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  698740 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  698747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  698750 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698754 */     GIR_RootConstrainSelectedInstOperands,
     /*  698755 */     // GIR_Coverage, 13018,
     /*  698755 */     GIR_EraseRootFromParent_Done,
     /*  698756 */   // Label 11019: @698756
     /*  698756 */   GIM_Try, /*On fail goto*//*Label 11020*/ GIMT_Encode4(698816), // Rule ID 10609 //
     /*  698761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  698764 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698772 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698785 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  698788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698793 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698814 */     GIR_RootConstrainSelectedInstOperands,
     /*  698815 */     // GIR_Coverage, 10609,
     /*  698815 */     GIR_EraseRootFromParent_Done,
     /*  698816 */   // Label 11020: @698816
     /*  698816 */   GIM_Try, /*On fail goto*//*Label 11021*/ GIMT_Encode4(698876), // Rule ID 10610 //
     /*  698821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  698824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698832 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698845 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  698848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698853 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698874 */     GIR_RootConstrainSelectedInstOperands,
     /*  698875 */     // GIR_Coverage, 10610,
     /*  698875 */     GIR_EraseRootFromParent_Done,
     /*  698876 */   // Label 11021: @698876
     /*  698876 */   GIM_Try, /*On fail goto*//*Label 11022*/ GIMT_Encode4(698936), // Rule ID 10611 //
     /*  698881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  698884 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698892 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698905 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  698908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698913 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698934 */     GIR_RootConstrainSelectedInstOperands,
     /*  698935 */     // GIR_Coverage, 10611,
     /*  698935 */     GIR_EraseRootFromParent_Done,
     /*  698936 */   // Label 11022: @698936
     /*  698936 */   GIM_Try, /*On fail goto*//*Label 11023*/ GIMT_Encode4(698996), // Rule ID 10612 //
     /*  698941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  698944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  698952 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  698954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  698958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  698965 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  698965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  698968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  698973 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  698975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  698980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  698985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  698990 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  698994 */     GIR_RootConstrainSelectedInstOperands,
     /*  698995 */     // GIR_Coverage, 10612,
     /*  698995 */     GIR_EraseRootFromParent_Done,
     /*  698996 */   // Label 11023: @698996
     /*  698996 */   GIM_Try, /*On fail goto*//*Label 11024*/ GIMT_Encode4(699056), // Rule ID 10613 //
     /*  699001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  699004 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699012 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699014 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699018 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  699025 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  699028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699033 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699050 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699054 */     GIR_RootConstrainSelectedInstOperands,
     /*  699055 */     // GIR_Coverage, 10613,
     /*  699055 */     GIR_EraseRootFromParent_Done,
     /*  699056 */   // Label 11024: @699056
     /*  699056 */   GIM_Try, /*On fail goto*//*Label 11025*/ GIMT_Encode4(699115), // Rule ID 11165 //
     /*  699061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  699064 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699071 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  699084 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  699087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699092 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699113 */     GIR_RootConstrainSelectedInstOperands,
     /*  699114 */     // GIR_Coverage, 11165,
     /*  699114 */     GIR_EraseRootFromParent_Done,
     /*  699115 */   // Label 11025: @699115
     /*  699115 */   GIM_Try, /*On fail goto*//*Label 11026*/ GIMT_Encode4(699174), // Rule ID 11166 //
     /*  699120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  699123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699130 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  699143 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  699146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699151 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699172 */     GIR_RootConstrainSelectedInstOperands,
     /*  699173 */     // GIR_Coverage, 11166,
     /*  699173 */     GIR_EraseRootFromParent_Done,
     /*  699174 */   // Label 11026: @699174
     /*  699174 */   GIM_Try, /*On fail goto*//*Label 11027*/ GIMT_Encode4(699233), // Rule ID 11167 //
     /*  699179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  699182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699189 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  699202 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  699205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699210 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699227 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699231 */     GIR_RootConstrainSelectedInstOperands,
     /*  699232 */     // GIR_Coverage, 11167,
     /*  699232 */     GIR_EraseRootFromParent_Done,
     /*  699233 */   // Label 11027: @699233
     /*  699233 */   GIM_Try, /*On fail goto*//*Label 11028*/ GIMT_Encode4(699292), // Rule ID 11168 //
     /*  699238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  699241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699248 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  699261 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  699264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699269 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699286 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699290 */     GIR_RootConstrainSelectedInstOperands,
     /*  699291 */     // GIR_Coverage, 11168,
     /*  699291 */     GIR_EraseRootFromParent_Done,
     /*  699292 */   // Label 11028: @699292
     /*  699292 */   GIM_Try, /*On fail goto*//*Label 11029*/ GIMT_Encode4(699351), // Rule ID 11169 //
     /*  699297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  699300 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699307 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699309 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  699320 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR),
     /*  699323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699328 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699349 */     GIR_RootConstrainSelectedInstOperands,
     /*  699350 */     // GIR_Coverage, 11169,
     /*  699350 */     GIR_EraseRootFromParent_Done,
     /*  699351 */   // Label 11029: @699351
     /*  699351 */   GIM_Try, /*On fail goto*//*Label 11030*/ GIMT_Encode4(699415), // Rule ID 10603 //
     /*  699356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  699359 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  699371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  699382 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR_RTN),
     /*  699385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  699387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699392 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699413 */     GIR_RootConstrainSelectedInstOperands,
     /*  699414 */     // GIR_Coverage, 10603,
     /*  699414 */     GIR_EraseRootFromParent_Done,
     /*  699415 */   // Label 11030: @699415
     /*  699415 */   GIM_Try, /*On fail goto*//*Label 11031*/ GIMT_Encode4(699478), // Rule ID 11159 //
     /*  699420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  699423 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  699434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  699445 */     // (atomic_load_umin:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (FLAT_ATOMIC_UMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  699445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_SADDR_RTN),
     /*  699448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  699450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  699455 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  699462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  699467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  699472 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699476 */     GIR_RootConstrainSelectedInstOperands,
     /*  699477 */     // GIR_Coverage, 11159,
     /*  699477 */     GIR_EraseRootFromParent_Done,
     /*  699478 */   // Label 11031: @699478
     /*  699478 */   GIM_Try, /*On fail goto*//*Label 11032*/ GIMT_Encode4(699531), // Rule ID 10604 //
     /*  699483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  699486 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699494 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699507 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699515 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699529 */     GIR_RootConstrainSelectedInstOperands,
     /*  699530 */     // GIR_Coverage, 10604,
     /*  699530 */     GIR_EraseRootFromParent_Done,
     /*  699531 */   // Label 11032: @699531
     /*  699531 */   GIM_Try, /*On fail goto*//*Label 11033*/ GIMT_Encode4(699584), // Rule ID 10605 //
     /*  699536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  699539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699547 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699549 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699560 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699568 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699582 */     GIR_RootConstrainSelectedInstOperands,
     /*  699583 */     // GIR_Coverage, 10605,
     /*  699583 */     GIR_EraseRootFromParent_Done,
     /*  699584 */   // Label 11033: @699584
     /*  699584 */   GIM_Try, /*On fail goto*//*Label 11034*/ GIMT_Encode4(699637), // Rule ID 10606 //
     /*  699589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  699592 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699600 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699613 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699621 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699635 */     GIR_RootConstrainSelectedInstOperands,
     /*  699636 */     // GIR_Coverage, 10606,
     /*  699636 */     GIR_EraseRootFromParent_Done,
     /*  699637 */   // Label 11034: @699637
     /*  699637 */   GIM_Try, /*On fail goto*//*Label 11035*/ GIMT_Encode4(699690), // Rule ID 10607 //
     /*  699642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  699645 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699653 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699666 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699674 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699684 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699688 */     GIR_RootConstrainSelectedInstOperands,
     /*  699689 */     // GIR_Coverage, 10607,
     /*  699689 */     GIR_EraseRootFromParent_Done,
     /*  699690 */   // Label 11035: @699690
     /*  699690 */   GIM_Try, /*On fail goto*//*Label 11036*/ GIMT_Encode4(699743), // Rule ID 10608 //
     /*  699695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  699698 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699706 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699708 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699719 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699727 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699741 */     GIR_RootConstrainSelectedInstOperands,
     /*  699742 */     // GIR_Coverage, 10608,
     /*  699742 */     GIR_EraseRootFromParent_Done,
     /*  699743 */   // Label 11036: @699743
     /*  699743 */   GIM_Try, /*On fail goto*//*Label 11037*/ GIMT_Encode4(699795), // Rule ID 11160 //
     /*  699748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  699751 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699758 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699771 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699779 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699793 */     GIR_RootConstrainSelectedInstOperands,
     /*  699794 */     // GIR_Coverage, 11160,
     /*  699794 */     GIR_EraseRootFromParent_Done,
     /*  699795 */   // Label 11037: @699795
     /*  699795 */   GIM_Try, /*On fail goto*//*Label 11038*/ GIMT_Encode4(699847), // Rule ID 11161 //
     /*  699800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  699803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699810 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699816 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699823 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699831 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699845 */     GIR_RootConstrainSelectedInstOperands,
     /*  699846 */     // GIR_Coverage, 11161,
     /*  699846 */     GIR_EraseRootFromParent_Done,
     /*  699847 */   // Label 11038: @699847
     /*  699847 */   GIM_Try, /*On fail goto*//*Label 11039*/ GIMT_Encode4(699899), // Rule ID 11162 //
     /*  699852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  699855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699862 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699875 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699883 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699897 */     GIR_RootConstrainSelectedInstOperands,
     /*  699898 */     // GIR_Coverage, 11162,
     /*  699898 */     GIR_EraseRootFromParent_Done,
     /*  699899 */   // Label 11039: @699899
     /*  699899 */   GIM_Try, /*On fail goto*//*Label 11040*/ GIMT_Encode4(699951), // Rule ID 11163 //
     /*  699904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  699907 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699914 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699927 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699935 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  699949 */     GIR_RootConstrainSelectedInstOperands,
     /*  699950 */     // GIR_Coverage, 11163,
     /*  699950 */     GIR_EraseRootFromParent_Done,
     /*  699951 */   // Label 11040: @699951
     /*  699951 */   GIM_Try, /*On fail goto*//*Label 11041*/ GIMT_Encode4(700003), // Rule ID 11164 //
     /*  699956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  699959 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  699966 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  699968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  699972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  699979 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>>  =>  (FLAT_ATOMIC_UMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  699979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
     /*  699982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  699987 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  699989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  699994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  699997 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700001 */     GIR_RootConstrainSelectedInstOperands,
     /*  700002 */     // GIR_Coverage, 11164,
     /*  700002 */     GIR_EraseRootFromParent_Done,
     /*  700003 */   // Label 11041: @700003
     /*  700003 */   GIM_Try, /*On fail goto*//*Label 11042*/ GIMT_Encode4(700060), // Rule ID 10598 //
     /*  700008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  700011 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700034 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700044 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700054 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700058 */     GIR_RootConstrainSelectedInstOperands,
     /*  700059 */     // GIR_Coverage, 10598,
     /*  700059 */     GIR_EraseRootFromParent_Done,
     /*  700060 */   // Label 11042: @700060
     /*  700060 */   GIM_Try, /*On fail goto*//*Label 11043*/ GIMT_Encode4(700117), // Rule ID 10599 //
     /*  700065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  700068 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700091 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700101 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700115 */     GIR_RootConstrainSelectedInstOperands,
     /*  700116 */     // GIR_Coverage, 10599,
     /*  700116 */     GIR_EraseRootFromParent_Done,
     /*  700117 */   // Label 11043: @700117
     /*  700117 */   GIM_Try, /*On fail goto*//*Label 11044*/ GIMT_Encode4(700174), // Rule ID 10600 //
     /*  700122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  700125 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700148 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700158 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700172 */     GIR_RootConstrainSelectedInstOperands,
     /*  700173 */     // GIR_Coverage, 10600,
     /*  700173 */     GIR_EraseRootFromParent_Done,
     /*  700174 */   // Label 11044: @700174
     /*  700174 */   GIM_Try, /*On fail goto*//*Label 11045*/ GIMT_Encode4(700231), // Rule ID 10601 //
     /*  700179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  700182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700194 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700205 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700215 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700225 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700229 */     GIR_RootConstrainSelectedInstOperands,
     /*  700230 */     // GIR_Coverage, 10601,
     /*  700230 */     GIR_EraseRootFromParent_Done,
     /*  700231 */   // Label 11045: @700231
     /*  700231 */   GIM_Try, /*On fail goto*//*Label 11046*/ GIMT_Encode4(700288), // Rule ID 10602 //
     /*  700236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  700239 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700262 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700272 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700286 */     GIR_RootConstrainSelectedInstOperands,
     /*  700287 */     // GIR_Coverage, 10602,
     /*  700287 */     GIR_EraseRootFromParent_Done,
     /*  700288 */   // Label 11046: @700288
     /*  700288 */   GIM_Try, /*On fail goto*//*Label 11047*/ GIMT_Encode4(700344), // Rule ID 11154 //
     /*  700293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  700296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700307 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700318 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700328 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700342 */     GIR_RootConstrainSelectedInstOperands,
     /*  700343 */     // GIR_Coverage, 11154,
     /*  700343 */     GIR_EraseRootFromParent_Done,
     /*  700344 */   // Label 11047: @700344
     /*  700344 */   GIM_Try, /*On fail goto*//*Label 11048*/ GIMT_Encode4(700400), // Rule ID 11155 //
     /*  700349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  700352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700374 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700384 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700398 */     GIR_RootConstrainSelectedInstOperands,
     /*  700399 */     // GIR_Coverage, 11155,
     /*  700399 */     GIR_EraseRootFromParent_Done,
     /*  700400 */   // Label 11048: @700400
     /*  700400 */   GIM_Try, /*On fail goto*//*Label 11049*/ GIMT_Encode4(700456), // Rule ID 11156 //
     /*  700405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  700408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700419 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700430 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700440 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700454 */     GIR_RootConstrainSelectedInstOperands,
     /*  700455 */     // GIR_Coverage, 11156,
     /*  700455 */     GIR_EraseRootFromParent_Done,
     /*  700456 */   // Label 11049: @700456
     /*  700456 */   GIM_Try, /*On fail goto*//*Label 11050*/ GIMT_Encode4(700512), // Rule ID 11157 //
     /*  700461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  700464 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700486 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700496 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700506 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700510 */     GIR_RootConstrainSelectedInstOperands,
     /*  700511 */     // GIR_Coverage, 11157,
     /*  700511 */     GIR_EraseRootFromParent_Done,
     /*  700512 */   // Label 11050: @700512
     /*  700512 */   GIM_Try, /*On fail goto*//*Label 11051*/ GIMT_Encode4(700568), // Rule ID 11158 //
     /*  700517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  700520 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  700531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  700542 */     // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  700542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
     /*  700545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  700547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  700552 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  700554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  700559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  700562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700566 */     GIR_RootConstrainSelectedInstOperands,
     /*  700567 */     // GIR_Coverage, 11158,
     /*  700567 */     GIR_EraseRootFromParent_Done,
     /*  700568 */   // Label 11051: @700568
     /*  700568 */   GIM_Reject,
     /*  700569 */ // Label 10945: @700569
     /*  700569 */ GIM_Reject,
     /*  700570 */ // Label 10943: @700570
     /*  700570 */ GIM_Try, /*On fail goto*//*Label 11052*/ GIMT_Encode4(708069),
     /*  700575 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  700578 */   GIM_Try, /*On fail goto*//*Label 11053*/ GIMT_Encode4(700640), // Rule ID 21378 //
     /*  700583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  700586 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700593 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700595 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700606 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64),
     /*  700609 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  700631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  700634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700638 */     GIR_RootConstrainSelectedInstOperands,
     /*  700639 */     // GIR_Coverage, 21378,
     /*  700639 */     GIR_EraseRootFromParent_Done,
     /*  700640 */   // Label 11053: @700640
     /*  700640 */   GIM_Try, /*On fail goto*//*Label 11054*/ GIMT_Encode4(700702), // Rule ID 21379 //
     /*  700645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  700648 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700655 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700668 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64),
     /*  700671 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  700693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  700696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700700 */     GIR_RootConstrainSelectedInstOperands,
     /*  700701 */     // GIR_Coverage, 21379,
     /*  700701 */     GIR_EraseRootFromParent_Done,
     /*  700702 */   // Label 11054: @700702
     /*  700702 */   GIM_Try, /*On fail goto*//*Label 11055*/ GIMT_Encode4(700764), // Rule ID 21380 //
     /*  700707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  700710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700717 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700730 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64),
     /*  700733 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  700755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  700758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700762 */     GIR_RootConstrainSelectedInstOperands,
     /*  700763 */     // GIR_Coverage, 21380,
     /*  700763 */     GIR_EraseRootFromParent_Done,
     /*  700764 */   // Label 11055: @700764
     /*  700764 */   GIM_Try, /*On fail goto*//*Label 11056*/ GIMT_Encode4(700826), // Rule ID 21381 //
     /*  700769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  700772 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700779 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700792 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64),
     /*  700795 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  700817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  700820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700824 */     GIR_RootConstrainSelectedInstOperands,
     /*  700825 */     // GIR_Coverage, 21381,
     /*  700825 */     GIR_EraseRootFromParent_Done,
     /*  700826 */   // Label 11056: @700826
     /*  700826 */   GIM_Try, /*On fail goto*//*Label 11057*/ GIMT_Encode4(700888), // Rule ID 21382 //
     /*  700831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  700834 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700841 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700854 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64),
     /*  700857 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  700879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  700882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700886 */     GIR_RootConstrainSelectedInstOperands,
     /*  700887 */     // GIR_Coverage, 21382,
     /*  700887 */     GIR_EraseRootFromParent_Done,
     /*  700888 */   // Label 11057: @700888
     /*  700888 */   GIM_Try, /*On fail goto*//*Label 11058*/ GIMT_Encode4(700950), // Rule ID 21398 //
     /*  700893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  700896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700903 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700916 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64),
     /*  700919 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  700941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  700944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  700948 */     GIR_RootConstrainSelectedInstOperands,
     /*  700949 */     // GIR_Coverage, 21398,
     /*  700949 */     GIR_EraseRootFromParent_Done,
     /*  700950 */   // Label 11058: @700950
     /*  700950 */   GIM_Try, /*On fail goto*//*Label 11059*/ GIMT_Encode4(701012), // Rule ID 21399 //
     /*  700955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  700958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  700965 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  700967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  700971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  700978 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  700978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64),
     /*  700981 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  700983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  700988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  700993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  700998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  701006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701010 */     GIR_RootConstrainSelectedInstOperands,
     /*  701011 */     // GIR_Coverage, 21399,
     /*  701011 */     GIR_EraseRootFromParent_Done,
     /*  701012 */   // Label 11059: @701012
     /*  701012 */   GIM_Try, /*On fail goto*//*Label 11060*/ GIMT_Encode4(701074), // Rule ID 21400 //
     /*  701017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  701020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701027 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  701029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701040 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64),
     /*  701043 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  701068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701072 */     GIR_RootConstrainSelectedInstOperands,
     /*  701073 */     // GIR_Coverage, 21400,
     /*  701073 */     GIR_EraseRootFromParent_Done,
     /*  701074 */   // Label 11060: @701074
     /*  701074 */   GIM_Try, /*On fail goto*//*Label 11061*/ GIMT_Encode4(701136), // Rule ID 21401 //
     /*  701079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  701082 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701089 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  701091 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701102 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64),
     /*  701105 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  701130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701134 */     GIR_RootConstrainSelectedInstOperands,
     /*  701135 */     // GIR_Coverage, 21401,
     /*  701135 */     GIR_EraseRootFromParent_Done,
     /*  701136 */   // Label 11061: @701136
     /*  701136 */   GIM_Try, /*On fail goto*//*Label 11062*/ GIMT_Encode4(701198), // Rule ID 21402 //
     /*  701141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  701144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701151 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  701153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701164 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64),
     /*  701167 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  701192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701196 */     GIR_RootConstrainSelectedInstOperands,
     /*  701197 */     // GIR_Coverage, 21402,
     /*  701197 */     GIR_EraseRootFromParent_Done,
     /*  701198 */   // Label 11062: @701198
     /*  701198 */   GIM_Try, /*On fail goto*//*Label 11063*/ GIMT_Encode4(701264), // Rule ID 21368 //
     /*  701203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  701206 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701228 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN),
     /*  701231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701233 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701262 */     GIR_RootConstrainSelectedInstOperands,
     /*  701263 */     // GIR_Coverage, 21368,
     /*  701263 */     GIR_EraseRootFromParent_Done,
     /*  701264 */   // Label 11063: @701264
     /*  701264 */   GIM_Try, /*On fail goto*//*Label 11064*/ GIMT_Encode4(701330), // Rule ID 21369 //
     /*  701269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  701272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701294 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN),
     /*  701297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701299 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701328 */     GIR_RootConstrainSelectedInstOperands,
     /*  701329 */     // GIR_Coverage, 21369,
     /*  701329 */     GIR_EraseRootFromParent_Done,
     /*  701330 */   // Label 11064: @701330
     /*  701330 */   GIM_Try, /*On fail goto*//*Label 11065*/ GIMT_Encode4(701396), // Rule ID 21370 //
     /*  701335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  701338 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701360 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN),
     /*  701363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701365 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701394 */     GIR_RootConstrainSelectedInstOperands,
     /*  701395 */     // GIR_Coverage, 21370,
     /*  701395 */     GIR_EraseRootFromParent_Done,
     /*  701396 */   // Label 11065: @701396
     /*  701396 */   GIM_Try, /*On fail goto*//*Label 11066*/ GIMT_Encode4(701462), // Rule ID 21371 //
     /*  701401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  701404 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701426 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN),
     /*  701429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701431 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701460 */     GIR_RootConstrainSelectedInstOperands,
     /*  701461 */     // GIR_Coverage, 21371,
     /*  701461 */     GIR_EraseRootFromParent_Done,
     /*  701462 */   // Label 11066: @701462
     /*  701462 */   GIM_Try, /*On fail goto*//*Label 11067*/ GIMT_Encode4(701528), // Rule ID 21372 //
     /*  701467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  701470 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701481 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701492 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN),
     /*  701495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701497 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701526 */     GIR_RootConstrainSelectedInstOperands,
     /*  701527 */     // GIR_Coverage, 21372,
     /*  701527 */     GIR_EraseRootFromParent_Done,
     /*  701528 */   // Label 11067: @701528
     /*  701528 */   GIM_Try, /*On fail goto*//*Label 11068*/ GIMT_Encode4(701594), // Rule ID 21388 //
     /*  701533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  701536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701547 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701551 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701558 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN),
     /*  701561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701563 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701592 */     GIR_RootConstrainSelectedInstOperands,
     /*  701593 */     // GIR_Coverage, 21388,
     /*  701593 */     GIR_EraseRootFromParent_Done,
     /*  701594 */   // Label 11068: @701594
     /*  701594 */   GIM_Try, /*On fail goto*//*Label 11069*/ GIMT_Encode4(701660), // Rule ID 21389 //
     /*  701599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  701602 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701624 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN),
     /*  701627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701629 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701654 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701658 */     GIR_RootConstrainSelectedInstOperands,
     /*  701659 */     // GIR_Coverage, 21389,
     /*  701659 */     GIR_EraseRootFromParent_Done,
     /*  701660 */   // Label 11069: @701660
     /*  701660 */   GIM_Try, /*On fail goto*//*Label 11070*/ GIMT_Encode4(701726), // Rule ID 21390 //
     /*  701665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  701668 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701679 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701683 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701690 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN),
     /*  701693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701695 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701724 */     GIR_RootConstrainSelectedInstOperands,
     /*  701725 */     // GIR_Coverage, 21390,
     /*  701725 */     GIR_EraseRootFromParent_Done,
     /*  701726 */   // Label 11070: @701726
     /*  701726 */   GIM_Try, /*On fail goto*//*Label 11071*/ GIMT_Encode4(701792), // Rule ID 21391 //
     /*  701731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  701734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701756 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN),
     /*  701759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701761 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701783 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701790 */     GIR_RootConstrainSelectedInstOperands,
     /*  701791 */     // GIR_Coverage, 21391,
     /*  701791 */     GIR_EraseRootFromParent_Done,
     /*  701792 */   // Label 11071: @701792
     /*  701792 */   GIM_Try, /*On fail goto*//*Label 11072*/ GIMT_Encode4(701858), // Rule ID 21392 //
     /*  701797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  701800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  701811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  701822 */     // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN),
     /*  701825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  701827 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  701834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  701844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  701849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  701852 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701856 */     GIR_RootConstrainSelectedInstOperands,
     /*  701857 */     // GIR_Coverage, 21392,
     /*  701857 */     GIR_EraseRootFromParent_Done,
     /*  701858 */   // Label 11072: @701858
     /*  701858 */   GIM_Try, /*On fail goto*//*Label 11073*/ GIMT_Encode4(701915), // Rule ID 21373 //
     /*  701863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  701866 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701873 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  701875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  701886 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
     /*  701889 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  701901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  701906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  701909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701913 */     GIR_RootConstrainSelectedInstOperands,
     /*  701914 */     // GIR_Coverage, 21373,
     /*  701914 */     GIR_EraseRootFromParent_Done,
     /*  701915 */   // Label 11073: @701915
     /*  701915 */   GIM_Try, /*On fail goto*//*Label 11074*/ GIMT_Encode4(701972), // Rule ID 21374 //
     /*  701920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  701923 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701930 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  701932 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701936 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  701943 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  701943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
     /*  701946 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  701948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  701953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  701958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  701963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  701966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  701970 */     GIR_RootConstrainSelectedInstOperands,
     /*  701971 */     // GIR_Coverage, 21374,
     /*  701971 */     GIR_EraseRootFromParent_Done,
     /*  701972 */   // Label 11074: @701972
     /*  701972 */   GIM_Try, /*On fail goto*//*Label 11075*/ GIMT_Encode4(702029), // Rule ID 21375 //
     /*  701977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  701980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  701987 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  701989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  701993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702000 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
     /*  702003 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702027 */     GIR_RootConstrainSelectedInstOperands,
     /*  702028 */     // GIR_Coverage, 21375,
     /*  702028 */     GIR_EraseRootFromParent_Done,
     /*  702029 */   // Label 11075: @702029
     /*  702029 */   GIM_Try, /*On fail goto*//*Label 11076*/ GIMT_Encode4(702086), // Rule ID 21376 //
     /*  702034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  702037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702044 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702050 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702057 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
     /*  702060 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702084 */     GIR_RootConstrainSelectedInstOperands,
     /*  702085 */     // GIR_Coverage, 21376,
     /*  702085 */     GIR_EraseRootFromParent_Done,
     /*  702086 */   // Label 11076: @702086
     /*  702086 */   GIM_Try, /*On fail goto*//*Label 11077*/ GIMT_Encode4(702143), // Rule ID 21377 //
     /*  702091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  702094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702101 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702114 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
     /*  702117 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702141 */     GIR_RootConstrainSelectedInstOperands,
     /*  702142 */     // GIR_Coverage, 21377,
     /*  702142 */     GIR_EraseRootFromParent_Done,
     /*  702143 */   // Label 11077: @702143
     /*  702143 */   GIM_Try, /*On fail goto*//*Label 11078*/ GIMT_Encode4(702200), // Rule ID 21393 //
     /*  702148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  702151 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702158 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702171 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
     /*  702174 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702198 */     GIR_RootConstrainSelectedInstOperands,
     /*  702199 */     // GIR_Coverage, 21393,
     /*  702199 */     GIR_EraseRootFromParent_Done,
     /*  702200 */   // Label 11078: @702200
     /*  702200 */   GIM_Try, /*On fail goto*//*Label 11079*/ GIMT_Encode4(702257), // Rule ID 21394 //
     /*  702205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  702208 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702215 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702228 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
     /*  702231 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702255 */     GIR_RootConstrainSelectedInstOperands,
     /*  702256 */     // GIR_Coverage, 21394,
     /*  702256 */     GIR_EraseRootFromParent_Done,
     /*  702257 */   // Label 11079: @702257
     /*  702257 */   GIM_Try, /*On fail goto*//*Label 11080*/ GIMT_Encode4(702314), // Rule ID 21395 //
     /*  702262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  702265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702272 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702285 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
     /*  702288 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702308 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702312 */     GIR_RootConstrainSelectedInstOperands,
     /*  702313 */     // GIR_Coverage, 21395,
     /*  702313 */     GIR_EraseRootFromParent_Done,
     /*  702314 */   // Label 11080: @702314
     /*  702314 */   GIM_Try, /*On fail goto*//*Label 11081*/ GIMT_Encode4(702371), // Rule ID 21396 //
     /*  702319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  702322 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702329 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702342 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
     /*  702345 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702365 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702369 */     GIR_RootConstrainSelectedInstOperands,
     /*  702370 */     // GIR_Coverage, 21396,
     /*  702370 */     GIR_EraseRootFromParent_Done,
     /*  702371 */   // Label 11081: @702371
     /*  702371 */   GIM_Try, /*On fail goto*//*Label 11082*/ GIMT_Encode4(702428), // Rule ID 21397 //
     /*  702376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  702379 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702386 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  702388 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702392 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702399 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
     /*  702402 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  702422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702426 */     GIR_RootConstrainSelectedInstOperands,
     /*  702427 */     // GIR_Coverage, 21397,
     /*  702427 */     GIR_EraseRootFromParent_Done,
     /*  702428 */   // Label 11082: @702428
     /*  702428 */   GIM_Try, /*On fail goto*//*Label 11083*/ GIMT_Encode4(702489), // Rule ID 21363 //
     /*  702433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  702436 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702447 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702451 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702458 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
     /*  702461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702463 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702487 */     GIR_RootConstrainSelectedInstOperands,
     /*  702488 */     // GIR_Coverage, 21363,
     /*  702488 */     GIR_EraseRootFromParent_Done,
     /*  702489 */   // Label 11083: @702489
     /*  702489 */   GIM_Try, /*On fail goto*//*Label 11084*/ GIMT_Encode4(702550), // Rule ID 21364 //
     /*  702494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  702497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702512 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702519 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
     /*  702522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702524 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702548 */     GIR_RootConstrainSelectedInstOperands,
     /*  702549 */     // GIR_Coverage, 21364,
     /*  702549 */     GIR_EraseRootFromParent_Done,
     /*  702550 */   // Label 11084: @702550
     /*  702550 */   GIM_Try, /*On fail goto*//*Label 11085*/ GIMT_Encode4(702611), // Rule ID 21365 //
     /*  702555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  702558 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702573 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702580 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
     /*  702583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702585 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702605 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702609 */     GIR_RootConstrainSelectedInstOperands,
     /*  702610 */     // GIR_Coverage, 21365,
     /*  702610 */     GIR_EraseRootFromParent_Done,
     /*  702611 */   // Label 11085: @702611
     /*  702611 */   GIM_Try, /*On fail goto*//*Label 11086*/ GIMT_Encode4(702672), // Rule ID 21366 //
     /*  702616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  702619 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702630 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702641 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
     /*  702644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702646 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702670 */     GIR_RootConstrainSelectedInstOperands,
     /*  702671 */     // GIR_Coverage, 21366,
     /*  702671 */     GIR_EraseRootFromParent_Done,
     /*  702672 */   // Label 11086: @702672
     /*  702672 */   GIM_Try, /*On fail goto*//*Label 11087*/ GIMT_Encode4(702733), // Rule ID 21367 //
     /*  702677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  702680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702702 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
     /*  702705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702707 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702731 */     GIR_RootConstrainSelectedInstOperands,
     /*  702732 */     // GIR_Coverage, 21367,
     /*  702732 */     GIR_EraseRootFromParent_Done,
     /*  702733 */   // Label 11087: @702733
     /*  702733 */   GIM_Try, /*On fail goto*//*Label 11088*/ GIMT_Encode4(702794), // Rule ID 21383 //
     /*  702738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  702741 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702763 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
     /*  702766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702768 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702792 */     GIR_RootConstrainSelectedInstOperands,
     /*  702793 */     // GIR_Coverage, 21383,
     /*  702793 */     GIR_EraseRootFromParent_Done,
     /*  702794 */   // Label 11088: @702794
     /*  702794 */   GIM_Try, /*On fail goto*//*Label 11089*/ GIMT_Encode4(702855), // Rule ID 21384 //
     /*  702799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  702802 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702817 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702824 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
     /*  702827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702829 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702853 */     GIR_RootConstrainSelectedInstOperands,
     /*  702854 */     // GIR_Coverage, 21384,
     /*  702854 */     GIR_EraseRootFromParent_Done,
     /*  702855 */   // Label 11089: @702855
     /*  702855 */   GIM_Try, /*On fail goto*//*Label 11090*/ GIMT_Encode4(702916), // Rule ID 21385 //
     /*  702860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  702863 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702874 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702885 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
     /*  702888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702890 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702910 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702914 */     GIR_RootConstrainSelectedInstOperands,
     /*  702915 */     // GIR_Coverage, 21385,
     /*  702915 */     GIR_EraseRootFromParent_Done,
     /*  702916 */   // Label 11090: @702916
     /*  702916 */   GIM_Try, /*On fail goto*//*Label 11091*/ GIMT_Encode4(702977), // Rule ID 21386 //
     /*  702921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  702924 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702935 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  702939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  702946 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  702946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
     /*  702949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  702951 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  702953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  702958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  702963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  702968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  702971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  702975 */     GIR_RootConstrainSelectedInstOperands,
     /*  702976 */     // GIR_Coverage, 21386,
     /*  702976 */     GIR_EraseRootFromParent_Done,
     /*  702977 */   // Label 11091: @702977
     /*  702977 */   GIM_Try, /*On fail goto*//*Label 11092*/ GIMT_Encode4(703038), // Rule ID 21387 //
     /*  702982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  702985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  702992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  702996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703000 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  703007 */     // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  703007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
     /*  703010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  703012 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  703014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  703019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  703024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  703029 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  703032 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703036 */     GIR_RootConstrainSelectedInstOperands,
     /*  703037 */     // GIR_Coverage, 21387,
     /*  703037 */     GIR_EraseRootFromParent_Done,
     /*  703038 */   // Label 11092: @703038
     /*  703038 */   GIM_Try, /*On fail goto*//*Label 11093*/ GIMT_Encode4(703088), // Rule ID 30835 //
     /*  703043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  703046 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703051 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703064 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703072 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703082 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703086 */     GIR_RootConstrainSelectedInstOperands,
     /*  703087 */     // GIR_Coverage, 30835,
     /*  703087 */     GIR_EraseRootFromParent_Done,
     /*  703088 */   // Label 11093: @703088
     /*  703088 */   GIM_Try, /*On fail goto*//*Label 11094*/ GIMT_Encode4(703138), // Rule ID 30836 //
     /*  703093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  703096 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703101 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703114 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703122 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703136 */     GIR_RootConstrainSelectedInstOperands,
     /*  703137 */     // GIR_Coverage, 30836,
     /*  703137 */     GIR_EraseRootFromParent_Done,
     /*  703138 */   // Label 11094: @703138
     /*  703138 */   GIM_Try, /*On fail goto*//*Label 11095*/ GIMT_Encode4(703188), // Rule ID 30837 //
     /*  703143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  703146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703151 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703164 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703172 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703186 */     GIR_RootConstrainSelectedInstOperands,
     /*  703187 */     // GIR_Coverage, 30837,
     /*  703187 */     GIR_EraseRootFromParent_Done,
     /*  703188 */   // Label 11095: @703188
     /*  703188 */   GIM_Try, /*On fail goto*//*Label 11096*/ GIMT_Encode4(703238), // Rule ID 30838 //
     /*  703193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  703196 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703201 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703214 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703222 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703236 */     GIR_RootConstrainSelectedInstOperands,
     /*  703237 */     // GIR_Coverage, 30838,
     /*  703237 */     GIR_EraseRootFromParent_Done,
     /*  703238 */   // Label 11096: @703238
     /*  703238 */   GIM_Try, /*On fail goto*//*Label 11097*/ GIMT_Encode4(703288), // Rule ID 30839 //
     /*  703243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  703246 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703251 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703264 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703272 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703286 */     GIR_RootConstrainSelectedInstOperands,
     /*  703287 */     // GIR_Coverage, 30839,
     /*  703287 */     GIR_EraseRootFromParent_Done,
     /*  703288 */   // Label 11097: @703288
     /*  703288 */   GIM_Try, /*On fail goto*//*Label 11098*/ GIMT_Encode4(703338), // Rule ID 30845 //
     /*  703293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  703296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703301 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703314 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i64>>  =>  (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9),
     /*  703317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703322 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703336 */     GIR_RootConstrainSelectedInstOperands,
     /*  703337 */     // GIR_Coverage, 30845,
     /*  703337 */     GIR_EraseRootFromParent_Done,
     /*  703338 */   // Label 11098: @703338
     /*  703338 */   GIM_Try, /*On fail goto*//*Label 11099*/ GIMT_Encode4(703388), // Rule ID 30846 //
     /*  703343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  703346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703351 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703353 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703364 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i64>>  =>  (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9),
     /*  703367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703372 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703386 */     GIR_RootConstrainSelectedInstOperands,
     /*  703387 */     // GIR_Coverage, 30846,
     /*  703387 */     GIR_EraseRootFromParent_Done,
     /*  703388 */   // Label 11099: @703388
     /*  703388 */   GIM_Try, /*On fail goto*//*Label 11100*/ GIMT_Encode4(703438), // Rule ID 30847 //
     /*  703393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  703396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703401 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703414 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i64>>  =>  (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9),
     /*  703417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703422 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703436 */     GIR_RootConstrainSelectedInstOperands,
     /*  703437 */     // GIR_Coverage, 30847,
     /*  703437 */     GIR_EraseRootFromParent_Done,
     /*  703438 */   // Label 11100: @703438
     /*  703438 */   GIM_Try, /*On fail goto*//*Label 11101*/ GIMT_Encode4(703488), // Rule ID 30848 //
     /*  703443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  703446 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703451 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703464 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i64>>  =>  (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9),
     /*  703467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703472 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703482 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703486 */     GIR_RootConstrainSelectedInstOperands,
     /*  703487 */     // GIR_Coverage, 30848,
     /*  703487 */     GIR_EraseRootFromParent_Done,
     /*  703488 */   // Label 11101: @703488
     /*  703488 */   GIM_Try, /*On fail goto*//*Label 11102*/ GIMT_Encode4(703538), // Rule ID 30849 //
     /*  703493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  703496 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703501 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703514 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i64>>  =>  (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9),
     /*  703517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703522 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703536 */     GIR_RootConstrainSelectedInstOperands,
     /*  703537 */     // GIR_Coverage, 30849,
     /*  703537 */     GIR_EraseRootFromParent_Done,
     /*  703538 */   // Label 11102: @703538
     /*  703538 */   GIM_Try, /*On fail goto*//*Label 11103*/ GIMT_Encode4(703588), // Rule ID 30855 //
     /*  703543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  703546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  703551 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703564 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  703564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703572 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  703582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703586 */     GIR_RootConstrainSelectedInstOperands,
     /*  703587 */     // GIR_Coverage, 30855,
     /*  703587 */     GIR_EraseRootFromParent_Done,
     /*  703588 */   // Label 11103: @703588
     /*  703588 */   GIM_Try, /*On fail goto*//*Label 11104*/ GIMT_Encode4(703638), // Rule ID 30856 //
     /*  703593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  703596 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  703601 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703603 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703614 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  703614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703622 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  703632 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703636 */     GIR_RootConstrainSelectedInstOperands,
     /*  703637 */     // GIR_Coverage, 30856,
     /*  703637 */     GIR_EraseRootFromParent_Done,
     /*  703638 */   // Label 11104: @703638
     /*  703638 */   GIM_Try, /*On fail goto*//*Label 11105*/ GIMT_Encode4(703688), // Rule ID 30857 //
     /*  703643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  703646 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  703651 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703664 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  703664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703672 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  703682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703686 */     GIR_RootConstrainSelectedInstOperands,
     /*  703687 */     // GIR_Coverage, 30857,
     /*  703687 */     GIR_EraseRootFromParent_Done,
     /*  703688 */   // Label 11105: @703688
     /*  703688 */   GIM_Try, /*On fail goto*//*Label 11106*/ GIMT_Encode4(703738), // Rule ID 30858 //
     /*  703693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  703696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  703701 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703703 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703714 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  703714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703722 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  703732 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703736 */     GIR_RootConstrainSelectedInstOperands,
     /*  703737 */     // GIR_Coverage, 30858,
     /*  703737 */     GIR_EraseRootFromParent_Done,
     /*  703738 */   // Label 11106: @703738
     /*  703738 */   GIM_Try, /*On fail goto*//*Label 11107*/ GIMT_Encode4(703788), // Rule ID 30859 //
     /*  703743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  703746 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  703751 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  703753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703764 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  703764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
     /*  703767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703772 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  703782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703786 */     GIR_RootConstrainSelectedInstOperands,
     /*  703787 */     // GIR_Coverage, 30859,
     /*  703787 */     GIR_EraseRootFromParent_Done,
     /*  703788 */   // Label 11107: @703788
     /*  703788 */   GIM_Try, /*On fail goto*//*Label 11108*/ GIMT_Encode4(703842), // Rule ID 30830 //
     /*  703793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  703796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  703805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703816 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  703819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  703821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703826 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703840 */     GIR_RootConstrainSelectedInstOperands,
     /*  703841 */     // GIR_Coverage, 30830,
     /*  703841 */     GIR_EraseRootFromParent_Done,
     /*  703842 */   // Label 11108: @703842
     /*  703842 */   GIM_Try, /*On fail goto*//*Label 11109*/ GIMT_Encode4(703896), // Rule ID 30831 //
     /*  703847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  703850 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  703859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703870 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  703873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  703875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703880 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703894 */     GIR_RootConstrainSelectedInstOperands,
     /*  703895 */     // GIR_Coverage, 30831,
     /*  703895 */     GIR_EraseRootFromParent_Done,
     /*  703896 */   // Label 11109: @703896
     /*  703896 */   GIM_Try, /*On fail goto*//*Label 11110*/ GIMT_Encode4(703950), // Rule ID 30832 //
     /*  703901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  703904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  703913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703924 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  703927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  703929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703934 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  703948 */     GIR_RootConstrainSelectedInstOperands,
     /*  703949 */     // GIR_Coverage, 30832,
     /*  703949 */     GIR_EraseRootFromParent_Done,
     /*  703950 */   // Label 11110: @703950
     /*  703950 */   GIM_Try, /*On fail goto*//*Label 11111*/ GIMT_Encode4(704004), // Rule ID 30833 //
     /*  703955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  703958 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  703963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  703967 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  703971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  703978 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  703978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  703981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  703983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  703988 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  703990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  703995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  703998 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704002 */     GIR_RootConstrainSelectedInstOperands,
     /*  704003 */     // GIR_Coverage, 30833,
     /*  704003 */     GIR_EraseRootFromParent_Done,
     /*  704004 */   // Label 11111: @704004
     /*  704004 */   GIM_Try, /*On fail goto*//*Label 11112*/ GIMT_Encode4(704058), // Rule ID 30834 //
     /*  704009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  704012 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  704017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704021 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704025 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704032 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  704032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  704035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704042 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704049 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  704052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704056 */     GIR_RootConstrainSelectedInstOperands,
     /*  704057 */     // GIR_Coverage, 30834,
     /*  704057 */     GIR_EraseRootFromParent_Done,
     /*  704058 */   // Label 11112: @704058
     /*  704058 */   GIM_Try, /*On fail goto*//*Label 11113*/ GIMT_Encode4(704112), // Rule ID 30840 //
     /*  704063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  704066 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  704071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704086 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_i64>>  =>  (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  704086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9),
     /*  704089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704096 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  704106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704110 */     GIR_RootConstrainSelectedInstOperands,
     /*  704111 */     // GIR_Coverage, 30840,
     /*  704111 */     GIR_EraseRootFromParent_Done,
     /*  704112 */   // Label 11113: @704112
     /*  704112 */   GIM_Try, /*On fail goto*//*Label 11114*/ GIMT_Encode4(704166), // Rule ID 30841 //
     /*  704117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  704120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  704125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704133 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704140 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_i64>>  =>  (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  704140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9),
     /*  704143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704150 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  704160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704164 */     GIR_RootConstrainSelectedInstOperands,
     /*  704165 */     // GIR_Coverage, 30841,
     /*  704165 */     GIR_EraseRootFromParent_Done,
     /*  704166 */   // Label 11114: @704166
     /*  704166 */   GIM_Try, /*On fail goto*//*Label 11115*/ GIMT_Encode4(704220), // Rule ID 30842 //
     /*  704171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  704174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  704179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704194 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_i64>>  =>  (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  704194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9),
     /*  704197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704204 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  704214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704218 */     GIR_RootConstrainSelectedInstOperands,
     /*  704219 */     // GIR_Coverage, 30842,
     /*  704219 */     GIR_EraseRootFromParent_Done,
     /*  704220 */   // Label 11115: @704220
     /*  704220 */   GIM_Try, /*On fail goto*//*Label 11116*/ GIMT_Encode4(704274), // Rule ID 30843 //
     /*  704225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  704228 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  704233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704237 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704248 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_i64>>  =>  (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  704248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9),
     /*  704251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704258 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  704268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704272 */     GIR_RootConstrainSelectedInstOperands,
     /*  704273 */     // GIR_Coverage, 30843,
     /*  704273 */     GIR_EraseRootFromParent_Done,
     /*  704274 */   // Label 11116: @704274
     /*  704274 */   GIM_Try, /*On fail goto*//*Label 11117*/ GIMT_Encode4(704328), // Rule ID 30844 //
     /*  704279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  704282 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  704287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704302 */     // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_i64>>  =>  (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  704302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9),
     /*  704305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704312 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  704322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704326 */     GIR_RootConstrainSelectedInstOperands,
     /*  704327 */     // GIR_Coverage, 30844,
     /*  704327 */     GIR_EraseRootFromParent_Done,
     /*  704328 */   // Label 11117: @704328
     /*  704328 */   GIM_Try, /*On fail goto*//*Label 11118*/ GIMT_Encode4(704382), // Rule ID 30850 //
     /*  704333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  704336 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  704341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704356 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  704356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  704359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704366 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  704376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704380 */     GIR_RootConstrainSelectedInstOperands,
     /*  704381 */     // GIR_Coverage, 30850,
     /*  704381 */     GIR_EraseRootFromParent_Done,
     /*  704382 */   // Label 11118: @704382
     /*  704382 */   GIM_Try, /*On fail goto*//*Label 11119*/ GIMT_Encode4(704436), // Rule ID 30851 //
     /*  704387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  704390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  704395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704410 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  704410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  704413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704420 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  704430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704434 */     GIR_RootConstrainSelectedInstOperands,
     /*  704435 */     // GIR_Coverage, 30851,
     /*  704435 */     GIR_EraseRootFromParent_Done,
     /*  704436 */   // Label 11119: @704436
     /*  704436 */   GIM_Try, /*On fail goto*//*Label 11120*/ GIMT_Encode4(704490), // Rule ID 30852 //
     /*  704441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  704444 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  704449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704464 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  704464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  704467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704474 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  704484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704488 */     GIR_RootConstrainSelectedInstOperands,
     /*  704489 */     // GIR_Coverage, 30852,
     /*  704489 */     GIR_EraseRootFromParent_Done,
     /*  704490 */   // Label 11120: @704490
     /*  704490 */   GIM_Try, /*On fail goto*//*Label 11121*/ GIMT_Encode4(704544), // Rule ID 30853 //
     /*  704495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  704498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  704503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704507 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704518 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  704518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  704521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704528 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  704538 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704542 */     GIR_RootConstrainSelectedInstOperands,
     /*  704543 */     // GIR_Coverage, 30853,
     /*  704543 */     GIR_EraseRootFromParent_Done,
     /*  704544 */   // Label 11121: @704544
     /*  704544 */   GIM_Try, /*On fail goto*//*Label 11122*/ GIMT_Encode4(704598), // Rule ID 30854 //
     /*  704549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  704552 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  704557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  704572 */     // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  704572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
     /*  704575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  704582 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  704584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  704589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  704592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704596 */     GIR_RootConstrainSelectedInstOperands,
     /*  704597 */     // GIR_Coverage, 30854,
     /*  704597 */     GIR_EraseRootFromParent_Done,
     /*  704598 */   // Label 11122: @704598
     /*  704598 */   GIM_Try, /*On fail goto*//*Label 11123*/ GIMT_Encode4(704657), // Rule ID 13265 //
     /*  704603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  704606 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704613 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  704615 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  704626 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR),
     /*  704629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704634 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  704641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  704646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  704651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704655 */     GIR_RootConstrainSelectedInstOperands,
     /*  704656 */     // GIR_Coverage, 13265,
     /*  704656 */     GIR_EraseRootFromParent_Done,
     /*  704657 */   // Label 11123: @704657
     /*  704657 */   GIM_Try, /*On fail goto*//*Label 11124*/ GIMT_Encode4(704716), // Rule ID 13266 //
     /*  704662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  704665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704672 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  704674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  704685 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR),
     /*  704688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704693 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  704700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  704705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  704710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704714 */     GIR_RootConstrainSelectedInstOperands,
     /*  704715 */     // GIR_Coverage, 13266,
     /*  704715 */     GIR_EraseRootFromParent_Done,
     /*  704716 */   // Label 11124: @704716
     /*  704716 */   GIM_Try, /*On fail goto*//*Label 11125*/ GIMT_Encode4(704775), // Rule ID 13267 //
     /*  704721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  704724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704731 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  704733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  704744 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR),
     /*  704747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704752 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  704759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  704764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  704769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704773 */     GIR_RootConstrainSelectedInstOperands,
     /*  704774 */     // GIR_Coverage, 13267,
     /*  704774 */     GIR_EraseRootFromParent_Done,
     /*  704775 */   // Label 11125: @704775
     /*  704775 */   GIM_Try, /*On fail goto*//*Label 11126*/ GIMT_Encode4(704834), // Rule ID 13268 //
     /*  704780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  704783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704790 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  704792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  704803 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR),
     /*  704806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704811 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  704818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  704823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  704828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704832 */     GIR_RootConstrainSelectedInstOperands,
     /*  704833 */     // GIR_Coverage, 13268,
     /*  704833 */     GIR_EraseRootFromParent_Done,
     /*  704834 */   // Label 11126: @704834
     /*  704834 */   GIM_Try, /*On fail goto*//*Label 11127*/ GIMT_Encode4(704893), // Rule ID 13269 //
     /*  704839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  704842 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704849 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  704851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  704862 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR),
     /*  704865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704870 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  704877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  704882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  704887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704891 */     GIR_RootConstrainSelectedInstOperands,
     /*  704892 */     // GIR_Coverage, 13269,
     /*  704892 */     GIR_EraseRootFromParent_Done,
     /*  704893 */   // Label 11127: @704893
     /*  704893 */   GIM_Try, /*On fail goto*//*Label 11128*/ GIMT_Encode4(704956), // Rule ID 13275 //
     /*  704898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  704901 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  704923 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  704926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704933 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  704940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  704945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  704950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  704954 */     GIR_RootConstrainSelectedInstOperands,
     /*  704955 */     // GIR_Coverage, 13275,
     /*  704955 */     GIR_EraseRootFromParent_Done,
     /*  704956 */   // Label 11128: @704956
     /*  704956 */   GIM_Try, /*On fail goto*//*Label 11129*/ GIMT_Encode4(705019), // Rule ID 13276 //
     /*  704961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  704964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  704971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  704975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  704979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  704986 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  704986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  704989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  704991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  704996 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  704998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705017 */     GIR_RootConstrainSelectedInstOperands,
     /*  705018 */     // GIR_Coverage, 13276,
     /*  705018 */     GIR_EraseRootFromParent_Done,
     /*  705019 */   // Label 11129: @705019
     /*  705019 */   GIM_Try, /*On fail goto*//*Label 11130*/ GIMT_Encode4(705082), // Rule ID 13277 //
     /*  705024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  705027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  705049 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  705052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705059 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705080 */     GIR_RootConstrainSelectedInstOperands,
     /*  705081 */     // GIR_Coverage, 13277,
     /*  705081 */     GIR_EraseRootFromParent_Done,
     /*  705082 */   // Label 11130: @705082
     /*  705082 */   GIM_Try, /*On fail goto*//*Label 11131*/ GIMT_Encode4(705145), // Rule ID 13278 //
     /*  705087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  705090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  705112 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  705115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705122 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705143 */     GIR_RootConstrainSelectedInstOperands,
     /*  705144 */     // GIR_Coverage, 13278,
     /*  705144 */     GIR_EraseRootFromParent_Done,
     /*  705145 */   // Label 11131: @705145
     /*  705145 */   GIM_Try, /*On fail goto*//*Label 11132*/ GIMT_Encode4(705208), // Rule ID 13279 //
     /*  705150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  705153 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  705175 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  705178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705185 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705206 */     GIR_RootConstrainSelectedInstOperands,
     /*  705207 */     // GIR_Coverage, 13279,
     /*  705207 */     GIR_EraseRootFromParent_Done,
     /*  705208 */   // Label 11132: @705208
     /*  705208 */   GIM_Try, /*On fail goto*//*Label 11133*/ GIMT_Encode4(705260), // Rule ID 13260 //
     /*  705213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  705216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705236 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2),
     /*  705239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705244 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  705254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705258 */     GIR_RootConstrainSelectedInstOperands,
     /*  705259 */     // GIR_Coverage, 13260,
     /*  705259 */     GIR_EraseRootFromParent_Done,
     /*  705260 */   // Label 11133: @705260
     /*  705260 */   GIM_Try, /*On fail goto*//*Label 11134*/ GIMT_Encode4(705312), // Rule ID 13261 //
     /*  705265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  705268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705275 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705288 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2),
     /*  705291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705296 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  705306 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705310 */     GIR_RootConstrainSelectedInstOperands,
     /*  705311 */     // GIR_Coverage, 13261,
     /*  705311 */     GIR_EraseRootFromParent_Done,
     /*  705312 */   // Label 11134: @705312
     /*  705312 */   GIM_Try, /*On fail goto*//*Label 11135*/ GIMT_Encode4(705364), // Rule ID 13262 //
     /*  705317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  705320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705327 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705340 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2),
     /*  705343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705348 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  705358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705362 */     GIR_RootConstrainSelectedInstOperands,
     /*  705363 */     // GIR_Coverage, 13262,
     /*  705363 */     GIR_EraseRootFromParent_Done,
     /*  705364 */   // Label 11135: @705364
     /*  705364 */   GIM_Try, /*On fail goto*//*Label 11136*/ GIMT_Encode4(705416), // Rule ID 13263 //
     /*  705369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  705372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705392 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2),
     /*  705395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  705410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705414 */     GIR_RootConstrainSelectedInstOperands,
     /*  705415 */     // GIR_Coverage, 13263,
     /*  705415 */     GIR_EraseRootFromParent_Done,
     /*  705416 */   // Label 11136: @705416
     /*  705416 */   GIM_Try, /*On fail goto*//*Label 11137*/ GIMT_Encode4(705468), // Rule ID 13264 //
     /*  705421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  705424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705431 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705444 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2),
     /*  705447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705452 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  705462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705466 */     GIR_RootConstrainSelectedInstOperands,
     /*  705467 */     // GIR_Coverage, 13264,
     /*  705467 */     GIR_EraseRootFromParent_Done,
     /*  705468 */   // Label 11137: @705468
     /*  705468 */   GIM_Try, /*On fail goto*//*Label 11138*/ GIMT_Encode4(705524), // Rule ID 13270 //
     /*  705473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  705476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705498 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN),
     /*  705501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705508 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  705518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705522 */     GIR_RootConstrainSelectedInstOperands,
     /*  705523 */     // GIR_Coverage, 13270,
     /*  705523 */     GIR_EraseRootFromParent_Done,
     /*  705524 */   // Label 11138: @705524
     /*  705524 */   GIM_Try, /*On fail goto*//*Label 11139*/ GIMT_Encode4(705580), // Rule ID 13271 //
     /*  705529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  705532 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705554 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN),
     /*  705557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705564 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  705574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705578 */     GIR_RootConstrainSelectedInstOperands,
     /*  705579 */     // GIR_Coverage, 13271,
     /*  705579 */     GIR_EraseRootFromParent_Done,
     /*  705580 */   // Label 11139: @705580
     /*  705580 */   GIM_Try, /*On fail goto*//*Label 11140*/ GIMT_Encode4(705636), // Rule ID 13272 //
     /*  705585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  705588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705599 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705603 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705610 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN),
     /*  705613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705620 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  705630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705634 */     GIR_RootConstrainSelectedInstOperands,
     /*  705635 */     // GIR_Coverage, 13272,
     /*  705635 */     GIR_EraseRootFromParent_Done,
     /*  705636 */   // Label 11140: @705636
     /*  705636 */   GIM_Try, /*On fail goto*//*Label 11141*/ GIMT_Encode4(705692), // Rule ID 13273 //
     /*  705641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  705644 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705666 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN),
     /*  705669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705676 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  705686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705690 */     GIR_RootConstrainSelectedInstOperands,
     /*  705691 */     // GIR_Coverage, 13273,
     /*  705691 */     GIR_EraseRootFromParent_Done,
     /*  705692 */   // Label 11141: @705692
     /*  705692 */   GIM_Try, /*On fail goto*//*Label 11142*/ GIMT_Encode4(705748), // Rule ID 13274 //
     /*  705697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  705700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  705711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  705722 */     // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  705722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN),
     /*  705725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  705727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  705732 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  705739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  705742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705746 */     GIR_RootConstrainSelectedInstOperands,
     /*  705747 */     // GIR_Coverage, 13274,
     /*  705747 */     GIR_EraseRootFromParent_Done,
     /*  705748 */   // Label 11142: @705748
     /*  705748 */   GIM_Try, /*On fail goto*//*Label 11143*/ GIMT_Encode4(705808), // Rule ID 10857 //
     /*  705753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  705756 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705764 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  705777 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  705780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705785 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705802 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705806 */     GIR_RootConstrainSelectedInstOperands,
     /*  705807 */     // GIR_Coverage, 10857,
     /*  705807 */     GIR_EraseRootFromParent_Done,
     /*  705808 */   // Label 11143: @705808
     /*  705808 */   GIM_Try, /*On fail goto*//*Label 11144*/ GIMT_Encode4(705868), // Rule ID 10858 //
     /*  705813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  705816 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705824 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  705837 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  705840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705845 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705866 */     GIR_RootConstrainSelectedInstOperands,
     /*  705867 */     // GIR_Coverage, 10858,
     /*  705867 */     GIR_EraseRootFromParent_Done,
     /*  705868 */   // Label 11144: @705868
     /*  705868 */   GIM_Try, /*On fail goto*//*Label 11145*/ GIMT_Encode4(705928), // Rule ID 10859 //
     /*  705873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  705876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705884 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705886 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  705897 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  705900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705905 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705926 */     GIR_RootConstrainSelectedInstOperands,
     /*  705927 */     // GIR_Coverage, 10859,
     /*  705927 */     GIR_EraseRootFromParent_Done,
     /*  705928 */   // Label 11145: @705928
     /*  705928 */   GIM_Try, /*On fail goto*//*Label 11146*/ GIMT_Encode4(705988), // Rule ID 10860 //
     /*  705933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  705936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  705944 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  705946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  705950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  705957 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  705957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  705960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  705965 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  705967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  705972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  705977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  705982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  705986 */     GIR_RootConstrainSelectedInstOperands,
     /*  705987 */     // GIR_Coverage, 10860,
     /*  705987 */     GIR_EraseRootFromParent_Done,
     /*  705988 */   // Label 11146: @705988
     /*  705988 */   GIM_Try, /*On fail goto*//*Label 11147*/ GIMT_Encode4(706048), // Rule ID 10861 //
     /*  705993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  705996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706004 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706006 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706010 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  706017 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  706020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706025 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706046 */     GIR_RootConstrainSelectedInstOperands,
     /*  706047 */     // GIR_Coverage, 10861,
     /*  706047 */     GIR_EraseRootFromParent_Done,
     /*  706048 */   // Label 11147: @706048
     /*  706048 */   GIM_Try, /*On fail goto*//*Label 11148*/ GIMT_Encode4(706107), // Rule ID 11413 //
     /*  706053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  706056 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706063 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  706076 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  706079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706084 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706105 */     GIR_RootConstrainSelectedInstOperands,
     /*  706106 */     // GIR_Coverage, 11413,
     /*  706106 */     GIR_EraseRootFromParent_Done,
     /*  706107 */   // Label 11148: @706107
     /*  706107 */   GIM_Try, /*On fail goto*//*Label 11149*/ GIMT_Encode4(706166), // Rule ID 11414 //
     /*  706112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  706115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706122 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706124 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706128 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  706135 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  706138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706143 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706160 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706164 */     GIR_RootConstrainSelectedInstOperands,
     /*  706165 */     // GIR_Coverage, 11414,
     /*  706165 */     GIR_EraseRootFromParent_Done,
     /*  706166 */   // Label 11149: @706166
     /*  706166 */   GIM_Try, /*On fail goto*//*Label 11150*/ GIMT_Encode4(706225), // Rule ID 11415 //
     /*  706171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  706174 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706181 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  706194 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  706197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706202 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706219 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706223 */     GIR_RootConstrainSelectedInstOperands,
     /*  706224 */     // GIR_Coverage, 11415,
     /*  706224 */     GIR_EraseRootFromParent_Done,
     /*  706225 */   // Label 11150: @706225
     /*  706225 */   GIM_Try, /*On fail goto*//*Label 11151*/ GIMT_Encode4(706284), // Rule ID 11416 //
     /*  706230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  706233 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706240 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706246 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  706253 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  706256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706261 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706282 */     GIR_RootConstrainSelectedInstOperands,
     /*  706283 */     // GIR_Coverage, 11416,
     /*  706283 */     GIR_EraseRootFromParent_Done,
     /*  706284 */   // Label 11151: @706284
     /*  706284 */   GIM_Try, /*On fail goto*//*Label 11152*/ GIMT_Encode4(706343), // Rule ID 11417 //
     /*  706289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  706292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706299 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  706312 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR),
     /*  706315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706320 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706337 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706341 */     GIR_RootConstrainSelectedInstOperands,
     /*  706342 */     // GIR_Coverage, 11417,
     /*  706342 */     GIR_EraseRootFromParent_Done,
     /*  706343 */   // Label 11152: @706343
     /*  706343 */   GIM_Try, /*On fail goto*//*Label 11153*/ GIMT_Encode4(706407), // Rule ID 10847 //
     /*  706348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  706351 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706374 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706384 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706405 */     GIR_RootConstrainSelectedInstOperands,
     /*  706406 */     // GIR_Coverage, 10847,
     /*  706406 */     GIR_EraseRootFromParent_Done,
     /*  706407 */   // Label 11153: @706407
     /*  706407 */   GIM_Try, /*On fail goto*//*Label 11154*/ GIMT_Encode4(706471), // Rule ID 10848 //
     /*  706412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  706415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706438 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706448 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706469 */     GIR_RootConstrainSelectedInstOperands,
     /*  706470 */     // GIR_Coverage, 10848,
     /*  706470 */     GIR_EraseRootFromParent_Done,
     /*  706471 */   // Label 11154: @706471
     /*  706471 */   GIM_Try, /*On fail goto*//*Label 11155*/ GIMT_Encode4(706535), // Rule ID 10849 //
     /*  706476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  706479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706502 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706512 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706529 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706533 */     GIR_RootConstrainSelectedInstOperands,
     /*  706534 */     // GIR_Coverage, 10849,
     /*  706534 */     GIR_EraseRootFromParent_Done,
     /*  706535 */   // Label 11155: @706535
     /*  706535 */   GIM_Try, /*On fail goto*//*Label 11156*/ GIMT_Encode4(706599), // Rule ID 10850 //
     /*  706540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  706543 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706555 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706559 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706566 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706576 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706593 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706597 */     GIR_RootConstrainSelectedInstOperands,
     /*  706598 */     // GIR_Coverage, 10850,
     /*  706598 */     GIR_EraseRootFromParent_Done,
     /*  706599 */   // Label 11156: @706599
     /*  706599 */   GIM_Try, /*On fail goto*//*Label 11157*/ GIMT_Encode4(706663), // Rule ID 10851 //
     /*  706604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  706607 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706619 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706630 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706640 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706661 */     GIR_RootConstrainSelectedInstOperands,
     /*  706662 */     // GIR_Coverage, 10851,
     /*  706662 */     GIR_EraseRootFromParent_Done,
     /*  706663 */   // Label 11157: @706663
     /*  706663 */   GIM_Try, /*On fail goto*//*Label 11158*/ GIMT_Encode4(706726), // Rule ID 11403 //
     /*  706668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  706671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706693 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706703 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706720 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706724 */     GIR_RootConstrainSelectedInstOperands,
     /*  706725 */     // GIR_Coverage, 11403,
     /*  706725 */     GIR_EraseRootFromParent_Done,
     /*  706726 */   // Label 11158: @706726
     /*  706726 */   GIM_Try, /*On fail goto*//*Label 11159*/ GIMT_Encode4(706789), // Rule ID 11404 //
     /*  706731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  706734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706756 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706766 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706787 */     GIR_RootConstrainSelectedInstOperands,
     /*  706788 */     // GIR_Coverage, 11404,
     /*  706788 */     GIR_EraseRootFromParent_Done,
     /*  706789 */   // Label 11159: @706789
     /*  706789 */   GIM_Try, /*On fail goto*//*Label 11160*/ GIMT_Encode4(706852), // Rule ID 11405 //
     /*  706794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  706797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706808 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706812 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706819 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706829 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706850 */     GIR_RootConstrainSelectedInstOperands,
     /*  706851 */     // GIR_Coverage, 11405,
     /*  706851 */     GIR_EraseRootFromParent_Done,
     /*  706852 */   // Label 11160: @706852
     /*  706852 */   GIM_Try, /*On fail goto*//*Label 11161*/ GIMT_Encode4(706915), // Rule ID 11406 //
     /*  706857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  706860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706882 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706892 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706913 */     GIR_RootConstrainSelectedInstOperands,
     /*  706914 */     // GIR_Coverage, 11406,
     /*  706914 */     GIR_EraseRootFromParent_Done,
     /*  706915 */   // Label 11161: @706915
     /*  706915 */   GIM_Try, /*On fail goto*//*Label 11162*/ GIMT_Encode4(706978), // Rule ID 11407 //
     /*  706920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  706923 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  706934 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  706938 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  706945 */     // (atomic_load_umin:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  706945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_SADDR_RTN),
     /*  706948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  706950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  706955 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  706957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  706962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  706967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  706972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  706976 */     GIR_RootConstrainSelectedInstOperands,
     /*  706977 */     // GIR_Coverage, 11407,
     /*  706977 */     GIR_EraseRootFromParent_Done,
     /*  706978 */   // Label 11162: @706978
     /*  706978 */   GIM_Try, /*On fail goto*//*Label 11163*/ GIMT_Encode4(707031), // Rule ID 10852 //
     /*  706983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  706986 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  706994 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  706996 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707000 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707007 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707015 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707022 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707025 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707029 */     GIR_RootConstrainSelectedInstOperands,
     /*  707030 */     // GIR_Coverage, 10852,
     /*  707030 */     GIR_EraseRootFromParent_Done,
     /*  707031 */   // Label 11163: @707031
     /*  707031 */   GIM_Try, /*On fail goto*//*Label 11164*/ GIMT_Encode4(707084), // Rule ID 10853 //
     /*  707036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  707039 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707047 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707060 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707068 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707082 */     GIR_RootConstrainSelectedInstOperands,
     /*  707083 */     // GIR_Coverage, 10853,
     /*  707083 */     GIR_EraseRootFromParent_Done,
     /*  707084 */   // Label 11164: @707084
     /*  707084 */   GIM_Try, /*On fail goto*//*Label 11165*/ GIMT_Encode4(707137), // Rule ID 10854 //
     /*  707089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  707092 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707100 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707102 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707113 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707121 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707135 */     GIR_RootConstrainSelectedInstOperands,
     /*  707136 */     // GIR_Coverage, 10854,
     /*  707136 */     GIR_EraseRootFromParent_Done,
     /*  707137 */   // Label 11165: @707137
     /*  707137 */   GIM_Try, /*On fail goto*//*Label 11166*/ GIMT_Encode4(707190), // Rule ID 10855 //
     /*  707142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  707145 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707153 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707166 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707174 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707188 */     GIR_RootConstrainSelectedInstOperands,
     /*  707189 */     // GIR_Coverage, 10855,
     /*  707189 */     GIR_EraseRootFromParent_Done,
     /*  707190 */   // Label 11166: @707190
     /*  707190 */   GIM_Try, /*On fail goto*//*Label 11167*/ GIMT_Encode4(707243), // Rule ID 10856 //
     /*  707195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  707198 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707206 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707208 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707219 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707227 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707241 */     GIR_RootConstrainSelectedInstOperands,
     /*  707242 */     // GIR_Coverage, 10856,
     /*  707242 */     GIR_EraseRootFromParent_Done,
     /*  707243 */   // Label 11167: @707243
     /*  707243 */   GIM_Try, /*On fail goto*//*Label 11168*/ GIMT_Encode4(707295), // Rule ID 11408 //
     /*  707248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  707251 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707258 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707271 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707279 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707293 */     GIR_RootConstrainSelectedInstOperands,
     /*  707294 */     // GIR_Coverage, 11408,
     /*  707294 */     GIR_EraseRootFromParent_Done,
     /*  707295 */   // Label 11168: @707295
     /*  707295 */   GIM_Try, /*On fail goto*//*Label 11169*/ GIMT_Encode4(707347), // Rule ID 11409 //
     /*  707300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  707303 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707310 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707312 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707316 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707323 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707331 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707345 */     GIR_RootConstrainSelectedInstOperands,
     /*  707346 */     // GIR_Coverage, 11409,
     /*  707346 */     GIR_EraseRootFromParent_Done,
     /*  707347 */   // Label 11169: @707347
     /*  707347 */   GIM_Try, /*On fail goto*//*Label 11170*/ GIMT_Encode4(707399), // Rule ID 11410 //
     /*  707352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  707355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707362 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707375 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707383 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707397 */     GIR_RootConstrainSelectedInstOperands,
     /*  707398 */     // GIR_Coverage, 11410,
     /*  707398 */     GIR_EraseRootFromParent_Done,
     /*  707399 */   // Label 11170: @707399
     /*  707399 */   GIM_Try, /*On fail goto*//*Label 11171*/ GIMT_Encode4(707451), // Rule ID 11411 //
     /*  707404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  707407 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707414 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707427 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707435 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707449 */     GIR_RootConstrainSelectedInstOperands,
     /*  707450 */     // GIR_Coverage, 11411,
     /*  707450 */     GIR_EraseRootFromParent_Done,
     /*  707451 */   // Label 11171: @707451
     /*  707451 */   GIM_Try, /*On fail goto*//*Label 11172*/ GIMT_Encode4(707503), // Rule ID 11412 //
     /*  707456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  707459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707466 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  707468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707479 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
     /*  707482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707487 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  707497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707501 */     GIR_RootConstrainSelectedInstOperands,
     /*  707502 */     // GIR_Coverage, 11412,
     /*  707502 */     GIR_EraseRootFromParent_Done,
     /*  707503 */   // Label 11172: @707503
     /*  707503 */   GIM_Try, /*On fail goto*//*Label 11173*/ GIMT_Encode4(707560), // Rule ID 10842 //
     /*  707508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  707511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707534 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707544 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707558 */     GIR_RootConstrainSelectedInstOperands,
     /*  707559 */     // GIR_Coverage, 10842,
     /*  707559 */     GIR_EraseRootFromParent_Done,
     /*  707560 */   // Label 11173: @707560
     /*  707560 */   GIM_Try, /*On fail goto*//*Label 11174*/ GIMT_Encode4(707617), // Rule ID 10843 //
     /*  707565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  707568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707591 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707601 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707615 */     GIR_RootConstrainSelectedInstOperands,
     /*  707616 */     // GIR_Coverage, 10843,
     /*  707616 */     GIR_EraseRootFromParent_Done,
     /*  707617 */   // Label 11174: @707617
     /*  707617 */   GIM_Try, /*On fail goto*//*Label 11175*/ GIMT_Encode4(707674), // Rule ID 10844 //
     /*  707622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  707625 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707648 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707658 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707668 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707672 */     GIR_RootConstrainSelectedInstOperands,
     /*  707673 */     // GIR_Coverage, 10844,
     /*  707673 */     GIR_EraseRootFromParent_Done,
     /*  707674 */   // Label 11175: @707674
     /*  707674 */   GIM_Try, /*On fail goto*//*Label 11176*/ GIMT_Encode4(707731), // Rule ID 10845 //
     /*  707679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  707682 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707705 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707715 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707729 */     GIR_RootConstrainSelectedInstOperands,
     /*  707730 */     // GIR_Coverage, 10845,
     /*  707730 */     GIR_EraseRootFromParent_Done,
     /*  707731 */   // Label 11176: @707731
     /*  707731 */   GIM_Try, /*On fail goto*//*Label 11177*/ GIMT_Encode4(707788), // Rule ID 10846 //
     /*  707736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  707739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707762 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707772 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707786 */     GIR_RootConstrainSelectedInstOperands,
     /*  707787 */     // GIR_Coverage, 10846,
     /*  707787 */     GIR_EraseRootFromParent_Done,
     /*  707788 */   // Label 11177: @707788
     /*  707788 */   GIM_Try, /*On fail goto*//*Label 11178*/ GIMT_Encode4(707844), // Rule ID 11398 //
     /*  707793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  707796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707818 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707828 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707835 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707842 */     GIR_RootConstrainSelectedInstOperands,
     /*  707843 */     // GIR_Coverage, 11398,
     /*  707843 */     GIR_EraseRootFromParent_Done,
     /*  707844 */   // Label 11178: @707844
     /*  707844 */   GIM_Try, /*On fail goto*//*Label 11179*/ GIMT_Encode4(707900), // Rule ID 11399 //
     /*  707849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  707852 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707874 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707884 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707898 */     GIR_RootConstrainSelectedInstOperands,
     /*  707899 */     // GIR_Coverage, 11399,
     /*  707899 */     GIR_EraseRootFromParent_Done,
     /*  707900 */   // Label 11179: @707900
     /*  707900 */   GIM_Try, /*On fail goto*//*Label 11180*/ GIMT_Encode4(707956), // Rule ID 11400 //
     /*  707905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  707908 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707930 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707940 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  707947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  707950 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  707954 */     GIR_RootConstrainSelectedInstOperands,
     /*  707955 */     // GIR_Coverage, 11400,
     /*  707955 */     GIR_EraseRootFromParent_Done,
     /*  707956 */   // Label 11180: @707956
     /*  707956 */   GIM_Try, /*On fail goto*//*Label 11181*/ GIMT_Encode4(708012), // Rule ID 11401 //
     /*  707961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  707964 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  707971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  707975 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  707979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  707986 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  707986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  707989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  707991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  707996 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  707998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708010 */     GIR_RootConstrainSelectedInstOperands,
     /*  708011 */     // GIR_Coverage, 11401,
     /*  708011 */     GIR_EraseRootFromParent_Done,
     /*  708012 */   // Label 11181: @708012
     /*  708012 */   GIM_Try, /*On fail goto*//*Label 11182*/ GIMT_Encode4(708068), // Rule ID 11402 //
     /*  708017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  708020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  708027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  708031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  708042 */     // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  708042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
     /*  708045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  708047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  708052 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  708054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708062 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708066 */     GIR_RootConstrainSelectedInstOperands,
     /*  708067 */     // GIR_Coverage, 11402,
     /*  708067 */     GIR_EraseRootFromParent_Done,
     /*  708068 */   // Label 11182: @708068
     /*  708068 */   GIM_Reject,
     /*  708069 */ // Label 11052: @708069
     /*  708069 */ GIM_Reject,
     /*  708070 */ // Label 10944: @708070
     /*  708070 */ GIM_Reject,
     /*  708071 */ // Label 29: @708071
     /*  708071 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 11186*/ GIMT_Encode4(716663),
     /*  708082 */ /*GILLT_s32*//*Label 11183*/ GIMT_Encode4(708094),
     /*  708086 */ /*GILLT_s64*//*Label 11184*/ GIMT_Encode4(710828),
     /*  708090 */ /*GILLT_v2s16*//*Label 11185*/ GIMT_Encode4(713678),
     /*  708094 */ // Label 11183: @708094
     /*  708094 */ GIM_Try, /*On fail goto*//*Label 11187*/ GIMT_Encode4(710827),
     /*  708099 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  708102 */   GIM_Try, /*On fail goto*//*Label 11188*/ GIMT_Encode4(708152), // Rule ID 30528 //
     /*  708107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode0),
     /*  708110 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708115 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708128 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708136 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708150 */     GIR_RootConstrainSelectedInstOperands,
     /*  708151 */     // GIR_Coverage, 30528,
     /*  708151 */     GIR_EraseRootFromParent_Done,
     /*  708152 */   // Label 11188: @708152
     /*  708152 */   GIM_Try, /*On fail goto*//*Label 11189*/ GIMT_Encode4(708202), // Rule ID 30529 //
     /*  708157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode1),
     /*  708160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708165 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708167 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708171 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708178 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708186 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708196 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708200 */     GIR_RootConstrainSelectedInstOperands,
     /*  708201 */     // GIR_Coverage, 30529,
     /*  708201 */     GIR_EraseRootFromParent_Done,
     /*  708202 */   // Label 11189: @708202
     /*  708202 */   GIM_Try, /*On fail goto*//*Label 11190*/ GIMT_Encode4(708252), // Rule ID 30530 //
     /*  708207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode2),
     /*  708210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708215 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708228 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708236 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708250 */     GIR_RootConstrainSelectedInstOperands,
     /*  708251 */     // GIR_Coverage, 30530,
     /*  708251 */     GIR_EraseRootFromParent_Done,
     /*  708252 */   // Label 11190: @708252
     /*  708252 */   GIM_Try, /*On fail goto*//*Label 11191*/ GIMT_Encode4(708302), // Rule ID 30531 //
     /*  708257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode3),
     /*  708260 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708265 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708278 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708286 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708300 */     GIR_RootConstrainSelectedInstOperands,
     /*  708301 */     // GIR_Coverage, 30531,
     /*  708301 */     GIR_EraseRootFromParent_Done,
     /*  708302 */   // Label 11191: @708302
     /*  708302 */   GIM_Try, /*On fail goto*//*Label 11192*/ GIMT_Encode4(708352), // Rule ID 30532 //
     /*  708307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init_HwMode4),
     /*  708310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708315 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708328 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708336 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708346 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708350 */     GIR_RootConstrainSelectedInstOperands,
     /*  708351 */     // GIR_Coverage, 30532,
     /*  708351 */     GIR_EraseRootFromParent_Done,
     /*  708352 */   // Label 11192: @708352
     /*  708352 */   GIM_Try, /*On fail goto*//*Label 11193*/ GIMT_Encode4(708402), // Rule ID 30534 //
     /*  708357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode0),
     /*  708360 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708365 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708371 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708378 */     // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f32>>  =>  (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9),
     /*  708381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708386 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708400 */     GIR_RootConstrainSelectedInstOperands,
     /*  708401 */     // GIR_Coverage, 30534,
     /*  708401 */     GIR_EraseRootFromParent_Done,
     /*  708402 */   // Label 11193: @708402
     /*  708402 */   GIM_Try, /*On fail goto*//*Label 11194*/ GIMT_Encode4(708452), // Rule ID 30535 //
     /*  708407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode1),
     /*  708410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708415 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708428 */     // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f32>>  =>  (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9),
     /*  708431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708436 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708450 */     GIR_RootConstrainSelectedInstOperands,
     /*  708451 */     // GIR_Coverage, 30535,
     /*  708451 */     GIR_EraseRootFromParent_Done,
     /*  708452 */   // Label 11194: @708452
     /*  708452 */   GIM_Try, /*On fail goto*//*Label 11195*/ GIMT_Encode4(708502), // Rule ID 30536 //
     /*  708457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode2),
     /*  708460 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708465 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708478 */     // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f32>>  =>  (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9),
     /*  708481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708486 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708500 */     GIR_RootConstrainSelectedInstOperands,
     /*  708501 */     // GIR_Coverage, 30536,
     /*  708501 */     GIR_EraseRootFromParent_Done,
     /*  708502 */   // Label 11195: @708502
     /*  708502 */   GIM_Try, /*On fail goto*//*Label 11196*/ GIMT_Encode4(708552), // Rule ID 30537 //
     /*  708507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode3),
     /*  708510 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708515 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708528 */     // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f32>>  =>  (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9),
     /*  708531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708536 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708550 */     GIR_RootConstrainSelectedInstOperands,
     /*  708551 */     // GIR_Coverage, 30537,
     /*  708551 */     GIR_EraseRootFromParent_Done,
     /*  708552 */   // Label 11196: @708552
     /*  708552 */   GIM_Try, /*On fail goto*//*Label 11197*/ GIMT_Encode4(708602), // Rule ID 30538 //
     /*  708557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init_HwMode4),
     /*  708560 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708565 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708578 */     // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f32>>  =>  (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9),
     /*  708581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708586 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708600 */     GIR_RootConstrainSelectedInstOperands,
     /*  708601 */     // GIR_Coverage, 30538,
     /*  708601 */     GIR_EraseRootFromParent_Done,
     /*  708602 */   // Label 11197: @708602
     /*  708602 */   GIM_Try, /*On fail goto*//*Label 11198*/ GIMT_Encode4(708652), // Rule ID 30540 //
     /*  708607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode0),
     /*  708610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  708615 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708628 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  708628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708636 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708650 */     GIR_RootConstrainSelectedInstOperands,
     /*  708651 */     // GIR_Coverage, 30540,
     /*  708651 */     GIR_EraseRootFromParent_Done,
     /*  708652 */   // Label 11198: @708652
     /*  708652 */   GIM_Try, /*On fail goto*//*Label 11199*/ GIMT_Encode4(708702), // Rule ID 30541 //
     /*  708657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode1),
     /*  708660 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  708665 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708678 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  708678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708686 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708700 */     GIR_RootConstrainSelectedInstOperands,
     /*  708701 */     // GIR_Coverage, 30541,
     /*  708701 */     GIR_EraseRootFromParent_Done,
     /*  708702 */   // Label 11199: @708702
     /*  708702 */   GIM_Try, /*On fail goto*//*Label 11200*/ GIMT_Encode4(708752), // Rule ID 30542 //
     /*  708707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode2),
     /*  708710 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  708715 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708728 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  708728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708736 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708750 */     GIR_RootConstrainSelectedInstOperands,
     /*  708751 */     // GIR_Coverage, 30542,
     /*  708751 */     GIR_EraseRootFromParent_Done,
     /*  708752 */   // Label 11200: @708752
     /*  708752 */   GIM_Try, /*On fail goto*//*Label 11201*/ GIMT_Encode4(708802), // Rule ID 30543 //
     /*  708757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode3),
     /*  708760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  708765 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708778 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  708778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708786 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708800 */     GIR_RootConstrainSelectedInstOperands,
     /*  708801 */     // GIR_Coverage, 30543,
     /*  708801 */     GIR_EraseRootFromParent_Done,
     /*  708802 */   // Label 11201: @708802
     /*  708802 */   GIM_Try, /*On fail goto*//*Label 11202*/ GIMT_Encode4(708852), // Rule ID 30544 //
     /*  708807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32_HwMode4),
     /*  708810 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  708815 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  708817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708828 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_f32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  708828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
     /*  708831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708836 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  708846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708850 */     GIR_RootConstrainSelectedInstOperands,
     /*  708851 */     // GIR_Coverage, 30544,
     /*  708851 */     GIR_EraseRootFromParent_Done,
     /*  708852 */   // Label 11202: @708852
     /*  708852 */   GIM_Try, /*On fail goto*//*Label 11203*/ GIMT_Encode4(708906), // Rule ID 30527 //
     /*  708857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init),
     /*  708860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  708869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708880 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_f32>>  =>  (DS_ADD_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32),
     /*  708883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  708885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708890 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708897 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708904 */     GIR_RootConstrainSelectedInstOperands,
     /*  708905 */     // GIR_Coverage, 30527,
     /*  708905 */     GIR_EraseRootFromParent_Done,
     /*  708906 */   // Label 11203: @708906
     /*  708906 */   GIM_Try, /*On fail goto*//*Label 11204*/ GIMT_Encode4(708960), // Rule ID 30533 //
     /*  708911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init),
     /*  708914 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  708919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  708923 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708927 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708934 */     // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_f32>>  =>  (DS_ADD_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  708934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32_gfx9),
     /*  708937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  708939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708944 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  708946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  708951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  708954 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  708958 */     GIR_RootConstrainSelectedInstOperands,
     /*  708959 */     // GIR_Coverage, 30533,
     /*  708959 */     GIR_EraseRootFromParent_Done,
     /*  708960 */   // Label 11204: @708960
     /*  708960 */   GIM_Try, /*On fail goto*//*Label 11205*/ GIMT_Encode4(709014), // Rule ID 30539 //
     /*  708965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32),
     /*  708968 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  708973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  708977 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  708981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  708988 */     // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_f32>>  =>  (DS_ADD_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  708988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32),
     /*  708991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  708993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  708998 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  709000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  709008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709012 */     GIR_RootConstrainSelectedInstOperands,
     /*  709013 */     // GIR_Coverage, 30539,
     /*  709013 */     GIR_EraseRootFromParent_Done,
     /*  709014 */   // Label 11205: @709014
     /*  709014 */   GIM_Try, /*On fail goto*//*Label 11206*/ GIMT_Encode4(709073), // Rule ID 13696 //
     /*  709019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode0),
     /*  709022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709029 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  709042 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
     /*  709045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709050 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709071 */     GIR_RootConstrainSelectedInstOperands,
     /*  709072 */     // GIR_Coverage, 13696,
     /*  709072 */     GIR_EraseRootFromParent_Done,
     /*  709073 */   // Label 11206: @709073
     /*  709073 */   GIM_Try, /*On fail goto*//*Label 11207*/ GIMT_Encode4(709132), // Rule ID 13697 //
     /*  709078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode1),
     /*  709081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709088 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709090 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709094 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  709101 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
     /*  709104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709109 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709130 */     GIR_RootConstrainSelectedInstOperands,
     /*  709131 */     // GIR_Coverage, 13697,
     /*  709131 */     GIR_EraseRootFromParent_Done,
     /*  709132 */   // Label 11207: @709132
     /*  709132 */   GIM_Try, /*On fail goto*//*Label 11208*/ GIMT_Encode4(709191), // Rule ID 13698 //
     /*  709137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode2),
     /*  709140 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709147 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709149 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  709160 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
     /*  709163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709168 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709185 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709189 */     GIR_RootConstrainSelectedInstOperands,
     /*  709190 */     // GIR_Coverage, 13698,
     /*  709190 */     GIR_EraseRootFromParent_Done,
     /*  709191 */   // Label 11208: @709191
     /*  709191 */   GIM_Try, /*On fail goto*//*Label 11209*/ GIMT_Encode4(709250), // Rule ID 13699 //
     /*  709196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode3),
     /*  709199 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709206 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709208 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  709219 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
     /*  709222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709227 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709248 */     GIR_RootConstrainSelectedInstOperands,
     /*  709249 */     // GIR_Coverage, 13699,
     /*  709249 */     GIR_EraseRootFromParent_Done,
     /*  709250 */   // Label 11209: @709250
     /*  709250 */   GIM_Try, /*On fail goto*//*Label 11210*/ GIMT_Encode4(709309), // Rule ID 13700 //
     /*  709255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode4),
     /*  709258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709265 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  709278 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
     /*  709281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709286 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709307 */     GIR_RootConstrainSelectedInstOperands,
     /*  709308 */     // GIR_Coverage, 13700,
     /*  709308 */     GIR_EraseRootFromParent_Done,
     /*  709309 */   // Label 11210: @709309
     /*  709309 */   GIM_Try, /*On fail goto*//*Label 11211*/ GIMT_Encode4(709372), // Rule ID 13716 //
     /*  709314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
     /*  709317 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  709328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  709339 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN),
     /*  709342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  709344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709349 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709370 */     GIR_RootConstrainSelectedInstOperands,
     /*  709371 */     // GIR_Coverage, 13716,
     /*  709371 */     GIR_EraseRootFromParent_Done,
     /*  709372 */   // Label 11211: @709372
     /*  709372 */   GIM_Try, /*On fail goto*//*Label 11212*/ GIMT_Encode4(709424), // Rule ID 13691 //
     /*  709377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode0),
     /*  709380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709400 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
     /*  709403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709408 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  709418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709422 */     GIR_RootConstrainSelectedInstOperands,
     /*  709423 */     // GIR_Coverage, 13691,
     /*  709423 */     GIR_EraseRootFromParent_Done,
     /*  709424 */   // Label 11212: @709424
     /*  709424 */   GIM_Try, /*On fail goto*//*Label 11213*/ GIMT_Encode4(709476), // Rule ID 13692 //
     /*  709429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode1),
     /*  709432 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709439 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709452 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
     /*  709455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709460 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  709470 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709474 */     GIR_RootConstrainSelectedInstOperands,
     /*  709475 */     // GIR_Coverage, 13692,
     /*  709475 */     GIR_EraseRootFromParent_Done,
     /*  709476 */   // Label 11213: @709476
     /*  709476 */   GIM_Try, /*On fail goto*//*Label 11214*/ GIMT_Encode4(709528), // Rule ID 13693 //
     /*  709481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode2),
     /*  709484 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709491 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709493 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709504 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
     /*  709507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709512 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  709522 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709526 */     GIR_RootConstrainSelectedInstOperands,
     /*  709527 */     // GIR_Coverage, 13693,
     /*  709527 */     GIR_EraseRootFromParent_Done,
     /*  709528 */   // Label 11214: @709528
     /*  709528 */   GIM_Try, /*On fail goto*//*Label 11215*/ GIMT_Encode4(709580), // Rule ID 13694 //
     /*  709533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode3),
     /*  709536 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709543 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709545 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709556 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
     /*  709559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709564 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  709574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709578 */     GIR_RootConstrainSelectedInstOperands,
     /*  709579 */     // GIR_Coverage, 13694,
     /*  709579 */     GIR_EraseRootFromParent_Done,
     /*  709580 */   // Label 11215: @709580
     /*  709580 */   GIM_Try, /*On fail goto*//*Label 11216*/ GIMT_Encode4(709632), // Rule ID 13695 //
     /*  709585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HwMode4),
     /*  709588 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709595 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709608 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
     /*  709611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709616 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  709626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709630 */     GIR_RootConstrainSelectedInstOperands,
     /*  709631 */     // GIR_Coverage, 13695,
     /*  709631 */     GIR_EraseRootFromParent_Done,
     /*  709632 */   // Label 11216: @709632
     /*  709632 */   GIM_Try, /*On fail goto*//*Label 11217*/ GIMT_Encode4(709688), // Rule ID 13711 //
     /*  709637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HwMode0),
     /*  709640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  709651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709662 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
     /*  709665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  709667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709672 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  709682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709686 */     GIR_RootConstrainSelectedInstOperands,
     /*  709687 */     // GIR_Coverage, 13711,
     /*  709687 */     GIR_EraseRootFromParent_Done,
     /*  709688 */   // Label 11217: @709688
     /*  709688 */   GIM_Try, /*On fail goto*//*Label 11218*/ GIMT_Encode4(709744), // Rule ID 13712 //
     /*  709693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HwMode1),
     /*  709696 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  709707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709718 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
     /*  709721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  709723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709728 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  709738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709742 */     GIR_RootConstrainSelectedInstOperands,
     /*  709743 */     // GIR_Coverage, 13712,
     /*  709743 */     GIR_EraseRootFromParent_Done,
     /*  709744 */   // Label 11218: @709744
     /*  709744 */   GIM_Try, /*On fail goto*//*Label 11219*/ GIMT_Encode4(709800), // Rule ID 13713 //
     /*  709749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HwMode2),
     /*  709752 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  709763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709774 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
     /*  709777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  709779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709784 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  709794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709798 */     GIR_RootConstrainSelectedInstOperands,
     /*  709799 */     // GIR_Coverage, 13713,
     /*  709799 */     GIR_EraseRootFromParent_Done,
     /*  709800 */   // Label 11219: @709800
     /*  709800 */   GIM_Try, /*On fail goto*//*Label 11220*/ GIMT_Encode4(709856), // Rule ID 13714 //
     /*  709805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HwMode3),
     /*  709808 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  709819 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709823 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709830 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
     /*  709833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  709835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709840 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  709850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709854 */     GIR_RootConstrainSelectedInstOperands,
     /*  709855 */     // GIR_Coverage, 13714,
     /*  709855 */     GIR_EraseRootFromParent_Done,
     /*  709856 */   // Label 11220: @709856
     /*  709856 */   GIM_Try, /*On fail goto*//*Label 11221*/ GIMT_Encode4(709912), // Rule ID 13715 //
     /*  709861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HwMode4),
     /*  709864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  709875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  709886 */     // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  709886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
     /*  709889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  709891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  709896 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  709903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  709906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709910 */     GIR_RootConstrainSelectedInstOperands,
     /*  709911 */     // GIR_Coverage, 13715,
     /*  709911 */     GIR_EraseRootFromParent_Done,
     /*  709912 */   // Label 11221: @709912
     /*  709912 */   GIM_Try, /*On fail goto*//*Label 11222*/ GIMT_Encode4(709972), // Rule ID 13824 //
     /*  709917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode0),
     /*  709920 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709928 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  709941 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  709941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR),
     /*  709944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  709949 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  709951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  709956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  709961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  709966 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  709970 */     GIR_RootConstrainSelectedInstOperands,
     /*  709971 */     // GIR_Coverage, 13824,
     /*  709971 */     GIR_EraseRootFromParent_Done,
     /*  709972 */   // Label 11222: @709972
     /*  709972 */   GIM_Try, /*On fail goto*//*Label 11223*/ GIMT_Encode4(710032), // Rule ID 13825 //
     /*  709977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode1),
     /*  709980 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  709988 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  709990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  709994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  710001 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  710001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR),
     /*  710004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  710009 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  710016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  710021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  710026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710030 */     GIR_RootConstrainSelectedInstOperands,
     /*  710031 */     // GIR_Coverage, 13825,
     /*  710031 */     GIR_EraseRootFromParent_Done,
     /*  710032 */   // Label 11223: @710032
     /*  710032 */   GIM_Try, /*On fail goto*//*Label 11224*/ GIMT_Encode4(710092), // Rule ID 13826 //
     /*  710037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode2),
     /*  710040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710048 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710050 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  710061 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  710061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR),
     /*  710064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  710069 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  710076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  710081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  710086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710090 */     GIR_RootConstrainSelectedInstOperands,
     /*  710091 */     // GIR_Coverage, 13826,
     /*  710091 */     GIR_EraseRootFromParent_Done,
     /*  710092 */   // Label 11224: @710092
     /*  710092 */   GIM_Try, /*On fail goto*//*Label 11225*/ GIMT_Encode4(710152), // Rule ID 13827 //
     /*  710097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode3),
     /*  710100 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710108 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  710121 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  710121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR),
     /*  710124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  710129 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  710136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  710141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  710146 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710150 */     GIR_RootConstrainSelectedInstOperands,
     /*  710151 */     // GIR_Coverage, 13827,
     /*  710151 */     GIR_EraseRootFromParent_Done,
     /*  710152 */   // Label 11225: @710152
     /*  710152 */   GIM_Try, /*On fail goto*//*Label 11226*/ GIMT_Encode4(710212), // Rule ID 13828 //
     /*  710157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode_HwMode4),
     /*  710160 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710168 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  710181 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  710181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR),
     /*  710184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  710189 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  710196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  710201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  710206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710210 */     GIR_RootConstrainSelectedInstOperands,
     /*  710211 */     // GIR_Coverage, 13828,
     /*  710211 */     GIR_EraseRootFromParent_Done,
     /*  710212 */   // Label 11226: @710212
     /*  710212 */   GIM_Try, /*On fail goto*//*Label 11227*/ GIMT_Encode4(710276), // Rule ID 13818 //
     /*  710217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HasFlatGVSMode),
     /*  710220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  710232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  710243 */     // (atomic_load_fadd:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>>  =>  (FLAT_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  710243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_SADDR_RTN),
     /*  710246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  710248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  710253 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  710260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  710265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  710270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710274 */     GIR_RootConstrainSelectedInstOperands,
     /*  710275 */     // GIR_Coverage, 13818,
     /*  710275 */     GIR_EraseRootFromParent_Done,
     /*  710276 */   // Label 11227: @710276
     /*  710276 */   GIM_Try, /*On fail goto*//*Label 11228*/ GIMT_Encode4(710329), // Rule ID 13819 //
     /*  710281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode0),
     /*  710284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710292 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710294 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710305 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
     /*  710308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710313 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710327 */     GIR_RootConstrainSelectedInstOperands,
     /*  710328 */     // GIR_Coverage, 13819,
     /*  710328 */     GIR_EraseRootFromParent_Done,
     /*  710329 */   // Label 11228: @710329
     /*  710329 */   GIM_Try, /*On fail goto*//*Label 11229*/ GIMT_Encode4(710382), // Rule ID 13820 //
     /*  710334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode1),
     /*  710337 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710345 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710358 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
     /*  710361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710366 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710380 */     GIR_RootConstrainSelectedInstOperands,
     /*  710381 */     // GIR_Coverage, 13820,
     /*  710381 */     GIR_EraseRootFromParent_Done,
     /*  710382 */   // Label 11229: @710382
     /*  710382 */   GIM_Try, /*On fail goto*//*Label 11230*/ GIMT_Encode4(710435), // Rule ID 13821 //
     /*  710387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode2),
     /*  710390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710398 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710411 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
     /*  710414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710419 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710429 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710433 */     GIR_RootConstrainSelectedInstOperands,
     /*  710434 */     // GIR_Coverage, 13821,
     /*  710434 */     GIR_EraseRootFromParent_Done,
     /*  710435 */   // Label 11230: @710435
     /*  710435 */   GIM_Try, /*On fail goto*//*Label 11231*/ GIMT_Encode4(710488), // Rule ID 13822 //
     /*  710440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode3),
     /*  710443 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710451 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710464 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
     /*  710467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710472 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710482 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710486 */     GIR_RootConstrainSelectedInstOperands,
     /*  710487 */     // GIR_Coverage, 13822,
     /*  710487 */     GIR_EraseRootFromParent_Done,
     /*  710488 */   // Label 11231: @710488
     /*  710488 */   GIM_Try, /*On fail goto*//*Label 11232*/ GIMT_Encode4(710541), // Rule ID 13823 //
     /*  710493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode4),
     /*  710496 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710504 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710517 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
     /*  710520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710525 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710539 */     GIR_RootConstrainSelectedInstOperands,
     /*  710540 */     // GIR_Coverage, 13823,
     /*  710540 */     GIR_EraseRootFromParent_Done,
     /*  710541 */   // Label 11232: @710541
     /*  710541 */   GIM_Try, /*On fail goto*//*Label 11233*/ GIMT_Encode4(710598), // Rule ID 13813 //
     /*  710546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode0),
     /*  710549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  710561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710572 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
     /*  710575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  710577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710582 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  710592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710596 */     GIR_RootConstrainSelectedInstOperands,
     /*  710597 */     // GIR_Coverage, 13813,
     /*  710597 */     GIR_EraseRootFromParent_Done,
     /*  710598 */   // Label 11233: @710598
     /*  710598 */   GIM_Try, /*On fail goto*//*Label 11234*/ GIMT_Encode4(710655), // Rule ID 13814 //
     /*  710603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode1),
     /*  710606 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  710618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710629 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
     /*  710632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  710634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710639 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  710649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710653 */     GIR_RootConstrainSelectedInstOperands,
     /*  710654 */     // GIR_Coverage, 13814,
     /*  710654 */     GIR_EraseRootFromParent_Done,
     /*  710655 */   // Label 11234: @710655
     /*  710655 */   GIM_Try, /*On fail goto*//*Label 11235*/ GIMT_Encode4(710712), // Rule ID 13815 //
     /*  710660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode2),
     /*  710663 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  710675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710686 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
     /*  710689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  710691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710696 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  710706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710710 */     GIR_RootConstrainSelectedInstOperands,
     /*  710711 */     // GIR_Coverage, 13815,
     /*  710711 */     GIR_EraseRootFromParent_Done,
     /*  710712 */   // Label 11235: @710712
     /*  710712 */   GIM_Try, /*On fail goto*//*Label 11236*/ GIMT_Encode4(710769), // Rule ID 13816 //
     /*  710717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode3),
     /*  710720 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  710732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710743 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
     /*  710746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  710748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710753 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  710763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710767 */     GIR_RootConstrainSelectedInstOperands,
     /*  710768 */     // GIR_Coverage, 13816,
     /*  710768 */     GIR_EraseRootFromParent_Done,
     /*  710769 */   // Label 11236: @710769
     /*  710769 */   GIM_Try, /*On fail goto*//*Label 11237*/ GIMT_Encode4(710826), // Rule ID 13817 //
     /*  710774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst_HwMode4),
     /*  710777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  710785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  710789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  710800 */     // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  710800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
     /*  710803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  710805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  710810 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  710812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  710820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710824 */     GIR_RootConstrainSelectedInstOperands,
     /*  710825 */     // GIR_Coverage, 13817,
     /*  710825 */     GIR_EraseRootFromParent_Done,
     /*  710826 */   // Label 11237: @710826
     /*  710826 */   GIM_Reject,
     /*  710827 */ // Label 11187: @710827
     /*  710827 */ GIM_Reject,
     /*  710828 */ // Label 11184: @710828
     /*  710828 */ GIM_Try, /*On fail goto*//*Label 11238*/ GIMT_Encode4(713677),
     /*  710833 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  710836 */   GIM_Try, /*On fail goto*//*Label 11239*/ GIMT_Encode4(710886), // Rule ID 31005 //
     /*  710841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode0),
     /*  710844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  710849 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  710862 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f64>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  710862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
     /*  710865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  710870 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  710872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710884 */     GIR_RootConstrainSelectedInstOperands,
     /*  710885 */     // GIR_Coverage, 31005,
     /*  710885 */     GIR_EraseRootFromParent_Done,
     /*  710886 */   // Label 11239: @710886
     /*  710886 */   GIM_Try, /*On fail goto*//*Label 11240*/ GIMT_Encode4(710936), // Rule ID 31006 //
     /*  710891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode1),
     /*  710894 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  710899 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  710912 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f64>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  710912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
     /*  710915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  710920 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  710922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710934 */     GIR_RootConstrainSelectedInstOperands,
     /*  710935 */     // GIR_Coverage, 31006,
     /*  710935 */     GIR_EraseRootFromParent_Done,
     /*  710936 */   // Label 11240: @710936
     /*  710936 */   GIM_Try, /*On fail goto*//*Label 11241*/ GIMT_Encode4(710986), // Rule ID 31007 //
     /*  710941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode2),
     /*  710944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  710949 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  710951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  710955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  710962 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f64>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  710962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
     /*  710965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  710970 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  710972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  710977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  710980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  710984 */     GIR_RootConstrainSelectedInstOperands,
     /*  710985 */     // GIR_Coverage, 31007,
     /*  710985 */     GIR_EraseRootFromParent_Done,
     /*  710986 */   // Label 11241: @710986
     /*  710986 */   GIM_Try, /*On fail goto*//*Label 11242*/ GIMT_Encode4(711036), // Rule ID 31008 //
     /*  710991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode3),
     /*  710994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  710999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711012 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f64>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
     /*  711015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711020 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711034 */     GIR_RootConstrainSelectedInstOperands,
     /*  711035 */     // GIR_Coverage, 31008,
     /*  711035 */     GIR_EraseRootFromParent_Done,
     /*  711036 */   // Label 11242: @711036
     /*  711036 */   GIM_Try, /*On fail goto*//*Label 11243*/ GIMT_Encode4(711086), // Rule ID 31009 //
     /*  711041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode4),
     /*  711044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  711049 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711062 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f64>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
     /*  711065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711070 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711084 */     GIR_RootConstrainSelectedInstOperands,
     /*  711085 */     // GIR_Coverage, 31009,
     /*  711085 */     GIR_EraseRootFromParent_Done,
     /*  711086 */   // Label 11243: @711086
     /*  711086 */   GIM_Try, /*On fail goto*//*Label 11244*/ GIMT_Encode4(711140), // Rule ID 31000 //
     /*  711091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode0),
     /*  711094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  711099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711114 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_f64>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
     /*  711117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711124 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711138 */     GIR_RootConstrainSelectedInstOperands,
     /*  711139 */     // GIR_Coverage, 31000,
     /*  711139 */     GIR_EraseRootFromParent_Done,
     /*  711140 */   // Label 11244: @711140
     /*  711140 */   GIM_Try, /*On fail goto*//*Label 11245*/ GIMT_Encode4(711194), // Rule ID 31001 //
     /*  711145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode1),
     /*  711148 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  711153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711168 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_f64>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
     /*  711171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711178 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711192 */     GIR_RootConstrainSelectedInstOperands,
     /*  711193 */     // GIR_Coverage, 31001,
     /*  711193 */     GIR_EraseRootFromParent_Done,
     /*  711194 */   // Label 11245: @711194
     /*  711194 */   GIM_Try, /*On fail goto*//*Label 11246*/ GIMT_Encode4(711248), // Rule ID 31002 //
     /*  711199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode2),
     /*  711202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  711207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711211 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711222 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_f64>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
     /*  711225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711232 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711246 */     GIR_RootConstrainSelectedInstOperands,
     /*  711247 */     // GIR_Coverage, 31002,
     /*  711247 */     GIR_EraseRootFromParent_Done,
     /*  711248 */   // Label 11246: @711248
     /*  711248 */   GIM_Try, /*On fail goto*//*Label 11247*/ GIMT_Encode4(711302), // Rule ID 31003 //
     /*  711253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode3),
     /*  711256 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  711261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711265 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711276 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_f64>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
     /*  711279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711286 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711300 */     GIR_RootConstrainSelectedInstOperands,
     /*  711301 */     // GIR_Coverage, 31003,
     /*  711301 */     GIR_EraseRootFromParent_Done,
     /*  711302 */   // Label 11247: @711302
     /*  711302 */   GIM_Try, /*On fail goto*//*Label 11248*/ GIMT_Encode4(711356), // Rule ID 31004 //
     /*  711307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64_HwMode4),
     /*  711310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  711315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  711330 */     // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_f64>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  711330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
     /*  711333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  711340 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  711342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  711347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  711350 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711354 */     GIR_RootConstrainSelectedInstOperands,
     /*  711355 */     // GIR_Coverage, 31004,
     /*  711355 */     GIR_EraseRootFromParent_Done,
     /*  711356 */   // Label 11248: @711356
     /*  711356 */   GIM_Try, /*On fail goto*//*Label 11249*/ GIMT_Encode4(711415), // Rule ID 13778 //
     /*  711361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0),
     /*  711364 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711371 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711373 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  711384 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
     /*  711387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711392 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711413 */     GIR_RootConstrainSelectedInstOperands,
     /*  711414 */     // GIR_Coverage, 13778,
     /*  711414 */     GIR_EraseRootFromParent_Done,
     /*  711415 */   // Label 11249: @711415
     /*  711415 */   GIM_Try, /*On fail goto*//*Label 11250*/ GIMT_Encode4(711474), // Rule ID 13779 //
     /*  711420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1),
     /*  711423 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711430 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711432 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  711443 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
     /*  711446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711451 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711468 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711472 */     GIR_RootConstrainSelectedInstOperands,
     /*  711473 */     // GIR_Coverage, 13779,
     /*  711473 */     GIR_EraseRootFromParent_Done,
     /*  711474 */   // Label 11250: @711474
     /*  711474 */   GIM_Try, /*On fail goto*//*Label 11251*/ GIMT_Encode4(711533), // Rule ID 13780 //
     /*  711479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2),
     /*  711482 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711489 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  711502 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
     /*  711505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711510 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711531 */     GIR_RootConstrainSelectedInstOperands,
     /*  711532 */     // GIR_Coverage, 13780,
     /*  711532 */     GIR_EraseRootFromParent_Done,
     /*  711533 */   // Label 11251: @711533
     /*  711533 */   GIM_Try, /*On fail goto*//*Label 11252*/ GIMT_Encode4(711592), // Rule ID 13781 //
     /*  711538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3),
     /*  711541 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711548 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  711561 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
     /*  711564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711569 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711586 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711590 */     GIR_RootConstrainSelectedInstOperands,
     /*  711591 */     // GIR_Coverage, 13781,
     /*  711591 */     GIR_EraseRootFromParent_Done,
     /*  711592 */   // Label 11252: @711592
     /*  711592 */   GIM_Try, /*On fail goto*//*Label 11253*/ GIMT_Encode4(711651), // Rule ID 13782 //
     /*  711597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4),
     /*  711600 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711607 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  711620 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
     /*  711623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711628 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711645 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711649 */     GIR_RootConstrainSelectedInstOperands,
     /*  711650 */     // GIR_Coverage, 13782,
     /*  711650 */     GIR_EraseRootFromParent_Done,
     /*  711651 */   // Label 11253: @711651
     /*  711651 */   GIM_Try, /*On fail goto*//*Label 11254*/ GIMT_Encode4(711714), // Rule ID 13788 //
     /*  711656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0),
     /*  711659 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711674 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  711681 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
     /*  711684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711691 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711708 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711712 */     GIR_RootConstrainSelectedInstOperands,
     /*  711713 */     // GIR_Coverage, 13788,
     /*  711713 */     GIR_EraseRootFromParent_Done,
     /*  711714 */   // Label 11254: @711714
     /*  711714 */   GIM_Try, /*On fail goto*//*Label 11255*/ GIMT_Encode4(711777), // Rule ID 13789 //
     /*  711719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1),
     /*  711722 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  711744 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
     /*  711747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711754 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711775 */     GIR_RootConstrainSelectedInstOperands,
     /*  711776 */     // GIR_Coverage, 13789,
     /*  711776 */     GIR_EraseRootFromParent_Done,
     /*  711777 */   // Label 11255: @711777
     /*  711777 */   GIM_Try, /*On fail goto*//*Label 11256*/ GIMT_Encode4(711840), // Rule ID 13790 //
     /*  711782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2),
     /*  711785 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  711807 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
     /*  711810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711817 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711838 */     GIR_RootConstrainSelectedInstOperands,
     /*  711839 */     // GIR_Coverage, 13790,
     /*  711839 */     GIR_EraseRootFromParent_Done,
     /*  711840 */   // Label 11256: @711840
     /*  711840 */   GIM_Try, /*On fail goto*//*Label 11257*/ GIMT_Encode4(711903), // Rule ID 13791 //
     /*  711845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3),
     /*  711848 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  711870 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
     /*  711873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711880 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711901 */     GIR_RootConstrainSelectedInstOperands,
     /*  711902 */     // GIR_Coverage, 13791,
     /*  711902 */     GIR_EraseRootFromParent_Done,
     /*  711903 */   // Label 11257: @711903
     /*  711903 */   GIM_Try, /*On fail goto*//*Label 11258*/ GIMT_Encode4(711966), // Rule ID 13792 //
     /*  711908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4),
     /*  711911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  711922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  711933 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  711933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
     /*  711936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  711938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  711943 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  711945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  711950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  711955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  711960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  711964 */     GIR_RootConstrainSelectedInstOperands,
     /*  711965 */     // GIR_Coverage, 13792,
     /*  711965 */     GIR_EraseRootFromParent_Done,
     /*  711966 */   // Label 11258: @711966
     /*  711966 */   GIM_Try, /*On fail goto*//*Label 11259*/ GIMT_Encode4(712018), // Rule ID 13773 //
     /*  711971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0),
     /*  711974 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  711981 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  711983 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  711987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  711994 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  711994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
     /*  711997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712002 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  712012 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712016 */     GIR_RootConstrainSelectedInstOperands,
     /*  712017 */     // GIR_Coverage, 13773,
     /*  712017 */     GIR_EraseRootFromParent_Done,
     /*  712018 */   // Label 11259: @712018
     /*  712018 */   GIM_Try, /*On fail goto*//*Label 11260*/ GIMT_Encode4(712070), // Rule ID 13774 //
     /*  712023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1),
     /*  712026 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712033 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712039 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712046 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
     /*  712049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712054 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  712064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712068 */     GIR_RootConstrainSelectedInstOperands,
     /*  712069 */     // GIR_Coverage, 13774,
     /*  712069 */     GIR_EraseRootFromParent_Done,
     /*  712070 */   // Label 11260: @712070
     /*  712070 */   GIM_Try, /*On fail goto*//*Label 11261*/ GIMT_Encode4(712122), // Rule ID 13775 //
     /*  712075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2),
     /*  712078 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712085 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712087 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712098 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
     /*  712101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712106 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  712116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712120 */     GIR_RootConstrainSelectedInstOperands,
     /*  712121 */     // GIR_Coverage, 13775,
     /*  712121 */     GIR_EraseRootFromParent_Done,
     /*  712122 */   // Label 11261: @712122
     /*  712122 */   GIM_Try, /*On fail goto*//*Label 11262*/ GIMT_Encode4(712174), // Rule ID 13776 //
     /*  712127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3),
     /*  712130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712137 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712150 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
     /*  712153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712158 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  712168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712172 */     GIR_RootConstrainSelectedInstOperands,
     /*  712173 */     // GIR_Coverage, 13776,
     /*  712173 */     GIR_EraseRootFromParent_Done,
     /*  712174 */   // Label 11262: @712174
     /*  712174 */   GIM_Try, /*On fail goto*//*Label 11263*/ GIMT_Encode4(712226), // Rule ID 13777 //
     /*  712179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4),
     /*  712182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712189 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712202 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
     /*  712205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712210 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  712220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712224 */     GIR_RootConstrainSelectedInstOperands,
     /*  712225 */     // GIR_Coverage, 13777,
     /*  712225 */     GIR_EraseRootFromParent_Done,
     /*  712226 */   // Label 11263: @712226
     /*  712226 */   GIM_Try, /*On fail goto*//*Label 11264*/ GIMT_Encode4(712282), // Rule ID 13783 //
     /*  712231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0),
     /*  712234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712245 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712249 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712256 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
     /*  712259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712266 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  712276 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712280 */     GIR_RootConstrainSelectedInstOperands,
     /*  712281 */     // GIR_Coverage, 13783,
     /*  712281 */     GIR_EraseRootFromParent_Done,
     /*  712282 */   // Label 11264: @712282
     /*  712282 */   GIM_Try, /*On fail goto*//*Label 11265*/ GIMT_Encode4(712338), // Rule ID 13784 //
     /*  712287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1),
     /*  712290 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712301 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712312 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
     /*  712315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712322 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  712332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712336 */     GIR_RootConstrainSelectedInstOperands,
     /*  712337 */     // GIR_Coverage, 13784,
     /*  712337 */     GIR_EraseRootFromParent_Done,
     /*  712338 */   // Label 11265: @712338
     /*  712338 */   GIM_Try, /*On fail goto*//*Label 11266*/ GIMT_Encode4(712394), // Rule ID 13785 //
     /*  712343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2),
     /*  712346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712368 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
     /*  712371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712378 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  712388 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712392 */     GIR_RootConstrainSelectedInstOperands,
     /*  712393 */     // GIR_Coverage, 13785,
     /*  712393 */     GIR_EraseRootFromParent_Done,
     /*  712394 */   // Label 11266: @712394
     /*  712394 */   GIM_Try, /*On fail goto*//*Label 11267*/ GIMT_Encode4(712450), // Rule ID 13786 //
     /*  712399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3),
     /*  712402 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712413 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712417 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712424 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
     /*  712427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712434 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  712444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712448 */     GIR_RootConstrainSelectedInstOperands,
     /*  712449 */     // GIR_Coverage, 13786,
     /*  712449 */     GIR_EraseRootFromParent_Done,
     /*  712450 */   // Label 11267: @712450
     /*  712450 */   GIM_Try, /*On fail goto*//*Label 11268*/ GIMT_Encode4(712506), // Rule ID 13787 //
     /*  712455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4),
     /*  712458 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712469 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  712480 */     // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  712480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
     /*  712483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  712490 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  712497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  712500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712504 */     GIR_RootConstrainSelectedInstOperands,
     /*  712505 */     // GIR_Coverage, 13787,
     /*  712505 */     GIR_EraseRootFromParent_Done,
     /*  712506 */   // Label 11268: @712506
     /*  712506 */   GIM_Try, /*On fail goto*//*Label 11269*/ GIMT_Encode4(712566), // Rule ID 13808 //
     /*  712511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode0),
     /*  712514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712522 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  712535 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR),
     /*  712538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712543 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712560 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712564 */     GIR_RootConstrainSelectedInstOperands,
     /*  712565 */     // GIR_Coverage, 13808,
     /*  712565 */     GIR_EraseRootFromParent_Done,
     /*  712566 */   // Label 11269: @712566
     /*  712566 */   GIM_Try, /*On fail goto*//*Label 11270*/ GIMT_Encode4(712626), // Rule ID 13809 //
     /*  712571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode1),
     /*  712574 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712582 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  712595 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR),
     /*  712598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712603 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712624 */     GIR_RootConstrainSelectedInstOperands,
     /*  712625 */     // GIR_Coverage, 13809,
     /*  712625 */     GIR_EraseRootFromParent_Done,
     /*  712626 */   // Label 11270: @712626
     /*  712626 */   GIM_Try, /*On fail goto*//*Label 11271*/ GIMT_Encode4(712686), // Rule ID 13810 //
     /*  712631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode2),
     /*  712634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712642 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712644 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  712655 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR),
     /*  712658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712663 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712680 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712684 */     GIR_RootConstrainSelectedInstOperands,
     /*  712685 */     // GIR_Coverage, 13810,
     /*  712685 */     GIR_EraseRootFromParent_Done,
     /*  712686 */   // Label 11271: @712686
     /*  712686 */   GIM_Try, /*On fail goto*//*Label 11272*/ GIMT_Encode4(712746), // Rule ID 13811 //
     /*  712691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode3),
     /*  712694 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712702 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  712715 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR),
     /*  712718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712723 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712744 */     GIR_RootConstrainSelectedInstOperands,
     /*  712745 */     // GIR_Coverage, 13811,
     /*  712745 */     GIR_EraseRootFromParent_Done,
     /*  712746 */   // Label 11272: @712746
     /*  712746 */   GIM_Try, /*On fail goto*//*Label 11273*/ GIMT_Encode4(712806), // Rule ID 13812 //
     /*  712751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode4),
     /*  712754 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712762 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  712764 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712768 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  712775 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR),
     /*  712778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712783 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712804 */     GIR_RootConstrainSelectedInstOperands,
     /*  712805 */     // GIR_Coverage, 13812,
     /*  712805 */     GIR_EraseRootFromParent_Done,
     /*  712806 */   // Label 11273: @712806
     /*  712806 */   GIM_Try, /*On fail goto*//*Label 11274*/ GIMT_Encode4(712870), // Rule ID 13798 //
     /*  712811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode0),
     /*  712814 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  712837 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN),
     /*  712840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712847 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712868 */     GIR_RootConstrainSelectedInstOperands,
     /*  712869 */     // GIR_Coverage, 13798,
     /*  712869 */     GIR_EraseRootFromParent_Done,
     /*  712870 */   // Label 11274: @712870
     /*  712870 */   GIM_Try, /*On fail goto*//*Label 11275*/ GIMT_Encode4(712934), // Rule ID 13799 //
     /*  712875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode1),
     /*  712878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712890 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  712901 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN),
     /*  712904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712911 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712932 */     GIR_RootConstrainSelectedInstOperands,
     /*  712933 */     // GIR_Coverage, 13799,
     /*  712933 */     GIR_EraseRootFromParent_Done,
     /*  712934 */   // Label 11275: @712934
     /*  712934 */   GIM_Try, /*On fail goto*//*Label 11276*/ GIMT_Encode4(712998), // Rule ID 13800 //
     /*  712939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode2),
     /*  712942 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  712950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  712954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  712958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  712965 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  712965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN),
     /*  712968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  712970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  712975 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  712977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  712982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  712987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  712992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  712996 */     GIR_RootConstrainSelectedInstOperands,
     /*  712997 */     // GIR_Coverage, 13800,
     /*  712997 */     GIR_EraseRootFromParent_Done,
     /*  712998 */   // Label 11276: @712998
     /*  712998 */   GIM_Try, /*On fail goto*//*Label 11277*/ GIMT_Encode4(713062), // Rule ID 13801 //
     /*  713003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode3),
     /*  713006 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  713029 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  713029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN),
     /*  713032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  713039 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  713046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  713051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  713056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713060 */     GIR_RootConstrainSelectedInstOperands,
     /*  713061 */     // GIR_Coverage, 13801,
     /*  713061 */     GIR_EraseRootFromParent_Done,
     /*  713062 */   // Label 11277: @713062
     /*  713062 */   GIM_Try, /*On fail goto*//*Label 11278*/ GIMT_Encode4(713126), // Rule ID 13802 //
     /*  713067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasFlatGVSMode_HwMode4),
     /*  713070 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  713093 */     // (atomic_load_fadd:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  713093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_SADDR_RTN),
     /*  713096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  713103 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  713110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  713115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  713120 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713124 */     GIR_RootConstrainSelectedInstOperands,
     /*  713125 */     // GIR_Coverage, 13802,
     /*  713125 */     GIR_EraseRootFromParent_Done,
     /*  713126 */   // Label 11278: @713126
     /*  713126 */   GIM_Try, /*On fail goto*//*Label 11279*/ GIMT_Encode4(713179), // Rule ID 13803 //
     /*  713131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0),
     /*  713134 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713142 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713144 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713155 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
     /*  713158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713163 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713177 */     GIR_RootConstrainSelectedInstOperands,
     /*  713178 */     // GIR_Coverage, 13803,
     /*  713178 */     GIR_EraseRootFromParent_Done,
     /*  713179 */   // Label 11279: @713179
     /*  713179 */   GIM_Try, /*On fail goto*//*Label 11280*/ GIMT_Encode4(713232), // Rule ID 13804 //
     /*  713184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1),
     /*  713187 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713195 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713197 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713208 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
     /*  713211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713216 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713230 */     GIR_RootConstrainSelectedInstOperands,
     /*  713231 */     // GIR_Coverage, 13804,
     /*  713231 */     GIR_EraseRootFromParent_Done,
     /*  713232 */   // Label 11280: @713232
     /*  713232 */   GIM_Try, /*On fail goto*//*Label 11281*/ GIMT_Encode4(713285), // Rule ID 13805 //
     /*  713237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2),
     /*  713240 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713248 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713261 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
     /*  713264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713269 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713283 */     GIR_RootConstrainSelectedInstOperands,
     /*  713284 */     // GIR_Coverage, 13805,
     /*  713284 */     GIR_EraseRootFromParent_Done,
     /*  713285 */   // Label 11281: @713285
     /*  713285 */   GIM_Try, /*On fail goto*//*Label 11282*/ GIMT_Encode4(713338), // Rule ID 13806 //
     /*  713290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3),
     /*  713293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713301 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713314 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
     /*  713317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713322 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713336 */     GIR_RootConstrainSelectedInstOperands,
     /*  713337 */     // GIR_Coverage, 13806,
     /*  713337 */     GIR_EraseRootFromParent_Done,
     /*  713338 */   // Label 11282: @713338
     /*  713338 */   GIM_Try, /*On fail goto*//*Label 11283*/ GIMT_Encode4(713391), // Rule ID 13807 //
     /*  713343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4),
     /*  713346 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713354 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713367 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
     /*  713370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713375 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713385 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713389 */     GIR_RootConstrainSelectedInstOperands,
     /*  713390 */     // GIR_Coverage, 13807,
     /*  713390 */     GIR_EraseRootFromParent_Done,
     /*  713391 */   // Label 11283: @713391
     /*  713391 */   GIM_Try, /*On fail goto*//*Label 11284*/ GIMT_Encode4(713448), // Rule ID 13793 //
     /*  713396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode0),
     /*  713399 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713422 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
     /*  713425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713432 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  713442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713446 */     GIR_RootConstrainSelectedInstOperands,
     /*  713447 */     // GIR_Coverage, 13793,
     /*  713447 */     GIR_EraseRootFromParent_Done,
     /*  713448 */   // Label 11284: @713448
     /*  713448 */   GIM_Try, /*On fail goto*//*Label 11285*/ GIMT_Encode4(713505), // Rule ID 13794 //
     /*  713453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode1),
     /*  713456 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713479 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
     /*  713482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713489 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  713499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713503 */     GIR_RootConstrainSelectedInstOperands,
     /*  713504 */     // GIR_Coverage, 13794,
     /*  713504 */     GIR_EraseRootFromParent_Done,
     /*  713505 */   // Label 11285: @713505
     /*  713505 */   GIM_Try, /*On fail goto*//*Label 11286*/ GIMT_Encode4(713562), // Rule ID 13795 //
     /*  713510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode2),
     /*  713513 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713525 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713529 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713536 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
     /*  713539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713546 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  713556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713560 */     GIR_RootConstrainSelectedInstOperands,
     /*  713561 */     // GIR_Coverage, 13795,
     /*  713561 */     GIR_EraseRootFromParent_Done,
     /*  713562 */   // Label 11286: @713562
     /*  713562 */   GIM_Try, /*On fail goto*//*Label 11287*/ GIMT_Encode4(713619), // Rule ID 13796 //
     /*  713567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode3),
     /*  713570 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713582 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713593 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
     /*  713596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713603 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  713613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713617 */     GIR_RootConstrainSelectedInstOperands,
     /*  713618 */     // GIR_Coverage, 13796,
     /*  713618 */     GIR_EraseRootFromParent_Done,
     /*  713619 */   // Label 11287: @713619
     /*  713619 */   GIM_Try, /*On fail goto*//*Label 11288*/ GIMT_Encode4(713676), // Rule ID 13797 //
     /*  713624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HwMode4),
     /*  713627 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  713635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  713639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713643 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  713650 */     // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  713650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
     /*  713653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  713655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  713660 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  713662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  713670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713674 */     GIR_RootConstrainSelectedInstOperands,
     /*  713675 */     // GIR_Coverage, 13797,
     /*  713675 */     GIR_EraseRootFromParent_Done,
     /*  713676 */   // Label 11288: @713676
     /*  713676 */   GIM_Reject,
     /*  713677 */ // Label 11238: @713677
     /*  713677 */ GIM_Reject,
     /*  713678 */ // Label 11185: @713678
     /*  713678 */ GIM_Try, /*On fail goto*//*Label 11289*/ GIMT_Encode4(716662),
     /*  713683 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  713686 */   GIM_Try, /*On fail goto*//*Label 11290*/ GIMT_Encode4(713736), // Rule ID 30510 //
     /*  713691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode0),
     /*  713694 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713699 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713705 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  713712 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  713712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  713715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  713720 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  713722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713734 */     GIR_RootConstrainSelectedInstOperands,
     /*  713735 */     // GIR_Coverage, 30510,
     /*  713735 */     GIR_EraseRootFromParent_Done,
     /*  713736 */   // Label 11290: @713736
     /*  713736 */   GIM_Try, /*On fail goto*//*Label 11291*/ GIMT_Encode4(713786), // Rule ID 30511 //
     /*  713741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode1),
     /*  713744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713749 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713751 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713755 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  713762 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  713762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  713765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  713770 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  713772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713784 */     GIR_RootConstrainSelectedInstOperands,
     /*  713785 */     // GIR_Coverage, 30511,
     /*  713785 */     GIR_EraseRootFromParent_Done,
     /*  713786 */   // Label 11291: @713786
     /*  713786 */   GIM_Try, /*On fail goto*//*Label 11292*/ GIMT_Encode4(713836), // Rule ID 30512 //
     /*  713791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode2),
     /*  713794 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713799 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  713812 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  713812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  713815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  713820 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  713822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713834 */     GIR_RootConstrainSelectedInstOperands,
     /*  713835 */     // GIR_Coverage, 30512,
     /*  713835 */     GIR_EraseRootFromParent_Done,
     /*  713836 */   // Label 11292: @713836
     /*  713836 */   GIM_Try, /*On fail goto*//*Label 11293*/ GIMT_Encode4(713886), // Rule ID 30513 //
     /*  713841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode3),
     /*  713844 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713849 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  713862 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  713862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  713865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  713870 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  713872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713880 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713884 */     GIR_RootConstrainSelectedInstOperands,
     /*  713885 */     // GIR_Coverage, 30513,
     /*  713885 */     GIR_EraseRootFromParent_Done,
     /*  713886 */   // Label 11293: @713886
     /*  713886 */   GIM_Try, /*On fail goto*//*Label 11294*/ GIMT_Encode4(713936), // Rule ID 30514 //
     /*  713891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode4),
     /*  713894 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713899 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713901 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  713912 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  713912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  713915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  713920 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  713922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713930 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713934 */     GIR_RootConstrainSelectedInstOperands,
     /*  713935 */     // GIR_Coverage, 30514,
     /*  713935 */     GIR_EraseRootFromParent_Done,
     /*  713936 */   // Label 11294: @713936
     /*  713936 */   GIM_Try, /*On fail goto*//*Label 11295*/ GIMT_Encode4(713986), // Rule ID 31011 //
     /*  713941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode0),
     /*  713944 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713949 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  713951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  713955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  713962 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  713962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  713965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  713970 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  713972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  713977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  713980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  713984 */     GIR_RootConstrainSelectedInstOperands,
     /*  713985 */     // GIR_Coverage, 31011,
     /*  713985 */     GIR_EraseRootFromParent_Done,
     /*  713986 */   // Label 11295: @713986
     /*  713986 */   GIM_Try, /*On fail goto*//*Label 11296*/ GIMT_Encode4(714036), // Rule ID 31012 //
     /*  713991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode1),
     /*  713994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  713999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  714012 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  714012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  714015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  714020 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  714022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714034 */     GIR_RootConstrainSelectedInstOperands,
     /*  714035 */     // GIR_Coverage, 31012,
     /*  714035 */     GIR_EraseRootFromParent_Done,
     /*  714036 */   // Label 11296: @714036
     /*  714036 */   GIM_Try, /*On fail goto*//*Label 11297*/ GIMT_Encode4(714086), // Rule ID 31013 //
     /*  714041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode2),
     /*  714044 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  714049 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  714062 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  714062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  714065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  714070 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  714072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714080 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714084 */     GIR_RootConstrainSelectedInstOperands,
     /*  714085 */     // GIR_Coverage, 31013,
     /*  714085 */     GIR_EraseRootFromParent_Done,
     /*  714086 */   // Label 11297: @714086
     /*  714086 */   GIM_Try, /*On fail goto*//*Label 11298*/ GIMT_Encode4(714136), // Rule ID 31014 //
     /*  714091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode3),
     /*  714094 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  714099 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714101 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  714112 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  714112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  714115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  714120 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  714122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714134 */     GIR_RootConstrainSelectedInstOperands,
     /*  714135 */     // GIR_Coverage, 31014,
     /*  714135 */     GIR_EraseRootFromParent_Done,
     /*  714136 */   // Label 11298: @714136
     /*  714136 */   GIM_Try, /*On fail goto*//*Label 11299*/ GIMT_Encode4(714186), // Rule ID 31015 //
     /*  714141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HwMode4),
     /*  714144 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  714149 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  714162 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  714162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
     /*  714165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  714170 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  714172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714184 */     GIR_RootConstrainSelectedInstOperands,
     /*  714185 */     // GIR_Coverage, 31015,
     /*  714185 */     GIR_EraseRootFromParent_Done,
     /*  714186 */   // Label 11299: @714186
     /*  714186 */   GIM_Try, /*On fail goto*//*Label 11300*/ GIMT_Encode4(714240), // Rule ID 30509 //
     /*  714191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts),
     /*  714194 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  714199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  714203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  714214 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_v2f16>>  =>  (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  714214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16),
     /*  714217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  714219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  714224 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  714226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714238 */     GIR_RootConstrainSelectedInstOperands,
     /*  714239 */     // GIR_Coverage, 30509,
     /*  714239 */     GIR_EraseRootFromParent_Done,
     /*  714240 */   // Label 11300: @714240
     /*  714240 */   GIM_Try, /*On fail goto*//*Label 11301*/ GIMT_Encode4(714294), // Rule ID 31010 //
     /*  714245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts),
     /*  714248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  714253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  714257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  714268 */     // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_v2f16>>  =>  (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  714268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16),
     /*  714271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  714273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  714278 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  714280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714292 */     GIR_RootConstrainSelectedInstOperands,
     /*  714293 */     // GIR_Coverage, 31010,
     /*  714293 */     GIR_EraseRootFromParent_Done,
     /*  714294 */   // Label 11301: @714294
     /*  714294 */   GIM_Try, /*On fail goto*//*Label 11302*/ GIMT_Encode4(714353), // Rule ID 13706 //
     /*  714299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode0),
     /*  714302 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714309 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714322 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714330 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714347 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714351 */     GIR_RootConstrainSelectedInstOperands,
     /*  714352 */     // GIR_Coverage, 13706,
     /*  714352 */     GIR_EraseRootFromParent_Done,
     /*  714353 */   // Label 11302: @714353
     /*  714353 */   GIM_Try, /*On fail goto*//*Label 11303*/ GIMT_Encode4(714412), // Rule ID 13707 //
     /*  714358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode1),
     /*  714361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714368 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714370 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714374 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714381 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714389 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714406 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714410 */     GIR_RootConstrainSelectedInstOperands,
     /*  714411 */     // GIR_Coverage, 13707,
     /*  714411 */     GIR_EraseRootFromParent_Done,
     /*  714412 */   // Label 11303: @714412
     /*  714412 */   GIM_Try, /*On fail goto*//*Label 11304*/ GIMT_Encode4(714471), // Rule ID 13708 //
     /*  714417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode2),
     /*  714420 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714427 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714440 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714448 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714469 */     GIR_RootConstrainSelectedInstOperands,
     /*  714470 */     // GIR_Coverage, 13708,
     /*  714470 */     GIR_EraseRootFromParent_Done,
     /*  714471 */   // Label 11304: @714471
     /*  714471 */   GIM_Try, /*On fail goto*//*Label 11305*/ GIMT_Encode4(714530), // Rule ID 13709 //
     /*  714476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode3),
     /*  714479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714486 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714499 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714507 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714524 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714528 */     GIR_RootConstrainSelectedInstOperands,
     /*  714529 */     // GIR_Coverage, 13709,
     /*  714529 */     GIR_EraseRootFromParent_Done,
     /*  714530 */   // Label 11305: @714530
     /*  714530 */   GIM_Try, /*On fail goto*//*Label 11306*/ GIMT_Encode4(714589), // Rule ID 13710 //
     /*  714535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode4),
     /*  714538 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714545 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714547 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714551 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714558 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714566 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714583 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714587 */     GIR_RootConstrainSelectedInstOperands,
     /*  714588 */     // GIR_Coverage, 13710,
     /*  714588 */     GIR_EraseRootFromParent_Done,
     /*  714589 */   // Label 11306: @714589
     /*  714589 */   GIM_Try, /*On fail goto*//*Label 11307*/ GIMT_Encode4(714648), // Rule ID 13722 //
     /*  714594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode0),
     /*  714597 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714604 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714617 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714625 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714646 */     GIR_RootConstrainSelectedInstOperands,
     /*  714647 */     // GIR_Coverage, 13722,
     /*  714647 */     GIR_EraseRootFromParent_Done,
     /*  714648 */   // Label 11307: @714648
     /*  714648 */   GIM_Try, /*On fail goto*//*Label 11308*/ GIMT_Encode4(714707), // Rule ID 13723 //
     /*  714653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode1),
     /*  714656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714663 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714676 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714684 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714705 */     GIR_RootConstrainSelectedInstOperands,
     /*  714706 */     // GIR_Coverage, 13723,
     /*  714706 */     GIR_EraseRootFromParent_Done,
     /*  714707 */   // Label 11308: @714707
     /*  714707 */   GIM_Try, /*On fail goto*//*Label 11309*/ GIMT_Encode4(714766), // Rule ID 13724 //
     /*  714712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode2),
     /*  714715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714722 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714724 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714735 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714743 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714760 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714764 */     GIR_RootConstrainSelectedInstOperands,
     /*  714765 */     // GIR_Coverage, 13724,
     /*  714765 */     GIR_EraseRootFromParent_Done,
     /*  714766 */   // Label 11309: @714766
     /*  714766 */   GIM_Try, /*On fail goto*//*Label 11310*/ GIMT_Encode4(714825), // Rule ID 13725 //
     /*  714771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode3),
     /*  714774 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714781 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714794 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714802 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714823 */     GIR_RootConstrainSelectedInstOperands,
     /*  714824 */     // GIR_Coverage, 13725,
     /*  714824 */     GIR_EraseRootFromParent_Done,
     /*  714825 */   // Label 11310: @714825
     /*  714825 */   GIM_Try, /*On fail goto*//*Label 11311*/ GIMT_Encode4(714884), // Rule ID 13726 //
     /*  714830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode4),
     /*  714833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714840 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714842 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  714853 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
     /*  714856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714861 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714878 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714882 */     GIR_RootConstrainSelectedInstOperands,
     /*  714883 */     // GIR_Coverage, 13726,
     /*  714883 */     GIR_EraseRootFromParent_Done,
     /*  714884 */   // Label 11311: @714884
     /*  714884 */   GIM_Try, /*On fail goto*//*Label 11312*/ GIMT_Encode4(714947), // Rule ID 13732 //
     /*  714889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts),
     /*  714892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  714903 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  714914 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  714914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN),
     /*  714917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  714919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  714924 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  714931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  714936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  714941 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714945 */     GIR_RootConstrainSelectedInstOperands,
     /*  714946 */     // GIR_Coverage, 13732,
     /*  714946 */     GIR_EraseRootFromParent_Done,
     /*  714947 */   // Label 11312: @714947
     /*  714947 */   GIM_Try, /*On fail goto*//*Label 11313*/ GIMT_Encode4(714999), // Rule ID 13701 //
     /*  714952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode0),
     /*  714955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  714962 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  714964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  714968 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  714975 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  714975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  714978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  714983 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  714985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  714990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  714993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  714997 */     GIR_RootConstrainSelectedInstOperands,
     /*  714998 */     // GIR_Coverage, 13701,
     /*  714998 */     GIR_EraseRootFromParent_Done,
     /*  714999 */   // Label 11313: @714999
     /*  714999 */   GIM_Try, /*On fail goto*//*Label 11314*/ GIMT_Encode4(715051), // Rule ID 13702 //
     /*  715004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode1),
     /*  715007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715014 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715027 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715035 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715049 */     GIR_RootConstrainSelectedInstOperands,
     /*  715050 */     // GIR_Coverage, 13702,
     /*  715050 */     GIR_EraseRootFromParent_Done,
     /*  715051 */   // Label 11314: @715051
     /*  715051 */   GIM_Try, /*On fail goto*//*Label 11315*/ GIMT_Encode4(715103), // Rule ID 13703 //
     /*  715056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode2),
     /*  715059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715066 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715079 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715087 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715097 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715101 */     GIR_RootConstrainSelectedInstOperands,
     /*  715102 */     // GIR_Coverage, 13703,
     /*  715102 */     GIR_EraseRootFromParent_Done,
     /*  715103 */   // Label 11315: @715103
     /*  715103 */   GIM_Try, /*On fail goto*//*Label 11316*/ GIMT_Encode4(715155), // Rule ID 13704 //
     /*  715108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode3),
     /*  715111 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715118 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715131 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715139 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715153 */     GIR_RootConstrainSelectedInstOperands,
     /*  715154 */     // GIR_Coverage, 13704,
     /*  715154 */     GIR_EraseRootFromParent_Done,
     /*  715155 */   // Label 11316: @715155
     /*  715155 */   GIM_Try, /*On fail goto*//*Label 11317*/ GIMT_Encode4(715207), // Rule ID 13705 //
     /*  715160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode4),
     /*  715163 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715170 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715183 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715191 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715205 */     GIR_RootConstrainSelectedInstOperands,
     /*  715206 */     // GIR_Coverage, 13705,
     /*  715206 */     GIR_EraseRootFromParent_Done,
     /*  715207 */   // Label 11317: @715207
     /*  715207 */   GIM_Try, /*On fail goto*//*Label 11318*/ GIMT_Encode4(715259), // Rule ID 13717 //
     /*  715212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode0),
     /*  715215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715222 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715235 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715243 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715257 */     GIR_RootConstrainSelectedInstOperands,
     /*  715258 */     // GIR_Coverage, 13717,
     /*  715258 */     GIR_EraseRootFromParent_Done,
     /*  715259 */   // Label 11318: @715259
     /*  715259 */   GIM_Try, /*On fail goto*//*Label 11319*/ GIMT_Encode4(715311), // Rule ID 13718 //
     /*  715264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode1),
     /*  715267 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715274 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715280 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715287 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715295 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715309 */     GIR_RootConstrainSelectedInstOperands,
     /*  715310 */     // GIR_Coverage, 13718,
     /*  715310 */     GIR_EraseRootFromParent_Done,
     /*  715311 */   // Label 11319: @715311
     /*  715311 */   GIM_Try, /*On fail goto*//*Label 11320*/ GIMT_Encode4(715363), // Rule ID 13719 //
     /*  715316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode2),
     /*  715319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715326 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715339 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715347 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715361 */     GIR_RootConstrainSelectedInstOperands,
     /*  715362 */     // GIR_Coverage, 13719,
     /*  715362 */     GIR_EraseRootFromParent_Done,
     /*  715363 */   // Label 11320: @715363
     /*  715363 */   GIM_Try, /*On fail goto*//*Label 11321*/ GIMT_Encode4(715415), // Rule ID 13720 //
     /*  715368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode3),
     /*  715371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715378 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715380 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715391 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715399 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715413 */     GIR_RootConstrainSelectedInstOperands,
     /*  715414 */     // GIR_Coverage, 13720,
     /*  715414 */     GIR_EraseRootFromParent_Done,
     /*  715415 */   // Label 11321: @715415
     /*  715415 */   GIM_Try, /*On fail goto*//*Label 11322*/ GIMT_Encode4(715467), // Rule ID 13721 //
     /*  715420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HwMode4),
     /*  715423 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715430 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715432 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715443 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
     /*  715446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715451 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  715461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715465 */     GIR_RootConstrainSelectedInstOperands,
     /*  715466 */     // GIR_Coverage, 13721,
     /*  715466 */     GIR_EraseRootFromParent_Done,
     /*  715467 */   // Label 11322: @715467
     /*  715467 */   GIM_Try, /*On fail goto*//*Label 11323*/ GIMT_Encode4(715523), // Rule ID 13727 //
     /*  715472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode0),
     /*  715475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  715486 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715497 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
     /*  715500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  715502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715507 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  715517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715521 */     GIR_RootConstrainSelectedInstOperands,
     /*  715522 */     // GIR_Coverage, 13727,
     /*  715522 */     GIR_EraseRootFromParent_Done,
     /*  715523 */   // Label 11323: @715523
     /*  715523 */   GIM_Try, /*On fail goto*//*Label 11324*/ GIMT_Encode4(715579), // Rule ID 13728 //
     /*  715528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode1),
     /*  715531 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  715542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715553 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
     /*  715556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  715558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715563 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  715573 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715577 */     GIR_RootConstrainSelectedInstOperands,
     /*  715578 */     // GIR_Coverage, 13728,
     /*  715578 */     GIR_EraseRootFromParent_Done,
     /*  715579 */   // Label 11324: @715579
     /*  715579 */   GIM_Try, /*On fail goto*//*Label 11325*/ GIMT_Encode4(715635), // Rule ID 13729 //
     /*  715584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode2),
     /*  715587 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  715598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715609 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
     /*  715612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  715614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715619 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  715629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715633 */     GIR_RootConstrainSelectedInstOperands,
     /*  715634 */     // GIR_Coverage, 13729,
     /*  715634 */     GIR_EraseRootFromParent_Done,
     /*  715635 */   // Label 11325: @715635
     /*  715635 */   GIM_Try, /*On fail goto*//*Label 11326*/ GIMT_Encode4(715691), // Rule ID 13730 //
     /*  715640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode3),
     /*  715643 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  715654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715665 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
     /*  715668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  715670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715675 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  715685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715689 */     GIR_RootConstrainSelectedInstOperands,
     /*  715690 */     // GIR_Coverage, 13730,
     /*  715690 */     GIR_EraseRootFromParent_Done,
     /*  715691 */   // Label 11326: @715691
     /*  715691 */   GIM_Try, /*On fail goto*//*Label 11327*/ GIMT_Encode4(715747), // Rule ID 13731 //
     /*  715696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HwMode4),
     /*  715699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  715710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  715721 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  715721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
     /*  715724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  715726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  715731 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  715738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  715741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715745 */     GIR_RootConstrainSelectedInstOperands,
     /*  715746 */     // GIR_Coverage, 13731,
     /*  715746 */     GIR_EraseRootFromParent_Done,
     /*  715747 */   // Label 11327: @715747
     /*  715747 */   GIM_Try, /*On fail goto*//*Label 11328*/ GIMT_Encode4(715807), // Rule ID 13840 //
     /*  715752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode0),
     /*  715755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715763 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  715776 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  715776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR),
     /*  715779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  715784 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  715791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  715796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  715801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715805 */     GIR_RootConstrainSelectedInstOperands,
     /*  715806 */     // GIR_Coverage, 13840,
     /*  715806 */     GIR_EraseRootFromParent_Done,
     /*  715807 */   // Label 11328: @715807
     /*  715807 */   GIM_Try, /*On fail goto*//*Label 11329*/ GIMT_Encode4(715867), // Rule ID 13841 //
     /*  715812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode1),
     /*  715815 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715823 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715825 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  715836 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  715836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR),
     /*  715839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  715844 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  715851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  715856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  715861 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715865 */     GIR_RootConstrainSelectedInstOperands,
     /*  715866 */     // GIR_Coverage, 13841,
     /*  715866 */     GIR_EraseRootFromParent_Done,
     /*  715867 */   // Label 11329: @715867
     /*  715867 */   GIM_Try, /*On fail goto*//*Label 11330*/ GIMT_Encode4(715927), // Rule ID 13842 //
     /*  715872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode2),
     /*  715875 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715883 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  715896 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  715896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR),
     /*  715899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  715904 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  715911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  715916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  715921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715925 */     GIR_RootConstrainSelectedInstOperands,
     /*  715926 */     // GIR_Coverage, 13842,
     /*  715926 */     GIR_EraseRootFromParent_Done,
     /*  715927 */   // Label 11330: @715927
     /*  715927 */   GIM_Try, /*On fail goto*//*Label 11331*/ GIMT_Encode4(715987), // Rule ID 13843 //
     /*  715932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode3),
     /*  715935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  715943 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  715945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  715949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  715956 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  715956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR),
     /*  715959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  715964 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  715966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  715971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  715976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  715981 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  715985 */     GIR_RootConstrainSelectedInstOperands,
     /*  715986 */     // GIR_Coverage, 13843,
     /*  715986 */     GIR_EraseRootFromParent_Done,
     /*  715987 */   // Label 11331: @715987
     /*  715987 */   GIM_Try, /*On fail goto*//*Label 11332*/ GIMT_Encode4(716047), // Rule ID 13844 //
     /*  715992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode_HwMode4),
     /*  715995 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716003 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  716016 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  716016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR),
     /*  716019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  716024 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  716031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  716036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  716041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716045 */     GIR_RootConstrainSelectedInstOperands,
     /*  716046 */     // GIR_Coverage, 13844,
     /*  716046 */     GIR_EraseRootFromParent_Done,
     /*  716047 */   // Label 11332: @716047
     /*  716047 */   GIM_Try, /*On fail goto*//*Label 11333*/ GIMT_Encode4(716111), // Rule ID 13834 //
     /*  716052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HasFlatGVSMode),
     /*  716055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  716067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716071 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  716078 */     // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  716078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_SADDR_RTN),
     /*  716081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  716083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  716088 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  716095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  716100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  716105 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716109 */     GIR_RootConstrainSelectedInstOperands,
     /*  716110 */     // GIR_Coverage, 13834,
     /*  716110 */     GIR_EraseRootFromParent_Done,
     /*  716111 */   // Label 11333: @716111
     /*  716111 */   GIM_Try, /*On fail goto*//*Label 11334*/ GIMT_Encode4(716164), // Rule ID 13835 //
     /*  716116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode0),
     /*  716119 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716127 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716133 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716140 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16),
     /*  716143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716148 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716162 */     GIR_RootConstrainSelectedInstOperands,
     /*  716163 */     // GIR_Coverage, 13835,
     /*  716163 */     GIR_EraseRootFromParent_Done,
     /*  716164 */   // Label 11334: @716164
     /*  716164 */   GIM_Try, /*On fail goto*//*Label 11335*/ GIMT_Encode4(716217), // Rule ID 13836 //
     /*  716169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode1),
     /*  716172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716180 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716182 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716193 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16),
     /*  716196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716201 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716215 */     GIR_RootConstrainSelectedInstOperands,
     /*  716216 */     // GIR_Coverage, 13836,
     /*  716216 */     GIR_EraseRootFromParent_Done,
     /*  716217 */   // Label 11335: @716217
     /*  716217 */   GIM_Try, /*On fail goto*//*Label 11336*/ GIMT_Encode4(716270), // Rule ID 13837 //
     /*  716222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode2),
     /*  716225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716233 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716235 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716239 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716246 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16),
     /*  716249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716254 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716268 */     GIR_RootConstrainSelectedInstOperands,
     /*  716269 */     // GIR_Coverage, 13837,
     /*  716269 */     GIR_EraseRootFromParent_Done,
     /*  716270 */   // Label 11336: @716270
     /*  716270 */   GIM_Try, /*On fail goto*//*Label 11337*/ GIMT_Encode4(716323), // Rule ID 13838 //
     /*  716275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode3),
     /*  716278 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716286 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716299 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16),
     /*  716302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716307 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716317 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716321 */     GIR_RootConstrainSelectedInstOperands,
     /*  716322 */     // GIR_Coverage, 13838,
     /*  716322 */     GIR_EraseRootFromParent_Done,
     /*  716323 */   // Label 11337: @716323
     /*  716323 */   GIM_Try, /*On fail goto*//*Label 11338*/ GIMT_Encode4(716376), // Rule ID 13839 //
     /*  716328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode4),
     /*  716331 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716339 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716341 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716352 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16),
     /*  716355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716360 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716374 */     GIR_RootConstrainSelectedInstOperands,
     /*  716375 */     // GIR_Coverage, 13839,
     /*  716375 */     GIR_EraseRootFromParent_Done,
     /*  716376 */   // Label 11338: @716376
     /*  716376 */   GIM_Try, /*On fail goto*//*Label 11339*/ GIMT_Encode4(716433), // Rule ID 13829 //
     /*  716381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode0),
     /*  716384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  716396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716407 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN),
     /*  716410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  716412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716417 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  716427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716431 */     GIR_RootConstrainSelectedInstOperands,
     /*  716432 */     // GIR_Coverage, 13829,
     /*  716432 */     GIR_EraseRootFromParent_Done,
     /*  716433 */   // Label 11339: @716433
     /*  716433 */   GIM_Try, /*On fail goto*//*Label 11340*/ GIMT_Encode4(716490), // Rule ID 13830 //
     /*  716438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode1),
     /*  716441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  716453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716464 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN),
     /*  716467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  716469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716474 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  716484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716488 */     GIR_RootConstrainSelectedInstOperands,
     /*  716489 */     // GIR_Coverage, 13830,
     /*  716489 */     GIR_EraseRootFromParent_Done,
     /*  716490 */   // Label 11340: @716490
     /*  716490 */   GIM_Try, /*On fail goto*//*Label 11341*/ GIMT_Encode4(716547), // Rule ID 13831 //
     /*  716495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode2),
     /*  716498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  716510 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716521 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN),
     /*  716524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  716526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716531 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  716541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716545 */     GIR_RootConstrainSelectedInstOperands,
     /*  716546 */     // GIR_Coverage, 13831,
     /*  716546 */     GIR_EraseRootFromParent_Done,
     /*  716547 */   // Label 11341: @716547
     /*  716547 */   GIM_Try, /*On fail goto*//*Label 11342*/ GIMT_Encode4(716604), // Rule ID 13832 //
     /*  716552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode3),
     /*  716555 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  716567 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716578 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN),
     /*  716581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  716583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716588 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  716598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716602 */     GIR_RootConstrainSelectedInstOperands,
     /*  716603 */     // GIR_Coverage, 13832,
     /*  716603 */     GIR_EraseRootFromParent_Done,
     /*  716604 */   // Label 11342: @716604
     /*  716604 */   GIM_Try, /*On fail goto*//*Label 11343*/ GIMT_Encode4(716661), // Rule ID 13833 //
     /*  716609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts_HwMode4),
     /*  716612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  716624 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  716635 */     // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>>  =>  (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
     /*  716635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN),
     /*  716638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  716640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  716645 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  716647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  716652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  716655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716659 */     GIR_RootConstrainSelectedInstOperands,
     /*  716660 */     // GIR_Coverage, 13833,
     /*  716660 */     GIR_EraseRootFromParent_Done,
     /*  716661 */   // Label 11343: @716661
     /*  716661 */   GIM_Reject,
     /*  716662 */ // Label 11289: @716662
     /*  716662 */ GIM_Reject,
     /*  716663 */ // Label 11186: @716663
     /*  716663 */ GIM_Reject,
     /*  716664 */ // Label 30: @716664
     /*  716664 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 11346*/ GIMT_Encode4(731189),
     /*  716675 */ /*GILLT_s32*//*Label 11344*/ GIMT_Encode4(716683),
     /*  716679 */ /*GILLT_s64*//*Label 11345*/ GIMT_Encode4(723689),
     /*  716683 */ // Label 11344: @716683
     /*  716683 */ GIM_Try, /*On fail goto*//*Label 11347*/ GIMT_Encode4(723688),
     /*  716688 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  716691 */   GIM_Try, /*On fail goto*//*Label 11348*/ GIMT_Encode4(716753), // Rule ID 21738 //
     /*  716696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  716699 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716706 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716708 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  716719 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  716719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64),
     /*  716722 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  716724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  716729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  716734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  716739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  716744 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716751 */     GIR_RootConstrainSelectedInstOperands,
     /*  716752 */     // GIR_Coverage, 21738,
     /*  716752 */     GIR_EraseRootFromParent_Done,
     /*  716753 */   // Label 11348: @716753
     /*  716753 */   GIM_Try, /*On fail goto*//*Label 11349*/ GIMT_Encode4(716815), // Rule ID 21739 //
     /*  716758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  716761 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716768 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716770 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716774 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  716781 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  716781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64),
     /*  716784 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  716786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  716791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  716796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  716801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  716806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716813 */     GIR_RootConstrainSelectedInstOperands,
     /*  716814 */     // GIR_Coverage, 21739,
     /*  716814 */     GIR_EraseRootFromParent_Done,
     /*  716815 */   // Label 11349: @716815
     /*  716815 */   GIM_Try, /*On fail goto*//*Label 11350*/ GIMT_Encode4(716877), // Rule ID 21740 //
     /*  716820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  716823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716830 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716832 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  716843 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  716843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64),
     /*  716846 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  716848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  716853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  716858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  716863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  716868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716871 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716875 */     GIR_RootConstrainSelectedInstOperands,
     /*  716876 */     // GIR_Coverage, 21740,
     /*  716876 */     GIR_EraseRootFromParent_Done,
     /*  716877 */   // Label 11350: @716877
     /*  716877 */   GIM_Try, /*On fail goto*//*Label 11351*/ GIMT_Encode4(716939), // Rule ID 21741 //
     /*  716882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  716885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716892 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  716905 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  716905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64),
     /*  716908 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  716910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  716915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  716920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  716925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  716930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716933 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716937 */     GIR_RootConstrainSelectedInstOperands,
     /*  716938 */     // GIR_Coverage, 21741,
     /*  716938 */     GIR_EraseRootFromParent_Done,
     /*  716939 */   // Label 11351: @716939
     /*  716939 */   GIM_Try, /*On fail goto*//*Label 11352*/ GIMT_Encode4(717001), // Rule ID 21742 //
     /*  716944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  716947 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  716954 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  716956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  716960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  716967 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  716967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64),
     /*  716970 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  716972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  716977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  716982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  716987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  716992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  716995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  716999 */     GIR_RootConstrainSelectedInstOperands,
     /*  717000 */     // GIR_Coverage, 21742,
     /*  717000 */     GIR_EraseRootFromParent_Done,
     /*  717001 */   // Label 11352: @717001
     /*  717001 */   GIM_Try, /*On fail goto*//*Label 11353*/ GIMT_Encode4(717063), // Rule ID 21758 //
     /*  717006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  717009 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717016 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  717018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717029 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64),
     /*  717032 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  717057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717061 */     GIR_RootConstrainSelectedInstOperands,
     /*  717062 */     // GIR_Coverage, 21758,
     /*  717062 */     GIR_EraseRootFromParent_Done,
     /*  717063 */   // Label 11353: @717063
     /*  717063 */   GIM_Try, /*On fail goto*//*Label 11354*/ GIMT_Encode4(717125), // Rule ID 21759 //
     /*  717068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  717071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717078 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  717080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717091 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64),
     /*  717094 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  717119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717123 */     GIR_RootConstrainSelectedInstOperands,
     /*  717124 */     // GIR_Coverage, 21759,
     /*  717124 */     GIR_EraseRootFromParent_Done,
     /*  717125 */   // Label 11354: @717125
     /*  717125 */   GIM_Try, /*On fail goto*//*Label 11355*/ GIMT_Encode4(717187), // Rule ID 21760 //
     /*  717130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  717133 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717140 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  717142 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717153 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64),
     /*  717156 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  717181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717185 */     GIR_RootConstrainSelectedInstOperands,
     /*  717186 */     // GIR_Coverage, 21760,
     /*  717186 */     GIR_EraseRootFromParent_Done,
     /*  717187 */   // Label 11355: @717187
     /*  717187 */   GIM_Try, /*On fail goto*//*Label 11356*/ GIMT_Encode4(717249), // Rule ID 21761 //
     /*  717192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  717195 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717202 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  717204 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717208 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717215 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64),
     /*  717218 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  717243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717247 */     GIR_RootConstrainSelectedInstOperands,
     /*  717248 */     // GIR_Coverage, 21761,
     /*  717248 */     GIR_EraseRootFromParent_Done,
     /*  717249 */   // Label 11356: @717249
     /*  717249 */   GIM_Try, /*On fail goto*//*Label 11357*/ GIMT_Encode4(717311), // Rule ID 21762 //
     /*  717254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  717257 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717264 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  717266 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717277 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64),
     /*  717280 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  717305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717309 */     GIR_RootConstrainSelectedInstOperands,
     /*  717310 */     // GIR_Coverage, 21762,
     /*  717310 */     GIR_EraseRootFromParent_Done,
     /*  717311 */   // Label 11357: @717311
     /*  717311 */   GIM_Try, /*On fail goto*//*Label 11358*/ GIMT_Encode4(717377), // Rule ID 21728 //
     /*  717316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  717319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717341 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN),
     /*  717344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717346 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717371 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717375 */     GIR_RootConstrainSelectedInstOperands,
     /*  717376 */     // GIR_Coverage, 21728,
     /*  717376 */     GIR_EraseRootFromParent_Done,
     /*  717377 */   // Label 11358: @717377
     /*  717377 */   GIM_Try, /*On fail goto*//*Label 11359*/ GIMT_Encode4(717443), // Rule ID 21729 //
     /*  717382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  717385 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717407 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN),
     /*  717410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717412 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717441 */     GIR_RootConstrainSelectedInstOperands,
     /*  717442 */     // GIR_Coverage, 21729,
     /*  717442 */     GIR_EraseRootFromParent_Done,
     /*  717443 */   // Label 11359: @717443
     /*  717443 */   GIM_Try, /*On fail goto*//*Label 11360*/ GIMT_Encode4(717509), // Rule ID 21730 //
     /*  717448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  717451 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717466 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717473 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN),
     /*  717476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717478 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717507 */     GIR_RootConstrainSelectedInstOperands,
     /*  717508 */     // GIR_Coverage, 21730,
     /*  717508 */     GIR_EraseRootFromParent_Done,
     /*  717509 */   // Label 11360: @717509
     /*  717509 */   GIM_Try, /*On fail goto*//*Label 11361*/ GIMT_Encode4(717575), // Rule ID 21731 //
     /*  717514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  717517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717539 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN),
     /*  717542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717544 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717569 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717573 */     GIR_RootConstrainSelectedInstOperands,
     /*  717574 */     // GIR_Coverage, 21731,
     /*  717574 */     GIR_EraseRootFromParent_Done,
     /*  717575 */   // Label 11361: @717575
     /*  717575 */   GIM_Try, /*On fail goto*//*Label 11362*/ GIMT_Encode4(717641), // Rule ID 21732 //
     /*  717580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  717583 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717605 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN),
     /*  717608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717610 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717639 */     GIR_RootConstrainSelectedInstOperands,
     /*  717640 */     // GIR_Coverage, 21732,
     /*  717640 */     GIR_EraseRootFromParent_Done,
     /*  717641 */   // Label 11362: @717641
     /*  717641 */   GIM_Try, /*On fail goto*//*Label 11363*/ GIMT_Encode4(717707), // Rule ID 21748 //
     /*  717646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  717649 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717671 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN),
     /*  717674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717676 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717705 */     GIR_RootConstrainSelectedInstOperands,
     /*  717706 */     // GIR_Coverage, 21748,
     /*  717706 */     GIR_EraseRootFromParent_Done,
     /*  717707 */   // Label 11363: @717707
     /*  717707 */   GIM_Try, /*On fail goto*//*Label 11364*/ GIMT_Encode4(717773), // Rule ID 21749 //
     /*  717712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  717715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717726 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717730 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717737 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN),
     /*  717740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717742 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717771 */     GIR_RootConstrainSelectedInstOperands,
     /*  717772 */     // GIR_Coverage, 21749,
     /*  717772 */     GIR_EraseRootFromParent_Done,
     /*  717773 */   // Label 11364: @717773
     /*  717773 */   GIM_Try, /*On fail goto*//*Label 11365*/ GIMT_Encode4(717839), // Rule ID 21750 //
     /*  717778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  717781 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717803 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN),
     /*  717806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717808 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717837 */     GIR_RootConstrainSelectedInstOperands,
     /*  717838 */     // GIR_Coverage, 21750,
     /*  717838 */     GIR_EraseRootFromParent_Done,
     /*  717839 */   // Label 11365: @717839
     /*  717839 */   GIM_Try, /*On fail goto*//*Label 11366*/ GIMT_Encode4(717905), // Rule ID 21751 //
     /*  717844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  717847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717862 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717869 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN),
     /*  717872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717874 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717903 */     GIR_RootConstrainSelectedInstOperands,
     /*  717904 */     // GIR_Coverage, 21751,
     /*  717904 */     GIR_EraseRootFromParent_Done,
     /*  717905 */   // Label 11366: @717905
     /*  717905 */   GIM_Try, /*On fail goto*//*Label 11367*/ GIMT_Encode4(717971), // Rule ID 21752 //
     /*  717910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  717913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  717924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  717935 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN),
     /*  717938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  717940 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  717942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  717947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  717952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  717957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  717962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  717965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  717969 */     GIR_RootConstrainSelectedInstOperands,
     /*  717970 */     // GIR_Coverage, 21752,
     /*  717970 */     GIR_EraseRootFromParent_Done,
     /*  717971 */   // Label 11367: @717971
     /*  717971 */   GIM_Try, /*On fail goto*//*Label 11368*/ GIMT_Encode4(718028), // Rule ID 21733 //
     /*  717976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  717979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  717986 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  717988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  717992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  717999 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  717999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET),
     /*  718002 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718026 */     GIR_RootConstrainSelectedInstOperands,
     /*  718027 */     // GIR_Coverage, 21733,
     /*  718027 */     GIR_EraseRootFromParent_Done,
     /*  718028 */   // Label 11368: @718028
     /*  718028 */   GIM_Try, /*On fail goto*//*Label 11369*/ GIMT_Encode4(718085), // Rule ID 21734 //
     /*  718033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  718036 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718043 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718056 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET),
     /*  718059 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718079 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718083 */     GIR_RootConstrainSelectedInstOperands,
     /*  718084 */     // GIR_Coverage, 21734,
     /*  718084 */     GIR_EraseRootFromParent_Done,
     /*  718085 */   // Label 11369: @718085
     /*  718085 */   GIM_Try, /*On fail goto*//*Label 11370*/ GIMT_Encode4(718142), // Rule ID 21735 //
     /*  718090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  718093 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718100 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718102 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718113 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET),
     /*  718116 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718140 */     GIR_RootConstrainSelectedInstOperands,
     /*  718141 */     // GIR_Coverage, 21735,
     /*  718141 */     GIR_EraseRootFromParent_Done,
     /*  718142 */   // Label 11370: @718142
     /*  718142 */   GIM_Try, /*On fail goto*//*Label 11371*/ GIMT_Encode4(718199), // Rule ID 21736 //
     /*  718147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  718150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718157 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718159 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718163 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718170 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET),
     /*  718173 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718197 */     GIR_RootConstrainSelectedInstOperands,
     /*  718198 */     // GIR_Coverage, 21736,
     /*  718198 */     GIR_EraseRootFromParent_Done,
     /*  718199 */   // Label 11371: @718199
     /*  718199 */   GIM_Try, /*On fail goto*//*Label 11372*/ GIMT_Encode4(718256), // Rule ID 21737 //
     /*  718204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  718207 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718214 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718227 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET),
     /*  718230 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718254 */     GIR_RootConstrainSelectedInstOperands,
     /*  718255 */     // GIR_Coverage, 21737,
     /*  718255 */     GIR_EraseRootFromParent_Done,
     /*  718256 */   // Label 11372: @718256
     /*  718256 */   GIM_Try, /*On fail goto*//*Label 11373*/ GIMT_Encode4(718313), // Rule ID 21753 //
     /*  718261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  718264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718271 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718277 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718284 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET),
     /*  718287 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718311 */     GIR_RootConstrainSelectedInstOperands,
     /*  718312 */     // GIR_Coverage, 21753,
     /*  718312 */     GIR_EraseRootFromParent_Done,
     /*  718313 */   // Label 11373: @718313
     /*  718313 */   GIM_Try, /*On fail goto*//*Label 11374*/ GIMT_Encode4(718370), // Rule ID 21754 //
     /*  718318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  718321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718328 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718341 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET),
     /*  718344 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718368 */     GIR_RootConstrainSelectedInstOperands,
     /*  718369 */     // GIR_Coverage, 21754,
     /*  718369 */     GIR_EraseRootFromParent_Done,
     /*  718370 */   // Label 11374: @718370
     /*  718370 */   GIM_Try, /*On fail goto*//*Label 11375*/ GIMT_Encode4(718427), // Rule ID 21755 //
     /*  718375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  718378 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718385 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718387 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718398 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET),
     /*  718401 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718425 */     GIR_RootConstrainSelectedInstOperands,
     /*  718426 */     // GIR_Coverage, 21755,
     /*  718426 */     GIR_EraseRootFromParent_Done,
     /*  718427 */   // Label 11375: @718427
     /*  718427 */   GIM_Try, /*On fail goto*//*Label 11376*/ GIMT_Encode4(718484), // Rule ID 21756 //
     /*  718432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  718435 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718442 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718444 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718455 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET),
     /*  718458 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718482 */     GIR_RootConstrainSelectedInstOperands,
     /*  718483 */     // GIR_Coverage, 21756,
     /*  718483 */     GIR_EraseRootFromParent_Done,
     /*  718484 */   // Label 11376: @718484
     /*  718484 */   GIM_Try, /*On fail goto*//*Label 11377*/ GIMT_Encode4(718541), // Rule ID 21757 //
     /*  718489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  718492 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718499 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  718501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718512 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET),
     /*  718515 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  718535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718539 */     GIR_RootConstrainSelectedInstOperands,
     /*  718540 */     // GIR_Coverage, 21757,
     /*  718540 */     GIR_EraseRootFromParent_Done,
     /*  718541 */   // Label 11377: @718541
     /*  718541 */   GIM_Try, /*On fail goto*//*Label 11378*/ GIMT_Encode4(718602), // Rule ID 21723 //
     /*  718546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  718549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718571 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN),
     /*  718574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718576 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718600 */     GIR_RootConstrainSelectedInstOperands,
     /*  718601 */     // GIR_Coverage, 21723,
     /*  718601 */     GIR_EraseRootFromParent_Done,
     /*  718602 */   // Label 11378: @718602
     /*  718602 */   GIM_Try, /*On fail goto*//*Label 11379*/ GIMT_Encode4(718663), // Rule ID 21724 //
     /*  718607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  718610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718632 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN),
     /*  718635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718637 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718661 */     GIR_RootConstrainSelectedInstOperands,
     /*  718662 */     // GIR_Coverage, 21724,
     /*  718662 */     GIR_EraseRootFromParent_Done,
     /*  718663 */   // Label 11379: @718663
     /*  718663 */   GIM_Try, /*On fail goto*//*Label 11380*/ GIMT_Encode4(718724), // Rule ID 21725 //
     /*  718668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  718671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718693 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN),
     /*  718696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718698 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718722 */     GIR_RootConstrainSelectedInstOperands,
     /*  718723 */     // GIR_Coverage, 21725,
     /*  718723 */     GIR_EraseRootFromParent_Done,
     /*  718724 */   // Label 11380: @718724
     /*  718724 */   GIM_Try, /*On fail goto*//*Label 11381*/ GIMT_Encode4(718785), // Rule ID 21726 //
     /*  718729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  718732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718754 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN),
     /*  718757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718759 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718783 */     GIR_RootConstrainSelectedInstOperands,
     /*  718784 */     // GIR_Coverage, 21726,
     /*  718784 */     GIR_EraseRootFromParent_Done,
     /*  718785 */   // Label 11381: @718785
     /*  718785 */   GIM_Try, /*On fail goto*//*Label 11382*/ GIMT_Encode4(718846), // Rule ID 21727 //
     /*  718790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  718793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718815 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN),
     /*  718818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718820 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718844 */     GIR_RootConstrainSelectedInstOperands,
     /*  718845 */     // GIR_Coverage, 21727,
     /*  718845 */     GIR_EraseRootFromParent_Done,
     /*  718846 */   // Label 11382: @718846
     /*  718846 */   GIM_Try, /*On fail goto*//*Label 11383*/ GIMT_Encode4(718907), // Rule ID 21743 //
     /*  718851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  718854 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718865 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718876 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN),
     /*  718879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718881 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718905 */     GIR_RootConstrainSelectedInstOperands,
     /*  718906 */     // GIR_Coverage, 21743,
     /*  718906 */     GIR_EraseRootFromParent_Done,
     /*  718907 */   // Label 11383: @718907
     /*  718907 */   GIM_Try, /*On fail goto*//*Label 11384*/ GIMT_Encode4(718968), // Rule ID 21744 //
     /*  718912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  718915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718937 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN),
     /*  718940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  718942 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  718944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  718949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  718954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  718959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  718962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  718966 */     GIR_RootConstrainSelectedInstOperands,
     /*  718967 */     // GIR_Coverage, 21744,
     /*  718967 */     GIR_EraseRootFromParent_Done,
     /*  718968 */   // Label 11384: @718968
     /*  718968 */   GIM_Try, /*On fail goto*//*Label 11385*/ GIMT_Encode4(719029), // Rule ID 21745 //
     /*  718973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  718976 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  718983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  718987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  718991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  718998 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  718998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN),
     /*  719001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  719003 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  719005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  719010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  719015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  719020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719027 */     GIR_RootConstrainSelectedInstOperands,
     /*  719028 */     // GIR_Coverage, 21745,
     /*  719028 */     GIR_EraseRootFromParent_Done,
     /*  719029 */   // Label 11385: @719029
     /*  719029 */   GIM_Try, /*On fail goto*//*Label 11386*/ GIMT_Encode4(719090), // Rule ID 21746 //
     /*  719034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  719037 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  719044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  719048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  719059 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  719059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN),
     /*  719062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  719064 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  719066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  719071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  719076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  719081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719088 */     GIR_RootConstrainSelectedInstOperands,
     /*  719089 */     // GIR_Coverage, 21746,
     /*  719089 */     GIR_EraseRootFromParent_Done,
     /*  719090 */   // Label 11386: @719090
     /*  719090 */   GIM_Try, /*On fail goto*//*Label 11387*/ GIMT_Encode4(719151), // Rule ID 21747 //
     /*  719095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  719098 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  719105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  719109 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  719120 */     // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  719120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN),
     /*  719123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  719125 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  719127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  719132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  719137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  719142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719149 */     GIR_RootConstrainSelectedInstOperands,
     /*  719150 */     // GIR_Coverage, 21747,
     /*  719150 */     GIR_EraseRootFromParent_Done,
     /*  719151 */   // Label 11387: @719151
     /*  719151 */   GIM_Try, /*On fail goto*//*Label 11388*/ GIMT_Encode4(719201), // Rule ID 30492 //
     /*  719156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  719159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719164 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719177 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719185 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719195 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719199 */     GIR_RootConstrainSelectedInstOperands,
     /*  719200 */     // GIR_Coverage, 30492,
     /*  719200 */     GIR_EraseRootFromParent_Done,
     /*  719201 */   // Label 11388: @719201
     /*  719201 */   GIM_Try, /*On fail goto*//*Label 11389*/ GIMT_Encode4(719251), // Rule ID 30493 //
     /*  719206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  719209 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719214 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719227 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719235 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719245 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719249 */     GIR_RootConstrainSelectedInstOperands,
     /*  719250 */     // GIR_Coverage, 30493,
     /*  719250 */     GIR_EraseRootFromParent_Done,
     /*  719251 */   // Label 11389: @719251
     /*  719251 */   GIM_Try, /*On fail goto*//*Label 11390*/ GIMT_Encode4(719301), // Rule ID 30494 //
     /*  719256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  719259 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719264 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719266 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719277 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719285 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719295 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719299 */     GIR_RootConstrainSelectedInstOperands,
     /*  719300 */     // GIR_Coverage, 30494,
     /*  719300 */     GIR_EraseRootFromParent_Done,
     /*  719301 */   // Label 11390: @719301
     /*  719301 */   GIM_Try, /*On fail goto*//*Label 11391*/ GIMT_Encode4(719351), // Rule ID 30495 //
     /*  719306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  719309 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719314 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719320 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719327 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719335 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719349 */     GIR_RootConstrainSelectedInstOperands,
     /*  719350 */     // GIR_Coverage, 30495,
     /*  719350 */     GIR_EraseRootFromParent_Done,
     /*  719351 */   // Label 11391: @719351
     /*  719351 */   GIM_Try, /*On fail goto*//*Label 11392*/ GIMT_Encode4(719401), // Rule ID 30496 //
     /*  719356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  719359 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719364 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719377 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719385 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719399 */     GIR_RootConstrainSelectedInstOperands,
     /*  719400 */     // GIR_Coverage, 30496,
     /*  719400 */     GIR_EraseRootFromParent_Done,
     /*  719401 */   // Label 11392: @719401
     /*  719401 */   GIM_Try, /*On fail goto*//*Label 11393*/ GIMT_Encode4(719451), // Rule ID 30498 //
     /*  719406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  719409 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719414 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719427 */     // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f32>>  =>  (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9),
     /*  719430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719435 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719445 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719449 */     GIR_RootConstrainSelectedInstOperands,
     /*  719450 */     // GIR_Coverage, 30498,
     /*  719450 */     GIR_EraseRootFromParent_Done,
     /*  719451 */   // Label 11393: @719451
     /*  719451 */   GIM_Try, /*On fail goto*//*Label 11394*/ GIMT_Encode4(719501), // Rule ID 30499 //
     /*  719456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  719459 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719464 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719466 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719470 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719477 */     // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f32>>  =>  (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9),
     /*  719480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719485 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719499 */     GIR_RootConstrainSelectedInstOperands,
     /*  719500 */     // GIR_Coverage, 30499,
     /*  719500 */     GIR_EraseRootFromParent_Done,
     /*  719501 */   // Label 11394: @719501
     /*  719501 */   GIM_Try, /*On fail goto*//*Label 11395*/ GIMT_Encode4(719551), // Rule ID 30500 //
     /*  719506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  719509 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719514 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719527 */     // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f32>>  =>  (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9),
     /*  719530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719535 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719545 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719549 */     GIR_RootConstrainSelectedInstOperands,
     /*  719550 */     // GIR_Coverage, 30500,
     /*  719550 */     GIR_EraseRootFromParent_Done,
     /*  719551 */   // Label 11395: @719551
     /*  719551 */   GIM_Try, /*On fail goto*//*Label 11396*/ GIMT_Encode4(719601), // Rule ID 30501 //
     /*  719556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  719559 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719564 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719577 */     // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f32>>  =>  (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9),
     /*  719580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719585 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719599 */     GIR_RootConstrainSelectedInstOperands,
     /*  719600 */     // GIR_Coverage, 30501,
     /*  719600 */     GIR_EraseRootFromParent_Done,
     /*  719601 */   // Label 11396: @719601
     /*  719601 */   GIM_Try, /*On fail goto*//*Label 11397*/ GIMT_Encode4(719651), // Rule ID 30502 //
     /*  719606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  719609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719614 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719627 */     // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f32>>  =>  (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9),
     /*  719630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719635 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719645 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719649 */     GIR_RootConstrainSelectedInstOperands,
     /*  719650 */     // GIR_Coverage, 30502,
     /*  719650 */     GIR_EraseRootFromParent_Done,
     /*  719651 */   // Label 11397: @719651
     /*  719651 */   GIM_Try, /*On fail goto*//*Label 11398*/ GIMT_Encode4(719701), // Rule ID 30504 //
     /*  719656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  719659 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  719664 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719666 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719670 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719677 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  719677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719685 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719695 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719699 */     GIR_RootConstrainSelectedInstOperands,
     /*  719700 */     // GIR_Coverage, 30504,
     /*  719700 */     GIR_EraseRootFromParent_Done,
     /*  719701 */   // Label 11398: @719701
     /*  719701 */   GIM_Try, /*On fail goto*//*Label 11399*/ GIMT_Encode4(719751), // Rule ID 30505 //
     /*  719706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  719709 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  719714 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719716 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719727 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  719727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719735 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719745 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719749 */     GIR_RootConstrainSelectedInstOperands,
     /*  719750 */     // GIR_Coverage, 30505,
     /*  719750 */     GIR_EraseRootFromParent_Done,
     /*  719751 */   // Label 11399: @719751
     /*  719751 */   GIM_Try, /*On fail goto*//*Label 11400*/ GIMT_Encode4(719801), // Rule ID 30506 //
     /*  719756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  719759 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  719764 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719777 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  719777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719785 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719799 */     GIR_RootConstrainSelectedInstOperands,
     /*  719800 */     // GIR_Coverage, 30506,
     /*  719800 */     GIR_EraseRootFromParent_Done,
     /*  719801 */   // Label 11400: @719801
     /*  719801 */   GIM_Try, /*On fail goto*//*Label 11401*/ GIMT_Encode4(719851), // Rule ID 30507 //
     /*  719806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  719809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  719814 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719816 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719820 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719827 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  719827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719835 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719845 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719849 */     GIR_RootConstrainSelectedInstOperands,
     /*  719850 */     // GIR_Coverage, 30507,
     /*  719850 */     GIR_EraseRootFromParent_Done,
     /*  719851 */   // Label 11401: @719851
     /*  719851 */   GIM_Try, /*On fail goto*//*Label 11402*/ GIMT_Encode4(719901), // Rule ID 30508 //
     /*  719856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  719859 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  719864 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  719866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719877 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  719877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
     /*  719880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719885 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  719895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719899 */     GIR_RootConstrainSelectedInstOperands,
     /*  719900 */     // GIR_Coverage, 30508,
     /*  719900 */     GIR_EraseRootFromParent_Done,
     /*  719901 */   // Label 11402: @719901
     /*  719901 */   GIM_Try, /*On fail goto*//*Label 11403*/ GIMT_Encode4(719955), // Rule ID 30491 //
     /*  719906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  719909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  719918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719929 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f32>>  =>  (DS_MAX_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32),
     /*  719932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  719934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719939 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  719946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  719949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  719953 */     GIR_RootConstrainSelectedInstOperands,
     /*  719954 */     // GIR_Coverage, 30491,
     /*  719954 */     GIR_EraseRootFromParent_Done,
     /*  719955 */   // Label 11403: @719955
     /*  719955 */   GIM_Try, /*On fail goto*//*Label 11404*/ GIMT_Encode4(720009), // Rule ID 30497 //
     /*  719960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  719963 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  719968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  719972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  719976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  719983 */     // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_f32>>  =>  (DS_MAX_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  719983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32_gfx9),
     /*  719986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  719988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  719993 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  719995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  720003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720007 */     GIR_RootConstrainSelectedInstOperands,
     /*  720008 */     // GIR_Coverage, 30497,
     /*  720008 */     GIR_EraseRootFromParent_Done,
     /*  720009 */   // Label 11404: @720009
     /*  720009 */   GIM_Try, /*On fail goto*//*Label 11405*/ GIMT_Encode4(720063), // Rule ID 30503 //
     /*  720014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  720017 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  720022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720026 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720030 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  720037 */     // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f32>>  =>  (DS_MAX_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  720037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32),
     /*  720040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  720047 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  720049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  720057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720061 */     GIR_RootConstrainSelectedInstOperands,
     /*  720062 */     // GIR_Coverage, 30503,
     /*  720062 */     GIR_EraseRootFromParent_Done,
     /*  720063 */   // Label 11405: @720063
     /*  720063 */   GIM_Try, /*On fail goto*//*Label 11406*/ GIMT_Encode4(720122), // Rule ID 13584 //
     /*  720068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode0),
     /*  720071 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720078 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  720091 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  720094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720099 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  720106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  720111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  720116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720120 */     GIR_RootConstrainSelectedInstOperands,
     /*  720121 */     // GIR_Coverage, 13584,
     /*  720121 */     GIR_EraseRootFromParent_Done,
     /*  720122 */   // Label 11406: @720122
     /*  720122 */   GIM_Try, /*On fail goto*//*Label 11407*/ GIMT_Encode4(720181), // Rule ID 13585 //
     /*  720127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode1),
     /*  720130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720137 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720139 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  720150 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  720153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720158 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  720165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  720170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  720175 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720179 */     GIR_RootConstrainSelectedInstOperands,
     /*  720180 */     // GIR_Coverage, 13585,
     /*  720180 */     GIR_EraseRootFromParent_Done,
     /*  720181 */   // Label 11407: @720181
     /*  720181 */   GIM_Try, /*On fail goto*//*Label 11408*/ GIMT_Encode4(720240), // Rule ID 13586 //
     /*  720186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode2),
     /*  720189 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720196 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720202 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  720209 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  720212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720217 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  720224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  720229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  720234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720238 */     GIR_RootConstrainSelectedInstOperands,
     /*  720239 */     // GIR_Coverage, 13586,
     /*  720239 */     GIR_EraseRootFromParent_Done,
     /*  720240 */   // Label 11408: @720240
     /*  720240 */   GIM_Try, /*On fail goto*//*Label 11409*/ GIMT_Encode4(720299), // Rule ID 13587 //
     /*  720245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode3),
     /*  720248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720255 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  720268 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  720271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720276 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  720283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  720288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  720293 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720297 */     GIR_RootConstrainSelectedInstOperands,
     /*  720298 */     // GIR_Coverage, 13587,
     /*  720298 */     GIR_EraseRootFromParent_Done,
     /*  720299 */   // Label 11409: @720299
     /*  720299 */   GIM_Try, /*On fail goto*//*Label 11410*/ GIMT_Encode4(720358), // Rule ID 13588 //
     /*  720304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode4),
     /*  720307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720314 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720320 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  720327 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  720330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720335 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  720342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  720347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  720352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720356 */     GIR_RootConstrainSelectedInstOperands,
     /*  720357 */     // GIR_Coverage, 13588,
     /*  720357 */     GIR_EraseRootFromParent_Done,
     /*  720358 */   // Label 11410: @720358
     /*  720358 */   GIM_Try, /*On fail goto*//*Label 11411*/ GIMT_Encode4(720421), // Rule ID 13594 //
     /*  720363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  720366 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  720388 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN),
     /*  720391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720398 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  720405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  720410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  720415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720419 */     GIR_RootConstrainSelectedInstOperands,
     /*  720420 */     // GIR_Coverage, 13594,
     /*  720420 */     GIR_EraseRootFromParent_Done,
     /*  720421 */   // Label 11411: @720421
     /*  720421 */   GIM_Try, /*On fail goto*//*Label 11412*/ GIMT_Encode4(720473), // Rule ID 13579 //
     /*  720426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode0),
     /*  720429 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720436 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720449 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  720452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720457 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  720467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720471 */     GIR_RootConstrainSelectedInstOperands,
     /*  720472 */     // GIR_Coverage, 13579,
     /*  720472 */     GIR_EraseRootFromParent_Done,
     /*  720473 */   // Label 11412: @720473
     /*  720473 */   GIM_Try, /*On fail goto*//*Label 11413*/ GIMT_Encode4(720525), // Rule ID 13580 //
     /*  720478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode1),
     /*  720481 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720488 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720501 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  720504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720509 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  720519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720523 */     GIR_RootConstrainSelectedInstOperands,
     /*  720524 */     // GIR_Coverage, 13580,
     /*  720524 */     GIR_EraseRootFromParent_Done,
     /*  720525 */   // Label 11413: @720525
     /*  720525 */   GIM_Try, /*On fail goto*//*Label 11414*/ GIMT_Encode4(720577), // Rule ID 13581 //
     /*  720530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode2),
     /*  720533 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720540 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720553 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  720556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720561 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  720571 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720575 */     GIR_RootConstrainSelectedInstOperands,
     /*  720576 */     // GIR_Coverage, 13581,
     /*  720576 */     GIR_EraseRootFromParent_Done,
     /*  720577 */   // Label 11414: @720577
     /*  720577 */   GIM_Try, /*On fail goto*//*Label 11415*/ GIMT_Encode4(720629), // Rule ID 13582 //
     /*  720582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode3),
     /*  720585 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720592 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720605 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  720608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720613 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  720623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720627 */     GIR_RootConstrainSelectedInstOperands,
     /*  720628 */     // GIR_Coverage, 13582,
     /*  720628 */     GIR_EraseRootFromParent_Done,
     /*  720629 */   // Label 11415: @720629
     /*  720629 */   GIM_Try, /*On fail goto*//*Label 11416*/ GIMT_Encode4(720681), // Rule ID 13583 //
     /*  720634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode4),
     /*  720637 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720644 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720657 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  720660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720665 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  720675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720679 */     GIR_RootConstrainSelectedInstOperands,
     /*  720680 */     // GIR_Coverage, 13583,
     /*  720680 */     GIR_EraseRootFromParent_Done,
     /*  720681 */   // Label 11416: @720681
     /*  720681 */   GIM_Try, /*On fail goto*//*Label 11417*/ GIMT_Encode4(720737), // Rule ID 13589 //
     /*  720686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode0),
     /*  720689 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720700 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720711 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  720714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720721 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  720731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720735 */     GIR_RootConstrainSelectedInstOperands,
     /*  720736 */     // GIR_Coverage, 13589,
     /*  720736 */     GIR_EraseRootFromParent_Done,
     /*  720737 */   // Label 11417: @720737
     /*  720737 */   GIM_Try, /*On fail goto*//*Label 11418*/ GIMT_Encode4(720793), // Rule ID 13590 //
     /*  720742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode1),
     /*  720745 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720756 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720760 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720767 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  720770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720777 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  720787 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720791 */     GIR_RootConstrainSelectedInstOperands,
     /*  720792 */     // GIR_Coverage, 13590,
     /*  720792 */     GIR_EraseRootFromParent_Done,
     /*  720793 */   // Label 11418: @720793
     /*  720793 */   GIM_Try, /*On fail goto*//*Label 11419*/ GIMT_Encode4(720849), // Rule ID 13591 //
     /*  720798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode2),
     /*  720801 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720816 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720823 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  720826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720833 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  720843 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720847 */     GIR_RootConstrainSelectedInstOperands,
     /*  720848 */     // GIR_Coverage, 13591,
     /*  720848 */     GIR_EraseRootFromParent_Done,
     /*  720849 */   // Label 11419: @720849
     /*  720849 */   GIM_Try, /*On fail goto*//*Label 11420*/ GIMT_Encode4(720905), // Rule ID 13592 //
     /*  720854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode3),
     /*  720857 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720879 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  720882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720889 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  720899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720903 */     GIR_RootConstrainSelectedInstOperands,
     /*  720904 */     // GIR_Coverage, 13592,
     /*  720904 */     GIR_EraseRootFromParent_Done,
     /*  720905 */   // Label 11420: @720905
     /*  720905 */   GIM_Try, /*On fail goto*//*Label 11421*/ GIMT_Encode4(720961), // Rule ID 13593 //
     /*  720910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode4),
     /*  720913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  720924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  720935 */     // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  720935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  720938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  720940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  720945 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  720947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  720952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  720955 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  720959 */     GIR_RootConstrainSelectedInstOperands,
     /*  720960 */     // GIR_Coverage, 13593,
     /*  720960 */     GIR_EraseRootFromParent_Done,
     /*  720961 */   // Label 11421: @720961
     /*  720961 */   GIM_Try, /*On fail goto*//*Label 11422*/ GIMT_Encode4(721021), // Rule ID 10969 //
     /*  720966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode0),
     /*  720969 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  720977 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  720979 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  720983 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  720990 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  720990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  720993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  720998 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721015 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721019 */     GIR_RootConstrainSelectedInstOperands,
     /*  721020 */     // GIR_Coverage, 10969,
     /*  721020 */     GIR_EraseRootFromParent_Done,
     /*  721021 */   // Label 11422: @721021
     /*  721021 */   GIM_Try, /*On fail goto*//*Label 11423*/ GIMT_Encode4(721081), // Rule ID 10970 //
     /*  721026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode1),
     /*  721029 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721037 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721050 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721058 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721079 */     GIR_RootConstrainSelectedInstOperands,
     /*  721080 */     // GIR_Coverage, 10970,
     /*  721080 */     GIR_EraseRootFromParent_Done,
     /*  721081 */   // Label 11423: @721081
     /*  721081 */   GIM_Try, /*On fail goto*//*Label 11424*/ GIMT_Encode4(721141), // Rule ID 10971 //
     /*  721086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode2),
     /*  721089 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721097 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721110 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721118 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721139 */     GIR_RootConstrainSelectedInstOperands,
     /*  721140 */     // GIR_Coverage, 10971,
     /*  721140 */     GIR_EraseRootFromParent_Done,
     /*  721141 */   // Label 11424: @721141
     /*  721141 */   GIM_Try, /*On fail goto*//*Label 11425*/ GIMT_Encode4(721201), // Rule ID 10972 //
     /*  721146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode3),
     /*  721149 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721157 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721159 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721163 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721170 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721178 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721195 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721199 */     GIR_RootConstrainSelectedInstOperands,
     /*  721200 */     // GIR_Coverage, 10972,
     /*  721200 */     GIR_EraseRootFromParent_Done,
     /*  721201 */   // Label 11425: @721201
     /*  721201 */   GIM_Try, /*On fail goto*//*Label 11426*/ GIMT_Encode4(721261), // Rule ID 10973 //
     /*  721206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode4),
     /*  721209 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721217 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721223 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721230 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721238 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721259 */     GIR_RootConstrainSelectedInstOperands,
     /*  721260 */     // GIR_Coverage, 10973,
     /*  721260 */     GIR_EraseRootFromParent_Done,
     /*  721261 */   // Label 11426: @721261
     /*  721261 */   GIM_Try, /*On fail goto*//*Label 11427*/ GIMT_Encode4(721320), // Rule ID 11525 //
     /*  721266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode0),
     /*  721269 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721276 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721289 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721297 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721318 */     GIR_RootConstrainSelectedInstOperands,
     /*  721319 */     // GIR_Coverage, 11525,
     /*  721319 */     GIR_EraseRootFromParent_Done,
     /*  721320 */   // Label 11427: @721320
     /*  721320 */   GIM_Try, /*On fail goto*//*Label 11428*/ GIMT_Encode4(721379), // Rule ID 11526 //
     /*  721325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode1),
     /*  721328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721335 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721348 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721356 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721377 */     GIR_RootConstrainSelectedInstOperands,
     /*  721378 */     // GIR_Coverage, 11526,
     /*  721378 */     GIR_EraseRootFromParent_Done,
     /*  721379 */   // Label 11428: @721379
     /*  721379 */   GIM_Try, /*On fail goto*//*Label 11429*/ GIMT_Encode4(721438), // Rule ID 11527 //
     /*  721384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode2),
     /*  721387 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721394 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721407 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721415 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721436 */     GIR_RootConstrainSelectedInstOperands,
     /*  721437 */     // GIR_Coverage, 11527,
     /*  721437 */     GIR_EraseRootFromParent_Done,
     /*  721438 */   // Label 11429: @721438
     /*  721438 */   GIM_Try, /*On fail goto*//*Label 11430*/ GIMT_Encode4(721497), // Rule ID 11528 //
     /*  721443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode3),
     /*  721446 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721453 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721466 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721474 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721495 */     GIR_RootConstrainSelectedInstOperands,
     /*  721496 */     // GIR_Coverage, 11528,
     /*  721496 */     GIR_EraseRootFromParent_Done,
     /*  721497 */   // Label 11430: @721497
     /*  721497 */   GIM_Try, /*On fail goto*//*Label 11431*/ GIMT_Encode4(721556), // Rule ID 11529 //
     /*  721502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode4),
     /*  721505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721512 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721525 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721533 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721550 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721554 */     GIR_RootConstrainSelectedInstOperands,
     /*  721555 */     // GIR_Coverage, 11529,
     /*  721555 */     GIR_EraseRootFromParent_Done,
     /*  721556 */   // Label 11431: @721556
     /*  721556 */   GIM_Try, /*On fail goto*//*Label 11432*/ GIMT_Encode4(721616), // Rule ID 13622 //
     /*  721561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode0),
     /*  721564 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721572 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721574 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721578 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721585 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721593 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721614 */     GIR_RootConstrainSelectedInstOperands,
     /*  721615 */     // GIR_Coverage, 13622,
     /*  721615 */     GIR_EraseRootFromParent_Done,
     /*  721616 */   // Label 11432: @721616
     /*  721616 */   GIM_Try, /*On fail goto*//*Label 11433*/ GIMT_Encode4(721676), // Rule ID 13623 //
     /*  721621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode1),
     /*  721624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721632 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721638 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721645 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721653 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721674 */     GIR_RootConstrainSelectedInstOperands,
     /*  721675 */     // GIR_Coverage, 13623,
     /*  721675 */     GIR_EraseRootFromParent_Done,
     /*  721676 */   // Label 11433: @721676
     /*  721676 */   GIM_Try, /*On fail goto*//*Label 11434*/ GIMT_Encode4(721736), // Rule ID 13624 //
     /*  721681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode2),
     /*  721684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721692 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721705 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721713 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721734 */     GIR_RootConstrainSelectedInstOperands,
     /*  721735 */     // GIR_Coverage, 13624,
     /*  721735 */     GIR_EraseRootFromParent_Done,
     /*  721736 */   // Label 11434: @721736
     /*  721736 */   GIM_Try, /*On fail goto*//*Label 11435*/ GIMT_Encode4(721796), // Rule ID 13625 //
     /*  721741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode3),
     /*  721744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721752 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721754 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721758 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721765 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721773 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721794 */     GIR_RootConstrainSelectedInstOperands,
     /*  721795 */     // GIR_Coverage, 13625,
     /*  721795 */     GIR_EraseRootFromParent_Done,
     /*  721796 */   // Label 11435: @721796
     /*  721796 */   GIM_Try, /*On fail goto*//*Label 11436*/ GIMT_Encode4(721856), // Rule ID 13626 //
     /*  721801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode4),
     /*  721804 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721812 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  721814 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721818 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  721825 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  721828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721833 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721854 */     GIR_RootConstrainSelectedInstOperands,
     /*  721855 */     // GIR_Coverage, 13626,
     /*  721855 */     GIR_EraseRootFromParent_Done,
     /*  721856 */   // Label 11436: @721856
     /*  721856 */   GIM_Try, /*On fail goto*//*Label 11437*/ GIMT_Encode4(721920), // Rule ID 10963 //
     /*  721861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode),
     /*  721864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  721876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  721887 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR_RTN),
     /*  721890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  721892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721897 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721918 */     GIR_RootConstrainSelectedInstOperands,
     /*  721919 */     // GIR_Coverage, 10963,
     /*  721919 */     GIR_EraseRootFromParent_Done,
     /*  721920 */   // Label 11437: @721920
     /*  721920 */   GIM_Try, /*On fail goto*//*Label 11438*/ GIMT_Encode4(721983), // Rule ID 11519 //
     /*  721925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode),
     /*  721928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  721939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  721943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  721950 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  721950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR_RTN),
     /*  721953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  721955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  721960 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  721962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  721967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  721972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  721977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  721981 */     GIR_RootConstrainSelectedInstOperands,
     /*  721982 */     // GIR_Coverage, 11519,
     /*  721982 */     GIR_EraseRootFromParent_Done,
     /*  721983 */   // Label 11438: @721983
     /*  721983 */   GIM_Try, /*On fail goto*//*Label 11439*/ GIMT_Encode4(722047), // Rule ID 13616 //
     /*  721988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11),
     /*  721991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  721999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  722003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  722014 */     // (atomic_load_fmax:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  722014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR_RTN),
     /*  722017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  722019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  722024 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  722031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  722036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  722041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722045 */     GIR_RootConstrainSelectedInstOperands,
     /*  722046 */     // GIR_Coverage, 13616,
     /*  722046 */     GIR_EraseRootFromParent_Done,
     /*  722047 */   // Label 11439: @722047
     /*  722047 */   GIM_Try, /*On fail goto*//*Label 11440*/ GIMT_Encode4(722100), // Rule ID 10964 //
     /*  722052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  722055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722063 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722076 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722084 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722098 */     GIR_RootConstrainSelectedInstOperands,
     /*  722099 */     // GIR_Coverage, 10964,
     /*  722099 */     GIR_EraseRootFromParent_Done,
     /*  722100 */   // Label 11440: @722100
     /*  722100 */   GIM_Try, /*On fail goto*//*Label 11441*/ GIMT_Encode4(722153), // Rule ID 10965 //
     /*  722105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  722108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722116 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722118 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722122 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722129 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722137 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722151 */     GIR_RootConstrainSelectedInstOperands,
     /*  722152 */     // GIR_Coverage, 10965,
     /*  722152 */     GIR_EraseRootFromParent_Done,
     /*  722153 */   // Label 11441: @722153
     /*  722153 */   GIM_Try, /*On fail goto*//*Label 11442*/ GIMT_Encode4(722206), // Rule ID 10966 //
     /*  722158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  722161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722169 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722182 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722190 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722204 */     GIR_RootConstrainSelectedInstOperands,
     /*  722205 */     // GIR_Coverage, 10966,
     /*  722205 */     GIR_EraseRootFromParent_Done,
     /*  722206 */   // Label 11442: @722206
     /*  722206 */   GIM_Try, /*On fail goto*//*Label 11443*/ GIMT_Encode4(722259), // Rule ID 10967 //
     /*  722211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  722214 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722222 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722235 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722243 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722253 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722257 */     GIR_RootConstrainSelectedInstOperands,
     /*  722258 */     // GIR_Coverage, 10967,
     /*  722258 */     GIR_EraseRootFromParent_Done,
     /*  722259 */   // Label 11443: @722259
     /*  722259 */   GIM_Try, /*On fail goto*//*Label 11444*/ GIMT_Encode4(722312), // Rule ID 10968 //
     /*  722264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  722267 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722275 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722277 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722288 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722296 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722306 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722310 */     GIR_RootConstrainSelectedInstOperands,
     /*  722311 */     // GIR_Coverage, 10968,
     /*  722311 */     GIR_EraseRootFromParent_Done,
     /*  722312 */   // Label 11444: @722312
     /*  722312 */   GIM_Try, /*On fail goto*//*Label 11445*/ GIMT_Encode4(722364), // Rule ID 11520 //
     /*  722317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  722320 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722327 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722329 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722340 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722348 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722362 */     GIR_RootConstrainSelectedInstOperands,
     /*  722363 */     // GIR_Coverage, 11520,
     /*  722363 */     GIR_EraseRootFromParent_Done,
     /*  722364 */   // Label 11445: @722364
     /*  722364 */   GIM_Try, /*On fail goto*//*Label 11446*/ GIMT_Encode4(722416), // Rule ID 11521 //
     /*  722369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  722372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722392 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722414 */     GIR_RootConstrainSelectedInstOperands,
     /*  722415 */     // GIR_Coverage, 11521,
     /*  722415 */     GIR_EraseRootFromParent_Done,
     /*  722416 */   // Label 11446: @722416
     /*  722416 */   GIM_Try, /*On fail goto*//*Label 11447*/ GIMT_Encode4(722468), // Rule ID 11522 //
     /*  722421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  722424 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722431 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722433 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722444 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722452 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722466 */     GIR_RootConstrainSelectedInstOperands,
     /*  722467 */     // GIR_Coverage, 11522,
     /*  722467 */     GIR_EraseRootFromParent_Done,
     /*  722468 */   // Label 11447: @722468
     /*  722468 */   GIM_Try, /*On fail goto*//*Label 11448*/ GIMT_Encode4(722520), // Rule ID 11523 //
     /*  722473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  722476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722483 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722496 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722504 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722518 */     GIR_RootConstrainSelectedInstOperands,
     /*  722519 */     // GIR_Coverage, 11523,
     /*  722519 */     GIR_EraseRootFromParent_Done,
     /*  722520 */   // Label 11448: @722520
     /*  722520 */   GIM_Try, /*On fail goto*//*Label 11449*/ GIMT_Encode4(722572), // Rule ID 11524 //
     /*  722525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  722528 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722535 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722537 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722541 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722548 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722556 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722566 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722570 */     GIR_RootConstrainSelectedInstOperands,
     /*  722571 */     // GIR_Coverage, 11524,
     /*  722571 */     GIR_EraseRootFromParent_Done,
     /*  722572 */   // Label 11449: @722572
     /*  722572 */   GIM_Try, /*On fail goto*//*Label 11450*/ GIMT_Encode4(722625), // Rule ID 13617 //
     /*  722577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode0),
     /*  722580 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722588 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722601 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722609 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722619 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722623 */     GIR_RootConstrainSelectedInstOperands,
     /*  722624 */     // GIR_Coverage, 13617,
     /*  722624 */     GIR_EraseRootFromParent_Done,
     /*  722625 */   // Label 11450: @722625
     /*  722625 */   GIM_Try, /*On fail goto*//*Label 11451*/ GIMT_Encode4(722678), // Rule ID 13618 //
     /*  722630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode1),
     /*  722633 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722641 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722654 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722662 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722672 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722676 */     GIR_RootConstrainSelectedInstOperands,
     /*  722677 */     // GIR_Coverage, 13618,
     /*  722677 */     GIR_EraseRootFromParent_Done,
     /*  722678 */   // Label 11451: @722678
     /*  722678 */   GIM_Try, /*On fail goto*//*Label 11452*/ GIMT_Encode4(722731), // Rule ID 13619 //
     /*  722683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode2),
     /*  722686 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722694 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722707 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722715 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722729 */     GIR_RootConstrainSelectedInstOperands,
     /*  722730 */     // GIR_Coverage, 13619,
     /*  722730 */     GIR_EraseRootFromParent_Done,
     /*  722731 */   // Label 11452: @722731
     /*  722731 */   GIM_Try, /*On fail goto*//*Label 11453*/ GIMT_Encode4(722784), // Rule ID 13620 //
     /*  722736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode3),
     /*  722739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722747 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722749 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722760 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722768 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722782 */     GIR_RootConstrainSelectedInstOperands,
     /*  722783 */     // GIR_Coverage, 13620,
     /*  722783 */     GIR_EraseRootFromParent_Done,
     /*  722784 */   // Label 11453: @722784
     /*  722784 */   GIM_Try, /*On fail goto*//*Label 11454*/ GIMT_Encode4(722837), // Rule ID 13621 //
     /*  722789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode4),
     /*  722792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722800 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  722802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722813 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  722816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722821 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  722831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722835 */     GIR_RootConstrainSelectedInstOperands,
     /*  722836 */     // GIR_Coverage, 13621,
     /*  722836 */     GIR_EraseRootFromParent_Done,
     /*  722837 */   // Label 11454: @722837
     /*  722837 */   GIM_Try, /*On fail goto*//*Label 11455*/ GIMT_Encode4(722894), // Rule ID 10958 //
     /*  722842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  722845 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  722857 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722861 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722868 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  722871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  722873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722878 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  722888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722892 */     GIR_RootConstrainSelectedInstOperands,
     /*  722893 */     // GIR_Coverage, 10958,
     /*  722893 */     GIR_EraseRootFromParent_Done,
     /*  722894 */   // Label 11455: @722894
     /*  722894 */   GIM_Try, /*On fail goto*//*Label 11456*/ GIMT_Encode4(722951), // Rule ID 10959 //
     /*  722899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  722902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  722914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722918 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722925 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  722928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  722930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722935 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  722945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  722949 */     GIR_RootConstrainSelectedInstOperands,
     /*  722950 */     // GIR_Coverage, 10959,
     /*  722950 */     GIR_EraseRootFromParent_Done,
     /*  722951 */   // Label 11456: @722951
     /*  722951 */   GIM_Try, /*On fail goto*//*Label 11457*/ GIMT_Encode4(723008), // Rule ID 10960 //
     /*  722956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  722959 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  722967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  722971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  722975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  722982 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  722982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  722985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  722987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  722992 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  722994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  722999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723006 */     GIR_RootConstrainSelectedInstOperands,
     /*  723007 */     // GIR_Coverage, 10960,
     /*  723007 */     GIR_EraseRootFromParent_Done,
     /*  723008 */   // Label 11457: @723008
     /*  723008 */   GIM_Try, /*On fail goto*//*Label 11458*/ GIMT_Encode4(723065), // Rule ID 10961 //
     /*  723013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  723016 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723028 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723032 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723039 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723049 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723063 */     GIR_RootConstrainSelectedInstOperands,
     /*  723064 */     // GIR_Coverage, 10961,
     /*  723064 */     GIR_EraseRootFromParent_Done,
     /*  723065 */   // Label 11458: @723065
     /*  723065 */   GIM_Try, /*On fail goto*//*Label 11459*/ GIMT_Encode4(723122), // Rule ID 10962 //
     /*  723070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  723073 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723085 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723096 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723106 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723120 */     GIR_RootConstrainSelectedInstOperands,
     /*  723121 */     // GIR_Coverage, 10962,
     /*  723121 */     GIR_EraseRootFromParent_Done,
     /*  723122 */   // Label 11459: @723122
     /*  723122 */   GIM_Try, /*On fail goto*//*Label 11460*/ GIMT_Encode4(723178), // Rule ID 11514 //
     /*  723127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  723130 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723152 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723162 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723172 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723176 */     GIR_RootConstrainSelectedInstOperands,
     /*  723177 */     // GIR_Coverage, 11514,
     /*  723177 */     GIR_EraseRootFromParent_Done,
     /*  723178 */   // Label 11460: @723178
     /*  723178 */   GIM_Try, /*On fail goto*//*Label 11461*/ GIMT_Encode4(723234), // Rule ID 11515 //
     /*  723183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  723186 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723197 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723208 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723218 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723232 */     GIR_RootConstrainSelectedInstOperands,
     /*  723233 */     // GIR_Coverage, 11515,
     /*  723233 */     GIR_EraseRootFromParent_Done,
     /*  723234 */   // Label 11461: @723234
     /*  723234 */   GIM_Try, /*On fail goto*//*Label 11462*/ GIMT_Encode4(723290), // Rule ID 11516 //
     /*  723239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  723242 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723264 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723274 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723281 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723288 */     GIR_RootConstrainSelectedInstOperands,
     /*  723289 */     // GIR_Coverage, 11516,
     /*  723289 */     GIR_EraseRootFromParent_Done,
     /*  723290 */   // Label 11462: @723290
     /*  723290 */   GIM_Try, /*On fail goto*//*Label 11463*/ GIMT_Encode4(723346), // Rule ID 11517 //
     /*  723295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  723298 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723309 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723320 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723330 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723340 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723344 */     GIR_RootConstrainSelectedInstOperands,
     /*  723345 */     // GIR_Coverage, 11517,
     /*  723345 */     GIR_EraseRootFromParent_Done,
     /*  723346 */   // Label 11463: @723346
     /*  723346 */   GIM_Try, /*On fail goto*//*Label 11464*/ GIMT_Encode4(723402), // Rule ID 11518 //
     /*  723351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  723354 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723376 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723386 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723400 */     GIR_RootConstrainSelectedInstOperands,
     /*  723401 */     // GIR_Coverage, 11518,
     /*  723401 */     GIR_EraseRootFromParent_Done,
     /*  723402 */   // Label 11464: @723402
     /*  723402 */   GIM_Try, /*On fail goto*//*Label 11465*/ GIMT_Encode4(723459), // Rule ID 13611 //
     /*  723407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode0),
     /*  723410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723433 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723443 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723457 */     GIR_RootConstrainSelectedInstOperands,
     /*  723458 */     // GIR_Coverage, 13611,
     /*  723458 */     GIR_EraseRootFromParent_Done,
     /*  723459 */   // Label 11465: @723459
     /*  723459 */   GIM_Try, /*On fail goto*//*Label 11466*/ GIMT_Encode4(723516), // Rule ID 13612 //
     /*  723464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode1),
     /*  723467 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723490 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723500 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723514 */     GIR_RootConstrainSelectedInstOperands,
     /*  723515 */     // GIR_Coverage, 13612,
     /*  723515 */     GIR_EraseRootFromParent_Done,
     /*  723516 */   // Label 11466: @723516
     /*  723516 */   GIM_Try, /*On fail goto*//*Label 11467*/ GIMT_Encode4(723573), // Rule ID 13613 //
     /*  723521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode2),
     /*  723524 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723547 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723557 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723567 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723571 */     GIR_RootConstrainSelectedInstOperands,
     /*  723572 */     // GIR_Coverage, 13613,
     /*  723572 */     GIR_EraseRootFromParent_Done,
     /*  723573 */   // Label 11467: @723573
     /*  723573 */   GIM_Try, /*On fail goto*//*Label 11468*/ GIMT_Encode4(723630), // Rule ID 13614 //
     /*  723578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode3),
     /*  723581 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723593 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723604 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723614 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723624 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723628 */     GIR_RootConstrainSelectedInstOperands,
     /*  723629 */     // GIR_Coverage, 13614,
     /*  723629 */     GIR_EraseRootFromParent_Done,
     /*  723630 */   // Label 11468: @723630
     /*  723630 */   GIM_Try, /*On fail goto*//*Label 11469*/ GIMT_Encode4(723687), // Rule ID 13615 //
     /*  723635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode4),
     /*  723638 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  723650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  723661 */     // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  723661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  723664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  723666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  723671 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  723673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  723678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  723681 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723685 */     GIR_RootConstrainSelectedInstOperands,
     /*  723686 */     // GIR_Coverage, 13615,
     /*  723686 */     GIR_EraseRootFromParent_Done,
     /*  723687 */   // Label 11469: @723687
     /*  723687 */   GIM_Reject,
     /*  723688 */ // Label 11347: @723688
     /*  723688 */ GIM_Reject,
     /*  723689 */ // Label 11345: @723689
     /*  723689 */ GIM_Try, /*On fail goto*//*Label 11470*/ GIMT_Encode4(731188),
     /*  723694 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  723697 */   GIM_Try, /*On fail goto*//*Label 11471*/ GIMT_Encode4(723759), // Rule ID 21818 //
     /*  723702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  723705 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723712 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  723714 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723718 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  723725 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  723725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64),
     /*  723728 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  723730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  723735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  723740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  723745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  723750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  723753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723757 */     GIR_RootConstrainSelectedInstOperands,
     /*  723758 */     // GIR_Coverage, 21818,
     /*  723758 */     GIR_EraseRootFromParent_Done,
     /*  723759 */   // Label 11471: @723759
     /*  723759 */   GIM_Try, /*On fail goto*//*Label 11472*/ GIMT_Encode4(723821), // Rule ID 21819 //
     /*  723764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  723767 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723774 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  723776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  723787 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  723787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64),
     /*  723790 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  723792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  723797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  723802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  723807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  723812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  723815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723819 */     GIR_RootConstrainSelectedInstOperands,
     /*  723820 */     // GIR_Coverage, 21819,
     /*  723820 */     GIR_EraseRootFromParent_Done,
     /*  723821 */   // Label 11472: @723821
     /*  723821 */   GIM_Try, /*On fail goto*//*Label 11473*/ GIMT_Encode4(723883), // Rule ID 21820 //
     /*  723826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  723829 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723836 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  723838 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  723849 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  723849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64),
     /*  723852 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  723854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  723859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  723864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  723869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  723874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  723877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723881 */     GIR_RootConstrainSelectedInstOperands,
     /*  723882 */     // GIR_Coverage, 21820,
     /*  723882 */     GIR_EraseRootFromParent_Done,
     /*  723883 */   // Label 11473: @723883
     /*  723883 */   GIM_Try, /*On fail goto*//*Label 11474*/ GIMT_Encode4(723945), // Rule ID 21821 //
     /*  723888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  723891 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723898 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  723900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  723911 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  723911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64),
     /*  723914 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  723916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  723921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  723926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  723931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  723936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  723939 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  723943 */     GIR_RootConstrainSelectedInstOperands,
     /*  723944 */     // GIR_Coverage, 21821,
     /*  723944 */     GIR_EraseRootFromParent_Done,
     /*  723945 */   // Label 11474: @723945
     /*  723945 */   GIM_Try, /*On fail goto*//*Label 11475*/ GIMT_Encode4(724007), // Rule ID 21822 //
     /*  723950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  723953 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  723960 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  723962 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  723966 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  723973 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  723973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64),
     /*  723976 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  723978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  723983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  723988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  723993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  723998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  724001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724005 */     GIR_RootConstrainSelectedInstOperands,
     /*  724006 */     // GIR_Coverage, 21822,
     /*  724006 */     GIR_EraseRootFromParent_Done,
     /*  724007 */   // Label 11475: @724007
     /*  724007 */   GIM_Try, /*On fail goto*//*Label 11476*/ GIMT_Encode4(724069), // Rule ID 21838 //
     /*  724012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  724015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724022 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  724024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724035 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64),
     /*  724038 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  724063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724067 */     GIR_RootConstrainSelectedInstOperands,
     /*  724068 */     // GIR_Coverage, 21838,
     /*  724068 */     GIR_EraseRootFromParent_Done,
     /*  724069 */   // Label 11476: @724069
     /*  724069 */   GIM_Try, /*On fail goto*//*Label 11477*/ GIMT_Encode4(724131), // Rule ID 21839 //
     /*  724074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  724077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724084 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  724086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724097 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64),
     /*  724100 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  724125 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724129 */     GIR_RootConstrainSelectedInstOperands,
     /*  724130 */     // GIR_Coverage, 21839,
     /*  724130 */     GIR_EraseRootFromParent_Done,
     /*  724131 */   // Label 11477: @724131
     /*  724131 */   GIM_Try, /*On fail goto*//*Label 11478*/ GIMT_Encode4(724193), // Rule ID 21840 //
     /*  724136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  724139 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724146 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  724148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724152 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724159 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64),
     /*  724162 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  724187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724191 */     GIR_RootConstrainSelectedInstOperands,
     /*  724192 */     // GIR_Coverage, 21840,
     /*  724192 */     GIR_EraseRootFromParent_Done,
     /*  724193 */   // Label 11478: @724193
     /*  724193 */   GIM_Try, /*On fail goto*//*Label 11479*/ GIMT_Encode4(724255), // Rule ID 21841 //
     /*  724198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  724201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724208 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  724210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724221 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64),
     /*  724224 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  724249 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724253 */     GIR_RootConstrainSelectedInstOperands,
     /*  724254 */     // GIR_Coverage, 21841,
     /*  724254 */     GIR_EraseRootFromParent_Done,
     /*  724255 */   // Label 11479: @724255
     /*  724255 */   GIM_Try, /*On fail goto*//*Label 11480*/ GIMT_Encode4(724317), // Rule ID 21842 //
     /*  724260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  724263 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724270 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  724272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724283 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64),
     /*  724286 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  724311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724315 */     GIR_RootConstrainSelectedInstOperands,
     /*  724316 */     // GIR_Coverage, 21842,
     /*  724316 */     GIR_EraseRootFromParent_Done,
     /*  724317 */   // Label 11480: @724317
     /*  724317 */   GIM_Try, /*On fail goto*//*Label 11481*/ GIMT_Encode4(724383), // Rule ID 21808 //
     /*  724322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  724325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724347 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64_RTN),
     /*  724350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724352 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724381 */     GIR_RootConstrainSelectedInstOperands,
     /*  724382 */     // GIR_Coverage, 21808,
     /*  724382 */     GIR_EraseRootFromParent_Done,
     /*  724383 */   // Label 11481: @724383
     /*  724383 */   GIM_Try, /*On fail goto*//*Label 11482*/ GIMT_Encode4(724449), // Rule ID 21809 //
     /*  724388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  724391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724413 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64_RTN),
     /*  724416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724418 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724447 */     GIR_RootConstrainSelectedInstOperands,
     /*  724448 */     // GIR_Coverage, 21809,
     /*  724448 */     GIR_EraseRootFromParent_Done,
     /*  724449 */   // Label 11482: @724449
     /*  724449 */   GIM_Try, /*On fail goto*//*Label 11483*/ GIMT_Encode4(724515), // Rule ID 21810 //
     /*  724454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  724457 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724479 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64_RTN),
     /*  724482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724484 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724513 */     GIR_RootConstrainSelectedInstOperands,
     /*  724514 */     // GIR_Coverage, 21810,
     /*  724514 */     GIR_EraseRootFromParent_Done,
     /*  724515 */   // Label 11483: @724515
     /*  724515 */   GIM_Try, /*On fail goto*//*Label 11484*/ GIMT_Encode4(724581), // Rule ID 21811 //
     /*  724520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  724523 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724545 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64_RTN),
     /*  724548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724550 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724575 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724579 */     GIR_RootConstrainSelectedInstOperands,
     /*  724580 */     // GIR_Coverage, 21811,
     /*  724580 */     GIR_EraseRootFromParent_Done,
     /*  724581 */   // Label 11484: @724581
     /*  724581 */   GIM_Try, /*On fail goto*//*Label 11485*/ GIMT_Encode4(724647), // Rule ID 21812 //
     /*  724586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  724589 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724611 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64_RTN),
     /*  724614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724616 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724641 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724645 */     GIR_RootConstrainSelectedInstOperands,
     /*  724646 */     // GIR_Coverage, 21812,
     /*  724646 */     GIR_EraseRootFromParent_Done,
     /*  724647 */   // Label 11485: @724647
     /*  724647 */   GIM_Try, /*On fail goto*//*Label 11486*/ GIMT_Encode4(724713), // Rule ID 21828 //
     /*  724652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  724655 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724666 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724670 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724677 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN),
     /*  724680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724682 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724711 */     GIR_RootConstrainSelectedInstOperands,
     /*  724712 */     // GIR_Coverage, 21828,
     /*  724712 */     GIR_EraseRootFromParent_Done,
     /*  724713 */   // Label 11486: @724713
     /*  724713 */   GIM_Try, /*On fail goto*//*Label 11487*/ GIMT_Encode4(724779), // Rule ID 21829 //
     /*  724718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  724721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724743 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN),
     /*  724746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724748 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724773 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724777 */     GIR_RootConstrainSelectedInstOperands,
     /*  724778 */     // GIR_Coverage, 21829,
     /*  724778 */     GIR_EraseRootFromParent_Done,
     /*  724779 */   // Label 11487: @724779
     /*  724779 */   GIM_Try, /*On fail goto*//*Label 11488*/ GIMT_Encode4(724845), // Rule ID 21830 //
     /*  724784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  724787 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724809 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN),
     /*  724812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724814 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724843 */     GIR_RootConstrainSelectedInstOperands,
     /*  724844 */     // GIR_Coverage, 21830,
     /*  724844 */     GIR_EraseRootFromParent_Done,
     /*  724845 */   // Label 11488: @724845
     /*  724845 */   GIM_Try, /*On fail goto*//*Label 11489*/ GIMT_Encode4(724911), // Rule ID 21831 //
     /*  724850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  724853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724875 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN),
     /*  724878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724880 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724909 */     GIR_RootConstrainSelectedInstOperands,
     /*  724910 */     // GIR_Coverage, 21831,
     /*  724910 */     GIR_EraseRootFromParent_Done,
     /*  724911 */   // Label 11489: @724911
     /*  724911 */   GIM_Try, /*On fail goto*//*Label 11490*/ GIMT_Encode4(724977), // Rule ID 21832 //
     /*  724916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  724919 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  724930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  724941 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  724941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN),
     /*  724944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  724946 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  724948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  724953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  724958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  724963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  724968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  724971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  724975 */     GIR_RootConstrainSelectedInstOperands,
     /*  724976 */     // GIR_Coverage, 21832,
     /*  724976 */     GIR_EraseRootFromParent_Done,
     /*  724977 */   // Label 11490: @724977
     /*  724977 */   GIM_Try, /*On fail goto*//*Label 11491*/ GIMT_Encode4(725034), // Rule ID 21813 //
     /*  724982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  724985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  724992 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  724994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  724998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725005 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET),
     /*  725008 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725032 */     GIR_RootConstrainSelectedInstOperands,
     /*  725033 */     // GIR_Coverage, 21813,
     /*  725033 */     GIR_EraseRootFromParent_Done,
     /*  725034 */   // Label 11491: @725034
     /*  725034 */   GIM_Try, /*On fail goto*//*Label 11492*/ GIMT_Encode4(725091), // Rule ID 21814 //
     /*  725039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  725042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725049 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725062 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET),
     /*  725065 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725089 */     GIR_RootConstrainSelectedInstOperands,
     /*  725090 */     // GIR_Coverage, 21814,
     /*  725090 */     GIR_EraseRootFromParent_Done,
     /*  725091 */   // Label 11492: @725091
     /*  725091 */   GIM_Try, /*On fail goto*//*Label 11493*/ GIMT_Encode4(725148), // Rule ID 21815 //
     /*  725096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  725099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725106 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725119 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET),
     /*  725122 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725146 */     GIR_RootConstrainSelectedInstOperands,
     /*  725147 */     // GIR_Coverage, 21815,
     /*  725147 */     GIR_EraseRootFromParent_Done,
     /*  725148 */   // Label 11493: @725148
     /*  725148 */   GIM_Try, /*On fail goto*//*Label 11494*/ GIMT_Encode4(725205), // Rule ID 21816 //
     /*  725153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  725156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725163 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725176 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET),
     /*  725179 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725203 */     GIR_RootConstrainSelectedInstOperands,
     /*  725204 */     // GIR_Coverage, 21816,
     /*  725204 */     GIR_EraseRootFromParent_Done,
     /*  725205 */   // Label 11494: @725205
     /*  725205 */   GIM_Try, /*On fail goto*//*Label 11495*/ GIMT_Encode4(725262), // Rule ID 21817 //
     /*  725210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  725213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725220 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725233 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET),
     /*  725236 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725260 */     GIR_RootConstrainSelectedInstOperands,
     /*  725261 */     // GIR_Coverage, 21817,
     /*  725261 */     GIR_EraseRootFromParent_Done,
     /*  725262 */   // Label 11495: @725262
     /*  725262 */   GIM_Try, /*On fail goto*//*Label 11496*/ GIMT_Encode4(725319), // Rule ID 21833 //
     /*  725267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  725270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725277 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725279 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725290 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET),
     /*  725293 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725317 */     GIR_RootConstrainSelectedInstOperands,
     /*  725318 */     // GIR_Coverage, 21833,
     /*  725318 */     GIR_EraseRootFromParent_Done,
     /*  725319 */   // Label 11496: @725319
     /*  725319 */   GIM_Try, /*On fail goto*//*Label 11497*/ GIMT_Encode4(725376), // Rule ID 21834 //
     /*  725324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  725327 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725334 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725347 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET),
     /*  725350 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725374 */     GIR_RootConstrainSelectedInstOperands,
     /*  725375 */     // GIR_Coverage, 21834,
     /*  725375 */     GIR_EraseRootFromParent_Done,
     /*  725376 */   // Label 11497: @725376
     /*  725376 */   GIM_Try, /*On fail goto*//*Label 11498*/ GIMT_Encode4(725433), // Rule ID 21835 //
     /*  725381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  725384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725391 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725404 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET),
     /*  725407 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725431 */     GIR_RootConstrainSelectedInstOperands,
     /*  725432 */     // GIR_Coverage, 21835,
     /*  725432 */     GIR_EraseRootFromParent_Done,
     /*  725433 */   // Label 11498: @725433
     /*  725433 */   GIM_Try, /*On fail goto*//*Label 11499*/ GIMT_Encode4(725490), // Rule ID 21836 //
     /*  725438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  725441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725448 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725461 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET),
     /*  725464 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725488 */     GIR_RootConstrainSelectedInstOperands,
     /*  725489 */     // GIR_Coverage, 21836,
     /*  725489 */     GIR_EraseRootFromParent_Done,
     /*  725490 */   // Label 11499: @725490
     /*  725490 */   GIM_Try, /*On fail goto*//*Label 11500*/ GIMT_Encode4(725547), // Rule ID 21837 //
     /*  725495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  725498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725505 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  725507 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725518 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET),
     /*  725521 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  725541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725545 */     GIR_RootConstrainSelectedInstOperands,
     /*  725546 */     // GIR_Coverage, 21837,
     /*  725546 */     GIR_EraseRootFromParent_Done,
     /*  725547 */   // Label 11500: @725547
     /*  725547 */   GIM_Try, /*On fail goto*//*Label 11501*/ GIMT_Encode4(725608), // Rule ID 21803 //
     /*  725552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  725555 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725577 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN),
     /*  725580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725582 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725606 */     GIR_RootConstrainSelectedInstOperands,
     /*  725607 */     // GIR_Coverage, 21803,
     /*  725607 */     GIR_EraseRootFromParent_Done,
     /*  725608 */   // Label 11501: @725608
     /*  725608 */   GIM_Try, /*On fail goto*//*Label 11502*/ GIMT_Encode4(725669), // Rule ID 21804 //
     /*  725613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  725616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725627 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725638 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN),
     /*  725641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725643 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725667 */     GIR_RootConstrainSelectedInstOperands,
     /*  725668 */     // GIR_Coverage, 21804,
     /*  725668 */     GIR_EraseRootFromParent_Done,
     /*  725669 */   // Label 11502: @725669
     /*  725669 */   GIM_Try, /*On fail goto*//*Label 11503*/ GIMT_Encode4(725730), // Rule ID 21805 //
     /*  725674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  725677 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725692 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725699 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN),
     /*  725702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725704 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725728 */     GIR_RootConstrainSelectedInstOperands,
     /*  725729 */     // GIR_Coverage, 21805,
     /*  725729 */     GIR_EraseRootFromParent_Done,
     /*  725730 */   // Label 11503: @725730
     /*  725730 */   GIM_Try, /*On fail goto*//*Label 11504*/ GIMT_Encode4(725791), // Rule ID 21806 //
     /*  725735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  725738 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725749 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725760 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN),
     /*  725763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725765 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725785 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725789 */     GIR_RootConstrainSelectedInstOperands,
     /*  725790 */     // GIR_Coverage, 21806,
     /*  725790 */     GIR_EraseRootFromParent_Done,
     /*  725791 */   // Label 11504: @725791
     /*  725791 */   GIM_Try, /*On fail goto*//*Label 11505*/ GIMT_Encode4(725852), // Rule ID 21807 //
     /*  725796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  725799 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725821 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN),
     /*  725824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725826 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725850 */     GIR_RootConstrainSelectedInstOperands,
     /*  725851 */     // GIR_Coverage, 21807,
     /*  725851 */     GIR_EraseRootFromParent_Done,
     /*  725852 */   // Label 11505: @725852
     /*  725852 */   GIM_Try, /*On fail goto*//*Label 11506*/ GIMT_Encode4(725913), // Rule ID 21823 //
     /*  725857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  725860 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725871 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725882 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN),
     /*  725885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725887 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725911 */     GIR_RootConstrainSelectedInstOperands,
     /*  725912 */     // GIR_Coverage, 21823,
     /*  725912 */     GIR_EraseRootFromParent_Done,
     /*  725913 */   // Label 11506: @725913
     /*  725913 */   GIM_Try, /*On fail goto*//*Label 11507*/ GIMT_Encode4(725974), // Rule ID 21824 //
     /*  725918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  725921 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725932 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725936 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  725943 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  725943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN),
     /*  725946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  725948 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  725950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  725955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  725960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  725965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  725968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  725972 */     GIR_RootConstrainSelectedInstOperands,
     /*  725973 */     // GIR_Coverage, 21824,
     /*  725973 */     GIR_EraseRootFromParent_Done,
     /*  725974 */   // Label 11507: @725974
     /*  725974 */   GIM_Try, /*On fail goto*//*Label 11508*/ GIMT_Encode4(726035), // Rule ID 21825 //
     /*  725979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  725982 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  725989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  725993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  725997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  726004 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  726004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN),
     /*  726007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  726009 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  726011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  726016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  726021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  726026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726033 */     GIR_RootConstrainSelectedInstOperands,
     /*  726034 */     // GIR_Coverage, 21825,
     /*  726034 */     GIR_EraseRootFromParent_Done,
     /*  726035 */   // Label 11508: @726035
     /*  726035 */   GIM_Try, /*On fail goto*//*Label 11509*/ GIMT_Encode4(726096), // Rule ID 21826 //
     /*  726040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  726043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  726050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  726054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  726065 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  726065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN),
     /*  726068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  726070 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  726072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  726077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  726082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  726087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726094 */     GIR_RootConstrainSelectedInstOperands,
     /*  726095 */     // GIR_Coverage, 21826,
     /*  726095 */     GIR_EraseRootFromParent_Done,
     /*  726096 */   // Label 11509: @726096
     /*  726096 */   GIM_Try, /*On fail goto*//*Label 11510*/ GIMT_Encode4(726157), // Rule ID 21827 //
     /*  726101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  726104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  726111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  726115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  726126 */     // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  726126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN),
     /*  726129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  726131 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  726133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  726138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  726143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  726148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726155 */     GIR_RootConstrainSelectedInstOperands,
     /*  726156 */     // GIR_Coverage, 21827,
     /*  726156 */     GIR_EraseRootFromParent_Done,
     /*  726157 */   // Label 11510: @726157
     /*  726157 */   GIM_Try, /*On fail goto*//*Label 11511*/ GIMT_Encode4(726207), // Rule ID 30925 //
     /*  726162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  726165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726170 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726183 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726191 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726205 */     GIR_RootConstrainSelectedInstOperands,
     /*  726206 */     // GIR_Coverage, 30925,
     /*  726206 */     GIR_EraseRootFromParent_Done,
     /*  726207 */   // Label 11511: @726207
     /*  726207 */   GIM_Try, /*On fail goto*//*Label 11512*/ GIMT_Encode4(726257), // Rule ID 30926 //
     /*  726212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  726215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726220 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726233 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726241 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726255 */     GIR_RootConstrainSelectedInstOperands,
     /*  726256 */     // GIR_Coverage, 30926,
     /*  726256 */     GIR_EraseRootFromParent_Done,
     /*  726257 */   // Label 11512: @726257
     /*  726257 */   GIM_Try, /*On fail goto*//*Label 11513*/ GIMT_Encode4(726307), // Rule ID 30927 //
     /*  726262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  726265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726270 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726283 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726291 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726305 */     GIR_RootConstrainSelectedInstOperands,
     /*  726306 */     // GIR_Coverage, 30927,
     /*  726306 */     GIR_EraseRootFromParent_Done,
     /*  726307 */   // Label 11513: @726307
     /*  726307 */   GIM_Try, /*On fail goto*//*Label 11514*/ GIMT_Encode4(726357), // Rule ID 30928 //
     /*  726312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  726315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726320 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726333 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726341 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726355 */     GIR_RootConstrainSelectedInstOperands,
     /*  726356 */     // GIR_Coverage, 30928,
     /*  726356 */     GIR_EraseRootFromParent_Done,
     /*  726357 */   // Label 11514: @726357
     /*  726357 */   GIM_Try, /*On fail goto*//*Label 11515*/ GIMT_Encode4(726407), // Rule ID 30929 //
     /*  726362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  726365 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726370 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726383 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726391 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726405 */     GIR_RootConstrainSelectedInstOperands,
     /*  726406 */     // GIR_Coverage, 30929,
     /*  726406 */     GIR_EraseRootFromParent_Done,
     /*  726407 */   // Label 11515: @726407
     /*  726407 */   GIM_Try, /*On fail goto*//*Label 11516*/ GIMT_Encode4(726457), // Rule ID 30935 //
     /*  726412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  726415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726420 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726433 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f64>>  =>  (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9),
     /*  726436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726441 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726455 */     GIR_RootConstrainSelectedInstOperands,
     /*  726456 */     // GIR_Coverage, 30935,
     /*  726456 */     GIR_EraseRootFromParent_Done,
     /*  726457 */   // Label 11516: @726457
     /*  726457 */   GIM_Try, /*On fail goto*//*Label 11517*/ GIMT_Encode4(726507), // Rule ID 30936 //
     /*  726462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  726465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726470 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726472 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726476 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726483 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f64>>  =>  (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9),
     /*  726486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726491 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726505 */     GIR_RootConstrainSelectedInstOperands,
     /*  726506 */     // GIR_Coverage, 30936,
     /*  726506 */     GIR_EraseRootFromParent_Done,
     /*  726507 */   // Label 11517: @726507
     /*  726507 */   GIM_Try, /*On fail goto*//*Label 11518*/ GIMT_Encode4(726557), // Rule ID 30937 //
     /*  726512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  726515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726520 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726533 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f64>>  =>  (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9),
     /*  726536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726541 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726555 */     GIR_RootConstrainSelectedInstOperands,
     /*  726556 */     // GIR_Coverage, 30937,
     /*  726556 */     GIR_EraseRootFromParent_Done,
     /*  726557 */   // Label 11518: @726557
     /*  726557 */   GIM_Try, /*On fail goto*//*Label 11519*/ GIMT_Encode4(726607), // Rule ID 30938 //
     /*  726562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  726565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726570 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726583 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f64>>  =>  (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9),
     /*  726586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726591 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726605 */     GIR_RootConstrainSelectedInstOperands,
     /*  726606 */     // GIR_Coverage, 30938,
     /*  726606 */     GIR_EraseRootFromParent_Done,
     /*  726607 */   // Label 11519: @726607
     /*  726607 */   GIM_Try, /*On fail goto*//*Label 11520*/ GIMT_Encode4(726657), // Rule ID 30939 //
     /*  726612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  726615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726620 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726626 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726633 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f64>>  =>  (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9),
     /*  726636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726641 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726655 */     GIR_RootConstrainSelectedInstOperands,
     /*  726656 */     // GIR_Coverage, 30939,
     /*  726656 */     GIR_EraseRootFromParent_Done,
     /*  726657 */   // Label 11520: @726657
     /*  726657 */   GIM_Try, /*On fail goto*//*Label 11521*/ GIMT_Encode4(726707), // Rule ID 30945 //
     /*  726662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  726665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  726670 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726683 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  726683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726691 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726705 */     GIR_RootConstrainSelectedInstOperands,
     /*  726706 */     // GIR_Coverage, 30945,
     /*  726706 */     GIR_EraseRootFromParent_Done,
     /*  726707 */   // Label 11521: @726707
     /*  726707 */   GIM_Try, /*On fail goto*//*Label 11522*/ GIMT_Encode4(726757), // Rule ID 30946 //
     /*  726712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  726715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  726720 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726733 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  726733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726741 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726751 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726755 */     GIR_RootConstrainSelectedInstOperands,
     /*  726756 */     // GIR_Coverage, 30946,
     /*  726756 */     GIR_EraseRootFromParent_Done,
     /*  726757 */   // Label 11522: @726757
     /*  726757 */   GIM_Try, /*On fail goto*//*Label 11523*/ GIMT_Encode4(726807), // Rule ID 30947 //
     /*  726762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  726765 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  726770 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726772 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726783 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  726783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726791 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726805 */     GIR_RootConstrainSelectedInstOperands,
     /*  726806 */     // GIR_Coverage, 30947,
     /*  726806 */     GIR_EraseRootFromParent_Done,
     /*  726807 */   // Label 11523: @726807
     /*  726807 */   GIM_Try, /*On fail goto*//*Label 11524*/ GIMT_Encode4(726857), // Rule ID 30948 //
     /*  726812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  726815 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  726820 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726833 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  726833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726841 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726855 */     GIR_RootConstrainSelectedInstOperands,
     /*  726856 */     // GIR_Coverage, 30948,
     /*  726856 */     GIR_EraseRootFromParent_Done,
     /*  726857 */   // Label 11524: @726857
     /*  726857 */   GIM_Try, /*On fail goto*//*Label 11525*/ GIMT_Encode4(726907), // Rule ID 30949 //
     /*  726862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  726865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  726870 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  726872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726883 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  726883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
     /*  726886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726891 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  726901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726905 */     GIR_RootConstrainSelectedInstOperands,
     /*  726906 */     // GIR_Coverage, 30949,
     /*  726906 */     GIR_EraseRootFromParent_Done,
     /*  726907 */   // Label 11525: @726907
     /*  726907 */   GIM_Try, /*On fail goto*//*Label 11526*/ GIMT_Encode4(726961), // Rule ID 30920 //
     /*  726912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  726915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  726924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726935 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  726938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  726940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726945 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  726947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  726952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  726955 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  726959 */     GIR_RootConstrainSelectedInstOperands,
     /*  726960 */     // GIR_Coverage, 30920,
     /*  726960 */     GIR_EraseRootFromParent_Done,
     /*  726961 */   // Label 11526: @726961
     /*  726961 */   GIM_Try, /*On fail goto*//*Label 11527*/ GIMT_Encode4(727015), // Rule ID 30921 //
     /*  726966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  726969 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  726974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  726978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  726982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  726989 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  726989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  726992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  726994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  726999 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727013 */     GIR_RootConstrainSelectedInstOperands,
     /*  727014 */     // GIR_Coverage, 30921,
     /*  727014 */     GIR_EraseRootFromParent_Done,
     /*  727015 */   // Label 11527: @727015
     /*  727015 */   GIM_Try, /*On fail goto*//*Label 11528*/ GIMT_Encode4(727069), // Rule ID 30922 //
     /*  727020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  727023 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727028 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727032 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727043 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727053 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727067 */     GIR_RootConstrainSelectedInstOperands,
     /*  727068 */     // GIR_Coverage, 30922,
     /*  727068 */     GIR_EraseRootFromParent_Done,
     /*  727069 */   // Label 11528: @727069
     /*  727069 */   GIM_Try, /*On fail goto*//*Label 11529*/ GIMT_Encode4(727123), // Rule ID 30923 //
     /*  727074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  727077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727097 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727107 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727121 */     GIR_RootConstrainSelectedInstOperands,
     /*  727122 */     // GIR_Coverage, 30923,
     /*  727122 */     GIR_EraseRootFromParent_Done,
     /*  727123 */   // Label 11529: @727123
     /*  727123 */   GIM_Try, /*On fail goto*//*Label 11530*/ GIMT_Encode4(727177), // Rule ID 30924 //
     /*  727128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  727131 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727140 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727151 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727161 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727171 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727175 */     GIR_RootConstrainSelectedInstOperands,
     /*  727176 */     // GIR_Coverage, 30924,
     /*  727176 */     GIR_EraseRootFromParent_Done,
     /*  727177 */   // Label 11530: @727177
     /*  727177 */   GIM_Try, /*On fail goto*//*Label 11531*/ GIMT_Encode4(727231), // Rule ID 30930 //
     /*  727182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  727185 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727194 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727205 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_f64>>  =>  (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9),
     /*  727208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727215 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727225 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727229 */     GIR_RootConstrainSelectedInstOperands,
     /*  727230 */     // GIR_Coverage, 30930,
     /*  727230 */     GIR_EraseRootFromParent_Done,
     /*  727231 */   // Label 11531: @727231
     /*  727231 */   GIM_Try, /*On fail goto*//*Label 11532*/ GIMT_Encode4(727285), // Rule ID 30931 //
     /*  727236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  727239 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727259 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_f64>>  =>  (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9),
     /*  727262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727269 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727283 */     GIR_RootConstrainSelectedInstOperands,
     /*  727284 */     // GIR_Coverage, 30931,
     /*  727284 */     GIR_EraseRootFromParent_Done,
     /*  727285 */   // Label 11532: @727285
     /*  727285 */   GIM_Try, /*On fail goto*//*Label 11533*/ GIMT_Encode4(727339), // Rule ID 30932 //
     /*  727290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  727293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727313 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_f64>>  =>  (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9),
     /*  727316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727323 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727337 */     GIR_RootConstrainSelectedInstOperands,
     /*  727338 */     // GIR_Coverage, 30932,
     /*  727338 */     GIR_EraseRootFromParent_Done,
     /*  727339 */   // Label 11533: @727339
     /*  727339 */   GIM_Try, /*On fail goto*//*Label 11534*/ GIMT_Encode4(727393), // Rule ID 30933 //
     /*  727344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  727347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727367 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_f64>>  =>  (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9),
     /*  727370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727377 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727391 */     GIR_RootConstrainSelectedInstOperands,
     /*  727392 */     // GIR_Coverage, 30933,
     /*  727392 */     GIR_EraseRootFromParent_Done,
     /*  727393 */   // Label 11534: @727393
     /*  727393 */   GIM_Try, /*On fail goto*//*Label 11535*/ GIMT_Encode4(727447), // Rule ID 30934 //
     /*  727398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  727401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  727406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727421 */     // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_f64>>  =>  (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  727421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9),
     /*  727424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727431 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  727441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727445 */     GIR_RootConstrainSelectedInstOperands,
     /*  727446 */     // GIR_Coverage, 30934,
     /*  727446 */     GIR_EraseRootFromParent_Done,
     /*  727447 */   // Label 11535: @727447
     /*  727447 */   GIM_Try, /*On fail goto*//*Label 11536*/ GIMT_Encode4(727501), // Rule ID 30940 //
     /*  727452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  727455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  727460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727475 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  727475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727485 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  727495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727499 */     GIR_RootConstrainSelectedInstOperands,
     /*  727500 */     // GIR_Coverage, 30940,
     /*  727500 */     GIR_EraseRootFromParent_Done,
     /*  727501 */   // Label 11536: @727501
     /*  727501 */   GIM_Try, /*On fail goto*//*Label 11537*/ GIMT_Encode4(727555), // Rule ID 30941 //
     /*  727506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  727509 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  727514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727529 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  727529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727539 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  727549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727553 */     GIR_RootConstrainSelectedInstOperands,
     /*  727554 */     // GIR_Coverage, 30941,
     /*  727554 */     GIR_EraseRootFromParent_Done,
     /*  727555 */   // Label 11537: @727555
     /*  727555 */   GIM_Try, /*On fail goto*//*Label 11538*/ GIMT_Encode4(727609), // Rule ID 30942 //
     /*  727560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  727563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  727568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727583 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  727583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727593 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  727603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727607 */     GIR_RootConstrainSelectedInstOperands,
     /*  727608 */     // GIR_Coverage, 30942,
     /*  727608 */     GIR_EraseRootFromParent_Done,
     /*  727609 */   // Label 11538: @727609
     /*  727609 */   GIM_Try, /*On fail goto*//*Label 11539*/ GIMT_Encode4(727663), // Rule ID 30943 //
     /*  727614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  727617 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  727622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727626 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727637 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  727637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727647 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  727657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727661 */     GIR_RootConstrainSelectedInstOperands,
     /*  727662 */     // GIR_Coverage, 30943,
     /*  727662 */     GIR_EraseRootFromParent_Done,
     /*  727663 */   // Label 11539: @727663
     /*  727663 */   GIM_Try, /*On fail goto*//*Label 11540*/ GIMT_Encode4(727717), // Rule ID 30944 //
     /*  727668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  727671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  727676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  727680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  727691 */     // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  727691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
     /*  727694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  727696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  727701 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  727703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  727708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  727711 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727715 */     GIR_RootConstrainSelectedInstOperands,
     /*  727716 */     // GIR_Coverage, 30944,
     /*  727716 */     GIR_EraseRootFromParent_Done,
     /*  727717 */   // Label 11540: @727717
     /*  727717 */   GIM_Try, /*On fail goto*//*Label 11541*/ GIMT_Encode4(727776), // Rule ID 13758 //
     /*  727722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  727725 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  727732 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  727734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  727745 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  727745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
     /*  727748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  727753 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  727755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  727760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  727765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  727770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727774 */     GIR_RootConstrainSelectedInstOperands,
     /*  727775 */     // GIR_Coverage, 13758,
     /*  727775 */     GIR_EraseRootFromParent_Done,
     /*  727776 */   // Label 11541: @727776
     /*  727776 */   GIM_Try, /*On fail goto*//*Label 11542*/ GIMT_Encode4(727835), // Rule ID 13759 //
     /*  727781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  727784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  727791 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  727793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  727804 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  727804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
     /*  727807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  727812 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  727814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  727819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  727824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  727829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727833 */     GIR_RootConstrainSelectedInstOperands,
     /*  727834 */     // GIR_Coverage, 13759,
     /*  727834 */     GIR_EraseRootFromParent_Done,
     /*  727835 */   // Label 11542: @727835
     /*  727835 */   GIM_Try, /*On fail goto*//*Label 11543*/ GIMT_Encode4(727894), // Rule ID 13760 //
     /*  727840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  727843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  727850 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  727852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  727863 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  727863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
     /*  727866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  727871 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  727873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  727878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  727883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  727888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727892 */     GIR_RootConstrainSelectedInstOperands,
     /*  727893 */     // GIR_Coverage, 13760,
     /*  727893 */     GIR_EraseRootFromParent_Done,
     /*  727894 */   // Label 11543: @727894
     /*  727894 */   GIM_Try, /*On fail goto*//*Label 11544*/ GIMT_Encode4(727953), // Rule ID 13761 //
     /*  727899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  727902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  727909 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  727911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  727922 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  727922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
     /*  727925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  727930 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  727932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  727937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  727942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  727947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  727951 */     GIR_RootConstrainSelectedInstOperands,
     /*  727952 */     // GIR_Coverage, 13761,
     /*  727952 */     GIR_EraseRootFromParent_Done,
     /*  727953 */   // Label 11544: @727953
     /*  727953 */   GIM_Try, /*On fail goto*//*Label 11545*/ GIMT_Encode4(728012), // Rule ID 13762 //
     /*  727958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  727961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  727968 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  727970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  727974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  727981 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  727981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
     /*  727984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  727989 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  727991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  727996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728010 */     GIR_RootConstrainSelectedInstOperands,
     /*  728011 */     // GIR_Coverage, 13762,
     /*  728011 */     GIR_EraseRootFromParent_Done,
     /*  728012 */   // Label 11545: @728012
     /*  728012 */   GIM_Try, /*On fail goto*//*Label 11546*/ GIMT_Encode4(728075), // Rule ID 13768 //
     /*  728017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  728020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  728042 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
     /*  728045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728052 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728069 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728073 */     GIR_RootConstrainSelectedInstOperands,
     /*  728074 */     // GIR_Coverage, 13768,
     /*  728074 */     GIR_EraseRootFromParent_Done,
     /*  728075 */   // Label 11546: @728075
     /*  728075 */   GIM_Try, /*On fail goto*//*Label 11547*/ GIMT_Encode4(728138), // Rule ID 13769 //
     /*  728080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  728083 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728094 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  728105 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
     /*  728108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728115 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728132 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728136 */     GIR_RootConstrainSelectedInstOperands,
     /*  728137 */     // GIR_Coverage, 13769,
     /*  728137 */     GIR_EraseRootFromParent_Done,
     /*  728138 */   // Label 11547: @728138
     /*  728138 */   GIM_Try, /*On fail goto*//*Label 11548*/ GIMT_Encode4(728201), // Rule ID 13770 //
     /*  728143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  728146 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  728168 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
     /*  728171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728178 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728195 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728199 */     GIR_RootConstrainSelectedInstOperands,
     /*  728200 */     // GIR_Coverage, 13770,
     /*  728200 */     GIR_EraseRootFromParent_Done,
     /*  728201 */   // Label 11548: @728201
     /*  728201 */   GIM_Try, /*On fail goto*//*Label 11549*/ GIMT_Encode4(728264), // Rule ID 13771 //
     /*  728206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  728209 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  728231 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
     /*  728234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728241 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728262 */     GIR_RootConstrainSelectedInstOperands,
     /*  728263 */     // GIR_Coverage, 13771,
     /*  728263 */     GIR_EraseRootFromParent_Done,
     /*  728264 */   // Label 11549: @728264
     /*  728264 */   GIM_Try, /*On fail goto*//*Label 11550*/ GIMT_Encode4(728327), // Rule ID 13772 //
     /*  728269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  728272 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  728294 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
     /*  728297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728304 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728325 */     GIR_RootConstrainSelectedInstOperands,
     /*  728326 */     // GIR_Coverage, 13772,
     /*  728326 */     GIR_EraseRootFromParent_Done,
     /*  728327 */   // Label 11550: @728327
     /*  728327 */   GIM_Try, /*On fail goto*//*Label 11551*/ GIMT_Encode4(728379), // Rule ID 13753 //
     /*  728332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  728335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728342 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728344 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728355 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
     /*  728358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728363 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  728373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728377 */     GIR_RootConstrainSelectedInstOperands,
     /*  728378 */     // GIR_Coverage, 13753,
     /*  728378 */     GIR_EraseRootFromParent_Done,
     /*  728379 */   // Label 11551: @728379
     /*  728379 */   GIM_Try, /*On fail goto*//*Label 11552*/ GIMT_Encode4(728431), // Rule ID 13754 //
     /*  728384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  728387 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728394 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728407 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
     /*  728410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728415 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  728425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728429 */     GIR_RootConstrainSelectedInstOperands,
     /*  728430 */     // GIR_Coverage, 13754,
     /*  728430 */     GIR_EraseRootFromParent_Done,
     /*  728431 */   // Label 11552: @728431
     /*  728431 */   GIM_Try, /*On fail goto*//*Label 11553*/ GIMT_Encode4(728483), // Rule ID 13755 //
     /*  728436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  728439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728446 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728459 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
     /*  728462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728467 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  728477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728481 */     GIR_RootConstrainSelectedInstOperands,
     /*  728482 */     // GIR_Coverage, 13755,
     /*  728482 */     GIR_EraseRootFromParent_Done,
     /*  728483 */   // Label 11553: @728483
     /*  728483 */   GIM_Try, /*On fail goto*//*Label 11554*/ GIMT_Encode4(728535), // Rule ID 13756 //
     /*  728488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  728491 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728498 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728500 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728504 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728511 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
     /*  728514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728519 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  728529 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728533 */     GIR_RootConstrainSelectedInstOperands,
     /*  728534 */     // GIR_Coverage, 13756,
     /*  728534 */     GIR_EraseRootFromParent_Done,
     /*  728535 */   // Label 11554: @728535
     /*  728535 */   GIM_Try, /*On fail goto*//*Label 11555*/ GIMT_Encode4(728587), // Rule ID 13757 //
     /*  728540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  728543 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728550 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728563 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
     /*  728566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728571 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  728581 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728585 */     GIR_RootConstrainSelectedInstOperands,
     /*  728586 */     // GIR_Coverage, 13757,
     /*  728586 */     GIR_EraseRootFromParent_Done,
     /*  728587 */   // Label 11555: @728587
     /*  728587 */   GIM_Try, /*On fail goto*//*Label 11556*/ GIMT_Encode4(728643), // Rule ID 13763 //
     /*  728592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  728595 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728617 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
     /*  728620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728627 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  728637 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728641 */     GIR_RootConstrainSelectedInstOperands,
     /*  728642 */     // GIR_Coverage, 13763,
     /*  728642 */     GIR_EraseRootFromParent_Done,
     /*  728643 */   // Label 11556: @728643
     /*  728643 */   GIM_Try, /*On fail goto*//*Label 11557*/ GIMT_Encode4(728699), // Rule ID 13764 //
     /*  728648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  728651 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728673 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
     /*  728676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728683 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  728693 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728697 */     GIR_RootConstrainSelectedInstOperands,
     /*  728698 */     // GIR_Coverage, 13764,
     /*  728698 */     GIR_EraseRootFromParent_Done,
     /*  728699 */   // Label 11557: @728699
     /*  728699 */   GIM_Try, /*On fail goto*//*Label 11558*/ GIMT_Encode4(728755), // Rule ID 13765 //
     /*  728704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  728707 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728718 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728722 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728729 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
     /*  728732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728739 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  728749 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728753 */     GIR_RootConstrainSelectedInstOperands,
     /*  728754 */     // GIR_Coverage, 13765,
     /*  728754 */     GIR_EraseRootFromParent_Done,
     /*  728755 */   // Label 11558: @728755
     /*  728755 */   GIM_Try, /*On fail goto*//*Label 11559*/ GIMT_Encode4(728811), // Rule ID 13766 //
     /*  728760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  728763 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728785 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
     /*  728788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728795 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  728805 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728809 */     GIR_RootConstrainSelectedInstOperands,
     /*  728810 */     // GIR_Coverage, 13766,
     /*  728810 */     GIR_EraseRootFromParent_Done,
     /*  728811 */   // Label 11559: @728811
     /*  728811 */   GIM_Try, /*On fail goto*//*Label 11560*/ GIMT_Encode4(728867), // Rule ID 13767 //
     /*  728816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  728819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  728830 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  728841 */     // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  728841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
     /*  728844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  728846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  728851 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  728858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  728861 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728865 */     GIR_RootConstrainSelectedInstOperands,
     /*  728866 */     // GIR_Coverage, 13767,
     /*  728866 */     GIR_EraseRootFromParent_Done,
     /*  728867 */   // Label 11560: @728867
     /*  728867 */   GIM_Try, /*On fail goto*//*Label 11561*/ GIMT_Encode4(728927), // Rule ID 11009 //
     /*  728872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  728875 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728883 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  728896 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  728899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728904 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728925 */     GIR_RootConstrainSelectedInstOperands,
     /*  728926 */     // GIR_Coverage, 11009,
     /*  728926 */     GIR_EraseRootFromParent_Done,
     /*  728927 */   // Label 11561: @728927
     /*  728927 */   GIM_Try, /*On fail goto*//*Label 11562*/ GIMT_Encode4(728987), // Rule ID 11010 //
     /*  728932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  728935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  728943 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  728945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  728949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  728956 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  728956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  728959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  728964 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  728966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  728971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  728976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  728981 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  728985 */     GIR_RootConstrainSelectedInstOperands,
     /*  728986 */     // GIR_Coverage, 11010,
     /*  728986 */     GIR_EraseRootFromParent_Done,
     /*  728987 */   // Label 11562: @728987
     /*  728987 */   GIM_Try, /*On fail goto*//*Label 11563*/ GIMT_Encode4(729047), // Rule ID 11011 //
     /*  728992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  728995 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729003 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729016 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729024 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729045 */     GIR_RootConstrainSelectedInstOperands,
     /*  729046 */     // GIR_Coverage, 11011,
     /*  729046 */     GIR_EraseRootFromParent_Done,
     /*  729047 */   // Label 11563: @729047
     /*  729047 */   GIM_Try, /*On fail goto*//*Label 11564*/ GIMT_Encode4(729107), // Rule ID 11012 //
     /*  729052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  729055 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729063 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729076 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729084 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729105 */     GIR_RootConstrainSelectedInstOperands,
     /*  729106 */     // GIR_Coverage, 11012,
     /*  729106 */     GIR_EraseRootFromParent_Done,
     /*  729107 */   // Label 11564: @729107
     /*  729107 */   GIM_Try, /*On fail goto*//*Label 11565*/ GIMT_Encode4(729167), // Rule ID 11013 //
     /*  729112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  729115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729123 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729136 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729144 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729165 */     GIR_RootConstrainSelectedInstOperands,
     /*  729166 */     // GIR_Coverage, 11013,
     /*  729166 */     GIR_EraseRootFromParent_Done,
     /*  729167 */   // Label 11565: @729167
     /*  729167 */   GIM_Try, /*On fail goto*//*Label 11566*/ GIMT_Encode4(729226), // Rule ID 11565 //
     /*  729172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  729175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729182 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729195 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729203 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729220 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729224 */     GIR_RootConstrainSelectedInstOperands,
     /*  729225 */     // GIR_Coverage, 11565,
     /*  729225 */     GIR_EraseRootFromParent_Done,
     /*  729226 */   // Label 11566: @729226
     /*  729226 */   GIM_Try, /*On fail goto*//*Label 11567*/ GIMT_Encode4(729285), // Rule ID 11566 //
     /*  729231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  729234 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729241 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729254 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729262 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729283 */     GIR_RootConstrainSelectedInstOperands,
     /*  729284 */     // GIR_Coverage, 11566,
     /*  729284 */     GIR_EraseRootFromParent_Done,
     /*  729285 */   // Label 11567: @729285
     /*  729285 */   GIM_Try, /*On fail goto*//*Label 11568*/ GIMT_Encode4(729344), // Rule ID 11567 //
     /*  729290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  729293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729300 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729313 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729321 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729342 */     GIR_RootConstrainSelectedInstOperands,
     /*  729343 */     // GIR_Coverage, 11567,
     /*  729343 */     GIR_EraseRootFromParent_Done,
     /*  729344 */   // Label 11568: @729344
     /*  729344 */   GIM_Try, /*On fail goto*//*Label 11569*/ GIMT_Encode4(729403), // Rule ID 11568 //
     /*  729349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  729352 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729359 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729365 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729372 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729380 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729401 */     GIR_RootConstrainSelectedInstOperands,
     /*  729402 */     // GIR_Coverage, 11568,
     /*  729402 */     GIR_EraseRootFromParent_Done,
     /*  729403 */   // Label 11569: @729403
     /*  729403 */   GIM_Try, /*On fail goto*//*Label 11570*/ GIMT_Encode4(729462), // Rule ID 11569 //
     /*  729408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  729411 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729418 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  729420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  729431 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR),
     /*  729434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729439 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729456 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729460 */     GIR_RootConstrainSelectedInstOperands,
     /*  729461 */     // GIR_Coverage, 11569,
     /*  729461 */     GIR_EraseRootFromParent_Done,
     /*  729462 */   // Label 11570: @729462
     /*  729462 */   GIM_Try, /*On fail goto*//*Label 11571*/ GIMT_Encode4(729526), // Rule ID 10999 //
     /*  729467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  729470 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729493 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729503 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729524 */     GIR_RootConstrainSelectedInstOperands,
     /*  729525 */     // GIR_Coverage, 10999,
     /*  729525 */     GIR_EraseRootFromParent_Done,
     /*  729526 */   // Label 11571: @729526
     /*  729526 */   GIM_Try, /*On fail goto*//*Label 11572*/ GIMT_Encode4(729590), // Rule ID 11000 //
     /*  729531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  729534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729557 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729567 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729588 */     GIR_RootConstrainSelectedInstOperands,
     /*  729589 */     // GIR_Coverage, 11000,
     /*  729589 */     GIR_EraseRootFromParent_Done,
     /*  729590 */   // Label 11572: @729590
     /*  729590 */   GIM_Try, /*On fail goto*//*Label 11573*/ GIMT_Encode4(729654), // Rule ID 11001 //
     /*  729595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  729598 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729621 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729631 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729652 */     GIR_RootConstrainSelectedInstOperands,
     /*  729653 */     // GIR_Coverage, 11001,
     /*  729653 */     GIR_EraseRootFromParent_Done,
     /*  729654 */   // Label 11573: @729654
     /*  729654 */   GIM_Try, /*On fail goto*//*Label 11574*/ GIMT_Encode4(729718), // Rule ID 11002 //
     /*  729659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  729662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729685 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729695 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729712 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729716 */     GIR_RootConstrainSelectedInstOperands,
     /*  729717 */     // GIR_Coverage, 11002,
     /*  729717 */     GIR_EraseRootFromParent_Done,
     /*  729718 */   // Label 11574: @729718
     /*  729718 */   GIM_Try, /*On fail goto*//*Label 11575*/ GIMT_Encode4(729782), // Rule ID 11003 //
     /*  729723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  729726 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729749 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729759 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729780 */     GIR_RootConstrainSelectedInstOperands,
     /*  729781 */     // GIR_Coverage, 11003,
     /*  729781 */     GIR_EraseRootFromParent_Done,
     /*  729782 */   // Label 11575: @729782
     /*  729782 */   GIM_Try, /*On fail goto*//*Label 11576*/ GIMT_Encode4(729845), // Rule ID 11555 //
     /*  729787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  729790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729812 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729822 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729843 */     GIR_RootConstrainSelectedInstOperands,
     /*  729844 */     // GIR_Coverage, 11555,
     /*  729844 */     GIR_EraseRootFromParent_Done,
     /*  729845 */   // Label 11576: @729845
     /*  729845 */   GIM_Try, /*On fail goto*//*Label 11577*/ GIMT_Encode4(729908), // Rule ID 11556 //
     /*  729850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  729853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729875 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729885 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729906 */     GIR_RootConstrainSelectedInstOperands,
     /*  729907 */     // GIR_Coverage, 11556,
     /*  729907 */     GIR_EraseRootFromParent_Done,
     /*  729908 */   // Label 11577: @729908
     /*  729908 */   GIM_Try, /*On fail goto*//*Label 11578*/ GIMT_Encode4(729971), // Rule ID 11557 //
     /*  729913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  729916 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  729938 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  729938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  729941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  729943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  729948 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  729950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  729955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  729960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  729965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  729969 */     GIR_RootConstrainSelectedInstOperands,
     /*  729970 */     // GIR_Coverage, 11557,
     /*  729970 */     GIR_EraseRootFromParent_Done,
     /*  729971 */   // Label 11578: @729971
     /*  729971 */   GIM_Try, /*On fail goto*//*Label 11579*/ GIMT_Encode4(730034), // Rule ID 11558 //
     /*  729976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  729979 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  729986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  729990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  729994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  730001 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  730001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  730004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  730011 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  730018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  730023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  730028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730032 */     GIR_RootConstrainSelectedInstOperands,
     /*  730033 */     // GIR_Coverage, 11558,
     /*  730033 */     GIR_EraseRootFromParent_Done,
     /*  730034 */   // Label 11579: @730034
     /*  730034 */   GIM_Try, /*On fail goto*//*Label 11580*/ GIMT_Encode4(730097), // Rule ID 11559 //
     /*  730039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  730042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  730064 */     // (atomic_load_fmax:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  730064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_SADDR_RTN),
     /*  730067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  730074 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  730081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  730086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  730091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730095 */     GIR_RootConstrainSelectedInstOperands,
     /*  730096 */     // GIR_Coverage, 11559,
     /*  730096 */     GIR_EraseRootFromParent_Done,
     /*  730097 */   // Label 11580: @730097
     /*  730097 */   GIM_Try, /*On fail goto*//*Label 11581*/ GIMT_Encode4(730150), // Rule ID 11004 //
     /*  730102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  730105 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730113 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730115 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730126 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730134 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730148 */     GIR_RootConstrainSelectedInstOperands,
     /*  730149 */     // GIR_Coverage, 11004,
     /*  730149 */     GIR_EraseRootFromParent_Done,
     /*  730150 */   // Label 11581: @730150
     /*  730150 */   GIM_Try, /*On fail goto*//*Label 11582*/ GIMT_Encode4(730203), // Rule ID 11005 //
     /*  730155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  730158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730166 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730179 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730187 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730197 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730201 */     GIR_RootConstrainSelectedInstOperands,
     /*  730202 */     // GIR_Coverage, 11005,
     /*  730202 */     GIR_EraseRootFromParent_Done,
     /*  730203 */   // Label 11582: @730203
     /*  730203 */   GIM_Try, /*On fail goto*//*Label 11583*/ GIMT_Encode4(730256), // Rule ID 11006 //
     /*  730208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  730211 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730219 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730232 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730240 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730254 */     GIR_RootConstrainSelectedInstOperands,
     /*  730255 */     // GIR_Coverage, 11006,
     /*  730255 */     GIR_EraseRootFromParent_Done,
     /*  730256 */   // Label 11583: @730256
     /*  730256 */   GIM_Try, /*On fail goto*//*Label 11584*/ GIMT_Encode4(730309), // Rule ID 11007 //
     /*  730261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  730264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730272 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730285 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730293 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730307 */     GIR_RootConstrainSelectedInstOperands,
     /*  730308 */     // GIR_Coverage, 11007,
     /*  730308 */     GIR_EraseRootFromParent_Done,
     /*  730309 */   // Label 11584: @730309
     /*  730309 */   GIM_Try, /*On fail goto*//*Label 11585*/ GIMT_Encode4(730362), // Rule ID 11008 //
     /*  730314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  730317 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730325 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730338 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730346 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730360 */     GIR_RootConstrainSelectedInstOperands,
     /*  730361 */     // GIR_Coverage, 11008,
     /*  730361 */     GIR_EraseRootFromParent_Done,
     /*  730362 */   // Label 11585: @730362
     /*  730362 */   GIM_Try, /*On fail goto*//*Label 11586*/ GIMT_Encode4(730414), // Rule ID 11560 //
     /*  730367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  730370 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730377 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730379 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730390 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730398 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730412 */     GIR_RootConstrainSelectedInstOperands,
     /*  730413 */     // GIR_Coverage, 11560,
     /*  730413 */     GIR_EraseRootFromParent_Done,
     /*  730414 */   // Label 11586: @730414
     /*  730414 */   GIM_Try, /*On fail goto*//*Label 11587*/ GIMT_Encode4(730466), // Rule ID 11561 //
     /*  730419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  730422 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730429 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730431 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730435 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730442 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730450 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730464 */     GIR_RootConstrainSelectedInstOperands,
     /*  730465 */     // GIR_Coverage, 11561,
     /*  730465 */     GIR_EraseRootFromParent_Done,
     /*  730466 */   // Label 11587: @730466
     /*  730466 */   GIM_Try, /*On fail goto*//*Label 11588*/ GIMT_Encode4(730518), // Rule ID 11562 //
     /*  730471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  730474 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730481 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730483 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730494 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730502 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730512 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730516 */     GIR_RootConstrainSelectedInstOperands,
     /*  730517 */     // GIR_Coverage, 11562,
     /*  730517 */     GIR_EraseRootFromParent_Done,
     /*  730518 */   // Label 11588: @730518
     /*  730518 */   GIM_Try, /*On fail goto*//*Label 11589*/ GIMT_Encode4(730570), // Rule ID 11563 //
     /*  730523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  730526 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730533 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730546 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730554 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730564 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730568 */     GIR_RootConstrainSelectedInstOperands,
     /*  730569 */     // GIR_Coverage, 11563,
     /*  730569 */     GIR_EraseRootFromParent_Done,
     /*  730570 */   // Label 11589: @730570
     /*  730570 */   GIM_Try, /*On fail goto*//*Label 11590*/ GIMT_Encode4(730622), // Rule ID 11564 //
     /*  730575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  730578 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730585 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  730587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730598 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
     /*  730601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730606 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  730616 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730620 */     GIR_RootConstrainSelectedInstOperands,
     /*  730621 */     // GIR_Coverage, 11564,
     /*  730621 */     GIR_EraseRootFromParent_Done,
     /*  730622 */   // Label 11590: @730622
     /*  730622 */   GIM_Try, /*On fail goto*//*Label 11591*/ GIMT_Encode4(730679), // Rule ID 10994 //
     /*  730627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  730630 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730653 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730663 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  730673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730677 */     GIR_RootConstrainSelectedInstOperands,
     /*  730678 */     // GIR_Coverage, 10994,
     /*  730678 */     GIR_EraseRootFromParent_Done,
     /*  730679 */   // Label 11591: @730679
     /*  730679 */   GIM_Try, /*On fail goto*//*Label 11592*/ GIMT_Encode4(730736), // Rule ID 10995 //
     /*  730684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  730687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730710 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730720 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  730730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730734 */     GIR_RootConstrainSelectedInstOperands,
     /*  730735 */     // GIR_Coverage, 10995,
     /*  730735 */     GIR_EraseRootFromParent_Done,
     /*  730736 */   // Label 11592: @730736
     /*  730736 */   GIM_Try, /*On fail goto*//*Label 11593*/ GIMT_Encode4(730793), // Rule ID 10996 //
     /*  730741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  730744 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730756 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730760 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730767 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730777 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  730787 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730791 */     GIR_RootConstrainSelectedInstOperands,
     /*  730792 */     // GIR_Coverage, 10996,
     /*  730792 */     GIR_EraseRootFromParent_Done,
     /*  730793 */   // Label 11593: @730793
     /*  730793 */   GIM_Try, /*On fail goto*//*Label 11594*/ GIMT_Encode4(730850), // Rule ID 10997 //
     /*  730798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  730801 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730817 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730824 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730834 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  730844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730848 */     GIR_RootConstrainSelectedInstOperands,
     /*  730849 */     // GIR_Coverage, 10997,
     /*  730849 */     GIR_EraseRootFromParent_Done,
     /*  730850 */   // Label 11594: @730850
     /*  730850 */   GIM_Try, /*On fail goto*//*Label 11595*/ GIMT_Encode4(730907), // Rule ID 10998 //
     /*  730855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  730858 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730874 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730881 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730891 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  730901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730905 */     GIR_RootConstrainSelectedInstOperands,
     /*  730906 */     // GIR_Coverage, 10998,
     /*  730906 */     GIR_EraseRootFromParent_Done,
     /*  730907 */   // Label 11595: @730907
     /*  730907 */   GIM_Try, /*On fail goto*//*Label 11596*/ GIMT_Encode4(730963), // Rule ID 11550 //
     /*  730912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  730915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730937 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  730947 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  730949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  730954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  730957 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  730961 */     GIR_RootConstrainSelectedInstOperands,
     /*  730962 */     // GIR_Coverage, 11550,
     /*  730962 */     GIR_EraseRootFromParent_Done,
     /*  730963 */   // Label 11596: @730963
     /*  730963 */   GIM_Try, /*On fail goto*//*Label 11597*/ GIMT_Encode4(731019), // Rule ID 11551 //
     /*  730968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  730971 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  730978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  730982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  730986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  730993 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  730993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  730996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  730998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  731003 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  731005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  731010 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  731013 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731017 */     GIR_RootConstrainSelectedInstOperands,
     /*  731018 */     // GIR_Coverage, 11551,
     /*  731018 */     GIR_EraseRootFromParent_Done,
     /*  731019 */   // Label 11597: @731019
     /*  731019 */   GIM_Try, /*On fail goto*//*Label 11598*/ GIMT_Encode4(731075), // Rule ID 11552 //
     /*  731024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  731027 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  731038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  731049 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  731049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  731052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  731054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  731059 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  731061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  731066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  731069 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731073 */     GIR_RootConstrainSelectedInstOperands,
     /*  731074 */     // GIR_Coverage, 11552,
     /*  731074 */     GIR_EraseRootFromParent_Done,
     /*  731075 */   // Label 11598: @731075
     /*  731075 */   GIM_Try, /*On fail goto*//*Label 11599*/ GIMT_Encode4(731131), // Rule ID 11553 //
     /*  731080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  731083 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  731094 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  731105 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  731105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  731108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  731110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  731115 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  731117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  731122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  731125 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731129 */     GIR_RootConstrainSelectedInstOperands,
     /*  731130 */     // GIR_Coverage, 11553,
     /*  731130 */     GIR_EraseRootFromParent_Done,
     /*  731131 */   // Label 11599: @731131
     /*  731131 */   GIM_Try, /*On fail goto*//*Label 11600*/ GIMT_Encode4(731187), // Rule ID 11554 //
     /*  731136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  731139 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  731150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  731161 */     // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  731161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
     /*  731164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  731166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  731171 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  731173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  731178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  731181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731185 */     GIR_RootConstrainSelectedInstOperands,
     /*  731186 */     // GIR_Coverage, 11554,
     /*  731186 */     GIR_EraseRootFromParent_Done,
     /*  731187 */   // Label 11600: @731187
     /*  731187 */   GIM_Reject,
     /*  731188 */ // Label 11470: @731188
     /*  731188 */ GIM_Reject,
     /*  731189 */ // Label 11346: @731189
     /*  731189 */ GIM_Reject,
     /*  731190 */ // Label 31: @731190
     /*  731190 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 11603*/ GIMT_Encode4(745715),
     /*  731201 */ /*GILLT_s32*//*Label 11601*/ GIMT_Encode4(731209),
     /*  731205 */ /*GILLT_s64*//*Label 11602*/ GIMT_Encode4(738215),
     /*  731209 */ // Label 11601: @731209
     /*  731209 */ GIM_Try, /*On fail goto*//*Label 11604*/ GIMT_Encode4(738214),
     /*  731214 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  731217 */   GIM_Try, /*On fail goto*//*Label 11605*/ GIMT_Encode4(731279), // Rule ID 21698 //
     /*  731222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  731225 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731232 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731245 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64),
     /*  731248 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731273 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731277 */     GIR_RootConstrainSelectedInstOperands,
     /*  731278 */     // GIR_Coverage, 21698,
     /*  731278 */     GIR_EraseRootFromParent_Done,
     /*  731279 */   // Label 11605: @731279
     /*  731279 */   GIM_Try, /*On fail goto*//*Label 11606*/ GIMT_Encode4(731341), // Rule ID 21699 //
     /*  731284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  731287 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731294 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731307 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64),
     /*  731310 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731335 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731339 */     GIR_RootConstrainSelectedInstOperands,
     /*  731340 */     // GIR_Coverage, 21699,
     /*  731340 */     GIR_EraseRootFromParent_Done,
     /*  731341 */   // Label 11606: @731341
     /*  731341 */   GIM_Try, /*On fail goto*//*Label 11607*/ GIMT_Encode4(731403), // Rule ID 21700 //
     /*  731346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  731349 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731356 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731369 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64),
     /*  731372 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731401 */     GIR_RootConstrainSelectedInstOperands,
     /*  731402 */     // GIR_Coverage, 21700,
     /*  731402 */     GIR_EraseRootFromParent_Done,
     /*  731403 */   // Label 11607: @731403
     /*  731403 */   GIM_Try, /*On fail goto*//*Label 11608*/ GIMT_Encode4(731465), // Rule ID 21701 //
     /*  731408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  731411 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731418 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731431 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64),
     /*  731434 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731463 */     GIR_RootConstrainSelectedInstOperands,
     /*  731464 */     // GIR_Coverage, 21701,
     /*  731464 */     GIR_EraseRootFromParent_Done,
     /*  731465 */   // Label 11608: @731465
     /*  731465 */   GIM_Try, /*On fail goto*//*Label 11609*/ GIMT_Encode4(731527), // Rule ID 21702 //
     /*  731470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  731473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731480 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731493 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64),
     /*  731496 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731525 */     GIR_RootConstrainSelectedInstOperands,
     /*  731526 */     // GIR_Coverage, 21702,
     /*  731526 */     GIR_EraseRootFromParent_Done,
     /*  731527 */   // Label 11609: @731527
     /*  731527 */   GIM_Try, /*On fail goto*//*Label 11610*/ GIMT_Encode4(731589), // Rule ID 21718 //
     /*  731532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  731535 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731542 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731544 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731548 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731555 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64),
     /*  731558 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731583 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731587 */     GIR_RootConstrainSelectedInstOperands,
     /*  731588 */     // GIR_Coverage, 21718,
     /*  731588 */     GIR_EraseRootFromParent_Done,
     /*  731589 */   // Label 11610: @731589
     /*  731589 */   GIM_Try, /*On fail goto*//*Label 11611*/ GIMT_Encode4(731651), // Rule ID 21719 //
     /*  731594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  731597 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731604 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731617 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64),
     /*  731620 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731645 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731649 */     GIR_RootConstrainSelectedInstOperands,
     /*  731650 */     // GIR_Coverage, 21719,
     /*  731650 */     GIR_EraseRootFromParent_Done,
     /*  731651 */   // Label 11611: @731651
     /*  731651 */   GIM_Try, /*On fail goto*//*Label 11612*/ GIMT_Encode4(731713), // Rule ID 21720 //
     /*  731656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  731659 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731666 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731668 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731672 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731679 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64),
     /*  731682 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731711 */     GIR_RootConstrainSelectedInstOperands,
     /*  731712 */     // GIR_Coverage, 21720,
     /*  731712 */     GIR_EraseRootFromParent_Done,
     /*  731713 */   // Label 11612: @731713
     /*  731713 */   GIM_Try, /*On fail goto*//*Label 11613*/ GIMT_Encode4(731775), // Rule ID 21721 //
     /*  731718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  731721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731728 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731741 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64),
     /*  731744 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731766 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731773 */     GIR_RootConstrainSelectedInstOperands,
     /*  731774 */     // GIR_Coverage, 21721,
     /*  731774 */     GIR_EraseRootFromParent_Done,
     /*  731775 */   // Label 11613: @731775
     /*  731775 */   GIM_Try, /*On fail goto*//*Label 11614*/ GIMT_Encode4(731837), // Rule ID 21722 //
     /*  731780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  731783 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731790 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  731792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731803 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64 anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64),
     /*  731806 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  731831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731835 */     GIR_RootConstrainSelectedInstOperands,
     /*  731836 */     // GIR_Coverage, 21722,
     /*  731836 */     GIR_EraseRootFromParent_Done,
     /*  731837 */   // Label 11614: @731837
     /*  731837 */   GIM_Try, /*On fail goto*//*Label 11615*/ GIMT_Encode4(731903), // Rule ID 21688 //
     /*  731842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  731845 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  731856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731867 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN),
     /*  731870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  731872 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  731897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731901 */     GIR_RootConstrainSelectedInstOperands,
     /*  731902 */     // GIR_Coverage, 21688,
     /*  731902 */     GIR_EraseRootFromParent_Done,
     /*  731903 */   // Label 11615: @731903
     /*  731903 */   GIM_Try, /*On fail goto*//*Label 11616*/ GIMT_Encode4(731969), // Rule ID 21689 //
     /*  731908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  731911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  731922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731933 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN),
     /*  731936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  731938 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  731940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  731945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  731950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  731955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  731960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  731963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  731967 */     GIR_RootConstrainSelectedInstOperands,
     /*  731968 */     // GIR_Coverage, 21689,
     /*  731968 */     GIR_EraseRootFromParent_Done,
     /*  731969 */   // Label 11616: @731969
     /*  731969 */   GIM_Try, /*On fail goto*//*Label 11617*/ GIMT_Encode4(732035), // Rule ID 21690 //
     /*  731974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  731977 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  731984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  731988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  731992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  731999 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  731999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN),
     /*  732002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732004 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732033 */     GIR_RootConstrainSelectedInstOperands,
     /*  732034 */     // GIR_Coverage, 21690,
     /*  732034 */     GIR_EraseRootFromParent_Done,
     /*  732035 */   // Label 11617: @732035
     /*  732035 */   GIM_Try, /*On fail goto*//*Label 11618*/ GIMT_Encode4(732101), // Rule ID 21691 //
     /*  732040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  732043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732065 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN),
     /*  732068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732070 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732099 */     GIR_RootConstrainSelectedInstOperands,
     /*  732100 */     // GIR_Coverage, 21691,
     /*  732100 */     GIR_EraseRootFromParent_Done,
     /*  732101 */   // Label 11618: @732101
     /*  732101 */   GIM_Try, /*On fail goto*//*Label 11619*/ GIMT_Encode4(732167), // Rule ID 21692 //
     /*  732106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  732109 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732131 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN),
     /*  732134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732136 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732161 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732165 */     GIR_RootConstrainSelectedInstOperands,
     /*  732166 */     // GIR_Coverage, 21692,
     /*  732166 */     GIR_EraseRootFromParent_Done,
     /*  732167 */   // Label 11619: @732167
     /*  732167 */   GIM_Try, /*On fail goto*//*Label 11620*/ GIMT_Encode4(732233), // Rule ID 21708 //
     /*  732172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  732175 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732186 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732190 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732197 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN),
     /*  732200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732202 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732227 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732231 */     GIR_RootConstrainSelectedInstOperands,
     /*  732232 */     // GIR_Coverage, 21708,
     /*  732232 */     GIR_EraseRootFromParent_Done,
     /*  732233 */   // Label 11620: @732233
     /*  732233 */   GIM_Try, /*On fail goto*//*Label 11621*/ GIMT_Encode4(732299), // Rule ID 21709 //
     /*  732238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  732241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732252 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732263 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN),
     /*  732266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732268 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732293 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732297 */     GIR_RootConstrainSelectedInstOperands,
     /*  732298 */     // GIR_Coverage, 21709,
     /*  732298 */     GIR_EraseRootFromParent_Done,
     /*  732299 */   // Label 11621: @732299
     /*  732299 */   GIM_Try, /*On fail goto*//*Label 11622*/ GIMT_Encode4(732365), // Rule ID 21710 //
     /*  732304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  732307 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732329 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN),
     /*  732332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732334 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732363 */     GIR_RootConstrainSelectedInstOperands,
     /*  732364 */     // GIR_Coverage, 21710,
     /*  732364 */     GIR_EraseRootFromParent_Done,
     /*  732365 */   // Label 11622: @732365
     /*  732365 */   GIM_Try, /*On fail goto*//*Label 11623*/ GIMT_Encode4(732431), // Rule ID 21711 //
     /*  732370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  732373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732384 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732395 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN),
     /*  732398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732400 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732429 */     GIR_RootConstrainSelectedInstOperands,
     /*  732430 */     // GIR_Coverage, 21711,
     /*  732430 */     GIR_EraseRootFromParent_Done,
     /*  732431 */   // Label 11623: @732431
     /*  732431 */   GIM_Try, /*On fail goto*//*Label 11624*/ GIMT_Encode4(732497), // Rule ID 21712 //
     /*  732436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  732439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  732450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  732461 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN),
     /*  732464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  732466 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  732473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  732483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  732488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  732491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732495 */     GIR_RootConstrainSelectedInstOperands,
     /*  732496 */     // GIR_Coverage, 21712,
     /*  732496 */     GIR_EraseRootFromParent_Done,
     /*  732497 */   // Label 11624: @732497
     /*  732497 */   GIM_Try, /*On fail goto*//*Label 11625*/ GIMT_Encode4(732554), // Rule ID 21693 //
     /*  732502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  732505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732512 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732525 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET),
     /*  732528 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732552 */     GIR_RootConstrainSelectedInstOperands,
     /*  732553 */     // GIR_Coverage, 21693,
     /*  732553 */     GIR_EraseRootFromParent_Done,
     /*  732554 */   // Label 11625: @732554
     /*  732554 */   GIM_Try, /*On fail goto*//*Label 11626*/ GIMT_Encode4(732611), // Rule ID 21694 //
     /*  732559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  732562 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732569 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732571 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732582 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET),
     /*  732585 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732605 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732609 */     GIR_RootConstrainSelectedInstOperands,
     /*  732610 */     // GIR_Coverage, 21694,
     /*  732610 */     GIR_EraseRootFromParent_Done,
     /*  732611 */   // Label 11626: @732611
     /*  732611 */   GIM_Try, /*On fail goto*//*Label 11627*/ GIMT_Encode4(732668), // Rule ID 21695 //
     /*  732616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  732619 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732626 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732639 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET),
     /*  732642 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732662 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732666 */     GIR_RootConstrainSelectedInstOperands,
     /*  732667 */     // GIR_Coverage, 21695,
     /*  732667 */     GIR_EraseRootFromParent_Done,
     /*  732668 */   // Label 11627: @732668
     /*  732668 */   GIM_Try, /*On fail goto*//*Label 11628*/ GIMT_Encode4(732725), // Rule ID 21696 //
     /*  732673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  732676 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732683 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732696 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET),
     /*  732699 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732723 */     GIR_RootConstrainSelectedInstOperands,
     /*  732724 */     // GIR_Coverage, 21696,
     /*  732724 */     GIR_EraseRootFromParent_Done,
     /*  732725 */   // Label 11628: @732725
     /*  732725 */   GIM_Try, /*On fail goto*//*Label 11629*/ GIMT_Encode4(732782), // Rule ID 21697 //
     /*  732730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  732733 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732740 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732753 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET),
     /*  732756 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732780 */     GIR_RootConstrainSelectedInstOperands,
     /*  732781 */     // GIR_Coverage, 21697,
     /*  732781 */     GIR_EraseRootFromParent_Done,
     /*  732782 */   // Label 11629: @732782
     /*  732782 */   GIM_Try, /*On fail goto*//*Label 11630*/ GIMT_Encode4(732839), // Rule ID 21713 //
     /*  732787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  732790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732797 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732810 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET),
     /*  732813 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732837 */     GIR_RootConstrainSelectedInstOperands,
     /*  732838 */     // GIR_Coverage, 21713,
     /*  732838 */     GIR_EraseRootFromParent_Done,
     /*  732839 */   // Label 11630: @732839
     /*  732839 */   GIM_Try, /*On fail goto*//*Label 11631*/ GIMT_Encode4(732896), // Rule ID 21714 //
     /*  732844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  732847 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732854 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732867 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET),
     /*  732870 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732894 */     GIR_RootConstrainSelectedInstOperands,
     /*  732895 */     // GIR_Coverage, 21714,
     /*  732895 */     GIR_EraseRootFromParent_Done,
     /*  732896 */   // Label 11631: @732896
     /*  732896 */   GIM_Try, /*On fail goto*//*Label 11632*/ GIMT_Encode4(732953), // Rule ID 21715 //
     /*  732901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  732904 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732911 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732924 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET),
     /*  732927 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  732944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  732947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  732951 */     GIR_RootConstrainSelectedInstOperands,
     /*  732952 */     // GIR_Coverage, 21715,
     /*  732952 */     GIR_EraseRootFromParent_Done,
     /*  732953 */   // Label 11632: @732953
     /*  732953 */   GIM_Try, /*On fail goto*//*Label 11633*/ GIMT_Encode4(733010), // Rule ID 21716 //
     /*  732958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  732961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  732968 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  732970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  732974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  732981 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  732981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET),
     /*  732984 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  732986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  732991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  732996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733004 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733008 */     GIR_RootConstrainSelectedInstOperands,
     /*  733009 */     // GIR_Coverage, 21716,
     /*  733009 */     GIR_EraseRootFromParent_Done,
     /*  733010 */   // Label 11633: @733010
     /*  733010 */   GIM_Try, /*On fail goto*//*Label 11634*/ GIMT_Encode4(733067), // Rule ID 21717 //
     /*  733015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  733018 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733025 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733038 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET),
     /*  733041 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733065 */     GIR_RootConstrainSelectedInstOperands,
     /*  733066 */     // GIR_Coverage, 21717,
     /*  733066 */     GIR_EraseRootFromParent_Done,
     /*  733067 */   // Label 11634: @733067
     /*  733067 */   GIM_Try, /*On fail goto*//*Label 11635*/ GIMT_Encode4(733128), // Rule ID 21683 //
     /*  733072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  733075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733097 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN),
     /*  733100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733102 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733122 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733126 */     GIR_RootConstrainSelectedInstOperands,
     /*  733127 */     // GIR_Coverage, 21683,
     /*  733127 */     GIR_EraseRootFromParent_Done,
     /*  733128 */   // Label 11635: @733128
     /*  733128 */   GIM_Try, /*On fail goto*//*Label 11636*/ GIMT_Encode4(733189), // Rule ID 21684 //
     /*  733133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  733136 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733158 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN),
     /*  733161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733163 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733187 */     GIR_RootConstrainSelectedInstOperands,
     /*  733188 */     // GIR_Coverage, 21684,
     /*  733188 */     GIR_EraseRootFromParent_Done,
     /*  733189 */   // Label 11636: @733189
     /*  733189 */   GIM_Try, /*On fail goto*//*Label 11637*/ GIMT_Encode4(733250), // Rule ID 21685 //
     /*  733194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  733197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733208 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733219 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN),
     /*  733222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733224 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733248 */     GIR_RootConstrainSelectedInstOperands,
     /*  733249 */     // GIR_Coverage, 21685,
     /*  733249 */     GIR_EraseRootFromParent_Done,
     /*  733250 */   // Label 11637: @733250
     /*  733250 */   GIM_Try, /*On fail goto*//*Label 11638*/ GIMT_Encode4(733311), // Rule ID 21686 //
     /*  733255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  733258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733280 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN),
     /*  733283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733285 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733309 */     GIR_RootConstrainSelectedInstOperands,
     /*  733310 */     // GIR_Coverage, 21686,
     /*  733310 */     GIR_EraseRootFromParent_Done,
     /*  733311 */   // Label 11638: @733311
     /*  733311 */   GIM_Try, /*On fail goto*//*Label 11639*/ GIMT_Encode4(733372), // Rule ID 21687 //
     /*  733316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  733319 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733341 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN),
     /*  733344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733346 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733370 */     GIR_RootConstrainSelectedInstOperands,
     /*  733371 */     // GIR_Coverage, 21687,
     /*  733371 */     GIR_EraseRootFromParent_Done,
     /*  733372 */   // Label 11639: @733372
     /*  733372 */   GIM_Try, /*On fail goto*//*Label 11640*/ GIMT_Encode4(733433), // Rule ID 21703 //
     /*  733377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode0),
     /*  733380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733391 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733402 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN),
     /*  733405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733407 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733431 */     GIR_RootConstrainSelectedInstOperands,
     /*  733432 */     // GIR_Coverage, 21703,
     /*  733432 */     GIR_EraseRootFromParent_Done,
     /*  733433 */   // Label 11640: @733433
     /*  733433 */   GIM_Try, /*On fail goto*//*Label 11641*/ GIMT_Encode4(733494), // Rule ID 21704 //
     /*  733438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode1),
     /*  733441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733452 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733463 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN),
     /*  733466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733468 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733488 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733492 */     GIR_RootConstrainSelectedInstOperands,
     /*  733493 */     // GIR_Coverage, 21704,
     /*  733493 */     GIR_EraseRootFromParent_Done,
     /*  733494 */   // Label 11641: @733494
     /*  733494 */   GIM_Try, /*On fail goto*//*Label 11642*/ GIMT_Encode4(733555), // Rule ID 21705 //
     /*  733499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode2),
     /*  733502 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733524 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN),
     /*  733527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733529 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733553 */     GIR_RootConstrainSelectedInstOperands,
     /*  733554 */     // GIR_Coverage, 21705,
     /*  733554 */     GIR_EraseRootFromParent_Done,
     /*  733555 */   // Label 11642: @733555
     /*  733555 */   GIM_Try, /*On fail goto*//*Label 11643*/ GIMT_Encode4(733616), // Rule ID 21706 //
     /*  733560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode3),
     /*  733563 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733574 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733578 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733585 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN),
     /*  733588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733590 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733614 */     GIR_RootConstrainSelectedInstOperands,
     /*  733615 */     // GIR_Coverage, 21706,
     /*  733615 */     GIR_EraseRootFromParent_Done,
     /*  733616 */   // Label 11643: @733616
     /*  733616 */   GIM_Try, /*On fail goto*//*Label 11644*/ GIMT_Encode4(733677), // Rule ID 21707 //
     /*  733621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HwMode4),
     /*  733624 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  733631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  733635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  733646 */     // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15624:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  733646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN),
     /*  733649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  733651 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  733653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  733658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  733663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  733668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  733671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733675 */     GIR_RootConstrainSelectedInstOperands,
     /*  733676 */     // GIR_Coverage, 21707,
     /*  733676 */     GIR_EraseRootFromParent_Done,
     /*  733677 */   // Label 11644: @733677
     /*  733677 */   GIM_Try, /*On fail goto*//*Label 11645*/ GIMT_Encode4(733727), // Rule ID 30474 //
     /*  733682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  733685 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733690 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733692 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  733703 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  733703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  733706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  733711 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  733713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  733718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733725 */     GIR_RootConstrainSelectedInstOperands,
     /*  733726 */     // GIR_Coverage, 30474,
     /*  733726 */     GIR_EraseRootFromParent_Done,
     /*  733727 */   // Label 11645: @733727
     /*  733727 */   GIM_Try, /*On fail goto*//*Label 11646*/ GIMT_Encode4(733777), // Rule ID 30475 //
     /*  733732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  733735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733740 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  733753 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  733753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  733756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  733761 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  733763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  733768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733775 */     GIR_RootConstrainSelectedInstOperands,
     /*  733776 */     // GIR_Coverage, 30475,
     /*  733776 */     GIR_EraseRootFromParent_Done,
     /*  733777 */   // Label 11646: @733777
     /*  733777 */   GIM_Try, /*On fail goto*//*Label 11647*/ GIMT_Encode4(733827), // Rule ID 30476 //
     /*  733782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  733785 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733790 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  733803 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  733803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  733806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  733811 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  733813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  733818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733821 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733825 */     GIR_RootConstrainSelectedInstOperands,
     /*  733826 */     // GIR_Coverage, 30476,
     /*  733826 */     GIR_EraseRootFromParent_Done,
     /*  733827 */   // Label 11647: @733827
     /*  733827 */   GIM_Try, /*On fail goto*//*Label 11648*/ GIMT_Encode4(733877), // Rule ID 30477 //
     /*  733832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  733835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733840 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733842 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  733853 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  733853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  733856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  733861 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  733863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  733868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733871 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733875 */     GIR_RootConstrainSelectedInstOperands,
     /*  733876 */     // GIR_Coverage, 30477,
     /*  733876 */     GIR_EraseRootFromParent_Done,
     /*  733877 */   // Label 11648: @733877
     /*  733877 */   GIM_Try, /*On fail goto*//*Label 11649*/ GIMT_Encode4(733927), // Rule ID 30478 //
     /*  733882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  733885 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733890 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733892 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733896 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  733903 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  733903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  733906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  733911 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  733913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  733918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733925 */     GIR_RootConstrainSelectedInstOperands,
     /*  733926 */     // GIR_Coverage, 30478,
     /*  733926 */     GIR_EraseRootFromParent_Done,
     /*  733927 */   // Label 11649: @733927
     /*  733927 */   GIM_Try, /*On fail goto*//*Label 11650*/ GIMT_Encode4(733977), // Rule ID 30480 //
     /*  733932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  733935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733940 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  733953 */     // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f32>>  =>  (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  733953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9),
     /*  733956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  733961 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  733963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  733968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  733971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  733975 */     GIR_RootConstrainSelectedInstOperands,
     /*  733976 */     // GIR_Coverage, 30480,
     /*  733976 */     GIR_EraseRootFromParent_Done,
     /*  733977 */   // Label 11650: @733977
     /*  733977 */   GIM_Try, /*On fail goto*//*Label 11651*/ GIMT_Encode4(734027), // Rule ID 30481 //
     /*  733982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  733985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  733990 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  733992 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  733996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734003 */     // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f32>>  =>  (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  734003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9),
     /*  734006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734011 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734025 */     GIR_RootConstrainSelectedInstOperands,
     /*  734026 */     // GIR_Coverage, 30481,
     /*  734026 */     GIR_EraseRootFromParent_Done,
     /*  734027 */   // Label 11651: @734027
     /*  734027 */   GIM_Try, /*On fail goto*//*Label 11652*/ GIMT_Encode4(734077), // Rule ID 30482 //
     /*  734032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  734035 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  734040 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734042 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734046 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734053 */     // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f32>>  =>  (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  734053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9),
     /*  734056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734061 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734075 */     GIR_RootConstrainSelectedInstOperands,
     /*  734076 */     // GIR_Coverage, 30482,
     /*  734076 */     GIR_EraseRootFromParent_Done,
     /*  734077 */   // Label 11652: @734077
     /*  734077 */   GIM_Try, /*On fail goto*//*Label 11653*/ GIMT_Encode4(734127), // Rule ID 30483 //
     /*  734082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  734085 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  734090 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734092 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734096 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734103 */     // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f32>>  =>  (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  734103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9),
     /*  734106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734111 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734121 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734125 */     GIR_RootConstrainSelectedInstOperands,
     /*  734126 */     // GIR_Coverage, 30483,
     /*  734126 */     GIR_EraseRootFromParent_Done,
     /*  734127 */   // Label 11653: @734127
     /*  734127 */   GIM_Try, /*On fail goto*//*Label 11654*/ GIMT_Encode4(734177), // Rule ID 30484 //
     /*  734132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  734135 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  734140 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734142 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734153 */     // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f32>>  =>  (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  734153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9),
     /*  734156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734161 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734171 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734175 */     GIR_RootConstrainSelectedInstOperands,
     /*  734176 */     // GIR_Coverage, 30484,
     /*  734176 */     GIR_EraseRootFromParent_Done,
     /*  734177 */   // Label 11654: @734177
     /*  734177 */   GIM_Try, /*On fail goto*//*Label 11655*/ GIMT_Encode4(734227), // Rule ID 30486 //
     /*  734182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  734185 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  734190 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734203 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  734203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  734206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734211 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  734221 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734225 */     GIR_RootConstrainSelectedInstOperands,
     /*  734226 */     // GIR_Coverage, 30486,
     /*  734226 */     GIR_EraseRootFromParent_Done,
     /*  734227 */   // Label 11655: @734227
     /*  734227 */   GIM_Try, /*On fail goto*//*Label 11656*/ GIMT_Encode4(734277), // Rule ID 30487 //
     /*  734232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  734235 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  734240 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734246 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734253 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  734253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  734256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734261 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  734271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734275 */     GIR_RootConstrainSelectedInstOperands,
     /*  734276 */     // GIR_Coverage, 30487,
     /*  734276 */     GIR_EraseRootFromParent_Done,
     /*  734277 */   // Label 11656: @734277
     /*  734277 */   GIM_Try, /*On fail goto*//*Label 11657*/ GIMT_Encode4(734327), // Rule ID 30488 //
     /*  734282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  734285 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  734290 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734303 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  734303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  734306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734311 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  734321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734325 */     GIR_RootConstrainSelectedInstOperands,
     /*  734326 */     // GIR_Coverage, 30488,
     /*  734326 */     GIR_EraseRootFromParent_Done,
     /*  734327 */   // Label 11657: @734327
     /*  734327 */   GIM_Try, /*On fail goto*//*Label 11658*/ GIMT_Encode4(734377), // Rule ID 30489 //
     /*  734332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  734335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  734340 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734353 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  734353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  734356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734361 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  734371 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734375 */     GIR_RootConstrainSelectedInstOperands,
     /*  734376 */     // GIR_Coverage, 30489,
     /*  734376 */     GIR_EraseRootFromParent_Done,
     /*  734377 */   // Label 11658: @734377
     /*  734377 */   GIM_Try, /*On fail goto*//*Label 11659*/ GIMT_Encode4(734427), // Rule ID 30490 //
     /*  734382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  734385 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  734390 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734396 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734403 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  734403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
     /*  734406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734411 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  734421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734425 */     GIR_RootConstrainSelectedInstOperands,
     /*  734426 */     // GIR_Coverage, 30490,
     /*  734426 */     GIR_EraseRootFromParent_Done,
     /*  734427 */   // Label 11659: @734427
     /*  734427 */   GIM_Try, /*On fail goto*//*Label 11660*/ GIMT_Encode4(734481), // Rule ID 30473 //
     /*  734432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  734435 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  734440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  734444 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734448 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734455 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f32>>  =>  (DS_MIN_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  734455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32),
     /*  734458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  734460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734465 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734475 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734479 */     GIR_RootConstrainSelectedInstOperands,
     /*  734480 */     // GIR_Coverage, 30473,
     /*  734480 */     GIR_EraseRootFromParent_Done,
     /*  734481 */   // Label 11660: @734481
     /*  734481 */   GIM_Try, /*On fail goto*//*Label 11661*/ GIMT_Encode4(734535), // Rule ID 30479 //
     /*  734486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  734489 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  734494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  734498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734509 */     // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_f32>>  =>  (DS_MIN_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  734509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32_gfx9),
     /*  734512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  734514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734519 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734529 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734533 */     GIR_RootConstrainSelectedInstOperands,
     /*  734534 */     // GIR_Coverage, 30479,
     /*  734534 */     GIR_EraseRootFromParent_Done,
     /*  734535 */   // Label 11661: @734535
     /*  734535 */   GIM_Try, /*On fail goto*//*Label 11662*/ GIMT_Encode4(734589), // Rule ID 30485 //
     /*  734540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  734543 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  734548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  734552 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  734563 */     // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f32>>  =>  (DS_MIN_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  734563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32),
     /*  734566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  734568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  734573 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  734575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  734583 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734587 */     GIR_RootConstrainSelectedInstOperands,
     /*  734588 */     // GIR_Coverage, 30485,
     /*  734588 */     GIR_EraseRootFromParent_Done,
     /*  734589 */   // Label 11662: @734589
     /*  734589 */   GIM_Try, /*On fail goto*//*Label 11663*/ GIMT_Encode4(734648), // Rule ID 13568 //
     /*  734594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode0),
     /*  734597 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734604 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  734617 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  734617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  734620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  734625 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  734632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  734637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  734642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734646 */     GIR_RootConstrainSelectedInstOperands,
     /*  734647 */     // GIR_Coverage, 13568,
     /*  734647 */     GIR_EraseRootFromParent_Done,
     /*  734648 */   // Label 11663: @734648
     /*  734648 */   GIM_Try, /*On fail goto*//*Label 11664*/ GIMT_Encode4(734707), // Rule ID 13569 //
     /*  734653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode1),
     /*  734656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734663 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734665 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  734676 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  734676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  734679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  734684 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  734691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  734696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  734701 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734705 */     GIR_RootConstrainSelectedInstOperands,
     /*  734706 */     // GIR_Coverage, 13569,
     /*  734706 */     GIR_EraseRootFromParent_Done,
     /*  734707 */   // Label 11664: @734707
     /*  734707 */   GIM_Try, /*On fail goto*//*Label 11665*/ GIMT_Encode4(734766), // Rule ID 13570 //
     /*  734712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode2),
     /*  734715 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734722 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734724 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  734735 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  734735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  734738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  734743 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  734750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  734755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  734760 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734764 */     GIR_RootConstrainSelectedInstOperands,
     /*  734765 */     // GIR_Coverage, 13570,
     /*  734765 */     GIR_EraseRootFromParent_Done,
     /*  734766 */   // Label 11665: @734766
     /*  734766 */   GIM_Try, /*On fail goto*//*Label 11666*/ GIMT_Encode4(734825), // Rule ID 13571 //
     /*  734771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode3),
     /*  734774 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734781 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734783 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  734794 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  734794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  734797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  734802 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  734809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  734814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  734819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734823 */     GIR_RootConstrainSelectedInstOperands,
     /*  734824 */     // GIR_Coverage, 13571,
     /*  734824 */     GIR_EraseRootFromParent_Done,
     /*  734825 */   // Label 11666: @734825
     /*  734825 */   GIM_Try, /*On fail goto*//*Label 11667*/ GIMT_Encode4(734884), // Rule ID 13572 //
     /*  734830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode4),
     /*  734833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734840 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734842 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  734853 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  734853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  734856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  734861 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  734868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  734873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  734878 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734882 */     GIR_RootConstrainSelectedInstOperands,
     /*  734883 */     // GIR_Coverage, 13572,
     /*  734883 */     GIR_EraseRootFromParent_Done,
     /*  734884 */   // Label 11667: @734884
     /*  734884 */   GIM_Try, /*On fail goto*//*Label 11668*/ GIMT_Encode4(734947), // Rule ID 13578 //
     /*  734889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  734892 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  734903 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  734914 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  734914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN),
     /*  734917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  734919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  734924 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  734931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  734936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  734941 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734945 */     GIR_RootConstrainSelectedInstOperands,
     /*  734946 */     // GIR_Coverage, 13578,
     /*  734946 */     GIR_EraseRootFromParent_Done,
     /*  734947 */   // Label 11668: @734947
     /*  734947 */   GIM_Try, /*On fail goto*//*Label 11669*/ GIMT_Encode4(734999), // Rule ID 13563 //
     /*  734952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode0),
     /*  734955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  734962 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  734964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  734968 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  734975 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  734975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  734978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  734983 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  734985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  734990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  734993 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  734997 */     GIR_RootConstrainSelectedInstOperands,
     /*  734998 */     // GIR_Coverage, 13563,
     /*  734998 */     GIR_EraseRootFromParent_Done,
     /*  734999 */   // Label 11669: @734999
     /*  734999 */   GIM_Try, /*On fail goto*//*Label 11670*/ GIMT_Encode4(735051), // Rule ID 13564 //
     /*  735004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode1),
     /*  735007 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735014 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735016 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735027 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  735030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735035 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  735045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735049 */     GIR_RootConstrainSelectedInstOperands,
     /*  735050 */     // GIR_Coverage, 13564,
     /*  735050 */     GIR_EraseRootFromParent_Done,
     /*  735051 */   // Label 11670: @735051
     /*  735051 */   GIM_Try, /*On fail goto*//*Label 11671*/ GIMT_Encode4(735103), // Rule ID 13565 //
     /*  735056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode2),
     /*  735059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735066 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735079 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  735082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735087 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  735097 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735101 */     GIR_RootConstrainSelectedInstOperands,
     /*  735102 */     // GIR_Coverage, 13565,
     /*  735102 */     GIR_EraseRootFromParent_Done,
     /*  735103 */   // Label 11671: @735103
     /*  735103 */   GIM_Try, /*On fail goto*//*Label 11672*/ GIMT_Encode4(735155), // Rule ID 13566 //
     /*  735108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode3),
     /*  735111 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735118 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735131 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  735134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735139 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  735149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735153 */     GIR_RootConstrainSelectedInstOperands,
     /*  735154 */     // GIR_Coverage, 13566,
     /*  735154 */     GIR_EraseRootFromParent_Done,
     /*  735155 */   // Label 11672: @735155
     /*  735155 */   GIM_Try, /*On fail goto*//*Label 11673*/ GIMT_Encode4(735207), // Rule ID 13567 //
     /*  735160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode4),
     /*  735163 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735170 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735183 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  735186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735191 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  735201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735205 */     GIR_RootConstrainSelectedInstOperands,
     /*  735206 */     // GIR_Coverage, 13567,
     /*  735206 */     GIR_EraseRootFromParent_Done,
     /*  735207 */   // Label 11673: @735207
     /*  735207 */   GIM_Try, /*On fail goto*//*Label 11674*/ GIMT_Encode4(735263), // Rule ID 13573 //
     /*  735212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode0),
     /*  735215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  735226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735237 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  735240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  735242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735247 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  735257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735261 */     GIR_RootConstrainSelectedInstOperands,
     /*  735262 */     // GIR_Coverage, 13573,
     /*  735262 */     GIR_EraseRootFromParent_Done,
     /*  735263 */   // Label 11674: @735263
     /*  735263 */   GIM_Try, /*On fail goto*//*Label 11675*/ GIMT_Encode4(735319), // Rule ID 13574 //
     /*  735268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode1),
     /*  735271 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  735282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735293 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  735296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  735298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735303 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  735313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735317 */     GIR_RootConstrainSelectedInstOperands,
     /*  735318 */     // GIR_Coverage, 13574,
     /*  735318 */     GIR_EraseRootFromParent_Done,
     /*  735319 */   // Label 11675: @735319
     /*  735319 */   GIM_Try, /*On fail goto*//*Label 11676*/ GIMT_Encode4(735375), // Rule ID 13575 //
     /*  735324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode2),
     /*  735327 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  735338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735349 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  735352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  735354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735359 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  735369 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735373 */     GIR_RootConstrainSelectedInstOperands,
     /*  735374 */     // GIR_Coverage, 13575,
     /*  735374 */     GIR_EraseRootFromParent_Done,
     /*  735375 */   // Label 11676: @735375
     /*  735375 */   GIM_Try, /*On fail goto*//*Label 11677*/ GIMT_Encode4(735431), // Rule ID 13576 //
     /*  735380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode3),
     /*  735383 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  735394 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735398 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735405 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  735408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  735410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735415 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  735425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735429 */     GIR_RootConstrainSelectedInstOperands,
     /*  735430 */     // GIR_Coverage, 13576,
     /*  735430 */     GIR_EraseRootFromParent_Done,
     /*  735431 */   // Label 11677: @735431
     /*  735431 */   GIM_Try, /*On fail goto*//*Label 11678*/ GIMT_Encode4(735487), // Rule ID 13577 //
     /*  735436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus_HwMode4),
     /*  735439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  735450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  735461 */     // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  735461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  735464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  735466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  735471 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  735478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  735481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735485 */     GIR_RootConstrainSelectedInstOperands,
     /*  735486 */     // GIR_Coverage, 13577,
     /*  735486 */     GIR_EraseRootFromParent_Done,
     /*  735487 */   // Label 11678: @735487
     /*  735487 */   GIM_Try, /*On fail goto*//*Label 11679*/ GIMT_Encode4(735547), // Rule ID 10953 //
     /*  735492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode0),
     /*  735495 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735503 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735505 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735509 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735516 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735524 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735545 */     GIR_RootConstrainSelectedInstOperands,
     /*  735546 */     // GIR_Coverage, 10953,
     /*  735546 */     GIR_EraseRootFromParent_Done,
     /*  735547 */   // Label 11679: @735547
     /*  735547 */   GIM_Try, /*On fail goto*//*Label 11680*/ GIMT_Encode4(735607), // Rule ID 10954 //
     /*  735552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode1),
     /*  735555 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735563 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735576 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735584 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735605 */     GIR_RootConstrainSelectedInstOperands,
     /*  735606 */     // GIR_Coverage, 10954,
     /*  735606 */     GIR_EraseRootFromParent_Done,
     /*  735607 */   // Label 11680: @735607
     /*  735607 */   GIM_Try, /*On fail goto*//*Label 11681*/ GIMT_Encode4(735667), // Rule ID 10955 //
     /*  735612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode2),
     /*  735615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735623 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735636 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735644 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735665 */     GIR_RootConstrainSelectedInstOperands,
     /*  735666 */     // GIR_Coverage, 10955,
     /*  735666 */     GIR_EraseRootFromParent_Done,
     /*  735667 */   // Label 11681: @735667
     /*  735667 */   GIM_Try, /*On fail goto*//*Label 11682*/ GIMT_Encode4(735727), // Rule ID 10956 //
     /*  735672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode3),
     /*  735675 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735683 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735696 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735704 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735725 */     GIR_RootConstrainSelectedInstOperands,
     /*  735726 */     // GIR_Coverage, 10956,
     /*  735726 */     GIR_EraseRootFromParent_Done,
     /*  735727 */   // Label 11682: @735727
     /*  735727 */   GIM_Try, /*On fail goto*//*Label 11683*/ GIMT_Encode4(735787), // Rule ID 10957 //
     /*  735732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode4),
     /*  735735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735743 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735756 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735764 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735785 */     GIR_RootConstrainSelectedInstOperands,
     /*  735786 */     // GIR_Coverage, 10957,
     /*  735786 */     GIR_EraseRootFromParent_Done,
     /*  735787 */   // Label 11683: @735787
     /*  735787 */   GIM_Try, /*On fail goto*//*Label 11684*/ GIMT_Encode4(735846), // Rule ID 11509 //
     /*  735792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode0),
     /*  735795 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735802 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735815 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735823 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735844 */     GIR_RootConstrainSelectedInstOperands,
     /*  735845 */     // GIR_Coverage, 11509,
     /*  735845 */     GIR_EraseRootFromParent_Done,
     /*  735846 */   // Label 11684: @735846
     /*  735846 */   GIM_Try, /*On fail goto*//*Label 11685*/ GIMT_Encode4(735905), // Rule ID 11510 //
     /*  735851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode1),
     /*  735854 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735861 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735874 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735882 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735903 */     GIR_RootConstrainSelectedInstOperands,
     /*  735904 */     // GIR_Coverage, 11510,
     /*  735904 */     GIR_EraseRootFromParent_Done,
     /*  735905 */   // Label 11685: @735905
     /*  735905 */   GIM_Try, /*On fail goto*//*Label 11686*/ GIMT_Encode4(735964), // Rule ID 11511 //
     /*  735910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode2),
     /*  735913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735920 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735933 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  735941 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  735943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  735948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  735953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  735958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  735962 */     GIR_RootConstrainSelectedInstOperands,
     /*  735963 */     // GIR_Coverage, 11511,
     /*  735963 */     GIR_EraseRootFromParent_Done,
     /*  735964 */   // Label 11686: @735964
     /*  735964 */   GIM_Try, /*On fail goto*//*Label 11687*/ GIMT_Encode4(736023), // Rule ID 11512 //
     /*  735969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode3),
     /*  735972 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  735979 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  735981 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  735985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  735992 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  735992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  735995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736000 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736021 */     GIR_RootConstrainSelectedInstOperands,
     /*  736022 */     // GIR_Coverage, 11512,
     /*  736022 */     GIR_EraseRootFromParent_Done,
     /*  736023 */   // Label 11687: @736023
     /*  736023 */   GIM_Try, /*On fail goto*//*Label 11688*/ GIMT_Encode4(736082), // Rule ID 11513 //
     /*  736028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode_HwMode4),
     /*  736031 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736038 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736040 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736044 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  736051 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  736054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736059 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736080 */     GIR_RootConstrainSelectedInstOperands,
     /*  736081 */     // GIR_Coverage, 11513,
     /*  736081 */     GIR_EraseRootFromParent_Done,
     /*  736082 */   // Label 11688: @736082
     /*  736082 */   GIM_Try, /*On fail goto*//*Label 11689*/ GIMT_Encode4(736142), // Rule ID 13606 //
     /*  736087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode0),
     /*  736090 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736098 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  736111 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  736114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736119 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736140 */     GIR_RootConstrainSelectedInstOperands,
     /*  736141 */     // GIR_Coverage, 13606,
     /*  736141 */     GIR_EraseRootFromParent_Done,
     /*  736142 */   // Label 11689: @736142
     /*  736142 */   GIM_Try, /*On fail goto*//*Label 11690*/ GIMT_Encode4(736202), // Rule ID 13607 //
     /*  736147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode1),
     /*  736150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736158 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  736171 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  736174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736179 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736196 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736200 */     GIR_RootConstrainSelectedInstOperands,
     /*  736201 */     // GIR_Coverage, 13607,
     /*  736201 */     GIR_EraseRootFromParent_Done,
     /*  736202 */   // Label 11690: @736202
     /*  736202 */   GIM_Try, /*On fail goto*//*Label 11691*/ GIMT_Encode4(736262), // Rule ID 13608 //
     /*  736207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode2),
     /*  736210 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736218 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  736231 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  736234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736239 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736260 */     GIR_RootConstrainSelectedInstOperands,
     /*  736261 */     // GIR_Coverage, 13608,
     /*  736261 */     GIR_EraseRootFromParent_Done,
     /*  736262 */   // Label 11691: @736262
     /*  736262 */   GIM_Try, /*On fail goto*//*Label 11692*/ GIMT_Encode4(736322), // Rule ID 13609 //
     /*  736267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode3),
     /*  736270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736278 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  736291 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  736294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736299 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736320 */     GIR_RootConstrainSelectedInstOperands,
     /*  736321 */     // GIR_Coverage, 13609,
     /*  736321 */     GIR_EraseRootFromParent_Done,
     /*  736322 */   // Label 11692: @736322
     /*  736322 */   GIM_Try, /*On fail goto*//*Label 11693*/ GIMT_Encode4(736382), // Rule ID 13610 //
     /*  736327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11_HwMode4),
     /*  736330 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736338 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  736351 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  736354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736359 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736376 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736380 */     GIR_RootConstrainSelectedInstOperands,
     /*  736381 */     // GIR_Coverage, 13610,
     /*  736381 */     GIR_EraseRootFromParent_Done,
     /*  736382 */   // Label 11693: @736382
     /*  736382 */   GIM_Try, /*On fail goto*//*Label 11694*/ GIMT_Encode4(736446), // Rule ID 10947 //
     /*  736387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode),
     /*  736390 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  736402 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  736413 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR_RTN),
     /*  736416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  736418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736423 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736444 */     GIR_RootConstrainSelectedInstOperands,
     /*  736445 */     // GIR_Coverage, 10947,
     /*  736445 */     GIR_EraseRootFromParent_Done,
     /*  736446 */   // Label 11694: @736446
     /*  736446 */   GIM_Try, /*On fail goto*//*Label 11695*/ GIMT_Encode4(736509), // Rule ID 11503 //
     /*  736451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGVSMode),
     /*  736454 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  736465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  736476 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR_RTN),
     /*  736479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  736481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736486 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736507 */     GIR_RootConstrainSelectedInstOperands,
     /*  736508 */     // GIR_Coverage, 11503,
     /*  736508 */     GIR_EraseRootFromParent_Done,
     /*  736509 */   // Label 11695: @736509
     /*  736509 */   GIM_Try, /*On fail goto*//*Label 11696*/ GIMT_Encode4(736573), // Rule ID 13600 //
     /*  736514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX7GFX10GFX11),
     /*  736517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  736529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736533 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  736540 */     // (atomic_load_fmin:{ *:[f32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  736540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR_RTN),
     /*  736543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  736545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  736550 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  736557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  736562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  736567 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736571 */     GIR_RootConstrainSelectedInstOperands,
     /*  736572 */     // GIR_Coverage, 13600,
     /*  736572 */     GIR_EraseRootFromParent_Done,
     /*  736573 */   // Label 11696: @736573
     /*  736573 */   GIM_Try, /*On fail goto*//*Label 11697*/ GIMT_Encode4(736626), // Rule ID 10948 //
     /*  736578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  736581 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736589 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736602 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736610 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736620 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736624 */     GIR_RootConstrainSelectedInstOperands,
     /*  736625 */     // GIR_Coverage, 10948,
     /*  736625 */     GIR_EraseRootFromParent_Done,
     /*  736626 */   // Label 11697: @736626
     /*  736626 */   GIM_Try, /*On fail goto*//*Label 11698*/ GIMT_Encode4(736679), // Rule ID 10949 //
     /*  736631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  736634 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736642 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736644 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736655 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736663 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736677 */     GIR_RootConstrainSelectedInstOperands,
     /*  736678 */     // GIR_Coverage, 10949,
     /*  736678 */     GIR_EraseRootFromParent_Done,
     /*  736679 */   // Label 11698: @736679
     /*  736679 */   GIM_Try, /*On fail goto*//*Label 11699*/ GIMT_Encode4(736732), // Rule ID 10950 //
     /*  736684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  736687 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736695 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736697 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736708 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736716 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736730 */     GIR_RootConstrainSelectedInstOperands,
     /*  736731 */     // GIR_Coverage, 10950,
     /*  736731 */     GIR_EraseRootFromParent_Done,
     /*  736732 */   // Label 11699: @736732
     /*  736732 */   GIM_Try, /*On fail goto*//*Label 11700*/ GIMT_Encode4(736785), // Rule ID 10951 //
     /*  736737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  736740 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736748 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736754 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736761 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736769 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736783 */     GIR_RootConstrainSelectedInstOperands,
     /*  736784 */     // GIR_Coverage, 10951,
     /*  736784 */     GIR_EraseRootFromParent_Done,
     /*  736785 */   // Label 11700: @736785
     /*  736785 */   GIM_Try, /*On fail goto*//*Label 11701*/ GIMT_Encode4(736838), // Rule ID 10952 //
     /*  736790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  736793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736801 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736814 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736822 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736836 */     GIR_RootConstrainSelectedInstOperands,
     /*  736837 */     // GIR_Coverage, 10952,
     /*  736837 */     GIR_EraseRootFromParent_Done,
     /*  736838 */   // Label 11701: @736838
     /*  736838 */   GIM_Try, /*On fail goto*//*Label 11702*/ GIMT_Encode4(736890), // Rule ID 11504 //
     /*  736843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  736846 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736853 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736855 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736866 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736874 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736888 */     GIR_RootConstrainSelectedInstOperands,
     /*  736889 */     // GIR_Coverage, 11504,
     /*  736889 */     GIR_EraseRootFromParent_Done,
     /*  736890 */   // Label 11702: @736890
     /*  736890 */   GIM_Try, /*On fail goto*//*Label 11703*/ GIMT_Encode4(736942), // Rule ID 11505 //
     /*  736895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  736898 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736905 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736918 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736921 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736926 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736940 */     GIR_RootConstrainSelectedInstOperands,
     /*  736941 */     // GIR_Coverage, 11505,
     /*  736941 */     GIR_EraseRootFromParent_Done,
     /*  736942 */   // Label 11703: @736942
     /*  736942 */   GIM_Try, /*On fail goto*//*Label 11704*/ GIMT_Encode4(736994), // Rule ID 11506 //
     /*  736947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  736950 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  736957 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  736959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  736963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  736970 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  736970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  736973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  736978 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  736980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  736985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  736988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  736992 */     GIR_RootConstrainSelectedInstOperands,
     /*  736993 */     // GIR_Coverage, 11506,
     /*  736993 */     GIR_EraseRootFromParent_Done,
     /*  736994 */   // Label 11704: @736994
     /*  736994 */   GIM_Try, /*On fail goto*//*Label 11705*/ GIMT_Encode4(737046), // Rule ID 11507 //
     /*  736999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  737002 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737009 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737022 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737030 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737044 */     GIR_RootConstrainSelectedInstOperands,
     /*  737045 */     // GIR_Coverage, 11507,
     /*  737045 */     GIR_EraseRootFromParent_Done,
     /*  737046 */   // Label 11705: @737046
     /*  737046 */   GIM_Try, /*On fail goto*//*Label 11706*/ GIMT_Encode4(737098), // Rule ID 11508 //
     /*  737051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  737054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737061 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737074 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737082 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737096 */     GIR_RootConstrainSelectedInstOperands,
     /*  737097 */     // GIR_Coverage, 11508,
     /*  737097 */     GIR_EraseRootFromParent_Done,
     /*  737098 */   // Label 11706: @737098
     /*  737098 */   GIM_Try, /*On fail goto*//*Label 11707*/ GIMT_Encode4(737151), // Rule ID 13601 //
     /*  737103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode0),
     /*  737106 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737114 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737120 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737127 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737135 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737145 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737149 */     GIR_RootConstrainSelectedInstOperands,
     /*  737150 */     // GIR_Coverage, 13601,
     /*  737150 */     GIR_EraseRootFromParent_Done,
     /*  737151 */   // Label 11707: @737151
     /*  737151 */   GIM_Try, /*On fail goto*//*Label 11708*/ GIMT_Encode4(737204), // Rule ID 13602 //
     /*  737156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode1),
     /*  737159 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737167 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737180 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737188 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737202 */     GIR_RootConstrainSelectedInstOperands,
     /*  737203 */     // GIR_Coverage, 13602,
     /*  737203 */     GIR_EraseRootFromParent_Done,
     /*  737204 */   // Label 11708: @737204
     /*  737204 */   GIM_Try, /*On fail goto*//*Label 11709*/ GIMT_Encode4(737257), // Rule ID 13603 //
     /*  737209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode2),
     /*  737212 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737220 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737233 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737241 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737255 */     GIR_RootConstrainSelectedInstOperands,
     /*  737256 */     // GIR_Coverage, 13603,
     /*  737256 */     GIR_EraseRootFromParent_Done,
     /*  737257 */   // Label 11709: @737257
     /*  737257 */   GIM_Try, /*On fail goto*//*Label 11710*/ GIMT_Encode4(737310), // Rule ID 13604 //
     /*  737262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode3),
     /*  737265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737273 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737286 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737294 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737308 */     GIR_RootConstrainSelectedInstOperands,
     /*  737309 */     // GIR_Coverage, 13604,
     /*  737309 */     GIR_EraseRootFromParent_Done,
     /*  737310 */   // Label 11710: @737310
     /*  737310 */   GIM_Try, /*On fail goto*//*Label 11711*/ GIMT_Encode4(737363), // Rule ID 13605 //
     /*  737315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode4),
     /*  737318 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737326 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  737328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737339 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  737342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737347 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  737357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737361 */     GIR_RootConstrainSelectedInstOperands,
     /*  737362 */     // GIR_Coverage, 13605,
     /*  737362 */     GIR_EraseRootFromParent_Done,
     /*  737363 */   // Label 11711: @737363
     /*  737363 */   GIM_Try, /*On fail goto*//*Label 11712*/ GIMT_Encode4(737420), // Rule ID 10942 //
     /*  737368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  737371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737383 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737394 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737404 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737418 */     GIR_RootConstrainSelectedInstOperands,
     /*  737419 */     // GIR_Coverage, 10942,
     /*  737419 */     GIR_EraseRootFromParent_Done,
     /*  737420 */   // Label 11712: @737420
     /*  737420 */   GIM_Try, /*On fail goto*//*Label 11713*/ GIMT_Encode4(737477), // Rule ID 10943 //
     /*  737425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  737428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737451 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737461 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737471 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737475 */     GIR_RootConstrainSelectedInstOperands,
     /*  737476 */     // GIR_Coverage, 10943,
     /*  737476 */     GIR_EraseRootFromParent_Done,
     /*  737477 */   // Label 11713: @737477
     /*  737477 */   GIM_Try, /*On fail goto*//*Label 11714*/ GIMT_Encode4(737534), // Rule ID 10944 //
     /*  737482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  737485 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737497 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737508 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737518 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737528 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737532 */     GIR_RootConstrainSelectedInstOperands,
     /*  737533 */     // GIR_Coverage, 10944,
     /*  737533 */     GIR_EraseRootFromParent_Done,
     /*  737534 */   // Label 11714: @737534
     /*  737534 */   GIM_Try, /*On fail goto*//*Label 11715*/ GIMT_Encode4(737591), // Rule ID 10945 //
     /*  737539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  737542 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737554 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737558 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737565 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737575 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737585 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737589 */     GIR_RootConstrainSelectedInstOperands,
     /*  737590 */     // GIR_Coverage, 10945,
     /*  737590 */     GIR_EraseRootFromParent_Done,
     /*  737591 */   // Label 11715: @737591
     /*  737591 */   GIM_Try, /*On fail goto*//*Label 11716*/ GIMT_Encode4(737648), // Rule ID 10946 //
     /*  737596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  737599 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737611 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737622 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737632 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737646 */     GIR_RootConstrainSelectedInstOperands,
     /*  737647 */     // GIR_Coverage, 10946,
     /*  737647 */     GIR_EraseRootFromParent_Done,
     /*  737648 */   // Label 11716: @737648
     /*  737648 */   GIM_Try, /*On fail goto*//*Label 11717*/ GIMT_Encode4(737704), // Rule ID 11498 //
     /*  737653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode0),
     /*  737656 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737667 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737671 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737678 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737688 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737702 */     GIR_RootConstrainSelectedInstOperands,
     /*  737703 */     // GIR_Coverage, 11498,
     /*  737703 */     GIR_EraseRootFromParent_Done,
     /*  737704 */   // Label 11717: @737704
     /*  737704 */   GIM_Try, /*On fail goto*//*Label 11718*/ GIMT_Encode4(737760), // Rule ID 11499 //
     /*  737709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode1),
     /*  737712 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737723 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737734 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737744 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737758 */     GIR_RootConstrainSelectedInstOperands,
     /*  737759 */     // GIR_Coverage, 11499,
     /*  737759 */     GIR_EraseRootFromParent_Done,
     /*  737760 */   // Label 11718: @737760
     /*  737760 */   GIM_Try, /*On fail goto*//*Label 11719*/ GIMT_Encode4(737816), // Rule ID 11500 //
     /*  737765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode2),
     /*  737768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737779 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737783 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737790 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737800 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737810 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737814 */     GIR_RootConstrainSelectedInstOperands,
     /*  737815 */     // GIR_Coverage, 11500,
     /*  737815 */     GIR_EraseRootFromParent_Done,
     /*  737816 */   // Label 11719: @737816
     /*  737816 */   GIM_Try, /*On fail goto*//*Label 11720*/ GIMT_Encode4(737872), // Rule ID 11501 //
     /*  737821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode3),
     /*  737824 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737835 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737846 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737856 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737870 */     GIR_RootConstrainSelectedInstOperands,
     /*  737871 */     // GIR_Coverage, 11501,
     /*  737871 */     GIR_EraseRootFromParent_Done,
     /*  737872 */   // Label 11720: @737872
     /*  737872 */   GIM_Try, /*On fail goto*//*Label 11721*/ GIMT_Encode4(737928), // Rule ID 11502 //
     /*  737877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HwMode4),
     /*  737880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737902 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737912 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737922 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737926 */     GIR_RootConstrainSelectedInstOperands,
     /*  737927 */     // GIR_Coverage, 11502,
     /*  737927 */     GIR_EraseRootFromParent_Done,
     /*  737928 */   // Label 11721: @737928
     /*  737928 */   GIM_Try, /*On fail goto*//*Label 11722*/ GIMT_Encode4(737985), // Rule ID 13595 //
     /*  737933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode0),
     /*  737936 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  737944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  737948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  737952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  737959 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  737959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  737962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  737964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  737969 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  737971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  737976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  737979 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  737983 */     GIR_RootConstrainSelectedInstOperands,
     /*  737984 */     // GIR_Coverage, 13595,
     /*  737984 */     GIR_EraseRootFromParent_Done,
     /*  737985 */   // Label 11722: @737985
     /*  737985 */   GIM_Try, /*On fail goto*//*Label 11723*/ GIMT_Encode4(738042), // Rule ID 13596 //
     /*  737990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode1),
     /*  737993 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  738005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  738016 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  738016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  738019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  738021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  738026 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  738028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  738033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  738036 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738040 */     GIR_RootConstrainSelectedInstOperands,
     /*  738041 */     // GIR_Coverage, 13596,
     /*  738041 */     GIR_EraseRootFromParent_Done,
     /*  738042 */   // Label 11723: @738042
     /*  738042 */   GIM_Try, /*On fail goto*//*Label 11724*/ GIMT_Encode4(738099), // Rule ID 13597 //
     /*  738047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode2),
     /*  738050 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  738062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  738073 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  738073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  738076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  738078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  738083 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  738085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  738090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  738093 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738097 */     GIR_RootConstrainSelectedInstOperands,
     /*  738098 */     // GIR_Coverage, 13597,
     /*  738098 */     GIR_EraseRootFromParent_Done,
     /*  738099 */   // Label 11724: @738099
     /*  738099 */   GIM_Try, /*On fail goto*//*Label 11725*/ GIMT_Encode4(738156), // Rule ID 13598 //
     /*  738104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode3),
     /*  738107 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  738119 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738123 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  738130 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  738130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  738133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  738135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  738140 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  738142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  738147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  738150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738154 */     GIR_RootConstrainSelectedInstOperands,
     /*  738155 */     // GIR_Coverage, 13598,
     /*  738155 */     GIR_EraseRootFromParent_Done,
     /*  738156 */   // Label 11725: @738156
     /*  738156 */   GIM_Try, /*On fail goto*//*Label 11726*/ GIMT_Encode4(738213), // Rule ID 13599 //
     /*  738161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX10GFX11_HwMode4),
     /*  738164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  738176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738180 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  738187 */     // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  738187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  738190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  738192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  738197 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  738199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  738204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  738207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738211 */     GIR_RootConstrainSelectedInstOperands,
     /*  738212 */     // GIR_Coverage, 13599,
     /*  738212 */     GIR_EraseRootFromParent_Done,
     /*  738213 */   // Label 11726: @738213
     /*  738213 */   GIM_Reject,
     /*  738214 */ // Label 11604: @738214
     /*  738214 */ GIM_Reject,
     /*  738215 */ // Label 11602: @738215
     /*  738215 */ GIM_Try, /*On fail goto*//*Label 11727*/ GIMT_Encode4(745714),
     /*  738220 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  738223 */   GIM_Try, /*On fail goto*//*Label 11728*/ GIMT_Encode4(738285), // Rule ID 21778 //
     /*  738228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  738231 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738238 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738244 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738251 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64),
     /*  738254 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738283 */     GIR_RootConstrainSelectedInstOperands,
     /*  738284 */     // GIR_Coverage, 21778,
     /*  738284 */     GIR_EraseRootFromParent_Done,
     /*  738285 */   // Label 11728: @738285
     /*  738285 */   GIM_Try, /*On fail goto*//*Label 11729*/ GIMT_Encode4(738347), // Rule ID 21779 //
     /*  738290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  738293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738300 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738313 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64),
     /*  738316 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738345 */     GIR_RootConstrainSelectedInstOperands,
     /*  738346 */     // GIR_Coverage, 21779,
     /*  738346 */     GIR_EraseRootFromParent_Done,
     /*  738347 */   // Label 11729: @738347
     /*  738347 */   GIM_Try, /*On fail goto*//*Label 11730*/ GIMT_Encode4(738409), // Rule ID 21780 //
     /*  738352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  738355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738362 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738375 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64),
     /*  738378 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738400 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738403 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738407 */     GIR_RootConstrainSelectedInstOperands,
     /*  738408 */     // GIR_Coverage, 21780,
     /*  738408 */     GIR_EraseRootFromParent_Done,
     /*  738409 */   // Label 11730: @738409
     /*  738409 */   GIM_Try, /*On fail goto*//*Label 11731*/ GIMT_Encode4(738471), // Rule ID 21781 //
     /*  738414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  738417 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738424 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738430 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738437 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64),
     /*  738440 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738465 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738469 */     GIR_RootConstrainSelectedInstOperands,
     /*  738470 */     // GIR_Coverage, 21781,
     /*  738470 */     GIR_EraseRootFromParent_Done,
     /*  738471 */   // Label 11731: @738471
     /*  738471 */   GIM_Try, /*On fail goto*//*Label 11732*/ GIMT_Encode4(738533), // Rule ID 21782 //
     /*  738476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  738479 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738486 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738499 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64),
     /*  738502 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738531 */     GIR_RootConstrainSelectedInstOperands,
     /*  738532 */     // GIR_Coverage, 21782,
     /*  738532 */     GIR_EraseRootFromParent_Done,
     /*  738533 */   // Label 11732: @738533
     /*  738533 */   GIM_Try, /*On fail goto*//*Label 11733*/ GIMT_Encode4(738595), // Rule ID 21798 //
     /*  738538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  738541 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738548 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738550 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738561 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64),
     /*  738564 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738593 */     GIR_RootConstrainSelectedInstOperands,
     /*  738594 */     // GIR_Coverage, 21798,
     /*  738594 */     GIR_EraseRootFromParent_Done,
     /*  738595 */   // Label 11733: @738595
     /*  738595 */   GIM_Try, /*On fail goto*//*Label 11734*/ GIMT_Encode4(738657), // Rule ID 21799 //
     /*  738600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  738603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738610 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738623 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64),
     /*  738626 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738655 */     GIR_RootConstrainSelectedInstOperands,
     /*  738656 */     // GIR_Coverage, 21799,
     /*  738656 */     GIR_EraseRootFromParent_Done,
     /*  738657 */   // Label 11734: @738657
     /*  738657 */   GIM_Try, /*On fail goto*//*Label 11735*/ GIMT_Encode4(738719), // Rule ID 21800 //
     /*  738662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  738665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738672 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738685 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64),
     /*  738688 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738717 */     GIR_RootConstrainSelectedInstOperands,
     /*  738718 */     // GIR_Coverage, 21800,
     /*  738718 */     GIR_EraseRootFromParent_Done,
     /*  738719 */   // Label 11735: @738719
     /*  738719 */   GIM_Try, /*On fail goto*//*Label 11736*/ GIMT_Encode4(738781), // Rule ID 21801 //
     /*  738724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  738727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738734 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738747 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64),
     /*  738750 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738779 */     GIR_RootConstrainSelectedInstOperands,
     /*  738780 */     // GIR_Coverage, 21801,
     /*  738780 */     GIR_EraseRootFromParent_Done,
     /*  738781 */   // Label 11736: @738781
     /*  738781 */   GIM_Try, /*On fail goto*//*Label 11737*/ GIMT_Encode4(738843), // Rule ID 21802 //
     /*  738786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  738789 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738796 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  738798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738809 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64 anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64),
     /*  738812 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  738837 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738841 */     GIR_RootConstrainSelectedInstOperands,
     /*  738842 */     // GIR_Coverage, 21802,
     /*  738842 */     GIR_EraseRootFromParent_Done,
     /*  738843 */   // Label 11737: @738843
     /*  738843 */   GIM_Try, /*On fail goto*//*Label 11738*/ GIMT_Encode4(738909), // Rule ID 21768 //
     /*  738848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  738851 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  738862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738873 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64_RTN),
     /*  738876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  738878 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738900 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  738903 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738907 */     GIR_RootConstrainSelectedInstOperands,
     /*  738908 */     // GIR_Coverage, 21768,
     /*  738908 */     GIR_EraseRootFromParent_Done,
     /*  738909 */   // Label 11738: @738909
     /*  738909 */   GIM_Try, /*On fail goto*//*Label 11739*/ GIMT_Encode4(738975), // Rule ID 21769 //
     /*  738914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  738917 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  738928 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738932 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  738939 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  738939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64_RTN),
     /*  738942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  738944 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  738946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  738951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  738956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  738961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  738966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  738969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  738973 */     GIR_RootConstrainSelectedInstOperands,
     /*  738974 */     // GIR_Coverage, 21769,
     /*  738974 */     GIR_EraseRootFromParent_Done,
     /*  738975 */   // Label 11739: @738975
     /*  738975 */   GIM_Try, /*On fail goto*//*Label 11740*/ GIMT_Encode4(739041), // Rule ID 21770 //
     /*  738980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  738983 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  738990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  738994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  738998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739005 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64_RTN),
     /*  739008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739010 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739035 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739039 */     GIR_RootConstrainSelectedInstOperands,
     /*  739040 */     // GIR_Coverage, 21770,
     /*  739040 */     GIR_EraseRootFromParent_Done,
     /*  739041 */   // Label 11740: @739041
     /*  739041 */   GIM_Try, /*On fail goto*//*Label 11741*/ GIMT_Encode4(739107), // Rule ID 21771 //
     /*  739046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  739049 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739071 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64_RTN),
     /*  739074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739076 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739105 */     GIR_RootConstrainSelectedInstOperands,
     /*  739106 */     // GIR_Coverage, 21771,
     /*  739106 */     GIR_EraseRootFromParent_Done,
     /*  739107 */   // Label 11741: @739107
     /*  739107 */   GIM_Try, /*On fail goto*//*Label 11742*/ GIMT_Encode4(739173), // Rule ID 21772 //
     /*  739112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  739115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739137 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64_RTN),
     /*  739140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739142 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739171 */     GIR_RootConstrainSelectedInstOperands,
     /*  739172 */     // GIR_Coverage, 21772,
     /*  739172 */     GIR_EraseRootFromParent_Done,
     /*  739173 */   // Label 11742: @739173
     /*  739173 */   GIM_Try, /*On fail goto*//*Label 11743*/ GIMT_Encode4(739239), // Rule ID 21788 //
     /*  739178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  739181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739203 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN),
     /*  739206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739208 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739237 */     GIR_RootConstrainSelectedInstOperands,
     /*  739238 */     // GIR_Coverage, 21788,
     /*  739238 */     GIR_EraseRootFromParent_Done,
     /*  739239 */   // Label 11743: @739239
     /*  739239 */   GIM_Try, /*On fail goto*//*Label 11744*/ GIMT_Encode4(739305), // Rule ID 21789 //
     /*  739244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  739247 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739269 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN),
     /*  739272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739274 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739303 */     GIR_RootConstrainSelectedInstOperands,
     /*  739304 */     // GIR_Coverage, 21789,
     /*  739304 */     GIR_EraseRootFromParent_Done,
     /*  739305 */   // Label 11744: @739305
     /*  739305 */   GIM_Try, /*On fail goto*//*Label 11745*/ GIMT_Encode4(739371), // Rule ID 21790 //
     /*  739310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  739313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739335 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN),
     /*  739338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739340 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739365 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739369 */     GIR_RootConstrainSelectedInstOperands,
     /*  739370 */     // GIR_Coverage, 21790,
     /*  739370 */     GIR_EraseRootFromParent_Done,
     /*  739371 */   // Label 11745: @739371
     /*  739371 */   GIM_Try, /*On fail goto*//*Label 11746*/ GIMT_Encode4(739437), // Rule ID 21791 //
     /*  739376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  739379 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739394 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739401 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN),
     /*  739404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739406 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739435 */     GIR_RootConstrainSelectedInstOperands,
     /*  739436 */     // GIR_Coverage, 21791,
     /*  739436 */     GIR_EraseRootFromParent_Done,
     /*  739437 */   // Label 11746: @739437
     /*  739437 */   GIM_Try, /*On fail goto*//*Label 11747*/ GIMT_Encode4(739503), // Rule ID 21792 //
     /*  739442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  739445 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  739456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  739467 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN),
     /*  739470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  739472 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  739479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  739489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  739494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  739497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739501 */     GIR_RootConstrainSelectedInstOperands,
     /*  739502 */     // GIR_Coverage, 21792,
     /*  739502 */     GIR_EraseRootFromParent_Done,
     /*  739503 */   // Label 11747: @739503
     /*  739503 */   GIM_Try, /*On fail goto*//*Label 11748*/ GIMT_Encode4(739560), // Rule ID 21773 //
     /*  739508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  739511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739518 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739531 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET),
     /*  739534 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739558 */     GIR_RootConstrainSelectedInstOperands,
     /*  739559 */     // GIR_Coverage, 21773,
     /*  739559 */     GIR_EraseRootFromParent_Done,
     /*  739560 */   // Label 11748: @739560
     /*  739560 */   GIM_Try, /*On fail goto*//*Label 11749*/ GIMT_Encode4(739617), // Rule ID 21774 //
     /*  739565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  739568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739575 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739588 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET),
     /*  739591 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739615 */     GIR_RootConstrainSelectedInstOperands,
     /*  739616 */     // GIR_Coverage, 21774,
     /*  739616 */     GIR_EraseRootFromParent_Done,
     /*  739617 */   // Label 11749: @739617
     /*  739617 */   GIM_Try, /*On fail goto*//*Label 11750*/ GIMT_Encode4(739674), // Rule ID 21775 //
     /*  739622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  739625 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739632 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739634 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739638 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739645 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET),
     /*  739648 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739668 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739672 */     GIR_RootConstrainSelectedInstOperands,
     /*  739673 */     // GIR_Coverage, 21775,
     /*  739673 */     GIR_EraseRootFromParent_Done,
     /*  739674 */   // Label 11750: @739674
     /*  739674 */   GIM_Try, /*On fail goto*//*Label 11751*/ GIMT_Encode4(739731), // Rule ID 21776 //
     /*  739679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  739682 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739689 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739702 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET),
     /*  739705 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739729 */     GIR_RootConstrainSelectedInstOperands,
     /*  739730 */     // GIR_Coverage, 21776,
     /*  739730 */     GIR_EraseRootFromParent_Done,
     /*  739731 */   // Label 11751: @739731
     /*  739731 */   GIM_Try, /*On fail goto*//*Label 11752*/ GIMT_Encode4(739788), // Rule ID 21777 //
     /*  739736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  739739 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739746 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739759 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET),
     /*  739762 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739786 */     GIR_RootConstrainSelectedInstOperands,
     /*  739787 */     // GIR_Coverage, 21777,
     /*  739787 */     GIR_EraseRootFromParent_Done,
     /*  739788 */   // Label 11752: @739788
     /*  739788 */   GIM_Try, /*On fail goto*//*Label 11753*/ GIMT_Encode4(739845), // Rule ID 21793 //
     /*  739793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  739796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739803 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739816 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET),
     /*  739819 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739843 */     GIR_RootConstrainSelectedInstOperands,
     /*  739844 */     // GIR_Coverage, 21793,
     /*  739844 */     GIR_EraseRootFromParent_Done,
     /*  739845 */   // Label 11753: @739845
     /*  739845 */   GIM_Try, /*On fail goto*//*Label 11754*/ GIMT_Encode4(739902), // Rule ID 21794 //
     /*  739850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  739853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739860 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739873 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET),
     /*  739876 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739900 */     GIR_RootConstrainSelectedInstOperands,
     /*  739901 */     // GIR_Coverage, 21794,
     /*  739901 */     GIR_EraseRootFromParent_Done,
     /*  739902 */   // Label 11754: @739902
     /*  739902 */   GIM_Try, /*On fail goto*//*Label 11755*/ GIMT_Encode4(739959), // Rule ID 21795 //
     /*  739907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  739910 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739917 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739919 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739930 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET),
     /*  739933 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  739945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  739950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  739953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  739957 */     GIR_RootConstrainSelectedInstOperands,
     /*  739958 */     // GIR_Coverage, 21795,
     /*  739958 */     GIR_EraseRootFromParent_Done,
     /*  739959 */   // Label 11755: @739959
     /*  739959 */   GIM_Try, /*On fail goto*//*Label 11756*/ GIMT_Encode4(740016), // Rule ID 21796 //
     /*  739964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  739967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  739974 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  739976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  739980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  739987 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  739987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET),
     /*  739990 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  739992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  739997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740014 */     GIR_RootConstrainSelectedInstOperands,
     /*  740015 */     // GIR_Coverage, 21796,
     /*  740015 */     GIR_EraseRootFromParent_Done,
     /*  740016 */   // Label 11756: @740016
     /*  740016 */   GIM_Try, /*On fail goto*//*Label 11757*/ GIMT_Encode4(740073), // Rule ID 21797 //
     /*  740021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  740024 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740031 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740044 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET),
     /*  740047 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740071 */     GIR_RootConstrainSelectedInstOperands,
     /*  740072 */     // GIR_Coverage, 21797,
     /*  740072 */     GIR_EraseRootFromParent_Done,
     /*  740073 */   // Label 11757: @740073
     /*  740073 */   GIM_Try, /*On fail goto*//*Label 11758*/ GIMT_Encode4(740134), // Rule ID 21763 //
     /*  740078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  740081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740092 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740096 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740103 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN),
     /*  740106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740108 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740128 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740132 */     GIR_RootConstrainSelectedInstOperands,
     /*  740133 */     // GIR_Coverage, 21763,
     /*  740133 */     GIR_EraseRootFromParent_Done,
     /*  740134 */   // Label 11758: @740134
     /*  740134 */   GIM_Try, /*On fail goto*//*Label 11759*/ GIMT_Encode4(740195), // Rule ID 21764 //
     /*  740139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  740142 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740164 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN),
     /*  740167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740169 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740189 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740193 */     GIR_RootConstrainSelectedInstOperands,
     /*  740194 */     // GIR_Coverage, 21764,
     /*  740194 */     GIR_EraseRootFromParent_Done,
     /*  740195 */   // Label 11759: @740195
     /*  740195 */   GIM_Try, /*On fail goto*//*Label 11760*/ GIMT_Encode4(740256), // Rule ID 21765 //
     /*  740200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  740203 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740225 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN),
     /*  740228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740230 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740254 */     GIR_RootConstrainSelectedInstOperands,
     /*  740255 */     // GIR_Coverage, 21765,
     /*  740255 */     GIR_EraseRootFromParent_Done,
     /*  740256 */   // Label 11760: @740256
     /*  740256 */   GIM_Try, /*On fail goto*//*Label 11761*/ GIMT_Encode4(740317), // Rule ID 21766 //
     /*  740261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  740264 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740286 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN),
     /*  740289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740291 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740315 */     GIR_RootConstrainSelectedInstOperands,
     /*  740316 */     // GIR_Coverage, 21766,
     /*  740316 */     GIR_EraseRootFromParent_Done,
     /*  740317 */   // Label 11761: @740317
     /*  740317 */   GIM_Try, /*On fail goto*//*Label 11762*/ GIMT_Encode4(740378), // Rule ID 21767 //
     /*  740322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  740325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740347 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN),
     /*  740350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740352 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740372 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740376 */     GIR_RootConstrainSelectedInstOperands,
     /*  740377 */     // GIR_Coverage, 21767,
     /*  740377 */     GIR_EraseRootFromParent_Done,
     /*  740378 */   // Label 11762: @740378
     /*  740378 */   GIM_Try, /*On fail goto*//*Label 11763*/ GIMT_Encode4(740439), // Rule ID 21783 //
     /*  740383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  740386 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740397 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740401 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740408 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN),
     /*  740411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740413 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740433 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740437 */     GIR_RootConstrainSelectedInstOperands,
     /*  740438 */     // GIR_Coverage, 21783,
     /*  740438 */     GIR_EraseRootFromParent_Done,
     /*  740439 */   // Label 11763: @740439
     /*  740439 */   GIM_Try, /*On fail goto*//*Label 11764*/ GIMT_Encode4(740500), // Rule ID 21784 //
     /*  740444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  740447 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740458 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740469 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN),
     /*  740472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740474 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740498 */     GIR_RootConstrainSelectedInstOperands,
     /*  740499 */     // GIR_Coverage, 21784,
     /*  740499 */     GIR_EraseRootFromParent_Done,
     /*  740500 */   // Label 11764: @740500
     /*  740500 */   GIM_Try, /*On fail goto*//*Label 11765*/ GIMT_Encode4(740561), // Rule ID 21785 //
     /*  740505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  740508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740523 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740530 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN),
     /*  740533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740535 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740559 */     GIR_RootConstrainSelectedInstOperands,
     /*  740560 */     // GIR_Coverage, 21785,
     /*  740560 */     GIR_EraseRootFromParent_Done,
     /*  740561 */   // Label 11765: @740561
     /*  740561 */   GIM_Try, /*On fail goto*//*Label 11766*/ GIMT_Encode4(740622), // Rule ID 21786 //
     /*  740566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  740569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740591 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN),
     /*  740594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740596 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740616 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740620 */     GIR_RootConstrainSelectedInstOperands,
     /*  740621 */     // GIR_Coverage, 21786,
     /*  740621 */     GIR_EraseRootFromParent_Done,
     /*  740622 */   // Label 11766: @740622
     /*  740622 */   GIM_Try, /*On fail goto*//*Label 11767*/ GIMT_Encode4(740683), // Rule ID 21787 //
     /*  740627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  740630 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  740637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  740641 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740645 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  740652 */     // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15623:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  740652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN),
     /*  740655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  740657 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  740659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  740664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  740669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  740674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  740677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740681 */     GIR_RootConstrainSelectedInstOperands,
     /*  740682 */     // GIR_Coverage, 21787,
     /*  740682 */     GIR_EraseRootFromParent_Done,
     /*  740683 */   // Label 11767: @740683
     /*  740683 */   GIM_Try, /*On fail goto*//*Label 11768*/ GIMT_Encode4(740733), // Rule ID 30895 //
     /*  740688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  740691 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740696 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740698 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740702 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  740709 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  740709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  740712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  740717 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  740719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  740724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740731 */     GIR_RootConstrainSelectedInstOperands,
     /*  740732 */     // GIR_Coverage, 30895,
     /*  740732 */     GIR_EraseRootFromParent_Done,
     /*  740733 */   // Label 11768: @740733
     /*  740733 */   GIM_Try, /*On fail goto*//*Label 11769*/ GIMT_Encode4(740783), // Rule ID 30896 //
     /*  740738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  740741 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740746 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  740759 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  740759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  740762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  740767 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  740769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  740774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740777 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740781 */     GIR_RootConstrainSelectedInstOperands,
     /*  740782 */     // GIR_Coverage, 30896,
     /*  740782 */     GIR_EraseRootFromParent_Done,
     /*  740783 */   // Label 11769: @740783
     /*  740783 */   GIM_Try, /*On fail goto*//*Label 11770*/ GIMT_Encode4(740833), // Rule ID 30897 //
     /*  740788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  740791 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740796 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  740809 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  740809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  740812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  740817 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  740819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  740824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740831 */     GIR_RootConstrainSelectedInstOperands,
     /*  740832 */     // GIR_Coverage, 30897,
     /*  740832 */     GIR_EraseRootFromParent_Done,
     /*  740833 */   // Label 11770: @740833
     /*  740833 */   GIM_Try, /*On fail goto*//*Label 11771*/ GIMT_Encode4(740883), // Rule ID 30898 //
     /*  740838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  740841 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740846 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  740859 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  740859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  740862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  740867 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  740869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  740874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740877 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740881 */     GIR_RootConstrainSelectedInstOperands,
     /*  740882 */     // GIR_Coverage, 30898,
     /*  740882 */     GIR_EraseRootFromParent_Done,
     /*  740883 */   // Label 11771: @740883
     /*  740883 */   GIM_Try, /*On fail goto*//*Label 11772*/ GIMT_Encode4(740933), // Rule ID 30899 //
     /*  740888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  740891 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740896 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  740909 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  740909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  740912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  740917 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  740919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  740924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740927 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740931 */     GIR_RootConstrainSelectedInstOperands,
     /*  740932 */     // GIR_Coverage, 30899,
     /*  740932 */     GIR_EraseRootFromParent_Done,
     /*  740933 */   // Label 11772: @740933
     /*  740933 */   GIM_Try, /*On fail goto*//*Label 11773*/ GIMT_Encode4(740983), // Rule ID 30905 //
     /*  740938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  740941 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740946 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  740952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  740959 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f64>>  =>  (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  740959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9),
     /*  740962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  740967 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  740969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  740974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  740977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  740981 */     GIR_RootConstrainSelectedInstOperands,
     /*  740982 */     // GIR_Coverage, 30905,
     /*  740982 */     GIR_EraseRootFromParent_Done,
     /*  740983 */   // Label 11773: @740983
     /*  740983 */   GIM_Try, /*On fail goto*//*Label 11774*/ GIMT_Encode4(741033), // Rule ID 30906 //
     /*  740988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  740991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  740996 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  740998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741009 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f64>>  =>  (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9),
     /*  741012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741017 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741031 */     GIR_RootConstrainSelectedInstOperands,
     /*  741032 */     // GIR_Coverage, 30906,
     /*  741032 */     GIR_EraseRootFromParent_Done,
     /*  741033 */   // Label 11774: @741033
     /*  741033 */   GIM_Try, /*On fail goto*//*Label 11775*/ GIMT_Encode4(741083), // Rule ID 30907 //
     /*  741038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  741041 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741046 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741059 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f64>>  =>  (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9),
     /*  741062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741067 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741074 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741077 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741081 */     GIR_RootConstrainSelectedInstOperands,
     /*  741082 */     // GIR_Coverage, 30907,
     /*  741082 */     GIR_EraseRootFromParent_Done,
     /*  741083 */   // Label 11775: @741083
     /*  741083 */   GIM_Try, /*On fail goto*//*Label 11776*/ GIMT_Encode4(741133), // Rule ID 30908 //
     /*  741088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  741091 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741096 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741102 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741109 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f64>>  =>  (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9),
     /*  741112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741117 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741131 */     GIR_RootConstrainSelectedInstOperands,
     /*  741132 */     // GIR_Coverage, 30908,
     /*  741132 */     GIR_EraseRootFromParent_Done,
     /*  741133 */   // Label 11776: @741133
     /*  741133 */   GIM_Try, /*On fail goto*//*Label 11777*/ GIMT_Encode4(741183), // Rule ID 30909 //
     /*  741138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  741141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741146 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741152 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741159 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f64>>  =>  (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9),
     /*  741162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741167 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741181 */     GIR_RootConstrainSelectedInstOperands,
     /*  741182 */     // GIR_Coverage, 30909,
     /*  741182 */     GIR_EraseRootFromParent_Done,
     /*  741183 */   // Label 11777: @741183
     /*  741183 */   GIM_Try, /*On fail goto*//*Label 11778*/ GIMT_Encode4(741233), // Rule ID 30915 //
     /*  741188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  741191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  741196 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741202 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741209 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  741209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  741212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741217 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  741227 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741231 */     GIR_RootConstrainSelectedInstOperands,
     /*  741232 */     // GIR_Coverage, 30915,
     /*  741232 */     GIR_EraseRootFromParent_Done,
     /*  741233 */   // Label 11778: @741233
     /*  741233 */   GIM_Try, /*On fail goto*//*Label 11779*/ GIMT_Encode4(741283), // Rule ID 30916 //
     /*  741238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  741241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  741246 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741259 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  741259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  741262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741267 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  741277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741281 */     GIR_RootConstrainSelectedInstOperands,
     /*  741282 */     // GIR_Coverage, 30916,
     /*  741282 */     GIR_EraseRootFromParent_Done,
     /*  741283 */   // Label 11779: @741283
     /*  741283 */   GIM_Try, /*On fail goto*//*Label 11780*/ GIMT_Encode4(741333), // Rule ID 30917 //
     /*  741288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  741291 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  741296 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741298 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741302 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741309 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  741309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  741312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741317 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741324 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  741327 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741331 */     GIR_RootConstrainSelectedInstOperands,
     /*  741332 */     // GIR_Coverage, 30917,
     /*  741332 */     GIR_EraseRootFromParent_Done,
     /*  741333 */   // Label 11780: @741333
     /*  741333 */   GIM_Try, /*On fail goto*//*Label 11781*/ GIMT_Encode4(741383), // Rule ID 30918 //
     /*  741338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  741341 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  741346 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741359 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  741359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  741362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741367 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  741377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741381 */     GIR_RootConstrainSelectedInstOperands,
     /*  741382 */     // GIR_Coverage, 30918,
     /*  741382 */     GIR_EraseRootFromParent_Done,
     /*  741383 */   // Label 11781: @741383
     /*  741383 */   GIM_Try, /*On fail goto*//*Label 11782*/ GIMT_Encode4(741433), // Rule ID 30919 //
     /*  741388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  741391 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  741396 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  741398 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741409 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  741409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
     /*  741412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741417 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  741427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741431 */     GIR_RootConstrainSelectedInstOperands,
     /*  741432 */     // GIR_Coverage, 30919,
     /*  741432 */     GIR_EraseRootFromParent_Done,
     /*  741433 */   // Label 11782: @741433
     /*  741433 */   GIM_Try, /*On fail goto*//*Label 11783*/ GIMT_Encode4(741487), // Rule ID 30890 //
     /*  741438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  741441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741450 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741461 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  741464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741471 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741485 */     GIR_RootConstrainSelectedInstOperands,
     /*  741486 */     // GIR_Coverage, 30890,
     /*  741486 */     GIR_EraseRootFromParent_Done,
     /*  741487 */   // Label 11783: @741487
     /*  741487 */   GIM_Try, /*On fail goto*//*Label 11784*/ GIMT_Encode4(741541), // Rule ID 30891 //
     /*  741492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  741495 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741515 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  741518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741525 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741539 */     GIR_RootConstrainSelectedInstOperands,
     /*  741540 */     // GIR_Coverage, 30891,
     /*  741540 */     GIR_EraseRootFromParent_Done,
     /*  741541 */   // Label 11784: @741541
     /*  741541 */   GIM_Try, /*On fail goto*//*Label 11785*/ GIMT_Encode4(741595), // Rule ID 30892 //
     /*  741546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  741549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741569 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  741572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741579 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741593 */     GIR_RootConstrainSelectedInstOperands,
     /*  741594 */     // GIR_Coverage, 30892,
     /*  741594 */     GIR_EraseRootFromParent_Done,
     /*  741595 */   // Label 11785: @741595
     /*  741595 */   GIM_Try, /*On fail goto*//*Label 11786*/ GIMT_Encode4(741649), // Rule ID 30893 //
     /*  741600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  741603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741623 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  741626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741633 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741647 */     GIR_RootConstrainSelectedInstOperands,
     /*  741648 */     // GIR_Coverage, 30893,
     /*  741648 */     GIR_EraseRootFromParent_Done,
     /*  741649 */   // Label 11786: @741649
     /*  741649 */   GIM_Try, /*On fail goto*//*Label 11787*/ GIMT_Encode4(741703), // Rule ID 30894 //
     /*  741654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  741657 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741666 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741670 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741677 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  741680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741687 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741701 */     GIR_RootConstrainSelectedInstOperands,
     /*  741702 */     // GIR_Coverage, 30894,
     /*  741702 */     GIR_EraseRootFromParent_Done,
     /*  741703 */   // Label 11787: @741703
     /*  741703 */   GIM_Try, /*On fail goto*//*Label 11788*/ GIMT_Encode4(741757), // Rule ID 30900 //
     /*  741708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  741711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741731 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_f64>>  =>  (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9),
     /*  741734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741741 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741751 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741755 */     GIR_RootConstrainSelectedInstOperands,
     /*  741756 */     // GIR_Coverage, 30900,
     /*  741756 */     GIR_EraseRootFromParent_Done,
     /*  741757 */   // Label 11788: @741757
     /*  741757 */   GIM_Try, /*On fail goto*//*Label 11789*/ GIMT_Encode4(741811), // Rule ID 30901 //
     /*  741762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  741765 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741785 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_f64>>  =>  (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9),
     /*  741788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741795 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741805 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741809 */     GIR_RootConstrainSelectedInstOperands,
     /*  741810 */     // GIR_Coverage, 30901,
     /*  741810 */     GIR_EraseRootFromParent_Done,
     /*  741811 */   // Label 11789: @741811
     /*  741811 */   GIM_Try, /*On fail goto*//*Label 11790*/ GIMT_Encode4(741865), // Rule ID 30902 //
     /*  741816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  741819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741839 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_f64>>  =>  (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9),
     /*  741842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741849 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741859 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741863 */     GIR_RootConstrainSelectedInstOperands,
     /*  741864 */     // GIR_Coverage, 30902,
     /*  741864 */     GIR_EraseRootFromParent_Done,
     /*  741865 */   // Label 11790: @741865
     /*  741865 */   GIM_Try, /*On fail goto*//*Label 11791*/ GIMT_Encode4(741919), // Rule ID 30903 //
     /*  741870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  741873 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741882 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741886 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741893 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_f64>>  =>  (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9),
     /*  741896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741903 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741913 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741917 */     GIR_RootConstrainSelectedInstOperands,
     /*  741918 */     // GIR_Coverage, 30903,
     /*  741918 */     GIR_EraseRootFromParent_Done,
     /*  741919 */   // Label 11791: @741919
     /*  741919 */   GIM_Try, /*On fail goto*//*Label 11792*/ GIMT_Encode4(741973), // Rule ID 30904 //
     /*  741924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  741927 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  741932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  741947 */     // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_f64>>  =>  (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  741947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9),
     /*  741950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  741952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  741957 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  741959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  741964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  741967 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  741971 */     GIR_RootConstrainSelectedInstOperands,
     /*  741972 */     // GIR_Coverage, 30904,
     /*  741972 */     GIR_EraseRootFromParent_Done,
     /*  741973 */   // Label 11792: @741973
     /*  741973 */   GIM_Try, /*On fail goto*//*Label 11793*/ GIMT_Encode4(742027), // Rule ID 30910 //
     /*  741978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  741981 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  741986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  741990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  741994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  742001 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  742001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  742004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  742011 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  742013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  742021 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742025 */     GIR_RootConstrainSelectedInstOperands,
     /*  742026 */     // GIR_Coverage, 30910,
     /*  742026 */     GIR_EraseRootFromParent_Done,
     /*  742027 */   // Label 11793: @742027
     /*  742027 */   GIM_Try, /*On fail goto*//*Label 11794*/ GIMT_Encode4(742081), // Rule ID 30911 //
     /*  742032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  742035 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  742040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742044 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742048 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  742055 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  742055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  742058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  742065 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  742067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  742075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742079 */     GIR_RootConstrainSelectedInstOperands,
     /*  742080 */     // GIR_Coverage, 30911,
     /*  742080 */     GIR_EraseRootFromParent_Done,
     /*  742081 */   // Label 11794: @742081
     /*  742081 */   GIM_Try, /*On fail goto*//*Label 11795*/ GIMT_Encode4(742135), // Rule ID 30912 //
     /*  742086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  742089 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  742094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742102 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  742109 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  742109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  742112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  742119 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  742121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  742129 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742133 */     GIR_RootConstrainSelectedInstOperands,
     /*  742134 */     // GIR_Coverage, 30912,
     /*  742134 */     GIR_EraseRootFromParent_Done,
     /*  742135 */   // Label 11795: @742135
     /*  742135 */   GIM_Try, /*On fail goto*//*Label 11796*/ GIMT_Encode4(742189), // Rule ID 30913 //
     /*  742140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  742143 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  742148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742152 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742156 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  742163 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  742163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  742166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  742173 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  742175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  742183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742187 */     GIR_RootConstrainSelectedInstOperands,
     /*  742188 */     // GIR_Coverage, 30913,
     /*  742188 */     GIR_EraseRootFromParent_Done,
     /*  742189 */   // Label 11796: @742189
     /*  742189 */   GIM_Try, /*On fail goto*//*Label 11797*/ GIMT_Encode4(742243), // Rule ID 30914 //
     /*  742194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  742197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  742202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  742217 */     // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  742217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
     /*  742220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  742227 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  742229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  742237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742241 */     GIR_RootConstrainSelectedInstOperands,
     /*  742242 */     // GIR_Coverage, 30914,
     /*  742242 */     GIR_EraseRootFromParent_Done,
     /*  742243 */   // Label 11797: @742243
     /*  742243 */   GIM_Try, /*On fail goto*//*Label 11798*/ GIMT_Encode4(742302), // Rule ID 13738 //
     /*  742248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  742251 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742258 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742264 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  742271 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
     /*  742274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742279 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742300 */     GIR_RootConstrainSelectedInstOperands,
     /*  742301 */     // GIR_Coverage, 13738,
     /*  742301 */     GIR_EraseRootFromParent_Done,
     /*  742302 */   // Label 11798: @742302
     /*  742302 */   GIM_Try, /*On fail goto*//*Label 11799*/ GIMT_Encode4(742361), // Rule ID 13739 //
     /*  742307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  742310 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742317 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742319 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  742330 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
     /*  742333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742338 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742355 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742359 */     GIR_RootConstrainSelectedInstOperands,
     /*  742360 */     // GIR_Coverage, 13739,
     /*  742360 */     GIR_EraseRootFromParent_Done,
     /*  742361 */   // Label 11799: @742361
     /*  742361 */   GIM_Try, /*On fail goto*//*Label 11800*/ GIMT_Encode4(742420), // Rule ID 13740 //
     /*  742366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  742369 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742376 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  742389 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
     /*  742392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742397 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742404 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742418 */     GIR_RootConstrainSelectedInstOperands,
     /*  742419 */     // GIR_Coverage, 13740,
     /*  742419 */     GIR_EraseRootFromParent_Done,
     /*  742420 */   // Label 11800: @742420
     /*  742420 */   GIM_Try, /*On fail goto*//*Label 11801*/ GIMT_Encode4(742479), // Rule ID 13741 //
     /*  742425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  742428 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742435 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  742448 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
     /*  742451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742456 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742477 */     GIR_RootConstrainSelectedInstOperands,
     /*  742478 */     // GIR_Coverage, 13741,
     /*  742478 */     GIR_EraseRootFromParent_Done,
     /*  742479 */   // Label 11801: @742479
     /*  742479 */   GIM_Try, /*On fail goto*//*Label 11802*/ GIMT_Encode4(742538), // Rule ID 13742 //
     /*  742484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  742487 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742494 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  742507 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
     /*  742510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742515 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742536 */     GIR_RootConstrainSelectedInstOperands,
     /*  742537 */     // GIR_Coverage, 13742,
     /*  742537 */     GIR_EraseRootFromParent_Done,
     /*  742538 */   // Label 11802: @742538
     /*  742538 */   GIM_Try, /*On fail goto*//*Label 11803*/ GIMT_Encode4(742601), // Rule ID 13748 //
     /*  742543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  742546 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742557 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  742568 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
     /*  742571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742578 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742599 */     GIR_RootConstrainSelectedInstOperands,
     /*  742600 */     // GIR_Coverage, 13748,
     /*  742600 */     GIR_EraseRootFromParent_Done,
     /*  742601 */   // Label 11803: @742601
     /*  742601 */   GIM_Try, /*On fail goto*//*Label 11804*/ GIMT_Encode4(742664), // Rule ID 13749 //
     /*  742606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  742609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  742631 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
     /*  742634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742641 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742662 */     GIR_RootConstrainSelectedInstOperands,
     /*  742663 */     // GIR_Coverage, 13749,
     /*  742663 */     GIR_EraseRootFromParent_Done,
     /*  742664 */   // Label 11804: @742664
     /*  742664 */   GIM_Try, /*On fail goto*//*Label 11805*/ GIMT_Encode4(742727), // Rule ID 13750 //
     /*  742669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  742672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742687 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  742694 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
     /*  742697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742704 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742725 */     GIR_RootConstrainSelectedInstOperands,
     /*  742726 */     // GIR_Coverage, 13750,
     /*  742726 */     GIR_EraseRootFromParent_Done,
     /*  742727 */   // Label 11805: @742727
     /*  742727 */   GIM_Try, /*On fail goto*//*Label 11806*/ GIMT_Encode4(742790), // Rule ID 13751 //
     /*  742732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  742735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  742757 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
     /*  742760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742767 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742788 */     GIR_RootConstrainSelectedInstOperands,
     /*  742789 */     // GIR_Coverage, 13751,
     /*  742789 */     GIR_EraseRootFromParent_Done,
     /*  742790 */   // Label 11806: @742790
     /*  742790 */   GIM_Try, /*On fail goto*//*Label 11807*/ GIMT_Encode4(742853), // Rule ID 13752 //
     /*  742795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  742798 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  742809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  742820 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  742820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
     /*  742823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  742825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  742830 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  742837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  742842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  742847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742851 */     GIR_RootConstrainSelectedInstOperands,
     /*  742852 */     // GIR_Coverage, 13752,
     /*  742852 */     GIR_EraseRootFromParent_Done,
     /*  742853 */   // Label 11807: @742853
     /*  742853 */   GIM_Try, /*On fail goto*//*Label 11808*/ GIMT_Encode4(742905), // Rule ID 13733 //
     /*  742858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  742861 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742868 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742874 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  742881 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  742881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
     /*  742884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  742889 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  742899 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742903 */     GIR_RootConstrainSelectedInstOperands,
     /*  742904 */     // GIR_Coverage, 13733,
     /*  742904 */     GIR_EraseRootFromParent_Done,
     /*  742905 */   // Label 11808: @742905
     /*  742905 */   GIM_Try, /*On fail goto*//*Label 11809*/ GIMT_Encode4(742957), // Rule ID 13734 //
     /*  742910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  742913 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742920 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  742933 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  742933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
     /*  742936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  742941 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  742948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  742951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  742955 */     GIR_RootConstrainSelectedInstOperands,
     /*  742956 */     // GIR_Coverage, 13734,
     /*  742956 */     GIR_EraseRootFromParent_Done,
     /*  742957 */   // Label 11809: @742957
     /*  742957 */   GIM_Try, /*On fail goto*//*Label 11810*/ GIMT_Encode4(743009), // Rule ID 13735 //
     /*  742962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  742965 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  742972 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  742974 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  742978 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  742985 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  742985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
     /*  742988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  742993 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  742995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  743003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743007 */     GIR_RootConstrainSelectedInstOperands,
     /*  743008 */     // GIR_Coverage, 13735,
     /*  743008 */     GIR_EraseRootFromParent_Done,
     /*  743009 */   // Label 11810: @743009
     /*  743009 */   GIM_Try, /*On fail goto*//*Label 11811*/ GIMT_Encode4(743061), // Rule ID 13736 //
     /*  743014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  743017 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743024 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743026 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743030 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743037 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
     /*  743040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743045 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  743055 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743059 */     GIR_RootConstrainSelectedInstOperands,
     /*  743060 */     // GIR_Coverage, 13736,
     /*  743060 */     GIR_EraseRootFromParent_Done,
     /*  743061 */   // Label 11811: @743061
     /*  743061 */   GIM_Try, /*On fail goto*//*Label 11812*/ GIMT_Encode4(743113), // Rule ID 13737 //
     /*  743066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  743069 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743076 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743089 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
     /*  743092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743097 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  743107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743111 */     GIR_RootConstrainSelectedInstOperands,
     /*  743112 */     // GIR_Coverage, 13737,
     /*  743112 */     GIR_EraseRootFromParent_Done,
     /*  743113 */   // Label 11812: @743113
     /*  743113 */   GIM_Try, /*On fail goto*//*Label 11813*/ GIMT_Encode4(743169), // Rule ID 13743 //
     /*  743118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode0),
     /*  743121 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  743132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743143 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
     /*  743146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  743148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743153 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  743163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743167 */     GIR_RootConstrainSelectedInstOperands,
     /*  743168 */     // GIR_Coverage, 13743,
     /*  743168 */     GIR_EraseRootFromParent_Done,
     /*  743169 */   // Label 11813: @743169
     /*  743169 */   GIM_Try, /*On fail goto*//*Label 11814*/ GIMT_Encode4(743225), // Rule ID 13744 //
     /*  743174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode1),
     /*  743177 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  743188 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743192 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743199 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
     /*  743202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  743204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743209 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743216 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  743219 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743223 */     GIR_RootConstrainSelectedInstOperands,
     /*  743224 */     // GIR_Coverage, 13744,
     /*  743224 */     GIR_EraseRootFromParent_Done,
     /*  743225 */   // Label 11814: @743225
     /*  743225 */   GIM_Try, /*On fail goto*//*Label 11815*/ GIMT_Encode4(743281), // Rule ID 13745 //
     /*  743230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode2),
     /*  743233 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  743244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743255 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
     /*  743258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  743260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743265 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  743275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743279 */     GIR_RootConstrainSelectedInstOperands,
     /*  743280 */     // GIR_Coverage, 13745,
     /*  743280 */     GIR_EraseRootFromParent_Done,
     /*  743281 */   // Label 11815: @743281
     /*  743281 */   GIM_Try, /*On fail goto*//*Label 11816*/ GIMT_Encode4(743337), // Rule ID 13746 //
     /*  743286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode3),
     /*  743289 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  743300 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743311 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
     /*  743314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  743316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743321 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  743331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743335 */     GIR_RootConstrainSelectedInstOperands,
     /*  743336 */     // GIR_Coverage, 13746,
     /*  743336 */     GIR_EraseRootFromParent_Done,
     /*  743337 */   // Label 11816: @743337
     /*  743337 */   GIM_Try, /*On fail goto*//*Label 11817*/ GIMT_Encode4(743393), // Rule ID 13747 //
     /*  743342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HwMode4),
     /*  743345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  743356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  743367 */     // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  743367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
     /*  743370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  743372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  743377 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  743384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  743387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743391 */     GIR_RootConstrainSelectedInstOperands,
     /*  743392 */     // GIR_Coverage, 13747,
     /*  743392 */     GIR_EraseRootFromParent_Done,
     /*  743393 */   // Label 11817: @743393
     /*  743393 */   GIM_Try, /*On fail goto*//*Label 11818*/ GIMT_Encode4(743453), // Rule ID 10989 //
     /*  743398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  743401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743409 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743422 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743430 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743451 */     GIR_RootConstrainSelectedInstOperands,
     /*  743452 */     // GIR_Coverage, 10989,
     /*  743452 */     GIR_EraseRootFromParent_Done,
     /*  743453 */   // Label 11818: @743453
     /*  743453 */   GIM_Try, /*On fail goto*//*Label 11819*/ GIMT_Encode4(743513), // Rule ID 10990 //
     /*  743458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  743461 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743469 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743482 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743490 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743507 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743511 */     GIR_RootConstrainSelectedInstOperands,
     /*  743512 */     // GIR_Coverage, 10990,
     /*  743512 */     GIR_EraseRootFromParent_Done,
     /*  743513 */   // Label 11819: @743513
     /*  743513 */   GIM_Try, /*On fail goto*//*Label 11820*/ GIMT_Encode4(743573), // Rule ID 10991 //
     /*  743518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  743521 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743529 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743542 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743550 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743567 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743571 */     GIR_RootConstrainSelectedInstOperands,
     /*  743572 */     // GIR_Coverage, 10991,
     /*  743572 */     GIR_EraseRootFromParent_Done,
     /*  743573 */   // Label 11820: @743573
     /*  743573 */   GIM_Try, /*On fail goto*//*Label 11821*/ GIMT_Encode4(743633), // Rule ID 10992 //
     /*  743578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  743581 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743589 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743602 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743610 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743627 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743631 */     GIR_RootConstrainSelectedInstOperands,
     /*  743632 */     // GIR_Coverage, 10992,
     /*  743632 */     GIR_EraseRootFromParent_Done,
     /*  743633 */   // Label 11821: @743633
     /*  743633 */   GIM_Try, /*On fail goto*//*Label 11822*/ GIMT_Encode4(743693), // Rule ID 10993 //
     /*  743638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  743641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743649 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743662 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743670 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743691 */     GIR_RootConstrainSelectedInstOperands,
     /*  743692 */     // GIR_Coverage, 10993,
     /*  743692 */     GIR_EraseRootFromParent_Done,
     /*  743693 */   // Label 11822: @743693
     /*  743693 */   GIM_Try, /*On fail goto*//*Label 11823*/ GIMT_Encode4(743752), // Rule ID 11545 //
     /*  743698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  743701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743708 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743721 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743729 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743750 */     GIR_RootConstrainSelectedInstOperands,
     /*  743751 */     // GIR_Coverage, 11545,
     /*  743751 */     GIR_EraseRootFromParent_Done,
     /*  743752 */   // Label 11823: @743752
     /*  743752 */   GIM_Try, /*On fail goto*//*Label 11824*/ GIMT_Encode4(743811), // Rule ID 11546 //
     /*  743757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  743760 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743767 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743780 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743788 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743805 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743809 */     GIR_RootConstrainSelectedInstOperands,
     /*  743810 */     // GIR_Coverage, 11546,
     /*  743810 */     GIR_EraseRootFromParent_Done,
     /*  743811 */   // Label 11824: @743811
     /*  743811 */   GIM_Try, /*On fail goto*//*Label 11825*/ GIMT_Encode4(743870), // Rule ID 11547 //
     /*  743816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  743819 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743826 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743839 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743847 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743864 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743868 */     GIR_RootConstrainSelectedInstOperands,
     /*  743869 */     // GIR_Coverage, 11547,
     /*  743869 */     GIR_EraseRootFromParent_Done,
     /*  743870 */   // Label 11825: @743870
     /*  743870 */   GIM_Try, /*On fail goto*//*Label 11826*/ GIMT_Encode4(743929), // Rule ID 11548 //
     /*  743875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  743878 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743885 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743898 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743906 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743927 */     GIR_RootConstrainSelectedInstOperands,
     /*  743928 */     // GIR_Coverage, 11548,
     /*  743928 */     GIR_EraseRootFromParent_Done,
     /*  743929 */   // Label 11826: @743929
     /*  743929 */   GIM_Try, /*On fail goto*//*Label 11827*/ GIMT_Encode4(743988), // Rule ID 11549 //
     /*  743934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  743937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  743944 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  743946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  743950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  743957 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  743957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR),
     /*  743960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  743965 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  743967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  743972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  743977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  743982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  743986 */     GIR_RootConstrainSelectedInstOperands,
     /*  743987 */     // GIR_Coverage, 11549,
     /*  743987 */     GIR_EraseRootFromParent_Done,
     /*  743988 */   // Label 11827: @743988
     /*  743988 */   GIM_Try, /*On fail goto*//*Label 11828*/ GIMT_Encode4(744052), // Rule ID 10979 //
     /*  743993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  743996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744019 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744029 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744050 */     GIR_RootConstrainSelectedInstOperands,
     /*  744051 */     // GIR_Coverage, 10979,
     /*  744051 */     GIR_EraseRootFromParent_Done,
     /*  744052 */   // Label 11828: @744052
     /*  744052 */   GIM_Try, /*On fail goto*//*Label 11829*/ GIMT_Encode4(744116), // Rule ID 10980 //
     /*  744057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  744060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744083 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744093 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744114 */     GIR_RootConstrainSelectedInstOperands,
     /*  744115 */     // GIR_Coverage, 10980,
     /*  744115 */     GIR_EraseRootFromParent_Done,
     /*  744116 */   // Label 11829: @744116
     /*  744116 */   GIM_Try, /*On fail goto*//*Label 11830*/ GIMT_Encode4(744180), // Rule ID 10981 //
     /*  744121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  744124 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744147 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744157 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744174 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744178 */     GIR_RootConstrainSelectedInstOperands,
     /*  744179 */     // GIR_Coverage, 10981,
     /*  744179 */     GIR_EraseRootFromParent_Done,
     /*  744180 */   // Label 11830: @744180
     /*  744180 */   GIM_Try, /*On fail goto*//*Label 11831*/ GIMT_Encode4(744244), // Rule ID 10982 //
     /*  744185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  744188 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744200 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744211 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744221 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744242 */     GIR_RootConstrainSelectedInstOperands,
     /*  744243 */     // GIR_Coverage, 10982,
     /*  744243 */     GIR_EraseRootFromParent_Done,
     /*  744244 */   // Label 11831: @744244
     /*  744244 */   GIM_Try, /*On fail goto*//*Label 11832*/ GIMT_Encode4(744308), // Rule ID 10983 //
     /*  744249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  744252 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744264 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744275 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744285 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744306 */     GIR_RootConstrainSelectedInstOperands,
     /*  744307 */     // GIR_Coverage, 10983,
     /*  744307 */     GIR_EraseRootFromParent_Done,
     /*  744308 */   // Label 11832: @744308
     /*  744308 */   GIM_Try, /*On fail goto*//*Label 11833*/ GIMT_Encode4(744371), // Rule ID 11535 //
     /*  744313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode0),
     /*  744316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744327 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744338 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744348 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744365 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744369 */     GIR_RootConstrainSelectedInstOperands,
     /*  744370 */     // GIR_Coverage, 11535,
     /*  744370 */     GIR_EraseRootFromParent_Done,
     /*  744371 */   // Label 11833: @744371
     /*  744371 */   GIM_Try, /*On fail goto*//*Label 11834*/ GIMT_Encode4(744434), // Rule ID 11536 //
     /*  744376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode1),
     /*  744379 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744394 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744401 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744411 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744432 */     GIR_RootConstrainSelectedInstOperands,
     /*  744433 */     // GIR_Coverage, 11536,
     /*  744433 */     GIR_EraseRootFromParent_Done,
     /*  744434 */   // Label 11834: @744434
     /*  744434 */   GIM_Try, /*On fail goto*//*Label 11835*/ GIMT_Encode4(744497), // Rule ID 11537 //
     /*  744439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode2),
     /*  744442 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744457 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744464 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744474 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744495 */     GIR_RootConstrainSelectedInstOperands,
     /*  744496 */     // GIR_Coverage, 11537,
     /*  744496 */     GIR_EraseRootFromParent_Done,
     /*  744497 */   // Label 11835: @744497
     /*  744497 */   GIM_Try, /*On fail goto*//*Label 11836*/ GIMT_Encode4(744560), // Rule ID 11538 //
     /*  744502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode3),
     /*  744505 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744527 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744537 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744558 */     GIR_RootConstrainSelectedInstOperands,
     /*  744559 */     // GIR_Coverage, 11538,
     /*  744559 */     GIR_EraseRootFromParent_Done,
     /*  744560 */   // Label 11836: @744560
     /*  744560 */   GIM_Try, /*On fail goto*//*Label 11837*/ GIMT_Encode4(744623), // Rule ID 11539 //
     /*  744565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGVSMode_HwMode4),
     /*  744568 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  744579 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  744590 */     // (atomic_load_fmin:{ *:[f64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  744590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_SADDR_RTN),
     /*  744593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  744595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  744600 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  744607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  744612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  744617 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744621 */     GIR_RootConstrainSelectedInstOperands,
     /*  744622 */     // GIR_Coverage, 11539,
     /*  744622 */     GIR_EraseRootFromParent_Done,
     /*  744623 */   // Label 11837: @744623
     /*  744623 */   GIM_Try, /*On fail goto*//*Label 11838*/ GIMT_Encode4(744676), // Rule ID 10984 //
     /*  744628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  744631 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744639 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744641 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744645 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744652 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744660 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744674 */     GIR_RootConstrainSelectedInstOperands,
     /*  744675 */     // GIR_Coverage, 10984,
     /*  744675 */     GIR_EraseRootFromParent_Done,
     /*  744676 */   // Label 11838: @744676
     /*  744676 */   GIM_Try, /*On fail goto*//*Label 11839*/ GIMT_Encode4(744729), // Rule ID 10985 //
     /*  744681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  744684 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744692 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744705 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744713 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744727 */     GIR_RootConstrainSelectedInstOperands,
     /*  744728 */     // GIR_Coverage, 10985,
     /*  744728 */     GIR_EraseRootFromParent_Done,
     /*  744729 */   // Label 11839: @744729
     /*  744729 */   GIM_Try, /*On fail goto*//*Label 11840*/ GIMT_Encode4(744782), // Rule ID 10986 //
     /*  744734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  744737 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744745 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744747 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744758 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744766 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744780 */     GIR_RootConstrainSelectedInstOperands,
     /*  744781 */     // GIR_Coverage, 10986,
     /*  744781 */     GIR_EraseRootFromParent_Done,
     /*  744782 */   // Label 11840: @744782
     /*  744782 */   GIM_Try, /*On fail goto*//*Label 11841*/ GIMT_Encode4(744835), // Rule ID 10987 //
     /*  744787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  744790 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744798 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744804 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744811 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744819 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744833 */     GIR_RootConstrainSelectedInstOperands,
     /*  744834 */     // GIR_Coverage, 10987,
     /*  744834 */     GIR_EraseRootFromParent_Done,
     /*  744835 */   // Label 11841: @744835
     /*  744835 */   GIM_Try, /*On fail goto*//*Label 11842*/ GIMT_Encode4(744888), // Rule ID 10988 //
     /*  744840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  744843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744851 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744864 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744872 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744886 */     GIR_RootConstrainSelectedInstOperands,
     /*  744887 */     // GIR_Coverage, 10988,
     /*  744887 */     GIR_EraseRootFromParent_Done,
     /*  744888 */   // Label 11842: @744888
     /*  744888 */   GIM_Try, /*On fail goto*//*Label 11843*/ GIMT_Encode4(744940), // Rule ID 11540 //
     /*  744893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  744896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744903 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744916 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744924 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744938 */     GIR_RootConstrainSelectedInstOperands,
     /*  744939 */     // GIR_Coverage, 11540,
     /*  744939 */     GIR_EraseRootFromParent_Done,
     /*  744940 */   // Label 11843: @744940
     /*  744940 */   GIM_Try, /*On fail goto*//*Label 11844*/ GIMT_Encode4(744992), // Rule ID 11541 //
     /*  744945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  744948 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  744955 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  744957 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  744961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  744968 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  744968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  744971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  744976 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  744978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  744983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  744986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  744990 */     GIR_RootConstrainSelectedInstOperands,
     /*  744991 */     // GIR_Coverage, 11541,
     /*  744991 */     GIR_EraseRootFromParent_Done,
     /*  744992 */   // Label 11844: @744992
     /*  744992 */   GIM_Try, /*On fail goto*//*Label 11845*/ GIMT_Encode4(745044), // Rule ID 11542 //
     /*  744997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  745000 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745007 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745020 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  745023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745028 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745042 */     GIR_RootConstrainSelectedInstOperands,
     /*  745043 */     // GIR_Coverage, 11542,
     /*  745043 */     GIR_EraseRootFromParent_Done,
     /*  745044 */   // Label 11845: @745044
     /*  745044 */   GIM_Try, /*On fail goto*//*Label 11846*/ GIMT_Encode4(745096), // Rule ID 11543 //
     /*  745049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  745052 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745059 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745061 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745072 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  745075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745080 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745090 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745094 */     GIR_RootConstrainSelectedInstOperands,
     /*  745095 */     // GIR_Coverage, 11543,
     /*  745095 */     GIR_EraseRootFromParent_Done,
     /*  745096 */   // Label 11846: @745096
     /*  745096 */   GIM_Try, /*On fail goto*//*Label 11847*/ GIMT_Encode4(745148), // Rule ID 11544 //
     /*  745101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  745104 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745111 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745124 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
     /*  745127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745132 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745146 */     GIR_RootConstrainSelectedInstOperands,
     /*  745147 */     // GIR_Coverage, 11544,
     /*  745147 */     GIR_EraseRootFromParent_Done,
     /*  745148 */   // Label 11847: @745148
     /*  745148 */   GIM_Try, /*On fail goto*//*Label 11848*/ GIMT_Encode4(745205), // Rule ID 10974 //
     /*  745153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  745156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745168 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745179 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745189 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745203 */     GIR_RootConstrainSelectedInstOperands,
     /*  745204 */     // GIR_Coverage, 10974,
     /*  745204 */     GIR_EraseRootFromParent_Done,
     /*  745205 */   // Label 11848: @745205
     /*  745205 */   GIM_Try, /*On fail goto*//*Label 11849*/ GIMT_Encode4(745262), // Rule ID 10975 //
     /*  745210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  745213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745236 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745246 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745260 */     GIR_RootConstrainSelectedInstOperands,
     /*  745261 */     // GIR_Coverage, 10975,
     /*  745261 */     GIR_EraseRootFromParent_Done,
     /*  745262 */   // Label 11849: @745262
     /*  745262 */   GIM_Try, /*On fail goto*//*Label 11850*/ GIMT_Encode4(745319), // Rule ID 10976 //
     /*  745267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  745270 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745293 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745303 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745317 */     GIR_RootConstrainSelectedInstOperands,
     /*  745318 */     // GIR_Coverage, 10976,
     /*  745318 */     GIR_EraseRootFromParent_Done,
     /*  745319 */   // Label 11850: @745319
     /*  745319 */   GIM_Try, /*On fail goto*//*Label 11851*/ GIMT_Encode4(745376), // Rule ID 10977 //
     /*  745324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  745327 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745339 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745350 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745360 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745374 */     GIR_RootConstrainSelectedInstOperands,
     /*  745375 */     // GIR_Coverage, 10977,
     /*  745375 */     GIR_EraseRootFromParent_Done,
     /*  745376 */   // Label 11851: @745376
     /*  745376 */   GIM_Try, /*On fail goto*//*Label 11852*/ GIMT_Encode4(745433), // Rule ID 10978 //
     /*  745381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  745384 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745396 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745407 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745417 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745431 */     GIR_RootConstrainSelectedInstOperands,
     /*  745432 */     // GIR_Coverage, 10978,
     /*  745432 */     GIR_EraseRootFromParent_Done,
     /*  745433 */   // Label 11852: @745433
     /*  745433 */   GIM_Try, /*On fail goto*//*Label 11853*/ GIMT_Encode4(745489), // Rule ID 11530 //
     /*  745438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode0),
     /*  745441 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745452 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745463 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745473 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745487 */     GIR_RootConstrainSelectedInstOperands,
     /*  745488 */     // GIR_Coverage, 11530,
     /*  745488 */     GIR_EraseRootFromParent_Done,
     /*  745489 */   // Label 11853: @745489
     /*  745489 */   GIM_Try, /*On fail goto*//*Label 11854*/ GIMT_Encode4(745545), // Rule ID 11531 //
     /*  745494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode1),
     /*  745497 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745512 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745519 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745529 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745543 */     GIR_RootConstrainSelectedInstOperands,
     /*  745544 */     // GIR_Coverage, 11531,
     /*  745544 */     GIR_EraseRootFromParent_Done,
     /*  745545 */   // Label 11854: @745545
     /*  745545 */   GIM_Try, /*On fail goto*//*Label 11855*/ GIMT_Encode4(745601), // Rule ID 11532 //
     /*  745550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode2),
     /*  745553 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745564 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745568 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745575 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745585 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745599 */     GIR_RootConstrainSelectedInstOperands,
     /*  745600 */     // GIR_Coverage, 11532,
     /*  745600 */     GIR_EraseRootFromParent_Done,
     /*  745601 */   // Label 11855: @745601
     /*  745601 */   GIM_Try, /*On fail goto*//*Label 11856*/ GIMT_Encode4(745657), // Rule ID 11533 //
     /*  745606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode3),
     /*  745609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745631 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745641 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745655 */     GIR_RootConstrainSelectedInstOperands,
     /*  745656 */     // GIR_Coverage, 11533,
     /*  745656 */     GIR_EraseRootFromParent_Done,
     /*  745657 */   // Label 11856: @745657
     /*  745657 */   GIM_Try, /*On fail goto*//*Label 11857*/ GIMT_Encode4(745713), // Rule ID 11534 //
     /*  745662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HwMode4),
     /*  745665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  745676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  745687 */     // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
     /*  745687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
     /*  745690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  745692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  745697 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  745699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  745704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  745707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745711 */     GIR_RootConstrainSelectedInstOperands,
     /*  745712 */     // GIR_Coverage, 11534,
     /*  745712 */     GIR_EraseRootFromParent_Done,
     /*  745713 */   // Label 11857: @745713
     /*  745713 */   GIM_Reject,
     /*  745714 */ // Label 11727: @745714
     /*  745714 */ GIM_Reject,
     /*  745715 */ // Label 11603: @745715
     /*  745715 */ GIM_Reject,
     /*  745716 */ // Label 32: @745716
     /*  745716 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 11860*/ GIMT_Encode4(759327),
     /*  745727 */ /*GILLT_s32*//*Label 11858*/ GIMT_Encode4(745735),
     /*  745731 */ /*GILLT_s64*//*Label 11859*/ GIMT_Encode4(751827),
     /*  745735 */ // Label 11858: @745735
     /*  745735 */ GIM_Try, /*On fail goto*//*Label 11861*/ GIMT_Encode4(751826),
     /*  745740 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  745743 */   GIM_Try, /*On fail goto*//*Label 11862*/ GIMT_Encode4(745805), // Rule ID 21138 //
     /*  745748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  745751 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745758 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  745771 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  745771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64),
     /*  745774 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  745776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  745781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  745786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  745791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  745796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745803 */     GIR_RootConstrainSelectedInstOperands,
     /*  745804 */     // GIR_Coverage, 21138,
     /*  745804 */     GIR_EraseRootFromParent_Done,
     /*  745805 */   // Label 11862: @745805
     /*  745805 */   GIM_Try, /*On fail goto*//*Label 11863*/ GIMT_Encode4(745867), // Rule ID 21139 //
     /*  745810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  745813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745820 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  745833 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  745833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64),
     /*  745836 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  745838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  745843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  745848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  745853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  745858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745861 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745865 */     GIR_RootConstrainSelectedInstOperands,
     /*  745866 */     // GIR_Coverage, 21139,
     /*  745866 */     GIR_EraseRootFromParent_Done,
     /*  745867 */   // Label 11863: @745867
     /*  745867 */   GIM_Try, /*On fail goto*//*Label 11864*/ GIMT_Encode4(745929), // Rule ID 21140 //
     /*  745872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  745875 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745882 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745884 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  745895 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  745895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64),
     /*  745898 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  745900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  745905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  745910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  745915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  745920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745927 */     GIR_RootConstrainSelectedInstOperands,
     /*  745928 */     // GIR_Coverage, 21140,
     /*  745928 */     GIR_EraseRootFromParent_Done,
     /*  745929 */   // Label 11864: @745929
     /*  745929 */   GIM_Try, /*On fail goto*//*Label 11865*/ GIMT_Encode4(745991), // Rule ID 21141 //
     /*  745934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  745937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  745944 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  745946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  745950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  745957 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  745957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64),
     /*  745960 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  745962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  745967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  745972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  745977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  745982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  745985 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  745989 */     GIR_RootConstrainSelectedInstOperands,
     /*  745990 */     // GIR_Coverage, 21141,
     /*  745990 */     GIR_EraseRootFromParent_Done,
     /*  745991 */   // Label 11865: @745991
     /*  745991 */   GIM_Try, /*On fail goto*//*Label 11866*/ GIMT_Encode4(746053), // Rule ID 21142 //
     /*  745996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  745999 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746006 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  746008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746019 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64),
     /*  746022 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  746047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746051 */     GIR_RootConstrainSelectedInstOperands,
     /*  746052 */     // GIR_Coverage, 21142,
     /*  746052 */     GIR_EraseRootFromParent_Done,
     /*  746053 */   // Label 11866: @746053
     /*  746053 */   GIM_Try, /*On fail goto*//*Label 11867*/ GIMT_Encode4(746115), // Rule ID 21158 //
     /*  746058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  746061 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746068 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  746070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746081 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64),
     /*  746084 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  746109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746113 */     GIR_RootConstrainSelectedInstOperands,
     /*  746114 */     // GIR_Coverage, 21158,
     /*  746114 */     GIR_EraseRootFromParent_Done,
     /*  746115 */   // Label 11867: @746115
     /*  746115 */   GIM_Try, /*On fail goto*//*Label 11868*/ GIMT_Encode4(746177), // Rule ID 21159 //
     /*  746120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  746123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746130 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  746132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746143 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64),
     /*  746146 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  746171 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746175 */     GIR_RootConstrainSelectedInstOperands,
     /*  746176 */     // GIR_Coverage, 21159,
     /*  746176 */     GIR_EraseRootFromParent_Done,
     /*  746177 */   // Label 11868: @746177
     /*  746177 */   GIM_Try, /*On fail goto*//*Label 11869*/ GIMT_Encode4(746239), // Rule ID 21160 //
     /*  746182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  746185 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746192 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  746194 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746205 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64),
     /*  746208 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  746233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746237 */     GIR_RootConstrainSelectedInstOperands,
     /*  746238 */     // GIR_Coverage, 21160,
     /*  746238 */     GIR_EraseRootFromParent_Done,
     /*  746239 */   // Label 11869: @746239
     /*  746239 */   GIM_Try, /*On fail goto*//*Label 11870*/ GIMT_Encode4(746301), // Rule ID 21161 //
     /*  746244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  746247 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746254 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  746256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746267 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64),
     /*  746270 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  746295 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746299 */     GIR_RootConstrainSelectedInstOperands,
     /*  746300 */     // GIR_Coverage, 21161,
     /*  746300 */     GIR_EraseRootFromParent_Done,
     /*  746301 */   // Label 11870: @746301
     /*  746301 */   GIM_Try, /*On fail goto*//*Label 11871*/ GIMT_Encode4(746363), // Rule ID 21162 //
     /*  746306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  746309 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746316 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  746318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746329 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64),
     /*  746332 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  746357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746361 */     GIR_RootConstrainSelectedInstOperands,
     /*  746362 */     // GIR_Coverage, 21162,
     /*  746362 */     GIR_EraseRootFromParent_Done,
     /*  746363 */   // Label 11871: @746363
     /*  746363 */   GIM_Try, /*On fail goto*//*Label 11872*/ GIMT_Encode4(746429), // Rule ID 21128 //
     /*  746368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  746371 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746382 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746393 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN),
     /*  746396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746398 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746427 */     GIR_RootConstrainSelectedInstOperands,
     /*  746428 */     // GIR_Coverage, 21128,
     /*  746428 */     GIR_EraseRootFromParent_Done,
     /*  746429 */   // Label 11872: @746429
     /*  746429 */   GIM_Try, /*On fail goto*//*Label 11873*/ GIMT_Encode4(746495), // Rule ID 21129 //
     /*  746434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  746437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746459 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN),
     /*  746462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746464 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746489 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746493 */     GIR_RootConstrainSelectedInstOperands,
     /*  746494 */     // GIR_Coverage, 21129,
     /*  746494 */     GIR_EraseRootFromParent_Done,
     /*  746495 */   // Label 11873: @746495
     /*  746495 */   GIM_Try, /*On fail goto*//*Label 11874*/ GIMT_Encode4(746561), // Rule ID 21130 //
     /*  746500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  746503 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746525 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN),
     /*  746528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746530 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746559 */     GIR_RootConstrainSelectedInstOperands,
     /*  746560 */     // GIR_Coverage, 21130,
     /*  746560 */     GIR_EraseRootFromParent_Done,
     /*  746561 */   // Label 11874: @746561
     /*  746561 */   GIM_Try, /*On fail goto*//*Label 11875*/ GIMT_Encode4(746627), // Rule ID 21131 //
     /*  746566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  746569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746591 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN),
     /*  746594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746596 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746621 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746625 */     GIR_RootConstrainSelectedInstOperands,
     /*  746626 */     // GIR_Coverage, 21131,
     /*  746626 */     GIR_EraseRootFromParent_Done,
     /*  746627 */   // Label 11875: @746627
     /*  746627 */   GIM_Try, /*On fail goto*//*Label 11876*/ GIMT_Encode4(746693), // Rule ID 21132 //
     /*  746632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  746635 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746657 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN),
     /*  746660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746662 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746691 */     GIR_RootConstrainSelectedInstOperands,
     /*  746692 */     // GIR_Coverage, 21132,
     /*  746692 */     GIR_EraseRootFromParent_Done,
     /*  746693 */   // Label 11876: @746693
     /*  746693 */   GIM_Try, /*On fail goto*//*Label 11877*/ GIMT_Encode4(746759), // Rule ID 21148 //
     /*  746698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  746701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746723 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN),
     /*  746726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746728 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746753 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746757 */     GIR_RootConstrainSelectedInstOperands,
     /*  746758 */     // GIR_Coverage, 21148,
     /*  746758 */     GIR_EraseRootFromParent_Done,
     /*  746759 */   // Label 11877: @746759
     /*  746759 */   GIM_Try, /*On fail goto*//*Label 11878*/ GIMT_Encode4(746825), // Rule ID 21149 //
     /*  746764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  746767 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746782 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746789 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN),
     /*  746792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746794 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746823 */     GIR_RootConstrainSelectedInstOperands,
     /*  746824 */     // GIR_Coverage, 21149,
     /*  746824 */     GIR_EraseRootFromParent_Done,
     /*  746825 */   // Label 11878: @746825
     /*  746825 */   GIM_Try, /*On fail goto*//*Label 11879*/ GIMT_Encode4(746891), // Rule ID 21150 //
     /*  746830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  746833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746855 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN),
     /*  746858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746860 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746889 */     GIR_RootConstrainSelectedInstOperands,
     /*  746890 */     // GIR_Coverage, 21150,
     /*  746890 */     GIR_EraseRootFromParent_Done,
     /*  746891 */   // Label 11879: @746891
     /*  746891 */   GIM_Try, /*On fail goto*//*Label 11880*/ GIMT_Encode4(746957), // Rule ID 21151 //
     /*  746896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  746899 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746921 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN),
     /*  746924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746926 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  746938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  746943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  746948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  746951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  746955 */     GIR_RootConstrainSelectedInstOperands,
     /*  746956 */     // GIR_Coverage, 21151,
     /*  746956 */     GIR_EraseRootFromParent_Done,
     /*  746957 */   // Label 11880: @746957
     /*  746957 */   GIM_Try, /*On fail goto*//*Label 11881*/ GIMT_Encode4(747023), // Rule ID 21152 //
     /*  746962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  746965 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  746972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  746976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  746980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  746987 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  746987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN),
     /*  746990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  746992 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  746994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  746999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  747009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  747014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747017 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747021 */     GIR_RootConstrainSelectedInstOperands,
     /*  747022 */     // GIR_Coverage, 21152,
     /*  747022 */     GIR_EraseRootFromParent_Done,
     /*  747023 */   // Label 11881: @747023
     /*  747023 */   GIM_Try, /*On fail goto*//*Label 11882*/ GIMT_Encode4(747080), // Rule ID 21133 //
     /*  747028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  747031 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747038 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747040 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747044 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747051 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
     /*  747054 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747078 */     GIR_RootConstrainSelectedInstOperands,
     /*  747079 */     // GIR_Coverage, 21133,
     /*  747079 */     GIR_EraseRootFromParent_Done,
     /*  747080 */   // Label 11882: @747080
     /*  747080 */   GIM_Try, /*On fail goto*//*Label 11883*/ GIMT_Encode4(747137), // Rule ID 21134 //
     /*  747085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  747088 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747095 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747097 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747101 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747108 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
     /*  747111 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747135 */     GIR_RootConstrainSelectedInstOperands,
     /*  747136 */     // GIR_Coverage, 21134,
     /*  747136 */     GIR_EraseRootFromParent_Done,
     /*  747137 */   // Label 11883: @747137
     /*  747137 */   GIM_Try, /*On fail goto*//*Label 11884*/ GIMT_Encode4(747194), // Rule ID 21135 //
     /*  747142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  747145 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747152 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747165 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
     /*  747168 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747192 */     GIR_RootConstrainSelectedInstOperands,
     /*  747193 */     // GIR_Coverage, 21135,
     /*  747193 */     GIR_EraseRootFromParent_Done,
     /*  747194 */   // Label 11884: @747194
     /*  747194 */   GIM_Try, /*On fail goto*//*Label 11885*/ GIMT_Encode4(747251), // Rule ID 21136 //
     /*  747199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  747202 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747209 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747211 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747222 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
     /*  747225 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747245 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747249 */     GIR_RootConstrainSelectedInstOperands,
     /*  747250 */     // GIR_Coverage, 21136,
     /*  747250 */     GIR_EraseRootFromParent_Done,
     /*  747251 */   // Label 11885: @747251
     /*  747251 */   GIM_Try, /*On fail goto*//*Label 11886*/ GIMT_Encode4(747308), // Rule ID 21137 //
     /*  747256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  747259 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747266 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747279 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
     /*  747282 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747306 */     GIR_RootConstrainSelectedInstOperands,
     /*  747307 */     // GIR_Coverage, 21137,
     /*  747307 */     GIR_EraseRootFromParent_Done,
     /*  747308 */   // Label 11886: @747308
     /*  747308 */   GIM_Try, /*On fail goto*//*Label 11887*/ GIMT_Encode4(747365), // Rule ID 21153 //
     /*  747313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  747316 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747323 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747325 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747336 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
     /*  747339 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747363 */     GIR_RootConstrainSelectedInstOperands,
     /*  747364 */     // GIR_Coverage, 21153,
     /*  747364 */     GIR_EraseRootFromParent_Done,
     /*  747365 */   // Label 11887: @747365
     /*  747365 */   GIM_Try, /*On fail goto*//*Label 11888*/ GIMT_Encode4(747422), // Rule ID 21154 //
     /*  747370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  747373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747380 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747382 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747393 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
     /*  747396 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747416 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747420 */     GIR_RootConstrainSelectedInstOperands,
     /*  747421 */     // GIR_Coverage, 21154,
     /*  747421 */     GIR_EraseRootFromParent_Done,
     /*  747422 */   // Label 11888: @747422
     /*  747422 */   GIM_Try, /*On fail goto*//*Label 11889*/ GIMT_Encode4(747479), // Rule ID 21155 //
     /*  747427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  747430 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747437 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747439 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747443 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747450 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
     /*  747453 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747477 */     GIR_RootConstrainSelectedInstOperands,
     /*  747478 */     // GIR_Coverage, 21155,
     /*  747478 */     GIR_EraseRootFromParent_Done,
     /*  747479 */   // Label 11889: @747479
     /*  747479 */   GIM_Try, /*On fail goto*//*Label 11890*/ GIMT_Encode4(747536), // Rule ID 21156 //
     /*  747484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  747487 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747494 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747507 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
     /*  747510 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747534 */     GIR_RootConstrainSelectedInstOperands,
     /*  747535 */     // GIR_Coverage, 21156,
     /*  747535 */     GIR_EraseRootFromParent_Done,
     /*  747536 */   // Label 11890: @747536
     /*  747536 */   GIM_Try, /*On fail goto*//*Label 11891*/ GIMT_Encode4(747593), // Rule ID 21157 //
     /*  747541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  747544 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747551 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  747553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747564 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
     /*  747567 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  747587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747591 */     GIR_RootConstrainSelectedInstOperands,
     /*  747592 */     // GIR_Coverage, 21157,
     /*  747592 */     GIR_EraseRootFromParent_Done,
     /*  747593 */   // Label 11891: @747593
     /*  747593 */   GIM_Try, /*On fail goto*//*Label 11892*/ GIMT_Encode4(747654), // Rule ID 21123 //
     /*  747598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  747601 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747623 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
     /*  747626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747628 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747652 */     GIR_RootConstrainSelectedInstOperands,
     /*  747653 */     // GIR_Coverage, 21123,
     /*  747653 */     GIR_EraseRootFromParent_Done,
     /*  747654 */   // Label 11892: @747654
     /*  747654 */   GIM_Try, /*On fail goto*//*Label 11893*/ GIMT_Encode4(747715), // Rule ID 21124 //
     /*  747659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  747662 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747684 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
     /*  747687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747689 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747713 */     GIR_RootConstrainSelectedInstOperands,
     /*  747714 */     // GIR_Coverage, 21124,
     /*  747714 */     GIR_EraseRootFromParent_Done,
     /*  747715 */   // Label 11893: @747715
     /*  747715 */   GIM_Try, /*On fail goto*//*Label 11894*/ GIMT_Encode4(747776), // Rule ID 21125 //
     /*  747720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  747723 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747734 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747745 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
     /*  747748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747750 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747770 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747774 */     GIR_RootConstrainSelectedInstOperands,
     /*  747775 */     // GIR_Coverage, 21125,
     /*  747775 */     GIR_EraseRootFromParent_Done,
     /*  747776 */   // Label 11894: @747776
     /*  747776 */   GIM_Try, /*On fail goto*//*Label 11895*/ GIMT_Encode4(747837), // Rule ID 21126 //
     /*  747781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  747784 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747799 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747806 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
     /*  747809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747811 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747835 */     GIR_RootConstrainSelectedInstOperands,
     /*  747836 */     // GIR_Coverage, 21126,
     /*  747836 */     GIR_EraseRootFromParent_Done,
     /*  747837 */   // Label 11895: @747837
     /*  747837 */   GIM_Try, /*On fail goto*//*Label 11896*/ GIMT_Encode4(747898), // Rule ID 21127 //
     /*  747842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  747845 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747867 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
     /*  747870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747872 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747896 */     GIR_RootConstrainSelectedInstOperands,
     /*  747897 */     // GIR_Coverage, 21127,
     /*  747897 */     GIR_EraseRootFromParent_Done,
     /*  747898 */   // Label 11896: @747898
     /*  747898 */   GIM_Try, /*On fail goto*//*Label 11897*/ GIMT_Encode4(747959), // Rule ID 21143 //
     /*  747903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  747906 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747928 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
     /*  747931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747933 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  747940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  747945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  747950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  747953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  747957 */     GIR_RootConstrainSelectedInstOperands,
     /*  747958 */     // GIR_Coverage, 21143,
     /*  747958 */     GIR_EraseRootFromParent_Done,
     /*  747959 */   // Label 11897: @747959
     /*  747959 */   GIM_Try, /*On fail goto*//*Label 11898*/ GIMT_Encode4(748020), // Rule ID 21144 //
     /*  747964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  747967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  747974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  747978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  747982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  747989 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  747989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
     /*  747992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  747994 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  747996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  748001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  748006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  748011 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748018 */     GIR_RootConstrainSelectedInstOperands,
     /*  748019 */     // GIR_Coverage, 21144,
     /*  748019 */     GIR_EraseRootFromParent_Done,
     /*  748020 */   // Label 11898: @748020
     /*  748020 */   GIM_Try, /*On fail goto*//*Label 11899*/ GIMT_Encode4(748081), // Rule ID 21145 //
     /*  748025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  748028 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  748035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  748039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  748050 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  748050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
     /*  748053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  748055 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  748057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  748062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  748067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  748072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748079 */     GIR_RootConstrainSelectedInstOperands,
     /*  748080 */     // GIR_Coverage, 21145,
     /*  748080 */     GIR_EraseRootFromParent_Done,
     /*  748081 */   // Label 11899: @748081
     /*  748081 */   GIM_Try, /*On fail goto*//*Label 11900*/ GIMT_Encode4(748142), // Rule ID 21146 //
     /*  748086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  748089 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  748096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  748100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  748111 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  748111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
     /*  748114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  748116 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  748118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  748123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  748128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  748133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748140 */     GIR_RootConstrainSelectedInstOperands,
     /*  748141 */     // GIR_Coverage, 21146,
     /*  748141 */     GIR_EraseRootFromParent_Done,
     /*  748142 */   // Label 11900: @748142
     /*  748142 */   GIM_Try, /*On fail goto*//*Label 11901*/ GIMT_Encode4(748203), // Rule ID 21147 //
     /*  748147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  748150 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  748157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  748161 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  748172 */     // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  748172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
     /*  748175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  748177 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  748179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  748184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  748189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  748194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748197 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748201 */     GIR_RootConstrainSelectedInstOperands,
     /*  748202 */     // GIR_Coverage, 21147,
     /*  748202 */     GIR_EraseRootFromParent_Done,
     /*  748203 */   // Label 11901: @748203
     /*  748203 */   GIM_Try, /*On fail goto*//*Label 11902*/ GIMT_Encode4(748253), // Rule ID 30312 //
     /*  748208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  748211 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748216 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748229 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748237 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748251 */     GIR_RootConstrainSelectedInstOperands,
     /*  748252 */     // GIR_Coverage, 30312,
     /*  748252 */     GIR_EraseRootFromParent_Done,
     /*  748253 */   // Label 11902: @748253
     /*  748253 */   GIM_Try, /*On fail goto*//*Label 11903*/ GIMT_Encode4(748303), // Rule ID 30313 //
     /*  748258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  748261 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748266 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748279 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748287 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748301 */     GIR_RootConstrainSelectedInstOperands,
     /*  748302 */     // GIR_Coverage, 30313,
     /*  748302 */     GIR_EraseRootFromParent_Done,
     /*  748303 */   // Label 11903: @748303
     /*  748303 */   GIM_Try, /*On fail goto*//*Label 11904*/ GIMT_Encode4(748353), // Rule ID 30314 //
     /*  748308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  748311 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748316 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748329 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748337 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748347 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748351 */     GIR_RootConstrainSelectedInstOperands,
     /*  748352 */     // GIR_Coverage, 30314,
     /*  748352 */     GIR_EraseRootFromParent_Done,
     /*  748353 */   // Label 11904: @748353
     /*  748353 */   GIM_Try, /*On fail goto*//*Label 11905*/ GIMT_Encode4(748403), // Rule ID 30315 //
     /*  748358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  748361 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748366 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748372 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748379 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748387 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748401 */     GIR_RootConstrainSelectedInstOperands,
     /*  748402 */     // GIR_Coverage, 30315,
     /*  748402 */     GIR_EraseRootFromParent_Done,
     /*  748403 */   // Label 11905: @748403
     /*  748403 */   GIM_Try, /*On fail goto*//*Label 11906*/ GIMT_Encode4(748453), // Rule ID 30316 //
     /*  748408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  748411 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748416 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748429 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748437 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748451 */     GIR_RootConstrainSelectedInstOperands,
     /*  748452 */     // GIR_Coverage, 30316,
     /*  748452 */     GIR_EraseRootFromParent_Done,
     /*  748453 */   // Label 11906: @748453
     /*  748453 */   GIM_Try, /*On fail goto*//*Label 11907*/ GIMT_Encode4(748503), // Rule ID 30318 //
     /*  748458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  748461 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748466 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748479 */     // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i32>>  =>  (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9),
     /*  748482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748487 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748501 */     GIR_RootConstrainSelectedInstOperands,
     /*  748502 */     // GIR_Coverage, 30318,
     /*  748502 */     GIR_EraseRootFromParent_Done,
     /*  748503 */   // Label 11907: @748503
     /*  748503 */   GIM_Try, /*On fail goto*//*Label 11908*/ GIMT_Encode4(748553), // Rule ID 30319 //
     /*  748508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  748511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748516 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748529 */     // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i32>>  =>  (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9),
     /*  748532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748537 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748547 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748551 */     GIR_RootConstrainSelectedInstOperands,
     /*  748552 */     // GIR_Coverage, 30319,
     /*  748552 */     GIR_EraseRootFromParent_Done,
     /*  748553 */   // Label 11908: @748553
     /*  748553 */   GIM_Try, /*On fail goto*//*Label 11909*/ GIMT_Encode4(748603), // Rule ID 30320 //
     /*  748558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  748561 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748566 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748579 */     // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i32>>  =>  (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9),
     /*  748582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748587 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748601 */     GIR_RootConstrainSelectedInstOperands,
     /*  748602 */     // GIR_Coverage, 30320,
     /*  748602 */     GIR_EraseRootFromParent_Done,
     /*  748603 */   // Label 11909: @748603
     /*  748603 */   GIM_Try, /*On fail goto*//*Label 11910*/ GIMT_Encode4(748653), // Rule ID 30321 //
     /*  748608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  748611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748616 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748629 */     // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i32>>  =>  (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9),
     /*  748632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748637 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748651 */     GIR_RootConstrainSelectedInstOperands,
     /*  748652 */     // GIR_Coverage, 30321,
     /*  748652 */     GIR_EraseRootFromParent_Done,
     /*  748653 */   // Label 11910: @748653
     /*  748653 */   GIM_Try, /*On fail goto*//*Label 11911*/ GIMT_Encode4(748703), // Rule ID 30322 //
     /*  748658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  748661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748666 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748668 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748672 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748679 */     // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i32>>  =>  (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9),
     /*  748682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748687 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  748697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748701 */     GIR_RootConstrainSelectedInstOperands,
     /*  748702 */     // GIR_Coverage, 30322,
     /*  748702 */     GIR_EraseRootFromParent_Done,
     /*  748703 */   // Label 11911: @748703
     /*  748703 */   GIM_Try, /*On fail goto*//*Label 11912*/ GIMT_Encode4(748753), // Rule ID 30324 //
     /*  748708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  748711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  748716 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748718 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748722 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748729 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  748729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748737 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748744 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748751 */     GIR_RootConstrainSelectedInstOperands,
     /*  748752 */     // GIR_Coverage, 30324,
     /*  748752 */     GIR_EraseRootFromParent_Done,
     /*  748753 */   // Label 11912: @748753
     /*  748753 */   GIM_Try, /*On fail goto*//*Label 11913*/ GIMT_Encode4(748803), // Rule ID 30325 //
     /*  748758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  748761 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  748766 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748768 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748779 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  748779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748787 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748797 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748801 */     GIR_RootConstrainSelectedInstOperands,
     /*  748802 */     // GIR_Coverage, 30325,
     /*  748802 */     GIR_EraseRootFromParent_Done,
     /*  748803 */   // Label 11913: @748803
     /*  748803 */   GIM_Try, /*On fail goto*//*Label 11914*/ GIMT_Encode4(748853), // Rule ID 30326 //
     /*  748808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  748811 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  748816 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748829 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  748829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748837 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748851 */     GIR_RootConstrainSelectedInstOperands,
     /*  748852 */     // GIR_Coverage, 30326,
     /*  748852 */     GIR_EraseRootFromParent_Done,
     /*  748853 */   // Label 11914: @748853
     /*  748853 */   GIM_Try, /*On fail goto*//*Label 11915*/ GIMT_Encode4(748903), // Rule ID 30327 //
     /*  748858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  748861 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  748866 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748879 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  748879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748887 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748897 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748901 */     GIR_RootConstrainSelectedInstOperands,
     /*  748902 */     // GIR_Coverage, 30327,
     /*  748902 */     GIR_EraseRootFromParent_Done,
     /*  748903 */   // Label 11915: @748903
     /*  748903 */   GIM_Try, /*On fail goto*//*Label 11916*/ GIMT_Encode4(748953), // Rule ID 30328 //
     /*  748908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  748911 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  748916 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  748918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748929 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  748929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
     /*  748932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748937 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  748947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  748951 */     GIR_RootConstrainSelectedInstOperands,
     /*  748952 */     // GIR_Coverage, 30328,
     /*  748952 */     GIR_EraseRootFromParent_Done,
     /*  748953 */   // Label 11916: @748953
     /*  748953 */   GIM_Try, /*On fail goto*//*Label 11917*/ GIMT_Encode4(749007), // Rule ID 30311 //
     /*  748958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  748961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  748966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  748970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  748974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  748981 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i32>>  =>  (DS_INC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  748981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32),
     /*  748984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  748986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  748991 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  748993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  748998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749005 */     GIR_RootConstrainSelectedInstOperands,
     /*  749006 */     // GIR_Coverage, 30311,
     /*  749006 */     GIR_EraseRootFromParent_Done,
     /*  749007 */   // Label 11917: @749007
     /*  749007 */   GIM_Try, /*On fail goto*//*Label 11918*/ GIMT_Encode4(749061), // Rule ID 30317 //
     /*  749012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  749015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  749020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  749035 */     // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i32>>  =>  (DS_INC_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  749035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32_gfx9),
     /*  749038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  749045 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  749047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749055 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749059 */     GIR_RootConstrainSelectedInstOperands,
     /*  749060 */     // GIR_Coverage, 30317,
     /*  749060 */     GIR_EraseRootFromParent_Done,
     /*  749061 */   // Label 11918: @749061
     /*  749061 */   GIM_Try, /*On fail goto*//*Label 11919*/ GIMT_Encode4(749115), // Rule ID 30323 //
     /*  749066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  749069 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  749074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  749089 */     // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i32>>  =>  (DS_INC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  749089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32),
     /*  749092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  749099 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  749101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  749109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749113 */     GIR_RootConstrainSelectedInstOperands,
     /*  749114 */     // GIR_Coverage, 30323,
     /*  749114 */     GIR_EraseRootFromParent_Done,
     /*  749115 */   // Label 11919: @749115
     /*  749115 */   GIM_Try, /*On fail goto*//*Label 11920*/ GIMT_Encode4(749174), // Rule ID 12913 //
     /*  749120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  749123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749130 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  749143 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  749143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR),
     /*  749146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  749151 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  749158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  749163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  749168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749172 */     GIR_RootConstrainSelectedInstOperands,
     /*  749173 */     // GIR_Coverage, 12913,
     /*  749173 */     GIR_EraseRootFromParent_Done,
     /*  749174 */   // Label 11920: @749174
     /*  749174 */   GIM_Try, /*On fail goto*//*Label 11921*/ GIMT_Encode4(749233), // Rule ID 12914 //
     /*  749179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  749182 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749189 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  749202 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  749202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR),
     /*  749205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  749210 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  749217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  749222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  749227 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749231 */     GIR_RootConstrainSelectedInstOperands,
     /*  749232 */     // GIR_Coverage, 12914,
     /*  749232 */     GIR_EraseRootFromParent_Done,
     /*  749233 */   // Label 11921: @749233
     /*  749233 */   GIM_Try, /*On fail goto*//*Label 11922*/ GIMT_Encode4(749292), // Rule ID 12915 //
     /*  749238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  749241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749248 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  749261 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  749261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR),
     /*  749264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  749269 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  749276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  749281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  749286 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749290 */     GIR_RootConstrainSelectedInstOperands,
     /*  749291 */     // GIR_Coverage, 12915,
     /*  749291 */     GIR_EraseRootFromParent_Done,
     /*  749292 */   // Label 11922: @749292
     /*  749292 */   GIM_Try, /*On fail goto*//*Label 11923*/ GIMT_Encode4(749351), // Rule ID 12916 //
     /*  749297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  749300 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749307 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749309 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  749320 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  749320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR),
     /*  749323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  749328 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  749335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  749340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  749345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749349 */     GIR_RootConstrainSelectedInstOperands,
     /*  749350 */     // GIR_Coverage, 12916,
     /*  749350 */     GIR_EraseRootFromParent_Done,
     /*  749351 */   // Label 11923: @749351
     /*  749351 */   GIM_Try, /*On fail goto*//*Label 11924*/ GIMT_Encode4(749410), // Rule ID 12917 //
     /*  749356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  749359 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749366 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749368 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749372 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  749379 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  749379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR),
     /*  749382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  749387 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  749394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  749399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  749404 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749408 */     GIR_RootConstrainSelectedInstOperands,
     /*  749409 */     // GIR_Coverage, 12917,
     /*  749409 */     GIR_EraseRootFromParent_Done,
     /*  749410 */   // Label 11924: @749410
     /*  749410 */   GIM_Try, /*On fail goto*//*Label 11925*/ GIMT_Encode4(749473), // Rule ID 12923 //
     /*  749415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  749418 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  749440 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_INC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  749440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN),
     /*  749443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  749450 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  749457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  749462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  749467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749471 */     GIR_RootConstrainSelectedInstOperands,
     /*  749472 */     // GIR_Coverage, 12923,
     /*  749472 */     GIR_EraseRootFromParent_Done,
     /*  749473 */   // Label 11925: @749473
     /*  749473 */   GIM_Try, /*On fail goto*//*Label 11926*/ GIMT_Encode4(749525), // Rule ID 12908 //
     /*  749478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  749481 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749488 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749490 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749501 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC),
     /*  749504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749509 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749519 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749523 */     GIR_RootConstrainSelectedInstOperands,
     /*  749524 */     // GIR_Coverage, 12908,
     /*  749524 */     GIR_EraseRootFromParent_Done,
     /*  749525 */   // Label 11926: @749525
     /*  749525 */   GIM_Try, /*On fail goto*//*Label 11927*/ GIMT_Encode4(749577), // Rule ID 12909 //
     /*  749530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  749533 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749540 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749553 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC),
     /*  749556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749561 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749571 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749575 */     GIR_RootConstrainSelectedInstOperands,
     /*  749576 */     // GIR_Coverage, 12909,
     /*  749576 */     GIR_EraseRootFromParent_Done,
     /*  749577 */   // Label 11927: @749577
     /*  749577 */   GIM_Try, /*On fail goto*//*Label 11928*/ GIMT_Encode4(749629), // Rule ID 12910 //
     /*  749582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  749585 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749592 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749605 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC),
     /*  749608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749613 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749615 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749627 */     GIR_RootConstrainSelectedInstOperands,
     /*  749628 */     // GIR_Coverage, 12910,
     /*  749628 */     GIR_EraseRootFromParent_Done,
     /*  749629 */   // Label 11928: @749629
     /*  749629 */   GIM_Try, /*On fail goto*//*Label 11929*/ GIMT_Encode4(749681), // Rule ID 12911 //
     /*  749634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  749637 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749644 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749657 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC),
     /*  749660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749665 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749679 */     GIR_RootConstrainSelectedInstOperands,
     /*  749680 */     // GIR_Coverage, 12911,
     /*  749680 */     GIR_EraseRootFromParent_Done,
     /*  749681 */   // Label 11929: @749681
     /*  749681 */   GIM_Try, /*On fail goto*//*Label 11930*/ GIMT_Encode4(749733), // Rule ID 12912 //
     /*  749686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  749689 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749696 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  749698 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749702 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749709 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC),
     /*  749712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749717 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  749727 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749731 */     GIR_RootConstrainSelectedInstOperands,
     /*  749732 */     // GIR_Coverage, 12912,
     /*  749732 */     GIR_EraseRootFromParent_Done,
     /*  749733 */   // Label 11930: @749733
     /*  749733 */   GIM_Try, /*On fail goto*//*Label 11931*/ GIMT_Encode4(749789), // Rule ID 12918 //
     /*  749738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  749741 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749763 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN),
     /*  749766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749773 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  749783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749787 */     GIR_RootConstrainSelectedInstOperands,
     /*  749788 */     // GIR_Coverage, 12918,
     /*  749788 */     GIR_EraseRootFromParent_Done,
     /*  749789 */   // Label 11931: @749789
     /*  749789 */   GIM_Try, /*On fail goto*//*Label 11932*/ GIMT_Encode4(749845), // Rule ID 12919 //
     /*  749794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  749797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749808 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749812 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749819 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN),
     /*  749822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749829 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  749839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749843 */     GIR_RootConstrainSelectedInstOperands,
     /*  749844 */     // GIR_Coverage, 12919,
     /*  749844 */     GIR_EraseRootFromParent_Done,
     /*  749845 */   // Label 11932: @749845
     /*  749845 */   GIM_Try, /*On fail goto*//*Label 11933*/ GIMT_Encode4(749901), // Rule ID 12920 //
     /*  749850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  749853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749864 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749875 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN),
     /*  749878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749885 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  749895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749899 */     GIR_RootConstrainSelectedInstOperands,
     /*  749900 */     // GIR_Coverage, 12920,
     /*  749900 */     GIR_EraseRootFromParent_Done,
     /*  749901 */   // Label 11933: @749901
     /*  749901 */   GIM_Try, /*On fail goto*//*Label 11934*/ GIMT_Encode4(749957), // Rule ID 12921 //
     /*  749906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  749909 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749920 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749931 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN),
     /*  749934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749941 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  749948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  749951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  749955 */     GIR_RootConstrainSelectedInstOperands,
     /*  749956 */     // GIR_Coverage, 12921,
     /*  749956 */     GIR_EraseRootFromParent_Done,
     /*  749957 */   // Label 11934: @749957
     /*  749957 */   GIM_Try, /*On fail goto*//*Label 11935*/ GIMT_Encode4(750013), // Rule ID 12922 //
     /*  749962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  749965 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  749972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  749976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  749980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  749987 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  749987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN),
     /*  749990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  749992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  749997 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  749999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  750004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  750007 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750011 */     GIR_RootConstrainSelectedInstOperands,
     /*  750012 */     // GIR_Coverage, 12922,
     /*  750012 */     GIR_EraseRootFromParent_Done,
     /*  750013 */   // Label 11935: @750013
     /*  750013 */   GIM_Try, /*On fail goto*//*Label 11936*/ GIMT_Encode4(750073), // Rule ID 10513 //
     /*  750018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  750021 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750029 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750042 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750050 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750071 */     GIR_RootConstrainSelectedInstOperands,
     /*  750072 */     // GIR_Coverage, 10513,
     /*  750072 */     GIR_EraseRootFromParent_Done,
     /*  750073 */   // Label 11936: @750073
     /*  750073 */   GIM_Try, /*On fail goto*//*Label 11937*/ GIMT_Encode4(750133), // Rule ID 10514 //
     /*  750078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  750081 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750089 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750091 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750102 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750110 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750131 */     GIR_RootConstrainSelectedInstOperands,
     /*  750132 */     // GIR_Coverage, 10514,
     /*  750132 */     GIR_EraseRootFromParent_Done,
     /*  750133 */   // Label 11937: @750133
     /*  750133 */   GIM_Try, /*On fail goto*//*Label 11938*/ GIMT_Encode4(750193), // Rule ID 10515 //
     /*  750138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  750141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750149 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750151 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750162 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750170 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750191 */     GIR_RootConstrainSelectedInstOperands,
     /*  750192 */     // GIR_Coverage, 10515,
     /*  750192 */     GIR_EraseRootFromParent_Done,
     /*  750193 */   // Label 11938: @750193
     /*  750193 */   GIM_Try, /*On fail goto*//*Label 11939*/ GIMT_Encode4(750253), // Rule ID 10516 //
     /*  750198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  750201 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750209 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750211 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750222 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750230 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750251 */     GIR_RootConstrainSelectedInstOperands,
     /*  750252 */     // GIR_Coverage, 10516,
     /*  750252 */     GIR_EraseRootFromParent_Done,
     /*  750253 */   // Label 11939: @750253
     /*  750253 */   GIM_Try, /*On fail goto*//*Label 11940*/ GIMT_Encode4(750313), // Rule ID 10517 //
     /*  750258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  750261 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750269 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750271 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750282 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750290 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750311 */     GIR_RootConstrainSelectedInstOperands,
     /*  750312 */     // GIR_Coverage, 10517,
     /*  750312 */     GIR_EraseRootFromParent_Done,
     /*  750313 */   // Label 11940: @750313
     /*  750313 */   GIM_Try, /*On fail goto*//*Label 11941*/ GIMT_Encode4(750372), // Rule ID 11069 //
     /*  750318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  750321 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750328 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750341 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750349 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750370 */     GIR_RootConstrainSelectedInstOperands,
     /*  750371 */     // GIR_Coverage, 11069,
     /*  750371 */     GIR_EraseRootFromParent_Done,
     /*  750372 */   // Label 11941: @750372
     /*  750372 */   GIM_Try, /*On fail goto*//*Label 11942*/ GIMT_Encode4(750431), // Rule ID 11070 //
     /*  750377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  750380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750387 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750400 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750408 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750429 */     GIR_RootConstrainSelectedInstOperands,
     /*  750430 */     // GIR_Coverage, 11070,
     /*  750430 */     GIR_EraseRootFromParent_Done,
     /*  750431 */   // Label 11942: @750431
     /*  750431 */   GIM_Try, /*On fail goto*//*Label 11943*/ GIMT_Encode4(750490), // Rule ID 11071 //
     /*  750436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  750439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750446 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750459 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750467 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750488 */     GIR_RootConstrainSelectedInstOperands,
     /*  750489 */     // GIR_Coverage, 11071,
     /*  750489 */     GIR_EraseRootFromParent_Done,
     /*  750490 */   // Label 11943: @750490
     /*  750490 */   GIM_Try, /*On fail goto*//*Label 11944*/ GIMT_Encode4(750549), // Rule ID 11072 //
     /*  750495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  750498 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750505 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750507 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750518 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750526 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750547 */     GIR_RootConstrainSelectedInstOperands,
     /*  750548 */     // GIR_Coverage, 11072,
     /*  750548 */     GIR_EraseRootFromParent_Done,
     /*  750549 */   // Label 11944: @750549
     /*  750549 */   GIM_Try, /*On fail goto*//*Label 11945*/ GIMT_Encode4(750608), // Rule ID 11073 //
     /*  750554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  750557 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750564 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  750577 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR),
     /*  750580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750585 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750606 */     GIR_RootConstrainSelectedInstOperands,
     /*  750607 */     // GIR_Coverage, 11073,
     /*  750607 */     GIR_EraseRootFromParent_Done,
     /*  750608 */   // Label 11945: @750608
     /*  750608 */   GIM_Try, /*On fail goto*//*Label 11946*/ GIMT_Encode4(750672), // Rule ID 10507 //
     /*  750613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  750616 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  750628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750632 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  750639 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>>  =>  (FLAT_ATOMIC_INC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR_RTN),
     /*  750642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  750644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750649 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750666 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750670 */     GIR_RootConstrainSelectedInstOperands,
     /*  750671 */     // GIR_Coverage, 10507,
     /*  750671 */     GIR_EraseRootFromParent_Done,
     /*  750672 */   // Label 11946: @750672
     /*  750672 */   GIM_Try, /*On fail goto*//*Label 11947*/ GIMT_Encode4(750735), // Rule ID 11063 //
     /*  750677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  750680 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  750691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  750702 */     // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (FLAT_ATOMIC_INC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  750702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_SADDR_RTN),
     /*  750705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  750707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  750712 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  750719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  750724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  750729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750733 */     GIR_RootConstrainSelectedInstOperands,
     /*  750734 */     // GIR_Coverage, 11063,
     /*  750734 */     GIR_EraseRootFromParent_Done,
     /*  750735 */   // Label 11947: @750735
     /*  750735 */   GIM_Try, /*On fail goto*//*Label 11948*/ GIMT_Encode4(750788), // Rule ID 10508 //
     /*  750740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  750743 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750751 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  750764 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  750764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  750767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  750772 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  750779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  750782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750786 */     GIR_RootConstrainSelectedInstOperands,
     /*  750787 */     // GIR_Coverage, 10508,
     /*  750787 */     GIR_EraseRootFromParent_Done,
     /*  750788 */   // Label 11948: @750788
     /*  750788 */   GIM_Try, /*On fail goto*//*Label 11949*/ GIMT_Encode4(750841), // Rule ID 10509 //
     /*  750793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  750796 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750804 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750806 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  750817 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  750817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  750820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  750825 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  750832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  750835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750839 */     GIR_RootConstrainSelectedInstOperands,
     /*  750840 */     // GIR_Coverage, 10509,
     /*  750840 */     GIR_EraseRootFromParent_Done,
     /*  750841 */   // Label 11949: @750841
     /*  750841 */   GIM_Try, /*On fail goto*//*Label 11950*/ GIMT_Encode4(750894), // Rule ID 10510 //
     /*  750846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  750849 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750857 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  750870 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  750870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  750873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  750878 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  750885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  750888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750892 */     GIR_RootConstrainSelectedInstOperands,
     /*  750893 */     // GIR_Coverage, 10510,
     /*  750893 */     GIR_EraseRootFromParent_Done,
     /*  750894 */   // Label 11950: @750894
     /*  750894 */   GIM_Try, /*On fail goto*//*Label 11951*/ GIMT_Encode4(750947), // Rule ID 10511 //
     /*  750899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  750902 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750910 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  750923 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  750923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  750926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  750931 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  750938 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  750941 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750945 */     GIR_RootConstrainSelectedInstOperands,
     /*  750946 */     // GIR_Coverage, 10511,
     /*  750946 */     GIR_EraseRootFromParent_Done,
     /*  750947 */   // Label 11951: @750947
     /*  750947 */   GIM_Try, /*On fail goto*//*Label 11952*/ GIMT_Encode4(751000), // Rule ID 10512 //
     /*  750952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  750955 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  750963 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  750965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  750969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  750976 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  750976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  750979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  750984 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  750986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  750991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  750994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  750998 */     GIR_RootConstrainSelectedInstOperands,
     /*  750999 */     // GIR_Coverage, 10512,
     /*  750999 */     GIR_EraseRootFromParent_Done,
     /*  751000 */   // Label 11952: @751000
     /*  751000 */   GIM_Try, /*On fail goto*//*Label 11953*/ GIMT_Encode4(751052), // Rule ID 11064 //
     /*  751005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  751008 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751015 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751017 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751028 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  751031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751036 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751050 */     GIR_RootConstrainSelectedInstOperands,
     /*  751051 */     // GIR_Coverage, 11064,
     /*  751051 */     GIR_EraseRootFromParent_Done,
     /*  751052 */   // Label 11953: @751052
     /*  751052 */   GIM_Try, /*On fail goto*//*Label 11954*/ GIMT_Encode4(751104), // Rule ID 11065 //
     /*  751057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  751060 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751067 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751069 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751080 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  751083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751088 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751102 */     GIR_RootConstrainSelectedInstOperands,
     /*  751103 */     // GIR_Coverage, 11065,
     /*  751103 */     GIR_EraseRootFromParent_Done,
     /*  751104 */   // Label 11954: @751104
     /*  751104 */   GIM_Try, /*On fail goto*//*Label 11955*/ GIMT_Encode4(751156), // Rule ID 11066 //
     /*  751109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  751112 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751119 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751132 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  751135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751140 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751154 */     GIR_RootConstrainSelectedInstOperands,
     /*  751155 */     // GIR_Coverage, 11066,
     /*  751155 */     GIR_EraseRootFromParent_Done,
     /*  751156 */   // Label 11955: @751156
     /*  751156 */   GIM_Try, /*On fail goto*//*Label 11956*/ GIMT_Encode4(751208), // Rule ID 11067 //
     /*  751161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  751164 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751171 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751184 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  751187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751192 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751206 */     GIR_RootConstrainSelectedInstOperands,
     /*  751207 */     // GIR_Coverage, 11067,
     /*  751207 */     GIR_EraseRootFromParent_Done,
     /*  751208 */   // Label 11956: @751208
     /*  751208 */   GIM_Try, /*On fail goto*//*Label 11957*/ GIMT_Encode4(751260), // Rule ID 11068 //
     /*  751213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  751216 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751236 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_INC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
     /*  751239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751244 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751258 */     GIR_RootConstrainSelectedInstOperands,
     /*  751259 */     // GIR_Coverage, 11068,
     /*  751259 */     GIR_EraseRootFromParent_Done,
     /*  751260 */   // Label 11957: @751260
     /*  751260 */   GIM_Try, /*On fail goto*//*Label 11958*/ GIMT_Encode4(751317), // Rule ID 10502 //
     /*  751265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  751268 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751291 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751301 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751311 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751315 */     GIR_RootConstrainSelectedInstOperands,
     /*  751316 */     // GIR_Coverage, 10502,
     /*  751316 */     GIR_EraseRootFromParent_Done,
     /*  751317 */   // Label 11958: @751317
     /*  751317 */   GIM_Try, /*On fail goto*//*Label 11959*/ GIMT_Encode4(751374), // Rule ID 10503 //
     /*  751322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  751325 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751348 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751358 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751368 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751372 */     GIR_RootConstrainSelectedInstOperands,
     /*  751373 */     // GIR_Coverage, 10503,
     /*  751373 */     GIR_EraseRootFromParent_Done,
     /*  751374 */   // Label 11959: @751374
     /*  751374 */   GIM_Try, /*On fail goto*//*Label 11960*/ GIMT_Encode4(751431), // Rule ID 10504 //
     /*  751379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  751382 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751394 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751398 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751405 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751415 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751425 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751429 */     GIR_RootConstrainSelectedInstOperands,
     /*  751430 */     // GIR_Coverage, 10504,
     /*  751430 */     GIR_EraseRootFromParent_Done,
     /*  751431 */   // Label 11960: @751431
     /*  751431 */   GIM_Try, /*On fail goto*//*Label 11961*/ GIMT_Encode4(751488), // Rule ID 10505 //
     /*  751436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  751439 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751462 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751472 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751482 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751486 */     GIR_RootConstrainSelectedInstOperands,
     /*  751487 */     // GIR_Coverage, 10505,
     /*  751487 */     GIR_EraseRootFromParent_Done,
     /*  751488 */   // Label 11961: @751488
     /*  751488 */   GIM_Try, /*On fail goto*//*Label 11962*/ GIMT_Encode4(751545), // Rule ID 10506 //
     /*  751493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  751496 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751512 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751519 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751529 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751543 */     GIR_RootConstrainSelectedInstOperands,
     /*  751544 */     // GIR_Coverage, 10506,
     /*  751544 */     GIR_EraseRootFromParent_Done,
     /*  751545 */   // Label 11962: @751545
     /*  751545 */   GIM_Try, /*On fail goto*//*Label 11963*/ GIMT_Encode4(751601), // Rule ID 11058 //
     /*  751550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  751553 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751564 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751568 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751575 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751585 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751599 */     GIR_RootConstrainSelectedInstOperands,
     /*  751600 */     // GIR_Coverage, 11058,
     /*  751600 */     GIR_EraseRootFromParent_Done,
     /*  751601 */   // Label 11963: @751601
     /*  751601 */   GIM_Try, /*On fail goto*//*Label 11964*/ GIMT_Encode4(751657), // Rule ID 11059 //
     /*  751606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  751609 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751631 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751641 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751655 */     GIR_RootConstrainSelectedInstOperands,
     /*  751656 */     // GIR_Coverage, 11059,
     /*  751656 */     GIR_EraseRootFromParent_Done,
     /*  751657 */   // Label 11964: @751657
     /*  751657 */   GIM_Try, /*On fail goto*//*Label 11965*/ GIMT_Encode4(751713), // Rule ID 11060 //
     /*  751662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  751665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751687 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751697 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751711 */     GIR_RootConstrainSelectedInstOperands,
     /*  751712 */     // GIR_Coverage, 11060,
     /*  751712 */     GIR_EraseRootFromParent_Done,
     /*  751713 */   // Label 11965: @751713
     /*  751713 */   GIM_Try, /*On fail goto*//*Label 11966*/ GIMT_Encode4(751769), // Rule ID 11061 //
     /*  751718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  751721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751743 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751753 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751767 */     GIR_RootConstrainSelectedInstOperands,
     /*  751768 */     // GIR_Coverage, 11061,
     /*  751768 */     GIR_EraseRootFromParent_Done,
     /*  751769 */   // Label 11966: @751769
     /*  751769 */   GIM_Try, /*On fail goto*//*Label 11967*/ GIMT_Encode4(751825), // Rule ID 11062 //
     /*  751774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  751777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  751788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  751799 */     // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  751799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
     /*  751802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  751804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  751809 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  751811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  751816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  751819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751823 */     GIR_RootConstrainSelectedInstOperands,
     /*  751824 */     // GIR_Coverage, 11062,
     /*  751824 */     GIR_EraseRootFromParent_Done,
     /*  751825 */   // Label 11967: @751825
     /*  751825 */   GIM_Reject,
     /*  751826 */ // Label 11861: @751826
     /*  751826 */ GIM_Reject,
     /*  751827 */ // Label 11859: @751827
     /*  751827 */ GIM_Try, /*On fail goto*//*Label 11968*/ GIMT_Encode4(759326),
     /*  751832 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  751835 */   GIM_Try, /*On fail goto*//*Label 11969*/ GIMT_Encode4(751897), // Rule ID 21618 //
     /*  751840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  751843 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751850 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  751863 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  751863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64),
     /*  751866 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  751868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  751873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  751878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  751883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  751888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751895 */     GIR_RootConstrainSelectedInstOperands,
     /*  751896 */     // GIR_Coverage, 21618,
     /*  751896 */     GIR_EraseRootFromParent_Done,
     /*  751897 */   // Label 11969: @751897
     /*  751897 */   GIM_Try, /*On fail goto*//*Label 11970*/ GIMT_Encode4(751959), // Rule ID 21619 //
     /*  751902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  751905 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751912 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751918 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  751925 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  751925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64),
     /*  751928 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  751930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  751935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  751940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  751945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  751950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  751953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  751957 */     GIR_RootConstrainSelectedInstOperands,
     /*  751958 */     // GIR_Coverage, 21619,
     /*  751958 */     GIR_EraseRootFromParent_Done,
     /*  751959 */   // Label 11970: @751959
     /*  751959 */   GIM_Try, /*On fail goto*//*Label 11971*/ GIMT_Encode4(752021), // Rule ID 21620 //
     /*  751964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  751967 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  751974 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  751976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  751980 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  751987 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  751987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64),
     /*  751990 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  751992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  751997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752015 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752019 */     GIR_RootConstrainSelectedInstOperands,
     /*  752020 */     // GIR_Coverage, 21620,
     /*  752020 */     GIR_EraseRootFromParent_Done,
     /*  752021 */   // Label 11971: @752021
     /*  752021 */   GIM_Try, /*On fail goto*//*Label 11972*/ GIMT_Encode4(752083), // Rule ID 21621 //
     /*  752026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  752029 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752036 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752049 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64),
     /*  752052 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752074 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752077 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752081 */     GIR_RootConstrainSelectedInstOperands,
     /*  752082 */     // GIR_Coverage, 21621,
     /*  752082 */     GIR_EraseRootFromParent_Done,
     /*  752083 */   // Label 11972: @752083
     /*  752083 */   GIM_Try, /*On fail goto*//*Label 11973*/ GIMT_Encode4(752145), // Rule ID 21622 //
     /*  752088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  752091 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752098 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752111 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64),
     /*  752114 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752143 */     GIR_RootConstrainSelectedInstOperands,
     /*  752144 */     // GIR_Coverage, 21622,
     /*  752144 */     GIR_EraseRootFromParent_Done,
     /*  752145 */   // Label 11973: @752145
     /*  752145 */   GIM_Try, /*On fail goto*//*Label 11974*/ GIMT_Encode4(752207), // Rule ID 21638 //
     /*  752150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  752153 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752160 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752162 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752166 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752173 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64),
     /*  752176 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752205 */     GIR_RootConstrainSelectedInstOperands,
     /*  752206 */     // GIR_Coverage, 21638,
     /*  752206 */     GIR_EraseRootFromParent_Done,
     /*  752207 */   // Label 11974: @752207
     /*  752207 */   GIM_Try, /*On fail goto*//*Label 11975*/ GIMT_Encode4(752269), // Rule ID 21639 //
     /*  752212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  752215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752222 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752235 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64),
     /*  752238 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752263 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752267 */     GIR_RootConstrainSelectedInstOperands,
     /*  752268 */     // GIR_Coverage, 21639,
     /*  752268 */     GIR_EraseRootFromParent_Done,
     /*  752269 */   // Label 11975: @752269
     /*  752269 */   GIM_Try, /*On fail goto*//*Label 11976*/ GIMT_Encode4(752331), // Rule ID 21640 //
     /*  752274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  752277 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752284 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752286 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752290 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752297 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64),
     /*  752300 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752329 */     GIR_RootConstrainSelectedInstOperands,
     /*  752330 */     // GIR_Coverage, 21640,
     /*  752330 */     GIR_EraseRootFromParent_Done,
     /*  752331 */   // Label 11976: @752331
     /*  752331 */   GIM_Try, /*On fail goto*//*Label 11977*/ GIMT_Encode4(752393), // Rule ID 21641 //
     /*  752336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  752339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752346 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752359 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64),
     /*  752362 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752391 */     GIR_RootConstrainSelectedInstOperands,
     /*  752392 */     // GIR_Coverage, 21641,
     /*  752392 */     GIR_EraseRootFromParent_Done,
     /*  752393 */   // Label 11977: @752393
     /*  752393 */   GIM_Try, /*On fail goto*//*Label 11978*/ GIMT_Encode4(752455), // Rule ID 21642 //
     /*  752398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  752401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752408 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  752410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752421 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64),
     /*  752424 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752446 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  752449 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752453 */     GIR_RootConstrainSelectedInstOperands,
     /*  752454 */     // GIR_Coverage, 21642,
     /*  752454 */     GIR_EraseRootFromParent_Done,
     /*  752455 */   // Label 11978: @752455
     /*  752455 */   GIM_Try, /*On fail goto*//*Label 11979*/ GIMT_Encode4(752521), // Rule ID 21608 //
     /*  752460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  752463 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752485 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN),
     /*  752488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752490 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752512 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752515 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752519 */     GIR_RootConstrainSelectedInstOperands,
     /*  752520 */     // GIR_Coverage, 21608,
     /*  752520 */     GIR_EraseRootFromParent_Done,
     /*  752521 */   // Label 11979: @752521
     /*  752521 */   GIM_Try, /*On fail goto*//*Label 11980*/ GIMT_Encode4(752587), // Rule ID 21609 //
     /*  752526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  752529 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752540 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752551 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN),
     /*  752554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752556 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752581 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752585 */     GIR_RootConstrainSelectedInstOperands,
     /*  752586 */     // GIR_Coverage, 21609,
     /*  752586 */     GIR_EraseRootFromParent_Done,
     /*  752587 */   // Label 11980: @752587
     /*  752587 */   GIM_Try, /*On fail goto*//*Label 11981*/ GIMT_Encode4(752653), // Rule ID 21610 //
     /*  752592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  752595 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752617 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN),
     /*  752620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752622 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752651 */     GIR_RootConstrainSelectedInstOperands,
     /*  752652 */     // GIR_Coverage, 21610,
     /*  752652 */     GIR_EraseRootFromParent_Done,
     /*  752653 */   // Label 11981: @752653
     /*  752653 */   GIM_Try, /*On fail goto*//*Label 11982*/ GIMT_Encode4(752719), // Rule ID 21611 //
     /*  752658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  752661 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752672 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752676 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752683 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN),
     /*  752686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752688 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752717 */     GIR_RootConstrainSelectedInstOperands,
     /*  752718 */     // GIR_Coverage, 21611,
     /*  752718 */     GIR_EraseRootFromParent_Done,
     /*  752719 */   // Label 11982: @752719
     /*  752719 */   GIM_Try, /*On fail goto*//*Label 11983*/ GIMT_Encode4(752785), // Rule ID 21612 //
     /*  752724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  752727 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752749 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN),
     /*  752752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752754 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752783 */     GIR_RootConstrainSelectedInstOperands,
     /*  752784 */     // GIR_Coverage, 21612,
     /*  752784 */     GIR_EraseRootFromParent_Done,
     /*  752785 */   // Label 11983: @752785
     /*  752785 */   GIM_Try, /*On fail goto*//*Label 11984*/ GIMT_Encode4(752851), // Rule ID 21628 //
     /*  752790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  752793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752815 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN),
     /*  752818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752820 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752845 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752849 */     GIR_RootConstrainSelectedInstOperands,
     /*  752850 */     // GIR_Coverage, 21628,
     /*  752850 */     GIR_EraseRootFromParent_Done,
     /*  752851 */   // Label 11984: @752851
     /*  752851 */   GIM_Try, /*On fail goto*//*Label 11985*/ GIMT_Encode4(752917), // Rule ID 21629 //
     /*  752856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  752859 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752874 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752881 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN),
     /*  752884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752886 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752915 */     GIR_RootConstrainSelectedInstOperands,
     /*  752916 */     // GIR_Coverage, 21629,
     /*  752916 */     GIR_EraseRootFromParent_Done,
     /*  752917 */   // Label 11985: @752917
     /*  752917 */   GIM_Try, /*On fail goto*//*Label 11986*/ GIMT_Encode4(752983), // Rule ID 21630 //
     /*  752922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  752925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  752936 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  752940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  752947 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  752947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN),
     /*  752950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  752952 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  752954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  752959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  752964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  752969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  752974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  752977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  752981 */     GIR_RootConstrainSelectedInstOperands,
     /*  752982 */     // GIR_Coverage, 21630,
     /*  752982 */     GIR_EraseRootFromParent_Done,
     /*  752983 */   // Label 11986: @752983
     /*  752983 */   GIM_Try, /*On fail goto*//*Label 11987*/ GIMT_Encode4(753049), // Rule ID 21631 //
     /*  752988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  752991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  752998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  753013 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN),
     /*  753016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753018 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  753025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  753035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  753040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753047 */     GIR_RootConstrainSelectedInstOperands,
     /*  753048 */     // GIR_Coverage, 21631,
     /*  753048 */     GIR_EraseRootFromParent_Done,
     /*  753049 */   // Label 11987: @753049
     /*  753049 */   GIM_Try, /*On fail goto*//*Label 11988*/ GIMT_Encode4(753115), // Rule ID 21632 //
     /*  753054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  753057 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  753079 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN),
     /*  753082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753084 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  753091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  753101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  753106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753113 */     GIR_RootConstrainSelectedInstOperands,
     /*  753114 */     // GIR_Coverage, 21632,
     /*  753114 */     GIR_EraseRootFromParent_Done,
     /*  753115 */   // Label 11988: @753115
     /*  753115 */   GIM_Try, /*On fail goto*//*Label 11989*/ GIMT_Encode4(753172), // Rule ID 21613 //
     /*  753120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  753123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753130 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753143 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
     /*  753146 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753170 */     GIR_RootConstrainSelectedInstOperands,
     /*  753171 */     // GIR_Coverage, 21613,
     /*  753171 */     GIR_EraseRootFromParent_Done,
     /*  753172 */   // Label 11989: @753172
     /*  753172 */   GIM_Try, /*On fail goto*//*Label 11990*/ GIMT_Encode4(753229), // Rule ID 21614 //
     /*  753177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  753180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753187 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753189 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753200 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
     /*  753203 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753227 */     GIR_RootConstrainSelectedInstOperands,
     /*  753228 */     // GIR_Coverage, 21614,
     /*  753228 */     GIR_EraseRootFromParent_Done,
     /*  753229 */   // Label 11990: @753229
     /*  753229 */   GIM_Try, /*On fail goto*//*Label 11991*/ GIMT_Encode4(753286), // Rule ID 21615 //
     /*  753234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  753237 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753244 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753257 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
     /*  753260 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753284 */     GIR_RootConstrainSelectedInstOperands,
     /*  753285 */     // GIR_Coverage, 21615,
     /*  753285 */     GIR_EraseRootFromParent_Done,
     /*  753286 */   // Label 11991: @753286
     /*  753286 */   GIM_Try, /*On fail goto*//*Label 11992*/ GIMT_Encode4(753343), // Rule ID 21616 //
     /*  753291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  753294 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753301 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753314 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
     /*  753317 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753337 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753341 */     GIR_RootConstrainSelectedInstOperands,
     /*  753342 */     // GIR_Coverage, 21616,
     /*  753342 */     GIR_EraseRootFromParent_Done,
     /*  753343 */   // Label 11992: @753343
     /*  753343 */   GIM_Try, /*On fail goto*//*Label 11993*/ GIMT_Encode4(753400), // Rule ID 21617 //
     /*  753348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  753351 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753358 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753371 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
     /*  753374 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753398 */     GIR_RootConstrainSelectedInstOperands,
     /*  753399 */     // GIR_Coverage, 21617,
     /*  753399 */     GIR_EraseRootFromParent_Done,
     /*  753400 */   // Label 11993: @753400
     /*  753400 */   GIM_Try, /*On fail goto*//*Label 11994*/ GIMT_Encode4(753457), // Rule ID 21633 //
     /*  753405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  753408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753415 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753417 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753428 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
     /*  753431 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753455 */     GIR_RootConstrainSelectedInstOperands,
     /*  753456 */     // GIR_Coverage, 21633,
     /*  753456 */     GIR_EraseRootFromParent_Done,
     /*  753457 */   // Label 11994: @753457
     /*  753457 */   GIM_Try, /*On fail goto*//*Label 11995*/ GIMT_Encode4(753514), // Rule ID 21634 //
     /*  753462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  753465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753472 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753485 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
     /*  753488 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753512 */     GIR_RootConstrainSelectedInstOperands,
     /*  753513 */     // GIR_Coverage, 21634,
     /*  753513 */     GIR_EraseRootFromParent_Done,
     /*  753514 */   // Label 11995: @753514
     /*  753514 */   GIM_Try, /*On fail goto*//*Label 11996*/ GIMT_Encode4(753571), // Rule ID 21635 //
     /*  753519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  753522 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753529 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753542 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
     /*  753545 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753569 */     GIR_RootConstrainSelectedInstOperands,
     /*  753570 */     // GIR_Coverage, 21635,
     /*  753570 */     GIR_EraseRootFromParent_Done,
     /*  753571 */   // Label 11996: @753571
     /*  753571 */   GIM_Try, /*On fail goto*//*Label 11997*/ GIMT_Encode4(753628), // Rule ID 21636 //
     /*  753576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  753579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753586 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753599 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
     /*  753602 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753626 */     GIR_RootConstrainSelectedInstOperands,
     /*  753627 */     // GIR_Coverage, 21636,
     /*  753627 */     GIR_EraseRootFromParent_Done,
     /*  753628 */   // Label 11997: @753628
     /*  753628 */   GIM_Try, /*On fail goto*//*Label 11998*/ GIMT_Encode4(753685), // Rule ID 21637 //
     /*  753633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  753636 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753643 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  753645 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753656 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
     /*  753659 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  753679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753683 */     GIR_RootConstrainSelectedInstOperands,
     /*  753684 */     // GIR_Coverage, 21637,
     /*  753684 */     GIR_EraseRootFromParent_Done,
     /*  753685 */   // Label 11998: @753685
     /*  753685 */   GIM_Try, /*On fail goto*//*Label 11999*/ GIMT_Encode4(753746), // Rule ID 21603 //
     /*  753690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  753693 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753715 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
     /*  753718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753720 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753737 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753744 */     GIR_RootConstrainSelectedInstOperands,
     /*  753745 */     // GIR_Coverage, 21603,
     /*  753745 */     GIR_EraseRootFromParent_Done,
     /*  753746 */   // Label 11999: @753746
     /*  753746 */   GIM_Try, /*On fail goto*//*Label 12000*/ GIMT_Encode4(753807), // Rule ID 21604 //
     /*  753751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  753754 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753776 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
     /*  753779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753781 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753805 */     GIR_RootConstrainSelectedInstOperands,
     /*  753806 */     // GIR_Coverage, 21604,
     /*  753806 */     GIR_EraseRootFromParent_Done,
     /*  753807 */   // Label 12000: @753807
     /*  753807 */   GIM_Try, /*On fail goto*//*Label 12001*/ GIMT_Encode4(753868), // Rule ID 21605 //
     /*  753812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  753815 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753826 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753837 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
     /*  753840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753842 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753866 */     GIR_RootConstrainSelectedInstOperands,
     /*  753867 */     // GIR_Coverage, 21605,
     /*  753867 */     GIR_EraseRootFromParent_Done,
     /*  753868 */   // Label 12001: @753868
     /*  753868 */   GIM_Try, /*On fail goto*//*Label 12002*/ GIMT_Encode4(753929), // Rule ID 21606 //
     /*  753873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  753876 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753887 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753898 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
     /*  753901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753903 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753927 */     GIR_RootConstrainSelectedInstOperands,
     /*  753928 */     // GIR_Coverage, 21606,
     /*  753928 */     GIR_EraseRootFromParent_Done,
     /*  753929 */   // Label 12002: @753929
     /*  753929 */   GIM_Try, /*On fail goto*//*Label 12003*/ GIMT_Encode4(753990), // Rule ID 21607 //
     /*  753934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  753937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  753944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  753948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  753952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  753959 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  753959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
     /*  753962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  753964 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  753966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  753971 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  753976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  753981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  753984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  753988 */     GIR_RootConstrainSelectedInstOperands,
     /*  753989 */     // GIR_Coverage, 21607,
     /*  753989 */     GIR_EraseRootFromParent_Done,
     /*  753990 */   // Label 12003: @753990
     /*  753990 */   GIM_Try, /*On fail goto*//*Label 12004*/ GIMT_Encode4(754051), // Rule ID 21623 //
     /*  753995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  753998 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  754005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  754009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  754020 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  754020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
     /*  754023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  754025 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  754027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  754032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  754037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  754042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754049 */     GIR_RootConstrainSelectedInstOperands,
     /*  754050 */     // GIR_Coverage, 21623,
     /*  754050 */     GIR_EraseRootFromParent_Done,
     /*  754051 */   // Label 12004: @754051
     /*  754051 */   GIM_Try, /*On fail goto*//*Label 12005*/ GIMT_Encode4(754112), // Rule ID 21624 //
     /*  754056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  754059 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  754066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  754070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  754081 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  754081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
     /*  754084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  754086 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  754088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  754093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  754098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  754103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754110 */     GIR_RootConstrainSelectedInstOperands,
     /*  754111 */     // GIR_Coverage, 21624,
     /*  754111 */     GIR_EraseRootFromParent_Done,
     /*  754112 */   // Label 12005: @754112
     /*  754112 */   GIM_Try, /*On fail goto*//*Label 12006*/ GIMT_Encode4(754173), // Rule ID 21625 //
     /*  754117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  754120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  754127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  754131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  754142 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  754142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
     /*  754145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  754147 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  754149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  754154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  754159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  754164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754171 */     GIR_RootConstrainSelectedInstOperands,
     /*  754172 */     // GIR_Coverage, 21625,
     /*  754172 */     GIR_EraseRootFromParent_Done,
     /*  754173 */   // Label 12006: @754173
     /*  754173 */   GIM_Try, /*On fail goto*//*Label 12007*/ GIMT_Encode4(754234), // Rule ID 21626 //
     /*  754178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  754181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  754188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  754192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  754203 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  754203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
     /*  754206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  754208 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  754210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  754215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  754220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  754225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754228 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754232 */     GIR_RootConstrainSelectedInstOperands,
     /*  754233 */     // GIR_Coverage, 21626,
     /*  754233 */     GIR_EraseRootFromParent_Done,
     /*  754234 */   // Label 12007: @754234
     /*  754234 */   GIM_Try, /*On fail goto*//*Label 12008*/ GIMT_Encode4(754295), // Rule ID 21627 //
     /*  754239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  754242 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  754249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  754253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  754264 */     // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  754264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
     /*  754267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  754269 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  754271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  754276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  754281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  754286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754293 */     GIR_RootConstrainSelectedInstOperands,
     /*  754294 */     // GIR_Coverage, 21627,
     /*  754294 */     GIR_EraseRootFromParent_Done,
     /*  754295 */   // Label 12008: @754295
     /*  754295 */   GIM_Try, /*On fail goto*//*Label 12009*/ GIMT_Encode4(754345), // Rule ID 30625 //
     /*  754300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  754303 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754308 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754321 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754329 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754343 */     GIR_RootConstrainSelectedInstOperands,
     /*  754344 */     // GIR_Coverage, 30625,
     /*  754344 */     GIR_EraseRootFromParent_Done,
     /*  754345 */   // Label 12009: @754345
     /*  754345 */   GIM_Try, /*On fail goto*//*Label 12010*/ GIMT_Encode4(754395), // Rule ID 30626 //
     /*  754350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  754353 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754358 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754371 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754379 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754389 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754393 */     GIR_RootConstrainSelectedInstOperands,
     /*  754394 */     // GIR_Coverage, 30626,
     /*  754394 */     GIR_EraseRootFromParent_Done,
     /*  754395 */   // Label 12010: @754395
     /*  754395 */   GIM_Try, /*On fail goto*//*Label 12011*/ GIMT_Encode4(754445), // Rule ID 30627 //
     /*  754400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  754403 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754408 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754414 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754421 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754429 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754443 */     GIR_RootConstrainSelectedInstOperands,
     /*  754444 */     // GIR_Coverage, 30627,
     /*  754444 */     GIR_EraseRootFromParent_Done,
     /*  754445 */   // Label 12011: @754445
     /*  754445 */   GIM_Try, /*On fail goto*//*Label 12012*/ GIMT_Encode4(754495), // Rule ID 30628 //
     /*  754450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  754453 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754458 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754460 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754471 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754479 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754489 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754493 */     GIR_RootConstrainSelectedInstOperands,
     /*  754494 */     // GIR_Coverage, 30628,
     /*  754494 */     GIR_EraseRootFromParent_Done,
     /*  754495 */   // Label 12012: @754495
     /*  754495 */   GIM_Try, /*On fail goto*//*Label 12013*/ GIMT_Encode4(754545), // Rule ID 30629 //
     /*  754500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  754503 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754508 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754510 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754521 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754529 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754539 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754543 */     GIR_RootConstrainSelectedInstOperands,
     /*  754544 */     // GIR_Coverage, 30629,
     /*  754544 */     GIR_EraseRootFromParent_Done,
     /*  754545 */   // Label 12013: @754545
     /*  754545 */   GIM_Try, /*On fail goto*//*Label 12014*/ GIMT_Encode4(754595), // Rule ID 30635 //
     /*  754550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  754553 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754558 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754571 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i64>>  =>  (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9),
     /*  754574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754579 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754593 */     GIR_RootConstrainSelectedInstOperands,
     /*  754594 */     // GIR_Coverage, 30635,
     /*  754594 */     GIR_EraseRootFromParent_Done,
     /*  754595 */   // Label 12014: @754595
     /*  754595 */   GIM_Try, /*On fail goto*//*Label 12015*/ GIMT_Encode4(754645), // Rule ID 30636 //
     /*  754600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  754603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754608 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754621 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i64>>  =>  (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9),
     /*  754624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754629 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754639 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754643 */     GIR_RootConstrainSelectedInstOperands,
     /*  754644 */     // GIR_Coverage, 30636,
     /*  754644 */     GIR_EraseRootFromParent_Done,
     /*  754645 */   // Label 12015: @754645
     /*  754645 */   GIM_Try, /*On fail goto*//*Label 12016*/ GIMT_Encode4(754695), // Rule ID 30637 //
     /*  754650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  754653 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754658 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754671 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i64>>  =>  (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9),
     /*  754674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754679 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754693 */     GIR_RootConstrainSelectedInstOperands,
     /*  754694 */     // GIR_Coverage, 30637,
     /*  754694 */     GIR_EraseRootFromParent_Done,
     /*  754695 */   // Label 12016: @754695
     /*  754695 */   GIM_Try, /*On fail goto*//*Label 12017*/ GIMT_Encode4(754745), // Rule ID 30638 //
     /*  754700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  754703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754708 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754721 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i64>>  =>  (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9),
     /*  754724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754729 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754743 */     GIR_RootConstrainSelectedInstOperands,
     /*  754744 */     // GIR_Coverage, 30638,
     /*  754744 */     GIR_EraseRootFromParent_Done,
     /*  754745 */   // Label 12017: @754745
     /*  754745 */   GIM_Try, /*On fail goto*//*Label 12018*/ GIMT_Encode4(754795), // Rule ID 30639 //
     /*  754750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  754753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  754758 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754771 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i64>>  =>  (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  754771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9),
     /*  754774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754779 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  754789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754793 */     GIR_RootConstrainSelectedInstOperands,
     /*  754794 */     // GIR_Coverage, 30639,
     /*  754794 */     GIR_EraseRootFromParent_Done,
     /*  754795 */   // Label 12018: @754795
     /*  754795 */   GIM_Try, /*On fail goto*//*Label 12019*/ GIMT_Encode4(754845), // Rule ID 30645 //
     /*  754800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  754803 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  754808 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754821 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  754821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754829 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754843 */     GIR_RootConstrainSelectedInstOperands,
     /*  754844 */     // GIR_Coverage, 30645,
     /*  754844 */     GIR_EraseRootFromParent_Done,
     /*  754845 */   // Label 12019: @754845
     /*  754845 */   GIM_Try, /*On fail goto*//*Label 12020*/ GIMT_Encode4(754895), // Rule ID 30646 //
     /*  754850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  754853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  754858 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754860 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754871 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  754871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754879 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754889 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754893 */     GIR_RootConstrainSelectedInstOperands,
     /*  754894 */     // GIR_Coverage, 30646,
     /*  754894 */     GIR_EraseRootFromParent_Done,
     /*  754895 */   // Label 12020: @754895
     /*  754895 */   GIM_Try, /*On fail goto*//*Label 12021*/ GIMT_Encode4(754945), // Rule ID 30647 //
     /*  754900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  754903 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  754908 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754921 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  754921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754929 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754939 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754943 */     GIR_RootConstrainSelectedInstOperands,
     /*  754944 */     // GIR_Coverage, 30647,
     /*  754944 */     GIR_EraseRootFromParent_Done,
     /*  754945 */   // Label 12021: @754945
     /*  754945 */   GIM_Try, /*On fail goto*//*Label 12022*/ GIMT_Encode4(754995), // Rule ID 30648 //
     /*  754950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  754953 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  754958 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  754960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  754964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  754971 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  754971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  754974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  754979 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  754981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  754986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  754989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  754993 */     GIR_RootConstrainSelectedInstOperands,
     /*  754994 */     // GIR_Coverage, 30648,
     /*  754994 */     GIR_EraseRootFromParent_Done,
     /*  754995 */   // Label 12022: @754995
     /*  754995 */   GIM_Try, /*On fail goto*//*Label 12023*/ GIMT_Encode4(755045), // Rule ID 30649 //
     /*  755000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  755003 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  755008 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  755010 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755014 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755021 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  755021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
     /*  755024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755029 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  755039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755043 */     GIR_RootConstrainSelectedInstOperands,
     /*  755044 */     // GIR_Coverage, 30649,
     /*  755044 */     GIR_EraseRootFromParent_Done,
     /*  755045 */   // Label 12023: @755045
     /*  755045 */   GIM_Try, /*On fail goto*//*Label 12024*/ GIMT_Encode4(755099), // Rule ID 30620 //
     /*  755050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  755053 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755073 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755083 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755093 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755097 */     GIR_RootConstrainSelectedInstOperands,
     /*  755098 */     // GIR_Coverage, 30620,
     /*  755098 */     GIR_EraseRootFromParent_Done,
     /*  755099 */   // Label 12024: @755099
     /*  755099 */   GIM_Try, /*On fail goto*//*Label 12025*/ GIMT_Encode4(755153), // Rule ID 30621 //
     /*  755104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  755107 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755116 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755120 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755127 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755137 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755151 */     GIR_RootConstrainSelectedInstOperands,
     /*  755152 */     // GIR_Coverage, 30621,
     /*  755152 */     GIR_EraseRootFromParent_Done,
     /*  755153 */   // Label 12025: @755153
     /*  755153 */   GIM_Try, /*On fail goto*//*Label 12026*/ GIMT_Encode4(755207), // Rule ID 30622 //
     /*  755158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  755161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755181 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755191 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755205 */     GIR_RootConstrainSelectedInstOperands,
     /*  755206 */     // GIR_Coverage, 30622,
     /*  755206 */     GIR_EraseRootFromParent_Done,
     /*  755207 */   // Label 12026: @755207
     /*  755207 */   GIM_Try, /*On fail goto*//*Label 12027*/ GIMT_Encode4(755261), // Rule ID 30623 //
     /*  755212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  755215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755235 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755245 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755259 */     GIR_RootConstrainSelectedInstOperands,
     /*  755260 */     // GIR_Coverage, 30623,
     /*  755260 */     GIR_EraseRootFromParent_Done,
     /*  755261 */   // Label 12027: @755261
     /*  755261 */   GIM_Try, /*On fail goto*//*Label 12028*/ GIMT_Encode4(755315), // Rule ID 30624 //
     /*  755266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  755269 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755278 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755289 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755299 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755313 */     GIR_RootConstrainSelectedInstOperands,
     /*  755314 */     // GIR_Coverage, 30624,
     /*  755314 */     GIR_EraseRootFromParent_Done,
     /*  755315 */   // Label 12028: @755315
     /*  755315 */   GIM_Try, /*On fail goto*//*Label 12029*/ GIMT_Encode4(755369), // Rule ID 30630 //
     /*  755320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  755323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755332 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755343 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i64>>  =>  (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9),
     /*  755346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755353 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755367 */     GIR_RootConstrainSelectedInstOperands,
     /*  755368 */     // GIR_Coverage, 30630,
     /*  755368 */     GIR_EraseRootFromParent_Done,
     /*  755369 */   // Label 12029: @755369
     /*  755369 */   GIM_Try, /*On fail goto*//*Label 12030*/ GIMT_Encode4(755423), // Rule ID 30631 //
     /*  755374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  755377 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755397 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i64>>  =>  (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9),
     /*  755400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755407 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755414 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755417 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755421 */     GIR_RootConstrainSelectedInstOperands,
     /*  755422 */     // GIR_Coverage, 30631,
     /*  755422 */     GIR_EraseRootFromParent_Done,
     /*  755423 */   // Label 12030: @755423
     /*  755423 */   GIM_Try, /*On fail goto*//*Label 12031*/ GIMT_Encode4(755477), // Rule ID 30632 //
     /*  755428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  755431 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755451 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i64>>  =>  (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9),
     /*  755454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755461 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755471 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755475 */     GIR_RootConstrainSelectedInstOperands,
     /*  755476 */     // GIR_Coverage, 30632,
     /*  755476 */     GIR_EraseRootFromParent_Done,
     /*  755477 */   // Label 12031: @755477
     /*  755477 */   GIM_Try, /*On fail goto*//*Label 12032*/ GIMT_Encode4(755531), // Rule ID 30633 //
     /*  755482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  755485 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755494 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755498 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755505 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i64>>  =>  (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9),
     /*  755508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755515 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755529 */     GIR_RootConstrainSelectedInstOperands,
     /*  755530 */     // GIR_Coverage, 30633,
     /*  755530 */     GIR_EraseRootFromParent_Done,
     /*  755531 */   // Label 12032: @755531
     /*  755531 */   GIM_Try, /*On fail goto*//*Label 12033*/ GIMT_Encode4(755585), // Rule ID 30634 //
     /*  755536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  755539 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  755544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755559 */     // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i64>>  =>  (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  755559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9),
     /*  755562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755569 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  755579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755583 */     GIR_RootConstrainSelectedInstOperands,
     /*  755584 */     // GIR_Coverage, 30634,
     /*  755584 */     GIR_EraseRootFromParent_Done,
     /*  755585 */   // Label 12033: @755585
     /*  755585 */   GIM_Try, /*On fail goto*//*Label 12034*/ GIMT_Encode4(755639), // Rule ID 30640 //
     /*  755590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  755593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  755598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755613 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  755613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755623 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  755633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755637 */     GIR_RootConstrainSelectedInstOperands,
     /*  755638 */     // GIR_Coverage, 30640,
     /*  755638 */     GIR_EraseRootFromParent_Done,
     /*  755639 */   // Label 12034: @755639
     /*  755639 */   GIM_Try, /*On fail goto*//*Label 12035*/ GIMT_Encode4(755693), // Rule ID 30641 //
     /*  755644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  755647 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  755652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755667 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  755667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755677 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  755687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755691 */     GIR_RootConstrainSelectedInstOperands,
     /*  755692 */     // GIR_Coverage, 30641,
     /*  755692 */     GIR_EraseRootFromParent_Done,
     /*  755693 */   // Label 12035: @755693
     /*  755693 */   GIM_Try, /*On fail goto*//*Label 12036*/ GIMT_Encode4(755747), // Rule ID 30642 //
     /*  755698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  755701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  755706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755721 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  755721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755731 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  755741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755745 */     GIR_RootConstrainSelectedInstOperands,
     /*  755746 */     // GIR_Coverage, 30642,
     /*  755746 */     GIR_EraseRootFromParent_Done,
     /*  755747 */   // Label 12036: @755747
     /*  755747 */   GIM_Try, /*On fail goto*//*Label 12037*/ GIMT_Encode4(755801), // Rule ID 30643 //
     /*  755752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  755755 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  755760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755764 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755768 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755775 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  755775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755785 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  755795 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755799 */     GIR_RootConstrainSelectedInstOperands,
     /*  755800 */     // GIR_Coverage, 30643,
     /*  755800 */     GIR_EraseRootFromParent_Done,
     /*  755801 */   // Label 12037: @755801
     /*  755801 */   GIM_Try, /*On fail goto*//*Label 12038*/ GIMT_Encode4(755855), // Rule ID 30644 //
     /*  755806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  755809 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  755814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  755818 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  755829 */     // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  755829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
     /*  755832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  755834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  755839 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  755841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  755846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  755849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755853 */     GIR_RootConstrainSelectedInstOperands,
     /*  755854 */     // GIR_Coverage, 30644,
     /*  755854 */     GIR_EraseRootFromParent_Done,
     /*  755855 */   // Label 12038: @755855
     /*  755855 */   GIM_Try, /*On fail goto*//*Label 12039*/ GIMT_Encode4(755914), // Rule ID 13145 //
     /*  755860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  755863 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  755870 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  755872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  755883 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  755883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR),
     /*  755886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  755891 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  755893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  755898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  755903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  755908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755912 */     GIR_RootConstrainSelectedInstOperands,
     /*  755913 */     // GIR_Coverage, 13145,
     /*  755913 */     GIR_EraseRootFromParent_Done,
     /*  755914 */   // Label 12039: @755914
     /*  755914 */   GIM_Try, /*On fail goto*//*Label 12040*/ GIMT_Encode4(755973), // Rule ID 13146 //
     /*  755919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  755922 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  755929 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  755931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  755942 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  755942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR),
     /*  755945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  755950 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  755952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  755957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  755962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  755967 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  755971 */     GIR_RootConstrainSelectedInstOperands,
     /*  755972 */     // GIR_Coverage, 13146,
     /*  755972 */     GIR_EraseRootFromParent_Done,
     /*  755973 */   // Label 12040: @755973
     /*  755973 */   GIM_Try, /*On fail goto*//*Label 12041*/ GIMT_Encode4(756032), // Rule ID 13147 //
     /*  755978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  755981 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  755988 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  755990 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  755994 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  756001 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR),
     /*  756004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756009 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756030 */     GIR_RootConstrainSelectedInstOperands,
     /*  756031 */     // GIR_Coverage, 13147,
     /*  756031 */     GIR_EraseRootFromParent_Done,
     /*  756032 */   // Label 12041: @756032
     /*  756032 */   GIM_Try, /*On fail goto*//*Label 12042*/ GIMT_Encode4(756091), // Rule ID 13148 //
     /*  756037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  756040 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756047 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756049 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  756060 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR),
     /*  756063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756068 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756089 */     GIR_RootConstrainSelectedInstOperands,
     /*  756090 */     // GIR_Coverage, 13148,
     /*  756090 */     GIR_EraseRootFromParent_Done,
     /*  756091 */   // Label 12042: @756091
     /*  756091 */   GIM_Try, /*On fail goto*//*Label 12043*/ GIMT_Encode4(756150), // Rule ID 13149 //
     /*  756096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  756099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756106 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  756119 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR),
     /*  756122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756127 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756148 */     GIR_RootConstrainSelectedInstOperands,
     /*  756149 */     // GIR_Coverage, 13149,
     /*  756149 */     GIR_EraseRootFromParent_Done,
     /*  756150 */   // Label 12043: @756150
     /*  756150 */   GIM_Try, /*On fail goto*//*Label 12044*/ GIMT_Encode4(756213), // Rule ID 13155 //
     /*  756155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  756158 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  756180 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN),
     /*  756183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756190 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756211 */     GIR_RootConstrainSelectedInstOperands,
     /*  756212 */     // GIR_Coverage, 13155,
     /*  756212 */     GIR_EraseRootFromParent_Done,
     /*  756213 */   // Label 12044: @756213
     /*  756213 */   GIM_Try, /*On fail goto*//*Label 12045*/ GIMT_Encode4(756276), // Rule ID 13156 //
     /*  756218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  756221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  756243 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN),
     /*  756246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756253 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756274 */     GIR_RootConstrainSelectedInstOperands,
     /*  756275 */     // GIR_Coverage, 13156,
     /*  756275 */     GIR_EraseRootFromParent_Done,
     /*  756276 */   // Label 12045: @756276
     /*  756276 */   GIM_Try, /*On fail goto*//*Label 12046*/ GIMT_Encode4(756339), // Rule ID 13157 //
     /*  756281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  756284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756295 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  756306 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN),
     /*  756309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756316 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756337 */     GIR_RootConstrainSelectedInstOperands,
     /*  756338 */     // GIR_Coverage, 13157,
     /*  756338 */     GIR_EraseRootFromParent_Done,
     /*  756339 */   // Label 12046: @756339
     /*  756339 */   GIM_Try, /*On fail goto*//*Label 12047*/ GIMT_Encode4(756402), // Rule ID 13158 //
     /*  756344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  756347 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  756369 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN),
     /*  756372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756379 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756400 */     GIR_RootConstrainSelectedInstOperands,
     /*  756401 */     // GIR_Coverage, 13158,
     /*  756401 */     GIR_EraseRootFromParent_Done,
     /*  756402 */   // Label 12047: @756402
     /*  756402 */   GIM_Try, /*On fail goto*//*Label 12048*/ GIMT_Encode4(756465), // Rule ID 13159 //
     /*  756407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  756410 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  756432 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  756432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN),
     /*  756435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  756442 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  756449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  756454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  756459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756463 */     GIR_RootConstrainSelectedInstOperands,
     /*  756464 */     // GIR_Coverage, 13159,
     /*  756464 */     GIR_EraseRootFromParent_Done,
     /*  756465 */   // Label 12048: @756465
     /*  756465 */   GIM_Try, /*On fail goto*//*Label 12049*/ GIMT_Encode4(756517), // Rule ID 13140 //
     /*  756470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  756473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756480 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756493 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2),
     /*  756496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756501 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  756511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756515 */     GIR_RootConstrainSelectedInstOperands,
     /*  756516 */     // GIR_Coverage, 13140,
     /*  756516 */     GIR_EraseRootFromParent_Done,
     /*  756517 */   // Label 12049: @756517
     /*  756517 */   GIM_Try, /*On fail goto*//*Label 12050*/ GIMT_Encode4(756569), // Rule ID 13141 //
     /*  756522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  756525 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756532 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756534 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756545 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2),
     /*  756548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756553 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  756563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756567 */     GIR_RootConstrainSelectedInstOperands,
     /*  756568 */     // GIR_Coverage, 13141,
     /*  756568 */     GIR_EraseRootFromParent_Done,
     /*  756569 */   // Label 12050: @756569
     /*  756569 */   GIM_Try, /*On fail goto*//*Label 12051*/ GIMT_Encode4(756621), // Rule ID 13142 //
     /*  756574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  756577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756584 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756586 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756590 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756597 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2),
     /*  756600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756605 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  756615 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756619 */     GIR_RootConstrainSelectedInstOperands,
     /*  756620 */     // GIR_Coverage, 13142,
     /*  756620 */     GIR_EraseRootFromParent_Done,
     /*  756621 */   // Label 12051: @756621
     /*  756621 */   GIM_Try, /*On fail goto*//*Label 12052*/ GIMT_Encode4(756673), // Rule ID 13143 //
     /*  756626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  756629 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756636 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756638 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756642 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756649 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2),
     /*  756652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756657 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  756667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756671 */     GIR_RootConstrainSelectedInstOperands,
     /*  756672 */     // GIR_Coverage, 13143,
     /*  756672 */     GIR_EraseRootFromParent_Done,
     /*  756673 */   // Label 12052: @756673
     /*  756673 */   GIM_Try, /*On fail goto*//*Label 12053*/ GIMT_Encode4(756725), // Rule ID 13144 //
     /*  756678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  756681 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756688 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  756690 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756701 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2),
     /*  756704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756709 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  756719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756723 */     GIR_RootConstrainSelectedInstOperands,
     /*  756724 */     // GIR_Coverage, 13144,
     /*  756724 */     GIR_EraseRootFromParent_Done,
     /*  756725 */   // Label 12053: @756725
     /*  756725 */   GIM_Try, /*On fail goto*//*Label 12054*/ GIMT_Encode4(756781), // Rule ID 13150 //
     /*  756730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  756733 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756755 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN),
     /*  756758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756765 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  756775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756779 */     GIR_RootConstrainSelectedInstOperands,
     /*  756780 */     // GIR_Coverage, 13150,
     /*  756780 */     GIR_EraseRootFromParent_Done,
     /*  756781 */   // Label 12054: @756781
     /*  756781 */   GIM_Try, /*On fail goto*//*Label 12055*/ GIMT_Encode4(756837), // Rule ID 13151 //
     /*  756786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  756789 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756800 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756804 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756811 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN),
     /*  756814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756821 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  756831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756835 */     GIR_RootConstrainSelectedInstOperands,
     /*  756836 */     // GIR_Coverage, 13151,
     /*  756836 */     GIR_EraseRootFromParent_Done,
     /*  756837 */   // Label 12055: @756837
     /*  756837 */   GIM_Try, /*On fail goto*//*Label 12056*/ GIMT_Encode4(756893), // Rule ID 13152 //
     /*  756842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  756845 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756867 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN),
     /*  756870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756877 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  756887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756891 */     GIR_RootConstrainSelectedInstOperands,
     /*  756892 */     // GIR_Coverage, 13152,
     /*  756892 */     GIR_EraseRootFromParent_Done,
     /*  756893 */   // Label 12056: @756893
     /*  756893 */   GIM_Try, /*On fail goto*//*Label 12057*/ GIMT_Encode4(756949), // Rule ID 13153 //
     /*  756898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  756901 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756912 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756923 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN),
     /*  756926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756933 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  756943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  756947 */     GIR_RootConstrainSelectedInstOperands,
     /*  756948 */     // GIR_Coverage, 13153,
     /*  756948 */     GIR_EraseRootFromParent_Done,
     /*  756949 */   // Label 12057: @756949
     /*  756949 */   GIM_Try, /*On fail goto*//*Label 12058*/ GIMT_Encode4(757005), // Rule ID 13154 //
     /*  756954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  756957 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  756964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  756968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  756972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  756979 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  756979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN),
     /*  756982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  756984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  756989 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  756991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  756996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  756999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757003 */     GIR_RootConstrainSelectedInstOperands,
     /*  757004 */     // GIR_Coverage, 13154,
     /*  757004 */     GIR_EraseRootFromParent_Done,
     /*  757005 */   // Label 12058: @757005
     /*  757005 */   GIM_Try, /*On fail goto*//*Label 12059*/ GIMT_Encode4(757065), // Rule ID 10737 //
     /*  757010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  757013 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757021 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757027 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757034 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757042 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757063 */     GIR_RootConstrainSelectedInstOperands,
     /*  757064 */     // GIR_Coverage, 10737,
     /*  757064 */     GIR_EraseRootFromParent_Done,
     /*  757065 */   // Label 12059: @757065
     /*  757065 */   GIM_Try, /*On fail goto*//*Label 12060*/ GIMT_Encode4(757125), // Rule ID 10738 //
     /*  757070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  757073 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757081 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757083 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757087 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757094 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757102 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757123 */     GIR_RootConstrainSelectedInstOperands,
     /*  757124 */     // GIR_Coverage, 10738,
     /*  757124 */     GIR_EraseRootFromParent_Done,
     /*  757125 */   // Label 12060: @757125
     /*  757125 */   GIM_Try, /*On fail goto*//*Label 12061*/ GIMT_Encode4(757185), // Rule ID 10739 //
     /*  757130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  757133 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757141 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757154 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757162 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757183 */     GIR_RootConstrainSelectedInstOperands,
     /*  757184 */     // GIR_Coverage, 10739,
     /*  757184 */     GIR_EraseRootFromParent_Done,
     /*  757185 */   // Label 12061: @757185
     /*  757185 */   GIM_Try, /*On fail goto*//*Label 12062*/ GIMT_Encode4(757245), // Rule ID 10740 //
     /*  757190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  757193 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757201 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757203 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757214 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757222 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757243 */     GIR_RootConstrainSelectedInstOperands,
     /*  757244 */     // GIR_Coverage, 10740,
     /*  757244 */     GIR_EraseRootFromParent_Done,
     /*  757245 */   // Label 12062: @757245
     /*  757245 */   GIM_Try, /*On fail goto*//*Label 12063*/ GIMT_Encode4(757305), // Rule ID 10741 //
     /*  757250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  757253 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757261 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757274 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757282 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757303 */     GIR_RootConstrainSelectedInstOperands,
     /*  757304 */     // GIR_Coverage, 10741,
     /*  757304 */     GIR_EraseRootFromParent_Done,
     /*  757305 */   // Label 12063: @757305
     /*  757305 */   GIM_Try, /*On fail goto*//*Label 12064*/ GIMT_Encode4(757364), // Rule ID 11293 //
     /*  757310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  757313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757320 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757333 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757341 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757362 */     GIR_RootConstrainSelectedInstOperands,
     /*  757363 */     // GIR_Coverage, 11293,
     /*  757363 */     GIR_EraseRootFromParent_Done,
     /*  757364 */   // Label 12064: @757364
     /*  757364 */   GIM_Try, /*On fail goto*//*Label 12065*/ GIMT_Encode4(757423), // Rule ID 11294 //
     /*  757369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  757372 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757379 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757392 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757400 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757417 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757421 */     GIR_RootConstrainSelectedInstOperands,
     /*  757422 */     // GIR_Coverage, 11294,
     /*  757422 */     GIR_EraseRootFromParent_Done,
     /*  757423 */   // Label 12065: @757423
     /*  757423 */   GIM_Try, /*On fail goto*//*Label 12066*/ GIMT_Encode4(757482), // Rule ID 11295 //
     /*  757428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  757431 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757438 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757451 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757459 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757476 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757480 */     GIR_RootConstrainSelectedInstOperands,
     /*  757481 */     // GIR_Coverage, 11295,
     /*  757481 */     GIR_EraseRootFromParent_Done,
     /*  757482 */   // Label 12066: @757482
     /*  757482 */   GIM_Try, /*On fail goto*//*Label 12067*/ GIMT_Encode4(757541), // Rule ID 11296 //
     /*  757487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  757490 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757497 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757503 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757510 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757518 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757539 */     GIR_RootConstrainSelectedInstOperands,
     /*  757540 */     // GIR_Coverage, 11296,
     /*  757540 */     GIR_EraseRootFromParent_Done,
     /*  757541 */   // Label 12067: @757541
     /*  757541 */   GIM_Try, /*On fail goto*//*Label 12068*/ GIMT_Encode4(757600), // Rule ID 11297 //
     /*  757546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  757549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757556 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  757558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  757569 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR),
     /*  757572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757577 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757598 */     GIR_RootConstrainSelectedInstOperands,
     /*  757599 */     // GIR_Coverage, 11297,
     /*  757599 */     GIR_EraseRootFromParent_Done,
     /*  757600 */   // Label 12068: @757600
     /*  757600 */   GIM_Try, /*On fail goto*//*Label 12069*/ GIMT_Encode4(757664), // Rule ID 10727 //
     /*  757605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  757608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  757620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  757631 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  757634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  757636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757641 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757662 */     GIR_RootConstrainSelectedInstOperands,
     /*  757663 */     // GIR_Coverage, 10727,
     /*  757663 */     GIR_EraseRootFromParent_Done,
     /*  757664 */   // Label 12069: @757664
     /*  757664 */   GIM_Try, /*On fail goto*//*Label 12070*/ GIMT_Encode4(757728), // Rule ID 10728 //
     /*  757669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  757672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  757684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  757695 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  757698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  757700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757705 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757722 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757726 */     GIR_RootConstrainSelectedInstOperands,
     /*  757727 */     // GIR_Coverage, 10728,
     /*  757727 */     GIR_EraseRootFromParent_Done,
     /*  757728 */   // Label 12070: @757728
     /*  757728 */   GIM_Try, /*On fail goto*//*Label 12071*/ GIMT_Encode4(757792), // Rule ID 10729 //
     /*  757733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  757736 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  757748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  757759 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  757762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  757764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757769 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757790 */     GIR_RootConstrainSelectedInstOperands,
     /*  757791 */     // GIR_Coverage, 10729,
     /*  757791 */     GIR_EraseRootFromParent_Done,
     /*  757792 */   // Label 12071: @757792
     /*  757792 */   GIM_Try, /*On fail goto*//*Label 12072*/ GIMT_Encode4(757856), // Rule ID 10730 //
     /*  757797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  757800 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  757812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757816 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  757823 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  757826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  757828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757833 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757854 */     GIR_RootConstrainSelectedInstOperands,
     /*  757855 */     // GIR_Coverage, 10730,
     /*  757855 */     GIR_EraseRootFromParent_Done,
     /*  757856 */   // Label 12072: @757856
     /*  757856 */   GIM_Try, /*On fail goto*//*Label 12073*/ GIMT_Encode4(757920), // Rule ID 10731 //
     /*  757861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  757864 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  757876 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  757887 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  757890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  757892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757897 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757918 */     GIR_RootConstrainSelectedInstOperands,
     /*  757919 */     // GIR_Coverage, 10731,
     /*  757919 */     GIR_EraseRootFromParent_Done,
     /*  757920 */   // Label 12073: @757920
     /*  757920 */   GIM_Try, /*On fail goto*//*Label 12074*/ GIMT_Encode4(757983), // Rule ID 11283 //
     /*  757925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  757928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  757939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  757943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  757950 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  757950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  757953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  757955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  757960 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  757962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  757967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  757972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  757977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  757981 */     GIR_RootConstrainSelectedInstOperands,
     /*  757982 */     // GIR_Coverage, 11283,
     /*  757982 */     GIR_EraseRootFromParent_Done,
     /*  757983 */   // Label 12074: @757983
     /*  757983 */   GIM_Try, /*On fail goto*//*Label 12075*/ GIMT_Encode4(758046), // Rule ID 11284 //
     /*  757988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  757991 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  757998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758002 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  758013 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  758013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  758016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  758023 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  758030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  758035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  758040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758044 */     GIR_RootConstrainSelectedInstOperands,
     /*  758045 */     // GIR_Coverage, 11284,
     /*  758045 */     GIR_EraseRootFromParent_Done,
     /*  758046 */   // Label 12075: @758046
     /*  758046 */   GIM_Try, /*On fail goto*//*Label 12076*/ GIMT_Encode4(758109), // Rule ID 11285 //
     /*  758051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  758054 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  758076 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  758076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  758079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  758086 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  758093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  758098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  758103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758107 */     GIR_RootConstrainSelectedInstOperands,
     /*  758108 */     // GIR_Coverage, 11285,
     /*  758108 */     GIR_EraseRootFromParent_Done,
     /*  758109 */   // Label 12076: @758109
     /*  758109 */   GIM_Try, /*On fail goto*//*Label 12077*/ GIMT_Encode4(758172), // Rule ID 11286 //
     /*  758114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  758117 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  758139 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  758139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  758142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  758149 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  758156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  758161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  758166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758170 */     GIR_RootConstrainSelectedInstOperands,
     /*  758171 */     // GIR_Coverage, 11286,
     /*  758171 */     GIR_EraseRootFromParent_Done,
     /*  758172 */   // Label 12077: @758172
     /*  758172 */   GIM_Try, /*On fail goto*//*Label 12078*/ GIMT_Encode4(758235), // Rule ID 11287 //
     /*  758177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  758180 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758191 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  758202 */     // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  758202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_SADDR_RTN),
     /*  758205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758207 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  758212 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  758219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  758224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  758229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758233 */     GIR_RootConstrainSelectedInstOperands,
     /*  758234 */     // GIR_Coverage, 11287,
     /*  758234 */     GIR_EraseRootFromParent_Done,
     /*  758235 */   // Label 12078: @758235
     /*  758235 */   GIM_Try, /*On fail goto*//*Label 12079*/ GIMT_Encode4(758288), // Rule ID 10732 //
     /*  758240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  758243 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758251 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758257 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758264 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758272 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758286 */     GIR_RootConstrainSelectedInstOperands,
     /*  758287 */     // GIR_Coverage, 10732,
     /*  758287 */     GIR_EraseRootFromParent_Done,
     /*  758288 */   // Label 12079: @758288
     /*  758288 */   GIM_Try, /*On fail goto*//*Label 12080*/ GIMT_Encode4(758341), // Rule ID 10733 //
     /*  758293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  758296 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758304 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758306 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758310 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758317 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758325 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758335 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758339 */     GIR_RootConstrainSelectedInstOperands,
     /*  758340 */     // GIR_Coverage, 10733,
     /*  758340 */     GIR_EraseRootFromParent_Done,
     /*  758341 */   // Label 12080: @758341
     /*  758341 */   GIM_Try, /*On fail goto*//*Label 12081*/ GIMT_Encode4(758394), // Rule ID 10734 //
     /*  758346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  758349 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758357 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758363 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758370 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758378 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758388 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758392 */     GIR_RootConstrainSelectedInstOperands,
     /*  758393 */     // GIR_Coverage, 10734,
     /*  758393 */     GIR_EraseRootFromParent_Done,
     /*  758394 */   // Label 12081: @758394
     /*  758394 */   GIM_Try, /*On fail goto*//*Label 12082*/ GIMT_Encode4(758447), // Rule ID 10735 //
     /*  758399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  758402 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758410 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758423 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758431 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758445 */     GIR_RootConstrainSelectedInstOperands,
     /*  758446 */     // GIR_Coverage, 10735,
     /*  758446 */     GIR_EraseRootFromParent_Done,
     /*  758447 */   // Label 12082: @758447
     /*  758447 */   GIM_Try, /*On fail goto*//*Label 12083*/ GIMT_Encode4(758500), // Rule ID 10736 //
     /*  758452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  758455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758463 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758465 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758476 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758484 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758498 */     GIR_RootConstrainSelectedInstOperands,
     /*  758499 */     // GIR_Coverage, 10736,
     /*  758499 */     GIR_EraseRootFromParent_Done,
     /*  758500 */   // Label 12083: @758500
     /*  758500 */   GIM_Try, /*On fail goto*//*Label 12084*/ GIMT_Encode4(758552), // Rule ID 11288 //
     /*  758505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  758508 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758515 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758517 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758528 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758536 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758550 */     GIR_RootConstrainSelectedInstOperands,
     /*  758551 */     // GIR_Coverage, 11288,
     /*  758551 */     GIR_EraseRootFromParent_Done,
     /*  758552 */   // Label 12084: @758552
     /*  758552 */   GIM_Try, /*On fail goto*//*Label 12085*/ GIMT_Encode4(758604), // Rule ID 11289 //
     /*  758557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  758560 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758567 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758573 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758580 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758588 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758602 */     GIR_RootConstrainSelectedInstOperands,
     /*  758603 */     // GIR_Coverage, 11289,
     /*  758603 */     GIR_EraseRootFromParent_Done,
     /*  758604 */   // Label 12085: @758604
     /*  758604 */   GIM_Try, /*On fail goto*//*Label 12086*/ GIMT_Encode4(758656), // Rule ID 11290 //
     /*  758609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  758612 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758619 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758632 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758640 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758650 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758654 */     GIR_RootConstrainSelectedInstOperands,
     /*  758655 */     // GIR_Coverage, 11290,
     /*  758655 */     GIR_EraseRootFromParent_Done,
     /*  758656 */   // Label 12086: @758656
     /*  758656 */   GIM_Try, /*On fail goto*//*Label 12087*/ GIMT_Encode4(758708), // Rule ID 11291 //
     /*  758661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  758664 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758671 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758684 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758692 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758702 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758706 */     GIR_RootConstrainSelectedInstOperands,
     /*  758707 */     // GIR_Coverage, 11291,
     /*  758707 */     GIR_EraseRootFromParent_Done,
     /*  758708 */   // Label 12087: @758708
     /*  758708 */   GIM_Try, /*On fail goto*//*Label 12088*/ GIMT_Encode4(758760), // Rule ID 11292 //
     /*  758713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  758716 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758723 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  758725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758736 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
     /*  758739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758744 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  758754 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758758 */     GIR_RootConstrainSelectedInstOperands,
     /*  758759 */     // GIR_Coverage, 11292,
     /*  758759 */     GIR_EraseRootFromParent_Done,
     /*  758760 */   // Label 12088: @758760
     /*  758760 */   GIM_Try, /*On fail goto*//*Label 12089*/ GIMT_Encode4(758817), // Rule ID 10722 //
     /*  758765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  758768 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758784 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758791 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  758794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758801 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  758811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758815 */     GIR_RootConstrainSelectedInstOperands,
     /*  758816 */     // GIR_Coverage, 10722,
     /*  758816 */     GIR_EraseRootFromParent_Done,
     /*  758817 */   // Label 12089: @758817
     /*  758817 */   GIM_Try, /*On fail goto*//*Label 12090*/ GIMT_Encode4(758874), // Rule ID 10723 //
     /*  758822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  758825 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758848 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  758851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758858 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  758868 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758872 */     GIR_RootConstrainSelectedInstOperands,
     /*  758873 */     // GIR_Coverage, 10723,
     /*  758873 */     GIR_EraseRootFromParent_Done,
     /*  758874 */   // Label 12090: @758874
     /*  758874 */   GIM_Try, /*On fail goto*//*Label 12091*/ GIMT_Encode4(758931), // Rule ID 10724 //
     /*  758879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  758882 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758894 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758898 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758905 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  758908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758915 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  758925 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758929 */     GIR_RootConstrainSelectedInstOperands,
     /*  758930 */     // GIR_Coverage, 10724,
     /*  758930 */     GIR_EraseRootFromParent_Done,
     /*  758931 */   // Label 12091: @758931
     /*  758931 */   GIM_Try, /*On fail goto*//*Label 12092*/ GIMT_Encode4(758988), // Rule ID 10725 //
     /*  758936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  758939 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  758947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  758951 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  758955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  758962 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  758962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  758965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  758967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  758972 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  758974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  758979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  758982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  758986 */     GIR_RootConstrainSelectedInstOperands,
     /*  758987 */     // GIR_Coverage, 10725,
     /*  758987 */     GIR_EraseRootFromParent_Done,
     /*  758988 */   // Label 12092: @758988
     /*  758988 */   GIM_Try, /*On fail goto*//*Label 12093*/ GIMT_Encode4(759045), // Rule ID 10726 //
     /*  758993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  758996 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  759008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  759019 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  759019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  759022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  759024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  759029 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  759031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  759036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  759039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759043 */     GIR_RootConstrainSelectedInstOperands,
     /*  759044 */     // GIR_Coverage, 10726,
     /*  759044 */     GIR_EraseRootFromParent_Done,
     /*  759045 */   // Label 12093: @759045
     /*  759045 */   GIM_Try, /*On fail goto*//*Label 12094*/ GIMT_Encode4(759101), // Rule ID 11278 //
     /*  759050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  759053 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  759064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  759075 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  759075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  759078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  759080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  759085 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  759087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  759092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  759095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759099 */     GIR_RootConstrainSelectedInstOperands,
     /*  759100 */     // GIR_Coverage, 11278,
     /*  759100 */     GIR_EraseRootFromParent_Done,
     /*  759101 */   // Label 12094: @759101
     /*  759101 */   GIM_Try, /*On fail goto*//*Label 12095*/ GIMT_Encode4(759157), // Rule ID 11279 //
     /*  759106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  759109 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  759120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  759131 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  759131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  759134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  759136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  759141 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  759143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  759148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  759151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759155 */     GIR_RootConstrainSelectedInstOperands,
     /*  759156 */     // GIR_Coverage, 11279,
     /*  759156 */     GIR_EraseRootFromParent_Done,
     /*  759157 */   // Label 12095: @759157
     /*  759157 */   GIM_Try, /*On fail goto*//*Label 12096*/ GIMT_Encode4(759213), // Rule ID 11280 //
     /*  759162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  759165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  759176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759180 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  759187 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  759187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  759190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  759192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  759197 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  759199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  759204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  759207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759211 */     GIR_RootConstrainSelectedInstOperands,
     /*  759212 */     // GIR_Coverage, 11280,
     /*  759212 */     GIR_EraseRootFromParent_Done,
     /*  759213 */   // Label 12096: @759213
     /*  759213 */   GIM_Try, /*On fail goto*//*Label 12097*/ GIMT_Encode4(759269), // Rule ID 11281 //
     /*  759218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  759221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  759232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  759243 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  759243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  759246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  759248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  759253 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  759255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  759260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  759263 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759267 */     GIR_RootConstrainSelectedInstOperands,
     /*  759268 */     // GIR_Coverage, 11281,
     /*  759268 */     GIR_EraseRootFromParent_Done,
     /*  759269 */   // Label 12097: @759269
     /*  759269 */   GIM_Try, /*On fail goto*//*Label 12098*/ GIMT_Encode4(759325), // Rule ID 11282 //
     /*  759274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  759277 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  759288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  759299 */     // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  759299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
     /*  759302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  759304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  759309 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  759311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  759316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  759319 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759323 */     GIR_RootConstrainSelectedInstOperands,
     /*  759324 */     // GIR_Coverage, 11282,
     /*  759324 */     GIR_EraseRootFromParent_Done,
     /*  759325 */   // Label 12098: @759325
     /*  759325 */   GIM_Reject,
     /*  759326 */ // Label 11968: @759326
     /*  759326 */ GIM_Reject,
     /*  759327 */ // Label 11860: @759327
     /*  759327 */ GIM_Reject,
     /*  759328 */ // Label 33: @759328
     /*  759328 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 12101*/ GIMT_Encode4(772939),
     /*  759339 */ /*GILLT_s32*//*Label 12099*/ GIMT_Encode4(759347),
     /*  759343 */ /*GILLT_s64*//*Label 12100*/ GIMT_Encode4(765439),
     /*  759347 */ // Label 12099: @759347
     /*  759347 */ GIM_Try, /*On fail goto*//*Label 12102*/ GIMT_Encode4(765438),
     /*  759352 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  759355 */   GIM_Try, /*On fail goto*//*Label 12103*/ GIMT_Encode4(759417), // Rule ID 21178 //
     /*  759360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  759363 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759370 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759383 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64),
     /*  759386 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759411 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759415 */     GIR_RootConstrainSelectedInstOperands,
     /*  759416 */     // GIR_Coverage, 21178,
     /*  759416 */     GIR_EraseRootFromParent_Done,
     /*  759417 */   // Label 12103: @759417
     /*  759417 */   GIM_Try, /*On fail goto*//*Label 12104*/ GIMT_Encode4(759479), // Rule ID 21179 //
     /*  759422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  759425 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759432 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759445 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64),
     /*  759448 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759477 */     GIR_RootConstrainSelectedInstOperands,
     /*  759478 */     // GIR_Coverage, 21179,
     /*  759478 */     GIR_EraseRootFromParent_Done,
     /*  759479 */   // Label 12104: @759479
     /*  759479 */   GIM_Try, /*On fail goto*//*Label 12105*/ GIMT_Encode4(759541), // Rule ID 21180 //
     /*  759484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  759487 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759494 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759496 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759507 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64),
     /*  759510 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759539 */     GIR_RootConstrainSelectedInstOperands,
     /*  759540 */     // GIR_Coverage, 21180,
     /*  759540 */     GIR_EraseRootFromParent_Done,
     /*  759541 */   // Label 12105: @759541
     /*  759541 */   GIM_Try, /*On fail goto*//*Label 12106*/ GIMT_Encode4(759603), // Rule ID 21181 //
     /*  759546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  759549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759556 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759569 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64),
     /*  759572 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759601 */     GIR_RootConstrainSelectedInstOperands,
     /*  759602 */     // GIR_Coverage, 21181,
     /*  759602 */     GIR_EraseRootFromParent_Done,
     /*  759603 */   // Label 12106: @759603
     /*  759603 */   GIM_Try, /*On fail goto*//*Label 12107*/ GIMT_Encode4(759665), // Rule ID 21182 //
     /*  759608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  759611 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759618 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759631 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64),
     /*  759634 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759663 */     GIR_RootConstrainSelectedInstOperands,
     /*  759664 */     // GIR_Coverage, 21182,
     /*  759664 */     GIR_EraseRootFromParent_Done,
     /*  759665 */   // Label 12107: @759665
     /*  759665 */   GIM_Try, /*On fail goto*//*Label 12108*/ GIMT_Encode4(759727), // Rule ID 21198 //
     /*  759670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  759673 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759680 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759693 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64),
     /*  759696 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759725 */     GIR_RootConstrainSelectedInstOperands,
     /*  759726 */     // GIR_Coverage, 21198,
     /*  759726 */     GIR_EraseRootFromParent_Done,
     /*  759727 */   // Label 12108: @759727
     /*  759727 */   GIM_Try, /*On fail goto*//*Label 12109*/ GIMT_Encode4(759789), // Rule ID 21199 //
     /*  759732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  759735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759742 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759755 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64),
     /*  759758 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759787 */     GIR_RootConstrainSelectedInstOperands,
     /*  759788 */     // GIR_Coverage, 21199,
     /*  759788 */     GIR_EraseRootFromParent_Done,
     /*  759789 */   // Label 12109: @759789
     /*  759789 */   GIM_Try, /*On fail goto*//*Label 12110*/ GIMT_Encode4(759851), // Rule ID 21200 //
     /*  759794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  759797 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759804 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759806 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759817 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64),
     /*  759820 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759845 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759849 */     GIR_RootConstrainSelectedInstOperands,
     /*  759850 */     // GIR_Coverage, 21200,
     /*  759850 */     GIR_EraseRootFromParent_Done,
     /*  759851 */   // Label 12110: @759851
     /*  759851 */   GIM_Try, /*On fail goto*//*Label 12111*/ GIMT_Encode4(759913), // Rule ID 21201 //
     /*  759856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  759859 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759866 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759879 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64),
     /*  759882 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759907 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759911 */     GIR_RootConstrainSelectedInstOperands,
     /*  759912 */     // GIR_Coverage, 21201,
     /*  759912 */     GIR_EraseRootFromParent_Done,
     /*  759913 */   // Label 12111: @759913
     /*  759913 */   GIM_Try, /*On fail goto*//*Label 12112*/ GIMT_Encode4(759975), // Rule ID 21202 //
     /*  759918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  759921 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759928 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  759930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  759941 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  759941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64),
     /*  759944 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  759946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  759951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  759956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  759961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  759966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  759969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  759973 */     GIR_RootConstrainSelectedInstOperands,
     /*  759974 */     // GIR_Coverage, 21202,
     /*  759974 */     GIR_EraseRootFromParent_Done,
     /*  759975 */   // Label 12112: @759975
     /*  759975 */   GIM_Try, /*On fail goto*//*Label 12113*/ GIMT_Encode4(760041), // Rule ID 21168 //
     /*  759980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  759983 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  759990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  759994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  759998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760005 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN),
     /*  760008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760010 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760035 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760039 */     GIR_RootConstrainSelectedInstOperands,
     /*  760040 */     // GIR_Coverage, 21168,
     /*  760040 */     GIR_EraseRootFromParent_Done,
     /*  760041 */   // Label 12113: @760041
     /*  760041 */   GIM_Try, /*On fail goto*//*Label 12114*/ GIMT_Encode4(760107), // Rule ID 21169 //
     /*  760046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  760049 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760071 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN),
     /*  760074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760076 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760105 */     GIR_RootConstrainSelectedInstOperands,
     /*  760106 */     // GIR_Coverage, 21169,
     /*  760106 */     GIR_EraseRootFromParent_Done,
     /*  760107 */   // Label 12114: @760107
     /*  760107 */   GIM_Try, /*On fail goto*//*Label 12115*/ GIMT_Encode4(760173), // Rule ID 21170 //
     /*  760112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  760115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760126 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760137 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN),
     /*  760140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760142 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760171 */     GIR_RootConstrainSelectedInstOperands,
     /*  760172 */     // GIR_Coverage, 21170,
     /*  760172 */     GIR_EraseRootFromParent_Done,
     /*  760173 */   // Label 12115: @760173
     /*  760173 */   GIM_Try, /*On fail goto*//*Label 12116*/ GIMT_Encode4(760239), // Rule ID 21171 //
     /*  760178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  760181 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760203 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN),
     /*  760206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760208 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760237 */     GIR_RootConstrainSelectedInstOperands,
     /*  760238 */     // GIR_Coverage, 21171,
     /*  760238 */     GIR_EraseRootFromParent_Done,
     /*  760239 */   // Label 12116: @760239
     /*  760239 */   GIM_Try, /*On fail goto*//*Label 12117*/ GIMT_Encode4(760305), // Rule ID 21172 //
     /*  760244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  760247 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760269 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN),
     /*  760272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760274 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760303 */     GIR_RootConstrainSelectedInstOperands,
     /*  760304 */     // GIR_Coverage, 21172,
     /*  760304 */     GIR_EraseRootFromParent_Done,
     /*  760305 */   // Label 12117: @760305
     /*  760305 */   GIM_Try, /*On fail goto*//*Label 12118*/ GIMT_Encode4(760371), // Rule ID 21188 //
     /*  760310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  760313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760335 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN),
     /*  760338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760340 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760365 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760369 */     GIR_RootConstrainSelectedInstOperands,
     /*  760370 */     // GIR_Coverage, 21188,
     /*  760370 */     GIR_EraseRootFromParent_Done,
     /*  760371 */   // Label 12118: @760371
     /*  760371 */   GIM_Try, /*On fail goto*//*Label 12119*/ GIMT_Encode4(760437), // Rule ID 21189 //
     /*  760376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  760379 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760394 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760401 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN),
     /*  760404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760406 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760435 */     GIR_RootConstrainSelectedInstOperands,
     /*  760436 */     // GIR_Coverage, 21189,
     /*  760436 */     GIR_EraseRootFromParent_Done,
     /*  760437 */   // Label 12119: @760437
     /*  760437 */   GIM_Try, /*On fail goto*//*Label 12120*/ GIMT_Encode4(760503), // Rule ID 21190 //
     /*  760442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  760445 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760456 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760460 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760467 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN),
     /*  760470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760472 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760501 */     GIR_RootConstrainSelectedInstOperands,
     /*  760502 */     // GIR_Coverage, 21190,
     /*  760502 */     GIR_EraseRootFromParent_Done,
     /*  760503 */   // Label 12120: @760503
     /*  760503 */   GIM_Try, /*On fail goto*//*Label 12121*/ GIMT_Encode4(760569), // Rule ID 21191 //
     /*  760508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  760511 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760533 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN),
     /*  760536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760538 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760567 */     GIR_RootConstrainSelectedInstOperands,
     /*  760568 */     // GIR_Coverage, 21191,
     /*  760568 */     GIR_EraseRootFromParent_Done,
     /*  760569 */   // Label 12121: @760569
     /*  760569 */   GIM_Try, /*On fail goto*//*Label 12122*/ GIMT_Encode4(760635), // Rule ID 21192 //
     /*  760574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  760577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  760588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  760599 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN),
     /*  760602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  760604 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  760611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  760621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  760626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  760629 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760633 */     GIR_RootConstrainSelectedInstOperands,
     /*  760634 */     // GIR_Coverage, 21192,
     /*  760634 */     GIR_EraseRootFromParent_Done,
     /*  760635 */   // Label 12122: @760635
     /*  760635 */   GIM_Try, /*On fail goto*//*Label 12123*/ GIMT_Encode4(760692), // Rule ID 21173 //
     /*  760640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  760643 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760650 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  760663 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
     /*  760666 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  760678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  760683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  760686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760690 */     GIR_RootConstrainSelectedInstOperands,
     /*  760691 */     // GIR_Coverage, 21173,
     /*  760691 */     GIR_EraseRootFromParent_Done,
     /*  760692 */   // Label 12123: @760692
     /*  760692 */   GIM_Try, /*On fail goto*//*Label 12124*/ GIMT_Encode4(760749), // Rule ID 21174 //
     /*  760697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  760700 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760707 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  760720 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
     /*  760723 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  760735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  760740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  760743 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760747 */     GIR_RootConstrainSelectedInstOperands,
     /*  760748 */     // GIR_Coverage, 21174,
     /*  760748 */     GIR_EraseRootFromParent_Done,
     /*  760749 */   // Label 12124: @760749
     /*  760749 */   GIM_Try, /*On fail goto*//*Label 12125*/ GIMT_Encode4(760806), // Rule ID 21175 //
     /*  760754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  760757 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760764 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  760777 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
     /*  760780 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  760792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  760797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  760800 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760804 */     GIR_RootConstrainSelectedInstOperands,
     /*  760805 */     // GIR_Coverage, 21175,
     /*  760805 */     GIR_EraseRootFromParent_Done,
     /*  760806 */   // Label 12125: @760806
     /*  760806 */   GIM_Try, /*On fail goto*//*Label 12126*/ GIMT_Encode4(760863), // Rule ID 21176 //
     /*  760811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  760814 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760821 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  760834 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
     /*  760837 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  760849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  760854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  760857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760861 */     GIR_RootConstrainSelectedInstOperands,
     /*  760862 */     // GIR_Coverage, 21176,
     /*  760862 */     GIR_EraseRootFromParent_Done,
     /*  760863 */   // Label 12126: @760863
     /*  760863 */   GIM_Try, /*On fail goto*//*Label 12127*/ GIMT_Encode4(760920), // Rule ID 21177 //
     /*  760868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  760871 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760878 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  760891 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
     /*  760894 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  760906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  760911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  760914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760918 */     GIR_RootConstrainSelectedInstOperands,
     /*  760919 */     // GIR_Coverage, 21177,
     /*  760919 */     GIR_EraseRootFromParent_Done,
     /*  760920 */   // Label 12127: @760920
     /*  760920 */   GIM_Try, /*On fail goto*//*Label 12128*/ GIMT_Encode4(760977), // Rule ID 21193 //
     /*  760925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  760928 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760935 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  760948 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  760948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
     /*  760951 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  760953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  760958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  760963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  760968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  760971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  760975 */     GIR_RootConstrainSelectedInstOperands,
     /*  760976 */     // GIR_Coverage, 21193,
     /*  760976 */     GIR_EraseRootFromParent_Done,
     /*  760977 */   // Label 12128: @760977
     /*  760977 */   GIM_Try, /*On fail goto*//*Label 12129*/ GIMT_Encode4(761034), // Rule ID 21194 //
     /*  760982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  760985 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  760992 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  760994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  760998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761005 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
     /*  761008 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761032 */     GIR_RootConstrainSelectedInstOperands,
     /*  761033 */     // GIR_Coverage, 21194,
     /*  761033 */     GIR_EraseRootFromParent_Done,
     /*  761034 */   // Label 12129: @761034
     /*  761034 */   GIM_Try, /*On fail goto*//*Label 12130*/ GIMT_Encode4(761091), // Rule ID 21195 //
     /*  761039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  761042 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761049 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761051 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761062 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
     /*  761065 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761089 */     GIR_RootConstrainSelectedInstOperands,
     /*  761090 */     // GIR_Coverage, 21195,
     /*  761090 */     GIR_EraseRootFromParent_Done,
     /*  761091 */   // Label 12130: @761091
     /*  761091 */   GIM_Try, /*On fail goto*//*Label 12131*/ GIMT_Encode4(761148), // Rule ID 21196 //
     /*  761096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  761099 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761106 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761119 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
     /*  761122 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761139 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761146 */     GIR_RootConstrainSelectedInstOperands,
     /*  761147 */     // GIR_Coverage, 21196,
     /*  761147 */     GIR_EraseRootFromParent_Done,
     /*  761148 */   // Label 12131: @761148
     /*  761148 */   GIM_Try, /*On fail goto*//*Label 12132*/ GIMT_Encode4(761205), // Rule ID 21197 //
     /*  761153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  761156 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761163 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761165 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761176 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
     /*  761179 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761199 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761203 */     GIR_RootConstrainSelectedInstOperands,
     /*  761204 */     // GIR_Coverage, 21197,
     /*  761204 */     GIR_EraseRootFromParent_Done,
     /*  761205 */   // Label 12132: @761205
     /*  761205 */   GIM_Try, /*On fail goto*//*Label 12133*/ GIMT_Encode4(761266), // Rule ID 21163 //
     /*  761210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  761213 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761224 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761235 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
     /*  761238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761240 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761264 */     GIR_RootConstrainSelectedInstOperands,
     /*  761265 */     // GIR_Coverage, 21163,
     /*  761265 */     GIR_EraseRootFromParent_Done,
     /*  761266 */   // Label 12133: @761266
     /*  761266 */   GIM_Try, /*On fail goto*//*Label 12134*/ GIMT_Encode4(761327), // Rule ID 21164 //
     /*  761271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  761274 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761296 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
     /*  761299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761301 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761321 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761325 */     GIR_RootConstrainSelectedInstOperands,
     /*  761326 */     // GIR_Coverage, 21164,
     /*  761326 */     GIR_EraseRootFromParent_Done,
     /*  761327 */   // Label 12134: @761327
     /*  761327 */   GIM_Try, /*On fail goto*//*Label 12135*/ GIMT_Encode4(761388), // Rule ID 21165 //
     /*  761332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  761335 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761346 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761350 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761357 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
     /*  761360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761362 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761386 */     GIR_RootConstrainSelectedInstOperands,
     /*  761387 */     // GIR_Coverage, 21165,
     /*  761387 */     GIR_EraseRootFromParent_Done,
     /*  761388 */   // Label 12135: @761388
     /*  761388 */   GIM_Try, /*On fail goto*//*Label 12136*/ GIMT_Encode4(761449), // Rule ID 21166 //
     /*  761393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  761396 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761407 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761411 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761418 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
     /*  761421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761423 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761447 */     GIR_RootConstrainSelectedInstOperands,
     /*  761448 */     // GIR_Coverage, 21166,
     /*  761448 */     GIR_EraseRootFromParent_Done,
     /*  761449 */   // Label 12136: @761449
     /*  761449 */   GIM_Try, /*On fail goto*//*Label 12137*/ GIMT_Encode4(761510), // Rule ID 21167 //
     /*  761454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  761457 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761479 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
     /*  761482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761484 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761504 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761508 */     GIR_RootConstrainSelectedInstOperands,
     /*  761509 */     // GIR_Coverage, 21167,
     /*  761509 */     GIR_EraseRootFromParent_Done,
     /*  761510 */   // Label 12137: @761510
     /*  761510 */   GIM_Try, /*On fail goto*//*Label 12138*/ GIMT_Encode4(761571), // Rule ID 21183 //
     /*  761515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  761518 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761529 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761533 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761540 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
     /*  761543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761545 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761569 */     GIR_RootConstrainSelectedInstOperands,
     /*  761570 */     // GIR_Coverage, 21183,
     /*  761570 */     GIR_EraseRootFromParent_Done,
     /*  761571 */   // Label 12138: @761571
     /*  761571 */   GIM_Try, /*On fail goto*//*Label 12139*/ GIMT_Encode4(761632), // Rule ID 21184 //
     /*  761576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  761579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761601 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
     /*  761604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761606 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761630 */     GIR_RootConstrainSelectedInstOperands,
     /*  761631 */     // GIR_Coverage, 21184,
     /*  761631 */     GIR_EraseRootFromParent_Done,
     /*  761632 */   // Label 12139: @761632
     /*  761632 */   GIM_Try, /*On fail goto*//*Label 12140*/ GIMT_Encode4(761693), // Rule ID 21185 //
     /*  761637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  761640 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761651 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761662 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
     /*  761665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761667 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761691 */     GIR_RootConstrainSelectedInstOperands,
     /*  761692 */     // GIR_Coverage, 21185,
     /*  761692 */     GIR_EraseRootFromParent_Done,
     /*  761693 */   // Label 12140: @761693
     /*  761693 */   GIM_Try, /*On fail goto*//*Label 12141*/ GIMT_Encode4(761754), // Rule ID 21186 //
     /*  761698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  761701 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761723 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
     /*  761726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761728 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761752 */     GIR_RootConstrainSelectedInstOperands,
     /*  761753 */     // GIR_Coverage, 21186,
     /*  761753 */     GIR_EraseRootFromParent_Done,
     /*  761754 */   // Label 12141: @761754
     /*  761754 */   GIM_Try, /*On fail goto*//*Label 12142*/ GIMT_Encode4(761815), // Rule ID 21187 //
     /*  761759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  761762 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  761769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  761773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  761784 */     // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15624:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  761784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
     /*  761787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  761789 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  761791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  761796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  761801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  761806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  761809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761813 */     GIR_RootConstrainSelectedInstOperands,
     /*  761814 */     // GIR_Coverage, 21187,
     /*  761814 */     GIR_EraseRootFromParent_Done,
     /*  761815 */   // Label 12142: @761815
     /*  761815 */   GIM_Try, /*On fail goto*//*Label 12143*/ GIMT_Encode4(761865), // Rule ID 30330 //
     /*  761820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  761823 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  761828 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761830 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  761841 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  761841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  761844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  761849 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  761851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  761856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761859 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761863 */     GIR_RootConstrainSelectedInstOperands,
     /*  761864 */     // GIR_Coverage, 30330,
     /*  761864 */     GIR_EraseRootFromParent_Done,
     /*  761865 */   // Label 12143: @761865
     /*  761865 */   GIM_Try, /*On fail goto*//*Label 12144*/ GIMT_Encode4(761915), // Rule ID 30331 //
     /*  761870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  761873 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  761878 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761880 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  761891 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  761891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  761894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  761899 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  761901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  761906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761909 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761913 */     GIR_RootConstrainSelectedInstOperands,
     /*  761914 */     // GIR_Coverage, 30331,
     /*  761914 */     GIR_EraseRootFromParent_Done,
     /*  761915 */   // Label 12144: @761915
     /*  761915 */   GIM_Try, /*On fail goto*//*Label 12145*/ GIMT_Encode4(761965), // Rule ID 30332 //
     /*  761920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  761923 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  761928 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  761941 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  761941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  761944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  761949 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  761951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  761956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  761959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  761963 */     GIR_RootConstrainSelectedInstOperands,
     /*  761964 */     // GIR_Coverage, 30332,
     /*  761964 */     GIR_EraseRootFromParent_Done,
     /*  761965 */   // Label 12145: @761965
     /*  761965 */   GIM_Try, /*On fail goto*//*Label 12146*/ GIMT_Encode4(762015), // Rule ID 30333 //
     /*  761970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  761973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  761978 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  761980 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  761984 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  761991 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  761991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  761994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  761999 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762013 */     GIR_RootConstrainSelectedInstOperands,
     /*  762014 */     // GIR_Coverage, 30333,
     /*  762014 */     GIR_EraseRootFromParent_Done,
     /*  762015 */   // Label 12146: @762015
     /*  762015 */   GIM_Try, /*On fail goto*//*Label 12147*/ GIMT_Encode4(762065), // Rule ID 30334 //
     /*  762020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  762023 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762028 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762030 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762034 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762041 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  762044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762049 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762063 */     GIR_RootConstrainSelectedInstOperands,
     /*  762064 */     // GIR_Coverage, 30334,
     /*  762064 */     GIR_EraseRootFromParent_Done,
     /*  762065 */   // Label 12147: @762065
     /*  762065 */   GIM_Try, /*On fail goto*//*Label 12148*/ GIMT_Encode4(762115), // Rule ID 30336 //
     /*  762070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  762073 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762078 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762080 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762091 */     // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i32>>  =>  (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9),
     /*  762094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762099 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762113 */     GIR_RootConstrainSelectedInstOperands,
     /*  762114 */     // GIR_Coverage, 30336,
     /*  762114 */     GIR_EraseRootFromParent_Done,
     /*  762115 */   // Label 12148: @762115
     /*  762115 */   GIM_Try, /*On fail goto*//*Label 12149*/ GIMT_Encode4(762165), // Rule ID 30337 //
     /*  762120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  762123 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762128 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762130 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762134 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762141 */     // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i32>>  =>  (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9),
     /*  762144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762149 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762163 */     GIR_RootConstrainSelectedInstOperands,
     /*  762164 */     // GIR_Coverage, 30337,
     /*  762164 */     GIR_EraseRootFromParent_Done,
     /*  762165 */   // Label 12149: @762165
     /*  762165 */   GIM_Try, /*On fail goto*//*Label 12150*/ GIMT_Encode4(762215), // Rule ID 30338 //
     /*  762170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  762173 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762178 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762180 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762191 */     // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i32>>  =>  (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9),
     /*  762194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762199 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762213 */     GIR_RootConstrainSelectedInstOperands,
     /*  762214 */     // GIR_Coverage, 30338,
     /*  762214 */     GIR_EraseRootFromParent_Done,
     /*  762215 */   // Label 12150: @762215
     /*  762215 */   GIM_Try, /*On fail goto*//*Label 12151*/ GIMT_Encode4(762265), // Rule ID 30339 //
     /*  762220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  762223 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762228 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762241 */     // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i32>>  =>  (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9),
     /*  762244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762249 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762263 */     GIR_RootConstrainSelectedInstOperands,
     /*  762264 */     // GIR_Coverage, 30339,
     /*  762264 */     GIR_EraseRootFromParent_Done,
     /*  762265 */   // Label 12151: @762265
     /*  762265 */   GIM_Try, /*On fail goto*//*Label 12152*/ GIMT_Encode4(762315), // Rule ID 30340 //
     /*  762270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  762273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762278 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762291 */     // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i32>>  =>  (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9),
     /*  762294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762299 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762313 */     GIR_RootConstrainSelectedInstOperands,
     /*  762314 */     // GIR_Coverage, 30340,
     /*  762314 */     GIR_EraseRootFromParent_Done,
     /*  762315 */   // Label 12152: @762315
     /*  762315 */   GIM_Try, /*On fail goto*//*Label 12153*/ GIMT_Encode4(762365), // Rule ID 30342 //
     /*  762320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  762323 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  762328 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762341 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  762341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  762344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762349 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  762359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762363 */     GIR_RootConstrainSelectedInstOperands,
     /*  762364 */     // GIR_Coverage, 30342,
     /*  762364 */     GIR_EraseRootFromParent_Done,
     /*  762365 */   // Label 12153: @762365
     /*  762365 */   GIM_Try, /*On fail goto*//*Label 12154*/ GIMT_Encode4(762415), // Rule ID 30343 //
     /*  762370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  762373 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  762378 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762380 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762391 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  762391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  762394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762399 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  762409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762413 */     GIR_RootConstrainSelectedInstOperands,
     /*  762414 */     // GIR_Coverage, 30343,
     /*  762414 */     GIR_EraseRootFromParent_Done,
     /*  762415 */   // Label 12154: @762415
     /*  762415 */   GIM_Try, /*On fail goto*//*Label 12155*/ GIMT_Encode4(762465), // Rule ID 30344 //
     /*  762420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  762423 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  762428 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762434 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762441 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  762441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  762444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762449 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  762459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762463 */     GIR_RootConstrainSelectedInstOperands,
     /*  762464 */     // GIR_Coverage, 30344,
     /*  762464 */     GIR_EraseRootFromParent_Done,
     /*  762465 */   // Label 12155: @762465
     /*  762465 */   GIM_Try, /*On fail goto*//*Label 12156*/ GIMT_Encode4(762515), // Rule ID 30345 //
     /*  762470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  762473 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  762478 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762480 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762484 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762491 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  762491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  762494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762499 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  762509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762513 */     GIR_RootConstrainSelectedInstOperands,
     /*  762514 */     // GIR_Coverage, 30345,
     /*  762514 */     GIR_EraseRootFromParent_Done,
     /*  762515 */   // Label 12156: @762515
     /*  762515 */   GIM_Try, /*On fail goto*//*Label 12157*/ GIMT_Encode4(762565), // Rule ID 30346 //
     /*  762520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  762523 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  762528 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762541 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  762541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
     /*  762544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762549 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  762559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762563 */     GIR_RootConstrainSelectedInstOperands,
     /*  762564 */     // GIR_Coverage, 30346,
     /*  762564 */     GIR_EraseRootFromParent_Done,
     /*  762565 */   // Label 12157: @762565
     /*  762565 */   GIM_Try, /*On fail goto*//*Label 12158*/ GIMT_Encode4(762619), // Rule ID 30329 //
     /*  762570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
     /*  762573 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  762582 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762593 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i32>>  =>  (DS_DEC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32),
     /*  762596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  762598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762603 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762617 */     GIR_RootConstrainSelectedInstOperands,
     /*  762618 */     // GIR_Coverage, 30329,
     /*  762618 */     GIR_EraseRootFromParent_Done,
     /*  762619 */   // Label 12158: @762619
     /*  762619 */   GIM_Try, /*On fail goto*//*Label 12159*/ GIMT_Encode4(762673), // Rule ID 30335 //
     /*  762624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
     /*  762627 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  762632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  762636 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762640 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762647 */     // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i32>>  =>  (DS_DEC_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  762647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32_gfx9),
     /*  762650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  762652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762657 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  762667 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762671 */     GIR_RootConstrainSelectedInstOperands,
     /*  762672 */     // GIR_Coverage, 30335,
     /*  762672 */     GIR_EraseRootFromParent_Done,
     /*  762673 */   // Label 12159: @762673
     /*  762673 */   GIM_Try, /*On fail goto*//*Label 12160*/ GIMT_Encode4(762727), // Rule ID 30341 //
     /*  762678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
     /*  762681 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  762686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  762690 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  762701 */     // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i32>>  =>  (DS_DEC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  762701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32),
     /*  762704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  762706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  762711 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  762713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  762718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  762721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762725 */     GIR_RootConstrainSelectedInstOperands,
     /*  762726 */     // GIR_Coverage, 30341,
     /*  762726 */     GIR_EraseRootFromParent_Done,
     /*  762727 */   // Label 12160: @762727
     /*  762727 */   GIM_Try, /*On fail goto*//*Label 12161*/ GIMT_Encode4(762786), // Rule ID 12929 //
     /*  762732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  762735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  762742 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  762755 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  762755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR),
     /*  762758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  762763 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  762765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  762770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  762775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  762780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762784 */     GIR_RootConstrainSelectedInstOperands,
     /*  762785 */     // GIR_Coverage, 12929,
     /*  762785 */     GIR_EraseRootFromParent_Done,
     /*  762786 */   // Label 12161: @762786
     /*  762786 */   GIM_Try, /*On fail goto*//*Label 12162*/ GIMT_Encode4(762845), // Rule ID 12930 //
     /*  762791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  762794 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  762801 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  762814 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  762814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR),
     /*  762817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  762822 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  762824 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  762829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  762834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  762839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762843 */     GIR_RootConstrainSelectedInstOperands,
     /*  762844 */     // GIR_Coverage, 12930,
     /*  762844 */     GIR_EraseRootFromParent_Done,
     /*  762845 */   // Label 12162: @762845
     /*  762845 */   GIM_Try, /*On fail goto*//*Label 12163*/ GIMT_Encode4(762904), // Rule ID 12931 //
     /*  762850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  762853 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  762860 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  762873 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  762873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR),
     /*  762876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  762881 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  762883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  762888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  762893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  762898 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762902 */     GIR_RootConstrainSelectedInstOperands,
     /*  762903 */     // GIR_Coverage, 12931,
     /*  762903 */     GIR_EraseRootFromParent_Done,
     /*  762904 */   // Label 12163: @762904
     /*  762904 */   GIM_Try, /*On fail goto*//*Label 12164*/ GIMT_Encode4(762963), // Rule ID 12932 //
     /*  762909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  762912 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  762919 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  762932 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  762932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR),
     /*  762935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  762940 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  762942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  762947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  762952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  762957 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  762961 */     GIR_RootConstrainSelectedInstOperands,
     /*  762962 */     // GIR_Coverage, 12932,
     /*  762962 */     GIR_EraseRootFromParent_Done,
     /*  762963 */   // Label 12164: @762963
     /*  762963 */   GIM_Try, /*On fail goto*//*Label 12165*/ GIMT_Encode4(763022), // Rule ID 12933 //
     /*  762968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  762971 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  762978 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  762980 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  762984 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  762991 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  762991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR),
     /*  762994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  762999 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763020 */     GIR_RootConstrainSelectedInstOperands,
     /*  763021 */     // GIR_Coverage, 12933,
     /*  763021 */     GIR_EraseRootFromParent_Done,
     /*  763022 */   // Label 12165: @763022
     /*  763022 */   GIM_Try, /*On fail goto*//*Label 12166*/ GIMT_Encode4(763085), // Rule ID 12939 //
     /*  763027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
     /*  763030 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  763041 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  763052 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN),
     /*  763055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  763057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763062 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763079 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763083 */     GIR_RootConstrainSelectedInstOperands,
     /*  763084 */     // GIR_Coverage, 12939,
     /*  763084 */     GIR_EraseRootFromParent_Done,
     /*  763085 */   // Label 12166: @763085
     /*  763085 */   GIM_Try, /*On fail goto*//*Label 12167*/ GIMT_Encode4(763137), // Rule ID 12924 //
     /*  763090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  763093 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763100 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763102 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763113 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC),
     /*  763116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763121 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  763131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763135 */     GIR_RootConstrainSelectedInstOperands,
     /*  763136 */     // GIR_Coverage, 12924,
     /*  763136 */     GIR_EraseRootFromParent_Done,
     /*  763137 */   // Label 12167: @763137
     /*  763137 */   GIM_Try, /*On fail goto*//*Label 12168*/ GIMT_Encode4(763189), // Rule ID 12925 //
     /*  763142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  763145 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763152 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763165 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC),
     /*  763168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763173 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  763183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763187 */     GIR_RootConstrainSelectedInstOperands,
     /*  763188 */     // GIR_Coverage, 12925,
     /*  763188 */     GIR_EraseRootFromParent_Done,
     /*  763189 */   // Label 12168: @763189
     /*  763189 */   GIM_Try, /*On fail goto*//*Label 12169*/ GIMT_Encode4(763241), // Rule ID 12926 //
     /*  763194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  763197 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763204 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763217 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC),
     /*  763220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763225 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  763235 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763239 */     GIR_RootConstrainSelectedInstOperands,
     /*  763240 */     // GIR_Coverage, 12926,
     /*  763240 */     GIR_EraseRootFromParent_Done,
     /*  763241 */   // Label 12169: @763241
     /*  763241 */   GIM_Try, /*On fail goto*//*Label 12170*/ GIMT_Encode4(763293), // Rule ID 12927 //
     /*  763246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  763249 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763256 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763269 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC),
     /*  763272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763277 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  763287 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763291 */     GIR_RootConstrainSelectedInstOperands,
     /*  763292 */     // GIR_Coverage, 12927,
     /*  763292 */     GIR_EraseRootFromParent_Done,
     /*  763293 */   // Label 12170: @763293
     /*  763293 */   GIM_Try, /*On fail goto*//*Label 12171*/ GIMT_Encode4(763345), // Rule ID 12928 //
     /*  763298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  763301 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763308 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763321 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (GLOBAL_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC),
     /*  763324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763329 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  763339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763343 */     GIR_RootConstrainSelectedInstOperands,
     /*  763344 */     // GIR_Coverage, 12928,
     /*  763344 */     GIR_EraseRootFromParent_Done,
     /*  763345 */   // Label 12171: @763345
     /*  763345 */   GIM_Try, /*On fail goto*//*Label 12172*/ GIMT_Encode4(763401), // Rule ID 12934 //
     /*  763350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  763353 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  763364 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763375 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN),
     /*  763378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  763380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763385 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  763395 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763399 */     GIR_RootConstrainSelectedInstOperands,
     /*  763400 */     // GIR_Coverage, 12934,
     /*  763400 */     GIR_EraseRootFromParent_Done,
     /*  763401 */   // Label 12172: @763401
     /*  763401 */   GIM_Try, /*On fail goto*//*Label 12173*/ GIMT_Encode4(763457), // Rule ID 12935 //
     /*  763406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  763409 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  763420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763431 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN),
     /*  763434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  763436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763441 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  763451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763455 */     GIR_RootConstrainSelectedInstOperands,
     /*  763456 */     // GIR_Coverage, 12935,
     /*  763456 */     GIR_EraseRootFromParent_Done,
     /*  763457 */   // Label 12173: @763457
     /*  763457 */   GIM_Try, /*On fail goto*//*Label 12174*/ GIMT_Encode4(763513), // Rule ID 12936 //
     /*  763462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  763465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  763476 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763480 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763487 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN),
     /*  763490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  763492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763497 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  763507 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763511 */     GIR_RootConstrainSelectedInstOperands,
     /*  763512 */     // GIR_Coverage, 12936,
     /*  763512 */     GIR_EraseRootFromParent_Done,
     /*  763513 */   // Label 12174: @763513
     /*  763513 */   GIM_Try, /*On fail goto*//*Label 12175*/ GIMT_Encode4(763569), // Rule ID 12937 //
     /*  763518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  763521 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  763532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763543 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN),
     /*  763546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  763548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763553 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  763563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763567 */     GIR_RootConstrainSelectedInstOperands,
     /*  763568 */     // GIR_Coverage, 12937,
     /*  763568 */     GIR_EraseRootFromParent_Done,
     /*  763569 */   // Label 12175: @763569
     /*  763569 */   GIM_Try, /*On fail goto*//*Label 12176*/ GIMT_Encode4(763625), // Rule ID 12938 //
     /*  763574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  763577 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  763588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  763599 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  763599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN),
     /*  763602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  763604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  763609 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  763616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  763619 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763623 */     GIR_RootConstrainSelectedInstOperands,
     /*  763624 */     // GIR_Coverage, 12938,
     /*  763624 */     GIR_EraseRootFromParent_Done,
     /*  763625 */   // Label 12176: @763625
     /*  763625 */   GIM_Try, /*On fail goto*//*Label 12177*/ GIMT_Encode4(763685), // Rule ID 10529 //
     /*  763630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  763633 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763641 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  763654 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  763657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763662 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763679 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763683 */     GIR_RootConstrainSelectedInstOperands,
     /*  763684 */     // GIR_Coverage, 10529,
     /*  763684 */     GIR_EraseRootFromParent_Done,
     /*  763685 */   // Label 12177: @763685
     /*  763685 */   GIM_Try, /*On fail goto*//*Label 12178*/ GIMT_Encode4(763745), // Rule ID 10530 //
     /*  763690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  763693 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763701 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763703 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  763714 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  763717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763722 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763743 */     GIR_RootConstrainSelectedInstOperands,
     /*  763744 */     // GIR_Coverage, 10530,
     /*  763744 */     GIR_EraseRootFromParent_Done,
     /*  763745 */   // Label 12178: @763745
     /*  763745 */   GIM_Try, /*On fail goto*//*Label 12179*/ GIMT_Encode4(763805), // Rule ID 10531 //
     /*  763750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  763753 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763761 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  763774 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  763777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763782 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763803 */     GIR_RootConstrainSelectedInstOperands,
     /*  763804 */     // GIR_Coverage, 10531,
     /*  763804 */     GIR_EraseRootFromParent_Done,
     /*  763805 */   // Label 12179: @763805
     /*  763805 */   GIM_Try, /*On fail goto*//*Label 12180*/ GIMT_Encode4(763865), // Rule ID 10532 //
     /*  763810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  763813 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763821 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  763834 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  763837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763842 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763844 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763854 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763859 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763863 */     GIR_RootConstrainSelectedInstOperands,
     /*  763864 */     // GIR_Coverage, 10532,
     /*  763864 */     GIR_EraseRootFromParent_Done,
     /*  763865 */   // Label 12180: @763865
     /*  763865 */   GIM_Try, /*On fail goto*//*Label 12181*/ GIMT_Encode4(763925), // Rule ID 10533 //
     /*  763870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  763873 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763881 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  763894 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  763897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763902 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763923 */     GIR_RootConstrainSelectedInstOperands,
     /*  763924 */     // GIR_Coverage, 10533,
     /*  763924 */     GIR_EraseRootFromParent_Done,
     /*  763925 */   // Label 12181: @763925
     /*  763925 */   GIM_Try, /*On fail goto*//*Label 12182*/ GIMT_Encode4(763984), // Rule ID 11085 //
     /*  763930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  763933 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763940 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  763942 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  763946 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  763953 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  763953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  763956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  763961 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  763963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  763968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  763973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  763978 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  763982 */     GIR_RootConstrainSelectedInstOperands,
     /*  763983 */     // GIR_Coverage, 11085,
     /*  763983 */     GIR_EraseRootFromParent_Done,
     /*  763984 */   // Label 12182: @763984
     /*  763984 */   GIM_Try, /*On fail goto*//*Label 12183*/ GIMT_Encode4(764043), // Rule ID 11086 //
     /*  763989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  763992 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  763999 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764001 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  764012 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  764012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  764015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  764020 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  764027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  764032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  764037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764041 */     GIR_RootConstrainSelectedInstOperands,
     /*  764042 */     // GIR_Coverage, 11086,
     /*  764042 */     GIR_EraseRootFromParent_Done,
     /*  764043 */   // Label 12183: @764043
     /*  764043 */   GIM_Try, /*On fail goto*//*Label 12184*/ GIMT_Encode4(764102), // Rule ID 11087 //
     /*  764048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  764051 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764058 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  764071 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  764071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  764074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  764079 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  764086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  764091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  764096 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764100 */     GIR_RootConstrainSelectedInstOperands,
     /*  764101 */     // GIR_Coverage, 11087,
     /*  764101 */     GIR_EraseRootFromParent_Done,
     /*  764102 */   // Label 12184: @764102
     /*  764102 */   GIM_Try, /*On fail goto*//*Label 12185*/ GIMT_Encode4(764161), // Rule ID 11088 //
     /*  764107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  764110 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764117 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764119 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764123 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  764130 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  764130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  764133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  764138 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  764145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  764150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  764155 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764159 */     GIR_RootConstrainSelectedInstOperands,
     /*  764160 */     // GIR_Coverage, 11088,
     /*  764160 */     GIR_EraseRootFromParent_Done,
     /*  764161 */   // Label 12185: @764161
     /*  764161 */   GIM_Try, /*On fail goto*//*Label 12186*/ GIMT_Encode4(764220), // Rule ID 11089 //
     /*  764166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  764169 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764176 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764182 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  764189 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  764189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR),
     /*  764192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  764197 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  764204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  764209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  764214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764218 */     GIR_RootConstrainSelectedInstOperands,
     /*  764219 */     // GIR_Coverage, 11089,
     /*  764219 */     GIR_EraseRootFromParent_Done,
     /*  764220 */   // Label 12186: @764220
     /*  764220 */   GIM_Try, /*On fail goto*//*Label 12187*/ GIMT_Encode4(764284), // Rule ID 10523 //
     /*  764225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  764228 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  764240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764244 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  764251 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  764251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR_RTN),
     /*  764254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  764256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  764261 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  764268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  764273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  764278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764282 */     GIR_RootConstrainSelectedInstOperands,
     /*  764283 */     // GIR_Coverage, 10523,
     /*  764283 */     GIR_EraseRootFromParent_Done,
     /*  764284 */   // Label 12187: @764284
     /*  764284 */   GIM_Try, /*On fail goto*//*Label 12188*/ GIMT_Encode4(764347), // Rule ID 11079 //
     /*  764289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode),
     /*  764292 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  764303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  764314 */     // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (FLAT_ATOMIC_DEC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  764314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_SADDR_RTN),
     /*  764317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  764319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  764324 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  764331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  764336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  764341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764345 */     GIR_RootConstrainSelectedInstOperands,
     /*  764346 */     // GIR_Coverage, 11079,
     /*  764346 */     GIR_EraseRootFromParent_Done,
     /*  764347 */   // Label 12188: @764347
     /*  764347 */   GIM_Try, /*On fail goto*//*Label 12189*/ GIMT_Encode4(764400), // Rule ID 10524 //
     /*  764352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  764355 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764363 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764376 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764384 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764398 */     GIR_RootConstrainSelectedInstOperands,
     /*  764399 */     // GIR_Coverage, 10524,
     /*  764399 */     GIR_EraseRootFromParent_Done,
     /*  764400 */   // Label 12189: @764400
     /*  764400 */   GIM_Try, /*On fail goto*//*Label 12190*/ GIMT_Encode4(764453), // Rule ID 10525 //
     /*  764405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  764408 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764416 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764429 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764437 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764451 */     GIR_RootConstrainSelectedInstOperands,
     /*  764452 */     // GIR_Coverage, 10525,
     /*  764452 */     GIR_EraseRootFromParent_Done,
     /*  764453 */   // Label 12190: @764453
     /*  764453 */   GIM_Try, /*On fail goto*//*Label 12191*/ GIMT_Encode4(764506), // Rule ID 10526 //
     /*  764458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  764461 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764469 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764482 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764490 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764504 */     GIR_RootConstrainSelectedInstOperands,
     /*  764505 */     // GIR_Coverage, 10526,
     /*  764505 */     GIR_EraseRootFromParent_Done,
     /*  764506 */   // Label 12191: @764506
     /*  764506 */   GIM_Try, /*On fail goto*//*Label 12192*/ GIMT_Encode4(764559), // Rule ID 10527 //
     /*  764511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  764514 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764522 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764535 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764543 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764553 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764557 */     GIR_RootConstrainSelectedInstOperands,
     /*  764558 */     // GIR_Coverage, 10527,
     /*  764558 */     GIR_EraseRootFromParent_Done,
     /*  764559 */   // Label 12192: @764559
     /*  764559 */   GIM_Try, /*On fail goto*//*Label 12193*/ GIMT_Encode4(764612), // Rule ID 10528 //
     /*  764564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  764567 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764575 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764588 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764596 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764610 */     GIR_RootConstrainSelectedInstOperands,
     /*  764611 */     // GIR_Coverage, 10528,
     /*  764611 */     GIR_EraseRootFromParent_Done,
     /*  764612 */   // Label 12193: @764612
     /*  764612 */   GIM_Try, /*On fail goto*//*Label 12194*/ GIMT_Encode4(764664), // Rule ID 11080 //
     /*  764617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  764620 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764627 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764640 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764648 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764662 */     GIR_RootConstrainSelectedInstOperands,
     /*  764663 */     // GIR_Coverage, 11080,
     /*  764663 */     GIR_EraseRootFromParent_Done,
     /*  764664 */   // Label 12194: @764664
     /*  764664 */   GIM_Try, /*On fail goto*//*Label 12195*/ GIMT_Encode4(764716), // Rule ID 11081 //
     /*  764669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  764672 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764679 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764681 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764692 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764700 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764714 */     GIR_RootConstrainSelectedInstOperands,
     /*  764715 */     // GIR_Coverage, 11081,
     /*  764715 */     GIR_EraseRootFromParent_Done,
     /*  764716 */   // Label 12195: @764716
     /*  764716 */   GIM_Try, /*On fail goto*//*Label 12196*/ GIMT_Encode4(764768), // Rule ID 11082 //
     /*  764721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  764724 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764731 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764744 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764752 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764766 */     GIR_RootConstrainSelectedInstOperands,
     /*  764767 */     // GIR_Coverage, 11082,
     /*  764767 */     GIR_EraseRootFromParent_Done,
     /*  764768 */   // Label 12196: @764768
     /*  764768 */   GIM_Try, /*On fail goto*//*Label 12197*/ GIMT_Encode4(764820), // Rule ID 11083 //
     /*  764773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  764776 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764783 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764785 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764789 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764796 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764804 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764818 */     GIR_RootConstrainSelectedInstOperands,
     /*  764819 */     // GIR_Coverage, 11083,
     /*  764819 */     GIR_EraseRootFromParent_Done,
     /*  764820 */   // Label 12197: @764820
     /*  764820 */   GIM_Try, /*On fail goto*//*Label 12198*/ GIMT_Encode4(764872), // Rule ID 11084 //
     /*  764825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  764828 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764835 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  764837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764848 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>>  =>  (FLAT_ATOMIC_DEC VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
     /*  764851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764856 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  764866 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764870 */     GIR_RootConstrainSelectedInstOperands,
     /*  764871 */     // GIR_Coverage, 11084,
     /*  764871 */     GIR_EraseRootFromParent_Done,
     /*  764872 */   // Label 12198: @764872
     /*  764872 */   GIM_Try, /*On fail goto*//*Label 12199*/ GIMT_Encode4(764929), // Rule ID 10518 //
     /*  764877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  764880 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  764892 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764896 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764903 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  764906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  764908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764913 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  764923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764927 */     GIR_RootConstrainSelectedInstOperands,
     /*  764928 */     // GIR_Coverage, 10518,
     /*  764928 */     GIR_EraseRootFromParent_Done,
     /*  764929 */   // Label 12199: @764929
     /*  764929 */   GIM_Try, /*On fail goto*//*Label 12200*/ GIMT_Encode4(764986), // Rule ID 10519 //
     /*  764934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  764937 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  764945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  764949 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  764953 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  764960 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  764960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  764963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  764965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  764970 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  764972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  764977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  764980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  764984 */     GIR_RootConstrainSelectedInstOperands,
     /*  764985 */     // GIR_Coverage, 10519,
     /*  764985 */     GIR_EraseRootFromParent_Done,
     /*  764986 */   // Label 12200: @764986
     /*  764986 */   GIM_Try, /*On fail goto*//*Label 12201*/ GIMT_Encode4(765043), // Rule ID 10520 //
     /*  764991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  764994 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765006 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765010 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765017 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765027 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765041 */     GIR_RootConstrainSelectedInstOperands,
     /*  765042 */     // GIR_Coverage, 10520,
     /*  765042 */     GIR_EraseRootFromParent_Done,
     /*  765043 */   // Label 12201: @765043
     /*  765043 */   GIM_Try, /*On fail goto*//*Label 12202*/ GIMT_Encode4(765100), // Rule ID 10521 //
     /*  765048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  765051 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765074 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765084 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765098 */     GIR_RootConstrainSelectedInstOperands,
     /*  765099 */     // GIR_Coverage, 10521,
     /*  765099 */     GIR_EraseRootFromParent_Done,
     /*  765100 */   // Label 12202: @765100
     /*  765100 */   GIM_Try, /*On fail goto*//*Label 12203*/ GIMT_Encode4(765157), // Rule ID 10522 //
     /*  765105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  765108 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765131 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765141 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765155 */     GIR_RootConstrainSelectedInstOperands,
     /*  765156 */     // GIR_Coverage, 10522,
     /*  765156 */     GIR_EraseRootFromParent_Done,
     /*  765157 */   // Label 12203: @765157
     /*  765157 */   GIM_Try, /*On fail goto*//*Label 12204*/ GIMT_Encode4(765213), // Rule ID 11074 //
     /*  765162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  765165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765180 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765187 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765197 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765211 */     GIR_RootConstrainSelectedInstOperands,
     /*  765212 */     // GIR_Coverage, 11074,
     /*  765212 */     GIR_EraseRootFromParent_Done,
     /*  765213 */   // Label 12204: @765213
     /*  765213 */   GIM_Try, /*On fail goto*//*Label 12205*/ GIMT_Encode4(765269), // Rule ID 11075 //
     /*  765218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  765221 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765243 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765253 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765263 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765267 */     GIR_RootConstrainSelectedInstOperands,
     /*  765268 */     // GIR_Coverage, 11075,
     /*  765268 */     GIR_EraseRootFromParent_Done,
     /*  765269 */   // Label 12205: @765269
     /*  765269 */   GIM_Try, /*On fail goto*//*Label 12206*/ GIMT_Encode4(765325), // Rule ID 11076 //
     /*  765274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  765277 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765299 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765309 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765319 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765323 */     GIR_RootConstrainSelectedInstOperands,
     /*  765324 */     // GIR_Coverage, 11076,
     /*  765324 */     GIR_EraseRootFromParent_Done,
     /*  765325 */   // Label 12206: @765325
     /*  765325 */   GIM_Try, /*On fail goto*//*Label 12207*/ GIMT_Encode4(765381), // Rule ID 11077 //
     /*  765330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  765333 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765344 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765355 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765365 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765375 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765379 */     GIR_RootConstrainSelectedInstOperands,
     /*  765380 */     // GIR_Coverage, 11077,
     /*  765380 */     GIR_EraseRootFromParent_Done,
     /*  765381 */   // Label 12207: @765381
     /*  765381 */   GIM_Try, /*On fail goto*//*Label 12208*/ GIMT_Encode4(765437), // Rule ID 11078 //
     /*  765386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  765389 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  765400 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  765411 */     // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  765411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
     /*  765414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  765416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  765421 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  765423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  765428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  765431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765435 */     GIR_RootConstrainSelectedInstOperands,
     /*  765436 */     // GIR_Coverage, 11078,
     /*  765436 */     GIR_EraseRootFromParent_Done,
     /*  765437 */   // Label 12208: @765437
     /*  765437 */   GIM_Reject,
     /*  765438 */ // Label 12102: @765438
     /*  765438 */ GIM_Reject,
     /*  765439 */ // Label 12100: @765439
     /*  765439 */ GIM_Try, /*On fail goto*//*Label 12209*/ GIMT_Encode4(772938),
     /*  765444 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  765447 */   GIM_Try, /*On fail goto*//*Label 12210*/ GIMT_Encode4(765509), // Rule ID 21658 //
     /*  765452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  765455 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765462 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765464 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765475 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64),
     /*  765478 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765507 */     GIR_RootConstrainSelectedInstOperands,
     /*  765508 */     // GIR_Coverage, 21658,
     /*  765508 */     GIR_EraseRootFromParent_Done,
     /*  765509 */   // Label 12210: @765509
     /*  765509 */   GIM_Try, /*On fail goto*//*Label 12211*/ GIMT_Encode4(765571), // Rule ID 21659 //
     /*  765514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  765517 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765524 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765537 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64),
     /*  765540 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765569 */     GIR_RootConstrainSelectedInstOperands,
     /*  765570 */     // GIR_Coverage, 21659,
     /*  765570 */     GIR_EraseRootFromParent_Done,
     /*  765571 */   // Label 12211: @765571
     /*  765571 */   GIM_Try, /*On fail goto*//*Label 12212*/ GIMT_Encode4(765633), // Rule ID 21660 //
     /*  765576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  765579 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765586 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765599 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64),
     /*  765602 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765627 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765631 */     GIR_RootConstrainSelectedInstOperands,
     /*  765632 */     // GIR_Coverage, 21660,
     /*  765632 */     GIR_EraseRootFromParent_Done,
     /*  765633 */   // Label 12212: @765633
     /*  765633 */   GIM_Try, /*On fail goto*//*Label 12213*/ GIMT_Encode4(765695), // Rule ID 21661 //
     /*  765638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  765641 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765648 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765661 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64),
     /*  765664 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765693 */     GIR_RootConstrainSelectedInstOperands,
     /*  765694 */     // GIR_Coverage, 21661,
     /*  765694 */     GIR_EraseRootFromParent_Done,
     /*  765695 */   // Label 12213: @765695
     /*  765695 */   GIM_Try, /*On fail goto*//*Label 12214*/ GIMT_Encode4(765757), // Rule ID 21662 //
     /*  765700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  765703 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765710 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765723 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64),
     /*  765726 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765751 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765755 */     GIR_RootConstrainSelectedInstOperands,
     /*  765756 */     // GIR_Coverage, 21662,
     /*  765756 */     GIR_EraseRootFromParent_Done,
     /*  765757 */   // Label 12214: @765757
     /*  765757 */   GIM_Try, /*On fail goto*//*Label 12215*/ GIMT_Encode4(765819), // Rule ID 21678 //
     /*  765762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  765765 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765772 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765774 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765778 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765785 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64),
     /*  765788 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765817 */     GIR_RootConstrainSelectedInstOperands,
     /*  765818 */     // GIR_Coverage, 21678,
     /*  765818 */     GIR_EraseRootFromParent_Done,
     /*  765819 */   // Label 12215: @765819
     /*  765819 */   GIM_Try, /*On fail goto*//*Label 12216*/ GIMT_Encode4(765881), // Rule ID 21679 //
     /*  765824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  765827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765834 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765847 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64),
     /*  765850 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765879 */     GIR_RootConstrainSelectedInstOperands,
     /*  765880 */     // GIR_Coverage, 21679,
     /*  765880 */     GIR_EraseRootFromParent_Done,
     /*  765881 */   // Label 12216: @765881
     /*  765881 */   GIM_Try, /*On fail goto*//*Label 12217*/ GIMT_Encode4(765943), // Rule ID 21680 //
     /*  765886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  765889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765896 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765909 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64),
     /*  765912 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  765941 */     GIR_RootConstrainSelectedInstOperands,
     /*  765942 */     // GIR_Coverage, 21680,
     /*  765942 */     GIR_EraseRootFromParent_Done,
     /*  765943 */   // Label 12217: @765943
     /*  765943 */   GIM_Try, /*On fail goto*//*Label 12218*/ GIMT_Encode4(766005), // Rule ID 21681 //
     /*  765948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  765951 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  765958 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  765960 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  765964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  765971 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  765971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64),
     /*  765974 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  765976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  765981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  765986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  765991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  765996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  765999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766003 */     GIR_RootConstrainSelectedInstOperands,
     /*  766004 */     // GIR_Coverage, 21681,
     /*  766004 */     GIR_EraseRootFromParent_Done,
     /*  766005 */   // Label 12218: @766005
     /*  766005 */   GIM_Try, /*On fail goto*//*Label 12219*/ GIMT_Encode4(766067), // Rule ID 21682 //
     /*  766010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  766013 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766020 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  766022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766026 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766033 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64),
     /*  766036 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  766061 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766065 */     GIR_RootConstrainSelectedInstOperands,
     /*  766066 */     // GIR_Coverage, 21682,
     /*  766066 */     GIR_EraseRootFromParent_Done,
     /*  766067 */   // Label 12219: @766067
     /*  766067 */   GIM_Try, /*On fail goto*//*Label 12220*/ GIMT_Encode4(766133), // Rule ID 21648 //
     /*  766072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  766075 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766097 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN),
     /*  766100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766102 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766131 */     GIR_RootConstrainSelectedInstOperands,
     /*  766132 */     // GIR_Coverage, 21648,
     /*  766132 */     GIR_EraseRootFromParent_Done,
     /*  766133 */   // Label 12220: @766133
     /*  766133 */   GIM_Try, /*On fail goto*//*Label 12221*/ GIMT_Encode4(766199), // Rule ID 21649 //
     /*  766138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  766141 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766152 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766156 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766163 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN),
     /*  766166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766168 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766197 */     GIR_RootConstrainSelectedInstOperands,
     /*  766198 */     // GIR_Coverage, 21649,
     /*  766198 */     GIR_EraseRootFromParent_Done,
     /*  766199 */   // Label 12221: @766199
     /*  766199 */   GIM_Try, /*On fail goto*//*Label 12222*/ GIMT_Encode4(766265), // Rule ID 21650 //
     /*  766204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  766207 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766229 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN),
     /*  766232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766234 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766259 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766263 */     GIR_RootConstrainSelectedInstOperands,
     /*  766264 */     // GIR_Coverage, 21650,
     /*  766264 */     GIR_EraseRootFromParent_Done,
     /*  766265 */   // Label 12222: @766265
     /*  766265 */   GIM_Try, /*On fail goto*//*Label 12223*/ GIMT_Encode4(766331), // Rule ID 21651 //
     /*  766270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  766273 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766284 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766288 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766295 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN),
     /*  766298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766300 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766325 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766329 */     GIR_RootConstrainSelectedInstOperands,
     /*  766330 */     // GIR_Coverage, 21651,
     /*  766330 */     GIR_EraseRootFromParent_Done,
     /*  766331 */   // Label 12223: @766331
     /*  766331 */   GIM_Try, /*On fail goto*//*Label 12224*/ GIMT_Encode4(766397), // Rule ID 21652 //
     /*  766336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  766339 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766361 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN),
     /*  766364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766366 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766395 */     GIR_RootConstrainSelectedInstOperands,
     /*  766396 */     // GIR_Coverage, 21652,
     /*  766396 */     GIR_EraseRootFromParent_Done,
     /*  766397 */   // Label 12224: @766397
     /*  766397 */   GIM_Try, /*On fail goto*//*Label 12225*/ GIMT_Encode4(766463), // Rule ID 21668 //
     /*  766402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  766405 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766427 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN),
     /*  766430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766432 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766454 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766457 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766461 */     GIR_RootConstrainSelectedInstOperands,
     /*  766462 */     // GIR_Coverage, 21668,
     /*  766462 */     GIR_EraseRootFromParent_Done,
     /*  766463 */   // Label 12225: @766463
     /*  766463 */   GIM_Try, /*On fail goto*//*Label 12226*/ GIMT_Encode4(766529), // Rule ID 21669 //
     /*  766468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  766471 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766493 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN),
     /*  766496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766498 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766523 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766527 */     GIR_RootConstrainSelectedInstOperands,
     /*  766528 */     // GIR_Coverage, 21669,
     /*  766528 */     GIR_EraseRootFromParent_Done,
     /*  766529 */   // Label 12226: @766529
     /*  766529 */   GIM_Try, /*On fail goto*//*Label 12227*/ GIMT_Encode4(766595), // Rule ID 21670 //
     /*  766534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  766537 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766559 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN),
     /*  766562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766564 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766593 */     GIR_RootConstrainSelectedInstOperands,
     /*  766594 */     // GIR_Coverage, 21670,
     /*  766594 */     GIR_EraseRootFromParent_Done,
     /*  766595 */   // Label 12227: @766595
     /*  766595 */   GIM_Try, /*On fail goto*//*Label 12228*/ GIMT_Encode4(766661), // Rule ID 21671 //
     /*  766600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  766603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766625 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN),
     /*  766628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766630 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766659 */     GIR_RootConstrainSelectedInstOperands,
     /*  766660 */     // GIR_Coverage, 21671,
     /*  766660 */     GIR_EraseRootFromParent_Done,
     /*  766661 */   // Label 12228: @766661
     /*  766661 */   GIM_Try, /*On fail goto*//*Label 12229*/ GIMT_Encode4(766727), // Rule ID 21672 //
     /*  766666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  766669 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  766680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
     /*  766691 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN),
     /*  766694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  766696 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
     /*  766703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
     /*  766713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
     /*  766718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  766721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766725 */     GIR_RootConstrainSelectedInstOperands,
     /*  766726 */     // GIR_Coverage, 21672,
     /*  766726 */     GIR_EraseRootFromParent_Done,
     /*  766727 */   // Label 12229: @766727
     /*  766727 */   GIM_Try, /*On fail goto*//*Label 12230*/ GIMT_Encode4(766784), // Rule ID 21653 //
     /*  766732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  766735 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766742 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  766744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  766755 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
     /*  766758 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  766770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  766775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  766778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766782 */     GIR_RootConstrainSelectedInstOperands,
     /*  766783 */     // GIR_Coverage, 21653,
     /*  766783 */     GIR_EraseRootFromParent_Done,
     /*  766784 */   // Label 12230: @766784
     /*  766784 */   GIM_Try, /*On fail goto*//*Label 12231*/ GIMT_Encode4(766841), // Rule ID 21654 //
     /*  766789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  766792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766799 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  766801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  766812 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
     /*  766815 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  766827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  766832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  766835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766839 */     GIR_RootConstrainSelectedInstOperands,
     /*  766840 */     // GIR_Coverage, 21654,
     /*  766840 */     GIR_EraseRootFromParent_Done,
     /*  766841 */   // Label 12231: @766841
     /*  766841 */   GIM_Try, /*On fail goto*//*Label 12232*/ GIMT_Encode4(766898), // Rule ID 21655 //
     /*  766846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  766849 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766856 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  766858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766862 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  766869 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
     /*  766872 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  766884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  766889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  766892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766896 */     GIR_RootConstrainSelectedInstOperands,
     /*  766897 */     // GIR_Coverage, 21655,
     /*  766897 */     GIR_EraseRootFromParent_Done,
     /*  766898 */   // Label 12232: @766898
     /*  766898 */   GIM_Try, /*On fail goto*//*Label 12233*/ GIMT_Encode4(766955), // Rule ID 21656 //
     /*  766903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  766906 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766913 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  766915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  766926 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
     /*  766929 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  766941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  766946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  766949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  766953 */     GIR_RootConstrainSelectedInstOperands,
     /*  766954 */     // GIR_Coverage, 21656,
     /*  766954 */     GIR_EraseRootFromParent_Done,
     /*  766955 */   // Label 12233: @766955
     /*  766955 */   GIM_Try, /*On fail goto*//*Label 12234*/ GIMT_Encode4(767012), // Rule ID 21657 //
     /*  766960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  766963 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  766970 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  766972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  766976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  766983 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  766983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
     /*  766986 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  766988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  766993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  766998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767010 */     GIR_RootConstrainSelectedInstOperands,
     /*  767011 */     // GIR_Coverage, 21657,
     /*  767011 */     GIR_EraseRootFromParent_Done,
     /*  767012 */   // Label 12234: @767012
     /*  767012 */   GIM_Try, /*On fail goto*//*Label 12235*/ GIMT_Encode4(767069), // Rule ID 21673 //
     /*  767017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  767020 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767027 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767040 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
     /*  767043 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767067 */     GIR_RootConstrainSelectedInstOperands,
     /*  767068 */     // GIR_Coverage, 21673,
     /*  767068 */     GIR_EraseRootFromParent_Done,
     /*  767069 */   // Label 12235: @767069
     /*  767069 */   GIM_Try, /*On fail goto*//*Label 12236*/ GIMT_Encode4(767126), // Rule ID 21674 //
     /*  767074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  767077 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767084 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767097 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
     /*  767100 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767120 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767124 */     GIR_RootConstrainSelectedInstOperands,
     /*  767125 */     // GIR_Coverage, 21674,
     /*  767125 */     GIR_EraseRootFromParent_Done,
     /*  767126 */   // Label 12236: @767126
     /*  767126 */   GIM_Try, /*On fail goto*//*Label 12237*/ GIMT_Encode4(767183), // Rule ID 21675 //
     /*  767131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  767134 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767141 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767143 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767154 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
     /*  767157 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767181 */     GIR_RootConstrainSelectedInstOperands,
     /*  767182 */     // GIR_Coverage, 21675,
     /*  767182 */     GIR_EraseRootFromParent_Done,
     /*  767183 */   // Label 12237: @767183
     /*  767183 */   GIM_Try, /*On fail goto*//*Label 12238*/ GIMT_Encode4(767240), // Rule ID 21676 //
     /*  767188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  767191 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767198 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767200 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767211 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
     /*  767214 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767238 */     GIR_RootConstrainSelectedInstOperands,
     /*  767239 */     // GIR_Coverage, 21676,
     /*  767239 */     GIR_EraseRootFromParent_Done,
     /*  767240 */   // Label 12238: @767240
     /*  767240 */   GIM_Try, /*On fail goto*//*Label 12239*/ GIMT_Encode4(767297), // Rule ID 21677 //
     /*  767245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  767248 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767255 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767268 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
     /*  767271 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767288 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767291 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767295 */     GIR_RootConstrainSelectedInstOperands,
     /*  767296 */     // GIR_Coverage, 21677,
     /*  767296 */     GIR_EraseRootFromParent_Done,
     /*  767297 */   // Label 12239: @767297
     /*  767297 */   GIM_Try, /*On fail goto*//*Label 12240*/ GIMT_Encode4(767358), // Rule ID 21643 //
     /*  767302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode0),
     /*  767305 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767320 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767327 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
     /*  767330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767332 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767356 */     GIR_RootConstrainSelectedInstOperands,
     /*  767357 */     // GIR_Coverage, 21643,
     /*  767357 */     GIR_EraseRootFromParent_Done,
     /*  767358 */   // Label 12240: @767358
     /*  767358 */   GIM_Try, /*On fail goto*//*Label 12241*/ GIMT_Encode4(767419), // Rule ID 21644 //
     /*  767363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode1),
     /*  767366 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767381 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767388 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
     /*  767391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767393 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767413 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767417 */     GIR_RootConstrainSelectedInstOperands,
     /*  767418 */     // GIR_Coverage, 21644,
     /*  767418 */     GIR_EraseRootFromParent_Done,
     /*  767419 */   // Label 12241: @767419
     /*  767419 */   GIM_Try, /*On fail goto*//*Label 12242*/ GIMT_Encode4(767480), // Rule ID 21645 //
     /*  767424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode2),
     /*  767427 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767449 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
     /*  767452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767454 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767478 */     GIR_RootConstrainSelectedInstOperands,
     /*  767479 */     // GIR_Coverage, 21645,
     /*  767479 */     GIR_EraseRootFromParent_Done,
     /*  767480 */   // Label 12242: @767480
     /*  767480 */   GIM_Try, /*On fail goto*//*Label 12243*/ GIMT_Encode4(767541), // Rule ID 21646 //
     /*  767485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode3),
     /*  767488 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767499 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767503 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767510 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
     /*  767513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767515 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767539 */     GIR_RootConstrainSelectedInstOperands,
     /*  767540 */     // GIR_Coverage, 21646,
     /*  767540 */     GIR_EraseRootFromParent_Done,
     /*  767541 */   // Label 12243: @767541
     /*  767541 */   GIM_Try, /*On fail goto*//*Label 12244*/ GIMT_Encode4(767602), // Rule ID 21647 //
     /*  767546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_HwMode4),
     /*  767549 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767560 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767571 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
     /*  767574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767576 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767600 */     GIR_RootConstrainSelectedInstOperands,
     /*  767601 */     // GIR_Coverage, 21647,
     /*  767601 */     GIR_EraseRootFromParent_Done,
     /*  767602 */   // Label 12244: @767602
     /*  767602 */   GIM_Try, /*On fail goto*//*Label 12245*/ GIMT_Encode4(767663), // Rule ID 21663 //
     /*  767607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  767610 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767621 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767632 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
     /*  767635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767637 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767661 */     GIR_RootConstrainSelectedInstOperands,
     /*  767662 */     // GIR_Coverage, 21663,
     /*  767662 */     GIR_EraseRootFromParent_Done,
     /*  767663 */   // Label 12245: @767663
     /*  767663 */   GIM_Try, /*On fail goto*//*Label 12246*/ GIMT_Encode4(767724), // Rule ID 21664 //
     /*  767668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  767671 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767693 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
     /*  767696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767698 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767722 */     GIR_RootConstrainSelectedInstOperands,
     /*  767723 */     // GIR_Coverage, 21664,
     /*  767723 */     GIR_EraseRootFromParent_Done,
     /*  767724 */   // Label 12246: @767724
     /*  767724 */   GIM_Try, /*On fail goto*//*Label 12247*/ GIMT_Encode4(767785), // Rule ID 21665 //
     /*  767729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  767732 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767754 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
     /*  767757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767759 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767783 */     GIR_RootConstrainSelectedInstOperands,
     /*  767784 */     // GIR_Coverage, 21665,
     /*  767784 */     GIR_EraseRootFromParent_Done,
     /*  767785 */   // Label 12247: @767785
     /*  767785 */   GIM_Try, /*On fail goto*//*Label 12248*/ GIMT_Encode4(767846), // Rule ID 21666 //
     /*  767790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  767793 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767808 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767815 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
     /*  767818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767820 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767844 */     GIR_RootConstrainSelectedInstOperands,
     /*  767845 */     // GIR_Coverage, 21666,
     /*  767845 */     GIR_EraseRootFromParent_Done,
     /*  767846 */   // Label 12248: @767846
     /*  767846 */   GIM_Try, /*On fail goto*//*Label 12249*/ GIMT_Encode4(767907), // Rule ID 21667 //
     /*  767851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  767854 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  767861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  767865 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
     /*  767876 */     // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15623:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset)
     /*  767876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
     /*  767879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata]
     /*  767881 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in
     /*  767883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
     /*  767888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
     /*  767893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  767898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  767901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767905 */     GIR_RootConstrainSelectedInstOperands,
     /*  767906 */     // GIR_Coverage, 21667,
     /*  767906 */     GIR_EraseRootFromParent_Done,
     /*  767907 */   // Label 12249: @767907
     /*  767907 */   GIM_Try, /*On fail goto*//*Label 12250*/ GIMT_Encode4(767957), // Rule ID 30655 //
     /*  767912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  767915 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  767920 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  767933 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  767933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  767936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  767941 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  767943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  767948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  767951 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  767955 */     GIR_RootConstrainSelectedInstOperands,
     /*  767956 */     // GIR_Coverage, 30655,
     /*  767956 */     GIR_EraseRootFromParent_Done,
     /*  767957 */   // Label 12250: @767957
     /*  767957 */   GIM_Try, /*On fail goto*//*Label 12251*/ GIMT_Encode4(768007), // Rule ID 30656 //
     /*  767962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  767965 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  767970 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  767972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  767976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  767983 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  767983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  767986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  767991 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  767993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  767998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768005 */     GIR_RootConstrainSelectedInstOperands,
     /*  768006 */     // GIR_Coverage, 30656,
     /*  768006 */     GIR_EraseRootFromParent_Done,
     /*  768007 */   // Label 12251: @768007
     /*  768007 */   GIM_Try, /*On fail goto*//*Label 12252*/ GIMT_Encode4(768057), // Rule ID 30657 //
     /*  768012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  768015 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768020 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768026 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768033 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768041 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768055 */     GIR_RootConstrainSelectedInstOperands,
     /*  768056 */     // GIR_Coverage, 30657,
     /*  768056 */     GIR_EraseRootFromParent_Done,
     /*  768057 */   // Label 12252: @768057
     /*  768057 */   GIM_Try, /*On fail goto*//*Label 12253*/ GIMT_Encode4(768107), // Rule ID 30658 //
     /*  768062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  768065 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768070 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768083 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768091 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768105 */     GIR_RootConstrainSelectedInstOperands,
     /*  768106 */     // GIR_Coverage, 30658,
     /*  768106 */     GIR_EraseRootFromParent_Done,
     /*  768107 */   // Label 12253: @768107
     /*  768107 */   GIM_Try, /*On fail goto*//*Label 12254*/ GIMT_Encode4(768157), // Rule ID 30659 //
     /*  768112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  768115 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768120 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768122 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768133 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768141 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768155 */     GIR_RootConstrainSelectedInstOperands,
     /*  768156 */     // GIR_Coverage, 30659,
     /*  768156 */     GIR_EraseRootFromParent_Done,
     /*  768157 */   // Label 12254: @768157
     /*  768157 */   GIM_Try, /*On fail goto*//*Label 12255*/ GIMT_Encode4(768207), // Rule ID 30665 //
     /*  768162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  768165 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768170 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768176 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768183 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i64>>  =>  (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9),
     /*  768186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768191 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768205 */     GIR_RootConstrainSelectedInstOperands,
     /*  768206 */     // GIR_Coverage, 30665,
     /*  768206 */     GIR_EraseRootFromParent_Done,
     /*  768207 */   // Label 12255: @768207
     /*  768207 */   GIM_Try, /*On fail goto*//*Label 12256*/ GIMT_Encode4(768257), // Rule ID 30666 //
     /*  768212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  768215 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768220 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768233 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i64>>  =>  (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9),
     /*  768236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768241 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768255 */     GIR_RootConstrainSelectedInstOperands,
     /*  768256 */     // GIR_Coverage, 30666,
     /*  768256 */     GIR_EraseRootFromParent_Done,
     /*  768257 */   // Label 12256: @768257
     /*  768257 */   GIM_Try, /*On fail goto*//*Label 12257*/ GIMT_Encode4(768307), // Rule ID 30667 //
     /*  768262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  768265 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768270 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768283 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i64>>  =>  (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9),
     /*  768286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768291 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768305 */     GIR_RootConstrainSelectedInstOperands,
     /*  768306 */     // GIR_Coverage, 30667,
     /*  768306 */     GIR_EraseRootFromParent_Done,
     /*  768307 */   // Label 12257: @768307
     /*  768307 */   GIM_Try, /*On fail goto*//*Label 12258*/ GIMT_Encode4(768357), // Rule ID 30668 //
     /*  768312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  768315 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768320 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768333 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i64>>  =>  (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9),
     /*  768336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768341 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768355 */     GIR_RootConstrainSelectedInstOperands,
     /*  768356 */     // GIR_Coverage, 30668,
     /*  768356 */     GIR_EraseRootFromParent_Done,
     /*  768357 */   // Label 12258: @768357
     /*  768357 */   GIM_Try, /*On fail goto*//*Label 12259*/ GIMT_Encode4(768407), // Rule ID 30669 //
     /*  768362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  768365 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768370 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768383 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i64>>  =>  (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9),
     /*  768386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768391 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768405 */     GIR_RootConstrainSelectedInstOperands,
     /*  768406 */     // GIR_Coverage, 30669,
     /*  768406 */     GIR_EraseRootFromParent_Done,
     /*  768407 */   // Label 12259: @768407
     /*  768407 */   GIM_Try, /*On fail goto*//*Label 12260*/ GIMT_Encode4(768457), // Rule ID 30675 //
     /*  768412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  768415 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  768420 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768433 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  768433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768441 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  768451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768455 */     GIR_RootConstrainSelectedInstOperands,
     /*  768456 */     // GIR_Coverage, 30675,
     /*  768456 */     GIR_EraseRootFromParent_Done,
     /*  768457 */   // Label 12260: @768457
     /*  768457 */   GIM_Try, /*On fail goto*//*Label 12261*/ GIMT_Encode4(768507), // Rule ID 30676 //
     /*  768462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  768465 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  768470 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768472 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768476 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768483 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  768483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768491 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  768501 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768505 */     GIR_RootConstrainSelectedInstOperands,
     /*  768506 */     // GIR_Coverage, 30676,
     /*  768506 */     GIR_EraseRootFromParent_Done,
     /*  768507 */   // Label 12261: @768507
     /*  768507 */   GIM_Try, /*On fail goto*//*Label 12262*/ GIMT_Encode4(768557), // Rule ID 30677 //
     /*  768512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  768515 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  768520 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768533 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  768533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768541 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  768551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768555 */     GIR_RootConstrainSelectedInstOperands,
     /*  768556 */     // GIR_Coverage, 30677,
     /*  768556 */     GIR_EraseRootFromParent_Done,
     /*  768557 */   // Label 12262: @768557
     /*  768557 */   GIM_Try, /*On fail goto*//*Label 12263*/ GIMT_Encode4(768607), // Rule ID 30678 //
     /*  768562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  768565 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  768570 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768572 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768576 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768583 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  768583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768591 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  768601 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768605 */     GIR_RootConstrainSelectedInstOperands,
     /*  768606 */     // GIR_Coverage, 30678,
     /*  768606 */     GIR_EraseRootFromParent_Done,
     /*  768607 */   // Label 12263: @768607
     /*  768607 */   GIM_Try, /*On fail goto*//*Label 12264*/ GIMT_Encode4(768657), // Rule ID 30679 //
     /*  768612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  768615 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  768620 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  768622 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768626 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768633 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  768633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
     /*  768636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768641 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  768651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768655 */     GIR_RootConstrainSelectedInstOperands,
     /*  768656 */     // GIR_Coverage, 30679,
     /*  768656 */     GIR_EraseRootFromParent_Done,
     /*  768657 */   // Label 12264: @768657
     /*  768657 */   GIM_Try, /*On fail goto*//*Label 12265*/ GIMT_Encode4(768711), // Rule ID 30650 //
     /*  768662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode0),
     /*  768665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768685 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  768688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  768690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768695 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768705 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768709 */     GIR_RootConstrainSelectedInstOperands,
     /*  768710 */     // GIR_Coverage, 30650,
     /*  768710 */     GIR_EraseRootFromParent_Done,
     /*  768711 */   // Label 12265: @768711
     /*  768711 */   GIM_Try, /*On fail goto*//*Label 12266*/ GIMT_Encode4(768765), // Rule ID 30651 //
     /*  768716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode1),
     /*  768719 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768728 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768732 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768739 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  768742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  768744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768749 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768759 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768763 */     GIR_RootConstrainSelectedInstOperands,
     /*  768764 */     // GIR_Coverage, 30651,
     /*  768764 */     GIR_EraseRootFromParent_Done,
     /*  768765 */   // Label 12266: @768765
     /*  768765 */   GIM_Try, /*On fail goto*//*Label 12267*/ GIMT_Encode4(768819), // Rule ID 30652 //
     /*  768770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode2),
     /*  768773 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768793 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  768796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  768798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768803 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768813 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768817 */     GIR_RootConstrainSelectedInstOperands,
     /*  768818 */     // GIR_Coverage, 30652,
     /*  768818 */     GIR_EraseRootFromParent_Done,
     /*  768819 */   // Label 12267: @768819
     /*  768819 */   GIM_Try, /*On fail goto*//*Label 12268*/ GIMT_Encode4(768873), // Rule ID 30653 //
     /*  768824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode3),
     /*  768827 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768836 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768847 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  768850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  768852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768857 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768867 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768871 */     GIR_RootConstrainSelectedInstOperands,
     /*  768872 */     // GIR_Coverage, 30653,
     /*  768872 */     GIR_EraseRootFromParent_Done,
     /*  768873 */   // Label 12268: @768873
     /*  768873 */   GIM_Try, /*On fail goto*//*Label 12269*/ GIMT_Encode4(768927), // Rule ID 30654 //
     /*  768878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_HwMode4),
     /*  768881 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768890 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768901 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  768904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  768906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768911 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768921 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768925 */     GIR_RootConstrainSelectedInstOperands,
     /*  768926 */     // GIR_Coverage, 30654,
     /*  768926 */     GIR_EraseRootFromParent_Done,
     /*  768927 */   // Label 12269: @768927
     /*  768927 */   GIM_Try, /*On fail goto*//*Label 12270*/ GIMT_Encode4(768981), // Rule ID 30660 //
     /*  768932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode0),
     /*  768935 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768944 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  768948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  768955 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i64>>  =>  (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  768955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9),
     /*  768958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  768960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  768965 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  768967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  768972 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  768975 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  768979 */     GIR_RootConstrainSelectedInstOperands,
     /*  768980 */     // GIR_Coverage, 30660,
     /*  768980 */     GIR_EraseRootFromParent_Done,
     /*  768981 */   // Label 12270: @768981
     /*  768981 */   GIM_Try, /*On fail goto*//*Label 12271*/ GIMT_Encode4(769035), // Rule ID 30661 //
     /*  768986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode1),
     /*  768989 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  768994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  768998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769009 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i64>>  =>  (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  769009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9),
     /*  769012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769019 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  769029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769033 */     GIR_RootConstrainSelectedInstOperands,
     /*  769034 */     // GIR_Coverage, 30661,
     /*  769034 */     GIR_EraseRootFromParent_Done,
     /*  769035 */   // Label 12271: @769035
     /*  769035 */   GIM_Try, /*On fail goto*//*Label 12272*/ GIMT_Encode4(769089), // Rule ID 30662 //
     /*  769040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode2),
     /*  769043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  769048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769052 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769056 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769063 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i64>>  =>  (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  769063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9),
     /*  769066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769073 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769075 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769080 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  769083 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769087 */     GIR_RootConstrainSelectedInstOperands,
     /*  769088 */     // GIR_Coverage, 30662,
     /*  769088 */     GIR_EraseRootFromParent_Done,
     /*  769089 */   // Label 12272: @769089
     /*  769089 */   GIM_Try, /*On fail goto*//*Label 12273*/ GIMT_Encode4(769143), // Rule ID 30663 //
     /*  769094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode3),
     /*  769097 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  769102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769117 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i64>>  =>  (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  769117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9),
     /*  769120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769127 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  769137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769141 */     GIR_RootConstrainSelectedInstOperands,
     /*  769142 */     // GIR_Coverage, 30663,
     /*  769142 */     GIR_EraseRootFromParent_Done,
     /*  769143 */   // Label 12273: @769143
     /*  769143 */   GIM_Try, /*On fail goto*//*Label 12274*/ GIMT_Encode4(769197), // Rule ID 30664 //
     /*  769148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_HwMode4),
     /*  769151 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  769156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769171 */     // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i64>>  =>  (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  769171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9),
     /*  769174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769181 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  769191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769195 */     GIR_RootConstrainSelectedInstOperands,
     /*  769196 */     // GIR_Coverage, 30664,
     /*  769196 */     GIR_EraseRootFromParent_Done,
     /*  769197 */   // Label 12274: @769197
     /*  769197 */   GIM_Try, /*On fail goto*//*Label 12275*/ GIMT_Encode4(769251), // Rule ID 30670 //
     /*  769202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode0),
     /*  769205 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  769210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769218 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769225 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  769225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  769228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769235 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  769245 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769249 */     GIR_RootConstrainSelectedInstOperands,
     /*  769250 */     // GIR_Coverage, 30670,
     /*  769250 */     GIR_EraseRootFromParent_Done,
     /*  769251 */   // Label 12275: @769251
     /*  769251 */   GIM_Try, /*On fail goto*//*Label 12276*/ GIMT_Encode4(769305), // Rule ID 30671 //
     /*  769256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode1),
     /*  769259 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  769264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769268 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769279 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  769279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  769282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769289 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  769299 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769303 */     GIR_RootConstrainSelectedInstOperands,
     /*  769304 */     // GIR_Coverage, 30671,
     /*  769304 */     GIR_EraseRootFromParent_Done,
     /*  769305 */   // Label 12276: @769305
     /*  769305 */   GIM_Try, /*On fail goto*//*Label 12277*/ GIMT_Encode4(769359), // Rule ID 30672 //
     /*  769310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode2),
     /*  769313 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  769318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769322 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769333 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  769333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  769336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769343 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  769353 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769357 */     GIR_RootConstrainSelectedInstOperands,
     /*  769358 */     // GIR_Coverage, 30672,
     /*  769358 */     GIR_EraseRootFromParent_Done,
     /*  769359 */   // Label 12277: @769359
     /*  769359 */   GIM_Try, /*On fail goto*//*Label 12278*/ GIMT_Encode4(769413), // Rule ID 30673 //
     /*  769364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode3),
     /*  769367 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  769372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769376 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769387 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  769387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  769390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769397 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  769407 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769411 */     GIR_RootConstrainSelectedInstOperands,
     /*  769412 */     // GIR_Coverage, 30673,
     /*  769412 */     GIR_EraseRootFromParent_Done,
     /*  769413 */   // Label 12278: @769413
     /*  769413 */   GIM_Try, /*On fail goto*//*Label 12279*/ GIMT_Encode4(769467), // Rule ID 30674 //
     /*  769418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HwMode4),
     /*  769421 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
     /*  769426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769434 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  769441 */     // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15623:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
     /*  769441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
     /*  769444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  769451 */     GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  769453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  769458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  769461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769465 */     GIR_RootConstrainSelectedInstOperands,
     /*  769466 */     // GIR_Coverage, 30674,
     /*  769466 */     GIR_EraseRootFromParent_Done,
     /*  769467 */   // Label 12279: @769467
     /*  769467 */   GIM_Try, /*On fail goto*//*Label 12280*/ GIMT_Encode4(769526), // Rule ID 13165 //
     /*  769472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  769475 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769482 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  769484 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  769495 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR),
     /*  769498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769503 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769520 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769524 */     GIR_RootConstrainSelectedInstOperands,
     /*  769525 */     // GIR_Coverage, 13165,
     /*  769525 */     GIR_EraseRootFromParent_Done,
     /*  769526 */   // Label 12280: @769526
     /*  769526 */   GIM_Try, /*On fail goto*//*Label 12281*/ GIMT_Encode4(769585), // Rule ID 13166 //
     /*  769531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  769534 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769541 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  769543 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  769554 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR),
     /*  769557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769562 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769583 */     GIR_RootConstrainSelectedInstOperands,
     /*  769584 */     // GIR_Coverage, 13166,
     /*  769584 */     GIR_EraseRootFromParent_Done,
     /*  769585 */   // Label 12281: @769585
     /*  769585 */   GIM_Try, /*On fail goto*//*Label 12282*/ GIMT_Encode4(769644), // Rule ID 13167 //
     /*  769590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  769593 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769600 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  769602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769606 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  769613 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR),
     /*  769616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769621 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769642 */     GIR_RootConstrainSelectedInstOperands,
     /*  769643 */     // GIR_Coverage, 13167,
     /*  769643 */     GIR_EraseRootFromParent_Done,
     /*  769644 */   // Label 12282: @769644
     /*  769644 */   GIM_Try, /*On fail goto*//*Label 12283*/ GIMT_Encode4(769703), // Rule ID 13168 //
     /*  769649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  769652 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769659 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  769661 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  769672 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR),
     /*  769675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769680 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769701 */     GIR_RootConstrainSelectedInstOperands,
     /*  769702 */     // GIR_Coverage, 13168,
     /*  769702 */     GIR_EraseRootFromParent_Done,
     /*  769703 */   // Label 12283: @769703
     /*  769703 */   GIM_Try, /*On fail goto*//*Label 12284*/ GIMT_Encode4(769762), // Rule ID 13169 //
     /*  769708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  769711 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769718 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  769720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  769731 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR),
     /*  769734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769739 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769760 */     GIR_RootConstrainSelectedInstOperands,
     /*  769761 */     // GIR_Coverage, 13169,
     /*  769761 */     GIR_EraseRootFromParent_Done,
     /*  769762 */   // Label 12284: @769762
     /*  769762 */   GIM_Try, /*On fail goto*//*Label 12285*/ GIMT_Encode4(769825), // Rule ID 13175 //
     /*  769767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  769770 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769781 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  769792 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN),
     /*  769795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769802 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769823 */     GIR_RootConstrainSelectedInstOperands,
     /*  769824 */     // GIR_Coverage, 13175,
     /*  769824 */     GIR_EraseRootFromParent_Done,
     /*  769825 */   // Label 12285: @769825
     /*  769825 */   GIM_Try, /*On fail goto*//*Label 12286*/ GIMT_Encode4(769888), // Rule ID 13176 //
     /*  769830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  769833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  769855 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN),
     /*  769858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769865 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769886 */     GIR_RootConstrainSelectedInstOperands,
     /*  769887 */     // GIR_Coverage, 13176,
     /*  769887 */     GIR_EraseRootFromParent_Done,
     /*  769888 */   // Label 12286: @769888
     /*  769888 */   GIM_Try, /*On fail goto*//*Label 12287*/ GIMT_Encode4(769951), // Rule ID 13177 //
     /*  769893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  769896 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  769918 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN),
     /*  769921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769928 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  769940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  769945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  769949 */     GIR_RootConstrainSelectedInstOperands,
     /*  769950 */     // GIR_Coverage, 13177,
     /*  769950 */     GIR_EraseRootFromParent_Done,
     /*  769951 */   // Label 12287: @769951
     /*  769951 */   GIM_Try, /*On fail goto*//*Label 12288*/ GIMT_Encode4(770014), // Rule ID 13178 //
     /*  769956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  769959 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  769966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  769970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  769974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  769981 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  769981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN),
     /*  769984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  769986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  769991 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  769993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  769998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770012 */     GIR_RootConstrainSelectedInstOperands,
     /*  770013 */     // GIR_Coverage, 13178,
     /*  770013 */     GIR_EraseRootFromParent_Done,
     /*  770014 */   // Label 12288: @770014
     /*  770014 */   GIM_Try, /*On fail goto*//*Label 12289*/ GIMT_Encode4(770077), // Rule ID 13179 //
     /*  770019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  770022 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  770033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  770044 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN),
     /*  770047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  770049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770054 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770075 */     GIR_RootConstrainSelectedInstOperands,
     /*  770076 */     // GIR_Coverage, 13179,
     /*  770076 */     GIR_EraseRootFromParent_Done,
     /*  770077 */   // Label 12289: @770077
     /*  770077 */   GIM_Try, /*On fail goto*//*Label 12290*/ GIMT_Encode4(770129), // Rule ID 13160 //
     /*  770082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  770085 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770092 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770094 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770105 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2),
     /*  770108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770113 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  770123 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770127 */     GIR_RootConstrainSelectedInstOperands,
     /*  770128 */     // GIR_Coverage, 13160,
     /*  770128 */     GIR_EraseRootFromParent_Done,
     /*  770129 */   // Label 12290: @770129
     /*  770129 */   GIM_Try, /*On fail goto*//*Label 12291*/ GIMT_Encode4(770181), // Rule ID 13161 //
     /*  770134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  770137 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770144 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770146 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770150 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770157 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2),
     /*  770160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770165 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770172 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  770175 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770179 */     GIR_RootConstrainSelectedInstOperands,
     /*  770180 */     // GIR_Coverage, 13161,
     /*  770180 */     GIR_EraseRootFromParent_Done,
     /*  770181 */   // Label 12291: @770181
     /*  770181 */   GIM_Try, /*On fail goto*//*Label 12292*/ GIMT_Encode4(770233), // Rule ID 13162 //
     /*  770186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  770189 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770196 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770202 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770209 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2),
     /*  770212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770217 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  770227 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770231 */     GIR_RootConstrainSelectedInstOperands,
     /*  770232 */     // GIR_Coverage, 13162,
     /*  770232 */     GIR_EraseRootFromParent_Done,
     /*  770233 */   // Label 12292: @770233
     /*  770233 */   GIM_Try, /*On fail goto*//*Label 12293*/ GIMT_Encode4(770285), // Rule ID 13163 //
     /*  770238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  770241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770248 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770261 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2),
     /*  770264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770269 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  770279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770283 */     GIR_RootConstrainSelectedInstOperands,
     /*  770284 */     // GIR_Coverage, 13163,
     /*  770284 */     GIR_EraseRootFromParent_Done,
     /*  770285 */   // Label 12293: @770285
     /*  770285 */   GIM_Try, /*On fail goto*//*Label 12294*/ GIMT_Encode4(770337), // Rule ID 13164 //
     /*  770290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  770293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770300 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770313 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2),
     /*  770316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770321 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  770331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770335 */     GIR_RootConstrainSelectedInstOperands,
     /*  770336 */     // GIR_Coverage, 13164,
     /*  770336 */     GIR_EraseRootFromParent_Done,
     /*  770337 */   // Label 12294: @770337
     /*  770337 */   GIM_Try, /*On fail goto*//*Label 12295*/ GIMT_Encode4(770393), // Rule ID 13170 //
     /*  770342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode0),
     /*  770345 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  770356 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770367 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN),
     /*  770370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  770372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770377 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  770387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770391 */     GIR_RootConstrainSelectedInstOperands,
     /*  770392 */     // GIR_Coverage, 13170,
     /*  770392 */     GIR_EraseRootFromParent_Done,
     /*  770393 */   // Label 12295: @770393
     /*  770393 */   GIM_Try, /*On fail goto*//*Label 12296*/ GIMT_Encode4(770449), // Rule ID 13171 //
     /*  770398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode1),
     /*  770401 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  770412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770423 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN),
     /*  770426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  770428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770433 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  770443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770447 */     GIR_RootConstrainSelectedInstOperands,
     /*  770448 */     // GIR_Coverage, 13171,
     /*  770448 */     GIR_EraseRootFromParent_Done,
     /*  770449 */   // Label 12296: @770449
     /*  770449 */   GIM_Try, /*On fail goto*//*Label 12297*/ GIMT_Encode4(770505), // Rule ID 13172 //
     /*  770454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode2),
     /*  770457 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  770468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770479 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN),
     /*  770482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  770484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770489 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  770499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770503 */     GIR_RootConstrainSelectedInstOperands,
     /*  770504 */     // GIR_Coverage, 13172,
     /*  770504 */     GIR_EraseRootFromParent_Done,
     /*  770505 */   // Label 12297: @770505
     /*  770505 */   GIM_Try, /*On fail goto*//*Label 12298*/ GIMT_Encode4(770561), // Rule ID 13173 //
     /*  770510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode3),
     /*  770513 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  770524 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770528 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770535 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN),
     /*  770538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  770540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770545 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  770555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770559 */     GIR_RootConstrainSelectedInstOperands,
     /*  770560 */     // GIR_Coverage, 13173,
     /*  770560 */     GIR_EraseRootFromParent_Done,
     /*  770561 */   // Label 12298: @770561
     /*  770561 */   GIM_Try, /*On fail goto*//*Label 12299*/ GIMT_Encode4(770617), // Rule ID 13174 //
     /*  770566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_HwMode4),
     /*  770569 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  770580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  770591 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  770591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN),
     /*  770594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  770596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  770601 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  770608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  770611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770615 */     GIR_RootConstrainSelectedInstOperands,
     /*  770616 */     // GIR_Coverage, 13174,
     /*  770616 */     GIR_EraseRootFromParent_Done,
     /*  770617 */   // Label 12299: @770617
     /*  770617 */   GIM_Try, /*On fail goto*//*Label 12300*/ GIMT_Encode4(770677), // Rule ID 10757 //
     /*  770622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  770625 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770633 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770635 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  770646 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  770649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770654 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770675 */     GIR_RootConstrainSelectedInstOperands,
     /*  770676 */     // GIR_Coverage, 10757,
     /*  770676 */     GIR_EraseRootFromParent_Done,
     /*  770677 */   // Label 12300: @770677
     /*  770677 */   GIM_Try, /*On fail goto*//*Label 12301*/ GIMT_Encode4(770737), // Rule ID 10758 //
     /*  770682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  770685 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770693 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  770706 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  770709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770714 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770731 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770735 */     GIR_RootConstrainSelectedInstOperands,
     /*  770736 */     // GIR_Coverage, 10758,
     /*  770736 */     GIR_EraseRootFromParent_Done,
     /*  770737 */   // Label 12301: @770737
     /*  770737 */   GIM_Try, /*On fail goto*//*Label 12302*/ GIMT_Encode4(770797), // Rule ID 10759 //
     /*  770742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  770745 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770753 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770755 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  770766 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  770769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770774 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770795 */     GIR_RootConstrainSelectedInstOperands,
     /*  770796 */     // GIR_Coverage, 10759,
     /*  770796 */     GIR_EraseRootFromParent_Done,
     /*  770797 */   // Label 12302: @770797
     /*  770797 */   GIM_Try, /*On fail goto*//*Label 12303*/ GIMT_Encode4(770857), // Rule ID 10760 //
     /*  770802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  770805 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770813 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770815 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  770826 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  770829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770834 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770851 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770855 */     GIR_RootConstrainSelectedInstOperands,
     /*  770856 */     // GIR_Coverage, 10760,
     /*  770856 */     GIR_EraseRootFromParent_Done,
     /*  770857 */   // Label 12303: @770857
     /*  770857 */   GIM_Try, /*On fail goto*//*Label 12304*/ GIMT_Encode4(770917), // Rule ID 10761 //
     /*  770862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  770865 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770873 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770879 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  770886 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  770889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770894 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770911 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770915 */     GIR_RootConstrainSelectedInstOperands,
     /*  770916 */     // GIR_Coverage, 10761,
     /*  770916 */     GIR_EraseRootFromParent_Done,
     /*  770917 */   // Label 12304: @770917
     /*  770917 */   GIM_Try, /*On fail goto*//*Label 12305*/ GIMT_Encode4(770976), // Rule ID 11313 //
     /*  770922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  770925 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770932 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770934 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770938 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  770945 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  770945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  770948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  770953 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  770955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  770960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  770965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  770970 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  770974 */     GIR_RootConstrainSelectedInstOperands,
     /*  770975 */     // GIR_Coverage, 11313,
     /*  770975 */     GIR_EraseRootFromParent_Done,
     /*  770976 */   // Label 12305: @770976
     /*  770976 */   GIM_Try, /*On fail goto*//*Label 12306*/ GIMT_Encode4(771035), // Rule ID 11314 //
     /*  770981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  770984 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  770991 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  770993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  770997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  771004 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  771007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771012 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771033 */     GIR_RootConstrainSelectedInstOperands,
     /*  771034 */     // GIR_Coverage, 11314,
     /*  771034 */     GIR_EraseRootFromParent_Done,
     /*  771035 */   // Label 12306: @771035
     /*  771035 */   GIM_Try, /*On fail goto*//*Label 12307*/ GIMT_Encode4(771094), // Rule ID 11315 //
     /*  771040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  771043 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771050 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  771052 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771056 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  771063 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  771066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771071 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771088 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771092 */     GIR_RootConstrainSelectedInstOperands,
     /*  771093 */     // GIR_Coverage, 11315,
     /*  771093 */     GIR_EraseRootFromParent_Done,
     /*  771094 */   // Label 12307: @771094
     /*  771094 */   GIM_Try, /*On fail goto*//*Label 12308*/ GIMT_Encode4(771153), // Rule ID 11316 //
     /*  771099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  771102 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771109 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  771111 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  771122 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  771125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771130 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771151 */     GIR_RootConstrainSelectedInstOperands,
     /*  771152 */     // GIR_Coverage, 11316,
     /*  771152 */     GIR_EraseRootFromParent_Done,
     /*  771153 */   // Label 12308: @771153
     /*  771153 */   GIM_Try, /*On fail goto*//*Label 12309*/ GIMT_Encode4(771212), // Rule ID 11317 //
     /*  771158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  771161 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771168 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  771170 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771174 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  771181 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR),
     /*  771184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771189 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771210 */     GIR_RootConstrainSelectedInstOperands,
     /*  771211 */     // GIR_Coverage, 11317,
     /*  771211 */     GIR_EraseRootFromParent_Done,
     /*  771212 */   // Label 12309: @771212
     /*  771212 */   GIM_Try, /*On fail goto*//*Label 12310*/ GIMT_Encode4(771276), // Rule ID 10747 //
     /*  771217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  771220 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771232 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771243 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771253 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771274 */     GIR_RootConstrainSelectedInstOperands,
     /*  771275 */     // GIR_Coverage, 10747,
     /*  771275 */     GIR_EraseRootFromParent_Done,
     /*  771276 */   // Label 12310: @771276
     /*  771276 */   GIM_Try, /*On fail goto*//*Label 12311*/ GIMT_Encode4(771340), // Rule ID 10748 //
     /*  771281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  771284 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771307 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771317 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771338 */     GIR_RootConstrainSelectedInstOperands,
     /*  771339 */     // GIR_Coverage, 10748,
     /*  771339 */     GIR_EraseRootFromParent_Done,
     /*  771340 */   // Label 12311: @771340
     /*  771340 */   GIM_Try, /*On fail goto*//*Label 12312*/ GIMT_Encode4(771404), // Rule ID 10749 //
     /*  771345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  771348 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771371 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771381 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771402 */     GIR_RootConstrainSelectedInstOperands,
     /*  771403 */     // GIR_Coverage, 10749,
     /*  771403 */     GIR_EraseRootFromParent_Done,
     /*  771404 */   // Label 12312: @771404
     /*  771404 */   GIM_Try, /*On fail goto*//*Label 12313*/ GIMT_Encode4(771468), // Rule ID 10750 //
     /*  771409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  771412 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771424 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771435 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771445 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771466 */     GIR_RootConstrainSelectedInstOperands,
     /*  771467 */     // GIR_Coverage, 10750,
     /*  771467 */     GIR_EraseRootFromParent_Done,
     /*  771468 */   // Label 12313: @771468
     /*  771468 */   GIM_Try, /*On fail goto*//*Label 12314*/ GIMT_Encode4(771532), // Rule ID 10751 //
     /*  771473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  771476 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771488 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771499 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771509 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771530 */     GIR_RootConstrainSelectedInstOperands,
     /*  771531 */     // GIR_Coverage, 10751,
     /*  771531 */     GIR_EraseRootFromParent_Done,
     /*  771532 */   // Label 12314: @771532
     /*  771532 */   GIM_Try, /*On fail goto*//*Label 12315*/ GIMT_Encode4(771595), // Rule ID 11303 //
     /*  771537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode0),
     /*  771540 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771562 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771572 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771593 */     GIR_RootConstrainSelectedInstOperands,
     /*  771594 */     // GIR_Coverage, 11303,
     /*  771594 */     GIR_EraseRootFromParent_Done,
     /*  771595 */   // Label 12315: @771595
     /*  771595 */   GIM_Try, /*On fail goto*//*Label 12316*/ GIMT_Encode4(771658), // Rule ID 11304 //
     /*  771600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode1),
     /*  771603 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771625 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771635 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771656 */     GIR_RootConstrainSelectedInstOperands,
     /*  771657 */     // GIR_Coverage, 11304,
     /*  771657 */     GIR_EraseRootFromParent_Done,
     /*  771658 */   // Label 12316: @771658
     /*  771658 */   GIM_Try, /*On fail goto*//*Label 12317*/ GIMT_Encode4(771721), // Rule ID 11305 //
     /*  771663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode2),
     /*  771666 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771688 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771698 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771710 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771719 */     GIR_RootConstrainSelectedInstOperands,
     /*  771720 */     // GIR_Coverage, 11305,
     /*  771720 */     GIR_EraseRootFromParent_Done,
     /*  771721 */   // Label 12317: @771721
     /*  771721 */   GIM_Try, /*On fail goto*//*Label 12318*/ GIMT_Encode4(771784), // Rule ID 11306 //
     /*  771726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode3),
     /*  771729 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771740 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771744 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771751 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771761 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771782 */     GIR_RootConstrainSelectedInstOperands,
     /*  771783 */     // GIR_Coverage, 11306,
     /*  771783 */     GIR_EraseRootFromParent_Done,
     /*  771784 */   // Label 12318: @771784
     /*  771784 */   GIM_Try, /*On fail goto*//*Label 12319*/ GIMT_Encode4(771847), // Rule ID 11307 //
     /*  771789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HasFlatGVSMode_HwMode4),
     /*  771792 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  771803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  771814 */     // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  771814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_SADDR_RTN),
     /*  771817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  771819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  771824 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  771831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  771836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  771841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771845 */     GIR_RootConstrainSelectedInstOperands,
     /*  771846 */     // GIR_Coverage, 11307,
     /*  771846 */     GIR_EraseRootFromParent_Done,
     /*  771847 */   // Label 12319: @771847
     /*  771847 */   GIM_Try, /*On fail goto*//*Label 12320*/ GIMT_Encode4(771900), // Rule ID 10752 //
     /*  771852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  771855 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771863 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  771865 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  771876 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  771876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  771879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  771884 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  771891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  771894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771898 */     GIR_RootConstrainSelectedInstOperands,
     /*  771899 */     // GIR_Coverage, 10752,
     /*  771899 */     GIR_EraseRootFromParent_Done,
     /*  771900 */   // Label 12320: @771900
     /*  771900 */   GIM_Try, /*On fail goto*//*Label 12321*/ GIMT_Encode4(771953), // Rule ID 10753 //
     /*  771905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  771908 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771916 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  771918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  771929 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  771929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  771932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  771937 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  771944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  771947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  771951 */     GIR_RootConstrainSelectedInstOperands,
     /*  771952 */     // GIR_Coverage, 10753,
     /*  771952 */     GIR_EraseRootFromParent_Done,
     /*  771953 */   // Label 12321: @771953
     /*  771953 */   GIM_Try, /*On fail goto*//*Label 12322*/ GIMT_Encode4(772006), // Rule ID 10754 //
     /*  771958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  771961 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  771969 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  771971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  771975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  771982 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  771982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  771985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  771990 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  771992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  771997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772000 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772004 */     GIR_RootConstrainSelectedInstOperands,
     /*  772005 */     // GIR_Coverage, 10754,
     /*  772005 */     GIR_EraseRootFromParent_Done,
     /*  772006 */   // Label 12322: @772006
     /*  772006 */   GIM_Try, /*On fail goto*//*Label 12323*/ GIMT_Encode4(772059), // Rule ID 10755 //
     /*  772011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  772014 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772022 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772024 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772035 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772043 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772057 */     GIR_RootConstrainSelectedInstOperands,
     /*  772058 */     // GIR_Coverage, 10755,
     /*  772058 */     GIR_EraseRootFromParent_Done,
     /*  772059 */   // Label 12323: @772059
     /*  772059 */   GIM_Try, /*On fail goto*//*Label 12324*/ GIMT_Encode4(772112), // Rule ID 10756 //
     /*  772064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  772067 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772075 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772088 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772096 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772110 */     GIR_RootConstrainSelectedInstOperands,
     /*  772111 */     // GIR_Coverage, 10756,
     /*  772111 */     GIR_EraseRootFromParent_Done,
     /*  772112 */   // Label 12324: @772112
     /*  772112 */   GIM_Try, /*On fail goto*//*Label 12325*/ GIMT_Encode4(772164), // Rule ID 11308 //
     /*  772117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  772120 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772127 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772133 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772140 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772148 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772162 */     GIR_RootConstrainSelectedInstOperands,
     /*  772163 */     // GIR_Coverage, 11308,
     /*  772163 */     GIR_EraseRootFromParent_Done,
     /*  772164 */   // Label 12325: @772164
     /*  772164 */   GIM_Try, /*On fail goto*//*Label 12326*/ GIMT_Encode4(772216), // Rule ID 11309 //
     /*  772169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  772172 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772179 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772181 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772185 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772192 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772200 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772202 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772210 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772214 */     GIR_RootConstrainSelectedInstOperands,
     /*  772215 */     // GIR_Coverage, 11309,
     /*  772215 */     GIR_EraseRootFromParent_Done,
     /*  772216 */   // Label 12326: @772216
     /*  772216 */   GIM_Try, /*On fail goto*//*Label 12327*/ GIMT_Encode4(772268), // Rule ID 11310 //
     /*  772221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  772224 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772231 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772244 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772252 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772266 */     GIR_RootConstrainSelectedInstOperands,
     /*  772267 */     // GIR_Coverage, 11310,
     /*  772267 */     GIR_EraseRootFromParent_Done,
     /*  772268 */   // Label 12327: @772268
     /*  772268 */   GIM_Try, /*On fail goto*//*Label 12328*/ GIMT_Encode4(772320), // Rule ID 11311 //
     /*  772273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  772276 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772283 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772296 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772304 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772318 */     GIR_RootConstrainSelectedInstOperands,
     /*  772319 */     // GIR_Coverage, 11311,
     /*  772319 */     GIR_EraseRootFromParent_Done,
     /*  772320 */   // Label 12328: @772320
     /*  772320 */   GIM_Try, /*On fail goto*//*Label 12329*/ GIMT_Encode4(772372), // Rule ID 11312 //
     /*  772325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  772328 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772335 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  772337 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772341 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772348 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
     /*  772351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772356 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  772366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772370 */     GIR_RootConstrainSelectedInstOperands,
     /*  772371 */     // GIR_Coverage, 11312,
     /*  772371 */     GIR_EraseRootFromParent_Done,
     /*  772372 */   // Label 12329: @772372
     /*  772372 */   GIM_Try, /*On fail goto*//*Label 12330*/ GIMT_Encode4(772429), // Rule ID 10742 //
     /*  772377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  772380 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772396 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772403 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772413 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772427 */     GIR_RootConstrainSelectedInstOperands,
     /*  772428 */     // GIR_Coverage, 10742,
     /*  772428 */     GIR_EraseRootFromParent_Done,
     /*  772429 */   // Label 12330: @772429
     /*  772429 */   GIM_Try, /*On fail goto*//*Label 12331*/ GIMT_Encode4(772486), // Rule ID 10743 //
     /*  772434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  772437 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772449 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772460 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772470 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772480 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772484 */     GIR_RootConstrainSelectedInstOperands,
     /*  772485 */     // GIR_Coverage, 10743,
     /*  772485 */     GIR_EraseRootFromParent_Done,
     /*  772486 */   // Label 12331: @772486
     /*  772486 */   GIM_Try, /*On fail goto*//*Label 12332*/ GIMT_Encode4(772543), // Rule ID 10744 //
     /*  772491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  772494 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772506 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772517 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772527 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772537 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772541 */     GIR_RootConstrainSelectedInstOperands,
     /*  772542 */     // GIR_Coverage, 10744,
     /*  772542 */     GIR_EraseRootFromParent_Done,
     /*  772543 */   // Label 12332: @772543
     /*  772543 */   GIM_Try, /*On fail goto*//*Label 12333*/ GIMT_Encode4(772600), // Rule ID 10745 //
     /*  772548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  772551 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772574 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772584 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772598 */     GIR_RootConstrainSelectedInstOperands,
     /*  772599 */     // GIR_Coverage, 10745,
     /*  772599 */     GIR_EraseRootFromParent_Done,
     /*  772600 */   // Label 12333: @772600
     /*  772600 */   GIM_Try, /*On fail goto*//*Label 12334*/ GIMT_Encode4(772657), // Rule ID 10746 //
     /*  772605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  772608 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772631 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772641 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772651 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772655 */     GIR_RootConstrainSelectedInstOperands,
     /*  772656 */     // GIR_Coverage, 10746,
     /*  772656 */     GIR_EraseRootFromParent_Done,
     /*  772657 */   // Label 12334: @772657
     /*  772657 */   GIM_Try, /*On fail goto*//*Label 12335*/ GIMT_Encode4(772713), // Rule ID 11298 //
     /*  772662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode0),
     /*  772665 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772687 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772697 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772711 */     GIR_RootConstrainSelectedInstOperands,
     /*  772712 */     // GIR_Coverage, 11298,
     /*  772712 */     GIR_EraseRootFromParent_Done,
     /*  772713 */   // Label 12335: @772713
     /*  772713 */   GIM_Try, /*On fail goto*//*Label 12336*/ GIMT_Encode4(772769), // Rule ID 11299 //
     /*  772718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode1),
     /*  772721 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772743 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772753 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772767 */     GIR_RootConstrainSelectedInstOperands,
     /*  772768 */     // GIR_Coverage, 11299,
     /*  772768 */     GIR_EraseRootFromParent_Done,
     /*  772769 */   // Label 12336: @772769
     /*  772769 */   GIM_Try, /*On fail goto*//*Label 12337*/ GIMT_Encode4(772825), // Rule ID 11300 //
     /*  772774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode2),
     /*  772777 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772799 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772809 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772819 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772823 */     GIR_RootConstrainSelectedInstOperands,
     /*  772824 */     // GIR_Coverage, 11300,
     /*  772824 */     GIR_EraseRootFromParent_Done,
     /*  772825 */   // Label 12337: @772825
     /*  772825 */   GIM_Try, /*On fail goto*//*Label 12338*/ GIMT_Encode4(772881), // Rule ID 11301 //
     /*  772830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode3),
     /*  772833 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772855 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772865 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772875 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772879 */     GIR_RootConstrainSelectedInstOperands,
     /*  772880 */     // GIR_Coverage, 11301,
     /*  772880 */     GIR_EraseRootFromParent_Done,
     /*  772881 */   // Label 12338: @772881
     /*  772881 */   GIM_Try, /*On fail goto*//*Label 12339*/ GIMT_Encode4(772937), // Rule ID 11302 //
     /*  772886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_HwMode4),
     /*  772889 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  772896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  772900 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  772911 */     // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  772911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
     /*  772914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  772916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  772921 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  772923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  772931 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  772935 */     GIR_RootConstrainSelectedInstOperands,
     /*  772936 */     // GIR_Coverage, 11302,
     /*  772936 */     GIR_EraseRootFromParent_Done,
     /*  772937 */   // Label 12339: @772937
     /*  772937 */   GIM_Reject,
     /*  772938 */ // Label 12209: @772938
     /*  772938 */ GIM_Reject,
     /*  772939 */ // Label 12101: @772939
     /*  772939 */ GIM_Reject,
     /*  772940 */ // Label 34: @772940
     /*  772940 */ GIM_Try, /*On fail goto*//*Label 12340*/ GIMT_Encode4(774956),
     /*  772945 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  772948 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  772951 */   GIM_Try, /*On fail goto*//*Label 12341*/ GIMT_Encode4(773236),
     /*  772956 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  772961 */     GIM_Try, /*On fail goto*//*Label 12342*/ GIMT_Encode4(773006), // Rule ID 30516 //
     /*  772966 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode0),
     /*  772969 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  772971 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  772975 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  772982 */       // (atomic_load_usub_cond:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_cond_local_noret_i32>>  =>  (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  772982 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32),
     /*  772985 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  772990 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  772992 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  772997 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773000 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773004 */       GIR_RootConstrainSelectedInstOperands,
     /*  773005 */       // GIR_Coverage, 30516,
     /*  773005 */       GIR_EraseRootFromParent_Done,
     /*  773006 */     // Label 12342: @773006
     /*  773006 */     GIM_Try, /*On fail goto*//*Label 12343*/ GIMT_Encode4(773051), // Rule ID 30517 //
     /*  773011 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode1),
     /*  773014 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773016 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773020 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  773027 */       // (atomic_load_usub_cond:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_cond_local_noret_i32>>  =>  (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  773027 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32),
     /*  773030 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  773035 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  773037 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773042 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773045 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773049 */       GIR_RootConstrainSelectedInstOperands,
     /*  773050 */       // GIR_Coverage, 30517,
     /*  773050 */       GIR_EraseRootFromParent_Done,
     /*  773051 */     // Label 12343: @773051
     /*  773051 */     GIM_Try, /*On fail goto*//*Label 12344*/ GIMT_Encode4(773096), // Rule ID 30518 //
     /*  773056 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode2),
     /*  773059 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773061 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773065 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  773072 */       // (atomic_load_usub_cond:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_cond_local_noret_i32>>  =>  (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  773072 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32),
     /*  773075 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  773080 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  773082 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773087 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773090 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773094 */       GIR_RootConstrainSelectedInstOperands,
     /*  773095 */       // GIR_Coverage, 30518,
     /*  773095 */       GIR_EraseRootFromParent_Done,
     /*  773096 */     // Label 12344: @773096
     /*  773096 */     GIM_Try, /*On fail goto*//*Label 12345*/ GIMT_Encode4(773141), // Rule ID 30519 //
     /*  773101 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode3),
     /*  773104 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773106 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773110 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  773117 */       // (atomic_load_usub_cond:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_cond_local_noret_i32>>  =>  (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  773117 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32),
     /*  773120 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  773125 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  773127 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773132 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773135 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773139 */       GIR_RootConstrainSelectedInstOperands,
     /*  773140 */       // GIR_Coverage, 30519,
     /*  773140 */       GIR_EraseRootFromParent_Done,
     /*  773141 */     // Label 12345: @773141
     /*  773141 */     GIM_Try, /*On fail goto*//*Label 12346*/ GIMT_Encode4(773186), // Rule ID 30520 //
     /*  773146 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode4),
     /*  773149 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773151 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773155 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  773162 */       // (atomic_load_usub_cond:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_cond_local_noret_i32>>  =>  (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  773162 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32),
     /*  773165 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  773170 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  773172 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773177 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773180 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773184 */       GIR_RootConstrainSelectedInstOperands,
     /*  773185 */       // GIR_Coverage, 30520,
     /*  773185 */       GIR_EraseRootFromParent_Done,
     /*  773186 */     // Label 12346: @773186
     /*  773186 */     GIM_Try, /*On fail goto*//*Label 12347*/ GIMT_Encode4(773235), // Rule ID 30515 //
     /*  773191 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts),
     /*  773194 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773198 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773202 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  773209 */       // (atomic_load_usub_cond:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_cond_local_i32>>  =>  (DS_COND_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  773209 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_RTN_U32),
     /*  773212 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773214 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  773219 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  773221 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773226 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773229 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773233 */       GIR_RootConstrainSelectedInstOperands,
     /*  773234 */       // GIR_Coverage, 30515,
     /*  773234 */       GIR_EraseRootFromParent_Done,
     /*  773235 */     // Label 12347: @773235
     /*  773235 */     GIM_Reject,
     /*  773236 */   // Label 12341: @773236
     /*  773236 */   GIM_Try, /*On fail goto*//*Label 12348*/ GIMT_Encode4(773827),
     /*  773241 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  773248 */     GIM_Try, /*On fail goto*//*Label 12349*/ GIMT_Encode4(773300), // Rule ID 13371 //
     /*  773253 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  773256 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773258 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773262 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  773269 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  773269 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR),
     /*  773272 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  773277 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773279 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  773284 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  773289 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  773294 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773298 */       GIR_RootConstrainSelectedInstOperands,
     /*  773299 */       // GIR_Coverage, 13371,
     /*  773299 */       GIR_EraseRootFromParent_Done,
     /*  773300 */     // Label 12349: @773300
     /*  773300 */     GIM_Try, /*On fail goto*//*Label 12350*/ GIMT_Encode4(773356), // Rule ID 13365 //
     /*  773305 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  773308 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773312 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773316 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  773323 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  773323 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN),
     /*  773326 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773328 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  773333 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773335 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  773340 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  773345 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  773350 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773354 */       GIR_RootConstrainSelectedInstOperands,
     /*  773355 */       // GIR_Coverage, 13365,
     /*  773355 */       GIR_EraseRootFromParent_Done,
     /*  773356 */     // Label 12350: @773356
     /*  773356 */     GIM_Try, /*On fail goto*//*Label 12351*/ GIMT_Encode4(773401), // Rule ID 13366 //
     /*  773361 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode0),
     /*  773364 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773366 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773370 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773377 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773377 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32),
     /*  773380 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773385 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773387 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773392 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773395 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773399 */       GIR_RootConstrainSelectedInstOperands,
     /*  773400 */       // GIR_Coverage, 13366,
     /*  773400 */       GIR_EraseRootFromParent_Done,
     /*  773401 */     // Label 12351: @773401
     /*  773401 */     GIM_Try, /*On fail goto*//*Label 12352*/ GIMT_Encode4(773446), // Rule ID 13367 //
     /*  773406 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode1),
     /*  773409 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773411 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773415 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773422 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773422 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32),
     /*  773425 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773430 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773432 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773437 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773440 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773444 */       GIR_RootConstrainSelectedInstOperands,
     /*  773445 */       // GIR_Coverage, 13367,
     /*  773445 */       GIR_EraseRootFromParent_Done,
     /*  773446 */     // Label 12352: @773446
     /*  773446 */     GIM_Try, /*On fail goto*//*Label 12353*/ GIMT_Encode4(773491), // Rule ID 13368 //
     /*  773451 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode2),
     /*  773454 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773456 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773460 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773467 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773467 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32),
     /*  773470 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773475 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773477 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773482 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773485 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773489 */       GIR_RootConstrainSelectedInstOperands,
     /*  773490 */       // GIR_Coverage, 13368,
     /*  773490 */       GIR_EraseRootFromParent_Done,
     /*  773491 */     // Label 12353: @773491
     /*  773491 */     GIM_Try, /*On fail goto*//*Label 12354*/ GIMT_Encode4(773536), // Rule ID 13369 //
     /*  773496 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode3),
     /*  773499 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773501 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773505 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773512 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773512 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32),
     /*  773515 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773520 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773522 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773527 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773530 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773534 */       GIR_RootConstrainSelectedInstOperands,
     /*  773535 */       // GIR_Coverage, 13369,
     /*  773535 */       GIR_EraseRootFromParent_Done,
     /*  773536 */     // Label 12354: @773536
     /*  773536 */     GIM_Try, /*On fail goto*//*Label 12355*/ GIMT_Encode4(773581), // Rule ID 13370 //
     /*  773541 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode4),
     /*  773544 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  773546 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773550 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773557 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773557 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32),
     /*  773560 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773565 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773567 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773572 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  773575 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773579 */       GIR_RootConstrainSelectedInstOperands,
     /*  773580 */       // GIR_Coverage, 13370,
     /*  773580 */       GIR_EraseRootFromParent_Done,
     /*  773581 */     // Label 12355: @773581
     /*  773581 */     GIM_Try, /*On fail goto*//*Label 12356*/ GIMT_Encode4(773630), // Rule ID 13360 //
     /*  773586 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode0),
     /*  773589 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773593 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773597 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773604 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773604 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN),
     /*  773607 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773609 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773614 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773616 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773621 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  773624 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773628 */       GIR_RootConstrainSelectedInstOperands,
     /*  773629 */       // GIR_Coverage, 13360,
     /*  773629 */       GIR_EraseRootFromParent_Done,
     /*  773630 */     // Label 12356: @773630
     /*  773630 */     GIM_Try, /*On fail goto*//*Label 12357*/ GIMT_Encode4(773679), // Rule ID 13361 //
     /*  773635 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode1),
     /*  773638 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773642 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773646 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773653 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773653 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN),
     /*  773656 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773658 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773663 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773665 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773670 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  773673 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773677 */       GIR_RootConstrainSelectedInstOperands,
     /*  773678 */       // GIR_Coverage, 13361,
     /*  773678 */       GIR_EraseRootFromParent_Done,
     /*  773679 */     // Label 12357: @773679
     /*  773679 */     GIM_Try, /*On fail goto*//*Label 12358*/ GIMT_Encode4(773728), // Rule ID 13362 //
     /*  773684 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode2),
     /*  773687 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773691 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773695 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773702 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773702 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN),
     /*  773705 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773707 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773712 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773714 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773719 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  773722 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773726 */       GIR_RootConstrainSelectedInstOperands,
     /*  773727 */       // GIR_Coverage, 13362,
     /*  773727 */       GIR_EraseRootFromParent_Done,
     /*  773728 */     // Label 12358: @773728
     /*  773728 */     GIM_Try, /*On fail goto*//*Label 12359*/ GIMT_Encode4(773777), // Rule ID 13363 //
     /*  773733 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode3),
     /*  773736 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773740 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773744 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773751 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773751 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN),
     /*  773754 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773756 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773761 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773763 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773768 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  773771 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773775 */       GIR_RootConstrainSelectedInstOperands,
     /*  773776 */       // GIR_Coverage, 13363,
     /*  773776 */       GIR_EraseRootFromParent_Done,
     /*  773777 */     // Label 12359: @773777
     /*  773777 */     GIM_Try, /*On fail goto*//*Label 12360*/ GIMT_Encode4(773826), // Rule ID 13364 //
     /*  773782 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode4),
     /*  773785 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773789 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773793 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  773800 */       // (atomic_load_usub_cond:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  773800 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN),
     /*  773803 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773805 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  773810 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773812 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  773817 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  773820 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773824 */       GIR_RootConstrainSelectedInstOperands,
     /*  773825 */       // GIR_Coverage, 13364,
     /*  773825 */       GIR_EraseRootFromParent_Done,
     /*  773826 */     // Label 12360: @773826
     /*  773826 */     GIM_Reject,
     /*  773827 */   // Label 12348: @773827
     /*  773827 */   GIM_Try, /*On fail goto*//*Label 12361*/ GIMT_Encode4(773887), // Rule ID 11025 //
     /*  773832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HasFlatGVSMode),
     /*  773835 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  773843 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  773845 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  773856 */     // (atomic_load_usub_cond:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  773856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR),
     /*  773859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  773864 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  773871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  773876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  773881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773885 */     GIR_RootConstrainSelectedInstOperands,
     /*  773886 */     // GIR_Coverage, 11025,
     /*  773886 */     GIR_EraseRootFromParent_Done,
     /*  773887 */   // Label 12361: @773887
     /*  773887 */   GIM_Try, /*On fail goto*//*Label 12362*/ GIMT_Encode4(773946), // Rule ID 11581 //
     /*  773892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HasFlatGVSMode),
     /*  773895 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  773902 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  773904 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  773915 */     // (atomic_load_usub_cond:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  773915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR),
     /*  773918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  773923 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  773930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  773935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  773940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  773944 */     GIR_RootConstrainSelectedInstOperands,
     /*  773945 */     // GIR_Coverage, 11581,
     /*  773945 */     GIR_EraseRootFromParent_Done,
     /*  773946 */   // Label 12362: @773946
     /*  773946 */   GIM_Try, /*On fail goto*//*Label 12363*/ GIMT_Encode4(774010), // Rule ID 11019 //
     /*  773951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HasFlatGVSMode),
     /*  773954 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  773962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  773966 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  773970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  773977 */     // (atomic_load_usub_cond:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  773977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN),
     /*  773980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  773982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  773987 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  773989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  773994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  773999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  774004 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774008 */     GIR_RootConstrainSelectedInstOperands,
     /*  774009 */     // GIR_Coverage, 11019,
     /*  774009 */     GIR_EraseRootFromParent_Done,
     /*  774010 */   // Label 12363: @774010
     /*  774010 */   GIM_Try, /*On fail goto*//*Label 12364*/ GIMT_Encode4(774073), // Rule ID 11575 //
     /*  774015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HasFlatGVSMode),
     /*  774018 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  774025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  774029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  774033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  774040 */     // (atomic_load_usub_cond:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  774040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_SADDR_RTN),
     /*  774043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  774050 */     GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  774057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  774062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  774067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774071 */     GIR_RootConstrainSelectedInstOperands,
     /*  774072 */     // GIR_Coverage, 11575,
     /*  774072 */     GIR_EraseRootFromParent_Done,
     /*  774073 */   // Label 12364: @774073
     /*  774073 */   GIM_Try, /*On fail goto*//*Label 12365*/ GIMT_Encode4(774288),
     /*  774078 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  774086 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  774088 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  774092 */     GIM_Try, /*On fail goto*//*Label 12366*/ GIMT_Encode4(774131), // Rule ID 11020 //
     /*  774097 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode0),
     /*  774100 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774107 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774107 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774110 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774115 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774117 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774122 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774125 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774129 */       GIR_RootConstrainSelectedInstOperands,
     /*  774130 */       // GIR_Coverage, 11020,
     /*  774130 */       GIR_EraseRootFromParent_Done,
     /*  774131 */     // Label 12366: @774131
     /*  774131 */     GIM_Try, /*On fail goto*//*Label 12367*/ GIMT_Encode4(774170), // Rule ID 11021 //
     /*  774136 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode1),
     /*  774139 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774146 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774146 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774149 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774154 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774156 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774161 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774164 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774168 */       GIR_RootConstrainSelectedInstOperands,
     /*  774169 */       // GIR_Coverage, 11021,
     /*  774169 */       GIR_EraseRootFromParent_Done,
     /*  774170 */     // Label 12367: @774170
     /*  774170 */     GIM_Try, /*On fail goto*//*Label 12368*/ GIMT_Encode4(774209), // Rule ID 11022 //
     /*  774175 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode2),
     /*  774178 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774185 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774185 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774188 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774193 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774195 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774200 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774203 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774207 */       GIR_RootConstrainSelectedInstOperands,
     /*  774208 */       // GIR_Coverage, 11022,
     /*  774208 */       GIR_EraseRootFromParent_Done,
     /*  774209 */     // Label 12368: @774209
     /*  774209 */     GIM_Try, /*On fail goto*//*Label 12369*/ GIMT_Encode4(774248), // Rule ID 11023 //
     /*  774214 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode3),
     /*  774217 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774224 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774224 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774227 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774232 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774234 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774239 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774242 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774246 */       GIR_RootConstrainSelectedInstOperands,
     /*  774247 */       // GIR_Coverage, 11023,
     /*  774247 */       GIR_EraseRootFromParent_Done,
     /*  774248 */     // Label 12369: @774248
     /*  774248 */     GIM_Try, /*On fail goto*//*Label 12370*/ GIMT_Encode4(774287), // Rule ID 11024 //
     /*  774253 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode4),
     /*  774256 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774263 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774263 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774266 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774271 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774273 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774278 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774281 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774285 */       GIR_RootConstrainSelectedInstOperands,
     /*  774286 */       // GIR_Coverage, 11024,
     /*  774286 */       GIR_EraseRootFromParent_Done,
     /*  774287 */     // Label 12370: @774287
     /*  774287 */     GIM_Reject,
     /*  774288 */   // Label 12365: @774288
     /*  774288 */   GIM_Try, /*On fail goto*//*Label 12371*/ GIMT_Encode4(774502),
     /*  774293 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  774300 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  774302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  774306 */     GIM_Try, /*On fail goto*//*Label 12372*/ GIMT_Encode4(774345), // Rule ID 11576 //
     /*  774311 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode0),
     /*  774314 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774321 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774321 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774324 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774329 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774331 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774336 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774339 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774343 */       GIR_RootConstrainSelectedInstOperands,
     /*  774344 */       // GIR_Coverage, 11576,
     /*  774344 */       GIR_EraseRootFromParent_Done,
     /*  774345 */     // Label 12372: @774345
     /*  774345 */     GIM_Try, /*On fail goto*//*Label 12373*/ GIMT_Encode4(774384), // Rule ID 11577 //
     /*  774350 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode1),
     /*  774353 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774360 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774360 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774363 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774368 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774370 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774375 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774378 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774382 */       GIR_RootConstrainSelectedInstOperands,
     /*  774383 */       // GIR_Coverage, 11577,
     /*  774383 */       GIR_EraseRootFromParent_Done,
     /*  774384 */     // Label 12373: @774384
     /*  774384 */     GIM_Try, /*On fail goto*//*Label 12374*/ GIMT_Encode4(774423), // Rule ID 11578 //
     /*  774389 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode2),
     /*  774392 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774399 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774399 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774402 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774407 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774409 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774414 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774417 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774421 */       GIR_RootConstrainSelectedInstOperands,
     /*  774422 */       // GIR_Coverage, 11578,
     /*  774422 */       GIR_EraseRootFromParent_Done,
     /*  774423 */     // Label 12374: @774423
     /*  774423 */     GIM_Try, /*On fail goto*//*Label 12375*/ GIMT_Encode4(774462), // Rule ID 11579 //
     /*  774428 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode3),
     /*  774431 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774438 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774438 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774441 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774446 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774448 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774453 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774456 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774460 */       GIR_RootConstrainSelectedInstOperands,
     /*  774461 */       // GIR_Coverage, 11579,
     /*  774461 */       GIR_EraseRootFromParent_Done,
     /*  774462 */     // Label 12375: @774462
     /*  774462 */     GIM_Try, /*On fail goto*//*Label 12376*/ GIMT_Encode4(774501), // Rule ID 11580 //
     /*  774467 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode4),
     /*  774470 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774477 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_noret_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774477 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
     /*  774480 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774485 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774487 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774492 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  774495 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774499 */       GIR_RootConstrainSelectedInstOperands,
     /*  774500 */       // GIR_Coverage, 11580,
     /*  774500 */       GIR_EraseRootFromParent_Done,
     /*  774501 */     // Label 12376: @774501
     /*  774501 */     GIM_Reject,
     /*  774502 */   // Label 12371: @774502
     /*  774502 */   GIM_Try, /*On fail goto*//*Label 12377*/ GIMT_Encode4(774729),
     /*  774507 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  774515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  774519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  774523 */     GIM_Try, /*On fail goto*//*Label 12378*/ GIMT_Encode4(774564), // Rule ID 11014 //
     /*  774528 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode0),
     /*  774531 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774538 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774538 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774541 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774543 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774548 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774550 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774555 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774558 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774562 */       GIR_RootConstrainSelectedInstOperands,
     /*  774563 */       // GIR_Coverage, 11014,
     /*  774563 */       GIR_EraseRootFromParent_Done,
     /*  774564 */     // Label 12378: @774564
     /*  774564 */     GIM_Try, /*On fail goto*//*Label 12379*/ GIMT_Encode4(774605), // Rule ID 11015 //
     /*  774569 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode1),
     /*  774572 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774579 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774579 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774582 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774584 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774589 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774591 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774596 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774599 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774603 */       GIR_RootConstrainSelectedInstOperands,
     /*  774604 */       // GIR_Coverage, 11015,
     /*  774604 */       GIR_EraseRootFromParent_Done,
     /*  774605 */     // Label 12379: @774605
     /*  774605 */     GIM_Try, /*On fail goto*//*Label 12380*/ GIMT_Encode4(774646), // Rule ID 11016 //
     /*  774610 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode2),
     /*  774613 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774620 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774620 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774623 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774625 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774630 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774632 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774637 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774640 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774644 */       GIR_RootConstrainSelectedInstOperands,
     /*  774645 */       // GIR_Coverage, 11016,
     /*  774645 */       GIR_EraseRootFromParent_Done,
     /*  774646 */     // Label 12380: @774646
     /*  774646 */     GIM_Try, /*On fail goto*//*Label 12381*/ GIMT_Encode4(774687), // Rule ID 11017 //
     /*  774651 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode3),
     /*  774654 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774661 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774661 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774664 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774666 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774671 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774673 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774678 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774681 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774685 */       GIR_RootConstrainSelectedInstOperands,
     /*  774686 */       // GIR_Coverage, 11017,
     /*  774686 */       GIR_EraseRootFromParent_Done,
     /*  774687 */     // Label 12381: @774687
     /*  774687 */     GIM_Try, /*On fail goto*//*Label 12382*/ GIMT_Encode4(774728), // Rule ID 11018 //
     /*  774692 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode4),
     /*  774695 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774702 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_flat_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774702 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774705 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774707 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774712 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774714 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774719 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774722 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774726 */       GIR_RootConstrainSelectedInstOperands,
     /*  774727 */       // GIR_Coverage, 11018,
     /*  774727 */       GIR_EraseRootFromParent_Done,
     /*  774728 */     // Label 12382: @774728
     /*  774728 */     GIM_Reject,
     /*  774729 */   // Label 12377: @774729
     /*  774729 */   GIM_Try, /*On fail goto*//*Label 12383*/ GIMT_Encode4(774955),
     /*  774734 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  774741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  774745 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  774749 */     GIM_Try, /*On fail goto*//*Label 12384*/ GIMT_Encode4(774790), // Rule ID 11570 //
     /*  774754 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode0),
     /*  774757 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774764 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774764 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774767 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774769 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774774 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774776 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774781 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774784 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774788 */       GIR_RootConstrainSelectedInstOperands,
     /*  774789 */       // GIR_Coverage, 11570,
     /*  774789 */       GIR_EraseRootFromParent_Done,
     /*  774790 */     // Label 12384: @774790
     /*  774790 */     GIM_Try, /*On fail goto*//*Label 12385*/ GIMT_Encode4(774831), // Rule ID 11571 //
     /*  774795 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode1),
     /*  774798 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774805 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774805 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774808 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774810 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774815 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774817 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774822 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774825 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774829 */       GIR_RootConstrainSelectedInstOperands,
     /*  774830 */       // GIR_Coverage, 11571,
     /*  774830 */       GIR_EraseRootFromParent_Done,
     /*  774831 */     // Label 12385: @774831
     /*  774831 */     GIM_Try, /*On fail goto*//*Label 12386*/ GIMT_Encode4(774872), // Rule ID 11572 //
     /*  774836 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode2),
     /*  774839 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774846 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774846 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774849 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774851 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774856 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774858 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774863 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774866 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774870 */       GIR_RootConstrainSelectedInstOperands,
     /*  774871 */       // GIR_Coverage, 11572,
     /*  774871 */       GIR_EraseRootFromParent_Done,
     /*  774872 */     // Label 12386: @774872
     /*  774872 */     GIM_Try, /*On fail goto*//*Label 12387*/ GIMT_Encode4(774913), // Rule ID 11573 //
     /*  774877 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode3),
     /*  774880 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774887 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774887 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774890 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774892 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774897 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774899 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774904 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774907 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774911 */       GIR_RootConstrainSelectedInstOperands,
     /*  774912 */       // GIR_Coverage, 11573,
     /*  774912 */       GIR_EraseRootFromParent_Done,
     /*  774913 */     // Label 12387: @774913
     /*  774913 */     GIM_Try, /*On fail goto*//*Label 12388*/ GIMT_Encode4(774954), // Rule ID 11574 //
     /*  774918 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCondSubClampFlatInsts_HwMode4),
     /*  774921 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  774928 */       // (atomic_load_usub_cond:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_cond_global_i32>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  774928 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
     /*  774931 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  774933 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  774938 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  774940 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  774945 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  774948 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  774952 */       GIR_RootConstrainSelectedInstOperands,
     /*  774953 */       // GIR_Coverage, 11574,
     /*  774953 */       GIR_EraseRootFromParent_Done,
     /*  774954 */     // Label 12388: @774954
     /*  774954 */     GIM_Reject,
     /*  774955 */   // Label 12383: @774955
     /*  774955 */   GIM_Reject,
     /*  774956 */ // Label 12340: @774956
     /*  774956 */ GIM_Reject,
     /*  774957 */ // Label 35: @774957
     /*  774957 */ GIM_Try, /*On fail goto*//*Label 12389*/ GIMT_Encode4(775845),
     /*  774962 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  774965 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  774968 */   GIM_Try, /*On fail goto*//*Label 12390*/ GIMT_Encode4(775253),
     /*  774973 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
     /*  774978 */     GIM_Try, /*On fail goto*//*Label 12391*/ GIMT_Encode4(775023), // Rule ID 30522 //
     /*  774983 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode0),
     /*  774986 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  774988 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  774992 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  774999 */       // (atomic_load_usub_sat:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_sat_local_noret_i32>>  =>  (DS_SUB_CLAMP_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  774999 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_CLAMP_U32),
     /*  775002 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  775007 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  775009 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775014 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775017 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775021 */       GIR_RootConstrainSelectedInstOperands,
     /*  775022 */       // GIR_Coverage, 30522,
     /*  775022 */       GIR_EraseRootFromParent_Done,
     /*  775023 */     // Label 12391: @775023
     /*  775023 */     GIM_Try, /*On fail goto*//*Label 12392*/ GIMT_Encode4(775068), // Rule ID 30523 //
     /*  775028 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode1),
     /*  775031 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775033 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775037 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  775044 */       // (atomic_load_usub_sat:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_sat_local_noret_i32>>  =>  (DS_SUB_CLAMP_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  775044 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_CLAMP_U32),
     /*  775047 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  775052 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  775054 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775059 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775062 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775066 */       GIR_RootConstrainSelectedInstOperands,
     /*  775067 */       // GIR_Coverage, 30523,
     /*  775067 */       GIR_EraseRootFromParent_Done,
     /*  775068 */     // Label 12392: @775068
     /*  775068 */     GIM_Try, /*On fail goto*//*Label 12393*/ GIMT_Encode4(775113), // Rule ID 30524 //
     /*  775073 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode2),
     /*  775076 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775078 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775082 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  775089 */       // (atomic_load_usub_sat:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_sat_local_noret_i32>>  =>  (DS_SUB_CLAMP_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  775089 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_CLAMP_U32),
     /*  775092 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  775097 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  775099 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775104 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775107 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775111 */       GIR_RootConstrainSelectedInstOperands,
     /*  775112 */       // GIR_Coverage, 30524,
     /*  775112 */       GIR_EraseRootFromParent_Done,
     /*  775113 */     // Label 12393: @775113
     /*  775113 */     GIM_Try, /*On fail goto*//*Label 12394*/ GIMT_Encode4(775158), // Rule ID 30525 //
     /*  775118 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode3),
     /*  775121 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775123 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775127 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  775134 */       // (atomic_load_usub_sat:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_sat_local_noret_i32>>  =>  (DS_SUB_CLAMP_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  775134 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_CLAMP_U32),
     /*  775137 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  775142 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  775144 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775149 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775152 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775156 */       GIR_RootConstrainSelectedInstOperands,
     /*  775157 */       // GIR_Coverage, 30525,
     /*  775157 */       GIR_EraseRootFromParent_Done,
     /*  775158 */     // Label 12394: @775158
     /*  775158 */     GIM_Try, /*On fail goto*//*Label 12395*/ GIMT_Encode4(775203), // Rule ID 30526 //
     /*  775163 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts_HwMode4),
     /*  775166 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775168 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775172 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  775179 */       // (atomic_load_usub_sat:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_sat_local_noret_i32>>  =>  (DS_SUB_CLAMP_U32 ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  775179 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_CLAMP_U32),
     /*  775182 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  775187 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  775189 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775194 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775197 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775201 */       GIR_RootConstrainSelectedInstOperands,
     /*  775202 */       // GIR_Coverage, 30526,
     /*  775202 */       GIR_EraseRootFromParent_Done,
     /*  775203 */     // Label 12395: @775203
     /*  775203 */     GIM_Try, /*On fail goto*//*Label 12396*/ GIMT_Encode4(775252), // Rule ID 30521 //
     /*  775208 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsCondSubClampInsts),
     /*  775211 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775215 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775219 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  775226 */       // (atomic_load_usub_sat:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_usub_sat_local_i32>>  =>  (DS_SUB_CLAMP_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15624:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  775226 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_CLAMP_RTN_U32),
     /*  775229 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775231 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  775236 */       GIR_RootToRootCopy, /*OpIdx*/2, // value
     /*  775238 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775243 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775246 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775250 */       GIR_RootConstrainSelectedInstOperands,
     /*  775251 */       // GIR_Coverage, 30521,
     /*  775251 */       GIR_EraseRootFromParent_Done,
     /*  775252 */     // Label 12396: @775252
     /*  775252 */     GIM_Reject,
     /*  775253 */   // Label 12390: @775253
     /*  775253 */   GIM_Try, /*On fail goto*//*Label 12397*/ GIMT_Encode4(775844),
     /*  775258 */     GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
     /*  775265 */     GIM_Try, /*On fail goto*//*Label 12398*/ GIMT_Encode4(775317), // Rule ID 13099 //
     /*  775270 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts),
     /*  775273 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775275 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775279 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  775286 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_noret_i32>>  =>  (GLOBAL_ATOMIC_CSUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  775286 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR),
     /*  775289 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  775294 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775296 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  775301 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  775306 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  775311 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775315 */       GIR_RootConstrainSelectedInstOperands,
     /*  775316 */       // GIR_Coverage, 13099,
     /*  775316 */       GIR_EraseRootFromParent_Done,
     /*  775317 */     // Label 12398: @775317
     /*  775317 */     GIM_Try, /*On fail goto*//*Label 12399*/ GIMT_Encode4(775373), // Rule ID 13093 //
     /*  775322 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding),
     /*  775325 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775329 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775333 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  775340 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_i32>>  =>  (GLOBAL_ATOMIC_CSUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  775340 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN),
     /*  775343 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775345 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  775350 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775352 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  775357 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  775362 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  775367 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775371 */       GIR_RootConstrainSelectedInstOperands,
     /*  775372 */       // GIR_Coverage, 13093,
     /*  775372 */       GIR_EraseRootFromParent_Done,
     /*  775373 */     // Label 12399: @775373
     /*  775373 */     GIM_Try, /*On fail goto*//*Label 12400*/ GIMT_Encode4(775418), // Rule ID 13094 //
     /*  775378 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_HwMode0),
     /*  775381 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775383 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775387 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775394 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_noret_i32>>  =>  (GLOBAL_ATOMIC_CSUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775394 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB),
     /*  775397 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775402 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775404 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775409 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775412 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775416 */       GIR_RootConstrainSelectedInstOperands,
     /*  775417 */       // GIR_Coverage, 13094,
     /*  775417 */       GIR_EraseRootFromParent_Done,
     /*  775418 */     // Label 12400: @775418
     /*  775418 */     GIM_Try, /*On fail goto*//*Label 12401*/ GIMT_Encode4(775463), // Rule ID 13095 //
     /*  775423 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_HwMode1),
     /*  775426 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775428 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775432 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775439 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_noret_i32>>  =>  (GLOBAL_ATOMIC_CSUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775439 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB),
     /*  775442 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775447 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775449 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775454 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775457 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775461 */       GIR_RootConstrainSelectedInstOperands,
     /*  775462 */       // GIR_Coverage, 13095,
     /*  775462 */       GIR_EraseRootFromParent_Done,
     /*  775463 */     // Label 12401: @775463
     /*  775463 */     GIM_Try, /*On fail goto*//*Label 12402*/ GIMT_Encode4(775508), // Rule ID 13096 //
     /*  775468 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_HwMode2),
     /*  775471 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775473 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775477 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775484 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_noret_i32>>  =>  (GLOBAL_ATOMIC_CSUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775484 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB),
     /*  775487 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775492 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775494 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775499 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775502 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775506 */       GIR_RootConstrainSelectedInstOperands,
     /*  775507 */       // GIR_Coverage, 13096,
     /*  775507 */       GIR_EraseRootFromParent_Done,
     /*  775508 */     // Label 12402: @775508
     /*  775508 */     GIM_Try, /*On fail goto*//*Label 12403*/ GIMT_Encode4(775553), // Rule ID 13097 //
     /*  775513 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_HwMode3),
     /*  775516 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775518 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775522 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775529 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_noret_i32>>  =>  (GLOBAL_ATOMIC_CSUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775529 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB),
     /*  775532 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775537 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775539 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775544 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775547 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775551 */       GIR_RootConstrainSelectedInstOperands,
     /*  775552 */       // GIR_Coverage, 13097,
     /*  775552 */       GIR_EraseRootFromParent_Done,
     /*  775553 */     // Label 12403: @775553
     /*  775553 */     GIM_Try, /*On fail goto*//*Label 12404*/ GIMT_Encode4(775598), // Rule ID 13098 //
     /*  775558 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_HwMode4),
     /*  775561 */       GIM_CheckHasNoUse, /*MI*/0,
     /*  775563 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775567 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775574 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_noret_i32>>  =>  (GLOBAL_ATOMIC_CSUB VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775574 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB),
     /*  775577 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775582 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775584 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775589 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  775592 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775596 */       GIR_RootConstrainSelectedInstOperands,
     /*  775597 */       // GIR_Coverage, 13098,
     /*  775597 */       GIR_EraseRootFromParent_Done,
     /*  775598 */     // Label 12404: @775598
     /*  775598 */     GIM_Try, /*On fail goto*//*Label 12405*/ GIMT_Encode4(775647), // Rule ID 13088 //
     /*  775603 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding_HwMode0),
     /*  775606 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775610 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775614 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775621 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_i32>>  =>  (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775621 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN),
     /*  775624 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775626 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775631 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775633 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775638 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  775641 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775645 */       GIR_RootConstrainSelectedInstOperands,
     /*  775646 */       // GIR_Coverage, 13088,
     /*  775646 */       GIR_EraseRootFromParent_Done,
     /*  775647 */     // Label 12405: @775647
     /*  775647 */     GIM_Try, /*On fail goto*//*Label 12406*/ GIMT_Encode4(775696), // Rule ID 13089 //
     /*  775652 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding_HwMode1),
     /*  775655 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775659 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775663 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775670 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_i32>>  =>  (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775670 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN),
     /*  775673 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775675 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775680 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775682 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775687 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  775690 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775694 */       GIR_RootConstrainSelectedInstOperands,
     /*  775695 */       // GIR_Coverage, 13089,
     /*  775695 */       GIR_EraseRootFromParent_Done,
     /*  775696 */     // Label 12406: @775696
     /*  775696 */     GIM_Try, /*On fail goto*//*Label 12407*/ GIMT_Encode4(775745), // Rule ID 13090 //
     /*  775701 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding_HwMode2),
     /*  775704 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775708 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775712 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775719 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_i32>>  =>  (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775719 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN),
     /*  775722 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775724 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775729 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775731 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775736 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  775739 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775743 */       GIR_RootConstrainSelectedInstOperands,
     /*  775744 */       // GIR_Coverage, 13090,
     /*  775744 */       GIR_EraseRootFromParent_Done,
     /*  775745 */     // Label 12407: @775745
     /*  775745 */     GIM_Try, /*On fail goto*//*Label 12408*/ GIMT_Encode4(775794), // Rule ID 13091 //
     /*  775750 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding_HwMode3),
     /*  775753 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775757 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775761 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775768 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_i32>>  =>  (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775768 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN),
     /*  775771 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775773 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775778 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775780 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775785 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  775788 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775792 */       GIR_RootConstrainSelectedInstOperands,
     /*  775793 */       // GIR_Coverage, 13091,
     /*  775793 */       GIR_EraseRootFromParent_Done,
     /*  775794 */     // Label 12408: @775794
     /*  775794 */     GIM_Try, /*On fail goto*//*Label 12409*/ GIMT_Encode4(775843), // Rule ID 13092 //
     /*  775799 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding_HwMode4),
     /*  775802 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  775806 */       GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  775810 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  775817 */       // (atomic_load_usub_sat:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_usub_sat_global_i32>>  =>  (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
     /*  775817 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN),
     /*  775820 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  775822 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  775827 */       GIR_RootToRootCopy, /*OpIdx*/2, // data
     /*  775829 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  775834 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  775837 */       GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775841 */       GIR_RootConstrainSelectedInstOperands,
     /*  775842 */       // GIR_Coverage, 13092,
     /*  775842 */       GIR_EraseRootFromParent_Done,
     /*  775843 */     // Label 12409: @775843
     /*  775843 */     GIM_Reject,
     /*  775844 */   // Label 12397: @775844
     /*  775844 */   GIM_Reject,
     /*  775845 */ // Label 12389: @775845
     /*  775845 */ GIM_Reject,
     /*  775846 */ // Label 36: @775846
     /*  775846 */ GIM_Try, /*On fail goto*//*Label 12410*/ GIMT_Encode4(775864), // Rule ID 4166 //
     /*  775851 */   // MIs[0] ordering
     /*  775851 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /*  775854 */   // MIs[0] scope
     /*  775854 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  775857 */   // (atomic_fence (timm:{ *:[i32] }):$ordering, (timm:{ *:[i32] }):$scope)  =>  (ATOMIC_FENCE (timm:{ *:[i32] }):$ordering, (timm:{ *:[i32] }):$scope)
     /*  775857 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::ATOMIC_FENCE),
     /*  775862 */   GIR_RootConstrainSelectedInstOperands,
     /*  775863 */   // GIR_Coverage, 4166,
     /*  775863 */   GIR_Done,
     /*  775864 */ // Label 12410: @775864
     /*  775864 */ GIM_Reject,
     /*  775865 */ // Label 37: @775865
     /*  775865 */ GIM_Try, /*On fail goto*//*Label 12411*/ GIMT_Encode4(775937), // Rule ID 15020 //
     /*  775870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts),
     /*  775873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  775877 */   // MIs[0] Operand 1
     /*  775877 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  775880 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  775885 */   // MIs[0] loc
     /*  775885 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  775888 */   // MIs[0] Operand 3
     /*  775888 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  775891 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  775896 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_flat),
     /*  775900 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  775907 */   // (prefetch (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  775907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8_SADDR),
     /*  775910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  775915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  775920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  775925 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  775931 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  775935 */   GIR_RootConstrainSelectedInstOperands,
     /*  775936 */   // GIR_Coverage, 15020,
     /*  775936 */   GIR_EraseRootFromParent_Done,
     /*  775937 */ // Label 12411: @775937
     /*  775937 */ GIM_Try, /*On fail goto*//*Label 12412*/ GIMT_Encode4(776009), // Rule ID 15026 //
     /*  775942 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts),
     /*  775945 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  775949 */   // MIs[0] Operand 1
     /*  775949 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  775952 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  775957 */   // MIs[0] loc
     /*  775957 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  775960 */   // MIs[0] Operand 3
     /*  775960 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  775963 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  775968 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_global),
     /*  775972 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  775979 */   // (prefetch (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  775979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8_SADDR),
     /*  775982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  775987 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  775992 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  775997 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776007 */   GIR_RootConstrainSelectedInstOperands,
     /*  776008 */   // GIR_Coverage, 15026,
     /*  776008 */   GIR_EraseRootFromParent_Done,
     /*  776009 */ // Label 12412: @776009
     /*  776009 */ GIM_Try, /*On fail goto*//*Label 12413*/ GIMT_Encode4(776071), // Rule ID 9285 //
     /*  776014 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  776018 */   // MIs[0] Operand 1
     /*  776018 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776021 */   // MIs[0] Operand 2
     /*  776021 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776024 */   // MIs[0] Operand 3
     /*  776024 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776027 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776032 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_prefetch),
     /*  776036 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  776043 */   // (prefetch (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
     /*  776043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  776046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  776051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776056 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  776062 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776065 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776069 */   GIR_RootConstrainSelectedInstOperands,
     /*  776070 */   // GIR_Coverage, 9285,
     /*  776070 */   GIR_EraseRootFromParent_Done,
     /*  776071 */ // Label 12413: @776071
     /*  776071 */ GIM_Try, /*On fail goto*//*Label 12414*/ GIMT_Encode4(776304),
     /*  776076 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_flat),
     /*  776080 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  776084 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776087 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776092 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776095 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776098 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776103 */   GIM_Try, /*On fail goto*//*Label 12415*/ GIMT_Encode4(776143), // Rule ID 15015 //
     /*  776108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode0),
     /*  776111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776118 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  776121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776131 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776137 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776141 */     GIR_RootConstrainSelectedInstOperands,
     /*  776142 */     // GIR_Coverage, 15015,
     /*  776142 */     GIR_EraseRootFromParent_Done,
     /*  776143 */   // Label 12415: @776143
     /*  776143 */   GIM_Try, /*On fail goto*//*Label 12416*/ GIMT_Encode4(776183), // Rule ID 15016 //
     /*  776148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode1),
     /*  776151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776158 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  776161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776171 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776177 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776181 */     GIR_RootConstrainSelectedInstOperands,
     /*  776182 */     // GIR_Coverage, 15016,
     /*  776182 */     GIR_EraseRootFromParent_Done,
     /*  776183 */   // Label 12416: @776183
     /*  776183 */   GIM_Try, /*On fail goto*//*Label 12417*/ GIMT_Encode4(776223), // Rule ID 15017 //
     /*  776188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode2),
     /*  776191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776198 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  776201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776217 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776221 */     GIR_RootConstrainSelectedInstOperands,
     /*  776222 */     // GIR_Coverage, 15017,
     /*  776222 */     GIR_EraseRootFromParent_Done,
     /*  776223 */   // Label 12417: @776223
     /*  776223 */   GIM_Try, /*On fail goto*//*Label 12418*/ GIMT_Encode4(776263), // Rule ID 15018 //
     /*  776228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode3),
     /*  776231 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776238 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  776241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776251 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776261 */     GIR_RootConstrainSelectedInstOperands,
     /*  776262 */     // GIR_Coverage, 15018,
     /*  776262 */     GIR_EraseRootFromParent_Done,
     /*  776263 */   // Label 12418: @776263
     /*  776263 */   GIM_Try, /*On fail goto*//*Label 12419*/ GIMT_Encode4(776303), // Rule ID 15019 //
     /*  776268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode4),
     /*  776271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776278 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  776281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776291 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776301 */     GIR_RootConstrainSelectedInstOperands,
     /*  776302 */     // GIR_Coverage, 15019,
     /*  776302 */     GIR_EraseRootFromParent_Done,
     /*  776303 */   // Label 12419: @776303
     /*  776303 */   GIM_Reject,
     /*  776304 */ // Label 12414: @776304
     /*  776304 */ GIM_Try, /*On fail goto*//*Label 12420*/ GIMT_Encode4(776537),
     /*  776309 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_global),
     /*  776313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  776317 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776320 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776325 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776328 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776331 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776336 */   GIM_Try, /*On fail goto*//*Label 12421*/ GIMT_Encode4(776376), // Rule ID 15021 //
     /*  776341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode0),
     /*  776344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776351 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  776354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776364 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776374 */     GIR_RootConstrainSelectedInstOperands,
     /*  776375 */     // GIR_Coverage, 15021,
     /*  776375 */     GIR_EraseRootFromParent_Done,
     /*  776376 */   // Label 12421: @776376
     /*  776376 */   GIM_Try, /*On fail goto*//*Label 12422*/ GIMT_Encode4(776416), // Rule ID 15022 //
     /*  776381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode1),
     /*  776384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776391 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  776394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776404 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776414 */     GIR_RootConstrainSelectedInstOperands,
     /*  776415 */     // GIR_Coverage, 15022,
     /*  776415 */     GIR_EraseRootFromParent_Done,
     /*  776416 */   // Label 12422: @776416
     /*  776416 */   GIM_Try, /*On fail goto*//*Label 12423*/ GIMT_Encode4(776456), // Rule ID 15023 //
     /*  776421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode2),
     /*  776424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776431 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  776434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776444 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776454 */     GIR_RootConstrainSelectedInstOperands,
     /*  776455 */     // GIR_Coverage, 15023,
     /*  776455 */     GIR_EraseRootFromParent_Done,
     /*  776456 */   // Label 12423: @776456
     /*  776456 */   GIM_Try, /*On fail goto*//*Label 12424*/ GIMT_Encode4(776496), // Rule ID 15024 //
     /*  776461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode3),
     /*  776464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776471 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  776474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776484 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776490 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776494 */     GIR_RootConstrainSelectedInstOperands,
     /*  776495 */     // GIR_Coverage, 15024,
     /*  776495 */     GIR_EraseRootFromParent_Done,
     /*  776496 */   // Label 12424: @776496
     /*  776496 */   GIM_Try, /*On fail goto*//*Label 12425*/ GIMT_Encode4(776536), // Rule ID 15025 //
     /*  776501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode4),
     /*  776504 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  776511 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  776514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  776519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776524 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776534 */     GIR_RootConstrainSelectedInstOperands,
     /*  776535 */     // GIR_Coverage, 15025,
     /*  776535 */     GIR_EraseRootFromParent_Done,
     /*  776536 */   // Label 12425: @776536
     /*  776536 */   GIM_Reject,
     /*  776537 */ // Label 12420: @776537
     /*  776537 */ GIM_Try, /*On fail goto*//*Label 12426*/ GIMT_Encode4(776763),
     /*  776542 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_prefetch),
     /*  776546 */   GIM_Try, /*On fail goto*//*Label 12427*/ GIMT_Encode4(776596), // Rule ID 9286 //
     /*  776551 */     // MIs[0] sbase
     /*  776551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
     /*  776555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  776559 */     // MIs[0] Operand 1
     /*  776559 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776562 */     // MIs[0] Operand 2
     /*  776562 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776565 */     // MIs[0] Operand 3
     /*  776565 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776568 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776573 */     // (prefetch SReg_64:{ *:[i64] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
     /*  776573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  776576 */     GIR_RootToRootCopy, /*OpIdx*/0, // sbase
     /*  776578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776581 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  776587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776594 */     GIR_RootConstrainSelectedInstOperands,
     /*  776595 */     // GIR_Coverage, 9286,
     /*  776595 */     GIR_EraseRootFromParent_Done,
     /*  776596 */   // Label 12427: @776596
     /*  776596 */   GIM_Try, /*On fail goto*//*Label 12428*/ GIMT_Encode4(776704), // Rule ID 9287 //
     /*  776601 */     // MIs[0] sbase
     /*  776601 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
     /*  776605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  776609 */     // MIs[0] Operand 1
     /*  776609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776612 */     // MIs[0] Operand 2
     /*  776612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776615 */     // MIs[0] Operand 3
     /*  776615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776618 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776623 */     // (prefetch SReg_32:{ *:[i32] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_DATA (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$sbase, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i32] } 0:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
     /*  776623 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  776626 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  776630 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  776635 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  776638 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  776640 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  776643 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  776647 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  776652 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // sbase
     /*  776656 */     GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
     /*  776659 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  776662 */     GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
     /*  776665 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  776670 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  776675 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  776680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  776683 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  776686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776689 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  776695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776698 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776702 */     GIR_RootConstrainSelectedInstOperands,
     /*  776703 */     // GIR_Coverage, 9287,
     /*  776703 */     GIR_EraseRootFromParent_Done,
     /*  776704 */   // Label 12428: @776704
     /*  776704 */   GIM_Try, /*On fail goto*//*Label 12429*/ GIMT_Encode4(776762), // Rule ID 9282 //
     /*  776709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  776713 */     // MIs[0] Operand 1
     /*  776713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776716 */     // MIs[0] Operand 2
     /*  776716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776719 */     // MIs[0] Operand 3
     /*  776719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776722 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  776727 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  776734 */     // (prefetch (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_INST ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
     /*  776734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST),
     /*  776737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  776742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  776747 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  776753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776760 */     GIR_RootConstrainSelectedInstOperands,
     /*  776761 */     // GIR_Coverage, 9282,
     /*  776761 */     GIR_EraseRootFromParent_Done,
     /*  776762 */   // Label 12429: @776762
     /*  776762 */   GIM_Reject,
     /*  776763 */ // Label 12426: @776763
     /*  776763 */ GIM_Try, /*On fail goto*//*Label 12430*/ GIMT_Encode4(776835), // Rule ID 15002 //
     /*  776768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts),
     /*  776771 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  776775 */   // MIs[0] Operand 1
     /*  776775 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776778 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  776783 */   // MIs[0] loc
     /*  776783 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776786 */   // MIs[0] Operand 3
     /*  776786 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776789 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776794 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_flat),
     /*  776798 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  776805 */   // (prefetch (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8_SADDR),
     /*  776808 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  776813 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  776818 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  776823 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776829 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776833 */   GIR_RootConstrainSelectedInstOperands,
     /*  776834 */   // GIR_Coverage, 15002,
     /*  776834 */   GIR_EraseRootFromParent_Done,
     /*  776835 */ // Label 12430: @776835
     /*  776835 */ GIM_Try, /*On fail goto*//*Label 12431*/ GIMT_Encode4(776907), // Rule ID 15014 //
     /*  776840 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts),
     /*  776843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  776847 */   // MIs[0] Operand 1
     /*  776847 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776850 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  776855 */   // MIs[0] loc
     /*  776855 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776858 */   // MIs[0] Operand 3
     /*  776858 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776861 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  776866 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_global),
     /*  776870 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  776877 */   // (prefetch (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  776877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8_SADDR),
     /*  776880 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  776885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  776890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  776895 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  776901 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776905 */   GIR_RootConstrainSelectedInstOperands,
     /*  776906 */   // GIR_Coverage, 15014,
     /*  776906 */   GIR_EraseRootFromParent_Done,
     /*  776907 */ // Label 12431: @776907
     /*  776907 */ GIM_Try, /*On fail goto*//*Label 12432*/ GIMT_Encode4(777075),
     /*  776912 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_prefetch),
     /*  776916 */   GIM_Try, /*On fail goto*//*Label 12433*/ GIMT_Encode4(776966), // Rule ID 9283 //
     /*  776921 */     // MIs[0] sbase
     /*  776921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
     /*  776925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  776929 */     // MIs[0] Operand 1
     /*  776929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776932 */     // MIs[0] Operand 2
     /*  776932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776935 */     // MIs[0] Operand 3
     /*  776935 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776938 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  776943 */     // (prefetch SReg_64:{ *:[i64] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_INST ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
     /*  776943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST),
     /*  776946 */     GIR_RootToRootCopy, /*OpIdx*/0, // sbase
     /*  776948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776951 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  776957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  776960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  776964 */     GIR_RootConstrainSelectedInstOperands,
     /*  776965 */     // GIR_Coverage, 9283,
     /*  776965 */     GIR_EraseRootFromParent_Done,
     /*  776966 */   // Label 12433: @776966
     /*  776966 */   GIM_Try, /*On fail goto*//*Label 12434*/ GIMT_Encode4(777074), // Rule ID 9284 //
     /*  776971 */     // MIs[0] sbase
     /*  776971 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
     /*  776975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  776979 */     // MIs[0] Operand 1
     /*  776979 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  776982 */     // MIs[0] Operand 2
     /*  776982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  776985 */     // MIs[0] Operand 3
     /*  776985 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  776988 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  776993 */     // (prefetch SReg_32:{ *:[i32] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_INST (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$sbase, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i32] } 0:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
     /*  776993 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  776996 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  777000 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  777005 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  777008 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  777010 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  777013 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  777017 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  777022 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // sbase
     /*  777026 */     GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
     /*  777029 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  777032 */     GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
     /*  777035 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777040 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  777045 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  777050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST),
     /*  777053 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  777056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  777059 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  777065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  777068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777072 */     GIR_RootConstrainSelectedInstOperands,
     /*  777073 */     // GIR_Coverage, 9284,
     /*  777073 */     GIR_EraseRootFromParent_Done,
     /*  777074 */   // Label 12434: @777074
     /*  777074 */   GIM_Reject,
     /*  777075 */ // Label 12432: @777075
     /*  777075 */ GIM_Try, /*On fail goto*//*Label 12435*/ GIMT_Encode4(777308),
     /*  777080 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_flat),
     /*  777084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  777088 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  777091 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  777096 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  777099 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  777102 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  777107 */   GIM_Try, /*On fail goto*//*Label 12436*/ GIMT_Encode4(777147), // Rule ID 14997 //
     /*  777112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode0),
     /*  777115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777122 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  777125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777135 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777145 */     GIR_RootConstrainSelectedInstOperands,
     /*  777146 */     // GIR_Coverage, 14997,
     /*  777146 */     GIR_EraseRootFromParent_Done,
     /*  777147 */   // Label 12436: @777147
     /*  777147 */   GIM_Try, /*On fail goto*//*Label 12437*/ GIMT_Encode4(777187), // Rule ID 14998 //
     /*  777152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode1),
     /*  777155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777162 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  777165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777175 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777185 */     GIR_RootConstrainSelectedInstOperands,
     /*  777186 */     // GIR_Coverage, 14998,
     /*  777186 */     GIR_EraseRootFromParent_Done,
     /*  777187 */   // Label 12437: @777187
     /*  777187 */   GIM_Try, /*On fail goto*//*Label 12438*/ GIMT_Encode4(777227), // Rule ID 14999 //
     /*  777192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode2),
     /*  777195 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777202 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  777205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777215 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777221 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777225 */     GIR_RootConstrainSelectedInstOperands,
     /*  777226 */     // GIR_Coverage, 14999,
     /*  777226 */     GIR_EraseRootFromParent_Done,
     /*  777227 */   // Label 12438: @777227
     /*  777227 */   GIM_Try, /*On fail goto*//*Label 12439*/ GIMT_Encode4(777267), // Rule ID 15000 //
     /*  777232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode3),
     /*  777235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777242 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  777245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777255 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777265 */     GIR_RootConstrainSelectedInstOperands,
     /*  777266 */     // GIR_Coverage, 15000,
     /*  777266 */     GIR_EraseRootFromParent_Done,
     /*  777267 */   // Label 12439: @777267
     /*  777267 */   GIM_Try, /*On fail goto*//*Label 12440*/ GIMT_Encode4(777307), // Rule ID 15001 //
     /*  777272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode4),
     /*  777275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777282 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_flat>>  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  777285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777295 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777305 */     GIR_RootConstrainSelectedInstOperands,
     /*  777306 */     // GIR_Coverage, 15001,
     /*  777306 */     GIR_EraseRootFromParent_Done,
     /*  777307 */   // Label 12440: @777307
     /*  777307 */   GIM_Reject,
     /*  777308 */ // Label 12435: @777308
     /*  777308 */ GIM_Try, /*On fail goto*//*Label 12441*/ GIMT_Encode4(777541),
     /*  777313 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_prefetch_global),
     /*  777317 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
     /*  777321 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  777324 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
     /*  777329 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  777332 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  777335 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
     /*  777340 */   GIM_Try, /*On fail goto*//*Label 12442*/ GIMT_Encode4(777380), // Rule ID 15009 //
     /*  777345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode0),
     /*  777348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777355 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  777358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777368 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777378 */     GIR_RootConstrainSelectedInstOperands,
     /*  777379 */     // GIR_Coverage, 15009,
     /*  777379 */     GIR_EraseRootFromParent_Done,
     /*  777380 */   // Label 12442: @777380
     /*  777380 */   GIM_Try, /*On fail goto*//*Label 12443*/ GIMT_Encode4(777420), // Rule ID 15010 //
     /*  777385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode1),
     /*  777388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777395 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  777398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777408 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777414 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777418 */     GIR_RootConstrainSelectedInstOperands,
     /*  777419 */     // GIR_Coverage, 15010,
     /*  777419 */     GIR_EraseRootFromParent_Done,
     /*  777420 */   // Label 12443: @777420
     /*  777420 */   GIM_Try, /*On fail goto*//*Label 12444*/ GIMT_Encode4(777460), // Rule ID 15011 //
     /*  777425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode2),
     /*  777428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777435 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  777438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777448 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777458 */     GIR_RootConstrainSelectedInstOperands,
     /*  777459 */     // GIR_Coverage, 15011,
     /*  777459 */     GIR_EraseRootFromParent_Done,
     /*  777460 */   // Label 12444: @777460
     /*  777460 */   GIM_Try, /*On fail goto*//*Label 12445*/ GIMT_Encode4(777500), // Rule ID 15012 //
     /*  777465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode3),
     /*  777468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777475 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  777478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777488 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777498 */     GIR_RootConstrainSelectedInstOperands,
     /*  777499 */     // GIR_Coverage, 15012,
     /*  777499 */     GIR_EraseRootFromParent_Done,
     /*  777500 */   // Label 12445: @777500
     /*  777500 */   GIM_Try, /*On fail goto*//*Label 12446*/ GIMT_Encode4(777540), // Rule ID 15013 //
     /*  777505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode4),
     /*  777508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  777515 */     // (prefetch (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>, (timm:{ *:[i32] }):$loc, (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_prefetch_global>>  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, (PrefetchLoc:{ *:[i32] } ?:{ *:[i32] }:$loc))
     /*  777515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  777518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  777523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  777528 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderPrefetchLoc), // loc
     /*  777534 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  777538 */     GIR_RootConstrainSelectedInstOperands,
     /*  777539 */     // GIR_Coverage, 15013,
     /*  777539 */     GIR_EraseRootFromParent_Done,
     /*  777540 */   // Label 12446: @777540
     /*  777540 */   GIM_Reject,
     /*  777541 */ // Label 12441: @777541
     /*  777541 */ GIM_Reject,
     /*  777542 */ // Label 38: @777542
     /*  777542 */ GIM_Try, /*On fail goto*//*Label 12447*/ GIMT_Encode4(777734),
     /*  777547 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     /*  777550 */   GIM_Try, /*On fail goto*//*Label 12448*/ GIMT_Encode4(777574), // Rule ID 20 //
     /*  777555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_getpc),
     /*  777560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  777563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777567 */     // (intrinsic_wo_chain:{ *:[i64] } 3442:{ *:[iPTR] })  =>  (S_GETPC_B64_pseudo:{ *:[i64] })
     /*  777567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETPC_B64_pseudo),
     /*  777570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  777572 */     GIR_RootConstrainSelectedInstOperands,
     /*  777573 */     // GIR_Coverage, 20,
     /*  777573 */     GIR_EraseRootFromParent_Done,
     /*  777574 */   // Label 12448: @777574
     /*  777574 */   GIM_Try, /*On fail goto*//*Label 12449*/ GIMT_Encode4(777598), // Rule ID 4240 //
     /*  777579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_groupstaticsize),
     /*  777584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  777587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  777591 */     // (intrinsic_wo_chain:{ *:[i32] } 2482:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
     /*  777591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GET_GROUPSTATICSIZE),
     /*  777594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  777596 */     GIR_RootConstrainSelectedInstOperands,
     /*  777597 */     // GIR_Coverage, 4240,
     /*  777597 */     GIR_EraseRootFromParent_Done,
     /*  777598 */   // Label 12449: @777598
     /*  777598 */   GIM_Try, /*On fail goto*//*Label 12450*/ GIMT_Encode4(777625), // Rule ID 4255 //
     /*  777603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  777606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live),
     /*  777611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  777614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777618 */     // (intrinsic_wo_chain:{ *:[i1] } 3359:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
     /*  777618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE),
     /*  777621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777623 */     GIR_RootConstrainSelectedInstOperands,
     /*  777624 */     // GIR_Coverage, 4255,
     /*  777624 */     GIR_EraseRootFromParent_Done,
     /*  777625 */   // Label 12450: @777625
     /*  777625 */   GIM_Try, /*On fail goto*//*Label 12451*/ GIMT_Encode4(777652), // Rule ID 4256 //
     /*  777630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  777633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live),
     /*  777638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  777641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777645 */     // (intrinsic_wo_chain:{ *:[i1] } 3359:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
     /*  777645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE),
     /*  777648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777650 */     GIR_RootConstrainSelectedInstOperands,
     /*  777651 */     // GIR_Coverage, 4256,
     /*  777651 */     GIR_EraseRootFromParent_Done,
     /*  777652 */   // Label 12451: @777652
     /*  777652 */   GIM_Try, /*On fail goto*//*Label 12452*/ GIMT_Encode4(777679), // Rule ID 4257 //
     /*  777657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  777660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live),
     /*  777665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  777668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777672 */     // (intrinsic_wo_chain:{ *:[i1] } 3359:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
     /*  777672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE),
     /*  777675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777677 */     GIR_RootConstrainSelectedInstOperands,
     /*  777678 */     // GIR_Coverage, 4257,
     /*  777678 */     GIR_EraseRootFromParent_Done,
     /*  777679 */   // Label 12452: @777679
     /*  777679 */   GIM_Try, /*On fail goto*//*Label 12453*/ GIMT_Encode4(777706), // Rule ID 4258 //
     /*  777684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  777687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live),
     /*  777692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  777695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777699 */     // (intrinsic_wo_chain:{ *:[i1] } 3359:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
     /*  777699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE),
     /*  777702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777704 */     GIR_RootConstrainSelectedInstOperands,
     /*  777705 */     // GIR_Coverage, 4258,
     /*  777705 */     GIR_EraseRootFromParent_Done,
     /*  777706 */   // Label 12453: @777706
     /*  777706 */   GIM_Try, /*On fail goto*//*Label 12454*/ GIMT_Encode4(777733), // Rule ID 4259 //
     /*  777711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  777714 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live),
     /*  777719 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  777722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  777726 */     // (intrinsic_wo_chain:{ *:[i1] } 3359:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
     /*  777726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE),
     /*  777729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777731 */     GIR_RootConstrainSelectedInstOperands,
     /*  777732 */     // GIR_Coverage, 4259,
     /*  777732 */     GIR_EraseRootFromParent_Done,
     /*  777733 */   // Label 12454: @777733
     /*  777733 */   GIM_Reject,
     /*  777734 */ // Label 12447: @777734
     /*  777734 */ GIM_Try, /*On fail goto*//*Label 12455*/ GIMT_Encode4(784192),
     /*  777739 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*  777742 */   GIM_Try, /*On fail goto*//*Label 12456*/ GIMT_Encode4(777824), // Rule ID 7521 //
     /*  777747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  777750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
     /*  777755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  777758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  777761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  777765 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29893),
     /*  777769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  777776 */     // (intrinsic_wo_chain:{ *:[f16] } 2441:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29893>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_EXP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
     /*  777776 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  777779 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F16_e64),
     /*  777783 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  777788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  777793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  777798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  777803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  777808 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  777810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  777813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777815 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  777818 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  777823 */     // GIR_Coverage, 7521,
     /*  777823 */     GIR_EraseRootFromParent_Done,
     /*  777824 */   // Label 12456: @777824
     /*  777824 */   GIM_Try, /*On fail goto*//*Label 12457*/ GIMT_Encode4(777906), // Rule ID 7523 //
     /*  777829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  777832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
     /*  777837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  777840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  777843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  777847 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29895),
     /*  777851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  777858 */     // (intrinsic_wo_chain:{ *:[f16] } 3275:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29895>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_LOG_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
     /*  777858 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  777861 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F16_e64),
     /*  777865 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  777870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  777875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  777880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  777885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  777890 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  777892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  777895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777897 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  777900 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  777905 */     // GIR_Coverage, 7523,
     /*  777905 */     GIR_EraseRootFromParent_Done,
     /*  777906 */   // Label 12457: @777906
     /*  777906 */   GIM_Try, /*On fail goto*//*Label 12458*/ GIMT_Encode4(777988), // Rule ID 7525 //
     /*  777911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  777914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  777919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  777922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  777925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  777929 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29887),
     /*  777933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  777940 */     // (intrinsic_wo_chain:{ *:[f16] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29887>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_RCP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
     /*  777940 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  777943 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RCP_F16_e64),
     /*  777947 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  777952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  777957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  777962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  777967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  777972 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  777974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  777977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  777979 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  777982 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  777987 */     // GIR_Coverage, 7525,
     /*  777987 */     GIR_EraseRootFromParent_Done,
     /*  777988 */   // Label 12458: @777988
     /*  777988 */   GIM_Try, /*On fail goto*//*Label 12459*/ GIMT_Encode4(778070), // Rule ID 7527 //
     /*  777993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  777996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  778001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  778004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  778007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778011 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29889),
     /*  778015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778022 */     // (intrinsic_wo_chain:{ *:[f16] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29889>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_RSQ_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
     /*  778022 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  778025 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RSQ_F16_e64),
     /*  778029 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  778034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778054 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  778056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  778059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  778061 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  778064 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778069 */     // GIR_Coverage, 7527,
     /*  778069 */     GIR_EraseRootFromParent_Done,
     /*  778070 */   // Label 12459: @778070
     /*  778070 */   GIM_Try, /*On fail goto*//*Label 12460*/ GIMT_Encode4(778152), // Rule ID 7530 //
     /*  778075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  778078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  778083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  778086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  778089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778093 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29891),
     /*  778097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778104 */     // (intrinsic_wo_chain:{ *:[f16] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29891>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_SQRT_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
     /*  778104 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  778107 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F16_e64),
     /*  778111 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  778116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778136 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  778138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  778141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  778143 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  778146 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778151 */     // GIR_Coverage, 7530,
     /*  778151 */     GIR_EraseRootFromParent_Done,
     /*  778152 */   // Label 12460: @778152
     /*  778152 */   GIM_Try, /*On fail goto*//*Label 12461*/ GIMT_Encode4(778185), // Rule ID 16 //
     /*  778157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sffbh),
     /*  778162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  778172 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20755),
     /*  778176 */     // (intrinsic_wo_chain:{ *:[i32] } 3488:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_20755>>  =>  (S_FLBIT_I32:{ *:[i32] } i32:{ *:[i32] }:$src0)
     /*  778176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32),
     /*  778179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  778181 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  778183 */     GIR_RootConstrainSelectedInstOperands,
     /*  778184 */     // GIR_Coverage, 16,
     /*  778184 */     GIR_EraseRootFromParent_Done,
     /*  778185 */   // Label 12461: @778185
     /*  778185 */   GIM_Try, /*On fail goto*//*Label 12462*/ GIMT_Encode4(778246), // Rule ID 3295 //
     /*  778190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  778193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
     /*  778198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778208 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29882),
     /*  778212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778219 */     // (intrinsic_wo_chain:{ *:[f32] } 2441:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29882>>  =>  (V_S_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F32_e64),
     /*  778222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778244 */     GIR_RootConstrainSelectedInstOperands,
     /*  778245 */     // GIR_Coverage, 3295,
     /*  778245 */     GIR_EraseRootFromParent_Done,
     /*  778246 */   // Label 12462: @778246
     /*  778246 */   GIM_Try, /*On fail goto*//*Label 12463*/ GIMT_Encode4(778307), // Rule ID 3297 //
     /*  778251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  778254 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
     /*  778259 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778262 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778269 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29885),
     /*  778273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778280 */     // (intrinsic_wo_chain:{ *:[f32] } 3275:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29885>>  =>  (V_S_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F32_e64),
     /*  778283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778305 */     GIR_RootConstrainSelectedInstOperands,
     /*  778306 */     // GIR_Coverage, 3297,
     /*  778306 */     GIR_EraseRootFromParent_Done,
     /*  778307 */   // Label 12463: @778307
     /*  778307 */   GIM_Try, /*On fail goto*//*Label 12464*/ GIMT_Encode4(778368), // Rule ID 3299 //
     /*  778312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  778315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  778320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778330 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29887),
     /*  778334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778341 */     // (intrinsic_wo_chain:{ *:[f32] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29887>>  =>  (V_S_RCP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RCP_F32_e64),
     /*  778344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778366 */     GIR_RootConstrainSelectedInstOperands,
     /*  778367 */     // GIR_Coverage, 3299,
     /*  778367 */     GIR_EraseRootFromParent_Done,
     /*  778368 */   // Label 12464: @778368
     /*  778368 */   GIM_Try, /*On fail goto*//*Label 12465*/ GIMT_Encode4(778429), // Rule ID 3301 //
     /*  778373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  778376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  778381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778391 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29889),
     /*  778395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778402 */     // (intrinsic_wo_chain:{ *:[f32] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29889>>  =>  (V_S_RSQ_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RSQ_F32_e64),
     /*  778405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778417 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778427 */     GIR_RootConstrainSelectedInstOperands,
     /*  778428 */     // GIR_Coverage, 3301,
     /*  778428 */     GIR_EraseRootFromParent_Done,
     /*  778429 */   // Label 12465: @778429
     /*  778429 */   GIM_Try, /*On fail goto*//*Label 12466*/ GIMT_Encode4(778490), // Rule ID 3304 //
     /*  778434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
     /*  778437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  778442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  778452 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_29891),
     /*  778456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778463 */     // (intrinsic_wo_chain:{ *:[f32] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_29891>>  =>  (V_S_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F32_e64),
     /*  778466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778488 */     GIR_RootConstrainSelectedInstOperands,
     /*  778489 */     // GIR_Coverage, 3304,
     /*  778489 */     GIR_EraseRootFromParent_Done,
     /*  778490 */   // Label 12466: @778490
     /*  778490 */   GIM_Try, /*On fail goto*//*Label 12467*/ GIMT_Encode4(778539), // Rule ID 2382 //
     /*  778495 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_off_f32_i4),
     /*  778500 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778503 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778510 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778517 */     // (intrinsic_wo_chain:{ *:[f32] } 2276:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_OFF_F32_I4_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_OFF_F32_I4_e64),
     /*  778520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
     /*  778532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
     /*  778537 */     GIR_RootConstrainSelectedInstOperands,
     /*  778538 */     // GIR_Coverage, 2382,
     /*  778538 */     GIR_EraseRootFromParent_Done,
     /*  778539 */   // Label 12467: @778539
     /*  778539 */   GIM_Try, /*On fail goto*//*Label 12468*/ GIMT_Encode4(778593), // Rule ID 2387 //
     /*  778544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  778549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778559 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778566 */     // (intrinsic_wo_chain:{ *:[f32] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F32_e64),
     /*  778569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778591 */     GIR_RootConstrainSelectedInstOperands,
     /*  778592 */     // GIR_Coverage, 2387,
     /*  778592 */     GIR_EraseRootFromParent_Done,
     /*  778593 */   // Label 12468: @778593
     /*  778593 */   GIM_Try, /*On fail goto*//*Label 12469*/ GIMT_Encode4(778647), // Rule ID 2393 //
     /*  778598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
     /*  778603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778620 */     // (intrinsic_wo_chain:{ *:[f32] } 2441:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F32_e64),
     /*  778623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778645 */     GIR_RootConstrainSelectedInstOperands,
     /*  778646 */     // GIR_Coverage, 2393,
     /*  778646 */     GIR_EraseRootFromParent_Done,
     /*  778647 */   // Label 12469: @778647
     /*  778647 */   GIM_Try, /*On fail goto*//*Label 12470*/ GIMT_Encode4(778701), // Rule ID 2395 //
     /*  778652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
     /*  778657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778674 */     // (intrinsic_wo_chain:{ *:[f32] } 3275:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F32_e64),
     /*  778677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778699 */     GIR_RootConstrainSelectedInstOperands,
     /*  778700 */     // GIR_Coverage, 2395,
     /*  778700 */     GIR_EraseRootFromParent_Done,
     /*  778701 */   // Label 12470: @778701
     /*  778701 */   GIM_Try, /*On fail goto*//*Label 12471*/ GIMT_Encode4(778755), // Rule ID 2397 //
     /*  778706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  778711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778728 */     // (intrinsic_wo_chain:{ *:[f32] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F32_e64),
     /*  778731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778753 */     GIR_RootConstrainSelectedInstOperands,
     /*  778754 */     // GIR_Coverage, 2397,
     /*  778754 */     GIR_EraseRootFromParent_Done,
     /*  778755 */   // Label 12471: @778755
     /*  778755 */   GIM_Try, /*On fail goto*//*Label 12472*/ GIMT_Encode4(778809), // Rule ID 2400 //
     /*  778760 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  778765 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778782 */     // (intrinsic_wo_chain:{ *:[f32] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F32_e64),
     /*  778785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778807 */     GIR_RootConstrainSelectedInstOperands,
     /*  778808 */     // GIR_Coverage, 2400,
     /*  778808 */     GIR_EraseRootFromParent_Done,
     /*  778809 */   // Label 12472: @778809
     /*  778809 */   GIM_Try, /*On fail goto*//*Label 12473*/ GIMT_Encode4(778863), // Rule ID 2402 //
     /*  778814 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  778819 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  778822 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  778825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  778829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778836 */     // (intrinsic_wo_chain:{ *:[f32] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F32_e64),
     /*  778839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778861 */     GIR_RootConstrainSelectedInstOperands,
     /*  778862 */     // GIR_Coverage, 2402,
     /*  778862 */     GIR_EraseRootFromParent_Done,
     /*  778863 */   // Label 12473: @778863
     /*  778863 */   GIM_Try, /*On fail goto*//*Label 12474*/ GIMT_Encode4(778920), // Rule ID 2403 //
     /*  778868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  778871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  778876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  778879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  778882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  778886 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778893 */     // (intrinsic_wo_chain:{ *:[f64] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64),
     /*  778896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778918 */     GIR_RootConstrainSelectedInstOperands,
     /*  778919 */     // GIR_Coverage, 2403,
     /*  778919 */     GIR_EraseRootFromParent_Done,
     /*  778920 */   // Label 12474: @778920
     /*  778920 */   GIM_Try, /*On fail goto*//*Label 12475*/ GIMT_Encode4(778977), // Rule ID 2404 //
     /*  778925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  778928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  778933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  778936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  778939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  778943 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  778950 */     // (intrinsic_wo_chain:{ *:[f64] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  778950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64),
     /*  778953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  778955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  778960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  778965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  778970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  778975 */     GIR_RootConstrainSelectedInstOperands,
     /*  778976 */     // GIR_Coverage, 2404,
     /*  778976 */     GIR_EraseRootFromParent_Done,
     /*  778977 */   // Label 12475: @778977
     /*  778977 */   GIM_Try, /*On fail goto*//*Label 12476*/ GIMT_Encode4(779034), // Rule ID 2405 //
     /*  778982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  778985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  778990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  778993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  778996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779000 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779007 */     // (intrinsic_wo_chain:{ *:[f64] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64),
     /*  779010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779012 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779032 */     GIR_RootConstrainSelectedInstOperands,
     /*  779033 */     // GIR_Coverage, 2405,
     /*  779033 */     GIR_EraseRootFromParent_Done,
     /*  779034 */   // Label 12476: @779034
     /*  779034 */   GIM_Try, /*On fail goto*//*Label 12477*/ GIMT_Encode4(779091), // Rule ID 2406 //
     /*  779039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  779042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  779047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779064 */     // (intrinsic_wo_chain:{ *:[f64] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64),
     /*  779067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779089 */     GIR_RootConstrainSelectedInstOperands,
     /*  779090 */     // GIR_Coverage, 2406,
     /*  779090 */     GIR_EraseRootFromParent_Done,
     /*  779091 */   // Label 12477: @779091
     /*  779091 */   GIM_Try, /*On fail goto*//*Label 12478*/ GIMT_Encode4(779148), // Rule ID 2407 //
     /*  779096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  779099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  779104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779121 */     // (intrinsic_wo_chain:{ *:[f64] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64),
     /*  779124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779136 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779146 */     GIR_RootConstrainSelectedInstOperands,
     /*  779147 */     // GIR_Coverage, 2407,
     /*  779147 */     GIR_EraseRootFromParent_Done,
     /*  779148 */   // Label 12478: @779148
     /*  779148 */   GIM_Try, /*On fail goto*//*Label 12479*/ GIMT_Encode4(779205), // Rule ID 2413 //
     /*  779153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  779156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  779161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779171 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779178 */     // (intrinsic_wo_chain:{ *:[f64] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64),
     /*  779181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779203 */     GIR_RootConstrainSelectedInstOperands,
     /*  779204 */     // GIR_Coverage, 2413,
     /*  779204 */     GIR_EraseRootFromParent_Done,
     /*  779205 */   // Label 12479: @779205
     /*  779205 */   GIM_Try, /*On fail goto*//*Label 12480*/ GIMT_Encode4(779262), // Rule ID 2414 //
     /*  779210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  779213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  779218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779221 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779235 */     // (intrinsic_wo_chain:{ *:[f64] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64),
     /*  779238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779260 */     GIR_RootConstrainSelectedInstOperands,
     /*  779261 */     // GIR_Coverage, 2414,
     /*  779261 */     GIR_EraseRootFromParent_Done,
     /*  779262 */   // Label 12480: @779262
     /*  779262 */   GIM_Try, /*On fail goto*//*Label 12481*/ GIMT_Encode4(779319), // Rule ID 2415 //
     /*  779267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  779270 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  779275 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779285 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779292 */     // (intrinsic_wo_chain:{ *:[f64] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64),
     /*  779295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779317 */     GIR_RootConstrainSelectedInstOperands,
     /*  779318 */     // GIR_Coverage, 2415,
     /*  779318 */     GIR_EraseRootFromParent_Done,
     /*  779319 */   // Label 12481: @779319
     /*  779319 */   GIM_Try, /*On fail goto*//*Label 12482*/ GIMT_Encode4(779376), // Rule ID 2416 //
     /*  779324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  779327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  779332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779349 */     // (intrinsic_wo_chain:{ *:[f64] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64),
     /*  779352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779374 */     GIR_RootConstrainSelectedInstOperands,
     /*  779375 */     // GIR_Coverage, 2416,
     /*  779375 */     GIR_EraseRootFromParent_Done,
     /*  779376 */   // Label 12482: @779376
     /*  779376 */   GIM_Try, /*On fail goto*//*Label 12483*/ GIMT_Encode4(779433), // Rule ID 2417 //
     /*  779381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  779384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  779389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779392 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779406 */     // (intrinsic_wo_chain:{ *:[f64] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64),
     /*  779409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779431 */     GIR_RootConstrainSelectedInstOperands,
     /*  779432 */     // GIR_Coverage, 2417,
     /*  779432 */     GIR_EraseRootFromParent_Done,
     /*  779433 */   // Label 12483: @779433
     /*  779433 */   GIM_Try, /*On fail goto*//*Label 12484*/ GIMT_Encode4(779490), // Rule ID 2423 //
     /*  779438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  779441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  779446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779463 */     // (intrinsic_wo_chain:{ *:[f64] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64),
     /*  779466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779488 */     GIR_RootConstrainSelectedInstOperands,
     /*  779489 */     // GIR_Coverage, 2423,
     /*  779489 */     GIR_EraseRootFromParent_Done,
     /*  779490 */   // Label 12484: @779490
     /*  779490 */   GIM_Try, /*On fail goto*//*Label 12485*/ GIMT_Encode4(779547), // Rule ID 2424 //
     /*  779495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  779498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  779503 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779506 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779520 */     // (intrinsic_wo_chain:{ *:[f64] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64),
     /*  779523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779545 */     GIR_RootConstrainSelectedInstOperands,
     /*  779546 */     // GIR_Coverage, 2424,
     /*  779546 */     GIR_EraseRootFromParent_Done,
     /*  779547 */   // Label 12485: @779547
     /*  779547 */   GIM_Try, /*On fail goto*//*Label 12486*/ GIMT_Encode4(779604), // Rule ID 2425 //
     /*  779552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  779555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  779560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779577 */     // (intrinsic_wo_chain:{ *:[f64] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64),
     /*  779580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779602 */     GIR_RootConstrainSelectedInstOperands,
     /*  779603 */     // GIR_Coverage, 2425,
     /*  779603 */     GIR_EraseRootFromParent_Done,
     /*  779604 */   // Label 12486: @779604
     /*  779604 */   GIM_Try, /*On fail goto*//*Label 12487*/ GIMT_Encode4(779661), // Rule ID 2426 //
     /*  779609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  779612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  779617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779627 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779634 */     // (intrinsic_wo_chain:{ *:[f64] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64),
     /*  779637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779659 */     GIR_RootConstrainSelectedInstOperands,
     /*  779660 */     // GIR_Coverage, 2426,
     /*  779660 */     GIR_EraseRootFromParent_Done,
     /*  779661 */   // Label 12487: @779661
     /*  779661 */   GIM_Try, /*On fail goto*//*Label 12488*/ GIMT_Encode4(779718), // Rule ID 2427 //
     /*  779666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  779669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  779674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  779677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  779684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779691 */     // (intrinsic_wo_chain:{ *:[f64] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64),
     /*  779694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779716 */     GIR_RootConstrainSelectedInstOperands,
     /*  779717 */     // GIR_Coverage, 2427,
     /*  779717 */     GIR_EraseRootFromParent_Done,
     /*  779718 */   // Label 12488: @779718
     /*  779718 */   GIM_Try, /*On fail goto*//*Label 12489*/ GIMT_Encode4(779772), // Rule ID 2428 //
     /*  779723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
     /*  779728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  779731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  779734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  779738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779745 */     // (intrinsic_wo_chain:{ *:[f32] } 3489:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F32_e64),
     /*  779748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779770 */     GIR_RootConstrainSelectedInstOperands,
     /*  779771 */     // GIR_Coverage, 2428,
     /*  779771 */     GIR_EraseRootFromParent_Done,
     /*  779772 */   // Label 12489: @779772
     /*  779772 */   GIM_Try, /*On fail goto*//*Label 12490*/ GIMT_Encode4(779826), // Rule ID 2430 //
     /*  779777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
     /*  779782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  779785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  779788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  779792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779799 */     // (intrinsic_wo_chain:{ *:[f32] } 2265:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F32_e64),
     /*  779802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779824 */     GIR_RootConstrainSelectedInstOperands,
     /*  779825 */     // GIR_Coverage, 2430,
     /*  779825 */     GIR_EraseRootFromParent_Done,
     /*  779826 */   // Label 12490: @779826
     /*  779826 */   GIM_Try, /*On fail goto*//*Label 12491*/ GIMT_Encode4(779883), // Rule ID 2432 //
     /*  779831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTanhInsts),
     /*  779834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_tanh),
     /*  779839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  779842 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  779845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  779849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779856 */     // (intrinsic_wo_chain:{ *:[f32] } 3601:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TANH_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TANH_F32_e64),
     /*  779859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779881 */     GIR_RootConstrainSelectedInstOperands,
     /*  779882 */     // GIR_Coverage, 2432,
     /*  779882 */     GIR_EraseRootFromParent_Done,
     /*  779883 */   // Label 12491: @779883
     /*  779883 */   GIM_Try, /*On fail goto*//*Label 12492*/ GIMT_Encode4(779922), // Rule ID 2438 //
     /*  779888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sffbh),
     /*  779893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  779896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  779899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  779903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779910 */     // (intrinsic_wo_chain:{ *:[i32] } 3488:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_FFBH_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
     /*  779910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_I32_e64),
     /*  779913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779920 */     GIR_RootConstrainSelectedInstOperands,
     /*  779921 */     // GIR_Coverage, 2438,
     /*  779921 */     GIR_EraseRootFromParent_Done,
     /*  779922 */   // Label 12492: @779922
     /*  779922 */   GIM_Try, /*On fail goto*//*Label 12493*/ GIMT_Encode4(779979), // Rule ID 2440 //
     /*  779927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  779930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  779935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  779938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  779945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  779952 */     // (intrinsic_wo_chain:{ *:[i32] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  779952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64),
     /*  779955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  779957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  779962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  779967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  779972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  779977 */     GIR_RootConstrainSelectedInstOperands,
     /*  779978 */     // GIR_Coverage, 2440,
     /*  779978 */     GIR_EraseRootFromParent_Done,
     /*  779979 */   // Label 12493: @779979
     /*  779979 */   GIM_Try, /*On fail goto*//*Label 12494*/ GIMT_Encode4(780036), // Rule ID 2441 //
     /*  779984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  779987 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  779992 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  779995 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  779998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780009 */     // (intrinsic_wo_chain:{ *:[i32] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64),
     /*  780012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780034 */     GIR_RootConstrainSelectedInstOperands,
     /*  780035 */     // GIR_Coverage, 2441,
     /*  780035 */     GIR_EraseRootFromParent_Done,
     /*  780036 */   // Label 12494: @780036
     /*  780036 */   GIM_Try, /*On fail goto*//*Label 12495*/ GIMT_Encode4(780093), // Rule ID 2442 //
     /*  780041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  780044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  780049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780066 */     // (intrinsic_wo_chain:{ *:[i32] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64),
     /*  780069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780091 */     GIR_RootConstrainSelectedInstOperands,
     /*  780092 */     // GIR_Coverage, 2442,
     /*  780092 */     GIR_EraseRootFromParent_Done,
     /*  780093 */   // Label 12495: @780093
     /*  780093 */   GIM_Try, /*On fail goto*//*Label 12496*/ GIMT_Encode4(780150), // Rule ID 2443 //
     /*  780098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  780101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  780106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780116 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780123 */     // (intrinsic_wo_chain:{ *:[i32] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64),
     /*  780126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780148 */     GIR_RootConstrainSelectedInstOperands,
     /*  780149 */     // GIR_Coverage, 2443,
     /*  780149 */     GIR_EraseRootFromParent_Done,
     /*  780150 */   // Label 12496: @780150
     /*  780150 */   GIM_Try, /*On fail goto*//*Label 12497*/ GIMT_Encode4(780207), // Rule ID 2444 //
     /*  780155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  780158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  780163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780180 */     // (intrinsic_wo_chain:{ *:[i32] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64),
     /*  780183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780205 */     GIR_RootConstrainSelectedInstOperands,
     /*  780206 */     // GIR_Coverage, 2444,
     /*  780206 */     GIR_EraseRootFromParent_Done,
     /*  780207 */   // Label 12497: @780207
     /*  780207 */   GIM_Try, /*On fail goto*//*Label 12498*/ GIMT_Encode4(780264), // Rule ID 2445 //
     /*  780212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  780215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  780220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780237 */     // (intrinsic_wo_chain:{ *:[f64] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64),
     /*  780240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780262 */     GIR_RootConstrainSelectedInstOperands,
     /*  780263 */     // GIR_Coverage, 2445,
     /*  780263 */     GIR_EraseRootFromParent_Done,
     /*  780264 */   // Label 12498: @780264
     /*  780264 */   GIM_Try, /*On fail goto*//*Label 12499*/ GIMT_Encode4(780321), // Rule ID 2446 //
     /*  780269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  780272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  780277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780294 */     // (intrinsic_wo_chain:{ *:[f64] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64),
     /*  780297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780319 */     GIR_RootConstrainSelectedInstOperands,
     /*  780320 */     // GIR_Coverage, 2446,
     /*  780320 */     GIR_EraseRootFromParent_Done,
     /*  780321 */   // Label 12499: @780321
     /*  780321 */   GIM_Try, /*On fail goto*//*Label 12500*/ GIMT_Encode4(780378), // Rule ID 2447 //
     /*  780326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  780329 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  780334 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780337 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780344 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780351 */     // (intrinsic_wo_chain:{ *:[f64] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64),
     /*  780354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780376 */     GIR_RootConstrainSelectedInstOperands,
     /*  780377 */     // GIR_Coverage, 2447,
     /*  780377 */     GIR_EraseRootFromParent_Done,
     /*  780378 */   // Label 12500: @780378
     /*  780378 */   GIM_Try, /*On fail goto*//*Label 12501*/ GIMT_Encode4(780435), // Rule ID 2448 //
     /*  780383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  780386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  780391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780401 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780408 */     // (intrinsic_wo_chain:{ *:[f64] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64),
     /*  780411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780433 */     GIR_RootConstrainSelectedInstOperands,
     /*  780434 */     // GIR_Coverage, 2448,
     /*  780434 */     GIR_EraseRootFromParent_Done,
     /*  780435 */   // Label 12501: @780435
     /*  780435 */   GIM_Try, /*On fail goto*//*Label 12502*/ GIMT_Encode4(780492), // Rule ID 2449 //
     /*  780440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  780443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  780448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780465 */     // (intrinsic_wo_chain:{ *:[f64] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64),
     /*  780468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780490 */     GIR_RootConstrainSelectedInstOperands,
     /*  780491 */     // GIR_Coverage, 2449,
     /*  780491 */     GIR_EraseRootFromParent_Done,
     /*  780492 */   // Label 12502: @780492
     /*  780492 */   GIM_Try, /*On fail goto*//*Label 12503*/ GIMT_Encode4(780549), // Rule ID 2450 //
     /*  780497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  780500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  780505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780522 */     // (intrinsic_wo_chain:{ *:[f64] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
     /*  780525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780547 */     GIR_RootConstrainSelectedInstOperands,
     /*  780548 */     // GIR_Coverage, 2450,
     /*  780548 */     GIR_EraseRootFromParent_Done,
     /*  780549 */   // Label 12503: @780549
     /*  780549 */   GIM_Try, /*On fail goto*//*Label 12504*/ GIMT_Encode4(780606), // Rule ID 2451 //
     /*  780554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  780557 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  780562 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780565 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780579 */     // (intrinsic_wo_chain:{ *:[f64] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
     /*  780582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780604 */     GIR_RootConstrainSelectedInstOperands,
     /*  780605 */     // GIR_Coverage, 2451,
     /*  780605 */     GIR_EraseRootFromParent_Done,
     /*  780606 */   // Label 12504: @780606
     /*  780606 */   GIM_Try, /*On fail goto*//*Label 12505*/ GIMT_Encode4(780663), // Rule ID 2452 //
     /*  780611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  780614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  780619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780636 */     // (intrinsic_wo_chain:{ *:[f64] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
     /*  780639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780661 */     GIR_RootConstrainSelectedInstOperands,
     /*  780662 */     // GIR_Coverage, 2452,
     /*  780662 */     GIR_EraseRootFromParent_Done,
     /*  780663 */   // Label 12505: @780663
     /*  780663 */   GIM_Try, /*On fail goto*//*Label 12506*/ GIMT_Encode4(780720), // Rule ID 2453 //
     /*  780668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  780671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  780676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780693 */     // (intrinsic_wo_chain:{ *:[f64] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
     /*  780696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780718 */     GIR_RootConstrainSelectedInstOperands,
     /*  780719 */     // GIR_Coverage, 2453,
     /*  780719 */     GIR_EraseRootFromParent_Done,
     /*  780720 */   // Label 12506: @780720
     /*  780720 */   GIM_Try, /*On fail goto*//*Label 12507*/ GIMT_Encode4(780777), // Rule ID 2454 //
     /*  780725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  780728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  780733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  780736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  780739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  780743 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780750 */     // (intrinsic_wo_chain:{ *:[f64] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
     /*  780753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780775 */     GIR_RootConstrainSelectedInstOperands,
     /*  780776 */     // GIR_Coverage, 2454,
     /*  780776 */     GIR_EraseRootFromParent_Done,
     /*  780777 */   // Label 12507: @780777
     /*  780777 */   GIM_Try, /*On fail goto*//*Label 12508*/ GIMT_Encode4(780826), // Rule ID 2460 //
     /*  780782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  780787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  780793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780804 */     // (intrinsic_wo_chain:{ *:[i32] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)
     /*  780804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F32_e64),
     /*  780807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780824 */     GIR_RootConstrainSelectedInstOperands,
     /*  780825 */     // GIR_Coverage, 2460,
     /*  780825 */     GIR_EraseRootFromParent_Done,
     /*  780826 */   // Label 12508: @780826
     /*  780826 */   GIM_Try, /*On fail goto*//*Label 12509*/ GIMT_Encode4(780880), // Rule ID 2461 //
     /*  780831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  780836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  780842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780853 */     // (intrinsic_wo_chain:{ *:[f32] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F32_e64),
     /*  780856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780878 */     GIR_RootConstrainSelectedInstOperands,
     /*  780879 */     // GIR_Coverage, 2461,
     /*  780879 */     GIR_EraseRootFromParent_Done,
     /*  780880 */   // Label 12509: @780880
     /*  780880 */   GIM_Try, /*On fail goto*//*Label 12510*/ GIMT_Encode4(780937), // Rule ID 2462 //
     /*  780885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /*  780888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log_clamp),
     /*  780893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  780899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780910 */     // (intrinsic_wo_chain:{ *:[f32] } 3276:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_CLAMP_F32_e64),
     /*  780913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780935 */     GIR_RootConstrainSelectedInstOperands,
     /*  780936 */     // GIR_Coverage, 2462,
     /*  780936 */     GIR_EraseRootFromParent_Done,
     /*  780937 */   // Label 12510: @780937
     /*  780937 */   GIM_Try, /*On fail goto*//*Label 12511*/ GIMT_Encode4(780994), // Rule ID 2463 //
     /*  780942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /*  780945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp_legacy),
     /*  780950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  780953 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  780956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  780960 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  780967 */     // (intrinsic_wo_chain:{ *:[f32] } 3415:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  780967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_LEGACY_F32_e64),
     /*  780970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  780972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  780977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  780982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  780987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  780992 */     GIR_RootConstrainSelectedInstOperands,
     /*  780993 */     // GIR_Coverage, 2463,
     /*  780993 */     GIR_EraseRootFromParent_Done,
     /*  780994 */   // Label 12511: @780994
     /*  780994 */   GIM_Try, /*On fail goto*//*Label 12512*/ GIMT_Encode4(781051), // Rule ID 2465 //
     /*  780999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /*  781002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
     /*  781007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  781010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  781013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781024 */     // (intrinsic_wo_chain:{ *:[f32] } 3420:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F32_e64),
     /*  781027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781049 */     GIR_RootConstrainSelectedInstOperands,
     /*  781050 */     // GIR_Coverage, 2465,
     /*  781050 */     GIR_EraseRootFromParent_Done,
     /*  781051 */   // Label 12512: @781051
     /*  781051 */   GIM_Try, /*On fail goto*//*Label 12513*/ GIMT_Encode4(781108), // Rule ID 2467 //
     /*  781056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /*  781059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_legacy),
     /*  781064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  781067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  781070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781074 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781081 */     // (intrinsic_wo_chain:{ *:[f32] } 3421:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_LEGACY_F32_e64),
     /*  781084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781106 */     GIR_RootConstrainSelectedInstOperands,
     /*  781107 */     // GIR_Coverage, 2467,
     /*  781107 */     GIR_EraseRootFromParent_Done,
     /*  781108 */   // Label 12513: @781108
     /*  781108 */   GIM_Try, /*On fail goto*//*Label 12514*/ GIMT_Encode4(781165), // Rule ID 2468 //
     /*  781113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /*  781116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
     /*  781121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  781124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  781127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  781131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781138 */     // (intrinsic_wo_chain:{ *:[f64] } 3420:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64),
     /*  781141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781163 */     GIR_RootConstrainSelectedInstOperands,
     /*  781164 */     // GIR_Coverage, 2468,
     /*  781164 */     GIR_EraseRootFromParent_Done,
     /*  781165 */   // Label 12514: @781165
     /*  781165 */   GIM_Try, /*On fail goto*//*Label 12515*/ GIMT_Encode4(781222), // Rule ID 2469 //
     /*  781170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /*  781173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
     /*  781178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  781181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  781184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  781188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781195 */     // (intrinsic_wo_chain:{ *:[f64] } 3420:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64),
     /*  781198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781220 */     GIR_RootConstrainSelectedInstOperands,
     /*  781221 */     // GIR_Coverage, 2469,
     /*  781221 */     GIR_EraseRootFromParent_Done,
     /*  781222 */   // Label 12515: @781222
     /*  781222 */   GIM_Try, /*On fail goto*//*Label 12516*/ GIMT_Encode4(781279), // Rule ID 2470 //
     /*  781227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /*  781230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
     /*  781235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  781238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  781241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  781245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781252 */     // (intrinsic_wo_chain:{ *:[f64] } 3420:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64),
     /*  781255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781277 */     GIR_RootConstrainSelectedInstOperands,
     /*  781278 */     // GIR_Coverage, 2470,
     /*  781278 */     GIR_EraseRootFromParent_Done,
     /*  781279 */   // Label 12516: @781279
     /*  781279 */   GIM_Try, /*On fail goto*//*Label 12517*/ GIMT_Encode4(781336), // Rule ID 2471 //
     /*  781284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /*  781287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
     /*  781292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  781295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  781298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  781302 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781309 */     // (intrinsic_wo_chain:{ *:[f64] } 3420:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64),
     /*  781312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781334 */     GIR_RootConstrainSelectedInstOperands,
     /*  781335 */     // GIR_Coverage, 2471,
     /*  781335 */     GIR_EraseRootFromParent_Done,
     /*  781336 */   // Label 12517: @781336
     /*  781336 */   GIM_Try, /*On fail goto*//*Label 12518*/ GIMT_Encode4(781393), // Rule ID 2472 //
     /*  781341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /*  781344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
     /*  781349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  781352 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  781355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  781359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781366 */     // (intrinsic_wo_chain:{ *:[f64] } 3420:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64),
     /*  781369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781391 */     GIR_RootConstrainSelectedInstOperands,
     /*  781392 */     // GIR_Coverage, 2472,
     /*  781392 */     GIR_EraseRootFromParent_Done,
     /*  781393 */   // Label 12518: @781393
     /*  781393 */   GIM_Try, /*On fail goto*//*Label 12519*/ GIMT_Encode4(781450), // Rule ID 2510 //
     /*  781398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  781401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  781406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781423 */     // (intrinsic_wo_chain:{ *:[f16] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_e64),
     /*  781426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781448 */     GIR_RootConstrainSelectedInstOperands,
     /*  781449 */     // GIR_Coverage, 2510,
     /*  781449 */     GIR_EraseRootFromParent_Done,
     /*  781450 */   // Label 12519: @781450
     /*  781450 */   GIM_Try, /*On fail goto*//*Label 12520*/ GIMT_Encode4(781507), // Rule ID 2514 //
     /*  781455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  781458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  781463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781480 */     // (intrinsic_wo_chain:{ *:[f16] } 3414:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_fake16_e64),
     /*  781483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781505 */     GIR_RootConstrainSelectedInstOperands,
     /*  781506 */     // GIR_Coverage, 2514,
     /*  781506 */     GIR_EraseRootFromParent_Done,
     /*  781507 */   // Label 12520: @781507
     /*  781507 */   GIM_Try, /*On fail goto*//*Label 12521*/ GIMT_Encode4(781564), // Rule ID 2517 //
     /*  781512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  781515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  781520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781537 */     // (intrinsic_wo_chain:{ *:[f16] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_e64),
     /*  781540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781562 */     GIR_RootConstrainSelectedInstOperands,
     /*  781563 */     // GIR_Coverage, 2517,
     /*  781563 */     GIR_EraseRootFromParent_Done,
     /*  781564 */   // Label 12521: @781564
     /*  781564 */   GIM_Try, /*On fail goto*//*Label 12522*/ GIMT_Encode4(781621), // Rule ID 2521 //
     /*  781569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  781572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  781577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781594 */     // (intrinsic_wo_chain:{ *:[f16] } 3519:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_fake16_e64),
     /*  781597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781619 */     GIR_RootConstrainSelectedInstOperands,
     /*  781620 */     // GIR_Coverage, 2521,
     /*  781620 */     GIR_EraseRootFromParent_Done,
     /*  781621 */   // Label 12522: @781621
     /*  781621 */   GIM_Try, /*On fail goto*//*Label 12523*/ GIMT_Encode4(781678), // Rule ID 2522 //
     /*  781626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  781629 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  781634 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781637 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781651 */     // (intrinsic_wo_chain:{ *:[f16] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_e64),
     /*  781654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781676 */     GIR_RootConstrainSelectedInstOperands,
     /*  781677 */     // GIR_Coverage, 2522,
     /*  781677 */     GIR_EraseRootFromParent_Done,
     /*  781678 */   // Label 12523: @781678
     /*  781678 */   GIM_Try, /*On fail goto*//*Label 12524*/ GIMT_Encode4(781735), // Rule ID 2526 //
     /*  781683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  781686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  781691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781694 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781708 */     // (intrinsic_wo_chain:{ *:[f16] } 3419:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_fake16_e64),
     /*  781711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781733 */     GIR_RootConstrainSelectedInstOperands,
     /*  781734 */     // GIR_Coverage, 2526,
     /*  781734 */     GIR_EraseRootFromParent_Done,
     /*  781735 */   // Label 12524: @781735
     /*  781735 */   GIM_Try, /*On fail goto*//*Label 12525*/ GIMT_Encode4(781792), // Rule ID 2528 //
     /*  781740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  781743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
     /*  781748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781758 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781765 */     // (intrinsic_wo_chain:{ *:[f16] } 3275:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_e64),
     /*  781768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781790 */     GIR_RootConstrainSelectedInstOperands,
     /*  781791 */     // GIR_Coverage, 2528,
     /*  781791 */     GIR_EraseRootFromParent_Done,
     /*  781792 */   // Label 12525: @781792
     /*  781792 */   GIM_Try, /*On fail goto*//*Label 12526*/ GIMT_Encode4(781849), // Rule ID 2532 //
     /*  781797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  781800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
     /*  781805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781822 */     // (intrinsic_wo_chain:{ *:[f16] } 3275:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_fake16_e64),
     /*  781825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781847 */     GIR_RootConstrainSelectedInstOperands,
     /*  781848 */     // GIR_Coverage, 2532,
     /*  781848 */     GIR_EraseRootFromParent_Done,
     /*  781849 */   // Label 12526: @781849
     /*  781849 */   GIM_Try, /*On fail goto*//*Label 12527*/ GIMT_Encode4(781906), // Rule ID 2534 //
     /*  781854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  781857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
     /*  781862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781879 */     // (intrinsic_wo_chain:{ *:[f16] } 2441:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_e64),
     /*  781882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781904 */     GIR_RootConstrainSelectedInstOperands,
     /*  781905 */     // GIR_Coverage, 2534,
     /*  781905 */     GIR_EraseRootFromParent_Done,
     /*  781906 */   // Label 12527: @781906
     /*  781906 */   GIM_Try, /*On fail goto*//*Label 12528*/ GIMT_Encode4(781963), // Rule ID 2538 //
     /*  781911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  781914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
     /*  781919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781936 */     // (intrinsic_wo_chain:{ *:[f16] } 2441:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_fake16_e64),
     /*  781939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  781946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  781951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  781956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  781961 */     GIR_RootConstrainSelectedInstOperands,
     /*  781962 */     // GIR_Coverage, 2538,
     /*  781962 */     GIR_EraseRootFromParent_Done,
     /*  781963 */   // Label 12528: @781963
     /*  781963 */   GIM_Try, /*On fail goto*//*Label 12529*/ GIMT_Encode4(782020), // Rule ID 2540 //
     /*  781968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  781971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
     /*  781976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  781979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  781982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  781986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  781993 */     // (intrinsic_wo_chain:{ *:[f16] } 3489:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  781993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_e64),
     /*  781996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  781998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782018 */     GIR_RootConstrainSelectedInstOperands,
     /*  782019 */     // GIR_Coverage, 2540,
     /*  782019 */     GIR_EraseRootFromParent_Done,
     /*  782020 */   // Label 12529: @782020
     /*  782020 */   GIM_Try, /*On fail goto*//*Label 12530*/ GIMT_Encode4(782077), // Rule ID 2544 //
     /*  782025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  782028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
     /*  782033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782050 */     // (intrinsic_wo_chain:{ *:[f16] } 3489:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_fake16_e64),
     /*  782053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782055 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782075 */     GIR_RootConstrainSelectedInstOperands,
     /*  782076 */     // GIR_Coverage, 2544,
     /*  782076 */     GIR_EraseRootFromParent_Done,
     /*  782077 */   // Label 12530: @782077
     /*  782077 */   GIM_Try, /*On fail goto*//*Label 12531*/ GIMT_Encode4(782134), // Rule ID 2546 //
     /*  782082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  782085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
     /*  782090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782100 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782107 */     // (intrinsic_wo_chain:{ *:[f16] } 2265:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_e64),
     /*  782110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782132 */     GIR_RootConstrainSelectedInstOperands,
     /*  782133 */     // GIR_Coverage, 2546,
     /*  782133 */     GIR_EraseRootFromParent_Done,
     /*  782134 */   // Label 12531: @782134
     /*  782134 */   GIM_Try, /*On fail goto*//*Label 12532*/ GIMT_Encode4(782191), // Rule ID 2550 //
     /*  782139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  782142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
     /*  782147 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782150 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782164 */     // (intrinsic_wo_chain:{ *:[f16] } 2265:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_fake16_e64),
     /*  782167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782189 */     GIR_RootConstrainSelectedInstOperands,
     /*  782190 */     // GIR_Coverage, 2550,
     /*  782190 */     GIR_EraseRootFromParent_Done,
     /*  782191 */   // Label 12532: @782191
     /*  782191 */   GIM_Try, /*On fail goto*//*Label 12533*/ GIMT_Encode4(782248), // Rule ID 2552 //
     /*  782196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTanhInsts_NotHasTrue16BitInsts),
     /*  782199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_tanh),
     /*  782204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782221 */     // (intrinsic_wo_chain:{ *:[f16] } 3601:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TANH_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TANH_F16_e64),
     /*  782224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782246 */     GIR_RootConstrainSelectedInstOperands,
     /*  782247 */     // GIR_Coverage, 2552,
     /*  782247 */     GIR_EraseRootFromParent_Done,
     /*  782248 */   // Label 12533: @782248
     /*  782248 */   GIM_Try, /*On fail goto*//*Label 12534*/ GIMT_Encode4(782305), // Rule ID 2554 //
     /*  782253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTanhInsts_UseFakeTrue16Insts),
     /*  782256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_tanh),
     /*  782261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782271 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782278 */     // (intrinsic_wo_chain:{ *:[f16] } 3601:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TANH_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TANH_F16_fake16_e64),
     /*  782281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782303 */     GIR_RootConstrainSelectedInstOperands,
     /*  782304 */     // GIR_Coverage, 2554,
     /*  782304 */     GIR_EraseRootFromParent_Done,
     /*  782305 */   // Label 12534: @782305
     /*  782305 */   GIM_Try, /*On fail goto*//*Label 12535*/ GIMT_Encode4(782362), // Rule ID 2555 //
     /*  782310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  782313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  782318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782335 */     // (intrinsic_wo_chain:{ *:[f16] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_e64),
     /*  782338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782360 */     GIR_RootConstrainSelectedInstOperands,
     /*  782361 */     // GIR_Coverage, 2555,
     /*  782361 */     GIR_EraseRootFromParent_Done,
     /*  782362 */   // Label 12535: @782362
     /*  782362 */   GIM_Try, /*On fail goto*//*Label 12536*/ GIMT_Encode4(782419), // Rule ID 2557 //
     /*  782367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  782370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  782375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782392 */     // (intrinsic_wo_chain:{ *:[f16] } 2461:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_fake16_e64),
     /*  782395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782417 */     GIR_RootConstrainSelectedInstOperands,
     /*  782418 */     // GIR_Coverage, 2557,
     /*  782418 */     GIR_EraseRootFromParent_Done,
     /*  782419 */   // Label 12536: @782419
     /*  782419 */   GIM_Try, /*On fail goto*//*Label 12537*/ GIMT_Encode4(782476), // Rule ID 2558 //
     /*  782424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  782427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  782432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782442 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782449 */     // (intrinsic_wo_chain:{ *:[i16] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_e64),
     /*  782452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782474 */     GIR_RootConstrainSelectedInstOperands,
     /*  782475 */     // GIR_Coverage, 2558,
     /*  782475 */     GIR_EraseRootFromParent_Done,
     /*  782476 */   // Label 12537: @782476
     /*  782476 */   GIM_Try, /*On fail goto*//*Label 12538*/ GIMT_Encode4(782533), // Rule ID 2560 //
     /*  782481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  782484 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  782489 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782492 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782506 */     // (intrinsic_wo_chain:{ *:[i16] } 2460:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_fake16_e64),
     /*  782509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782531 */     GIR_RootConstrainSelectedInstOperands,
     /*  782532 */     // GIR_Coverage, 2560,
     /*  782532 */     GIR_EraseRootFromParent_Done,
     /*  782533 */   // Label 12538: @782533
     /*  782533 */   GIM_Try, /*On fail goto*//*Label 12539*/ GIMT_Encode4(782590), // Rule ID 2573 //
     /*  782538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  782541 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  782546 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782549 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782563 */     // (intrinsic_wo_chain:{ *:[f16] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_e64),
     /*  782566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782588 */     GIR_RootConstrainSelectedInstOperands,
     /*  782589 */     // GIR_Coverage, 2573,
     /*  782589 */     GIR_EraseRootFromParent_Done,
     /*  782590 */   // Label 12539: @782590
     /*  782590 */   GIM_Try, /*On fail goto*//*Label 12540*/ GIMT_Encode4(782647), // Rule ID 2577 //
     /*  782595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  782598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  782603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782620 */     // (intrinsic_wo_chain:{ *:[f16] } 2459:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  782620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_fake16_e64),
     /*  782623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  782640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  782645 */     GIR_RootConstrainSelectedInstOperands,
     /*  782646 */     // GIR_Coverage, 2577,
     /*  782646 */     GIR_EraseRootFromParent_Done,
     /*  782647 */   // Label 12540: @782647
     /*  782647 */   GIM_Try, /*On fail goto*//*Label 12541*/ GIMT_Encode4(782689), // Rule ID 2585 //
     /*  782652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX1250Plus),
     /*  782655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sat_pk4_i4_i8),
     /*  782660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  782666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782670 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782677 */     // (intrinsic_wo_chain:{ *:[i16] } 3478:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_SAT_PK4_I4_I8_e64:{ *:[i16] } i32:{ *:[i32] }:$src0)
     /*  782677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAT_PK4_I4_I8_e64),
     /*  782680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782687 */     GIR_RootConstrainSelectedInstOperands,
     /*  782688 */     // GIR_Coverage, 2585,
     /*  782688 */     GIR_EraseRootFromParent_Done,
     /*  782689 */   // Label 12541: @782689
     /*  782689 */   GIM_Try, /*On fail goto*//*Label 12542*/ GIMT_Encode4(782731), // Rule ID 2587 //
     /*  782694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  782697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sat_pk4_i4_i8),
     /*  782702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  782708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782719 */     // (intrinsic_wo_chain:{ *:[i16] } 3478:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_SAT_PK4_I4_I8_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0)
     /*  782719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAT_PK4_I4_I8_fake16_e64),
     /*  782722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782729 */     GIR_RootConstrainSelectedInstOperands,
     /*  782730 */     // GIR_Coverage, 2587,
     /*  782730 */     GIR_EraseRootFromParent_Done,
     /*  782731 */   // Label 12542: @782731
     /*  782731 */   GIM_Try, /*On fail goto*//*Label 12543*/ GIMT_Encode4(782773), // Rule ID 2588 //
     /*  782736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX1250Plus),
     /*  782739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sat_pk4_u4_u8),
     /*  782744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782747 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  782750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782754 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782761 */     // (intrinsic_wo_chain:{ *:[i16] } 3479:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_SAT_PK4_U4_U8_e64:{ *:[i16] } i32:{ *:[i32] }:$src0)
     /*  782761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAT_PK4_U4_U8_e64),
     /*  782764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782771 */     GIR_RootConstrainSelectedInstOperands,
     /*  782772 */     // GIR_Coverage, 2588,
     /*  782772 */     GIR_EraseRootFromParent_Done,
     /*  782773 */   // Label 12543: @782773
     /*  782773 */   GIM_Try, /*On fail goto*//*Label 12544*/ GIMT_Encode4(782815), // Rule ID 2590 //
     /*  782778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  782781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sat_pk4_u4_u8),
     /*  782786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  782792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782803 */     // (intrinsic_wo_chain:{ *:[i16] } 3479:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_SAT_PK4_U4_U8_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0)
     /*  782803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAT_PK4_U4_U8_fake16_e64),
     /*  782806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782813 */     GIR_RootConstrainSelectedInstOperands,
     /*  782814 */     // GIR_Coverage, 2590,
     /*  782814 */     GIR_EraseRootFromParent_Done,
     /*  782815 */   // Label 12544: @782815
     /*  782815 */   GIM_Try, /*On fail goto*//*Label 12545*/ GIMT_Encode4(782857), // Rule ID 2591 //
     /*  782820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPrngInst),
     /*  782823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_prng_b32),
     /*  782828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  782831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  782834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  782838 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  782845 */     // (intrinsic_wo_chain:{ *:[i32] } 3358:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_PRNG_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
     /*  782845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PRNG_B32_e64),
     /*  782848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782855 */     GIR_RootConstrainSelectedInstOperands,
     /*  782856 */     // GIR_Coverage, 2591,
     /*  782856 */     GIR_EraseRootFromParent_Done,
     /*  782857 */   // Label 12545: @782857
     /*  782857 */   GIM_Try, /*On fail goto*//*Label 12546*/ GIMT_Encode4(782913), // Rule ID 2512 //
     /*  782862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  782865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
     /*  782870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  782880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  782887 */     // (intrinsic_wo_chain:{ *:[f16] } 3414:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_RCP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  782887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_t16_e64),
     /*  782890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  782905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  782908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  782911 */     GIR_RootConstrainSelectedInstOperands,
     /*  782912 */     // GIR_Coverage, 2512,
     /*  782912 */     GIR_EraseRootFromParent_Done,
     /*  782913 */   // Label 12546: @782913
     /*  782913 */   GIM_Try, /*On fail goto*//*Label 12547*/ GIMT_Encode4(782969), // Rule ID 2519 //
     /*  782918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  782921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
     /*  782926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  782936 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  782943 */     // (intrinsic_wo_chain:{ *:[f16] } 3519:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_SQRT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  782943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_t16_e64),
     /*  782946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  782948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  782953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  782958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  782961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  782964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  782967 */     GIR_RootConstrainSelectedInstOperands,
     /*  782968 */     // GIR_Coverage, 2519,
     /*  782968 */     GIR_EraseRootFromParent_Done,
     /*  782969 */   // Label 12547: @782969
     /*  782969 */   GIM_Try, /*On fail goto*//*Label 12548*/ GIMT_Encode4(783025), // Rule ID 2524 //
     /*  782974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  782977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
     /*  782982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  782985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  782988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  782992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  782999 */     // (intrinsic_wo_chain:{ *:[f16] } 3419:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_RSQ_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  782999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_t16_e64),
     /*  783002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783023 */     GIR_RootConstrainSelectedInstOperands,
     /*  783024 */     // GIR_Coverage, 2524,
     /*  783024 */     GIR_EraseRootFromParent_Done,
     /*  783025 */   // Label 12548: @783025
     /*  783025 */   GIM_Try, /*On fail goto*//*Label 12549*/ GIMT_Encode4(783081), // Rule ID 2530 //
     /*  783030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
     /*  783038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783048 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783055 */     // (intrinsic_wo_chain:{ *:[f16] } 3275:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_LOG_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_t16_e64),
     /*  783058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783079 */     GIR_RootConstrainSelectedInstOperands,
     /*  783080 */     // GIR_Coverage, 2530,
     /*  783080 */     GIR_EraseRootFromParent_Done,
     /*  783081 */   // Label 12549: @783081
     /*  783081 */   GIM_Try, /*On fail goto*//*Label 12550*/ GIMT_Encode4(783137), // Rule ID 2536 //
     /*  783086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
     /*  783094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783111 */     // (intrinsic_wo_chain:{ *:[f16] } 2441:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_EXP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_t16_e64),
     /*  783114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783126 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783135 */     GIR_RootConstrainSelectedInstOperands,
     /*  783136 */     // GIR_Coverage, 2536,
     /*  783136 */     GIR_EraseRootFromParent_Done,
     /*  783137 */   // Label 12550: @783137
     /*  783137 */   GIM_Try, /*On fail goto*//*Label 12551*/ GIMT_Encode4(783193), // Rule ID 2542 //
     /*  783142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
     /*  783150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783160 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783167 */     // (intrinsic_wo_chain:{ *:[f16] } 3489:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_SIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_t16_e64),
     /*  783170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783191 */     GIR_RootConstrainSelectedInstOperands,
     /*  783192 */     // GIR_Coverage, 2542,
     /*  783192 */     GIR_EraseRootFromParent_Done,
     /*  783193 */   // Label 12551: @783193
     /*  783193 */   GIM_Try, /*On fail goto*//*Label 12552*/ GIMT_Encode4(783249), // Rule ID 2548 //
     /*  783198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
     /*  783206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783216 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783223 */     // (intrinsic_wo_chain:{ *:[f16] } 2265:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_COS_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_t16_e64),
     /*  783226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783247 */     GIR_RootConstrainSelectedInstOperands,
     /*  783248 */     // GIR_Coverage, 2548,
     /*  783248 */     GIR_EraseRootFromParent_Done,
     /*  783249 */   // Label 12552: @783249
     /*  783249 */   GIM_Try, /*On fail goto*//*Label 12553*/ GIMT_Encode4(783305), // Rule ID 2553 //
     /*  783254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTanhInsts_UseRealTrue16Insts),
     /*  783257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_tanh),
     /*  783262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783272 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783279 */     // (intrinsic_wo_chain:{ *:[f16] } 3601:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_TANH_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TANH_F16_t16_e64),
     /*  783282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783303 */     GIR_RootConstrainSelectedInstOperands,
     /*  783304 */     // GIR_Coverage, 2553,
     /*  783304 */     GIR_EraseRootFromParent_Done,
     /*  783305 */   // Label 12553: @783305
     /*  783305 */   GIM_Try, /*On fail goto*//*Label 12554*/ GIMT_Encode4(783361), // Rule ID 2556 //
     /*  783310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
     /*  783318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783328 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783335 */     // (intrinsic_wo_chain:{ *:[f16] } 2461:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_FREXP_MANT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_t16_e64),
     /*  783338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783359 */     GIR_RootConstrainSelectedInstOperands,
     /*  783360 */     // GIR_Coverage, 2556,
     /*  783360 */     GIR_EraseRootFromParent_Done,
     /*  783361 */   // Label 12554: @783361
     /*  783361 */   GIM_Try, /*On fail goto*//*Label 12555*/ GIMT_Encode4(783417), // Rule ID 2559 //
     /*  783366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
     /*  783374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783391 */     // (intrinsic_wo_chain:{ *:[i16] } 2460:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_FREXP_EXP_I16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_t16_e64),
     /*  783394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783415 */     GIR_RootConstrainSelectedInstOperands,
     /*  783416 */     // GIR_Coverage, 2559,
     /*  783416 */     GIR_EraseRootFromParent_Done,
     /*  783417 */   // Label 12555: @783417
     /*  783417 */   GIM_Try, /*On fail goto*//*Label 12556*/ GIMT_Encode4(783473), // Rule ID 2575 //
     /*  783422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  783425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
     /*  783430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783447 */     // (intrinsic_wo_chain:{ *:[f16] } 2459:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_FRACT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0)
     /*  783447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_t16_e64),
     /*  783450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783471 */     GIR_RootConstrainSelectedInstOperands,
     /*  783472 */     // GIR_Coverage, 2575,
     /*  783472 */     GIR_EraseRootFromParent_Done,
     /*  783473 */   // Label 12556: @783473
     /*  783473 */   GIM_Try, /*On fail goto*//*Label 12557*/ GIMT_Encode4(783523), // Rule ID 2579 //
     /*  783478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX1250Plus),
     /*  783481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f16_fp8),
     /*  783486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  783489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783492 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783503 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2280:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_F16_FP8_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0)
     /*  783503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_FP8_e64),
     /*  783506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783521 */     GIR_RootConstrainSelectedInstOperands,
     /*  783522 */     // GIR_Coverage, 2579,
     /*  783522 */     GIR_EraseRootFromParent_Done,
     /*  783523 */   // Label 12557: @783523
     /*  783523 */   GIM_Try, /*On fail goto*//*Label 12558*/ GIMT_Encode4(783573), // Rule ID 2580 //
     /*  783528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  783531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f16_fp8),
     /*  783536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  783539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783553 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2280:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_F16_FP8_t16_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0)
     /*  783553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_FP8_t16_e64),
     /*  783556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783571 */     GIR_RootConstrainSelectedInstOperands,
     /*  783572 */     // GIR_Coverage, 2580,
     /*  783572 */     GIR_EraseRootFromParent_Done,
     /*  783573 */   // Label 12558: @783573
     /*  783573 */   GIM_Try, /*On fail goto*//*Label 12559*/ GIMT_Encode4(783623), // Rule ID 2581 //
     /*  783578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  783581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f16_fp8),
     /*  783586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  783589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783596 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783603 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2280:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_F16_FP8_fake16_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0)
     /*  783603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_FP8_fake16_e64),
     /*  783606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783621 */     GIR_RootConstrainSelectedInstOperands,
     /*  783622 */     // GIR_Coverage, 2581,
     /*  783622 */     GIR_EraseRootFromParent_Done,
     /*  783623 */   // Label 12559: @783623
     /*  783623 */   GIM_Try, /*On fail goto*//*Label 12560*/ GIMT_Encode4(783673), // Rule ID 2582 //
     /*  783628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX1250Plus),
     /*  783631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f16_bf8),
     /*  783636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  783639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783653 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2279:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_F16_BF8_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0)
     /*  783653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_BF8_e64),
     /*  783656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783671 */     GIR_RootConstrainSelectedInstOperands,
     /*  783672 */     // GIR_Coverage, 2582,
     /*  783672 */     GIR_EraseRootFromParent_Done,
     /*  783673 */   // Label 12560: @783673
     /*  783673 */   GIM_Try, /*On fail goto*//*Label 12561*/ GIMT_Encode4(783723), // Rule ID 2583 //
     /*  783678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  783681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f16_bf8),
     /*  783686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  783689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783703 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2279:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_F16_BF8_t16_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0)
     /*  783703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_BF8_t16_e64),
     /*  783706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783721 */     GIR_RootConstrainSelectedInstOperands,
     /*  783722 */     // GIR_Coverage, 2583,
     /*  783722 */     GIR_EraseRootFromParent_Done,
     /*  783723 */   // Label 12561: @783723
     /*  783723 */   GIM_Try, /*On fail goto*//*Label 12562*/ GIMT_Encode4(783773), // Rule ID 2584 //
     /*  783728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  783731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f16_bf8),
     /*  783736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  783739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  783742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783753 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2279:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_F16_BF8_fake16_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0)
     /*  783753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F16_BF8_fake16_e64),
     /*  783756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783771 */     GIR_RootConstrainSelectedInstOperands,
     /*  783772 */     // GIR_Coverage, 2584,
     /*  783772 */     GIR_EraseRootFromParent_Done,
     /*  783773 */   // Label 12562: @783773
     /*  783773 */   GIM_Try, /*On fail goto*//*Label 12563*/ GIMT_Encode4(783823), // Rule ID 2586 //
     /*  783778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  783781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sat_pk4_i4_i8),
     /*  783786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  783792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783803 */     // (intrinsic_wo_chain:{ *:[i16] } 3478:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_SAT_PK4_I4_I8_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0)
     /*  783803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAT_PK4_I4_I8_t16_e64),
     /*  783806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783821 */     GIR_RootConstrainSelectedInstOperands,
     /*  783822 */     // GIR_Coverage, 2586,
     /*  783822 */     GIR_EraseRootFromParent_Done,
     /*  783823 */   // Label 12563: @783823
     /*  783823 */   GIM_Try, /*On fail goto*//*Label 12564*/ GIMT_Encode4(783873), // Rule ID 2589 //
     /*  783828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  783831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sat_pk4_u4_u8),
     /*  783836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  783842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783853 */     // (intrinsic_wo_chain:{ *:[i16] } 3479:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_SAT_PK4_U4_U8_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0)
     /*  783853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAT_PK4_U4_U8_t16_e64),
     /*  783856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783871 */     GIR_RootConstrainSelectedInstOperands,
     /*  783872 */     // GIR_Coverage, 2589,
     /*  783872 */     GIR_EraseRootFromParent_Done,
     /*  783873 */   // Label 12564: @783873
     /*  783873 */   GIM_Try, /*On fail goto*//*Label 12565*/ GIMT_Encode4(783926), // Rule ID 3120 //
     /*  783878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX125xOnly),
     /*  783881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f16),
     /*  783886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  783892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  783896 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783903 */     // (intrinsic_wo_chain:{ *:[i16] } 2283:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_FP8_F16_gfx1250_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0)
     /*  783903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F16_gfx1250_e64),
     /*  783906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783924 */     GIR_RootConstrainSelectedInstOperands,
     /*  783925 */     // GIR_Coverage, 3120,
     /*  783925 */     GIR_EraseRootFromParent_Done,
     /*  783926 */   // Label 12565: @783926
     /*  783926 */   GIM_Try, /*On fail goto*//*Label 12566*/ GIMT_Encode4(783979), // Rule ID 3121 //
     /*  783931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX125xOnly),
     /*  783934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f16),
     /*  783939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  783945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  783949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  783956 */     // (intrinsic_wo_chain:{ *:[i16] } 2283:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_FP8_F16_gfx1250_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0)
     /*  783956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F16_gfx1250_t16_e64),
     /*  783959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  783961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  783966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  783971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  783977 */     GIR_RootConstrainSelectedInstOperands,
     /*  783978 */     // GIR_Coverage, 3121,
     /*  783978 */     GIR_EraseRootFromParent_Done,
     /*  783979 */   // Label 12566: @783979
     /*  783979 */   GIM_Try, /*On fail goto*//*Label 12567*/ GIMT_Encode4(784032), // Rule ID 3122 //
     /*  783984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX125xOnly),
     /*  783987 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f16),
     /*  783992 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  783995 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  783998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  784009 */     // (intrinsic_wo_chain:{ *:[i16] } 2283:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_FP8_F16_gfx1250_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0)
     /*  784009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F16_gfx1250_fake16_e64),
     /*  784012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  784014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784030 */     GIR_RootConstrainSelectedInstOperands,
     /*  784031 */     // GIR_Coverage, 3122,
     /*  784031 */     GIR_EraseRootFromParent_Done,
     /*  784032 */   // Label 12567: @784032
     /*  784032 */   GIM_Try, /*On fail goto*//*Label 12568*/ GIMT_Encode4(784085), // Rule ID 3123 //
     /*  784037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX125xOnly),
     /*  784040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f16),
     /*  784045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  784048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  784051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  784062 */     // (intrinsic_wo_chain:{ *:[i16] } 2277:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_BF8_F16_gfx1250_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0)
     /*  784062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F16_gfx1250_e64),
     /*  784065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  784067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784080 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784083 */     GIR_RootConstrainSelectedInstOperands,
     /*  784084 */     // GIR_Coverage, 3123,
     /*  784084 */     GIR_EraseRootFromParent_Done,
     /*  784085 */   // Label 12568: @784085
     /*  784085 */   GIM_Try, /*On fail goto*//*Label 12569*/ GIMT_Encode4(784138), // Rule ID 3124 //
     /*  784090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX125xOnly),
     /*  784093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f16),
     /*  784098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  784101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  784104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  784108 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  784115 */     // (intrinsic_wo_chain:{ *:[i16] } 2277:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_BF8_F16_gfx1250_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0)
     /*  784115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F16_gfx1250_t16_e64),
     /*  784118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  784120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784136 */     GIR_RootConstrainSelectedInstOperands,
     /*  784137 */     // GIR_Coverage, 3124,
     /*  784137 */     GIR_EraseRootFromParent_Done,
     /*  784138 */   // Label 12569: @784138
     /*  784138 */   GIM_Try, /*On fail goto*//*Label 12570*/ GIMT_Encode4(784191), // Rule ID 3125 //
     /*  784143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX125xOnly),
     /*  784146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f16),
     /*  784151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  784154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  784157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  784168 */     // (intrinsic_wo_chain:{ *:[i16] } 2277:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CVT_PK_BF8_F16_gfx1250_fake16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0)
     /*  784168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F16_gfx1250_fake16_e64),
     /*  784171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  784173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784189 */     GIR_RootConstrainSelectedInstOperands,
     /*  784190 */     // GIR_Coverage, 3125,
     /*  784190 */     GIR_EraseRootFromParent_Done,
     /*  784191 */   // Label 12570: @784191
     /*  784191 */   GIM_Reject,
     /*  784192 */ // Label 12455: @784192
     /*  784192 */ GIM_Try, /*On fail goto*//*Label 12571*/ GIMT_Encode4(793519),
     /*  784197 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /*  784200 */   GIM_Try, /*On fail goto*//*Label 12572*/ GIMT_Encode4(784252), // Rule ID 4824 //
     /*  784205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  784208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784216 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  784219 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784233 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  784233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
     /*  784236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784248 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  784250 */     GIR_RootConstrainSelectedInstOperands,
     /*  784251 */     // GIR_Coverage, 4824,
     /*  784251 */     GIR_EraseRootFromParent_Done,
     /*  784252 */   // Label 12572: @784252
     /*  784252 */   GIM_Try, /*On fail goto*//*Label 12573*/ GIMT_Encode4(784304), // Rule ID 4825 //
     /*  784257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  784260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  784271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784285 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  784285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
     /*  784288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784300 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  784302 */     GIR_RootConstrainSelectedInstOperands,
     /*  784303 */     // GIR_Coverage, 4825,
     /*  784303 */     GIR_EraseRootFromParent_Done,
     /*  784304 */   // Label 12573: @784304
     /*  784304 */   GIM_Try, /*On fail goto*//*Label 12574*/ GIMT_Encode4(784356), // Rule ID 4826 //
     /*  784309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  784312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  784323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784337 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  784337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
     /*  784340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784352 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  784354 */     GIR_RootConstrainSelectedInstOperands,
     /*  784355 */     // GIR_Coverage, 4826,
     /*  784355 */     GIR_EraseRootFromParent_Done,
     /*  784356 */   // Label 12574: @784356
     /*  784356 */   GIM_Try, /*On fail goto*//*Label 12575*/ GIMT_Encode4(784408), // Rule ID 4827 //
     /*  784361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  784364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  784375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784382 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784389 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  784389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
     /*  784392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784404 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  784406 */     GIR_RootConstrainSelectedInstOperands,
     /*  784407 */     // GIR_Coverage, 4827,
     /*  784407 */     GIR_EraseRootFromParent_Done,
     /*  784408 */   // Label 12575: @784408
     /*  784408 */   GIM_Try, /*On fail goto*//*Label 12576*/ GIMT_Encode4(784460), // Rule ID 4828 //
     /*  784413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  784416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  784427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784434 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784441 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  784441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
     /*  784444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784456 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  784458 */     GIR_RootConstrainSelectedInstOperands,
     /*  784459 */     // GIR_Coverage, 4828,
     /*  784459 */     GIR_EraseRootFromParent_Done,
     /*  784460 */   // Label 12576: @784460
     /*  784460 */   GIM_Try, /*On fail goto*//*Label 12577*/ GIMT_Encode4(784547), // Rule ID 4834 //
     /*  784465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode0),
     /*  784468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784493 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, VSrcT_f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[i32] }:$src1, lo16:{ *:[i32] }), 0:{ *:[i32] })
     /*  784493 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  784496 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  784500 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  784505 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(2), // src1
     /*  784511 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  784516 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
     /*  784524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784539 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  784542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784545 */     GIR_RootConstrainSelectedInstOperands,
     /*  784546 */     // GIR_Coverage, 4834,
     /*  784546 */     GIR_EraseRootFromParent_Done,
     /*  784547 */   // Label 12577: @784547
     /*  784547 */   GIM_Try, /*On fail goto*//*Label 12578*/ GIMT_Encode4(784634), // Rule ID 4835 //
     /*  784552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode1),
     /*  784555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784573 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784580 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, VSrcT_f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[i32] }:$src1, lo16:{ *:[i32] }), 0:{ *:[i32] })
     /*  784580 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  784583 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  784587 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  784592 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(2), // src1
     /*  784598 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  784603 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
     /*  784611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784626 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  784629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784632 */     GIR_RootConstrainSelectedInstOperands,
     /*  784633 */     // GIR_Coverage, 4835,
     /*  784633 */     GIR_EraseRootFromParent_Done,
     /*  784634 */   // Label 12578: @784634
     /*  784634 */   GIM_Try, /*On fail goto*//*Label 12579*/ GIMT_Encode4(784721), // Rule ID 4836 //
     /*  784639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode2),
     /*  784642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784667 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, VSrcT_f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[i32] }:$src1, lo16:{ *:[i32] }), 0:{ *:[i32] })
     /*  784667 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  784670 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  784674 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  784679 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(2), // src1
     /*  784685 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  784690 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
     /*  784698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784713 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  784716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784719 */     GIR_RootConstrainSelectedInstOperands,
     /*  784720 */     // GIR_Coverage, 4836,
     /*  784720 */     GIR_EraseRootFromParent_Done,
     /*  784721 */   // Label 12579: @784721
     /*  784721 */   GIM_Try, /*On fail goto*//*Label 12580*/ GIMT_Encode4(784808), // Rule ID 4837 //
     /*  784726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode3),
     /*  784729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784754 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, VSrcT_f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[i32] }:$src1, lo16:{ *:[i32] }), 0:{ *:[i32] })
     /*  784754 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  784757 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  784761 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  784766 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(2), // src1
     /*  784772 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  784777 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
     /*  784785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784800 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  784803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784806 */     GIR_RootConstrainSelectedInstOperands,
     /*  784807 */     // GIR_Coverage, 4837,
     /*  784807 */     GIR_EraseRootFromParent_Done,
     /*  784808 */   // Label 12580: @784808
     /*  784808 */   GIM_Try, /*On fail goto*//*Label 12581*/ GIMT_Encode4(784895), // Rule ID 4838 //
     /*  784813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode4),
     /*  784816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784841 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, VSrcT_f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[i32] }:$src1, lo16:{ *:[i32] }), 0:{ *:[i32] })
     /*  784841 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  784844 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  784848 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  784853 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(2), // src1
     /*  784859 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  784864 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  784869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
     /*  784872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784887 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  784890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784893 */     GIR_RootConstrainSelectedInstOperands,
     /*  784894 */     // GIR_Coverage, 4838,
     /*  784894 */     GIR_EraseRootFromParent_Done,
     /*  784895 */   // Label 12581: @784895
     /*  784895 */   GIM_Try, /*On fail goto*//*Label 12582*/ GIMT_Encode4(784950), // Rule ID 4844 //
     /*  784900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_HwMode0),
     /*  784903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784928 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_fake16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src1)
     /*  784928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_fake16_e64),
     /*  784931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  784946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  784948 */     GIR_RootConstrainSelectedInstOperands,
     /*  784949 */     // GIR_Coverage, 4844,
     /*  784949 */     GIR_EraseRootFromParent_Done,
     /*  784950 */   // Label 12582: @784950
     /*  784950 */   GIM_Try, /*On fail goto*//*Label 12583*/ GIMT_Encode4(785005), // Rule ID 4845 //
     /*  784955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_HwMode1),
     /*  784958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  784963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  784966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  784969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  784972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  784976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  784983 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_fake16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src1)
     /*  784983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_fake16_e64),
     /*  784986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  784988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  784993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  784998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785001 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785003 */     GIR_RootConstrainSelectedInstOperands,
     /*  785004 */     // GIR_Coverage, 4845,
     /*  785004 */     GIR_EraseRootFromParent_Done,
     /*  785005 */   // Label 12583: @785005
     /*  785005 */   GIM_Try, /*On fail goto*//*Label 12584*/ GIMT_Encode4(785060), // Rule ID 4846 //
     /*  785010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_HwMode2),
     /*  785013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785038 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_fake16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src1)
     /*  785038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_fake16_e64),
     /*  785041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785056 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785058 */     GIR_RootConstrainSelectedInstOperands,
     /*  785059 */     // GIR_Coverage, 4846,
     /*  785059 */     GIR_EraseRootFromParent_Done,
     /*  785060 */   // Label 12584: @785060
     /*  785060 */   GIM_Try, /*On fail goto*//*Label 12585*/ GIMT_Encode4(785115), // Rule ID 4847 //
     /*  785065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_HwMode3),
     /*  785068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785079 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785093 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_fake16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src1)
     /*  785093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_fake16_e64),
     /*  785096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785111 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785113 */     GIR_RootConstrainSelectedInstOperands,
     /*  785114 */     // GIR_Coverage, 4847,
     /*  785114 */     GIR_EraseRootFromParent_Done,
     /*  785115 */   // Label 12585: @785115
     /*  785115 */   GIM_Try, /*On fail goto*//*Label 12586*/ GIMT_Encode4(785170), // Rule ID 4848 //
     /*  785120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_HwMode4),
     /*  785123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785148 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_fake16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src1)
     /*  785148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_fake16_e64),
     /*  785151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785166 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785168 */     GIR_RootConstrainSelectedInstOperands,
     /*  785169 */     // GIR_Coverage, 4848,
     /*  785169 */     GIR_EraseRootFromParent_Done,
     /*  785170 */   // Label 12586: @785170
     /*  785170 */   GIM_Try, /*On fail goto*//*Label 12587*/ GIMT_Encode4(785222), // Rule ID 4854 //
     /*  785175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  785178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  785189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785203 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
     /*  785206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785218 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785220 */     GIR_RootConstrainSelectedInstOperands,
     /*  785221 */     // GIR_Coverage, 4854,
     /*  785221 */     GIR_EraseRootFromParent_Done,
     /*  785222 */   // Label 12587: @785222
     /*  785222 */   GIM_Try, /*On fail goto*//*Label 12588*/ GIMT_Encode4(785274), // Rule ID 4855 //
     /*  785227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  785230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  785241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785255 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
     /*  785258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785270 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785272 */     GIR_RootConstrainSelectedInstOperands,
     /*  785273 */     // GIR_Coverage, 4855,
     /*  785273 */     GIR_EraseRootFromParent_Done,
     /*  785274 */   // Label 12588: @785274
     /*  785274 */   GIM_Try, /*On fail goto*//*Label 12589*/ GIMT_Encode4(785326), // Rule ID 4856 //
     /*  785279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  785282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  785293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785307 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
     /*  785310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785322 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785324 */     GIR_RootConstrainSelectedInstOperands,
     /*  785325 */     // GIR_Coverage, 4856,
     /*  785325 */     GIR_EraseRootFromParent_Done,
     /*  785326 */   // Label 12589: @785326
     /*  785326 */   GIM_Try, /*On fail goto*//*Label 12590*/ GIMT_Encode4(785378), // Rule ID 4857 //
     /*  785331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  785334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  785345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785359 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
     /*  785362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785374 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785376 */     GIR_RootConstrainSelectedInstOperands,
     /*  785377 */     // GIR_Coverage, 4857,
     /*  785377 */     GIR_EraseRootFromParent_Done,
     /*  785378 */   // Label 12590: @785378
     /*  785378 */   GIM_Try, /*On fail goto*//*Label 12591*/ GIMT_Encode4(785430), // Rule ID 4858 //
     /*  785383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  785386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  785397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785404 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785411 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
     /*  785414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785426 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785428 */     GIR_RootConstrainSelectedInstOperands,
     /*  785429 */     // GIR_Coverage, 4858,
     /*  785429 */     GIR_EraseRootFromParent_Done,
     /*  785430 */   // Label 12591: @785430
     /*  785430 */   GIM_Try, /*On fail goto*//*Label 12592*/ GIMT_Encode4(785482), // Rule ID 4864 //
     /*  785435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode0),
     /*  785438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785443 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785463 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
     /*  785466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785478 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785480 */     GIR_RootConstrainSelectedInstOperands,
     /*  785481 */     // GIR_Coverage, 4864,
     /*  785481 */     GIR_EraseRootFromParent_Done,
     /*  785482 */   // Label 12592: @785482
     /*  785482 */   GIM_Try, /*On fail goto*//*Label 12593*/ GIMT_Encode4(785534), // Rule ID 4865 //
     /*  785487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode1),
     /*  785490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785515 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
     /*  785518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785530 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785532 */     GIR_RootConstrainSelectedInstOperands,
     /*  785533 */     // GIR_Coverage, 4865,
     /*  785533 */     GIR_EraseRootFromParent_Done,
     /*  785534 */   // Label 12593: @785534
     /*  785534 */   GIM_Try, /*On fail goto*//*Label 12594*/ GIMT_Encode4(785586), // Rule ID 4866 //
     /*  785539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode2),
     /*  785542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785553 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785560 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785567 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
     /*  785570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785582 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785584 */     GIR_RootConstrainSelectedInstOperands,
     /*  785585 */     // GIR_Coverage, 4866,
     /*  785585 */     GIR_EraseRootFromParent_Done,
     /*  785586 */   // Label 12594: @785586
     /*  785586 */   GIM_Try, /*On fail goto*//*Label 12595*/ GIMT_Encode4(785638), // Rule ID 4867 //
     /*  785591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode3),
     /*  785594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785612 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785619 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
     /*  785622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785634 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785636 */     GIR_RootConstrainSelectedInstOperands,
     /*  785637 */     // GIR_Coverage, 4867,
     /*  785637 */     GIR_EraseRootFromParent_Done,
     /*  785638 */   // Label 12595: @785638
     /*  785638 */   GIM_Try, /*On fail goto*//*Label 12596*/ GIMT_Encode4(785690), // Rule ID 4868 //
     /*  785643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_HwMode4),
     /*  785646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
     /*  785651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  785654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  785657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  785660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  785664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
     /*  785671 */     // (intrinsic_wo_chain:{ *:[i1] } 2240:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
     /*  785671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
     /*  785674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  785676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  785681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  785686 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  785688 */     GIR_RootConstrainSelectedInstOperands,
     /*  785689 */     // GIR_Coverage, 4868,
     /*  785689 */     GIR_EraseRootFromParent_Done,
     /*  785690 */   // Label 12596: @785690
     /*  785690 */   GIM_Try, /*On fail goto*//*Label 12597*/ GIMT_Encode4(785745), // Rule ID 6988 //
     /*  785695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtFP8VOP1Bug_HasFP8ConversionInsts),
     /*  785698 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  785703 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  785706 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  785709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  785713 */     // MIs[0] Operand 3
     /*  785713 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  785724 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  785724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
     /*  785727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  785729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785732 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  785734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785737 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785743 */     GIR_RootConstrainSelectedInstOperands,
     /*  785744 */     // GIR_Coverage, 6988,
     /*  785744 */     GIR_EraseRootFromParent_Done,
     /*  785745 */   // Label 12597: @785745
     /*  785745 */   GIM_Try, /*On fail goto*//*Label 12598*/ GIMT_Encode4(785800), // Rule ID 6989 //
     /*  785750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtFP8VOP1Bug_HasFP8ConversionInsts),
     /*  785753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
     /*  785758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  785761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  785764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  785768 */     // MIs[0] Operand 3
     /*  785768 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  785779 */     // (intrinsic_wo_chain:{ *:[f32] } 2273:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] })
     /*  785779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
     /*  785782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  785784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785787 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  785789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785798 */     GIR_RootConstrainSelectedInstOperands,
     /*  785799 */     // GIR_Coverage, 6989,
     /*  785799 */     GIR_EraseRootFromParent_Done,
     /*  785800 */   // Label 12598: @785800
     /*  785800 */   GIM_Try, /*On fail goto*//*Label 12599*/ GIMT_Encode4(785843), // Rule ID 6990 //
     /*  785805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasNoCvtFP8VOP1Bug_HasSDWA),
     /*  785808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  785813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  785816 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  785819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  785823 */     // MIs[0] Operand 3
     /*  785823 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  785834 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_FP8_e32:{ *:[f32] } ?:{ *:[i32] }:$src)
     /*  785834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_e32),
     /*  785837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  785839 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  785841 */     GIR_RootConstrainSelectedInstOperands,
     /*  785842 */     // GIR_Coverage, 6990,
     /*  785842 */     GIR_EraseRootFromParent_Done,
     /*  785843 */   // Label 12599: @785843
     /*  785843 */   GIM_Try, /*On fail goto*//*Label 12600*/ GIMT_Encode4(785886), // Rule ID 6991 //
     /*  785848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasNoCvtFP8VOP1Bug_HasSDWA),
     /*  785851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
     /*  785856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  785859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  785862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  785866 */     // MIs[0] Operand 3
     /*  785866 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  785877 */     // (intrinsic_wo_chain:{ *:[f32] } 2273:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_BF8_e32:{ *:[f32] } ?:{ *:[i32] }:$src)
     /*  785877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_e32),
     /*  785880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  785882 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  785884 */     GIR_RootConstrainSelectedInstOperands,
     /*  785885 */     // GIR_Coverage, 6991,
     /*  785885 */     GIR_EraseRootFromParent_Done,
     /*  785886 */   // Label 12600: @785886
     /*  785886 */   GIM_Try, /*On fail goto*//*Label 12601*/ GIMT_Encode4(785941), // Rule ID 6992 //
     /*  785891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA),
     /*  785894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  785899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  785902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  785905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  785909 */     // MIs[0] Operand 3
     /*  785909 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
     /*  785920 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 1:{ *:[i32] })
     /*  785920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
     /*  785923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  785925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785928 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  785930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  785939 */     GIR_RootConstrainSelectedInstOperands,
     /*  785940 */     // GIR_Coverage, 6992,
     /*  785940 */     GIR_EraseRootFromParent_Done,
     /*  785941 */   // Label 12601: @785941
     /*  785941 */   GIM_Try, /*On fail goto*//*Label 12602*/ GIMT_Encode4(785996), // Rule ID 6993 //
     /*  785946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA),
     /*  785949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
     /*  785954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  785957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  785960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  785964 */     // MIs[0] Operand 3
     /*  785964 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
     /*  785975 */     // (intrinsic_wo_chain:{ *:[f32] } 2273:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 1:{ *:[i32] })
     /*  785975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
     /*  785978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  785980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785983 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  785985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  785991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  785994 */     GIR_RootConstrainSelectedInstOperands,
     /*  785995 */     // GIR_Coverage, 6993,
     /*  785995 */     GIR_EraseRootFromParent_Done,
     /*  785996 */   // Label 12602: @785996
     /*  785996 */   GIM_Try, /*On fail goto*//*Label 12603*/ GIMT_Encode4(786051), // Rule ID 6994 //
     /*  786001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA),
     /*  786004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  786009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  786012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  786019 */     // MIs[0] Operand 3
     /*  786019 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
     /*  786030 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 2:{ *:[i32] })
     /*  786030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
     /*  786033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786038 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /*  786049 */     GIR_RootConstrainSelectedInstOperands,
     /*  786050 */     // GIR_Coverage, 6994,
     /*  786050 */     GIR_EraseRootFromParent_Done,
     /*  786051 */   // Label 12603: @786051
     /*  786051 */   GIM_Try, /*On fail goto*//*Label 12604*/ GIMT_Encode4(786106), // Rule ID 6995 //
     /*  786056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA),
     /*  786059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
     /*  786064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  786067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  786074 */     // MIs[0] Operand 3
     /*  786074 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
     /*  786085 */     // (intrinsic_wo_chain:{ *:[f32] } 2273:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 2:{ *:[i32] })
     /*  786085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
     /*  786088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /*  786104 */     GIR_RootConstrainSelectedInstOperands,
     /*  786105 */     // GIR_Coverage, 6995,
     /*  786105 */     GIR_EraseRootFromParent_Done,
     /*  786106 */   // Label 12604: @786106
     /*  786106 */   GIM_Try, /*On fail goto*//*Label 12605*/ GIMT_Encode4(786161), // Rule ID 6996 //
     /*  786111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA),
     /*  786114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  786119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  786122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  786129 */     // MIs[0] Operand 3
     /*  786129 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
     /*  786140 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 3:{ *:[i32] })
     /*  786140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
     /*  786143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786148 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786150 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /*  786159 */     GIR_RootConstrainSelectedInstOperands,
     /*  786160 */     // GIR_Coverage, 6996,
     /*  786160 */     GIR_EraseRootFromParent_Done,
     /*  786161 */   // Label 12605: @786161
     /*  786161 */   GIM_Try, /*On fail goto*//*Label 12606*/ GIMT_Encode4(786216), // Rule ID 6997 //
     /*  786166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA),
     /*  786169 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
     /*  786174 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  786177 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  786184 */     // MIs[0] Operand 3
     /*  786184 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
     /*  786195 */     // (intrinsic_wo_chain:{ *:[f32] } 2273:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 3:{ *:[i32] })
     /*  786195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
     /*  786198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786203 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /*  786214 */     GIR_RootConstrainSelectedInstOperands,
     /*  786215 */     // GIR_Coverage, 6997,
     /*  786215 */     GIR_EraseRootFromParent_Done,
     /*  786216 */   // Label 12606: @786216
     /*  786216 */   GIM_Try, /*On fail goto*//*Label 12607*/ GIMT_Encode4(786259), // Rule ID 6998 //
     /*  786221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode0),
     /*  786224 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786229 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786232 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786239 */     // MIs[0] Operand 3
     /*  786239 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786250 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
     /*  786253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786255 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786257 */     GIR_RootConstrainSelectedInstOperands,
     /*  786258 */     // GIR_Coverage, 6998,
     /*  786258 */     GIR_EraseRootFromParent_Done,
     /*  786259 */   // Label 12607: @786259
     /*  786259 */   GIM_Try, /*On fail goto*//*Label 12608*/ GIMT_Encode4(786302), // Rule ID 6999 //
     /*  786264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode1),
     /*  786267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786282 */     // MIs[0] Operand 3
     /*  786282 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786293 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
     /*  786296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786298 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786300 */     GIR_RootConstrainSelectedInstOperands,
     /*  786301 */     // GIR_Coverage, 6999,
     /*  786301 */     GIR_EraseRootFromParent_Done,
     /*  786302 */   // Label 12608: @786302
     /*  786302 */   GIM_Try, /*On fail goto*//*Label 12609*/ GIMT_Encode4(786345), // Rule ID 7000 //
     /*  786307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode2),
     /*  786310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786325 */     // MIs[0] Operand 3
     /*  786325 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786336 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
     /*  786339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786341 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786343 */     GIR_RootConstrainSelectedInstOperands,
     /*  786344 */     // GIR_Coverage, 7000,
     /*  786344 */     GIR_EraseRootFromParent_Done,
     /*  786345 */   // Label 12609: @786345
     /*  786345 */   GIM_Try, /*On fail goto*//*Label 12610*/ GIMT_Encode4(786388), // Rule ID 7001 //
     /*  786350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode3),
     /*  786353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786368 */     // MIs[0] Operand 3
     /*  786368 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786379 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
     /*  786382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786384 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786386 */     GIR_RootConstrainSelectedInstOperands,
     /*  786387 */     // GIR_Coverage, 7001,
     /*  786387 */     GIR_EraseRootFromParent_Done,
     /*  786388 */   // Label 12610: @786388
     /*  786388 */   GIM_Try, /*On fail goto*//*Label 12611*/ GIMT_Encode4(786431), // Rule ID 7002 //
     /*  786393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode4),
     /*  786396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786411 */     // MIs[0] Operand 3
     /*  786411 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786422 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
     /*  786425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786427 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786429 */     GIR_RootConstrainSelectedInstOperands,
     /*  786430 */     // GIR_Coverage, 7002,
     /*  786430 */     GIR_EraseRootFromParent_Done,
     /*  786431 */   // Label 12611: @786431
     /*  786431 */   GIM_Try, /*On fail goto*//*Label 12612*/ GIMT_Encode4(786474), // Rule ID 7003 //
     /*  786436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode0),
     /*  786439 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786444 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786447 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786454 */     // MIs[0] Operand 3
     /*  786454 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786465 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
     /*  786468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786470 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786472 */     GIR_RootConstrainSelectedInstOperands,
     /*  786473 */     // GIR_Coverage, 7003,
     /*  786473 */     GIR_EraseRootFromParent_Done,
     /*  786474 */   // Label 12612: @786474
     /*  786474 */   GIM_Try, /*On fail goto*//*Label 12613*/ GIMT_Encode4(786517), // Rule ID 7004 //
     /*  786479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode1),
     /*  786482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786497 */     // MIs[0] Operand 3
     /*  786497 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786508 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
     /*  786511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786513 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786515 */     GIR_RootConstrainSelectedInstOperands,
     /*  786516 */     // GIR_Coverage, 7004,
     /*  786516 */     GIR_EraseRootFromParent_Done,
     /*  786517 */   // Label 12613: @786517
     /*  786517 */   GIM_Try, /*On fail goto*//*Label 12614*/ GIMT_Encode4(786560), // Rule ID 7005 //
     /*  786522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode2),
     /*  786525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786540 */     // MIs[0] Operand 3
     /*  786540 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786551 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
     /*  786554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786556 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786558 */     GIR_RootConstrainSelectedInstOperands,
     /*  786559 */     // GIR_Coverage, 7005,
     /*  786559 */     GIR_EraseRootFromParent_Done,
     /*  786560 */   // Label 12614: @786560
     /*  786560 */   GIM_Try, /*On fail goto*//*Label 12615*/ GIMT_Encode4(786603), // Rule ID 7006 //
     /*  786565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode3),
     /*  786568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786583 */     // MIs[0] Operand 3
     /*  786583 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786594 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
     /*  786597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786599 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786601 */     GIR_RootConstrainSelectedInstOperands,
     /*  786602 */     // GIR_Coverage, 7006,
     /*  786602 */     GIR_EraseRootFromParent_Done,
     /*  786603 */   // Label 12615: @786603
     /*  786603 */   GIM_Try, /*On fail goto*//*Label 12616*/ GIMT_Encode4(786646), // Rule ID 7007 //
     /*  786608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode4),
     /*  786611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786626 */     // MIs[0] Operand 3
     /*  786626 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  786637 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  786637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
     /*  786640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786642 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786644 */     GIR_RootConstrainSelectedInstOperands,
     /*  786645 */     // GIR_Coverage, 7007,
     /*  786645 */     GIR_EraseRootFromParent_Done,
     /*  786646 */   // Label 12616: @786646
     /*  786646 */   GIM_Try, /*On fail goto*//*Label 12617*/ GIMT_Encode4(786701), // Rule ID 7008 //
     /*  786651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode0),
     /*  786654 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786659 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786669 */     // MIs[0] Operand 3
     /*  786669 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  786680 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  786680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa),
     /*  786683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786685 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786688 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  786699 */     GIR_RootConstrainSelectedInstOperands,
     /*  786700 */     // GIR_Coverage, 7008,
     /*  786700 */     GIR_EraseRootFromParent_Done,
     /*  786701 */   // Label 12617: @786701
     /*  786701 */   GIM_Try, /*On fail goto*//*Label 12618*/ GIMT_Encode4(786756), // Rule ID 7009 //
     /*  786706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode1),
     /*  786709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786724 */     // MIs[0] Operand 3
     /*  786724 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  786735 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  786735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa),
     /*  786738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786743 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  786754 */     GIR_RootConstrainSelectedInstOperands,
     /*  786755 */     // GIR_Coverage, 7009,
     /*  786755 */     GIR_EraseRootFromParent_Done,
     /*  786756 */   // Label 12618: @786756
     /*  786756 */   GIM_Try, /*On fail goto*//*Label 12619*/ GIMT_Encode4(786811), // Rule ID 7010 //
     /*  786761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode2),
     /*  786764 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786769 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786779 */     // MIs[0] Operand 3
     /*  786779 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  786790 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  786790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa),
     /*  786793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786798 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  786809 */     GIR_RootConstrainSelectedInstOperands,
     /*  786810 */     // GIR_Coverage, 7010,
     /*  786810 */     GIR_EraseRootFromParent_Done,
     /*  786811 */   // Label 12619: @786811
     /*  786811 */   GIM_Try, /*On fail goto*//*Label 12620*/ GIMT_Encode4(786866), // Rule ID 7011 //
     /*  786816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode3),
     /*  786819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786824 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786827 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786834 */     // MIs[0] Operand 3
     /*  786834 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  786845 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  786845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa),
     /*  786848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786853 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  786864 */     GIR_RootConstrainSelectedInstOperands,
     /*  786865 */     // GIR_Coverage, 7011,
     /*  786865 */     GIR_EraseRootFromParent_Done,
     /*  786866 */   // Label 12620: @786866
     /*  786866 */   GIM_Try, /*On fail goto*//*Label 12621*/ GIMT_Encode4(786921), // Rule ID 7012 //
     /*  786871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode4),
     /*  786874 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  786879 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786882 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786889 */     // MIs[0] Operand 3
     /*  786889 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  786900 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  786900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa),
     /*  786903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786908 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  786919 */     GIR_RootConstrainSelectedInstOperands,
     /*  786920 */     // GIR_Coverage, 7012,
     /*  786920 */     GIR_EraseRootFromParent_Done,
     /*  786921 */   // Label 12621: @786921
     /*  786921 */   GIM_Try, /*On fail goto*//*Label 12622*/ GIMT_Encode4(786976), // Rule ID 7013 //
     /*  786926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode0),
     /*  786929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786944 */     // MIs[0] Operand 3
     /*  786944 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  786955 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  786955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa),
     /*  786958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  786960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786963 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  786965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  786971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  786974 */     GIR_RootConstrainSelectedInstOperands,
     /*  786975 */     // GIR_Coverage, 7013,
     /*  786975 */     GIR_EraseRootFromParent_Done,
     /*  786976 */   // Label 12622: @786976
     /*  786976 */   GIM_Try, /*On fail goto*//*Label 12623*/ GIMT_Encode4(787031), // Rule ID 7014 //
     /*  786981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode1),
     /*  786984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  786989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  786992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  786995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  786999 */     // MIs[0] Operand 3
     /*  786999 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787010 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  787010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa),
     /*  787013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787018 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  787029 */     GIR_RootConstrainSelectedInstOperands,
     /*  787030 */     // GIR_Coverage, 7014,
     /*  787030 */     GIR_EraseRootFromParent_Done,
     /*  787031 */   // Label 12623: @787031
     /*  787031 */   GIM_Try, /*On fail goto*//*Label 12624*/ GIMT_Encode4(787086), // Rule ID 7015 //
     /*  787036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode2),
     /*  787039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787054 */     // MIs[0] Operand 3
     /*  787054 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787065 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  787065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa),
     /*  787068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787073 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  787084 */     GIR_RootConstrainSelectedInstOperands,
     /*  787085 */     // GIR_Coverage, 7015,
     /*  787085 */     GIR_EraseRootFromParent_Done,
     /*  787086 */   // Label 12624: @787086
     /*  787086 */   GIM_Try, /*On fail goto*//*Label 12625*/ GIMT_Encode4(787141), // Rule ID 7016 //
     /*  787091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode3),
     /*  787094 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787099 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787102 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787109 */     // MIs[0] Operand 3
     /*  787109 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787120 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  787120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa),
     /*  787123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787128 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  787139 */     GIR_RootConstrainSelectedInstOperands,
     /*  787140 */     // GIR_Coverage, 7016,
     /*  787140 */     GIR_EraseRootFromParent_Done,
     /*  787141 */   // Label 12625: @787141
     /*  787141 */   GIM_Try, /*On fail goto*//*Label 12626*/ GIMT_Encode4(787196), // Rule ID 7017 //
     /*  787146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasSDWA_HwMode4),
     /*  787149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787164 */     // MIs[0] Operand 3
     /*  787164 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787175 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
     /*  787175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa),
     /*  787178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787183 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
     /*  787194 */     GIR_RootConstrainSelectedInstOperands,
     /*  787195 */     // GIR_Coverage, 7017,
     /*  787195 */     GIR_EraseRootFromParent_Done,
     /*  787196 */   // Label 12626: @787196
     /*  787196 */   GIM_Try, /*On fail goto*//*Label 12627*/ GIMT_Encode4(787239), // Rule ID 7022 //
     /*  787201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode0),
     /*  787204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787219 */     // MIs[0] Operand 3
     /*  787219 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787230 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e32),
     /*  787233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787235 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787237 */     GIR_RootConstrainSelectedInstOperands,
     /*  787238 */     // GIR_Coverage, 7022,
     /*  787238 */     GIR_EraseRootFromParent_Done,
     /*  787239 */   // Label 12627: @787239
     /*  787239 */   GIM_Try, /*On fail goto*//*Label 12628*/ GIMT_Encode4(787282), // Rule ID 7023 //
     /*  787244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode1),
     /*  787247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787262 */     // MIs[0] Operand 3
     /*  787262 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787273 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e32),
     /*  787276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787278 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787280 */     GIR_RootConstrainSelectedInstOperands,
     /*  787281 */     // GIR_Coverage, 7023,
     /*  787281 */     GIR_EraseRootFromParent_Done,
     /*  787282 */   // Label 12628: @787282
     /*  787282 */   GIM_Try, /*On fail goto*//*Label 12629*/ GIMT_Encode4(787325), // Rule ID 7024 //
     /*  787287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode2),
     /*  787290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787298 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787305 */     // MIs[0] Operand 3
     /*  787305 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787316 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e32),
     /*  787319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787321 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787323 */     GIR_RootConstrainSelectedInstOperands,
     /*  787324 */     // GIR_Coverage, 7024,
     /*  787324 */     GIR_EraseRootFromParent_Done,
     /*  787325 */   // Label 12629: @787325
     /*  787325 */   GIM_Try, /*On fail goto*//*Label 12630*/ GIMT_Encode4(787368), // Rule ID 7025 //
     /*  787330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode3),
     /*  787333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787348 */     // MIs[0] Operand 3
     /*  787348 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787359 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e32),
     /*  787362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787364 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787366 */     GIR_RootConstrainSelectedInstOperands,
     /*  787367 */     // GIR_Coverage, 7025,
     /*  787367 */     GIR_EraseRootFromParent_Done,
     /*  787368 */   // Label 12630: @787368
     /*  787368 */   GIM_Try, /*On fail goto*//*Label 12631*/ GIMT_Encode4(787411), // Rule ID 7026 //
     /*  787373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode4),
     /*  787376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787391 */     // MIs[0] Operand 3
     /*  787391 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787402 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e32),
     /*  787405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787407 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787409 */     GIR_RootConstrainSelectedInstOperands,
     /*  787410 */     // GIR_Coverage, 7026,
     /*  787410 */     GIR_EraseRootFromParent_Done,
     /*  787411 */   // Label 12631: @787411
     /*  787411 */   GIM_Try, /*On fail goto*//*Label 12632*/ GIMT_Encode4(787454), // Rule ID 7027 //
     /*  787416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode0),
     /*  787419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787434 */     // MIs[0] Operand 3
     /*  787434 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787445 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e32),
     /*  787448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787450 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787452 */     GIR_RootConstrainSelectedInstOperands,
     /*  787453 */     // GIR_Coverage, 7027,
     /*  787453 */     GIR_EraseRootFromParent_Done,
     /*  787454 */   // Label 12632: @787454
     /*  787454 */   GIM_Try, /*On fail goto*//*Label 12633*/ GIMT_Encode4(787497), // Rule ID 7028 //
     /*  787459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode1),
     /*  787462 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787467 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787470 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787477 */     // MIs[0] Operand 3
     /*  787477 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787488 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e32),
     /*  787491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787493 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787495 */     GIR_RootConstrainSelectedInstOperands,
     /*  787496 */     // GIR_Coverage, 7028,
     /*  787496 */     GIR_EraseRootFromParent_Done,
     /*  787497 */   // Label 12633: @787497
     /*  787497 */   GIM_Try, /*On fail goto*//*Label 12634*/ GIMT_Encode4(787540), // Rule ID 7029 //
     /*  787502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode2),
     /*  787505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787520 */     // MIs[0] Operand 3
     /*  787520 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787531 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e32),
     /*  787534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787536 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787538 */     GIR_RootConstrainSelectedInstOperands,
     /*  787539 */     // GIR_Coverage, 7029,
     /*  787539 */     GIR_EraseRootFromParent_Done,
     /*  787540 */   // Label 12634: @787540
     /*  787540 */   GIM_Try, /*On fail goto*//*Label 12635*/ GIMT_Encode4(787583), // Rule ID 7030 //
     /*  787545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode3),
     /*  787548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787563 */     // MIs[0] Operand 3
     /*  787563 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787574 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e32),
     /*  787577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787579 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787581 */     GIR_RootConstrainSelectedInstOperands,
     /*  787582 */     // GIR_Coverage, 7030,
     /*  787582 */     GIR_EraseRootFromParent_Done,
     /*  787583 */   // Label 12635: @787583
     /*  787583 */   GIM_Try, /*On fail goto*//*Label 12636*/ GIMT_Encode4(787626), // Rule ID 7031 //
     /*  787588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode4),
     /*  787591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787606 */     // MIs[0] Operand 3
     /*  787606 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /*  787617 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
     /*  787617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e32),
     /*  787620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787622 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787624 */     GIR_RootConstrainSelectedInstOperands,
     /*  787625 */     // GIR_Coverage, 7031,
     /*  787625 */     GIR_EraseRootFromParent_Done,
     /*  787626 */   // Label 12636: @787626
     /*  787626 */   GIM_Try, /*On fail goto*//*Label 12637*/ GIMT_Encode4(787675), // Rule ID 7032 //
     /*  787631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode0),
     /*  787634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787649 */     // MIs[0] Operand 3
     /*  787649 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787660 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e64),
     /*  787663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787668 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787673 */     GIR_RootConstrainSelectedInstOperands,
     /*  787674 */     // GIR_Coverage, 7032,
     /*  787674 */     GIR_EraseRootFromParent_Done,
     /*  787675 */   // Label 12637: @787675
     /*  787675 */   GIM_Try, /*On fail goto*//*Label 12638*/ GIMT_Encode4(787724), // Rule ID 7033 //
     /*  787680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode1),
     /*  787683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787698 */     // MIs[0] Operand 3
     /*  787698 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787709 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e64),
     /*  787712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787717 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787722 */     GIR_RootConstrainSelectedInstOperands,
     /*  787723 */     // GIR_Coverage, 7033,
     /*  787723 */     GIR_EraseRootFromParent_Done,
     /*  787724 */   // Label 12638: @787724
     /*  787724 */   GIM_Try, /*On fail goto*//*Label 12639*/ GIMT_Encode4(787773), // Rule ID 7034 //
     /*  787729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode2),
     /*  787732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787747 */     // MIs[0] Operand 3
     /*  787747 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787758 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e64),
     /*  787761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787763 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787766 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787771 */     GIR_RootConstrainSelectedInstOperands,
     /*  787772 */     // GIR_Coverage, 7034,
     /*  787772 */     GIR_EraseRootFromParent_Done,
     /*  787773 */   // Label 12639: @787773
     /*  787773 */   GIM_Try, /*On fail goto*//*Label 12640*/ GIMT_Encode4(787822), // Rule ID 7035 //
     /*  787778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode3),
     /*  787781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787796 */     // MIs[0] Operand 3
     /*  787796 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787807 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e64),
     /*  787810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787815 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787820 */     GIR_RootConstrainSelectedInstOperands,
     /*  787821 */     // GIR_Coverage, 7035,
     /*  787821 */     GIR_EraseRootFromParent_Done,
     /*  787822 */   // Label 12640: @787822
     /*  787822 */   GIM_Try, /*On fail goto*//*Label 12641*/ GIMT_Encode4(787871), // Rule ID 7036 //
     /*  787827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode4),
     /*  787830 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
     /*  787835 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787838 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787845 */     // MIs[0] Operand 3
     /*  787845 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787856 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2282:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_fake16_e64),
     /*  787859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787864 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787869 */     GIR_RootConstrainSelectedInstOperands,
     /*  787870 */     // GIR_Coverage, 7036,
     /*  787870 */     GIR_EraseRootFromParent_Done,
     /*  787871 */   // Label 12641: @787871
     /*  787871 */   GIM_Try, /*On fail goto*//*Label 12642*/ GIMT_Encode4(787920), // Rule ID 7037 //
     /*  787876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode0),
     /*  787879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787894 */     // MIs[0] Operand 3
     /*  787894 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787905 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e64),
     /*  787908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787913 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787918 */     GIR_RootConstrainSelectedInstOperands,
     /*  787919 */     // GIR_Coverage, 7037,
     /*  787919 */     GIR_EraseRootFromParent_Done,
     /*  787920 */   // Label 12642: @787920
     /*  787920 */   GIM_Try, /*On fail goto*//*Label 12643*/ GIMT_Encode4(787969), // Rule ID 7038 //
     /*  787925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode1),
     /*  787928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787943 */     // MIs[0] Operand 3
     /*  787943 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  787954 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  787954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e64),
     /*  787957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  787959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  787962 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  787964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  787967 */     GIR_RootConstrainSelectedInstOperands,
     /*  787968 */     // GIR_Coverage, 7038,
     /*  787968 */     GIR_EraseRootFromParent_Done,
     /*  787969 */   // Label 12643: @787969
     /*  787969 */   GIM_Try, /*On fail goto*//*Label 12644*/ GIMT_Encode4(788018), // Rule ID 7039 //
     /*  787974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode2),
     /*  787977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  787982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  787985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  787988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  787992 */     // MIs[0] Operand 3
     /*  787992 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  788003 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  788003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e64),
     /*  788006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  788011 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  788013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788016 */     GIR_RootConstrainSelectedInstOperands,
     /*  788017 */     // GIR_Coverage, 7039,
     /*  788017 */     GIR_EraseRootFromParent_Done,
     /*  788018 */   // Label 12644: @788018
     /*  788018 */   GIM_Try, /*On fail goto*//*Label 12645*/ GIMT_Encode4(788067), // Rule ID 7040 //
     /*  788023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode3),
     /*  788026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  788031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  788034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  788041 */     // MIs[0] Operand 3
     /*  788041 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  788052 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  788052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e64),
     /*  788055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  788060 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  788062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788065 */     GIR_RootConstrainSelectedInstOperands,
     /*  788066 */     // GIR_Coverage, 7040,
     /*  788066 */     GIR_EraseRootFromParent_Done,
     /*  788067 */   // Label 12645: @788067
     /*  788067 */   GIM_Try, /*On fail goto*//*Label 12646*/ GIMT_Encode4(788116), // Rule ID 7041 //
     /*  788072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus_HwMode4),
     /*  788075 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
     /*  788080 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  788083 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  788090 */     // MIs[0] Operand 3
     /*  788090 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709551615u),
     /*  788101 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2281:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_fake16_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
     /*  788101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_fake16_e64),
     /*  788104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  788109 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  788111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788114 */     GIR_RootConstrainSelectedInstOperands,
     /*  788115 */     // GIR_Coverage, 7041,
     /*  788115 */     GIR_EraseRootFromParent_Done,
     /*  788116 */   // Label 12646: @788116
     /*  788116 */   GIM_Try, /*On fail goto*//*Label 12647*/ GIMT_Encode4(788157), // Rule ID 7018 //
     /*  788121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12PlusNot12_50),
     /*  788124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  788129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  788132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788139 */     // MIs[0] byte_sel
     /*  788139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788142 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F32_FP8_OP_SEL_e64:{ *:[f32] } ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_OP_SEL_e64),
     /*  788145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788147 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788149 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788155 */     GIR_RootConstrainSelectedInstOperands,
     /*  788156 */     // GIR_Coverage, 7018,
     /*  788156 */     GIR_EraseRootFromParent_Done,
     /*  788157 */   // Label 12647: @788157
     /*  788157 */   GIM_Try, /*On fail goto*//*Label 12648*/ GIMT_Encode4(788201), // Rule ID 7019 //
     /*  788162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX125xOnly),
     /*  788165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
     /*  788170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  788173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788180 */     // MIs[0] byte_sel
     /*  788180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788183 */     // (intrinsic_wo_chain:{ *:[f32] } 2274:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F32_FP8_gfx1250_e64:{ *:[f32] } ?:{ *:[i32] }:$src0, 0:{ *:[i1] }, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_gfx1250_e64),
     /*  788186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788188 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788193 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788199 */     GIR_RootConstrainSelectedInstOperands,
     /*  788200 */     // GIR_Coverage, 7019,
     /*  788200 */     GIR_EraseRootFromParent_Done,
     /*  788201 */   // Label 12648: @788201
     /*  788201 */   GIM_Try, /*On fail goto*//*Label 12649*/ GIMT_Encode4(788245), // Rule ID 7020 //
     /*  788206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX125xOnly),
     /*  788209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8_e5m3),
     /*  788214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  788217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788224 */     // MIs[0] byte_sel
     /*  788224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788227 */     // (intrinsic_wo_chain:{ *:[f32] } 2275:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F32_FP8_gfx1250_e64:{ *:[f32] } ?:{ *:[i32] }:$src0, 1:{ *:[i1] }, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_gfx1250_e64),
     /*  788230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788232 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  788237 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788243 */     GIR_RootConstrainSelectedInstOperands,
     /*  788244 */     // GIR_Coverage, 7020,
     /*  788244 */     GIR_EraseRootFromParent_Done,
     /*  788245 */   // Label 12649: @788245
     /*  788245 */   GIM_Try, /*On fail goto*//*Label 12650*/ GIMT_Encode4(788286), // Rule ID 7021 //
     /*  788250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus),
     /*  788253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
     /*  788258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  788261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788268 */     // MIs[0] byte_sel
     /*  788268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788271 */     // (intrinsic_wo_chain:{ *:[f32] } 2273:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F32_BF8_OP_SEL_e64:{ *:[f32] } ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_OP_SEL_e64),
     /*  788274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788276 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788278 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788284 */     GIR_RootConstrainSelectedInstOperands,
     /*  788285 */     // GIR_Coverage, 7021,
     /*  788285 */     GIR_EraseRootFromParent_Done,
     /*  788286 */   // Label 12650: @788286
     /*  788286 */   GIM_Try, /*On fail goto*//*Label 12651*/ GIMT_Encode4(788333), // Rule ID 7042 //
     /*  788291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  788294 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f16_fp8),
     /*  788299 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  788302 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  788309 */     // MIs[0] byte_sel
     /*  788309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788312 */     // (intrinsic_wo_chain:{ *:[f16] } 2272:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F16_FP8_t16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_FP8_t16_e64),
     /*  788315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788320 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788322 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788331 */     GIR_RootConstrainSelectedInstOperands,
     /*  788332 */     // GIR_Coverage, 7042,
     /*  788332 */     GIR_EraseRootFromParent_Done,
     /*  788333 */   // Label 12651: @788333
     /*  788333 */   GIM_Try, /*On fail goto*//*Label 12652*/ GIMT_Encode4(788380), // Rule ID 7043 //
     /*  788338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  788341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f16_bf8),
     /*  788346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  788349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  788356 */     // MIs[0] byte_sel
     /*  788356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788359 */     // (intrinsic_wo_chain:{ *:[f16] } 2271:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F16_BF8_t16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_BF8_t16_e64),
     /*  788362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788367 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788369 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788378 */     GIR_RootConstrainSelectedInstOperands,
     /*  788379 */     // GIR_Coverage, 7043,
     /*  788379 */     GIR_EraseRootFromParent_Done,
     /*  788380 */   // Label 12652: @788380
     /*  788380 */   GIM_Try, /*On fail goto*//*Label 12653*/ GIMT_Encode4(788427), // Rule ID 7044 //
     /*  788385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  788388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f16_fp8),
     /*  788393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  788396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788403 */     // MIs[0] byte_sel
     /*  788403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788406 */     // (intrinsic_wo_chain:{ *:[f16] } 2272:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F16_FP8_fake16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_FP8_fake16_e64),
     /*  788409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788414 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788416 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788425 */     GIR_RootConstrainSelectedInstOperands,
     /*  788426 */     // GIR_Coverage, 7044,
     /*  788426 */     GIR_EraseRootFromParent_Done,
     /*  788427 */   // Label 12653: @788427
     /*  788427 */   GIM_Try, /*On fail goto*//*Label 12654*/ GIMT_Encode4(788474), // Rule ID 7045 //
     /*  788432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  788435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f16_bf8),
     /*  788440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  788443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788450 */     // MIs[0] byte_sel
     /*  788450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  788453 */     // (intrinsic_wo_chain:{ *:[f16] } 2271:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_F16_BF8_fake16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  788453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_BF8_fake16_e64),
     /*  788456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788461 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788463 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  788469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  788472 */     GIR_RootConstrainSelectedInstOperands,
     /*  788473 */     // GIR_Coverage, 7045,
     /*  788473 */     GIR_EraseRootFromParent_Done,
     /*  788474 */   // Label 12654: @788474
     /*  788474 */   GIM_Try, /*On fail goto*//*Label 12655*/ GIMT_Encode4(788523), // Rule ID 109 //
     /*  788479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
     /*  788482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pkrtz),
     /*  788487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  788490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788493 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  788500 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  788504 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  788508 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20797),
     /*  788512 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2291:{ *:[iPTR] }, SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_20797>>  =>  (S_CVT_PK_RTZ_F16_F32:{ *:[v2f16] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
     /*  788512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_PK_RTZ_F16_F32),
     /*  788515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  788517 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  788519 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  788521 */     GIR_RootConstrainSelectedInstOperands,
     /*  788522 */     // GIR_Coverage, 109,
     /*  788522 */     GIR_EraseRootFromParent_Done,
     /*  788523 */   // Label 12655: @788523
     /*  788523 */   GIM_Try, /*On fail goto*//*Label 12656*/ GIMT_Encode4(788626), // Rule ID 7141 //
     /*  788528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*  788533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  788536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  788546 */     // (intrinsic_wo_chain:{ *:[i64] } 3333:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_I32_I24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub0:{ *:[i32] }, (V_MUL_HI_I32_I24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub1:{ *:[i32] })
     /*  788546 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  788549 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_I24_e64),
     /*  788553 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  788558 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src0
     /*  788562 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src1
     /*  788566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  788568 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  788571 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_I32_I24_e64),
     /*  788575 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  788580 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src0
     /*  788584 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src1
     /*  788588 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  788591 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  788593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  788596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  788598 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  788601 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  788604 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  788607 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  788610 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  788615 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788620 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788625 */     // GIR_Coverage, 7141,
     /*  788625 */     GIR_EraseRootFromParent_Done,
     /*  788626 */   // Label 12656: @788626
     /*  788626 */   GIM_Try, /*On fail goto*//*Label 12657*/ GIMT_Encode4(788729), // Rule ID 7143 //
     /*  788631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*  788636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  788639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  788649 */     // (intrinsic_wo_chain:{ *:[i64] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_U32_U24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub0:{ *:[i32] }, (V_MUL_HI_U32_U24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub1:{ *:[i32] })
     /*  788649 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  788652 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_U24_e64),
     /*  788656 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  788661 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src0
     /*  788665 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src1
     /*  788669 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  788671 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  788674 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U32_U24_e64),
     /*  788678 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  788683 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src0
     /*  788687 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src1
     /*  788691 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  788694 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  788696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  788699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  788701 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  788704 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  788707 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  788710 */     GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  788713 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  788718 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788723 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788728 */     // GIR_Coverage, 7143,
     /*  788728 */     GIR_EraseRootFromParent_Done,
     /*  788729 */   // Label 12657: @788729
     /*  788729 */   GIM_Try, /*On fail goto*//*Label 12658*/ GIMT_Encode4(788803), // Rule ID 2596 //
     /*  788734 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
     /*  788739 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  788742 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788745 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  788759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  788766 */     // (intrinsic_wo_chain:{ *:[f32] } 2458:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  788766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64),
     /*  788769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  788776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  788781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  788786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  788791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  788796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  788801 */     GIR_RootConstrainSelectedInstOperands,
     /*  788802 */     // GIR_Coverage, 2596,
     /*  788802 */     GIR_EraseRootFromParent_Done,
     /*  788803 */   // Label 12658: @788803
     /*  788803 */   GIM_Try, /*On fail goto*//*Label 12659*/ GIMT_Encode4(788875), // Rule ID 2635 //
     /*  788808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtPkNormVOP2Insts),
     /*  788811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pknorm_i16),
     /*  788816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  788819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788822 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788829 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  788836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  788843 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2289:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKNORM_I16_F32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
     /*  788843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKNORM_I16_F32_e64),
     /*  788846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  788853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  788858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  788863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  788868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  788873 */     GIR_RootConstrainSelectedInstOperands,
     /*  788874 */     // GIR_Coverage, 2635,
     /*  788874 */     GIR_EraseRootFromParent_Done,
     /*  788875 */   // Label 12659: @788875
     /*  788875 */   GIM_Try, /*On fail goto*//*Label 12660*/ GIMT_Encode4(788947), // Rule ID 2637 //
     /*  788880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtPkNormVOP2Insts),
     /*  788883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pknorm_u16),
     /*  788888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  788891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  788908 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  788915 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2290:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKNORM_U16_F32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
     /*  788915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKNORM_U16_F32_e64),
     /*  788918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  788925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  788930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  788935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  788940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  788945 */     GIR_RootConstrainSelectedInstOperands,
     /*  788946 */     // GIR_Coverage, 2637,
     /*  788946 */     GIR_EraseRootFromParent_Done,
     /*  788947 */   // Label 12660: @788947
     /*  788947 */   GIM_Try, /*On fail goto*//*Label 12661*/ GIMT_Encode4(789021), // Rule ID 2639 //
     /*  788952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pkrtz),
     /*  788957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  788960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  788963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  788966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  788970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  788977 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  788984 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2291:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKRTZ_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  788984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKRTZ_F16_F32_e64),
     /*  788987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  788989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  788994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  788999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  789004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  789009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  789014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  789019 */     GIR_RootConstrainSelectedInstOperands,
     /*  789020 */     // GIR_Coverage, 2639,
     /*  789020 */     GIR_EraseRootFromParent_Done,
     /*  789021 */   // Label 12661: @789021
     /*  789021 */   GIM_Try, /*On fail goto*//*Label 12662*/ GIMT_Encode4(789098), // Rule ID 2926 //
     /*  789026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  789029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop),
     /*  789034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  789037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  789040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  789047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  789061 */     // (intrinsic_wo_chain:{ *:[f64] } 3606:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  789061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64),
     /*  789064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  789071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  789081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  789086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  789091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  789096 */     GIR_RootConstrainSelectedInstOperands,
     /*  789097 */     // GIR_Coverage, 2926,
     /*  789097 */     GIR_EraseRootFromParent_Done,
     /*  789098 */   // Label 12662: @789098
     /*  789098 */   GIM_Try, /*On fail goto*//*Label 12663*/ GIMT_Encode4(789175), // Rule ID 2927 //
     /*  789103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  789106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop),
     /*  789111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  789114 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  789117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  789124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789131 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  789138 */     // (intrinsic_wo_chain:{ *:[f64] } 3606:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  789138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64),
     /*  789141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  789148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  789158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  789163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  789168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  789173 */     GIR_RootConstrainSelectedInstOperands,
     /*  789174 */     // GIR_Coverage, 2927,
     /*  789174 */     GIR_EraseRootFromParent_Done,
     /*  789175 */   // Label 12663: @789175
     /*  789175 */   GIM_Try, /*On fail goto*//*Label 12664*/ GIMT_Encode4(789252), // Rule ID 2928 //
     /*  789180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  789183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop),
     /*  789188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  789191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  789194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  789201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789208 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  789215 */     // (intrinsic_wo_chain:{ *:[f64] } 3606:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  789215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64),
     /*  789218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  789225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  789235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  789240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  789245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  789250 */     GIR_RootConstrainSelectedInstOperands,
     /*  789251 */     // GIR_Coverage, 2928,
     /*  789251 */     GIR_EraseRootFromParent_Done,
     /*  789252 */   // Label 12664: @789252
     /*  789252 */   GIM_Try, /*On fail goto*//*Label 12665*/ GIMT_Encode4(789329), // Rule ID 2929 //
     /*  789257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  789260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop),
     /*  789265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  789268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  789271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  789278 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789285 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  789292 */     // (intrinsic_wo_chain:{ *:[f64] } 3606:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  789292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64),
     /*  789295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  789302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  789312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  789317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  789322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  789327 */     GIR_RootConstrainSelectedInstOperands,
     /*  789328 */     // GIR_Coverage, 2929,
     /*  789328 */     GIR_EraseRootFromParent_Done,
     /*  789329 */   // Label 12665: @789329
     /*  789329 */   GIM_Try, /*On fail goto*//*Label 12666*/ GIMT_Encode4(789406), // Rule ID 2930 //
     /*  789334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  789337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop),
     /*  789342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  789345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  789348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  789355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  789369 */     // (intrinsic_wo_chain:{ *:[f64] } 3606:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  789369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64),
     /*  789372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  789379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  789389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  789394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  789399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  789404 */     GIR_RootConstrainSelectedInstOperands,
     /*  789405 */     // GIR_Coverage, 2930,
     /*  789405 */     GIR_EraseRootFromParent_Done,
     /*  789406 */   // Label 12666: @789406
     /*  789406 */   GIM_Try, /*On fail goto*//*Label 12667*/ GIMT_Encode4(789480), // Rule ID 31170 //
     /*  789411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
     /*  789416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  789419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  789422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  789429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  789436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789443 */     // (intrinsic_wo_chain:{ *:[f32] } 2458:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  789443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64),
     /*  789446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  789453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  789458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /*  789463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /*  789468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
     /*  789473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
     /*  789478 */     GIR_RootConstrainSelectedInstOperands,
     /*  789479 */     // GIR_Coverage, 31170,
     /*  789479 */     GIR_EraseRootFromParent_Done,
     /*  789480 */   // Label 12667: @789480
     /*  789480 */   GIM_Try, /*On fail goto*//*Label 12668*/ GIMT_Encode4(789527), // Rule ID 3054 //
     /*  789485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode0),
     /*  789488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_fp6),
     /*  789493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789499 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789506 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789513 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2344:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_FP6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_e64),
     /*  789516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789523 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789525 */     GIR_RootConstrainSelectedInstOperands,
     /*  789526 */     // GIR_Coverage, 3054,
     /*  789526 */     GIR_EraseRootFromParent_Done,
     /*  789527 */   // Label 12668: @789527
     /*  789527 */   GIM_Try, /*On fail goto*//*Label 12669*/ GIMT_Encode4(789574), // Rule ID 3055 //
     /*  789532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode1),
     /*  789535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_fp6),
     /*  789540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789560 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2344:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_FP6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_e64),
     /*  789563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789570 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789572 */     GIR_RootConstrainSelectedInstOperands,
     /*  789573 */     // GIR_Coverage, 3055,
     /*  789573 */     GIR_EraseRootFromParent_Done,
     /*  789574 */   // Label 12669: @789574
     /*  789574 */   GIM_Try, /*On fail goto*//*Label 12670*/ GIMT_Encode4(789621), // Rule ID 3056 //
     /*  789579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode2),
     /*  789582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_fp6),
     /*  789587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789607 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2344:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_FP6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_e64),
     /*  789610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789617 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789619 */     GIR_RootConstrainSelectedInstOperands,
     /*  789620 */     // GIR_Coverage, 3056,
     /*  789620 */     GIR_EraseRootFromParent_Done,
     /*  789621 */   // Label 12670: @789621
     /*  789621 */   GIM_Try, /*On fail goto*//*Label 12671*/ GIMT_Encode4(789668), // Rule ID 3057 //
     /*  789626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode3),
     /*  789629 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_fp6),
     /*  789634 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789637 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789640 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789654 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2344:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_FP6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_e64),
     /*  789657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789664 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789666 */     GIR_RootConstrainSelectedInstOperands,
     /*  789667 */     // GIR_Coverage, 3057,
     /*  789667 */     GIR_EraseRootFromParent_Done,
     /*  789668 */   // Label 12671: @789668
     /*  789668 */   GIM_Try, /*On fail goto*//*Label 12672*/ GIMT_Encode4(789715), // Rule ID 3058 //
     /*  789673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode4),
     /*  789676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_fp6),
     /*  789681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789701 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2344:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_FP6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_FP6_e64),
     /*  789704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789711 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789713 */     GIR_RootConstrainSelectedInstOperands,
     /*  789714 */     // GIR_Coverage, 3058,
     /*  789714 */     GIR_EraseRootFromParent_Done,
     /*  789715 */   // Label 12672: @789715
     /*  789715 */   GIM_Try, /*On fail goto*//*Label 12673*/ GIMT_Encode4(789762), // Rule ID 3059 //
     /*  789720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode0),
     /*  789723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_bf6),
     /*  789728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789741 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789748 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2343:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_BF6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_e64),
     /*  789751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789758 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789760 */     GIR_RootConstrainSelectedInstOperands,
     /*  789761 */     // GIR_Coverage, 3059,
     /*  789761 */     GIR_EraseRootFromParent_Done,
     /*  789762 */   // Label 12673: @789762
     /*  789762 */   GIM_Try, /*On fail goto*//*Label 12674*/ GIMT_Encode4(789809), // Rule ID 3060 //
     /*  789767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode1),
     /*  789770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_bf6),
     /*  789775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789795 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2343:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_BF6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_e64),
     /*  789798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789805 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789807 */     GIR_RootConstrainSelectedInstOperands,
     /*  789808 */     // GIR_Coverage, 3060,
     /*  789808 */     GIR_EraseRootFromParent_Done,
     /*  789809 */   // Label 12674: @789809
     /*  789809 */   GIM_Try, /*On fail goto*//*Label 12675*/ GIMT_Encode4(789856), // Rule ID 3061 //
     /*  789814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode2),
     /*  789817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_bf6),
     /*  789822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789825 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789828 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789835 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789842 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2343:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_BF6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_e64),
     /*  789845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789852 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789854 */     GIR_RootConstrainSelectedInstOperands,
     /*  789855 */     // GIR_Coverage, 3061,
     /*  789855 */     GIR_EraseRootFromParent_Done,
     /*  789856 */   // Label 12675: @789856
     /*  789856 */   GIM_Try, /*On fail goto*//*Label 12676*/ GIMT_Encode4(789903), // Rule ID 3062 //
     /*  789861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode3),
     /*  789864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_bf6),
     /*  789869 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789875 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789889 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2343:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_BF6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_e64),
     /*  789892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789899 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789901 */     GIR_RootConstrainSelectedInstOperands,
     /*  789902 */     // GIR_Coverage, 3062,
     /*  789902 */     GIR_EraseRootFromParent_Done,
     /*  789903 */   // Label 12676: @789903
     /*  789903 */   GIM_Try, /*On fail goto*//*Label 12677*/ GIMT_Encode4(789950), // Rule ID 3063 //
     /*  789908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode4),
     /*  789911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f32_bf6),
     /*  789916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  789919 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789922 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  789929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789936 */     // (intrinsic_wo_chain:{ *:[v32f32] } 2343:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F32_BF6_e64:{ *:[v32f32] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F32_BF6_e64),
     /*  789939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789948 */     GIR_RootConstrainSelectedInstOperands,
     /*  789949 */     // GIR_Coverage, 3063,
     /*  789949 */     GIR_EraseRootFromParent_Done,
     /*  789950 */   // Label 12677: @789950
     /*  789950 */   GIM_Try, /*On fail goto*//*Label 12678*/ GIMT_Encode4(789997), // Rule ID 3064 //
     /*  789955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode0),
     /*  789958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_fp6),
     /*  789963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  789966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  789969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  789972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  789976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  789983 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2342:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_FP6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  789983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_e64),
     /*  789986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  789988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  789993 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  789995 */     GIR_RootConstrainSelectedInstOperands,
     /*  789996 */     // GIR_Coverage, 3064,
     /*  789996 */     GIR_EraseRootFromParent_Done,
     /*  789997 */   // Label 12678: @789997
     /*  789997 */   GIM_Try, /*On fail goto*//*Label 12679*/ GIMT_Encode4(790044), // Rule ID 3065 //
     /*  790002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode1),
     /*  790005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_fp6),
     /*  790010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790016 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790023 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790030 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2342:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_FP6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_e64),
     /*  790033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790040 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790042 */     GIR_RootConstrainSelectedInstOperands,
     /*  790043 */     // GIR_Coverage, 3065,
     /*  790043 */     GIR_EraseRootFromParent_Done,
     /*  790044 */   // Label 12679: @790044
     /*  790044 */   GIM_Try, /*On fail goto*//*Label 12680*/ GIMT_Encode4(790091), // Rule ID 3066 //
     /*  790049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode2),
     /*  790052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_fp6),
     /*  790057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790070 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790077 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2342:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_FP6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_e64),
     /*  790080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790087 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790089 */     GIR_RootConstrainSelectedInstOperands,
     /*  790090 */     // GIR_Coverage, 3066,
     /*  790090 */     GIR_EraseRootFromParent_Done,
     /*  790091 */   // Label 12680: @790091
     /*  790091 */   GIM_Try, /*On fail goto*//*Label 12681*/ GIMT_Encode4(790138), // Rule ID 3067 //
     /*  790096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode3),
     /*  790099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_fp6),
     /*  790104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790110 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790124 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2342:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_FP6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_e64),
     /*  790127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790134 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790136 */     GIR_RootConstrainSelectedInstOperands,
     /*  790137 */     // GIR_Coverage, 3067,
     /*  790137 */     GIR_EraseRootFromParent_Done,
     /*  790138 */   // Label 12681: @790138
     /*  790138 */   GIM_Try, /*On fail goto*//*Label 12682*/ GIMT_Encode4(790185), // Rule ID 3068 //
     /*  790143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode4),
     /*  790146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_fp6),
     /*  790151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790171 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2342:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_FP6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_FP6_e64),
     /*  790174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790181 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790183 */     GIR_RootConstrainSelectedInstOperands,
     /*  790184 */     // GIR_Coverage, 3068,
     /*  790184 */     GIR_EraseRootFromParent_Done,
     /*  790185 */   // Label 12682: @790185
     /*  790185 */   GIM_Try, /*On fail goto*//*Label 12683*/ GIMT_Encode4(790232), // Rule ID 3069 //
     /*  790190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode0),
     /*  790193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_bf6),
     /*  790198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790218 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2341:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_BF6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_e64),
     /*  790221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790228 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790230 */     GIR_RootConstrainSelectedInstOperands,
     /*  790231 */     // GIR_Coverage, 3069,
     /*  790231 */     GIR_EraseRootFromParent_Done,
     /*  790232 */   // Label 12683: @790232
     /*  790232 */   GIM_Try, /*On fail goto*//*Label 12684*/ GIMT_Encode4(790279), // Rule ID 3070 //
     /*  790237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode1),
     /*  790240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_bf6),
     /*  790245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790251 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790258 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790265 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2341:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_BF6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_e64),
     /*  790268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790270 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790275 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790277 */     GIR_RootConstrainSelectedInstOperands,
     /*  790278 */     // GIR_Coverage, 3070,
     /*  790278 */     GIR_EraseRootFromParent_Done,
     /*  790279 */   // Label 12684: @790279
     /*  790279 */   GIM_Try, /*On fail goto*//*Label 12685*/ GIMT_Encode4(790326), // Rule ID 3071 //
     /*  790284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode2),
     /*  790287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_bf6),
     /*  790292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790298 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790312 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2341:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_BF6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_e64),
     /*  790315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790322 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790324 */     GIR_RootConstrainSelectedInstOperands,
     /*  790325 */     // GIR_Coverage, 3071,
     /*  790325 */     GIR_EraseRootFromParent_Done,
     /*  790326 */   // Label 12685: @790326
     /*  790326 */   GIM_Try, /*On fail goto*//*Label 12686*/ GIMT_Encode4(790373), // Rule ID 3072 //
     /*  790331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode3),
     /*  790334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_bf6),
     /*  790339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790359 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2341:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_BF6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_e64),
     /*  790362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790369 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790371 */     GIR_RootConstrainSelectedInstOperands,
     /*  790372 */     // GIR_Coverage, 3072,
     /*  790372 */     GIR_EraseRootFromParent_Done,
     /*  790373 */   // Label 12686: @790373
     /*  790373 */   GIM_Try, /*On fail goto*//*Label 12687*/ GIMT_Encode4(790420), // Rule ID 3073 //
     /*  790378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP6BF6ConversionScaleInsts_HwMode4),
     /*  790381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_f16_bf6),
     /*  790386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s16,
     /*  790389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  790392 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  790399 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790406 */     // (intrinsic_wo_chain:{ *:[v32f16] } 2341:{ *:[iPTR] }, (VOP3Mods0:{ *:[v6i32] } v6i32:{ *:[v6i32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_F16_BF6_e64:{ *:[v32f16] } v6i32:{ *:[v6i32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_F16_BF6_e64),
     /*  790409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790416 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790418 */     GIR_RootConstrainSelectedInstOperands,
     /*  790419 */     // GIR_Coverage, 3073,
     /*  790419 */     GIR_EraseRootFromParent_Done,
     /*  790420 */   // Label 12687: @790420
     /*  790420 */   GIM_Try, /*On fail goto*//*Label 12688*/ GIMT_Encode4(790467), // Rule ID 3074 //
     /*  790425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0),
     /*  790428 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_fp6_f16),
     /*  790433 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790446 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790453 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2346:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_e64),
     /*  790456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790463 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790465 */     GIR_RootConstrainSelectedInstOperands,
     /*  790466 */     // GIR_Coverage, 3074,
     /*  790466 */     GIR_EraseRootFromParent_Done,
     /*  790467 */   // Label 12688: @790467
     /*  790467 */   GIM_Try, /*On fail goto*//*Label 12689*/ GIMT_Encode4(790514), // Rule ID 3075 //
     /*  790472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1),
     /*  790475 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_fp6_f16),
     /*  790480 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790483 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790486 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790493 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790500 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2346:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_e64),
     /*  790503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790510 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790512 */     GIR_RootConstrainSelectedInstOperands,
     /*  790513 */     // GIR_Coverage, 3075,
     /*  790513 */     GIR_EraseRootFromParent_Done,
     /*  790514 */   // Label 12689: @790514
     /*  790514 */   GIM_Try, /*On fail goto*//*Label 12690*/ GIMT_Encode4(790561), // Rule ID 3076 //
     /*  790519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2),
     /*  790522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_fp6_f16),
     /*  790527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790547 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2346:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_e64),
     /*  790550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790557 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790559 */     GIR_RootConstrainSelectedInstOperands,
     /*  790560 */     // GIR_Coverage, 3076,
     /*  790560 */     GIR_EraseRootFromParent_Done,
     /*  790561 */   // Label 12690: @790561
     /*  790561 */   GIM_Try, /*On fail goto*//*Label 12691*/ GIMT_Encode4(790608), // Rule ID 3077 //
     /*  790566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3),
     /*  790569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_fp6_f16),
     /*  790574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790594 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2346:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_e64),
     /*  790597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790604 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790606 */     GIR_RootConstrainSelectedInstOperands,
     /*  790607 */     // GIR_Coverage, 3077,
     /*  790607 */     GIR_EraseRootFromParent_Done,
     /*  790608 */   // Label 12691: @790608
     /*  790608 */   GIM_Try, /*On fail goto*//*Label 12692*/ GIMT_Encode4(790655), // Rule ID 3078 //
     /*  790613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4),
     /*  790616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_fp6_f16),
     /*  790621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790641 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2346:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_FP6_F16_e64),
     /*  790644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790651 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790653 */     GIR_RootConstrainSelectedInstOperands,
     /*  790654 */     // GIR_Coverage, 3078,
     /*  790654 */     GIR_EraseRootFromParent_Done,
     /*  790655 */   // Label 12692: @790655
     /*  790655 */   GIM_Try, /*On fail goto*//*Label 12693*/ GIMT_Encode4(790702), // Rule ID 3079 //
     /*  790660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0),
     /*  790663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_bf6_f16),
     /*  790668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790688 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2340:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_e64),
     /*  790691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790698 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790700 */     GIR_RootConstrainSelectedInstOperands,
     /*  790701 */     // GIR_Coverage, 3079,
     /*  790701 */     GIR_EraseRootFromParent_Done,
     /*  790702 */   // Label 12693: @790702
     /*  790702 */   GIM_Try, /*On fail goto*//*Label 12694*/ GIMT_Encode4(790749), // Rule ID 3080 //
     /*  790707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1),
     /*  790710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_bf6_f16),
     /*  790715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790735 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2340:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_e64),
     /*  790738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790745 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790747 */     GIR_RootConstrainSelectedInstOperands,
     /*  790748 */     // GIR_Coverage, 3080,
     /*  790748 */     GIR_EraseRootFromParent_Done,
     /*  790749 */   // Label 12694: @790749
     /*  790749 */   GIM_Try, /*On fail goto*//*Label 12695*/ GIMT_Encode4(790796), // Rule ID 3081 //
     /*  790754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2),
     /*  790757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_bf6_f16),
     /*  790762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790768 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790782 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2340:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_e64),
     /*  790785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790792 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790794 */     GIR_RootConstrainSelectedInstOperands,
     /*  790795 */     // GIR_Coverage, 3081,
     /*  790795 */     GIR_EraseRootFromParent_Done,
     /*  790796 */   // Label 12695: @790796
     /*  790796 */   GIM_Try, /*On fail goto*//*Label 12696*/ GIMT_Encode4(790843), // Rule ID 3082 //
     /*  790801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3),
     /*  790804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_bf6_f16),
     /*  790809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790822 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790829 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2340:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_e64),
     /*  790832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790834 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790839 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790841 */     GIR_RootConstrainSelectedInstOperands,
     /*  790842 */     // GIR_Coverage, 3082,
     /*  790842 */     GIR_EraseRootFromParent_Done,
     /*  790843 */   // Label 12696: @790843
     /*  790843 */   GIM_Try, /*On fail goto*//*Label 12697*/ GIMT_Encode4(790890), // Rule ID 3083 //
     /*  790848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4),
     /*  790851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk32_bf6_f16),
     /*  790856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  790859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  790862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  790869 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790876 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2340:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK32_BF6_F16_e64),
     /*  790879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790886 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790888 */     GIR_RootConstrainSelectedInstOperands,
     /*  790889 */     // GIR_Coverage, 3083,
     /*  790889 */     GIR_EraseRootFromParent_Done,
     /*  790890 */   // Label 12697: @790890
     /*  790890 */   GIM_Try, /*On fail goto*//*Label 12698*/ GIMT_Encode4(790937), // Rule ID 3177 //
     /*  790895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  790898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f16),
     /*  790903 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  790906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  790909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  790916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790923 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2354:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64),
     /*  790926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790933 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790935 */     GIR_RootConstrainSelectedInstOperands,
     /*  790936 */     // GIR_Coverage, 3177,
     /*  790936 */     GIR_EraseRootFromParent_Done,
     /*  790937 */   // Label 12698: @790937
     /*  790937 */   GIM_Try, /*On fail goto*//*Label 12699*/ GIMT_Encode4(790984), // Rule ID 3178 //
     /*  790942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  790945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f16),
     /*  790950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  790953 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  790956 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  790959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  790963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  790970 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2354:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  790970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64),
     /*  790973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  790975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  790980 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  790982 */     GIR_RootConstrainSelectedInstOperands,
     /*  790983 */     // GIR_Coverage, 3178,
     /*  790983 */     GIR_EraseRootFromParent_Done,
     /*  790984 */   // Label 12699: @790984
     /*  790984 */   GIM_Try, /*On fail goto*//*Label 12700*/ GIMT_Encode4(791031), // Rule ID 3179 //
     /*  790989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  790992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f16),
     /*  790997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791010 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791017 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2354:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64),
     /*  791020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791027 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791029 */     GIR_RootConstrainSelectedInstOperands,
     /*  791030 */     // GIR_Coverage, 3179,
     /*  791030 */     GIR_EraseRootFromParent_Done,
     /*  791031 */   // Label 12700: @791031
     /*  791031 */   GIM_Try, /*On fail goto*//*Label 12701*/ GIMT_Encode4(791078), // Rule ID 3180 //
     /*  791036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  791039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f16),
     /*  791044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791050 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791064 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2354:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64),
     /*  791067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791074 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791076 */     GIR_RootConstrainSelectedInstOperands,
     /*  791077 */     // GIR_Coverage, 3180,
     /*  791077 */     GIR_EraseRootFromParent_Done,
     /*  791078 */   // Label 12701: @791078
     /*  791078 */   GIM_Try, /*On fail goto*//*Label 12702*/ GIMT_Encode4(791125), // Rule ID 3181 //
     /*  791083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  791086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f16),
     /*  791091 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791094 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791097 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791111 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2354:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F16_e64),
     /*  791114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791121 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791123 */     GIR_RootConstrainSelectedInstOperands,
     /*  791124 */     // GIR_Coverage, 3181,
     /*  791124 */     GIR_EraseRootFromParent_Done,
     /*  791125 */   // Label 12702: @791125
     /*  791125 */   GIM_Try, /*On fail goto*//*Label 12703*/ GIMT_Encode4(791172), // Rule ID 3182 //
     /*  791130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  791133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f16),
     /*  791138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791158 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2348:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64),
     /*  791161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791168 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791170 */     GIR_RootConstrainSelectedInstOperands,
     /*  791171 */     // GIR_Coverage, 3182,
     /*  791171 */     GIR_EraseRootFromParent_Done,
     /*  791172 */   // Label 12703: @791172
     /*  791172 */   GIM_Try, /*On fail goto*//*Label 12704*/ GIMT_Encode4(791219), // Rule ID 3183 //
     /*  791177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  791180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f16),
     /*  791185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791205 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2348:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64),
     /*  791208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791215 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791217 */     GIR_RootConstrainSelectedInstOperands,
     /*  791218 */     // GIR_Coverage, 3183,
     /*  791218 */     GIR_EraseRootFromParent_Done,
     /*  791219 */   // Label 12704: @791219
     /*  791219 */   GIM_Try, /*On fail goto*//*Label 12705*/ GIMT_Encode4(791266), // Rule ID 3184 //
     /*  791224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  791227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f16),
     /*  791232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791252 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2348:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64),
     /*  791255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791262 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791264 */     GIR_RootConstrainSelectedInstOperands,
     /*  791265 */     // GIR_Coverage, 3184,
     /*  791265 */     GIR_EraseRootFromParent_Done,
     /*  791266 */   // Label 12705: @791266
     /*  791266 */   GIM_Try, /*On fail goto*//*Label 12706*/ GIMT_Encode4(791313), // Rule ID 3185 //
     /*  791271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  791274 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f16),
     /*  791279 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791282 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791285 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791299 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2348:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64),
     /*  791302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791309 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791311 */     GIR_RootConstrainSelectedInstOperands,
     /*  791312 */     // GIR_Coverage, 3185,
     /*  791312 */     GIR_EraseRootFromParent_Done,
     /*  791313 */   // Label 12706: @791313
     /*  791313 */   GIM_Try, /*On fail goto*//*Label 12707*/ GIMT_Encode4(791360), // Rule ID 3186 //
     /*  791318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  791321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f16),
     /*  791326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  791332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791339 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791346 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2348:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F16_e64),
     /*  791349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791356 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791358 */     GIR_RootConstrainSelectedInstOperands,
     /*  791359 */     // GIR_Coverage, 3186,
     /*  791359 */     GIR_EraseRootFromParent_Done,
     /*  791360 */   // Label 12707: @791360
     /*  791360 */   GIM_Try, /*On fail goto*//*Label 12708*/ GIMT_Encode4(791407), // Rule ID 3187 //
     /*  791365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  791368 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f32),
     /*  791373 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791376 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791379 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791393 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2355:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64),
     /*  791396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791403 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791405 */     GIR_RootConstrainSelectedInstOperands,
     /*  791406 */     // GIR_Coverage, 3187,
     /*  791406 */     GIR_EraseRootFromParent_Done,
     /*  791407 */   // Label 12708: @791407
     /*  791407 */   GIM_Try, /*On fail goto*//*Label 12709*/ GIMT_Encode4(791454), // Rule ID 3188 //
     /*  791412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  791415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f32),
     /*  791420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791426 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791440 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2355:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64),
     /*  791443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791450 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791452 */     GIR_RootConstrainSelectedInstOperands,
     /*  791453 */     // GIR_Coverage, 3188,
     /*  791453 */     GIR_EraseRootFromParent_Done,
     /*  791454 */   // Label 12709: @791454
     /*  791454 */   GIM_Try, /*On fail goto*//*Label 12710*/ GIMT_Encode4(791501), // Rule ID 3189 //
     /*  791459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  791462 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f32),
     /*  791467 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791470 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791473 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791480 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791487 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2355:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64),
     /*  791490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791497 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791499 */     GIR_RootConstrainSelectedInstOperands,
     /*  791500 */     // GIR_Coverage, 3189,
     /*  791500 */     GIR_EraseRootFromParent_Done,
     /*  791501 */   // Label 12710: @791501
     /*  791501 */   GIM_Try, /*On fail goto*//*Label 12711*/ GIMT_Encode4(791548), // Rule ID 3190 //
     /*  791506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  791509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f32),
     /*  791514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791534 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2355:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64),
     /*  791537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791544 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791546 */     GIR_RootConstrainSelectedInstOperands,
     /*  791547 */     // GIR_Coverage, 3190,
     /*  791547 */     GIR_EraseRootFromParent_Done,
     /*  791548 */   // Label 12711: @791548
     /*  791548 */   GIM_Try, /*On fail goto*//*Label 12712*/ GIMT_Encode4(791595), // Rule ID 3191 //
     /*  791553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  791556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp8_f32),
     /*  791561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791574 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791581 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2355:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP8_F32_e64),
     /*  791584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791591 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791593 */     GIR_RootConstrainSelectedInstOperands,
     /*  791594 */     // GIR_Coverage, 3191,
     /*  791594 */     GIR_EraseRootFromParent_Done,
     /*  791595 */   // Label 12712: @791595
     /*  791595 */   GIM_Try, /*On fail goto*//*Label 12713*/ GIMT_Encode4(791642), // Rule ID 3192 //
     /*  791600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  791603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f32),
     /*  791608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791628 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2349:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64),
     /*  791631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791638 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791640 */     GIR_RootConstrainSelectedInstOperands,
     /*  791641 */     // GIR_Coverage, 3192,
     /*  791641 */     GIR_EraseRootFromParent_Done,
     /*  791642 */   // Label 12713: @791642
     /*  791642 */   GIM_Try, /*On fail goto*//*Label 12714*/ GIMT_Encode4(791689), // Rule ID 3193 //
     /*  791647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  791650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f32),
     /*  791655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791675 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2349:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64),
     /*  791678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791685 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791687 */     GIR_RootConstrainSelectedInstOperands,
     /*  791688 */     // GIR_Coverage, 3193,
     /*  791688 */     GIR_EraseRootFromParent_Done,
     /*  791689 */   // Label 12714: @791689
     /*  791689 */   GIM_Try, /*On fail goto*//*Label 12715*/ GIMT_Encode4(791736), // Rule ID 3194 //
     /*  791694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  791697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f32),
     /*  791702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791715 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791722 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2349:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64),
     /*  791725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791732 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791734 */     GIR_RootConstrainSelectedInstOperands,
     /*  791735 */     // GIR_Coverage, 3194,
     /*  791735 */     GIR_EraseRootFromParent_Done,
     /*  791736 */   // Label 12715: @791736
     /*  791736 */   GIM_Try, /*On fail goto*//*Label 12716*/ GIMT_Encode4(791783), // Rule ID 3195 //
     /*  791741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  791744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f32),
     /*  791749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791755 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791762 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791769 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2349:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64),
     /*  791772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791774 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791781 */     GIR_RootConstrainSelectedInstOperands,
     /*  791782 */     // GIR_Coverage, 3195,
     /*  791782 */     GIR_EraseRootFromParent_Done,
     /*  791783 */   // Label 12716: @791783
     /*  791783 */   GIM_Try, /*On fail goto*//*Label 12717*/ GIMT_Encode4(791830), // Rule ID 3196 //
     /*  791788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  791791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_bf8_f32),
     /*  791796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  791799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  791809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791816 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2349:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_BF8_F32_e64),
     /*  791819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791826 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791828 */     GIR_RootConstrainSelectedInstOperands,
     /*  791829 */     // GIR_Coverage, 3196,
     /*  791829 */     GIR_EraseRootFromParent_Done,
     /*  791830 */   // Label 12717: @791830
     /*  791830 */   GIM_Try, /*On fail goto*//*Label 12718*/ GIMT_Encode4(791877), // Rule ID 3197 //
     /*  791835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  791838 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f32),
     /*  791843 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  791846 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791849 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  791856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791863 */     // (intrinsic_wo_chain:{ *:[i32] } 2352:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64),
     /*  791866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791873 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791875 */     GIR_RootConstrainSelectedInstOperands,
     /*  791876 */     // GIR_Coverage, 3197,
     /*  791876 */     GIR_EraseRootFromParent_Done,
     /*  791877 */   // Label 12718: @791877
     /*  791877 */   GIM_Try, /*On fail goto*//*Label 12719*/ GIMT_Encode4(791924), // Rule ID 3198 //
     /*  791882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  791885 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f32),
     /*  791890 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  791893 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791896 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  791903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791910 */     // (intrinsic_wo_chain:{ *:[i32] } 2352:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64),
     /*  791913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791920 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791922 */     GIR_RootConstrainSelectedInstOperands,
     /*  791923 */     // GIR_Coverage, 3198,
     /*  791923 */     GIR_EraseRootFromParent_Done,
     /*  791924 */   // Label 12719: @791924
     /*  791924 */   GIM_Try, /*On fail goto*//*Label 12720*/ GIMT_Encode4(791971), // Rule ID 3199 //
     /*  791929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  791932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f32),
     /*  791937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  791940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  791950 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  791957 */     // (intrinsic_wo_chain:{ *:[i32] } 2352:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  791957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64),
     /*  791960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  791962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  791967 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  791969 */     GIR_RootConstrainSelectedInstOperands,
     /*  791970 */     // GIR_Coverage, 3199,
     /*  791970 */     GIR_EraseRootFromParent_Done,
     /*  791971 */   // Label 12720: @791971
     /*  791971 */   GIM_Try, /*On fail goto*//*Label 12721*/ GIMT_Encode4(792018), // Rule ID 3200 //
     /*  791976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  791979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f32),
     /*  791984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  791987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  791990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  791993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  791997 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792004 */     // (intrinsic_wo_chain:{ *:[i32] } 2352:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64),
     /*  792007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792014 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792016 */     GIR_RootConstrainSelectedInstOperands,
     /*  792017 */     // GIR_Coverage, 3200,
     /*  792017 */     GIR_EraseRootFromParent_Done,
     /*  792018 */   // Label 12721: @792018
     /*  792018 */   GIM_Try, /*On fail goto*//*Label 12722*/ GIMT_Encode4(792065), // Rule ID 3201 //
     /*  792023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  792026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f32),
     /*  792031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  792034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  792037 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  792044 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792051 */     // (intrinsic_wo_chain:{ *:[i32] } 2352:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F32_e64),
     /*  792054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792061 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792063 */     GIR_RootConstrainSelectedInstOperands,
     /*  792064 */     // GIR_Coverage, 3201,
     /*  792064 */     GIR_EraseRootFromParent_Done,
     /*  792065 */   // Label 12722: @792065
     /*  792065 */   GIM_Try, /*On fail goto*//*Label 12723*/ GIMT_Encode4(792112), // Rule ID 3202 //
     /*  792070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  792073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f16),
     /*  792078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  792081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  792084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  792091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792098 */     // (intrinsic_wo_chain:{ *:[i32] } 2351:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64),
     /*  792101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792108 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792110 */     GIR_RootConstrainSelectedInstOperands,
     /*  792111 */     // GIR_Coverage, 3202,
     /*  792111 */     GIR_EraseRootFromParent_Done,
     /*  792112 */   // Label 12723: @792112
     /*  792112 */   GIM_Try, /*On fail goto*//*Label 12724*/ GIMT_Encode4(792159), // Rule ID 3203 //
     /*  792117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  792120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f16),
     /*  792125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  792128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  792131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  792138 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792145 */     // (intrinsic_wo_chain:{ *:[i32] } 2351:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64),
     /*  792148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792155 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792157 */     GIR_RootConstrainSelectedInstOperands,
     /*  792158 */     // GIR_Coverage, 3203,
     /*  792158 */     GIR_EraseRootFromParent_Done,
     /*  792159 */   // Label 12724: @792159
     /*  792159 */   GIM_Try, /*On fail goto*//*Label 12725*/ GIMT_Encode4(792206), // Rule ID 3204 //
     /*  792164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  792167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f16),
     /*  792172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  792175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  792178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  792185 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792192 */     // (intrinsic_wo_chain:{ *:[i32] } 2351:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64),
     /*  792195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792202 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792204 */     GIR_RootConstrainSelectedInstOperands,
     /*  792205 */     // GIR_Coverage, 3204,
     /*  792205 */     GIR_EraseRootFromParent_Done,
     /*  792206 */   // Label 12725: @792206
     /*  792206 */   GIM_Try, /*On fail goto*//*Label 12726*/ GIMT_Encode4(792253), // Rule ID 3205 //
     /*  792211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  792214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f16),
     /*  792219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  792222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  792225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  792232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792239 */     // (intrinsic_wo_chain:{ *:[i32] } 2351:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64),
     /*  792242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792249 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792251 */     GIR_RootConstrainSelectedInstOperands,
     /*  792252 */     // GIR_Coverage, 3205,
     /*  792252 */     GIR_EraseRootFromParent_Done,
     /*  792253 */   // Label 12726: @792253
     /*  792253 */   GIM_Try, /*On fail goto*//*Label 12727*/ GIMT_Encode4(792300), // Rule ID 3206 //
     /*  792258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  792261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk8_fp4_f16),
     /*  792266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  792269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  792272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  792279 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792286 */     // (intrinsic_wo_chain:{ *:[i32] } 2351:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK8_FP4_F16_e64),
     /*  792289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792296 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792298 */     GIR_RootConstrainSelectedInstOperands,
     /*  792299 */     // GIR_Coverage, 3206,
     /*  792299 */     GIR_EraseRootFromParent_Done,
     /*  792300 */   // Label 12727: @792300
     /*  792300 */   GIM_Try, /*On fail goto*//*Label 12728*/ GIMT_Encode4(792347), // Rule ID 3207 //
     /*  792305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  792308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f32),
     /*  792313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792319 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792333 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2336:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64),
     /*  792336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792343 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792345 */     GIR_RootConstrainSelectedInstOperands,
     /*  792346 */     // GIR_Coverage, 3207,
     /*  792346 */     GIR_EraseRootFromParent_Done,
     /*  792347 */   // Label 12728: @792347
     /*  792347 */   GIM_Try, /*On fail goto*//*Label 12729*/ GIMT_Encode4(792394), // Rule ID 3208 //
     /*  792352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  792355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f32),
     /*  792360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792380 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2336:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64),
     /*  792383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792390 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792392 */     GIR_RootConstrainSelectedInstOperands,
     /*  792393 */     // GIR_Coverage, 3208,
     /*  792393 */     GIR_EraseRootFromParent_Done,
     /*  792394 */   // Label 12729: @792394
     /*  792394 */   GIM_Try, /*On fail goto*//*Label 12730*/ GIMT_Encode4(792441), // Rule ID 3209 //
     /*  792399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  792402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f32),
     /*  792407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792427 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2336:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64),
     /*  792430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792437 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792439 */     GIR_RootConstrainSelectedInstOperands,
     /*  792440 */     // GIR_Coverage, 3209,
     /*  792440 */     GIR_EraseRootFromParent_Done,
     /*  792441 */   // Label 12730: @792441
     /*  792441 */   GIM_Try, /*On fail goto*//*Label 12731*/ GIMT_Encode4(792488), // Rule ID 3210 //
     /*  792446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  792449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f32),
     /*  792454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792474 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2336:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64),
     /*  792477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792484 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792486 */     GIR_RootConstrainSelectedInstOperands,
     /*  792487 */     // GIR_Coverage, 3210,
     /*  792487 */     GIR_EraseRootFromParent_Done,
     /*  792488 */   // Label 12731: @792488
     /*  792488 */   GIM_Try, /*On fail goto*//*Label 12732*/ GIMT_Encode4(792535), // Rule ID 3211 //
     /*  792493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  792496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f32),
     /*  792501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792521 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2336:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F32_e64),
     /*  792524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792533 */     GIR_RootConstrainSelectedInstOperands,
     /*  792534 */     // GIR_Coverage, 3211,
     /*  792534 */     GIR_EraseRootFromParent_Done,
     /*  792535 */   // Label 12732: @792535
     /*  792535 */   GIM_Try, /*On fail goto*//*Label 12733*/ GIMT_Encode4(792582), // Rule ID 3212 //
     /*  792540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  792543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f32),
     /*  792548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792568 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2333:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64),
     /*  792571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792578 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792580 */     GIR_RootConstrainSelectedInstOperands,
     /*  792581 */     // GIR_Coverage, 3212,
     /*  792581 */     GIR_EraseRootFromParent_Done,
     /*  792582 */   // Label 12733: @792582
     /*  792582 */   GIM_Try, /*On fail goto*//*Label 12734*/ GIMT_Encode4(792629), // Rule ID 3213 //
     /*  792587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  792590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f32),
     /*  792595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792608 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792615 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2333:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64),
     /*  792618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792620 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792625 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792627 */     GIR_RootConstrainSelectedInstOperands,
     /*  792628 */     // GIR_Coverage, 3213,
     /*  792628 */     GIR_EraseRootFromParent_Done,
     /*  792629 */   // Label 12734: @792629
     /*  792629 */   GIM_Try, /*On fail goto*//*Label 12735*/ GIMT_Encode4(792676), // Rule ID 3214 //
     /*  792634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  792637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f32),
     /*  792642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792662 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2333:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64),
     /*  792665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792672 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792674 */     GIR_RootConstrainSelectedInstOperands,
     /*  792675 */     // GIR_Coverage, 3214,
     /*  792675 */     GIR_EraseRootFromParent_Done,
     /*  792676 */   // Label 12735: @792676
     /*  792676 */   GIM_Try, /*On fail goto*//*Label 12736*/ GIMT_Encode4(792723), // Rule ID 3215 //
     /*  792681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  792684 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f32),
     /*  792689 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792692 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792695 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792702 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792709 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2333:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64),
     /*  792712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792719 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792721 */     GIR_RootConstrainSelectedInstOperands,
     /*  792722 */     // GIR_Coverage, 3215,
     /*  792722 */     GIR_EraseRootFromParent_Done,
     /*  792723 */   // Label 12736: @792723
     /*  792723 */   GIM_Try, /*On fail goto*//*Label 12737*/ GIMT_Encode4(792770), // Rule ID 3216 //
     /*  792728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  792731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f32),
     /*  792736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  792742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792756 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2333:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F32_e64),
     /*  792759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792766 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792768 */     GIR_RootConstrainSelectedInstOperands,
     /*  792769 */     // GIR_Coverage, 3216,
     /*  792769 */     GIR_EraseRootFromParent_Done,
     /*  792770 */   // Label 12737: @792770
     /*  792770 */   GIM_Try, /*On fail goto*//*Label 12738*/ GIMT_Encode4(792817), // Rule ID 3217 //
     /*  792775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  792778 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f16),
     /*  792783 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792786 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  792789 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792803 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2335:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64),
     /*  792806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792813 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792815 */     GIR_RootConstrainSelectedInstOperands,
     /*  792816 */     // GIR_Coverage, 3217,
     /*  792816 */     GIR_EraseRootFromParent_Done,
     /*  792817 */   // Label 12738: @792817
     /*  792817 */   GIM_Try, /*On fail goto*//*Label 12739*/ GIMT_Encode4(792864), // Rule ID 3218 //
     /*  792822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  792825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f16),
     /*  792830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  792836 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792850 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2335:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64),
     /*  792853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792860 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792862 */     GIR_RootConstrainSelectedInstOperands,
     /*  792863 */     // GIR_Coverage, 3218,
     /*  792863 */     GIR_EraseRootFromParent_Done,
     /*  792864 */   // Label 12739: @792864
     /*  792864 */   GIM_Try, /*On fail goto*//*Label 12740*/ GIMT_Encode4(792911), // Rule ID 3219 //
     /*  792869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  792872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f16),
     /*  792877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  792883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792897 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2335:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64),
     /*  792900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792907 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792909 */     GIR_RootConstrainSelectedInstOperands,
     /*  792910 */     // GIR_Coverage, 3219,
     /*  792910 */     GIR_EraseRootFromParent_Done,
     /*  792911 */   // Label 12740: @792911
     /*  792911 */   GIM_Try, /*On fail goto*//*Label 12741*/ GIMT_Encode4(792958), // Rule ID 3220 //
     /*  792916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  792919 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f16),
     /*  792924 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792927 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  792930 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792944 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2335:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64),
     /*  792947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  792954 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  792956 */     GIR_RootConstrainSelectedInstOperands,
     /*  792957 */     // GIR_Coverage, 3220,
     /*  792957 */     GIR_EraseRootFromParent_Done,
     /*  792958 */   // Label 12741: @792958
     /*  792958 */   GIM_Try, /*On fail goto*//*Label 12742*/ GIMT_Encode4(793005), // Rule ID 3221 //
     /*  792963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  792966 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_fp6_f16),
     /*  792971 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  792974 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  792977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  792980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  792984 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  792991 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2335:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  792991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_FP6_F16_e64),
     /*  792994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  792996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793001 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793003 */     GIR_RootConstrainSelectedInstOperands,
     /*  793004 */     // GIR_Coverage, 3221,
     /*  793004 */     GIR_EraseRootFromParent_Done,
     /*  793005 */   // Label 12742: @793005
     /*  793005 */   GIM_Try, /*On fail goto*//*Label 12743*/ GIMT_Encode4(793052), // Rule ID 3222 //
     /*  793010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  793013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f16),
     /*  793018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  793021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  793024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  793031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  793038 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2332:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  793038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64),
     /*  793041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793048 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793050 */     GIR_RootConstrainSelectedInstOperands,
     /*  793051 */     // GIR_Coverage, 3222,
     /*  793051 */     GIR_EraseRootFromParent_Done,
     /*  793052 */   // Label 12743: @793052
     /*  793052 */   GIM_Try, /*On fail goto*//*Label 12744*/ GIMT_Encode4(793099), // Rule ID 3223 //
     /*  793057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  793060 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f16),
     /*  793065 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  793068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  793071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  793078 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  793085 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2332:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  793085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64),
     /*  793088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793097 */     GIR_RootConstrainSelectedInstOperands,
     /*  793098 */     // GIR_Coverage, 3223,
     /*  793098 */     GIR_EraseRootFromParent_Done,
     /*  793099 */   // Label 12744: @793099
     /*  793099 */   GIM_Try, /*On fail goto*//*Label 12745*/ GIMT_Encode4(793146), // Rule ID 3224 //
     /*  793104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  793107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f16),
     /*  793112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  793115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  793118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  793125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  793132 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2332:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  793132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64),
     /*  793135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793142 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793144 */     GIR_RootConstrainSelectedInstOperands,
     /*  793145 */     // GIR_Coverage, 3224,
     /*  793145 */     GIR_EraseRootFromParent_Done,
     /*  793146 */   // Label 12745: @793146
     /*  793146 */   GIM_Try, /*On fail goto*//*Label 12746*/ GIMT_Encode4(793193), // Rule ID 3225 //
     /*  793151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  793154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f16),
     /*  793159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  793162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  793165 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  793172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  793179 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2332:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  793179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64),
     /*  793182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793189 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793191 */     GIR_RootConstrainSelectedInstOperands,
     /*  793192 */     // GIR_Coverage, 3225,
     /*  793192 */     GIR_EraseRootFromParent_Done,
     /*  793193 */   // Label 12746: @793193
     /*  793193 */   GIM_Try, /*On fail goto*//*Label 12747*/ GIMT_Encode4(793240), // Rule ID 3226 //
     /*  793198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  793201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk16_bf6_f16),
     /*  793206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  793209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  793212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  793219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  793226 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2332:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), f32:{ *:[f32] }:$src1)  =>  (V_CVT_SCALEF32_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, f32:{ *:[f32] }:$src1)
     /*  793226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK16_BF6_F16_e64),
     /*  793229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793236 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793238 */     GIR_RootConstrainSelectedInstOperands,
     /*  793239 */     // GIR_Coverage, 3226,
     /*  793239 */     GIR_EraseRootFromParent_Done,
     /*  793240 */   // Label 12747: @793240
     /*  793240 */   GIM_Try, /*On fail goto*//*Label 12748*/ GIMT_Encode4(793277), // Rule ID 2600 //
     /*  793245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
     /*  793250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793263 */     // (intrinsic_wo_chain:{ *:[i32] } 3333:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_I32_I24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_I32_I24_e64),
     /*  793266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793268 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793270 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793275 */     GIR_RootConstrainSelectedInstOperands,
     /*  793276 */     // GIR_Coverage, 2600,
     /*  793276 */     GIR_EraseRootFromParent_Done,
     /*  793277 */   // Label 12748: @793277
     /*  793277 */   GIM_Try, /*On fail goto*//*Label 12749*/ GIMT_Encode4(793311), // Rule ID 2602 //
     /*  793282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mulhi_i24),
     /*  793287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793300 */     // (intrinsic_wo_chain:{ *:[i32] } 3335:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_HI_I32_I24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_I24_e64),
     /*  793303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793305 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793307 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793309 */     GIR_RootConstrainSelectedInstOperands,
     /*  793310 */     // GIR_Coverage, 2602,
     /*  793310 */     GIR_EraseRootFromParent_Done,
     /*  793311 */   // Label 12749: @793311
     /*  793311 */   GIM_Try, /*On fail goto*//*Label 12750*/ GIMT_Encode4(793348), // Rule ID 2604 //
     /*  793316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
     /*  793321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793334 */     // (intrinsic_wo_chain:{ *:[i32] } 3334:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_U32_U24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U32_U24_e64),
     /*  793337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793339 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793341 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793346 */     GIR_RootConstrainSelectedInstOperands,
     /*  793347 */     // GIR_Coverage, 2604,
     /*  793347 */     GIR_EraseRootFromParent_Done,
     /*  793348 */   // Label 12750: @793348
     /*  793348 */   GIM_Try, /*On fail goto*//*Label 12751*/ GIMT_Encode4(793382), // Rule ID 2606 //
     /*  793353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mulhi_u24),
     /*  793358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793371 */     // (intrinsic_wo_chain:{ *:[i32] } 3336:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_HI_U32_U24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_U24_e64),
     /*  793374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793376 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793378 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793380 */     GIR_RootConstrainSelectedInstOperands,
     /*  793381 */     // GIR_Coverage, 2606,
     /*  793381 */     GIR_EraseRootFromParent_Done,
     /*  793382 */   // Label 12751: @793382
     /*  793382 */   GIM_Try, /*On fail goto*//*Label 12752*/ GIMT_Encode4(793416), // Rule ID 2631 //
     /*  793387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mbcnt_lo),
     /*  793392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793405 */     // (intrinsic_wo_chain:{ *:[i32] } 3280:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MBCNT_LO_U32_B32_e64),
     /*  793408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793410 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793412 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793414 */     GIR_RootConstrainSelectedInstOperands,
     /*  793415 */     // GIR_Coverage, 2631,
     /*  793415 */     GIR_EraseRootFromParent_Done,
     /*  793416 */   // Label 12752: @793416
     /*  793416 */   GIM_Try, /*On fail goto*//*Label 12753*/ GIMT_Encode4(793450), // Rule ID 2632 //
     /*  793421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mbcnt_hi),
     /*  793426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793439 */     // (intrinsic_wo_chain:{ *:[i32] } 3279:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MBCNT_HI_U32_B32_e64),
     /*  793442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793444 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793446 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793448 */     GIR_RootConstrainSelectedInstOperands,
     /*  793449 */     // GIR_Coverage, 2632,
     /*  793449 */     GIR_EraseRootFromParent_Done,
     /*  793450 */   // Label 12753: @793450
     /*  793450 */   GIM_Try, /*On fail goto*//*Label 12754*/ GIMT_Encode4(793484), // Rule ID 2641 //
     /*  793455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_u16),
     /*  793460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  793463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793473 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2287:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_CVT_PK_U16_U32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U16_U32_e64),
     /*  793476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793478 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793480 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793482 */     GIR_RootConstrainSelectedInstOperands,
     /*  793483 */     // GIR_Coverage, 2641,
     /*  793483 */     GIR_EraseRootFromParent_Done,
     /*  793484 */   // Label 12754: @793484
     /*  793484 */   GIM_Try, /*On fail goto*//*Label 12755*/ GIMT_Encode4(793518), // Rule ID 2643 //
     /*  793489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_i16),
     /*  793494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  793497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793500 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793507 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2286:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_CVT_PK_I16_I32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  793507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_I16_I32_e64),
     /*  793510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793512 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  793514 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  793516 */     GIR_RootConstrainSelectedInstOperands,
     /*  793517 */     // GIR_Coverage, 2643,
     /*  793517 */     GIR_EraseRootFromParent_Done,
     /*  793518 */   // Label 12755: @793518
     /*  793518 */   GIM_Reject,
     /*  793519 */ // Label 12571: @793519
     /*  793519 */ GIM_Try, /*On fail goto*//*Label 12756*/ GIMT_Encode4(804501),
     /*  793524 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /*  793527 */   GIM_Try, /*On fail goto*//*Label 12757*/ GIMT_Encode4(793620), // Rule ID 7223 //
     /*  793532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9GFX10),
     /*  793535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_alignbyte),
     /*  793540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793549 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  793552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793577 */     // (intrinsic_wo_chain:{ *:[i32] } 2231:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_ALIGNBYTE_B32_opsel_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, VSrc_b32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, VSrc_b32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, VGPR_32:{ *:[i32] }:$src2)
     /*  793577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBYTE_B32_opsel_e64),
     /*  793580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  793587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  793597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  793602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  793607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  793612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793618 */     GIR_RootConstrainSelectedInstOperands,
     /*  793619 */     // GIR_Coverage, 7223,
     /*  793619 */     GIR_EraseRootFromParent_Done,
     /*  793620 */   // Label 12757: @793620
     /*  793620 */   GIM_Try, /*On fail goto*//*Label 12758*/ GIMT_Encode4(793713), // Rule ID 7224 //
     /*  793625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  793628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_alignbyte),
     /*  793633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793639 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793642 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  793645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793670 */     // (intrinsic_wo_chain:{ *:[i32] } 2231:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_ALIGNBYTE_B32_fake16_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, VSrc_b32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, VSrc_b32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, VGPR_32:{ *:[i32] }:$src2)
     /*  793670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBYTE_B32_fake16_e64),
     /*  793673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  793680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  793690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  793695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  793700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  793705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793711 */     GIR_RootConstrainSelectedInstOperands,
     /*  793712 */     // GIR_Coverage, 7224,
     /*  793712 */     GIR_EraseRootFromParent_Done,
     /*  793713 */   // Label 12758: @793713
     /*  793713 */   GIM_Try, /*On fail goto*//*Label 12759*/ GIMT_Encode4(793833), // Rule ID 7225 //
     /*  793718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  793721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_alignbyte),
     /*  793726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793735 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  793738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  793763 */     // (intrinsic_wo_chain:{ *:[i32] } 2231:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_ALIGNBYTE_B32_t16_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, VSrc_b32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, VSrc_b32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, (EXTRACT_SUBREG:{ *:[i16] } VGPR_32:{ *:[i32] }:$src2, lo16:{ *:[i32] }))
     /*  793763 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  793766 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  793770 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  793775 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src2
     /*  793782 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  793787 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBYTE_B32_t16_e64),
     /*  793795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  793802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  793812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  793817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  793822 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  793825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793831 */     GIR_RootConstrainSelectedInstOperands,
     /*  793832 */     // GIR_Coverage, 7225,
     /*  793832 */     GIR_EraseRootFromParent_Done,
     /*  793833 */   // Label 12759: @793833
     /*  793833 */   GIM_Try, /*On fail goto*//*Label 12760*/ GIMT_Encode4(793923), // Rule ID 27301 //
     /*  793838 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10),
     /*  793843 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793846 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793849 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793852 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  793855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  793866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  793873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  793880 */     // (intrinsic_wo_chain:{ *:[f32] } 3253:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_INTERP_P10_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  793880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F32_inreg),
     /*  793883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  793890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  793900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  793905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  793910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  793915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  793918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  793921 */     GIR_RootConstrainSelectedInstOperands,
     /*  793922 */     // GIR_Coverage, 27301,
     /*  793922 */     GIR_EraseRootFromParent_Done,
     /*  793923 */   // Label 12760: @793923
     /*  793923 */   GIM_Try, /*On fail goto*//*Label 12761*/ GIMT_Encode4(794013), // Rule ID 27302 //
     /*  793928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2),
     /*  793933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  793936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  793939 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  793942 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  793945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  793949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  793956 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  793963 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  793970 */     // (intrinsic_wo_chain:{ *:[f32] } 3255:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_INTERP_P2_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  793970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F32_inreg),
     /*  793973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  793975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  793980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  793985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  793990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  793995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  794000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  794005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  794011 */     GIR_RootConstrainSelectedInstOperands,
     /*  794012 */     // GIR_Coverage, 27302,
     /*  794012 */     GIR_EraseRootFromParent_Done,
     /*  794013 */   // Label 12761: @794013
     /*  794013 */   GIM_Try, /*On fail goto*//*Label 12762*/ GIMT_Encode4(794100), // Rule ID 27475 //
     /*  794018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
     /*  794021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
     /*  794026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794035 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794042 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794056 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794063 */     // (intrinsic_wo_chain:{ *:[f32] } 2456:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_MAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*  794063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F32_e64),
     /*  794066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  794076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  794084 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  794092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794098 */     GIR_RootConstrainSelectedInstOperands,
     /*  794099 */     // GIR_Coverage, 27475,
     /*  794099 */     GIR_EraseRootFromParent_Done,
     /*  794100 */   // Label 12762: @794100
     /*  794100 */   GIM_Try, /*On fail goto*//*Label 12763*/ GIMT_Encode4(794187), // Rule ID 27479 //
     /*  794105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmacLegacy32),
     /*  794108 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy),
     /*  794113 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794116 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794119 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794122 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794150 */     // (intrinsic_wo_chain:{ *:[f32] } 2455:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_FMAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*  794150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_LEGACY_F32_e64),
     /*  794153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  794163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  794171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  794179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794185 */     GIR_RootConstrainSelectedInstOperands,
     /*  794186 */     // GIR_Coverage, 27479,
     /*  794186 */     GIR_EraseRootFromParent_Done,
     /*  794187 */   // Label 12763: @794187
     /*  794187 */   GIM_Try, /*On fail goto*//*Label 12764*/ GIMT_Encode4(794274), // Rule ID 27481 //
     /*  794192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
     /*  794195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
     /*  794200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  794203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  794206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  794209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  794212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794216 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794223 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
     /*  794237 */     // (intrinsic_wo_chain:{ *:[f16] } 2456:{ *:[iPTR] }, (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src0), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src1), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src2))  =>  (V_MAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f16] }:$src1, 0:{ *:[i32] }, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
     /*  794237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F16_e64),
     /*  794240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  794250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  794258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  794266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794272 */     GIR_RootConstrainSelectedInstOperands,
     /*  794273 */     // GIR_Coverage, 27481,
     /*  794273 */     GIR_EraseRootFromParent_Done,
     /*  794274 */   // Label 12764: @794274
     /*  794274 */   GIM_Try, /*On fail goto*//*Label 12765*/ GIMT_Encode4(794337), // Rule ID 7600 //
     /*  794279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus),
     /*  794282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_fp8_bf8),
     /*  794287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794296 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794303 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  794310 */     // (intrinsic_wo_chain:{ *:[f32] } 2403:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_FP8_BF8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
     /*  794310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_FP8_BF8),
     /*  794313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794315 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794317 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  794324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  794329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794335 */     GIR_RootConstrainSelectedInstOperands,
     /*  794336 */     // GIR_Coverage, 7600,
     /*  794336 */     GIR_EraseRootFromParent_Done,
     /*  794337 */   // Label 12765: @794337
     /*  794337 */   GIM_Try, /*On fail goto*//*Label 12766*/ GIMT_Encode4(794400), // Rule ID 7601 //
     /*  794342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus),
     /*  794345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_bf8_fp8),
     /*  794350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794359 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794366 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  794373 */     // (intrinsic_wo_chain:{ *:[f32] } 2402:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_BF8_FP8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
     /*  794373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_BF8_FP8),
     /*  794376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794378 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794380 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  794387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  794392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794398 */     GIR_RootConstrainSelectedInstOperands,
     /*  794399 */     // GIR_Coverage, 7601,
     /*  794399 */     GIR_EraseRootFromParent_Done,
     /*  794400 */   // Label 12766: @794400
     /*  794400 */   GIM_Try, /*On fail goto*//*Label 12767*/ GIMT_Encode4(794463), // Rule ID 7602 //
     /*  794405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus),
     /*  794408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_fp8_fp8),
     /*  794413 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794416 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794419 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794422 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  794436 */     // (intrinsic_wo_chain:{ *:[f32] } 2404:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_FP8_FP8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
     /*  794436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_FP8_FP8),
     /*  794439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794441 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794443 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794445 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  794450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  794455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794461 */     GIR_RootConstrainSelectedInstOperands,
     /*  794462 */     // GIR_Coverage, 7602,
     /*  794462 */     GIR_EraseRootFromParent_Done,
     /*  794463 */   // Label 12767: @794463
     /*  794463 */   GIM_Try, /*On fail goto*//*Label 12768*/ GIMT_Encode4(794526), // Rule ID 7603 //
     /*  794468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus),
     /*  794471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_bf8_bf8),
     /*  794476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794485 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  794499 */     // (intrinsic_wo_chain:{ *:[f32] } 2401:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_BF8_BF8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
     /*  794499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_BF8_BF8),
     /*  794502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794504 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794506 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  794513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  794518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794524 */     GIR_RootConstrainSelectedInstOperands,
     /*  794525 */     // GIR_Coverage, 7603,
     /*  794525 */     GIR_EraseRootFromParent_Done,
     /*  794526 */   // Label 12768: @794526
     /*  794526 */   GIM_Try, /*On fail goto*//*Label 12769*/ GIMT_Encode4(794591), // Rule ID 27294 //
     /*  794531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  794534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_param_load),
     /*  794539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794542 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794549 */     // MIs[0] attrchan
     /*  794549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  794552 */     // MIs[0] attr
     /*  794552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  794555 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  794559 */     // (intrinsic_wo_chain:{ *:[f32] } 3271:{ *:[iPTR] }, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (LDS_PARAM_LOAD:{ *:[f32] } (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, 0:{ *:[i32] })
     /*  794559 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  794563 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  794569 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  794573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::LDS_PARAM_LOAD),
     /*  794576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794578 */     GIR_RootToRootCopy, /*OpIdx*/3, // attr
     /*  794580 */     GIR_RootToRootCopy, /*OpIdx*/2, // attrchan
     /*  794582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794585 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  794589 */     GIR_RootConstrainSelectedInstOperands,
     /*  794590 */     // GIR_Coverage, 27294,
     /*  794590 */     GIR_EraseRootFromParent_Done,
     /*  794591 */   // Label 12769: @794591
     /*  794591 */   GIM_Try, /*On fail goto*//*Label 12770*/ GIMT_Encode4(794659), // Rule ID 27296 //
     /*  794596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50),
     /*  794599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_param_load),
     /*  794604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794607 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  794610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794614 */     // MIs[0] attrchan
     /*  794614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  794617 */     // MIs[0] attr
     /*  794617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  794620 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  794624 */     // (intrinsic_wo_chain:{ *:[f32] } 3271:{ *:[iPTR] }, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (DS_PARAM_LOAD:{ *:[f32] } (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, 0:{ *:[i32] }, 1:{ *:[i32] })
     /*  794624 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  794628 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  794634 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  794638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PARAM_LOAD),
     /*  794641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794643 */     GIR_RootToRootCopy, /*OpIdx*/3, // attr
     /*  794645 */     GIR_RootToRootCopy, /*OpIdx*/2, // attrchan
     /*  794647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  794653 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  794657 */     GIR_RootConstrainSelectedInstOperands,
     /*  794658 */     // GIR_Coverage, 27296,
     /*  794658 */     GIR_EraseRootFromParent_Done,
     /*  794659 */   // Label 12770: @794659
     /*  794659 */   GIM_Try, /*On fail goto*//*Label 12771*/ GIMT_Encode4(794711), // Rule ID 7405 //
     /*  794664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_f32_fp8),
     /*  794669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794672 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794682 */     // MIs[0] index
     /*  794682 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  794685 */     // (intrinsic_wo_chain:{ *:[f32] } 2312:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_F32_FP8_e64:{ *:[f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  794685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_F32_FP8_e64),
     /*  794688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794690 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  794696 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794698 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  794704 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794709 */     GIR_RootConstrainSelectedInstOperands,
     /*  794710 */     // GIR_Coverage, 7405,
     /*  794710 */     GIR_EraseRootFromParent_Done,
     /*  794711 */   // Label 12771: @794711
     /*  794711 */   GIM_Try, /*On fail goto*//*Label 12772*/ GIMT_Encode4(794763), // Rule ID 7406 //
     /*  794716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_f32_bf8),
     /*  794721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  794724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794734 */     // MIs[0] index
     /*  794734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  794737 */     // (intrinsic_wo_chain:{ *:[f32] } 2311:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_F32_BF8_e64:{ *:[f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  794737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_F32_BF8_e64),
     /*  794740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794742 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  794748 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794750 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  794756 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794758 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794761 */     GIR_RootConstrainSelectedInstOperands,
     /*  794762 */     // GIR_Coverage, 7406,
     /*  794762 */     GIR_EraseRootFromParent_Done,
     /*  794763 */   // Label 12772: @794763
     /*  794763 */   GIM_Try, /*On fail goto*//*Label 12773*/ GIMT_Encode4(794815), // Rule ID 7407 //
     /*  794768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f16_fp4),
     /*  794773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  794776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  794786 */     // MIs[0] index
     /*  794786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  794789 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2320:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_F16_FP4_e64:{ *:[v2f16] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  794789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F16_FP4_e64),
     /*  794792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794794 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  794800 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794802 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  794808 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794813 */     GIR_RootConstrainSelectedInstOperands,
     /*  794814 */     // GIR_Coverage, 7407,
     /*  794814 */     GIR_EraseRootFromParent_Done,
     /*  794815 */   // Label 12773: @794815
     /*  794815 */   GIM_Try, /*On fail goto*//*Label 12774*/ GIMT_Encode4(794867), // Rule ID 7414 //
     /*  794820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  794823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp8),
     /*  794828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  794831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  794841 */     // MIs[0] word_sel
     /*  794841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  794844 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_FP8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  794844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_e64),
     /*  794847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794849 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  794855 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794860 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794865 */     GIR_RootConstrainSelectedInstOperands,
     /*  794866 */     // GIR_Coverage, 7414,
     /*  794866 */     GIR_EraseRootFromParent_Done,
     /*  794867 */   // Label 12774: @794867
     /*  794867 */   GIM_Try, /*On fail goto*//*Label 12775*/ GIMT_Encode4(794919), // Rule ID 7415 //
     /*  794872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  794875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp8),
     /*  794880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  794883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794886 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  794893 */     // MIs[0] word_sel
     /*  794893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  794896 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_FP8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  794896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_e64),
     /*  794899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794901 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  794907 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794912 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794917 */     GIR_RootConstrainSelectedInstOperands,
     /*  794918 */     // GIR_Coverage, 7415,
     /*  794918 */     GIR_EraseRootFromParent_Done,
     /*  794919 */   // Label 12775: @794919
     /*  794919 */   GIM_Try, /*On fail goto*//*Label 12776*/ GIMT_Encode4(794971), // Rule ID 7416 //
     /*  794924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  794927 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp8),
     /*  794932 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  794935 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794938 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  794945 */     // MIs[0] word_sel
     /*  794945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  794948 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_FP8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  794948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_e64),
     /*  794951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  794953 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  794959 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  794961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794964 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  794966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  794969 */     GIR_RootConstrainSelectedInstOperands,
     /*  794970 */     // GIR_Coverage, 7416,
     /*  794970 */     GIR_EraseRootFromParent_Done,
     /*  794971 */   // Label 12776: @794971
     /*  794971 */   GIM_Try, /*On fail goto*//*Label 12777*/ GIMT_Encode4(795023), // Rule ID 7417 //
     /*  794976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  794979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp8),
     /*  794984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  794987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  794990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  794993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  794997 */     // MIs[0] word_sel
     /*  794997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795000 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_FP8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_e64),
     /*  795003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795005 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795011 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795016 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795021 */     GIR_RootConstrainSelectedInstOperands,
     /*  795022 */     // GIR_Coverage, 7417,
     /*  795022 */     GIR_EraseRootFromParent_Done,
     /*  795023 */   // Label 12777: @795023
     /*  795023 */   GIM_Try, /*On fail goto*//*Label 12778*/ GIMT_Encode4(795075), // Rule ID 7418 //
     /*  795028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  795031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp8),
     /*  795036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795049 */     // MIs[0] word_sel
     /*  795049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795052 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_FP8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP8_e64),
     /*  795055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795057 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795063 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795068 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795070 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795073 */     GIR_RootConstrainSelectedInstOperands,
     /*  795074 */     // GIR_Coverage, 7418,
     /*  795074 */     GIR_EraseRootFromParent_Done,
     /*  795075 */   // Label 12778: @795075
     /*  795075 */   GIM_Try, /*On fail goto*//*Label 12779*/ GIMT_Encode4(795127), // Rule ID 7419 //
     /*  795080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  795083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_bf8),
     /*  795088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795101 */     // MIs[0] word_sel
     /*  795101 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795104 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2322:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_BF8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_e64),
     /*  795107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795109 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795115 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795120 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795125 */     GIR_RootConstrainSelectedInstOperands,
     /*  795126 */     // GIR_Coverage, 7419,
     /*  795126 */     GIR_EraseRootFromParent_Done,
     /*  795127 */   // Label 12779: @795127
     /*  795127 */   GIM_Try, /*On fail goto*//*Label 12780*/ GIMT_Encode4(795179), // Rule ID 7420 //
     /*  795132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  795135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_bf8),
     /*  795140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795153 */     // MIs[0] word_sel
     /*  795153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795156 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2322:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_BF8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_e64),
     /*  795159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795161 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795167 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795172 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795177 */     GIR_RootConstrainSelectedInstOperands,
     /*  795178 */     // GIR_Coverage, 7420,
     /*  795178 */     GIR_EraseRootFromParent_Done,
     /*  795179 */   // Label 12780: @795179
     /*  795179 */   GIM_Try, /*On fail goto*//*Label 12781*/ GIMT_Encode4(795231), // Rule ID 7421 //
     /*  795184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  795187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_bf8),
     /*  795192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795205 */     // MIs[0] word_sel
     /*  795205 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795208 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2322:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_BF8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_e64),
     /*  795211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795213 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795219 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795224 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795229 */     GIR_RootConstrainSelectedInstOperands,
     /*  795230 */     // GIR_Coverage, 7421,
     /*  795230 */     GIR_EraseRootFromParent_Done,
     /*  795231 */   // Label 12781: @795231
     /*  795231 */   GIM_Try, /*On fail goto*//*Label 12782*/ GIMT_Encode4(795283), // Rule ID 7422 //
     /*  795236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  795239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_bf8),
     /*  795244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795257 */     // MIs[0] word_sel
     /*  795257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795260 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2322:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_BF8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_e64),
     /*  795263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795265 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795271 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795276 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795281 */     GIR_RootConstrainSelectedInstOperands,
     /*  795282 */     // GIR_Coverage, 7422,
     /*  795282 */     GIR_EraseRootFromParent_Done,
     /*  795283 */   // Label 12782: @795283
     /*  795283 */   GIM_Try, /*On fail goto*//*Label 12783*/ GIMT_Encode4(795335), // Rule ID 7423 //
     /*  795288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  795291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_bf8),
     /*  795296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795309 */     // MIs[0] word_sel
     /*  795309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795312 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2322:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F32_BF8_e64:{ *:[v2f32] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_BF8_e64),
     /*  795315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795317 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795323 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795328 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795333 */     GIR_RootConstrainSelectedInstOperands,
     /*  795334 */     // GIR_Coverage, 7423,
     /*  795334 */     GIR_EraseRootFromParent_Done,
     /*  795335 */   // Label 12783: @795335
     /*  795335 */   GIM_Try, /*On fail goto*//*Label 12784*/ GIMT_Encode4(795384), // Rule ID 7424 //
     /*  795340 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f16_bf8),
     /*  795345 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  795348 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795351 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  795358 */     // MIs[0] word_sel
     /*  795358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795361 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F16_BF8_e64:{ *:[v2f16] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F16_BF8_e64),
     /*  795364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795366 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795372 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795377 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795382 */     GIR_RootConstrainSelectedInstOperands,
     /*  795383 */     // GIR_Coverage, 7424,
     /*  795383 */     GIR_EraseRootFromParent_Done,
     /*  795384 */   // Label 12784: @795384
     /*  795384 */   GIM_Try, /*On fail goto*//*Label 12785*/ GIMT_Encode4(795433), // Rule ID 7425 //
     /*  795389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f16_fp8),
     /*  795394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  795397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795400 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  795407 */     // MIs[0] word_sel
     /*  795407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795410 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2321:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_F16_FP8_e64:{ *:[v2f16] } (SrcSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1)
     /*  795410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F16_FP8_e64),
     /*  795413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795415 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcSelToOpSelXForm), // word_sel
     /*  795421 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795426 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795431 */     GIR_RootConstrainSelectedInstOperands,
     /*  795432 */     // GIR_Coverage, 7425,
     /*  795432 */     GIR_EraseRootFromParent_Done,
     /*  795433 */   // Label 12785: @795433
     /*  795433 */   GIM_Try, /*On fail goto*//*Label 12786*/ GIMT_Encode4(795488), // Rule ID 7428 //
     /*  795438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  795441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp4),
     /*  795446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795459 */     // MIs[0] index
     /*  795459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795462 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_F32_FP4_e64:{ *:[v2f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  795462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_e64),
     /*  795465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795467 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  795473 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795475 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  795481 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795486 */     GIR_RootConstrainSelectedInstOperands,
     /*  795487 */     // GIR_Coverage, 7428,
     /*  795487 */     GIR_EraseRootFromParent_Done,
     /*  795488 */   // Label 12786: @795488
     /*  795488 */   GIM_Try, /*On fail goto*//*Label 12787*/ GIMT_Encode4(795543), // Rule ID 7429 //
     /*  795493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  795496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp4),
     /*  795501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795514 */     // MIs[0] index
     /*  795514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795517 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_F32_FP4_e64:{ *:[v2f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  795517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_e64),
     /*  795520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795522 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  795528 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795530 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  795536 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795541 */     GIR_RootConstrainSelectedInstOperands,
     /*  795542 */     // GIR_Coverage, 7429,
     /*  795542 */     GIR_EraseRootFromParent_Done,
     /*  795543 */   // Label 12787: @795543
     /*  795543 */   GIM_Try, /*On fail goto*//*Label 12788*/ GIMT_Encode4(795598), // Rule ID 7430 //
     /*  795548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  795551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp4),
     /*  795556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795569 */     // MIs[0] index
     /*  795569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795572 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_F32_FP4_e64:{ *:[v2f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  795572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_e64),
     /*  795575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795577 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  795583 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795585 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  795591 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795596 */     GIR_RootConstrainSelectedInstOperands,
     /*  795597 */     // GIR_Coverage, 7430,
     /*  795597 */     GIR_EraseRootFromParent_Done,
     /*  795598 */   // Label 12788: @795598
     /*  795598 */   GIM_Try, /*On fail goto*//*Label 12789*/ GIMT_Encode4(795653), // Rule ID 7431 //
     /*  795603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  795606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp4),
     /*  795611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795624 */     // MIs[0] index
     /*  795624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795627 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_F32_FP4_e64:{ *:[v2f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  795627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_e64),
     /*  795630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795632 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  795638 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795640 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  795646 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795651 */     GIR_RootConstrainSelectedInstOperands,
     /*  795652 */     // GIR_Coverage, 7431,
     /*  795652 */     GIR_EraseRootFromParent_Done,
     /*  795653 */   // Label 12789: @795653
     /*  795653 */   GIM_Try, /*On fail goto*//*Label 12790*/ GIMT_Encode4(795708), // Rule ID 7432 //
     /*  795658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  795661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_f32_fp4),
     /*  795666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  795669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795679 */     // MIs[0] index
     /*  795679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  795682 */     // (intrinsic_wo_chain:{ *:[v2f32] } 2323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_F32_FP4_e64:{ *:[v2f32] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src1)
     /*  795682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_F32_FP4_e64),
     /*  795685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795687 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // index
     /*  795693 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795695 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // index
     /*  795701 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795706 */     GIR_RootConstrainSelectedInstOperands,
     /*  795707 */     // GIR_Coverage, 7432,
     /*  795707 */     GIR_EraseRootFromParent_Done,
     /*  795708 */   // Label 12790: @795708
     /*  795708 */   GIM_Try, /*On fail goto*//*Label 12791*/ GIMT_Encode4(795750), // Rule ID 7535 //
     /*  795713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_u8),
     /*  795718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  795721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  795730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  795734 */     // (intrinsic_wo_chain:{ *:[i32] } 3477:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*  795734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U8_e64),
     /*  795737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795739 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795741 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795743 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  795745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795748 */     GIR_RootConstrainSelectedInstOperands,
     /*  795749 */     // GIR_Coverage, 7535,
     /*  795749 */     GIR_EraseRootFromParent_Done,
     /*  795750 */   // Label 12791: @795750
     /*  795750 */   GIM_Try, /*On fail goto*//*Label 12792*/ GIMT_Encode4(795792), // Rule ID 7536 //
     /*  795755 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_hi_u8),
     /*  795760 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  795763 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795766 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795769 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  795772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  795776 */     // (intrinsic_wo_chain:{ *:[i32] } 3475:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*  795776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_HI_U8_e64),
     /*  795779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795781 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795783 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795785 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  795787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795790 */     GIR_RootConstrainSelectedInstOperands,
     /*  795791 */     // GIR_Coverage, 7536,
     /*  795791 */     GIR_EraseRootFromParent_Done,
     /*  795792 */   // Label 12792: @795792
     /*  795792 */   GIM_Try, /*On fail goto*//*Label 12793*/ GIMT_Encode4(795834), // Rule ID 7537 //
     /*  795797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_u16),
     /*  795802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  795805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795811 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  795814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  795818 */     // (intrinsic_wo_chain:{ *:[i32] } 3476:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*  795818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U16_e64),
     /*  795821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795823 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795825 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795827 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  795829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795832 */     GIR_RootConstrainSelectedInstOperands,
     /*  795833 */     // GIR_Coverage, 7537,
     /*  795833 */     GIR_EraseRootFromParent_Done,
     /*  795834 */   // Label 12793: @795834
     /*  795834 */   GIM_Try, /*On fail goto*//*Label 12794*/ GIMT_Encode4(795876), // Rule ID 7538 //
     /*  795839 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_msad_u8),
     /*  795844 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  795847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  795850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795853 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  795856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  795860 */     // (intrinsic_wo_chain:{ *:[i32] } 3332:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
     /*  795860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MSAD_U8_e64),
     /*  795863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795865 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795867 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795869 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  795871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795874 */     GIR_RootConstrainSelectedInstOperands,
     /*  795875 */     // GIR_Coverage, 7538,
     /*  795875 */     GIR_EraseRootFromParent_Done,
     /*  795876 */   // Label 12794: @795876
     /*  795876 */   GIM_Try, /*On fail goto*//*Label 12795*/ GIMT_Encode4(795921), // Rule ID 7539 //
     /*  795881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  795884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8),
     /*  795889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  795892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  795895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795898 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  795901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795905 */     // (intrinsic_wo_chain:{ *:[i64] } 3330:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  795905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64),
     /*  795908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795910 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795912 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795914 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  795916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795919 */     GIR_RootConstrainSelectedInstOperands,
     /*  795920 */     // GIR_Coverage, 7539,
     /*  795920 */     GIR_EraseRootFromParent_Done,
     /*  795921 */   // Label 12795: @795921
     /*  795921 */   GIM_Try, /*On fail goto*//*Label 12796*/ GIMT_Encode4(795966), // Rule ID 7540 //
     /*  795926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  795929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8),
     /*  795934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  795937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  795940 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795943 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  795946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795950 */     // (intrinsic_wo_chain:{ *:[i64] } 3330:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  795950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64),
     /*  795953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  795955 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  795957 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  795959 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  795961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  795964 */     GIR_RootConstrainSelectedInstOperands,
     /*  795965 */     // GIR_Coverage, 7540,
     /*  795965 */     GIR_EraseRootFromParent_Done,
     /*  795966 */   // Label 12796: @795966
     /*  795966 */   GIM_Try, /*On fail goto*//*Label 12797*/ GIMT_Encode4(796011), // Rule ID 7541 //
     /*  795971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  795974 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8),
     /*  795979 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  795982 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  795985 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  795988 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  795991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  795995 */     // (intrinsic_wo_chain:{ *:[i64] } 3330:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  795995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64),
     /*  795998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796000 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796002 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796004 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796009 */     GIR_RootConstrainSelectedInstOperands,
     /*  796010 */     // GIR_Coverage, 7541,
     /*  796010 */     GIR_EraseRootFromParent_Done,
     /*  796011 */   // Label 12797: @796011
     /*  796011 */   GIM_Try, /*On fail goto*//*Label 12798*/ GIMT_Encode4(796056), // Rule ID 7542 //
     /*  796016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  796019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8),
     /*  796024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796033 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796040 */     // (intrinsic_wo_chain:{ *:[i64] } 3330:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64),
     /*  796043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796045 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796047 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796049 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796054 */     GIR_RootConstrainSelectedInstOperands,
     /*  796055 */     // GIR_Coverage, 7542,
     /*  796055 */     GIR_EraseRootFromParent_Done,
     /*  796056 */   // Label 12798: @796056
     /*  796056 */   GIM_Try, /*On fail goto*//*Label 12799*/ GIMT_Encode4(796101), // Rule ID 7543 //
     /*  796061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  796064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8),
     /*  796069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796078 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796085 */     // (intrinsic_wo_chain:{ *:[i64] } 3330:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64),
     /*  796088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796090 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796092 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796094 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796099 */     GIR_RootConstrainSelectedInstOperands,
     /*  796100 */     // GIR_Coverage, 7543,
     /*  796100 */     GIR_EraseRootFromParent_Done,
     /*  796101 */   // Label 12799: @796101
     /*  796101 */   GIM_Try, /*On fail goto*//*Label 12800*/ GIMT_Encode4(796146), // Rule ID 7544 //
     /*  796106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  796109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8),
     /*  796114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796120 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796123 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796130 */     // (intrinsic_wo_chain:{ *:[i64] } 3360:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64),
     /*  796133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796135 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796137 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796139 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796144 */     GIR_RootConstrainSelectedInstOperands,
     /*  796145 */     // GIR_Coverage, 7544,
     /*  796145 */     GIR_EraseRootFromParent_Done,
     /*  796146 */   // Label 12800: @796146
     /*  796146 */   GIM_Try, /*On fail goto*//*Label 12801*/ GIMT_Encode4(796191), // Rule ID 7545 //
     /*  796151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  796154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8),
     /*  796159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796165 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796168 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796175 */     // (intrinsic_wo_chain:{ *:[i64] } 3360:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64),
     /*  796178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796180 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796182 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796184 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796189 */     GIR_RootConstrainSelectedInstOperands,
     /*  796190 */     // GIR_Coverage, 7545,
     /*  796190 */     GIR_EraseRootFromParent_Done,
     /*  796191 */   // Label 12801: @796191
     /*  796191 */   GIM_Try, /*On fail goto*//*Label 12802*/ GIMT_Encode4(796236), // Rule ID 7546 //
     /*  796196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  796199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8),
     /*  796204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796220 */     // (intrinsic_wo_chain:{ *:[i64] } 3360:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64),
     /*  796223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796225 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796227 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796229 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796234 */     GIR_RootConstrainSelectedInstOperands,
     /*  796235 */     // GIR_Coverage, 7546,
     /*  796235 */     GIR_EraseRootFromParent_Done,
     /*  796236 */   // Label 12802: @796236
     /*  796236 */   GIM_Try, /*On fail goto*//*Label 12803*/ GIMT_Encode4(796281), // Rule ID 7547 //
     /*  796241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  796244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8),
     /*  796249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796258 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796265 */     // (intrinsic_wo_chain:{ *:[i64] } 3360:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64),
     /*  796268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796270 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796272 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796274 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796279 */     GIR_RootConstrainSelectedInstOperands,
     /*  796280 */     // GIR_Coverage, 7547,
     /*  796280 */     GIR_EraseRootFromParent_Done,
     /*  796281 */   // Label 12803: @796281
     /*  796281 */   GIM_Try, /*On fail goto*//*Label 12804*/ GIMT_Encode4(796326), // Rule ID 7548 //
     /*  796286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  796289 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8),
     /*  796294 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  796297 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796300 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796303 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  796306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  796310 */     // (intrinsic_wo_chain:{ *:[i64] } 3360:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
     /*  796310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64),
     /*  796313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796315 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796317 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796319 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796324 */     GIR_RootConstrainSelectedInstOperands,
     /*  796325 */     // GIR_Coverage, 7548,
     /*  796325 */     GIR_EraseRootFromParent_Done,
     /*  796326 */   // Label 12804: @796326
     /*  796326 */   GIM_Try, /*On fail goto*//*Label 12805*/ GIMT_Encode4(796371), // Rule ID 7549 //
     /*  796331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  796334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8),
     /*  796339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  796342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796348 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  796351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  796355 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3331:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
     /*  796355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64),
     /*  796358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796360 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796362 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796364 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796369 */     GIR_RootConstrainSelectedInstOperands,
     /*  796370 */     // GIR_Coverage, 7549,
     /*  796370 */     GIR_EraseRootFromParent_Done,
     /*  796371 */   // Label 12805: @796371
     /*  796371 */   GIM_Try, /*On fail goto*//*Label 12806*/ GIMT_Encode4(796416), // Rule ID 7550 //
     /*  796376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  796379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8),
     /*  796384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  796387 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796390 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796393 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  796396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  796400 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3331:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
     /*  796400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64),
     /*  796403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796405 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796407 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796409 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796414 */     GIR_RootConstrainSelectedInstOperands,
     /*  796415 */     // GIR_Coverage, 7550,
     /*  796415 */     GIR_EraseRootFromParent_Done,
     /*  796416 */   // Label 12806: @796416
     /*  796416 */   GIM_Try, /*On fail goto*//*Label 12807*/ GIMT_Encode4(796461), // Rule ID 7551 //
     /*  796421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  796424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8),
     /*  796429 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  796432 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796435 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796438 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  796441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  796445 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3331:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
     /*  796445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64),
     /*  796448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796450 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796452 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796454 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796459 */     GIR_RootConstrainSelectedInstOperands,
     /*  796460 */     // GIR_Coverage, 7551,
     /*  796460 */     GIR_EraseRootFromParent_Done,
     /*  796461 */   // Label 12807: @796461
     /*  796461 */   GIM_Try, /*On fail goto*//*Label 12808*/ GIMT_Encode4(796506), // Rule ID 7552 //
     /*  796466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  796469 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8),
     /*  796474 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  796477 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796480 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796483 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  796486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  796490 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3331:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
     /*  796490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64),
     /*  796493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796495 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796497 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796499 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796504 */     GIR_RootConstrainSelectedInstOperands,
     /*  796505 */     // GIR_Coverage, 7552,
     /*  796505 */     GIR_EraseRootFromParent_Done,
     /*  796506 */   // Label 12808: @796506
     /*  796506 */   GIM_Try, /*On fail goto*//*Label 12809*/ GIMT_Encode4(796551), // Rule ID 7553 //
     /*  796511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  796514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8),
     /*  796519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  796522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  796525 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796528 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  796531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  796535 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3331:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
     /*  796535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64),
     /*  796538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796540 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  796542 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  796544 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  796546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  796549 */     GIR_RootConstrainSelectedInstOperands,
     /*  796550 */     // GIR_Coverage, 7553,
     /*  796550 */     GIR_EraseRootFromParent_Done,
     /*  796551 */   // Label 12809: @796551
     /*  796551 */   GIM_Try, /*On fail goto*//*Label 12810*/ GIMT_Encode4(796648), // Rule ID 2782 //
     /*  796556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
     /*  796559 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
     /*  796564 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  796567 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  796570 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796573 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  796576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  796580 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  796587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796601 */     // (intrinsic_wo_chain:{ *:[f32] } 2456:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  796601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64),
     /*  796604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  796611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  796616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  796621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  796626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  796631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  796636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  796641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  796646 */     GIR_RootConstrainSelectedInstOperands,
     /*  796647 */     // GIR_Coverage, 2782,
     /*  796647 */     GIR_EraseRootFromParent_Done,
     /*  796648 */   // Label 12810: @796648
     /*  796648 */   GIM_Try, /*On fail goto*//*Label 12811*/ GIMT_Encode4(796745), // Rule ID 2784 //
     /*  796653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32),
     /*  796656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy),
     /*  796661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  796664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  796667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796670 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  796673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  796677 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  796684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796698 */     // (intrinsic_wo_chain:{ *:[f32] } 2455:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  796698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_LEGACY_F32_e64),
     /*  796701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  796708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  796713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  796718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  796723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  796728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  796733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  796738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  796743 */     GIR_RootConstrainSelectedInstOperands,
     /*  796744 */     // GIR_Coverage, 2784,
     /*  796744 */     GIR_EraseRootFromParent_Done,
     /*  796745 */   // Label 12811: @796745
     /*  796745 */   GIM_Try, /*On fail goto*//*Label 12812*/ GIMT_Encode4(796842), // Rule ID 2879 //
     /*  796750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCubeInsts),
     /*  796753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubeid),
     /*  796758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  796761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  796764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  796770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  796774 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  796781 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796795 */     // (intrinsic_wo_chain:{ *:[f32] } 2267:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  796795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBEID_F32_e64),
     /*  796798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  796805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  796810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  796815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  796820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  796825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  796830 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  796835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  796840 */     GIR_RootConstrainSelectedInstOperands,
     /*  796841 */     // GIR_Coverage, 2879,
     /*  796841 */     GIR_EraseRootFromParent_Done,
     /*  796842 */   // Label 12812: @796842
     /*  796842 */   GIM_Try, /*On fail goto*//*Label 12813*/ GIMT_Encode4(796939), // Rule ID 2880 //
     /*  796847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCubeInsts),
     /*  796850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubesc),
     /*  796855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  796858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  796861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796864 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  796867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  796871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  796878 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796892 */     // (intrinsic_wo_chain:{ *:[f32] } 2269:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  796892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBESC_F32_e64),
     /*  796895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796897 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  796902 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  796907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  796912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  796917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  796922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  796927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  796932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  796937 */     GIR_RootConstrainSelectedInstOperands,
     /*  796938 */     // GIR_Coverage, 2880,
     /*  796938 */     GIR_EraseRootFromParent_Done,
     /*  796939 */   // Label 12813: @796939
     /*  796939 */   GIM_Try, /*On fail goto*//*Label 12814*/ GIMT_Encode4(797036), // Rule ID 2881 //
     /*  796944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCubeInsts),
     /*  796947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubetc),
     /*  796952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  796955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  796958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  796961 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  796964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  796968 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  796975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  796989 */     // (intrinsic_wo_chain:{ *:[f32] } 2270:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  796989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBETC_F32_e64),
     /*  796992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  796994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  796999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797034 */     GIR_RootConstrainSelectedInstOperands,
     /*  797035 */     // GIR_Coverage, 2881,
     /*  797035 */     GIR_EraseRootFromParent_Done,
     /*  797036 */   // Label 12814: @797036
     /*  797036 */   GIM_Try, /*On fail goto*//*Label 12815*/ GIMT_Encode4(797133), // Rule ID 2882 //
     /*  797041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCubeInsts),
     /*  797044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubema),
     /*  797049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  797052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  797055 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  797058 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  797061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  797065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797072 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797086 */     // (intrinsic_wo_chain:{ *:[f32] } 2268:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBEMA_F32_e64),
     /*  797089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797131 */     GIR_RootConstrainSelectedInstOperands,
     /*  797132 */     // GIR_Coverage, 2882,
     /*  797132 */     GIR_EraseRootFromParent_Done,
     /*  797133 */   // Label 12815: @797133
     /*  797133 */   GIM_Try, /*On fail goto*//*Label 12816*/ GIMT_Encode4(797227), // Rule ID 2899 //
     /*  797138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3),
     /*  797143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  797146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  797149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  797152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  797155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  797159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797166 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797173 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797180 */     // (intrinsic_wo_chain:{ *:[f32] } 2457:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
     /*  797183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797225 */     GIR_RootConstrainSelectedInstOperands,
     /*  797226 */     // GIR_Coverage, 2899,
     /*  797226 */     GIR_EraseRootFromParent_Done,
     /*  797227 */   // Label 12816: @797227
     /*  797227 */   GIM_Try, /*On fail goto*//*Label 12817*/ GIMT_Encode4(797316), // Rule ID 2903 //
     /*  797232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_u8_f32),
     /*  797237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  797240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  797243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  797246 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  797249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  797253 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797267 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797274 */     // (intrinsic_wo_chain:{ *:[i32] } 2288:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  797274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U8_F32_e64),
     /*  797277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797314 */     GIR_RootConstrainSelectedInstOperands,
     /*  797315 */     // GIR_Coverage, 2903,
     /*  797315 */     GIR_EraseRootFromParent_Done,
     /*  797316 */   // Label 12817: @797316
     /*  797316 */   GIM_Try, /*On fail goto*//*Label 12818*/ GIMT_Encode4(797410), // Rule ID 2904 //
     /*  797321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  797329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  797332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  797335 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  797338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  797342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797363 */     // (intrinsic_wo_chain:{ *:[f32] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F32_e64),
     /*  797366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797408 */     GIR_RootConstrainSelectedInstOperands,
     /*  797409 */     // GIR_Coverage, 2904,
     /*  797409 */     GIR_EraseRootFromParent_Done,
     /*  797410 */   // Label 12818: @797410
     /*  797410 */   GIM_Try, /*On fail goto*//*Label 12819*/ GIMT_Encode4(797507), // Rule ID 2906 //
     /*  797415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  797418 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797423 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  797426 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  797429 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  797432 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  797435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  797439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797446 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797453 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797460 */     // (intrinsic_wo_chain:{ *:[f64] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64),
     /*  797463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797505 */     GIR_RootConstrainSelectedInstOperands,
     /*  797506 */     // GIR_Coverage, 2906,
     /*  797506 */     GIR_EraseRootFromParent_Done,
     /*  797507 */   // Label 12819: @797507
     /*  797507 */   GIM_Try, /*On fail goto*//*Label 12820*/ GIMT_Encode4(797604), // Rule ID 2907 //
     /*  797512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  797515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  797523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  797526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  797529 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  797532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  797536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797557 */     // (intrinsic_wo_chain:{ *:[f64] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64),
     /*  797560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797602 */     GIR_RootConstrainSelectedInstOperands,
     /*  797603 */     // GIR_Coverage, 2907,
     /*  797603 */     GIR_EraseRootFromParent_Done,
     /*  797604 */   // Label 12820: @797604
     /*  797604 */   GIM_Try, /*On fail goto*//*Label 12821*/ GIMT_Encode4(797701), // Rule ID 2908 //
     /*  797609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  797612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  797620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  797623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  797626 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  797629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  797633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797640 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797654 */     // (intrinsic_wo_chain:{ *:[f64] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64),
     /*  797657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797699 */     GIR_RootConstrainSelectedInstOperands,
     /*  797700 */     // GIR_Coverage, 2908,
     /*  797700 */     GIR_EraseRootFromParent_Done,
     /*  797701 */   // Label 12821: @797701
     /*  797701 */   GIM_Try, /*On fail goto*//*Label 12822*/ GIMT_Encode4(797798), // Rule ID 2909 //
     /*  797706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  797709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  797717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  797720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  797723 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  797726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  797730 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797744 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797751 */     // (intrinsic_wo_chain:{ *:[f64] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64),
     /*  797754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797796 */     GIR_RootConstrainSelectedInstOperands,
     /*  797797 */     // GIR_Coverage, 2909,
     /*  797797 */     GIR_EraseRootFromParent_Done,
     /*  797798 */   // Label 12822: @797798
     /*  797798 */   GIM_Try, /*On fail goto*//*Label 12823*/ GIMT_Encode4(797895), // Rule ID 2910 //
     /*  797803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  797806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  797814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  797817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  797820 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  797823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  797827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797841 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797848 */     // (intrinsic_wo_chain:{ *:[f64] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64),
     /*  797851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797893 */     GIR_RootConstrainSelectedInstOperands,
     /*  797894 */     // GIR_Coverage, 2910,
     /*  797894 */     GIR_EraseRootFromParent_Done,
     /*  797895 */   // Label 12823: @797895
     /*  797895 */   GIM_Try, /*On fail goto*//*Label 12824*/ GIMT_Encode4(797992), // Rule ID 2993 //
     /*  797900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only),
     /*  797903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  797908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  797911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  797914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  797917 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  797920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  797924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  797931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797938 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  797945 */     // (intrinsic_wo_chain:{ *:[f16] } 2398:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  797945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_e64),
     /*  797948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  797950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  797955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  797960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  797965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  797970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  797975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  797980 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  797985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  797990 */     GIR_RootConstrainSelectedInstOperands,
     /*  797991 */     // GIR_Coverage, 2993,
     /*  797991 */     GIR_EraseRootFromParent_Done,
     /*  797992 */   // Label 12824: @797992
     /*  797992 */   GIM_Try, /*On fail goto*//*Label 12825*/ GIMT_Encode4(798089), // Rule ID 3010 //
     /*  797997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
     /*  798000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
     /*  798005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798014 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  798028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  798035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  798042 */     // (intrinsic_wo_chain:{ *:[f16] } 2456:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  798042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64),
     /*  798045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  798082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  798087 */     GIR_RootConstrainSelectedInstOperands,
     /*  798088 */     // GIR_Coverage, 3010,
     /*  798088 */     GIR_EraseRootFromParent_Done,
     /*  798089 */   // Label 12825: @798089
     /*  798089 */   GIM_Try, /*On fail goto*//*Label 12826*/ GIMT_Encode4(798186), // Rule ID 3126 //
     /*  798094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  798097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_pk_f16_f32),
     /*  798102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  798105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  798108 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  798111 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  798114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798118 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  798125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  798132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  798139 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2394:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_SR_PK_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  798139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_PK_F16_F32_e64),
     /*  798142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
     /*  798179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
     /*  798184 */     GIR_RootConstrainSelectedInstOperands,
     /*  798185 */     // GIR_Coverage, 3126,
     /*  798185 */     GIR_EraseRootFromParent_Done,
     /*  798186 */   // Label 12826: @798186
     /*  798186 */   GIM_Try, /*On fail goto*//*Label 12827*/ GIMT_Encode4(798283), // Rule ID 31233 //
     /*  798191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32),
     /*  798194 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy),
     /*  798199 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  798202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  798205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  798208 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  798211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798215 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  798222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  798229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  798236 */     // (intrinsic_wo_chain:{ *:[f32] } 2455:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
     /*  798236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_LEGACY_F32_e64),
     /*  798239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  798246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  798251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /*  798256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /*  798261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
     /*  798276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
     /*  798281 */     GIR_RootConstrainSelectedInstOperands,
     /*  798282 */     // GIR_Coverage, 31233,
     /*  798282 */     GIR_EraseRootFromParent_Done,
     /*  798283 */   // Label 12827: @798283
     /*  798283 */   GIM_Try, /*On fail goto*//*Label 12828*/ GIMT_Encode4(798379), // Rule ID 2997 //
     /*  798288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX9Plus),
     /*  798291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  798296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798305 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798312 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798326 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798333 */     // (intrinsic_wo_chain:{ *:[f16] } 2398:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_gfx9_e64),
     /*  798336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798343 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798348 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798377 */     GIR_RootConstrainSelectedInstOperands,
     /*  798378 */     // GIR_Coverage, 2997,
     /*  798378 */     GIR_EraseRootFromParent_Done,
     /*  798379 */   // Label 12828: @798379
     /*  798379 */   GIM_Try, /*On fail goto*//*Label 12829*/ GIMT_Encode4(798475), // Rule ID 2999 //
     /*  798384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX9Plus),
     /*  798387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  798392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798401 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  798408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798429 */     // (intrinsic_wo_chain:{ *:[f16] } 2398:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F16_gfx9_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_gfx9_t16_e64),
     /*  798432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798473 */     GIR_RootConstrainSelectedInstOperands,
     /*  798474 */     // GIR_Coverage, 2999,
     /*  798474 */     GIR_EraseRootFromParent_Done,
     /*  798475 */   // Label 12829: @798475
     /*  798475 */   GIM_Try, /*On fail goto*//*Label 12830*/ GIMT_Encode4(798571), // Rule ID 3001 //
     /*  798480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX9Plus),
     /*  798483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
     /*  798488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798497 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798504 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798525 */     // (intrinsic_wo_chain:{ *:[f16] } 2398:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F16_gfx9_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_gfx9_fake16_e64),
     /*  798528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798545 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798569 */     GIR_RootConstrainSelectedInstOperands,
     /*  798570 */     // GIR_Coverage, 3001,
     /*  798570 */     GIR_EraseRootFromParent_Done,
     /*  798571 */   // Label 12830: @798571
     /*  798571 */   GIM_Try, /*On fail goto*//*Label 12831*/ GIMT_Encode4(798667), // Rule ID 3014 //
     /*  798576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX9Plus),
     /*  798579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3),
     /*  798584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798593 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798621 */     // (intrinsic_wo_chain:{ *:[f16] } 2457:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
     /*  798624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798662 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798665 */     GIR_RootConstrainSelectedInstOperands,
     /*  798666 */     // GIR_Coverage, 3014,
     /*  798666 */     GIR_EraseRootFromParent_Done,
     /*  798667 */   // Label 12831: @798667
     /*  798667 */   GIM_Try, /*On fail goto*//*Label 12832*/ GIMT_Encode4(798763), // Rule ID 3016 //
     /*  798672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX9Plus),
     /*  798675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3),
     /*  798680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798689 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  798696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798717 */     // (intrinsic_wo_chain:{ *:[f16] } 2457:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_t16_e64),
     /*  798720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798758 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798761 */     GIR_RootConstrainSelectedInstOperands,
     /*  798762 */     // GIR_Coverage, 3016,
     /*  798762 */     GIR_EraseRootFromParent_Done,
     /*  798763 */   // Label 12832: @798763
     /*  798763 */   GIM_Try, /*On fail goto*//*Label 12833*/ GIMT_Encode4(798859), // Rule ID 3018 //
     /*  798768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX9Plus),
     /*  798771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3),
     /*  798776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  798782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  798785 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798799 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798813 */     // (intrinsic_wo_chain:{ *:[f16] } 2457:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_fake16_e64),
     /*  798816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798857 */     GIR_RootConstrainSelectedInstOperands,
     /*  798858 */     // GIR_Coverage, 3018,
     /*  798858 */     GIR_EraseRootFromParent_Done,
     /*  798859 */   // Label 12833: @798859
     /*  798859 */   GIM_Try, /*On fail goto*//*Label 12834*/ GIMT_Encode4(798949), // Rule ID 3292 //
     /*  798864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts_NotHasTrue16BitInsts),
     /*  798867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f16_f16),
     /*  798872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  798878 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  798881 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  798888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798895 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798909 */     // (intrinsic_wo_chain:{ *:[f16] } 2446:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT2_F16_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F16_F16_e64),
     /*  798912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  798914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  798919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  798924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  798929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  798934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  798939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  798944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  798947 */     GIR_RootConstrainSelectedInstOperands,
     /*  798948 */     // GIR_Coverage, 3292,
     /*  798948 */     GIR_EraseRootFromParent_Done,
     /*  798949 */   // Label 12834: @798949
     /*  798949 */   GIM_Try, /*On fail goto*//*Label 12835*/ GIMT_Encode4(799039), // Rule ID 3293 //
     /*  798954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts_UseRealTrue16Insts),
     /*  798957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f16_f16),
     /*  798962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  798965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  798968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  798971 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  798974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  798978 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  798999 */     // (intrinsic_wo_chain:{ *:[f16] } 2446:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT2_F16_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  798999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F16_F16_t16_e64),
     /*  799002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  799009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  799019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  799024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  799029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  799034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  799037 */     GIR_RootConstrainSelectedInstOperands,
     /*  799038 */     // GIR_Coverage, 3293,
     /*  799038 */     GIR_EraseRootFromParent_Done,
     /*  799039 */   // Label 12835: @799039
     /*  799039 */   GIM_Try, /*On fail goto*//*Label 12836*/ GIMT_Encode4(799129), // Rule ID 3294 //
     /*  799044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts_UseFakeTrue16Insts),
     /*  799047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f16_f16),
     /*  799052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  799055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  799058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  799061 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  799064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799089 */     // (intrinsic_wo_chain:{ *:[f16] } 2446:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT2_F16_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
     /*  799089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F16_F16_fake16_e64),
     /*  799092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  799099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  799109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  799114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  799119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  799124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  799127 */     GIR_RootConstrainSelectedInstOperands,
     /*  799128 */     // GIR_Coverage, 3294,
     /*  799128 */     GIR_EraseRootFromParent_Done,
     /*  799129 */   // Label 12836: @799129
     /*  799129 */   GIM_Try, /*On fail goto*//*Label 12837*/ GIMT_Encode4(799219), // Rule ID 3305 //
     /*  799134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAshrPkInsts),
     /*  799137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ashr_pk_i8_i32),
     /*  799142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  799145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799151 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799179 */     // (intrinsic_wo_chain:{ *:[i16] } 2232:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_ASHR_PK_I8_I32_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2)
     /*  799179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_PK_I8_I32_e64),
     /*  799182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  799189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  799199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  799204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  799209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  799214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  799217 */     GIR_RootConstrainSelectedInstOperands,
     /*  799218 */     // GIR_Coverage, 3305,
     /*  799218 */     GIR_EraseRootFromParent_Done,
     /*  799219 */   // Label 12837: @799219
     /*  799219 */   GIM_Try, /*On fail goto*//*Label 12838*/ GIMT_Encode4(799309), // Rule ID 3306 //
     /*  799224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAshrPkInsts),
     /*  799227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ashr_pk_u8_i32),
     /*  799232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  799235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799241 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  799269 */     // (intrinsic_wo_chain:{ *:[i16] } 2233:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_ASHR_PK_U8_I32_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2)
     /*  799269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_PK_U8_I32_e64),
     /*  799272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  799279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  799289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  799294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  799299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  799304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  799307 */     GIR_RootConstrainSelectedInstOperands,
     /*  799308 */     // GIR_Coverage, 3306,
     /*  799308 */     GIR_EraseRootFromParent_Done,
     /*  799309 */   // Label 12838: @799309
     /*  799309 */   GIM_Try, /*On fail goto*//*Label 12839*/ GIMT_Encode4(799361), // Rule ID 2787 //
     /*  799314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLerpInst),
     /*  799317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lerp),
     /*  799322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  799325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799331 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799345 */     // (intrinsic_wo_chain:{ *:[i32] } 3272:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
     /*  799345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LERP_U8_e64),
     /*  799348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799355 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799357 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799359 */     GIR_RootConstrainSelectedInstOperands,
     /*  799360 */     // GIR_Coverage, 2787,
     /*  799360 */     GIR_EraseRootFromParent_Done,
     /*  799361 */   // Label 12839: @799361
     /*  799361 */   GIM_Try, /*On fail goto*//*Label 12840*/ GIMT_Encode4(799410), // Rule ID 2883 //
     /*  799366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ubfe),
     /*  799371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  799374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799380 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799394 */     // (intrinsic_wo_chain:{ *:[i32] } 3607:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_BFE_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
     /*  799394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
     /*  799397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799404 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799406 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799408 */     GIR_RootConstrainSelectedInstOperands,
     /*  799409 */     // GIR_Coverage, 2883,
     /*  799409 */     GIR_EraseRootFromParent_Done,
     /*  799410 */   // Label 12840: @799410
     /*  799410 */   GIM_Try, /*On fail goto*//*Label 12841*/ GIMT_Encode4(799459), // Rule ID 2885 //
     /*  799415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sbfe),
     /*  799420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  799423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799426 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799429 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799443 */     // (intrinsic_wo_chain:{ *:[i32] } 3480:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_BFE_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
     /*  799443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  799446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799453 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799455 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799457 */     GIR_RootConstrainSelectedInstOperands,
     /*  799458 */     // GIR_Coverage, 2885,
     /*  799458 */     GIR_EraseRootFromParent_Done,
     /*  799459 */   // Label 12841: @799459
     /*  799459 */   GIM_Try, /*On fail goto*//*Label 12842*/ GIMT_Encode4(799508), // Rule ID 2890 //
     /*  799464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_alignbyte),
     /*  799469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  799472 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799475 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799478 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799492 */     // (intrinsic_wo_chain:{ *:[i32] } 2231:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
     /*  799492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBYTE_B32_e64),
     /*  799495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799502 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799504 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799506 */     GIR_RootConstrainSelectedInstOperands,
     /*  799507 */     // GIR_Coverage, 2890,
     /*  799507 */     GIR_EraseRootFromParent_Done,
     /*  799508 */   // Label 12842: @799508
     /*  799508 */   GIM_Try, /*On fail goto*//*Label 12843*/ GIMT_Encode4(799560), // Rule ID 2991 //
     /*  799513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  799516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm),
     /*  799521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  799524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  799527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799530 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  799537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799544 */     // (intrinsic_wo_chain:{ *:[i32] } 3337:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_PERM_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
     /*  799544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*  799547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799554 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799556 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799558 */     GIR_RootConstrainSelectedInstOperands,
     /*  799559 */     // GIR_Coverage, 2991,
     /*  799559 */     GIR_EraseRootFromParent_Done,
     /*  799560 */   // Label 12843: @799560
     /*  799560 */   GIM_Try, /*On fail goto*//*Label 12844*/ GIMT_Encode4(799612), // Rule ID 3084 //
     /*  799565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0),
     /*  799568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f16),
     /*  799573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  799579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799582 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799589 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799596 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2372:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_e64),
     /*  799599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799606 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799608 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799610 */     GIR_RootConstrainSelectedInstOperands,
     /*  799611 */     // GIR_Coverage, 3084,
     /*  799611 */     GIR_EraseRootFromParent_Done,
     /*  799612 */   // Label 12844: @799612
     /*  799612 */   GIM_Try, /*On fail goto*//*Label 12845*/ GIMT_Encode4(799664), // Rule ID 3085 //
     /*  799617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1),
     /*  799620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f16),
     /*  799625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  799631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799634 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799648 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2372:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_e64),
     /*  799651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799658 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799660 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799662 */     GIR_RootConstrainSelectedInstOperands,
     /*  799663 */     // GIR_Coverage, 3085,
     /*  799663 */     GIR_EraseRootFromParent_Done,
     /*  799664 */   // Label 12845: @799664
     /*  799664 */   GIM_Try, /*On fail goto*//*Label 12846*/ GIMT_Encode4(799716), // Rule ID 3086 //
     /*  799669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2),
     /*  799672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f16),
     /*  799677 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  799683 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799686 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799700 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2372:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_e64),
     /*  799703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799710 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799712 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799714 */     GIR_RootConstrainSelectedInstOperands,
     /*  799715 */     // GIR_Coverage, 3086,
     /*  799715 */     GIR_EraseRootFromParent_Done,
     /*  799716 */   // Label 12846: @799716
     /*  799716 */   GIM_Try, /*On fail goto*//*Label 12847*/ GIMT_Encode4(799768), // Rule ID 3087 //
     /*  799721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3),
     /*  799724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f16),
     /*  799729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  799735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799738 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799745 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799752 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2372:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_e64),
     /*  799755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799762 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799764 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799766 */     GIR_RootConstrainSelectedInstOperands,
     /*  799767 */     // GIR_Coverage, 3087,
     /*  799767 */     GIR_EraseRootFromParent_Done,
     /*  799768 */   // Label 12847: @799768
     /*  799768 */   GIM_Try, /*On fail goto*//*Label 12848*/ GIMT_Encode4(799820), // Rule ID 3088 //
     /*  799773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4),
     /*  799776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f16),
     /*  799781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  799787 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799790 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799797 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799804 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2372:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F16_e64),
     /*  799807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799814 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799816 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799818 */     GIR_RootConstrainSelectedInstOperands,
     /*  799819 */     // GIR_Coverage, 3088,
     /*  799819 */     GIR_EraseRootFromParent_Done,
     /*  799820 */   // Label 12848: @799820
     /*  799820 */   GIM_Try, /*On fail goto*//*Label 12849*/ GIMT_Encode4(799872), // Rule ID 3089 //
     /*  799825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0),
     /*  799828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f32),
     /*  799833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  799839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799842 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799856 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2373:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_e64),
     /*  799859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799866 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799868 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799870 */     GIR_RootConstrainSelectedInstOperands,
     /*  799871 */     // GIR_Coverage, 3089,
     /*  799871 */     GIR_EraseRootFromParent_Done,
     /*  799872 */   // Label 12849: @799872
     /*  799872 */   GIM_Try, /*On fail goto*//*Label 12850*/ GIMT_Encode4(799924), // Rule ID 3090 //
     /*  799877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1),
     /*  799880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f32),
     /*  799885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  799891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799894 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799908 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2373:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_e64),
     /*  799911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799918 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799920 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799922 */     GIR_RootConstrainSelectedInstOperands,
     /*  799923 */     // GIR_Coverage, 3090,
     /*  799923 */     GIR_EraseRootFromParent_Done,
     /*  799924 */   // Label 12850: @799924
     /*  799924 */   GIM_Try, /*On fail goto*//*Label 12851*/ GIMT_Encode4(799976), // Rule ID 3091 //
     /*  799929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2),
     /*  799932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f32),
     /*  799937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  799943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799946 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  799949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  799953 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  799960 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2373:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  799960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_e64),
     /*  799963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  799965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  799970 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  799972 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  799974 */     GIR_RootConstrainSelectedInstOperands,
     /*  799975 */     // GIR_Coverage, 3091,
     /*  799975 */     GIR_EraseRootFromParent_Done,
     /*  799976 */   // Label 12851: @799976
     /*  799976 */   GIM_Try, /*On fail goto*//*Label 12852*/ GIMT_Encode4(800028), // Rule ID 3092 //
     /*  799981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3),
     /*  799984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f32),
     /*  799989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  799992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  799995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  799998 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800012 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2373:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_e64),
     /*  800015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800017 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800022 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800024 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800026 */     GIR_RootConstrainSelectedInstOperands,
     /*  800027 */     // GIR_Coverage, 3092,
     /*  800027 */     GIR_EraseRootFromParent_Done,
     /*  800028 */   // Label 12852: @800028
     /*  800028 */   GIM_Try, /*On fail goto*//*Label 12853*/ GIMT_Encode4(800080), // Rule ID 3093 //
     /*  800033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4),
     /*  800036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_bf6_f32),
     /*  800041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  800047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800050 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800057 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800064 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2373:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_BF6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_BF6_F32_e64),
     /*  800067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800074 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800076 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800078 */     GIR_RootConstrainSelectedInstOperands,
     /*  800079 */     // GIR_Coverage, 3093,
     /*  800079 */     GIR_EraseRootFromParent_Done,
     /*  800080 */   // Label 12853: @800080
     /*  800080 */   GIM_Try, /*On fail goto*//*Label 12854*/ GIMT_Encode4(800132), // Rule ID 3094 //
     /*  800085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0),
     /*  800088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f16),
     /*  800093 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800096 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  800099 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800102 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800116 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2375:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_e64),
     /*  800119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800126 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800128 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800130 */     GIR_RootConstrainSelectedInstOperands,
     /*  800131 */     // GIR_Coverage, 3094,
     /*  800131 */     GIR_EraseRootFromParent_Done,
     /*  800132 */   // Label 12854: @800132
     /*  800132 */   GIM_Try, /*On fail goto*//*Label 12855*/ GIMT_Encode4(800184), // Rule ID 3095 //
     /*  800137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1),
     /*  800140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f16),
     /*  800145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  800151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800154 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800168 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2375:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_e64),
     /*  800171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800178 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800180 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800182 */     GIR_RootConstrainSelectedInstOperands,
     /*  800183 */     // GIR_Coverage, 3095,
     /*  800183 */     GIR_EraseRootFromParent_Done,
     /*  800184 */   // Label 12855: @800184
     /*  800184 */   GIM_Try, /*On fail goto*//*Label 12856*/ GIMT_Encode4(800236), // Rule ID 3096 //
     /*  800189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2),
     /*  800192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f16),
     /*  800197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  800203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800206 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800213 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800220 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2375:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_e64),
     /*  800223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800230 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800232 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800234 */     GIR_RootConstrainSelectedInstOperands,
     /*  800235 */     // GIR_Coverage, 3096,
     /*  800235 */     GIR_EraseRootFromParent_Done,
     /*  800236 */   // Label 12856: @800236
     /*  800236 */   GIM_Try, /*On fail goto*//*Label 12857*/ GIMT_Encode4(800288), // Rule ID 3097 //
     /*  800241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3),
     /*  800244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f16),
     /*  800249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  800255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800258 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800265 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800272 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2375:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_e64),
     /*  800275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800282 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800284 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800286 */     GIR_RootConstrainSelectedInstOperands,
     /*  800287 */     // GIR_Coverage, 3097,
     /*  800287 */     GIR_EraseRootFromParent_Done,
     /*  800288 */   // Label 12857: @800288
     /*  800288 */   GIM_Try, /*On fail goto*//*Label 12858*/ GIMT_Encode4(800340), // Rule ID 3098 //
     /*  800293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4),
     /*  800296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f16),
     /*  800301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s16,
     /*  800307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800310 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800317 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800324 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2375:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f16] } v32f16:{ *:[v32f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F16_e64:{ *:[v6i32] } v32f16:{ *:[v32f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F16_e64),
     /*  800327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800334 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800336 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800338 */     GIR_RootConstrainSelectedInstOperands,
     /*  800339 */     // GIR_Coverage, 3098,
     /*  800339 */     GIR_EraseRootFromParent_Done,
     /*  800340 */   // Label 12858: @800340
     /*  800340 */   GIM_Try, /*On fail goto*//*Label 12859*/ GIMT_Encode4(800392), // Rule ID 3099 //
     /*  800345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode0),
     /*  800348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f32),
     /*  800353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800356 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  800359 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800362 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800376 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2376:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_e64),
     /*  800379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800386 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800388 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800390 */     GIR_RootConstrainSelectedInstOperands,
     /*  800391 */     // GIR_Coverage, 3099,
     /*  800391 */     GIR_EraseRootFromParent_Done,
     /*  800392 */   // Label 12859: @800392
     /*  800392 */   GIM_Try, /*On fail goto*//*Label 12860*/ GIMT_Encode4(800444), // Rule ID 3100 //
     /*  800397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode1),
     /*  800400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f32),
     /*  800405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  800411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800414 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800428 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2376:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_e64),
     /*  800431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800438 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800440 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800442 */     GIR_RootConstrainSelectedInstOperands,
     /*  800443 */     // GIR_Coverage, 3100,
     /*  800443 */     GIR_EraseRootFromParent_Done,
     /*  800444 */   // Label 12860: @800444
     /*  800444 */   GIM_Try, /*On fail goto*//*Label 12861*/ GIMT_Encode4(800496), // Rule ID 3101 //
     /*  800449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode2),
     /*  800452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f32),
     /*  800457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  800463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800466 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800473 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800480 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2376:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_e64),
     /*  800483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800490 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800492 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800494 */     GIR_RootConstrainSelectedInstOperands,
     /*  800495 */     // GIR_Coverage, 3101,
     /*  800495 */     GIR_EraseRootFromParent_Done,
     /*  800496 */   // Label 12861: @800496
     /*  800496 */   GIM_Try, /*On fail goto*//*Label 12862*/ GIMT_Encode4(800548), // Rule ID 3102 //
     /*  800501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode3),
     /*  800504 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f32),
     /*  800509 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800512 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  800515 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800518 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800532 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2376:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_e64),
     /*  800535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800542 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800544 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800546 */     GIR_RootConstrainSelectedInstOperands,
     /*  800547 */     // GIR_Coverage, 3102,
     /*  800547 */     GIR_EraseRootFromParent_Done,
     /*  800548 */   // Label 12862: @800548
     /*  800548 */   GIM_Try, /*On fail goto*//*Label 12863*/ GIMT_Encode4(800600), // Rule ID 3103 //
     /*  800553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF16BF16ToFP6BF6ConversionScaleInsts_HwMode4),
     /*  800556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk32_fp6_f32),
     /*  800561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v32s32,
     /*  800567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  800570 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800584 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2376:{ *:[iPTR] }, (VOP3Mods0:{ *:[v32f32] } v32f32:{ *:[v32f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK32_FP6_F32_e64:{ *:[v6i32] } v32f32:{ *:[v32f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK32_FP6_F32_e64),
     /*  800587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800594 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800596 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800598 */     GIR_RootConstrainSelectedInstOperands,
     /*  800599 */     // GIR_Coverage, 3103,
     /*  800599 */     GIR_EraseRootFromParent_Done,
     /*  800600 */   // Label 12863: @800600
     /*  800600 */   GIM_Try, /*On fail goto*//*Label 12864*/ GIMT_Encode4(800652), // Rule ID 3104 //
     /*  800605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  800608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_fp6_f32),
     /*  800613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800616 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800619 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800622 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800636 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2308:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_FP6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_e64),
     /*  800639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800646 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800648 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800650 */     GIR_RootConstrainSelectedInstOperands,
     /*  800651 */     // GIR_Coverage, 3104,
     /*  800651 */     GIR_EraseRootFromParent_Done,
     /*  800652 */   // Label 12864: @800652
     /*  800652 */   GIM_Try, /*On fail goto*//*Label 12865*/ GIMT_Encode4(800704), // Rule ID 3105 //
     /*  800657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  800660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_fp6_f32),
     /*  800665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800674 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800688 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2308:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_FP6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_e64),
     /*  800691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800698 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800700 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800702 */     GIR_RootConstrainSelectedInstOperands,
     /*  800703 */     // GIR_Coverage, 3105,
     /*  800703 */     GIR_EraseRootFromParent_Done,
     /*  800704 */   // Label 12865: @800704
     /*  800704 */   GIM_Try, /*On fail goto*//*Label 12866*/ GIMT_Encode4(800756), // Rule ID 3106 //
     /*  800709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  800712 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_fp6_f32),
     /*  800717 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800726 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800740 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2308:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_FP6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_e64),
     /*  800743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800750 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800752 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800754 */     GIR_RootConstrainSelectedInstOperands,
     /*  800755 */     // GIR_Coverage, 3106,
     /*  800755 */     GIR_EraseRootFromParent_Done,
     /*  800756 */   // Label 12866: @800756
     /*  800756 */   GIM_Try, /*On fail goto*//*Label 12867*/ GIMT_Encode4(800808), // Rule ID 3107 //
     /*  800761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  800764 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_fp6_f32),
     /*  800769 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800775 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800778 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800792 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2308:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_FP6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_e64),
     /*  800795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800802 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800804 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800806 */     GIR_RootConstrainSelectedInstOperands,
     /*  800807 */     // GIR_Coverage, 3107,
     /*  800807 */     GIR_EraseRootFromParent_Done,
     /*  800808 */   // Label 12867: @800808
     /*  800808 */   GIM_Try, /*On fail goto*//*Label 12868*/ GIMT_Encode4(800860), // Rule ID 3108 //
     /*  800813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  800816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_fp6_f32),
     /*  800821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800830 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800837 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800844 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2308:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_FP6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_FP6_F32_e64),
     /*  800847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800854 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800856 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800858 */     GIR_RootConstrainSelectedInstOperands,
     /*  800859 */     // GIR_Coverage, 3108,
     /*  800859 */     GIR_EraseRootFromParent_Done,
     /*  800860 */   // Label 12868: @800860
     /*  800860 */   GIM_Try, /*On fail goto*//*Label 12869*/ GIMT_Encode4(800912), // Rule ID 3109 //
     /*  800865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  800868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_bf6_f32),
     /*  800873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800876 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800879 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800882 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800896 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2307:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_BF6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_e64),
     /*  800899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800906 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800908 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800910 */     GIR_RootConstrainSelectedInstOperands,
     /*  800911 */     // GIR_Coverage, 3109,
     /*  800911 */     GIR_EraseRootFromParent_Done,
     /*  800912 */   // Label 12869: @800912
     /*  800912 */   GIM_Try, /*On fail goto*//*Label 12870*/ GIMT_Encode4(800964), // Rule ID 3110 //
     /*  800917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  800920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_bf6_f32),
     /*  800925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800934 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  800948 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2307:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_BF6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  800948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_e64),
     /*  800951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  800953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  800958 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  800960 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  800962 */     GIR_RootConstrainSelectedInstOperands,
     /*  800963 */     // GIR_Coverage, 3110,
     /*  800963 */     GIR_EraseRootFromParent_Done,
     /*  800964 */   // Label 12870: @800964
     /*  800964 */   GIM_Try, /*On fail goto*//*Label 12871*/ GIMT_Encode4(801016), // Rule ID 3111 //
     /*  800969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  800972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_bf6_f32),
     /*  800977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  800980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  800983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  800986 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  800989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  800993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801000 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2307:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_BF6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_e64),
     /*  801003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801010 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801012 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801014 */     GIR_RootConstrainSelectedInstOperands,
     /*  801015 */     // GIR_Coverage, 3111,
     /*  801015 */     GIR_EraseRootFromParent_Done,
     /*  801016 */   // Label 12871: @801016
     /*  801016 */   GIM_Try, /*On fail goto*//*Label 12872*/ GIMT_Encode4(801068), // Rule ID 3112 //
     /*  801021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  801024 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_bf6_f32),
     /*  801029 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  801032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  801035 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  801038 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  801045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801052 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2307:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_BF6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_e64),
     /*  801055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801062 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801064 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801066 */     GIR_RootConstrainSelectedInstOperands,
     /*  801067 */     // GIR_Coverage, 3112,
     /*  801067 */     GIR_EraseRootFromParent_Done,
     /*  801068 */   // Label 12872: @801068
     /*  801068 */   GIM_Try, /*On fail goto*//*Label 12873*/ GIMT_Encode4(801120), // Rule ID 3113 //
     /*  801073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  801076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_2xpk16_bf6_f32),
     /*  801081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v6s32,
     /*  801084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  801087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  801090 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
     /*  801097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801104 */     // (intrinsic_wo_chain:{ *:[v6i32] } 2307:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_2XPK16_BF6_F32_e64:{ *:[v6i32] } v16f32:{ *:[v16f32] }:$src0, v16f32:{ *:[v16f32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_2XPK16_BF6_F32_e64),
     /*  801107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801114 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801116 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801118 */     GIR_RootConstrainSelectedInstOperands,
     /*  801119 */     // GIR_Coverage, 3113,
     /*  801119 */     GIR_EraseRootFromParent_Done,
     /*  801120 */   // Label 12873: @801120
     /*  801120 */   GIM_Try, /*On fail goto*//*Label 12874*/ GIMT_Encode4(801172), // Rule ID 3227 //
     /*  801125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  801128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f16),
     /*  801133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801139 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801142 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801149 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801156 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2384:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64),
     /*  801159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801166 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801168 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801170 */     GIR_RootConstrainSelectedInstOperands,
     /*  801171 */     // GIR_Coverage, 3227,
     /*  801171 */     GIR_EraseRootFromParent_Done,
     /*  801172 */   // Label 12874: @801172
     /*  801172 */   GIM_Try, /*On fail goto*//*Label 12875*/ GIMT_Encode4(801224), // Rule ID 3228 //
     /*  801177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  801180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f16),
     /*  801185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801194 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801201 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801208 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2384:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64),
     /*  801211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801218 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801220 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801222 */     GIR_RootConstrainSelectedInstOperands,
     /*  801223 */     // GIR_Coverage, 3228,
     /*  801223 */     GIR_EraseRootFromParent_Done,
     /*  801224 */   // Label 12875: @801224
     /*  801224 */   GIM_Try, /*On fail goto*//*Label 12876*/ GIMT_Encode4(801276), // Rule ID 3229 //
     /*  801229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  801232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f16),
     /*  801237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801246 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801253 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801260 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2384:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64),
     /*  801263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801270 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801272 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801274 */     GIR_RootConstrainSelectedInstOperands,
     /*  801275 */     // GIR_Coverage, 3229,
     /*  801275 */     GIR_EraseRootFromParent_Done,
     /*  801276 */   // Label 12876: @801276
     /*  801276 */   GIM_Try, /*On fail goto*//*Label 12877*/ GIMT_Encode4(801328), // Rule ID 3230 //
     /*  801281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  801284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f16),
     /*  801289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801298 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801312 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2384:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64),
     /*  801315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801322 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801324 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801326 */     GIR_RootConstrainSelectedInstOperands,
     /*  801327 */     // GIR_Coverage, 3230,
     /*  801327 */     GIR_EraseRootFromParent_Done,
     /*  801328 */   // Label 12877: @801328
     /*  801328 */   GIM_Try, /*On fail goto*//*Label 12878*/ GIMT_Encode4(801380), // Rule ID 3231 //
     /*  801333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  801336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f16),
     /*  801341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801350 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801364 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2384:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F16_e64),
     /*  801367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801374 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801376 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801378 */     GIR_RootConstrainSelectedInstOperands,
     /*  801379 */     // GIR_Coverage, 3231,
     /*  801379 */     GIR_EraseRootFromParent_Done,
     /*  801380 */   // Label 12878: @801380
     /*  801380 */   GIM_Try, /*On fail goto*//*Label 12879*/ GIMT_Encode4(801432), // Rule ID 3232 //
     /*  801385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  801388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f16),
     /*  801393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801402 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801409 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801416 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2378:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64),
     /*  801419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801421 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801426 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801428 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801430 */     GIR_RootConstrainSelectedInstOperands,
     /*  801431 */     // GIR_Coverage, 3232,
     /*  801431 */     GIR_EraseRootFromParent_Done,
     /*  801432 */   // Label 12879: @801432
     /*  801432 */   GIM_Try, /*On fail goto*//*Label 12880*/ GIMT_Encode4(801484), // Rule ID 3233 //
     /*  801437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  801440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f16),
     /*  801445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801454 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801468 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2378:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64),
     /*  801471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801478 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801480 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801482 */     GIR_RootConstrainSelectedInstOperands,
     /*  801483 */     // GIR_Coverage, 3233,
     /*  801483 */     GIR_EraseRootFromParent_Done,
     /*  801484 */   // Label 12880: @801484
     /*  801484 */   GIM_Try, /*On fail goto*//*Label 12881*/ GIMT_Encode4(801536), // Rule ID 3234 //
     /*  801489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  801492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f16),
     /*  801497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801506 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801520 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2378:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64),
     /*  801523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801530 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801532 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801534 */     GIR_RootConstrainSelectedInstOperands,
     /*  801535 */     // GIR_Coverage, 3234,
     /*  801535 */     GIR_EraseRootFromParent_Done,
     /*  801536 */   // Label 12881: @801536
     /*  801536 */   GIM_Try, /*On fail goto*//*Label 12882*/ GIMT_Encode4(801588), // Rule ID 3235 //
     /*  801541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  801544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f16),
     /*  801549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801555 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801558 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801572 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2378:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64),
     /*  801575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801582 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801584 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801586 */     GIR_RootConstrainSelectedInstOperands,
     /*  801587 */     // GIR_Coverage, 3235,
     /*  801587 */     GIR_EraseRootFromParent_Done,
     /*  801588 */   // Label 12882: @801588
     /*  801588 */   GIM_Try, /*On fail goto*//*Label 12883*/ GIMT_Encode4(801640), // Rule ID 3236 //
     /*  801593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  801596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f16),
     /*  801601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  801607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801610 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801624 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2378:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F16_e64:{ *:[v2i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F16_e64),
     /*  801627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801634 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801636 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801638 */     GIR_RootConstrainSelectedInstOperands,
     /*  801639 */     // GIR_Coverage, 3236,
     /*  801639 */     GIR_EraseRootFromParent_Done,
     /*  801640 */   // Label 12883: @801640
     /*  801640 */   GIM_Try, /*On fail goto*//*Label 12884*/ GIMT_Encode4(801692), // Rule ID 3237 //
     /*  801645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  801648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f32),
     /*  801653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801662 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801669 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801676 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2385:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64),
     /*  801679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801686 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801688 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801690 */     GIR_RootConstrainSelectedInstOperands,
     /*  801691 */     // GIR_Coverage, 3237,
     /*  801691 */     GIR_EraseRootFromParent_Done,
     /*  801692 */   // Label 12884: @801692
     /*  801692 */   GIM_Try, /*On fail goto*//*Label 12885*/ GIMT_Encode4(801744), // Rule ID 3238 //
     /*  801697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  801700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f32),
     /*  801705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801728 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2385:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64),
     /*  801731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801738 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801740 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801742 */     GIR_RootConstrainSelectedInstOperands,
     /*  801743 */     // GIR_Coverage, 3238,
     /*  801743 */     GIR_EraseRootFromParent_Done,
     /*  801744 */   // Label 12885: @801744
     /*  801744 */   GIM_Try, /*On fail goto*//*Label 12886*/ GIMT_Encode4(801796), // Rule ID 3239 //
     /*  801749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  801752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f32),
     /*  801757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801766 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801780 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2385:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64),
     /*  801783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801790 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801792 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801794 */     GIR_RootConstrainSelectedInstOperands,
     /*  801795 */     // GIR_Coverage, 3239,
     /*  801795 */     GIR_EraseRootFromParent_Done,
     /*  801796 */   // Label 12886: @801796
     /*  801796 */   GIM_Try, /*On fail goto*//*Label 12887*/ GIMT_Encode4(801848), // Rule ID 3240 //
     /*  801801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  801804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f32),
     /*  801809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801818 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801832 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2385:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64),
     /*  801835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801842 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801844 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801846 */     GIR_RootConstrainSelectedInstOperands,
     /*  801847 */     // GIR_Coverage, 3240,
     /*  801847 */     GIR_EraseRootFromParent_Done,
     /*  801848 */   // Label 12887: @801848
     /*  801848 */   GIM_Try, /*On fail goto*//*Label 12888*/ GIMT_Encode4(801900), // Rule ID 3241 //
     /*  801853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  801856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp8_f32),
     /*  801861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801870 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801884 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2385:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP8_F32_e64),
     /*  801887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801894 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801896 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801898 */     GIR_RootConstrainSelectedInstOperands,
     /*  801899 */     // GIR_Coverage, 3241,
     /*  801899 */     GIR_EraseRootFromParent_Done,
     /*  801900 */   // Label 12888: @801900
     /*  801900 */   GIM_Try, /*On fail goto*//*Label 12889*/ GIMT_Encode4(801952), // Rule ID 3242 //
     /*  801905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  801908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f32),
     /*  801913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801936 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2379:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64),
     /*  801939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  801948 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  801950 */     GIR_RootConstrainSelectedInstOperands,
     /*  801951 */     // GIR_Coverage, 3242,
     /*  801951 */     GIR_EraseRootFromParent_Done,
     /*  801952 */   // Label 12889: @801952
     /*  801952 */   GIM_Try, /*On fail goto*//*Label 12890*/ GIMT_Encode4(802004), // Rule ID 3243 //
     /*  801957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  801960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f32),
     /*  801965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  801968 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  801971 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  801974 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  801977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  801981 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  801988 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2379:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  801988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64),
     /*  801991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  801993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  801998 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802000 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802002 */     GIR_RootConstrainSelectedInstOperands,
     /*  802003 */     // GIR_Coverage, 3243,
     /*  802003 */     GIR_EraseRootFromParent_Done,
     /*  802004 */   // Label 12890: @802004
     /*  802004 */   GIM_Try, /*On fail goto*//*Label 12891*/ GIMT_Encode4(802056), // Rule ID 3244 //
     /*  802009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  802012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f32),
     /*  802017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  802020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802026 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  802033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802040 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2379:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64),
     /*  802043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802050 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802052 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802054 */     GIR_RootConstrainSelectedInstOperands,
     /*  802055 */     // GIR_Coverage, 3244,
     /*  802055 */     GIR_EraseRootFromParent_Done,
     /*  802056 */   // Label 12891: @802056
     /*  802056 */   GIM_Try, /*On fail goto*//*Label 12892*/ GIMT_Encode4(802108), // Rule ID 3245 //
     /*  802061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  802064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f32),
     /*  802069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  802072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802078 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  802085 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802092 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2379:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64),
     /*  802095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802102 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802104 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802106 */     GIR_RootConstrainSelectedInstOperands,
     /*  802107 */     // GIR_Coverage, 3245,
     /*  802107 */     GIR_EraseRootFromParent_Done,
     /*  802108 */   // Label 12892: @802108
     /*  802108 */   GIM_Try, /*On fail goto*//*Label 12893*/ GIMT_Encode4(802160), // Rule ID 3246 //
     /*  802113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  802116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_bf8_f32),
     /*  802121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  802124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802130 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  802137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802144 */     // (intrinsic_wo_chain:{ *:[v2i32] } 2379:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_BF8_F32_e64:{ *:[v2i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_BF8_F32_e64),
     /*  802147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802154 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802156 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802158 */     GIR_RootConstrainSelectedInstOperands,
     /*  802159 */     // GIR_Coverage, 3246,
     /*  802159 */     GIR_EraseRootFromParent_Done,
     /*  802160 */   // Label 12893: @802160
     /*  802160 */   GIM_Try, /*On fail goto*//*Label 12894*/ GIMT_Encode4(802212), // Rule ID 3247 //
     /*  802165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  802168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f32),
     /*  802173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802176 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802179 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802182 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802196 */     // (intrinsic_wo_chain:{ *:[i32] } 2382:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64),
     /*  802199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802206 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802208 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802210 */     GIR_RootConstrainSelectedInstOperands,
     /*  802211 */     // GIR_Coverage, 3247,
     /*  802211 */     GIR_EraseRootFromParent_Done,
     /*  802212 */   // Label 12894: @802212
     /*  802212 */   GIM_Try, /*On fail goto*//*Label 12895*/ GIMT_Encode4(802264), // Rule ID 3248 //
     /*  802217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  802220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f32),
     /*  802225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802231 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802234 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802248 */     // (intrinsic_wo_chain:{ *:[i32] } 2382:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64),
     /*  802251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802258 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802260 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802262 */     GIR_RootConstrainSelectedInstOperands,
     /*  802263 */     // GIR_Coverage, 3248,
     /*  802263 */     GIR_EraseRootFromParent_Done,
     /*  802264 */   // Label 12895: @802264
     /*  802264 */   GIM_Try, /*On fail goto*//*Label 12896*/ GIMT_Encode4(802316), // Rule ID 3249 //
     /*  802269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  802272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f32),
     /*  802277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802286 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802300 */     // (intrinsic_wo_chain:{ *:[i32] } 2382:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64),
     /*  802303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802310 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802312 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802314 */     GIR_RootConstrainSelectedInstOperands,
     /*  802315 */     // GIR_Coverage, 3249,
     /*  802315 */     GIR_EraseRootFromParent_Done,
     /*  802316 */   // Label 12896: @802316
     /*  802316 */   GIM_Try, /*On fail goto*//*Label 12897*/ GIMT_Encode4(802368), // Rule ID 3250 //
     /*  802321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  802324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f32),
     /*  802329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802335 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802338 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802352 */     // (intrinsic_wo_chain:{ *:[i32] } 2382:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64),
     /*  802355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802362 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802364 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802366 */     GIR_RootConstrainSelectedInstOperands,
     /*  802367 */     // GIR_Coverage, 3250,
     /*  802367 */     GIR_EraseRootFromParent_Done,
     /*  802368 */   // Label 12897: @802368
     /*  802368 */   GIM_Try, /*On fail goto*//*Label 12898*/ GIMT_Encode4(802420), // Rule ID 3251 //
     /*  802373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  802376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f32),
     /*  802381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  802387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802390 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802404 */     // (intrinsic_wo_chain:{ *:[i32] } 2382:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F32_e64:{ *:[i32] } v8f32:{ *:[v8f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F32_e64),
     /*  802407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802414 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802416 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802418 */     GIR_RootConstrainSelectedInstOperands,
     /*  802419 */     // GIR_Coverage, 3251,
     /*  802419 */     GIR_EraseRootFromParent_Done,
     /*  802420 */   // Label 12898: @802420
     /*  802420 */   GIM_Try, /*On fail goto*//*Label 12899*/ GIMT_Encode4(802472), // Rule ID 3252 //
     /*  802425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  802428 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f16),
     /*  802433 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  802439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802442 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802456 */     // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64),
     /*  802459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802466 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802468 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802470 */     GIR_RootConstrainSelectedInstOperands,
     /*  802471 */     // GIR_Coverage, 3252,
     /*  802471 */     GIR_EraseRootFromParent_Done,
     /*  802472 */   // Label 12899: @802472
     /*  802472 */   GIM_Try, /*On fail goto*//*Label 12900*/ GIMT_Encode4(802524), // Rule ID 3253 //
     /*  802477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  802480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f16),
     /*  802485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  802491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802494 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802508 */     // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64),
     /*  802511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802518 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802520 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802522 */     GIR_RootConstrainSelectedInstOperands,
     /*  802523 */     // GIR_Coverage, 3253,
     /*  802523 */     GIR_EraseRootFromParent_Done,
     /*  802524 */   // Label 12900: @802524
     /*  802524 */   GIM_Try, /*On fail goto*//*Label 12901*/ GIMT_Encode4(802576), // Rule ID 3254 //
     /*  802529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  802532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f16),
     /*  802537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  802543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802546 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802560 */     // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64),
     /*  802563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802570 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802572 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802574 */     GIR_RootConstrainSelectedInstOperands,
     /*  802575 */     // GIR_Coverage, 3254,
     /*  802575 */     GIR_EraseRootFromParent_Done,
     /*  802576 */   // Label 12901: @802576
     /*  802576 */   GIM_Try, /*On fail goto*//*Label 12902*/ GIMT_Encode4(802628), // Rule ID 3255 //
     /*  802581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  802584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f16),
     /*  802589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  802595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802598 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802612 */     // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64),
     /*  802615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802622 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802624 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802626 */     GIR_RootConstrainSelectedInstOperands,
     /*  802627 */     // GIR_Coverage, 3255,
     /*  802627 */     GIR_EraseRootFromParent_Done,
     /*  802628 */   // Label 12902: @802628
     /*  802628 */   GIM_Try, /*On fail goto*//*Label 12903*/ GIMT_Encode4(802680), // Rule ID 3256 //
     /*  802633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  802636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk8_fp4_f16),
     /*  802641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  802644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  802647 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802650 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  802657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802664 */     // (intrinsic_wo_chain:{ *:[i32] } 2381:{ *:[iPTR] }, (VOP3Mods0:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK8_FP4_F16_e64:{ *:[i32] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK8_FP4_F16_e64),
     /*  802667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802674 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802676 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802678 */     GIR_RootConstrainSelectedInstOperands,
     /*  802679 */     // GIR_Coverage, 3256,
     /*  802679 */     GIR_EraseRootFromParent_Done,
     /*  802680 */   // Label 12903: @802680
     /*  802680 */   GIM_Try, /*On fail goto*//*Label 12904*/ GIMT_Encode4(802732), // Rule ID 3257 //
     /*  802685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  802688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f16),
     /*  802693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  802696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  802699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802702 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  802709 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802716 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2366:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64),
     /*  802719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802726 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802728 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802730 */     GIR_RootConstrainSelectedInstOperands,
     /*  802731 */     // GIR_Coverage, 3257,
     /*  802731 */     GIR_EraseRootFromParent_Done,
     /*  802732 */   // Label 12904: @802732
     /*  802732 */   GIM_Try, /*On fail goto*//*Label 12905*/ GIMT_Encode4(802784), // Rule ID 3258 //
     /*  802737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  802740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f16),
     /*  802745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  802748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  802751 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802754 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  802761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802768 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2366:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64),
     /*  802771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802778 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802780 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802782 */     GIR_RootConstrainSelectedInstOperands,
     /*  802783 */     // GIR_Coverage, 3258,
     /*  802783 */     GIR_EraseRootFromParent_Done,
     /*  802784 */   // Label 12905: @802784
     /*  802784 */   GIM_Try, /*On fail goto*//*Label 12906*/ GIMT_Encode4(802836), // Rule ID 3259 //
     /*  802789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  802792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f16),
     /*  802797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  802800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  802803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802806 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  802813 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802820 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2366:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64),
     /*  802823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802830 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802832 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802834 */     GIR_RootConstrainSelectedInstOperands,
     /*  802835 */     // GIR_Coverage, 3259,
     /*  802835 */     GIR_EraseRootFromParent_Done,
     /*  802836 */   // Label 12906: @802836
     /*  802836 */   GIM_Try, /*On fail goto*//*Label 12907*/ GIMT_Encode4(802888), // Rule ID 3260 //
     /*  802841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  802844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f16),
     /*  802849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  802852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  802855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802858 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  802865 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802872 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2366:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64),
     /*  802875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802882 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802884 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802886 */     GIR_RootConstrainSelectedInstOperands,
     /*  802887 */     // GIR_Coverage, 3260,
     /*  802887 */     GIR_EraseRootFromParent_Done,
     /*  802888 */   // Label 12907: @802888
     /*  802888 */   GIM_Try, /*On fail goto*//*Label 12908*/ GIMT_Encode4(802940), // Rule ID 3261 //
     /*  802893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  802896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f16),
     /*  802901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  802904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  802907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802910 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  802917 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802924 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2366:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F16_e64),
     /*  802927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802934 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802936 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802938 */     GIR_RootConstrainSelectedInstOperands,
     /*  802939 */     // GIR_Coverage, 3261,
     /*  802939 */     GIR_EraseRootFromParent_Done,
     /*  802940 */   // Label 12908: @802940
     /*  802940 */   GIM_Try, /*On fail goto*//*Label 12909*/ GIMT_Encode4(802992), // Rule ID 3262 //
     /*  802945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  802948 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f32),
     /*  802953 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  802956 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  802959 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  802962 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  802965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  802969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  802976 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2367:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  802976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64),
     /*  802979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  802981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  802986 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  802988 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  802990 */     GIR_RootConstrainSelectedInstOperands,
     /*  802991 */     // GIR_Coverage, 3262,
     /*  802991 */     GIR_EraseRootFromParent_Done,
     /*  802992 */   // Label 12909: @802992
     /*  802992 */   GIM_Try, /*On fail goto*//*Label 12910*/ GIMT_Encode4(803044), // Rule ID 3263 //
     /*  802997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  803000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f32),
     /*  803005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803014 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803028 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2367:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64),
     /*  803031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803038 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803040 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803042 */     GIR_RootConstrainSelectedInstOperands,
     /*  803043 */     // GIR_Coverage, 3263,
     /*  803043 */     GIR_EraseRootFromParent_Done,
     /*  803044 */   // Label 12910: @803044
     /*  803044 */   GIM_Try, /*On fail goto*//*Label 12911*/ GIMT_Encode4(803096), // Rule ID 3264 //
     /*  803049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  803052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f32),
     /*  803057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803066 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803080 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2367:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64),
     /*  803083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803090 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803092 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803094 */     GIR_RootConstrainSelectedInstOperands,
     /*  803095 */     // GIR_Coverage, 3264,
     /*  803095 */     GIR_EraseRootFromParent_Done,
     /*  803096 */   // Label 12911: @803096
     /*  803096 */   GIM_Try, /*On fail goto*//*Label 12912*/ GIMT_Encode4(803148), // Rule ID 3265 //
     /*  803101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  803104 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f32),
     /*  803109 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803118 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803132 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2367:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64),
     /*  803135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803142 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803144 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803146 */     GIR_RootConstrainSelectedInstOperands,
     /*  803147 */     // GIR_Coverage, 3265,
     /*  803147 */     GIR_EraseRootFromParent_Done,
     /*  803148 */   // Label 12912: @803148
     /*  803148 */   GIM_Try, /*On fail goto*//*Label 12913*/ GIMT_Encode4(803200), // Rule ID 3266 //
     /*  803153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  803156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_bf6_f32),
     /*  803161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803170 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803184 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2367:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_BF6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_BF6_F32_e64),
     /*  803187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803194 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803196 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803198 */     GIR_RootConstrainSelectedInstOperands,
     /*  803199 */     // GIR_Coverage, 3266,
     /*  803199 */     GIR_EraseRootFromParent_Done,
     /*  803200 */   // Label 12913: @803200
     /*  803200 */   GIM_Try, /*On fail goto*//*Label 12914*/ GIMT_Encode4(803252), // Rule ID 3267 //
     /*  803205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  803208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f16),
     /*  803213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803216 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  803219 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803222 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803236 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2369:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64),
     /*  803239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803246 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803248 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803250 */     GIR_RootConstrainSelectedInstOperands,
     /*  803251 */     // GIR_Coverage, 3267,
     /*  803251 */     GIR_EraseRootFromParent_Done,
     /*  803252 */   // Label 12914: @803252
     /*  803252 */   GIM_Try, /*On fail goto*//*Label 12915*/ GIMT_Encode4(803304), // Rule ID 3268 //
     /*  803257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  803260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f16),
     /*  803265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  803271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803274 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803288 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2369:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64),
     /*  803291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803298 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803300 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803302 */     GIR_RootConstrainSelectedInstOperands,
     /*  803303 */     // GIR_Coverage, 3268,
     /*  803303 */     GIR_EraseRootFromParent_Done,
     /*  803304 */   // Label 12915: @803304
     /*  803304 */   GIM_Try, /*On fail goto*//*Label 12916*/ GIMT_Encode4(803356), // Rule ID 3269 //
     /*  803309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  803312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f16),
     /*  803317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  803323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803326 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803340 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2369:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64),
     /*  803343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803350 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803352 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803354 */     GIR_RootConstrainSelectedInstOperands,
     /*  803355 */     // GIR_Coverage, 3269,
     /*  803355 */     GIR_EraseRootFromParent_Done,
     /*  803356 */   // Label 12916: @803356
     /*  803356 */   GIM_Try, /*On fail goto*//*Label 12917*/ GIMT_Encode4(803408), // Rule ID 3270 //
     /*  803361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  803364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f16),
     /*  803369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  803375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803378 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803392 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2369:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64),
     /*  803395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803402 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803404 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803406 */     GIR_RootConstrainSelectedInstOperands,
     /*  803407 */     // GIR_Coverage, 3270,
     /*  803407 */     GIR_EraseRootFromParent_Done,
     /*  803408 */   // Label 12917: @803408
     /*  803408 */   GIM_Try, /*On fail goto*//*Label 12918*/ GIMT_Encode4(803460), // Rule ID 3271 //
     /*  803413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  803416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f16),
     /*  803421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  803427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803430 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803437 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803444 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2369:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F16_e64:{ *:[v3i32] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F16_e64),
     /*  803447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803454 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803456 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803458 */     GIR_RootConstrainSelectedInstOperands,
     /*  803459 */     // GIR_Coverage, 3271,
     /*  803459 */     GIR_EraseRootFromParent_Done,
     /*  803460 */   // Label 12918: @803460
     /*  803460 */   GIM_Try, /*On fail goto*//*Label 12919*/ GIMT_Encode4(803512), // Rule ID 3272 //
     /*  803465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  803468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f32),
     /*  803473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803482 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803496 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2370:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64),
     /*  803499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803506 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803508 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803510 */     GIR_RootConstrainSelectedInstOperands,
     /*  803511 */     // GIR_Coverage, 3272,
     /*  803511 */     GIR_EraseRootFromParent_Done,
     /*  803512 */   // Label 12919: @803512
     /*  803512 */   GIM_Try, /*On fail goto*//*Label 12920*/ GIMT_Encode4(803564), // Rule ID 3273 //
     /*  803517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  803520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f32),
     /*  803525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803528 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803531 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803534 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803541 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803548 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2370:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64),
     /*  803551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803558 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803560 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803562 */     GIR_RootConstrainSelectedInstOperands,
     /*  803563 */     // GIR_Coverage, 3273,
     /*  803563 */     GIR_EraseRootFromParent_Done,
     /*  803564 */   // Label 12920: @803564
     /*  803564 */   GIM_Try, /*On fail goto*//*Label 12921*/ GIMT_Encode4(803616), // Rule ID 3274 //
     /*  803569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  803572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f32),
     /*  803577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803586 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803593 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803600 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2370:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64),
     /*  803603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803610 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803612 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803614 */     GIR_RootConstrainSelectedInstOperands,
     /*  803615 */     // GIR_Coverage, 3274,
     /*  803615 */     GIR_EraseRootFromParent_Done,
     /*  803616 */   // Label 12921: @803616
     /*  803616 */   GIM_Try, /*On fail goto*//*Label 12922*/ GIMT_Encode4(803668), // Rule ID 3275 //
     /*  803621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  803624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f32),
     /*  803629 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803632 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803635 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803638 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803645 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803652 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2370:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64),
     /*  803655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803662 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803664 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803666 */     GIR_RootConstrainSelectedInstOperands,
     /*  803667 */     // GIR_Coverage, 3275,
     /*  803667 */     GIR_EraseRootFromParent_Done,
     /*  803668 */   // Label 12922: @803668
     /*  803668 */   GIM_Try, /*On fail goto*//*Label 12923*/ GIMT_Encode4(803720), // Rule ID 3276 //
     /*  803673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  803676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk16_fp6_f32),
     /*  803681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  803687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803690 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  803693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  803697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803704 */     // (intrinsic_wo_chain:{ *:[v3i32] } 2370:{ *:[iPTR] }, (VOP3Mods0:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src0), i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_CVT_SCALEF32_SR_PK16_FP6_F32_e64:{ *:[v3i32] } v16f32:{ *:[v16f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)
     /*  803704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK16_FP6_F32_e64),
     /*  803707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803714 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803716 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803718 */     GIR_RootConstrainSelectedInstOperands,
     /*  803719 */     // GIR_Coverage, 3276,
     /*  803719 */     GIR_EraseRootFromParent_Done,
     /*  803720 */   // Label 12923: @803720
     /*  803720 */   GIM_Try, /*On fail goto*//*Label 12924*/ GIMT_Encode4(803772), // Rule ID 3277 //
     /*  803725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode0),
     /*  803728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b4_u4),
     /*  803733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  803736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  803739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803742 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  803745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  803749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803756 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3338:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B4_U4_e64:{ *:[v2i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  803756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B4_U4_e64),
     /*  803759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803766 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803768 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803770 */     GIR_RootConstrainSelectedInstOperands,
     /*  803771 */     // GIR_Coverage, 3277,
     /*  803771 */     GIR_EraseRootFromParent_Done,
     /*  803772 */   // Label 12924: @803772
     /*  803772 */   GIM_Try, /*On fail goto*//*Label 12925*/ GIMT_Encode4(803824), // Rule ID 3278 //
     /*  803777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode1),
     /*  803780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b4_u4),
     /*  803785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  803788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  803791 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803794 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  803797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  803801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803808 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3338:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B4_U4_e64:{ *:[v2i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  803808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B4_U4_e64),
     /*  803811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803818 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803820 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803822 */     GIR_RootConstrainSelectedInstOperands,
     /*  803823 */     // GIR_Coverage, 3278,
     /*  803823 */     GIR_EraseRootFromParent_Done,
     /*  803824 */   // Label 12925: @803824
     /*  803824 */   GIM_Try, /*On fail goto*//*Label 12926*/ GIMT_Encode4(803876), // Rule ID 3279 //
     /*  803829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode2),
     /*  803832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b4_u4),
     /*  803837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  803840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  803843 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803846 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  803849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  803853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803860 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3338:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B4_U4_e64:{ *:[v2i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  803860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B4_U4_e64),
     /*  803863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803870 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803872 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803874 */     GIR_RootConstrainSelectedInstOperands,
     /*  803875 */     // GIR_Coverage, 3279,
     /*  803875 */     GIR_EraseRootFromParent_Done,
     /*  803876 */   // Label 12926: @803876
     /*  803876 */   GIM_Try, /*On fail goto*//*Label 12927*/ GIMT_Encode4(803928), // Rule ID 3280 //
     /*  803881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode3),
     /*  803884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b4_u4),
     /*  803889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  803892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  803895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803898 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  803901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  803905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803912 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3338:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B4_U4_e64:{ *:[v2i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  803912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B4_U4_e64),
     /*  803915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803922 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803924 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803926 */     GIR_RootConstrainSelectedInstOperands,
     /*  803927 */     // GIR_Coverage, 3280,
     /*  803927 */     GIR_EraseRootFromParent_Done,
     /*  803928 */   // Label 12927: @803928
     /*  803928 */   GIM_Try, /*On fail goto*//*Label 12928*/ GIMT_Encode4(803980), // Rule ID 3281 //
     /*  803933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode4),
     /*  803936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b4_u4),
     /*  803941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  803944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  803947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  803950 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  803953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  803957 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  803964 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3338:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B4_U4_e64:{ *:[v2i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  803964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B4_U4_e64),
     /*  803967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  803969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  803974 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  803976 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  803978 */     GIR_RootConstrainSelectedInstOperands,
     /*  803979 */     // GIR_Coverage, 3281,
     /*  803979 */     GIR_EraseRootFromParent_Done,
     /*  803980 */   // Label 12928: @803980
     /*  803980 */   GIM_Try, /*On fail goto*//*Label 12929*/ GIMT_Encode4(804032), // Rule ID 3282 //
     /*  803985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode0),
     /*  803988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b6_u4),
     /*  803993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  803996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  803999 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804002 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  804009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804016 */     // (intrinsic_wo_chain:{ *:[v3i32] } 3339:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B6_U4_e64:{ *:[v3i32] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B6_U4_e64),
     /*  804019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804026 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804028 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804030 */     GIR_RootConstrainSelectedInstOperands,
     /*  804031 */     // GIR_Coverage, 3282,
     /*  804031 */     GIR_EraseRootFromParent_Done,
     /*  804032 */   // Label 12929: @804032
     /*  804032 */   GIM_Try, /*On fail goto*//*Label 12930*/ GIMT_Encode4(804084), // Rule ID 3283 //
     /*  804037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode1),
     /*  804040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b6_u4),
     /*  804045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  804048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804054 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  804061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804068 */     // (intrinsic_wo_chain:{ *:[v3i32] } 3339:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B6_U4_e64:{ *:[v3i32] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B6_U4_e64),
     /*  804071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804078 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804080 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804082 */     GIR_RootConstrainSelectedInstOperands,
     /*  804083 */     // GIR_Coverage, 3283,
     /*  804083 */     GIR_EraseRootFromParent_Done,
     /*  804084 */   // Label 12930: @804084
     /*  804084 */   GIM_Try, /*On fail goto*//*Label 12931*/ GIMT_Encode4(804136), // Rule ID 3284 //
     /*  804089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode2),
     /*  804092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b6_u4),
     /*  804097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  804100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804103 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804106 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  804113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804120 */     // (intrinsic_wo_chain:{ *:[v3i32] } 3339:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B6_U4_e64:{ *:[v3i32] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B6_U4_e64),
     /*  804123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804130 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804132 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804134 */     GIR_RootConstrainSelectedInstOperands,
     /*  804135 */     // GIR_Coverage, 3284,
     /*  804135 */     GIR_EraseRootFromParent_Done,
     /*  804136 */   // Label 12931: @804136
     /*  804136 */   GIM_Try, /*On fail goto*//*Label 12932*/ GIMT_Encode4(804188), // Rule ID 3285 //
     /*  804141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode3),
     /*  804144 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b6_u4),
     /*  804149 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  804152 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804155 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804158 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  804165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804172 */     // (intrinsic_wo_chain:{ *:[v3i32] } 3339:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B6_U4_e64:{ *:[v3i32] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B6_U4_e64),
     /*  804175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804182 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804184 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804186 */     GIR_RootConstrainSelectedInstOperands,
     /*  804187 */     // GIR_Coverage, 3285,
     /*  804187 */     GIR_EraseRootFromParent_Done,
     /*  804188 */   // Label 12932: @804188
     /*  804188 */   GIM_Try, /*On fail goto*//*Label 12933*/ GIMT_Encode4(804240), // Rule ID 3286 //
     /*  804193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode4),
     /*  804196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b6_u4),
     /*  804201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  804204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804207 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804210 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  804217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804224 */     // (intrinsic_wo_chain:{ *:[v3i32] } 3339:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B6_U4_e64:{ *:[v3i32] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B6_U4_e64),
     /*  804227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804234 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804236 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804238 */     GIR_RootConstrainSelectedInstOperands,
     /*  804239 */     // GIR_Coverage, 3286,
     /*  804239 */     GIR_EraseRootFromParent_Done,
     /*  804240 */   // Label 12933: @804240
     /*  804240 */   GIM_Try, /*On fail goto*//*Label 12934*/ GIMT_Encode4(804292), // Rule ID 3287 //
     /*  804245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode0),
     /*  804248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b8_u4),
     /*  804253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  804256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  804259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804262 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  804269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804276 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3340:{ *:[iPTR] }, (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B8_U4_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B8_U4_e64),
     /*  804279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804286 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804288 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804290 */     GIR_RootConstrainSelectedInstOperands,
     /*  804291 */     // GIR_Coverage, 3287,
     /*  804291 */     GIR_EraseRootFromParent_Done,
     /*  804292 */   // Label 12934: @804292
     /*  804292 */   GIM_Try, /*On fail goto*//*Label 12935*/ GIMT_Encode4(804344), // Rule ID 3288 //
     /*  804297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode1),
     /*  804300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b8_u4),
     /*  804305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  804308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  804311 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804314 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  804321 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804328 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3340:{ *:[iPTR] }, (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B8_U4_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B8_U4_e64),
     /*  804331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804338 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804340 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804342 */     GIR_RootConstrainSelectedInstOperands,
     /*  804343 */     // GIR_Coverage, 3288,
     /*  804343 */     GIR_EraseRootFromParent_Done,
     /*  804344 */   // Label 12935: @804344
     /*  804344 */   GIM_Try, /*On fail goto*//*Label 12936*/ GIMT_Encode4(804396), // Rule ID 3289 //
     /*  804349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode2),
     /*  804352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b8_u4),
     /*  804357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  804360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  804363 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804366 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  804373 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804380 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3340:{ *:[iPTR] }, (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B8_U4_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B8_U4_e64),
     /*  804383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804390 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804392 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804394 */     GIR_RootConstrainSelectedInstOperands,
     /*  804395 */     // GIR_Coverage, 3289,
     /*  804395 */     GIR_EraseRootFromParent_Done,
     /*  804396 */   // Label 12936: @804396
     /*  804396 */   GIM_Try, /*On fail goto*//*Label 12937*/ GIMT_Encode4(804448), // Rule ID 3290 //
     /*  804401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode3),
     /*  804404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b8_u4),
     /*  804409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  804412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  804415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804418 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  804425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804432 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3340:{ *:[iPTR] }, (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B8_U4_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B8_U4_e64),
     /*  804435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804442 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804444 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804446 */     GIR_RootConstrainSelectedInstOperands,
     /*  804447 */     // GIR_Coverage, 3290,
     /*  804447 */     GIR_EraseRootFromParent_Done,
     /*  804448 */   // Label 12937: @804448
     /*  804448 */   GIM_Try, /*On fail goto*//*Label 12938*/ GIMT_Encode4(804500), // Rule ID 3291 //
     /*  804453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTensorCvtLutInsts_HwMode4),
     /*  804456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm_pk16_b8_u4),
     /*  804461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  804464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  804467 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  804470 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /*  804473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  804477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  804484 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3340:{ *:[iPTR] }, (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)  =>  (V_PERM_PK16_B8_U4_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v2i32:{ *:[v2i32] }:$src2)
     /*  804484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_PK16_B8_U4_e64),
     /*  804487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804494 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804496 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804498 */     GIR_RootConstrainSelectedInstOperands,
     /*  804499 */     // GIR_Coverage, 3291,
     /*  804499 */     GIR_EraseRootFromParent_Done,
     /*  804500 */   // Label 12938: @804500
     /*  804500 */   GIM_Reject,
     /*  804501 */ // Label 12756: @804501
     /*  804501 */ GIM_Try, /*On fail goto*//*Label 12939*/ GIMT_Encode4(812090),
     /*  804506 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /*  804509 */   GIM_Try, /*On fail goto*//*Label 12940*/ GIMT_Encode4(804562), // Rule ID 7155 //
     /*  804514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot5Insts),
     /*  804517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2),
     /*  804522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  804528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  804531 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804538 */     // MIs[0] Operand 5
     /*  804538 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  804549 */     // (intrinsic_wo_chain:{ *:[f32] } 2444:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, v2f16:{ *:[v2f16] }:$src1, f32:{ *:[f32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT2C_F32_F16_e32:{ *:[f32] } ?:{ *:[v2f16] }:$src0, ?:{ *:[v2f16] }:$src1, ?:{ *:[f32] }:$src2)
     /*  804549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2C_F32_F16_e32),
     /*  804552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804554 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  804556 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804558 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804560 */     GIR_RootConstrainSelectedInstOperands,
     /*  804561 */     // GIR_Coverage, 7155,
     /*  804561 */     GIR_EraseRootFromParent_Done,
     /*  804562 */   // Label 12940: @804562
     /*  804562 */   GIM_Try, /*On fail goto*//*Label 12941*/ GIMT_Encode4(804615), // Rule ID 7157 //
     /*  804567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot6Insts),
     /*  804570 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4),
     /*  804575 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804578 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804581 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  804584 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804591 */     // MIs[0] Operand 5
     /*  804591 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  804602 */     // (intrinsic_wo_chain:{ *:[i32] } 3484:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT4C_I32_I8_e32:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2)
     /*  804602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4C_I32_I8_e32),
     /*  804605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804607 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  804609 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804611 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804613 */     GIR_RootConstrainSelectedInstOperands,
     /*  804614 */     // GIR_Coverage, 7157,
     /*  804614 */     GIR_EraseRootFromParent_Done,
     /*  804615 */   // Label 12941: @804615
     /*  804615 */   GIM_Try, /*On fail goto*//*Label 12942*/ GIMT_Encode4(804668), // Rule ID 7158 //
     /*  804620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot4Insts),
     /*  804623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot2),
     /*  804628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  804634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  804637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804644 */     // MIs[0] Operand 5
     /*  804644 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  804655 */     // (intrinsic_wo_chain:{ *:[i32] } 3483:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT2C_I32_I16_e32:{ *:[i32] } ?:{ *:[v2i16] }:$src0, ?:{ *:[v2i16] }:$src1, ?:{ *:[i32] }:$src2)
     /*  804655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2C_I32_I16_e32),
     /*  804658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804660 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  804662 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804664 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804666 */     GIR_RootConstrainSelectedInstOperands,
     /*  804667 */     // GIR_Coverage, 7158,
     /*  804667 */     GIR_EraseRootFromParent_Done,
     /*  804668 */   // Label 12942: @804668
     /*  804668 */   GIM_Try, /*On fail goto*//*Label 12943*/ GIMT_Encode4(804721), // Rule ID 7159 //
     /*  804673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot3Insts),
     /*  804676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8),
     /*  804681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  804690 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804697 */     // MIs[0] Operand 5
     /*  804697 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  804708 */     // (intrinsic_wo_chain:{ *:[i32] } 3485:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT8C_I32_I4_e32:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2)
     /*  804708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8C_I32_I4_e32),
     /*  804711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804713 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  804715 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  804717 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  804719 */     GIR_RootConstrainSelectedInstOperands,
     /*  804720 */     // GIR_Coverage, 7159,
     /*  804720 */     GIR_EraseRootFromParent_Done,
     /*  804721 */   // Label 12943: @804721
     /*  804721 */   GIM_Try, /*On fail goto*//*Label 12944*/ GIMT_Encode4(804828), // Rule ID 27297 //
     /*  804726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  804729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16),
     /*  804734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  804743 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804750 */     // MIs[0] Operand 5
     /*  804750 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  804761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804768 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804782 */     // (intrinsic_wo_chain:{ *:[f32] } 3254:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P10_F16_F32_inreg_fake16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  804782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16),
     /*  804785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  804792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  804802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  804807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  804812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  804817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  804820 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  804823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  804826 */     GIR_RootConstrainSelectedInstOperands,
     /*  804827 */     // GIR_Coverage, 27297,
     /*  804827 */     GIR_EraseRootFromParent_Done,
     /*  804828 */   // Label 12944: @804828
     /*  804828 */   GIM_Try, /*On fail goto*//*Label 12945*/ GIMT_Encode4(804935), // Rule ID 27298 //
     /*  804833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  804836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16),
     /*  804841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  804850 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804857 */     // MIs[0] Operand 5
     /*  804857 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  804868 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi),
     /*  804875 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods_hi),
     /*  804889 */     // (intrinsic_wo_chain:{ *:[f32] } 3254:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P10_F16_F32_inreg_fake16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  804889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16),
     /*  804892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  804894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  804899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  804904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  804909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  804914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  804919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  804924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  804927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  804930 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  804933 */     GIR_RootConstrainSelectedInstOperands,
     /*  804934 */     // GIR_Coverage, 27298,
     /*  804934 */     GIR_EraseRootFromParent_Done,
     /*  804935 */   // Label 12945: @804935
     /*  804935 */   GIM_Try, /*On fail goto*//*Label 12946*/ GIMT_Encode4(805096), // Rule ID 27299 //
     /*  804940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  804943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16),
     /*  804948 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  804951 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  804954 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  804957 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  804960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  804964 */     // MIs[0] Operand 5
     /*  804964 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  804975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  804996 */     // (intrinsic_wo_chain:{ *:[f32] } 3254:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P10_F16_F32_inreg_t16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, lo16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src2, lo16:{ *:[i32] }), 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  804996 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  804999 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805003 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805008 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src2
     /*  805015 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805020 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805025 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805028 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805032 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805037 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src0
     /*  805044 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805049 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg_t16),
     /*  805057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805064 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805082 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  805085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805094 */     GIR_RootConstrainSelectedInstOperands,
     /*  805095 */     // GIR_Coverage, 27299,
     /*  805095 */     GIR_EraseRootFromParent_Done,
     /*  805096 */   // Label 12946: @805096
     /*  805096 */   GIM_Try, /*On fail goto*//*Label 12947*/ GIMT_Encode4(805257), // Rule ID 27300 //
     /*  805101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805104 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16),
     /*  805109 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  805112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  805115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  805118 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  805121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805125 */     // MIs[0] Operand 5
     /*  805125 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  805136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805150 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805157 */     // (intrinsic_wo_chain:{ *:[f32] } 3254:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P10_F16_F32_inreg_t16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, hi16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src2, hi16:{ *:[i32] }), 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  805157 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  805160 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805164 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805169 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src2
     /*  805176 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805181 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805186 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805189 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805193 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805198 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src0
     /*  805205 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805210 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg_t16),
     /*  805218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805225 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805228 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805243 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  805246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805249 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805255 */     GIR_RootConstrainSelectedInstOperands,
     /*  805256 */     // GIR_Coverage, 27300,
     /*  805256 */     GIR_EraseRootFromParent_Done,
     /*  805257 */   // Label 12947: @805257
     /*  805257 */   GIM_Try, /*On fail goto*//*Label 12948*/ GIMT_Encode4(805391), // Rule ID 27303 //
     /*  805262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16),
     /*  805270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  805273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  805276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  805279 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  805282 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805286 */     // MIs[0] Operand 5
     /*  805286 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  805297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805304 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805318 */     // (intrinsic_wo_chain:{ *:[f16] } 3256:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P2_F16_F32_inreg_t16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, lo16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, VGPR_32:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  805318 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805321 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805325 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805330 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src0
     /*  805337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805342 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg_t16),
     /*  805350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805357 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  805380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805389 */     GIR_RootConstrainSelectedInstOperands,
     /*  805390 */     // GIR_Coverage, 27303,
     /*  805390 */     GIR_EraseRootFromParent_Done,
     /*  805391 */   // Label 12948: @805391
     /*  805391 */   GIM_Try, /*On fail goto*//*Label 12949*/ GIMT_Encode4(805525), // Rule ID 27304 //
     /*  805396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805399 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16),
     /*  805404 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  805407 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  805410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  805413 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  805416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805420 */     // MIs[0] Operand 5
     /*  805420 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  805431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805452 */     // (intrinsic_wo_chain:{ *:[f16] } 3256:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P2_F16_F32_inreg_t16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, hi16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, VGPR_32:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  805452 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805455 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805459 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805464 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src0
     /*  805471 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805476 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg_t16),
     /*  805484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805491 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  805514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805523 */     GIR_RootConstrainSelectedInstOperands,
     /*  805524 */     // GIR_Coverage, 27304,
     /*  805524 */     GIR_EraseRootFromParent_Done,
     /*  805525 */   // Label 12949: @805525
     /*  805525 */   GIM_Try, /*On fail goto*//*Label 12950*/ GIMT_Encode4(805686), // Rule ID 27305 //
     /*  805530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p10_rtz_f16),
     /*  805538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  805541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  805544 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  805547 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  805550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805554 */     // MIs[0] Operand 5
     /*  805554 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  805565 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805586 */     // (intrinsic_wo_chain:{ *:[f32] } 3260:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P10_RTZ_F16_F32_inreg_t16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, lo16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src2, lo16:{ *:[i32] }), 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  805586 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  805589 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805593 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805598 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src2
     /*  805605 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805610 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805615 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805618 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805622 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805627 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src0
     /*  805634 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805639 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16),
     /*  805647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805654 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805672 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  805675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805684 */     GIR_RootConstrainSelectedInstOperands,
     /*  805685 */     // GIR_Coverage, 27305,
     /*  805685 */     GIR_EraseRootFromParent_Done,
     /*  805686 */   // Label 12950: @805686
     /*  805686 */   GIM_Try, /*On fail goto*//*Label 12951*/ GIMT_Encode4(805847), // Rule ID 27306 //
     /*  805691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805694 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p10_rtz_f16),
     /*  805699 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  805702 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  805705 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  805708 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  805711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805715 */     // MIs[0] Operand 5
     /*  805715 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  805726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805747 */     // (intrinsic_wo_chain:{ *:[f32] } 3260:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P10_RTZ_F16_F32_inreg_t16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, hi16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src2, hi16:{ *:[i32] }), 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  805747 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  805750 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805754 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805759 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src2
     /*  805766 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805771 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805776 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805779 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805783 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805788 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src0
     /*  805795 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805800 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16),
     /*  805808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805815 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805833 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  805836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805839 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805845 */     GIR_RootConstrainSelectedInstOperands,
     /*  805846 */     // GIR_Coverage, 27306,
     /*  805846 */     GIR_EraseRootFromParent_Done,
     /*  805847 */   // Label 12951: @805847
     /*  805847 */   GIM_Try, /*On fail goto*//*Label 12952*/ GIMT_Encode4(805981), // Rule ID 27307 //
     /*  805852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_rtz_f16),
     /*  805860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  805863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  805866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  805869 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  805872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805876 */     // MIs[0] Operand 5
     /*  805876 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  805887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805894 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  805908 */     // (intrinsic_wo_chain:{ *:[f16] } 3263:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P2_RTZ_F16_F32_inreg_t16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, lo16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, VGPR_32:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  805908 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  805911 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  805915 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  805920 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(2), // src0
     /*  805927 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  805932 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  805937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16),
     /*  805940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  805942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  805947 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  805950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  805955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  805960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  805965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  805970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  805976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  805979 */     GIR_RootConstrainSelectedInstOperands,
     /*  805980 */     // GIR_Coverage, 27307,
     /*  805980 */     GIR_EraseRootFromParent_Done,
     /*  805981 */   // Label 12952: @805981
     /*  805981 */   GIM_Try, /*On fail goto*//*Label 12953*/ GIMT_Encode4(806115), // Rule ID 27308 //
     /*  805986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  805989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_rtz_f16),
     /*  805994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  805997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806003 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  806010 */     // MIs[0] Operand 5
     /*  806010 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  806021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806042 */     // (intrinsic_wo_chain:{ *:[f16] } 3263:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P2_RTZ_F16_F32_inreg_t16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, (EXTRACT_SUBREG:{ *:[f16] } VGPR_32:{ *:[f32] }:$src0, hi16:{ *:[i32] }), ?:{ *:[i32] }:$src1_modifiers, VGPR_32:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, VGPR_32:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806042 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  806045 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  806049 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  806054 */     GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src0
     /*  806061 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  806066 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16),
     /*  806074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806081 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  806084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806113 */     GIR_RootConstrainSelectedInstOperands,
     /*  806114 */     // GIR_Coverage, 27308,
     /*  806114 */     GIR_EraseRootFromParent_Done,
     /*  806115 */   // Label 12953: @806115
     /*  806115 */   GIM_Try, /*On fail goto*//*Label 12954*/ GIMT_Encode4(806222), // Rule ID 27309 //
     /*  806120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  806123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16),
     /*  806128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  806131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806144 */     // MIs[0] Operand 5
     /*  806144 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  806155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806162 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806176 */     // (intrinsic_wo_chain:{ *:[f16] } 3256:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P2_F16_F32_inreg_fake16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16),
     /*  806179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806220 */     GIR_RootConstrainSelectedInstOperands,
     /*  806221 */     // GIR_Coverage, 27309,
     /*  806221 */     GIR_EraseRootFromParent_Done,
     /*  806222 */   // Label 12954: @806222
     /*  806222 */   GIM_Try, /*On fail goto*//*Label 12955*/ GIMT_Encode4(806329), // Rule ID 27310 //
     /*  806227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  806230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16),
     /*  806235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  806238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806244 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806251 */     // MIs[0] Operand 5
     /*  806251 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  806262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi),
     /*  806269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806283 */     // (intrinsic_wo_chain:{ *:[f16] } 3256:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P2_F16_F32_inreg_fake16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16),
     /*  806286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806324 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806327 */     GIR_RootConstrainSelectedInstOperands,
     /*  806328 */     // GIR_Coverage, 27310,
     /*  806328 */     GIR_EraseRootFromParent_Done,
     /*  806329 */   // Label 12955: @806329
     /*  806329 */   GIM_Try, /*On fail goto*//*Label 12956*/ GIMT_Encode4(806436), // Rule ID 27311 //
     /*  806334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  806337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p10_rtz_f16),
     /*  806342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  806345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806351 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806358 */     // MIs[0] Operand 5
     /*  806358 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  806369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806376 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806383 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806390 */     // (intrinsic_wo_chain:{ *:[f32] } 3260:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P10_RTZ_F16_F32_inreg_fake16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16),
     /*  806393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806428 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806434 */     GIR_RootConstrainSelectedInstOperands,
     /*  806435 */     // GIR_Coverage, 27311,
     /*  806435 */     GIR_EraseRootFromParent_Done,
     /*  806436 */   // Label 12956: @806436
     /*  806436 */   GIM_Try, /*On fail goto*//*Label 12957*/ GIMT_Encode4(806543), // Rule ID 27312 //
     /*  806441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  806444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p10_rtz_f16),
     /*  806449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  806452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806455 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806458 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806465 */     // MIs[0] Operand 5
     /*  806465 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  806476 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi),
     /*  806483 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods_hi),
     /*  806497 */     // (intrinsic_wo_chain:{ *:[f32] } 3260:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P10_RTZ_F16_F32_inreg_fake16:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16),
     /*  806500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806541 */     GIR_RootConstrainSelectedInstOperands,
     /*  806542 */     // GIR_Coverage, 27312,
     /*  806542 */     GIR_EraseRootFromParent_Done,
     /*  806543 */   // Label 12957: @806543
     /*  806543 */   GIM_Try, /*On fail goto*//*Label 12958*/ GIMT_Encode4(806650), // Rule ID 27313 //
     /*  806548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  806551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_rtz_f16),
     /*  806556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  806559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806565 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806572 */     // MIs[0] Operand 5
     /*  806572 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  806583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806590 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806604 */     // (intrinsic_wo_chain:{ *:[f16] } 3263:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P2_RTZ_F16_F32_inreg_fake16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16),
     /*  806607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806648 */     GIR_RootConstrainSelectedInstOperands,
     /*  806649 */     // GIR_Coverage, 27313,
     /*  806649 */     GIR_EraseRootFromParent_Done,
     /*  806650 */   // Label 12958: @806650
     /*  806650 */   GIM_Try, /*On fail goto*//*Label 12959*/ GIMT_Encode4(806757), // Rule ID 27314 //
     /*  806655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  806658 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_rtz_f16),
     /*  806663 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  806666 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806669 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806672 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806679 */     // MIs[0] Operand 5
     /*  806679 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  806690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi),
     /*  806697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806704 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
     /*  806711 */     // (intrinsic_wo_chain:{ *:[f16] } 3263:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P2_RTZ_F16_F32_inreg_fake16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i32] })
     /*  806711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16),
     /*  806714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /*  806755 */     GIR_RootConstrainSelectedInstOperands,
     /*  806756 */     // GIR_Coverage, 27314,
     /*  806756 */     GIR_EraseRootFromParent_Done,
     /*  806757 */   // Label 12959: @806757
     /*  806757 */   GIM_Try, /*On fail goto*//*Label 12960*/ GIMT_Encode4(806871), // Rule ID 7486 //
     /*  806762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*  806765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  806770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  806773 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  806776 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  806779 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  806782 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  806785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  806789 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXEC_XNULLRegClassID),
     /*  806793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  806800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  806807 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  806814 */     // (intrinsic_wo_chain:{ *:[f32] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2)
     /*  806814 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  806818 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  806824 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
     /*  806828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F32_e64),
     /*  806831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806848 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806869 */     GIR_RootConstrainSelectedInstOperands,
     /*  806870 */     // GIR_Coverage, 7486,
     /*  806870 */     GIR_EraseRootFromParent_Done,
     /*  806871 */   // Label 12960: @806871
     /*  806871 */   GIM_Try, /*On fail goto*//*Label 12961*/ GIMT_Encode4(806985), // Rule ID 7488 //
     /*  806876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64_HwMode0),
     /*  806879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  806884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  806887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  806890 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  806893 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  806896 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  806899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  806903 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXEC_XNULLRegClassID),
     /*  806907 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  806914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  806921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  806928 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  806928 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  806932 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  806938 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
     /*  806942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  806945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  806947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  806952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  806957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  806962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  806967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  806972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  806977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  806983 */     GIR_RootConstrainSelectedInstOperands,
     /*  806984 */     // GIR_Coverage, 7488,
     /*  806984 */     GIR_EraseRootFromParent_Done,
     /*  806985 */   // Label 12961: @806985
     /*  806985 */   GIM_Try, /*On fail goto*//*Label 12962*/ GIMT_Encode4(807099), // Rule ID 7489 //
     /*  806990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64_HwMode1),
     /*  806993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  806998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807007 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807010 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807017 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXEC_XNULLRegClassID),
     /*  807021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807042 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807042 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807046 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807052 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
     /*  807056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807097 */     GIR_RootConstrainSelectedInstOperands,
     /*  807098 */     // GIR_Coverage, 7489,
     /*  807098 */     GIR_EraseRootFromParent_Done,
     /*  807099 */   // Label 12962: @807099
     /*  807099 */   GIM_Try, /*On fail goto*//*Label 12963*/ GIMT_Encode4(807213), // Rule ID 7490 //
     /*  807104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64_HwMode2),
     /*  807107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807121 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807124 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807131 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXEC_XNULLRegClassID),
     /*  807135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807149 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807156 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807156 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807160 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807166 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
     /*  807170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807211 */     GIR_RootConstrainSelectedInstOperands,
     /*  807212 */     // GIR_Coverage, 7490,
     /*  807212 */     GIR_EraseRootFromParent_Done,
     /*  807213 */   // Label 12963: @807213
     /*  807213 */   GIM_Try, /*On fail goto*//*Label 12964*/ GIMT_Encode4(807327), // Rule ID 7491 //
     /*  807218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64_HwMode3),
     /*  807221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807235 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807238 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807245 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXEC_XNULLRegClassID),
     /*  807249 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807270 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807270 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807274 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807280 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
     /*  807284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807325 */     GIR_RootConstrainSelectedInstOperands,
     /*  807326 */     // GIR_Coverage, 7491,
     /*  807326 */     GIR_EraseRootFromParent_Done,
     /*  807327 */   // Label 12964: @807327
     /*  807327 */   GIM_Try, /*On fail goto*//*Label 12965*/ GIMT_Encode4(807441), // Rule ID 7492 //
     /*  807332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64_HwMode4),
     /*  807335 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807340 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807343 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807346 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807349 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807352 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807359 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXEC_XNULLRegClassID),
     /*  807363 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807384 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807384 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807388 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807394 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
     /*  807398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807439 */     GIR_RootConstrainSelectedInstOperands,
     /*  807440 */     // GIR_Coverage, 7492,
     /*  807440 */     GIR_EraseRootFromParent_Done,
     /*  807441 */   // Label 12965: @807441
     /*  807441 */   GIM_Try, /*On fail goto*//*Label 12966*/ GIMT_Encode4(807555), // Rule ID 7498 //
     /*  807446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*  807449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  807457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  807460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  807463 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  807466 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  807473 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  807477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807484 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807491 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807498 */     // (intrinsic_wo_chain:{ *:[f32] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2)
     /*  807498 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807502 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807508 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
     /*  807512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F32_e64),
     /*  807515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807527 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807553 */     GIR_RootConstrainSelectedInstOperands,
     /*  807554 */     // GIR_Coverage, 7498,
     /*  807554 */     GIR_EraseRootFromParent_Done,
     /*  807555 */   // Label 12966: @807555
     /*  807555 */   GIM_Try, /*On fail goto*//*Label 12967*/ GIMT_Encode4(807669), // Rule ID 7500 //
     /*  807560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32_HwMode0),
     /*  807563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807580 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807587 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  807591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807612 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807612 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807616 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807622 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
     /*  807626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807667 */     GIR_RootConstrainSelectedInstOperands,
     /*  807668 */     // GIR_Coverage, 7500,
     /*  807668 */     GIR_EraseRootFromParent_Done,
     /*  807669 */   // Label 12967: @807669
     /*  807669 */   GIM_Try, /*On fail goto*//*Label 12968*/ GIMT_Encode4(807783), // Rule ID 7501 //
     /*  807674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32_HwMode1),
     /*  807677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807691 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807694 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807701 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  807705 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807712 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807726 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807726 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807730 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807736 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
     /*  807740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807781 */     GIR_RootConstrainSelectedInstOperands,
     /*  807782 */     // GIR_Coverage, 7501,
     /*  807782 */     GIR_EraseRootFromParent_Done,
     /*  807783 */   // Label 12968: @807783
     /*  807783 */   GIM_Try, /*On fail goto*//*Label 12969*/ GIMT_Encode4(807897), // Rule ID 7502 //
     /*  807788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32_HwMode2),
     /*  807791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807805 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807808 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807815 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  807819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807840 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807840 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807844 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807850 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
     /*  807854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807884 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  807889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  807895 */     GIR_RootConstrainSelectedInstOperands,
     /*  807896 */     // GIR_Coverage, 7502,
     /*  807896 */     GIR_EraseRootFromParent_Done,
     /*  807897 */   // Label 12969: @807897
     /*  807897 */   GIM_Try, /*On fail goto*//*Label 12970*/ GIMT_Encode4(808011), // Rule ID 7503 //
     /*  807902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32_HwMode3),
     /*  807905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  807910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  807913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  807916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  807919 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  807922 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  807925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  807929 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  807933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  807954 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  807954 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  807958 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  807964 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
     /*  807968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  807971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  807973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  807978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  807983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  807988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  807993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  807998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  808003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808009 */     GIR_RootConstrainSelectedInstOperands,
     /*  808010 */     // GIR_Coverage, 7503,
     /*  808010 */     GIR_EraseRootFromParent_Done,
     /*  808011 */   // Label 12970: @808011
     /*  808011 */   GIM_Try, /*On fail goto*//*Label 12971*/ GIMT_Encode4(808125), // Rule ID 7504 //
     /*  808016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32_HwMode4),
     /*  808019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
     /*  808024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  808027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  808030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  808033 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  808036 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1,
     /*  808039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  808043 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  808047 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808054 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808068 */     // (intrinsic_wo_chain:{ *:[f64] } 2399:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
     /*  808068 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  808072 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  808078 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
     /*  808082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
     /*  808085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  808112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  808117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808123 */     GIR_RootConstrainSelectedInstOperands,
     /*  808124 */     // GIR_Coverage, 7504,
     /*  808124 */     GIR_EraseRootFromParent_Done,
     /*  808125 */   // Label 12971: @808125
     /*  808125 */   GIM_Try, /*On fail goto*//*Label 12972*/ GIMT_Encode4(808206), // Rule ID 7263 //
     /*  808130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_NotHasFP8E5M3Insts_isGFX12Plus),
     /*  808133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
     /*  808138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808147 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808154 */     // MIs[0] byte_sel
     /*  808154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808171 */     // (intrinsic_wo_chain:{ *:[i32] } 2391:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_FP8_F32_gfx12_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64),
     /*  808174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808196 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808198 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808204 */     GIR_RootConstrainSelectedInstOperands,
     /*  808205 */     // GIR_Coverage, 7263,
     /*  808205 */     GIR_EraseRootFromParent_Done,
     /*  808206 */   // Label 12972: @808206
     /*  808206 */   GIM_Try, /*On fail goto*//*Label 12973*/ GIMT_Encode4(808290), // Rule ID 7264 //
     /*  808211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_isGFX12Plus),
     /*  808214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
     /*  808219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808228 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808235 */     // MIs[0] byte_sel
     /*  808235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808252 */     // (intrinsic_wo_chain:{ *:[i32] } 2391:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_FP8_F32_gfx1250_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, 0:{ *:[i1] }, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64),
     /*  808255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808280 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808282 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808288 */     GIR_RootConstrainSelectedInstOperands,
     /*  808289 */     // GIR_Coverage, 7264,
     /*  808289 */     GIR_EraseRootFromParent_Done,
     /*  808290 */   // Label 12973: @808290
     /*  808290 */   GIM_Try, /*On fail goto*//*Label 12974*/ GIMT_Encode4(808374), // Rule ID 7265 //
     /*  808295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_isGFX12Plus),
     /*  808298 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32_e5m3),
     /*  808303 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808306 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808309 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808312 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808319 */     // MIs[0] byte_sel
     /*  808319 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808336 */     // (intrinsic_wo_chain:{ *:[i32] } 2392:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_FP8_F32_gfx1250_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, 1:{ *:[i1] }, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64),
     /*  808339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  808364 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808366 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808372 */     GIR_RootConstrainSelectedInstOperands,
     /*  808373 */     // GIR_Coverage, 7265,
     /*  808373 */     GIR_EraseRootFromParent_Done,
     /*  808374 */   // Label 12974: @808374
     /*  808374 */   GIM_Try, /*On fail goto*//*Label 12975*/ GIMT_Encode4(808455), // Rule ID 7266 //
     /*  808379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus),
     /*  808382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
     /*  808387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808396 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808403 */     // MIs[0] byte_sel
     /*  808403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808420 */     // (intrinsic_wo_chain:{ *:[i32] } 2388:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_BF8_F32_gfx12_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64),
     /*  808423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808445 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808447 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808453 */     GIR_RootConstrainSelectedInstOperands,
     /*  808454 */     // GIR_Coverage, 7266,
     /*  808454 */     GIR_EraseRootFromParent_Done,
     /*  808455 */   // Label 12975: @808455
     /*  808455 */   GIM_Try, /*On fail goto*//*Label 12976*/ GIMT_Encode4(808539), // Rule ID 7516 //
     /*  808460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  808463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f16),
     /*  808468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  808474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808484 */     // MIs[0] byte_sel
     /*  808484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808487 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808501 */     // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_FP8_F16_t16_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F16_t16_e64),
     /*  808504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808526 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808528 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808537 */     GIR_RootConstrainSelectedInstOperands,
     /*  808538 */     // GIR_Coverage, 7516,
     /*  808538 */     GIR_EraseRootFromParent_Done,
     /*  808539 */   // Label 12976: @808539
     /*  808539 */   GIM_Try, /*On fail goto*//*Label 12977*/ GIMT_Encode4(808623), // Rule ID 7517 //
     /*  808544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX1250Plus),
     /*  808547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f16),
     /*  808552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  808558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808568 */     // MIs[0] byte_sel
     /*  808568 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808578 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808585 */     // (intrinsic_wo_chain:{ *:[i32] } 2387:{ *:[iPTR] }, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_BF8_F16_t16_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F16_t16_e64),
     /*  808588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808610 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808612 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808621 */     GIR_RootConstrainSelectedInstOperands,
     /*  808622 */     // GIR_Coverage, 7517,
     /*  808622 */     GIR_EraseRootFromParent_Done,
     /*  808623 */   // Label 12977: @808623
     /*  808623 */   GIM_Try, /*On fail goto*//*Label 12978*/ GIMT_Encode4(808707), // Rule ID 7518 //
     /*  808628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  808631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f16),
     /*  808636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  808642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808645 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808652 */     // MIs[0] byte_sel
     /*  808652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808662 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808669 */     // (intrinsic_wo_chain:{ *:[i32] } 2390:{ *:[iPTR] }, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_FP8_F16_fake16_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F16_fake16_e64),
     /*  808672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808694 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808696 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808705 */     GIR_RootConstrainSelectedInstOperands,
     /*  808706 */     // GIR_Coverage, 7518,
     /*  808706 */     GIR_EraseRootFromParent_Done,
     /*  808707 */   // Label 12978: @808707
     /*  808707 */   GIM_Try, /*On fail goto*//*Label 12979*/ GIMT_Encode4(808791), // Rule ID 7519 //
     /*  808712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts_isGFX1250Plus),
     /*  808715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f16),
     /*  808720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  808726 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  808729 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  808732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808736 */     // MIs[0] byte_sel
     /*  808736 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  808739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  808753 */     // (intrinsic_wo_chain:{ *:[i32] } 2387:{ *:[iPTR] }, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel)  =>  (V_CVT_SR_BF8_F16_fake16_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$byte_sel))
     /*  808753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F16_fake16_e64),
     /*  808756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  808763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  808768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  808773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  808778 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  808780 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel
     /*  808786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  808789 */     GIR_RootConstrainSelectedInstOperands,
     /*  808790 */     // GIR_Coverage, 7519,
     /*  808790 */     GIR_EraseRootFromParent_Done,
     /*  808791 */   // Label 12979: @808791
     /*  808791 */   GIM_Try, /*On fail goto*//*Label 12980*/ GIMT_Encode4(808854), // Rule ID 4163 //
     /*  808796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX90APlus),
     /*  808799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_mov),
     /*  808804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808807 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  808810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808814 */     // MIs[0] vsrc
     /*  808814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  808817 */     // MIs[0] attrchan
     /*  808817 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  808820 */     // MIs[0] attr
     /*  808820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  808823 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  808827 */     // (intrinsic_wo_chain:{ *:[f32] } 3257:{ *:[iPTR] }, (timm:{ *:[i32] }):$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_MOV_F32:{ *:[f32] } (timm:{ *:[i32] }):$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
     /*  808827 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  808831 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  808837 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  808841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_MOV_F32),
     /*  808844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808846 */     GIR_RootToRootCopy, /*OpIdx*/2, // vsrc
     /*  808848 */     GIR_RootToRootCopy, /*OpIdx*/4, // attr
     /*  808850 */     GIR_RootToRootCopy, /*OpIdx*/3, // attrchan
     /*  808852 */     GIR_RootConstrainSelectedInstOperands,
     /*  808853 */     // GIR_Coverage, 4163,
     /*  808853 */     GIR_EraseRootFromParent_Done,
     /*  808854 */   // Label 12980: @808854
     /*  808854 */   GIM_Try, /*On fail goto*//*Label 12981*/ GIMT_Encode4(808917), // Rule ID 4160 //
     /*  808859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_has32BankLDS_isNotGFX90APlus),
     /*  808862 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1),
     /*  808867 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808870 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808873 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  808876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808880 */     // MIs[0] attrchan
     /*  808880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  808883 */     // MIs[0] attr
     /*  808883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  808886 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  808890 */     // (intrinsic_wo_chain:{ *:[f32] } 3258:{ *:[iPTR] }, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_P1_F32:{ *:[f32] } f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
     /*  808890 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  808894 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  808900 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  808904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1_F32),
     /*  808907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808909 */     GIR_RootToRootCopy, /*OpIdx*/2, // vsrc
     /*  808911 */     GIR_RootToRootCopy, /*OpIdx*/4, // attr
     /*  808913 */     GIR_RootToRootCopy, /*OpIdx*/3, // attrchan
     /*  808915 */     GIR_RootConstrainSelectedInstOperands,
     /*  808916 */     // GIR_Coverage, 4160,
     /*  808916 */     GIR_EraseRootFromParent_Done,
     /*  808917 */   // Label 12981: @808917
     /*  808917 */   GIM_Try, /*On fail goto*//*Label 12982*/ GIMT_Encode4(808980), // Rule ID 4161 //
     /*  808922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_has16BankLDS_isNotGFX90APlus),
     /*  808925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1),
     /*  808930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808936 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  808939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  808943 */     // MIs[0] attrchan
     /*  808943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  808946 */     // MIs[0] attr
     /*  808946 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  808949 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  808953 */     // (intrinsic_wo_chain:{ *:[f32] } 3258:{ *:[iPTR] }, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_P1_F32_16bank:{ *:[f32] } f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
     /*  808953 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  808957 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  808963 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  808967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1_F32_16bank),
     /*  808970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  808972 */     GIR_RootToRootCopy, /*OpIdx*/2, // vsrc
     /*  808974 */     GIR_RootToRootCopy, /*OpIdx*/4, // attr
     /*  808976 */     GIR_RootToRootCopy, /*OpIdx*/3, // attrchan
     /*  808978 */     GIR_RootConstrainSelectedInstOperands,
     /*  808979 */     // GIR_Coverage, 4161,
     /*  808979 */     GIR_EraseRootFromParent_Done,
     /*  808980 */   // Label 12982: @808980
     /*  808980 */   GIM_Try, /*On fail goto*//*Label 12983*/ GIMT_Encode4(809042), // Rule ID 7239 //
     /*  808985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_NotHasFP8E5M3Insts_NotHasTrue16BitInsts_isGFX9Plus),
     /*  808988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
     /*  808993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  808996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  808999 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809002 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809009 */     // MIs[0] Operand 5
     /*  809009 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809020 */     // (intrinsic_wo_chain:{ *:[i32] } 2284:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_e64),
     /*  809023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809028 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809033 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809035 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809040 */     GIR_RootConstrainSelectedInstOperands,
     /*  809041 */     // GIR_Coverage, 7239,
     /*  809041 */     GIR_EraseRootFromParent_Done,
     /*  809042 */   // Label 12983: @809042
     /*  809042 */   GIM_Try, /*On fail goto*//*Label 12984*/ GIMT_Encode4(809104), // Rule ID 7240 //
     /*  809047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_NotHasTrue16BitInsts_isGFX9Plus),
     /*  809050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32),
     /*  809055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809058 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809061 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809064 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809071 */     // MIs[0] Operand 5
     /*  809071 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809082 */     // (intrinsic_wo_chain:{ *:[i32] } 2278:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_e64),
     /*  809085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809090 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809097 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809102 */     GIR_RootConstrainSelectedInstOperands,
     /*  809103 */     // GIR_Coverage, 7240,
     /*  809103 */     GIR_EraseRootFromParent_Done,
     /*  809104 */   // Label 12984: @809104
     /*  809104 */   GIM_Try, /*On fail goto*//*Label 12985*/ GIMT_Encode4(809166), // Rule ID 7241 //
     /*  809109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
     /*  809117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809126 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809133 */     // MIs[0] Operand 5
     /*  809133 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809144 */     // (intrinsic_wo_chain:{ *:[i32] } 2284:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_fake16_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_fake16_e64),
     /*  809147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809152 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809157 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809159 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809164 */     GIR_RootConstrainSelectedInstOperands,
     /*  809165 */     // GIR_Coverage, 7241,
     /*  809165 */     GIR_EraseRootFromParent_Done,
     /*  809166 */   // Label 12985: @809166
     /*  809166 */   GIM_Try, /*On fail goto*//*Label 12986*/ GIMT_Encode4(809228), // Rule ID 7242 //
     /*  809171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809174 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32),
     /*  809179 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809182 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809185 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809188 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809195 */     // MIs[0] Operand 5
     /*  809195 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809206 */     // (intrinsic_wo_chain:{ *:[i32] } 2278:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_BF8_F32_fake16_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_fake16_e64),
     /*  809209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809214 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809216 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809219 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809221 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809226 */     GIR_RootConstrainSelectedInstOperands,
     /*  809227 */     // GIR_Coverage, 7242,
     /*  809227 */     GIR_EraseRootFromParent_Done,
     /*  809228 */   // Label 12986: @809228
     /*  809228 */   GIM_Try, /*On fail goto*//*Label 12987*/ GIMT_Encode4(809293), // Rule ID 7243 //
     /*  809233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
     /*  809241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809250 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809257 */     // MIs[0] Operand 5
     /*  809257 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809268 */     // (intrinsic_wo_chain:{ *:[i32] } 2284:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_gfx1250_fake16_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i1] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64),
     /*  809271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809276 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809281 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809283 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809286 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809288 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809291 */     GIR_RootConstrainSelectedInstOperands,
     /*  809292 */     // GIR_Coverage, 7243,
     /*  809292 */     GIR_EraseRootFromParent_Done,
     /*  809293 */   // Label 12987: @809293
     /*  809293 */   GIM_Try, /*On fail goto*//*Label 12988*/ GIMT_Encode4(809358), // Rule ID 7244 //
     /*  809298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32_e5m3),
     /*  809306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809312 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809315 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809322 */     // MIs[0] Operand 5
     /*  809322 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809333 */     // (intrinsic_wo_chain:{ *:[i32] } 2285:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_gfx1250_fake16_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 1:{ *:[i1] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64),
     /*  809336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809341 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809346 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  809351 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809356 */     GIR_RootConstrainSelectedInstOperands,
     /*  809357 */     // GIR_Coverage, 7244,
     /*  809357 */     GIR_EraseRootFromParent_Done,
     /*  809358 */   // Label 12988: @809358
     /*  809358 */   GIM_Try, /*On fail goto*//*Label 12989*/ GIMT_Encode4(809420), // Rule ID 7245 //
     /*  809363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_NotHasFP8E5M3Insts_NotHasTrue16BitInsts_isGFX9Plus),
     /*  809366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
     /*  809371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809380 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809387 */     // MIs[0] Operand 5
     /*  809387 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  809398 */     // (intrinsic_wo_chain:{ *:[i32] } 2284:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_e64),
     /*  809401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  809406 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809411 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809413 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809418 */     GIR_RootConstrainSelectedInstOperands,
     /*  809419 */     // GIR_Coverage, 7245,
     /*  809419 */     GIR_EraseRootFromParent_Done,
     /*  809420 */   // Label 12989: @809420
     /*  809420 */   GIM_Try, /*On fail goto*//*Label 12990*/ GIMT_Encode4(809482), // Rule ID 7246 //
     /*  809425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_NotHasTrue16BitInsts_isGFX9Plus),
     /*  809428 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32),
     /*  809433 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809442 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809449 */     // MIs[0] Operand 5
     /*  809449 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  809460 */     // (intrinsic_wo_chain:{ *:[i32] } 2278:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_e64),
     /*  809463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  809468 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809473 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809475 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809480 */     GIR_RootConstrainSelectedInstOperands,
     /*  809481 */     // GIR_Coverage, 7246,
     /*  809481 */     GIR_EraseRootFromParent_Done,
     /*  809482 */   // Label 12990: @809482
     /*  809482 */   GIM_Try, /*On fail goto*//*Label 12991*/ GIMT_Encode4(809544), // Rule ID 7247 //
     /*  809487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
     /*  809495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809504 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809511 */     // MIs[0] Operand 5
     /*  809511 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  809522 */     // (intrinsic_wo_chain:{ *:[i32] } 2284:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_fake16_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_fake16_e64),
     /*  809525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  809530 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809535 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809537 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809542 */     GIR_RootConstrainSelectedInstOperands,
     /*  809543 */     // GIR_Coverage, 7247,
     /*  809543 */     GIR_EraseRootFromParent_Done,
     /*  809544 */   // Label 12991: @809544
     /*  809544 */   GIM_Try, /*On fail goto*//*Label 12992*/ GIMT_Encode4(809606), // Rule ID 7248 //
     /*  809549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32),
     /*  809557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809566 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809573 */     // MIs[0] Operand 5
     /*  809573 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  809584 */     // (intrinsic_wo_chain:{ *:[i32] } 2278:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_BF8_F32_fake16_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_fake16_e64),
     /*  809587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  809592 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809597 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809599 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809604 */     GIR_RootConstrainSelectedInstOperands,
     /*  809605 */     // GIR_Coverage, 7248,
     /*  809605 */     GIR_EraseRootFromParent_Done,
     /*  809606 */   // Label 12992: @809606
     /*  809606 */   GIM_Try, /*On fail goto*//*Label 12993*/ GIMT_Encode4(809671), // Rule ID 7249 //
     /*  809611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
     /*  809619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809628 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809635 */     // MIs[0] Operand 5
     /*  809635 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  809646 */     // (intrinsic_wo_chain:{ *:[i32] } 2284:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_gfx1250_fake16_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i1] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64),
     /*  809649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  809654 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809659 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809664 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809669 */     GIR_RootConstrainSelectedInstOperands,
     /*  809670 */     // GIR_Coverage, 7249,
     /*  809670 */     GIR_EraseRootFromParent_Done,
     /*  809671 */   // Label 12993: @809671
     /*  809671 */   GIM_Try, /*On fail goto*//*Label 12994*/ GIMT_Encode4(809736), // Rule ID 7250 //
     /*  809676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_HasFP8E5M3Insts_UseFakeTrue16Insts_isGFX9Plus),
     /*  809679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32_e5m3),
     /*  809684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809693 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809700 */     // MIs[0] Operand 5
     /*  809700 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  809711 */     // (intrinsic_wo_chain:{ *:[i32] } 2285:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_gfx1250_fake16_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 1:{ *:[i1] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_gfx1250_fake16_e64),
     /*  809714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  809719 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809724 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  809729 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809734 */     GIR_RootConstrainSelectedInstOperands,
     /*  809735 */     // GIR_Coverage, 7250,
     /*  809735 */     GIR_EraseRootFromParent_Done,
     /*  809736 */   // Label 12994: @809736
     /*  809736 */   GIM_Try, /*On fail goto*//*Label 12995*/ GIMT_Encode4(809801), // Rule ID 7255 //
     /*  809741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  809744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
     /*  809749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809755 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809758 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809765 */     // MIs[0] Operand 5
     /*  809765 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809776 */     // (intrinsic_wo_chain:{ *:[i32] } 2391:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
     /*  809779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809784 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809789 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809794 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809799 */     GIR_RootConstrainSelectedInstOperands,
     /*  809800 */     // GIR_Coverage, 7255,
     /*  809800 */     GIR_EraseRootFromParent_Done,
     /*  809801 */   // Label 12995: @809801
     /*  809801 */   GIM_Try, /*On fail goto*//*Label 12996*/ GIMT_Encode4(809866), // Rule ID 7256 //
     /*  809806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  809809 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
     /*  809814 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809817 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809820 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809823 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809830 */     // MIs[0] Operand 5
     /*  809830 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  809841 */     // (intrinsic_wo_chain:{ *:[i32] } 2388:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
     /*  809844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809849 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809854 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809859 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809864 */     GIR_RootConstrainSelectedInstOperands,
     /*  809865 */     // GIR_Coverage, 7256,
     /*  809865 */     GIR_EraseRootFromParent_Done,
     /*  809866 */   // Label 12996: @809866
     /*  809866 */   GIM_Try, /*On fail goto*//*Label 12997*/ GIMT_Encode4(809931), // Rule ID 7257 //
     /*  809871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  809874 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
     /*  809879 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809882 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809885 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809888 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809895 */     // MIs[0] Operand 5
     /*  809895 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(1),
     /*  809906 */     // (intrinsic_wo_chain:{ *:[i32] } 2391:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 1:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
     /*  809909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809914 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809919 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  809924 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809929 */     GIR_RootConstrainSelectedInstOperands,
     /*  809930 */     // GIR_Coverage, 7257,
     /*  809930 */     GIR_EraseRootFromParent_Done,
     /*  809931 */   // Label 12997: @809931
     /*  809931 */   GIM_Try, /*On fail goto*//*Label 12998*/ GIMT_Encode4(809996), // Rule ID 7258 //
     /*  809936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  809939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
     /*  809944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  809947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  809950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  809953 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  809956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  809960 */     // MIs[0] Operand 5
     /*  809960 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(1),
     /*  809971 */     // (intrinsic_wo_chain:{ *:[i32] } 2388:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 1:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  809971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
     /*  809974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  809976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809979 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  809981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809984 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  809986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  809989 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  809991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  809994 */     GIR_RootConstrainSelectedInstOperands,
     /*  809995 */     // GIR_Coverage, 7258,
     /*  809995 */     GIR_EraseRootFromParent_Done,
     /*  809996 */   // Label 12998: @809996
     /*  809996 */   GIM_Try, /*On fail goto*//*Label 12999*/ GIMT_Encode4(810061), // Rule ID 7259 //
     /*  810001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  810004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
     /*  810009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810018 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810025 */     // MIs[0] Operand 5
     /*  810025 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(2),
     /*  810036 */     // (intrinsic_wo_chain:{ *:[i32] } 2391:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 2:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  810036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
     /*  810039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  810044 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810049 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810051 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810054 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  810056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810059 */     GIR_RootConstrainSelectedInstOperands,
     /*  810060 */     // GIR_Coverage, 7259,
     /*  810060 */     GIR_EraseRootFromParent_Done,
     /*  810061 */   // Label 12999: @810061
     /*  810061 */   GIM_Try, /*On fail goto*//*Label 13000*/ GIMT_Encode4(810126), // Rule ID 7260 //
     /*  810066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  810069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
     /*  810074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810083 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810090 */     // MIs[0] Operand 5
     /*  810090 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(2),
     /*  810101 */     // (intrinsic_wo_chain:{ *:[i32] } 2388:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 2:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  810101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
     /*  810104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  810109 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810114 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810119 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  810121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810124 */     GIR_RootConstrainSelectedInstOperands,
     /*  810125 */     // GIR_Coverage, 7260,
     /*  810125 */     GIR_EraseRootFromParent_Done,
     /*  810126 */   // Label 13000: @810126
     /*  810126 */   GIM_Try, /*On fail goto*//*Label 13001*/ GIMT_Encode4(810191), // Rule ID 7261 //
     /*  810131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  810134 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
     /*  810139 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810142 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810145 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810148 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810155 */     // MIs[0] Operand 5
     /*  810155 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(3),
     /*  810166 */     // (intrinsic_wo_chain:{ *:[i32] } 2391:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 3:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  810166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
     /*  810169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  810174 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810179 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  810184 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  810186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810189 */     GIR_RootConstrainSelectedInstOperands,
     /*  810190 */     // GIR_Coverage, 7261,
     /*  810190 */     GIR_EraseRootFromParent_Done,
     /*  810191 */   // Label 13001: @810191
     /*  810191 */   GIM_Try, /*On fail goto*//*Label 13002*/ GIMT_Encode4(810256), // Rule ID 7262 //
     /*  810196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus),
     /*  810199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
     /*  810204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810220 */     // MIs[0] Operand 5
     /*  810220 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(3),
     /*  810231 */     // (intrinsic_wo_chain:{ *:[i32] } 2388:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 3:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
     /*  810231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
     /*  810234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  810239 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810244 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
     /*  810249 */     GIR_RootToRootCopy, /*OpIdx*/4, // old
     /*  810251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810254 */     GIR_RootConstrainSelectedInstOperands,
     /*  810255 */     // GIR_Coverage, 7262,
     /*  810255 */     GIR_EraseRootFromParent_Done,
     /*  810256 */   // Label 13002: @810256
     /*  810256 */   GIM_Try, /*On fail goto*//*Label 13003*/ GIMT_Encode4(810310), // Rule ID 7426 //
     /*  810261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_fp8_f16),
     /*  810266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  810269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  810272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  810275 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810282 */     // MIs[0] word_sel
     /*  810282 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810285 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2329:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_FP8_F16_e64:{ *:[v2i16] } (DstSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[v2f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, VGPR_32:{ *:[v2i16] }:$vdst_in)
     /*  810285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_FP8_F16_e64),
     /*  810288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810290 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSelXForm), // word_sel
     /*  810296 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  810298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810301 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  810303 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  810305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810308 */     GIR_RootConstrainSelectedInstOperands,
     /*  810309 */     // GIR_Coverage, 7426,
     /*  810309 */     GIR_EraseRootFromParent_Done,
     /*  810310 */   // Label 13003: @810310
     /*  810310 */   GIM_Try, /*On fail goto*//*Label 13004*/ GIMT_Encode4(810364), // Rule ID 7427 //
     /*  810315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_bf8_f16),
     /*  810320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  810323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  810326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  810329 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810336 */     // MIs[0] word_sel
     /*  810336 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810339 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2317:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_BF8_F16_e64:{ *:[v2i16] } (DstSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[v2f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, VGPR_32:{ *:[v2i16] }:$vdst_in)
     /*  810339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_BF8_F16_e64),
     /*  810342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810344 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSelXForm), // word_sel
     /*  810350 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  810352 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810355 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  810357 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  810359 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810362 */     GIR_RootConstrainSelectedInstOperands,
     /*  810363 */     // GIR_Coverage, 7427,
     /*  810363 */     GIR_EraseRootFromParent_Done,
     /*  810364 */   // Label 13004: @810364
     /*  810364 */   GIM_Try, /*On fail goto*//*Label 13005*/ GIMT_Encode4(810424), // Rule ID 7434 //
     /*  810369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_fp4_f16),
     /*  810374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  810383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810390 */     // MIs[0] index
     /*  810390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810393 */     // (intrinsic_wo_chain:{ *:[i32] } 2326:{ *:[iPTR] }, i32:{ *:[i32] }:$src2, v2f16:{ *:[v2f16] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_FP4_F16_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[i32] }:$src2)
     /*  810393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_FP4_F16_e64),
     /*  810396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810398 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  810404 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  810406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810409 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  810411 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  810417 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*  810419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810422 */     GIR_RootConstrainSelectedInstOperands,
     /*  810423 */     // GIR_Coverage, 7434,
     /*  810423 */     GIR_EraseRootFromParent_Done,
     /*  810424 */   // Label 13005: @810424
     /*  810424 */   GIM_Try, /*On fail goto*//*Label 13006*/ GIMT_Encode4(810481), // Rule ID 7520 //
     /*  810429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF32ToF16BF16ConversionSRInsts),
     /*  810432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_f16_f32),
     /*  810437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  810440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  810443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810453 */     // MIs[0] word_sel
     /*  810453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810456 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2389:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SR_F16_F32_e64:{ *:[v2f16] } (DstSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  810456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_F16_F32_e64),
     /*  810459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810461 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSelXForm), // word_sel
     /*  810467 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  810469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810472 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  810474 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  810476 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810479 */     GIR_RootConstrainSelectedInstOperands,
     /*  810480 */     // GIR_Coverage, 7520,
     /*  810480 */     GIR_EraseRootFromParent_Done,
     /*  810481 */   // Label 13006: @810481
     /*  810481 */   GIM_Try, /*On fail goto*//*Label 13007*/ GIMT_Encode4(810543), // Rule ID 7598 //
     /*  810486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
     /*  810489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8),
     /*  810494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810500 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810503 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810510 */     // MIs[0] clamp
     /*  810510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810513 */     // (intrinsic_wo_chain:{ *:[i32] } 3485:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_I32_IU4:{ *:[i32] } 9:{ *:[i32] }, i32:{ *:[i32] }:$src0, 9:{ *:[i32] }, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  810513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_IU4),
     /*  810516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /*  810521 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /*  810526 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810528 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  810531 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  810533 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  810535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810541 */     GIR_RootConstrainSelectedInstOperands,
     /*  810542 */     // GIR_Coverage, 7598,
     /*  810542 */     GIR_EraseRootFromParent_Done,
     /*  810543 */   // Label 13007: @810543
     /*  810543 */   GIM_Try, /*On fail goto*//*Label 13008*/ GIMT_Encode4(810605), // Rule ID 7599 //
     /*  810548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
     /*  810551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4),
     /*  810556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810565 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810572 */     // MIs[0] clamp
     /*  810572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810575 */     // (intrinsic_wo_chain:{ *:[i32] } 3484:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_I32_IU8:{ *:[i32] } 9:{ *:[i32] }, i32:{ *:[i32] }:$src0, 9:{ *:[i32] }, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  810575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_IU8),
     /*  810578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /*  810583 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /*  810588 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810590 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  810593 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  810595 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  810597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810603 */     GIR_RootConstrainSelectedInstOperands,
     /*  810604 */     // GIR_Coverage, 7599,
     /*  810604 */     GIR_EraseRootFromParent_Done,
     /*  810605 */   // Label 13008: @810605
     /*  810605 */   GIM_Try, /*On fail goto*//*Label 13009*/ GIMT_Encode4(810649), // Rule ID 7478 //
     /*  810610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBitOp3Insts),
     /*  810613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_bitop3),
     /*  810618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  810621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  810624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  810627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  810630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810634 */     // MIs[0] bitop3
     /*  810634 */     // No operand predicates
     /*  810634 */     // (intrinsic_wo_chain:{ *:[i32] } 2235:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$bitop3)  =>  (V_BITOP3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2, (timm:{ *:[i32] }):$bitop3)
     /*  810634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BITOP3_B32_e64),
     /*  810637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810639 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810641 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810643 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  810645 */     GIR_RootToRootCopy, /*OpIdx*/5, // bitop3
     /*  810647 */     GIR_RootConstrainSelectedInstOperands,
     /*  810648 */     // GIR_Coverage, 7478,
     /*  810648 */     GIR_EraseRootFromParent_Done,
     /*  810649 */   // Label 13009: @810649
     /*  810649 */   GIM_Try, /*On fail goto*//*Label 13010*/ GIMT_Encode4(810705), // Rule ID 7480 //
     /*  810654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBitOp3Insts_isGFX940Plus),
     /*  810657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_bitop3),
     /*  810662 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  810665 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  810668 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  810671 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  810674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810678 */     // MIs[0] bitop3
     /*  810678 */     // No operand predicates
     /*  810678 */     // (intrinsic_wo_chain:{ *:[i16] } 2235:{ *:[iPTR] }, i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$bitop3)  =>  (V_BITOP3_B16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, (timm:{ *:[i32] }):$bitop3, 0:{ *:[i32] })
     /*  810678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BITOP3_B16_e64),
     /*  810681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810686 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810688 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810691 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810696 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  810698 */     GIR_RootToRootCopy, /*OpIdx*/5, // bitop3
     /*  810700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810703 */     GIR_RootConstrainSelectedInstOperands,
     /*  810704 */     // GIR_Coverage, 7480,
     /*  810704 */     GIR_EraseRootFromParent_Done,
     /*  810705 */   // Label 13010: @810705
     /*  810705 */   GIM_Try, /*On fail goto*//*Label 13011*/ GIMT_Encode4(810761), // Rule ID 7482 //
     /*  810710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBitOp3Insts_UseFakeTrue16Insts_isGFX1250Plus),
     /*  810713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_bitop3),
     /*  810718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  810721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  810724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  810727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  810730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810734 */     // MIs[0] bitop3
     /*  810734 */     // No operand predicates
     /*  810734 */     // (intrinsic_wo_chain:{ *:[i16] } 2235:{ *:[iPTR] }, i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$bitop3)  =>  (V_BITOP3_B16_gfx1250_fake16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, (timm:{ *:[i32] }):$bitop3, 0:{ *:[i32] })
     /*  810734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BITOP3_B16_gfx1250_fake16_e64),
     /*  810737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810742 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810744 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810747 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810752 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  810754 */     GIR_RootToRootCopy, /*OpIdx*/5, // bitop3
     /*  810756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810759 */     GIR_RootConstrainSelectedInstOperands,
     /*  810760 */     // GIR_Coverage, 7482,
     /*  810760 */     GIR_EraseRootFromParent_Done,
     /*  810761 */   // Label 13011: @810761
     /*  810761 */   GIM_Try, /*On fail goto*//*Label 13012*/ GIMT_Encode4(810817), // Rule ID 7484 //
     /*  810766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBitOp3Insts_UseRealTrue16Insts_isGFX1250Plus),
     /*  810769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_bitop3),
     /*  810774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  810777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  810780 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  810783 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16,
     /*  810786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  810790 */     // MIs[0] bitop3
     /*  810790 */     // No operand predicates
     /*  810790 */     // (intrinsic_wo_chain:{ *:[i16] } 2235:{ *:[iPTR] }, i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$bitop3)  =>  (V_BITOP3_B16_gfx1250_t16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrcT_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrcT_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrcT_b16:{ *:[i16] }:$src2, (timm:{ *:[i32] }):$bitop3, 0:{ *:[i32] })
     /*  810790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BITOP3_B16_gfx1250_t16_e64),
     /*  810793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810798 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  810800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810803 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  810805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810808 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  810810 */     GIR_RootToRootCopy, /*OpIdx*/5, // bitop3
     /*  810812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810815 */     GIR_RootConstrainSelectedInstOperands,
     /*  810816 */     // GIR_Coverage, 7484,
     /*  810816 */     GIR_EraseRootFromParent_Done,
     /*  810817 */   // Label 13012: @810817
     /*  810817 */   GIM_Try, /*On fail goto*//*Label 13013*/ GIMT_Encode4(810915), // Rule ID 3337 //
     /*  810822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPkAddMinMaxInsts),
     /*  810825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_pk_add_max_i16),
     /*  810830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  810833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  810836 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  810839 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  810842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810846 */     // MIs[0] clamp
     /*  810846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  810856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  810863 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  810870 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3353:{ *:[iPTR] }, (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_PK_ADD_MAX_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  810870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_MAX_I16),
     /*  810873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  810880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  810885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  810890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  810895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  810900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  810905 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  810907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  810913 */     GIR_RootConstrainSelectedInstOperands,
     /*  810914 */     // GIR_Coverage, 3337,
     /*  810914 */     GIR_EraseRootFromParent_Done,
     /*  810915 */   // Label 13013: @810915
     /*  810915 */   GIM_Try, /*On fail goto*//*Label 13014*/ GIMT_Encode4(811013), // Rule ID 3338 //
     /*  810920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPkAddMinMaxInsts),
     /*  810923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_pk_add_max_u16),
     /*  810928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  810931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  810934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  810937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  810940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  810944 */     // MIs[0] clamp
     /*  810944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  810947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  810954 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  810961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  810968 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3354:{ *:[iPTR] }, (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_PK_ADD_MAX_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  810968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_MAX_U16),
     /*  810971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  810973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  810978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  810983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  810988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  810993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  810998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811003 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811011 */     GIR_RootConstrainSelectedInstOperands,
     /*  811012 */     // GIR_Coverage, 3338,
     /*  811012 */     GIR_EraseRootFromParent_Done,
     /*  811013 */   // Label 13014: @811013
     /*  811013 */   GIM_Try, /*On fail goto*//*Label 13015*/ GIMT_Encode4(811111), // Rule ID 3339 //
     /*  811018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPkAddMinMaxInsts),
     /*  811021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_pk_add_min_i16),
     /*  811026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  811029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  811032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  811035 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  811038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811042 */     // MIs[0] clamp
     /*  811042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811045 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  811052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  811059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  811066 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3355:{ *:[iPTR] }, (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_PK_ADD_MIN_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_MIN_I16),
     /*  811069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811101 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811109 */     GIR_RootConstrainSelectedInstOperands,
     /*  811110 */     // GIR_Coverage, 3339,
     /*  811110 */     GIR_EraseRootFromParent_Done,
     /*  811111 */   // Label 13015: @811111
     /*  811111 */   GIM_Try, /*On fail goto*//*Label 13016*/ GIMT_Encode4(811209), // Rule ID 3340 //
     /*  811116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPkAddMinMaxInsts),
     /*  811119 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_pk_add_min_u16),
     /*  811124 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  811127 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  811130 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  811133 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  811136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811140 */     // MIs[0] clamp
     /*  811140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811143 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  811150 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  811157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  811164 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3356:{ *:[iPTR] }, (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_PK_ADD_MIN_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_MIN_U16),
     /*  811167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811199 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811207 */     GIR_RootConstrainSelectedInstOperands,
     /*  811208 */     // GIR_Coverage, 3340,
     /*  811208 */     GIR_EraseRootFromParent_Done,
     /*  811209 */   // Label 13016: @811209
     /*  811209 */   GIM_Try, /*On fail goto*//*Label 13017*/ GIMT_Encode4(811313), // Rule ID 3341 //
     /*  811214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*  811217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot2),
     /*  811222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  811228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  811231 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811238 */     // MIs[0] clamp
     /*  811238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811248 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811255 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811262 */     // (intrinsic_wo_chain:{ *:[i32] } 3483:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_I32_I16:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16),
     /*  811265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811297 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811311 */     GIR_RootConstrainSelectedInstOperands,
     /*  811312 */     // GIR_Coverage, 3341,
     /*  811312 */     GIR_EraseRootFromParent_Done,
     /*  811313 */   // Label 13017: @811313
     /*  811313 */   GIM_Try, /*On fail goto*//*Label 13018*/ GIMT_Encode4(811417), // Rule ID 3342 //
     /*  811318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
     /*  811321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot2),
     /*  811326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  811332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  811335 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811342 */     // MIs[0] clamp
     /*  811342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811359 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811366 */     // (intrinsic_wo_chain:{ *:[i32] } 3608:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_U32_U16:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16),
     /*  811369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811401 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811415 */     GIR_RootConstrainSelectedInstOperands,
     /*  811416 */     // GIR_Coverage, 3342,
     /*  811416 */     GIR_EraseRootFromParent_Done,
     /*  811417 */   // Label 13018: @811417
     /*  811417 */   GIM_Try, /*On fail goto*//*Label 13019*/ GIMT_Encode4(811521), // Rule ID 3343 //
     /*  811422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot10Insts),
     /*  811425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2),
     /*  811430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  811436 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  811439 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811446 */     // MIs[0] clamp
     /*  811446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811449 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811456 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811470 */     // (intrinsic_wo_chain:{ *:[f32] } 2444:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_F32_F16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F32_F16),
     /*  811473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811505 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811519 */     GIR_RootConstrainSelectedInstOperands,
     /*  811520 */     // GIR_Coverage, 3343,
     /*  811520 */     GIR_EraseRootFromParent_Done,
     /*  811521 */   // Label 13019: @811521
     /*  811521 */   GIM_Try, /*On fail goto*//*Label 13020*/ GIMT_Encode4(811619), // Rule ID 3345 //
     /*  811526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*  811529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot4),
     /*  811534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  811540 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  811543 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811550 */     // MIs[0] clamp
     /*  811550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811553 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811560 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811574 */     // (intrinsic_wo_chain:{ *:[i32] } 3609:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_U32_U8:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
     /*  811577 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811609 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811617 */     GIR_RootConstrainSelectedInstOperands,
     /*  811618 */     // GIR_Coverage, 3345,
     /*  811618 */     GIR_EraseRootFromParent_Done,
     /*  811619 */   // Label 13020: @811619
     /*  811619 */   GIM_Try, /*On fail goto*//*Label 13021*/ GIMT_Encode4(811717), // Rule ID 3346 //
     /*  811624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
     /*  811627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot8),
     /*  811632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  811638 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  811641 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811648 */     // MIs[0] clamp
     /*  811648 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811651 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811672 */     // (intrinsic_wo_chain:{ *:[i32] } 3610:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_U32_U4:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_U32_U4),
     /*  811675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811707 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811715 */     GIR_RootConstrainSelectedInstOperands,
     /*  811716 */     // GIR_Coverage, 3346,
     /*  811716 */     GIR_EraseRootFromParent_Done,
     /*  811717 */   // Label 13021: @811717
     /*  811717 */   GIM_Try, /*On fail goto*//*Label 13022*/ GIMT_Encode4(811815), // Rule ID 3347 //
     /*  811722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*  811725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4),
     /*  811730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  811736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  811739 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811746 */     // MIs[0] clamp
     /*  811746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811770 */     // (intrinsic_wo_chain:{ *:[i32] } 3484:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_I32_I8:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
     /*  811773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811805 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811813 */     GIR_RootConstrainSelectedInstOperands,
     /*  811814 */     // GIR_Coverage, 3347,
     /*  811814 */     GIR_EraseRootFromParent_Done,
     /*  811815 */   // Label 13022: @811815
     /*  811815 */   GIM_Try, /*On fail goto*//*Label 13023*/ GIMT_Encode4(811913), // Rule ID 3348 //
     /*  811820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
     /*  811823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8),
     /*  811828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  811834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  811837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811844 */     // MIs[0] clamp
     /*  811844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  811847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811854 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811861 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
     /*  811868 */     // (intrinsic_wo_chain:{ *:[i32] } 3485:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_I32_I4:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
     /*  811868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_I4),
     /*  811871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  811878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  811883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  811888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  811893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  811898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  811903 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811905 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  811911 */     GIR_RootConstrainSelectedInstOperands,
     /*  811912 */     // GIR_Coverage, 3348,
     /*  811912 */     GIR_EraseRootFromParent_Done,
     /*  811913 */   // Label 13023: @811913
     /*  811913 */   GIM_Try, /*On fail goto*//*Label 13024*/ GIMT_Encode4(811957), // Rule ID 3050 //
     /*  811918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddMinMaxInsts),
     /*  811921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_add_max_i32),
     /*  811926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  811932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  811935 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811942 */     // MIs[0] clamp
     /*  811942 */     // No operand predicates
     /*  811942 */     // (intrinsic_wo_chain:{ *:[i32] } 2226:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_ADD_MAX_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  811942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_MAX_I32_e64),
     /*  811945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811947 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  811949 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  811951 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  811953 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811955 */     GIR_RootConstrainSelectedInstOperands,
     /*  811956 */     // GIR_Coverage, 3050,
     /*  811956 */     GIR_EraseRootFromParent_Done,
     /*  811957 */   // Label 13024: @811957
     /*  811957 */   GIM_Try, /*On fail goto*//*Label 13025*/ GIMT_Encode4(812001), // Rule ID 3051 //
     /*  811962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddMinMaxInsts),
     /*  811965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_add_max_u32),
     /*  811970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  811973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  811976 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  811979 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  811982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  811986 */     // MIs[0] clamp
     /*  811986 */     // No operand predicates
     /*  811986 */     // (intrinsic_wo_chain:{ *:[i32] } 2227:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_ADD_MAX_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  811986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_MAX_U32_e64),
     /*  811989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  811991 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  811993 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  811995 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  811997 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  811999 */     GIR_RootConstrainSelectedInstOperands,
     /*  812000 */     // GIR_Coverage, 3051,
     /*  812000 */     GIR_EraseRootFromParent_Done,
     /*  812001 */   // Label 13025: @812001
     /*  812001 */   GIM_Try, /*On fail goto*//*Label 13026*/ GIMT_Encode4(812045), // Rule ID 3052 //
     /*  812006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddMinMaxInsts),
     /*  812009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_add_min_i32),
     /*  812014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812023 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812030 */     // MIs[0] clamp
     /*  812030 */     // No operand predicates
     /*  812030 */     // (intrinsic_wo_chain:{ *:[i32] } 2228:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_ADD_MIN_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  812030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_MIN_I32_e64),
     /*  812033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812035 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  812037 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  812039 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  812041 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  812043 */     GIR_RootConstrainSelectedInstOperands,
     /*  812044 */     // GIR_Coverage, 3052,
     /*  812044 */     GIR_EraseRootFromParent_Done,
     /*  812045 */   // Label 13026: @812045
     /*  812045 */   GIM_Try, /*On fail goto*//*Label 13027*/ GIMT_Encode4(812089), // Rule ID 3053 //
     /*  812050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddMinMaxInsts),
     /*  812053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_add_min_u32),
     /*  812058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812074 */     // MIs[0] clamp
     /*  812074 */     // No operand predicates
     /*  812074 */     // (intrinsic_wo_chain:{ *:[i32] } 2229:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_ADD_MIN_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  812074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_MIN_U32_e64),
     /*  812077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812079 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  812081 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  812083 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  812085 */     GIR_RootToRootCopy, /*OpIdx*/5, // clamp
     /*  812087 */     GIR_RootConstrainSelectedInstOperands,
     /*  812088 */     // GIR_Coverage, 3053,
     /*  812088 */     GIR_EraseRootFromParent_Done,
     /*  812089 */   // Label 13027: @812089
     /*  812089 */   GIM_Reject,
     /*  812090 */ // Label 12939: @812090
     /*  812090 */ GIM_Try, /*On fail goto*//*Label 13028*/ GIMT_Encode4(813382),
     /*  812095 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
     /*  812098 */   GIM_Try, /*On fail goto*//*Label 13029*/ GIMT_Encode4(812166), // Rule ID 7408 //
     /*  812103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_f16_fp8),
     /*  812108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  812111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  812114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812124 */     // MIs[0] src_sel
     /*  812124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  812127 */     // MIs[0] Operand 6
     /*  812127 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/6, GIMT_Encode8(0),
     /*  812138 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2310:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$src_sel, 0:{ *:[i1] })  =>  (V_CVT_SCALEF32_F16_FP8_e64:{ *:[v2f16] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[f32] }:$src1, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  812138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_F16_FP8_e64),
     /*  812141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812143 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // src_sel
     /*  812149 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812151 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // src_sel
     /*  812157 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812159 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812164 */     GIR_RootConstrainSelectedInstOperands,
     /*  812165 */     // GIR_Coverage, 7408,
     /*  812165 */     GIR_EraseRootFromParent_Done,
     /*  812166 */   // Label 13029: @812166
     /*  812166 */   GIM_Try, /*On fail goto*//*Label 13030*/ GIMT_Encode4(812234), // Rule ID 7409 //
     /*  812171 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_f16_bf8),
     /*  812176 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  812179 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  812182 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812185 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812192 */     // MIs[0] src_sel
     /*  812192 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  812195 */     // MIs[0] Operand 6
     /*  812195 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/6, GIMT_Encode8(0),
     /*  812206 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2309:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$src_sel, 0:{ *:[i1] })  =>  (V_CVT_SCALEF32_F16_BF8_e64:{ *:[v2f16] } (SrcAndDstSelToOpSelXForm_0_0:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_0:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[f32] }:$src1, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  812206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_F16_BF8_e64),
     /*  812209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_0), // src_sel
     /*  812217 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812219 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_0), // src_sel
     /*  812225 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812227 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812232 */     GIR_RootConstrainSelectedInstOperands,
     /*  812233 */     // GIR_Coverage, 7409,
     /*  812233 */     GIR_EraseRootFromParent_Done,
     /*  812234 */   // Label 13030: @812234
     /*  812234 */   GIM_Try, /*On fail goto*//*Label 13031*/ GIMT_Encode4(812302), // Rule ID 7410 //
     /*  812239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_f16_fp8),
     /*  812244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  812247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  812250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812253 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812260 */     // MIs[0] src_sel
     /*  812260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  812263 */     // MIs[0] Operand 6
     /*  812263 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/6, GIMT_Encode8(18446744073709551615u),
     /*  812274 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2310:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$src_sel, -1:{ *:[i1] })  =>  (V_CVT_SCALEF32_F16_FP8_e64:{ *:[v2f16] } (SrcAndDstSelToOpSelXForm_0_1:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_1:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[f32] }:$src1, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  812274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_F16_FP8_e64),
     /*  812277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812279 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_1), // src_sel
     /*  812285 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812287 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_1), // src_sel
     /*  812293 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812295 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812300 */     GIR_RootConstrainSelectedInstOperands,
     /*  812301 */     // GIR_Coverage, 7410,
     /*  812301 */     GIR_EraseRootFromParent_Done,
     /*  812302 */   // Label 13031: @812302
     /*  812302 */   GIM_Try, /*On fail goto*//*Label 13032*/ GIMT_Encode4(812370), // Rule ID 7411 //
     /*  812307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_f16_bf8),
     /*  812312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  812315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  812318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812321 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812328 */     // MIs[0] src_sel
     /*  812328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  812331 */     // MIs[0] Operand 6
     /*  812331 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/6, GIMT_Encode8(18446744073709551615u),
     /*  812342 */     // (intrinsic_wo_chain:{ *:[v2f16] } 2309:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, i32:{ *:[i32] }:$src0, f32:{ *:[f32] }:$src1, (timm:{ *:[i32] }):$src_sel, -1:{ *:[i1] })  =>  (V_CVT_SCALEF32_F16_BF8_e64:{ *:[v2f16] } (SrcAndDstSelToOpSelXForm_0_1:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[i32] }:$src0, (SrcAndDstSelToOpSelXForm_1_1:{ *:[i32] } ?:{ *:[i32] }:$src_sel), ?:{ *:[f32] }:$src1, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  812342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_F16_BF8_e64),
     /*  812345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812347 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_0_1), // src_sel
     /*  812353 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812355 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_1_1), // src_sel
     /*  812361 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812363 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812368 */     GIR_RootConstrainSelectedInstOperands,
     /*  812369 */     // GIR_Coverage, 7411,
     /*  812369 */     GIR_EraseRootFromParent_Done,
     /*  812370 */   // Label 13032: @812370
     /*  812370 */   GIM_Try, /*On fail goto*//*Label 13033*/ GIMT_Encode4(812438), // Rule ID 4162 //
     /*  812375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX90APlus),
     /*  812378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2),
     /*  812383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812392 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  812395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812399 */     // MIs[0] attrchan
     /*  812399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  812402 */     // MIs[0] attr
     /*  812402 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  812405 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  812409 */     // (intrinsic_wo_chain:{ *:[f32] } 3261:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_P2_F32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
     /*  812409 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  812413 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  812419 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // M0
     /*  812423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F32),
     /*  812426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812428 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  812430 */     GIR_RootToRootCopy, /*OpIdx*/3, // vsrc
     /*  812432 */     GIR_RootToRootCopy, /*OpIdx*/5, // attr
     /*  812434 */     GIR_RootToRootCopy, /*OpIdx*/4, // attrchan
     /*  812436 */     GIR_RootConstrainSelectedInstOperands,
     /*  812437 */     // GIR_Coverage, 4162,
     /*  812437 */     GIR_EraseRootFromParent_Done,
     /*  812438 */   // Label 13033: @812438
     /*  812438 */   GIM_Try, /*On fail goto*//*Label 13034*/ GIMT_Encode4(812500), // Rule ID 7412 //
     /*  812443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_fp8_f32),
     /*  812448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  812451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  812454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812460 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812467 */     // MIs[0] word_sel
     /*  812467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812470 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2330:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_FP8_F32_e64:{ *:[v2i16] } (DstSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, VGPR_32:{ *:[v2i16] }:$vdst_in)
     /*  812470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_FP8_F32_e64),
     /*  812473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812475 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSelXForm), // word_sel
     /*  812481 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812486 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812491 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812493 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812498 */     GIR_RootConstrainSelectedInstOperands,
     /*  812499 */     // GIR_Coverage, 7412,
     /*  812499 */     GIR_EraseRootFromParent_Done,
     /*  812500 */   // Label 13034: @812500
     /*  812500 */   GIM_Try, /*On fail goto*//*Label 13035*/ GIMT_Encode4(812562), // Rule ID 7413 //
     /*  812505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_bf8_f32),
     /*  812510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  812513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  812516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812519 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812522 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812529 */     // MIs[0] word_sel
     /*  812529 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812532 */     // (intrinsic_wo_chain:{ *:[v2i16] } 2318:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$word_sel)  =>  (V_CVT_SCALEF32_PK_BF8_F32_e64:{ *:[v2i16] } (DstSelToOpSelXForm:{ *:[i32] } ?:{ *:[i1] }:$word_sel), ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, VGPR_32:{ *:[v2i16] }:$vdst_in)
     /*  812532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_BF8_F32_e64),
     /*  812535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812537 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSelXForm), // word_sel
     /*  812543 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812548 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812553 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812555 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812560 */     GIR_RootConstrainSelectedInstOperands,
     /*  812561 */     // GIR_Coverage, 7413,
     /*  812561 */     GIR_EraseRootFromParent_Done,
     /*  812562 */   // Label 13035: @812562
     /*  812562 */   GIM_Try, /*On fail goto*//*Label 13036*/ GIMT_Encode4(812627), // Rule ID 7433 //
     /*  812567 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_pk_fp4_f32),
     /*  812572 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812575 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812578 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  812581 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812584 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812591 */     // MIs[0] index
     /*  812591 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812594 */     // (intrinsic_wo_chain:{ *:[i32] } 2327:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_PK_FP4_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_PK_FP4_F32_e64),
     /*  812597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812599 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  812605 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812610 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812612 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  812618 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812620 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812625 */     GIR_RootConstrainSelectedInstOperands,
     /*  812626 */     // GIR_Coverage, 7433,
     /*  812626 */     GIR_EraseRootFromParent_Done,
     /*  812627 */   // Label 13036: @812627
     /*  812627 */   GIM_Try, /*On fail goto*//*Label 13037*/ GIMT_Encode4(812692), // Rule ID 7435 //
     /*  812632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk_fp4_f16),
     /*  812637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  812646 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812649 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812656 */     // MIs[0] index
     /*  812656 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812659 */     // (intrinsic_wo_chain:{ *:[i32] } 2363:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_PK_FP4_F16_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F16_e64),
     /*  812662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812664 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  812670 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812675 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812677 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  812683 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812685 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812690 */     GIR_RootConstrainSelectedInstOperands,
     /*  812691 */     // GIR_Coverage, 7435,
     /*  812691 */     GIR_EraseRootFromParent_Done,
     /*  812692 */   // Label 13037: @812692
     /*  812692 */   GIM_Try, /*On fail goto*//*Label 13038*/ GIMT_Encode4(812760), // Rule ID 7436 //
     /*  812697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  812700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk_fp4_f32),
     /*  812705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  812714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812717 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812724 */     // MIs[0] index
     /*  812724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812727 */     // (intrinsic_wo_chain:{ *:[i32] } 2364:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_PK_FP4_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_e64),
     /*  812730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812732 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  812738 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812743 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812745 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  812751 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812753 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812758 */     GIR_RootConstrainSelectedInstOperands,
     /*  812759 */     // GIR_Coverage, 7436,
     /*  812759 */     GIR_EraseRootFromParent_Done,
     /*  812760 */   // Label 13038: @812760
     /*  812760 */   GIM_Try, /*On fail goto*//*Label 13039*/ GIMT_Encode4(812828), // Rule ID 7437 //
     /*  812765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  812768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk_fp4_f32),
     /*  812773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  812782 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812785 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812792 */     // MIs[0] index
     /*  812792 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812795 */     // (intrinsic_wo_chain:{ *:[i32] } 2364:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_PK_FP4_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_e64),
     /*  812798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812800 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  812806 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812811 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812813 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  812819 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812821 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812826 */     GIR_RootConstrainSelectedInstOperands,
     /*  812827 */     // GIR_Coverage, 7437,
     /*  812827 */     GIR_EraseRootFromParent_Done,
     /*  812828 */   // Label 13039: @812828
     /*  812828 */   GIM_Try, /*On fail goto*//*Label 13040*/ GIMT_Encode4(812896), // Rule ID 7438 //
     /*  812833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  812836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk_fp4_f32),
     /*  812841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  812850 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812853 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812860 */     // MIs[0] index
     /*  812860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812863 */     // (intrinsic_wo_chain:{ *:[i32] } 2364:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_PK_FP4_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_e64),
     /*  812866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812868 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  812874 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812879 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812881 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  812887 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812889 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812894 */     GIR_RootConstrainSelectedInstOperands,
     /*  812895 */     // GIR_Coverage, 7438,
     /*  812895 */     GIR_EraseRootFromParent_Done,
     /*  812896 */   // Label 13040: @812896
     /*  812896 */   GIM_Try, /*On fail goto*//*Label 13041*/ GIMT_Encode4(812964), // Rule ID 7439 //
     /*  812901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  812904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk_fp4_f32),
     /*  812909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812915 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  812918 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812921 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812928 */     // MIs[0] index
     /*  812928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812931 */     // (intrinsic_wo_chain:{ *:[i32] } 2364:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_PK_FP4_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_e64),
     /*  812934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  812936 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  812942 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  812944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812947 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  812949 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  812955 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  812957 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  812959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  812962 */     GIR_RootConstrainSelectedInstOperands,
     /*  812963 */     // GIR_Coverage, 7439,
     /*  812963 */     GIR_EraseRootFromParent_Done,
     /*  812964 */   // Label 13041: @812964
     /*  812964 */   GIM_Try, /*On fail goto*//*Label 13042*/ GIMT_Encode4(813032), // Rule ID 7440 //
     /*  812969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  812972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_pk_fp4_f32),
     /*  812977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  812980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  812983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  812986 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  812989 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  812992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  812996 */     // MIs[0] index
     /*  812996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  812999 */     // (intrinsic_wo_chain:{ *:[i32] } 2364:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_PK_FP4_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[v2f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  812999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_PK_FP4_F32_e64),
     /*  813002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813004 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  813010 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813015 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  813017 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  813023 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  813025 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  813027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813030 */     GIR_RootConstrainSelectedInstOperands,
     /*  813031 */     // GIR_Coverage, 7440,
     /*  813031 */     GIR_EraseRootFromParent_Done,
     /*  813032 */   // Label 13042: @813032
     /*  813032 */   GIM_Try, /*On fail goto*//*Label 13043*/ GIMT_Encode4(813097), // Rule ID 7441 //
     /*  813037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_bf8_f16),
     /*  813042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  813048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  813051 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  813054 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  813057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813061 */     // MIs[0] index
     /*  813061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  813064 */     // (intrinsic_wo_chain:{ *:[i32] } 2357:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_BF8_F16_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  813064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_BF8_F16_e64),
     /*  813067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813069 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  813075 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813080 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  813082 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  813088 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  813090 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  813092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813095 */     GIR_RootConstrainSelectedInstOperands,
     /*  813096 */     // GIR_Coverage, 7441,
     /*  813096 */     GIR_EraseRootFromParent_Done,
     /*  813097 */   // Label 13043: @813097
     /*  813097 */   GIM_Try, /*On fail goto*//*Label 13044*/ GIMT_Encode4(813162), // Rule ID 7442 //
     /*  813102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_bf8_f32),
     /*  813107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  813113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  813116 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  813119 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  813122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813126 */     // MIs[0] index
     /*  813126 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  813129 */     // (intrinsic_wo_chain:{ *:[i32] } 2358:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_BF8_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  813129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_BF8_F32_e64),
     /*  813132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813134 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  813140 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813145 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  813147 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  813153 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  813155 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  813157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813160 */     GIR_RootConstrainSelectedInstOperands,
     /*  813161 */     // GIR_Coverage, 7442,
     /*  813161 */     GIR_EraseRootFromParent_Done,
     /*  813162 */   // Label 13044: @813162
     /*  813162 */   GIM_Try, /*On fail goto*//*Label 13045*/ GIMT_Encode4(813227), // Rule ID 7443 //
     /*  813167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_fp8_f16),
     /*  813172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  813178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /*  813181 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  813184 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  813187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813191 */     // MIs[0] index
     /*  813191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  813194 */     // (intrinsic_wo_chain:{ *:[i32] } 2360:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_FP8_F16_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  813194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_FP8_F16_e64),
     /*  813197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813199 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  813205 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813210 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  813212 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  813218 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  813220 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  813222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813225 */     GIR_RootConstrainSelectedInstOperands,
     /*  813226 */     // GIR_Coverage, 7443,
     /*  813226 */     GIR_EraseRootFromParent_Done,
     /*  813227 */   // Label 13045: @813227
     /*  813227 */   GIM_Try, /*On fail goto*//*Label 13046*/ GIMT_Encode4(813292), // Rule ID 7444 //
     /*  813232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scalef32_sr_fp8_f32),
     /*  813237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  813243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  813246 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  813249 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  813252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813256 */     // MIs[0] index
     /*  813256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  813259 */     // (intrinsic_wo_chain:{ *:[i32] } 2361:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2, (timm:{ *:[i32] }):$index)  =>  (V_CVT_SCALEF32_SR_FP8_F32_e64:{ *:[i32] } (DstSelToOpSel3XForm:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, (SrcAndDstSelToOpSelXForm_2_0:{ *:[i32] } ?:{ *:[i32] }:$index), ?:{ *:[f32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  813259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALEF32_SR_FP8_F32_e64),
     /*  813262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813264 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderDstSelToOpSel3XFormXForm), // index
     /*  813270 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813275 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  813277 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderSrcAndDstSelToOpSelXForm_2_0), // index
     /*  813283 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  813285 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  813287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813290 */     GIR_RootConstrainSelectedInstOperands,
     /*  813291 */     // GIR_Coverage, 7444,
     /*  813291 */     GIR_EraseRootFromParent_Done,
     /*  813292 */   // Label 13046: @813292
     /*  813292 */   GIM_Try, /*On fail goto*//*Label 13047*/ GIMT_Encode4(813381), // Rule ID 3013 //
     /*  813297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_has32BankLDS_isNotGFX90APlus),
     /*  813300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1_f16),
     /*  813305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  813311 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  813314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813318 */     // MIs[0] attrchan
     /*  813318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  813321 */     // MIs[0] attr
     /*  813321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  813324 */     // MIs[0] high
     /*  813324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  813327 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  813331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  813338 */     // (intrinsic_wo_chain:{ *:[f32] } 3259:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, (timm:{ *:[i1] }):$high, M0:{ *:[i32] })  =>  (V_INTERP_P1LL_F16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i1] }):$high)
     /*  813338 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  813342 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  813348 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // M0
     /*  813352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1LL_F16),
     /*  813355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  813362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  813367 */     GIR_RootToRootCopy, /*OpIdx*/4, // attr
     /*  813369 */     GIR_RootToRootCopy, /*OpIdx*/3, // attrchan
     /*  813371 */     GIR_RootToRootCopy, /*OpIdx*/5, // high
     /*  813373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813379 */     GIR_RootConstrainSelectedInstOperands,
     /*  813380 */     // GIR_Coverage, 3013,
     /*  813380 */     GIR_EraseRootFromParent_Done,
     /*  813381 */   // Label 13047: @813381
     /*  813381 */   GIM_Reject,
     /*  813382 */ // Label 13028: @813382
     /*  813382 */ GIM_Try, /*On fail goto*//*Label 13048*/ GIMT_Encode4(813645),
     /*  813387 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
     /*  813390 */   GIM_Try, /*On fail goto*//*Label 13049*/ GIMT_Encode4(813464), // Rule ID 7596 //
     /*  813395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
     /*  813398 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sudot4),
     /*  813403 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  813409 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  813412 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  813415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813419 */     // MIs[0] src0_mods
     /*  813419 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  813422 */     // MIs[0] src1_mods
     /*  813422 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  813425 */     // MIs[0] clamp
     /*  813425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  813428 */     // (intrinsic_wo_chain:{ *:[i32] } 3574:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_mods, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_mods, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_I32_IU8:{ *:[i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_mods), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_mods), i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  813428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_IU8),
     /*  813431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813433 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_mods
     /*  813439 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813441 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_mods
     /*  813447 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  813449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  813452 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  813454 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  813456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813462 */     GIR_RootConstrainSelectedInstOperands,
     /*  813463 */     // GIR_Coverage, 7596,
     /*  813463 */     GIR_EraseRootFromParent_Done,
     /*  813464 */   // Label 13049: @813464
     /*  813464 */   GIM_Try, /*On fail goto*//*Label 13050*/ GIMT_Encode4(813538), // Rule ID 7597 //
     /*  813469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
     /*  813472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sudot8),
     /*  813477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  813480 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  813483 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  813486 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  813489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813493 */     // MIs[0] src0_mods
     /*  813493 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  813496 */     // MIs[0] src1_mods
     /*  813496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  813499 */     // MIs[0] clamp
     /*  813499 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  813502 */     // (intrinsic_wo_chain:{ *:[i32] } 3575:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_mods, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_mods, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_I32_IU4:{ *:[i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_mods), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_mods), i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  813502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_IU4),
     /*  813505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813507 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_mods
     /*  813513 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  813515 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_mods
     /*  813521 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  813523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  813526 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  813528 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  813530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813533 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813536 */     GIR_RootConstrainSelectedInstOperands,
     /*  813537 */     // GIR_Coverage, 7597,
     /*  813537 */     GIR_EraseRootFromParent_Done,
     /*  813538 */   // Label 13050: @813538
     /*  813538 */   GIM_Try, /*On fail goto*//*Label 13051*/ GIMT_Encode4(813644), // Rule ID 3012 //
     /*  813543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isNotGFX90APlus),
     /*  813546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_f16),
     /*  813551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /*  813554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  813557 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  813560 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  813563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  813567 */     // MIs[0] attrchan
     /*  813567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  813570 */     // MIs[0] attr
     /*  813570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  813573 */     // MIs[0] high
     /*  813573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  813576 */     GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  813580 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
     /*  813587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /*  813594 */     // (intrinsic_wo_chain:{ *:[f16] } 3262:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, (timm:{ *:[i1] }):$high, M0:{ *:[i32] })  =>  (V_INTERP_P2_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$high)
     /*  813594 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  813598 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  813604 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // M0
     /*  813608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16),
     /*  813611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  813613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  813618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  813623 */     GIR_RootToRootCopy, /*OpIdx*/5, // attr
     /*  813625 */     GIR_RootToRootCopy, /*OpIdx*/4, // attrchan
     /*  813627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  813632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  813637 */     GIR_RootToRootCopy, /*OpIdx*/6, // high
     /*  813639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813642 */     GIR_RootConstrainSelectedInstOperands,
     /*  813643 */     // GIR_Coverage, 3012,
     /*  813643 */     GIR_EraseRootFromParent_Done,
     /*  813644 */   // Label 13051: @813644
     /*  813644 */   GIM_Reject,
     /*  813645 */ // Label 13048: @813645
     /*  813645 */ GIM_Reject,
     /*  813646 */ // Label 39: @813646
     /*  813646 */ GIM_Try, /*On fail goto*//*Label 13052*/ GIMT_Encode4(813820),
     /*  813651 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
     /*  813654 */   GIM_Try, /*On fail goto*//*Label 13053*/ GIMT_Encode4(813669), // Rule ID 4151 //
     /*  813659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_inv),
     /*  813664 */     // (intrinsic_void 3434:{ *:[iPTR] })  =>  (S_DCACHE_INV)
     /*  813664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_INV),
     /*  813667 */     GIR_RootConstrainSelectedInstOperands,
     /*  813668 */     // GIR_Coverage, 4151,
     /*  813668 */     GIR_EraseRootFromParent_Done,
     /*  813669 */   // Label 13053: @813669
     /*  813669 */   GIM_Try, /*On fail goto*//*Label 13054*/ GIMT_Encode4(813687), // Rule ID 4152 //
     /*  813674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX8GFX9),
     /*  813677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_inv_vol),
     /*  813682 */     // (intrinsic_void 3435:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
     /*  813682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_INV_VOL),
     /*  813685 */     GIR_RootConstrainSelectedInstOperands,
     /*  813686 */     // GIR_Coverage, 4152,
     /*  813686 */     GIR_EraseRootFromParent_Done,
     /*  813687 */   // Label 13054: @813687
     /*  813687 */   GIM_Try, /*On fail goto*//*Label 13055*/ GIMT_Encode4(813705), // Rule ID 4153 //
     /*  813692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasScalarStores_isGFX8Plus),
     /*  813695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_wb),
     /*  813700 */     // (intrinsic_void 3436:{ *:[iPTR] })  =>  (S_DCACHE_WB)
     /*  813700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_WB),
     /*  813703 */     GIR_RootConstrainSelectedInstOperands,
     /*  813704 */     // GIR_Coverage, 4153,
     /*  813704 */     GIR_EraseRootFromParent_Done,
     /*  813705 */   // Label 13055: @813705
     /*  813705 */   GIM_Try, /*On fail goto*//*Label 13056*/ GIMT_Encode4(813723), // Rule ID 4154 //
     /*  813710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasScalarStores_isGFX8Plus),
     /*  813713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_wb_vol),
     /*  813718 */     // (intrinsic_void 3437:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
     /*  813718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_WB_VOL),
     /*  813721 */     GIR_RootConstrainSelectedInstOperands,
     /*  813722 */     // GIR_Coverage, 4154,
     /*  813722 */     GIR_EraseRootFromParent_Done,
     /*  813723 */   // Label 13056: @813723
     /*  813723 */   GIM_Try, /*On fail goto*//*Label 13057*/ GIMT_Encode4(813741), // Rule ID 4157 //
     /*  813728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6),
     /*  813731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1_sc),
     /*  813736 */     // (intrinsic_void 2237:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
     /*  813736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1_SC),
     /*  813739 */     GIR_RootConstrainSelectedInstOperands,
     /*  813740 */     // GIR_Coverage, 4157,
     /*  813740 */     GIR_EraseRootFromParent_Done,
     /*  813741 */   // Label 13057: @813741
     /*  813741 */   GIM_Try, /*On fail goto*//*Label 13058*/ GIMT_Encode4(813759), // Rule ID 4158 //
     /*  813746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX940Plus),
     /*  813749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1),
     /*  813754 */     // (intrinsic_void 2236:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
     /*  813754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1),
     /*  813757 */     GIR_RootConstrainSelectedInstOperands,
     /*  813758 */     // GIR_Coverage, 4158,
     /*  813758 */     GIR_EraseRootFromParent_Done,
     /*  813759 */   // Label 13058: @813759
     /*  813759 */   GIM_Try, /*On fail goto*//*Label 13059*/ GIMT_Encode4(813777), // Rule ID 4159 //
     /*  813764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX940Plus),
     /*  813767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1_vol),
     /*  813772 */     // (intrinsic_void 2238:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
     /*  813772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1_VOL),
     /*  813775 */     GIR_RootConstrainSelectedInstOperands,
     /*  813776 */     // GIR_Coverage, 4159,
     /*  813776 */     GIR_EraseRootFromParent_Done,
     /*  813777 */   // Label 13059: @813777
     /*  813777 */   GIM_Try, /*On fail goto*//*Label 13060*/ GIMT_Encode4(813798), // Rule ID 4803 //
     /*  813782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
     /*  813785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_event_export_ready),
     /*  813790 */     // (intrinsic_void 3465:{ *:[iPTR] })  =>  (S_WAIT_EVENT 0:{ *:[i16] })
     /*  813790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EVENT),
     /*  813793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  813796 */     GIR_RootConstrainSelectedInstOperands,
     /*  813797 */     // GIR_Coverage, 4803,
     /*  813797 */     GIR_EraseRootFromParent_Done,
     /*  813798 */   // Label 13060: @813798
     /*  813798 */   GIM_Try, /*On fail goto*//*Label 13061*/ GIMT_Encode4(813819), // Rule ID 4804 //
     /*  813803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  813806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_event_export_ready),
     /*  813811 */     // (intrinsic_void 3465:{ *:[iPTR] })  =>  (S_WAIT_EVENT 2:{ *:[i16] })
     /*  813811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EVENT),
     /*  813814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /*  813817 */     GIR_RootConstrainSelectedInstOperands,
     /*  813818 */     // GIR_Coverage, 4804,
     /*  813818 */     GIR_EraseRootFromParent_Done,
     /*  813819 */   // Label 13061: @813819
     /*  813819 */   GIM_Reject,
     /*  813820 */ // Label 13052: @813820
     /*  813820 */ GIM_Try, /*On fail goto*//*Label 13062*/ GIMT_Encode4(815561),
     /*  813825 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     /*  813828 */   GIM_Try, /*On fail goto*//*Label 13063*/ GIMT_Encode4(813889), // Rule ID 27398 //
     /*  813833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  813836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  813841 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  813844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  813848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  813852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  813856 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  813860 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  813864 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  813866 */     // (intrinsic_void 3268:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  813866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  813869 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  813873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  813876 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  813879 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  813882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  813887 */     GIR_RootConstrainSelectedInstOperands,
     /*  813888 */     // GIR_Coverage, 27398,
     /*  813888 */     GIR_EraseRootFromParent_Done,
     /*  813889 */   // Label 13063: @813889
     /*  813889 */   GIM_Try, /*On fail goto*//*Label 13064*/ GIMT_Encode4(813950), // Rule ID 27399 //
     /*  813894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  813897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  813902 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  813905 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  813909 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  813913 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  813917 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  813921 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  813925 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  813927 */     // (intrinsic_void 3268:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  813927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  813930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  813934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  813937 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  813940 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  813943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  813948 */     GIR_RootConstrainSelectedInstOperands,
     /*  813949 */     // GIR_Coverage, 27399,
     /*  813949 */     GIR_EraseRootFromParent_Done,
     /*  813950 */   // Label 13064: @813950
     /*  813950 */   GIM_Try, /*On fail goto*//*Label 13065*/ GIMT_Encode4(814011), // Rule ID 27400 //
     /*  813955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  813958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  813963 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  813966 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  813970 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  813974 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  813978 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  813982 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  813986 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  813988 */     // (intrinsic_void 3268:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  813988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  813991 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  813995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  813998 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814001 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814004 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814009 */     GIR_RootConstrainSelectedInstOperands,
     /*  814010 */     // GIR_Coverage, 27400,
     /*  814010 */     GIR_EraseRootFromParent_Done,
     /*  814011 */   // Label 13065: @814011
     /*  814011 */   GIM_Try, /*On fail goto*//*Label 13066*/ GIMT_Encode4(814072), // Rule ID 27401 //
     /*  814016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  814019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  814024 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814027 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814031 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814035 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814039 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814043 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814047 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814049 */     // (intrinsic_void 3268:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  814052 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814059 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814062 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814070 */     GIR_RootConstrainSelectedInstOperands,
     /*  814071 */     // GIR_Coverage, 27401,
     /*  814071 */     GIR_EraseRootFromParent_Done,
     /*  814072 */   // Label 13066: @814072
     /*  814072 */   GIM_Try, /*On fail goto*//*Label 13067*/ GIMT_Encode4(814133), // Rule ID 27402 //
     /*  814077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  814080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  814085 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814096 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814100 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814104 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814108 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814110 */     // (intrinsic_void 3268:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  814113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814120 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814123 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814131 */     GIR_RootConstrainSelectedInstOperands,
     /*  814132 */     // GIR_Coverage, 27402,
     /*  814132 */     GIR_EraseRootFromParent_Done,
     /*  814133 */   // Label 13067: @814133
     /*  814133 */   GIM_Try, /*On fail goto*//*Label 13068*/ GIMT_Encode4(814194), // Rule ID 27409 //
     /*  814138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  814141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  814146 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814161 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814165 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814169 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814171 */     // (intrinsic_void 3679:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  814174 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814181 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814184 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814187 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814192 */     GIR_RootConstrainSelectedInstOperands,
     /*  814193 */     // GIR_Coverage, 27409,
     /*  814193 */     GIR_EraseRootFromParent_Done,
     /*  814194 */   // Label 13068: @814194
     /*  814194 */   GIM_Try, /*On fail goto*//*Label 13069*/ GIMT_Encode4(814255), // Rule ID 27410 //
     /*  814199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  814202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  814207 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814210 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814214 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814218 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814222 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814226 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814230 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814232 */     // (intrinsic_void 3679:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  814235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814242 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814245 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814253 */     GIR_RootConstrainSelectedInstOperands,
     /*  814254 */     // GIR_Coverage, 27410,
     /*  814254 */     GIR_EraseRootFromParent_Done,
     /*  814255 */   // Label 13069: @814255
     /*  814255 */   GIM_Try, /*On fail goto*//*Label 13070*/ GIMT_Encode4(814316), // Rule ID 27411 //
     /*  814260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  814263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  814268 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814279 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814287 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814291 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814293 */     // (intrinsic_void 3679:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  814296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814303 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814306 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814309 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814314 */     GIR_RootConstrainSelectedInstOperands,
     /*  814315 */     // GIR_Coverage, 27411,
     /*  814315 */     GIR_EraseRootFromParent_Done,
     /*  814316 */   // Label 13070: @814316
     /*  814316 */   GIM_Try, /*On fail goto*//*Label 13071*/ GIMT_Encode4(814377), // Rule ID 27412 //
     /*  814321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  814324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  814329 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814340 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814344 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814348 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814352 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814354 */     // (intrinsic_void 3679:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  814357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814364 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814367 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814375 */     GIR_RootConstrainSelectedInstOperands,
     /*  814376 */     // GIR_Coverage, 27412,
     /*  814376 */     GIR_EraseRootFromParent_Done,
     /*  814377 */   // Label 13071: @814377
     /*  814377 */   GIM_Try, /*On fail goto*//*Label 13072*/ GIMT_Encode4(814438), // Rule ID 27413 //
     /*  814382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  814385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  814390 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  814393 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  814397 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  814401 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
     /*  814405 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
     /*  814409 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  814413 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  814415 */     // (intrinsic_void 3679:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
     /*  814415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  814418 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
     /*  814422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  814425 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  814428 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  814431 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  814436 */     GIR_RootConstrainSelectedInstOperands,
     /*  814437 */     // GIR_Coverage, 27413,
     /*  814437 */     GIR_EraseRootFromParent_Done,
     /*  814438 */   // Label 13072: @814438
     /*  814438 */   GIM_Try, /*On fail goto*//*Label 13073*/ GIMT_Encode4(814458), // Rule ID 179 //
     /*  814443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_nop),
     /*  814448 */     // MIs[0] simm16
     /*  814448 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814451 */     // (intrinsic_void 3448:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_NOP (timm:{ *:[i16] }):$simm16)
     /*  814451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOP),
     /*  814454 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814456 */     GIR_RootConstrainSelectedInstOperands,
     /*  814457 */     // GIR_Coverage, 179,
     /*  814457 */     GIR_EraseRootFromParent_Done,
     /*  814458 */   // Label 13073: @814458
     /*  814458 */   GIM_Try, /*On fail goto*//*Label 13074*/ GIMT_Encode4(814481), // Rule ID 185 //
     /*  814463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX1250Plus),
     /*  814466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_waitcnt),
     /*  814471 */     // MIs[0] simm16
     /*  814471 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814474 */     // (intrinsic_void 3472:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_WAITCNT (timm:{ *:[i32] }):$simm16)
     /*  814474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAITCNT),
     /*  814477 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814479 */     GIR_RootConstrainSelectedInstOperands,
     /*  814480 */     // GIR_Coverage, 185,
     /*  814480 */     GIR_EraseRootFromParent_Done,
     /*  814481 */   // Label 13074: @814481
     /*  814481 */   GIM_Try, /*On fail goto*//*Label 13075*/ GIMT_Encode4(814501), // Rule ID 186 //
     /*  814486 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sethalt),
     /*  814491 */     // MIs[0] simm16
     /*  814491 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814494 */     // (intrinsic_void 3454:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_SETHALT (timm:{ *:[i32] }):$simm16)
     /*  814494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETHALT),
     /*  814497 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814499 */     GIR_RootConstrainSelectedInstOperands,
     /*  814500 */     // GIR_Coverage, 186,
     /*  814500 */     GIR_EraseRootFromParent_Done,
     /*  814501 */   // Label 13075: @814501
     /*  814501 */   GIM_Try, /*On fail goto*//*Label 13076*/ GIMT_Encode4(814521), // Rule ID 187 //
     /*  814506 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sleep),
     /*  814511 */     // MIs[0] simm16
     /*  814511 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814514 */     // (intrinsic_void 3458:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_SLEEP (timm:{ *:[i32] }):$simm16)
     /*  814514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SLEEP),
     /*  814517 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814519 */     GIR_RootConstrainSelectedInstOperands,
     /*  814520 */     // GIR_Coverage, 187,
     /*  814520 */     GIR_EraseRootFromParent_Done,
     /*  814521 */   // Label 13076: @814521
     /*  814521 */   GIM_Try, /*On fail goto*//*Label 13077*/ GIMT_Encode4(814541), // Rule ID 189 //
     /*  814526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setprio),
     /*  814531 */     // MIs[0] simm16
     /*  814531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814534 */     // (intrinsic_void 3455:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_SETPRIO (timm:{ *:[i16] }):$simm16)
     /*  814534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETPRIO),
     /*  814537 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814539 */     GIR_RootConstrainSelectedInstOperands,
     /*  814540 */     // GIR_Coverage, 189,
     /*  814540 */     GIR_EraseRootFromParent_Done,
     /*  814541 */   // Label 13077: @814541
     /*  814541 */   GIM_Try, /*On fail goto*//*Label 13078*/ GIMT_Encode4(814564), // Rule ID 190 //
     /*  814546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSetPrioIncWgInst),
     /*  814549 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setprio_inc_wg),
     /*  814554 */     // MIs[0] simm16
     /*  814554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814557 */     // (intrinsic_void 3456:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_SETPRIO_INC_WG (timm:{ *:[i16] }):$simm16)
     /*  814557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETPRIO_INC_WG),
     /*  814560 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814562 */     GIR_RootConstrainSelectedInstOperands,
     /*  814563 */     // GIR_Coverage, 190,
     /*  814563 */     GIR_EraseRootFromParent_Done,
     /*  814564 */   // Label 13078: @814564
     /*  814564 */   GIM_Try, /*On fail goto*//*Label 13079*/ GIMT_Encode4(814584), // Rule ID 194 //
     /*  814569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_incperflevel),
     /*  814574 */     // MIs[0] simm16
     /*  814574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814577 */     // (intrinsic_void 3444:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_INCPERFLEVEL (timm:{ *:[i32] }):$simm16)
     /*  814577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INCPERFLEVEL),
     /*  814580 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814582 */     GIR_RootConstrainSelectedInstOperands,
     /*  814583 */     // GIR_Coverage, 194,
     /*  814583 */     GIR_EraseRootFromParent_Done,
     /*  814584 */   // Label 13079: @814584
     /*  814584 */   GIM_Try, /*On fail goto*//*Label 13080*/ GIMT_Encode4(814604), // Rule ID 195 //
     /*  814589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_decperflevel),
     /*  814594 */     // MIs[0] simm16
     /*  814594 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814597 */     // (intrinsic_void 3438:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_DECPERFLEVEL (timm:{ *:[i32] }):$simm16)
     /*  814597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DECPERFLEVEL),
     /*  814600 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814602 */     GIR_RootConstrainSelectedInstOperands,
     /*  814603 */     // GIR_Coverage, 195,
     /*  814603 */     GIR_EraseRootFromParent_Done,
     /*  814604 */   // Label 13080: @814604
     /*  814604 */   GIM_Try, /*On fail goto*//*Label 13081*/ GIMT_Encode4(814627), // Rule ID 197 //
     /*  814609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  814612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_monitor_sleep),
     /*  814617 */     // MIs[0] simm16
     /*  814617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814620 */     // (intrinsic_void 3447:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_MONITOR_SLEEP (timm:{ *:[i16] }):$simm16)
     /*  814620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MONITOR_SLEEP),
     /*  814623 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814625 */     GIR_RootConstrainSelectedInstOperands,
     /*  814626 */     // GIR_Coverage, 197,
     /*  814626 */     GIR_EraseRootFromParent_Done,
     /*  814627 */   // Label 13081: @814627
     /*  814627 */   GIM_Try, /*On fail goto*//*Label 13082*/ GIMT_Encode4(814650), // Rule ID 199 //
     /*  814632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  814635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_ttracedata_imm),
     /*  814640 */     // MIs[0] simm16
     /*  814640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814643 */     // (intrinsic_void 3461:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_TTRACEDATA_IMM (timm:{ *:[i16] }):$simm16)
     /*  814643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_TTRACEDATA_IMM),
     /*  814646 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814648 */     GIR_RootConstrainSelectedInstOperands,
     /*  814649 */     // GIR_Coverage, 199,
     /*  814649 */     GIR_EraseRootFromParent_Done,
     /*  814650 */   // Label 13082: @814650
     /*  814650 */   GIM_Try, /*On fail goto*//*Label 13083*/ GIMT_Encode4(814673), // Rule ID 200 //
     /*  814655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  814658 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_loadcnt),
     /*  814663 */     // MIs[0] simm16
     /*  814663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814666 */     // (intrinsic_void 3468:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_LOADCNT (timm:{ *:[i16] }):$simm16)
     /*  814666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_LOADCNT),
     /*  814669 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814671 */     GIR_RootConstrainSelectedInstOperands,
     /*  814672 */     // GIR_Coverage, 200,
     /*  814672 */     GIR_EraseRootFromParent_Done,
     /*  814673 */   // Label 13083: @814673
     /*  814673 */   GIM_Try, /*On fail goto*//*Label 13084*/ GIMT_Encode4(814696), // Rule ID 201 //
     /*  814678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  814681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_storecnt),
     /*  814686 */     // MIs[0] simm16
     /*  814686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814689 */     // (intrinsic_void 3470:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_STORECNT (timm:{ *:[i16] }):$simm16)
     /*  814689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_STORECNT),
     /*  814692 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814694 */     GIR_RootConstrainSelectedInstOperands,
     /*  814695 */     // GIR_Coverage, 201,
     /*  814695 */     GIR_EraseRootFromParent_Done,
     /*  814696 */   // Label 13084: @814696
     /*  814696 */   GIM_Try, /*On fail goto*//*Label 13085*/ GIMT_Encode4(814719), // Rule ID 202 //
     /*  814701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasImageInsts_isGFX12Plus),
     /*  814704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_samplecnt),
     /*  814709 */     // MIs[0] simm16
     /*  814709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814712 */     // (intrinsic_void 3469:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_SAMPLECNT (timm:{ *:[i16] }):$simm16)
     /*  814712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_SAMPLECNT),
     /*  814715 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814717 */     GIR_RootConstrainSelectedInstOperands,
     /*  814718 */     // GIR_Coverage, 202,
     /*  814718 */     GIR_EraseRootFromParent_Done,
     /*  814719 */   // Label 13085: @814719
     /*  814719 */   GIM_Try, /*On fail goto*//*Label 13086*/ GIMT_Encode4(814742), // Rule ID 203 //
     /*  814724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasImageInsts_isGFX12Plus),
     /*  814727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_bvhcnt),
     /*  814732 */     // MIs[0] simm16
     /*  814732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814735 */     // (intrinsic_void 3463:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_BVHCNT (timm:{ *:[i16] }):$simm16)
     /*  814735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_BVHCNT),
     /*  814738 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814740 */     GIR_RootConstrainSelectedInstOperands,
     /*  814741 */     // GIR_Coverage, 203,
     /*  814741 */     GIR_EraseRootFromParent_Done,
     /*  814742 */   // Label 13086: @814742
     /*  814742 */   GIM_Try, /*On fail goto*//*Label 13087*/ GIMT_Encode4(814765), // Rule ID 204 //
     /*  814747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExportInsts_isGFX12Plus),
     /*  814750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_expcnt),
     /*  814755 */     // MIs[0] simm16
     /*  814755 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814758 */     // (intrinsic_void 3466:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_EXPCNT (timm:{ *:[i16] }):$simm16)
     /*  814758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EXPCNT),
     /*  814761 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814763 */     GIR_RootConstrainSelectedInstOperands,
     /*  814764 */     // GIR_Coverage, 204,
     /*  814764 */     GIR_EraseRootFromParent_Done,
     /*  814765 */   // Label 13087: @814765
     /*  814765 */   GIM_Try, /*On fail goto*//*Label 13088*/ GIMT_Encode4(814788), // Rule ID 205 //
     /*  814770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  814773 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_dscnt),
     /*  814778 */     // MIs[0] simm16
     /*  814778 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814781 */     // (intrinsic_void 3464:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_DSCNT (timm:{ *:[i16] }):$simm16)
     /*  814781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_DSCNT),
     /*  814784 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814786 */     GIR_RootConstrainSelectedInstOperands,
     /*  814787 */     // GIR_Coverage, 205,
     /*  814787 */     GIR_EraseRootFromParent_Done,
     /*  814788 */   // Label 13088: @814788
     /*  814788 */   GIM_Try, /*On fail goto*//*Label 13089*/ GIMT_Encode4(814811), // Rule ID 206 //
     /*  814793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  814796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_kmcnt),
     /*  814801 */     // MIs[0] simm16
     /*  814801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814804 */     // (intrinsic_void 3467:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_KMCNT (timm:{ *:[i16] }):$simm16)
     /*  814804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_KMCNT),
     /*  814807 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814809 */     GIR_RootConstrainSelectedInstOperands,
     /*  814810 */     // GIR_Coverage, 206,
     /*  814810 */     GIR_EraseRootFromParent_Done,
     /*  814811 */   // Label 13089: @814811
     /*  814811 */   GIM_Try, /*On fail goto*//*Label 13090*/ GIMT_Encode4(814841), // Rule ID 207 //
     /*  814816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  814819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_asynccnt),
     /*  814824 */     // MIs[0] simm16
     /*  814824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814827 */     // (intrinsic_void 3462:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_ASYNCCNT (timm:{ *:[i16] }):$simm16)
     /*  814827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_ASYNCCNT),
     /*  814830 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814832 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  814835 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  814839 */     GIR_RootConstrainSelectedInstOperands,
     /*  814840 */     // GIR_Coverage, 207,
     /*  814840 */     GIR_EraseRootFromParent_Done,
     /*  814841 */   // Label 13090: @814841
     /*  814841 */   GIM_Try, /*On fail goto*//*Label 13091*/ GIMT_Encode4(814871), // Rule ID 208 //
     /*  814846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  814849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_tensorcnt),
     /*  814854 */     // MIs[0] simm16
     /*  814854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  814857 */     // (intrinsic_void 3471:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_TENSORCNT (timm:{ *:[i16] }):$simm16)
     /*  814857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_TENSORCNT),
     /*  814860 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  814862 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::TENSORcnt*/0,
     /*  814865 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  814869 */     GIR_RootConstrainSelectedInstOperands,
     /*  814870 */     // GIR_Coverage, 208,
     /*  814870 */     GIR_EraseRootFromParent_Done,
     /*  814871 */   // Label 13091: @814871
     /*  814871 */   GIM_Try, /*On fail goto*//*Label 13092*/ GIMT_Encode4(814898), // Rule ID 4150 //
     /*  814876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemTimeInst),
     /*  814879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_memtime),
     /*  814884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  814887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  814891 */     // (intrinsic_w_chain:{ *:[i64] } 3446:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
     /*  814891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMTIME),
     /*  814894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  814896 */     GIR_RootConstrainSelectedInstOperands,
     /*  814897 */     // GIR_Coverage, 4150,
     /*  814897 */     GIR_EraseRootFromParent_Done,
     /*  814898 */   // Label 13092: @814898
     /*  814898 */   GIM_Try, /*On fail goto*//*Label 13093*/ GIMT_Encode4(814925), // Rule ID 4155 //
     /*  814903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemRealTime),
     /*  814906 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_memrealtime),
     /*  814911 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  814914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
     /*  814918 */     // (intrinsic_w_chain:{ *:[i64] } 3445:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
     /*  814918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMREALTIME),
     /*  814921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  814923 */     GIR_RootConstrainSelectedInstOperands,
     /*  814924 */     // GIR_Coverage, 4155,
     /*  814924 */     GIR_EraseRootFromParent_Done,
     /*  814925 */   // Label 13093: @814925
     /*  814925 */   GIM_Try, /*On fail goto*//*Label 13094*/ GIMT_Encode4(814952), // Rule ID 4156 //
     /*  814930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGetWaveIdInst),
     /*  814933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_get_waveid_in_workgroup),
     /*  814938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  814941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
     /*  814945 */     // (intrinsic_w_chain:{ *:[i32] } 3441:{ *:[iPTR] })  =>  (S_GET_WAVEID_IN_WORKGROUP:{ *:[i32] })
     /*  814945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_GET_WAVEID_IN_WORKGROUP),
     /*  814948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  814950 */     GIR_RootConstrainSelectedInstOperands,
     /*  814951 */     // GIR_Coverage, 4156,
     /*  814951 */     GIR_EraseRootFromParent_Done,
     /*  814952 */   // Label 13094: @814952
     /*  814952 */   GIM_Try, /*On fail goto*//*Label 13095*/ GIMT_Encode4(814983), // Rule ID 4260 //
     /*  814957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  814960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask),
     /*  814965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  814968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  814972 */     // (intrinsic_w_chain:{ *:[i1] } 3273:{ *:[iPTR] })  =>  (SI_LIVE_MASK:{ *:[i1] })
     /*  814972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK),
     /*  814975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  814977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  814981 */     GIR_RootConstrainSelectedInstOperands,
     /*  814982 */     // GIR_Coverage, 4260,
     /*  814982 */     GIR_EraseRootFromParent_Done,
     /*  814983 */   // Label 13095: @814983
     /*  814983 */   GIM_Try, /*On fail goto*//*Label 13096*/ GIMT_Encode4(815014), // Rule ID 4261 //
     /*  814988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  814991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask),
     /*  814996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  814999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  815003 */     // (intrinsic_w_chain:{ *:[i1] } 3273:{ *:[iPTR] })  =>  (SI_LIVE_MASK:{ *:[i1] })
     /*  815003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK),
     /*  815006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  815008 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815012 */     GIR_RootConstrainSelectedInstOperands,
     /*  815013 */     // GIR_Coverage, 4261,
     /*  815013 */     GIR_EraseRootFromParent_Done,
     /*  815014 */   // Label 13096: @815014
     /*  815014 */   GIM_Try, /*On fail goto*//*Label 13097*/ GIMT_Encode4(815045), // Rule ID 4262 //
     /*  815019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  815022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask),
     /*  815027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  815030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  815034 */     // (intrinsic_w_chain:{ *:[i1] } 3273:{ *:[iPTR] })  =>  (SI_LIVE_MASK:{ *:[i1] })
     /*  815034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK),
     /*  815037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  815039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815043 */     GIR_RootConstrainSelectedInstOperands,
     /*  815044 */     // GIR_Coverage, 4262,
     /*  815044 */     GIR_EraseRootFromParent_Done,
     /*  815045 */   // Label 13097: @815045
     /*  815045 */   GIM_Try, /*On fail goto*//*Label 13098*/ GIMT_Encode4(815076), // Rule ID 4263 //
     /*  815050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  815053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask),
     /*  815058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  815061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  815065 */     // (intrinsic_w_chain:{ *:[i1] } 3273:{ *:[iPTR] })  =>  (SI_LIVE_MASK:{ *:[i1] })
     /*  815065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK),
     /*  815068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  815070 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815074 */     GIR_RootConstrainSelectedInstOperands,
     /*  815075 */     // GIR_Coverage, 4263,
     /*  815075 */     GIR_EraseRootFromParent_Done,
     /*  815076 */   // Label 13098: @815076
     /*  815076 */   GIM_Try, /*On fail goto*//*Label 13099*/ GIMT_Encode4(815107), // Rule ID 4264 //
     /*  815081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  815084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask),
     /*  815089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  815092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  815096 */     // (intrinsic_w_chain:{ *:[i1] } 3273:{ *:[iPTR] })  =>  (SI_LIVE_MASK:{ *:[i1] })
     /*  815096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK),
     /*  815099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  815101 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815105 */     GIR_RootConstrainSelectedInstOperands,
     /*  815106 */     // GIR_Coverage, 4264,
     /*  815106 */     GIR_EraseRootFromParent_Done,
     /*  815107 */   // Label 13099: @815107
     /*  815107 */   GIM_Try, /*On fail goto*//*Label 13100*/ GIMT_Encode4(815140), // Rule ID 4807 //
     /*  815112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9GFX10),
     /*  815115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_pops_exiting_wave_id),
     /*  815120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  815123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  815127 */     // (intrinsic_w_chain:{ *:[i32] } 3357:{ *:[iPTR] })  =>  (S_MOV_B32_sideeffects:{ *:[i32] } SRC_POPS_EXITING_WAVE_ID:{ *:[i32] })
     /*  815127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32_sideeffects),
     /*  815130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  815132 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SRC_POPS_EXITING_WAVE_ID), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  815138 */     GIR_RootConstrainSelectedInstOperands,
     /*  815139 */     // GIR_Coverage, 4807,
     /*  815139 */     GIR_EraseRootFromParent_Done,
     /*  815140 */   // Label 13100: @815140
     /*  815140 */   GIM_Try, /*On fail goto*//*Label 13101*/ GIMT_Encode4(815164), // Rule ID 188 //
     /*  815145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sleep_var),
     /*  815150 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  815153 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  815157 */     // (intrinsic_void 3459:{ *:[iPTR] }, SSrc_b32:{ *:[i32] }:$src0)  =>  (S_SLEEP_VAR SSrc_b32:{ *:[i32] }:$src0)
     /*  815157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SLEEP_VAR),
     /*  815160 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  815162 */     GIR_RootConstrainSelectedInstOperands,
     /*  815163 */     // GIR_Coverage, 188,
     /*  815163 */     GIR_EraseRootFromParent_Done,
     /*  815164 */   // Label 13101: @815164
     /*  815164 */   GIM_Try, /*On fail goto*//*Label 13102*/ GIMT_Encode4(815200), // Rule ID 196 //
     /*  815169 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_ttracedata),
     /*  815174 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  815177 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  815181 */     // (intrinsic_void 3460:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (S_TTRACEDATA)
     /*  815181 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  815185 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  815191 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // M0
     /*  815195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_TTRACEDATA),
     /*  815198 */     GIR_RootConstrainSelectedInstOperands,
     /*  815199 */     // GIR_Coverage, 196,
     /*  815199 */     GIR_EraseRootFromParent_Done,
     /*  815200 */   // Label 13102: @815200
     /*  815200 */   GIM_Try, /*On fail goto*//*Label 13103*/ GIMT_Encode4(815236), // Rule ID 27393 //
     /*  815205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  815208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  815213 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815216 */     // (intrinsic_void 3268:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  815219 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815224 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815227 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815234 */     GIR_RootConstrainSelectedInstOperands,
     /*  815235 */     // GIR_Coverage, 27393,
     /*  815235 */     GIR_EraseRootFromParent_Done,
     /*  815236 */   // Label 13103: @815236
     /*  815236 */   GIM_Try, /*On fail goto*//*Label 13104*/ GIMT_Encode4(815272), // Rule ID 27394 //
     /*  815241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  815244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  815249 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815252 */     // (intrinsic_void 3268:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  815255 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815260 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815263 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815266 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815270 */     GIR_RootConstrainSelectedInstOperands,
     /*  815271 */     // GIR_Coverage, 27394,
     /*  815271 */     GIR_EraseRootFromParent_Done,
     /*  815272 */   // Label 13104: @815272
     /*  815272 */   GIM_Try, /*On fail goto*//*Label 13105*/ GIMT_Encode4(815308), // Rule ID 27395 //
     /*  815277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  815280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  815285 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815288 */     // (intrinsic_void 3268:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  815291 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815296 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815299 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815302 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815306 */     GIR_RootConstrainSelectedInstOperands,
     /*  815307 */     // GIR_Coverage, 27395,
     /*  815307 */     GIR_EraseRootFromParent_Done,
     /*  815308 */   // Label 13105: @815308
     /*  815308 */   GIM_Try, /*On fail goto*//*Label 13106*/ GIMT_Encode4(815344), // Rule ID 27396 //
     /*  815313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  815316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  815321 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815324 */     // (intrinsic_void 3268:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  815327 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815332 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815335 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815342 */     GIR_RootConstrainSelectedInstOperands,
     /*  815343 */     // GIR_Coverage, 27396,
     /*  815343 */     GIR_EraseRootFromParent_Done,
     /*  815344 */   // Label 13106: @815344
     /*  815344 */   GIM_Try, /*On fail goto*//*Label 13107*/ GIMT_Encode4(815380), // Rule ID 27397 //
     /*  815349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  815352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
     /*  815357 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815360 */     // (intrinsic_void 3268:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
     /*  815363 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815368 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815371 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815378 */     GIR_RootConstrainSelectedInstOperands,
     /*  815379 */     // GIR_Coverage, 27397,
     /*  815379 */     GIR_EraseRootFromParent_Done,
     /*  815380 */   // Label 13107: @815380
     /*  815380 */   GIM_Try, /*On fail goto*//*Label 13108*/ GIMT_Encode4(815416), // Rule ID 27404 //
     /*  815385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  815388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  815393 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815396 */     // (intrinsic_void 3679:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  815399 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815404 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815407 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815414 */     GIR_RootConstrainSelectedInstOperands,
     /*  815415 */     // GIR_Coverage, 27404,
     /*  815415 */     GIR_EraseRootFromParent_Done,
     /*  815416 */   // Label 13108: @815416
     /*  815416 */   GIM_Try, /*On fail goto*//*Label 13109*/ GIMT_Encode4(815452), // Rule ID 27405 //
     /*  815421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  815424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  815429 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815432 */     // (intrinsic_void 3679:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  815435 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815440 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815443 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815446 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815450 */     GIR_RootConstrainSelectedInstOperands,
     /*  815451 */     // GIR_Coverage, 27405,
     /*  815451 */     GIR_EraseRootFromParent_Done,
     /*  815452 */   // Label 13109: @815452
     /*  815452 */   GIM_Try, /*On fail goto*//*Label 13110*/ GIMT_Encode4(815488), // Rule ID 27406 //
     /*  815457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  815460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  815465 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815468 */     // (intrinsic_void 3679:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  815471 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815473 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815476 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815479 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815482 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815486 */     GIR_RootConstrainSelectedInstOperands,
     /*  815487 */     // GIR_Coverage, 27406,
     /*  815487 */     GIR_EraseRootFromParent_Done,
     /*  815488 */   // Label 13110: @815488
     /*  815488 */   GIM_Try, /*On fail goto*//*Label 13111*/ GIMT_Encode4(815524), // Rule ID 27407 //
     /*  815493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  815496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  815501 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815504 */     // (intrinsic_void 3679:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  815507 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815512 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815515 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815522 */     GIR_RootConstrainSelectedInstOperands,
     /*  815523 */     // GIR_Coverage, 27407,
     /*  815523 */     GIR_EraseRootFromParent_Done,
     /*  815524 */   // Label 13111: @815524
     /*  815524 */   GIM_Try, /*On fail goto*//*Label 13112*/ GIMT_Encode4(815560), // Rule ID 27408 //
     /*  815529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  815532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
     /*  815537 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  815540 */     // (intrinsic_void 3679:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
     /*  815540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
     /*  815543 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  815545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815548 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  815551 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
     /*  815554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815558 */     GIR_RootConstrainSelectedInstOperands,
     /*  815559 */     // GIR_Coverage, 27408,
     /*  815559 */     GIR_EraseRootFromParent_Done,
     /*  815560 */   // Label 13112: @815560
     /*  815560 */   GIM_Reject,
     /*  815561 */ // Label 13062: @815561
     /*  815561 */ GIM_Try, /*On fail goto*//*Label 13113*/ GIMT_Encode4(816713),
     /*  815566 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*  815569 */   GIM_Try, /*On fail goto*//*Label 13114*/ GIMT_Encode4(815638), // Rule ID 9290 //
     /*  815574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  815577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_prefetch_data),
     /*  815582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  815585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  815589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  815593 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  815597 */     // MIs[1] Operand 1
     /*  815597 */     // No operand predicates
     /*  815597 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  815599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  815606 */     // (intrinsic_void 3449:{ *:[iPTR] }, (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (imm:{ *:[i32] }):$len)  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$len))
     /*  815606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  815609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  815614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  815619 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  815625 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // len
     /*  815631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  815636 */     GIR_RootConstrainSelectedInstOperands,
     /*  815637 */     // GIR_Coverage, 9290,
     /*  815637 */     GIR_EraseRootFromParent_Done,
     /*  815638 */   // Label 13114: @815638
     /*  815638 */   GIM_Try, /*On fail goto*//*Label 13115*/ GIMT_Encode4(815693), // Rule ID 9288 //
     /*  815643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  815646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_prefetch_data),
     /*  815651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  815654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  815658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  815662 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
     /*  815669 */     // (intrinsic_void 3449:{ *:[iPTR] }, (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), SReg_32:{ *:[i32] }:$len)  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$len, 0:{ *:[i8] })
     /*  815669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  815672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
     /*  815677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  815682 */     GIR_RootToRootCopy, /*OpIdx*/2, // len
     /*  815684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815691 */     GIR_RootConstrainSelectedInstOperands,
     /*  815692 */     // GIR_Coverage, 9288,
     /*  815692 */     GIR_EraseRootFromParent_Done,
     /*  815693 */   // Label 13115: @815693
     /*  815693 */   GIM_Try, /*On fail goto*//*Label 13116*/ GIMT_Encode4(815746), // Rule ID 15008 //
     /*  815698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts),
     /*  815701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_flat_prefetch),
     /*  815706 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  815710 */     // MIs[0] cpol
     /*  815710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  815713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  815720 */     // (intrinsic_void 2454:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_PREFETCH_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  815720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8_SADDR),
     /*  815723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  815728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  815733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  815738 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  815740 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815744 */     GIR_RootConstrainSelectedInstOperands,
     /*  815745 */     // GIR_Coverage, 15008,
     /*  815745 */     GIR_EraseRootFromParent_Done,
     /*  815746 */   // Label 13116: @815746
     /*  815746 */   GIM_Try, /*On fail goto*//*Label 13117*/ GIMT_Encode4(815799), // Rule ID 15032 //
     /*  815751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts),
     /*  815754 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_prefetch),
     /*  815759 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  815763 */     // MIs[0] cpol
     /*  815763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  815766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  815773 */     // (intrinsic_void 2477:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_PREFETCH_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  815773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8_SADDR),
     /*  815776 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  815781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  815786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  815791 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  815793 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  815797 */     GIR_RootConstrainSelectedInstOperands,
     /*  815798 */     // GIR_Coverage, 15032,
     /*  815798 */     GIR_EraseRootFromParent_Done,
     /*  815799 */   // Label 13117: @815799
     /*  815799 */   GIM_Try, /*On fail goto*//*Label 13118*/ GIMT_Encode4(815836), // Rule ID 120 //
     /*  815804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setreg),
     /*  815809 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  815812 */     // MIs[0] simm16
     /*  815812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  815815 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SIMM16bit),
     /*  815820 */     // (intrinsic_void 3457:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_SIMM16bit>><<X:as_i16timm>>:$simm16, i32:{ *:[i32] }:$sdst)  =>  (S_SETREG_B32 i32:{ *:[i32] }:$sdst, (as_i16timm:{ *:[i32] } (timm:{ *:[i32] }):$simm16))
     /*  815820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETREG_B32),
     /*  815823 */     GIR_RootToRootCopy, /*OpIdx*/2, // sdst
     /*  815825 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // simm16
     /*  815831 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::MODE*/0,
     /*  815834 */     GIR_RootConstrainSelectedInstOperands,
     /*  815835 */     // GIR_Coverage, 120,
     /*  815835 */     GIR_EraseRootFromParent_Done,
     /*  815836 */   // Label 13118: @815836
     /*  815836 */   GIM_Try, /*On fail goto*//*Label 13119*/ GIMT_Encode4(815868), // Rule ID 25 //
     /*  815841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*  815844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg_rtn),
     /*  815849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  815852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  815856 */     // MIs[0] src0
     /*  815856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  815859 */     // (intrinsic_w_chain:{ *:[i32] } 3452:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0)  =>  (S_SENDMSG_RTN_B32:{ *:[i32] } (timm:{ *:[i32] }):$src0)
     /*  815859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B32),
     /*  815862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  815864 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  815866 */     GIR_RootConstrainSelectedInstOperands,
     /*  815867 */     // GIR_Coverage, 25,
     /*  815867 */     GIR_EraseRootFromParent_Done,
     /*  815868 */   // Label 13119: @815868
     /*  815868 */   GIM_Try, /*On fail goto*//*Label 13120*/ GIMT_Encode4(815900), // Rule ID 26 //
     /*  815873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
     /*  815876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg_rtn),
     /*  815881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  815884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  815888 */     // MIs[0] src0
     /*  815888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  815891 */     // (intrinsic_w_chain:{ *:[i64] } 3452:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0)  =>  (S_SENDMSG_RTN_B64:{ *:[i64] } (timm:{ *:[i32] }):$src0)
     /*  815891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B64),
     /*  815894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  815896 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  815898 */     GIR_RootConstrainSelectedInstOperands,
     /*  815899 */     // GIR_Coverage, 26,
     /*  815899 */     GIR_EraseRootFromParent_Done,
     /*  815900 */   // Label 13120: @815900
     /*  815900 */   GIM_Try, /*On fail goto*//*Label 13121*/ GIMT_Encode4(815929), // Rule ID 119 //
     /*  815905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_getreg),
     /*  815910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  815913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  815917 */     // MIs[0] simm16
     /*  815917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  815920 */     // (intrinsic_w_chain:{ *:[i32] } 3443:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_GETREG_B32:{ *:[i32] } (timm:{ *:[i32] }):$simm16)
     /*  815920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32),
     /*  815923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  815925 */     GIR_RootToRootCopy, /*OpIdx*/2, // simm16
     /*  815927 */     GIR_RootConstrainSelectedInstOperands,
     /*  815928 */     // GIR_Coverage, 119,
     /*  815928 */     GIR_EraseRootFromParent_Done,
     /*  815929 */   // Label 13121: @815929
     /*  815929 */   GIM_Try, /*On fail goto*//*Label 13122*/ GIMT_Encode4(815990), // Rule ID 9291 //
     /*  815934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  815937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_prefetch_data),
     /*  815942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  815945 */     // MIs[0] sbase
     /*  815945 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  815949 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  815953 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  815957 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  815961 */     // MIs[1] Operand 1
     /*  815961 */     // No operand predicates
     /*  815961 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  815963 */     // (intrinsic_void 3449:{ *:[iPTR] }, SReg_64:{ *:[i64] }:$sbase, (imm:{ *:[i32] }):$len)  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$len))
     /*  815963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  815966 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  815968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  815971 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  815977 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // len
     /*  815983 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  815988 */     GIR_RootConstrainSelectedInstOperands,
     /*  815989 */     // GIR_Coverage, 9291,
     /*  815989 */     GIR_EraseRootFromParent_Done,
     /*  815990 */   // Label 13122: @815990
     /*  815990 */   GIM_Try, /*On fail goto*//*Label 13123*/ GIMT_Encode4(816031), // Rule ID 192 //
     /*  815995 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg),
     /*  816000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  816003 */     // MIs[0] simm16
     /*  816003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  816006 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  816010 */     // (intrinsic_void 3451:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16, M0:{ *:[i32] })  =>  (S_SENDMSG (timm:{ *:[i32] }):$simm16)
     /*  816010 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  816014 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  816020 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
     /*  816024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG),
     /*  816027 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  816029 */     GIR_RootConstrainSelectedInstOperands,
     /*  816030 */     // GIR_Coverage, 192,
     /*  816030 */     GIR_EraseRootFromParent_Done,
     /*  816031 */   // Label 13123: @816031
     /*  816031 */   GIM_Try, /*On fail goto*//*Label 13124*/ GIMT_Encode4(816072), // Rule ID 193 //
     /*  816036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsghalt),
     /*  816041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  816044 */     // MIs[0] simm16
     /*  816044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  816047 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  816051 */     // (intrinsic_void 3453:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16, M0:{ *:[i32] })  =>  (S_SENDMSGHALT (timm:{ *:[i32] }):$simm16)
     /*  816051 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  816055 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  816061 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
     /*  816065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSGHALT),
     /*  816068 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  816070 */     GIR_RootConstrainSelectedInstOperands,
     /*  816071 */     // GIR_Coverage, 193,
     /*  816071 */     GIR_EraseRootFromParent_Done,
     /*  816072 */   // Label 13124: @816072
     /*  816072 */   GIM_Try, /*On fail goto*//*Label 13125*/ GIMT_Encode4(816127), // Rule ID 27293 //
     /*  816077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  816080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_direct_load),
     /*  816085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  816091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  816095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  816099 */     // (intrinsic_w_chain:{ *:[f32] } 3269:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (LDS_DIRECT_LOAD:{ *:[f32] } 0:{ *:[i32] })
     /*  816099 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  816103 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  816109 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
     /*  816113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::LDS_DIRECT_LOAD),
     /*  816116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  816118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  816121 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816125 */     GIR_RootConstrainSelectedInstOperands,
     /*  816126 */     // GIR_Coverage, 27293,
     /*  816126 */     GIR_EraseRootFromParent_Done,
     /*  816127 */   // Label 13125: @816127
     /*  816127 */   GIM_Try, /*On fail goto*//*Label 13126*/ GIMT_Encode4(816185), // Rule ID 27295 //
     /*  816132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50),
     /*  816135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_direct_load),
     /*  816140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  816146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  816150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  816154 */     // (intrinsic_w_chain:{ *:[f32] } 3269:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (DS_DIRECT_LOAD:{ *:[f32] } 0:{ *:[i32] }, 1:{ *:[i32] })
     /*  816154 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  816158 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  816164 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
     /*  816168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DIRECT_LOAD),
     /*  816171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  816173 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  816176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  816179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816183 */     GIR_RootConstrainSelectedInstOperands,
     /*  816184 */     // GIR_Coverage, 27295,
     /*  816184 */     GIR_EraseRootFromParent_Done,
     /*  816185 */   // Label 13126: @816185
     /*  816185 */   GIM_Try, /*On fail goto*//*Label 13127*/ GIMT_Encode4(816232), // Rule ID 9289 //
     /*  816190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  816193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_prefetch_data),
     /*  816198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  816201 */     // MIs[0] sbase
     /*  816201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  816205 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  816209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  816213 */     // (intrinsic_void 3449:{ *:[iPTR] }, SReg_64:{ *:[i64] }:$sbase, SReg_32:{ *:[i32] }:$len)  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, ?:{ *:[i32] }:$len, 0:{ *:[i8] })
     /*  816213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
     /*  816216 */     GIR_RootToRootCopy, /*OpIdx*/1, // sbase
     /*  816218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  816221 */     GIR_RootToRootCopy, /*OpIdx*/2, // len
     /*  816223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  816226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816230 */     GIR_RootConstrainSelectedInstOperands,
     /*  816231 */     // GIR_Coverage, 9289,
     /*  816231 */     GIR_EraseRootFromParent_Done,
     /*  816232 */   // Label 13127: @816232
     /*  816232 */   GIM_Try, /*On fail goto*//*Label 13128*/ GIMT_Encode4(816280), // Rule ID 15003 //
     /*  816237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode0),
     /*  816240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_flat_prefetch),
     /*  816245 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816249 */     // MIs[0] cpol
     /*  816249 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816259 */     // (intrinsic_void 2454:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  816262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816272 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816278 */     GIR_RootConstrainSelectedInstOperands,
     /*  816279 */     // GIR_Coverage, 15003,
     /*  816279 */     GIR_EraseRootFromParent_Done,
     /*  816280 */   // Label 13128: @816280
     /*  816280 */   GIM_Try, /*On fail goto*//*Label 13129*/ GIMT_Encode4(816328), // Rule ID 15004 //
     /*  816285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode1),
     /*  816288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_flat_prefetch),
     /*  816293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816297 */     // MIs[0] cpol
     /*  816297 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816300 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816307 */     // (intrinsic_void 2454:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  816310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816320 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816326 */     GIR_RootConstrainSelectedInstOperands,
     /*  816327 */     // GIR_Coverage, 15004,
     /*  816327 */     GIR_EraseRootFromParent_Done,
     /*  816328 */   // Label 13129: @816328
     /*  816328 */   GIM_Try, /*On fail goto*//*Label 13130*/ GIMT_Encode4(816376), // Rule ID 15005 //
     /*  816333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode2),
     /*  816336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_flat_prefetch),
     /*  816341 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816345 */     // MIs[0] cpol
     /*  816345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816355 */     // (intrinsic_void 2454:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  816358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816368 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816374 */     GIR_RootConstrainSelectedInstOperands,
     /*  816375 */     // GIR_Coverage, 15005,
     /*  816375 */     GIR_EraseRootFromParent_Done,
     /*  816376 */   // Label 13130: @816376
     /*  816376 */   GIM_Try, /*On fail goto*//*Label 13131*/ GIMT_Encode4(816424), // Rule ID 15006 //
     /*  816381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode3),
     /*  816384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_flat_prefetch),
     /*  816389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816393 */     // MIs[0] cpol
     /*  816393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816396 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816403 */     // (intrinsic_void 2454:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  816406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816416 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816422 */     GIR_RootConstrainSelectedInstOperands,
     /*  816423 */     // GIR_Coverage, 15006,
     /*  816423 */     GIR_EraseRootFromParent_Done,
     /*  816424 */   // Label 13131: @816424
     /*  816424 */   GIM_Try, /*On fail goto*//*Label 13132*/ GIMT_Encode4(816472), // Rule ID 15007 //
     /*  816429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode4),
     /*  816432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_flat_prefetch),
     /*  816437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816441 */     // MIs[0] cpol
     /*  816441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816451 */     // (intrinsic_void 2454:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_PREFETCH_B8),
     /*  816454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816464 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816466 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816470 */     GIR_RootConstrainSelectedInstOperands,
     /*  816471 */     // GIR_Coverage, 15007,
     /*  816471 */     GIR_EraseRootFromParent_Done,
     /*  816472 */   // Label 13132: @816472
     /*  816472 */   GIM_Try, /*On fail goto*//*Label 13133*/ GIMT_Encode4(816520), // Rule ID 15027 //
     /*  816477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode0),
     /*  816480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_prefetch),
     /*  816485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816489 */     // MIs[0] cpol
     /*  816489 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816499 */     // (intrinsic_void 2477:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  816502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816512 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816518 */     GIR_RootConstrainSelectedInstOperands,
     /*  816519 */     // GIR_Coverage, 15027,
     /*  816519 */     GIR_EraseRootFromParent_Done,
     /*  816520 */   // Label 13133: @816520
     /*  816520 */   GIM_Try, /*On fail goto*//*Label 13134*/ GIMT_Encode4(816568), // Rule ID 15028 //
     /*  816525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode1),
     /*  816528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_prefetch),
     /*  816533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816537 */     // MIs[0] cpol
     /*  816537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816547 */     // (intrinsic_void 2477:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  816550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816560 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816566 */     GIR_RootConstrainSelectedInstOperands,
     /*  816567 */     // GIR_Coverage, 15028,
     /*  816567 */     GIR_EraseRootFromParent_Done,
     /*  816568 */   // Label 13134: @816568
     /*  816568 */   GIM_Try, /*On fail goto*//*Label 13135*/ GIMT_Encode4(816616), // Rule ID 15029 //
     /*  816573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode2),
     /*  816576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_prefetch),
     /*  816581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816585 */     // MIs[0] cpol
     /*  816585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816588 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816595 */     // (intrinsic_void 2477:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  816598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816608 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816614 */     GIR_RootConstrainSelectedInstOperands,
     /*  816615 */     // GIR_Coverage, 15029,
     /*  816615 */     GIR_EraseRootFromParent_Done,
     /*  816616 */   // Label 13135: @816616
     /*  816616 */   GIM_Try, /*On fail goto*//*Label 13136*/ GIMT_Encode4(816664), // Rule ID 15030 //
     /*  816621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode3),
     /*  816624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_prefetch),
     /*  816629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816633 */     // MIs[0] cpol
     /*  816633 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816643 */     // (intrinsic_void 2477:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  816646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816656 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816662 */     GIR_RootConstrainSelectedInstOperands,
     /*  816663 */     // GIR_Coverage, 15030,
     /*  816663 */     GIR_EraseRootFromParent_Done,
     /*  816664 */   // Label 13136: @816664
     /*  816664 */   GIM_Try, /*On fail goto*//*Label 13137*/ GIMT_Encode4(816712), // Rule ID 15031 //
     /*  816669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVmemPrefInsts_HwMode4),
     /*  816672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_prefetch),
     /*  816677 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  816681 */     // MIs[0] cpol
     /*  816681 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  816684 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  816691 */     // (intrinsic_void 2477:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_PREFETCH_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_PREFETCH_B8),
     /*  816694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  816699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  816704 */     GIR_RootToRootCopy, /*OpIdx*/2, // cpol
     /*  816706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816710 */     GIR_RootConstrainSelectedInstOperands,
     /*  816711 */     // GIR_Coverage, 15031,
     /*  816711 */     GIR_EraseRootFromParent_Done,
     /*  816712 */   // Label 13137: @816712
     /*  816712 */   GIM_Reject,
     /*  816713 */ // Label 13113: @816713
     /*  816713 */ GIM_Try, /*On fail goto*//*Label 13138*/ GIMT_Encode4(822625),
     /*  816718 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /*  816721 */   GIM_Try, /*On fail goto*//*Label 13139*/ GIMT_Encode4(816784), // Rule ID 13632 //
     /*  816726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  816729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  816734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816737 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  816740 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  816742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  816746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  816753 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  816756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  816761 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  816763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  816768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  816773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  816778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816782 */     GIR_RootConstrainSelectedInstOperands,
     /*  816783 */     // GIR_Coverage, 13632,
     /*  816783 */     GIR_EraseRootFromParent_Done,
     /*  816784 */   // Label 13139: @816784
     /*  816784 */   GIM_Try, /*On fail goto*//*Label 13140*/ GIMT_Encode4(816847), // Rule ID 13633 //
     /*  816789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  816792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  816797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816800 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  816803 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  816805 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  816809 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  816816 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  816819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  816824 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  816826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  816831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  816836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  816841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816845 */     GIR_RootConstrainSelectedInstOperands,
     /*  816846 */     // GIR_Coverage, 13633,
     /*  816846 */     GIR_EraseRootFromParent_Done,
     /*  816847 */   // Label 13140: @816847
     /*  816847 */   GIM_Try, /*On fail goto*//*Label 13141*/ GIMT_Encode4(816910), // Rule ID 13634 //
     /*  816852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  816855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  816860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  816866 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  816868 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  816872 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  816879 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  816882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  816887 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  816889 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  816894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  816899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  816904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816908 */     GIR_RootConstrainSelectedInstOperands,
     /*  816909 */     // GIR_Coverage, 13634,
     /*  816909 */     GIR_EraseRootFromParent_Done,
     /*  816910 */   // Label 13141: @816910
     /*  816910 */   GIM_Try, /*On fail goto*//*Label 13142*/ GIMT_Encode4(816973), // Rule ID 13635 //
     /*  816915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  816918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  816923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  816929 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  816931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  816935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  816942 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  816942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  816945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  816950 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  816952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  816957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  816962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  816967 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  816971 */     GIR_RootConstrainSelectedInstOperands,
     /*  816972 */     // GIR_Coverage, 13635,
     /*  816972 */     GIR_EraseRootFromParent_Done,
     /*  816973 */   // Label 13142: @816973
     /*  816973 */   GIM_Try, /*On fail goto*//*Label 13143*/ GIMT_Encode4(817036), // Rule ID 13636 //
     /*  816978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  816981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  816986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  816989 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  816992 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  816994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  816998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  817005 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
     /*  817008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817013 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817034 */     GIR_RootConstrainSelectedInstOperands,
     /*  817035 */     // GIR_Coverage, 13636,
     /*  817035 */     GIR_EraseRootFromParent_Done,
     /*  817036 */   // Label 13143: @817036
     /*  817036 */   GIM_Try, /*On fail goto*//*Label 13144*/ GIMT_Encode4(817099), // Rule ID 13648 //
     /*  817041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  817044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  817049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817055 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817057 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  817068 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  817071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817076 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817093 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817097 */     GIR_RootConstrainSelectedInstOperands,
     /*  817098 */     // GIR_Coverage, 13648,
     /*  817098 */     GIR_EraseRootFromParent_Done,
     /*  817099 */   // Label 13144: @817099
     /*  817099 */   GIM_Try, /*On fail goto*//*Label 13145*/ GIMT_Encode4(817162), // Rule ID 13649 //
     /*  817104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  817107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  817112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817118 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817124 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  817131 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  817134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817139 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817160 */     GIR_RootConstrainSelectedInstOperands,
     /*  817161 */     // GIR_Coverage, 13649,
     /*  817161 */     GIR_EraseRootFromParent_Done,
     /*  817162 */   // Label 13145: @817162
     /*  817162 */   GIM_Try, /*On fail goto*//*Label 13146*/ GIMT_Encode4(817225), // Rule ID 13650 //
     /*  817167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  817170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  817175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817181 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  817194 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  817197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817202 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817219 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817223 */     GIR_RootConstrainSelectedInstOperands,
     /*  817224 */     // GIR_Coverage, 13650,
     /*  817224 */     GIR_EraseRootFromParent_Done,
     /*  817225 */   // Label 13146: @817225
     /*  817225 */   GIM_Try, /*On fail goto*//*Label 13147*/ GIMT_Encode4(817288), // Rule ID 13651 //
     /*  817230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  817233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  817238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817244 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  817257 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  817260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817265 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817282 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817286 */     GIR_RootConstrainSelectedInstOperands,
     /*  817287 */     // GIR_Coverage, 13651,
     /*  817287 */     GIR_EraseRootFromParent_Done,
     /*  817288 */   // Label 13147: @817288
     /*  817288 */   GIM_Try, /*On fail goto*//*Label 13148*/ GIMT_Encode4(817351), // Rule ID 13652 //
     /*  817293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  817296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  817301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817307 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817309 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  817320 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
     /*  817323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817328 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817349 */     GIR_RootConstrainSelectedInstOperands,
     /*  817350 */     // GIR_Coverage, 13652,
     /*  817350 */     GIR_EraseRootFromParent_Done,
     /*  817351 */   // Label 13148: @817351
     /*  817351 */   GIM_Try, /*On fail goto*//*Label 13149*/ GIMT_Encode4(817418), // Rule ID 13377 //
     /*  817356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode0),
     /*  817359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  817364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  817367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  817370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  817374 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817378 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817385 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN),
     /*  817388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817395 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817397 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817412 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817416 */     GIR_RootConstrainSelectedInstOperands,
     /*  817417 */     // GIR_Coverage, 13377,
     /*  817417 */     GIR_EraseRootFromParent_Done,
     /*  817418 */   // Label 13149: @817418
     /*  817418 */   GIM_Try, /*On fail goto*//*Label 13150*/ GIMT_Encode4(817485), // Rule ID 13378 //
     /*  817423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode1),
     /*  817426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  817431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  817434 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  817437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  817441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817452 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN),
     /*  817455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817462 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817479 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817483 */     GIR_RootConstrainSelectedInstOperands,
     /*  817484 */     // GIR_Coverage, 13378,
     /*  817484 */     GIR_EraseRootFromParent_Done,
     /*  817485 */   // Label 13150: @817485
     /*  817485 */   GIM_Try, /*On fail goto*//*Label 13151*/ GIMT_Encode4(817552), // Rule ID 13379 //
     /*  817490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode2),
     /*  817493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  817498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  817501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  817504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  817508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817512 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817519 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN),
     /*  817522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817529 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817531 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817546 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817550 */     GIR_RootConstrainSelectedInstOperands,
     /*  817551 */     // GIR_Coverage, 13379,
     /*  817551 */     GIR_EraseRootFromParent_Done,
     /*  817552 */   // Label 13151: @817552
     /*  817552 */   GIM_Try, /*On fail goto*//*Label 13152*/ GIMT_Encode4(817619), // Rule ID 13380 //
     /*  817557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode3),
     /*  817560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  817565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  817568 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  817571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  817575 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817586 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN),
     /*  817589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817596 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817617 */     GIR_RootConstrainSelectedInstOperands,
     /*  817618 */     // GIR_Coverage, 13380,
     /*  817618 */     GIR_EraseRootFromParent_Done,
     /*  817619 */   // Label 13152: @817619
     /*  817619 */   GIM_Try, /*On fail goto*//*Label 13153*/ GIMT_Encode4(817686), // Rule ID 13381 //
     /*  817624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode4),
     /*  817627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  817632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  817635 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  817638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  817642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817653 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN),
     /*  817656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817663 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817680 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817684 */     GIR_RootConstrainSelectedInstOperands,
     /*  817685 */     // GIR_Coverage, 13381,
     /*  817685 */     GIR_EraseRootFromParent_Done,
     /*  817686 */   // Label 13153: @817686
     /*  817686 */   GIM_Try, /*On fail goto*//*Label 13154*/ GIMT_Encode4(817753), // Rule ID 13642 //
     /*  817691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  817694 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  817699 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  817709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817720 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN),
     /*  817723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817730 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817751 */     GIR_RootConstrainSelectedInstOperands,
     /*  817752 */     // GIR_Coverage, 13642,
     /*  817752 */     GIR_EraseRootFromParent_Done,
     /*  817753 */   // Label 13154: @817753
     /*  817753 */   GIM_Try, /*On fail goto*//*Label 13155*/ GIMT_Encode4(817820), // Rule ID 13658 //
     /*  817758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  817761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  817766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  817776 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  817787 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  817787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN),
     /*  817790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  817792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  817797 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  817804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  817809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  817814 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817818 */     GIR_RootConstrainSelectedInstOperands,
     /*  817819 */     // GIR_Coverage, 13658,
     /*  817819 */     GIR_EraseRootFromParent_Done,
     /*  817820 */   // Label 13155: @817820
     /*  817820 */   GIM_Try, /*On fail goto*//*Label 13156*/ GIMT_Encode4(817876), // Rule ID 13627 //
     /*  817825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  817828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  817833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817836 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817839 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  817852 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  817852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  817855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  817860 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  817867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  817870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817874 */     GIR_RootConstrainSelectedInstOperands,
     /*  817875 */     // GIR_Coverage, 13627,
     /*  817875 */     GIR_EraseRootFromParent_Done,
     /*  817876 */   // Label 13156: @817876
     /*  817876 */   GIM_Try, /*On fail goto*//*Label 13157*/ GIMT_Encode4(817932), // Rule ID 13628 //
     /*  817881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  817884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  817889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817895 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817897 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  817908 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  817908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  817911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  817916 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  817923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  817926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817930 */     GIR_RootConstrainSelectedInstOperands,
     /*  817931 */     // GIR_Coverage, 13628,
     /*  817931 */     GIR_EraseRootFromParent_Done,
     /*  817932 */   // Label 13157: @817932
     /*  817932 */   GIM_Try, /*On fail goto*//*Label 13158*/ GIMT_Encode4(817988), // Rule ID 13629 //
     /*  817937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  817940 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  817945 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  817948 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  817951 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  817953 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  817957 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  817964 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  817964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  817967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  817972 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  817974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  817979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  817982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  817986 */     GIR_RootConstrainSelectedInstOperands,
     /*  817987 */     // GIR_Coverage, 13629,
     /*  817987 */     GIR_EraseRootFromParent_Done,
     /*  817988 */   // Label 13158: @817988
     /*  817988 */   GIM_Try, /*On fail goto*//*Label 13159*/ GIMT_Encode4(818044), // Rule ID 13630 //
     /*  817993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  817996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818007 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818020 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  818023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818028 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818042 */     GIR_RootConstrainSelectedInstOperands,
     /*  818043 */     // GIR_Coverage, 13630,
     /*  818043 */     GIR_EraseRootFromParent_Done,
     /*  818044 */   // Label 13159: @818044
     /*  818044 */   GIM_Try, /*On fail goto*//*Label 13160*/ GIMT_Encode4(818100), // Rule ID 13631 //
     /*  818049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  818052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818063 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818065 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818069 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818076 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
     /*  818079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818084 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818098 */     GIR_RootConstrainSelectedInstOperands,
     /*  818099 */     // GIR_Coverage, 13631,
     /*  818099 */     GIR_EraseRootFromParent_Done,
     /*  818100 */   // Label 13160: @818100
     /*  818100 */   GIM_Try, /*On fail goto*//*Label 13161*/ GIMT_Encode4(818156), // Rule ID 13643 //
     /*  818105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  818108 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  818113 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818119 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818121 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818125 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818132 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  818135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818140 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818154 */     GIR_RootConstrainSelectedInstOperands,
     /*  818155 */     // GIR_Coverage, 13643,
     /*  818155 */     GIR_EraseRootFromParent_Done,
     /*  818156 */   // Label 13161: @818156
     /*  818156 */   GIM_Try, /*On fail goto*//*Label 13162*/ GIMT_Encode4(818212), // Rule ID 13644 //
     /*  818161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  818164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  818169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818172 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818175 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818188 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  818191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818196 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818203 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818210 */     GIR_RootConstrainSelectedInstOperands,
     /*  818211 */     // GIR_Coverage, 13644,
     /*  818211 */     GIR_EraseRootFromParent_Done,
     /*  818212 */   // Label 13162: @818212
     /*  818212 */   GIM_Try, /*On fail goto*//*Label 13163*/ GIMT_Encode4(818268), // Rule ID 13645 //
     /*  818217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  818220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  818225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818231 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818244 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  818247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818252 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818266 */     GIR_RootConstrainSelectedInstOperands,
     /*  818267 */     // GIR_Coverage, 13645,
     /*  818267 */     GIR_EraseRootFromParent_Done,
     /*  818268 */   // Label 13163: @818268
     /*  818268 */   GIM_Try, /*On fail goto*//*Label 13164*/ GIMT_Encode4(818324), // Rule ID 13646 //
     /*  818273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  818276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  818281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818287 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818300 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  818303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818308 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818322 */     GIR_RootConstrainSelectedInstOperands,
     /*  818323 */     // GIR_Coverage, 13646,
     /*  818323 */     GIR_EraseRootFromParent_Done,
     /*  818324 */   // Label 13164: @818324
     /*  818324 */   GIM_Try, /*On fail goto*//*Label 13165*/ GIMT_Encode4(818380), // Rule ID 13647 //
     /*  818329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  818332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  818337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818340 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818343 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  818345 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818356 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
     /*  818359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818364 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  818374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818378 */     GIR_RootConstrainSelectedInstOperands,
     /*  818379 */     // GIR_Coverage, 13647,
     /*  818379 */     GIR_EraseRootFromParent_Done,
     /*  818380 */   // Label 13165: @818380
     /*  818380 */   GIM_Try, /*On fail goto*//*Label 13166*/ GIMT_Encode4(818440), // Rule ID 13372 //
     /*  818385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode0),
     /*  818388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  818393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  818396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  818399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  818403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818414 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  818414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN),
     /*  818417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818424 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818426 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818431 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818434 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818438 */     GIR_RootConstrainSelectedInstOperands,
     /*  818439 */     // GIR_Coverage, 13372,
     /*  818439 */     GIR_EraseRootFromParent_Done,
     /*  818440 */   // Label 13166: @818440
     /*  818440 */   GIM_Try, /*On fail goto*//*Label 13167*/ GIMT_Encode4(818500), // Rule ID 13373 //
     /*  818445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode1),
     /*  818448 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  818453 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  818456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  818459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  818463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818474 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  818474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN),
     /*  818477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818484 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818494 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818498 */     GIR_RootConstrainSelectedInstOperands,
     /*  818499 */     // GIR_Coverage, 13373,
     /*  818499 */     GIR_EraseRootFromParent_Done,
     /*  818500 */   // Label 13167: @818500
     /*  818500 */   GIM_Try, /*On fail goto*//*Label 13168*/ GIMT_Encode4(818560), // Rule ID 13374 //
     /*  818505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode2),
     /*  818508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  818513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  818516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  818519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  818523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818534 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  818534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN),
     /*  818537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818544 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818551 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818558 */     GIR_RootConstrainSelectedInstOperands,
     /*  818559 */     // GIR_Coverage, 13374,
     /*  818559 */     GIR_EraseRootFromParent_Done,
     /*  818560 */   // Label 13168: @818560
     /*  818560 */   GIM_Try, /*On fail goto*//*Label 13169*/ GIMT_Encode4(818620), // Rule ID 13375 //
     /*  818565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode3),
     /*  818568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  818573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  818576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  818579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  818583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818587 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818594 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  818594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN),
     /*  818597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818604 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818618 */     GIR_RootConstrainSelectedInstOperands,
     /*  818619 */     // GIR_Coverage, 13375,
     /*  818619 */     GIR_EraseRootFromParent_Done,
     /*  818620 */   // Label 13169: @818620
     /*  818620 */   GIM_Try, /*On fail goto*//*Label 13170*/ GIMT_Encode4(818680), // Rule ID 13376 //
     /*  818625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_HwMode4),
     /*  818628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
     /*  818633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  818636 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  818639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  818643 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818654 */     // (intrinsic_w_chain:{ *:[i64] } 2464:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15623:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
     /*  818654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN),
     /*  818657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818664 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818678 */     GIR_RootConstrainSelectedInstOperands,
     /*  818679 */     // GIR_Coverage, 13376,
     /*  818679 */     GIR_EraseRootFromParent_Done,
     /*  818680 */   // Label 13170: @818680
     /*  818680 */   GIM_Try, /*On fail goto*//*Label 13171*/ GIMT_Encode4(818740), // Rule ID 13637 //
     /*  818685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  818688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  818703 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818714 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  818717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818724 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818738 */     GIR_RootConstrainSelectedInstOperands,
     /*  818739 */     // GIR_Coverage, 13637,
     /*  818739 */     GIR_EraseRootFromParent_Done,
     /*  818740 */   // Label 13171: @818740
     /*  818740 */   GIM_Try, /*On fail goto*//*Label 13172*/ GIMT_Encode4(818800), // Rule ID 13638 //
     /*  818745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  818748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  818763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818774 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  818777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818784 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818798 */     GIR_RootConstrainSelectedInstOperands,
     /*  818799 */     // GIR_Coverage, 13638,
     /*  818799 */     GIR_EraseRootFromParent_Done,
     /*  818800 */   // Label 13172: @818800
     /*  818800 */   GIM_Try, /*On fail goto*//*Label 13173*/ GIMT_Encode4(818860), // Rule ID 13639 //
     /*  818805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  818808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  818823 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818834 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  818837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818844 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818858 */     GIR_RootConstrainSelectedInstOperands,
     /*  818859 */     // GIR_Coverage, 13639,
     /*  818859 */     GIR_EraseRootFromParent_Done,
     /*  818860 */   // Label 13173: @818860
     /*  818860 */   GIM_Try, /*On fail goto*//*Label 13174*/ GIMT_Encode4(818920), // Rule ID 13640 //
     /*  818865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  818868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  818883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818887 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818894 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  818897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818904 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818914 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818918 */     GIR_RootConstrainSelectedInstOperands,
     /*  818919 */     // GIR_Coverage, 13640,
     /*  818919 */     GIR_EraseRootFromParent_Done,
     /*  818920 */   // Label 13174: @818920
     /*  818920 */   GIM_Try, /*On fail goto*//*Label 13175*/ GIMT_Encode4(818980), // Rule ID 13641 //
     /*  818925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  818928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
     /*  818933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818936 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  818943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  818947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  818954 */     // (intrinsic_w_chain:{ *:[f32] } 2463:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  818954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
     /*  818957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  818959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  818964 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  818966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  818971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  818974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  818978 */     GIR_RootConstrainSelectedInstOperands,
     /*  818979 */     // GIR_Coverage, 13641,
     /*  818979 */     GIR_EraseRootFromParent_Done,
     /*  818980 */   // Label 13175: @818980
     /*  818980 */   GIM_Try, /*On fail goto*//*Label 13176*/ GIMT_Encode4(819040), // Rule ID 13653 //
     /*  818985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  818988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  818993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  818996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  818999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  819007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  819014 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  819014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  819017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  819024 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  819026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  819031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  819034 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819038 */     GIR_RootConstrainSelectedInstOperands,
     /*  819039 */     // GIR_Coverage, 13653,
     /*  819039 */     GIR_EraseRootFromParent_Done,
     /*  819040 */   // Label 13176: @819040
     /*  819040 */   GIM_Try, /*On fail goto*//*Label 13177*/ GIMT_Encode4(819100), // Rule ID 13654 //
     /*  819045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  819048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  819053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  819059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  819067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  819074 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  819074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  819077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  819084 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  819086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  819091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  819094 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819098 */     GIR_RootConstrainSelectedInstOperands,
     /*  819099 */     // GIR_Coverage, 13654,
     /*  819099 */     GIR_EraseRootFromParent_Done,
     /*  819100 */   // Label 13177: @819100
     /*  819100 */   GIM_Try, /*On fail goto*//*Label 13178*/ GIMT_Encode4(819160), // Rule ID 13655 //
     /*  819105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  819108 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  819113 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  819119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  819127 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  819134 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  819134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  819137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  819144 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  819146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  819151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  819154 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819158 */     GIR_RootConstrainSelectedInstOperands,
     /*  819159 */     // GIR_Coverage, 13655,
     /*  819159 */     GIR_EraseRootFromParent_Done,
     /*  819160 */   // Label 13178: @819160
     /*  819160 */   GIM_Try, /*On fail goto*//*Label 13179*/ GIMT_Encode4(819220), // Rule ID 13656 //
     /*  819165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  819168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  819173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  819179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  819187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  819194 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  819194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  819197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  819204 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  819206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  819211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  819214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819218 */     GIR_RootConstrainSelectedInstOperands,
     /*  819219 */     // GIR_Coverage, 13656,
     /*  819219 */     GIR_EraseRootFromParent_Done,
     /*  819220 */   // Label 13179: @819220
     /*  819220 */   GIM_Try, /*On fail goto*//*Label 13180*/ GIMT_Encode4(819280), // Rule ID 13657 //
     /*  819225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  819228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
     /*  819233 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819236 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  819239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  819247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  819254 */     // (intrinsic_w_chain:{ *:[f32] } 2462:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  819254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
     /*  819257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  819264 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  819266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  819271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  819274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819278 */     GIR_RootConstrainSelectedInstOperands,
     /*  819279 */     // GIR_Coverage, 13657,
     /*  819279 */     GIR_EraseRootFromParent_Done,
     /*  819280 */   // Label 13180: @819280
     /*  819280 */   GIM_Try, /*On fail goto*//*Label 13181*/ GIMT_Encode4(819325), // Rule ID 31021 //
     /*  819285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  819288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  819296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819303 */     // MIs[0] offset32
     /*  819303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819306 */     // (intrinsic_w_chain:{ *:[i64] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  819306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819311 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  819313 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819319 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819323 */     GIR_RootConstrainSelectedInstOperands,
     /*  819324 */     // GIR_Coverage, 31021,
     /*  819324 */     GIR_EraseRootFromParent_Done,
     /*  819325 */   // Label 13181: @819325
     /*  819325 */   GIM_Try, /*On fail goto*//*Label 13182*/ GIMT_Encode4(819370), // Rule ID 31022 //
     /*  819330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  819333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  819341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819348 */     // MIs[0] offset32
     /*  819348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819351 */     // (intrinsic_w_chain:{ *:[i64] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  819351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819356 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  819358 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819368 */     GIR_RootConstrainSelectedInstOperands,
     /*  819369 */     // GIR_Coverage, 31022,
     /*  819369 */     GIR_EraseRootFromParent_Done,
     /*  819370 */   // Label 13182: @819370
     /*  819370 */   GIM_Try, /*On fail goto*//*Label 13183*/ GIMT_Encode4(819415), // Rule ID 31023 //
     /*  819375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  819378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  819386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819393 */     // MIs[0] offset32
     /*  819393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819396 */     // (intrinsic_w_chain:{ *:[i64] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  819396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819401 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  819403 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819409 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819413 */     GIR_RootConstrainSelectedInstOperands,
     /*  819414 */     // GIR_Coverage, 31023,
     /*  819414 */     GIR_EraseRootFromParent_Done,
     /*  819415 */   // Label 13183: @819415
     /*  819415 */   GIM_Try, /*On fail goto*//*Label 13184*/ GIMT_Encode4(819460), // Rule ID 31024 //
     /*  819420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  819423 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819428 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  819431 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819438 */     // MIs[0] offset32
     /*  819438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819441 */     // (intrinsic_w_chain:{ *:[i64] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  819441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819446 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  819448 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819458 */     GIR_RootConstrainSelectedInstOperands,
     /*  819459 */     // GIR_Coverage, 31024,
     /*  819459 */     GIR_EraseRootFromParent_Done,
     /*  819460 */   // Label 13184: @819460
     /*  819460 */   GIM_Try, /*On fail goto*//*Label 13185*/ GIMT_Encode4(819505), // Rule ID 31025 //
     /*  819465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  819468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  819476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819483 */     // MIs[0] offset32
     /*  819483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819486 */     // (intrinsic_w_chain:{ *:[i64] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  819486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  819491 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  819493 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819503 */     GIR_RootConstrainSelectedInstOperands,
     /*  819504 */     // GIR_Coverage, 31025,
     /*  819504 */     GIR_EraseRootFromParent_Done,
     /*  819505 */   // Label 13185: @819505
     /*  819505 */   GIM_Try, /*On fail goto*//*Label 13186*/ GIMT_Encode4(819602), // Rule ID 31026 //
     /*  819510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  819513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819528 */     // MIs[0] offset32
     /*  819528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819531 */     // (intrinsic_w_chain:{ *:[i32] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  819531 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  819534 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819538 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819543 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  819547 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819553 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819557 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  819559 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  819562 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819566 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819571 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  819574 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  819584 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  819591 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819596 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819601 */     // GIR_Coverage, 31026,
     /*  819601 */     GIR_EraseRootFromParent_Done,
     /*  819602 */   // Label 13186: @819602
     /*  819602 */   GIM_Try, /*On fail goto*//*Label 13187*/ GIMT_Encode4(819699), // Rule ID 31027 //
     /*  819607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  819610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819618 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819625 */     // MIs[0] offset32
     /*  819625 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819628 */     // (intrinsic_w_chain:{ *:[i32] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  819628 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  819631 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819635 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819640 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  819644 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819650 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819654 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  819656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  819659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819668 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  819671 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  819681 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  819688 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819693 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819698 */     // GIR_Coverage, 31027,
     /*  819698 */     GIR_EraseRootFromParent_Done,
     /*  819699 */   // Label 13187: @819699
     /*  819699 */   GIM_Try, /*On fail goto*//*Label 13188*/ GIMT_Encode4(819796), // Rule ID 31028 //
     /*  819704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  819707 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819712 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819715 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819722 */     // MIs[0] offset32
     /*  819722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819725 */     // (intrinsic_w_chain:{ *:[i32] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  819725 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  819728 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819732 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819737 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  819741 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819747 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819751 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  819753 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  819756 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819760 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819765 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  819768 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  819778 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  819785 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819790 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819795 */     // GIR_Coverage, 31028,
     /*  819795 */     GIR_EraseRootFromParent_Done,
     /*  819796 */   // Label 13188: @819796
     /*  819796 */   GIM_Try, /*On fail goto*//*Label 13189*/ GIMT_Encode4(819893), // Rule ID 31029 //
     /*  819801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  819804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819819 */     // MIs[0] offset32
     /*  819819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819822 */     // (intrinsic_w_chain:{ *:[i32] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  819822 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  819825 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819829 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819834 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  819838 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819844 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819848 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  819850 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  819853 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819857 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819862 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  819865 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  819875 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  819882 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819887 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819892 */     // GIR_Coverage, 31029,
     /*  819892 */     GIR_EraseRootFromParent_Done,
     /*  819893 */   // Label 13189: @819893
     /*  819893 */   GIM_Try, /*On fail goto*//*Label 13190*/ GIMT_Encode4(819990), // Rule ID 31030 //
     /*  819898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  819901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
     /*  819906 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  819909 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  819912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819916 */     // MIs[0] offset32
     /*  819916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  819919 */     // (intrinsic_w_chain:{ *:[i32] } 2405:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  819919 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  819922 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
     /*  819926 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819931 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  819935 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  819941 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  819945 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  819947 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  819950 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819954 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  819959 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  819962 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  819970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  819972 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  819979 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  819984 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  819989 */     // GIR_Coverage, 31030,
     /*  819989 */     GIR_EraseRootFromParent_Done,
     /*  819990 */   // Label 13190: @819990
     /*  819990 */   GIM_Try, /*On fail goto*//*Label 13191*/ GIMT_Encode4(820035), // Rule ID 31031 //
     /*  819995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  819998 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820003 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  820006 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820013 */     // MIs[0] offset32
     /*  820013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820016 */     // (intrinsic_w_chain:{ *:[i64] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  820016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  820021 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  820023 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820029 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820033 */     GIR_RootConstrainSelectedInstOperands,
     /*  820034 */     // GIR_Coverage, 31031,
     /*  820034 */     GIR_EraseRootFromParent_Done,
     /*  820035 */   // Label 13191: @820035
     /*  820035 */   GIM_Try, /*On fail goto*//*Label 13192*/ GIMT_Encode4(820080), // Rule ID 31032 //
     /*  820040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  820043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  820051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820058 */     // MIs[0] offset32
     /*  820058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820061 */     // (intrinsic_w_chain:{ *:[i64] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  820061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  820066 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  820068 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820074 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820078 */     GIR_RootConstrainSelectedInstOperands,
     /*  820079 */     // GIR_Coverage, 31032,
     /*  820079 */     GIR_EraseRootFromParent_Done,
     /*  820080 */   // Label 13192: @820080
     /*  820080 */   GIM_Try, /*On fail goto*//*Label 13193*/ GIMT_Encode4(820125), // Rule ID 31033 //
     /*  820085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  820088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820093 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  820096 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820103 */     // MIs[0] offset32
     /*  820103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820106 */     // (intrinsic_w_chain:{ *:[i64] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  820106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  820111 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  820113 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820123 */     GIR_RootConstrainSelectedInstOperands,
     /*  820124 */     // GIR_Coverage, 31033,
     /*  820124 */     GIR_EraseRootFromParent_Done,
     /*  820125 */   // Label 13193: @820125
     /*  820125 */   GIM_Try, /*On fail goto*//*Label 13194*/ GIMT_Encode4(820170), // Rule ID 31034 //
     /*  820130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  820133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  820141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820148 */     // MIs[0] offset32
     /*  820148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820151 */     // (intrinsic_w_chain:{ *:[i64] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  820151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  820156 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  820158 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820164 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820168 */     GIR_RootConstrainSelectedInstOperands,
     /*  820169 */     // GIR_Coverage, 31034,
     /*  820169 */     GIR_EraseRootFromParent_Done,
     /*  820170 */   // Label 13194: @820170
     /*  820170 */   GIM_Try, /*On fail goto*//*Label 13195*/ GIMT_Encode4(820215), // Rule ID 31035 //
     /*  820175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  820178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  820186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820193 */     // MIs[0] offset32
     /*  820193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820196 */     // (intrinsic_w_chain:{ *:[i64] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
     /*  820196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  820201 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  820203 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820209 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820213 */     GIR_RootConstrainSelectedInstOperands,
     /*  820214 */     // GIR_Coverage, 31035,
     /*  820214 */     GIR_EraseRootFromParent_Done,
     /*  820215 */   // Label 13195: @820215
     /*  820215 */   GIM_Try, /*On fail goto*//*Label 13196*/ GIMT_Encode4(820312), // Rule ID 31036 //
     /*  820220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  820223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820231 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820238 */     // MIs[0] offset32
     /*  820238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820241 */     // (intrinsic_w_chain:{ *:[i32] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  820241 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  820244 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820248 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820253 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  820257 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820263 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820267 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  820269 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  820272 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820276 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820281 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  820284 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  820294 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  820301 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820306 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820311 */     // GIR_Coverage, 31036,
     /*  820311 */     GIR_EraseRootFromParent_Done,
     /*  820312 */   // Label 13196: @820312
     /*  820312 */   GIM_Try, /*On fail goto*//*Label 13197*/ GIMT_Encode4(820409), // Rule ID 31037 //
     /*  820317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  820320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820328 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820335 */     // MIs[0] offset32
     /*  820335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820338 */     // (intrinsic_w_chain:{ *:[i32] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  820338 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  820341 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820345 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820350 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  820354 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820360 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820364 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  820366 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  820369 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820373 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820378 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  820381 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  820391 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  820398 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820403 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820408 */     // GIR_Coverage, 31037,
     /*  820408 */     GIR_EraseRootFromParent_Done,
     /*  820409 */   // Label 13197: @820409
     /*  820409 */   GIM_Try, /*On fail goto*//*Label 13198*/ GIMT_Encode4(820506), // Rule ID 31038 //
     /*  820414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  820417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820432 */     // MIs[0] offset32
     /*  820432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820435 */     // (intrinsic_w_chain:{ *:[i32] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  820435 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  820438 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820442 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820447 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  820451 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820457 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820461 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  820463 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  820466 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820470 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820475 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  820478 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  820488 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  820495 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820500 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820505 */     // GIR_Coverage, 31038,
     /*  820505 */     GIR_EraseRootFromParent_Done,
     /*  820506 */   // Label 13198: @820506
     /*  820506 */   GIM_Try, /*On fail goto*//*Label 13199*/ GIMT_Encode4(820603), // Rule ID 31039 //
     /*  820511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  820514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820529 */     // MIs[0] offset32
     /*  820529 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820532 */     // (intrinsic_w_chain:{ *:[i32] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  820532 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  820535 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820539 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820544 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  820548 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820554 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820558 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  820560 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  820563 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820567 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820572 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  820575 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  820585 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  820592 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820597 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820602 */     // GIR_Coverage, 31039,
     /*  820602 */     GIR_EraseRootFromParent_Done,
     /*  820603 */   // Label 13199: @820603
     /*  820603 */   GIM_Try, /*On fail goto*//*Label 13200*/ GIMT_Encode4(820700), // Rule ID 31040 //
     /*  820608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  820611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
     /*  820616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  820622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820626 */     // MIs[0] offset32
     /*  820626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  820629 */     // (intrinsic_w_chain:{ *:[i32] } 2433:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
     /*  820629 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  820632 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
     /*  820636 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820641 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
     /*  820645 */     GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
     /*  820651 */     GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820655 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  820657 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  820660 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820664 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  820669 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  820672 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  820680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  820682 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /*  820689 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  820694 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  820699 */     // GIR_Coverage, 31040,
     /*  820699 */     GIR_EraseRootFromParent_Done,
     /*  820700 */   // Label 13200: @820700
     /*  820700 */   GIM_Try, /*On fail goto*//*Label 13201*/ GIMT_Encode4(820763), // Rule ID 13670 //
     /*  820705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode0),
     /*  820708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  820713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  820719 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  820721 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  820725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  820732 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  820732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  820735 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  820740 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  820742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  820747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  820752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  820757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820761 */     GIR_RootConstrainSelectedInstOperands,
     /*  820762 */     // GIR_Coverage, 13670,
     /*  820762 */     GIR_EraseRootFromParent_Done,
     /*  820763 */   // Label 13201: @820763
     /*  820763 */   GIM_Try, /*On fail goto*//*Label 13202*/ GIMT_Encode4(820826), // Rule ID 13671 //
     /*  820768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode1),
     /*  820771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  820776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  820782 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  820784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  820788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  820795 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  820795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  820798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  820803 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  820805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  820810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  820815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  820820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820824 */     GIR_RootConstrainSelectedInstOperands,
     /*  820825 */     // GIR_Coverage, 13671,
     /*  820825 */     GIR_EraseRootFromParent_Done,
     /*  820826 */   // Label 13202: @820826
     /*  820826 */   GIM_Try, /*On fail goto*//*Label 13203*/ GIMT_Encode4(820889), // Rule ID 13672 //
     /*  820831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode2),
     /*  820834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  820839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  820845 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  820847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  820851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  820858 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  820858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  820861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  820866 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  820868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  820873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  820878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  820883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820887 */     GIR_RootConstrainSelectedInstOperands,
     /*  820888 */     // GIR_Coverage, 13672,
     /*  820888 */     GIR_EraseRootFromParent_Done,
     /*  820889 */   // Label 13203: @820889
     /*  820889 */   GIM_Try, /*On fail goto*//*Label 13204*/ GIMT_Encode4(820952), // Rule ID 13673 //
     /*  820894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode3),
     /*  820897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  820902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  820908 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  820910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  820914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  820921 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  820921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  820924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  820929 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  820931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  820936 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  820941 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  820946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  820950 */     GIR_RootConstrainSelectedInstOperands,
     /*  820951 */     // GIR_Coverage, 13673,
     /*  820951 */     GIR_EraseRootFromParent_Done,
     /*  820952 */   // Label 13204: @820952
     /*  820952 */   GIM_Try, /*On fail goto*//*Label 13205*/ GIMT_Encode4(821015), // Rule ID 13674 //
     /*  820957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode4),
     /*  820960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  820965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  820968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  820971 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  820973 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  820977 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  820984 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  820984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR),
     /*  820987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  820992 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  820994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  820999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821013 */     GIR_RootConstrainSelectedInstOperands,
     /*  821014 */     // GIR_Coverage, 13674,
     /*  821014 */     GIR_EraseRootFromParent_Done,
     /*  821015 */   // Label 13205: @821015
     /*  821015 */   GIM_Try, /*On fail goto*//*Label 13206*/ GIMT_Encode4(821078), // Rule ID 13686 //
     /*  821020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode0),
     /*  821023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821031 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821034 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  821047 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  821050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821055 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821076 */     GIR_RootConstrainSelectedInstOperands,
     /*  821077 */     // GIR_Coverage, 13686,
     /*  821077 */     GIR_EraseRootFromParent_Done,
     /*  821078 */   // Label 13206: @821078
     /*  821078 */   GIM_Try, /*On fail goto*//*Label 13207*/ GIMT_Encode4(821141), // Rule ID 13687 //
     /*  821083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode1),
     /*  821086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821091 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821097 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821099 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  821110 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  821113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821118 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821139 */     GIR_RootConstrainSelectedInstOperands,
     /*  821140 */     // GIR_Coverage, 13687,
     /*  821140 */     GIR_EraseRootFromParent_Done,
     /*  821141 */   // Label 13207: @821141
     /*  821141 */   GIM_Try, /*On fail goto*//*Label 13208*/ GIMT_Encode4(821204), // Rule ID 13688 //
     /*  821146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode2),
     /*  821149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821160 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821162 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821166 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  821173 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  821176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821181 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821202 */     GIR_RootConstrainSelectedInstOperands,
     /*  821203 */     // GIR_Coverage, 13688,
     /*  821203 */     GIR_EraseRootFromParent_Done,
     /*  821204 */   // Label 13208: @821204
     /*  821204 */   GIM_Try, /*On fail goto*//*Label 13209*/ GIMT_Encode4(821267), // Rule ID 13689 //
     /*  821209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode3),
     /*  821212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821220 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821223 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821229 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  821236 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  821239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821244 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821265 */     GIR_RootConstrainSelectedInstOperands,
     /*  821266 */     // GIR_Coverage, 13689,
     /*  821266 */     GIR_EraseRootFromParent_Done,
     /*  821267 */   // Label 13209: @821267
     /*  821267 */   GIM_Try, /*On fail goto*//*Label 13210*/ GIMT_Encode4(821330), // Rule ID 13690 //
     /*  821272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only_HwMode4),
     /*  821275 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821280 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821286 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  821299 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR),
     /*  821302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821307 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821328 */     GIR_RootConstrainSelectedInstOperands,
     /*  821329 */     // GIR_Coverage, 13690,
     /*  821329 */     GIR_EraseRootFromParent_Done,
     /*  821330 */   // Label 13210: @821330
     /*  821330 */   GIM_Try, /*On fail goto*//*Label 13211*/ GIMT_Encode4(821397), // Rule ID 13664 //
     /*  821335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only),
     /*  821338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  821343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821346 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  821353 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821357 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  821364 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_SADDR_RTN),
     /*  821367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  821369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821374 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821391 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821395 */     GIR_RootConstrainSelectedInstOperands,
     /*  821396 */     // GIR_Coverage, 13664,
     /*  821396 */     GIR_EraseRootFromParent_Done,
     /*  821397 */   // Label 13211: @821397
     /*  821397 */   GIM_Try, /*On fail goto*//*Label 13212*/ GIMT_Encode4(821464), // Rule ID 13680 //
     /*  821402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGVSMode_isGFX12Only),
     /*  821405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  821420 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_glc),
     /*  821431 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (GlobalSAddrGLC:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  821431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_SADDR_RTN),
     /*  821434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  821436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  821441 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  821448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  821453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  821458 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821462 */     GIR_RootConstrainSelectedInstOperands,
     /*  821463 */     // GIR_Coverage, 13680,
     /*  821463 */     GIR_EraseRootFromParent_Done,
     /*  821464 */   // Label 13212: @821464
     /*  821464 */   GIM_Try, /*On fail goto*//*Label 13213*/ GIMT_Encode4(821520), // Rule ID 13665 //
     /*  821469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  821472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  821477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821480 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821483 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821496 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  821499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821504 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821514 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821518 */     GIR_RootConstrainSelectedInstOperands,
     /*  821519 */     // GIR_Coverage, 13665,
     /*  821519 */     GIR_EraseRootFromParent_Done,
     /*  821520 */   // Label 13213: @821520
     /*  821520 */   GIM_Try, /*On fail goto*//*Label 13214*/ GIMT_Encode4(821576), // Rule ID 13666 //
     /*  821525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  821528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  821533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821536 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821539 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821541 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821552 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  821555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821560 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821570 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821574 */     GIR_RootConstrainSelectedInstOperands,
     /*  821575 */     // GIR_Coverage, 13666,
     /*  821575 */     GIR_EraseRootFromParent_Done,
     /*  821576 */   // Label 13214: @821576
     /*  821576 */   GIM_Try, /*On fail goto*//*Label 13215*/ GIMT_Encode4(821632), // Rule ID 13667 //
     /*  821581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  821584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  821589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821595 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821597 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821608 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  821611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821616 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821630 */     GIR_RootConstrainSelectedInstOperands,
     /*  821631 */     // GIR_Coverage, 13667,
     /*  821631 */     GIR_EraseRootFromParent_Done,
     /*  821632 */   // Label 13215: @821632
     /*  821632 */   GIM_Try, /*On fail goto*//*Label 13216*/ GIMT_Encode4(821688), // Rule ID 13668 //
     /*  821637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  821640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  821645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821651 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821653 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821664 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  821667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821672 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821686 */     GIR_RootConstrainSelectedInstOperands,
     /*  821687 */     // GIR_Coverage, 13668,
     /*  821687 */     GIR_EraseRootFromParent_Done,
     /*  821688 */   // Label 13216: @821688
     /*  821688 */   GIM_Try, /*On fail goto*//*Label 13217*/ GIMT_Encode4(821744), // Rule ID 13669 //
     /*  821693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  821696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  821701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821704 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821707 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821709 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821720 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
     /*  821723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821728 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821742 */     GIR_RootConstrainSelectedInstOperands,
     /*  821743 */     // GIR_Coverage, 13669,
     /*  821743 */     GIR_EraseRootFromParent_Done,
     /*  821744 */   // Label 13217: @821744
     /*  821744 */   GIM_Try, /*On fail goto*//*Label 13218*/ GIMT_Encode4(821800), // Rule ID 13681 //
     /*  821749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  821752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821760 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821763 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821765 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821776 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  821779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821784 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821798 */     GIR_RootConstrainSelectedInstOperands,
     /*  821799 */     // GIR_Coverage, 13681,
     /*  821799 */     GIR_EraseRootFromParent_Done,
     /*  821800 */   // Label 13218: @821800
     /*  821800 */   GIM_Try, /*On fail goto*//*Label 13219*/ GIMT_Encode4(821856), // Rule ID 13682 //
     /*  821805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  821808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821819 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821821 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821832 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  821835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821840 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821854 */     GIR_RootConstrainSelectedInstOperands,
     /*  821855 */     // GIR_Coverage, 13682,
     /*  821855 */     GIR_EraseRootFromParent_Done,
     /*  821856 */   // Label 13219: @821856
     /*  821856 */   GIM_Try, /*On fail goto*//*Label 13220*/ GIMT_Encode4(821912), // Rule ID 13683 //
     /*  821861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  821864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821869 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821872 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821875 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821877 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821888 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  821891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821896 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821910 */     GIR_RootConstrainSelectedInstOperands,
     /*  821911 */     // GIR_Coverage, 13683,
     /*  821911 */     GIR_EraseRootFromParent_Done,
     /*  821912 */   // Label 13220: @821912
     /*  821912 */   GIM_Try, /*On fail goto*//*Label 13221*/ GIMT_Encode4(821968), // Rule ID 13684 //
     /*  821917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  821920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821928 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821931 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  821944 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  821944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  821947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  821952 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  821954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  821959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  821962 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  821966 */     GIR_RootConstrainSelectedInstOperands,
     /*  821967 */     // GIR_Coverage, 13684,
     /*  821967 */     GIR_EraseRootFromParent_Done,
     /*  821968 */   // Label 13221: @821968
     /*  821968 */   GIM_Try, /*On fail goto*//*Label 13222*/ GIMT_Encode4(822024), // Rule ID 13685 //
     /*  821973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  821976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  821981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  821984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  821987 */     GIM_CheckHasNoUse, /*MI*/0,
     /*  821989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  821993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822000 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
     /*  822003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822008 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  822018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822022 */     GIR_RootConstrainSelectedInstOperands,
     /*  822023 */     // GIR_Coverage, 13685,
     /*  822023 */     GIR_EraseRootFromParent_Done,
     /*  822024 */   // Label 13222: @822024
     /*  822024 */   GIM_Try, /*On fail goto*//*Label 13223*/ GIMT_Encode4(822084), // Rule ID 13659 //
     /*  822029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  822032 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  822037 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822047 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822058 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  822061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822068 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822078 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822082 */     GIR_RootConstrainSelectedInstOperands,
     /*  822083 */     // GIR_Coverage, 13659,
     /*  822083 */     GIR_EraseRootFromParent_Done,
     /*  822084 */   // Label 13223: @822084
     /*  822084 */   GIM_Try, /*On fail goto*//*Label 13224*/ GIMT_Encode4(822144), // Rule ID 13660 //
     /*  822089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  822092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  822097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822107 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822118 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  822121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822128 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822142 */     GIR_RootConstrainSelectedInstOperands,
     /*  822143 */     // GIR_Coverage, 13660,
     /*  822143 */     GIR_EraseRootFromParent_Done,
     /*  822144 */   // Label 13224: @822144
     /*  822144 */   GIM_Try, /*On fail goto*//*Label 13225*/ GIMT_Encode4(822204), // Rule ID 13661 //
     /*  822149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  822152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  822157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822160 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822167 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822171 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822178 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  822181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822188 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822202 */     GIR_RootConstrainSelectedInstOperands,
     /*  822203 */     // GIR_Coverage, 13661,
     /*  822203 */     GIR_EraseRootFromParent_Done,
     /*  822204 */   // Label 13225: @822204
     /*  822204 */   GIM_Try, /*On fail goto*//*Label 13226*/ GIMT_Encode4(822264), // Rule ID 13662 //
     /*  822209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  822212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  822217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822220 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822227 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822231 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822238 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  822241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822248 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822262 */     GIR_RootConstrainSelectedInstOperands,
     /*  822263 */     // GIR_Coverage, 13662,
     /*  822263 */     GIR_EraseRootFromParent_Done,
     /*  822264 */   // Label 13226: @822264
     /*  822264 */   GIM_Try, /*On fail goto*//*Label 13227*/ GIMT_Encode4(822324), // Rule ID 13663 //
     /*  822269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  822272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
     /*  822277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822287 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822298 */     // (intrinsic_w_chain:{ *:[f32] } 2450:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
     /*  822301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822308 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822322 */     GIR_RootConstrainSelectedInstOperands,
     /*  822323 */     // GIR_Coverage, 13663,
     /*  822323 */     GIR_EraseRootFromParent_Done,
     /*  822324 */   // Label 13227: @822324
     /*  822324 */   GIM_Try, /*On fail goto*//*Label 13228*/ GIMT_Encode4(822384), // Rule ID 13675 //
     /*  822329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode0),
     /*  822332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  822337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822340 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822347 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822358 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  822361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822368 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822382 */     GIR_RootConstrainSelectedInstOperands,
     /*  822383 */     // GIR_Coverage, 13675,
     /*  822383 */     GIR_EraseRootFromParent_Done,
     /*  822384 */   // Label 13228: @822384
     /*  822384 */   GIM_Try, /*On fail goto*//*Label 13229*/ GIMT_Encode4(822444), // Rule ID 13676 //
     /*  822389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode1),
     /*  822392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  822397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822400 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822407 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822411 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822418 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  822421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822428 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822442 */     GIR_RootConstrainSelectedInstOperands,
     /*  822443 */     // GIR_Coverage, 13676,
     /*  822443 */     GIR_EraseRootFromParent_Done,
     /*  822444 */   // Label 13229: @822444
     /*  822444 */   GIM_Try, /*On fail goto*//*Label 13230*/ GIMT_Encode4(822504), // Rule ID 13677 //
     /*  822449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode2),
     /*  822452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  822457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822478 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  822481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822488 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822498 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822502 */     GIR_RootConstrainSelectedInstOperands,
     /*  822503 */     // GIR_Coverage, 13677,
     /*  822503 */     GIR_EraseRootFromParent_Done,
     /*  822504 */   // Label 13230: @822504
     /*  822504 */   GIM_Try, /*On fail goto*//*Label 13231*/ GIMT_Encode4(822564), // Rule ID 13678 //
     /*  822509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode3),
     /*  822512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  822517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822538 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  822541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822548 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822562 */     GIR_RootConstrainSelectedInstOperands,
     /*  822563 */     // GIR_Coverage, 13678,
     /*  822563 */     GIR_EraseRootFromParent_Done,
     /*  822564 */   // Label 13231: @822564
     /*  822564 */   GIM_Try, /*On fail goto*//*Label 13232*/ GIMT_Encode4(822624), // Rule ID 13679 //
     /*  822569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only_HwMode4),
     /*  822572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
     /*  822577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  822580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  822583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  822591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  822598 */     // (intrinsic_w_chain:{ *:[f32] } 2449:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64_AlignTarget:{ *:[i64] }:$vaddr, anonymous_15624:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
     /*  822598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
     /*  822601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  822603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  822608 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  822610 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  822615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  822618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822622 */     GIR_RootConstrainSelectedInstOperands,
     /*  822623 */     // GIR_Coverage, 13679,
     /*  822623 */     GIR_EraseRootFromParent_Done,
     /*  822624 */   // Label 13232: @822624
     /*  822624 */   GIM_Reject,
     /*  822625 */ // Label 13138: @822625
     /*  822625 */ GIM_Try, /*On fail goto*//*Label 13233*/ GIMT_Encode4(825386),
     /*  822630 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /*  822633 */   GIM_Try, /*On fail goto*//*Label 13234*/ GIMT_Encode4(822702), // Rule ID 9321 //
     /*  822638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  822641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b8),
     /*  822646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  822650 */     // MIs[0] dsaddr
     /*  822650 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  822654 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822658 */     // MIs[0] offset
     /*  822658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  822661 */     // MIs[0] Operand 4
     /*  822661 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  822664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  822671 */     // (intrinsic_void 2468:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B8_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  822671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8_SADDR),
     /*  822674 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  822676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  822681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  822686 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  822688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  822693 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  822696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822700 */     GIR_RootConstrainSelectedInstOperands,
     /*  822701 */     // GIR_Coverage, 9321,
     /*  822701 */     GIR_EraseRootFromParent_Done,
     /*  822702 */   // Label 13234: @822702
     /*  822702 */   GIM_Try, /*On fail goto*//*Label 13235*/ GIMT_Encode4(822771), // Rule ID 9327 //
     /*  822707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  822710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b8),
     /*  822715 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  822719 */     // MIs[0] dsaddr
     /*  822719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  822723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822727 */     // MIs[0] offset
     /*  822727 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  822730 */     // MIs[0] Operand 4
     /*  822730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  822733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  822740 */     // (intrinsic_void 2481:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B8_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  822740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8_SADDR),
     /*  822743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  822748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  822753 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  822755 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  822757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  822762 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  822765 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822769 */     GIR_RootConstrainSelectedInstOperands,
     /*  822770 */     // GIR_Coverage, 9327,
     /*  822770 */     GIR_EraseRootFromParent_Done,
     /*  822771 */   // Label 13235: @822771
     /*  822771 */   GIM_Try, /*On fail goto*//*Label 13236*/ GIMT_Encode4(822840), // Rule ID 13532 //
     /*  822776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  822779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b32),
     /*  822784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  822788 */     // MIs[0] dsaddr
     /*  822788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  822792 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822796 */     // MIs[0] offset
     /*  822796 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  822799 */     // MIs[0] Operand 4
     /*  822799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  822802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  822809 */     // (intrinsic_void 2466:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B32_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  822809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32_SADDR),
     /*  822812 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  822814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  822819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  822824 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  822826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  822831 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  822834 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822838 */     GIR_RootConstrainSelectedInstOperands,
     /*  822839 */     // GIR_Coverage, 13532,
     /*  822839 */     GIR_EraseRootFromParent_Done,
     /*  822840 */   // Label 13236: @822840
     /*  822840 */   GIM_Try, /*On fail goto*//*Label 13237*/ GIMT_Encode4(822909), // Rule ID 13538 //
     /*  822845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  822848 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b64),
     /*  822853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  822857 */     // MIs[0] dsaddr
     /*  822857 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  822861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822865 */     // MIs[0] offset
     /*  822865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  822868 */     // MIs[0] Operand 4
     /*  822868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  822871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  822878 */     // (intrinsic_void 2467:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  822878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR),
     /*  822881 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  822883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  822888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  822893 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  822895 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  822900 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  822903 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822907 */     GIR_RootConstrainSelectedInstOperands,
     /*  822908 */     // GIR_Coverage, 13538,
     /*  822908 */     GIR_EraseRootFromParent_Done,
     /*  822909 */   // Label 13237: @822909
     /*  822909 */   GIM_Try, /*On fail goto*//*Label 13238*/ GIMT_Encode4(822978), // Rule ID 13544 //
     /*  822914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  822917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b128),
     /*  822922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  822926 */     // MIs[0] dsaddr
     /*  822926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  822930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  822934 */     // MIs[0] offset
     /*  822934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  822937 */     // MIs[0] Operand 4
     /*  822937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  822940 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  822947 */     // (intrinsic_void 2465:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B128_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  822947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128_SADDR),
     /*  822950 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  822952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  822957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  822962 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  822964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  822969 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  822972 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  822976 */     GIR_RootConstrainSelectedInstOperands,
     /*  822977 */     // GIR_Coverage, 13544,
     /*  822977 */     GIR_EraseRootFromParent_Done,
     /*  822978 */   // Label 13238: @822978
     /*  822978 */   GIM_Try, /*On fail goto*//*Label 13239*/ GIMT_Encode4(823047), // Rule ID 13550 //
     /*  822983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  822986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b32),
     /*  822991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  822995 */     // MIs[0] dsaddr
     /*  822995 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  822999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823003 */     // MIs[0] offset
     /*  823003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823006 */     // MIs[0] Operand 4
     /*  823006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  823016 */     // (intrinsic_void 2479:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B32_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32_SADDR),
     /*  823019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  823024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  823029 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823031 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  823038 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823045 */     GIR_RootConstrainSelectedInstOperands,
     /*  823046 */     // GIR_Coverage, 13550,
     /*  823046 */     GIR_EraseRootFromParent_Done,
     /*  823047 */   // Label 13239: @823047
     /*  823047 */   GIM_Try, /*On fail goto*//*Label 13240*/ GIMT_Encode4(823116), // Rule ID 13556 //
     /*  823052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  823055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b64),
     /*  823060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  823064 */     // MIs[0] dsaddr
     /*  823064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823068 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823072 */     // MIs[0] offset
     /*  823072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823075 */     // MIs[0] Operand 4
     /*  823075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823078 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  823085 */     // (intrinsic_void 2480:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B64_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64_SADDR),
     /*  823088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  823093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  823098 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823100 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  823107 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823110 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823114 */     GIR_RootConstrainSelectedInstOperands,
     /*  823115 */     // GIR_Coverage, 13556,
     /*  823115 */     GIR_EraseRootFromParent_Done,
     /*  823116 */   // Label 13240: @823116
     /*  823116 */   GIM_Try, /*On fail goto*//*Label 13241*/ GIMT_Encode4(823185), // Rule ID 13562 //
     /*  823121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  823124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b128),
     /*  823129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  823133 */     // MIs[0] dsaddr
     /*  823133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823141 */     // MIs[0] offset
     /*  823141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823144 */     // MIs[0] Operand 4
     /*  823144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823147 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset),
     /*  823154 */     // (intrinsic_void 2478:{ *:[iPTR] }, (GlobalSAddrNoIOffset:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }))  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B128_SADDR ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128_SADDR),
     /*  823157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  823162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  823167 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823169 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  823176 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823183 */     GIR_RootConstrainSelectedInstOperands,
     /*  823184 */     // GIR_Coverage, 13562,
     /*  823184 */     GIR_EraseRootFromParent_Done,
     /*  823185 */   // Label 13241: @823185
     /*  823185 */   GIM_Try, /*On fail goto*//*Label 13242*/ GIMT_Encode4(823240), // Rule ID 9316 //
     /*  823190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  823193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b8),
     /*  823198 */     // MIs[0] vaddr
     /*  823198 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823202 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823206 */     // MIs[0] dsaddr
     /*  823206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823214 */     // MIs[0] offset
     /*  823214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823217 */     // MIs[0] cpol
     /*  823217 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823220 */     // (intrinsic_void 2468:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8),
     /*  823223 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823225 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823227 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823229 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823231 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823238 */     GIR_RootConstrainSelectedInstOperands,
     /*  823239 */     // GIR_Coverage, 9316,
     /*  823239 */     GIR_EraseRootFromParent_Done,
     /*  823240 */   // Label 13242: @823240
     /*  823240 */   GIM_Try, /*On fail goto*//*Label 13243*/ GIMT_Encode4(823295), // Rule ID 9317 //
     /*  823245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  823248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b8),
     /*  823253 */     // MIs[0] vaddr
     /*  823253 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823257 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823261 */     // MIs[0] dsaddr
     /*  823261 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823269 */     // MIs[0] offset
     /*  823269 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823272 */     // MIs[0] cpol
     /*  823272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823275 */     // (intrinsic_void 2468:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8),
     /*  823278 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823280 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823282 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823284 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823286 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823293 */     GIR_RootConstrainSelectedInstOperands,
     /*  823294 */     // GIR_Coverage, 9317,
     /*  823294 */     GIR_EraseRootFromParent_Done,
     /*  823295 */   // Label 13243: @823295
     /*  823295 */   GIM_Try, /*On fail goto*//*Label 13244*/ GIMT_Encode4(823350), // Rule ID 9318 //
     /*  823300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  823303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b8),
     /*  823308 */     // MIs[0] vaddr
     /*  823308 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823312 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823316 */     // MIs[0] dsaddr
     /*  823316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823320 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823324 */     // MIs[0] offset
     /*  823324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823327 */     // MIs[0] cpol
     /*  823327 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823330 */     // (intrinsic_void 2468:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8),
     /*  823333 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823335 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823337 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823339 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823341 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823348 */     GIR_RootConstrainSelectedInstOperands,
     /*  823349 */     // GIR_Coverage, 9318,
     /*  823349 */     GIR_EraseRootFromParent_Done,
     /*  823350 */   // Label 13244: @823350
     /*  823350 */   GIM_Try, /*On fail goto*//*Label 13245*/ GIMT_Encode4(823405), // Rule ID 9319 //
     /*  823355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  823358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b8),
     /*  823363 */     // MIs[0] vaddr
     /*  823363 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823367 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823371 */     // MIs[0] dsaddr
     /*  823371 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823379 */     // MIs[0] offset
     /*  823379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823382 */     // MIs[0] cpol
     /*  823382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823385 */     // (intrinsic_void 2468:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8),
     /*  823388 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823390 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823392 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823394 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823396 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823399 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823403 */     GIR_RootConstrainSelectedInstOperands,
     /*  823404 */     // GIR_Coverage, 9319,
     /*  823404 */     GIR_EraseRootFromParent_Done,
     /*  823405 */   // Label 13245: @823405
     /*  823405 */   GIM_Try, /*On fail goto*//*Label 13246*/ GIMT_Encode4(823460), // Rule ID 9320 //
     /*  823410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  823413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b8),
     /*  823418 */     // MIs[0] vaddr
     /*  823418 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823422 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823426 */     // MIs[0] dsaddr
     /*  823426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823434 */     // MIs[0] offset
     /*  823434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823437 */     // MIs[0] cpol
     /*  823437 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823440 */     // (intrinsic_void 2468:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B8),
     /*  823443 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823445 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823447 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823449 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823451 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823454 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823458 */     GIR_RootConstrainSelectedInstOperands,
     /*  823459 */     // GIR_Coverage, 9320,
     /*  823459 */     GIR_EraseRootFromParent_Done,
     /*  823460 */   // Label 13246: @823460
     /*  823460 */   GIM_Try, /*On fail goto*//*Label 13247*/ GIMT_Encode4(823515), // Rule ID 9322 //
     /*  823465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  823468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b8),
     /*  823473 */     // MIs[0] vaddr
     /*  823473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823481 */     // MIs[0] dsaddr
     /*  823481 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823485 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823489 */     // MIs[0] offset
     /*  823489 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823492 */     // MIs[0] cpol
     /*  823492 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823495 */     // (intrinsic_void 2481:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8),
     /*  823498 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823500 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823502 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823504 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823506 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823513 */     GIR_RootConstrainSelectedInstOperands,
     /*  823514 */     // GIR_Coverage, 9322,
     /*  823514 */     GIR_EraseRootFromParent_Done,
     /*  823515 */   // Label 13247: @823515
     /*  823515 */   GIM_Try, /*On fail goto*//*Label 13248*/ GIMT_Encode4(823570), // Rule ID 9323 //
     /*  823520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  823523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b8),
     /*  823528 */     // MIs[0] vaddr
     /*  823528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823532 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823536 */     // MIs[0] dsaddr
     /*  823536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823544 */     // MIs[0] offset
     /*  823544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823547 */     // MIs[0] cpol
     /*  823547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823550 */     // (intrinsic_void 2481:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8),
     /*  823553 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823555 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823557 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823559 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823561 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823564 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823568 */     GIR_RootConstrainSelectedInstOperands,
     /*  823569 */     // GIR_Coverage, 9323,
     /*  823569 */     GIR_EraseRootFromParent_Done,
     /*  823570 */   // Label 13248: @823570
     /*  823570 */   GIM_Try, /*On fail goto*//*Label 13249*/ GIMT_Encode4(823625), // Rule ID 9324 //
     /*  823575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  823578 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b8),
     /*  823583 */     // MIs[0] vaddr
     /*  823583 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823587 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823591 */     // MIs[0] dsaddr
     /*  823591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823599 */     // MIs[0] offset
     /*  823599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823602 */     // MIs[0] cpol
     /*  823602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823605 */     // (intrinsic_void 2481:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8),
     /*  823608 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823610 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823612 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823614 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823616 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823619 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823623 */     GIR_RootConstrainSelectedInstOperands,
     /*  823624 */     // GIR_Coverage, 9324,
     /*  823624 */     GIR_EraseRootFromParent_Done,
     /*  823625 */   // Label 13249: @823625
     /*  823625 */   GIM_Try, /*On fail goto*//*Label 13250*/ GIMT_Encode4(823680), // Rule ID 9325 //
     /*  823630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  823633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b8),
     /*  823638 */     // MIs[0] vaddr
     /*  823638 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823642 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823646 */     // MIs[0] dsaddr
     /*  823646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823654 */     // MIs[0] offset
     /*  823654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823657 */     // MIs[0] cpol
     /*  823657 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823660 */     // (intrinsic_void 2481:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8),
     /*  823663 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823665 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823667 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823669 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823671 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823678 */     GIR_RootConstrainSelectedInstOperands,
     /*  823679 */     // GIR_Coverage, 9325,
     /*  823679 */     GIR_EraseRootFromParent_Done,
     /*  823680 */   // Label 13250: @823680
     /*  823680 */   GIM_Try, /*On fail goto*//*Label 13251*/ GIMT_Encode4(823735), // Rule ID 9326 //
     /*  823685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  823688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b8),
     /*  823693 */     // MIs[0] vaddr
     /*  823693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823697 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823701 */     // MIs[0] dsaddr
     /*  823701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823709 */     // MIs[0] offset
     /*  823709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823712 */     // MIs[0] cpol
     /*  823712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823715 */     // (intrinsic_void 2481:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B8 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B8),
     /*  823718 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823720 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823722 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823724 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823726 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823733 */     GIR_RootConstrainSelectedInstOperands,
     /*  823734 */     // GIR_Coverage, 9326,
     /*  823734 */     GIR_EraseRootFromParent_Done,
     /*  823735 */   // Label 13251: @823735
     /*  823735 */   GIM_Try, /*On fail goto*//*Label 13252*/ GIMT_Encode4(823790), // Rule ID 13527 //
     /*  823740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  823743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b32),
     /*  823748 */     // MIs[0] vaddr
     /*  823748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823752 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823756 */     // MIs[0] dsaddr
     /*  823756 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823760 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823764 */     // MIs[0] offset
     /*  823764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823767 */     // MIs[0] cpol
     /*  823767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823770 */     // (intrinsic_void 2466:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32),
     /*  823773 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823775 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823777 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823779 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823781 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823788 */     GIR_RootConstrainSelectedInstOperands,
     /*  823789 */     // GIR_Coverage, 13527,
     /*  823789 */     GIR_EraseRootFromParent_Done,
     /*  823790 */   // Label 13252: @823790
     /*  823790 */   GIM_Try, /*On fail goto*//*Label 13253*/ GIMT_Encode4(823845), // Rule ID 13528 //
     /*  823795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  823798 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b32),
     /*  823803 */     // MIs[0] vaddr
     /*  823803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823807 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823811 */     // MIs[0] dsaddr
     /*  823811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823819 */     // MIs[0] offset
     /*  823819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823822 */     // MIs[0] cpol
     /*  823822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823825 */     // (intrinsic_void 2466:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32),
     /*  823828 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823830 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823832 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823834 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823836 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823839 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823843 */     GIR_RootConstrainSelectedInstOperands,
     /*  823844 */     // GIR_Coverage, 13528,
     /*  823844 */     GIR_EraseRootFromParent_Done,
     /*  823845 */   // Label 13253: @823845
     /*  823845 */   GIM_Try, /*On fail goto*//*Label 13254*/ GIMT_Encode4(823900), // Rule ID 13529 //
     /*  823850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  823853 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b32),
     /*  823858 */     // MIs[0] vaddr
     /*  823858 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823862 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823866 */     // MIs[0] dsaddr
     /*  823866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823874 */     // MIs[0] offset
     /*  823874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823877 */     // MIs[0] cpol
     /*  823877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823880 */     // (intrinsic_void 2466:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32),
     /*  823883 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823885 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823887 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823889 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823891 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823894 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823898 */     GIR_RootConstrainSelectedInstOperands,
     /*  823899 */     // GIR_Coverage, 13529,
     /*  823899 */     GIR_EraseRootFromParent_Done,
     /*  823900 */   // Label 13254: @823900
     /*  823900 */   GIM_Try, /*On fail goto*//*Label 13255*/ GIMT_Encode4(823955), // Rule ID 13530 //
     /*  823905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  823908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b32),
     /*  823913 */     // MIs[0] vaddr
     /*  823913 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823917 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823921 */     // MIs[0] dsaddr
     /*  823921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823929 */     // MIs[0] offset
     /*  823929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823932 */     // MIs[0] cpol
     /*  823932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823935 */     // (intrinsic_void 2466:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32),
     /*  823938 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823940 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823942 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823944 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  823946 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  823949 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  823953 */     GIR_RootConstrainSelectedInstOperands,
     /*  823954 */     // GIR_Coverage, 13530,
     /*  823954 */     GIR_EraseRootFromParent_Done,
     /*  823955 */   // Label 13255: @823955
     /*  823955 */   GIM_Try, /*On fail goto*//*Label 13256*/ GIMT_Encode4(824010), // Rule ID 13531 //
     /*  823960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  823963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b32),
     /*  823968 */     // MIs[0] vaddr
     /*  823968 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  823972 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  823976 */     // MIs[0] dsaddr
     /*  823976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  823980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  823984 */     // MIs[0] offset
     /*  823984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  823987 */     // MIs[0] cpol
     /*  823987 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  823990 */     // (intrinsic_void 2466:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  823990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B32),
     /*  823993 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  823995 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  823997 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  823999 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824001 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824004 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824008 */     GIR_RootConstrainSelectedInstOperands,
     /*  824009 */     // GIR_Coverage, 13531,
     /*  824009 */     GIR_EraseRootFromParent_Done,
     /*  824010 */   // Label 13256: @824010
     /*  824010 */   GIM_Try, /*On fail goto*//*Label 13257*/ GIMT_Encode4(824065), // Rule ID 13533 //
     /*  824015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  824018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b64),
     /*  824023 */     // MIs[0] vaddr
     /*  824023 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824027 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824031 */     // MIs[0] dsaddr
     /*  824031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824039 */     // MIs[0] offset
     /*  824039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824042 */     // MIs[0] cpol
     /*  824042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824045 */     // (intrinsic_void 2467:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64),
     /*  824048 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824050 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824052 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824054 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824056 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824063 */     GIR_RootConstrainSelectedInstOperands,
     /*  824064 */     // GIR_Coverage, 13533,
     /*  824064 */     GIR_EraseRootFromParent_Done,
     /*  824065 */   // Label 13257: @824065
     /*  824065 */   GIM_Try, /*On fail goto*//*Label 13258*/ GIMT_Encode4(824120), // Rule ID 13534 //
     /*  824070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  824073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b64),
     /*  824078 */     // MIs[0] vaddr
     /*  824078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824082 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824086 */     // MIs[0] dsaddr
     /*  824086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824090 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824094 */     // MIs[0] offset
     /*  824094 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824097 */     // MIs[0] cpol
     /*  824097 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824100 */     // (intrinsic_void 2467:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64),
     /*  824103 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824105 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824107 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824109 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824111 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824114 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824118 */     GIR_RootConstrainSelectedInstOperands,
     /*  824119 */     // GIR_Coverage, 13534,
     /*  824119 */     GIR_EraseRootFromParent_Done,
     /*  824120 */   // Label 13258: @824120
     /*  824120 */   GIM_Try, /*On fail goto*//*Label 13259*/ GIMT_Encode4(824175), // Rule ID 13535 //
     /*  824125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  824128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b64),
     /*  824133 */     // MIs[0] vaddr
     /*  824133 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824137 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824141 */     // MIs[0] dsaddr
     /*  824141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824149 */     // MIs[0] offset
     /*  824149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824152 */     // MIs[0] cpol
     /*  824152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824155 */     // (intrinsic_void 2467:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64),
     /*  824158 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824160 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824162 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824164 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824166 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824173 */     GIR_RootConstrainSelectedInstOperands,
     /*  824174 */     // GIR_Coverage, 13535,
     /*  824174 */     GIR_EraseRootFromParent_Done,
     /*  824175 */   // Label 13259: @824175
     /*  824175 */   GIM_Try, /*On fail goto*//*Label 13260*/ GIMT_Encode4(824230), // Rule ID 13536 //
     /*  824180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  824183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b64),
     /*  824188 */     // MIs[0] vaddr
     /*  824188 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824192 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824196 */     // MIs[0] dsaddr
     /*  824196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824200 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824204 */     // MIs[0] offset
     /*  824204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824207 */     // MIs[0] cpol
     /*  824207 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824210 */     // (intrinsic_void 2467:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64),
     /*  824213 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824215 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824217 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824219 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824221 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824224 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824228 */     GIR_RootConstrainSelectedInstOperands,
     /*  824229 */     // GIR_Coverage, 13536,
     /*  824229 */     GIR_EraseRootFromParent_Done,
     /*  824230 */   // Label 13260: @824230
     /*  824230 */   GIM_Try, /*On fail goto*//*Label 13261*/ GIMT_Encode4(824285), // Rule ID 13537 //
     /*  824235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  824238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b64),
     /*  824243 */     // MIs[0] vaddr
     /*  824243 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824247 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824251 */     // MIs[0] dsaddr
     /*  824251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824259 */     // MIs[0] offset
     /*  824259 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824262 */     // MIs[0] cpol
     /*  824262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824265 */     // (intrinsic_void 2467:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B64),
     /*  824268 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824270 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824272 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824274 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824276 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824283 */     GIR_RootConstrainSelectedInstOperands,
     /*  824284 */     // GIR_Coverage, 13537,
     /*  824284 */     GIR_EraseRootFromParent_Done,
     /*  824285 */   // Label 13261: @824285
     /*  824285 */   GIM_Try, /*On fail goto*//*Label 13262*/ GIMT_Encode4(824340), // Rule ID 13539 //
     /*  824290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  824293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b128),
     /*  824298 */     // MIs[0] vaddr
     /*  824298 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824302 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824306 */     // MIs[0] dsaddr
     /*  824306 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824314 */     // MIs[0] offset
     /*  824314 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824317 */     // MIs[0] cpol
     /*  824317 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824320 */     // (intrinsic_void 2465:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128),
     /*  824323 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824325 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824327 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824329 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824331 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824334 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824338 */     GIR_RootConstrainSelectedInstOperands,
     /*  824339 */     // GIR_Coverage, 13539,
     /*  824339 */     GIR_EraseRootFromParent_Done,
     /*  824340 */   // Label 13262: @824340
     /*  824340 */   GIM_Try, /*On fail goto*//*Label 13263*/ GIMT_Encode4(824395), // Rule ID 13540 //
     /*  824345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  824348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b128),
     /*  824353 */     // MIs[0] vaddr
     /*  824353 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824357 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824361 */     // MIs[0] dsaddr
     /*  824361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824369 */     // MIs[0] offset
     /*  824369 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824372 */     // MIs[0] cpol
     /*  824372 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824375 */     // (intrinsic_void 2465:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128),
     /*  824378 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824380 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824382 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824384 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824386 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824389 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824393 */     GIR_RootConstrainSelectedInstOperands,
     /*  824394 */     // GIR_Coverage, 13540,
     /*  824394 */     GIR_EraseRootFromParent_Done,
     /*  824395 */   // Label 13263: @824395
     /*  824395 */   GIM_Try, /*On fail goto*//*Label 13264*/ GIMT_Encode4(824450), // Rule ID 13541 //
     /*  824400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  824403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b128),
     /*  824408 */     // MIs[0] vaddr
     /*  824408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824412 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824416 */     // MIs[0] dsaddr
     /*  824416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824420 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824424 */     // MIs[0] offset
     /*  824424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824427 */     // MIs[0] cpol
     /*  824427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824430 */     // (intrinsic_void 2465:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128),
     /*  824433 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824435 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824437 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824439 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824441 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824444 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824448 */     GIR_RootConstrainSelectedInstOperands,
     /*  824449 */     // GIR_Coverage, 13541,
     /*  824449 */     GIR_EraseRootFromParent_Done,
     /*  824450 */   // Label 13264: @824450
     /*  824450 */   GIM_Try, /*On fail goto*//*Label 13265*/ GIMT_Encode4(824505), // Rule ID 13542 //
     /*  824455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  824458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b128),
     /*  824463 */     // MIs[0] vaddr
     /*  824463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824467 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824471 */     // MIs[0] dsaddr
     /*  824471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824479 */     // MIs[0] offset
     /*  824479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824482 */     // MIs[0] cpol
     /*  824482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824485 */     // (intrinsic_void 2465:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128),
     /*  824488 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824490 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824492 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824494 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824496 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824503 */     GIR_RootConstrainSelectedInstOperands,
     /*  824504 */     // GIR_Coverage, 13542,
     /*  824504 */     GIR_EraseRootFromParent_Done,
     /*  824505 */   // Label 13265: @824505
     /*  824505 */   GIM_Try, /*On fail goto*//*Label 13266*/ GIMT_Encode4(824560), // Rule ID 13543 //
     /*  824510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  824513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_load_async_to_lds_b128),
     /*  824518 */     // MIs[0] vaddr
     /*  824518 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824522 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824526 */     // MIs[0] dsaddr
     /*  824526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824530 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824534 */     // MIs[0] offset
     /*  824534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824537 */     // MIs[0] cpol
     /*  824537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824540 */     // (intrinsic_void 2465:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_ASYNC_TO_LDS_B128),
     /*  824543 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824545 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824547 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824549 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824551 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824558 */     GIR_RootConstrainSelectedInstOperands,
     /*  824559 */     // GIR_Coverage, 13543,
     /*  824559 */     GIR_EraseRootFromParent_Done,
     /*  824560 */   // Label 13266: @824560
     /*  824560 */   GIM_Try, /*On fail goto*//*Label 13267*/ GIMT_Encode4(824615), // Rule ID 13545 //
     /*  824565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  824568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b32),
     /*  824573 */     // MIs[0] vaddr
     /*  824573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824577 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824581 */     // MIs[0] dsaddr
     /*  824581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824585 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824589 */     // MIs[0] offset
     /*  824589 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824592 */     // MIs[0] cpol
     /*  824592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824595 */     // (intrinsic_void 2479:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B32 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32),
     /*  824598 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824600 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824602 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824604 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824606 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824613 */     GIR_RootConstrainSelectedInstOperands,
     /*  824614 */     // GIR_Coverage, 13545,
     /*  824614 */     GIR_EraseRootFromParent_Done,
     /*  824615 */   // Label 13267: @824615
     /*  824615 */   GIM_Try, /*On fail goto*//*Label 13268*/ GIMT_Encode4(824670), // Rule ID 13546 //
     /*  824620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  824623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b32),
     /*  824628 */     // MIs[0] vaddr
     /*  824628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824632 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824636 */     // MIs[0] dsaddr
     /*  824636 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824640 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824644 */     // MIs[0] offset
     /*  824644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824647 */     // MIs[0] cpol
     /*  824647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824650 */     // (intrinsic_void 2479:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B32 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32),
     /*  824653 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824655 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824657 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824659 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824661 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824664 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824668 */     GIR_RootConstrainSelectedInstOperands,
     /*  824669 */     // GIR_Coverage, 13546,
     /*  824669 */     GIR_EraseRootFromParent_Done,
     /*  824670 */   // Label 13268: @824670
     /*  824670 */   GIM_Try, /*On fail goto*//*Label 13269*/ GIMT_Encode4(824725), // Rule ID 13547 //
     /*  824675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  824678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b32),
     /*  824683 */     // MIs[0] vaddr
     /*  824683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824687 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824691 */     // MIs[0] dsaddr
     /*  824691 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824699 */     // MIs[0] offset
     /*  824699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824702 */     // MIs[0] cpol
     /*  824702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824705 */     // (intrinsic_void 2479:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B32 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32),
     /*  824708 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824710 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824712 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824714 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824716 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824719 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824723 */     GIR_RootConstrainSelectedInstOperands,
     /*  824724 */     // GIR_Coverage, 13547,
     /*  824724 */     GIR_EraseRootFromParent_Done,
     /*  824725 */   // Label 13269: @824725
     /*  824725 */   GIM_Try, /*On fail goto*//*Label 13270*/ GIMT_Encode4(824780), // Rule ID 13548 //
     /*  824730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  824733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b32),
     /*  824738 */     // MIs[0] vaddr
     /*  824738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824742 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824746 */     // MIs[0] dsaddr
     /*  824746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824754 */     // MIs[0] offset
     /*  824754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824757 */     // MIs[0] cpol
     /*  824757 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824760 */     // (intrinsic_void 2479:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B32 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32),
     /*  824763 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824765 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824767 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824769 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824771 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824774 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824778 */     GIR_RootConstrainSelectedInstOperands,
     /*  824779 */     // GIR_Coverage, 13548,
     /*  824779 */     GIR_EraseRootFromParent_Done,
     /*  824780 */   // Label 13270: @824780
     /*  824780 */   GIM_Try, /*On fail goto*//*Label 13271*/ GIMT_Encode4(824835), // Rule ID 13549 //
     /*  824785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  824788 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b32),
     /*  824793 */     // MIs[0] vaddr
     /*  824793 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824797 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824801 */     // MIs[0] dsaddr
     /*  824801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824805 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824809 */     // MIs[0] offset
     /*  824809 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824812 */     // MIs[0] cpol
     /*  824812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824815 */     // (intrinsic_void 2479:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B32 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B32),
     /*  824818 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824820 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824822 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824824 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824826 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824833 */     GIR_RootConstrainSelectedInstOperands,
     /*  824834 */     // GIR_Coverage, 13549,
     /*  824834 */     GIR_EraseRootFromParent_Done,
     /*  824835 */   // Label 13271: @824835
     /*  824835 */   GIM_Try, /*On fail goto*//*Label 13272*/ GIMT_Encode4(824890), // Rule ID 13551 //
     /*  824840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  824843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b64),
     /*  824848 */     // MIs[0] vaddr
     /*  824848 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824852 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824856 */     // MIs[0] dsaddr
     /*  824856 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824860 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824864 */     // MIs[0] offset
     /*  824864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824867 */     // MIs[0] cpol
     /*  824867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824870 */     // (intrinsic_void 2480:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B64 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64),
     /*  824873 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824875 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824877 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824879 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824881 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824888 */     GIR_RootConstrainSelectedInstOperands,
     /*  824889 */     // GIR_Coverage, 13551,
     /*  824889 */     GIR_EraseRootFromParent_Done,
     /*  824890 */   // Label 13272: @824890
     /*  824890 */   GIM_Try, /*On fail goto*//*Label 13273*/ GIMT_Encode4(824945), // Rule ID 13552 //
     /*  824895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  824898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b64),
     /*  824903 */     // MIs[0] vaddr
     /*  824903 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824907 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824911 */     // MIs[0] dsaddr
     /*  824911 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824919 */     // MIs[0] offset
     /*  824919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824922 */     // MIs[0] cpol
     /*  824922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824925 */     // (intrinsic_void 2480:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B64 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64),
     /*  824928 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824930 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824932 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824934 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824936 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824939 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824943 */     GIR_RootConstrainSelectedInstOperands,
     /*  824944 */     // GIR_Coverage, 13552,
     /*  824944 */     GIR_EraseRootFromParent_Done,
     /*  824945 */   // Label 13273: @824945
     /*  824945 */   GIM_Try, /*On fail goto*//*Label 13274*/ GIMT_Encode4(825000), // Rule ID 13553 //
     /*  824950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  824953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b64),
     /*  824958 */     // MIs[0] vaddr
     /*  824958 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  824962 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  824966 */     // MIs[0] dsaddr
     /*  824966 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  824970 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  824974 */     // MIs[0] offset
     /*  824974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  824977 */     // MIs[0] cpol
     /*  824977 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  824980 */     // (intrinsic_void 2480:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B64 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  824980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64),
     /*  824983 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  824985 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  824987 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  824989 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  824991 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  824994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  824998 */     GIR_RootConstrainSelectedInstOperands,
     /*  824999 */     // GIR_Coverage, 13553,
     /*  824999 */     GIR_EraseRootFromParent_Done,
     /*  825000 */   // Label 13274: @825000
     /*  825000 */   GIM_Try, /*On fail goto*//*Label 13275*/ GIMT_Encode4(825055), // Rule ID 13554 //
     /*  825005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  825008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b64),
     /*  825013 */     // MIs[0] vaddr
     /*  825013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825017 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825021 */     // MIs[0] dsaddr
     /*  825021 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825025 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825029 */     // MIs[0] offset
     /*  825029 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825032 */     // MIs[0] cpol
     /*  825032 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825035 */     // (intrinsic_void 2480:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B64 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64),
     /*  825038 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825040 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825042 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825044 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825046 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825053 */     GIR_RootConstrainSelectedInstOperands,
     /*  825054 */     // GIR_Coverage, 13554,
     /*  825054 */     GIR_EraseRootFromParent_Done,
     /*  825055 */   // Label 13275: @825055
     /*  825055 */   GIM_Try, /*On fail goto*//*Label 13276*/ GIMT_Encode4(825110), // Rule ID 13555 //
     /*  825060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  825063 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b64),
     /*  825068 */     // MIs[0] vaddr
     /*  825068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825072 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825076 */     // MIs[0] dsaddr
     /*  825076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825084 */     // MIs[0] offset
     /*  825084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825087 */     // MIs[0] cpol
     /*  825087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825090 */     // (intrinsic_void 2480:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B64 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B64),
     /*  825093 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825095 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825097 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825099 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825101 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825104 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825108 */     GIR_RootConstrainSelectedInstOperands,
     /*  825109 */     // GIR_Coverage, 13555,
     /*  825109 */     GIR_EraseRootFromParent_Done,
     /*  825110 */   // Label 13276: @825110
     /*  825110 */   GIM_Try, /*On fail goto*//*Label 13277*/ GIMT_Encode4(825165), // Rule ID 13557 //
     /*  825115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  825118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b128),
     /*  825123 */     // MIs[0] vaddr
     /*  825123 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825131 */     // MIs[0] dsaddr
     /*  825131 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825135 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825139 */     // MIs[0] offset
     /*  825139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825142 */     // MIs[0] cpol
     /*  825142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825145 */     // (intrinsic_void 2478:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B128 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128),
     /*  825148 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825150 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825152 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825154 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825156 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825159 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825163 */     GIR_RootConstrainSelectedInstOperands,
     /*  825164 */     // GIR_Coverage, 13557,
     /*  825164 */     GIR_EraseRootFromParent_Done,
     /*  825165 */   // Label 13277: @825165
     /*  825165 */   GIM_Try, /*On fail goto*//*Label 13278*/ GIMT_Encode4(825220), // Rule ID 13558 //
     /*  825170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  825173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b128),
     /*  825178 */     // MIs[0] vaddr
     /*  825178 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825182 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825186 */     // MIs[0] dsaddr
     /*  825186 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825190 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825194 */     // MIs[0] offset
     /*  825194 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825197 */     // MIs[0] cpol
     /*  825197 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825200 */     // (intrinsic_void 2478:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B128 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128),
     /*  825203 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825205 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825207 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825209 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825211 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825218 */     GIR_RootConstrainSelectedInstOperands,
     /*  825219 */     // GIR_Coverage, 13558,
     /*  825219 */     GIR_EraseRootFromParent_Done,
     /*  825220 */   // Label 13278: @825220
     /*  825220 */   GIM_Try, /*On fail goto*//*Label 13279*/ GIMT_Encode4(825275), // Rule ID 13559 //
     /*  825225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  825228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b128),
     /*  825233 */     // MIs[0] vaddr
     /*  825233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825237 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825241 */     // MIs[0] dsaddr
     /*  825241 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825245 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825249 */     // MIs[0] offset
     /*  825249 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825252 */     // MIs[0] cpol
     /*  825252 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825255 */     // (intrinsic_void 2478:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B128 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128),
     /*  825258 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825260 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825262 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825264 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825266 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825269 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825273 */     GIR_RootConstrainSelectedInstOperands,
     /*  825274 */     // GIR_Coverage, 13559,
     /*  825274 */     GIR_EraseRootFromParent_Done,
     /*  825275 */   // Label 13279: @825275
     /*  825275 */   GIM_Try, /*On fail goto*//*Label 13280*/ GIMT_Encode4(825330), // Rule ID 13560 //
     /*  825280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  825283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b128),
     /*  825288 */     // MIs[0] vaddr
     /*  825288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825292 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825296 */     // MIs[0] dsaddr
     /*  825296 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825300 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825304 */     // MIs[0] offset
     /*  825304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825307 */     // MIs[0] cpol
     /*  825307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825310 */     // (intrinsic_void 2478:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B128 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128),
     /*  825313 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825315 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825317 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825319 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825321 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825328 */     GIR_RootConstrainSelectedInstOperands,
     /*  825329 */     // GIR_Coverage, 13560,
     /*  825329 */     GIR_EraseRootFromParent_Done,
     /*  825330 */   // Label 13280: @825330
     /*  825330 */   GIM_Try, /*On fail goto*//*Label 13281*/ GIMT_Encode4(825385), // Rule ID 13561 //
     /*  825335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  825338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_global_store_async_from_lds_b128),
     /*  825343 */     // MIs[0] vaddr
     /*  825343 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825351 */     // MIs[0] dsaddr
     /*  825351 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825355 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825359 */     // MIs[0] offset
     /*  825359 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825362 */     // MIs[0] cpol
     /*  825362 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825365 */     // (intrinsic_void 2478:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_STORE_ASYNC_FROM_LDS_B128 ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$dsaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_ASYNC_FROM_LDS_B128),
     /*  825368 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825370 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825372 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825374 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825376 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825379 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825383 */     GIR_RootConstrainSelectedInstOperands,
     /*  825384 */     // GIR_Coverage, 13561,
     /*  825384 */     GIR_EraseRootFromParent_Done,
     /*  825385 */   // Label 13281: @825385
     /*  825385 */   GIM_Reject,
     /*  825386 */ // Label 13233: @825386
     /*  825386 */ GIM_Try, /*On fail goto*//*Label 13282*/ GIMT_Encode4(827275),
     /*  825391 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /*  825394 */   GIM_Try, /*On fail goto*//*Label 13283*/ GIMT_Encode4(825484), // Rule ID 9315 //
     /*  825399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  825402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b8),
     /*  825407 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825410 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  825414 */     // MIs[0] dsaddr
     /*  825414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825418 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825422 */     // MIs[0] offset
     /*  825422 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825425 */     // MIs[0] Operand 4
     /*  825425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825428 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825432 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset_m0),
     /*  825439 */     // (intrinsic_void 2247:{ *:[iPTR] }, (GlobalSAddrNoIOffsetM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B8_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825439 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825443 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825449 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8_SADDR),
     /*  825456 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  825463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  825468 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  825475 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825482 */     GIR_RootConstrainSelectedInstOperands,
     /*  825483 */     // GIR_Coverage, 9315,
     /*  825483 */     GIR_EraseRootFromParent_Done,
     /*  825484 */   // Label 13283: @825484
     /*  825484 */   GIM_Try, /*On fail goto*//*Label 13284*/ GIMT_Encode4(825574), // Rule ID 13514 //
     /*  825489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  825492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b32),
     /*  825497 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825500 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  825504 */     // MIs[0] dsaddr
     /*  825504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825508 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825512 */     // MIs[0] offset
     /*  825512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825515 */     // MIs[0] Operand 4
     /*  825515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825518 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset_m0),
     /*  825529 */     // (intrinsic_void 2245:{ *:[iPTR] }, (GlobalSAddrNoIOffsetM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B32_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825529 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825533 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825539 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32_SADDR),
     /*  825546 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  825553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  825558 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  825565 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825572 */     GIR_RootConstrainSelectedInstOperands,
     /*  825573 */     // GIR_Coverage, 13514,
     /*  825573 */     GIR_EraseRootFromParent_Done,
     /*  825574 */   // Label 13284: @825574
     /*  825574 */   GIM_Try, /*On fail goto*//*Label 13285*/ GIMT_Encode4(825664), // Rule ID 13520 //
     /*  825579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  825582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b64),
     /*  825587 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  825594 */     // MIs[0] dsaddr
     /*  825594 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825602 */     // MIs[0] offset
     /*  825602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825605 */     // MIs[0] Operand 4
     /*  825605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825608 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825612 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset_m0),
     /*  825619 */     // (intrinsic_void 2246:{ *:[iPTR] }, (GlobalSAddrNoIOffsetM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B64_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825619 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825623 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825629 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64_SADDR),
     /*  825636 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  825643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  825648 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  825655 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825658 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825662 */     GIR_RootConstrainSelectedInstOperands,
     /*  825663 */     // GIR_Coverage, 13520,
     /*  825663 */     GIR_EraseRootFromParent_Done,
     /*  825664 */   // Label 13285: @825664
     /*  825664 */   GIM_Try, /*On fail goto*//*Label 13286*/ GIMT_Encode4(825754), // Rule ID 13526 //
     /*  825669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  825672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b128),
     /*  825677 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825680 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  825684 */     // MIs[0] dsaddr
     /*  825684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825688 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825692 */     // MIs[0] offset
     /*  825692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825695 */     // MIs[0] Operand 4
     /*  825695 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825698 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825702 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_no_ioffset_m0),
     /*  825709 */     // (intrinsic_void 2244:{ *:[iPTR] }, (GlobalSAddrNoIOffsetM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, CPol:{ *:[i32] }:$cpol), VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B128_SADDR ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825709 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825713 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825719 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128_SADDR),
     /*  825726 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  825733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  825738 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // cpol
     /*  825745 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825752 */     GIR_RootConstrainSelectedInstOperands,
     /*  825753 */     // GIR_Coverage, 13526,
     /*  825753 */     GIR_EraseRootFromParent_Done,
     /*  825754 */   // Label 13286: @825754
     /*  825754 */   GIM_Try, /*On fail goto*//*Label 13287*/ GIMT_Encode4(825830), // Rule ID 9310 //
     /*  825759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  825762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b8),
     /*  825767 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825770 */     // MIs[0] vaddr
     /*  825770 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825774 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825778 */     // MIs[0] dsaddr
     /*  825778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825782 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825786 */     // MIs[0] offset
     /*  825786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825789 */     // MIs[0] cpol
     /*  825789 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825792 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825796 */     // (intrinsic_void 2247:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825796 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825800 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825806 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8),
     /*  825813 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825815 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825817 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825819 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825821 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825824 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825828 */     GIR_RootConstrainSelectedInstOperands,
     /*  825829 */     // GIR_Coverage, 9310,
     /*  825829 */     GIR_EraseRootFromParent_Done,
     /*  825830 */   // Label 13287: @825830
     /*  825830 */   GIM_Try, /*On fail goto*//*Label 13288*/ GIMT_Encode4(825906), // Rule ID 9311 //
     /*  825835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  825838 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b8),
     /*  825843 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825846 */     // MIs[0] vaddr
     /*  825846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825850 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825854 */     // MIs[0] dsaddr
     /*  825854 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825858 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825862 */     // MIs[0] offset
     /*  825862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825865 */     // MIs[0] cpol
     /*  825865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825868 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825872 */     // (intrinsic_void 2247:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825872 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825876 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825882 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8),
     /*  825889 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825891 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825893 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825895 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825897 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825904 */     GIR_RootConstrainSelectedInstOperands,
     /*  825905 */     // GIR_Coverage, 9311,
     /*  825905 */     GIR_EraseRootFromParent_Done,
     /*  825906 */   // Label 13288: @825906
     /*  825906 */   GIM_Try, /*On fail goto*//*Label 13289*/ GIMT_Encode4(825982), // Rule ID 9312 //
     /*  825911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  825914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b8),
     /*  825919 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825922 */     // MIs[0] vaddr
     /*  825922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  825926 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  825930 */     // MIs[0] dsaddr
     /*  825930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  825934 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  825938 */     // MIs[0] offset
     /*  825938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  825941 */     // MIs[0] cpol
     /*  825941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  825944 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  825948 */     // (intrinsic_void 2247:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  825948 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  825952 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  825958 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  825962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8),
     /*  825965 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  825967 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  825969 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  825971 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  825973 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  825976 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  825980 */     GIR_RootConstrainSelectedInstOperands,
     /*  825981 */     // GIR_Coverage, 9312,
     /*  825981 */     GIR_EraseRootFromParent_Done,
     /*  825982 */   // Label 13289: @825982
     /*  825982 */   GIM_Try, /*On fail goto*//*Label 13290*/ GIMT_Encode4(826058), // Rule ID 9313 //
     /*  825987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  825990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b8),
     /*  825995 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  825998 */     // MIs[0] vaddr
     /*  825998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826002 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826006 */     // MIs[0] dsaddr
     /*  826006 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826014 */     // MIs[0] offset
     /*  826014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826017 */     // MIs[0] cpol
     /*  826017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826020 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826024 */     // (intrinsic_void 2247:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826024 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826028 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826034 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8),
     /*  826041 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826043 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826045 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826047 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826049 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826056 */     GIR_RootConstrainSelectedInstOperands,
     /*  826057 */     // GIR_Coverage, 9313,
     /*  826057 */     GIR_EraseRootFromParent_Done,
     /*  826058 */   // Label 13290: @826058
     /*  826058 */   GIM_Try, /*On fail goto*//*Label 13291*/ GIMT_Encode4(826134), // Rule ID 9314 //
     /*  826063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  826066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b8),
     /*  826071 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826074 */     // MIs[0] vaddr
     /*  826074 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826078 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826082 */     // MIs[0] dsaddr
     /*  826082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826086 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826090 */     // MIs[0] offset
     /*  826090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826093 */     // MIs[0] cpol
     /*  826093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826096 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826100 */     // (intrinsic_void 2247:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B8 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826100 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826104 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826110 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B8),
     /*  826117 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826119 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826121 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826123 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826125 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826128 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826132 */     GIR_RootConstrainSelectedInstOperands,
     /*  826133 */     // GIR_Coverage, 9314,
     /*  826133 */     GIR_EraseRootFromParent_Done,
     /*  826134 */   // Label 13291: @826134
     /*  826134 */   GIM_Try, /*On fail goto*//*Label 13292*/ GIMT_Encode4(826210), // Rule ID 13509 //
     /*  826139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  826142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b32),
     /*  826147 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826150 */     // MIs[0] vaddr
     /*  826150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826154 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826158 */     // MIs[0] dsaddr
     /*  826158 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826166 */     // MIs[0] offset
     /*  826166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826169 */     // MIs[0] cpol
     /*  826169 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826172 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826176 */     // (intrinsic_void 2245:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826176 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826180 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826186 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32),
     /*  826193 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826195 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826197 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826199 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826201 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826208 */     GIR_RootConstrainSelectedInstOperands,
     /*  826209 */     // GIR_Coverage, 13509,
     /*  826209 */     GIR_EraseRootFromParent_Done,
     /*  826210 */   // Label 13292: @826210
     /*  826210 */   GIM_Try, /*On fail goto*//*Label 13293*/ GIMT_Encode4(826286), // Rule ID 13510 //
     /*  826215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  826218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b32),
     /*  826223 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826226 */     // MIs[0] vaddr
     /*  826226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826230 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826234 */     // MIs[0] dsaddr
     /*  826234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826238 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826242 */     // MIs[0] offset
     /*  826242 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826245 */     // MIs[0] cpol
     /*  826245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826248 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826252 */     // (intrinsic_void 2245:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826252 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826256 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826262 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32),
     /*  826269 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826271 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826273 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826275 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826277 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826284 */     GIR_RootConstrainSelectedInstOperands,
     /*  826285 */     // GIR_Coverage, 13510,
     /*  826285 */     GIR_EraseRootFromParent_Done,
     /*  826286 */   // Label 13293: @826286
     /*  826286 */   GIM_Try, /*On fail goto*//*Label 13294*/ GIMT_Encode4(826362), // Rule ID 13511 //
     /*  826291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  826294 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b32),
     /*  826299 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826302 */     // MIs[0] vaddr
     /*  826302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826306 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826310 */     // MIs[0] dsaddr
     /*  826310 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826314 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826318 */     // MIs[0] offset
     /*  826318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826321 */     // MIs[0] cpol
     /*  826321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826324 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826328 */     // (intrinsic_void 2245:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826328 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826332 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826338 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32),
     /*  826345 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826347 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826349 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826351 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826353 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826356 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826360 */     GIR_RootConstrainSelectedInstOperands,
     /*  826361 */     // GIR_Coverage, 13511,
     /*  826361 */     GIR_EraseRootFromParent_Done,
     /*  826362 */   // Label 13294: @826362
     /*  826362 */   GIM_Try, /*On fail goto*//*Label 13295*/ GIMT_Encode4(826438), // Rule ID 13512 //
     /*  826367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  826370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b32),
     /*  826375 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826378 */     // MIs[0] vaddr
     /*  826378 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826382 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826386 */     // MIs[0] dsaddr
     /*  826386 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826390 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826394 */     // MIs[0] offset
     /*  826394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826397 */     // MIs[0] cpol
     /*  826397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826400 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826404 */     // (intrinsic_void 2245:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826404 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826408 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826414 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32),
     /*  826421 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826423 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826425 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826427 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826429 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826436 */     GIR_RootConstrainSelectedInstOperands,
     /*  826437 */     // GIR_Coverage, 13512,
     /*  826437 */     GIR_EraseRootFromParent_Done,
     /*  826438 */   // Label 13295: @826438
     /*  826438 */   GIM_Try, /*On fail goto*//*Label 13296*/ GIMT_Encode4(826514), // Rule ID 13513 //
     /*  826443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  826446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b32),
     /*  826451 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826454 */     // MIs[0] vaddr
     /*  826454 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826458 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826462 */     // MIs[0] dsaddr
     /*  826462 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826466 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826470 */     // MIs[0] offset
     /*  826470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826473 */     // MIs[0] cpol
     /*  826473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826476 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826480 */     // (intrinsic_void 2245:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B32 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826480 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826484 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826490 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B32),
     /*  826497 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826499 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826501 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826503 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826505 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826512 */     GIR_RootConstrainSelectedInstOperands,
     /*  826513 */     // GIR_Coverage, 13513,
     /*  826513 */     GIR_EraseRootFromParent_Done,
     /*  826514 */   // Label 13296: @826514
     /*  826514 */   GIM_Try, /*On fail goto*//*Label 13297*/ GIMT_Encode4(826590), // Rule ID 13515 //
     /*  826519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  826522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b64),
     /*  826527 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826530 */     // MIs[0] vaddr
     /*  826530 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826534 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826538 */     // MIs[0] dsaddr
     /*  826538 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826542 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826546 */     // MIs[0] offset
     /*  826546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826549 */     // MIs[0] cpol
     /*  826549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826552 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826556 */     // (intrinsic_void 2246:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826556 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826560 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826566 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64),
     /*  826573 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826575 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826577 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826579 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826581 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826584 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826588 */     GIR_RootConstrainSelectedInstOperands,
     /*  826589 */     // GIR_Coverage, 13515,
     /*  826589 */     GIR_EraseRootFromParent_Done,
     /*  826590 */   // Label 13297: @826590
     /*  826590 */   GIM_Try, /*On fail goto*//*Label 13298*/ GIMT_Encode4(826666), // Rule ID 13516 //
     /*  826595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  826598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b64),
     /*  826603 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826606 */     // MIs[0] vaddr
     /*  826606 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826610 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826614 */     // MIs[0] dsaddr
     /*  826614 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826618 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826622 */     // MIs[0] offset
     /*  826622 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826625 */     // MIs[0] cpol
     /*  826625 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826628 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826632 */     // (intrinsic_void 2246:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826632 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826636 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826642 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64),
     /*  826649 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826651 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826653 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826655 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826657 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826664 */     GIR_RootConstrainSelectedInstOperands,
     /*  826665 */     // GIR_Coverage, 13516,
     /*  826665 */     GIR_EraseRootFromParent_Done,
     /*  826666 */   // Label 13298: @826666
     /*  826666 */   GIM_Try, /*On fail goto*//*Label 13299*/ GIMT_Encode4(826742), // Rule ID 13517 //
     /*  826671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  826674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b64),
     /*  826679 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826682 */     // MIs[0] vaddr
     /*  826682 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826686 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826690 */     // MIs[0] dsaddr
     /*  826690 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826694 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826698 */     // MIs[0] offset
     /*  826698 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826701 */     // MIs[0] cpol
     /*  826701 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826704 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826708 */     // (intrinsic_void 2246:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826708 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826712 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826718 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64),
     /*  826725 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826727 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826729 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826731 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826733 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826740 */     GIR_RootConstrainSelectedInstOperands,
     /*  826741 */     // GIR_Coverage, 13517,
     /*  826741 */     GIR_EraseRootFromParent_Done,
     /*  826742 */   // Label 13299: @826742
     /*  826742 */   GIM_Try, /*On fail goto*//*Label 13300*/ GIMT_Encode4(826818), // Rule ID 13518 //
     /*  826747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  826750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b64),
     /*  826755 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826758 */     // MIs[0] vaddr
     /*  826758 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826762 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826766 */     // MIs[0] dsaddr
     /*  826766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826774 */     // MIs[0] offset
     /*  826774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826777 */     // MIs[0] cpol
     /*  826777 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826780 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826784 */     // (intrinsic_void 2246:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826784 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826788 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826794 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64),
     /*  826801 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826803 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826805 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826807 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826809 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826812 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826816 */     GIR_RootConstrainSelectedInstOperands,
     /*  826817 */     // GIR_Coverage, 13518,
     /*  826817 */     GIR_EraseRootFromParent_Done,
     /*  826818 */   // Label 13300: @826818
     /*  826818 */   GIM_Try, /*On fail goto*//*Label 13301*/ GIMT_Encode4(826894), // Rule ID 13519 //
     /*  826823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  826826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b64),
     /*  826831 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826834 */     // MIs[0] vaddr
     /*  826834 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826838 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826842 */     // MIs[0] dsaddr
     /*  826842 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826850 */     // MIs[0] offset
     /*  826850 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826853 */     // MIs[0] cpol
     /*  826853 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826856 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826860 */     // (intrinsic_void 2246:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B64 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826860 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826864 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826870 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B64),
     /*  826877 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826879 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826881 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826883 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826885 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826892 */     GIR_RootConstrainSelectedInstOperands,
     /*  826893 */     // GIR_Coverage, 13519,
     /*  826893 */     GIR_EraseRootFromParent_Done,
     /*  826894 */   // Label 13301: @826894
     /*  826894 */   GIM_Try, /*On fail goto*//*Label 13302*/ GIMT_Encode4(826970), // Rule ID 13521 //
     /*  826899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  826902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b128),
     /*  826907 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826910 */     // MIs[0] vaddr
     /*  826910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826914 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826918 */     // MIs[0] dsaddr
     /*  826918 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826922 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  826926 */     // MIs[0] offset
     /*  826926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  826929 */     // MIs[0] cpol
     /*  826929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  826932 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  826936 */     // (intrinsic_void 2244:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  826936 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  826940 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  826946 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  826950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128),
     /*  826953 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  826955 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  826957 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  826959 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  826961 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  826964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  826968 */     GIR_RootConstrainSelectedInstOperands,
     /*  826969 */     // GIR_Coverage, 13521,
     /*  826969 */     GIR_EraseRootFromParent_Done,
     /*  826970 */   // Label 13302: @826970
     /*  826970 */   GIM_Try, /*On fail goto*//*Label 13303*/ GIMT_Encode4(827046), // Rule ID 13522 //
     /*  826975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  826978 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b128),
     /*  826983 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  826986 */     // MIs[0] vaddr
     /*  826986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  826990 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  826994 */     // MIs[0] dsaddr
     /*  826994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  826998 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827002 */     // MIs[0] offset
     /*  827002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  827005 */     // MIs[0] cpol
     /*  827005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  827008 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  827012 */     // (intrinsic_void 2244:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  827012 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  827016 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827022 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  827026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128),
     /*  827029 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  827031 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  827033 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  827035 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  827037 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  827040 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827044 */     GIR_RootConstrainSelectedInstOperands,
     /*  827045 */     // GIR_Coverage, 13522,
     /*  827045 */     GIR_EraseRootFromParent_Done,
     /*  827046 */   // Label 13303: @827046
     /*  827046 */   GIM_Try, /*On fail goto*//*Label 13304*/ GIMT_Encode4(827122), // Rule ID 13523 //
     /*  827051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  827054 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b128),
     /*  827059 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827062 */     // MIs[0] vaddr
     /*  827062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  827066 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  827070 */     // MIs[0] dsaddr
     /*  827070 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  827074 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827078 */     // MIs[0] offset
     /*  827078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  827081 */     // MIs[0] cpol
     /*  827081 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  827084 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  827088 */     // (intrinsic_void 2244:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  827088 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  827092 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827098 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  827102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128),
     /*  827105 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  827107 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  827109 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  827111 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  827113 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  827116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827120 */     GIR_RootConstrainSelectedInstOperands,
     /*  827121 */     // GIR_Coverage, 13523,
     /*  827121 */     GIR_EraseRootFromParent_Done,
     /*  827122 */   // Label 13304: @827122
     /*  827122 */   GIM_Try, /*On fail goto*//*Label 13305*/ GIMT_Encode4(827198), // Rule ID 13524 //
     /*  827127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  827130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b128),
     /*  827135 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827138 */     // MIs[0] vaddr
     /*  827138 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  827142 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  827146 */     // MIs[0] dsaddr
     /*  827146 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  827150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827154 */     // MIs[0] offset
     /*  827154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  827157 */     // MIs[0] cpol
     /*  827157 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  827160 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  827164 */     // (intrinsic_void 2244:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  827164 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  827168 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827174 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  827178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128),
     /*  827181 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  827183 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  827185 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  827187 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  827189 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  827192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827196 */     GIR_RootConstrainSelectedInstOperands,
     /*  827197 */     // GIR_Coverage, 13524,
     /*  827197 */     GIR_EraseRootFromParent_Done,
     /*  827198 */   // Label 13305: @827198
     /*  827198 */   GIM_Try, /*On fail goto*//*Label 13306*/ GIMT_Encode4(827274), // Rule ID 13525 //
     /*  827203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  827206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_async_to_lds_b128),
     /*  827211 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827214 */     // MIs[0] vaddr
     /*  827214 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /*  827218 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  827222 */     // MIs[0] dsaddr
     /*  827222 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
     /*  827226 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827230 */     // MIs[0] offset
     /*  827230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  827233 */     // MIs[0] cpol
     /*  827233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  827236 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  827240 */     // (intrinsic_void 2244:{ *:[iPTR] }, VReg_64:{ *:[i64] }:$vaddr, VGPR_32:{ *:[i32] }:$dsaddr, (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_ASYNC_TO_LDS_B128 ?:{ *:[i32] }:$dsaddr, ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  827240 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  827244 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827250 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
     /*  827254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_ASYNC_TO_LDS_B128),
     /*  827257 */     GIR_RootToRootCopy, /*OpIdx*/2, // dsaddr
     /*  827259 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr
     /*  827261 */     GIR_RootToRootCopy, /*OpIdx*/3, // offset
     /*  827263 */     GIR_RootToRootCopy, /*OpIdx*/4, // cpol
     /*  827265 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  827268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827272 */     GIR_RootConstrainSelectedInstOperands,
     /*  827273 */     // GIR_Coverage, 13525,
     /*  827273 */     GIR_EraseRootFromParent_Done,
     /*  827274 */   // Label 13306: @827274
     /*  827274 */   GIM_Reject,
     /*  827275 */ // Label 13282: @827275
     /*  827275 */ GIM_Try, /*On fail goto*//*Label 13307*/ GIMT_Encode4(827609),
     /*  827280 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
     /*  827283 */   GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_compr),
     /*  827288 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  827291 */   GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  827294 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  827297 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  827300 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827304 */   GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827308 */   GIM_Try, /*On fail goto*//*Label 13308*/ GIMT_Encode4(827383), // Rule ID 27289 //
     /*  827313 */     // MIs[0] Operand 5
     /*  827313 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  827324 */     // MIs[0] vm
     /*  827324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  827327 */     // (intrinsic_void 2439:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827327 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  827330 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827334 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827339 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  827341 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  827344 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827348 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827353 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  827355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
     /*  827358 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827360 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827362 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827364 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  827367 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  827370 */     GIR_RootToRootCopy, /*OpIdx*/6, // vm
     /*  827372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  827375 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827381 */     GIR_RootConstrainSelectedInstOperands,
     /*  827382 */     // GIR_Coverage, 27289,
     /*  827382 */     GIR_EraseRootFromParent_Done,
     /*  827383 */   // Label 13308: @827383
     /*  827383 */   GIM_Try, /*On fail goto*//*Label 13309*/ GIMT_Encode4(827458), // Rule ID 27290 //
     /*  827388 */     // MIs[0] Operand 5
     /*  827388 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  827399 */     // MIs[0] vm
     /*  827399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  827402 */     // (intrinsic_void 2439:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827402 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  827405 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827409 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827414 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  827416 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  827419 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827423 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827428 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  827430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
     /*  827433 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827435 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827437 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827439 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  827442 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  827445 */     GIR_RootToRootCopy, /*OpIdx*/6, // vm
     /*  827447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  827450 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827456 */     GIR_RootConstrainSelectedInstOperands,
     /*  827457 */     // GIR_Coverage, 27290,
     /*  827457 */     GIR_EraseRootFromParent_Done,
     /*  827458 */   // Label 13309: @827458
     /*  827458 */   GIM_Try, /*On fail goto*//*Label 13310*/ GIMT_Encode4(827533), // Rule ID 27291 //
     /*  827463 */     // MIs[0] Operand 5
     /*  827463 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  827474 */     // MIs[0] vm
     /*  827474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  827477 */     // (intrinsic_void 2439:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827477 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  827480 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827484 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827489 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  827491 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  827494 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827498 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827503 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  827505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
     /*  827508 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827510 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827512 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827514 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  827517 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  827520 */     GIR_RootToRootCopy, /*OpIdx*/6, // vm
     /*  827522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  827525 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827527 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827531 */     GIR_RootConstrainSelectedInstOperands,
     /*  827532 */     // GIR_Coverage, 27291,
     /*  827532 */     GIR_EraseRootFromParent_Done,
     /*  827533 */   // Label 13310: @827533
     /*  827533 */   GIM_Try, /*On fail goto*//*Label 13311*/ GIMT_Encode4(827608), // Rule ID 27292 //
     /*  827538 */     // MIs[0] Operand 5
     /*  827538 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(18446744073709551615u),
     /*  827549 */     // MIs[0] vm
     /*  827549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  827552 */     // (intrinsic_void 2439:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827552 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  827555 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827559 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827564 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  827566 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  827569 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  827573 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  827578 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  827580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
     /*  827583 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827585 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827587 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827589 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  827592 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  827595 */     GIR_RootToRootCopy, /*OpIdx*/6, // vm
     /*  827597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  827600 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827602 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827606 */     GIR_RootConstrainSelectedInstOperands,
     /*  827607 */     // GIR_Coverage, 27292,
     /*  827607 */     GIR_EraseRootFromParent_Done,
     /*  827608 */   // Label 13311: @827608
     /*  827608 */   GIM_Reject,
     /*  827609 */ // Label 13307: @827609
     /*  827609 */ GIM_Try, /*On fail goto*//*Label 13312*/ GIMT_Encode4(828366),
     /*  827614 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
     /*  827617 */   GIM_Try, /*On fail goto*//*Label 13313*/ GIMT_Encode4(827701), // Rule ID 27281 //
     /*  827622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
     /*  827627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  827630 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  827633 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827636 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  827639 */     // MIs[0] tgt
     /*  827639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  827642 */     // MIs[0] en
     /*  827642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  827645 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827649 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827653 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827657 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827661 */     // MIs[0] Operand 7
     /*  827661 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
     /*  827672 */     // MIs[0] vm
     /*  827672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  827675 */     // (intrinsic_void 2438:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
     /*  827678 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827680 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827682 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827684 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  827686 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  827688 */     GIR_RootToRootCopy, /*OpIdx*/8, // vm
     /*  827690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  827693 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827695 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827699 */     GIR_RootConstrainSelectedInstOperands,
     /*  827700 */     // GIR_Coverage, 27281,
     /*  827700 */     GIR_EraseRootFromParent_Done,
     /*  827701 */   // Label 13313: @827701
     /*  827701 */   GIM_Try, /*On fail goto*//*Label 13314*/ GIMT_Encode4(827785), // Rule ID 27282 //
     /*  827706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
     /*  827711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  827714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  827717 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827720 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  827723 */     // MIs[0] tgt
     /*  827723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  827726 */     // MIs[0] en
     /*  827726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  827729 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827733 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827737 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827741 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827745 */     // MIs[0] Operand 7
     /*  827745 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(18446744073709551615u),
     /*  827756 */     // MIs[0] vm
     /*  827756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  827759 */     // (intrinsic_void 2438:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
     /*  827762 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827764 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827766 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827768 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  827770 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  827772 */     GIR_RootToRootCopy, /*OpIdx*/8, // vm
     /*  827774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  827777 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827779 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827783 */     GIR_RootConstrainSelectedInstOperands,
     /*  827784 */     // GIR_Coverage, 27282,
     /*  827784 */     GIR_EraseRootFromParent_Done,
     /*  827785 */   // Label 13314: @827785
     /*  827785 */   GIM_Try, /*On fail goto*//*Label 13315*/ GIMT_Encode4(827869), // Rule ID 27283 //
     /*  827790 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
     /*  827795 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  827798 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  827801 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827804 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  827807 */     // MIs[0] tgt
     /*  827807 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  827810 */     // MIs[0] en
     /*  827810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  827813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827817 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827821 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827825 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827829 */     // MIs[0] Operand 7
     /*  827829 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
     /*  827840 */     // MIs[0] vm
     /*  827840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  827843 */     // (intrinsic_void 2438:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
     /*  827846 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827848 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827850 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827852 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  827854 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  827856 */     GIR_RootToRootCopy, /*OpIdx*/8, // vm
     /*  827858 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  827861 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827863 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827867 */     GIR_RootConstrainSelectedInstOperands,
     /*  827868 */     // GIR_Coverage, 27283,
     /*  827868 */     GIR_EraseRootFromParent_Done,
     /*  827869 */   // Label 13315: @827869
     /*  827869 */   GIM_Try, /*On fail goto*//*Label 13316*/ GIMT_Encode4(827953), // Rule ID 27284 //
     /*  827874 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
     /*  827879 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  827882 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  827885 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827888 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  827891 */     // MIs[0] tgt
     /*  827891 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  827894 */     // MIs[0] en
     /*  827894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  827897 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827901 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827905 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827909 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827913 */     // MIs[0] Operand 7
     /*  827913 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(18446744073709551615u),
     /*  827924 */     // MIs[0] vm
     /*  827924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  827927 */     // (intrinsic_void 2438:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  827927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
     /*  827930 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  827932 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  827934 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  827936 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  827938 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  827940 */     GIR_RootToRootCopy, /*OpIdx*/8, // vm
     /*  827942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  827945 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  827947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  827951 */     GIR_RootConstrainSelectedInstOperands,
     /*  827952 */     // GIR_Coverage, 27284,
     /*  827952 */     GIR_EraseRootFromParent_Done,
     /*  827953 */   // Label 13316: @827953
     /*  827953 */   GIM_Try, /*On fail goto*//*Label 13317*/ GIMT_Encode4(828056), // Rule ID 27285 //
     /*  827958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
     /*  827963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  827966 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  827969 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  827972 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  827975 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  827978 */     // MIs[0] tgt
     /*  827978 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  827981 */     // MIs[0] en
     /*  827981 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  827984 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827988 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827992 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  827996 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828000 */     // MIs[0] Operand 7
     /*  828000 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
     /*  828011 */     GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  828015 */     // (intrinsic_void 2440:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  828015 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  828019 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  828025 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
     /*  828029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW),
     /*  828032 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  828034 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  828036 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  828038 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  828040 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  828042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828048 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  828050 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  828054 */     GIR_RootConstrainSelectedInstOperands,
     /*  828055 */     // GIR_Coverage, 27285,
     /*  828055 */     GIR_EraseRootFromParent_Done,
     /*  828056 */   // Label 13317: @828056
     /*  828056 */   GIM_Try, /*On fail goto*//*Label 13318*/ GIMT_Encode4(828159), // Rule ID 27286 //
     /*  828061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
     /*  828066 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  828069 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  828072 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  828075 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  828078 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  828081 */     // MIs[0] tgt
     /*  828081 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  828084 */     // MIs[0] en
     /*  828084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  828087 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828091 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828095 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828099 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828103 */     // MIs[0] Operand 7
     /*  828103 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(18446744073709551615u),
     /*  828114 */     GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  828118 */     // (intrinsic_void 2440:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, -1:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  828118 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  828122 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  828128 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
     /*  828132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW_DONE),
     /*  828135 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  828137 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  828139 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  828141 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  828143 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  828145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828151 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  828153 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  828157 */     GIR_RootConstrainSelectedInstOperands,
     /*  828158 */     // GIR_Coverage, 27286,
     /*  828158 */     GIR_EraseRootFromParent_Done,
     /*  828159 */   // Label 13318: @828159
     /*  828159 */   GIM_Try, /*On fail goto*//*Label 13319*/ GIMT_Encode4(828262), // Rule ID 27287 //
     /*  828164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
     /*  828169 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  828172 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  828175 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  828178 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  828181 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  828184 */     // MIs[0] tgt
     /*  828184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  828187 */     // MIs[0] en
     /*  828187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  828190 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828194 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828198 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828202 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828206 */     // MIs[0] Operand 7
     /*  828206 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
     /*  828217 */     GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  828221 */     // (intrinsic_void 2440:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  828221 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  828225 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  828231 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
     /*  828235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW),
     /*  828238 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  828240 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  828242 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  828244 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  828246 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  828248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828254 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  828256 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  828260 */     GIR_RootConstrainSelectedInstOperands,
     /*  828261 */     // GIR_Coverage, 27287,
     /*  828261 */     GIR_EraseRootFromParent_Done,
     /*  828262 */   // Label 13319: @828262
     /*  828262 */   GIM_Try, /*On fail goto*//*Label 13320*/ GIMT_Encode4(828365), // Rule ID 27288 //
     /*  828267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
     /*  828272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  828275 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  828278 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  828281 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
     /*  828284 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  828287 */     // MIs[0] tgt
     /*  828287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  828290 */     // MIs[0] en
     /*  828290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  828293 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828297 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828301 */     GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828305 */     GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828309 */     // MIs[0] Operand 7
     /*  828309 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(18446744073709551615u),
     /*  828320 */     GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  828324 */     // (intrinsic_void 2440:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, -1:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
     /*  828324 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  828328 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  828334 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
     /*  828338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW_DONE),
     /*  828341 */     GIR_RootToRootCopy, /*OpIdx*/1, // tgt
     /*  828343 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  828345 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  828347 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  828349 */     GIR_RootToRootCopy, /*OpIdx*/6, // src3
     /*  828351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  828357 */     GIR_RootToRootCopy, /*OpIdx*/2, // en
     /*  828359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  828363 */     GIR_RootConstrainSelectedInstOperands,
     /*  828364 */     // GIR_Coverage, 27288,
     /*  828364 */     GIR_EraseRootFromParent_Done,
     /*  828365 */   // Label 13320: @828365
     /*  828365 */   GIM_Reject,
     /*  828366 */ // Label 13312: @828366
     /*  828366 */ GIM_Reject,
     /*  828367 */ // Label 40: @828367
     /*  828367 */ GIM_Try, /*On fail goto*//*Label 13321*/ GIMT_Encode4(829298),
     /*  828372 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*  828375 */   GIM_Try, /*On fail goto*//*Label 13322*/ GIMT_Encode4(828414), // Rule ID 28492 //
     /*  828380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  828391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  828395 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  828399 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  828403 */     // MIs[1] Operand 1
     /*  828403 */     // No operand predicates
     /*  828403 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  828405 */     // (intrinsic_wo_chain:{ *:[i32] } 3416:{ *:[iPTR] }, (imm:{ *:[i32] }):$src)  =>  (S_MOV_B32:{ *:[i32] } SReg_32:{ *:[i32] }:$src)
     /*  828405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  828408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  828410 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  828412 */     GIR_RootConstrainSelectedInstOperands,
     /*  828413 */     // GIR_Coverage, 28492,
     /*  828413 */     GIR_EraseRootFromParent_Done,
     /*  828414 */   // Label 13322: @828414
     /*  828414 */   GIM_Try, /*On fail goto*//*Label 13323*/ GIMT_Encode4(828447), // Rule ID 6974 //
     /*  828419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  828430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828434 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828438 */     // (intrinsic_wo_chain:{ *:[i32] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0)
     /*  828438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828443 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828445 */     GIR_RootConstrainSelectedInstOperands,
     /*  828446 */     // GIR_Coverage, 6974,
     /*  828446 */     GIR_EraseRootFromParent_Done,
     /*  828447 */   // Label 13323: @828447
     /*  828447 */   GIM_Try, /*On fail goto*//*Label 13324*/ GIMT_Encode4(828480), // Rule ID 6975 //
     /*  828452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  828463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828467 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828471 */     // (intrinsic_wo_chain:{ *:[f32] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[f32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[f32] } VRegOrLdsSrc_32:{ *:[f32] }:$src0)
     /*  828471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828476 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828478 */     GIR_RootConstrainSelectedInstOperands,
     /*  828479 */     // GIR_Coverage, 6975,
     /*  828479 */     GIR_EraseRootFromParent_Done,
     /*  828480 */   // Label 13324: @828480
     /*  828480 */   GIM_Try, /*On fail goto*//*Label 13325*/ GIMT_Encode4(828513), // Rule ID 6976 //
     /*  828485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  828493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  828496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828500 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828504 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[v2i16] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[v2i16] } VRegOrLdsSrc_32:{ *:[v2i16] }:$src0)
     /*  828504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828509 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828511 */     GIR_RootConstrainSelectedInstOperands,
     /*  828512 */     // GIR_Coverage, 6976,
     /*  828512 */     GIR_EraseRootFromParent_Done,
     /*  828513 */   // Label 13325: @828513
     /*  828513 */   GIM_Try, /*On fail goto*//*Label 13326*/ GIMT_Encode4(828546), // Rule ID 6977 //
     /*  828518 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828523 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  828526 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  828529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828533 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828537 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[v2f16] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[v2f16] } VRegOrLdsSrc_32:{ *:[v2f16] }:$src0)
     /*  828537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828542 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828544 */     GIR_RootConstrainSelectedInstOperands,
     /*  828545 */     // GIR_Coverage, 6977,
     /*  828545 */     GIR_EraseRootFromParent_Done,
     /*  828546 */   // Label 13326: @828546
     /*  828546 */   GIM_Try, /*On fail goto*//*Label 13327*/ GIMT_Encode4(828579), // Rule ID 6978 //
     /*  828551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  828559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  828562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828566 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828570 */     // (intrinsic_wo_chain:{ *:[i32] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0)
     /*  828570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828575 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828577 */     GIR_RootConstrainSelectedInstOperands,
     /*  828578 */     // GIR_Coverage, 6978,
     /*  828578 */     GIR_EraseRootFromParent_Done,
     /*  828579 */   // Label 13327: @828579
     /*  828579 */   GIM_Try, /*On fail goto*//*Label 13328*/ GIMT_Encode4(828612), // Rule ID 6979 //
     /*  828584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  828592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  828595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828603 */     // (intrinsic_wo_chain:{ *:[i32] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0)
     /*  828603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828608 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828610 */     GIR_RootConstrainSelectedInstOperands,
     /*  828611 */     // GIR_Coverage, 6979,
     /*  828611 */     GIR_EraseRootFromParent_Done,
     /*  828612 */   // Label 13328: @828612
     /*  828612 */   GIM_Try, /*On fail goto*//*Label 13329*/ GIMT_Encode4(828645), // Rule ID 6980 //
     /*  828617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  828625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  828628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828632 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828636 */     // (intrinsic_wo_chain:{ *:[i32] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0)
     /*  828636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828641 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828643 */     GIR_RootConstrainSelectedInstOperands,
     /*  828644 */     // GIR_Coverage, 6980,
     /*  828644 */     GIR_EraseRootFromParent_Done,
     /*  828645 */   // Label 13329: @828645
     /*  828645 */   GIM_Try, /*On fail goto*//*Label 13330*/ GIMT_Encode4(828678), // Rule ID 6981 //
     /*  828650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
     /*  828655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  828658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  828661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  828665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
     /*  828669 */     // (intrinsic_wo_chain:{ *:[i32] } 3416:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0)
     /*  828669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
     /*  828672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828674 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828676 */     GIR_RootConstrainSelectedInstOperands,
     /*  828677 */     // GIR_Coverage, 6981,
     /*  828677 */     GIR_EraseRootFromParent_Done,
     /*  828678 */   // Label 13330: @828678
     /*  828678 */   GIM_Try, /*On fail goto*//*Label 13331*/ GIMT_Encode4(828711), // Rule ID 7046 //
     /*  828683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  828694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828698 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828702 */     // (intrinsic_wo_chain:{ *:[i32] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0)
     /*  828702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828707 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828709 */     GIR_RootConstrainSelectedInstOperands,
     /*  828710 */     // GIR_Coverage, 7046,
     /*  828710 */     GIR_EraseRootFromParent_Done,
     /*  828711 */   // Label 13331: @828711
     /*  828711 */   GIM_Try, /*On fail goto*//*Label 13332*/ GIMT_Encode4(828744), // Rule ID 7047 //
     /*  828716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  828727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828731 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828735 */     // (intrinsic_wo_chain:{ *:[f32] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[f32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[f32] } VRegSrc_32:{ *:[f32] }:$src0)
     /*  828735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828740 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828742 */     GIR_RootConstrainSelectedInstOperands,
     /*  828743 */     // GIR_Coverage, 7047,
     /*  828743 */     GIR_EraseRootFromParent_Done,
     /*  828744 */   // Label 13332: @828744
     /*  828744 */   GIM_Try, /*On fail goto*//*Label 13333*/ GIMT_Encode4(828777), // Rule ID 7048 //
     /*  828749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  828757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  828760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828768 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[v2i16] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[v2i16] } VRegSrc_32:{ *:[v2i16] }:$src0)
     /*  828768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828773 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828775 */     GIR_RootConstrainSelectedInstOperands,
     /*  828776 */     // GIR_Coverage, 7048,
     /*  828776 */     GIR_EraseRootFromParent_Done,
     /*  828777 */   // Label 13333: @828777
     /*  828777 */   GIM_Try, /*On fail goto*//*Label 13334*/ GIMT_Encode4(828810), // Rule ID 7049 //
     /*  828782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  828790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  828793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828797 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828801 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[v2f16] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[v2f16] } VRegSrc_32:{ *:[v2f16] }:$src0)
     /*  828801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828806 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828808 */     GIR_RootConstrainSelectedInstOperands,
     /*  828809 */     // GIR_Coverage, 7049,
     /*  828809 */     GIR_EraseRootFromParent_Done,
     /*  828810 */   // Label 13334: @828810
     /*  828810 */   GIM_Try, /*On fail goto*//*Label 13335*/ GIMT_Encode4(828843), // Rule ID 7050 //
     /*  828815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  828826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828830 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828834 */     // (intrinsic_wo_chain:{ *:[i32] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0)
     /*  828834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828839 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828841 */     GIR_RootConstrainSelectedInstOperands,
     /*  828842 */     // GIR_Coverage, 7050,
     /*  828842 */     GIR_EraseRootFromParent_Done,
     /*  828843 */   // Label 13335: @828843
     /*  828843 */   GIM_Try, /*On fail goto*//*Label 13336*/ GIMT_Encode4(828876), // Rule ID 7051 //
     /*  828848 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828853 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828856 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  828859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828863 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828867 */     // (intrinsic_wo_chain:{ *:[i32] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0)
     /*  828867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828872 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828874 */     GIR_RootConstrainSelectedInstOperands,
     /*  828875 */     // GIR_Coverage, 7051,
     /*  828875 */     GIR_EraseRootFromParent_Done,
     /*  828876 */   // Label 13336: @828876
     /*  828876 */   GIM_Try, /*On fail goto*//*Label 13337*/ GIMT_Encode4(828909), // Rule ID 7052 //
     /*  828881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  828892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828896 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828900 */     // (intrinsic_wo_chain:{ *:[i32] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0)
     /*  828900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828905 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828907 */     GIR_RootConstrainSelectedInstOperands,
     /*  828908 */     // GIR_Coverage, 7052,
     /*  828908 */     GIR_EraseRootFromParent_Done,
     /*  828909 */   // Label 13337: @828909
     /*  828909 */   GIM_Try, /*On fail goto*//*Label 13338*/ GIMT_Encode4(828942), // Rule ID 7053 //
     /*  828914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
     /*  828919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  828925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  828933 */     // (intrinsic_wo_chain:{ *:[i32] } 3350:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0)
     /*  828933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
     /*  828936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  828938 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828940 */     GIR_RootConstrainSelectedInstOperands,
     /*  828941 */     // GIR_Coverage, 7053,
     /*  828941 */     GIR_EraseRootFromParent_Done,
     /*  828942 */   // Label 13338: @828942
     /*  828942 */   GIM_Try, /*On fail goto*//*Label 13339*/ GIMT_Encode4(828974), // Rule ID 2 //
     /*  828947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_wqm),
     /*  828952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  828955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  828958 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  828962 */     // (intrinsic_wo_chain:{ *:[i32] } 3474:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (S_WQM_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
     /*  828962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B32),
     /*  828965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  828967 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  828969 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  828972 */     GIR_RootConstrainSelectedInstOperands,
     /*  828973 */     // GIR_Coverage, 2,
     /*  828973 */     GIR_EraseRootFromParent_Done,
     /*  828974 */   // Label 13339: @828974
     /*  828974 */   GIM_Try, /*On fail goto*//*Label 13340*/ GIMT_Encode4(829006), // Rule ID 3 //
     /*  828979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_wqm),
     /*  828984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  828987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  828990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  828994 */     // (intrinsic_wo_chain:{ *:[i64] } 3474:{ *:[iPTR] }, i64:{ *:[i64] }:$src0)  =>  (S_WQM_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
     /*  828994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B64),
     /*  828997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  828999 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  829001 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  829004 */     GIR_RootConstrainSelectedInstOperands,
     /*  829005 */     // GIR_Coverage, 3,
     /*  829005 */     GIR_EraseRootFromParent_Done,
     /*  829006 */   // Label 13340: @829006
     /*  829006 */   GIM_Try, /*On fail goto*//*Label 13341*/ GIMT_Encode4(829038), // Rule ID 21 //
     /*  829011 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_quadmask),
     /*  829016 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829019 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  829026 */     // (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (S_QUADMASK_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
     /*  829026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_QUADMASK_B32),
     /*  829029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829031 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  829033 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  829036 */     GIR_RootConstrainSelectedInstOperands,
     /*  829037 */     // GIR_Coverage, 21,
     /*  829037 */     GIR_EraseRootFromParent_Done,
     /*  829038 */   // Label 13341: @829038
     /*  829038 */   GIM_Try, /*On fail goto*//*Label 13342*/ GIMT_Encode4(829070), // Rule ID 22 //
     /*  829043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_quadmask),
     /*  829048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  829051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  829054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  829058 */     // (intrinsic_wo_chain:{ *:[i64] } 3450:{ *:[iPTR] }, i64:{ *:[i64] }:$src0)  =>  (S_QUADMASK_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
     /*  829058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_QUADMASK_B64),
     /*  829061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829063 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  829065 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  829068 */     GIR_RootConstrainSelectedInstOperands,
     /*  829069 */     // GIR_Coverage, 22,
     /*  829069 */     GIR_EraseRootFromParent_Done,
     /*  829070 */   // Label 13342: @829070
     /*  829070 */   GIM_Try, /*On fail goto*//*Label 13343*/ GIMT_Encode4(829102), // Rule ID 24 //
     /*  829075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  829078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_bitreplicate),
     /*  829083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  829086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  829093 */     // (intrinsic_wo_chain:{ *:[i64] } 3430:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (S_BITREPLICATE_B64_B32:{ *:[i64] } i32:{ *:[i32] }:$src0)
     /*  829093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BITREPLICATE_B64_B32),
     /*  829096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829098 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  829100 */     GIR_RootConstrainSelectedInstOperands,
     /*  829101 */     // GIR_Coverage, 24,
     /*  829101 */     GIR_EraseRootFromParent_Done,
     /*  829102 */   // Label 13343: @829102
     /*  829102 */   GIM_Try, /*On fail goto*//*Label 13344*/ GIMT_Encode4(829134), // Rule ID 4167 //
     /*  829107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*  829110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_inverse_ballot),
     /*  829115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  829118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  829125 */     // (intrinsic_wo_chain:{ *:[i1] } 3264:{ *:[iPTR] }, i32:{ *:[i32] }:$mask)  =>  (S_INVERSE_BALLOT_U32:{ *:[i1] } i32:{ *:[i32] }:$mask)
     /*  829125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INVERSE_BALLOT_U32),
     /*  829128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829130 */     GIR_RootToRootCopy, /*OpIdx*/2, // mask
     /*  829132 */     GIR_RootConstrainSelectedInstOperands,
     /*  829133 */     // GIR_Coverage, 4167,
     /*  829133 */     GIR_EraseRootFromParent_Done,
     /*  829134 */   // Label 13344: @829134
     /*  829134 */   GIM_Try, /*On fail goto*//*Label 13345*/ GIMT_Encode4(829166), // Rule ID 4168 //
     /*  829139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*  829142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_inverse_ballot),
     /*  829147 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  829150 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  829153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  829157 */     // (intrinsic_wo_chain:{ *:[i1] } 3264:{ *:[iPTR] }, i64:{ *:[i64] }:$mask)  =>  (S_INVERSE_BALLOT_U64:{ *:[i1] } i64:{ *:[i64] }:$mask)
     /*  829157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INVERSE_BALLOT_U64),
     /*  829160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829162 */     GIR_RootToRootCopy, /*OpIdx*/2, // mask
     /*  829164 */     GIR_RootConstrainSelectedInstOperands,
     /*  829165 */     // GIR_Coverage, 4168,
     /*  829165 */     GIR_EraseRootFromParent_Done,
     /*  829166 */   // Label 13345: @829166
     /*  829166 */   GIM_Try, /*On fail goto*//*Label 13346*/ GIMT_Encode4(829201), // Rule ID 4790 //
     /*  829171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*  829174 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wqm_vote),
     /*  829179 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  829182 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*  829185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  829189 */     // (intrinsic_wo_chain:{ *:[i1] } 3680:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B32:{ *:[i1] }:{ *:[i1] } SSrc_b32:{ *:[i1] }:$src0)
     /*  829189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B32),
     /*  829192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829194 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  829196 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  829199 */     GIR_RootConstrainSelectedInstOperands,
     /*  829200 */     // GIR_Coverage, 4790,
     /*  829200 */     GIR_EraseRootFromParent_Done,
     /*  829201 */   // Label 13346: @829201
     /*  829201 */   GIM_Try, /*On fail goto*//*Label 13347*/ GIMT_Encode4(829236), // Rule ID 4791 //
     /*  829206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*  829209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wqm_vote),
     /*  829214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  829217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1,
     /*  829220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  829224 */     // (intrinsic_wo_chain:{ *:[i1] } 3680:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } SSrc_b64:{ *:[i1] }:$src0)
     /*  829224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B64),
     /*  829227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829229 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  829231 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  829234 */     GIR_RootConstrainSelectedInstOperands,
     /*  829235 */     // GIR_Coverage, 4791,
     /*  829235 */     GIR_EraseRootFromParent_Done,
     /*  829236 */   // Label 13347: @829236
     /*  829236 */   GIM_Try, /*On fail goto*//*Label 13348*/ GIMT_Encode4(829297), // Rule ID 27315 //
     /*  829241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*  829244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_inverse_ballot),
     /*  829249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  829252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  829255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  829259 */     // (intrinsic_wo_chain:{ *:[i1] } 3264:{ *:[iPTR] }, i64:{ *:[i64] }:$src)  =>  (S_INVERSE_BALLOT_U32:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[i64] }:$src, sub0:{ *:[i32] }))
     /*  829259 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  829262 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  829266 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  829271 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // src
     /*  829277 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  829282 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  829287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INVERSE_BALLOT_U32),
     /*  829290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  829292 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  829295 */     GIR_RootConstrainSelectedInstOperands,
     /*  829296 */     // GIR_Coverage, 27315,
     /*  829296 */     GIR_EraseRootFromParent_Done,
     /*  829297 */   // Label 13348: @829297
     /*  829297 */   GIM_Reject,
     /*  829298 */ // Label 13321: @829298
     /*  829298 */ GIM_Try, /*On fail goto*//*Label 13349*/ GIMT_Encode4(836105),
     /*  829303 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /*  829306 */   GIM_Try, /*On fail goto*//*Label 13350*/ GIMT_Encode4(829358), // Rule ID 4287 //
     /*  829311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  829314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_permute),
     /*  829319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829339 */     // (intrinsic_wo_chain:{ *:[i32] } 2428:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_PERMUTE_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PERMUTE_B32),
     /*  829342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829349 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829356 */     GIR_RootConstrainSelectedInstOperands,
     /*  829357 */     // GIR_Coverage, 4287,
     /*  829357 */     GIR_EraseRootFromParent_Done,
     /*  829358 */   // Label 13350: @829358
     /*  829358 */   GIM_Try, /*On fail goto*//*Label 13351*/ GIMT_Encode4(829410), // Rule ID 4288 //
     /*  829363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  829366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute),
     /*  829371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829391 */     // (intrinsic_wo_chain:{ *:[i32] } 2409:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_B32),
     /*  829394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829401 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829408 */     GIR_RootConstrainSelectedInstOperands,
     /*  829409 */     // GIR_Coverage, 4288,
     /*  829409 */     GIR_EraseRootFromParent_Done,
     /*  829410 */   // Label 13351: @829410
     /*  829410 */   GIM_Try, /*On fail goto*//*Label 13352*/ GIMT_Encode4(829462), // Rule ID 4289 //
     /*  829415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode0),
     /*  829418 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute_fi_b32),
     /*  829423 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829426 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829429 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829443 */     // (intrinsic_wo_chain:{ *:[i32] } 2410:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_FI_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_FI_B32),
     /*  829446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829453 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829460 */     GIR_RootConstrainSelectedInstOperands,
     /*  829461 */     // GIR_Coverage, 4289,
     /*  829461 */     GIR_EraseRootFromParent_Done,
     /*  829462 */   // Label 13352: @829462
     /*  829462 */   GIM_Try, /*On fail goto*//*Label 13353*/ GIMT_Encode4(829514), // Rule ID 4290 //
     /*  829467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode1),
     /*  829470 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute_fi_b32),
     /*  829475 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829478 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829481 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829488 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829495 */     // (intrinsic_wo_chain:{ *:[i32] } 2410:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_FI_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_FI_B32),
     /*  829498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829505 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829512 */     GIR_RootConstrainSelectedInstOperands,
     /*  829513 */     // GIR_Coverage, 4290,
     /*  829513 */     GIR_EraseRootFromParent_Done,
     /*  829514 */   // Label 13353: @829514
     /*  829514 */   GIM_Try, /*On fail goto*//*Label 13354*/ GIMT_Encode4(829566), // Rule ID 4291 //
     /*  829519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode2),
     /*  829522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute_fi_b32),
     /*  829527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829547 */     // (intrinsic_wo_chain:{ *:[i32] } 2410:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_FI_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_FI_B32),
     /*  829550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829557 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829564 */     GIR_RootConstrainSelectedInstOperands,
     /*  829565 */     // GIR_Coverage, 4291,
     /*  829565 */     GIR_EraseRootFromParent_Done,
     /*  829566 */   // Label 13354: @829566
     /*  829566 */   GIM_Try, /*On fail goto*//*Label 13355*/ GIMT_Encode4(829618), // Rule ID 4292 //
     /*  829571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode3),
     /*  829574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute_fi_b32),
     /*  829579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829592 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829599 */     // (intrinsic_wo_chain:{ *:[i32] } 2410:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_FI_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_FI_B32),
     /*  829602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829609 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829616 */     GIR_RootConstrainSelectedInstOperands,
     /*  829617 */     // GIR_Coverage, 4292,
     /*  829617 */     GIR_EraseRootFromParent_Done,
     /*  829618 */   // Label 13355: @829618
     /*  829618 */   GIM_Try, /*On fail goto*//*Label 13356*/ GIMT_Encode4(829670), // Rule ID 4293 //
     /*  829623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode4),
     /*  829626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute_fi_b32),
     /*  829631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  829640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  829651 */     // (intrinsic_wo_chain:{ *:[i32] } 2410:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_FI_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
     /*  829651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_FI_B32),
     /*  829654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
     /*  829661 */     GIR_RootToRootCopy, /*OpIdx*/3, // data0
     /*  829663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  829668 */     GIR_RootConstrainSelectedInstOperands,
     /*  829669 */     // GIR_Coverage, 4293,
     /*  829669 */     GIR_EraseRootFromParent_Done,
     /*  829670 */   // Label 13356: @829670
     /*  829670 */   GIM_Try, /*On fail goto*//*Label 13357*/ GIMT_Encode4(829723), // Rule ID 7075 //
     /*  829675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  829678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  829683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829686 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829693 */     // MIs[0] dpp8
     /*  829693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  829696 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  829696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  829699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829701 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829703 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829705 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  829711 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  829721 */     GIR_RootConstrainSelectedInstOperands,
     /*  829722 */     // GIR_Coverage, 7075,
     /*  829722 */     GIR_EraseRootFromParent_Done,
     /*  829723 */   // Label 13357: @829723
     /*  829723 */   GIM_Try, /*On fail goto*//*Label 13358*/ GIMT_Encode4(829776), // Rule ID 7076 //
     /*  829728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  829731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  829736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829746 */     // MIs[0] dpp8
     /*  829746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  829749 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  829749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  829752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829754 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829756 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829758 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  829764 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  829774 */     GIR_RootConstrainSelectedInstOperands,
     /*  829775 */     // GIR_Coverage, 7076,
     /*  829775 */     GIR_EraseRootFromParent_Done,
     /*  829776 */   // Label 13358: @829776
     /*  829776 */   GIM_Try, /*On fail goto*//*Label 13359*/ GIMT_Encode4(829829), // Rule ID 7077 //
     /*  829781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  829784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  829789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829792 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829799 */     // MIs[0] dpp8
     /*  829799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  829802 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  829802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  829805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829807 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829809 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829811 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  829817 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  829827 */     GIR_RootConstrainSelectedInstOperands,
     /*  829828 */     // GIR_Coverage, 7077,
     /*  829828 */     GIR_EraseRootFromParent_Done,
     /*  829829 */   // Label 13359: @829829
     /*  829829 */   GIM_Try, /*On fail goto*//*Label 13360*/ GIMT_Encode4(829882), // Rule ID 7078 //
     /*  829834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  829837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  829842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829852 */     // MIs[0] dpp8
     /*  829852 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  829855 */     // (intrinsic_wo_chain:{ *:[f32] } 3329:{ *:[iPTR] }, f32:{ *:[f32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[f32] } VGPR_32:{ *:[f32] }:$src, VGPR_32:{ *:[f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  829855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  829858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829860 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829862 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829864 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  829870 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  829880 */     GIR_RootConstrainSelectedInstOperands,
     /*  829881 */     // GIR_Coverage, 7078,
     /*  829881 */     GIR_EraseRootFromParent_Done,
     /*  829882 */   // Label 13360: @829882
     /*  829882 */   GIM_Try, /*On fail goto*//*Label 13361*/ GIMT_Encode4(829935), // Rule ID 7079 //
     /*  829887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  829890 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  829895 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829898 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829905 */     // MIs[0] dpp8
     /*  829905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  829908 */     // (intrinsic_wo_chain:{ *:[f32] } 3329:{ *:[iPTR] }, f32:{ *:[f32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[f32] } VGPR_32:{ *:[f32] }:$src, VGPR_32:{ *:[f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  829908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  829911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829913 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829915 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829917 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  829923 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  829933 */     GIR_RootConstrainSelectedInstOperands,
     /*  829934 */     // GIR_Coverage, 7079,
     /*  829934 */     GIR_EraseRootFromParent_Done,
     /*  829935 */   // Label 13361: @829935
     /*  829935 */   GIM_Try, /*On fail goto*//*Label 13362*/ GIMT_Encode4(829988), // Rule ID 7080 //
     /*  829940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  829943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  829948 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  829951 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  829954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  829958 */     // MIs[0] dpp8
     /*  829958 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  829961 */     // (intrinsic_wo_chain:{ *:[f32] } 3329:{ *:[iPTR] }, f32:{ *:[f32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[f32] } VGPR_32:{ *:[f32] }:$src, VGPR_32:{ *:[f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  829961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  829964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  829966 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829968 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  829970 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  829976 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  829986 */     GIR_RootConstrainSelectedInstOperands,
     /*  829987 */     // GIR_Coverage, 7080,
     /*  829987 */     GIR_EraseRootFromParent_Done,
     /*  829988 */   // Label 13362: @829988
     /*  829988 */   GIM_Try, /*On fail goto*//*Label 13363*/ GIMT_Encode4(830041), // Rule ID 7081 //
     /*  829993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  829996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  830004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  830007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830011 */     // MIs[0] dpp8
     /*  830011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830014 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3329:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[v2i16] } VGPR_32:{ *:[v2i16] }:$src, VGPR_32:{ *:[v2i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  830017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830019 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830021 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830023 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830029 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830039 */     GIR_RootConstrainSelectedInstOperands,
     /*  830040 */     // GIR_Coverage, 7081,
     /*  830040 */     GIR_EraseRootFromParent_Done,
     /*  830041 */   // Label 13363: @830041
     /*  830041 */   GIM_Try, /*On fail goto*//*Label 13364*/ GIMT_Encode4(830094), // Rule ID 7082 //
     /*  830046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  830049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  830057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  830060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830064 */     // MIs[0] dpp8
     /*  830064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830067 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3329:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[v2i16] } VGPR_32:{ *:[v2i16] }:$src, VGPR_32:{ *:[v2i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  830070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830072 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830074 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830076 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830082 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830092 */     GIR_RootConstrainSelectedInstOperands,
     /*  830093 */     // GIR_Coverage, 7082,
     /*  830093 */     GIR_EraseRootFromParent_Done,
     /*  830094 */   // Label 13364: @830094
     /*  830094 */   GIM_Try, /*On fail goto*//*Label 13365*/ GIMT_Encode4(830147), // Rule ID 7083 //
     /*  830099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  830102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  830110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  830113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830117 */     // MIs[0] dpp8
     /*  830117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830120 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3329:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[v2i16] } VGPR_32:{ *:[v2i16] }:$src, VGPR_32:{ *:[v2i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  830123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830125 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830127 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830129 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830135 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830145 */     GIR_RootConstrainSelectedInstOperands,
     /*  830146 */     // GIR_Coverage, 7083,
     /*  830146 */     GIR_EraseRootFromParent_Done,
     /*  830147 */   // Label 13365: @830147
     /*  830147 */   GIM_Try, /*On fail goto*//*Label 13366*/ GIMT_Encode4(830200), // Rule ID 7084 //
     /*  830152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  830155 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830160 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  830163 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  830166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830170 */     // MIs[0] dpp8
     /*  830170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830173 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3329:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src, VGPR_32:{ *:[v2f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  830176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830178 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830180 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830182 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830188 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830198 */     GIR_RootConstrainSelectedInstOperands,
     /*  830199 */     // GIR_Coverage, 7084,
     /*  830199 */     GIR_EraseRootFromParent_Done,
     /*  830200 */   // Label 13366: @830200
     /*  830200 */   GIM_Try, /*On fail goto*//*Label 13367*/ GIMT_Encode4(830253), // Rule ID 7085 //
     /*  830205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  830208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  830216 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  830219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830223 */     // MIs[0] dpp8
     /*  830223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830226 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3329:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src, VGPR_32:{ *:[v2f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  830229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830231 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830233 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830235 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830241 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830251 */     GIR_RootConstrainSelectedInstOperands,
     /*  830252 */     // GIR_Coverage, 7085,
     /*  830252 */     GIR_EraseRootFromParent_Done,
     /*  830253 */   // Label 13367: @830253
     /*  830253 */   GIM_Try, /*On fail goto*//*Label 13368*/ GIMT_Encode4(830306), // Rule ID 7086 //
     /*  830258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  830261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  830269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  830272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830276 */     // MIs[0] dpp8
     /*  830276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830279 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3329:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src, VGPR_32:{ *:[v2f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  830282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830284 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830286 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830288 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830294 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830304 */     GIR_RootConstrainSelectedInstOperands,
     /*  830305 */     // GIR_Coverage, 7086,
     /*  830305 */     GIR_EraseRootFromParent_Done,
     /*  830306 */   // Label 13368: @830306
     /*  830306 */   GIM_Try, /*On fail goto*//*Label 13369*/ GIMT_Encode4(830359), // Rule ID 7087 //
     /*  830311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  830314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  830322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  830325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830329 */     // MIs[0] dpp8
     /*  830329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830332 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p2:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  830335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830337 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830339 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830341 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830347 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830357 */     GIR_RootConstrainSelectedInstOperands,
     /*  830358 */     // GIR_Coverage, 7087,
     /*  830358 */     GIR_EraseRootFromParent_Done,
     /*  830359 */   // Label 13369: @830359
     /*  830359 */   GIM_Try, /*On fail goto*//*Label 13370*/ GIMT_Encode4(830412), // Rule ID 7088 //
     /*  830364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  830367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  830375 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  830378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830382 */     // MIs[0] dpp8
     /*  830382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830385 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p2:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  830388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830390 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830392 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830394 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830400 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830410 */     GIR_RootConstrainSelectedInstOperands,
     /*  830411 */     // GIR_Coverage, 7088,
     /*  830411 */     GIR_EraseRootFromParent_Done,
     /*  830412 */   // Label 13370: @830412
     /*  830412 */   GIM_Try, /*On fail goto*//*Label 13371*/ GIMT_Encode4(830465), // Rule ID 7089 //
     /*  830417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  830420 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830425 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  830428 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  830431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830435 */     // MIs[0] dpp8
     /*  830435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830438 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p2:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  830441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830443 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830445 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830447 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830453 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830463 */     GIR_RootConstrainSelectedInstOperands,
     /*  830464 */     // GIR_Coverage, 7089,
     /*  830464 */     GIR_EraseRootFromParent_Done,
     /*  830465 */   // Label 13371: @830465
     /*  830465 */   GIM_Try, /*On fail goto*//*Label 13372*/ GIMT_Encode4(830518), // Rule ID 7090 //
     /*  830470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  830473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  830481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  830484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830488 */     // MIs[0] dpp8
     /*  830488 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830491 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p3:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  830494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830496 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830498 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830500 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830506 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830516 */     GIR_RootConstrainSelectedInstOperands,
     /*  830517 */     // GIR_Coverage, 7090,
     /*  830517 */     GIR_EraseRootFromParent_Done,
     /*  830518 */   // Label 13372: @830518
     /*  830518 */   GIM_Try, /*On fail goto*//*Label 13373*/ GIMT_Encode4(830571), // Rule ID 7091 //
     /*  830523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  830526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  830534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  830537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830541 */     // MIs[0] dpp8
     /*  830541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830544 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p3:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  830547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830549 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830551 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830553 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830559 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830569 */     GIR_RootConstrainSelectedInstOperands,
     /*  830570 */     // GIR_Coverage, 7091,
     /*  830570 */     GIR_EraseRootFromParent_Done,
     /*  830571 */   // Label 13373: @830571
     /*  830571 */   GIM_Try, /*On fail goto*//*Label 13374*/ GIMT_Encode4(830624), // Rule ID 7092 //
     /*  830576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  830579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  830587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  830590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830594 */     // MIs[0] dpp8
     /*  830594 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830597 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p3:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  830600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830602 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830604 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830606 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830612 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830622 */     GIR_RootConstrainSelectedInstOperands,
     /*  830623 */     // GIR_Coverage, 7092,
     /*  830623 */     GIR_EraseRootFromParent_Done,
     /*  830624 */   // Label 13374: @830624
     /*  830624 */   GIM_Try, /*On fail goto*//*Label 13375*/ GIMT_Encode4(830677), // Rule ID 7093 //
     /*  830629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  830632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  830640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  830643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830647 */     // MIs[0] dpp8
     /*  830647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830650 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p5:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  830653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830655 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830657 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830659 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830665 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830675 */     GIR_RootConstrainSelectedInstOperands,
     /*  830676 */     // GIR_Coverage, 7093,
     /*  830676 */     GIR_EraseRootFromParent_Done,
     /*  830677 */   // Label 13375: @830677
     /*  830677 */   GIM_Try, /*On fail goto*//*Label 13376*/ GIMT_Encode4(830730), // Rule ID 7094 //
     /*  830682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  830685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  830693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  830696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830700 */     // MIs[0] dpp8
     /*  830700 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830703 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p5:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  830706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830708 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830710 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830712 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830718 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830728 */     GIR_RootConstrainSelectedInstOperands,
     /*  830729 */     // GIR_Coverage, 7094,
     /*  830729 */     GIR_EraseRootFromParent_Done,
     /*  830730 */   // Label 13376: @830730
     /*  830730 */   GIM_Try, /*On fail goto*//*Label 13377*/ GIMT_Encode4(830783), // Rule ID 7095 //
     /*  830735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  830738 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830743 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  830746 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  830749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830753 */     // MIs[0] dpp8
     /*  830753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830756 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p5:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  830759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830761 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830763 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830765 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830771 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830781 */     GIR_RootConstrainSelectedInstOperands,
     /*  830782 */     // GIR_Coverage, 7095,
     /*  830782 */     GIR_EraseRootFromParent_Done,
     /*  830783 */   // Label 13377: @830783
     /*  830783 */   GIM_Try, /*On fail goto*//*Label 13378*/ GIMT_Encode4(830836), // Rule ID 7096 //
     /*  830788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
     /*  830791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  830799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  830802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830806 */     // MIs[0] dpp8
     /*  830806 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830809 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p6:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
     /*  830812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830814 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830816 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830818 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830824 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830834 */     GIR_RootConstrainSelectedInstOperands,
     /*  830835 */     // GIR_Coverage, 7096,
     /*  830835 */     GIR_EraseRootFromParent_Done,
     /*  830836 */   // Label 13378: @830836
     /*  830836 */   GIM_Try, /*On fail goto*//*Label 13379*/ GIMT_Encode4(830889), // Rule ID 7097 //
     /*  830841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
     /*  830844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  830852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  830855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830859 */     // MIs[0] dpp8
     /*  830859 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830862 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p6:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
     /*  830865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830867 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830869 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830871 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830877 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830887 */     GIR_RootConstrainSelectedInstOperands,
     /*  830888 */     // GIR_Coverage, 7097,
     /*  830888 */     GIR_EraseRootFromParent_Done,
     /*  830889 */   // Label 13379: @830889
     /*  830889 */   GIM_Try, /*On fail goto*//*Label 13380*/ GIMT_Encode4(830942), // Rule ID 7098 //
     /*  830894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
     /*  830897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
     /*  830902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  830905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  830908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830912 */     // MIs[0] dpp8
     /*  830912 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830915 */     // (intrinsic_wo_chain:{ *:[i32] } 3329:{ *:[iPTR] }, p6:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
     /*  830915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
     /*  830918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830920 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830922 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830924 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
     /*  830930 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
     /*  830940 */     GIR_RootConstrainSelectedInstOperands,
     /*  830941 */     // GIR_Coverage, 7098,
     /*  830941 */     GIR_EraseRootFromParent_Done,
     /*  830942 */   // Label 13380: @830942
     /*  830942 */   GIM_Try, /*On fail goto*//*Label 13381*/ GIMT_Encode4(830986), // Rule ID 28768 //
     /*  830947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  830950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle),
     /*  830955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  830958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  830961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  830965 */     // MIs[0] offset16
     /*  830965 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  830968 */     // (intrinsic_wo_chain:{ *:[i32] } 2434:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16)  =>  (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] })
     /*  830968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32),
     /*  830971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  830973 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  830975 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16
     /*  830981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  830984 */     GIR_RootConstrainSelectedInstOperands,
     /*  830985 */     // GIR_Coverage, 28768,
     /*  830985 */     GIR_EraseRootFromParent_Done,
     /*  830986 */   // Label 13381: @830986
     /*  830986 */   GIM_Try, /*On fail goto*//*Label 13382*/ GIMT_Encode4(831030), // Rule ID 28769 //
     /*  830991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  830994 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle),
     /*  830999 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831002 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831009 */     // MIs[0] offset16
     /*  831009 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  831012 */     // (intrinsic_wo_chain:{ *:[i32] } 2434:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16)  =>  (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] })
     /*  831012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32),
     /*  831015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831017 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831019 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16
     /*  831025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831028 */     GIR_RootConstrainSelectedInstOperands,
     /*  831029 */     // GIR_Coverage, 28769,
     /*  831029 */     GIR_EraseRootFromParent_Done,
     /*  831030 */   // Label 13382: @831030
     /*  831030 */   GIM_Try, /*On fail goto*//*Label 13383*/ GIMT_Encode4(831074), // Rule ID 28770 //
     /*  831035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  831038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle),
     /*  831043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831053 */     // MIs[0] offset16
     /*  831053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  831056 */     // (intrinsic_wo_chain:{ *:[i32] } 2434:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16)  =>  (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] })
     /*  831056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32),
     /*  831059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831061 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831063 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16
     /*  831069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831072 */     GIR_RootConstrainSelectedInstOperands,
     /*  831073 */     // GIR_Coverage, 28770,
     /*  831073 */     GIR_EraseRootFromParent_Done,
     /*  831074 */   // Label 13383: @831074
     /*  831074 */   GIM_Try, /*On fail goto*//*Label 13384*/ GIMT_Encode4(831118), // Rule ID 28771 //
     /*  831079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  831082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle),
     /*  831087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831097 */     // MIs[0] offset16
     /*  831097 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  831100 */     // (intrinsic_wo_chain:{ *:[i32] } 2434:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16)  =>  (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] })
     /*  831100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32),
     /*  831103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831105 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831107 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16
     /*  831113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831116 */     GIR_RootConstrainSelectedInstOperands,
     /*  831117 */     // GIR_Coverage, 28771,
     /*  831117 */     GIR_EraseRootFromParent_Done,
     /*  831118 */   // Label 13384: @831118
     /*  831118 */   GIM_Try, /*On fail goto*//*Label 13385*/ GIMT_Encode4(831162), // Rule ID 28772 //
     /*  831123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  831126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle),
     /*  831131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831141 */     // MIs[0] offset16
     /*  831141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  831144 */     // (intrinsic_wo_chain:{ *:[i32] } 2434:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16)  =>  (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] })
     /*  831144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32),
     /*  831147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831149 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831151 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16
     /*  831157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831160 */     GIR_RootConstrainSelectedInstOperands,
     /*  831161 */     // GIR_Coverage, 28772,
     /*  831161 */     GIR_EraseRootFromParent_Done,
     /*  831162 */   // Label 13385: @831162
     /*  831162 */   GIM_Try, /*On fail goto*//*Label 13386*/ GIMT_Encode4(831196), // Rule ID 7099 //
     /*  831167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831185 */     // (intrinsic_wo_chain:{ *:[i32] } 3417:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831190 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831192 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831194 */     GIR_RootConstrainSelectedInstOperands,
     /*  831195 */     // GIR_Coverage, 7099,
     /*  831195 */     GIR_EraseRootFromParent_Done,
     /*  831196 */   // Label 13386: @831196
     /*  831196 */   GIM_Try, /*On fail goto*//*Label 13387*/ GIMT_Encode4(831230), // Rule ID 7101 //
     /*  831201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831219 */     // (intrinsic_wo_chain:{ *:[f32] } 3417:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[f32] } VRegOrLdsSrc_32:{ *:[f32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831224 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831226 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831228 */     GIR_RootConstrainSelectedInstOperands,
     /*  831229 */     // GIR_Coverage, 7101,
     /*  831229 */     GIR_EraseRootFromParent_Done,
     /*  831230 */   // Label 13387: @831230
     /*  831230 */   GIM_Try, /*On fail goto*//*Label 13388*/ GIMT_Encode4(831264), // Rule ID 7103 //
     /*  831235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  831243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  831246 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831253 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3417:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[v2i16] } VRegOrLdsSrc_32:{ *:[v2i16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831258 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831260 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831262 */     GIR_RootConstrainSelectedInstOperands,
     /*  831263 */     // GIR_Coverage, 7103,
     /*  831263 */     GIR_EraseRootFromParent_Done,
     /*  831264 */   // Label 13388: @831264
     /*  831264 */   GIM_Try, /*On fail goto*//*Label 13389*/ GIMT_Encode4(831298), // Rule ID 7105 //
     /*  831269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  831277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  831280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831287 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3417:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[v2f16] } VRegOrLdsSrc_32:{ *:[v2f16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831292 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831294 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831296 */     GIR_RootConstrainSelectedInstOperands,
     /*  831297 */     // GIR_Coverage, 7105,
     /*  831297 */     GIR_EraseRootFromParent_Done,
     /*  831298 */   // Label 13389: @831298
     /*  831298 */   GIM_Try, /*On fail goto*//*Label 13390*/ GIMT_Encode4(831332), // Rule ID 7107 //
     /*  831303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  831311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  831314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831321 */     // (intrinsic_wo_chain:{ *:[i32] } 3417:{ *:[iPTR] }, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831326 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831328 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831330 */     GIR_RootConstrainSelectedInstOperands,
     /*  831331 */     // GIR_Coverage, 7107,
     /*  831331 */     GIR_EraseRootFromParent_Done,
     /*  831332 */   // Label 13390: @831332
     /*  831332 */   GIM_Try, /*On fail goto*//*Label 13391*/ GIMT_Encode4(831366), // Rule ID 7109 //
     /*  831337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  831345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  831348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831355 */     // (intrinsic_wo_chain:{ *:[i32] } 3417:{ *:[iPTR] }, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831360 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831362 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831364 */     GIR_RootConstrainSelectedInstOperands,
     /*  831365 */     // GIR_Coverage, 7109,
     /*  831365 */     GIR_EraseRootFromParent_Done,
     /*  831366 */   // Label 13391: @831366
     /*  831366 */   GIM_Try, /*On fail goto*//*Label 13392*/ GIMT_Encode4(831400), // Rule ID 7111 //
     /*  831371 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831376 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  831379 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  831382 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831389 */     // (intrinsic_wo_chain:{ *:[i32] } 3417:{ *:[iPTR] }, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831394 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831396 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831398 */     GIR_RootConstrainSelectedInstOperands,
     /*  831399 */     // GIR_Coverage, 7111,
     /*  831399 */     GIR_EraseRootFromParent_Done,
     /*  831400 */   // Label 13392: @831400
     /*  831400 */   GIM_Try, /*On fail goto*//*Label 13393*/ GIMT_Encode4(831434), // Rule ID 7113 //
     /*  831405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
     /*  831410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  831413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  831416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  831423 */     // (intrinsic_wo_chain:{ *:[i32] } 3417:{ *:[iPTR] }, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
     /*  831426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831428 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831430 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831432 */     GIR_RootConstrainSelectedInstOperands,
     /*  831433 */     // GIR_Coverage, 7113,
     /*  831433 */     GIR_EraseRootFromParent_Done,
     /*  831434 */   // Label 13393: @831434
     /*  831434 */   GIM_Try, /*On fail goto*//*Label 13394*/ GIMT_Encode4(831471), // Rule ID 7477 //
     /*  831439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32),
     /*  831442 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane_idx_gen),
     /*  831447 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831460 */     // (intrinsic_wo_chain:{ *:[i32] } 3343:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_PERMLANE_IDX_GEN_B32_e64:{ *:[i32] } VGPR_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1)
     /*  831460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE_IDX_GEN_B32_e64),
     /*  831463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831465 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  831467 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  831469 */     GIR_RootConstrainSelectedInstOperands,
     /*  831470 */     // GIR_Coverage, 7477,
     /*  831470 */     GIR_EraseRootFromParent_Done,
     /*  831471 */   // Label 13394: @831471
     /*  831471 */   GIM_Try, /*On fail goto*//*Label 13395*/ GIMT_Encode4(831531), // Rule ID 27320 //
     /*  831476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  831479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831484 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831497 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831497 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831500 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831504 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831509 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831519 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831524 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831526 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831529 */     GIR_RootConstrainSelectedInstOperands,
     /*  831530 */     // GIR_Coverage, 27320,
     /*  831530 */     GIR_EraseRootFromParent_Done,
     /*  831531 */   // Label 13395: @831531
     /*  831531 */   GIM_Try, /*On fail goto*//*Label 13396*/ GIMT_Encode4(831591), // Rule ID 27321 //
     /*  831536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  831539 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831544 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831547 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831550 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831557 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831557 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831560 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831564 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831569 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831579 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831584 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831586 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831589 */     GIR_RootConstrainSelectedInstOperands,
     /*  831590 */     // GIR_Coverage, 27321,
     /*  831590 */     GIR_EraseRootFromParent_Done,
     /*  831591 */   // Label 13396: @831591
     /*  831591 */   GIM_Try, /*On fail goto*//*Label 13397*/ GIMT_Encode4(831651), // Rule ID 27322 //
     /*  831596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  831599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831610 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831617 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831617 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831620 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831624 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831629 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831639 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831644 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831646 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831649 */     GIR_RootConstrainSelectedInstOperands,
     /*  831650 */     // GIR_Coverage, 27322,
     /*  831650 */     GIR_EraseRootFromParent_Done,
     /*  831651 */   // Label 13397: @831651
     /*  831651 */   GIM_Try, /*On fail goto*//*Label 13398*/ GIMT_Encode4(831711), // Rule ID 27323 //
     /*  831656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  831659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831667 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831677 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831677 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831680 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831684 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831689 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831699 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831704 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831706 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831709 */     GIR_RootConstrainSelectedInstOperands,
     /*  831710 */     // GIR_Coverage, 27323,
     /*  831710 */     GIR_EraseRootFromParent_Done,
     /*  831711 */   // Label 13398: @831711
     /*  831711 */   GIM_Try, /*On fail goto*//*Label 13399*/ GIMT_Encode4(831771), // Rule ID 27324 //
     /*  831716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  831719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831727 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831730 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831737 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831737 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831740 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831744 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831749 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831759 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831764 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831766 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831769 */     GIR_RootConstrainSelectedInstOperands,
     /*  831770 */     // GIR_Coverage, 27324,
     /*  831770 */     GIR_EraseRootFromParent_Done,
     /*  831771 */   // Label 13399: @831771
     /*  831771 */   GIM_Try, /*On fail goto*//*Label 13400*/ GIMT_Encode4(831831), // Rule ID 27325 //
     /*  831776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  831779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831797 */     // (intrinsic_wo_chain:{ *:[f32] } 3486:{ *:[iPTR] }, f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[f32] } 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831797 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831800 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831804 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831809 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831819 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831824 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831826 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831829 */     GIR_RootConstrainSelectedInstOperands,
     /*  831830 */     // GIR_Coverage, 27325,
     /*  831830 */     GIR_EraseRootFromParent_Done,
     /*  831831 */   // Label 13400: @831831
     /*  831831 */   GIM_Try, /*On fail goto*//*Label 13401*/ GIMT_Encode4(831891), // Rule ID 27326 //
     /*  831836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  831839 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831844 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831857 */     // (intrinsic_wo_chain:{ *:[f32] } 3486:{ *:[iPTR] }, f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[f32] } 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831857 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831860 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831864 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831869 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831879 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831884 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831886 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831889 */     GIR_RootConstrainSelectedInstOperands,
     /*  831890 */     // GIR_Coverage, 27326,
     /*  831890 */     GIR_EraseRootFromParent_Done,
     /*  831891 */   // Label 13401: @831891
     /*  831891 */   GIM_Try, /*On fail goto*//*Label 13402*/ GIMT_Encode4(831951), // Rule ID 27327 //
     /*  831896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  831899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831917 */     // (intrinsic_wo_chain:{ *:[f32] } 3486:{ *:[iPTR] }, f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[f32] } 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831917 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831920 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831924 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831929 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831939 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  831941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831944 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  831946 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  831949 */     GIR_RootConstrainSelectedInstOperands,
     /*  831950 */     // GIR_Coverage, 27327,
     /*  831950 */     GIR_EraseRootFromParent_Done,
     /*  831951 */   // Label 13402: @831951
     /*  831951 */   GIM_Try, /*On fail goto*//*Label 13403*/ GIMT_Encode4(832011), // Rule ID 27328 //
     /*  831956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  831959 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  831964 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  831967 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  831970 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  831973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  831977 */     // (intrinsic_wo_chain:{ *:[f32] } 3486:{ *:[iPTR] }, f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[f32] } 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  831977 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  831980 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  831984 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  831989 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  831991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  831994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  831996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  831999 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832004 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832006 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832009 */     GIR_RootConstrainSelectedInstOperands,
     /*  832010 */     // GIR_Coverage, 27328,
     /*  832010 */     GIR_EraseRootFromParent_Done,
     /*  832011 */   // Label 13403: @832011
     /*  832011 */   GIM_Try, /*On fail goto*//*Label 13404*/ GIMT_Encode4(832071), // Rule ID 27329 //
     /*  832016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  832019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  832027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  832030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  832033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832037 */     // (intrinsic_wo_chain:{ *:[f32] } 3486:{ *:[iPTR] }, f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[f32] } 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[f32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832037 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832040 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832044 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832049 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832059 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832064 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832066 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832069 */     GIR_RootConstrainSelectedInstOperands,
     /*  832070 */     // GIR_Coverage, 27329,
     /*  832070 */     GIR_EraseRootFromParent_Done,
     /*  832071 */   // Label 13404: @832071
     /*  832071 */   GIM_Try, /*On fail goto*//*Label 13405*/ GIMT_Encode4(832131), // Rule ID 27330 //
     /*  832076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  832079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832097 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, v2i16:{ *:[v2i16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832097 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832100 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832104 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832109 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832119 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832124 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832126 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832129 */     GIR_RootConstrainSelectedInstOperands,
     /*  832130 */     // GIR_Coverage, 27330,
     /*  832130 */     GIR_EraseRootFromParent_Done,
     /*  832131 */   // Label 13405: @832131
     /*  832131 */   GIM_Try, /*On fail goto*//*Label 13406*/ GIMT_Encode4(832191), // Rule ID 27331 //
     /*  832136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  832139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832150 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832157 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, v2i16:{ *:[v2i16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832157 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832160 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832164 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832169 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832179 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832184 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832186 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832189 */     GIR_RootConstrainSelectedInstOperands,
     /*  832190 */     // GIR_Coverage, 27331,
     /*  832190 */     GIR_EraseRootFromParent_Done,
     /*  832191 */   // Label 13406: @832191
     /*  832191 */   GIM_Try, /*On fail goto*//*Label 13407*/ GIMT_Encode4(832251), // Rule ID 27332 //
     /*  832196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  832199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832217 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, v2i16:{ *:[v2i16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832217 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832220 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832224 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832229 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832239 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832244 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832246 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832249 */     GIR_RootConstrainSelectedInstOperands,
     /*  832250 */     // GIR_Coverage, 27332,
     /*  832250 */     GIR_EraseRootFromParent_Done,
     /*  832251 */   // Label 13407: @832251
     /*  832251 */   GIM_Try, /*On fail goto*//*Label 13408*/ GIMT_Encode4(832311), // Rule ID 27333 //
     /*  832256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  832259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832277 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, v2i16:{ *:[v2i16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832277 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832280 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832284 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832289 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832299 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832304 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832306 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832309 */     GIR_RootConstrainSelectedInstOperands,
     /*  832310 */     // GIR_Coverage, 27333,
     /*  832310 */     GIR_EraseRootFromParent_Done,
     /*  832311 */   // Label 13408: @832311
     /*  832311 */   GIM_Try, /*On fail goto*//*Label 13409*/ GIMT_Encode4(832371), // Rule ID 27334 //
     /*  832316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  832319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832337 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, v2i16:{ *:[v2i16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832337 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832340 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832344 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832349 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832359 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832364 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832366 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832369 */     GIR_RootConstrainSelectedInstOperands,
     /*  832370 */     // GIR_Coverage, 27334,
     /*  832370 */     GIR_EraseRootFromParent_Done,
     /*  832371 */   // Label 13409: @832371
     /*  832371 */   GIM_Try, /*On fail goto*//*Label 13410*/ GIMT_Encode4(832431), // Rule ID 27335 //
     /*  832376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  832379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832387 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832390 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832397 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3486:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, v2f16:{ *:[v2f16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832397 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832400 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832404 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832409 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832419 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832424 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832426 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832429 */     GIR_RootConstrainSelectedInstOperands,
     /*  832430 */     // GIR_Coverage, 27335,
     /*  832430 */     GIR_EraseRootFromParent_Done,
     /*  832431 */   // Label 13410: @832431
     /*  832431 */   GIM_Try, /*On fail goto*//*Label 13411*/ GIMT_Encode4(832491), // Rule ID 27336 //
     /*  832436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  832439 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832444 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832447 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832450 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832457 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3486:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, v2f16:{ *:[v2f16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832457 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832460 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832464 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832469 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832476 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832479 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832484 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832486 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832489 */     GIR_RootConstrainSelectedInstOperands,
     /*  832490 */     // GIR_Coverage, 27336,
     /*  832490 */     GIR_EraseRootFromParent_Done,
     /*  832491 */   // Label 13411: @832491
     /*  832491 */   GIM_Try, /*On fail goto*//*Label 13412*/ GIMT_Encode4(832551), // Rule ID 27337 //
     /*  832496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  832499 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832504 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832507 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832510 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832517 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3486:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, v2f16:{ *:[v2f16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832517 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832520 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832524 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832529 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832539 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832544 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832546 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832549 */     GIR_RootConstrainSelectedInstOperands,
     /*  832550 */     // GIR_Coverage, 27337,
     /*  832550 */     GIR_EraseRootFromParent_Done,
     /*  832551 */   // Label 13412: @832551
     /*  832551 */   GIM_Try, /*On fail goto*//*Label 13413*/ GIMT_Encode4(832611), // Rule ID 27338 //
     /*  832556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  832559 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832564 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832567 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832570 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832577 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3486:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, v2f16:{ *:[v2f16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832577 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832580 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832584 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832589 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832599 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832604 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832606 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832609 */     GIR_RootConstrainSelectedInstOperands,
     /*  832610 */     // GIR_Coverage, 27338,
     /*  832610 */     GIR_EraseRootFromParent_Done,
     /*  832611 */   // Label 13413: @832611
     /*  832611 */   GIM_Try, /*On fail goto*//*Label 13414*/ GIMT_Encode4(832671), // Rule ID 27339 //
     /*  832616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  832619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  832627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  832630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  832633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832637 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3486:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, v2f16:{ *:[v2f16] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[v2f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[v2f16] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832637 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832640 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832644 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832649 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832659 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832664 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832666 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832669 */     GIR_RootConstrainSelectedInstOperands,
     /*  832670 */     // GIR_Coverage, 27339,
     /*  832670 */     GIR_EraseRootFromParent_Done,
     /*  832671 */   // Label 13414: @832671
     /*  832671 */   GIM_Try, /*On fail goto*//*Label 13415*/ GIMT_Encode4(832731), // Rule ID 27340 //
     /*  832676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  832679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  832687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  832690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  832693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832697 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p2:{ *:[i32] }:$src, p2:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832697 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832700 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832704 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832709 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832719 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832724 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832726 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832729 */     GIR_RootConstrainSelectedInstOperands,
     /*  832730 */     // GIR_Coverage, 27340,
     /*  832730 */     GIR_EraseRootFromParent_Done,
     /*  832731 */   // Label 13415: @832731
     /*  832731 */   GIM_Try, /*On fail goto*//*Label 13416*/ GIMT_Encode4(832791), // Rule ID 27341 //
     /*  832736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  832739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  832747 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  832750 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  832753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832757 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p2:{ *:[i32] }:$src, p2:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832757 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832760 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832764 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832769 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832779 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832784 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832786 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832789 */     GIR_RootConstrainSelectedInstOperands,
     /*  832790 */     // GIR_Coverage, 27341,
     /*  832790 */     GIR_EraseRootFromParent_Done,
     /*  832791 */   // Label 13416: @832791
     /*  832791 */   GIM_Try, /*On fail goto*//*Label 13417*/ GIMT_Encode4(832851), // Rule ID 27342 //
     /*  832796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  832799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  832807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  832810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  832813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832817 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p2:{ *:[i32] }:$src, p2:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832817 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832820 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832824 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832829 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832839 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832844 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832846 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832849 */     GIR_RootConstrainSelectedInstOperands,
     /*  832850 */     // GIR_Coverage, 27342,
     /*  832850 */     GIR_EraseRootFromParent_Done,
     /*  832851 */   // Label 13417: @832851
     /*  832851 */   GIM_Try, /*On fail goto*//*Label 13418*/ GIMT_Encode4(832911), // Rule ID 27343 //
     /*  832856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  832859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  832867 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  832870 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  832873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832877 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p2:{ *:[i32] }:$src, p2:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832877 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832880 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832884 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832889 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832899 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832904 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832906 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832909 */     GIR_RootConstrainSelectedInstOperands,
     /*  832910 */     // GIR_Coverage, 27343,
     /*  832910 */     GIR_EraseRootFromParent_Done,
     /*  832911 */   // Label 13418: @832911
     /*  832911 */   GIM_Try, /*On fail goto*//*Label 13419*/ GIMT_Encode4(832971), // Rule ID 27344 //
     /*  832916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  832919 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832924 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  832927 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  832930 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  832933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832937 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p2:{ *:[i32] }:$src, p2:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832937 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  832940 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  832944 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  832949 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  832951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  832954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  832956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832959 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  832961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  832964 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  832966 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  832969 */     GIR_RootConstrainSelectedInstOperands,
     /*  832970 */     // GIR_Coverage, 27344,
     /*  832970 */     GIR_EraseRootFromParent_Done,
     /*  832971 */   // Label 13419: @832971
     /*  832971 */   GIM_Try, /*On fail goto*//*Label 13420*/ GIMT_Encode4(833031), // Rule ID 27345 //
     /*  832976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  832979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  832984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  832987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  832990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  832993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  832997 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p3:{ *:[i32] }:$src, p3:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  832997 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833000 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833004 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833009 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833019 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833024 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833026 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833029 */     GIR_RootConstrainSelectedInstOperands,
     /*  833030 */     // GIR_Coverage, 27345,
     /*  833030 */     GIR_EraseRootFromParent_Done,
     /*  833031 */   // Label 13420: @833031
     /*  833031 */   GIM_Try, /*On fail goto*//*Label 13421*/ GIMT_Encode4(833091), // Rule ID 27346 //
     /*  833036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  833039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  833047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  833050 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  833053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833057 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p3:{ *:[i32] }:$src, p3:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833057 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833060 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833064 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833069 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833079 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833084 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833086 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833089 */     GIR_RootConstrainSelectedInstOperands,
     /*  833090 */     // GIR_Coverage, 27346,
     /*  833090 */     GIR_EraseRootFromParent_Done,
     /*  833091 */   // Label 13421: @833091
     /*  833091 */   GIM_Try, /*On fail goto*//*Label 13422*/ GIMT_Encode4(833151), // Rule ID 27347 //
     /*  833096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  833099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  833107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  833110 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  833113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833117 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p3:{ *:[i32] }:$src, p3:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833117 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833120 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833124 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833129 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833139 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833144 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833146 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833149 */     GIR_RootConstrainSelectedInstOperands,
     /*  833150 */     // GIR_Coverage, 27347,
     /*  833150 */     GIR_EraseRootFromParent_Done,
     /*  833151 */   // Label 13422: @833151
     /*  833151 */   GIM_Try, /*On fail goto*//*Label 13423*/ GIMT_Encode4(833211), // Rule ID 27348 //
     /*  833156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  833159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  833167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  833170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  833173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833177 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p3:{ *:[i32] }:$src, p3:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833177 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833180 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833184 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833189 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833199 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833204 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833206 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833209 */     GIR_RootConstrainSelectedInstOperands,
     /*  833210 */     // GIR_Coverage, 27348,
     /*  833210 */     GIR_EraseRootFromParent_Done,
     /*  833211 */   // Label 13423: @833211
     /*  833211 */   GIM_Try, /*On fail goto*//*Label 13424*/ GIMT_Encode4(833271), // Rule ID 27349 //
     /*  833216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  833219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  833227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  833230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  833233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833237 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p3:{ *:[i32] }:$src, p3:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833237 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833240 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833244 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833249 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833259 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833264 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833266 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833269 */     GIR_RootConstrainSelectedInstOperands,
     /*  833270 */     // GIR_Coverage, 27349,
     /*  833270 */     GIR_EraseRootFromParent_Done,
     /*  833271 */   // Label 13424: @833271
     /*  833271 */   GIM_Try, /*On fail goto*//*Label 13425*/ GIMT_Encode4(833331), // Rule ID 27350 //
     /*  833276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  833279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  833287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  833290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  833293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833297 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p5:{ *:[i32] }:$src, p5:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833297 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833300 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833304 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833309 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833319 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833324 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833326 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833329 */     GIR_RootConstrainSelectedInstOperands,
     /*  833330 */     // GIR_Coverage, 27350,
     /*  833330 */     GIR_EraseRootFromParent_Done,
     /*  833331 */   // Label 13425: @833331
     /*  833331 */   GIM_Try, /*On fail goto*//*Label 13426*/ GIMT_Encode4(833391), // Rule ID 27351 //
     /*  833336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  833339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  833347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  833350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  833353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833357 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p5:{ *:[i32] }:$src, p5:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833357 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833360 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833364 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833369 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833379 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833384 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833386 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833389 */     GIR_RootConstrainSelectedInstOperands,
     /*  833390 */     // GIR_Coverage, 27351,
     /*  833390 */     GIR_EraseRootFromParent_Done,
     /*  833391 */   // Label 13426: @833391
     /*  833391 */   GIM_Try, /*On fail goto*//*Label 13427*/ GIMT_Encode4(833451), // Rule ID 27352 //
     /*  833396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  833399 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833404 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  833407 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  833410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  833413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833417 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p5:{ *:[i32] }:$src, p5:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833417 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833420 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833424 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833429 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833439 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833444 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833446 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833449 */     GIR_RootConstrainSelectedInstOperands,
     /*  833450 */     // GIR_Coverage, 27352,
     /*  833450 */     GIR_EraseRootFromParent_Done,
     /*  833451 */   // Label 13427: @833451
     /*  833451 */   GIM_Try, /*On fail goto*//*Label 13428*/ GIMT_Encode4(833511), // Rule ID 27353 //
     /*  833456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  833459 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833464 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  833467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  833470 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  833473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833477 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p5:{ *:[i32] }:$src, p5:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833477 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833480 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833484 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833489 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833499 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833504 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833506 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833509 */     GIR_RootConstrainSelectedInstOperands,
     /*  833510 */     // GIR_Coverage, 27353,
     /*  833510 */     GIR_EraseRootFromParent_Done,
     /*  833511 */   // Label 13428: @833511
     /*  833511 */   GIM_Try, /*On fail goto*//*Label 13429*/ GIMT_Encode4(833571), // Rule ID 27354 //
     /*  833516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  833519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  833527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  833530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  833533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833537 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p5:{ *:[i32] }:$src, p5:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833537 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833540 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833544 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833549 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833559 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833564 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833566 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833569 */     GIR_RootConstrainSelectedInstOperands,
     /*  833570 */     // GIR_Coverage, 27354,
     /*  833570 */     GIR_EraseRootFromParent_Done,
     /*  833571 */   // Label 13429: @833571
     /*  833571 */   GIM_Try, /*On fail goto*//*Label 13430*/ GIMT_Encode4(833631), // Rule ID 27355 //
     /*  833576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  833579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  833587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  833590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  833593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833597 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p6:{ *:[i32] }:$src, p6:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833597 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833600 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833604 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833609 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833619 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833624 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833626 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833629 */     GIR_RootConstrainSelectedInstOperands,
     /*  833630 */     // GIR_Coverage, 27355,
     /*  833630 */     GIR_EraseRootFromParent_Done,
     /*  833631 */   // Label 13430: @833631
     /*  833631 */   GIM_Try, /*On fail goto*//*Label 13431*/ GIMT_Encode4(833691), // Rule ID 27356 //
     /*  833636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  833639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  833647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  833650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  833653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833657 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p6:{ *:[i32] }:$src, p6:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833657 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833660 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833664 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833669 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833679 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833684 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833686 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833689 */     GIR_RootConstrainSelectedInstOperands,
     /*  833690 */     // GIR_Coverage, 27356,
     /*  833690 */     GIR_EraseRootFromParent_Done,
     /*  833691 */   // Label 13431: @833691
     /*  833691 */   GIM_Try, /*On fail goto*//*Label 13432*/ GIMT_Encode4(833751), // Rule ID 27357 //
     /*  833696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  833699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  833707 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  833710 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  833713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833717 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p6:{ *:[i32] }:$src, p6:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833717 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833720 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833724 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833729 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833739 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833744 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833746 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833749 */     GIR_RootConstrainSelectedInstOperands,
     /*  833750 */     // GIR_Coverage, 27357,
     /*  833750 */     GIR_EraseRootFromParent_Done,
     /*  833751 */   // Label 13432: @833751
     /*  833751 */   GIM_Try, /*On fail goto*//*Label 13433*/ GIMT_Encode4(833811), // Rule ID 27358 //
     /*  833756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  833759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  833767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  833770 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  833773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833777 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p6:{ *:[i32] }:$src, p6:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833777 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833780 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833784 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833789 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833799 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833804 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833806 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833809 */     GIR_RootConstrainSelectedInstOperands,
     /*  833810 */     // GIR_Coverage, 27358,
     /*  833810 */     GIR_EraseRootFromParent_Done,
     /*  833811 */   // Label 13433: @833811
     /*  833811 */   GIM_Try, /*On fail goto*//*Label 13434*/ GIMT_Encode4(833871), // Rule ID 27359 //
     /*  833816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  833819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
     /*  833824 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  833827 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  833830 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  833833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833837 */     // (intrinsic_wo_chain:{ *:[i32] } 3486:{ *:[iPTR] }, p6:{ *:[i32] }:$src, p6:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$src, 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833837 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833840 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833844 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833849 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833859 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833864 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833866 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833869 */     GIR_RootConstrainSelectedInstOperands,
     /*  833870 */     // GIR_Coverage, 27359,
     /*  833870 */     GIR_EraseRootFromParent_Done,
     /*  833871 */   // Label 13434: @833871
     /*  833871 */   GIM_Try, /*On fail goto*//*Label 13435*/ GIMT_Encode4(833931), // Rule ID 27360 //
     /*  833876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  833879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
     /*  833884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  833887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  833890 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  833893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833897 */     // (intrinsic_wo_chain:{ *:[i32] } 3487:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833897 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833900 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833904 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833909 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833919 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833924 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833926 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833929 */     GIR_RootConstrainSelectedInstOperands,
     /*  833930 */     // GIR_Coverage, 27360,
     /*  833930 */     GIR_EraseRootFromParent_Done,
     /*  833931 */   // Label 13435: @833931
     /*  833931 */   GIM_Try, /*On fail goto*//*Label 13436*/ GIMT_Encode4(833991), // Rule ID 27361 //
     /*  833936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  833939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
     /*  833944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  833947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  833950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  833953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  833957 */     // (intrinsic_wo_chain:{ *:[i32] } 3487:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  833957 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  833960 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  833964 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  833969 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  833971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  833974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  833976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833979 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  833981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  833984 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  833986 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  833989 */     GIR_RootConstrainSelectedInstOperands,
     /*  833990 */     // GIR_Coverage, 27361,
     /*  833990 */     GIR_EraseRootFromParent_Done,
     /*  833991 */   // Label 13436: @833991
     /*  833991 */   GIM_Try, /*On fail goto*//*Label 13437*/ GIMT_Encode4(834051), // Rule ID 27362 //
     /*  833996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  833999 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
     /*  834004 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834007 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834010 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  834013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  834017 */     // (intrinsic_wo_chain:{ *:[i32] } 3487:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  834017 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  834020 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  834024 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  834029 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  834031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  834034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  834036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  834039 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  834044 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  834046 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  834049 */     GIR_RootConstrainSelectedInstOperands,
     /*  834050 */     // GIR_Coverage, 27362,
     /*  834050 */     GIR_EraseRootFromParent_Done,
     /*  834051 */   // Label 13437: @834051
     /*  834051 */   GIM_Try, /*On fail goto*//*Label 13438*/ GIMT_Encode4(834111), // Rule ID 27363 //
     /*  834056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  834059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
     /*  834064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834070 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  834073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  834077 */     // (intrinsic_wo_chain:{ *:[i32] } 3487:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  834077 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  834080 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  834084 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  834089 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  834091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  834094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  834096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  834099 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  834104 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  834106 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  834109 */     GIR_RootConstrainSelectedInstOperands,
     /*  834110 */     // GIR_Coverage, 27363,
     /*  834110 */     GIR_EraseRootFromParent_Done,
     /*  834111 */   // Label 13438: @834111
     /*  834111 */   GIM_Try, /*On fail goto*//*Label 13439*/ GIMT_Encode4(834171), // Rule ID 27364 //
     /*  834116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  834119 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
     /*  834124 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834127 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834130 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  834133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  834137 */     // (intrinsic_wo_chain:{ *:[i32] } 3487:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$src, 0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$inactive, (IMPLICIT_DEF:{ *:[i1] }))
     /*  834137 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  834140 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  834144 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  834149 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  834151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
     /*  834154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  834156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  834159 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  834164 */     GIR_RootToRootCopy, /*OpIdx*/3, // inactive
     /*  834166 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  834169 */     GIR_RootConstrainSelectedInstOperands,
     /*  834170 */     // GIR_Coverage, 27364,
     /*  834170 */     GIR_EraseRootFromParent_Done,
     /*  834171 */   // Label 13439: @834171
     /*  834171 */   GIM_Try, /*On fail goto*//*Label 13440*/ GIMT_Encode4(834202), // Rule ID 4169 //
     /*  834176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
     /*  834181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834184 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834191 */     // MIs[0] strategy
     /*  834191 */     // No operand predicates
     /*  834191 */     // (intrinsic_wo_chain:{ *:[i32] } 3626:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U32),
     /*  834194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834196 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834198 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834200 */     GIR_RootConstrainSelectedInstOperands,
     /*  834201 */     // GIR_Coverage, 4169,
     /*  834201 */     GIR_EraseRootFromParent_Done,
     /*  834202 */   // Label 13440: @834202
     /*  834202 */   GIM_Try, /*On fail goto*//*Label 13441*/ GIMT_Encode4(834233), // Rule ID 4170 //
     /*  834207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_min),
     /*  834212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834222 */     // MIs[0] strategy
     /*  834222 */     // No operand predicates
     /*  834222 */     // (intrinsic_wo_chain:{ *:[i32] } 3622:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MIN_PSEUDO_I32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I32),
     /*  834225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834229 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834231 */     GIR_RootConstrainSelectedInstOperands,
     /*  834232 */     // GIR_Coverage, 4170,
     /*  834232 */     GIR_EraseRootFromParent_Done,
     /*  834233 */   // Label 13441: @834233
     /*  834233 */   GIM_Try, /*On fail goto*//*Label 13442*/ GIMT_Encode4(834264), // Rule ID 4171 //
     /*  834238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
     /*  834243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834253 */     // MIs[0] strategy
     /*  834253 */     // No operand predicates
     /*  834253 */     // (intrinsic_wo_chain:{ *:[i32] } 3625:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U32),
     /*  834256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834258 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834260 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834262 */     GIR_RootConstrainSelectedInstOperands,
     /*  834263 */     // GIR_Coverage, 4171,
     /*  834263 */     GIR_EraseRootFromParent_Done,
     /*  834264 */   // Label 13442: @834264
     /*  834264 */   GIM_Try, /*On fail goto*//*Label 13443*/ GIMT_Encode4(834295), // Rule ID 4172 //
     /*  834269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_max),
     /*  834274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834284 */     // MIs[0] strategy
     /*  834284 */     // No operand predicates
     /*  834284 */     // (intrinsic_wo_chain:{ *:[i32] } 3621:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MAX_PSEUDO_I32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I32),
     /*  834287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834289 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834291 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834293 */     GIR_RootConstrainSelectedInstOperands,
     /*  834294 */     // GIR_Coverage, 4172,
     /*  834294 */     GIR_EraseRootFromParent_Done,
     /*  834295 */   // Label 13443: @834295
     /*  834295 */   GIM_Try, /*On fail goto*//*Label 13444*/ GIMT_Encode4(834326), // Rule ID 4173 //
     /*  834300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_add),
     /*  834305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834315 */     // MIs[0] strategy
     /*  834315 */     // No operand predicates
     /*  834315 */     // (intrinsic_wo_chain:{ *:[i32] } 3615:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_ADD_PSEUDO_I32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I32),
     /*  834318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834320 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834322 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834324 */     GIR_RootConstrainSelectedInstOperands,
     /*  834325 */     // GIR_Coverage, 4173,
     /*  834325 */     GIR_EraseRootFromParent_Done,
     /*  834326 */   // Label 13444: @834326
     /*  834326 */   GIM_Try, /*On fail goto*//*Label 13445*/ GIMT_Encode4(834357), // Rule ID 4174 //
     /*  834331 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_sub),
     /*  834336 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834339 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834342 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834346 */     // MIs[0] strategy
     /*  834346 */     // No operand predicates
     /*  834346 */     // (intrinsic_wo_chain:{ *:[i32] } 3624:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_SUB_PSEUDO_I32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_SUB_PSEUDO_I32),
     /*  834349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834351 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834353 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834355 */     GIR_RootConstrainSelectedInstOperands,
     /*  834356 */     // GIR_Coverage, 4174,
     /*  834356 */     GIR_EraseRootFromParent_Done,
     /*  834357 */   // Label 13445: @834357
     /*  834357 */   GIM_Try, /*On fail goto*//*Label 13446*/ GIMT_Encode4(834388), // Rule ID 4175 //
     /*  834362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_and),
     /*  834367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834377 */     // MIs[0] strategy
     /*  834377 */     // No operand predicates
     /*  834377 */     // (intrinsic_wo_chain:{ *:[i32] } 3616:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_AND_PSEUDO_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_AND_PSEUDO_B32),
     /*  834380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834382 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834384 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834386 */     GIR_RootConstrainSelectedInstOperands,
     /*  834387 */     // GIR_Coverage, 4175,
     /*  834387 */     GIR_EraseRootFromParent_Done,
     /*  834388 */   // Label 13446: @834388
     /*  834388 */   GIM_Try, /*On fail goto*//*Label 13447*/ GIMT_Encode4(834419), // Rule ID 4176 //
     /*  834393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_or),
     /*  834398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834408 */     // MIs[0] strategy
     /*  834408 */     // No operand predicates
     /*  834408 */     // (intrinsic_wo_chain:{ *:[i32] } 3623:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_OR_PSEUDO_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_OR_PSEUDO_B32),
     /*  834411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834413 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834415 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834417 */     GIR_RootConstrainSelectedInstOperands,
     /*  834418 */     // GIR_Coverage, 4176,
     /*  834418 */     GIR_EraseRootFromParent_Done,
     /*  834419 */   // Label 13447: @834419
     /*  834419 */   GIM_Try, /*On fail goto*//*Label 13448*/ GIMT_Encode4(834450), // Rule ID 4177 //
     /*  834424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_xor),
     /*  834429 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  834432 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  834435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  834439 */     // MIs[0] strategy
     /*  834439 */     // No operand predicates
     /*  834439 */     // (intrinsic_wo_chain:{ *:[i32] } 3627:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_XOR_PSEUDO_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B32),
     /*  834442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834444 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834446 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834448 */     GIR_RootConstrainSelectedInstOperands,
     /*  834449 */     // GIR_Coverage, 4177,
     /*  834449 */     GIR_EraseRootFromParent_Done,
     /*  834450 */   // Label 13448: @834450
     /*  834450 */   GIM_Try, /*On fail goto*//*Label 13449*/ GIMT_Encode4(834484), // Rule ID 4178 //
     /*  834455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  834458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
     /*  834463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834473 */     // MIs[0] strategy
     /*  834473 */     // No operand predicates
     /*  834473 */     // (intrinsic_wo_chain:{ *:[i64] } 3626:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U64),
     /*  834476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834478 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834480 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834482 */     GIR_RootConstrainSelectedInstOperands,
     /*  834483 */     // GIR_Coverage, 4178,
     /*  834483 */     GIR_EraseRootFromParent_Done,
     /*  834484 */   // Label 13449: @834484
     /*  834484 */   GIM_Try, /*On fail goto*//*Label 13450*/ GIMT_Encode4(834518), // Rule ID 4179 //
     /*  834489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  834492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
     /*  834497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834507 */     // MIs[0] strategy
     /*  834507 */     // No operand predicates
     /*  834507 */     // (intrinsic_wo_chain:{ *:[i64] } 3626:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U64),
     /*  834510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834512 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834514 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834516 */     GIR_RootConstrainSelectedInstOperands,
     /*  834517 */     // GIR_Coverage, 4179,
     /*  834517 */     GIR_EraseRootFromParent_Done,
     /*  834518 */   // Label 13450: @834518
     /*  834518 */   GIM_Try, /*On fail goto*//*Label 13451*/ GIMT_Encode4(834552), // Rule ID 4180 //
     /*  834523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  834526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
     /*  834531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834541 */     // MIs[0] strategy
     /*  834541 */     // No operand predicates
     /*  834541 */     // (intrinsic_wo_chain:{ *:[i64] } 3626:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U64),
     /*  834544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834546 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834548 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834550 */     GIR_RootConstrainSelectedInstOperands,
     /*  834551 */     // GIR_Coverage, 4180,
     /*  834551 */     GIR_EraseRootFromParent_Done,
     /*  834552 */   // Label 13451: @834552
     /*  834552 */   GIM_Try, /*On fail goto*//*Label 13452*/ GIMT_Encode4(834586), // Rule ID 4181 //
     /*  834557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  834560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
     /*  834565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834568 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834575 */     // MIs[0] strategy
     /*  834575 */     // No operand predicates
     /*  834575 */     // (intrinsic_wo_chain:{ *:[i64] } 3626:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U64),
     /*  834578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834580 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834582 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834584 */     GIR_RootConstrainSelectedInstOperands,
     /*  834585 */     // GIR_Coverage, 4181,
     /*  834585 */     GIR_EraseRootFromParent_Done,
     /*  834586 */   // Label 13452: @834586
     /*  834586 */   GIM_Try, /*On fail goto*//*Label 13453*/ GIMT_Encode4(834620), // Rule ID 4182 //
     /*  834591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  834594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
     /*  834599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834609 */     // MIs[0] strategy
     /*  834609 */     // No operand predicates
     /*  834609 */     // (intrinsic_wo_chain:{ *:[i64] } 3626:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U64),
     /*  834612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834614 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834616 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834618 */     GIR_RootConstrainSelectedInstOperands,
     /*  834619 */     // GIR_Coverage, 4182,
     /*  834619 */     GIR_EraseRootFromParent_Done,
     /*  834620 */   // Label 13453: @834620
     /*  834620 */   GIM_Try, /*On fail goto*//*Label 13454*/ GIMT_Encode4(834654), // Rule ID 4183 //
     /*  834625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  834628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_min),
     /*  834633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834643 */     // MIs[0] strategy
     /*  834643 */     // No operand predicates
     /*  834643 */     // (intrinsic_wo_chain:{ *:[i64] } 3622:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MIN_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I64),
     /*  834646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834648 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834650 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834652 */     GIR_RootConstrainSelectedInstOperands,
     /*  834653 */     // GIR_Coverage, 4183,
     /*  834653 */     GIR_EraseRootFromParent_Done,
     /*  834654 */   // Label 13454: @834654
     /*  834654 */   GIM_Try, /*On fail goto*//*Label 13455*/ GIMT_Encode4(834688), // Rule ID 4184 //
     /*  834659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  834662 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_min),
     /*  834667 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834670 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834677 */     // MIs[0] strategy
     /*  834677 */     // No operand predicates
     /*  834677 */     // (intrinsic_wo_chain:{ *:[i64] } 3622:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MIN_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I64),
     /*  834680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834682 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834684 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834686 */     GIR_RootConstrainSelectedInstOperands,
     /*  834687 */     // GIR_Coverage, 4184,
     /*  834687 */     GIR_EraseRootFromParent_Done,
     /*  834688 */   // Label 13455: @834688
     /*  834688 */   GIM_Try, /*On fail goto*//*Label 13456*/ GIMT_Encode4(834722), // Rule ID 4185 //
     /*  834693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  834696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_min),
     /*  834701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834711 */     // MIs[0] strategy
     /*  834711 */     // No operand predicates
     /*  834711 */     // (intrinsic_wo_chain:{ *:[i64] } 3622:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MIN_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I64),
     /*  834714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834716 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834718 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834720 */     GIR_RootConstrainSelectedInstOperands,
     /*  834721 */     // GIR_Coverage, 4185,
     /*  834721 */     GIR_EraseRootFromParent_Done,
     /*  834722 */   // Label 13456: @834722
     /*  834722 */   GIM_Try, /*On fail goto*//*Label 13457*/ GIMT_Encode4(834756), // Rule ID 4186 //
     /*  834727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  834730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_min),
     /*  834735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834745 */     // MIs[0] strategy
     /*  834745 */     // No operand predicates
     /*  834745 */     // (intrinsic_wo_chain:{ *:[i64] } 3622:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MIN_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I64),
     /*  834748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834750 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834752 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834754 */     GIR_RootConstrainSelectedInstOperands,
     /*  834755 */     // GIR_Coverage, 4186,
     /*  834755 */     GIR_EraseRootFromParent_Done,
     /*  834756 */   // Label 13457: @834756
     /*  834756 */   GIM_Try, /*On fail goto*//*Label 13458*/ GIMT_Encode4(834790), // Rule ID 4187 //
     /*  834761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  834764 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_min),
     /*  834769 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834779 */     // MIs[0] strategy
     /*  834779 */     // No operand predicates
     /*  834779 */     // (intrinsic_wo_chain:{ *:[i64] } 3622:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MIN_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I64),
     /*  834782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834784 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834786 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834788 */     GIR_RootConstrainSelectedInstOperands,
     /*  834789 */     // GIR_Coverage, 4187,
     /*  834789 */     GIR_EraseRootFromParent_Done,
     /*  834790 */   // Label 13458: @834790
     /*  834790 */   GIM_Try, /*On fail goto*//*Label 13459*/ GIMT_Encode4(834824), // Rule ID 4188 //
     /*  834795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  834798 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
     /*  834803 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834806 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834813 */     // MIs[0] strategy
     /*  834813 */     // No operand predicates
     /*  834813 */     // (intrinsic_wo_chain:{ *:[i64] } 3625:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64),
     /*  834816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834818 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834820 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834822 */     GIR_RootConstrainSelectedInstOperands,
     /*  834823 */     // GIR_Coverage, 4188,
     /*  834823 */     GIR_EraseRootFromParent_Done,
     /*  834824 */   // Label 13459: @834824
     /*  834824 */   GIM_Try, /*On fail goto*//*Label 13460*/ GIMT_Encode4(834858), // Rule ID 4189 //
     /*  834829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  834832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
     /*  834837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834847 */     // MIs[0] strategy
     /*  834847 */     // No operand predicates
     /*  834847 */     // (intrinsic_wo_chain:{ *:[i64] } 3625:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64),
     /*  834850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834852 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834854 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834856 */     GIR_RootConstrainSelectedInstOperands,
     /*  834857 */     // GIR_Coverage, 4189,
     /*  834857 */     GIR_EraseRootFromParent_Done,
     /*  834858 */   // Label 13460: @834858
     /*  834858 */   GIM_Try, /*On fail goto*//*Label 13461*/ GIMT_Encode4(834892), // Rule ID 4190 //
     /*  834863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  834866 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
     /*  834871 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834874 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834881 */     // MIs[0] strategy
     /*  834881 */     // No operand predicates
     /*  834881 */     // (intrinsic_wo_chain:{ *:[i64] } 3625:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64),
     /*  834884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834886 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834888 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834890 */     GIR_RootConstrainSelectedInstOperands,
     /*  834891 */     // GIR_Coverage, 4190,
     /*  834891 */     GIR_EraseRootFromParent_Done,
     /*  834892 */   // Label 13461: @834892
     /*  834892 */   GIM_Try, /*On fail goto*//*Label 13462*/ GIMT_Encode4(834926), // Rule ID 4191 //
     /*  834897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  834900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
     /*  834905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834915 */     // MIs[0] strategy
     /*  834915 */     // No operand predicates
     /*  834915 */     // (intrinsic_wo_chain:{ *:[i64] } 3625:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64),
     /*  834918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834920 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834922 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834924 */     GIR_RootConstrainSelectedInstOperands,
     /*  834925 */     // GIR_Coverage, 4191,
     /*  834925 */     GIR_EraseRootFromParent_Done,
     /*  834926 */   // Label 13462: @834926
     /*  834926 */   GIM_Try, /*On fail goto*//*Label 13463*/ GIMT_Encode4(834960), // Rule ID 4192 //
     /*  834931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  834934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
     /*  834939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834949 */     // MIs[0] strategy
     /*  834949 */     // No operand predicates
     /*  834949 */     // (intrinsic_wo_chain:{ *:[i64] } 3625:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64),
     /*  834952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834954 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834956 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834958 */     GIR_RootConstrainSelectedInstOperands,
     /*  834959 */     // GIR_Coverage, 4192,
     /*  834959 */     GIR_EraseRootFromParent_Done,
     /*  834960 */   // Label 13463: @834960
     /*  834960 */   GIM_Try, /*On fail goto*//*Label 13464*/ GIMT_Encode4(834994), // Rule ID 4193 //
     /*  834965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  834968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_max),
     /*  834973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  834976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  834979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  834983 */     // MIs[0] strategy
     /*  834983 */     // No operand predicates
     /*  834983 */     // (intrinsic_wo_chain:{ *:[i64] } 3621:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MAX_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  834983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I64),
     /*  834986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  834988 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  834990 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  834992 */     GIR_RootConstrainSelectedInstOperands,
     /*  834993 */     // GIR_Coverage, 4193,
     /*  834993 */     GIR_EraseRootFromParent_Done,
     /*  834994 */   // Label 13464: @834994
     /*  834994 */   GIM_Try, /*On fail goto*//*Label 13465*/ GIMT_Encode4(835028), // Rule ID 4194 //
     /*  834999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  835002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_max),
     /*  835007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835017 */     // MIs[0] strategy
     /*  835017 */     // No operand predicates
     /*  835017 */     // (intrinsic_wo_chain:{ *:[i64] } 3621:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MAX_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I64),
     /*  835020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835022 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835024 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835026 */     GIR_RootConstrainSelectedInstOperands,
     /*  835027 */     // GIR_Coverage, 4194,
     /*  835027 */     GIR_EraseRootFromParent_Done,
     /*  835028 */   // Label 13465: @835028
     /*  835028 */   GIM_Try, /*On fail goto*//*Label 13466*/ GIMT_Encode4(835062), // Rule ID 4195 //
     /*  835033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  835036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_max),
     /*  835041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835051 */     // MIs[0] strategy
     /*  835051 */     // No operand predicates
     /*  835051 */     // (intrinsic_wo_chain:{ *:[i64] } 3621:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MAX_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I64),
     /*  835054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835056 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835058 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835060 */     GIR_RootConstrainSelectedInstOperands,
     /*  835061 */     // GIR_Coverage, 4195,
     /*  835061 */     GIR_EraseRootFromParent_Done,
     /*  835062 */   // Label 13466: @835062
     /*  835062 */   GIM_Try, /*On fail goto*//*Label 13467*/ GIMT_Encode4(835096), // Rule ID 4196 //
     /*  835067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  835070 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_max),
     /*  835075 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835078 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835085 */     // MIs[0] strategy
     /*  835085 */     // No operand predicates
     /*  835085 */     // (intrinsic_wo_chain:{ *:[i64] } 3621:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MAX_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I64),
     /*  835088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835090 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835092 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835094 */     GIR_RootConstrainSelectedInstOperands,
     /*  835095 */     // GIR_Coverage, 4196,
     /*  835095 */     GIR_EraseRootFromParent_Done,
     /*  835096 */   // Label 13467: @835096
     /*  835096 */   GIM_Try, /*On fail goto*//*Label 13468*/ GIMT_Encode4(835130), // Rule ID 4197 //
     /*  835101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  835104 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_max),
     /*  835109 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835119 */     // MIs[0] strategy
     /*  835119 */     // No operand predicates
     /*  835119 */     // (intrinsic_wo_chain:{ *:[i64] } 3621:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_MAX_PSEUDO_I64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I64),
     /*  835122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835124 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835126 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835128 */     GIR_RootConstrainSelectedInstOperands,
     /*  835129 */     // GIR_Coverage, 4197,
     /*  835129 */     GIR_EraseRootFromParent_Done,
     /*  835130 */   // Label 13468: @835130
     /*  835130 */   GIM_Try, /*On fail goto*//*Label 13469*/ GIMT_Encode4(835164), // Rule ID 4198 //
     /*  835135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  835138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_add),
     /*  835143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835153 */     // MIs[0] strategy
     /*  835153 */     // No operand predicates
     /*  835153 */     // (intrinsic_wo_chain:{ *:[i64] } 3615:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_ADD_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64),
     /*  835156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835158 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835160 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835162 */     GIR_RootConstrainSelectedInstOperands,
     /*  835163 */     // GIR_Coverage, 4198,
     /*  835163 */     GIR_EraseRootFromParent_Done,
     /*  835164 */   // Label 13469: @835164
     /*  835164 */   GIM_Try, /*On fail goto*//*Label 13470*/ GIMT_Encode4(835198), // Rule ID 4199 //
     /*  835169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  835172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_add),
     /*  835177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835187 */     // MIs[0] strategy
     /*  835187 */     // No operand predicates
     /*  835187 */     // (intrinsic_wo_chain:{ *:[i64] } 3615:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_ADD_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64),
     /*  835190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835192 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835194 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835196 */     GIR_RootConstrainSelectedInstOperands,
     /*  835197 */     // GIR_Coverage, 4199,
     /*  835197 */     GIR_EraseRootFromParent_Done,
     /*  835198 */   // Label 13470: @835198
     /*  835198 */   GIM_Try, /*On fail goto*//*Label 13471*/ GIMT_Encode4(835232), // Rule ID 4200 //
     /*  835203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  835206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_add),
     /*  835211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835221 */     // MIs[0] strategy
     /*  835221 */     // No operand predicates
     /*  835221 */     // (intrinsic_wo_chain:{ *:[i64] } 3615:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_ADD_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64),
     /*  835224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835226 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835228 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835230 */     GIR_RootConstrainSelectedInstOperands,
     /*  835231 */     // GIR_Coverage, 4200,
     /*  835231 */     GIR_EraseRootFromParent_Done,
     /*  835232 */   // Label 13471: @835232
     /*  835232 */   GIM_Try, /*On fail goto*//*Label 13472*/ GIMT_Encode4(835266), // Rule ID 4201 //
     /*  835237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  835240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_add),
     /*  835245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835255 */     // MIs[0] strategy
     /*  835255 */     // No operand predicates
     /*  835255 */     // (intrinsic_wo_chain:{ *:[i64] } 3615:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_ADD_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64),
     /*  835258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835260 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835262 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835264 */     GIR_RootConstrainSelectedInstOperands,
     /*  835265 */     // GIR_Coverage, 4201,
     /*  835265 */     GIR_EraseRootFromParent_Done,
     /*  835266 */   // Label 13472: @835266
     /*  835266 */   GIM_Try, /*On fail goto*//*Label 13473*/ GIMT_Encode4(835300), // Rule ID 4202 //
     /*  835271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  835274 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_add),
     /*  835279 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835282 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835289 */     // MIs[0] strategy
     /*  835289 */     // No operand predicates
     /*  835289 */     // (intrinsic_wo_chain:{ *:[i64] } 3615:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_ADD_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64),
     /*  835292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835294 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835296 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835298 */     GIR_RootConstrainSelectedInstOperands,
     /*  835299 */     // GIR_Coverage, 4202,
     /*  835299 */     GIR_EraseRootFromParent_Done,
     /*  835300 */   // Label 13473: @835300
     /*  835300 */   GIM_Try, /*On fail goto*//*Label 13474*/ GIMT_Encode4(835334), // Rule ID 4203 //
     /*  835305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  835308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_sub),
     /*  835313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835323 */     // MIs[0] strategy
     /*  835323 */     // No operand predicates
     /*  835323 */     // (intrinsic_wo_chain:{ *:[i64] } 3624:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_SUB_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_SUB_PSEUDO_U64),
     /*  835326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835328 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835330 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835332 */     GIR_RootConstrainSelectedInstOperands,
     /*  835333 */     // GIR_Coverage, 4203,
     /*  835333 */     GIR_EraseRootFromParent_Done,
     /*  835334 */   // Label 13474: @835334
     /*  835334 */   GIM_Try, /*On fail goto*//*Label 13475*/ GIMT_Encode4(835368), // Rule ID 4204 //
     /*  835339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  835342 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_sub),
     /*  835347 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835350 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835357 */     // MIs[0] strategy
     /*  835357 */     // No operand predicates
     /*  835357 */     // (intrinsic_wo_chain:{ *:[i64] } 3624:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_SUB_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_SUB_PSEUDO_U64),
     /*  835360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835362 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835364 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835366 */     GIR_RootConstrainSelectedInstOperands,
     /*  835367 */     // GIR_Coverage, 4204,
     /*  835367 */     GIR_EraseRootFromParent_Done,
     /*  835368 */   // Label 13475: @835368
     /*  835368 */   GIM_Try, /*On fail goto*//*Label 13476*/ GIMT_Encode4(835402), // Rule ID 4205 //
     /*  835373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  835376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_sub),
     /*  835381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835391 */     // MIs[0] strategy
     /*  835391 */     // No operand predicates
     /*  835391 */     // (intrinsic_wo_chain:{ *:[i64] } 3624:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_SUB_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_SUB_PSEUDO_U64),
     /*  835394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835396 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835398 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835400 */     GIR_RootConstrainSelectedInstOperands,
     /*  835401 */     // GIR_Coverage, 4205,
     /*  835401 */     GIR_EraseRootFromParent_Done,
     /*  835402 */   // Label 13476: @835402
     /*  835402 */   GIM_Try, /*On fail goto*//*Label 13477*/ GIMT_Encode4(835436), // Rule ID 4206 //
     /*  835407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  835410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_sub),
     /*  835415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835418 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835425 */     // MIs[0] strategy
     /*  835425 */     // No operand predicates
     /*  835425 */     // (intrinsic_wo_chain:{ *:[i64] } 3624:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_SUB_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_SUB_PSEUDO_U64),
     /*  835428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835430 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835432 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835434 */     GIR_RootConstrainSelectedInstOperands,
     /*  835435 */     // GIR_Coverage, 4206,
     /*  835435 */     GIR_EraseRootFromParent_Done,
     /*  835436 */   // Label 13477: @835436
     /*  835436 */   GIM_Try, /*On fail goto*//*Label 13478*/ GIMT_Encode4(835470), // Rule ID 4207 //
     /*  835441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  835444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_sub),
     /*  835449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835459 */     // MIs[0] strategy
     /*  835459 */     // No operand predicates
     /*  835459 */     // (intrinsic_wo_chain:{ *:[i64] } 3624:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_SUB_PSEUDO_U64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_SUB_PSEUDO_U64),
     /*  835462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835464 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835466 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835468 */     GIR_RootConstrainSelectedInstOperands,
     /*  835469 */     // GIR_Coverage, 4207,
     /*  835469 */     GIR_EraseRootFromParent_Done,
     /*  835470 */   // Label 13478: @835470
     /*  835470 */   GIM_Try, /*On fail goto*//*Label 13479*/ GIMT_Encode4(835504), // Rule ID 4208 //
     /*  835475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  835478 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_and),
     /*  835483 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835486 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835493 */     // MIs[0] strategy
     /*  835493 */     // No operand predicates
     /*  835493 */     // (intrinsic_wo_chain:{ *:[i64] } 3616:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_AND_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64),
     /*  835496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835498 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835500 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835502 */     GIR_RootConstrainSelectedInstOperands,
     /*  835503 */     // GIR_Coverage, 4208,
     /*  835503 */     GIR_EraseRootFromParent_Done,
     /*  835504 */   // Label 13479: @835504
     /*  835504 */   GIM_Try, /*On fail goto*//*Label 13480*/ GIMT_Encode4(835538), // Rule ID 4209 //
     /*  835509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  835512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_and),
     /*  835517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835527 */     // MIs[0] strategy
     /*  835527 */     // No operand predicates
     /*  835527 */     // (intrinsic_wo_chain:{ *:[i64] } 3616:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_AND_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64),
     /*  835530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835532 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835534 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835536 */     GIR_RootConstrainSelectedInstOperands,
     /*  835537 */     // GIR_Coverage, 4209,
     /*  835537 */     GIR_EraseRootFromParent_Done,
     /*  835538 */   // Label 13480: @835538
     /*  835538 */   GIM_Try, /*On fail goto*//*Label 13481*/ GIMT_Encode4(835572), // Rule ID 4210 //
     /*  835543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  835546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_and),
     /*  835551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835561 */     // MIs[0] strategy
     /*  835561 */     // No operand predicates
     /*  835561 */     // (intrinsic_wo_chain:{ *:[i64] } 3616:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_AND_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64),
     /*  835564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835566 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835568 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835570 */     GIR_RootConstrainSelectedInstOperands,
     /*  835571 */     // GIR_Coverage, 4210,
     /*  835571 */     GIR_EraseRootFromParent_Done,
     /*  835572 */   // Label 13481: @835572
     /*  835572 */   GIM_Try, /*On fail goto*//*Label 13482*/ GIMT_Encode4(835606), // Rule ID 4211 //
     /*  835577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  835580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_and),
     /*  835585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835595 */     // MIs[0] strategy
     /*  835595 */     // No operand predicates
     /*  835595 */     // (intrinsic_wo_chain:{ *:[i64] } 3616:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_AND_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64),
     /*  835598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835600 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835602 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835604 */     GIR_RootConstrainSelectedInstOperands,
     /*  835605 */     // GIR_Coverage, 4211,
     /*  835605 */     GIR_EraseRootFromParent_Done,
     /*  835606 */   // Label 13482: @835606
     /*  835606 */   GIM_Try, /*On fail goto*//*Label 13483*/ GIMT_Encode4(835640), // Rule ID 4212 //
     /*  835611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  835614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_and),
     /*  835619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835629 */     // MIs[0] strategy
     /*  835629 */     // No operand predicates
     /*  835629 */     // (intrinsic_wo_chain:{ *:[i64] } 3616:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_AND_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_AND_PSEUDO_B64),
     /*  835632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835634 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835636 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835638 */     GIR_RootConstrainSelectedInstOperands,
     /*  835639 */     // GIR_Coverage, 4212,
     /*  835639 */     GIR_EraseRootFromParent_Done,
     /*  835640 */   // Label 13483: @835640
     /*  835640 */   GIM_Try, /*On fail goto*//*Label 13484*/ GIMT_Encode4(835674), // Rule ID 4213 //
     /*  835645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  835648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_or),
     /*  835653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835663 */     // MIs[0] strategy
     /*  835663 */     // No operand predicates
     /*  835663 */     // (intrinsic_wo_chain:{ *:[i64] } 3623:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_OR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64),
     /*  835666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835668 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835670 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835672 */     GIR_RootConstrainSelectedInstOperands,
     /*  835673 */     // GIR_Coverage, 4213,
     /*  835673 */     GIR_EraseRootFromParent_Done,
     /*  835674 */   // Label 13484: @835674
     /*  835674 */   GIM_Try, /*On fail goto*//*Label 13485*/ GIMT_Encode4(835708), // Rule ID 4214 //
     /*  835679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  835682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_or),
     /*  835687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835697 */     // MIs[0] strategy
     /*  835697 */     // No operand predicates
     /*  835697 */     // (intrinsic_wo_chain:{ *:[i64] } 3623:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_OR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64),
     /*  835700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835702 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835704 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835706 */     GIR_RootConstrainSelectedInstOperands,
     /*  835707 */     // GIR_Coverage, 4214,
     /*  835707 */     GIR_EraseRootFromParent_Done,
     /*  835708 */   // Label 13485: @835708
     /*  835708 */   GIM_Try, /*On fail goto*//*Label 13486*/ GIMT_Encode4(835742), // Rule ID 4215 //
     /*  835713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  835716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_or),
     /*  835721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835731 */     // MIs[0] strategy
     /*  835731 */     // No operand predicates
     /*  835731 */     // (intrinsic_wo_chain:{ *:[i64] } 3623:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_OR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64),
     /*  835734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835736 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835738 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835740 */     GIR_RootConstrainSelectedInstOperands,
     /*  835741 */     // GIR_Coverage, 4215,
     /*  835741 */     GIR_EraseRootFromParent_Done,
     /*  835742 */   // Label 13486: @835742
     /*  835742 */   GIM_Try, /*On fail goto*//*Label 13487*/ GIMT_Encode4(835776), // Rule ID 4216 //
     /*  835747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  835750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_or),
     /*  835755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835765 */     // MIs[0] strategy
     /*  835765 */     // No operand predicates
     /*  835765 */     // (intrinsic_wo_chain:{ *:[i64] } 3623:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_OR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64),
     /*  835768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835770 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835772 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835774 */     GIR_RootConstrainSelectedInstOperands,
     /*  835775 */     // GIR_Coverage, 4216,
     /*  835775 */     GIR_EraseRootFromParent_Done,
     /*  835776 */   // Label 13487: @835776
     /*  835776 */   GIM_Try, /*On fail goto*//*Label 13488*/ GIMT_Encode4(835810), // Rule ID 4217 //
     /*  835781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  835784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_or),
     /*  835789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835792 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835799 */     // MIs[0] strategy
     /*  835799 */     // No operand predicates
     /*  835799 */     // (intrinsic_wo_chain:{ *:[i64] } 3623:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_OR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_OR_PSEUDO_B64),
     /*  835802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835804 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835806 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835808 */     GIR_RootConstrainSelectedInstOperands,
     /*  835809 */     // GIR_Coverage, 4217,
     /*  835809 */     GIR_EraseRootFromParent_Done,
     /*  835810 */   // Label 13488: @835810
     /*  835810 */   GIM_Try, /*On fail goto*//*Label 13489*/ GIMT_Encode4(835844), // Rule ID 4218 //
     /*  835815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  835818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_xor),
     /*  835823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835826 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835833 */     // MIs[0] strategy
     /*  835833 */     // No operand predicates
     /*  835833 */     // (intrinsic_wo_chain:{ *:[i64] } 3627:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_XOR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B64),
     /*  835836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835838 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835840 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835842 */     GIR_RootConstrainSelectedInstOperands,
     /*  835843 */     // GIR_Coverage, 4218,
     /*  835843 */     GIR_EraseRootFromParent_Done,
     /*  835844 */   // Label 13489: @835844
     /*  835844 */   GIM_Try, /*On fail goto*//*Label 13490*/ GIMT_Encode4(835878), // Rule ID 4219 //
     /*  835849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  835852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_xor),
     /*  835857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835867 */     // MIs[0] strategy
     /*  835867 */     // No operand predicates
     /*  835867 */     // (intrinsic_wo_chain:{ *:[i64] } 3627:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_XOR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B64),
     /*  835870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835872 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835874 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835876 */     GIR_RootConstrainSelectedInstOperands,
     /*  835877 */     // GIR_Coverage, 4219,
     /*  835877 */     GIR_EraseRootFromParent_Done,
     /*  835878 */   // Label 13490: @835878
     /*  835878 */   GIM_Try, /*On fail goto*//*Label 13491*/ GIMT_Encode4(835912), // Rule ID 4220 //
     /*  835883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  835886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_xor),
     /*  835891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835901 */     // MIs[0] strategy
     /*  835901 */     // No operand predicates
     /*  835901 */     // (intrinsic_wo_chain:{ *:[i64] } 3627:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_XOR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B64),
     /*  835904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835906 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835908 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835910 */     GIR_RootConstrainSelectedInstOperands,
     /*  835911 */     // GIR_Coverage, 4220,
     /*  835911 */     GIR_EraseRootFromParent_Done,
     /*  835912 */   // Label 13491: @835912
     /*  835912 */   GIM_Try, /*On fail goto*//*Label 13492*/ GIMT_Encode4(835946), // Rule ID 4221 //
     /*  835917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  835920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_xor),
     /*  835925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835935 */     // MIs[0] strategy
     /*  835935 */     // No operand predicates
     /*  835935 */     // (intrinsic_wo_chain:{ *:[i64] } 3627:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_XOR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B64),
     /*  835938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835940 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835942 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835944 */     GIR_RootConstrainSelectedInstOperands,
     /*  835945 */     // GIR_Coverage, 4221,
     /*  835945 */     GIR_EraseRootFromParent_Done,
     /*  835946 */   // Label 13492: @835946
     /*  835946 */   GIM_Try, /*On fail goto*//*Label 13493*/ GIMT_Encode4(835980), // Rule ID 4222 //
     /*  835951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  835954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_xor),
     /*  835959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  835962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  835965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_64RegClassID),
     /*  835969 */     // MIs[0] strategy
     /*  835969 */     // No operand predicates
     /*  835969 */     // (intrinsic_wo_chain:{ *:[i64] } 3627:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_XOR_PSEUDO_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i32:{ *:[i32] }:$strategy)
     /*  835969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_XOR_PSEUDO_B64),
     /*  835972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  835974 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  835976 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  835978 */     GIR_RootConstrainSelectedInstOperands,
     /*  835979 */     // GIR_Coverage, 4222,
     /*  835979 */     GIR_EraseRootFromParent_Done,
     /*  835980 */   // Label 13493: @835980
     /*  835980 */   GIM_Try, /*On fail goto*//*Label 13494*/ GIMT_Encode4(836011), // Rule ID 4223 //
     /*  835985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_fmin),
     /*  835990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  835993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  835996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  836000 */     // MIs[0] strategy
     /*  836000 */     // No operand predicates
     /*  836000 */     // (intrinsic_wo_chain:{ *:[f32] } 3619:{ *:[iPTR] }, f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_FMIN_PSEUDO_F32:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  836000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_FMIN_PSEUDO_F32),
     /*  836003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  836005 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  836007 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  836009 */     GIR_RootConstrainSelectedInstOperands,
     /*  836010 */     // GIR_Coverage, 4223,
     /*  836010 */     GIR_EraseRootFromParent_Done,
     /*  836011 */   // Label 13494: @836011
     /*  836011 */   GIM_Try, /*On fail goto*//*Label 13495*/ GIMT_Encode4(836042), // Rule ID 4224 //
     /*  836016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_fmax),
     /*  836021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  836024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  836027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  836031 */     // MIs[0] strategy
     /*  836031 */     // No operand predicates
     /*  836031 */     // (intrinsic_wo_chain:{ *:[f32] } 3618:{ *:[iPTR] }, f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_FMAX_PSEUDO_F32:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  836031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_FMAX_PSEUDO_F32),
     /*  836034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  836036 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  836038 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  836040 */     GIR_RootConstrainSelectedInstOperands,
     /*  836041 */     // GIR_Coverage, 4224,
     /*  836041 */     GIR_EraseRootFromParent_Done,
     /*  836042 */   // Label 13495: @836042
     /*  836042 */   GIM_Try, /*On fail goto*//*Label 13496*/ GIMT_Encode4(836073), // Rule ID 4225 //
     /*  836047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_fadd),
     /*  836052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  836055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  836058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  836062 */     // MIs[0] strategy
     /*  836062 */     // No operand predicates
     /*  836062 */     // (intrinsic_wo_chain:{ *:[f32] } 3617:{ *:[iPTR] }, f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_FADD_PSEUDO_F32:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  836062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_FADD_PSEUDO_F32),
     /*  836065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  836067 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  836069 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  836071 */     GIR_RootConstrainSelectedInstOperands,
     /*  836072 */     // GIR_Coverage, 4225,
     /*  836072 */     GIR_EraseRootFromParent_Done,
     /*  836073 */   // Label 13496: @836073
     /*  836073 */   GIM_Try, /*On fail goto*//*Label 13497*/ GIMT_Encode4(836104), // Rule ID 4226 //
     /*  836078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_fsub),
     /*  836083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  836086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  836089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  836093 */     // MIs[0] strategy
     /*  836093 */     // No operand predicates
     /*  836093 */     // (intrinsic_wo_chain:{ *:[f32] } 3620:{ *:[iPTR] }, f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_FSUB_PSEUDO_F32:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$strategy)
     /*  836093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_FSUB_PSEUDO_F32),
     /*  836096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  836098 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  836100 */     GIR_RootToRootCopy, /*OpIdx*/3, // strategy
     /*  836102 */     GIR_RootConstrainSelectedInstOperands,
     /*  836103 */     // GIR_Coverage, 4226,
     /*  836103 */     GIR_EraseRootFromParent_Done,
     /*  836104 */   // Label 13497: @836104
     /*  836104 */   GIM_Reject,
     /*  836105 */ // Label 13349: @836105
     /*  836105 */ GIM_Try, /*On fail goto*//*Label 13498*/ GIMT_Encode4(849064),
     /*  836110 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /*  836113 */   GIM_Try, /*On fail goto*//*Label 13499*/ GIMT_Encode4(836204), // Rule ID 7733 //
     /*  836118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  836121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  836129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  836132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  836135 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  836138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  836142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836149 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836156 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836163 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  836163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr),
     /*  836166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836202 */     GIR_RootConstrainSelectedInstOperands,
     /*  836203 */     // GIR_Coverage, 7733,
     /*  836203 */     GIR_EraseRootFromParent_Done,
     /*  836204 */   // Label 13499: @836204
     /*  836204 */   GIM_Try, /*On fail goto*//*Label 13500*/ GIMT_Encode4(836295), // Rule ID 7734 //
     /*  836209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  836212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  836220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  836223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  836226 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  836229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  836233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836240 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836247 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836254 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  836254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr),
     /*  836257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836293 */     GIR_RootConstrainSelectedInstOperands,
     /*  836294 */     // GIR_Coverage, 7734,
     /*  836294 */     GIR_EraseRootFromParent_Done,
     /*  836295 */   // Label 13500: @836295
     /*  836295 */   GIM_Try, /*On fail goto*//*Label 13501*/ GIMT_Encode4(836386), // Rule ID 7735 //
     /*  836300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  836303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  836311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  836314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  836317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  836320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  836324 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836345 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  836345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr),
     /*  836348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836384 */     GIR_RootConstrainSelectedInstOperands,
     /*  836385 */     // GIR_Coverage, 7735,
     /*  836385 */     GIR_EraseRootFromParent_Done,
     /*  836386 */   // Label 13501: @836386
     /*  836386 */   GIM_Try, /*On fail goto*//*Label 13502*/ GIMT_Encode4(836477), // Rule ID 7736 //
     /*  836391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  836394 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836399 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  836402 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  836405 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  836408 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  836411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  836415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836422 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836429 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836436 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  836436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr),
     /*  836439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836441 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836461 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836475 */     GIR_RootConstrainSelectedInstOperands,
     /*  836476 */     // GIR_Coverage, 7736,
     /*  836476 */     GIR_EraseRootFromParent_Done,
     /*  836477 */   // Label 13502: @836477
     /*  836477 */   GIM_Try, /*On fail goto*//*Label 13503*/ GIMT_Encode4(836568), // Rule ID 7737 //
     /*  836482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  836485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  836493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  836496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  836499 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  836502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  836506 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836527 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  836527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr),
     /*  836530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836537 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836542 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836566 */     GIR_RootConstrainSelectedInstOperands,
     /*  836567 */     // GIR_Coverage, 7737,
     /*  836567 */     GIR_EraseRootFromParent_Done,
     /*  836568 */   // Label 13503: @836568
     /*  836568 */   GIM_Try, /*On fail goto*//*Label 13504*/ GIMT_Encode4(836659), // Rule ID 7898 //
     /*  836573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  836576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  836584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  836587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  836590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  836593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  836597 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836618 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  836618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr),
     /*  836621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836657 */     GIR_RootConstrainSelectedInstOperands,
     /*  836658 */     // GIR_Coverage, 7898,
     /*  836658 */     GIR_EraseRootFromParent_Done,
     /*  836659 */   // Label 13504: @836659
     /*  836659 */   GIM_Try, /*On fail goto*//*Label 13505*/ GIMT_Encode4(836750), // Rule ID 7899 //
     /*  836664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  836667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  836675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  836678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  836681 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  836684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  836688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836702 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836709 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  836709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr),
     /*  836712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836748 */     GIR_RootConstrainSelectedInstOperands,
     /*  836749 */     // GIR_Coverage, 7899,
     /*  836749 */     GIR_EraseRootFromParent_Done,
     /*  836750 */   // Label 13505: @836750
     /*  836750 */   GIM_Try, /*On fail goto*//*Label 13506*/ GIMT_Encode4(836841), // Rule ID 7900 //
     /*  836755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  836758 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836763 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  836766 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  836769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  836772 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  836775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  836779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836800 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  836800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr),
     /*  836803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836839 */     GIR_RootConstrainSelectedInstOperands,
     /*  836840 */     // GIR_Coverage, 7900,
     /*  836840 */     GIR_EraseRootFromParent_Done,
     /*  836841 */   // Label 13506: @836841
     /*  836841 */   GIM_Try, /*On fail goto*//*Label 13507*/ GIMT_Encode4(836932), // Rule ID 7901 //
     /*  836846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  836849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  836857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  836860 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  836863 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  836866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  836870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836877 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836891 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  836891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr),
     /*  836894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  836911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  836916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  836919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  836924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836927 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  836930 */     GIR_RootConstrainSelectedInstOperands,
     /*  836931 */     // GIR_Coverage, 7901,
     /*  836931 */     GIR_EraseRootFromParent_Done,
     /*  836932 */   // Label 13507: @836932
     /*  836932 */   GIM_Try, /*On fail goto*//*Label 13508*/ GIMT_Encode4(837023), // Rule ID 7902 //
     /*  836937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  836940 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  836945 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  836948 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  836951 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  836954 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  836957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  836961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836968 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  836975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  836982 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  836982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr),
     /*  836985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  836987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  836992 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  836997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  837010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837021 */     GIR_RootConstrainSelectedInstOperands,
     /*  837022 */     // GIR_Coverage, 7902,
     /*  837022 */     GIR_EraseRootFromParent_Done,
     /*  837023 */   // Label 13508: @837023
     /*  837023 */   GIM_Try, /*On fail goto*//*Label 13509*/ GIMT_Encode4(837116), // Rule ID 7658 //
     /*  837028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  837031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  837036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837045 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837052 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837066 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837073 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32),
     /*  837076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837078 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837114 */     GIR_RootConstrainSelectedInstOperands,
     /*  837115 */     // GIR_Coverage, 7658,
     /*  837115 */     GIR_EraseRootFromParent_Done,
     /*  837116 */   // Label 13509: @837116
     /*  837116 */   GIM_Try, /*On fail goto*//*Label 13510*/ GIMT_Encode4(837209), // Rule ID 7659 //
     /*  837121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  837124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  837129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837135 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837138 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837152 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837166 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32),
     /*  837169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837207 */     GIR_RootConstrainSelectedInstOperands,
     /*  837208 */     // GIR_Coverage, 7659,
     /*  837208 */     GIR_EraseRootFromParent_Done,
     /*  837209 */   // Label 13510: @837209
     /*  837209 */   GIM_Try, /*On fail goto*//*Label 13511*/ GIMT_Encode4(837302), // Rule ID 7660 //
     /*  837214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  837217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  837222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837231 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837259 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32),
     /*  837262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837300 */     GIR_RootConstrainSelectedInstOperands,
     /*  837301 */     // GIR_Coverage, 7660,
     /*  837301 */     GIR_EraseRootFromParent_Done,
     /*  837302 */   // Label 13511: @837302
     /*  837302 */   GIM_Try, /*On fail goto*//*Label 13512*/ GIMT_Encode4(837395), // Rule ID 7661 //
     /*  837307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  837310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  837315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837321 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837324 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837345 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837352 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32),
     /*  837355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837367 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837372 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837377 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837390 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837393 */     GIR_RootConstrainSelectedInstOperands,
     /*  837394 */     // GIR_Coverage, 7661,
     /*  837394 */     GIR_EraseRootFromParent_Done,
     /*  837395 */   // Label 13512: @837395
     /*  837395 */   GIM_Try, /*On fail goto*//*Label 13513*/ GIMT_Encode4(837488), // Rule ID 7662 //
     /*  837400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  837403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  837408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837417 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837445 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32),
     /*  837448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837460 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837486 */     GIR_RootConstrainSelectedInstOperands,
     /*  837487 */     // GIR_Coverage, 7662,
     /*  837487 */     GIR_EraseRootFromParent_Done,
     /*  837488 */   // Label 13513: @837488
     /*  837488 */   GIM_Try, /*On fail goto*//*Label 13514*/ GIMT_Encode4(837581), // Rule ID 7663 //
     /*  837493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  837496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  837501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837510 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837538 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32),
     /*  837541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837579 */     GIR_RootConstrainSelectedInstOperands,
     /*  837580 */     // GIR_Coverage, 7663,
     /*  837580 */     GIR_EraseRootFromParent_Done,
     /*  837581 */   // Label 13514: @837581
     /*  837581 */   GIM_Try, /*On fail goto*//*Label 13515*/ GIMT_Encode4(837674), // Rule ID 7664 //
     /*  837586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  837589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  837594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837603 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837610 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837624 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837631 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32),
     /*  837634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837646 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837672 */     GIR_RootConstrainSelectedInstOperands,
     /*  837673 */     // GIR_Coverage, 7664,
     /*  837673 */     GIR_EraseRootFromParent_Done,
     /*  837674 */   // Label 13515: @837674
     /*  837674 */   GIM_Try, /*On fail goto*//*Label 13516*/ GIMT_Encode4(837767), // Rule ID 7665 //
     /*  837679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  837682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  837687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837693 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837696 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837710 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837724 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32),
     /*  837727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837734 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837765 */     GIR_RootConstrainSelectedInstOperands,
     /*  837766 */     // GIR_Coverage, 7665,
     /*  837766 */     GIR_EraseRootFromParent_Done,
     /*  837767 */   // Label 13516: @837767
     /*  837767 */   GIM_Try, /*On fail goto*//*Label 13517*/ GIMT_Encode4(837860), // Rule ID 7666 //
     /*  837772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  837775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  837780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837789 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837810 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837817 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32),
     /*  837820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837852 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837858 */     GIR_RootConstrainSelectedInstOperands,
     /*  837859 */     // GIR_Coverage, 7666,
     /*  837859 */     GIR_EraseRootFromParent_Done,
     /*  837860 */   // Label 13517: @837860
     /*  837860 */   GIM_Try, /*On fail goto*//*Label 13518*/ GIMT_Encode4(837953), // Rule ID 7667 //
     /*  837865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  837868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  837873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  837876 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837879 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837882 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  837885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  837889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837896 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837903 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837910 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  837910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32),
     /*  837913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  837915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  837920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  837925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  837930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  837935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  837940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  837945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  837951 */     GIR_RootConstrainSelectedInstOperands,
     /*  837952 */     // GIR_Coverage, 7667,
     /*  837952 */     GIR_EraseRootFromParent_Done,
     /*  837953 */   // Label 13518: @837953
     /*  837953 */   GIM_Try, /*On fail goto*//*Label 13519*/ GIMT_Encode4(838046), // Rule ID 7688 //
     /*  837958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  837961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  837966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  837969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  837972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  837975 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  837978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  837982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837989 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  837996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838003 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64),
     /*  838006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838044 */     GIR_RootConstrainSelectedInstOperands,
     /*  838045 */     // GIR_Coverage, 7688,
     /*  838045 */     GIR_EraseRootFromParent_Done,
     /*  838046 */   // Label 13519: @838046
     /*  838046 */   GIM_Try, /*On fail goto*//*Label 13520*/ GIMT_Encode4(838139), // Rule ID 7689 //
     /*  838051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  838054 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  838059 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838062 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838065 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838068 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838096 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64),
     /*  838099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838116 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838137 */     GIR_RootConstrainSelectedInstOperands,
     /*  838138 */     // GIR_Coverage, 7689,
     /*  838138 */     GIR_EraseRootFromParent_Done,
     /*  838139 */   // Label 13520: @838139
     /*  838139 */   GIM_Try, /*On fail goto*//*Label 13521*/ GIMT_Encode4(838232), // Rule ID 7690 //
     /*  838144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  838147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  838152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838161 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838175 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838182 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838189 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64),
     /*  838192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838230 */     GIR_RootConstrainSelectedInstOperands,
     /*  838231 */     // GIR_Coverage, 7690,
     /*  838231 */     GIR_EraseRootFromParent_Done,
     /*  838232 */   // Label 13521: @838232
     /*  838232 */   GIM_Try, /*On fail goto*//*Label 13522*/ GIMT_Encode4(838325), // Rule ID 7691 //
     /*  838237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  838240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  838245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838251 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838254 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838282 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64),
     /*  838285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838323 */     GIR_RootConstrainSelectedInstOperands,
     /*  838324 */     // GIR_Coverage, 7691,
     /*  838324 */     GIR_EraseRootFromParent_Done,
     /*  838325 */   // Label 13522: @838325
     /*  838325 */   GIM_Try, /*On fail goto*//*Label 13523*/ GIMT_Encode4(838418), // Rule ID 7692 //
     /*  838330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  838333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  838338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838375 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64),
     /*  838378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838416 */     GIR_RootConstrainSelectedInstOperands,
     /*  838417 */     // GIR_Coverage, 7692,
     /*  838417 */     GIR_EraseRootFromParent_Done,
     /*  838418 */   // Label 13523: @838418
     /*  838418 */   GIM_Try, /*On fail goto*//*Label 13524*/ GIMT_Encode4(838511), // Rule ID 7693 //
     /*  838423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  838426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  838431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838434 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838440 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838447 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838468 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64),
     /*  838471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838509 */     GIR_RootConstrainSelectedInstOperands,
     /*  838510 */     // GIR_Coverage, 7693,
     /*  838510 */     GIR_EraseRootFromParent_Done,
     /*  838511 */   // Label 13524: @838511
     /*  838511 */   GIM_Try, /*On fail goto*//*Label 13525*/ GIMT_Encode4(838604), // Rule ID 7694 //
     /*  838516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  838519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  838524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838533 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838554 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838561 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64),
     /*  838564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838602 */     GIR_RootConstrainSelectedInstOperands,
     /*  838603 */     // GIR_Coverage, 7694,
     /*  838603 */     GIR_EraseRootFromParent_Done,
     /*  838604 */   // Label 13525: @838604
     /*  838604 */   GIM_Try, /*On fail goto*//*Label 13526*/ GIMT_Encode4(838697), // Rule ID 7695 //
     /*  838609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  838612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  838617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838626 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838640 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838654 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64),
     /*  838657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838695 */     GIR_RootConstrainSelectedInstOperands,
     /*  838696 */     // GIR_Coverage, 7695,
     /*  838696 */     GIR_EraseRootFromParent_Done,
     /*  838697 */   // Label 13526: @838697
     /*  838697 */   GIM_Try, /*On fail goto*//*Label 13527*/ GIMT_Encode4(838790), // Rule ID 7696 //
     /*  838702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  838705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  838710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838719 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838733 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838747 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64),
     /*  838750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838788 */     GIR_RootConstrainSelectedInstOperands,
     /*  838789 */     // GIR_Coverage, 7696,
     /*  838789 */     GIR_EraseRootFromParent_Done,
     /*  838790 */   // Label 13527: @838790
     /*  838790 */   GIM_Try, /*On fail goto*//*Label 13528*/ GIMT_Encode4(838883), // Rule ID 7697 //
     /*  838795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  838798 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  838803 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  838806 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  838809 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  838812 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  838815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  838819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
     /*  838840 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  838840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64),
     /*  838843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838881 */     GIR_RootConstrainSelectedInstOperands,
     /*  838882 */     // GIR_Coverage, 7697,
     /*  838882 */     GIR_EraseRootFromParent_Done,
     /*  838883 */   // Label 13528: @838883
     /*  838883 */   GIM_Try, /*On fail goto*//*Label 13529*/ GIMT_Encode4(838976), // Rule ID 7728 //
     /*  838888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  838891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  838896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  838899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  838902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  838905 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  838908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  838912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  838919 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  838926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  838933 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  838933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr),
     /*  838936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  838938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  838943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  838948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  838953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  838958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  838963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  838968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  838974 */     GIR_RootConstrainSelectedInstOperands,
     /*  838975 */     // GIR_Coverage, 7728,
     /*  838975 */     GIR_EraseRootFromParent_Done,
     /*  838976 */   // Label 13529: @838976
     /*  838976 */   GIM_Try, /*On fail goto*//*Label 13530*/ GIMT_Encode4(839069), // Rule ID 7729 //
     /*  838981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  838984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  838989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  838992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  838995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  838998 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839026 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  839026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr),
     /*  839029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839041 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839067 */     GIR_RootConstrainSelectedInstOperands,
     /*  839068 */     // GIR_Coverage, 7729,
     /*  839068 */     GIR_EraseRootFromParent_Done,
     /*  839069 */   // Label 13530: @839069
     /*  839069 */   GIM_Try, /*On fail goto*//*Label 13531*/ GIMT_Encode4(839162), // Rule ID 7730 //
     /*  839074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  839077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  839085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  839088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  839091 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839119 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  839119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr),
     /*  839122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839160 */     GIR_RootConstrainSelectedInstOperands,
     /*  839161 */     // GIR_Coverage, 7730,
     /*  839161 */     GIR_EraseRootFromParent_Done,
     /*  839162 */   // Label 13531: @839162
     /*  839162 */   GIM_Try, /*On fail goto*//*Label 13532*/ GIMT_Encode4(839255), // Rule ID 7731 //
     /*  839167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  839170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  839178 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  839181 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  839184 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839191 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839198 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839205 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839212 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  839212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr),
     /*  839215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839253 */     GIR_RootConstrainSelectedInstOperands,
     /*  839254 */     // GIR_Coverage, 7731,
     /*  839254 */     GIR_EraseRootFromParent_Done,
     /*  839255 */   // Label 13532: @839255
     /*  839255 */   GIM_Try, /*On fail goto*//*Label 13533*/ GIMT_Encode4(839348), // Rule ID 7732 //
     /*  839260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  839263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839268 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  839271 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  839274 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  839277 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839298 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839305 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  839305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr),
     /*  839308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839340 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839346 */     GIR_RootConstrainSelectedInstOperands,
     /*  839347 */     // GIR_Coverage, 7732,
     /*  839347 */     GIR_EraseRootFromParent_Done,
     /*  839348 */   // Label 13533: @839348
     /*  839348 */   GIM_Try, /*On fail goto*//*Label 13534*/ GIMT_Encode4(839441), // Rule ID 7893 //
     /*  839353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  839356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  839364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  839367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  839370 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  839373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  839377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839398 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  839398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr),
     /*  839401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839418 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839423 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839433 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839436 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839439 */     GIR_RootConstrainSelectedInstOperands,
     /*  839440 */     // GIR_Coverage, 7893,
     /*  839440 */     GIR_EraseRootFromParent_Done,
     /*  839441 */   // Label 13534: @839441
     /*  839441 */   GIM_Try, /*On fail goto*//*Label 13535*/ GIMT_Encode4(839534), // Rule ID 7894 //
     /*  839446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  839449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  839457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  839460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  839463 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  839466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  839470 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839484 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839491 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  839491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr),
     /*  839494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839532 */     GIR_RootConstrainSelectedInstOperands,
     /*  839533 */     // GIR_Coverage, 7894,
     /*  839533 */     GIR_EraseRootFromParent_Done,
     /*  839534 */   // Label 13535: @839534
     /*  839534 */   GIM_Try, /*On fail goto*//*Label 13536*/ GIMT_Encode4(839627), // Rule ID 7895 //
     /*  839539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  839542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  839550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  839553 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  839556 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  839559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  839563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839584 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  839584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr),
     /*  839587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839625 */     GIR_RootConstrainSelectedInstOperands,
     /*  839626 */     // GIR_Coverage, 7895,
     /*  839626 */     GIR_EraseRootFromParent_Done,
     /*  839627 */   // Label 13536: @839627
     /*  839627 */   GIM_Try, /*On fail goto*//*Label 13537*/ GIMT_Encode4(839720), // Rule ID 7896 //
     /*  839632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  839635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  839643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  839646 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  839649 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  839652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  839656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839670 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839677 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  839677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr),
     /*  839680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839718 */     GIR_RootConstrainSelectedInstOperands,
     /*  839719 */     // GIR_Coverage, 7896,
     /*  839719 */     GIR_EraseRootFromParent_Done,
     /*  839720 */   // Label 13537: @839720
     /*  839720 */   GIM_Try, /*On fail goto*//*Label 13538*/ GIMT_Encode4(839813), // Rule ID 7897 //
     /*  839725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  839728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
     /*  839733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  839736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  839739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  839742 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  839745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  839749 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  839763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
     /*  839770 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3653:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  839770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr),
     /*  839773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  839780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  839785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  839790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  839795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  839800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  839805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839811 */     GIR_RootConstrainSelectedInstOperands,
     /*  839812 */     // GIR_Coverage, 7897,
     /*  839812 */     GIR_EraseRootFromParent_Done,
     /*  839813 */   // Label 13538: @839813
     /*  839813 */   GIM_Try, /*On fail goto*//*Label 13539*/ GIMT_Encode4(839880), // Rule ID 7743 //
     /*  839818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  839821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  839826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  839829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  839832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  839835 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839842 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  839849 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  839849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr),
     /*  839852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839857 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  839859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839862 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  839864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  839872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839878 */     GIR_RootConstrainSelectedInstOperands,
     /*  839879 */     // GIR_Coverage, 7743,
     /*  839879 */     GIR_EraseRootFromParent_Done,
     /*  839880 */   // Label 13539: @839880
     /*  839880 */   GIM_Try, /*On fail goto*//*Label 13540*/ GIMT_Encode4(839947), // Rule ID 7744 //
     /*  839885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  839888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  839893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  839896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  839899 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  839902 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  839916 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  839916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr),
     /*  839919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839924 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  839926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839929 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  839931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  839939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  839945 */     GIR_RootConstrainSelectedInstOperands,
     /*  839946 */     // GIR_Coverage, 7744,
     /*  839946 */     GIR_EraseRootFromParent_Done,
     /*  839947 */   // Label 13540: @839947
     /*  839947 */   GIM_Try, /*On fail goto*//*Label 13541*/ GIMT_Encode4(840014), // Rule ID 7745 //
     /*  839952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  839955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  839960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  839963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  839966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  839969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  839972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  839976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  839983 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  839983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr),
     /*  839986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  839988 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839991 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  839993 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  839996 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  839998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840012 */     GIR_RootConstrainSelectedInstOperands,
     /*  840013 */     // GIR_Coverage, 7745,
     /*  840013 */     GIR_EraseRootFromParent_Done,
     /*  840014 */   // Label 13541: @840014
     /*  840014 */   GIM_Try, /*On fail goto*//*Label 13542*/ GIMT_Encode4(840081), // Rule ID 7746 //
     /*  840019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  840022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  840027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  840033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  840036 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840043 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840050 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr),
     /*  840053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840058 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840063 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840068 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840079 */     GIR_RootConstrainSelectedInstOperands,
     /*  840080 */     // GIR_Coverage, 7746,
     /*  840080 */     GIR_EraseRootFromParent_Done,
     /*  840081 */   // Label 13542: @840081
     /*  840081 */   GIM_Try, /*On fail goto*//*Label 13543*/ GIMT_Encode4(840148), // Rule ID 7747 //
     /*  840086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  840089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  840094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  840100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  840103 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840117 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr),
     /*  840120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840125 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840130 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840146 */     GIR_RootConstrainSelectedInstOperands,
     /*  840147 */     // GIR_Coverage, 7747,
     /*  840147 */     GIR_EraseRootFromParent_Done,
     /*  840148 */   // Label 13543: @840148
     /*  840148 */   GIM_Try, /*On fail goto*//*Label 13544*/ GIMT_Encode4(840209), // Rule ID 7793 //
     /*  840153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  840156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  840161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840170 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840184 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr),
     /*  840187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840189 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840191 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840207 */     GIR_RootConstrainSelectedInstOperands,
     /*  840208 */     // GIR_Coverage, 7793,
     /*  840208 */     GIR_EraseRootFromParent_Done,
     /*  840209 */   // Label 13544: @840209
     /*  840209 */   GIM_Try, /*On fail goto*//*Label 13545*/ GIMT_Encode4(840270), // Rule ID 7794 //
     /*  840214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  840217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  840222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840231 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840245 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr),
     /*  840248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840250 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840252 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840268 */     GIR_RootConstrainSelectedInstOperands,
     /*  840269 */     // GIR_Coverage, 7794,
     /*  840269 */     GIR_EraseRootFromParent_Done,
     /*  840270 */   // Label 13545: @840270
     /*  840270 */   GIM_Try, /*On fail goto*//*Label 13546*/ GIMT_Encode4(840331), // Rule ID 7795 //
     /*  840275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  840278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  840283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840306 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr),
     /*  840309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840311 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840313 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840329 */     GIR_RootConstrainSelectedInstOperands,
     /*  840330 */     // GIR_Coverage, 7795,
     /*  840330 */     GIR_EraseRootFromParent_Done,
     /*  840331 */   // Label 13546: @840331
     /*  840331 */   GIM_Try, /*On fail goto*//*Label 13547*/ GIMT_Encode4(840392), // Rule ID 7796 //
     /*  840336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  840339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  840344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840353 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840367 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr),
     /*  840370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840372 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840374 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840387 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840390 */     GIR_RootConstrainSelectedInstOperands,
     /*  840391 */     // GIR_Coverage, 7796,
     /*  840391 */     GIR_EraseRootFromParent_Done,
     /*  840392 */   // Label 13547: @840392
     /*  840392 */   GIM_Try, /*On fail goto*//*Label 13548*/ GIMT_Encode4(840453), // Rule ID 7797 //
     /*  840397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  840400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  840405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840414 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840428 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr),
     /*  840431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840433 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840435 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840451 */     GIR_RootConstrainSelectedInstOperands,
     /*  840452 */     // GIR_Coverage, 7797,
     /*  840452 */     GIR_EraseRootFromParent_Done,
     /*  840453 */   // Label 13548: @840453
     /*  840453 */   GIM_Try, /*On fail goto*//*Label 13549*/ GIMT_Encode4(840514), // Rule ID 7803 //
     /*  840458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  840461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  840466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840475 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840482 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840489 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr),
     /*  840492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840494 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840496 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840512 */     GIR_RootConstrainSelectedInstOperands,
     /*  840513 */     // GIR_Coverage, 7803,
     /*  840513 */     GIR_EraseRootFromParent_Done,
     /*  840514 */   // Label 13549: @840514
     /*  840514 */   GIM_Try, /*On fail goto*//*Label 13550*/ GIMT_Encode4(840575), // Rule ID 7804 //
     /*  840519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  840522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  840527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840536 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840550 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr),
     /*  840553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840555 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840557 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840567 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840573 */     GIR_RootConstrainSelectedInstOperands,
     /*  840574 */     // GIR_Coverage, 7804,
     /*  840574 */     GIR_EraseRootFromParent_Done,
     /*  840575 */   // Label 13550: @840575
     /*  840575 */   GIM_Try, /*On fail goto*//*Label 13551*/ GIMT_Encode4(840636), // Rule ID 7805 //
     /*  840580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  840583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  840588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840594 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840597 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840604 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840611 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr),
     /*  840614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840616 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840618 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840634 */     GIR_RootConstrainSelectedInstOperands,
     /*  840635 */     // GIR_Coverage, 7805,
     /*  840635 */     GIR_EraseRootFromParent_Done,
     /*  840636 */   // Label 13551: @840636
     /*  840636 */   GIM_Try, /*On fail goto*//*Label 13552*/ GIMT_Encode4(840697), // Rule ID 7806 //
     /*  840641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  840644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  840649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840655 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840658 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840672 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr),
     /*  840675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840677 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840679 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840695 */     GIR_RootConstrainSelectedInstOperands,
     /*  840696 */     // GIR_Coverage, 7806,
     /*  840696 */     GIR_EraseRootFromParent_Done,
     /*  840697 */   // Label 13552: @840697
     /*  840697 */   GIM_Try, /*On fail goto*//*Label 13553*/ GIMT_Encode4(840758), // Rule ID 7807 //
     /*  840702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  840705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  840710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840719 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840733 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr),
     /*  840736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840738 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840740 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840742 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840756 */     GIR_RootConstrainSelectedInstOperands,
     /*  840757 */     // GIR_Coverage, 7807,
     /*  840757 */     GIR_EraseRootFromParent_Done,
     /*  840758 */   // Label 13553: @840758
     /*  840758 */   GIM_Try, /*On fail goto*//*Label 13554*/ GIMT_Encode4(840819), // Rule ID 7813 //
     /*  840763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  840766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  840771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840780 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840787 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840794 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr),
     /*  840797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840799 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840801 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840817 */     GIR_RootConstrainSelectedInstOperands,
     /*  840818 */     // GIR_Coverage, 7813,
     /*  840818 */     GIR_EraseRootFromParent_Done,
     /*  840819 */   // Label 13554: @840819
     /*  840819 */   GIM_Try, /*On fail goto*//*Label 13555*/ GIMT_Encode4(840880), // Rule ID 7814 //
     /*  840824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  840827 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  840832 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840835 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840838 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840841 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840855 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr),
     /*  840858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840860 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840862 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840878 */     GIR_RootConstrainSelectedInstOperands,
     /*  840879 */     // GIR_Coverage, 7814,
     /*  840879 */     GIR_EraseRootFromParent_Done,
     /*  840880 */   // Label 13555: @840880
     /*  840880 */   GIM_Try, /*On fail goto*//*Label 13556*/ GIMT_Encode4(840941), // Rule ID 7815 //
     /*  840885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  840888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  840893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840899 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840902 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840916 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr),
     /*  840919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840921 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840923 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840925 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840928 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840939 */     GIR_RootConstrainSelectedInstOperands,
     /*  840940 */     // GIR_Coverage, 7815,
     /*  840940 */     GIR_EraseRootFromParent_Done,
     /*  840941 */   // Label 13556: @840941
     /*  840941 */   GIM_Try, /*On fail goto*//*Label 13557*/ GIMT_Encode4(841002), // Rule ID 7816 //
     /*  840946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  840949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  840954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  840957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  840960 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  840963 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  840966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  840970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  840977 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  840977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr),
     /*  840980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  840982 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  840984 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  840986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  840989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  840994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  840997 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841000 */     GIR_RootConstrainSelectedInstOperands,
     /*  841001 */     // GIR_Coverage, 7816,
     /*  841001 */     GIR_EraseRootFromParent_Done,
     /*  841002 */   // Label 13557: @841002
     /*  841002 */   GIM_Try, /*On fail goto*//*Label 13558*/ GIMT_Encode4(841063), // Rule ID 7817 //
     /*  841007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  841010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  841015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  841018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  841021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  841024 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  841027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  841031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841038 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  841038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr),
     /*  841041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841043 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841045 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841047 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841055 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841061 */     GIR_RootConstrainSelectedInstOperands,
     /*  841062 */     // GIR_Coverage, 7817,
     /*  841062 */     GIR_EraseRootFromParent_Done,
     /*  841063 */   // Label 13558: @841063
     /*  841063 */   GIM_Try, /*On fail goto*//*Label 13559*/ GIMT_Encode4(841124), // Rule ID 7823 //
     /*  841068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  841071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  841076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  841079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  841082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  841085 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  841088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  841092 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841099 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  841099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr),
     /*  841102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841104 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841106 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841111 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841122 */     GIR_RootConstrainSelectedInstOperands,
     /*  841123 */     // GIR_Coverage, 7823,
     /*  841123 */     GIR_EraseRootFromParent_Done,
     /*  841124 */   // Label 13559: @841124
     /*  841124 */   GIM_Try, /*On fail goto*//*Label 13560*/ GIMT_Encode4(841185), // Rule ID 7824 //
     /*  841129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  841132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  841137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  841140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  841143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  841146 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  841149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  841153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841160 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  841160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr),
     /*  841163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841165 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841167 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841183 */     GIR_RootConstrainSelectedInstOperands,
     /*  841184 */     // GIR_Coverage, 7824,
     /*  841184 */     GIR_EraseRootFromParent_Done,
     /*  841185 */   // Label 13560: @841185
     /*  841185 */   GIM_Try, /*On fail goto*//*Label 13561*/ GIMT_Encode4(841246), // Rule ID 7825 //
     /*  841190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  841193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  841198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  841201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  841204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  841207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  841210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  841214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841221 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  841221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr),
     /*  841224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841226 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841228 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841244 */     GIR_RootConstrainSelectedInstOperands,
     /*  841245 */     // GIR_Coverage, 7825,
     /*  841245 */     GIR_EraseRootFromParent_Done,
     /*  841246 */   // Label 13561: @841246
     /*  841246 */   GIM_Try, /*On fail goto*//*Label 13562*/ GIMT_Encode4(841307), // Rule ID 7826 //
     /*  841251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  841254 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  841259 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  841262 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  841265 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  841268 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  841271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  841275 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841282 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  841282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr),
     /*  841285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841287 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841289 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841291 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841305 */     GIR_RootConstrainSelectedInstOperands,
     /*  841306 */     // GIR_Coverage, 7826,
     /*  841306 */     GIR_EraseRootFromParent_Done,
     /*  841307 */   // Label 13562: @841307
     /*  841307 */   GIM_Try, /*On fail goto*//*Label 13563*/ GIMT_Encode4(841368), // Rule ID 7827 //
     /*  841312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  841315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  841320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  841323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  841326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  841329 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  841332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  841336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841343 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
     /*  841343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr),
     /*  841346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841348 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841350 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841352 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841366 */     GIR_RootConstrainSelectedInstOperands,
     /*  841367 */     // GIR_Coverage, 7827,
     /*  841367 */     GIR_EraseRootFromParent_Done,
     /*  841368 */   // Label 13563: @841368
     /*  841368 */   GIM_Try, /*On fail goto*//*Label 13564*/ GIMT_Encode4(841435), // Rule ID 7908 //
     /*  841373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  841376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  841381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  841387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  841390 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841404 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr),
     /*  841407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841412 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841414 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841417 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841433 */     GIR_RootConstrainSelectedInstOperands,
     /*  841434 */     // GIR_Coverage, 7908,
     /*  841434 */     GIR_EraseRootFromParent_Done,
     /*  841435 */   // Label 13564: @841435
     /*  841435 */   GIM_Try, /*On fail goto*//*Label 13565*/ GIMT_Encode4(841502), // Rule ID 7909 //
     /*  841440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  841443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  841448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  841454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  841457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841471 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr),
     /*  841474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841476 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841479 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841484 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841500 */     GIR_RootConstrainSelectedInstOperands,
     /*  841501 */     // GIR_Coverage, 7909,
     /*  841501 */     GIR_EraseRootFromParent_Done,
     /*  841502 */   // Label 13565: @841502
     /*  841502 */   GIM_Try, /*On fail goto*//*Label 13566*/ GIMT_Encode4(841569), // Rule ID 7910 //
     /*  841507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  841510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  841515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  841521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  841524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841531 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841538 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr),
     /*  841541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841546 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841551 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841567 */     GIR_RootConstrainSelectedInstOperands,
     /*  841568 */     // GIR_Coverage, 7910,
     /*  841568 */     GIR_EraseRootFromParent_Done,
     /*  841569 */   // Label 13566: @841569
     /*  841569 */   GIM_Try, /*On fail goto*//*Label 13567*/ GIMT_Encode4(841636), // Rule ID 7911 //
     /*  841574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  841577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  841582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  841588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  841591 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841598 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841605 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr),
     /*  841608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841613 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841618 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841634 */     GIR_RootConstrainSelectedInstOperands,
     /*  841635 */     // GIR_Coverage, 7911,
     /*  841635 */     GIR_EraseRootFromParent_Done,
     /*  841636 */   // Label 13567: @841636
     /*  841636 */   GIM_Try, /*On fail goto*//*Label 13568*/ GIMT_Encode4(841703), // Rule ID 7912 //
     /*  841641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  841644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  841649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  841655 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  841658 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841672 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr),
     /*  841675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841677 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841680 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841685 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841701 */     GIR_RootConstrainSelectedInstOperands,
     /*  841702 */     // GIR_Coverage, 7912,
     /*  841702 */     GIR_EraseRootFromParent_Done,
     /*  841703 */   // Label 13568: @841703
     /*  841703 */   GIM_Try, /*On fail goto*//*Label 13569*/ GIMT_Encode4(841764), // Rule ID 7958 //
     /*  841708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  841711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  841716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  841722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  841725 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841732 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841739 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr),
     /*  841742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841744 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841746 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841762 */     GIR_RootConstrainSelectedInstOperands,
     /*  841763 */     // GIR_Coverage, 7958,
     /*  841763 */     GIR_EraseRootFromParent_Done,
     /*  841764 */   // Label 13569: @841764
     /*  841764 */   GIM_Try, /*On fail goto*//*Label 13570*/ GIMT_Encode4(841825), // Rule ID 7959 //
     /*  841769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  841772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  841777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  841783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  841786 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841800 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr),
     /*  841803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841805 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841807 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841820 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841823 */     GIR_RootConstrainSelectedInstOperands,
     /*  841824 */     // GIR_Coverage, 7959,
     /*  841824 */     GIR_EraseRootFromParent_Done,
     /*  841825 */   // Label 13570: @841825
     /*  841825 */   GIM_Try, /*On fail goto*//*Label 13571*/ GIMT_Encode4(841886), // Rule ID 7960 //
     /*  841830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  841833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  841838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  841844 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  841847 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841854 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841861 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr),
     /*  841864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841866 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841868 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841884 */     GIR_RootConstrainSelectedInstOperands,
     /*  841885 */     // GIR_Coverage, 7960,
     /*  841885 */     GIR_EraseRootFromParent_Done,
     /*  841886 */   // Label 13571: @841886
     /*  841886 */   GIM_Try, /*On fail goto*//*Label 13572*/ GIMT_Encode4(841947), // Rule ID 7961 //
     /*  841891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  841894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  841899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  841905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  841908 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841915 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841922 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr),
     /*  841925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841927 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841929 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  841939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  841945 */     GIR_RootConstrainSelectedInstOperands,
     /*  841946 */     // GIR_Coverage, 7961,
     /*  841946 */     GIR_EraseRootFromParent_Done,
     /*  841947 */   // Label 13572: @841947
     /*  841947 */   GIM_Try, /*On fail goto*//*Label 13573*/ GIMT_Encode4(842008), // Rule ID 7962 //
     /*  841952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  841955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  841960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  841963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  841966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  841969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  841972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  841976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  841983 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  841983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr),
     /*  841986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  841988 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  841990 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  841992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  841995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842006 */     GIR_RootConstrainSelectedInstOperands,
     /*  842007 */     // GIR_Coverage, 7962,
     /*  842007 */     GIR_EraseRootFromParent_Done,
     /*  842008 */   // Label 13573: @842008
     /*  842008 */   GIM_Try, /*On fail goto*//*Label 13574*/ GIMT_Encode4(842069), // Rule ID 7968 //
     /*  842013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  842016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  842021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842030 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842044 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr),
     /*  842047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842049 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842051 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842067 */     GIR_RootConstrainSelectedInstOperands,
     /*  842068 */     // GIR_Coverage, 7968,
     /*  842068 */     GIR_EraseRootFromParent_Done,
     /*  842069 */   // Label 13574: @842069
     /*  842069 */   GIM_Try, /*On fail goto*//*Label 13575*/ GIMT_Encode4(842130), // Rule ID 7969 //
     /*  842074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  842077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  842082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842091 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842105 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr),
     /*  842108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842110 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842112 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842128 */     GIR_RootConstrainSelectedInstOperands,
     /*  842129 */     // GIR_Coverage, 7969,
     /*  842129 */     GIR_EraseRootFromParent_Done,
     /*  842130 */   // Label 13575: @842130
     /*  842130 */   GIM_Try, /*On fail goto*//*Label 13576*/ GIMT_Encode4(842191), // Rule ID 7970 //
     /*  842135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  842138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  842143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842166 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr),
     /*  842169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842171 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842173 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842189 */     GIR_RootConstrainSelectedInstOperands,
     /*  842190 */     // GIR_Coverage, 7970,
     /*  842190 */     GIR_EraseRootFromParent_Done,
     /*  842191 */   // Label 13576: @842191
     /*  842191 */   GIM_Try, /*On fail goto*//*Label 13577*/ GIMT_Encode4(842252), // Rule ID 7971 //
     /*  842196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  842199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  842204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842220 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842227 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr),
     /*  842230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842232 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842234 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842250 */     GIR_RootConstrainSelectedInstOperands,
     /*  842251 */     // GIR_Coverage, 7971,
     /*  842251 */     GIR_EraseRootFromParent_Done,
     /*  842252 */   // Label 13577: @842252
     /*  842252 */   GIM_Try, /*On fail goto*//*Label 13578*/ GIMT_Encode4(842313), // Rule ID 7972 //
     /*  842257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  842260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  842265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842274 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842288 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr),
     /*  842291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842293 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842295 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842311 */     GIR_RootConstrainSelectedInstOperands,
     /*  842312 */     // GIR_Coverage, 7972,
     /*  842312 */     GIR_EraseRootFromParent_Done,
     /*  842313 */   // Label 13578: @842313
     /*  842313 */   GIM_Try, /*On fail goto*//*Label 13579*/ GIMT_Encode4(842374), // Rule ID 7978 //
     /*  842318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  842321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  842326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842335 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842349 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr),
     /*  842352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842354 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842356 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842372 */     GIR_RootConstrainSelectedInstOperands,
     /*  842373 */     // GIR_Coverage, 7978,
     /*  842373 */     GIR_EraseRootFromParent_Done,
     /*  842374 */   // Label 13579: @842374
     /*  842374 */   GIM_Try, /*On fail goto*//*Label 13580*/ GIMT_Encode4(842435), // Rule ID 7979 //
     /*  842379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  842382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  842387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842396 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842410 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr),
     /*  842413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842415 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842417 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842433 */     GIR_RootConstrainSelectedInstOperands,
     /*  842434 */     // GIR_Coverage, 7979,
     /*  842434 */     GIR_EraseRootFromParent_Done,
     /*  842435 */   // Label 13580: @842435
     /*  842435 */   GIM_Try, /*On fail goto*//*Label 13581*/ GIMT_Encode4(842496), // Rule ID 7980 //
     /*  842440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  842443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  842448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842471 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr),
     /*  842474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842476 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842478 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842494 */     GIR_RootConstrainSelectedInstOperands,
     /*  842495 */     // GIR_Coverage, 7980,
     /*  842495 */     GIR_EraseRootFromParent_Done,
     /*  842496 */   // Label 13581: @842496
     /*  842496 */   GIM_Try, /*On fail goto*//*Label 13582*/ GIMT_Encode4(842557), // Rule ID 7981 //
     /*  842501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  842504 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  842509 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842512 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842515 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842518 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842525 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842532 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr),
     /*  842535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842537 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842539 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842555 */     GIR_RootConstrainSelectedInstOperands,
     /*  842556 */     // GIR_Coverage, 7981,
     /*  842556 */     GIR_EraseRootFromParent_Done,
     /*  842557 */   // Label 13582: @842557
     /*  842557 */   GIM_Try, /*On fail goto*//*Label 13583*/ GIMT_Encode4(842618), // Rule ID 7982 //
     /*  842562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  842565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  842570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842593 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr),
     /*  842596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842598 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842600 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842616 */     GIR_RootConstrainSelectedInstOperands,
     /*  842617 */     // GIR_Coverage, 7982,
     /*  842617 */     GIR_EraseRootFromParent_Done,
     /*  842618 */   // Label 13583: @842618
     /*  842618 */   GIM_Try, /*On fail goto*//*Label 13584*/ GIMT_Encode4(842679), // Rule ID 7988 //
     /*  842623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  842626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  842631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842640 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842654 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr),
     /*  842657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842659 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842661 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842677 */     GIR_RootConstrainSelectedInstOperands,
     /*  842678 */     // GIR_Coverage, 7988,
     /*  842678 */     GIR_EraseRootFromParent_Done,
     /*  842679 */   // Label 13584: @842679
     /*  842679 */   GIM_Try, /*On fail goto*//*Label 13585*/ GIMT_Encode4(842740), // Rule ID 7989 //
     /*  842684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  842687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  842692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842701 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842715 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr),
     /*  842718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842720 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842722 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842738 */     GIR_RootConstrainSelectedInstOperands,
     /*  842739 */     // GIR_Coverage, 7989,
     /*  842739 */     GIR_EraseRootFromParent_Done,
     /*  842740 */   // Label 13585: @842740
     /*  842740 */   GIM_Try, /*On fail goto*//*Label 13586*/ GIMT_Encode4(842801), // Rule ID 7990 //
     /*  842745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  842748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  842753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842762 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842776 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr),
     /*  842779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842781 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842783 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842799 */     GIR_RootConstrainSelectedInstOperands,
     /*  842800 */     // GIR_Coverage, 7990,
     /*  842800 */     GIR_EraseRootFromParent_Done,
     /*  842801 */   // Label 13586: @842801
     /*  842801 */   GIM_Try, /*On fail goto*//*Label 13587*/ GIMT_Encode4(842862), // Rule ID 7991 //
     /*  842806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  842809 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  842814 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842817 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842820 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842823 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842837 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr),
     /*  842840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842842 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842844 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842849 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842857 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842860 */     GIR_RootConstrainSelectedInstOperands,
     /*  842861 */     // GIR_Coverage, 7991,
     /*  842861 */     GIR_EraseRootFromParent_Done,
     /*  842862 */   // Label 13587: @842862
     /*  842862 */   GIM_Try, /*On fail goto*//*Label 13588*/ GIMT_Encode4(842923), // Rule ID 7992 //
     /*  842867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  842870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  842875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  842878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  842881 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  842884 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  842887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  842891 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  842898 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
     /*  842898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr),
     /*  842901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842903 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842905 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842907 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842921 */     GIR_RootConstrainSelectedInstOperands,
     /*  842922 */     // GIR_Coverage, 7992,
     /*  842922 */     GIR_EraseRootFromParent_Done,
     /*  842923 */   // Label 13588: @842923
     /*  842923 */   GIM_Try, /*On fail goto*//*Label 13589*/ GIMT_Encode4(842992), // Rule ID 7738 //
     /*  842928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  842931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  842936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  842939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  842942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  842945 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  842948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  842952 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  842959 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  842959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr),
     /*  842962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  842964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842967 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  842969 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  842972 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  842974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  842979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  842984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  842990 */     GIR_RootConstrainSelectedInstOperands,
     /*  842991 */     // GIR_Coverage, 7738,
     /*  842991 */     GIR_EraseRootFromParent_Done,
     /*  842992 */   // Label 13589: @842992
     /*  842992 */   GIM_Try, /*On fail goto*//*Label 13590*/ GIMT_Encode4(843061), // Rule ID 7739 //
     /*  842997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  843000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  843005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  843011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  843014 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843028 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr),
     /*  843031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843036 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843041 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843059 */     GIR_RootConstrainSelectedInstOperands,
     /*  843060 */     // GIR_Coverage, 7739,
     /*  843060 */     GIR_EraseRootFromParent_Done,
     /*  843061 */   // Label 13590: @843061
     /*  843061 */   GIM_Try, /*On fail goto*//*Label 13591*/ GIMT_Encode4(843130), // Rule ID 7740 //
     /*  843066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  843069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  843074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  843080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  843083 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843097 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr),
     /*  843100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843105 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843110 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843117 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843128 */     GIR_RootConstrainSelectedInstOperands,
     /*  843129 */     // GIR_Coverage, 7740,
     /*  843129 */     GIR_EraseRootFromParent_Done,
     /*  843130 */   // Label 13591: @843130
     /*  843130 */   GIM_Try, /*On fail goto*//*Label 13592*/ GIMT_Encode4(843199), // Rule ID 7741 //
     /*  843135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  843138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  843143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  843149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  843152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843166 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr),
     /*  843169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843174 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843179 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843197 */     GIR_RootConstrainSelectedInstOperands,
     /*  843198 */     // GIR_Coverage, 7741,
     /*  843198 */     GIR_EraseRootFromParent_Done,
     /*  843199 */   // Label 13592: @843199
     /*  843199 */   GIM_Try, /*On fail goto*//*Label 13593*/ GIMT_Encode4(843268), // Rule ID 7742 //
     /*  843204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  843207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  843212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  843218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  843221 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843235 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3650:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr),
     /*  843238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843243 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  843248 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843266 */     GIR_RootConstrainSelectedInstOperands,
     /*  843267 */     // GIR_Coverage, 7742,
     /*  843267 */     GIR_EraseRootFromParent_Done,
     /*  843268 */   // Label 13593: @843268
     /*  843268 */   GIM_Try, /*On fail goto*//*Label 13594*/ GIMT_Encode4(843331), // Rule ID 7788 //
     /*  843273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  843276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  843281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843290 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843304 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr),
     /*  843307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843309 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843311 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843329 */     GIR_RootConstrainSelectedInstOperands,
     /*  843330 */     // GIR_Coverage, 7788,
     /*  843330 */     GIR_EraseRootFromParent_Done,
     /*  843331 */   // Label 13594: @843331
     /*  843331 */   GIM_Try, /*On fail goto*//*Label 13595*/ GIMT_Encode4(843394), // Rule ID 7789 //
     /*  843336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  843339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  843344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843353 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843367 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr),
     /*  843370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843372 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843374 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843392 */     GIR_RootConstrainSelectedInstOperands,
     /*  843393 */     // GIR_Coverage, 7789,
     /*  843393 */     GIR_EraseRootFromParent_Done,
     /*  843394 */   // Label 13595: @843394
     /*  843394 */   GIM_Try, /*On fail goto*//*Label 13596*/ GIMT_Encode4(843457), // Rule ID 7790 //
     /*  843399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  843402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  843407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843416 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843430 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr),
     /*  843433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843437 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843455 */     GIR_RootConstrainSelectedInstOperands,
     /*  843456 */     // GIR_Coverage, 7790,
     /*  843456 */     GIR_EraseRootFromParent_Done,
     /*  843457 */   // Label 13596: @843457
     /*  843457 */   GIM_Try, /*On fail goto*//*Label 13597*/ GIMT_Encode4(843520), // Rule ID 7791 //
     /*  843462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  843465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  843470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843479 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843493 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr),
     /*  843496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843498 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843500 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843512 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843518 */     GIR_RootConstrainSelectedInstOperands,
     /*  843519 */     // GIR_Coverage, 7791,
     /*  843519 */     GIR_EraseRootFromParent_Done,
     /*  843520 */   // Label 13597: @843520
     /*  843520 */   GIM_Try, /*On fail goto*//*Label 13598*/ GIMT_Encode4(843583), // Rule ID 7792 //
     /*  843525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  843528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  843533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843542 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843549 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843556 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3655:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr),
     /*  843559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843561 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843563 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843570 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843581 */     GIR_RootConstrainSelectedInstOperands,
     /*  843582 */     // GIR_Coverage, 7792,
     /*  843582 */     GIR_EraseRootFromParent_Done,
     /*  843583 */   // Label 13598: @843583
     /*  843583 */   GIM_Try, /*On fail goto*//*Label 13599*/ GIMT_Encode4(843646), // Rule ID 7798 //
     /*  843588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  843591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  843596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843605 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843612 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843619 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr),
     /*  843622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843624 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843626 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843644 */     GIR_RootConstrainSelectedInstOperands,
     /*  843645 */     // GIR_Coverage, 7798,
     /*  843645 */     GIR_EraseRootFromParent_Done,
     /*  843646 */   // Label 13599: @843646
     /*  843646 */   GIM_Try, /*On fail goto*//*Label 13600*/ GIMT_Encode4(843709), // Rule ID 7799 //
     /*  843651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  843654 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  843659 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843668 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843682 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr),
     /*  843685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843687 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843689 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843707 */     GIR_RootConstrainSelectedInstOperands,
     /*  843708 */     // GIR_Coverage, 7799,
     /*  843708 */     GIR_EraseRootFromParent_Done,
     /*  843709 */   // Label 13600: @843709
     /*  843709 */   GIM_Try, /*On fail goto*//*Label 13601*/ GIMT_Encode4(843772), // Rule ID 7800 //
     /*  843714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  843717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  843722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843728 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843731 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843745 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr),
     /*  843748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843750 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843752 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843770 */     GIR_RootConstrainSelectedInstOperands,
     /*  843771 */     // GIR_Coverage, 7800,
     /*  843771 */     GIR_EraseRootFromParent_Done,
     /*  843772 */   // Label 13601: @843772
     /*  843772 */   GIM_Try, /*On fail goto*//*Label 13602*/ GIMT_Encode4(843835), // Rule ID 7801 //
     /*  843777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  843780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  843785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843791 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843794 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843808 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr),
     /*  843811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843813 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843815 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843833 */     GIR_RootConstrainSelectedInstOperands,
     /*  843834 */     // GIR_Coverage, 7801,
     /*  843834 */     GIR_EraseRootFromParent_Done,
     /*  843835 */   // Label 13602: @843835
     /*  843835 */   GIM_Try, /*On fail goto*//*Label 13603*/ GIMT_Encode4(843898), // Rule ID 7802 //
     /*  843840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  843843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  843848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843857 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843871 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3654:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr),
     /*  843874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843876 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843878 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843896 */     GIR_RootConstrainSelectedInstOperands,
     /*  843897 */     // GIR_Coverage, 7802,
     /*  843897 */     GIR_EraseRootFromParent_Done,
     /*  843898 */   // Label 13603: @843898
     /*  843898 */   GIM_Try, /*On fail goto*//*Label 13604*/ GIMT_Encode4(843961), // Rule ID 7808 //
     /*  843903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  843906 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  843911 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843914 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843917 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843920 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843927 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843934 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr),
     /*  843937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  843939 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  843941 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  843943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  843948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  843953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  843959 */     GIR_RootConstrainSelectedInstOperands,
     /*  843960 */     // GIR_Coverage, 7808,
     /*  843960 */     GIR_EraseRootFromParent_Done,
     /*  843961 */   // Label 13604: @843961
     /*  843961 */   GIM_Try, /*On fail goto*//*Label 13605*/ GIMT_Encode4(844024), // Rule ID 7809 //
     /*  843966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  843969 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  843974 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  843977 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  843980 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  843983 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  843986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  843990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  843997 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  843997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr),
     /*  844000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844002 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844004 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844006 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844022 */     GIR_RootConstrainSelectedInstOperands,
     /*  844023 */     // GIR_Coverage, 7809,
     /*  844023 */     GIR_EraseRootFromParent_Done,
     /*  844024 */   // Label 13605: @844024
     /*  844024 */   GIM_Try, /*On fail goto*//*Label 13606*/ GIMT_Encode4(844087), // Rule ID 7810 //
     /*  844029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  844032 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  844037 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844040 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844043 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844046 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844060 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr),
     /*  844063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844065 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844067 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844085 */     GIR_RootConstrainSelectedInstOperands,
     /*  844086 */     // GIR_Coverage, 7810,
     /*  844086 */     GIR_EraseRootFromParent_Done,
     /*  844087 */   // Label 13606: @844087
     /*  844087 */   GIM_Try, /*On fail goto*//*Label 13607*/ GIMT_Encode4(844150), // Rule ID 7811 //
     /*  844092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  844095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  844100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844109 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844116 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844123 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr),
     /*  844126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844128 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844130 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844145 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844148 */     GIR_RootConstrainSelectedInstOperands,
     /*  844149 */     // GIR_Coverage, 7811,
     /*  844149 */     GIR_EraseRootFromParent_Done,
     /*  844150 */   // Label 13607: @844150
     /*  844150 */   GIM_Try, /*On fail goto*//*Label 13608*/ GIMT_Encode4(844213), // Rule ID 7812 //
     /*  844155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  844158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  844163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844169 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844172 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844186 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3652:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr),
     /*  844189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844191 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844193 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844211 */     GIR_RootConstrainSelectedInstOperands,
     /*  844212 */     // GIR_Coverage, 7812,
     /*  844212 */     GIR_EraseRootFromParent_Done,
     /*  844213 */   // Label 13608: @844213
     /*  844213 */   GIM_Try, /*On fail goto*//*Label 13609*/ GIMT_Encode4(844276), // Rule ID 7818 //
     /*  844218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  844221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  844226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844235 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844242 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844249 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr),
     /*  844252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844254 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844256 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844274 */     GIR_RootConstrainSelectedInstOperands,
     /*  844275 */     // GIR_Coverage, 7818,
     /*  844275 */     GIR_EraseRootFromParent_Done,
     /*  844276 */   // Label 13609: @844276
     /*  844276 */   GIM_Try, /*On fail goto*//*Label 13610*/ GIMT_Encode4(844339), // Rule ID 7819 //
     /*  844281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  844284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  844289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844298 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844312 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr),
     /*  844315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844317 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844319 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844326 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844337 */     GIR_RootConstrainSelectedInstOperands,
     /*  844338 */     // GIR_Coverage, 7819,
     /*  844338 */     GIR_EraseRootFromParent_Done,
     /*  844339 */   // Label 13610: @844339
     /*  844339 */   GIM_Try, /*On fail goto*//*Label 13611*/ GIMT_Encode4(844402), // Rule ID 7820 //
     /*  844344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  844347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  844352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844361 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844368 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844375 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr),
     /*  844378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844380 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844382 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844397 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844400 */     GIR_RootConstrainSelectedInstOperands,
     /*  844401 */     // GIR_Coverage, 7820,
     /*  844401 */     GIR_EraseRootFromParent_Done,
     /*  844402 */   // Label 13611: @844402
     /*  844402 */   GIM_Try, /*On fail goto*//*Label 13612*/ GIMT_Encode4(844465), // Rule ID 7821 //
     /*  844407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  844410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  844415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844418 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844421 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844424 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844431 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844438 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr),
     /*  844441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844443 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844445 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844463 */     GIR_RootConstrainSelectedInstOperands,
     /*  844464 */     // GIR_Coverage, 7821,
     /*  844464 */     GIR_EraseRootFromParent_Done,
     /*  844465 */   // Label 13612: @844465
     /*  844465 */   GIM_Try, /*On fail goto*//*Label 13613*/ GIMT_Encode4(844528), // Rule ID 7822 //
     /*  844470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  844473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  844478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  844481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  844484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  844487 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  844490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  844494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844501 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3651:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
     /*  844501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr),
     /*  844504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844506 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844508 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844523 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844526 */     GIR_RootConstrainSelectedInstOperands,
     /*  844527 */     // GIR_Coverage, 7822,
     /*  844527 */     GIR_EraseRootFromParent_Done,
     /*  844528 */   // Label 13613: @844528
     /*  844528 */   GIM_Try, /*On fail goto*//*Label 13614*/ GIMT_Encode4(844597), // Rule ID 7903 //
     /*  844533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  844536 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  844541 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  844547 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  844550 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844564 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr),
     /*  844567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844572 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844577 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844595 */     GIR_RootConstrainSelectedInstOperands,
     /*  844596 */     // GIR_Coverage, 7903,
     /*  844596 */     GIR_EraseRootFromParent_Done,
     /*  844597 */   // Label 13614: @844597
     /*  844597 */   GIM_Try, /*On fail goto*//*Label 13615*/ GIMT_Encode4(844666), // Rule ID 7904 //
     /*  844602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  844605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  844610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  844616 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  844619 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844626 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844633 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr),
     /*  844636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844641 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844646 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844664 */     GIR_RootConstrainSelectedInstOperands,
     /*  844665 */     // GIR_Coverage, 7904,
     /*  844665 */     GIR_EraseRootFromParent_Done,
     /*  844666 */   // Label 13615: @844666
     /*  844666 */   GIM_Try, /*On fail goto*//*Label 13616*/ GIMT_Encode4(844735), // Rule ID 7905 //
     /*  844671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  844674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  844679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  844685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  844688 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844702 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr),
     /*  844705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844710 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844715 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844733 */     GIR_RootConstrainSelectedInstOperands,
     /*  844734 */     // GIR_Coverage, 7905,
     /*  844734 */     GIR_EraseRootFromParent_Done,
     /*  844735 */   // Label 13616: @844735
     /*  844735 */   GIM_Try, /*On fail goto*//*Label 13617*/ GIMT_Encode4(844804), // Rule ID 7906 //
     /*  844740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  844743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  844748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  844754 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  844757 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844771 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr),
     /*  844774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844779 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844784 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844802 */     GIR_RootConstrainSelectedInstOperands,
     /*  844803 */     // GIR_Coverage, 7906,
     /*  844803 */     GIR_EraseRootFromParent_Done,
     /*  844804 */   // Label 13617: @844804
     /*  844804 */   GIM_Try, /*On fail goto*//*Label 13618*/ GIMT_Encode4(844873), // Rule ID 7907 //
     /*  844809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  844812 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
     /*  844817 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844820 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  844823 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  844826 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844840 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3650:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr),
     /*  844843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844848 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  844853 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844871 */     GIR_RootConstrainSelectedInstOperands,
     /*  844872 */     // GIR_Coverage, 7907,
     /*  844872 */     GIR_EraseRootFromParent_Done,
     /*  844873 */   // Label 13618: @844873
     /*  844873 */   GIM_Try, /*On fail goto*//*Label 13619*/ GIMT_Encode4(844936), // Rule ID 7953 //
     /*  844878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  844881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  844886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  844892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  844895 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844909 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr),
     /*  844912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844914 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844916 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844918 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844934 */     GIR_RootConstrainSelectedInstOperands,
     /*  844935 */     // GIR_Coverage, 7953,
     /*  844935 */     GIR_EraseRootFromParent_Done,
     /*  844936 */   // Label 13619: @844936
     /*  844936 */   GIM_Try, /*On fail goto*//*Label 13620*/ GIMT_Encode4(844999), // Rule ID 7954 //
     /*  844941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  844944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  844949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  844952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  844955 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  844958 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  844961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  844965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  844972 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  844972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr),
     /*  844975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  844977 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  844979 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  844981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  844986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  844991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  844997 */     GIR_RootConstrainSelectedInstOperands,
     /*  844998 */     // GIR_Coverage, 7954,
     /*  844998 */     GIR_EraseRootFromParent_Done,
     /*  844999 */   // Label 13620: @844999
     /*  844999 */   GIM_Try, /*On fail goto*//*Label 13621*/ GIMT_Encode4(845062), // Rule ID 7955 //
     /*  845004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  845007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  845012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845021 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845028 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845035 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr),
     /*  845038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845040 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845042 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845060 */     GIR_RootConstrainSelectedInstOperands,
     /*  845061 */     // GIR_Coverage, 7955,
     /*  845061 */     GIR_EraseRootFromParent_Done,
     /*  845062 */   // Label 13621: @845062
     /*  845062 */   GIM_Try, /*On fail goto*//*Label 13622*/ GIMT_Encode4(845125), // Rule ID 7956 //
     /*  845067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  845070 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  845075 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845078 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845081 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845084 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845091 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845098 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr),
     /*  845101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845103 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845105 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845112 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845123 */     GIR_RootConstrainSelectedInstOperands,
     /*  845124 */     // GIR_Coverage, 7956,
     /*  845124 */     GIR_EraseRootFromParent_Done,
     /*  845125 */   // Label 13622: @845125
     /*  845125 */   GIM_Try, /*On fail goto*//*Label 13623*/ GIMT_Encode4(845188), // Rule ID 7957 //
     /*  845130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  845133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
     /*  845138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845147 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845161 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3655:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr),
     /*  845164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845166 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845168 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845186 */     GIR_RootConstrainSelectedInstOperands,
     /*  845187 */     // GIR_Coverage, 7957,
     /*  845187 */     GIR_EraseRootFromParent_Done,
     /*  845188 */   // Label 13623: @845188
     /*  845188 */   GIM_Try, /*On fail goto*//*Label 13624*/ GIMT_Encode4(845251), // Rule ID 7963 //
     /*  845193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  845196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  845201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845207 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845210 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845224 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr),
     /*  845227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845229 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845231 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845233 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845249 */     GIR_RootConstrainSelectedInstOperands,
     /*  845250 */     // GIR_Coverage, 7963,
     /*  845250 */     GIR_EraseRootFromParent_Done,
     /*  845251 */   // Label 13624: @845251
     /*  845251 */   GIM_Try, /*On fail goto*//*Label 13625*/ GIMT_Encode4(845314), // Rule ID 7964 //
     /*  845256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  845259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  845264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845273 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845280 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845287 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr),
     /*  845290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845292 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845294 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845312 */     GIR_RootConstrainSelectedInstOperands,
     /*  845313 */     // GIR_Coverage, 7964,
     /*  845313 */     GIR_EraseRootFromParent_Done,
     /*  845314 */   // Label 13625: @845314
     /*  845314 */   GIM_Try, /*On fail goto*//*Label 13626*/ GIMT_Encode4(845377), // Rule ID 7965 //
     /*  845319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  845322 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  845327 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845330 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845333 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845336 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845343 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845350 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr),
     /*  845353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845355 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845357 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845375 */     GIR_RootConstrainSelectedInstOperands,
     /*  845376 */     // GIR_Coverage, 7965,
     /*  845376 */     GIR_EraseRootFromParent_Done,
     /*  845377 */   // Label 13626: @845377
     /*  845377 */   GIM_Try, /*On fail goto*//*Label 13627*/ GIMT_Encode4(845440), // Rule ID 7966 //
     /*  845382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  845385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  845390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845399 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845413 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr),
     /*  845416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845418 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845420 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845422 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845435 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845438 */     GIR_RootConstrainSelectedInstOperands,
     /*  845439 */     // GIR_Coverage, 7966,
     /*  845439 */     GIR_EraseRootFromParent_Done,
     /*  845440 */   // Label 13627: @845440
     /*  845440 */   GIM_Try, /*On fail goto*//*Label 13628*/ GIMT_Encode4(845503), // Rule ID 7967 //
     /*  845445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  845448 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
     /*  845453 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845456 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845459 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845462 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845476 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3654:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr),
     /*  845479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845481 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845483 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845501 */     GIR_RootConstrainSelectedInstOperands,
     /*  845502 */     // GIR_Coverage, 7967,
     /*  845502 */     GIR_EraseRootFromParent_Done,
     /*  845503 */   // Label 13628: @845503
     /*  845503 */   GIM_Try, /*On fail goto*//*Label 13629*/ GIMT_Encode4(845566), // Rule ID 7973 //
     /*  845508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  845511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  845516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845525 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845539 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr),
     /*  845542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845544 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845546 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845564 */     GIR_RootConstrainSelectedInstOperands,
     /*  845565 */     // GIR_Coverage, 7973,
     /*  845565 */     GIR_EraseRootFromParent_Done,
     /*  845566 */   // Label 13629: @845566
     /*  845566 */   GIM_Try, /*On fail goto*//*Label 13630*/ GIMT_Encode4(845629), // Rule ID 7974 //
     /*  845571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  845574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  845579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845588 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845602 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr),
     /*  845605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845607 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845609 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845627 */     GIR_RootConstrainSelectedInstOperands,
     /*  845628 */     // GIR_Coverage, 7974,
     /*  845628 */     GIR_EraseRootFromParent_Done,
     /*  845629 */   // Label 13630: @845629
     /*  845629 */   GIM_Try, /*On fail goto*//*Label 13631*/ GIMT_Encode4(845692), // Rule ID 7975 //
     /*  845634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  845637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  845642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845651 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845665 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr),
     /*  845668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845670 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845672 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845684 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845690 */     GIR_RootConstrainSelectedInstOperands,
     /*  845691 */     // GIR_Coverage, 7975,
     /*  845691 */     GIR_EraseRootFromParent_Done,
     /*  845692 */   // Label 13631: @845692
     /*  845692 */   GIM_Try, /*On fail goto*//*Label 13632*/ GIMT_Encode4(845755), // Rule ID 7976 //
     /*  845697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  845700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  845705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845728 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr),
     /*  845731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845733 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845735 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845742 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845753 */     GIR_RootConstrainSelectedInstOperands,
     /*  845754 */     // GIR_Coverage, 7976,
     /*  845754 */     GIR_EraseRootFromParent_Done,
     /*  845755 */   // Label 13632: @845755
     /*  845755 */   GIM_Try, /*On fail goto*//*Label 13633*/ GIMT_Encode4(845818), // Rule ID 7977 //
     /*  845760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  845763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
     /*  845768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845784 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845791 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3652:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr),
     /*  845794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845796 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845798 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845816 */     GIR_RootConstrainSelectedInstOperands,
     /*  845817 */     // GIR_Coverage, 7977,
     /*  845817 */     GIR_EraseRootFromParent_Done,
     /*  845818 */   // Label 13633: @845818
     /*  845818 */   GIM_Try, /*On fail goto*//*Label 13634*/ GIMT_Encode4(845881), // Rule ID 7983 //
     /*  845823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  845826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  845831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845840 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845854 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr),
     /*  845857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845859 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845861 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845879 */     GIR_RootConstrainSelectedInstOperands,
     /*  845880 */     // GIR_Coverage, 7983,
     /*  845880 */     GIR_EraseRootFromParent_Done,
     /*  845881 */   // Label 13634: @845881
     /*  845881 */   GIM_Try, /*On fail goto*//*Label 13635*/ GIMT_Encode4(845944), // Rule ID 7984 //
     /*  845886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  845889 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  845894 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845897 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845900 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845903 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845910 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845917 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr),
     /*  845920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845922 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845924 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  845942 */     GIR_RootConstrainSelectedInstOperands,
     /*  845943 */     // GIR_Coverage, 7984,
     /*  845943 */     GIR_EraseRootFromParent_Done,
     /*  845944 */   // Label 13635: @845944
     /*  845944 */   GIM_Try, /*On fail goto*//*Label 13636*/ GIMT_Encode4(846007), // Rule ID 7985 //
     /*  845949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  845952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  845957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  845960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  845963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  845966 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  845969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  845973 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  845980 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  845980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr),
     /*  845983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  845985 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  845987 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  845989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  845994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  845999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  846002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  846005 */     GIR_RootConstrainSelectedInstOperands,
     /*  846006 */     // GIR_Coverage, 7985,
     /*  846006 */     GIR_EraseRootFromParent_Done,
     /*  846007 */   // Label 13636: @846007
     /*  846007 */   GIM_Try, /*On fail goto*//*Label 13637*/ GIMT_Encode4(846070), // Rule ID 7986 //
     /*  846012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  846015 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  846020 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  846023 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846026 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846029 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  846032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  846043 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  846043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr),
     /*  846046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846048 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846050 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  846057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  846062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  846065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  846068 */     GIR_RootConstrainSelectedInstOperands,
     /*  846069 */     // GIR_Coverage, 7986,
     /*  846069 */     GIR_EraseRootFromParent_Done,
     /*  846070 */   // Label 13637: @846070
     /*  846070 */   GIM_Try, /*On fail goto*//*Label 13638*/ GIMT_Encode4(846133), // Rule ID 7987 //
     /*  846075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  846078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
     /*  846083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  846086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846092 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  846095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846099 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
     /*  846106 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3651:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
     /*  846106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr),
     /*  846109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846111 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846113 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
     /*  846120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  846125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  846128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  846131 */     GIR_RootConstrainSelectedInstOperands,
     /*  846132 */     // GIR_Coverage, 7987,
     /*  846132 */     GIR_EraseRootFromParent_Done,
     /*  846133 */   // Label 13638: @846133
     /*  846133 */   GIM_Try, /*On fail goto*//*Label 13639*/ GIMT_Encode4(846172), // Rule ID 7100 //
     /*  846138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  846146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  846155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846159 */     // (intrinsic_wo_chain:{ *:[i32] } 3681:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2)
     /*  846159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846164 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846166 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846168 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846170 */     GIR_RootConstrainSelectedInstOperands,
     /*  846171 */     // GIR_Coverage, 7100,
     /*  846171 */     GIR_EraseRootFromParent_Done,
     /*  846172 */   // Label 13639: @846172
     /*  846172 */   GIM_Try, /*On fail goto*//*Label 13640*/ GIMT_Encode4(846211), // Rule ID 7102 //
     /*  846177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  846185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846191 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  846194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846198 */     // (intrinsic_wo_chain:{ *:[f32] } 3681:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2)  =>  (V_WRITELANE_B32:{ *:[f32] } SCSrc_b32:{ *:[f32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[f32] }:$src2)
     /*  846198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846203 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846205 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846207 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846209 */     GIR_RootConstrainSelectedInstOperands,
     /*  846210 */     // GIR_Coverage, 7102,
     /*  846210 */     GIR_EraseRootFromParent_Done,
     /*  846211 */   // Label 13640: @846211
     /*  846211 */   GIM_Try, /*On fail goto*//*Label 13641*/ GIMT_Encode4(846250), // Rule ID 7104 //
     /*  846216 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846221 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  846224 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  846227 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846230 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  846233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846237 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3681:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1, v2i16:{ *:[v2i16] }:$src2)  =>  (V_WRITELANE_B32:{ *:[v2i16] } SCSrc_b32:{ *:[v2i16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[v2i16] }:$src2)
     /*  846237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846242 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846244 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846246 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846248 */     GIR_RootConstrainSelectedInstOperands,
     /*  846249 */     // GIR_Coverage, 7104,
     /*  846249 */     GIR_EraseRootFromParent_Done,
     /*  846250 */   // Label 13641: @846250
     /*  846250 */   GIM_Try, /*On fail goto*//*Label 13642*/ GIMT_Encode4(846289), // Rule ID 7106 //
     /*  846255 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846260 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  846263 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  846266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846269 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16,
     /*  846272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846276 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3681:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, v2f16:{ *:[v2f16] }:$src2)  =>  (V_WRITELANE_B32:{ *:[v2f16] } SCSrc_b32:{ *:[v2f16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[v2f16] }:$src2)
     /*  846276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846281 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846283 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846285 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846287 */     GIR_RootConstrainSelectedInstOperands,
     /*  846288 */     // GIR_Coverage, 7106,
     /*  846288 */     GIR_EraseRootFromParent_Done,
     /*  846289 */   // Label 13642: @846289
     /*  846289 */   GIM_Try, /*On fail goto*//*Label 13643*/ GIMT_Encode4(846328), // Rule ID 7108 //
     /*  846294 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846299 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  846302 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  846305 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846308 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p2s32,
     /*  846311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846315 */     // (intrinsic_wo_chain:{ *:[i32] } 3681:{ *:[iPTR] }, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p2:{ *:[i32] }:$src2)  =>  (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2)
     /*  846315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846320 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846322 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846324 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846326 */     GIR_RootConstrainSelectedInstOperands,
     /*  846327 */     // GIR_Coverage, 7108,
     /*  846327 */     GIR_EraseRootFromParent_Done,
     /*  846328 */   // Label 13643: @846328
     /*  846328 */   GIM_Try, /*On fail goto*//*Label 13644*/ GIMT_Encode4(846367), // Rule ID 7110 //
     /*  846333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  846341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  846344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p3s32,
     /*  846350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846354 */     // (intrinsic_wo_chain:{ *:[i32] } 3681:{ *:[iPTR] }, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p3:{ *:[i32] }:$src2)  =>  (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2)
     /*  846354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846359 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846361 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846363 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846365 */     GIR_RootConstrainSelectedInstOperands,
     /*  846366 */     // GIR_Coverage, 7110,
     /*  846366 */     GIR_EraseRootFromParent_Done,
     /*  846367 */   // Label 13644: @846367
     /*  846367 */   GIM_Try, /*On fail goto*//*Label 13645*/ GIMT_Encode4(846406), // Rule ID 7112 //
     /*  846372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  846380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  846383 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846386 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p5s32,
     /*  846389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846393 */     // (intrinsic_wo_chain:{ *:[i32] } 3681:{ *:[iPTR] }, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p5:{ *:[i32] }:$src2)  =>  (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2)
     /*  846393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846398 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846400 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846402 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846404 */     GIR_RootConstrainSelectedInstOperands,
     /*  846405 */     // GIR_Coverage, 7112,
     /*  846405 */     GIR_EraseRootFromParent_Done,
     /*  846406 */   // Label 13645: @846406
     /*  846406 */   GIM_Try, /*On fail goto*//*Label 13646*/ GIMT_Encode4(846445), // Rule ID 7114 //
     /*  846411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
     /*  846416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  846419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  846422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846425 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p6s32,
     /*  846428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846432 */     // (intrinsic_wo_chain:{ *:[i32] } 3681:{ *:[iPTR] }, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p6:{ *:[i32] }:$src2)  =>  (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2)
     /*  846432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
     /*  846435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846437 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846439 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846441 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846443 */     GIR_RootConstrainSelectedInstOperands,
     /*  846444 */     // GIR_Coverage, 7114,
     /*  846444 */     GIR_EraseRootFromParent_Done,
     /*  846445 */   // Label 13646: @846445
     /*  846445 */   GIM_Try, /*On fail goto*//*Label 13647*/ GIMT_Encode4(846487), // Rule ID 7473 //
     /*  846450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32),
     /*  846453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane_bcast),
     /*  846458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  846461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  846470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846474 */     // (intrinsic_wo_chain:{ *:[i32] } 3341:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_PERMLANE_BCAST_B32_e64:{ *:[i32] } VGPR_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, SCSrc_b32:{ *:[i32] }:$src2)
     /*  846474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE_BCAST_B32_e64),
     /*  846477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846479 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846481 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846483 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846485 */     GIR_RootConstrainSelectedInstOperands,
     /*  846486 */     // GIR_Coverage, 7473,
     /*  846486 */     GIR_EraseRootFromParent_Done,
     /*  846487 */   // Label 13647: @846487
     /*  846487 */   GIM_Try, /*On fail goto*//*Label 13648*/ GIMT_Encode4(846529), // Rule ID 7474 //
     /*  846492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32),
     /*  846495 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane_up),
     /*  846500 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  846503 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846506 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846509 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  846512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846516 */     // (intrinsic_wo_chain:{ *:[i32] } 3344:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_PERMLANE_UP_B32_e64:{ *:[i32] } VGPR_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, SCSrc_b32:{ *:[i32] }:$src2)
     /*  846516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE_UP_B32_e64),
     /*  846519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846521 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846523 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846525 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846527 */     GIR_RootConstrainSelectedInstOperands,
     /*  846528 */     // GIR_Coverage, 7474,
     /*  846528 */     GIR_EraseRootFromParent_Done,
     /*  846529 */   // Label 13648: @846529
     /*  846529 */   GIM_Try, /*On fail goto*//*Label 13649*/ GIMT_Encode4(846571), // Rule ID 7475 //
     /*  846534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32),
     /*  846537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane_down),
     /*  846542 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  846545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846551 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  846554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846558 */     // (intrinsic_wo_chain:{ *:[i32] } 3342:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_PERMLANE_DOWN_B32_e64:{ *:[i32] } VGPR_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, SCSrc_b32:{ *:[i32] }:$src2)
     /*  846558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE_DOWN_B32_e64),
     /*  846561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846563 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846565 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846567 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846569 */     GIR_RootConstrainSelectedInstOperands,
     /*  846570 */     // GIR_Coverage, 7475,
     /*  846570 */     GIR_EraseRootFromParent_Done,
     /*  846571 */   // Label 13649: @846571
     /*  846571 */   GIM_Try, /*On fail goto*//*Label 13650*/ GIMT_Encode4(846613), // Rule ID 7476 //
     /*  846576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32),
     /*  846579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane_xor),
     /*  846584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  846587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  846590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846593 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  846596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  846600 */     // (intrinsic_wo_chain:{ *:[i32] } 3345:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_PERMLANE_XOR_B32_e64:{ *:[i32] } VGPR_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, SCSrc_b32:{ *:[i32] }:$src2)
     /*  846600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE_XOR_B32_e64),
     /*  846603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846605 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  846607 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846609 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  846611 */     GIR_RootConstrainSelectedInstOperands,
     /*  846612 */     // GIR_Coverage, 7476,
     /*  846612 */     GIR_EraseRootFromParent_Done,
     /*  846613 */   // Label 13650: @846613
     /*  846613 */   GIM_Try, /*On fail goto*//*Label 13651*/ GIMT_Encode4(846662), // Rule ID 3127 //
     /*  846618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  846621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp8),
     /*  846626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846639 */     // MIs[0] scale_sel
     /*  846639 */     // No operand predicates
     /*  846639 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846646 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2303:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64),
     /*  846649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846656 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846658 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846660 */     GIR_RootConstrainSelectedInstOperands,
     /*  846661 */     // GIR_Coverage, 3127,
     /*  846661 */     GIR_EraseRootFromParent_Done,
     /*  846662 */   // Label 13651: @846662
     /*  846662 */   GIM_Try, /*On fail goto*//*Label 13652*/ GIMT_Encode4(846711), // Rule ID 3128 //
     /*  846667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  846670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp8),
     /*  846675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846678 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846681 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846688 */     // MIs[0] scale_sel
     /*  846688 */     // No operand predicates
     /*  846688 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846695 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2303:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64),
     /*  846698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846705 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846707 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846709 */     GIR_RootConstrainSelectedInstOperands,
     /*  846710 */     // GIR_Coverage, 3128,
     /*  846710 */     GIR_EraseRootFromParent_Done,
     /*  846711 */   // Label 13652: @846711
     /*  846711 */   GIM_Try, /*On fail goto*//*Label 13653*/ GIMT_Encode4(846760), // Rule ID 3129 //
     /*  846716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  846719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp8),
     /*  846724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846727 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846730 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846737 */     // MIs[0] scale_sel
     /*  846737 */     // No operand predicates
     /*  846737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846744 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2303:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64),
     /*  846747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846754 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846756 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846758 */     GIR_RootConstrainSelectedInstOperands,
     /*  846759 */     // GIR_Coverage, 3129,
     /*  846759 */     GIR_EraseRootFromParent_Done,
     /*  846760 */   // Label 13653: @846760
     /*  846760 */   GIM_Try, /*On fail goto*//*Label 13654*/ GIMT_Encode4(846809), // Rule ID 3130 //
     /*  846765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  846768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp8),
     /*  846773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846786 */     // MIs[0] scale_sel
     /*  846786 */     // No operand predicates
     /*  846786 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846793 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2303:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64),
     /*  846796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846803 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846805 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846807 */     GIR_RootConstrainSelectedInstOperands,
     /*  846808 */     // GIR_Coverage, 3130,
     /*  846808 */     GIR_EraseRootFromParent_Done,
     /*  846809 */   // Label 13654: @846809
     /*  846809 */   GIM_Try, /*On fail goto*//*Label 13655*/ GIMT_Encode4(846858), // Rule ID 3131 //
     /*  846814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  846817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp8),
     /*  846822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846825 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846828 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846835 */     // MIs[0] scale_sel
     /*  846835 */     // No operand predicates
     /*  846835 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846842 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2303:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP8_e64),
     /*  846845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846852 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846854 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846856 */     GIR_RootConstrainSelectedInstOperands,
     /*  846857 */     // GIR_Coverage, 3131,
     /*  846857 */     GIR_EraseRootFromParent_Done,
     /*  846858 */   // Label 13655: @846858
     /*  846858 */   GIM_Try, /*On fail goto*//*Label 13656*/ GIMT_Encode4(846907), // Rule ID 3132 //
     /*  846863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  846866 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_bf8),
     /*  846871 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846874 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846877 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846884 */     // MIs[0] scale_sel
     /*  846884 */     // No operand predicates
     /*  846884 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846891 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2301:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_BF8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64),
     /*  846894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846901 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846903 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846905 */     GIR_RootConstrainSelectedInstOperands,
     /*  846906 */     // GIR_Coverage, 3132,
     /*  846906 */     GIR_EraseRootFromParent_Done,
     /*  846907 */   // Label 13656: @846907
     /*  846907 */   GIM_Try, /*On fail goto*//*Label 13657*/ GIMT_Encode4(846956), // Rule ID 3133 //
     /*  846912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  846915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_bf8),
     /*  846920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846933 */     // MIs[0] scale_sel
     /*  846933 */     // No operand predicates
     /*  846933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846940 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2301:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_BF8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64),
     /*  846943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846950 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  846952 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  846954 */     GIR_RootConstrainSelectedInstOperands,
     /*  846955 */     // GIR_Coverage, 3133,
     /*  846955 */     GIR_EraseRootFromParent_Done,
     /*  846956 */   // Label 13657: @846956
     /*  846956 */   GIM_Try, /*On fail goto*//*Label 13658*/ GIMT_Encode4(847005), // Rule ID 3134 //
     /*  846961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  846964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_bf8),
     /*  846969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  846972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  846975 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  846978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  846982 */     // MIs[0] scale_sel
     /*  846982 */     // No operand predicates
     /*  846982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  846989 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2301:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_BF8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  846989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64),
     /*  846992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  846994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  846999 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847001 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847003 */     GIR_RootConstrainSelectedInstOperands,
     /*  847004 */     // GIR_Coverage, 3134,
     /*  847004 */     GIR_EraseRootFromParent_Done,
     /*  847005 */   // Label 13658: @847005
     /*  847005 */   GIM_Try, /*On fail goto*//*Label 13659*/ GIMT_Encode4(847054), // Rule ID 3135 //
     /*  847010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  847013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_bf8),
     /*  847018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  847021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  847031 */     // MIs[0] scale_sel
     /*  847031 */     // No operand predicates
     /*  847031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847038 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2301:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_BF8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64),
     /*  847041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847048 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847050 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847052 */     GIR_RootConstrainSelectedInstOperands,
     /*  847053 */     // GIR_Coverage, 3135,
     /*  847053 */     GIR_EraseRootFromParent_Done,
     /*  847054 */   // Label 13659: @847054
     /*  847054 */   GIM_Try, /*On fail goto*//*Label 13660*/ GIMT_Encode4(847103), // Rule ID 3136 //
     /*  847059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  847062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_bf8),
     /*  847067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  847070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  847080 */     // MIs[0] scale_sel
     /*  847080 */     // No operand predicates
     /*  847080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847087 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2301:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_BF8_e64:{ *:[v8f16] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_BF8_e64),
     /*  847090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847097 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847099 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847101 */     GIR_RootConstrainSelectedInstOperands,
     /*  847102 */     // GIR_Coverage, 3136,
     /*  847102 */     GIR_EraseRootFromParent_Done,
     /*  847103 */   // Label 13660: @847103
     /*  847103 */   GIM_Try, /*On fail goto*//*Label 13661*/ GIMT_Encode4(847152), // Rule ID 3137 //
     /*  847108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  847111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp8),
     /*  847116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847129 */     // MIs[0] scale_sel
     /*  847129 */     // No operand predicates
     /*  847129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847136 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2306:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64),
     /*  847139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847146 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847148 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847150 */     GIR_RootConstrainSelectedInstOperands,
     /*  847151 */     // GIR_Coverage, 3137,
     /*  847151 */     GIR_EraseRootFromParent_Done,
     /*  847152 */   // Label 13661: @847152
     /*  847152 */   GIM_Try, /*On fail goto*//*Label 13662*/ GIMT_Encode4(847201), // Rule ID 3138 //
     /*  847157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  847160 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp8),
     /*  847165 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847171 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847178 */     // MIs[0] scale_sel
     /*  847178 */     // No operand predicates
     /*  847178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847185 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2306:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64),
     /*  847188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847195 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847197 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847199 */     GIR_RootConstrainSelectedInstOperands,
     /*  847200 */     // GIR_Coverage, 3138,
     /*  847200 */     GIR_EraseRootFromParent_Done,
     /*  847201 */   // Label 13662: @847201
     /*  847201 */   GIM_Try, /*On fail goto*//*Label 13663*/ GIMT_Encode4(847250), // Rule ID 3139 //
     /*  847206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  847209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp8),
     /*  847214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847220 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847227 */     // MIs[0] scale_sel
     /*  847227 */     // No operand predicates
     /*  847227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847234 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2306:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64),
     /*  847237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847244 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847246 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847248 */     GIR_RootConstrainSelectedInstOperands,
     /*  847249 */     // GIR_Coverage, 3139,
     /*  847249 */     GIR_EraseRootFromParent_Done,
     /*  847250 */   // Label 13663: @847250
     /*  847250 */   GIM_Try, /*On fail goto*//*Label 13664*/ GIMT_Encode4(847299), // Rule ID 3140 //
     /*  847255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  847258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp8),
     /*  847263 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847266 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847269 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847276 */     // MIs[0] scale_sel
     /*  847276 */     // No operand predicates
     /*  847276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847283 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2306:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64),
     /*  847286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847293 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847295 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847297 */     GIR_RootConstrainSelectedInstOperands,
     /*  847298 */     // GIR_Coverage, 3140,
     /*  847298 */     GIR_EraseRootFromParent_Done,
     /*  847299 */   // Label 13664: @847299
     /*  847299 */   GIM_Try, /*On fail goto*//*Label 13665*/ GIMT_Encode4(847348), // Rule ID 3141 //
     /*  847304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  847307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp8),
     /*  847312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847325 */     // MIs[0] scale_sel
     /*  847325 */     // No operand predicates
     /*  847325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847332 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2306:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP8_e64),
     /*  847335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847342 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847344 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847346 */     GIR_RootConstrainSelectedInstOperands,
     /*  847347 */     // GIR_Coverage, 3141,
     /*  847347 */     GIR_EraseRootFromParent_Done,
     /*  847348 */   // Label 13665: @847348
     /*  847348 */   GIM_Try, /*On fail goto*//*Label 13666*/ GIMT_Encode4(847397), // Rule ID 3142 //
     /*  847353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  847356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_bf8),
     /*  847361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847374 */     // MIs[0] scale_sel
     /*  847374 */     // No operand predicates
     /*  847374 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847381 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2304:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_BF8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64),
     /*  847384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847391 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847393 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847395 */     GIR_RootConstrainSelectedInstOperands,
     /*  847396 */     // GIR_Coverage, 3142,
     /*  847396 */     GIR_EraseRootFromParent_Done,
     /*  847397 */   // Label 13666: @847397
     /*  847397 */   GIM_Try, /*On fail goto*//*Label 13667*/ GIMT_Encode4(847446), // Rule ID 3143 //
     /*  847402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  847405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_bf8),
     /*  847410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847423 */     // MIs[0] scale_sel
     /*  847423 */     // No operand predicates
     /*  847423 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847430 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2304:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_BF8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64),
     /*  847433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847440 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847442 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847444 */     GIR_RootConstrainSelectedInstOperands,
     /*  847445 */     // GIR_Coverage, 3143,
     /*  847445 */     GIR_EraseRootFromParent_Done,
     /*  847446 */   // Label 13667: @847446
     /*  847446 */   GIM_Try, /*On fail goto*//*Label 13668*/ GIMT_Encode4(847495), // Rule ID 3144 //
     /*  847451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  847454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_bf8),
     /*  847459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847472 */     // MIs[0] scale_sel
     /*  847472 */     // No operand predicates
     /*  847472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847479 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2304:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_BF8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64),
     /*  847482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847489 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847491 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847493 */     GIR_RootConstrainSelectedInstOperands,
     /*  847494 */     // GIR_Coverage, 3144,
     /*  847494 */     GIR_EraseRootFromParent_Done,
     /*  847495 */   // Label 13668: @847495
     /*  847495 */   GIM_Try, /*On fail goto*//*Label 13669*/ GIMT_Encode4(847544), // Rule ID 3145 //
     /*  847500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  847503 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_bf8),
     /*  847508 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847511 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847514 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847521 */     // MIs[0] scale_sel
     /*  847521 */     // No operand predicates
     /*  847521 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847528 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2304:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_BF8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64),
     /*  847531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847538 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847540 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847542 */     GIR_RootConstrainSelectedInstOperands,
     /*  847543 */     // GIR_Coverage, 3145,
     /*  847543 */     GIR_EraseRootFromParent_Done,
     /*  847544 */   // Label 13669: @847544
     /*  847544 */   GIM_Try, /*On fail goto*//*Label 13670*/ GIMT_Encode4(847593), // Rule ID 3146 //
     /*  847549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  847552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_bf8),
     /*  847557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  847560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  847563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847570 */     // MIs[0] scale_sel
     /*  847570 */     // No operand predicates
     /*  847570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847577 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2304:{ *:[iPTR] }, (VOP3Mods0:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_BF8_e64:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_BF8_e64),
     /*  847580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847587 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847589 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847591 */     GIR_RootConstrainSelectedInstOperands,
     /*  847592 */     // GIR_Coverage, 3146,
     /*  847592 */     GIR_EraseRootFromParent_Done,
     /*  847593 */   // Label 13670: @847593
     /*  847593 */   GIM_Try, /*On fail goto*//*Label 13671*/ GIMT_Encode4(847642), // Rule ID 3147 //
     /*  847598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  847601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_fp6),
     /*  847606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847619 */     // MIs[0] scale_sel
     /*  847619 */     // No operand predicates
     /*  847619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847626 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2295:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_FP6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64),
     /*  847629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847636 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847638 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847640 */     GIR_RootConstrainSelectedInstOperands,
     /*  847641 */     // GIR_Coverage, 3147,
     /*  847641 */     GIR_EraseRootFromParent_Done,
     /*  847642 */   // Label 13671: @847642
     /*  847642 */   GIM_Try, /*On fail goto*//*Label 13672*/ GIMT_Encode4(847691), // Rule ID 3148 //
     /*  847647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  847650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_fp6),
     /*  847655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847668 */     // MIs[0] scale_sel
     /*  847668 */     // No operand predicates
     /*  847668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847675 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2295:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_FP6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64),
     /*  847678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847685 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847687 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847689 */     GIR_RootConstrainSelectedInstOperands,
     /*  847690 */     // GIR_Coverage, 3148,
     /*  847690 */     GIR_EraseRootFromParent_Done,
     /*  847691 */   // Label 13672: @847691
     /*  847691 */   GIM_Try, /*On fail goto*//*Label 13673*/ GIMT_Encode4(847740), // Rule ID 3149 //
     /*  847696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  847699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_fp6),
     /*  847704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847707 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847710 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847717 */     // MIs[0] scale_sel
     /*  847717 */     // No operand predicates
     /*  847717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847724 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2295:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_FP6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64),
     /*  847727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847734 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847736 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847738 */     GIR_RootConstrainSelectedInstOperands,
     /*  847739 */     // GIR_Coverage, 3149,
     /*  847739 */     GIR_EraseRootFromParent_Done,
     /*  847740 */   // Label 13673: @847740
     /*  847740 */   GIM_Try, /*On fail goto*//*Label 13674*/ GIMT_Encode4(847789), // Rule ID 3150 //
     /*  847745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  847748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_fp6),
     /*  847753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847766 */     // MIs[0] scale_sel
     /*  847766 */     // No operand predicates
     /*  847766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847773 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2295:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_FP6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64),
     /*  847776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847783 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847785 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847787 */     GIR_RootConstrainSelectedInstOperands,
     /*  847788 */     // GIR_Coverage, 3150,
     /*  847788 */     GIR_EraseRootFromParent_Done,
     /*  847789 */   // Label 13674: @847789
     /*  847789 */   GIM_Try, /*On fail goto*//*Label 13675*/ GIMT_Encode4(847838), // Rule ID 3151 //
     /*  847794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  847797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_fp6),
     /*  847802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847815 */     // MIs[0] scale_sel
     /*  847815 */     // No operand predicates
     /*  847815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847822 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2295:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_FP6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_FP6_e64),
     /*  847825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847832 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847834 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847836 */     GIR_RootConstrainSelectedInstOperands,
     /*  847837 */     // GIR_Coverage, 3151,
     /*  847837 */     GIR_EraseRootFromParent_Done,
     /*  847838 */   // Label 13675: @847838
     /*  847838 */   GIM_Try, /*On fail goto*//*Label 13676*/ GIMT_Encode4(847887), // Rule ID 3152 //
     /*  847843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  847846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_bf6),
     /*  847851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847864 */     // MIs[0] scale_sel
     /*  847864 */     // No operand predicates
     /*  847864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847871 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2294:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_BF6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64),
     /*  847874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847881 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847883 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847885 */     GIR_RootConstrainSelectedInstOperands,
     /*  847886 */     // GIR_Coverage, 3152,
     /*  847886 */     GIR_EraseRootFromParent_Done,
     /*  847887 */   // Label 13676: @847887
     /*  847887 */   GIM_Try, /*On fail goto*//*Label 13677*/ GIMT_Encode4(847936), // Rule ID 3153 //
     /*  847892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  847895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_bf6),
     /*  847900 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847903 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847906 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847913 */     // MIs[0] scale_sel
     /*  847913 */     // No operand predicates
     /*  847913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847920 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2294:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_BF6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64),
     /*  847923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847930 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847932 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847934 */     GIR_RootConstrainSelectedInstOperands,
     /*  847935 */     // GIR_Coverage, 3153,
     /*  847935 */     GIR_EraseRootFromParent_Done,
     /*  847936 */   // Label 13677: @847936
     /*  847936 */   GIM_Try, /*On fail goto*//*Label 13678*/ GIMT_Encode4(847985), // Rule ID 3154 //
     /*  847941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  847944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_bf6),
     /*  847949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  847952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  847955 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  847958 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  847962 */     // MIs[0] scale_sel
     /*  847962 */     // No operand predicates
     /*  847962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  847969 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2294:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_BF6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  847969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64),
     /*  847972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  847974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  847979 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  847981 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  847983 */     GIR_RootConstrainSelectedInstOperands,
     /*  847984 */     // GIR_Coverage, 3154,
     /*  847984 */     GIR_EraseRootFromParent_Done,
     /*  847985 */   // Label 13678: @847985
     /*  847985 */   GIM_Try, /*On fail goto*//*Label 13679*/ GIMT_Encode4(848034), // Rule ID 3155 //
     /*  847990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  847993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_bf6),
     /*  847998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  848001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  848011 */     // MIs[0] scale_sel
     /*  848011 */     // No operand predicates
     /*  848011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848018 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2294:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_BF6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64),
     /*  848021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848028 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848030 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848032 */     GIR_RootConstrainSelectedInstOperands,
     /*  848033 */     // GIR_Coverage, 3155,
     /*  848033 */     GIR_EraseRootFromParent_Done,
     /*  848034 */   // Label 13679: @848034
     /*  848034 */   GIM_Try, /*On fail goto*//*Label 13680*/ GIMT_Encode4(848083), // Rule ID 3156 //
     /*  848039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  848042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f16_bf6),
     /*  848047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  848050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  848060 */     // MIs[0] scale_sel
     /*  848060 */     // No operand predicates
     /*  848060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848067 */     // (intrinsic_wo_chain:{ *:[v16f16] } 2294:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F16_BF6_e64:{ *:[v16f16] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F16_BF6_e64),
     /*  848070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848077 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848079 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848081 */     GIR_RootConstrainSelectedInstOperands,
     /*  848082 */     // GIR_Coverage, 3156,
     /*  848082 */     GIR_EraseRootFromParent_Done,
     /*  848083 */   // Label 13680: @848083
     /*  848083 */   GIM_Try, /*On fail goto*//*Label 13681*/ GIMT_Encode4(848132), // Rule ID 3157 //
     /*  848088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  848091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_fp6),
     /*  848096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848102 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848109 */     // MIs[0] scale_sel
     /*  848109 */     // No operand predicates
     /*  848109 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848116 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2297:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_FP6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64),
     /*  848119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848126 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848128 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848130 */     GIR_RootConstrainSelectedInstOperands,
     /*  848131 */     // GIR_Coverage, 3157,
     /*  848131 */     GIR_EraseRootFromParent_Done,
     /*  848132 */   // Label 13681: @848132
     /*  848132 */   GIM_Try, /*On fail goto*//*Label 13682*/ GIMT_Encode4(848181), // Rule ID 3158 //
     /*  848137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  848140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_fp6),
     /*  848145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848158 */     // MIs[0] scale_sel
     /*  848158 */     // No operand predicates
     /*  848158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848165 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2297:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_FP6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64),
     /*  848168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848175 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848177 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848179 */     GIR_RootConstrainSelectedInstOperands,
     /*  848180 */     // GIR_Coverage, 3158,
     /*  848180 */     GIR_EraseRootFromParent_Done,
     /*  848181 */   // Label 13682: @848181
     /*  848181 */   GIM_Try, /*On fail goto*//*Label 13683*/ GIMT_Encode4(848230), // Rule ID 3159 //
     /*  848186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  848189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_fp6),
     /*  848194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848197 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848200 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848207 */     // MIs[0] scale_sel
     /*  848207 */     // No operand predicates
     /*  848207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848214 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2297:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_FP6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64),
     /*  848217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848224 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848226 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848228 */     GIR_RootConstrainSelectedInstOperands,
     /*  848229 */     // GIR_Coverage, 3159,
     /*  848229 */     GIR_EraseRootFromParent_Done,
     /*  848230 */   // Label 13683: @848230
     /*  848230 */   GIM_Try, /*On fail goto*//*Label 13684*/ GIMT_Encode4(848279), // Rule ID 3160 //
     /*  848235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  848238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_fp6),
     /*  848243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848249 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848256 */     // MIs[0] scale_sel
     /*  848256 */     // No operand predicates
     /*  848256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848263 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2297:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_FP6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64),
     /*  848266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848273 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848275 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848277 */     GIR_RootConstrainSelectedInstOperands,
     /*  848278 */     // GIR_Coverage, 3160,
     /*  848278 */     GIR_EraseRootFromParent_Done,
     /*  848279 */   // Label 13684: @848279
     /*  848279 */   GIM_Try, /*On fail goto*//*Label 13685*/ GIMT_Encode4(848328), // Rule ID 3161 //
     /*  848284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  848287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_fp6),
     /*  848292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848298 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848305 */     // MIs[0] scale_sel
     /*  848305 */     // No operand predicates
     /*  848305 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848312 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2297:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_FP6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_FP6_e64),
     /*  848315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848322 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848324 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848326 */     GIR_RootConstrainSelectedInstOperands,
     /*  848327 */     // GIR_Coverage, 3161,
     /*  848327 */     GIR_EraseRootFromParent_Done,
     /*  848328 */   // Label 13685: @848328
     /*  848328 */   GIM_Try, /*On fail goto*//*Label 13686*/ GIMT_Encode4(848377), // Rule ID 3162 //
     /*  848333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  848336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_bf6),
     /*  848341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848354 */     // MIs[0] scale_sel
     /*  848354 */     // No operand predicates
     /*  848354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848361 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2296:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_BF6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64),
     /*  848364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848371 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848373 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848375 */     GIR_RootConstrainSelectedInstOperands,
     /*  848376 */     // GIR_Coverage, 3162,
     /*  848376 */     GIR_EraseRootFromParent_Done,
     /*  848377 */   // Label 13686: @848377
     /*  848377 */   GIM_Try, /*On fail goto*//*Label 13687*/ GIMT_Encode4(848426), // Rule ID 3163 //
     /*  848382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  848385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_bf6),
     /*  848390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848403 */     // MIs[0] scale_sel
     /*  848403 */     // No operand predicates
     /*  848403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848410 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2296:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_BF6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64),
     /*  848413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848420 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848422 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848424 */     GIR_RootConstrainSelectedInstOperands,
     /*  848425 */     // GIR_Coverage, 3163,
     /*  848425 */     GIR_EraseRootFromParent_Done,
     /*  848426 */   // Label 13687: @848426
     /*  848426 */   GIM_Try, /*On fail goto*//*Label 13688*/ GIMT_Encode4(848475), // Rule ID 3164 //
     /*  848431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  848434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_bf6),
     /*  848439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848452 */     // MIs[0] scale_sel
     /*  848452 */     // No operand predicates
     /*  848452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848459 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2296:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_BF6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64),
     /*  848462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848469 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848471 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848473 */     GIR_RootConstrainSelectedInstOperands,
     /*  848474 */     // GIR_Coverage, 3164,
     /*  848474 */     GIR_EraseRootFromParent_Done,
     /*  848475 */   // Label 13688: @848475
     /*  848475 */   GIM_Try, /*On fail goto*//*Label 13689*/ GIMT_Encode4(848524), // Rule ID 3165 //
     /*  848480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  848483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_bf6),
     /*  848488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848501 */     // MIs[0] scale_sel
     /*  848501 */     // No operand predicates
     /*  848501 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848508 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2296:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_BF6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64),
     /*  848511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848518 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848520 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848522 */     GIR_RootConstrainSelectedInstOperands,
     /*  848523 */     // GIR_Coverage, 3165,
     /*  848523 */     GIR_EraseRootFromParent_Done,
     /*  848524 */   // Label 13689: @848524
     /*  848524 */   GIM_Try, /*On fail goto*//*Label 13690*/ GIMT_Encode4(848573), // Rule ID 3166 //
     /*  848529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  848532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk16_f32_bf6),
     /*  848537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  848540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v3s32,
     /*  848543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  848550 */     // MIs[0] scale_sel
     /*  848550 */     // No operand predicates
     /*  848550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848557 */     // (intrinsic_wo_chain:{ *:[v16f32] } 2296:{ *:[iPTR] }, (VOP3Mods0:{ *:[v3i32] } v3i32:{ *:[v3i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK16_F32_BF6_e64:{ *:[v16f32] } v3i32:{ *:[v3i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK16_F32_BF6_e64),
     /*  848560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848567 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848569 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848571 */     GIR_RootConstrainSelectedInstOperands,
     /*  848572 */     // GIR_Coverage, 3166,
     /*  848572 */     GIR_EraseRootFromParent_Done,
     /*  848573 */   // Label 13690: @848573
     /*  848573 */   GIM_Try, /*On fail goto*//*Label 13691*/ GIMT_Encode4(848622), // Rule ID 3167 //
     /*  848578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  848581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp4),
     /*  848586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  848589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  848599 */     // MIs[0] scale_sel
     /*  848599 */     // No operand predicates
     /*  848599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848606 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2302:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP4_e64:{ *:[v8f16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64),
     /*  848609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848616 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848618 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848620 */     GIR_RootConstrainSelectedInstOperands,
     /*  848621 */     // GIR_Coverage, 3167,
     /*  848621 */     GIR_EraseRootFromParent_Done,
     /*  848622 */   // Label 13691: @848622
     /*  848622 */   GIM_Try, /*On fail goto*//*Label 13692*/ GIMT_Encode4(848671), // Rule ID 3168 //
     /*  848627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  848630 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp4),
     /*  848635 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  848638 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848641 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  848648 */     // MIs[0] scale_sel
     /*  848648 */     // No operand predicates
     /*  848648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848655 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2302:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP4_e64:{ *:[v8f16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64),
     /*  848658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848665 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848667 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848669 */     GIR_RootConstrainSelectedInstOperands,
     /*  848670 */     // GIR_Coverage, 3168,
     /*  848670 */     GIR_EraseRootFromParent_Done,
     /*  848671 */   // Label 13692: @848671
     /*  848671 */   GIM_Try, /*On fail goto*//*Label 13693*/ GIMT_Encode4(848720), // Rule ID 3169 //
     /*  848676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  848679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp4),
     /*  848684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  848687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  848697 */     // MIs[0] scale_sel
     /*  848697 */     // No operand predicates
     /*  848697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848704 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2302:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP4_e64:{ *:[v8f16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64),
     /*  848707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848714 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848716 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848718 */     GIR_RootConstrainSelectedInstOperands,
     /*  848719 */     // GIR_Coverage, 3169,
     /*  848719 */     GIR_EraseRootFromParent_Done,
     /*  848720 */   // Label 13693: @848720
     /*  848720 */   GIM_Try, /*On fail goto*//*Label 13694*/ GIMT_Encode4(848769), // Rule ID 3170 //
     /*  848725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  848728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp4),
     /*  848733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  848736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  848746 */     // MIs[0] scale_sel
     /*  848746 */     // No operand predicates
     /*  848746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848753 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2302:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP4_e64:{ *:[v8f16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64),
     /*  848756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848763 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848765 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848767 */     GIR_RootConstrainSelectedInstOperands,
     /*  848768 */     // GIR_Coverage, 3170,
     /*  848768 */     GIR_EraseRootFromParent_Done,
     /*  848769 */   // Label 13694: @848769
     /*  848769 */   GIM_Try, /*On fail goto*//*Label 13695*/ GIMT_Encode4(848818), // Rule ID 3171 //
     /*  848774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  848777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f16_fp4),
     /*  848782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  848785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848788 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  848795 */     // MIs[0] scale_sel
     /*  848795 */     // No operand predicates
     /*  848795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848802 */     // (intrinsic_wo_chain:{ *:[v8f16] } 2302:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F16_FP4_e64:{ *:[v8f16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F16_FP4_e64),
     /*  848805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848812 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848814 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848816 */     GIR_RootConstrainSelectedInstOperands,
     /*  848817 */     // GIR_Coverage, 3171,
     /*  848817 */     GIR_EraseRootFromParent_Done,
     /*  848818 */   // Label 13695: @848818
     /*  848818 */   GIM_Try, /*On fail goto*//*Label 13696*/ GIMT_Encode4(848867), // Rule ID 3172 //
     /*  848823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  848826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp4),
     /*  848831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  848834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  848844 */     // MIs[0] scale_sel
     /*  848844 */     // No operand predicates
     /*  848844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848851 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2305:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP4_e64:{ *:[v8f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64),
     /*  848854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848861 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848863 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848865 */     GIR_RootConstrainSelectedInstOperands,
     /*  848866 */     // GIR_Coverage, 3172,
     /*  848866 */     GIR_EraseRootFromParent_Done,
     /*  848867 */   // Label 13696: @848867
     /*  848867 */   GIM_Try, /*On fail goto*//*Label 13697*/ GIMT_Encode4(848916), // Rule ID 3173 //
     /*  848872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  848875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp4),
     /*  848880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  848883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848886 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  848893 */     // MIs[0] scale_sel
     /*  848893 */     // No operand predicates
     /*  848893 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848900 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2305:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP4_e64:{ *:[v8f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64),
     /*  848903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848910 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848912 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848914 */     GIR_RootConstrainSelectedInstOperands,
     /*  848915 */     // GIR_Coverage, 3173,
     /*  848915 */     GIR_EraseRootFromParent_Done,
     /*  848916 */   // Label 13697: @848916
     /*  848916 */   GIM_Try, /*On fail goto*//*Label 13698*/ GIMT_Encode4(848965), // Rule ID 3174 //
     /*  848921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  848924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp4),
     /*  848929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  848932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  848942 */     // MIs[0] scale_sel
     /*  848942 */     // No operand predicates
     /*  848942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848949 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2305:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP4_e64:{ *:[v8f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64),
     /*  848952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  848954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  848959 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  848961 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  848963 */     GIR_RootConstrainSelectedInstOperands,
     /*  848964 */     // GIR_Coverage, 3174,
     /*  848964 */     GIR_EraseRootFromParent_Done,
     /*  848965 */   // Label 13698: @848965
     /*  848965 */   GIM_Try, /*On fail goto*//*Label 13699*/ GIMT_Encode4(849014), // Rule ID 3175 //
     /*  848970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  848973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp4),
     /*  848978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  848981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  848984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  848987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  848991 */     // MIs[0] scale_sel
     /*  848991 */     // No operand predicates
     /*  848991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  848998 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2305:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP4_e64:{ *:[v8f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  848998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64),
     /*  849001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849008 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  849010 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  849012 */     GIR_RootConstrainSelectedInstOperands,
     /*  849013 */     // GIR_Coverage, 3175,
     /*  849013 */     GIR_EraseRootFromParent_Done,
     /*  849014 */   // Label 13699: @849014
     /*  849014 */   GIM_Try, /*On fail goto*//*Label 13700*/ GIMT_Encode4(849063), // Rule ID 3176 //
     /*  849019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  849022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_scale_pk8_f32_fp4),
     /*  849027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  849030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  849033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  849036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  849040 */     // MIs[0] scale_sel
     /*  849040 */     // No operand predicates
     /*  849040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /*  849047 */     // (intrinsic_wo_chain:{ *:[v8f32] } 2305:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)  =>  (V_CVT_SCALE_PK8_F32_FP4_e64:{ *:[v8f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$scale_sel)
     /*  849047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SCALE_PK8_F32_FP4_e64),
     /*  849050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849057 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  849059 */     GIR_RootToRootCopy, /*OpIdx*/4, // scale_sel
     /*  849061 */     GIR_RootConstrainSelectedInstOperands,
     /*  849062 */     // GIR_Coverage, 3176,
     /*  849062 */     GIR_EraseRootFromParent_Done,
     /*  849063 */   // Label 13700: @849063
     /*  849063 */   GIM_Reject,
     /*  849064 */ // Label 13498: @849064
     /*  849064 */ GIM_Try, /*On fail goto*//*Label 13701*/ GIMT_Encode4(862013),
     /*  849069 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /*  849072 */   GIM_Try, /*On fail goto*//*Label 13702*/ GIMT_Encode4(849174), // Rule ID 7753 //
     /*  849077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  849080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  849088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  849091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  849094 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  849097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  849101 */     // MIs[0] Operand 5
     /*  849101 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849119 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849133 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2)
     /*  849133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr),
     /*  849136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849143 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849166 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849172 */     GIR_RootConstrainSelectedInstOperands,
     /*  849173 */     // GIR_Coverage, 7753,
     /*  849173 */     GIR_EraseRootFromParent_Done,
     /*  849174 */   // Label 13702: @849174
     /*  849174 */   GIM_Try, /*On fail goto*//*Label 13703*/ GIMT_Encode4(849276), // Rule ID 7754 //
     /*  849179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  849182 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849187 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  849190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  849193 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  849196 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  849199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  849203 */     // MIs[0] Operand 5
     /*  849203 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849214 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849228 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849235 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2)
     /*  849235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr),
     /*  849238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849274 */     GIR_RootConstrainSelectedInstOperands,
     /*  849275 */     // GIR_Coverage, 7754,
     /*  849275 */     GIR_EraseRootFromParent_Done,
     /*  849276 */   // Label 13703: @849276
     /*  849276 */   GIM_Try, /*On fail goto*//*Label 13704*/ GIMT_Encode4(849378), // Rule ID 7755 //
     /*  849281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  849284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  849292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  849295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  849298 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  849301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  849305 */     // MIs[0] Operand 5
     /*  849305 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849316 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849337 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2)
     /*  849337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr),
     /*  849340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849376 */     GIR_RootConstrainSelectedInstOperands,
     /*  849377 */     // GIR_Coverage, 7755,
     /*  849377 */     GIR_EraseRootFromParent_Done,
     /*  849378 */   // Label 13704: @849378
     /*  849378 */   GIM_Try, /*On fail goto*//*Label 13705*/ GIMT_Encode4(849480), // Rule ID 7756 //
     /*  849383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  849386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  849394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  849397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  849400 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  849403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  849407 */     // MIs[0] Operand 5
     /*  849407 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849418 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849432 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849439 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2)
     /*  849439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr),
     /*  849442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849464 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849478 */     GIR_RootConstrainSelectedInstOperands,
     /*  849479 */     // GIR_Coverage, 7756,
     /*  849479 */     GIR_EraseRootFromParent_Done,
     /*  849480 */   // Label 13705: @849480
     /*  849480 */   GIM_Try, /*On fail goto*//*Label 13706*/ GIMT_Encode4(849582), // Rule ID 7757 //
     /*  849485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  849488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  849496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  849499 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  849502 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  849505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  849509 */     // MIs[0] Operand 5
     /*  849509 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849520 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849541 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2)
     /*  849541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr),
     /*  849544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849556 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849580 */     GIR_RootConstrainSelectedInstOperands,
     /*  849581 */     // GIR_Coverage, 7757,
     /*  849581 */     GIR_EraseRootFromParent_Done,
     /*  849582 */   // Label 13706: @849582
     /*  849582 */   GIM_Try, /*On fail goto*//*Label 13707*/ GIMT_Encode4(849684), // Rule ID 7918 //
     /*  849587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  849590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  849598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  849601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  849604 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  849607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  849611 */     // MIs[0] Operand 5
     /*  849611 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849629 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849643 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2)
     /*  849643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr),
     /*  849646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849682 */     GIR_RootConstrainSelectedInstOperands,
     /*  849683 */     // GIR_Coverage, 7918,
     /*  849683 */     GIR_EraseRootFromParent_Done,
     /*  849684 */   // Label 13707: @849684
     /*  849684 */   GIM_Try, /*On fail goto*//*Label 13708*/ GIMT_Encode4(849786), // Rule ID 7919 //
     /*  849689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  849692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849697 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  849700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  849703 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  849706 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  849709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  849713 */     // MIs[0] Operand 5
     /*  849713 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849724 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849738 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849745 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2)
     /*  849745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr),
     /*  849748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849784 */     GIR_RootConstrainSelectedInstOperands,
     /*  849785 */     // GIR_Coverage, 7919,
     /*  849785 */     GIR_EraseRootFromParent_Done,
     /*  849786 */   // Label 13708: @849786
     /*  849786 */   GIM_Try, /*On fail goto*//*Label 13709*/ GIMT_Encode4(849888), // Rule ID 7920 //
     /*  849791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  849794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  849802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  849805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  849808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  849811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  849815 */     // MIs[0] Operand 5
     /*  849815 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849840 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849847 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2)
     /*  849847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr),
     /*  849850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849886 */     GIR_RootConstrainSelectedInstOperands,
     /*  849887 */     // GIR_Coverage, 7920,
     /*  849887 */     GIR_EraseRootFromParent_Done,
     /*  849888 */   // Label 13709: @849888
     /*  849888 */   GIM_Try, /*On fail goto*//*Label 13710*/ GIMT_Encode4(849990), // Rule ID 7921 //
     /*  849893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  849896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  849901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  849904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  849907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  849910 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  849913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  849917 */     // MIs[0] Operand 5
     /*  849917 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  849928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  849942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  849949 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2)
     /*  849949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr),
     /*  849952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  849954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  849959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  849964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  849969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  849974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  849977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  849982 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849985 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  849988 */     GIR_RootConstrainSelectedInstOperands,
     /*  849989 */     // GIR_Coverage, 7921,
     /*  849989 */     GIR_EraseRootFromParent_Done,
     /*  849990 */   // Label 13710: @849990
     /*  849990 */   GIM_Try, /*On fail goto*//*Label 13711*/ GIMT_Encode4(850092), // Rule ID 7922 //
     /*  849995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  849998 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850003 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  850006 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  850009 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  850012 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  850015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  850019 */     // MIs[0] Operand 5
     /*  850019 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850030 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850044 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  850051 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2)
     /*  850051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr),
     /*  850054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  850079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850084 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850090 */     GIR_RootConstrainSelectedInstOperands,
     /*  850091 */     // GIR_Coverage, 7922,
     /*  850091 */     GIR_EraseRootFromParent_Done,
     /*  850092 */   // Label 13711: @850092
     /*  850092 */   GIM_Try, /*On fail goto*//*Label 13712*/ GIMT_Encode4(850196), // Rule ID 7748 //
     /*  850097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  850100 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850105 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  850108 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  850111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  850114 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  850117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  850121 */     // MIs[0] Operand 5
     /*  850121 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850139 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850153 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  850153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr),
     /*  850156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850194 */     GIR_RootConstrainSelectedInstOperands,
     /*  850195 */     // GIR_Coverage, 7748,
     /*  850195 */     GIR_EraseRootFromParent_Done,
     /*  850196 */   // Label 13712: @850196
     /*  850196 */   GIM_Try, /*On fail goto*//*Label 13713*/ GIMT_Encode4(850300), // Rule ID 7749 //
     /*  850201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  850204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  850212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  850215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  850218 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  850221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  850225 */     // MIs[0] Operand 5
     /*  850225 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850257 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  850257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr),
     /*  850260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850262 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850267 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850272 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850277 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850298 */     GIR_RootConstrainSelectedInstOperands,
     /*  850299 */     // GIR_Coverage, 7749,
     /*  850299 */     GIR_EraseRootFromParent_Done,
     /*  850300 */   // Label 13713: @850300
     /*  850300 */   GIM_Try, /*On fail goto*//*Label 13714*/ GIMT_Encode4(850404), // Rule ID 7750 //
     /*  850305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  850308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  850316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  850319 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  850322 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  850325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  850329 */     // MIs[0] Operand 5
     /*  850329 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850361 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  850361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr),
     /*  850364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850402 */     GIR_RootConstrainSelectedInstOperands,
     /*  850403 */     // GIR_Coverage, 7750,
     /*  850403 */     GIR_EraseRootFromParent_Done,
     /*  850404 */   // Label 13714: @850404
     /*  850404 */   GIM_Try, /*On fail goto*//*Label 13715*/ GIMT_Encode4(850508), // Rule ID 7751 //
     /*  850409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  850412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  850420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  850423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  850426 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  850429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  850433 */     // MIs[0] Operand 5
     /*  850433 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850451 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850465 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  850465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr),
     /*  850468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850480 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850506 */     GIR_RootConstrainSelectedInstOperands,
     /*  850507 */     // GIR_Coverage, 7751,
     /*  850507 */     GIR_EraseRootFromParent_Done,
     /*  850508 */   // Label 13715: @850508
     /*  850508 */   GIM_Try, /*On fail goto*//*Label 13716*/ GIMT_Encode4(850612), // Rule ID 7752 //
     /*  850513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  850516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  850524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  850527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  850530 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  850533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  850537 */     // MIs[0] Operand 5
     /*  850537 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850548 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850569 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  850569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr),
     /*  850572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850610 */     GIR_RootConstrainSelectedInstOperands,
     /*  850611 */     // GIR_Coverage, 7752,
     /*  850611 */     GIR_EraseRootFromParent_Done,
     /*  850612 */   // Label 13716: @850612
     /*  850612 */   GIM_Try, /*On fail goto*//*Label 13717*/ GIMT_Encode4(850716), // Rule ID 7913 //
     /*  850617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  850620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  850628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  850631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  850634 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  850637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  850641 */     // MIs[0] Operand 5
     /*  850641 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850652 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850666 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850673 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2)
     /*  850673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr),
     /*  850676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850688 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850714 */     GIR_RootConstrainSelectedInstOperands,
     /*  850715 */     // GIR_Coverage, 7913,
     /*  850715 */     GIR_EraseRootFromParent_Done,
     /*  850716 */   // Label 13717: @850716
     /*  850716 */   GIM_Try, /*On fail goto*//*Label 13718*/ GIMT_Encode4(850820), // Rule ID 7914 //
     /*  850721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  850724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  850732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  850735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  850738 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  850741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  850745 */     // MIs[0] Operand 5
     /*  850745 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850763 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850777 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2)
     /*  850777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr),
     /*  850780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850818 */     GIR_RootConstrainSelectedInstOperands,
     /*  850819 */     // GIR_Coverage, 7914,
     /*  850819 */     GIR_EraseRootFromParent_Done,
     /*  850820 */   // Label 13718: @850820
     /*  850820 */   GIM_Try, /*On fail goto*//*Label 13719*/ GIMT_Encode4(850924), // Rule ID 7915 //
     /*  850825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  850828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  850836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  850839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  850842 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  850845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  850849 */     // MIs[0] Operand 5
     /*  850849 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850867 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850874 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850881 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2)
     /*  850881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr),
     /*  850884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  850896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  850901 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  850906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  850911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  850916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  850922 */     GIR_RootConstrainSelectedInstOperands,
     /*  850923 */     // GIR_Coverage, 7915,
     /*  850923 */     GIR_EraseRootFromParent_Done,
     /*  850924 */   // Label 13719: @850924
     /*  850924 */   GIM_Try, /*On fail goto*//*Label 13720*/ GIMT_Encode4(851028), // Rule ID 7916 //
     /*  850929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  850932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  850937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  850940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  850943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  850946 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  850949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  850953 */     // MIs[0] Operand 5
     /*  850953 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  850964 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  850978 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  850985 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2)
     /*  850985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr),
     /*  850988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  850990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  850995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  851015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851026 */     GIR_RootConstrainSelectedInstOperands,
     /*  851027 */     // GIR_Coverage, 7916,
     /*  851027 */     GIR_EraseRootFromParent_Done,
     /*  851028 */   // Label 13720: @851028
     /*  851028 */   GIM_Try, /*On fail goto*//*Label 13721*/ GIMT_Encode4(851132), // Rule ID 7917 //
     /*  851033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  851036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  851041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  851044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  851047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  851050 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  851053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  851057 */     // MIs[0] Operand 5
     /*  851057 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  851068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
     /*  851089 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3638:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2)
     /*  851089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr),
     /*  851092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /*  851119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851124 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851130 */     GIR_RootConstrainSelectedInstOperands,
     /*  851131 */     // GIR_Coverage, 7917,
     /*  851131 */     GIR_EraseRootFromParent_Done,
     /*  851132 */   // Label 13721: @851132
     /*  851132 */   GIM_Try, /*On fail goto*//*Label 13722*/ GIMT_Encode4(851230), // Rule ID 7838 //
     /*  851137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  851140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  851145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  851148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851154 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  851157 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  851164 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851171 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851185 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr),
     /*  851188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851210 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851217 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851228 */     GIR_RootConstrainSelectedInstOperands,
     /*  851229 */     // GIR_Coverage, 7838,
     /*  851229 */     GIR_EraseRootFromParent_Done,
     /*  851230 */   // Label 13722: @851230
     /*  851230 */   GIM_Try, /*On fail goto*//*Label 13723*/ GIMT_Encode4(851328), // Rule ID 7839 //
     /*  851235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  851238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  851243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  851246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851249 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851252 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  851255 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  851262 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851283 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr),
     /*  851286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851308 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851323 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851326 */     GIR_RootConstrainSelectedInstOperands,
     /*  851327 */     // GIR_Coverage, 7839,
     /*  851327 */     GIR_EraseRootFromParent_Done,
     /*  851328 */   // Label 13723: @851328
     /*  851328 */   GIM_Try, /*On fail goto*//*Label 13724*/ GIMT_Encode4(851426), // Rule ID 7840 //
     /*  851333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  851336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  851341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  851344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851350 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  851353 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  851360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851374 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851381 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr),
     /*  851384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851401 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851406 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851424 */     GIR_RootConstrainSelectedInstOperands,
     /*  851425 */     // GIR_Coverage, 7840,
     /*  851425 */     GIR_EraseRootFromParent_Done,
     /*  851426 */   // Label 13724: @851426
     /*  851426 */   GIM_Try, /*On fail goto*//*Label 13725*/ GIMT_Encode4(851524), // Rule ID 7841 //
     /*  851431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  851434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  851439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  851442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851448 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  851451 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  851458 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851479 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr),
     /*  851482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851494 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851504 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851522 */     GIR_RootConstrainSelectedInstOperands,
     /*  851523 */     // GIR_Coverage, 7841,
     /*  851523 */     GIR_EraseRootFromParent_Done,
     /*  851524 */   // Label 13725: @851524
     /*  851524 */   GIM_Try, /*On fail goto*//*Label 13726*/ GIMT_Encode4(851622), // Rule ID 7842 //
     /*  851529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  851532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  851537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  851540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851546 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  851549 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  851556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851563 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851577 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr),
     /*  851580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851582 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851602 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851620 */     GIR_RootConstrainSelectedInstOperands,
     /*  851621 */     // GIR_Coverage, 7842,
     /*  851621 */     GIR_EraseRootFromParent_Done,
     /*  851622 */   // Label 13726: @851622
     /*  851622 */   GIM_Try, /*On fail goto*//*Label 13727*/ GIMT_Encode4(851720), // Rule ID 7848 //
     /*  851627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  851630 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  851635 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  851638 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851641 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851644 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  851647 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  851654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851675 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr),
     /*  851678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851700 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851718 */     GIR_RootConstrainSelectedInstOperands,
     /*  851719 */     // GIR_Coverage, 7848,
     /*  851719 */     GIR_EraseRootFromParent_Done,
     /*  851720 */   // Label 13727: @851720
     /*  851720 */   GIM_Try, /*On fail goto*//*Label 13728*/ GIMT_Encode4(851818), // Rule ID 7849 //
     /*  851725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  851728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  851733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  851736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851742 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  851745 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  851752 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851759 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851773 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr),
     /*  851776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851798 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851816 */     GIR_RootConstrainSelectedInstOperands,
     /*  851817 */     // GIR_Coverage, 7849,
     /*  851817 */     GIR_EraseRootFromParent_Done,
     /*  851818 */   // Label 13728: @851818
     /*  851818 */   GIM_Try, /*On fail goto*//*Label 13729*/ GIMT_Encode4(851916), // Rule ID 7850 //
     /*  851823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  851826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  851831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  851834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851840 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  851843 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  851850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851864 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851871 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr),
     /*  851874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851896 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  851903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  851908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  851914 */     GIR_RootConstrainSelectedInstOperands,
     /*  851915 */     // GIR_Coverage, 7850,
     /*  851915 */     GIR_EraseRootFromParent_Done,
     /*  851916 */   // Label 13729: @851916
     /*  851916 */   GIM_Try, /*On fail goto*//*Label 13730*/ GIMT_Encode4(852014), // Rule ID 7851 //
     /*  851921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  851924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  851929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  851932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  851935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  851938 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  851941 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  851944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  851948 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851955 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  851962 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  851969 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  851969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr),
     /*  851972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  851974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  851979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  851984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  851989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  851994 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  851996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  852006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852012 */     GIR_RootConstrainSelectedInstOperands,
     /*  852013 */     // GIR_Coverage, 7851,
     /*  852013 */     GIR_EraseRootFromParent_Done,
     /*  852014 */   // Label 13730: @852014
     /*  852014 */   GIM_Try, /*On fail goto*//*Label 13731*/ GIMT_Encode4(852112), // Rule ID 7852 //
     /*  852019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  852022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  852027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  852030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  852033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  852036 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  852039 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  852046 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  852067 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  852067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr),
     /*  852070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852092 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
     /*  852104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852110 */     GIR_RootConstrainSelectedInstOperands,
     /*  852111 */     // GIR_Coverage, 7852,
     /*  852111 */     GIR_EraseRootFromParent_Done,
     /*  852112 */   // Label 13731: @852112
     /*  852112 */   GIM_Try, /*On fail goto*//*Label 13732*/ GIMT_Encode4(852210), // Rule ID 8003 //
     /*  852117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  852120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  852125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  852128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852134 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  852137 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  852144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852165 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr),
     /*  852168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852190 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852192 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852208 */     GIR_RootConstrainSelectedInstOperands,
     /*  852209 */     // GIR_Coverage, 8003,
     /*  852209 */     GIR_EraseRootFromParent_Done,
     /*  852210 */   // Label 13732: @852210
     /*  852210 */   GIM_Try, /*On fail goto*//*Label 13733*/ GIMT_Encode4(852308), // Rule ID 8004 //
     /*  852215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  852218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  852223 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  852226 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852229 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852232 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  852235 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  852242 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852249 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852256 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852263 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr),
     /*  852266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852283 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852288 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852306 */     GIR_RootConstrainSelectedInstOperands,
     /*  852307 */     // GIR_Coverage, 8004,
     /*  852307 */     GIR_EraseRootFromParent_Done,
     /*  852308 */   // Label 13733: @852308
     /*  852308 */   GIM_Try, /*On fail goto*//*Label 13734*/ GIMT_Encode4(852406), // Rule ID 8005 //
     /*  852313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  852316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  852321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  852324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852330 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  852333 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  852340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852347 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852361 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr),
     /*  852364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852386 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852404 */     GIR_RootConstrainSelectedInstOperands,
     /*  852405 */     // GIR_Coverage, 8005,
     /*  852405 */     GIR_EraseRootFromParent_Done,
     /*  852406 */   // Label 13734: @852406
     /*  852406 */   GIM_Try, /*On fail goto*//*Label 13735*/ GIMT_Encode4(852504), // Rule ID 8006 //
     /*  852411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  852414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  852419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  852422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852428 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  852431 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  852438 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852445 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852459 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr),
     /*  852462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852484 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852502 */     GIR_RootConstrainSelectedInstOperands,
     /*  852503 */     // GIR_Coverage, 8006,
     /*  852503 */     GIR_EraseRootFromParent_Done,
     /*  852504 */   // Label 13735: @852504
     /*  852504 */   GIM_Try, /*On fail goto*//*Label 13736*/ GIMT_Encode4(852602), // Rule ID 8007 //
     /*  852509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  852512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
     /*  852517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  852520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852526 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  852529 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  852536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852557 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3592:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr),
     /*  852560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852577 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852582 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852600 */     GIR_RootConstrainSelectedInstOperands,
     /*  852601 */     // GIR_Coverage, 8007,
     /*  852601 */     GIR_EraseRootFromParent_Done,
     /*  852602 */   // Label 13736: @852602
     /*  852602 */   GIM_Try, /*On fail goto*//*Label 13737*/ GIMT_Encode4(852700), // Rule ID 8013 //
     /*  852607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  852610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  852615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  852618 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852621 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852624 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  852627 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  852634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852648 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852655 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr),
     /*  852658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852660 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852680 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852682 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852698 */     GIR_RootConstrainSelectedInstOperands,
     /*  852699 */     // GIR_Coverage, 8013,
     /*  852699 */     GIR_EraseRootFromParent_Done,
     /*  852700 */   // Label 13737: @852700
     /*  852700 */   GIM_Try, /*On fail goto*//*Label 13738*/ GIMT_Encode4(852798), // Rule ID 8014 //
     /*  852705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  852708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  852713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  852716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852719 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852722 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  852725 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  852732 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852753 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr),
     /*  852756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852778 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852780 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852790 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852796 */     GIR_RootConstrainSelectedInstOperands,
     /*  852797 */     // GIR_Coverage, 8014,
     /*  852797 */     GIR_EraseRootFromParent_Done,
     /*  852798 */   // Label 13738: @852798
     /*  852798 */   GIM_Try, /*On fail goto*//*Label 13739*/ GIMT_Encode4(852896), // Rule ID 8015 //
     /*  852803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  852806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  852811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  852814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852820 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  852823 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  852830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852837 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852851 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr),
     /*  852854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852876 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852894 */     GIR_RootConstrainSelectedInstOperands,
     /*  852895 */     // GIR_Coverage, 8015,
     /*  852895 */     GIR_EraseRootFromParent_Done,
     /*  852896 */   // Label 13739: @852896
     /*  852896 */   GIM_Try, /*On fail goto*//*Label 13740*/ GIMT_Encode4(852994), // Rule ID 8016 //
     /*  852901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  852904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  852909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  852912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  852915 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  852918 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  852921 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  852924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  852928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852935 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  852942 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  852949 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  852949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr),
     /*  852952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  852954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  852959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  852964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  852969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  852974 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  852976 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  852981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  852986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  852992 */     GIR_RootConstrainSelectedInstOperands,
     /*  852993 */     // GIR_Coverage, 8016,
     /*  852993 */     GIR_EraseRootFromParent_Done,
     /*  852994 */   // Label 13740: @852994
     /*  852994 */   GIM_Try, /*On fail goto*//*Label 13741*/ GIMT_Encode4(853092), // Rule ID 8017 //
     /*  852999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  853002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
     /*  853007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  853010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  853013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  853016 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  853019 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  853022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  853026 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  853033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
     /*  853040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  853047 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3583:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  853047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr),
     /*  853050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /*  853057 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /*  853062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /*  853067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /*  853072 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  853074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /*  853079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
     /*  853084 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853090 */     GIR_RootConstrainSelectedInstOperands,
     /*  853091 */     // GIR_Coverage, 8017,
     /*  853091 */     GIR_EraseRootFromParent_Done,
     /*  853092 */   // Label 13741: @853092
     /*  853092 */   GIM_Try, /*On fail goto*//*Label 13742*/ GIMT_Encode4(853170), // Rule ID 7763 //
     /*  853097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  853100 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853105 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  853108 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  853111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  853114 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  853117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  853121 */     // MIs[0] Operand 5
     /*  853121 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853139 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  853139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr),
     /*  853142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853147 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853152 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853157 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853168 */     GIR_RootConstrainSelectedInstOperands,
     /*  853169 */     // GIR_Coverage, 7763,
     /*  853169 */     GIR_EraseRootFromParent_Done,
     /*  853170 */   // Label 13742: @853170
     /*  853170 */   GIM_Try, /*On fail goto*//*Label 13743*/ GIMT_Encode4(853248), // Rule ID 7764 //
     /*  853175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  853178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  853186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  853189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  853192 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  853195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  853199 */     // MIs[0] Operand 5
     /*  853199 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853217 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  853217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr),
     /*  853220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853222 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853225 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853230 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853246 */     GIR_RootConstrainSelectedInstOperands,
     /*  853247 */     // GIR_Coverage, 7764,
     /*  853247 */     GIR_EraseRootFromParent_Done,
     /*  853248 */   // Label 13743: @853248
     /*  853248 */   GIM_Try, /*On fail goto*//*Label 13744*/ GIMT_Encode4(853326), // Rule ID 7765 //
     /*  853253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  853256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  853264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  853267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  853270 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  853273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  853277 */     // MIs[0] Operand 5
     /*  853277 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853288 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853295 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  853295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr),
     /*  853298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853303 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853308 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853318 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853324 */     GIR_RootConstrainSelectedInstOperands,
     /*  853325 */     // GIR_Coverage, 7765,
     /*  853325 */     GIR_EraseRootFromParent_Done,
     /*  853326 */   // Label 13744: @853326
     /*  853326 */   GIM_Try, /*On fail goto*//*Label 13745*/ GIMT_Encode4(853404), // Rule ID 7766 //
     /*  853331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  853334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  853342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  853345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  853348 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  853351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  853355 */     // MIs[0] Operand 5
     /*  853355 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853366 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853373 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  853373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr),
     /*  853376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853381 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853386 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853402 */     GIR_RootConstrainSelectedInstOperands,
     /*  853403 */     // GIR_Coverage, 7766,
     /*  853403 */     GIR_EraseRootFromParent_Done,
     /*  853404 */   // Label 13745: @853404
     /*  853404 */   GIM_Try, /*On fail goto*//*Label 13746*/ GIMT_Encode4(853482), // Rule ID 7767 //
     /*  853409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  853412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  853420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  853423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  853426 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  853429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  853433 */     // MIs[0] Operand 5
     /*  853433 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853451 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  853451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr),
     /*  853454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853459 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853461 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853464 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853480 */     GIR_RootConstrainSelectedInstOperands,
     /*  853481 */     // GIR_Coverage, 7767,
     /*  853481 */     GIR_EraseRootFromParent_Done,
     /*  853482 */   // Label 13746: @853482
     /*  853482 */   GIM_Try, /*On fail goto*//*Label 13747*/ GIMT_Encode4(853560), // Rule ID 7928 //
     /*  853487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  853490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  853498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  853501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  853504 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  853507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  853511 */     // MIs[0] Operand 5
     /*  853511 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853522 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853529 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  853529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr),
     /*  853532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853537 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853542 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853558 */     GIR_RootConstrainSelectedInstOperands,
     /*  853559 */     // GIR_Coverage, 7928,
     /*  853559 */     GIR_EraseRootFromParent_Done,
     /*  853560 */   // Label 13747: @853560
     /*  853560 */   GIM_Try, /*On fail goto*//*Label 13748*/ GIMT_Encode4(853638), // Rule ID 7929 //
     /*  853565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  853568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  853576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  853579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  853582 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  853585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  853589 */     // MIs[0] Operand 5
     /*  853589 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853607 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  853607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr),
     /*  853610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853615 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853620 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853636 */     GIR_RootConstrainSelectedInstOperands,
     /*  853637 */     // GIR_Coverage, 7929,
     /*  853637 */     GIR_EraseRootFromParent_Done,
     /*  853638 */   // Label 13748: @853638
     /*  853638 */   GIM_Try, /*On fail goto*//*Label 13749*/ GIMT_Encode4(853716), // Rule ID 7930 //
     /*  853643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  853646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  853654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  853657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  853660 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  853663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  853667 */     // MIs[0] Operand 5
     /*  853667 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853685 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  853685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr),
     /*  853688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853693 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853698 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853711 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853714 */     GIR_RootConstrainSelectedInstOperands,
     /*  853715 */     // GIR_Coverage, 7930,
     /*  853715 */     GIR_EraseRootFromParent_Done,
     /*  853716 */   // Label 13749: @853716
     /*  853716 */   GIM_Try, /*On fail goto*//*Label 13750*/ GIMT_Encode4(853794), // Rule ID 7931 //
     /*  853721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  853724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  853732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  853735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  853738 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  853741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  853745 */     // MIs[0] Operand 5
     /*  853745 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853763 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  853763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr),
     /*  853766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853771 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853776 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853792 */     GIR_RootConstrainSelectedInstOperands,
     /*  853793 */     // GIR_Coverage, 7931,
     /*  853793 */     GIR_EraseRootFromParent_Done,
     /*  853794 */   // Label 13750: @853794
     /*  853794 */   GIM_Try, /*On fail goto*//*Label 13751*/ GIMT_Encode4(853872), // Rule ID 7932 //
     /*  853799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  853802 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  853807 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  853810 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  853813 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  853816 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  853819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  853823 */     // MIs[0] Operand 5
     /*  853823 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  853834 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853841 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  853841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr),
     /*  853844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853849 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853854 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  853859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853870 */     GIR_RootConstrainSelectedInstOperands,
     /*  853871 */     // GIR_Coverage, 7932,
     /*  853871 */     GIR_EraseRootFromParent_Done,
     /*  853872 */   // Label 13751: @853872
     /*  853872 */   GIM_Try, /*On fail goto*//*Label 13752*/ GIMT_Encode4(853939), // Rule ID 8263 //
     /*  853877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  853880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  853885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  853888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  853891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  853894 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  853897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  853901 */     // MIs[0] src2_modifiers
     /*  853901 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  853904 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853911 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2))  =>  (V_WMMA_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  853911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_threeaddr),
     /*  853914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853916 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853918 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853920 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  853926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  853937 */     GIR_RootConstrainSelectedInstOperands,
     /*  853938 */     // GIR_Coverage, 8263,
     /*  853938 */     GIR_EraseRootFromParent_Done,
     /*  853939 */   // Label 13752: @853939
     /*  853939 */   GIM_Try, /*On fail goto*//*Label 13753*/ GIMT_Encode4(854006), // Rule ID 8264 //
     /*  853944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  853947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  853952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  853955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  853958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  853961 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  853964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  853968 */     // MIs[0] src2_modifiers
     /*  853968 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  853971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  853978 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2))  =>  (V_WMMA_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  853978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_threeaddr),
     /*  853981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  853983 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  853985 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  853987 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  853993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  853998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854004 */     GIR_RootConstrainSelectedInstOperands,
     /*  854005 */     // GIR_Coverage, 8264,
     /*  854005 */     GIR_EraseRootFromParent_Done,
     /*  854006 */   // Label 13753: @854006
     /*  854006 */   GIM_Try, /*On fail goto*//*Label 13754*/ GIMT_Encode4(854073), // Rule ID 8265 //
     /*  854011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  854014 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  854019 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  854022 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  854025 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  854028 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  854031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  854035 */     // MIs[0] src2_modifiers
     /*  854035 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  854038 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  854045 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2))  =>  (V_WMMA_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  854045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_threeaddr),
     /*  854048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854050 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854052 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854054 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  854060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854071 */     GIR_RootConstrainSelectedInstOperands,
     /*  854072 */     // GIR_Coverage, 8265,
     /*  854072 */     GIR_EraseRootFromParent_Done,
     /*  854073 */   // Label 13754: @854073
     /*  854073 */   GIM_Try, /*On fail goto*//*Label 13755*/ GIMT_Encode4(854140), // Rule ID 8266 //
     /*  854078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  854081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  854086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  854089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  854092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  854095 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  854098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  854102 */     // MIs[0] src2_modifiers
     /*  854102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  854105 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  854112 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2))  =>  (V_WMMA_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  854112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_threeaddr),
     /*  854115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854117 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854119 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854121 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  854127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854138 */     GIR_RootConstrainSelectedInstOperands,
     /*  854139 */     // GIR_Coverage, 8266,
     /*  854139 */     GIR_EraseRootFromParent_Done,
     /*  854140 */   // Label 13755: @854140
     /*  854140 */   GIM_Try, /*On fail goto*//*Label 13756*/ GIMT_Encode4(854207), // Rule ID 8267 //
     /*  854145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  854148 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  854153 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  854156 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  854159 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  854162 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  854165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  854169 */     // MIs[0] src2_modifiers
     /*  854169 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  854172 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  854179 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2))  =>  (V_WMMA_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  854179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_threeaddr),
     /*  854182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854184 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854186 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854188 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  854194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854205 */     GIR_RootConstrainSelectedInstOperands,
     /*  854206 */     // GIR_Coverage, 8267,
     /*  854206 */     GIR_EraseRootFromParent_Done,
     /*  854207 */   // Label 13756: @854207
     /*  854207 */   GIM_Try, /*On fail goto*//*Label 13757*/ GIMT_Encode4(854281), // Rule ID 7843 //
     /*  854212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  854215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  854220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  854223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854229 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  854232 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  854239 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854246 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3589:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr),
     /*  854249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854254 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854259 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854261 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854279 */     GIR_RootConstrainSelectedInstOperands,
     /*  854280 */     // GIR_Coverage, 7843,
     /*  854280 */     GIR_EraseRootFromParent_Done,
     /*  854281 */   // Label 13757: @854281
     /*  854281 */   GIM_Try, /*On fail goto*//*Label 13758*/ GIMT_Encode4(854355), // Rule ID 7844 //
     /*  854286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  854289 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  854294 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  854297 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854300 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854303 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  854306 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  854313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854320 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3589:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr),
     /*  854323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854325 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854328 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854333 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854335 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854353 */     GIR_RootConstrainSelectedInstOperands,
     /*  854354 */     // GIR_Coverage, 7844,
     /*  854354 */     GIR_EraseRootFromParent_Done,
     /*  854355 */   // Label 13758: @854355
     /*  854355 */   GIM_Try, /*On fail goto*//*Label 13759*/ GIMT_Encode4(854429), // Rule ID 7845 //
     /*  854360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  854363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  854368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  854371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854374 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854377 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  854380 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  854387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854394 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3589:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr),
     /*  854397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854402 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854407 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854409 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854427 */     GIR_RootConstrainSelectedInstOperands,
     /*  854428 */     // GIR_Coverage, 7845,
     /*  854428 */     GIR_EraseRootFromParent_Done,
     /*  854429 */   // Label 13759: @854429
     /*  854429 */   GIM_Try, /*On fail goto*//*Label 13760*/ GIMT_Encode4(854503), // Rule ID 7846 //
     /*  854434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  854437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  854442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  854445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854451 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  854454 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  854461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854468 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3589:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr),
     /*  854471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854473 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854476 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854481 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854483 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854501 */     GIR_RootConstrainSelectedInstOperands,
     /*  854502 */     // GIR_Coverage, 7846,
     /*  854502 */     GIR_EraseRootFromParent_Done,
     /*  854503 */   // Label 13760: @854503
     /*  854503 */   GIM_Try, /*On fail goto*//*Label 13761*/ GIMT_Encode4(854577), // Rule ID 7847 //
     /*  854508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  854511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  854516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  854519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854525 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  854528 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  854535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854542 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3589:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr),
     /*  854545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854550 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854555 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854557 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854575 */     GIR_RootConstrainSelectedInstOperands,
     /*  854576 */     // GIR_Coverage, 7847,
     /*  854576 */     GIR_EraseRootFromParent_Done,
     /*  854577 */   // Label 13761: @854577
     /*  854577 */   GIM_Try, /*On fail goto*//*Label 13762*/ GIMT_Encode4(854651), // Rule ID 7853 //
     /*  854582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  854585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  854590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  854593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854599 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  854602 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  854609 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854616 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr),
     /*  854619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854624 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854629 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854631 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854649 */     GIR_RootConstrainSelectedInstOperands,
     /*  854650 */     // GIR_Coverage, 7853,
     /*  854650 */     GIR_EraseRootFromParent_Done,
     /*  854651 */   // Label 13762: @854651
     /*  854651 */   GIM_Try, /*On fail goto*//*Label 13763*/ GIMT_Encode4(854725), // Rule ID 7854 //
     /*  854656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  854659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  854664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  854667 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854673 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  854676 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  854683 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854690 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr),
     /*  854693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854698 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854703 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854705 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854707 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854712 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854723 */     GIR_RootConstrainSelectedInstOperands,
     /*  854724 */     // GIR_Coverage, 7854,
     /*  854724 */     GIR_EraseRootFromParent_Done,
     /*  854725 */   // Label 13763: @854725
     /*  854725 */   GIM_Try, /*On fail goto*//*Label 13764*/ GIMT_Encode4(854799), // Rule ID 7855 //
     /*  854730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  854733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  854738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  854741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854747 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  854750 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  854757 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854764 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr),
     /*  854767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854772 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854777 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854779 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854781 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854797 */     GIR_RootConstrainSelectedInstOperands,
     /*  854798 */     // GIR_Coverage, 7855,
     /*  854798 */     GIR_EraseRootFromParent_Done,
     /*  854799 */   // Label 13764: @854799
     /*  854799 */   GIM_Try, /*On fail goto*//*Label 13765*/ GIMT_Encode4(854873), // Rule ID 7856 //
     /*  854804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  854807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  854812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  854815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854821 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  854824 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  854831 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854838 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr),
     /*  854841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854846 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854851 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854853 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854871 */     GIR_RootConstrainSelectedInstOperands,
     /*  854872 */     // GIR_Coverage, 7856,
     /*  854872 */     GIR_EraseRootFromParent_Done,
     /*  854873 */   // Label 13765: @854873
     /*  854873 */   GIM_Try, /*On fail goto*//*Label 13766*/ GIMT_Encode4(854947), // Rule ID 7857 //
     /*  854878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  854881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  854886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  854889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  854892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  854895 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  854898 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  854905 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854912 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr),
     /*  854915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854920 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  854925 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854927 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  854934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  854939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  854945 */     GIR_RootConstrainSelectedInstOperands,
     /*  854946 */     // GIR_Coverage, 7857,
     /*  854946 */     GIR_EraseRootFromParent_Done,
     /*  854947 */   // Label 13766: @854947
     /*  854947 */   GIM_Try, /*On fail goto*//*Label 13767*/ GIMT_Encode4(855009), // Rule ID 7873 //
     /*  854952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  854955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  854960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  854963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  854966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  854969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  854972 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  854975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  854979 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  854986 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3594:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  854986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr),
     /*  854989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  854991 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  854993 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  854995 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  854997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855007 */     GIR_RootConstrainSelectedInstOperands,
     /*  855008 */     // GIR_Coverage, 7873,
     /*  855008 */     GIR_EraseRootFromParent_Done,
     /*  855009 */   // Label 13767: @855009
     /*  855009 */   GIM_Try, /*On fail goto*//*Label 13768*/ GIMT_Encode4(855071), // Rule ID 7874 //
     /*  855014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  855017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  855022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855031 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855034 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855041 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855048 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3594:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr),
     /*  855051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855053 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855055 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855057 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855069 */     GIR_RootConstrainSelectedInstOperands,
     /*  855070 */     // GIR_Coverage, 7874,
     /*  855070 */     GIR_EraseRootFromParent_Done,
     /*  855071 */   // Label 13768: @855071
     /*  855071 */   GIM_Try, /*On fail goto*//*Label 13769*/ GIMT_Encode4(855133), // Rule ID 7875 //
     /*  855076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  855079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  855084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855093 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855096 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855103 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855110 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3594:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr),
     /*  855113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855115 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855117 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855119 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855131 */     GIR_RootConstrainSelectedInstOperands,
     /*  855132 */     // GIR_Coverage, 7875,
     /*  855132 */     GIR_EraseRootFromParent_Done,
     /*  855133 */   // Label 13769: @855133
     /*  855133 */   GIM_Try, /*On fail goto*//*Label 13770*/ GIMT_Encode4(855195), // Rule ID 7876 //
     /*  855138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  855141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  855146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855152 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855155 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855158 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855172 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3594:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr),
     /*  855175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855177 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855179 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855181 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855193 */     GIR_RootConstrainSelectedInstOperands,
     /*  855194 */     // GIR_Coverage, 7876,
     /*  855194 */     GIR_EraseRootFromParent_Done,
     /*  855195 */   // Label 13770: @855195
     /*  855195 */   GIM_Try, /*On fail goto*//*Label 13771*/ GIMT_Encode4(855257), // Rule ID 7877 //
     /*  855200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  855203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  855208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855217 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855220 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855234 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3594:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr),
     /*  855237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855239 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855241 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855243 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855250 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855255 */     GIR_RootConstrainSelectedInstOperands,
     /*  855256 */     // GIR_Coverage, 7877,
     /*  855256 */     GIR_EraseRootFromParent_Done,
     /*  855257 */   // Label 13771: @855257
     /*  855257 */   GIM_Try, /*On fail goto*//*Label 13772*/ GIMT_Encode4(855319), // Rule ID 7878 //
     /*  855262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  855265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  855270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855279 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855282 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855296 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3593:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr),
     /*  855299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855301 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855303 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855305 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855317 */     GIR_RootConstrainSelectedInstOperands,
     /*  855318 */     // GIR_Coverage, 7878,
     /*  855318 */     GIR_EraseRootFromParent_Done,
     /*  855319 */   // Label 13772: @855319
     /*  855319 */   GIM_Try, /*On fail goto*//*Label 13773*/ GIMT_Encode4(855381), // Rule ID 7879 //
     /*  855324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  855327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  855332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855341 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855344 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855351 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855358 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3593:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr),
     /*  855361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855363 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855365 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855367 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855379 */     GIR_RootConstrainSelectedInstOperands,
     /*  855380 */     // GIR_Coverage, 7879,
     /*  855380 */     GIR_EraseRootFromParent_Done,
     /*  855381 */   // Label 13773: @855381
     /*  855381 */   GIM_Try, /*On fail goto*//*Label 13774*/ GIMT_Encode4(855443), // Rule ID 7880 //
     /*  855386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  855389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  855394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855400 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855403 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855406 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855420 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3593:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr),
     /*  855423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855425 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855427 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855429 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855441 */     GIR_RootConstrainSelectedInstOperands,
     /*  855442 */     // GIR_Coverage, 7880,
     /*  855442 */     GIR_EraseRootFromParent_Done,
     /*  855443 */   // Label 13774: @855443
     /*  855443 */   GIM_Try, /*On fail goto*//*Label 13775*/ GIMT_Encode4(855505), // Rule ID 7881 //
     /*  855448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  855451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  855456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855462 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855465 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855468 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855482 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3593:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr),
     /*  855485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855487 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855489 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855491 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855503 */     GIR_RootConstrainSelectedInstOperands,
     /*  855504 */     // GIR_Coverage, 7881,
     /*  855504 */     GIR_EraseRootFromParent_Done,
     /*  855505 */   // Label 13775: @855505
     /*  855505 */   GIM_Try, /*On fail goto*//*Label 13776*/ GIMT_Encode4(855567), // Rule ID 7882 //
     /*  855510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  855513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  855518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855530 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855544 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3593:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr),
     /*  855547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855549 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855551 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855553 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855565 */     GIR_RootConstrainSelectedInstOperands,
     /*  855566 */     // GIR_Coverage, 7882,
     /*  855566 */     GIR_EraseRootFromParent_Done,
     /*  855567 */   // Label 13776: @855567
     /*  855567 */   GIM_Try, /*On fail goto*//*Label 13777*/ GIMT_Encode4(855629), // Rule ID 7883 //
     /*  855572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  855575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  855580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855589 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855592 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855606 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3591:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr),
     /*  855609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855611 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855613 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855615 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855617 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855627 */     GIR_RootConstrainSelectedInstOperands,
     /*  855628 */     // GIR_Coverage, 7883,
     /*  855628 */     GIR_EraseRootFromParent_Done,
     /*  855629 */   // Label 13777: @855629
     /*  855629 */   GIM_Try, /*On fail goto*//*Label 13778*/ GIMT_Encode4(855691), // Rule ID 7884 //
     /*  855634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  855637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  855642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855651 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855654 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855668 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3591:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr),
     /*  855671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855673 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855675 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855677 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855689 */     GIR_RootConstrainSelectedInstOperands,
     /*  855690 */     // GIR_Coverage, 7884,
     /*  855690 */     GIR_EraseRootFromParent_Done,
     /*  855691 */   // Label 13778: @855691
     /*  855691 */   GIM_Try, /*On fail goto*//*Label 13779*/ GIMT_Encode4(855753), // Rule ID 7885 //
     /*  855696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  855699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  855704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855707 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855710 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855713 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855716 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855723 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855730 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3591:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr),
     /*  855733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855735 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855737 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855739 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855751 */     GIR_RootConstrainSelectedInstOperands,
     /*  855752 */     // GIR_Coverage, 7885,
     /*  855752 */     GIR_EraseRootFromParent_Done,
     /*  855753 */   // Label 13779: @855753
     /*  855753 */   GIM_Try, /*On fail goto*//*Label 13780*/ GIMT_Encode4(855815), // Rule ID 7886 //
     /*  855758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  855761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  855766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855775 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855778 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855792 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3591:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr),
     /*  855795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855797 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855799 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855801 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855813 */     GIR_RootConstrainSelectedInstOperands,
     /*  855814 */     // GIR_Coverage, 7886,
     /*  855814 */     GIR_EraseRootFromParent_Done,
     /*  855815 */   // Label 13780: @855815
     /*  855815 */   GIM_Try, /*On fail goto*//*Label 13781*/ GIMT_Encode4(855877), // Rule ID 7887 //
     /*  855820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  855823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  855828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855840 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855854 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3591:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr),
     /*  855857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855859 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855861 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855863 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855875 */     GIR_RootConstrainSelectedInstOperands,
     /*  855876 */     // GIR_Coverage, 7887,
     /*  855876 */     GIR_EraseRootFromParent_Done,
     /*  855877 */   // Label 13781: @855877
     /*  855877 */   GIM_Try, /*On fail goto*//*Label 13782*/ GIMT_Encode4(855939), // Rule ID 7888 //
     /*  855882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  855885 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  855890 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855893 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855896 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855899 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855902 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855909 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855916 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3590:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr),
     /*  855919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855921 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855923 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855925 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855937 */     GIR_RootConstrainSelectedInstOperands,
     /*  855938 */     // GIR_Coverage, 7888,
     /*  855938 */     GIR_EraseRootFromParent_Done,
     /*  855939 */   // Label 13782: @855939
     /*  855939 */   GIM_Try, /*On fail goto*//*Label 13783*/ GIMT_Encode4(856001), // Rule ID 7889 //
     /*  855944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  855947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  855952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  855955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  855958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  855961 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  855964 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  855967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  855971 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  855978 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3590:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  855978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr),
     /*  855981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  855983 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  855985 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  855987 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  855989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  855994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  855999 */     GIR_RootConstrainSelectedInstOperands,
     /*  856000 */     // GIR_Coverage, 7889,
     /*  856000 */     GIR_EraseRootFromParent_Done,
     /*  856001 */   // Label 13783: @856001
     /*  856001 */   GIM_Try, /*On fail goto*//*Label 13784*/ GIMT_Encode4(856063), // Rule ID 7890 //
     /*  856006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  856009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  856014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  856017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  856020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  856023 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  856026 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  856033 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  856040 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3590:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  856040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr),
     /*  856043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856045 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856047 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856049 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  856061 */     GIR_RootConstrainSelectedInstOperands,
     /*  856062 */     // GIR_Coverage, 7890,
     /*  856062 */     GIR_EraseRootFromParent_Done,
     /*  856063 */   // Label 13784: @856063
     /*  856063 */   GIM_Try, /*On fail goto*//*Label 13785*/ GIMT_Encode4(856125), // Rule ID 7891 //
     /*  856068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  856071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  856076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  856079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  856082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  856085 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  856088 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  856095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  856102 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3590:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  856102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr),
     /*  856105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856107 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856109 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856111 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  856123 */     GIR_RootConstrainSelectedInstOperands,
     /*  856124 */     // GIR_Coverage, 7891,
     /*  856124 */     GIR_EraseRootFromParent_Done,
     /*  856125 */   // Label 13785: @856125
     /*  856125 */   GIM_Try, /*On fail goto*//*Label 13786*/ GIMT_Encode4(856187), // Rule ID 7892 //
     /*  856130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  856133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  856138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  856141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  856144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  856147 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  856150 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  856157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  856164 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3590:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
     /*  856164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr),
     /*  856167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856169 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856171 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856173 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  856185 */     GIR_RootConstrainSelectedInstOperands,
     /*  856186 */     // GIR_Coverage, 7892,
     /*  856186 */     GIR_EraseRootFromParent_Done,
     /*  856187 */   // Label 13786: @856187
     /*  856187 */   GIM_Try, /*On fail goto*//*Label 13787*/ GIMT_Encode4(856261), // Rule ID 8008 //
     /*  856192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  856195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  856200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  856203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  856212 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  856219 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856226 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3589:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr),
     /*  856229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856234 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856239 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856241 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856259 */     GIR_RootConstrainSelectedInstOperands,
     /*  856260 */     // GIR_Coverage, 8008,
     /*  856260 */     GIR_EraseRootFromParent_Done,
     /*  856261 */   // Label 13787: @856261
     /*  856261 */   GIM_Try, /*On fail goto*//*Label 13788*/ GIMT_Encode4(856335), // Rule ID 8009 //
     /*  856266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  856269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  856274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  856277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856283 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  856286 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  856293 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856300 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3589:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr),
     /*  856303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856308 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856313 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856315 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856327 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856333 */     GIR_RootConstrainSelectedInstOperands,
     /*  856334 */     // GIR_Coverage, 8009,
     /*  856334 */     GIR_EraseRootFromParent_Done,
     /*  856335 */   // Label 13788: @856335
     /*  856335 */   GIM_Try, /*On fail goto*//*Label 13789*/ GIMT_Encode4(856409), // Rule ID 8010 //
     /*  856340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  856343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  856348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  856351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  856360 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  856367 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856374 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3589:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr),
     /*  856377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856382 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856387 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856389 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856407 */     GIR_RootConstrainSelectedInstOperands,
     /*  856408 */     // GIR_Coverage, 8010,
     /*  856408 */     GIR_EraseRootFromParent_Done,
     /*  856409 */   // Label 13789: @856409
     /*  856409 */   GIM_Try, /*On fail goto*//*Label 13790*/ GIMT_Encode4(856483), // Rule ID 8011 //
     /*  856414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  856417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  856422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  856425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856428 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856431 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  856434 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  856441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856448 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3589:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr),
     /*  856451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856456 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856461 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856463 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856465 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856470 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856481 */     GIR_RootConstrainSelectedInstOperands,
     /*  856482 */     // GIR_Coverage, 8011,
     /*  856482 */     GIR_EraseRootFromParent_Done,
     /*  856483 */   // Label 13790: @856483
     /*  856483 */   GIM_Try, /*On fail goto*//*Label 13791*/ GIMT_Encode4(856557), // Rule ID 8012 //
     /*  856488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  856491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
     /*  856496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  856499 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856505 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  856508 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  856515 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856522 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3589:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr),
     /*  856525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856530 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856535 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856537 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856552 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856555 */     GIR_RootConstrainSelectedInstOperands,
     /*  856556 */     // GIR_Coverage, 8012,
     /*  856556 */     GIR_EraseRootFromParent_Done,
     /*  856557 */   // Label 13791: @856557
     /*  856557 */   GIM_Try, /*On fail goto*//*Label 13792*/ GIMT_Encode4(856631), // Rule ID 8018 //
     /*  856562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  856565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  856570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  856573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  856582 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  856589 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856596 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3576:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr),
     /*  856599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856604 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856609 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856611 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856629 */     GIR_RootConstrainSelectedInstOperands,
     /*  856630 */     // GIR_Coverage, 8018,
     /*  856630 */     GIR_EraseRootFromParent_Done,
     /*  856631 */   // Label 13792: @856631
     /*  856631 */   GIM_Try, /*On fail goto*//*Label 13793*/ GIMT_Encode4(856705), // Rule ID 8019 //
     /*  856636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  856639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  856644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  856647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856653 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  856656 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  856663 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856670 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3576:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr),
     /*  856673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856678 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856683 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856685 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856703 */     GIR_RootConstrainSelectedInstOperands,
     /*  856704 */     // GIR_Coverage, 8019,
     /*  856704 */     GIR_EraseRootFromParent_Done,
     /*  856705 */   // Label 13793: @856705
     /*  856705 */   GIM_Try, /*On fail goto*//*Label 13794*/ GIMT_Encode4(856779), // Rule ID 8020 //
     /*  856710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  856713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  856718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  856721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  856730 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  856737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856744 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3576:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr),
     /*  856747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856749 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856752 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856757 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856759 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856777 */     GIR_RootConstrainSelectedInstOperands,
     /*  856778 */     // GIR_Coverage, 8020,
     /*  856778 */     GIR_EraseRootFromParent_Done,
     /*  856779 */   // Label 13794: @856779
     /*  856779 */   GIM_Try, /*On fail goto*//*Label 13795*/ GIMT_Encode4(856853), // Rule ID 8021 //
     /*  856784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  856787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  856792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  856795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856801 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  856804 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  856811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856818 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3576:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr),
     /*  856821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856826 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856831 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856833 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856851 */     GIR_RootConstrainSelectedInstOperands,
     /*  856852 */     // GIR_Coverage, 8021,
     /*  856852 */     GIR_EraseRootFromParent_Done,
     /*  856853 */   // Label 13795: @856853
     /*  856853 */   GIM_Try, /*On fail goto*//*Label 13796*/ GIMT_Encode4(856927), // Rule ID 8022 //
     /*  856858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  856861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
     /*  856866 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  856869 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  856872 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  856875 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  856878 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  856885 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856892 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3576:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr),
     /*  856895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856897 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856900 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856902 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  856905 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856907 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856919 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  856925 */     GIR_RootConstrainSelectedInstOperands,
     /*  856926 */     // GIR_Coverage, 8022,
     /*  856926 */     GIR_EraseRootFromParent_Done,
     /*  856927 */   // Label 13796: @856927
     /*  856927 */   GIM_Try, /*On fail goto*//*Label 13797*/ GIMT_Encode4(856989), // Rule ID 8038 //
     /*  856932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  856935 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  856940 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  856943 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  856946 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  856949 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  856952 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  856955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  856959 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  856966 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3594:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  856966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr),
     /*  856969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  856971 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  856973 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  856975 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  856977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  856982 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  856987 */     GIR_RootConstrainSelectedInstOperands,
     /*  856988 */     // GIR_Coverage, 8038,
     /*  856988 */     GIR_EraseRootFromParent_Done,
     /*  856989 */   // Label 13797: @856989
     /*  856989 */   GIM_Try, /*On fail goto*//*Label 13798*/ GIMT_Encode4(857051), // Rule ID 8039 //
     /*  856994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  856997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  857002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857008 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857011 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857014 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857021 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857028 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3594:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr),
     /*  857031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857033 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857035 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857037 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857049 */     GIR_RootConstrainSelectedInstOperands,
     /*  857050 */     // GIR_Coverage, 8039,
     /*  857050 */     GIR_EraseRootFromParent_Done,
     /*  857051 */   // Label 13798: @857051
     /*  857051 */   GIM_Try, /*On fail goto*//*Label 13799*/ GIMT_Encode4(857113), // Rule ID 8040 //
     /*  857056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  857059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  857064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857070 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857073 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857076 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857090 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3594:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr),
     /*  857093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857095 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857097 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857099 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857111 */     GIR_RootConstrainSelectedInstOperands,
     /*  857112 */     // GIR_Coverage, 8040,
     /*  857112 */     GIR_EraseRootFromParent_Done,
     /*  857113 */   // Label 13799: @857113
     /*  857113 */   GIM_Try, /*On fail goto*//*Label 13800*/ GIMT_Encode4(857175), // Rule ID 8041 //
     /*  857118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  857121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  857126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857135 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857138 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857152 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3594:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr),
     /*  857155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857157 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857159 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857161 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857173 */     GIR_RootConstrainSelectedInstOperands,
     /*  857174 */     // GIR_Coverage, 8041,
     /*  857174 */     GIR_EraseRootFromParent_Done,
     /*  857175 */   // Label 13800: @857175
     /*  857175 */   GIM_Try, /*On fail goto*//*Label 13801*/ GIMT_Encode4(857237), // Rule ID 8042 //
     /*  857180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  857183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
     /*  857188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857197 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857200 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857214 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3594:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr),
     /*  857217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857219 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857221 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857223 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857230 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857235 */     GIR_RootConstrainSelectedInstOperands,
     /*  857236 */     // GIR_Coverage, 8042,
     /*  857236 */     GIR_EraseRootFromParent_Done,
     /*  857237 */   // Label 13801: @857237
     /*  857237 */   GIM_Try, /*On fail goto*//*Label 13802*/ GIMT_Encode4(857299), // Rule ID 8043 //
     /*  857242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  857245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  857250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857259 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857262 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857276 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3593:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr),
     /*  857279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857281 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857283 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857285 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857297 */     GIR_RootConstrainSelectedInstOperands,
     /*  857298 */     // GIR_Coverage, 8043,
     /*  857298 */     GIR_EraseRootFromParent_Done,
     /*  857299 */   // Label 13802: @857299
     /*  857299 */   GIM_Try, /*On fail goto*//*Label 13803*/ GIMT_Encode4(857361), // Rule ID 8044 //
     /*  857304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  857307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  857312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857321 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857324 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857331 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857338 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3593:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr),
     /*  857341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857343 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857345 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857347 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857359 */     GIR_RootConstrainSelectedInstOperands,
     /*  857360 */     // GIR_Coverage, 8044,
     /*  857360 */     GIR_EraseRootFromParent_Done,
     /*  857361 */   // Label 13803: @857361
     /*  857361 */   GIM_Try, /*On fail goto*//*Label 13804*/ GIMT_Encode4(857423), // Rule ID 8045 //
     /*  857366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  857369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  857374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857386 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857400 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3593:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr),
     /*  857403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857405 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857407 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857409 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857416 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857421 */     GIR_RootConstrainSelectedInstOperands,
     /*  857422 */     // GIR_Coverage, 8045,
     /*  857422 */     GIR_EraseRootFromParent_Done,
     /*  857423 */   // Label 13804: @857423
     /*  857423 */   GIM_Try, /*On fail goto*//*Label 13805*/ GIMT_Encode4(857485), // Rule ID 8046 //
     /*  857428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  857431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  857436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857445 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857448 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857462 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3593:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr),
     /*  857465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857467 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857469 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857471 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857483 */     GIR_RootConstrainSelectedInstOperands,
     /*  857484 */     // GIR_Coverage, 8046,
     /*  857484 */     GIR_EraseRootFromParent_Done,
     /*  857485 */   // Label 13805: @857485
     /*  857485 */   GIM_Try, /*On fail goto*//*Label 13806*/ GIMT_Encode4(857547), // Rule ID 8047 //
     /*  857490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  857493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
     /*  857498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857507 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857510 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857524 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3593:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr),
     /*  857527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857529 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857533 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857545 */     GIR_RootConstrainSelectedInstOperands,
     /*  857546 */     // GIR_Coverage, 8047,
     /*  857546 */     GIR_EraseRootFromParent_Done,
     /*  857547 */   // Label 13806: @857547
     /*  857547 */   GIM_Try, /*On fail goto*//*Label 13807*/ GIMT_Encode4(857609), // Rule ID 8048 //
     /*  857552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  857555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  857560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857569 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857572 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857579 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857586 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3591:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr),
     /*  857589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857591 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857593 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857595 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857607 */     GIR_RootConstrainSelectedInstOperands,
     /*  857608 */     // GIR_Coverage, 8048,
     /*  857608 */     GIR_EraseRootFromParent_Done,
     /*  857609 */   // Label 13807: @857609
     /*  857609 */   GIM_Try, /*On fail goto*//*Label 13808*/ GIMT_Encode4(857671), // Rule ID 8049 //
     /*  857614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  857617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  857622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857631 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857634 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857648 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3591:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr),
     /*  857651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857653 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857655 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857657 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857669 */     GIR_RootConstrainSelectedInstOperands,
     /*  857670 */     // GIR_Coverage, 8049,
     /*  857670 */     GIR_EraseRootFromParent_Done,
     /*  857671 */   // Label 13808: @857671
     /*  857671 */   GIM_Try, /*On fail goto*//*Label 13809*/ GIMT_Encode4(857733), // Rule ID 8050 //
     /*  857676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  857679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  857684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857693 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857696 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857710 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3591:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr),
     /*  857713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857715 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857717 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857719 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857731 */     GIR_RootConstrainSelectedInstOperands,
     /*  857732 */     // GIR_Coverage, 8050,
     /*  857732 */     GIR_EraseRootFromParent_Done,
     /*  857733 */   // Label 13809: @857733
     /*  857733 */   GIM_Try, /*On fail goto*//*Label 13810*/ GIMT_Encode4(857795), // Rule ID 8051 //
     /*  857738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  857741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  857746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857752 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857755 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857758 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857772 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3591:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr),
     /*  857775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857777 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857781 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857788 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857793 */     GIR_RootConstrainSelectedInstOperands,
     /*  857794 */     // GIR_Coverage, 8051,
     /*  857794 */     GIR_EraseRootFromParent_Done,
     /*  857795 */   // Label 13810: @857795
     /*  857795 */   GIM_Try, /*On fail goto*//*Label 13811*/ GIMT_Encode4(857857), // Rule ID 8052 //
     /*  857800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  857803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
     /*  857808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857817 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857820 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857834 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3591:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr),
     /*  857837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857839 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857841 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857843 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857855 */     GIR_RootConstrainSelectedInstOperands,
     /*  857856 */     // GIR_Coverage, 8052,
     /*  857856 */     GIR_EraseRootFromParent_Done,
     /*  857857 */   // Label 13811: @857857
     /*  857857 */   GIM_Try, /*On fail goto*//*Label 13812*/ GIMT_Encode4(857919), // Rule ID 8053 //
     /*  857862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  857865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  857870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857879 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857882 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857889 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857896 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3590:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr),
     /*  857899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857901 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857903 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857905 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857907 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857917 */     GIR_RootConstrainSelectedInstOperands,
     /*  857918 */     // GIR_Coverage, 8053,
     /*  857918 */     GIR_EraseRootFromParent_Done,
     /*  857919 */   // Label 13812: @857919
     /*  857919 */   GIM_Try, /*On fail goto*//*Label 13813*/ GIMT_Encode4(857981), // Rule ID 8054 //
     /*  857924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  857927 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  857932 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857935 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  857938 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  857941 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  857944 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  857947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  857951 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  857958 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3590:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  857958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr),
     /*  857961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  857963 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  857965 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  857967 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  857969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  857974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  857979 */     GIR_RootConstrainSelectedInstOperands,
     /*  857980 */     // GIR_Coverage, 8054,
     /*  857980 */     GIR_EraseRootFromParent_Done,
     /*  857981 */   // Label 13813: @857981
     /*  857981 */   GIM_Try, /*On fail goto*//*Label 13814*/ GIMT_Encode4(858043), // Rule ID 8055 //
     /*  857986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  857989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  857994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  857997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  858000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  858003 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  858006 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  858009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  858013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  858020 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3590:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  858020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr),
     /*  858023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858025 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858027 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858029 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  858031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  858036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  858041 */     GIR_RootConstrainSelectedInstOperands,
     /*  858042 */     // GIR_Coverage, 8055,
     /*  858042 */     GIR_EraseRootFromParent_Done,
     /*  858043 */   // Label 13814: @858043
     /*  858043 */   GIM_Try, /*On fail goto*//*Label 13815*/ GIMT_Encode4(858105), // Rule ID 8056 //
     /*  858048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  858051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  858056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  858059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  858062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  858065 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  858068 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  858071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  858075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  858082 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3590:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  858082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr),
     /*  858085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858087 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858089 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858091 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  858093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  858098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  858103 */     GIR_RootConstrainSelectedInstOperands,
     /*  858104 */     // GIR_Coverage, 8056,
     /*  858104 */     GIR_EraseRootFromParent_Done,
     /*  858105 */   // Label 13815: @858105
     /*  858105 */   GIM_Try, /*On fail goto*//*Label 13816*/ GIMT_Encode4(858167), // Rule ID 8057 //
     /*  858110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  858113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
     /*  858118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  858121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  858124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  858127 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  858130 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  858133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  858137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  858144 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3590:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
     /*  858144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr),
     /*  858147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858149 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858151 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858153 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  858155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  858160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  858165 */     GIR_RootConstrainSelectedInstOperands,
     /*  858166 */     // GIR_Coverage, 8057,
     /*  858166 */     GIR_EraseRootFromParent_Done,
     /*  858167 */   // Label 13816: @858167
     /*  858167 */   GIM_Try, /*On fail goto*//*Label 13817*/ GIMT_Encode4(858239), // Rule ID 7648 //
     /*  858172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  858175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  858180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858189 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858203 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32),
     /*  858206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858211 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858216 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858223 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858225 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858237 */     GIR_RootConstrainSelectedInstOperands,
     /*  858238 */     // GIR_Coverage, 7648,
     /*  858238 */     GIR_EraseRootFromParent_Done,
     /*  858239 */   // Label 13817: @858239
     /*  858239 */   GIM_Try, /*On fail goto*//*Label 13818*/ GIMT_Encode4(858311), // Rule ID 7649 //
     /*  858244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  858247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  858252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858261 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858268 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858275 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32),
     /*  858278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858283 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858288 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858295 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858297 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858309 */     GIR_RootConstrainSelectedInstOperands,
     /*  858310 */     // GIR_Coverage, 7649,
     /*  858310 */     GIR_EraseRootFromParent_Done,
     /*  858311 */   // Label 13818: @858311
     /*  858311 */   GIM_Try, /*On fail goto*//*Label 13819*/ GIMT_Encode4(858383), // Rule ID 7650 //
     /*  858316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  858319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  858324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858333 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858347 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32),
     /*  858350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858352 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858355 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858360 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858367 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858381 */     GIR_RootConstrainSelectedInstOperands,
     /*  858382 */     // GIR_Coverage, 7650,
     /*  858382 */     GIR_EraseRootFromParent_Done,
     /*  858383 */   // Label 13819: @858383
     /*  858383 */   GIM_Try, /*On fail goto*//*Label 13820*/ GIMT_Encode4(858455), // Rule ID 7651 //
     /*  858388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  858391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  858396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858405 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858419 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32),
     /*  858422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858427 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858432 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858439 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858453 */     GIR_RootConstrainSelectedInstOperands,
     /*  858454 */     // GIR_Coverage, 7651,
     /*  858454 */     GIR_EraseRootFromParent_Done,
     /*  858455 */   // Label 13820: @858455
     /*  858455 */   GIM_Try, /*On fail goto*//*Label 13821*/ GIMT_Encode4(858527), // Rule ID 7652 //
     /*  858460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  858463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  858468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858484 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858491 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32),
     /*  858494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858499 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858504 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858511 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858525 */     GIR_RootConstrainSelectedInstOperands,
     /*  858526 */     // GIR_Coverage, 7652,
     /*  858526 */     GIR_EraseRootFromParent_Done,
     /*  858527 */   // Label 13821: @858527
     /*  858527 */   GIM_Try, /*On fail goto*//*Label 13822*/ GIMT_Encode4(858599), // Rule ID 7668 //
     /*  858532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  858535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  858540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858549 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858556 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858563 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  858563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32),
     /*  858566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858571 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858576 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858583 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858597 */     GIR_RootConstrainSelectedInstOperands,
     /*  858598 */     // GIR_Coverage, 7668,
     /*  858598 */     GIR_EraseRootFromParent_Done,
     /*  858599 */   // Label 13822: @858599
     /*  858599 */   GIM_Try, /*On fail goto*//*Label 13823*/ GIMT_Encode4(858671), // Rule ID 7669 //
     /*  858604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  858607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  858612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858621 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858635 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  858635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32),
     /*  858638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858643 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858648 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858655 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858663 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858669 */     GIR_RootConstrainSelectedInstOperands,
     /*  858670 */     // GIR_Coverage, 7669,
     /*  858670 */     GIR_EraseRootFromParent_Done,
     /*  858671 */   // Label 13823: @858671
     /*  858671 */   GIM_Try, /*On fail goto*//*Label 13824*/ GIMT_Encode4(858743), // Rule ID 7670 //
     /*  858676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  858679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  858684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858693 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858707 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  858707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32),
     /*  858710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858715 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858720 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858727 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858741 */     GIR_RootConstrainSelectedInstOperands,
     /*  858742 */     // GIR_Coverage, 7670,
     /*  858742 */     GIR_EraseRootFromParent_Done,
     /*  858743 */   // Label 13824: @858743
     /*  858743 */   GIM_Try, /*On fail goto*//*Label 13825*/ GIMT_Encode4(858815), // Rule ID 7671 //
     /*  858748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  858751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  858756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858765 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858779 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  858779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32),
     /*  858782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858787 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858792 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858799 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858813 */     GIR_RootConstrainSelectedInstOperands,
     /*  858814 */     // GIR_Coverage, 7671,
     /*  858814 */     GIR_EraseRootFromParent_Done,
     /*  858815 */   // Label 13825: @858815
     /*  858815 */   GIM_Try, /*On fail goto*//*Label 13826*/ GIMT_Encode4(858887), // Rule ID 7672 //
     /*  858820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  858823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  858828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858844 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858851 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  858851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32),
     /*  858854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858859 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858861 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858864 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858871 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858885 */     GIR_RootConstrainSelectedInstOperands,
     /*  858886 */     // GIR_Coverage, 7672,
     /*  858886 */     GIR_EraseRootFromParent_Done,
     /*  858887 */   // Label 13826: @858887
     /*  858887 */   GIM_Try, /*On fail goto*//*Label 13827*/ GIMT_Encode4(858959), // Rule ID 7673 //
     /*  858892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  858895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  858900 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858903 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858906 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858909 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858916 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858923 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32),
     /*  858926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  858928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858931 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  858933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  858936 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  858938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  858943 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  858945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  858957 */     GIR_RootConstrainSelectedInstOperands,
     /*  858958 */     // GIR_Coverage, 7673,
     /*  858958 */     GIR_EraseRootFromParent_Done,
     /*  858959 */   // Label 13827: @858959
     /*  858959 */   GIM_Try, /*On fail goto*//*Label 13828*/ GIMT_Encode4(859031), // Rule ID 7674 //
     /*  858964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  858967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  858972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  858975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  858978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  858981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  858984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  858988 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  858995 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  858995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32),
     /*  858998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859003 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859008 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859015 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859029 */     GIR_RootConstrainSelectedInstOperands,
     /*  859030 */     // GIR_Coverage, 7674,
     /*  859030 */     GIR_EraseRootFromParent_Done,
     /*  859031 */   // Label 13828: @859031
     /*  859031 */   GIM_Try, /*On fail goto*//*Label 13829*/ GIMT_Encode4(859103), // Rule ID 7675 //
     /*  859036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  859039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  859044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859050 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859053 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859067 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  859067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32),
     /*  859070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859072 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859075 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859080 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859082 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859087 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859101 */     GIR_RootConstrainSelectedInstOperands,
     /*  859102 */     // GIR_Coverage, 7675,
     /*  859102 */     GIR_EraseRootFromParent_Done,
     /*  859103 */   // Label 13829: @859103
     /*  859103 */   GIM_Try, /*On fail goto*//*Label 13830*/ GIMT_Encode4(859175), // Rule ID 7676 //
     /*  859108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  859111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  859116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859125 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859139 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  859139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32),
     /*  859142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859147 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859152 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859159 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859173 */     GIR_RootConstrainSelectedInstOperands,
     /*  859174 */     // GIR_Coverage, 7676,
     /*  859174 */     GIR_EraseRootFromParent_Done,
     /*  859175 */   // Label 13830: @859175
     /*  859175 */   GIM_Try, /*On fail goto*//*Label 13831*/ GIMT_Encode4(859247), // Rule ID 7677 //
     /*  859180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  859183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  859188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859197 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859204 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859211 */     // (intrinsic_wo_chain:{ *:[v16f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
     /*  859211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32),
     /*  859214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859216 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859219 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859224 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859231 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859245 */     GIR_RootConstrainSelectedInstOperands,
     /*  859246 */     // GIR_Coverage, 7677,
     /*  859246 */     GIR_EraseRootFromParent_Done,
     /*  859247 */   // Label 13831: @859247
     /*  859247 */   GIM_Try, /*On fail goto*//*Label 13832*/ GIMT_Encode4(859319), // Rule ID 7678 //
     /*  859252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  859255 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  859260 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859263 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859269 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859283 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  859283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32),
     /*  859286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859288 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859291 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859296 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859303 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859317 */     GIR_RootConstrainSelectedInstOperands,
     /*  859318 */     // GIR_Coverage, 7678,
     /*  859318 */     GIR_EraseRootFromParent_Done,
     /*  859319 */   // Label 13832: @859319
     /*  859319 */   GIM_Try, /*On fail goto*//*Label 13833*/ GIMT_Encode4(859391), // Rule ID 7679 //
     /*  859324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  859327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  859332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859341 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859348 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859355 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  859355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32),
     /*  859358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859363 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859368 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859375 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859389 */     GIR_RootConstrainSelectedInstOperands,
     /*  859390 */     // GIR_Coverage, 7679,
     /*  859390 */     GIR_EraseRootFromParent_Done,
     /*  859391 */   // Label 13833: @859391
     /*  859391 */   GIM_Try, /*On fail goto*//*Label 13834*/ GIMT_Encode4(859463), // Rule ID 7680 //
     /*  859396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  859399 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  859404 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859407 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859413 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859427 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  859427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32),
     /*  859430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859440 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859447 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859461 */     GIR_RootConstrainSelectedInstOperands,
     /*  859462 */     // GIR_Coverage, 7680,
     /*  859462 */     GIR_EraseRootFromParent_Done,
     /*  859463 */   // Label 13834: @859463
     /*  859463 */   GIM_Try, /*On fail goto*//*Label 13835*/ GIMT_Encode4(859535), // Rule ID 7681 //
     /*  859468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  859471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  859476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859485 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859492 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859499 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  859499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32),
     /*  859502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859507 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859512 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859519 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859533 */     GIR_RootConstrainSelectedInstOperands,
     /*  859534 */     // GIR_Coverage, 7681,
     /*  859534 */     GIR_EraseRootFromParent_Done,
     /*  859535 */   // Label 13835: @859535
     /*  859535 */   GIM_Try, /*On fail goto*//*Label 13836*/ GIMT_Encode4(859607), // Rule ID 7682 //
     /*  859540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  859543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  859548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16,
     /*  859551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859557 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16,
     /*  859560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  859564 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859571 */     // (intrinsic_wo_chain:{ *:[v16i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
     /*  859571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32),
     /*  859574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859579 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859584 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859591 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859605 */     GIR_RootConstrainSelectedInstOperands,
     /*  859606 */     // GIR_Coverage, 7682,
     /*  859606 */     GIR_EraseRootFromParent_Done,
     /*  859607 */   // Label 13836: @859607
     /*  859607 */   GIM_Try, /*On fail goto*//*Label 13837*/ GIMT_Encode4(859679), // Rule ID 7698 //
     /*  859612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  859615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  859620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  859623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859629 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  859632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  859636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859643 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  859643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64),
     /*  859646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859651 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859656 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859663 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859677 */     GIR_RootConstrainSelectedInstOperands,
     /*  859678 */     // GIR_Coverage, 7698,
     /*  859678 */     GIR_EraseRootFromParent_Done,
     /*  859679 */   // Label 13837: @859679
     /*  859679 */   GIM_Try, /*On fail goto*//*Label 13838*/ GIMT_Encode4(859751), // Rule ID 7699 //
     /*  859684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  859687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  859692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  859695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859701 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  859704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  859708 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859715 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  859715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64),
     /*  859718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859723 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859728 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859735 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859737 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859749 */     GIR_RootConstrainSelectedInstOperands,
     /*  859750 */     // GIR_Coverage, 7699,
     /*  859750 */     GIR_EraseRootFromParent_Done,
     /*  859751 */   // Label 13838: @859751
     /*  859751 */   GIM_Try, /*On fail goto*//*Label 13839*/ GIMT_Encode4(859823), // Rule ID 7700 //
     /*  859756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  859759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  859764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  859767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859770 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859773 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  859776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  859780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859787 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  859787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64),
     /*  859790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859795 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859800 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859807 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859821 */     GIR_RootConstrainSelectedInstOperands,
     /*  859822 */     // GIR_Coverage, 7700,
     /*  859822 */     GIR_EraseRootFromParent_Done,
     /*  859823 */   // Label 13839: @859823
     /*  859823 */   GIM_Try, /*On fail goto*//*Label 13840*/ GIMT_Encode4(859895), // Rule ID 7701 //
     /*  859828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  859831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  859836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  859839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859845 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  859848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  859852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859859 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  859859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64),
     /*  859862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859867 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859872 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859879 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859893 */     GIR_RootConstrainSelectedInstOperands,
     /*  859894 */     // GIR_Coverage, 7701,
     /*  859894 */     GIR_EraseRootFromParent_Done,
     /*  859895 */   // Label 13840: @859895
     /*  859895 */   GIM_Try, /*On fail goto*//*Label 13841*/ GIMT_Encode4(859967), // Rule ID 7702 //
     /*  859900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  859903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
     /*  859908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  859911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859917 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  859920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  859924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  859931 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3638:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  859931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64),
     /*  859934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  859936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859939 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  859941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  859944 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  859946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  859951 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  859953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  859965 */     GIR_RootConstrainSelectedInstOperands,
     /*  859966 */     // GIR_Coverage, 7702,
     /*  859966 */     GIR_EraseRootFromParent_Done,
     /*  859967 */   // Label 13841: @859967
     /*  859967 */   GIM_Try, /*On fail goto*//*Label 13842*/ GIMT_Encode4(860039), // Rule ID 7703 //
     /*  859972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  859975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  859980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  859983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  859986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  859989 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  859992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  859996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860003 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64),
     /*  860006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860011 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860016 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860023 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860037 */     GIR_RootConstrainSelectedInstOperands,
     /*  860038 */     // GIR_Coverage, 7703,
     /*  860038 */     GIR_EraseRootFromParent_Done,
     /*  860039 */   // Label 13842: @860039
     /*  860039 */   GIM_Try, /*On fail goto*//*Label 13843*/ GIMT_Encode4(860111), // Rule ID 7704 //
     /*  860044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  860047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  860052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860061 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860075 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64),
     /*  860078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860080 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860083 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860088 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860095 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860106 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860109 */     GIR_RootConstrainSelectedInstOperands,
     /*  860110 */     // GIR_Coverage, 7704,
     /*  860110 */     GIR_EraseRootFromParent_Done,
     /*  860111 */   // Label 13843: @860111
     /*  860111 */   GIM_Try, /*On fail goto*//*Label 13844*/ GIMT_Encode4(860183), // Rule ID 7705 //
     /*  860116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  860119 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  860124 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860127 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860130 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860133 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860140 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860147 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64),
     /*  860150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860152 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860155 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860157 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860160 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860162 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860167 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860172 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860181 */     GIR_RootConstrainSelectedInstOperands,
     /*  860182 */     // GIR_Coverage, 7705,
     /*  860182 */     GIR_EraseRootFromParent_Done,
     /*  860183 */   // Label 13844: @860183
     /*  860183 */   GIM_Try, /*On fail goto*//*Label 13845*/ GIMT_Encode4(860255), // Rule ID 7706 //
     /*  860188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  860191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  860196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860212 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860219 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64),
     /*  860222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860224 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860232 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860239 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860250 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860253 */     GIR_RootConstrainSelectedInstOperands,
     /*  860254 */     // GIR_Coverage, 7706,
     /*  860254 */     GIR_EraseRootFromParent_Done,
     /*  860255 */   // Label 13845: @860255
     /*  860255 */   GIM_Try, /*On fail goto*//*Label 13846*/ GIMT_Encode4(860327), // Rule ID 7707 //
     /*  860260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  860263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  860268 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860271 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860274 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860277 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860291 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64),
     /*  860294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860299 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860304 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860311 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860325 */     GIR_RootConstrainSelectedInstOperands,
     /*  860326 */     // GIR_Coverage, 7707,
     /*  860326 */     GIR_EraseRootFromParent_Done,
     /*  860327 */   // Label 13846: @860327
     /*  860327 */   GIM_Try, /*On fail goto*//*Label 13847*/ GIMT_Encode4(860399), // Rule ID 7708 //
     /*  860332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  860335 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  860340 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860343 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860346 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860349 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860363 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  860363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64),
     /*  860366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860368 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860371 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860376 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860383 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860397 */     GIR_RootConstrainSelectedInstOperands,
     /*  860398 */     // GIR_Coverage, 7708,
     /*  860398 */     GIR_EraseRootFromParent_Done,
     /*  860399 */   // Label 13847: @860399
     /*  860399 */   GIM_Try, /*On fail goto*//*Label 13848*/ GIMT_Encode4(860471), // Rule ID 7709 //
     /*  860404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  860407 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  860412 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860415 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860418 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860421 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860435 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  860435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64),
     /*  860438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860443 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860445 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860448 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860450 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860455 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860457 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860469 */     GIR_RootConstrainSelectedInstOperands,
     /*  860470 */     // GIR_Coverage, 7709,
     /*  860470 */     GIR_EraseRootFromParent_Done,
     /*  860471 */   // Label 13848: @860471
     /*  860471 */   GIM_Try, /*On fail goto*//*Label 13849*/ GIMT_Encode4(860543), // Rule ID 7710 //
     /*  860476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  860479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  860484 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860493 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860500 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860507 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  860507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64),
     /*  860510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860512 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860515 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860520 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860522 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860527 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860538 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860541 */     GIR_RootConstrainSelectedInstOperands,
     /*  860542 */     // GIR_Coverage, 7710,
     /*  860542 */     GIR_EraseRootFromParent_Done,
     /*  860543 */   // Label 13849: @860543
     /*  860543 */   GIM_Try, /*On fail goto*//*Label 13850*/ GIMT_Encode4(860615), // Rule ID 7711 //
     /*  860548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  860551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  860556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860565 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860579 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  860579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64),
     /*  860582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860587 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860589 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860592 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860599 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860613 */     GIR_RootConstrainSelectedInstOperands,
     /*  860614 */     // GIR_Coverage, 7711,
     /*  860614 */     GIR_EraseRootFromParent_Done,
     /*  860615 */   // Label 13850: @860615
     /*  860615 */   GIM_Try, /*On fail goto*//*Label 13851*/ GIMT_Encode4(860687), // Rule ID 7712 //
     /*  860620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  860623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
     /*  860628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860644 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860651 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3639:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
     /*  860651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64),
     /*  860654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860659 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860664 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860671 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860673 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860685 */     GIR_RootConstrainSelectedInstOperands,
     /*  860686 */     // GIR_Coverage, 7712,
     /*  860686 */     GIR_EraseRootFromParent_Done,
     /*  860687 */   // Label 13851: @860687
     /*  860687 */   GIM_Try, /*On fail goto*//*Label 13852*/ GIMT_Encode4(860759), // Rule ID 7713 //
     /*  860692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  860695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  860700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860709 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860716 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860723 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64),
     /*  860726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860731 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860736 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860743 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860745 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860751 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860757 */     GIR_RootConstrainSelectedInstOperands,
     /*  860758 */     // GIR_Coverage, 7713,
     /*  860758 */     GIR_EraseRootFromParent_Done,
     /*  860759 */   // Label 13852: @860759
     /*  860759 */   GIM_Try, /*On fail goto*//*Label 13853*/ GIMT_Encode4(860831), // Rule ID 7714 //
     /*  860764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  860767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  860772 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860775 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860778 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860781 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860795 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64),
     /*  860798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860803 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860808 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860815 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860820 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860829 */     GIR_RootConstrainSelectedInstOperands,
     /*  860830 */     // GIR_Coverage, 7714,
     /*  860830 */     GIR_EraseRootFromParent_Done,
     /*  860831 */   // Label 13853: @860831
     /*  860831 */   GIM_Try, /*On fail goto*//*Label 13854*/ GIMT_Encode4(860903), // Rule ID 7715 //
     /*  860836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  860839 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  860844 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860853 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860860 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860867 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64),
     /*  860870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860875 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860880 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860887 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860892 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860901 */     GIR_RootConstrainSelectedInstOperands,
     /*  860902 */     // GIR_Coverage, 7715,
     /*  860902 */     GIR_EraseRootFromParent_Done,
     /*  860903 */   // Label 13854: @860903
     /*  860903 */   GIM_Try, /*On fail goto*//*Label 13855*/ GIMT_Encode4(860975), // Rule ID 7716 //
     /*  860908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  860911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  860916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860919 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860922 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860925 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  860928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  860932 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  860939 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  860939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64),
     /*  860942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  860944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860947 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  860949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  860952 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  860954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  860959 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  860961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  860973 */     GIR_RootConstrainSelectedInstOperands,
     /*  860974 */     // GIR_Coverage, 7716,
     /*  860974 */     GIR_EraseRootFromParent_Done,
     /*  860975 */   // Label 13855: @860975
     /*  860975 */   GIM_Try, /*On fail goto*//*Label 13856*/ GIMT_Encode4(861047), // Rule ID 7717 //
     /*  860980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  860983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
     /*  860988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  860991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16,
     /*  860994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  860997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  861000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  861004 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
     /*  861011 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3631:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
     /*  861011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64),
     /*  861014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861016 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861019 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861024 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
     /*  861031 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861045 */     GIR_RootConstrainSelectedInstOperands,
     /*  861046 */     // GIR_Coverage, 7717,
     /*  861046 */     GIR_EraseRootFromParent_Done,
     /*  861047 */   // Label 13856: @861047
     /*  861047 */   GIM_Try, /*On fail goto*//*Label 13857*/ GIMT_Encode4(861115), // Rule ID 7758 //
     /*  861052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  861055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861060 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  861063 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  861066 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  861069 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  861072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  861076 */     // MIs[0] Operand 5
     /*  861076 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861087 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  861087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr),
     /*  861090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861095 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861100 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861105 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861113 */     GIR_RootConstrainSelectedInstOperands,
     /*  861114 */     // GIR_Coverage, 7758,
     /*  861114 */     GIR_EraseRootFromParent_Done,
     /*  861115 */   // Label 13857: @861115
     /*  861115 */   GIM_Try, /*On fail goto*//*Label 13858*/ GIMT_Encode4(861183), // Rule ID 7759 //
     /*  861120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  861123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  861131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  861134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  861137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  861140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  861144 */     // MIs[0] Operand 5
     /*  861144 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861155 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  861155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr),
     /*  861158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861163 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861168 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861173 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861181 */     GIR_RootConstrainSelectedInstOperands,
     /*  861182 */     // GIR_Coverage, 7759,
     /*  861182 */     GIR_EraseRootFromParent_Done,
     /*  861183 */   // Label 13858: @861183
     /*  861183 */   GIM_Try, /*On fail goto*//*Label 13859*/ GIMT_Encode4(861251), // Rule ID 7760 //
     /*  861188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  861191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  861199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  861202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  861205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  861208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  861212 */     // MIs[0] Operand 5
     /*  861212 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861223 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  861223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr),
     /*  861226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861231 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861236 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861241 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861249 */     GIR_RootConstrainSelectedInstOperands,
     /*  861250 */     // GIR_Coverage, 7760,
     /*  861250 */     GIR_EraseRootFromParent_Done,
     /*  861251 */   // Label 13859: @861251
     /*  861251 */   GIM_Try, /*On fail goto*//*Label 13860*/ GIMT_Encode4(861319), // Rule ID 7761 //
     /*  861256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  861259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  861267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  861270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  861273 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  861276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  861280 */     // MIs[0] Operand 5
     /*  861280 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861291 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  861291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr),
     /*  861294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861299 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861304 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861309 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861317 */     GIR_RootConstrainSelectedInstOperands,
     /*  861318 */     // GIR_Coverage, 7761,
     /*  861318 */     GIR_EraseRootFromParent_Done,
     /*  861319 */   // Label 13860: @861319
     /*  861319 */   GIM_Try, /*On fail goto*//*Label 13861*/ GIMT_Encode4(861387), // Rule ID 7762 //
     /*  861324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  861327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  861335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  861338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  861341 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  861344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  861348 */     // MIs[0] Operand 5
     /*  861348 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861359 */     // (intrinsic_wo_chain:{ *:[v8i16] } 3630:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
     /*  861359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr),
     /*  861362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861367 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861372 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861377 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861379 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861385 */     GIR_RootConstrainSelectedInstOperands,
     /*  861386 */     // GIR_Coverage, 7762,
     /*  861386 */     GIR_EraseRootFromParent_Done,
     /*  861387 */   // Label 13861: @861387
     /*  861387 */   GIM_Try, /*On fail goto*//*Label 13862*/ GIMT_Encode4(861455), // Rule ID 7923 //
     /*  861392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  861395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  861403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  861406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  861409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  861412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  861416 */     // MIs[0] Operand 5
     /*  861416 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861427 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  861427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr),
     /*  861430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861440 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861445 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861453 */     GIR_RootConstrainSelectedInstOperands,
     /*  861454 */     // GIR_Coverage, 7923,
     /*  861454 */     GIR_EraseRootFromParent_Done,
     /*  861455 */   // Label 13862: @861455
     /*  861455 */   GIM_Try, /*On fail goto*//*Label 13863*/ GIMT_Encode4(861523), // Rule ID 7924 //
     /*  861460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  861463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  861471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  861474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  861477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  861480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  861484 */     // MIs[0] Operand 5
     /*  861484 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861495 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  861495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr),
     /*  861498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861503 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861508 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861510 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861513 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861521 */     GIR_RootConstrainSelectedInstOperands,
     /*  861522 */     // GIR_Coverage, 7924,
     /*  861522 */     GIR_EraseRootFromParent_Done,
     /*  861523 */   // Label 13863: @861523
     /*  861523 */   GIM_Try, /*On fail goto*//*Label 13864*/ GIMT_Encode4(861591), // Rule ID 7925 //
     /*  861528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  861531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  861539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  861542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  861545 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  861548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  861552 */     // MIs[0] Operand 5
     /*  861552 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861563 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  861563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr),
     /*  861566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861571 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861576 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861581 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861589 */     GIR_RootConstrainSelectedInstOperands,
     /*  861590 */     // GIR_Coverage, 7925,
     /*  861590 */     GIR_EraseRootFromParent_Done,
     /*  861591 */   // Label 13864: @861591
     /*  861591 */   GIM_Try, /*On fail goto*//*Label 13865*/ GIMT_Encode4(861659), // Rule ID 7926 //
     /*  861596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  861599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  861607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  861610 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  861613 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  861616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  861620 */     // MIs[0] Operand 5
     /*  861620 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861631 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  861631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr),
     /*  861634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861639 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861644 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861649 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861657 */     GIR_RootConstrainSelectedInstOperands,
     /*  861658 */     // GIR_Coverage, 7926,
     /*  861658 */     GIR_EraseRootFromParent_Done,
     /*  861659 */   // Label 13865: @861659
     /*  861659 */   GIM_Try, /*On fail goto*//*Label 13866*/ GIMT_Encode4(861727), // Rule ID 7927 //
     /*  861664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  861667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
     /*  861672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  861675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  861678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  861681 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /*  861684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  861688 */     // MIs[0] Operand 5
     /*  861688 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
     /*  861699 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3630:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
     /*  861699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr),
     /*  861702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861707 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861712 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  861717 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  861719 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861725 */     GIR_RootConstrainSelectedInstOperands,
     /*  861726 */     // GIR_Coverage, 7927,
     /*  861726 */     GIR_EraseRootFromParent_Done,
     /*  861727 */   // Label 13866: @861727
     /*  861727 */   GIM_Try, /*On fail goto*//*Label 13867*/ GIMT_Encode4(861784), // Rule ID 8258 //
     /*  861732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  861735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  861740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  861743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  861746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  861749 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  861752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  861756 */     // MIs[0] src2_modifiers
     /*  861756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  861759 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2)  =>  (V_WMMA_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  861759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr),
     /*  861762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861764 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861766 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861768 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  861774 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  861776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861782 */     GIR_RootConstrainSelectedInstOperands,
     /*  861783 */     // GIR_Coverage, 8258,
     /*  861783 */     GIR_EraseRootFromParent_Done,
     /*  861784 */   // Label 13867: @861784
     /*  861784 */   GIM_Try, /*On fail goto*//*Label 13868*/ GIMT_Encode4(861841), // Rule ID 8259 //
     /*  861789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  861792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  861797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  861800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  861803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  861806 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  861809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  861813 */     // MIs[0] src2_modifiers
     /*  861813 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  861816 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2)  =>  (V_WMMA_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  861816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr),
     /*  861819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861821 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861823 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861825 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  861831 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  861833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861839 */     GIR_RootConstrainSelectedInstOperands,
     /*  861840 */     // GIR_Coverage, 8259,
     /*  861840 */     GIR_EraseRootFromParent_Done,
     /*  861841 */   // Label 13868: @861841
     /*  861841 */   GIM_Try, /*On fail goto*//*Label 13869*/ GIMT_Encode4(861898), // Rule ID 8260 //
     /*  861846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  861849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  861854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  861857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  861860 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  861863 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  861866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  861870 */     // MIs[0] src2_modifiers
     /*  861870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  861873 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2)  =>  (V_WMMA_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  861873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr),
     /*  861876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861878 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861880 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861882 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  861888 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  861890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861896 */     GIR_RootConstrainSelectedInstOperands,
     /*  861897 */     // GIR_Coverage, 8260,
     /*  861897 */     GIR_EraseRootFromParent_Done,
     /*  861898 */   // Label 13869: @861898
     /*  861898 */   GIM_Try, /*On fail goto*//*Label 13870*/ GIMT_Encode4(861955), // Rule ID 8261 //
     /*  861903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  861906 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  861911 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  861914 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  861917 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  861920 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  861923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  861927 */     // MIs[0] src2_modifiers
     /*  861927 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  861930 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2)  =>  (V_WMMA_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  861930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr),
     /*  861933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861935 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861937 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861939 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  861945 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  861947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  861953 */     GIR_RootConstrainSelectedInstOperands,
     /*  861954 */     // GIR_Coverage, 8261,
     /*  861954 */     GIR_EraseRootFromParent_Done,
     /*  861955 */   // Label 13870: @861955
     /*  861955 */   GIM_Try, /*On fail goto*//*Label 13871*/ GIMT_Encode4(862012), // Rule ID 8262 //
     /*  861960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  861963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_32x16x128_f4),
     /*  861968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  861971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  861974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  861977 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  861980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  861984 */     // MIs[0] src2_modifiers
     /*  861984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  861987 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3663:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2)  =>  (V_WMMA_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2)
     /*  861987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_32X16X128_F4_w32_twoaddr),
     /*  861990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  861992 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  861994 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  861996 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  862002 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  862004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862010 */     GIR_RootConstrainSelectedInstOperands,
     /*  862011 */     // GIR_Coverage, 8262,
     /*  862011 */     GIR_EraseRootFromParent_Done,
     /*  862012 */   // Label 13871: @862012
     /*  862012 */   GIM_Reject,
     /*  862013 */ // Label 13701: @862013
     /*  862013 */ GIM_Try, /*On fail goto*//*Label 13872*/ GIMT_Encode4(862568),
     /*  862018 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
     /*  862021 */   GIM_Try, /*On fail goto*//*Label 13873*/ GIMT_Encode4(862091), // Rule ID 7054 //
     /*  862026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  862029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
     /*  862034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  862037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  862040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  862044 */     // MIs[0] dpp_ctrl
     /*  862044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  862047 */     // MIs[0] row_mask
     /*  862047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862050 */     // MIs[0] bank_mask
     /*  862050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862053 */     // MIs[0] bound_ctrl
     /*  862053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862056 */     // (intrinsic_wo_chain:{ *:[i32] } 3328:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  862056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  862059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862061 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862063 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862065 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  862071 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  862077 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  862083 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  862089 */     GIR_RootConstrainSelectedInstOperands,
     /*  862090 */     // GIR_Coverage, 7054,
     /*  862090 */     GIR_EraseRootFromParent_Done,
     /*  862091 */   // Label 13873: @862091
     /*  862091 */   GIM_Try, /*On fail goto*//*Label 13874*/ GIMT_Encode4(862161), // Rule ID 28430 //
     /*  862096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  862099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
     /*  862104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  862107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  862110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  862114 */     // MIs[0] dpp_ctrl
     /*  862114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  862117 */     // MIs[0] row_mask
     /*  862117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862120 */     // MIs[0] bank_mask
     /*  862120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862123 */     // MIs[0] bound_ctrl
     /*  862123 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862126 */     // (intrinsic_wo_chain:{ *:[i64] } 3328:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  862126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  862129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862131 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862133 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862135 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  862141 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  862147 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  862153 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  862159 */     GIR_RootConstrainSelectedInstOperands,
     /*  862160 */     // GIR_Coverage, 28430,
     /*  862160 */     GIR_EraseRootFromParent_Done,
     /*  862161 */   // Label 13874: @862161
     /*  862161 */   GIM_Try, /*On fail goto*//*Label 13875*/ GIMT_Encode4(862231), // Rule ID 28431 //
     /*  862166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  862169 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
     /*  862174 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  862177 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  862180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  862184 */     // MIs[0] dpp_ctrl
     /*  862184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  862187 */     // MIs[0] row_mask
     /*  862187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862190 */     // MIs[0] bank_mask
     /*  862190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862193 */     // MIs[0] bound_ctrl
     /*  862193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862196 */     // (intrinsic_wo_chain:{ *:[i64] } 3328:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  862196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  862199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862201 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862203 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862205 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  862211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  862217 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  862223 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  862229 */     GIR_RootConstrainSelectedInstOperands,
     /*  862230 */     // GIR_Coverage, 28431,
     /*  862230 */     GIR_EraseRootFromParent_Done,
     /*  862231 */   // Label 13875: @862231
     /*  862231 */   GIM_Try, /*On fail goto*//*Label 13876*/ GIMT_Encode4(862301), // Rule ID 28432 //
     /*  862236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  862239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
     /*  862244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  862247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  862250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  862254 */     // MIs[0] dpp_ctrl
     /*  862254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  862257 */     // MIs[0] row_mask
     /*  862257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862260 */     // MIs[0] bank_mask
     /*  862260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862263 */     // MIs[0] bound_ctrl
     /*  862263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862266 */     // (intrinsic_wo_chain:{ *:[i64] } 3328:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  862266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  862269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862271 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862273 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862275 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  862281 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  862287 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  862293 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  862299 */     GIR_RootConstrainSelectedInstOperands,
     /*  862300 */     // GIR_Coverage, 28432,
     /*  862300 */     GIR_EraseRootFromParent_Done,
     /*  862301 */   // Label 13876: @862301
     /*  862301 */   GIM_Try, /*On fail goto*//*Label 13877*/ GIMT_Encode4(862371), // Rule ID 28433 //
     /*  862306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  862309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
     /*  862314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  862317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  862320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  862324 */     // MIs[0] dpp_ctrl
     /*  862324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  862327 */     // MIs[0] row_mask
     /*  862327 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862330 */     // MIs[0] bank_mask
     /*  862330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862333 */     // MIs[0] bound_ctrl
     /*  862333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862336 */     // (intrinsic_wo_chain:{ *:[i64] } 3328:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  862336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  862339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862341 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862343 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862345 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  862351 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  862357 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  862363 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  862369 */     GIR_RootConstrainSelectedInstOperands,
     /*  862370 */     // GIR_Coverage, 28433,
     /*  862370 */     GIR_EraseRootFromParent_Done,
     /*  862371 */   // Label 13877: @862371
     /*  862371 */   GIM_Try, /*On fail goto*//*Label 13878*/ GIMT_Encode4(862441), // Rule ID 28434 //
     /*  862376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  862379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
     /*  862384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  862387 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  862390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  862394 */     // MIs[0] dpp_ctrl
     /*  862394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  862397 */     // MIs[0] row_mask
     /*  862397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862400 */     // MIs[0] bank_mask
     /*  862400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862403 */     // MIs[0] bound_ctrl
     /*  862403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862406 */     // (intrinsic_wo_chain:{ *:[i64] } 3328:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  862406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  862409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862411 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862413 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /*  862415 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  862421 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  862427 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  862433 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  862439 */     GIR_RootConstrainSelectedInstOperands,
     /*  862440 */     // GIR_Coverage, 28434,
     /*  862440 */     GIR_EraseRootFromParent_Done,
     /*  862441 */   // Label 13878: @862441
     /*  862441 */   GIM_Try, /*On fail goto*//*Label 13879*/ GIMT_Encode4(862504), // Rule ID 7471 //
     /*  862446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  862449 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16_var),
     /*  862454 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  862457 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  862460 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  862463 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  862466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  862470 */     // MIs[0] fi
     /*  862470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862473 */     // MIs[0] bc
     /*  862473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862476 */     // (intrinsic_wo_chain:{ *:[i32] } 3348:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_VAR_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), VGPR_32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  862476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_VAR_B32_e64),
     /*  862479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862481 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  862487 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862489 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  862495 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  862497 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  862499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862502 */     GIR_RootConstrainSelectedInstOperands,
     /*  862503 */     // GIR_Coverage, 7471,
     /*  862503 */     GIR_EraseRootFromParent_Done,
     /*  862504 */   // Label 13879: @862504
     /*  862504 */   GIM_Try, /*On fail goto*//*Label 13880*/ GIMT_Encode4(862567), // Rule ID 7472 //
     /*  862509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
     /*  862512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16_var),
     /*  862517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  862520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  862523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  862526 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  862529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  862533 */     // MIs[0] fi
     /*  862533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  862536 */     // MIs[0] bc
     /*  862536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862539 */     // (intrinsic_wo_chain:{ *:[i32] } 3352:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_VAR_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), VGPR_32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  862539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_VAR_B32_e64),
     /*  862542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862544 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  862550 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862552 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  862558 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  862560 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  862562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862565 */     GIR_RootConstrainSelectedInstOperands,
     /*  862566 */     // GIR_Coverage, 7472,
     /*  862566 */     GIR_EraseRootFromParent_Done,
     /*  862567 */   // Label 13880: @862567
     /*  862567 */   GIM_Reject,
     /*  862568 */ // Label 13872: @862568
     /*  862568 */ GIM_Try, /*On fail goto*//*Label 13881*/ GIMT_Encode4(918249),
     /*  862573 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
     /*  862576 */   GIM_Try, /*On fail goto*//*Label 13882*/ GIMT_Encode4(862653), // Rule ID 8293 //
     /*  862581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  862584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  862589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  862592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  862595 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  862598 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  862601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  862605 */     // MIs[0] matrix_a_fmt
     /*  862605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  862608 */     // MIs[0] matrix_b_fmt
     /*  862608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862611 */     // MIs[0] src2_modifiers
     /*  862611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  862621 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  862621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  862624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862626 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862628 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  862630 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  862636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  862641 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  862643 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  862645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862651 */     GIR_RootConstrainSelectedInstOperands,
     /*  862652 */     // GIR_Coverage, 8293,
     /*  862652 */     GIR_EraseRootFromParent_Done,
     /*  862653 */   // Label 13882: @862653
     /*  862653 */   GIM_Try, /*On fail goto*//*Label 13883*/ GIMT_Encode4(862730), // Rule ID 8294 //
     /*  862658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  862661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  862666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  862669 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  862672 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  862675 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  862678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  862682 */     // MIs[0] matrix_a_fmt
     /*  862682 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  862685 */     // MIs[0] matrix_b_fmt
     /*  862685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862688 */     // MIs[0] src2_modifiers
     /*  862688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  862698 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  862698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  862701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862703 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862705 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  862707 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  862713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  862718 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  862720 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  862722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862728 */     GIR_RootConstrainSelectedInstOperands,
     /*  862729 */     // GIR_Coverage, 8294,
     /*  862729 */     GIR_EraseRootFromParent_Done,
     /*  862730 */   // Label 13883: @862730
     /*  862730 */   GIM_Try, /*On fail goto*//*Label 13884*/ GIMT_Encode4(862807), // Rule ID 8295 //
     /*  862735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  862738 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  862743 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  862746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  862749 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  862752 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  862755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  862759 */     // MIs[0] matrix_a_fmt
     /*  862759 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  862762 */     // MIs[0] matrix_b_fmt
     /*  862762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862765 */     // MIs[0] src2_modifiers
     /*  862765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862768 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  862775 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  862775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  862778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862780 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862782 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  862784 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  862790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  862795 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  862797 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  862799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862805 */     GIR_RootConstrainSelectedInstOperands,
     /*  862806 */     // GIR_Coverage, 8295,
     /*  862806 */     GIR_EraseRootFromParent_Done,
     /*  862807 */   // Label 13884: @862807
     /*  862807 */   GIM_Try, /*On fail goto*//*Label 13885*/ GIMT_Encode4(862884), // Rule ID 8296 //
     /*  862812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  862815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  862820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  862823 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  862826 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  862829 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  862832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  862836 */     // MIs[0] matrix_a_fmt
     /*  862836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  862839 */     // MIs[0] matrix_b_fmt
     /*  862839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862842 */     // MIs[0] src2_modifiers
     /*  862842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  862852 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  862852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  862855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862857 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862859 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  862861 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  862867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  862872 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  862874 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  862876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862882 */     GIR_RootConstrainSelectedInstOperands,
     /*  862883 */     // GIR_Coverage, 8296,
     /*  862883 */     GIR_EraseRootFromParent_Done,
     /*  862884 */   // Label 13885: @862884
     /*  862884 */   GIM_Try, /*On fail goto*//*Label 13886*/ GIMT_Encode4(862961), // Rule ID 8297 //
     /*  862889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  862892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  862897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  862900 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  862903 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  862906 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  862909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  862913 */     // MIs[0] matrix_a_fmt
     /*  862913 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  862916 */     // MIs[0] matrix_b_fmt
     /*  862916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862919 */     // MIs[0] src2_modifiers
     /*  862919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862922 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  862929 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  862929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  862932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  862934 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  862936 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  862938 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  862944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  862949 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  862951 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  862953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  862959 */     GIR_RootConstrainSelectedInstOperands,
     /*  862960 */     // GIR_Coverage, 8297,
     /*  862960 */     GIR_EraseRootFromParent_Done,
     /*  862961 */   // Label 13886: @862961
     /*  862961 */   GIM_Try, /*On fail goto*//*Label 13887*/ GIMT_Encode4(863038), // Rule ID 8323 //
     /*  862966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  862969 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  862974 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  862977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  862980 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  862983 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  862986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  862990 */     // MIs[0] matrix_a_fmt
     /*  862990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  862993 */     // MIs[0] matrix_b_fmt
     /*  862993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  862996 */     // MIs[0] src2_modifiers
     /*  862996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  862999 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863006 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  863009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863011 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863013 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863015 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863026 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863028 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863036 */     GIR_RootConstrainSelectedInstOperands,
     /*  863037 */     // GIR_Coverage, 8323,
     /*  863037 */     GIR_EraseRootFromParent_Done,
     /*  863038 */   // Label 13887: @863038
     /*  863038 */   GIM_Try, /*On fail goto*//*Label 13888*/ GIMT_Encode4(863115), // Rule ID 8324 //
     /*  863043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  863046 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863051 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863057 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  863060 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863067 */     // MIs[0] matrix_a_fmt
     /*  863067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863070 */     // MIs[0] matrix_b_fmt
     /*  863070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863073 */     // MIs[0] src2_modifiers
     /*  863073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863083 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  863086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863088 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863090 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863092 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863103 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863105 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863113 */     GIR_RootConstrainSelectedInstOperands,
     /*  863114 */     // GIR_Coverage, 8324,
     /*  863114 */     GIR_EraseRootFromParent_Done,
     /*  863115 */   // Label 13888: @863115
     /*  863115 */   GIM_Try, /*On fail goto*//*Label 13889*/ GIMT_Encode4(863192), // Rule ID 8325 //
     /*  863120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  863123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863134 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  863137 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863144 */     // MIs[0] matrix_a_fmt
     /*  863144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863147 */     // MIs[0] matrix_b_fmt
     /*  863147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863150 */     // MIs[0] src2_modifiers
     /*  863150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863160 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  863163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863165 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863167 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863169 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863180 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863182 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863184 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863190 */     GIR_RootConstrainSelectedInstOperands,
     /*  863191 */     // GIR_Coverage, 8325,
     /*  863191 */     GIR_EraseRootFromParent_Done,
     /*  863192 */   // Label 13889: @863192
     /*  863192 */   GIM_Try, /*On fail goto*//*Label 13890*/ GIMT_Encode4(863269), // Rule ID 8326 //
     /*  863197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  863200 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863205 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863211 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  863214 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863221 */     // MIs[0] matrix_a_fmt
     /*  863221 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863224 */     // MIs[0] matrix_b_fmt
     /*  863224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863227 */     // MIs[0] src2_modifiers
     /*  863227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863237 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  863240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863242 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863244 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863246 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863257 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863259 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863267 */     GIR_RootConstrainSelectedInstOperands,
     /*  863268 */     // GIR_Coverage, 8326,
     /*  863268 */     GIR_EraseRootFromParent_Done,
     /*  863269 */   // Label 13890: @863269
     /*  863269 */   GIM_Try, /*On fail goto*//*Label 13891*/ GIMT_Encode4(863346), // Rule ID 8327 //
     /*  863274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  863277 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863282 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863285 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863288 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  863291 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863298 */     // MIs[0] matrix_a_fmt
     /*  863298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863301 */     // MIs[0] matrix_b_fmt
     /*  863301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863304 */     // MIs[0] src2_modifiers
     /*  863304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863314 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  863317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863319 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863321 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863323 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863334 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863336 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863344 */     GIR_RootConstrainSelectedInstOperands,
     /*  863345 */     // GIR_Coverage, 8327,
     /*  863345 */     GIR_EraseRootFromParent_Done,
     /*  863346 */   // Label 13891: @863346
     /*  863346 */   GIM_Try, /*On fail goto*//*Label 13892*/ GIMT_Encode4(863423), // Rule ID 8353 //
     /*  863351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  863354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863365 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  863368 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863375 */     // MIs[0] matrix_a_fmt
     /*  863375 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863378 */     // MIs[0] matrix_b_fmt
     /*  863378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863381 */     // MIs[0] src2_modifiers
     /*  863381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863384 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863391 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  863394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863396 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863398 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863400 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863406 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863411 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863413 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863421 */     GIR_RootConstrainSelectedInstOperands,
     /*  863422 */     // GIR_Coverage, 8353,
     /*  863422 */     GIR_EraseRootFromParent_Done,
     /*  863423 */   // Label 13892: @863423
     /*  863423 */   GIM_Try, /*On fail goto*//*Label 13893*/ GIMT_Encode4(863500), // Rule ID 8354 //
     /*  863428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  863431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863442 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  863445 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863452 */     // MIs[0] matrix_a_fmt
     /*  863452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863455 */     // MIs[0] matrix_b_fmt
     /*  863455 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863458 */     // MIs[0] src2_modifiers
     /*  863458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863468 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  863471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863473 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863475 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863477 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863488 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863490 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863498 */     GIR_RootConstrainSelectedInstOperands,
     /*  863499 */     // GIR_Coverage, 8354,
     /*  863499 */     GIR_EraseRootFromParent_Done,
     /*  863500 */   // Label 13893: @863500
     /*  863500 */   GIM_Try, /*On fail goto*//*Label 13894*/ GIMT_Encode4(863577), // Rule ID 8355 //
     /*  863505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  863508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863519 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  863522 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863529 */     // MIs[0] matrix_a_fmt
     /*  863529 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863532 */     // MIs[0] matrix_b_fmt
     /*  863532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863535 */     // MIs[0] src2_modifiers
     /*  863535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863545 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  863548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863550 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863552 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863554 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863560 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863565 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863567 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863575 */     GIR_RootConstrainSelectedInstOperands,
     /*  863576 */     // GIR_Coverage, 8355,
     /*  863576 */     GIR_EraseRootFromParent_Done,
     /*  863577 */   // Label 13894: @863577
     /*  863577 */   GIM_Try, /*On fail goto*//*Label 13895*/ GIMT_Encode4(863654), // Rule ID 8356 //
     /*  863582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  863585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863596 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  863599 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863606 */     // MIs[0] matrix_a_fmt
     /*  863606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863609 */     // MIs[0] matrix_b_fmt
     /*  863609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863612 */     // MIs[0] src2_modifiers
     /*  863612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863615 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863622 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  863625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863627 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863629 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863631 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863642 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863644 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863652 */     GIR_RootConstrainSelectedInstOperands,
     /*  863653 */     // GIR_Coverage, 8356,
     /*  863653 */     GIR_EraseRootFromParent_Done,
     /*  863654 */   // Label 13895: @863654
     /*  863654 */   GIM_Try, /*On fail goto*//*Label 13896*/ GIMT_Encode4(863731), // Rule ID 8357 //
     /*  863659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  863662 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863667 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  863673 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  863676 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863683 */     // MIs[0] matrix_a_fmt
     /*  863683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863686 */     // MIs[0] matrix_b_fmt
     /*  863686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863689 */     // MIs[0] src2_modifiers
     /*  863689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863692 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863699 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  863702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863704 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863706 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863708 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863719 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863721 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863729 */     GIR_RootConstrainSelectedInstOperands,
     /*  863730 */     // GIR_Coverage, 8357,
     /*  863730 */     GIR_EraseRootFromParent_Done,
     /*  863731 */   // Label 13896: @863731
     /*  863731 */   GIM_Try, /*On fail goto*//*Label 13897*/ GIMT_Encode4(863808), // Rule ID 8383 //
     /*  863736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  863739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863747 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  863750 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  863753 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863760 */     // MIs[0] matrix_a_fmt
     /*  863760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863763 */     // MIs[0] matrix_b_fmt
     /*  863763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863766 */     // MIs[0] src2_modifiers
     /*  863766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863769 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863776 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  863779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863781 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863783 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863785 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863796 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863798 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863806 */     GIR_RootConstrainSelectedInstOperands,
     /*  863807 */     // GIR_Coverage, 8383,
     /*  863807 */     GIR_EraseRootFromParent_Done,
     /*  863808 */   // Label 13897: @863808
     /*  863808 */   GIM_Try, /*On fail goto*//*Label 13898*/ GIMT_Encode4(863885), // Rule ID 8384 //
     /*  863813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  863816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  863827 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  863830 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863837 */     // MIs[0] matrix_a_fmt
     /*  863837 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863840 */     // MIs[0] matrix_b_fmt
     /*  863840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863843 */     // MIs[0] src2_modifiers
     /*  863843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863846 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863853 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  863856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863858 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863860 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863862 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863873 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863875 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863877 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863883 */     GIR_RootConstrainSelectedInstOperands,
     /*  863884 */     // GIR_Coverage, 8384,
     /*  863884 */     GIR_EraseRootFromParent_Done,
     /*  863885 */   // Label 13898: @863885
     /*  863885 */   GIM_Try, /*On fail goto*//*Label 13899*/ GIMT_Encode4(863962), // Rule ID 8385 //
     /*  863890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  863893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863901 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  863904 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  863907 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863914 */     // MIs[0] matrix_a_fmt
     /*  863914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863917 */     // MIs[0] matrix_b_fmt
     /*  863917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863920 */     // MIs[0] src2_modifiers
     /*  863920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  863923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  863930 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  863930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  863933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  863935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  863937 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  863939 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  863945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  863950 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  863952 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  863954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  863960 */     GIR_RootConstrainSelectedInstOperands,
     /*  863961 */     // GIR_Coverage, 8385,
     /*  863961 */     GIR_EraseRootFromParent_Done,
     /*  863962 */   // Label 13899: @863962
     /*  863962 */   GIM_Try, /*On fail goto*//*Label 13900*/ GIMT_Encode4(864039), // Rule ID 8386 //
     /*  863967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  863970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  863975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  863978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  863981 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  863984 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  863987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  863991 */     // MIs[0] matrix_a_fmt
     /*  863991 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  863994 */     // MIs[0] matrix_b_fmt
     /*  863994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  863997 */     // MIs[0] src2_modifiers
     /*  863997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864000 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864007 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  864010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864012 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864014 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864016 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864027 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864029 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864037 */     GIR_RootConstrainSelectedInstOperands,
     /*  864038 */     // GIR_Coverage, 8386,
     /*  864038 */     GIR_EraseRootFromParent_Done,
     /*  864039 */   // Label 13900: @864039
     /*  864039 */   GIM_Try, /*On fail goto*//*Label 13901*/ GIMT_Encode4(864116), // Rule ID 8387 //
     /*  864044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  864047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864055 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864058 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  864061 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864068 */     // MIs[0] matrix_a_fmt
     /*  864068 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864071 */     // MIs[0] matrix_b_fmt
     /*  864071 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864074 */     // MIs[0] src2_modifiers
     /*  864074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864084 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  864087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864089 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864091 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864093 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864104 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864106 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864114 */     GIR_RootConstrainSelectedInstOperands,
     /*  864115 */     // GIR_Coverage, 8387,
     /*  864115 */     GIR_EraseRootFromParent_Done,
     /*  864116 */   // Label 13901: @864116
     /*  864116 */   GIM_Try, /*On fail goto*//*Label 13902*/ GIMT_Encode4(864193), // Rule ID 8413 //
     /*  864121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  864124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864135 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  864138 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864145 */     // MIs[0] matrix_a_fmt
     /*  864145 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864148 */     // MIs[0] matrix_b_fmt
     /*  864148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864151 */     // MIs[0] src2_modifiers
     /*  864151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864161 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  864164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864166 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864168 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864170 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864181 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864183 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864185 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864191 */     GIR_RootConstrainSelectedInstOperands,
     /*  864192 */     // GIR_Coverage, 8413,
     /*  864192 */     GIR_EraseRootFromParent_Done,
     /*  864193 */   // Label 13902: @864193
     /*  864193 */   GIM_Try, /*On fail goto*//*Label 13903*/ GIMT_Encode4(864270), // Rule ID 8414 //
     /*  864198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  864201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864212 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  864215 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864222 */     // MIs[0] matrix_a_fmt
     /*  864222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864225 */     // MIs[0] matrix_b_fmt
     /*  864225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864228 */     // MIs[0] src2_modifiers
     /*  864228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864231 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864238 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  864241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864243 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864245 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864247 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864258 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864260 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864268 */     GIR_RootConstrainSelectedInstOperands,
     /*  864269 */     // GIR_Coverage, 8414,
     /*  864269 */     GIR_EraseRootFromParent_Done,
     /*  864270 */   // Label 13903: @864270
     /*  864270 */   GIM_Try, /*On fail goto*//*Label 13904*/ GIMT_Encode4(864347), // Rule ID 8415 //
     /*  864275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  864278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864286 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864289 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  864292 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864299 */     // MIs[0] matrix_a_fmt
     /*  864299 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864302 */     // MIs[0] matrix_b_fmt
     /*  864302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864305 */     // MIs[0] src2_modifiers
     /*  864305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864308 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864315 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  864318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864320 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864322 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864324 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864335 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864337 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864345 */     GIR_RootConstrainSelectedInstOperands,
     /*  864346 */     // GIR_Coverage, 8415,
     /*  864346 */     GIR_EraseRootFromParent_Done,
     /*  864347 */   // Label 13904: @864347
     /*  864347 */   GIM_Try, /*On fail goto*//*Label 13905*/ GIMT_Encode4(864424), // Rule ID 8416 //
     /*  864352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  864355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864363 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864366 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  864369 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864376 */     // MIs[0] matrix_a_fmt
     /*  864376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864379 */     // MIs[0] matrix_b_fmt
     /*  864379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864382 */     // MIs[0] src2_modifiers
     /*  864382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864385 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864392 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  864395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864397 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864399 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864401 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864412 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864414 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864422 */     GIR_RootConstrainSelectedInstOperands,
     /*  864423 */     // GIR_Coverage, 8416,
     /*  864423 */     GIR_EraseRootFromParent_Done,
     /*  864424 */   // Label 13905: @864424
     /*  864424 */   GIM_Try, /*On fail goto*//*Label 13906*/ GIMT_Encode4(864501), // Rule ID 8417 //
     /*  864429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  864432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864440 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864443 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  864446 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864453 */     // MIs[0] matrix_a_fmt
     /*  864453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864456 */     // MIs[0] matrix_b_fmt
     /*  864456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864459 */     // MIs[0] src2_modifiers
     /*  864459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864469 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  864472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864474 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864476 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864478 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864489 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864491 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864499 */     GIR_RootConstrainSelectedInstOperands,
     /*  864500 */     // GIR_Coverage, 8417,
     /*  864500 */     GIR_EraseRootFromParent_Done,
     /*  864501 */   // Label 13906: @864501
     /*  864501 */   GIM_Try, /*On fail goto*//*Label 13907*/ GIMT_Encode4(864578), // Rule ID 8443 //
     /*  864506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  864509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864520 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  864523 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864530 */     // MIs[0] matrix_a_fmt
     /*  864530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864533 */     // MIs[0] matrix_b_fmt
     /*  864533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864536 */     // MIs[0] src2_modifiers
     /*  864536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864546 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  864549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864551 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864553 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864555 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864561 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864566 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864568 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864576 */     GIR_RootConstrainSelectedInstOperands,
     /*  864577 */     // GIR_Coverage, 8443,
     /*  864577 */     GIR_EraseRootFromParent_Done,
     /*  864578 */   // Label 13907: @864578
     /*  864578 */   GIM_Try, /*On fail goto*//*Label 13908*/ GIMT_Encode4(864655), // Rule ID 8444 //
     /*  864583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  864586 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864591 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864594 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864597 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  864600 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864603 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864607 */     // MIs[0] matrix_a_fmt
     /*  864607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864610 */     // MIs[0] matrix_b_fmt
     /*  864610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864613 */     // MIs[0] src2_modifiers
     /*  864613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864623 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  864626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864628 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864630 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864632 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864643 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864645 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864653 */     GIR_RootConstrainSelectedInstOperands,
     /*  864654 */     // GIR_Coverage, 8444,
     /*  864654 */     GIR_EraseRootFromParent_Done,
     /*  864655 */   // Label 13908: @864655
     /*  864655 */   GIM_Try, /*On fail goto*//*Label 13909*/ GIMT_Encode4(864732), // Rule ID 8445 //
     /*  864660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  864663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864674 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  864677 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864684 */     // MIs[0] matrix_a_fmt
     /*  864684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864687 */     // MIs[0] matrix_b_fmt
     /*  864687 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864690 */     // MIs[0] src2_modifiers
     /*  864690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864693 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864700 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  864703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864705 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864707 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864709 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864720 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864722 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864730 */     GIR_RootConstrainSelectedInstOperands,
     /*  864731 */     // GIR_Coverage, 8445,
     /*  864731 */     GIR_EraseRootFromParent_Done,
     /*  864732 */   // Label 13909: @864732
     /*  864732 */   GIM_Try, /*On fail goto*//*Label 13910*/ GIMT_Encode4(864809), // Rule ID 8446 //
     /*  864737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  864740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864751 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  864754 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864761 */     // MIs[0] matrix_a_fmt
     /*  864761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864764 */     // MIs[0] matrix_b_fmt
     /*  864764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864767 */     // MIs[0] src2_modifiers
     /*  864767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864777 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  864780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864782 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864784 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864786 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864797 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864799 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864807 */     GIR_RootConstrainSelectedInstOperands,
     /*  864808 */     // GIR_Coverage, 8446,
     /*  864808 */     GIR_EraseRootFromParent_Done,
     /*  864809 */   // Label 13910: @864809
     /*  864809 */   GIM_Try, /*On fail goto*//*Label 13911*/ GIMT_Encode4(864886), // Rule ID 8447 //
     /*  864814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  864817 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864822 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864825 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  864828 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  864831 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864838 */     // MIs[0] matrix_a_fmt
     /*  864838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864841 */     // MIs[0] matrix_b_fmt
     /*  864841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864844 */     // MIs[0] src2_modifiers
     /*  864844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864854 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  864857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864859 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864861 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864863 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864874 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864876 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864884 */     GIR_RootConstrainSelectedInstOperands,
     /*  864885 */     // GIR_Coverage, 8447,
     /*  864885 */     GIR_EraseRootFromParent_Done,
     /*  864886 */   // Label 13911: @864886
     /*  864886 */   GIM_Try, /*On fail goto*//*Label 13912*/ GIMT_Encode4(864963), // Rule ID 8473 //
     /*  864891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  864894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  864905 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  864908 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864915 */     // MIs[0] matrix_a_fmt
     /*  864915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864918 */     // MIs[0] matrix_b_fmt
     /*  864918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864921 */     // MIs[0] src2_modifiers
     /*  864921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  864924 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  864931 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  864931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  864934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  864936 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  864938 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  864940 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  864946 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  864951 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  864953 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  864955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  864961 */     GIR_RootConstrainSelectedInstOperands,
     /*  864962 */     // GIR_Coverage, 8473,
     /*  864962 */     GIR_EraseRootFromParent_Done,
     /*  864963 */   // Label 13912: @864963
     /*  864963 */   GIM_Try, /*On fail goto*//*Label 13913*/ GIMT_Encode4(865040), // Rule ID 8474 //
     /*  864968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  864971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  864976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  864979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  864982 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  864985 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  864988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  864992 */     // MIs[0] matrix_a_fmt
     /*  864992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  864995 */     // MIs[0] matrix_b_fmt
     /*  864995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  864998 */     // MIs[0] src2_modifiers
     /*  864998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865008 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  865011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865013 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865015 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865017 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865028 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865030 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865038 */     GIR_RootConstrainSelectedInstOperands,
     /*  865039 */     // GIR_Coverage, 8474,
     /*  865039 */     GIR_EraseRootFromParent_Done,
     /*  865040 */   // Label 13913: @865040
     /*  865040 */   GIM_Try, /*On fail goto*//*Label 13914*/ GIMT_Encode4(865117), // Rule ID 8475 //
     /*  865045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  865048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865059 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  865062 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865069 */     // MIs[0] matrix_a_fmt
     /*  865069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865072 */     // MIs[0] matrix_b_fmt
     /*  865072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865075 */     // MIs[0] src2_modifiers
     /*  865075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865078 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865085 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  865088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865090 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865092 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865094 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865100 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865105 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865107 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865115 */     GIR_RootConstrainSelectedInstOperands,
     /*  865116 */     // GIR_Coverage, 8475,
     /*  865116 */     GIR_EraseRootFromParent_Done,
     /*  865117 */   // Label 13914: @865117
     /*  865117 */   GIM_Try, /*On fail goto*//*Label 13915*/ GIMT_Encode4(865194), // Rule ID 8476 //
     /*  865122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  865125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865136 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  865139 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865146 */     // MIs[0] matrix_a_fmt
     /*  865146 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865149 */     // MIs[0] matrix_b_fmt
     /*  865149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865152 */     // MIs[0] src2_modifiers
     /*  865152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865155 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865162 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  865165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865167 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865169 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865171 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865182 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865184 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865186 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865192 */     GIR_RootConstrainSelectedInstOperands,
     /*  865193 */     // GIR_Coverage, 8476,
     /*  865193 */     GIR_EraseRootFromParent_Done,
     /*  865194 */   // Label 13915: @865194
     /*  865194 */   GIM_Try, /*On fail goto*//*Label 13916*/ GIMT_Encode4(865271), // Rule ID 8477 //
     /*  865199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  865202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865213 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  865216 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865223 */     // MIs[0] matrix_a_fmt
     /*  865223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865226 */     // MIs[0] matrix_b_fmt
     /*  865226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865229 */     // MIs[0] src2_modifiers
     /*  865229 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865239 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  865242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865244 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865246 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865248 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865259 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865261 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865263 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865269 */     GIR_RootConstrainSelectedInstOperands,
     /*  865270 */     // GIR_Coverage, 8477,
     /*  865270 */     GIR_EraseRootFromParent_Done,
     /*  865271 */   // Label 13916: @865271
     /*  865271 */   GIM_Try, /*On fail goto*//*Label 13917*/ GIMT_Encode4(865348), // Rule ID 8503 //
     /*  865276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  865279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865290 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  865293 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865300 */     // MIs[0] matrix_a_fmt
     /*  865300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865303 */     // MIs[0] matrix_b_fmt
     /*  865303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865306 */     // MIs[0] src2_modifiers
     /*  865306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865316 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  865319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865321 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865323 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865325 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865331 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865336 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865338 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865340 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865346 */     GIR_RootConstrainSelectedInstOperands,
     /*  865347 */     // GIR_Coverage, 8503,
     /*  865347 */     GIR_EraseRootFromParent_Done,
     /*  865348 */   // Label 13917: @865348
     /*  865348 */   GIM_Try, /*On fail goto*//*Label 13918*/ GIMT_Encode4(865425), // Rule ID 8504 //
     /*  865353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  865356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865367 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  865370 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865377 */     // MIs[0] matrix_a_fmt
     /*  865377 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865380 */     // MIs[0] matrix_b_fmt
     /*  865380 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865383 */     // MIs[0] src2_modifiers
     /*  865383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865393 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  865396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865398 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865400 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865402 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865413 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865415 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865423 */     GIR_RootConstrainSelectedInstOperands,
     /*  865424 */     // GIR_Coverage, 8504,
     /*  865424 */     GIR_EraseRootFromParent_Done,
     /*  865425 */   // Label 13918: @865425
     /*  865425 */   GIM_Try, /*On fail goto*//*Label 13919*/ GIMT_Encode4(865502), // Rule ID 8505 //
     /*  865430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  865433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865444 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  865447 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865454 */     // MIs[0] matrix_a_fmt
     /*  865454 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865457 */     // MIs[0] matrix_b_fmt
     /*  865457 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865460 */     // MIs[0] src2_modifiers
     /*  865460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865463 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865470 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  865473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865475 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865477 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865479 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865485 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865490 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865492 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865500 */     GIR_RootConstrainSelectedInstOperands,
     /*  865501 */     // GIR_Coverage, 8505,
     /*  865501 */     GIR_EraseRootFromParent_Done,
     /*  865502 */   // Label 13919: @865502
     /*  865502 */   GIM_Try, /*On fail goto*//*Label 13920*/ GIMT_Encode4(865579), // Rule ID 8506 //
     /*  865507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  865510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865521 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  865524 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865531 */     // MIs[0] matrix_a_fmt
     /*  865531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865534 */     // MIs[0] matrix_b_fmt
     /*  865534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865537 */     // MIs[0] src2_modifiers
     /*  865537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865547 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  865550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865552 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865554 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865556 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865567 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865569 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865577 */     GIR_RootConstrainSelectedInstOperands,
     /*  865578 */     // GIR_Coverage, 8506,
     /*  865578 */     GIR_EraseRootFromParent_Done,
     /*  865579 */   // Label 13920: @865579
     /*  865579 */   GIM_Try, /*On fail goto*//*Label 13921*/ GIMT_Encode4(865656), // Rule ID 8507 //
     /*  865584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  865587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865598 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  865601 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865608 */     // MIs[0] matrix_a_fmt
     /*  865608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865611 */     // MIs[0] matrix_b_fmt
     /*  865611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865614 */     // MIs[0] src2_modifiers
     /*  865614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865624 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  865627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865629 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865631 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865633 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865644 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865646 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865654 */     GIR_RootConstrainSelectedInstOperands,
     /*  865655 */     // GIR_Coverage, 8507,
     /*  865655 */     GIR_EraseRootFromParent_Done,
     /*  865656 */   // Label 13921: @865656
     /*  865656 */   GIM_Try, /*On fail goto*//*Label 13922*/ GIMT_Encode4(865733), // Rule ID 8533 //
     /*  865661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  865664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865675 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  865678 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865685 */     // MIs[0] matrix_a_fmt
     /*  865685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865688 */     // MIs[0] matrix_b_fmt
     /*  865688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865691 */     // MIs[0] src2_modifiers
     /*  865691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865694 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865701 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  865704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865706 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865708 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865710 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865721 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865723 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865731 */     GIR_RootConstrainSelectedInstOperands,
     /*  865732 */     // GIR_Coverage, 8533,
     /*  865732 */     GIR_EraseRootFromParent_Done,
     /*  865733 */   // Label 13922: @865733
     /*  865733 */   GIM_Try, /*On fail goto*//*Label 13923*/ GIMT_Encode4(865810), // Rule ID 8534 //
     /*  865738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  865741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865752 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  865755 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865762 */     // MIs[0] matrix_a_fmt
     /*  865762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865765 */     // MIs[0] matrix_b_fmt
     /*  865765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865768 */     // MIs[0] src2_modifiers
     /*  865768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865771 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865778 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  865781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865783 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865785 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865787 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865798 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865800 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865808 */     GIR_RootConstrainSelectedInstOperands,
     /*  865809 */     // GIR_Coverage, 8534,
     /*  865809 */     GIR_EraseRootFromParent_Done,
     /*  865810 */   // Label 13923: @865810
     /*  865810 */   GIM_Try, /*On fail goto*//*Label 13924*/ GIMT_Encode4(865887), // Rule ID 8535 //
     /*  865815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  865818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865829 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  865832 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865839 */     // MIs[0] matrix_a_fmt
     /*  865839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865842 */     // MIs[0] matrix_b_fmt
     /*  865842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865845 */     // MIs[0] src2_modifiers
     /*  865845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865855 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  865858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865860 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865862 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865864 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865875 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865877 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865885 */     GIR_RootConstrainSelectedInstOperands,
     /*  865886 */     // GIR_Coverage, 8535,
     /*  865886 */     GIR_EraseRootFromParent_Done,
     /*  865887 */   // Label 13924: @865887
     /*  865887 */   GIM_Try, /*On fail goto*//*Label 13925*/ GIMT_Encode4(865964), // Rule ID 8536 //
     /*  865892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  865895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865900 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865903 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865906 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  865909 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865916 */     // MIs[0] matrix_a_fmt
     /*  865916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865919 */     // MIs[0] matrix_b_fmt
     /*  865919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865922 */     // MIs[0] src2_modifiers
     /*  865922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  865925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  865932 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  865932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  865935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  865937 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  865939 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  865941 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  865947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  865952 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  865954 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  865956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  865962 */     GIR_RootConstrainSelectedInstOperands,
     /*  865963 */     // GIR_Coverage, 8536,
     /*  865963 */     GIR_EraseRootFromParent_Done,
     /*  865964 */   // Label 13925: @865964
     /*  865964 */   GIM_Try, /*On fail goto*//*Label 13926*/ GIMT_Encode4(866041), // Rule ID 8537 //
     /*  865969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  865972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  865977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  865980 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  865983 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  865986 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  865989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  865993 */     // MIs[0] matrix_a_fmt
     /*  865993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  865996 */     // MIs[0] matrix_b_fmt
     /*  865996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  865999 */     // MIs[0] src2_modifiers
     /*  865999 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866009 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  866009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  866012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866014 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  866016 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  866018 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866029 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  866031 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  866033 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866039 */     GIR_RootConstrainSelectedInstOperands,
     /*  866040 */     // GIR_Coverage, 8537,
     /*  866040 */     GIR_EraseRootFromParent_Done,
     /*  866041 */   // Label 13926: @866041
     /*  866041 */   GIM_Try, /*On fail goto*//*Label 13927*/ GIMT_Encode4(866118), // Rule ID 8073 //
     /*  866046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  866049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  866054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866063 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866070 */     // MIs[0] src2_modifiers
     /*  866070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866073 */     // MIs[0] matrix_a_reuse
     /*  866073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866076 */     // MIs[0] matrix_b_reuse
     /*  866076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866079 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866086 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr),
     /*  866089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866091 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866093 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866095 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866106 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866108 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866116 */     GIR_RootConstrainSelectedInstOperands,
     /*  866117 */     // GIR_Coverage, 8073,
     /*  866117 */     GIR_EraseRootFromParent_Done,
     /*  866118 */   // Label 13927: @866118
     /*  866118 */   GIM_Try, /*On fail goto*//*Label 13928*/ GIMT_Encode4(866195), // Rule ID 8074 //
     /*  866123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  866126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  866131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866140 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866147 */     // MIs[0] src2_modifiers
     /*  866147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866150 */     // MIs[0] matrix_a_reuse
     /*  866150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866153 */     // MIs[0] matrix_b_reuse
     /*  866153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866156 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866163 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr),
     /*  866166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866168 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866170 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866172 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866183 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866185 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866193 */     GIR_RootConstrainSelectedInstOperands,
     /*  866194 */     // GIR_Coverage, 8074,
     /*  866194 */     GIR_EraseRootFromParent_Done,
     /*  866195 */   // Label 13928: @866195
     /*  866195 */   GIM_Try, /*On fail goto*//*Label 13929*/ GIMT_Encode4(866272), // Rule ID 8075 //
     /*  866200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  866203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  866208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866217 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866224 */     // MIs[0] src2_modifiers
     /*  866224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866227 */     // MIs[0] matrix_a_reuse
     /*  866227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866230 */     // MIs[0] matrix_b_reuse
     /*  866230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866233 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866240 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr),
     /*  866243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866245 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866247 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866249 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866260 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866262 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866270 */     GIR_RootConstrainSelectedInstOperands,
     /*  866271 */     // GIR_Coverage, 8075,
     /*  866271 */     GIR_EraseRootFromParent_Done,
     /*  866272 */   // Label 13929: @866272
     /*  866272 */   GIM_Try, /*On fail goto*//*Label 13930*/ GIMT_Encode4(866349), // Rule ID 8076 //
     /*  866277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  866280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  866285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866294 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866301 */     // MIs[0] src2_modifiers
     /*  866301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866304 */     // MIs[0] matrix_a_reuse
     /*  866304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866307 */     // MIs[0] matrix_b_reuse
     /*  866307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866310 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866317 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr),
     /*  866320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866322 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866324 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866326 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866337 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866339 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866347 */     GIR_RootConstrainSelectedInstOperands,
     /*  866348 */     // GIR_Coverage, 8076,
     /*  866348 */     GIR_EraseRootFromParent_Done,
     /*  866349 */   // Label 13930: @866349
     /*  866349 */   GIM_Try, /*On fail goto*//*Label 13931*/ GIMT_Encode4(866426), // Rule ID 8077 //
     /*  866354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  866357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  866362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866371 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866378 */     // MIs[0] src2_modifiers
     /*  866378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866381 */     // MIs[0] matrix_a_reuse
     /*  866381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866384 */     // MIs[0] matrix_b_reuse
     /*  866384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866387 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866394 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr),
     /*  866397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866399 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866401 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866403 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866414 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866416 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866424 */     GIR_RootConstrainSelectedInstOperands,
     /*  866425 */     // GIR_Coverage, 8077,
     /*  866425 */     GIR_EraseRootFromParent_Done,
     /*  866426 */   // Label 13931: @866426
     /*  866426 */   GIM_Try, /*On fail goto*//*Label 13932*/ GIMT_Encode4(866503), // Rule ID 8083 //
     /*  866431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  866434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  866439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866448 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866455 */     // MIs[0] src2_modifiers
     /*  866455 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866458 */     // MIs[0] matrix_a_reuse
     /*  866458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866461 */     // MIs[0] matrix_b_reuse
     /*  866461 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866471 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr),
     /*  866474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866476 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866478 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866480 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866486 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866491 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866493 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866495 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866501 */     GIR_RootConstrainSelectedInstOperands,
     /*  866502 */     // GIR_Coverage, 8083,
     /*  866502 */     GIR_EraseRootFromParent_Done,
     /*  866503 */   // Label 13932: @866503
     /*  866503 */   GIM_Try, /*On fail goto*//*Label 13933*/ GIMT_Encode4(866580), // Rule ID 8084 //
     /*  866508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  866511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  866516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866525 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866532 */     // MIs[0] src2_modifiers
     /*  866532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866535 */     // MIs[0] matrix_a_reuse
     /*  866535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866538 */     // MIs[0] matrix_b_reuse
     /*  866538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866541 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866548 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr),
     /*  866551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866553 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866555 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866557 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866568 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866570 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866572 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866578 */     GIR_RootConstrainSelectedInstOperands,
     /*  866579 */     // GIR_Coverage, 8084,
     /*  866579 */     GIR_EraseRootFromParent_Done,
     /*  866580 */   // Label 13933: @866580
     /*  866580 */   GIM_Try, /*On fail goto*//*Label 13934*/ GIMT_Encode4(866657), // Rule ID 8085 //
     /*  866585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  866588 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  866593 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866596 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866599 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866602 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866609 */     // MIs[0] src2_modifiers
     /*  866609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866612 */     // MIs[0] matrix_a_reuse
     /*  866612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866615 */     // MIs[0] matrix_b_reuse
     /*  866615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866618 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866625 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr),
     /*  866628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866630 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866632 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866634 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866645 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866647 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866655 */     GIR_RootConstrainSelectedInstOperands,
     /*  866656 */     // GIR_Coverage, 8085,
     /*  866656 */     GIR_EraseRootFromParent_Done,
     /*  866657 */   // Label 13934: @866657
     /*  866657 */   GIM_Try, /*On fail goto*//*Label 13935*/ GIMT_Encode4(866734), // Rule ID 8086 //
     /*  866662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  866665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  866670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866679 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866686 */     // MIs[0] src2_modifiers
     /*  866686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866689 */     // MIs[0] matrix_a_reuse
     /*  866689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866692 */     // MIs[0] matrix_b_reuse
     /*  866692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866695 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866702 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr),
     /*  866705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866707 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866709 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866711 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866717 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866722 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866724 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866732 */     GIR_RootConstrainSelectedInstOperands,
     /*  866733 */     // GIR_Coverage, 8086,
     /*  866733 */     GIR_EraseRootFromParent_Done,
     /*  866734 */   // Label 13935: @866734
     /*  866734 */   GIM_Try, /*On fail goto*//*Label 13936*/ GIMT_Encode4(866811), // Rule ID 8087 //
     /*  866739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  866742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  866747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866756 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866763 */     // MIs[0] src2_modifiers
     /*  866763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866766 */     // MIs[0] matrix_a_reuse
     /*  866766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866769 */     // MIs[0] matrix_b_reuse
     /*  866769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866779 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr),
     /*  866782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866784 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866786 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866788 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866799 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866801 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866809 */     GIR_RootConstrainSelectedInstOperands,
     /*  866810 */     // GIR_Coverage, 8087,
     /*  866810 */     GIR_EraseRootFromParent_Done,
     /*  866811 */   // Label 13936: @866811
     /*  866811 */   GIM_Try, /*On fail goto*//*Label 13937*/ GIMT_Encode4(866888), // Rule ID 8093 //
     /*  866816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  866819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  866824 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866827 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866830 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866833 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866840 */     // MIs[0] src2_modifiers
     /*  866840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866843 */     // MIs[0] matrix_a_reuse
     /*  866843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866846 */     // MIs[0] matrix_b_reuse
     /*  866846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866856 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr),
     /*  866859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866861 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866863 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866865 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866876 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866878 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866886 */     GIR_RootConstrainSelectedInstOperands,
     /*  866887 */     // GIR_Coverage, 8093,
     /*  866887 */     GIR_EraseRootFromParent_Done,
     /*  866888 */   // Label 13937: @866888
     /*  866888 */   GIM_Try, /*On fail goto*//*Label 13938*/ GIMT_Encode4(866965), // Rule ID 8094 //
     /*  866893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  866896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  866901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866910 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866917 */     // MIs[0] src2_modifiers
     /*  866917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866920 */     // MIs[0] matrix_a_reuse
     /*  866920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  866923 */     // MIs[0] matrix_b_reuse
     /*  866923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  866926 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  866933 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  866933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr),
     /*  866936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  866938 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  866940 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  866942 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  866948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  866953 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  866955 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  866957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  866963 */     GIR_RootConstrainSelectedInstOperands,
     /*  866964 */     // GIR_Coverage, 8094,
     /*  866964 */     GIR_EraseRootFromParent_Done,
     /*  866965 */   // Label 13938: @866965
     /*  866965 */   GIM_Try, /*On fail goto*//*Label 13939*/ GIMT_Encode4(867042), // Rule ID 8095 //
     /*  866970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  866973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  866978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  866981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  866984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  866987 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  866990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  866994 */     // MIs[0] src2_modifiers
     /*  866994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  866997 */     // MIs[0] matrix_a_reuse
     /*  866997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867000 */     // MIs[0] matrix_b_reuse
     /*  867000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867010 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr),
     /*  867013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867015 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867017 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867019 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867030 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867032 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867040 */     GIR_RootConstrainSelectedInstOperands,
     /*  867041 */     // GIR_Coverage, 8095,
     /*  867041 */     GIR_EraseRootFromParent_Done,
     /*  867042 */   // Label 13939: @867042
     /*  867042 */   GIM_Try, /*On fail goto*//*Label 13940*/ GIMT_Encode4(867119), // Rule ID 8096 //
     /*  867047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  867050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  867055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867058 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867061 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867064 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867071 */     // MIs[0] src2_modifiers
     /*  867071 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867074 */     // MIs[0] matrix_a_reuse
     /*  867074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867077 */     // MIs[0] matrix_b_reuse
     /*  867077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867087 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr),
     /*  867090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867092 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867094 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867096 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867107 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867109 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867117 */     GIR_RootConstrainSelectedInstOperands,
     /*  867118 */     // GIR_Coverage, 8096,
     /*  867118 */     GIR_EraseRootFromParent_Done,
     /*  867119 */   // Label 13940: @867119
     /*  867119 */   GIM_Try, /*On fail goto*//*Label 13941*/ GIMT_Encode4(867196), // Rule ID 8097 //
     /*  867124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  867127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  867132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867141 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867148 */     // MIs[0] src2_modifiers
     /*  867148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867151 */     // MIs[0] matrix_a_reuse
     /*  867151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867154 */     // MIs[0] matrix_b_reuse
     /*  867154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867164 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr),
     /*  867167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867169 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867171 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867173 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867184 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867186 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867188 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867194 */     GIR_RootConstrainSelectedInstOperands,
     /*  867195 */     // GIR_Coverage, 8097,
     /*  867195 */     GIR_EraseRootFromParent_Done,
     /*  867196 */   // Label 13941: @867196
     /*  867196 */   GIM_Try, /*On fail goto*//*Label 13942*/ GIMT_Encode4(867273), // Rule ID 8103 //
     /*  867201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  867204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  867209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867218 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867225 */     // MIs[0] src2_modifiers
     /*  867225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867228 */     // MIs[0] matrix_a_reuse
     /*  867228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867231 */     // MIs[0] matrix_b_reuse
     /*  867231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867241 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr),
     /*  867244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867246 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867248 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867250 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867261 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867263 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867271 */     GIR_RootConstrainSelectedInstOperands,
     /*  867272 */     // GIR_Coverage, 8103,
     /*  867272 */     GIR_EraseRootFromParent_Done,
     /*  867273 */   // Label 13942: @867273
     /*  867273 */   GIM_Try, /*On fail goto*//*Label 13943*/ GIMT_Encode4(867350), // Rule ID 8104 //
     /*  867278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  867281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  867286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867295 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867302 */     // MIs[0] src2_modifiers
     /*  867302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867305 */     // MIs[0] matrix_a_reuse
     /*  867305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867308 */     // MIs[0] matrix_b_reuse
     /*  867308 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867318 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr),
     /*  867321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867323 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867325 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867327 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867338 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867340 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867348 */     GIR_RootConstrainSelectedInstOperands,
     /*  867349 */     // GIR_Coverage, 8104,
     /*  867349 */     GIR_EraseRootFromParent_Done,
     /*  867350 */   // Label 13943: @867350
     /*  867350 */   GIM_Try, /*On fail goto*//*Label 13944*/ GIMT_Encode4(867427), // Rule ID 8105 //
     /*  867355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  867358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  867363 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867366 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867369 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867372 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867379 */     // MIs[0] src2_modifiers
     /*  867379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867382 */     // MIs[0] matrix_a_reuse
     /*  867382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867385 */     // MIs[0] matrix_b_reuse
     /*  867385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867395 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr),
     /*  867398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867400 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867402 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867404 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867415 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867417 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867425 */     GIR_RootConstrainSelectedInstOperands,
     /*  867426 */     // GIR_Coverage, 8105,
     /*  867426 */     GIR_EraseRootFromParent_Done,
     /*  867427 */   // Label 13944: @867427
     /*  867427 */   GIM_Try, /*On fail goto*//*Label 13945*/ GIMT_Encode4(867504), // Rule ID 8106 //
     /*  867432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  867435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  867440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867449 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867456 */     // MIs[0] src2_modifiers
     /*  867456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867459 */     // MIs[0] matrix_a_reuse
     /*  867459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867462 */     // MIs[0] matrix_b_reuse
     /*  867462 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867472 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr),
     /*  867475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867477 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867479 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867481 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867492 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867494 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867502 */     GIR_RootConstrainSelectedInstOperands,
     /*  867503 */     // GIR_Coverage, 8106,
     /*  867503 */     GIR_EraseRootFromParent_Done,
     /*  867504 */   // Label 13945: @867504
     /*  867504 */   GIM_Try, /*On fail goto*//*Label 13946*/ GIMT_Encode4(867581), // Rule ID 8107 //
     /*  867509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  867512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  867517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  867520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867526 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  867529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  867533 */     // MIs[0] src2_modifiers
     /*  867533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867536 */     // MIs[0] matrix_a_reuse
     /*  867536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867539 */     // MIs[0] matrix_b_reuse
     /*  867539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867542 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867549 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr),
     /*  867552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867554 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867556 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867558 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867569 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867571 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867579 */     GIR_RootConstrainSelectedInstOperands,
     /*  867580 */     // GIR_Coverage, 8107,
     /*  867580 */     GIR_EraseRootFromParent_Done,
     /*  867581 */   // Label 13946: @867581
     /*  867581 */   GIM_Try, /*On fail goto*//*Label 13947*/ GIMT_Encode4(867658), // Rule ID 8113 //
     /*  867586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  867589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  867594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  867597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867603 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  867606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  867610 */     // MIs[0] src2_modifiers
     /*  867610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867613 */     // MIs[0] matrix_a_reuse
     /*  867613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867616 */     // MIs[0] matrix_b_reuse
     /*  867616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867619 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867626 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr),
     /*  867629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867631 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867633 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867635 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867646 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867648 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867650 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867656 */     GIR_RootConstrainSelectedInstOperands,
     /*  867657 */     // GIR_Coverage, 8113,
     /*  867657 */     GIR_EraseRootFromParent_Done,
     /*  867658 */   // Label 13947: @867658
     /*  867658 */   GIM_Try, /*On fail goto*//*Label 13948*/ GIMT_Encode4(867735), // Rule ID 8114 //
     /*  867663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  867666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  867671 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  867674 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867677 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867680 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  867683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  867687 */     // MIs[0] src2_modifiers
     /*  867687 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867690 */     // MIs[0] matrix_a_reuse
     /*  867690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867693 */     // MIs[0] matrix_b_reuse
     /*  867693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867696 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867703 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr),
     /*  867706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867708 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867710 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867712 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867723 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867725 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867733 */     GIR_RootConstrainSelectedInstOperands,
     /*  867734 */     // GIR_Coverage, 8114,
     /*  867734 */     GIR_EraseRootFromParent_Done,
     /*  867735 */   // Label 13948: @867735
     /*  867735 */   GIM_Try, /*On fail goto*//*Label 13949*/ GIMT_Encode4(867812), // Rule ID 8115 //
     /*  867740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  867743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  867748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  867751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867754 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867757 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  867760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  867764 */     // MIs[0] src2_modifiers
     /*  867764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867767 */     // MIs[0] matrix_a_reuse
     /*  867767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867770 */     // MIs[0] matrix_b_reuse
     /*  867770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867780 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr),
     /*  867783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867785 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867787 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867789 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867800 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867802 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867804 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867810 */     GIR_RootConstrainSelectedInstOperands,
     /*  867811 */     // GIR_Coverage, 8115,
     /*  867811 */     GIR_EraseRootFromParent_Done,
     /*  867812 */   // Label 13949: @867812
     /*  867812 */   GIM_Try, /*On fail goto*//*Label 13950*/ GIMT_Encode4(867889), // Rule ID 8116 //
     /*  867817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  867820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  867825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  867828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867831 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867834 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  867837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  867841 */     // MIs[0] src2_modifiers
     /*  867841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867844 */     // MIs[0] matrix_a_reuse
     /*  867844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867847 */     // MIs[0] matrix_b_reuse
     /*  867847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867857 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr),
     /*  867860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867862 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867864 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867866 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867877 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867879 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867887 */     GIR_RootConstrainSelectedInstOperands,
     /*  867888 */     // GIR_Coverage, 8116,
     /*  867888 */     GIR_EraseRootFromParent_Done,
     /*  867889 */   // Label 13950: @867889
     /*  867889 */   GIM_Try, /*On fail goto*//*Label 13951*/ GIMT_Encode4(867966), // Rule ID 8117 //
     /*  867894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  867897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  867902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  867905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867911 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  867914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  867918 */     // MIs[0] src2_modifiers
     /*  867918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867921 */     // MIs[0] matrix_a_reuse
     /*  867921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  867924 */     // MIs[0] matrix_b_reuse
     /*  867924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  867927 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  867934 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  867934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr),
     /*  867937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  867939 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  867941 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  867943 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  867949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  867954 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  867956 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  867958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  867964 */     GIR_RootConstrainSelectedInstOperands,
     /*  867965 */     // GIR_Coverage, 8117,
     /*  867965 */     GIR_EraseRootFromParent_Done,
     /*  867966 */   // Label 13951: @867966
     /*  867966 */   GIM_Try, /*On fail goto*//*Label 13952*/ GIMT_Encode4(868043), // Rule ID 8123 //
     /*  867971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  867974 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  867979 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  867982 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  867985 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  867988 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  867991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  867995 */     // MIs[0] src2_modifiers
     /*  867995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  867998 */     // MIs[0] matrix_a_reuse
     /*  867998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868001 */     // MIs[0] matrix_b_reuse
     /*  868001 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868004 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868011 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr),
     /*  868014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868016 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868018 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868020 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868026 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868031 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868033 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868041 */     GIR_RootConstrainSelectedInstOperands,
     /*  868042 */     // GIR_Coverage, 8123,
     /*  868042 */     GIR_EraseRootFromParent_Done,
     /*  868043 */   // Label 13952: @868043
     /*  868043 */   GIM_Try, /*On fail goto*//*Label 13953*/ GIMT_Encode4(868120), // Rule ID 8124 //
     /*  868048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  868051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  868056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868065 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868072 */     // MIs[0] src2_modifiers
     /*  868072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868075 */     // MIs[0] matrix_a_reuse
     /*  868075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868078 */     // MIs[0] matrix_b_reuse
     /*  868078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868088 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr),
     /*  868091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868097 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868108 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868110 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868118 */     GIR_RootConstrainSelectedInstOperands,
     /*  868119 */     // GIR_Coverage, 8124,
     /*  868119 */     GIR_EraseRootFromParent_Done,
     /*  868120 */   // Label 13953: @868120
     /*  868120 */   GIM_Try, /*On fail goto*//*Label 13954*/ GIMT_Encode4(868197), // Rule ID 8125 //
     /*  868125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  868128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  868133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868139 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868142 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868149 */     // MIs[0] src2_modifiers
     /*  868149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868152 */     // MIs[0] matrix_a_reuse
     /*  868152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868155 */     // MIs[0] matrix_b_reuse
     /*  868155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868158 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868165 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr),
     /*  868168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868170 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868172 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868174 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868185 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868187 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868189 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868195 */     GIR_RootConstrainSelectedInstOperands,
     /*  868196 */     // GIR_Coverage, 8125,
     /*  868196 */     GIR_EraseRootFromParent_Done,
     /*  868197 */   // Label 13954: @868197
     /*  868197 */   GIM_Try, /*On fail goto*//*Label 13955*/ GIMT_Encode4(868274), // Rule ID 8126 //
     /*  868202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  868205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  868210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868219 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868226 */     // MIs[0] src2_modifiers
     /*  868226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868229 */     // MIs[0] matrix_a_reuse
     /*  868229 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868232 */     // MIs[0] matrix_b_reuse
     /*  868232 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868242 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr),
     /*  868245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868247 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868249 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868251 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868262 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868264 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868272 */     GIR_RootConstrainSelectedInstOperands,
     /*  868273 */     // GIR_Coverage, 8126,
     /*  868273 */     GIR_EraseRootFromParent_Done,
     /*  868274 */   // Label 13955: @868274
     /*  868274 */   GIM_Try, /*On fail goto*//*Label 13956*/ GIMT_Encode4(868351), // Rule ID 8127 //
     /*  868279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  868282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  868287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868296 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868303 */     // MIs[0] src2_modifiers
     /*  868303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868306 */     // MIs[0] matrix_a_reuse
     /*  868306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868309 */     // MIs[0] matrix_b_reuse
     /*  868309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868312 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868319 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr),
     /*  868322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868324 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868326 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868328 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868339 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868341 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868349 */     GIR_RootConstrainSelectedInstOperands,
     /*  868350 */     // GIR_Coverage, 8127,
     /*  868350 */     GIR_EraseRootFromParent_Done,
     /*  868351 */   // Label 13956: @868351
     /*  868351 */   GIM_Try, /*On fail goto*//*Label 13957*/ GIMT_Encode4(868428), // Rule ID 8133 //
     /*  868356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  868359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  868364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868373 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868380 */     // MIs[0] src2_modifiers
     /*  868380 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868383 */     // MIs[0] matrix_a_reuse
     /*  868383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868386 */     // MIs[0] matrix_b_reuse
     /*  868386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868389 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868396 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr),
     /*  868399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868401 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868403 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868405 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868411 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868416 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868418 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868420 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868426 */     GIR_RootConstrainSelectedInstOperands,
     /*  868427 */     // GIR_Coverage, 8133,
     /*  868427 */     GIR_EraseRootFromParent_Done,
     /*  868428 */   // Label 13957: @868428
     /*  868428 */   GIM_Try, /*On fail goto*//*Label 13958*/ GIMT_Encode4(868505), // Rule ID 8134 //
     /*  868433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  868436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  868441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868450 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868453 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868457 */     // MIs[0] src2_modifiers
     /*  868457 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868460 */     // MIs[0] matrix_a_reuse
     /*  868460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868463 */     // MIs[0] matrix_b_reuse
     /*  868463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868466 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868473 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr),
     /*  868476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868478 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868480 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868482 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868493 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868495 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868503 */     GIR_RootConstrainSelectedInstOperands,
     /*  868504 */     // GIR_Coverage, 8134,
     /*  868504 */     GIR_EraseRootFromParent_Done,
     /*  868505 */   // Label 13958: @868505
     /*  868505 */   GIM_Try, /*On fail goto*//*Label 13959*/ GIMT_Encode4(868582), // Rule ID 8135 //
     /*  868510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  868513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  868518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868527 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868534 */     // MIs[0] src2_modifiers
     /*  868534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868537 */     // MIs[0] matrix_a_reuse
     /*  868537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868540 */     // MIs[0] matrix_b_reuse
     /*  868540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868543 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868550 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr),
     /*  868553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868555 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868557 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868559 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868565 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868570 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868572 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868580 */     GIR_RootConstrainSelectedInstOperands,
     /*  868581 */     // GIR_Coverage, 8135,
     /*  868581 */     GIR_EraseRootFromParent_Done,
     /*  868582 */   // Label 13959: @868582
     /*  868582 */   GIM_Try, /*On fail goto*//*Label 13960*/ GIMT_Encode4(868659), // Rule ID 8136 //
     /*  868587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  868590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  868595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868604 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868611 */     // MIs[0] src2_modifiers
     /*  868611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868614 */     // MIs[0] matrix_a_reuse
     /*  868614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868617 */     // MIs[0] matrix_b_reuse
     /*  868617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868627 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr),
     /*  868630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868632 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868634 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868636 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868647 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868649 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868657 */     GIR_RootConstrainSelectedInstOperands,
     /*  868658 */     // GIR_Coverage, 8136,
     /*  868658 */     GIR_EraseRootFromParent_Done,
     /*  868659 */   // Label 13960: @868659
     /*  868659 */   GIM_Try, /*On fail goto*//*Label 13961*/ GIMT_Encode4(868736), // Rule ID 8137 //
     /*  868664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  868667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  868672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868681 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868688 */     // MIs[0] src2_modifiers
     /*  868688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868691 */     // MIs[0] matrix_a_reuse
     /*  868691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868694 */     // MIs[0] matrix_b_reuse
     /*  868694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868697 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868704 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr),
     /*  868707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868709 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868711 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868713 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868724 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868726 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868734 */     GIR_RootConstrainSelectedInstOperands,
     /*  868735 */     // GIR_Coverage, 8137,
     /*  868735 */     GIR_EraseRootFromParent_Done,
     /*  868736 */   // Label 13961: @868736
     /*  868736 */   GIM_Try, /*On fail goto*//*Label 13962*/ GIMT_Encode4(868813), // Rule ID 8143 //
     /*  868741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  868744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  868749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868755 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868758 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868765 */     // MIs[0] src2_modifiers
     /*  868765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868768 */     // MIs[0] matrix_a_reuse
     /*  868768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868771 */     // MIs[0] matrix_b_reuse
     /*  868771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868774 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868781 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr),
     /*  868784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868786 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868788 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868790 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868801 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868803 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868811 */     GIR_RootConstrainSelectedInstOperands,
     /*  868812 */     // GIR_Coverage, 8143,
     /*  868812 */     GIR_EraseRootFromParent_Done,
     /*  868813 */   // Label 13962: @868813
     /*  868813 */   GIM_Try, /*On fail goto*//*Label 13963*/ GIMT_Encode4(868890), // Rule ID 8144 //
     /*  868818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  868821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  868826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868835 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868842 */     // MIs[0] src2_modifiers
     /*  868842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868845 */     // MIs[0] matrix_a_reuse
     /*  868845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868848 */     // MIs[0] matrix_b_reuse
     /*  868848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868851 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868858 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr),
     /*  868861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868863 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868865 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868867 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868878 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868880 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868888 */     GIR_RootConstrainSelectedInstOperands,
     /*  868889 */     // GIR_Coverage, 8144,
     /*  868889 */     GIR_EraseRootFromParent_Done,
     /*  868890 */   // Label 13963: @868890
     /*  868890 */   GIM_Try, /*On fail goto*//*Label 13964*/ GIMT_Encode4(868967), // Rule ID 8145 //
     /*  868895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  868898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  868903 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868912 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868919 */     // MIs[0] src2_modifiers
     /*  868919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868922 */     // MIs[0] matrix_a_reuse
     /*  868922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  868925 */     // MIs[0] matrix_b_reuse
     /*  868925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  868928 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  868935 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  868935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr),
     /*  868938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  868940 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  868942 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  868944 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  868950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  868955 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  868957 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  868959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  868965 */     GIR_RootConstrainSelectedInstOperands,
     /*  868966 */     // GIR_Coverage, 8145,
     /*  868966 */     GIR_EraseRootFromParent_Done,
     /*  868967 */   // Label 13964: @868967
     /*  868967 */   GIM_Try, /*On fail goto*//*Label 13965*/ GIMT_Encode4(869044), // Rule ID 8146 //
     /*  868972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  868975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  868980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  868983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  868986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  868989 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  868992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  868996 */     // MIs[0] src2_modifiers
     /*  868996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  868999 */     // MIs[0] matrix_a_reuse
     /*  868999 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869002 */     // MIs[0] matrix_b_reuse
     /*  869002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869005 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869012 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr),
     /*  869015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869017 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869019 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869021 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869032 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869034 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869036 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869042 */     GIR_RootConstrainSelectedInstOperands,
     /*  869043 */     // GIR_Coverage, 8146,
     /*  869043 */     GIR_EraseRootFromParent_Done,
     /*  869044 */   // Label 13965: @869044
     /*  869044 */   GIM_Try, /*On fail goto*//*Label 13966*/ GIMT_Encode4(869121), // Rule ID 8147 //
     /*  869049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  869052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  869057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  869063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  869066 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869073 */     // MIs[0] src2_modifiers
     /*  869073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869076 */     // MIs[0] matrix_a_reuse
     /*  869076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869079 */     // MIs[0] matrix_b_reuse
     /*  869079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869089 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr),
     /*  869092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869094 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869096 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869098 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869109 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869111 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869119 */     GIR_RootConstrainSelectedInstOperands,
     /*  869120 */     // GIR_Coverage, 8147,
     /*  869120 */     GIR_EraseRootFromParent_Done,
     /*  869121 */   // Label 13966: @869121
     /*  869121 */   GIM_Try, /*On fail goto*//*Label 13967*/ GIMT_Encode4(869198), // Rule ID 8183 //
     /*  869126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  869129 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  869134 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869137 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869140 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869143 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869150 */     // MIs[0] src2_modifiers
     /*  869150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869153 */     // MIs[0] matrix_a_reuse
     /*  869153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869156 */     // MIs[0] matrix_b_reuse
     /*  869156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869159 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869166 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr),
     /*  869169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869171 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869173 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869175 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869186 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869188 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869190 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869196 */     GIR_RootConstrainSelectedInstOperands,
     /*  869197 */     // GIR_Coverage, 8183,
     /*  869197 */     GIR_EraseRootFromParent_Done,
     /*  869198 */   // Label 13967: @869198
     /*  869198 */   GIM_Try, /*On fail goto*//*Label 13968*/ GIMT_Encode4(869275), // Rule ID 8184 //
     /*  869203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  869206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  869211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869220 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869227 */     // MIs[0] src2_modifiers
     /*  869227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869230 */     // MIs[0] matrix_a_reuse
     /*  869230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869233 */     // MIs[0] matrix_b_reuse
     /*  869233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869243 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr),
     /*  869246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869248 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869250 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869252 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869258 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869263 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869265 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869273 */     GIR_RootConstrainSelectedInstOperands,
     /*  869274 */     // GIR_Coverage, 8184,
     /*  869274 */     GIR_EraseRootFromParent_Done,
     /*  869275 */   // Label 13968: @869275
     /*  869275 */   GIM_Try, /*On fail goto*//*Label 13969*/ GIMT_Encode4(869352), // Rule ID 8185 //
     /*  869280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  869283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  869288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869297 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869304 */     // MIs[0] src2_modifiers
     /*  869304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869307 */     // MIs[0] matrix_a_reuse
     /*  869307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869310 */     // MIs[0] matrix_b_reuse
     /*  869310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869313 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869320 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr),
     /*  869323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869325 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869327 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869329 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869340 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869342 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869350 */     GIR_RootConstrainSelectedInstOperands,
     /*  869351 */     // GIR_Coverage, 8185,
     /*  869351 */     GIR_EraseRootFromParent_Done,
     /*  869352 */   // Label 13969: @869352
     /*  869352 */   GIM_Try, /*On fail goto*//*Label 13970*/ GIMT_Encode4(869429), // Rule ID 8186 //
     /*  869357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  869360 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  869365 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869374 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869381 */     // MIs[0] src2_modifiers
     /*  869381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869384 */     // MIs[0] matrix_a_reuse
     /*  869384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869387 */     // MIs[0] matrix_b_reuse
     /*  869387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869390 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869397 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr),
     /*  869400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869402 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869404 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869406 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869417 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869419 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869427 */     GIR_RootConstrainSelectedInstOperands,
     /*  869428 */     // GIR_Coverage, 8186,
     /*  869428 */     GIR_EraseRootFromParent_Done,
     /*  869429 */   // Label 13970: @869429
     /*  869429 */   GIM_Try, /*On fail goto*//*Label 13971*/ GIMT_Encode4(869506), // Rule ID 8187 //
     /*  869434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  869437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  869442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869451 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869458 */     // MIs[0] src2_modifiers
     /*  869458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869461 */     // MIs[0] matrix_a_reuse
     /*  869461 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869464 */     // MIs[0] matrix_b_reuse
     /*  869464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869467 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869474 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr),
     /*  869477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869479 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869481 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869483 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869494 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869496 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869498 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869504 */     GIR_RootConstrainSelectedInstOperands,
     /*  869505 */     // GIR_Coverage, 8187,
     /*  869505 */     GIR_EraseRootFromParent_Done,
     /*  869506 */   // Label 13971: @869506
     /*  869506 */   GIM_Try, /*On fail goto*//*Label 13972*/ GIMT_Encode4(869583), // Rule ID 8193 //
     /*  869511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  869514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  869519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869525 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869528 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869535 */     // MIs[0] src2_modifiers
     /*  869535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869538 */     // MIs[0] matrix_a_reuse
     /*  869538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869541 */     // MIs[0] matrix_b_reuse
     /*  869541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869544 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869551 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr),
     /*  869554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869556 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869558 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869560 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869566 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869571 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869573 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869575 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869581 */     GIR_RootConstrainSelectedInstOperands,
     /*  869582 */     // GIR_Coverage, 8193,
     /*  869582 */     GIR_EraseRootFromParent_Done,
     /*  869583 */   // Label 13972: @869583
     /*  869583 */   GIM_Try, /*On fail goto*//*Label 13973*/ GIMT_Encode4(869660), // Rule ID 8194 //
     /*  869588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  869591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  869596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869605 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869612 */     // MIs[0] src2_modifiers
     /*  869612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869615 */     // MIs[0] matrix_a_reuse
     /*  869615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869618 */     // MIs[0] matrix_b_reuse
     /*  869618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869628 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr),
     /*  869631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869633 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869635 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869637 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869648 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869650 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869658 */     GIR_RootConstrainSelectedInstOperands,
     /*  869659 */     // GIR_Coverage, 8194,
     /*  869659 */     GIR_EraseRootFromParent_Done,
     /*  869660 */   // Label 13973: @869660
     /*  869660 */   GIM_Try, /*On fail goto*//*Label 13974*/ GIMT_Encode4(869737), // Rule ID 8195 //
     /*  869665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  869668 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  869673 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869676 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869679 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869682 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869689 */     // MIs[0] src2_modifiers
     /*  869689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869692 */     // MIs[0] matrix_a_reuse
     /*  869692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869695 */     // MIs[0] matrix_b_reuse
     /*  869695 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869698 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869705 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr),
     /*  869708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869710 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869712 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869714 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869725 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869727 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869735 */     GIR_RootConstrainSelectedInstOperands,
     /*  869736 */     // GIR_Coverage, 8195,
     /*  869736 */     GIR_EraseRootFromParent_Done,
     /*  869737 */   // Label 13974: @869737
     /*  869737 */   GIM_Try, /*On fail goto*//*Label 13975*/ GIMT_Encode4(869814), // Rule ID 8196 //
     /*  869742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  869745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  869750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869759 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869766 */     // MIs[0] src2_modifiers
     /*  869766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869769 */     // MIs[0] matrix_a_reuse
     /*  869769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869772 */     // MIs[0] matrix_b_reuse
     /*  869772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869782 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr),
     /*  869785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869787 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869789 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869791 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869802 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869804 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869812 */     GIR_RootConstrainSelectedInstOperands,
     /*  869813 */     // GIR_Coverage, 8196,
     /*  869813 */     GIR_EraseRootFromParent_Done,
     /*  869814 */   // Label 13975: @869814
     /*  869814 */   GIM_Try, /*On fail goto*//*Label 13976*/ GIMT_Encode4(869891), // Rule ID 8197 //
     /*  869819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  869822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  869827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869836 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869843 */     // MIs[0] src2_modifiers
     /*  869843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869846 */     // MIs[0] matrix_a_reuse
     /*  869846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869849 */     // MIs[0] matrix_b_reuse
     /*  869849 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869852 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869859 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr),
     /*  869862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869864 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869866 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869868 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869879 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869881 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869889 */     GIR_RootConstrainSelectedInstOperands,
     /*  869890 */     // GIR_Coverage, 8197,
     /*  869890 */     GIR_EraseRootFromParent_Done,
     /*  869891 */   // Label 13976: @869891
     /*  869891 */   GIM_Try, /*On fail goto*//*Label 13977*/ GIMT_Encode4(869968), // Rule ID 8203 //
     /*  869896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  869899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  869904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869913 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869920 */     // MIs[0] src2_modifiers
     /*  869920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  869923 */     // MIs[0] matrix_a_reuse
     /*  869923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  869926 */     // MIs[0] matrix_b_reuse
     /*  869926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  869929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  869936 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  869936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr),
     /*  869939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  869941 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  869943 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  869945 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  869951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  869956 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  869958 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  869960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  869966 */     GIR_RootConstrainSelectedInstOperands,
     /*  869967 */     // GIR_Coverage, 8203,
     /*  869967 */     GIR_EraseRootFromParent_Done,
     /*  869968 */   // Label 13977: @869968
     /*  869968 */   GIM_Try, /*On fail goto*//*Label 13978*/ GIMT_Encode4(870045), // Rule ID 8204 //
     /*  869973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  869976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  869981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  869984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  869987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  869990 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  869993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  869997 */     // MIs[0] src2_modifiers
     /*  869997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870000 */     // MIs[0] matrix_a_reuse
     /*  870000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870003 */     // MIs[0] matrix_b_reuse
     /*  870003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870013 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr),
     /*  870016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870018 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870020 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870022 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870033 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870035 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870043 */     GIR_RootConstrainSelectedInstOperands,
     /*  870044 */     // GIR_Coverage, 8204,
     /*  870044 */     GIR_EraseRootFromParent_Done,
     /*  870045 */   // Label 13978: @870045
     /*  870045 */   GIM_Try, /*On fail goto*//*Label 13979*/ GIMT_Encode4(870122), // Rule ID 8205 //
     /*  870050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  870053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  870058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870067 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870074 */     // MIs[0] src2_modifiers
     /*  870074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870077 */     // MIs[0] matrix_a_reuse
     /*  870077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870080 */     // MIs[0] matrix_b_reuse
     /*  870080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870083 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870090 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr),
     /*  870093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870095 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870097 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870099 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870110 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870112 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870120 */     GIR_RootConstrainSelectedInstOperands,
     /*  870121 */     // GIR_Coverage, 8205,
     /*  870121 */     GIR_EraseRootFromParent_Done,
     /*  870122 */   // Label 13979: @870122
     /*  870122 */   GIM_Try, /*On fail goto*//*Label 13980*/ GIMT_Encode4(870199), // Rule ID 8206 //
     /*  870127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  870130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  870135 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870138 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870141 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870144 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870151 */     // MIs[0] src2_modifiers
     /*  870151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870154 */     // MIs[0] matrix_a_reuse
     /*  870154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870157 */     // MIs[0] matrix_b_reuse
     /*  870157 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870160 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870167 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr),
     /*  870170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870172 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870174 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870176 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870187 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870189 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870197 */     GIR_RootConstrainSelectedInstOperands,
     /*  870198 */     // GIR_Coverage, 8206,
     /*  870198 */     GIR_EraseRootFromParent_Done,
     /*  870199 */   // Label 13980: @870199
     /*  870199 */   GIM_Try, /*On fail goto*//*Label 13981*/ GIMT_Encode4(870276), // Rule ID 8207 //
     /*  870204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  870207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  870212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870221 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870228 */     // MIs[0] src2_modifiers
     /*  870228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870231 */     // MIs[0] matrix_a_reuse
     /*  870231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870234 */     // MIs[0] matrix_b_reuse
     /*  870234 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870237 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870244 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr),
     /*  870247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870249 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870251 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870253 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870264 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870266 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870274 */     GIR_RootConstrainSelectedInstOperands,
     /*  870275 */     // GIR_Coverage, 8207,
     /*  870275 */     GIR_EraseRootFromParent_Done,
     /*  870276 */   // Label 13981: @870276
     /*  870276 */   GIM_Try, /*On fail goto*//*Label 13982*/ GIMT_Encode4(870353), // Rule ID 8213 //
     /*  870281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  870284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  870289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870298 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870305 */     // MIs[0] src2_modifiers
     /*  870305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870308 */     // MIs[0] matrix_a_reuse
     /*  870308 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870311 */     // MIs[0] matrix_b_reuse
     /*  870311 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870314 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870321 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr),
     /*  870324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870326 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870328 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870330 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870336 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870341 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870343 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870351 */     GIR_RootConstrainSelectedInstOperands,
     /*  870352 */     // GIR_Coverage, 8213,
     /*  870352 */     GIR_EraseRootFromParent_Done,
     /*  870353 */   // Label 13982: @870353
     /*  870353 */   GIM_Try, /*On fail goto*//*Label 13983*/ GIMT_Encode4(870430), // Rule ID 8214 //
     /*  870358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  870361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  870366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870375 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870382 */     // MIs[0] src2_modifiers
     /*  870382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870385 */     // MIs[0] matrix_a_reuse
     /*  870385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870388 */     // MIs[0] matrix_b_reuse
     /*  870388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870398 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr),
     /*  870401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870403 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870405 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870407 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870418 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870420 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870425 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870428 */     GIR_RootConstrainSelectedInstOperands,
     /*  870429 */     // GIR_Coverage, 8214,
     /*  870429 */     GIR_EraseRootFromParent_Done,
     /*  870430 */   // Label 13983: @870430
     /*  870430 */   GIM_Try, /*On fail goto*//*Label 13984*/ GIMT_Encode4(870507), // Rule ID 8215 //
     /*  870435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  870438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  870443 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870452 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870459 */     // MIs[0] src2_modifiers
     /*  870459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870462 */     // MIs[0] matrix_a_reuse
     /*  870462 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870465 */     // MIs[0] matrix_b_reuse
     /*  870465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870468 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870475 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr),
     /*  870478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870480 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870482 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870484 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870495 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870497 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870505 */     GIR_RootConstrainSelectedInstOperands,
     /*  870506 */     // GIR_Coverage, 8215,
     /*  870506 */     GIR_EraseRootFromParent_Done,
     /*  870507 */   // Label 13984: @870507
     /*  870507 */   GIM_Try, /*On fail goto*//*Label 13985*/ GIMT_Encode4(870584), // Rule ID 8216 //
     /*  870512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  870515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  870520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870529 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870536 */     // MIs[0] src2_modifiers
     /*  870536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870539 */     // MIs[0] matrix_a_reuse
     /*  870539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870542 */     // MIs[0] matrix_b_reuse
     /*  870542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870552 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr),
     /*  870555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870557 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870559 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870561 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870572 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870574 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870582 */     GIR_RootConstrainSelectedInstOperands,
     /*  870583 */     // GIR_Coverage, 8216,
     /*  870583 */     GIR_EraseRootFromParent_Done,
     /*  870584 */   // Label 13985: @870584
     /*  870584 */   GIM_Try, /*On fail goto*//*Label 13986*/ GIMT_Encode4(870661), // Rule ID 8217 //
     /*  870589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  870592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  870597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  870600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870606 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  870609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  870613 */     // MIs[0] src2_modifiers
     /*  870613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870616 */     // MIs[0] matrix_a_reuse
     /*  870616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870619 */     // MIs[0] matrix_b_reuse
     /*  870619 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870629 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr),
     /*  870632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870634 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870636 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870638 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870649 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870651 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870659 */     GIR_RootConstrainSelectedInstOperands,
     /*  870660 */     // GIR_Coverage, 8217,
     /*  870660 */     GIR_EraseRootFromParent_Done,
     /*  870661 */   // Label 13986: @870661
     /*  870661 */   GIM_Try, /*On fail goto*//*Label 13987*/ GIMT_Encode4(870738), // Rule ID 8223 //
     /*  870666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  870669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  870674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  870677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870683 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  870686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  870690 */     // MIs[0] src2_modifiers
     /*  870690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870693 */     // MIs[0] matrix_a_reuse
     /*  870693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870696 */     // MIs[0] matrix_b_reuse
     /*  870696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870706 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr),
     /*  870709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870711 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870713 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870715 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870721 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870726 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870728 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870736 */     GIR_RootConstrainSelectedInstOperands,
     /*  870737 */     // GIR_Coverage, 8223,
     /*  870737 */     GIR_EraseRootFromParent_Done,
     /*  870738 */   // Label 13987: @870738
     /*  870738 */   GIM_Try, /*On fail goto*//*Label 13988*/ GIMT_Encode4(870815), // Rule ID 8224 //
     /*  870743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  870746 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  870751 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  870754 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870760 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  870763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  870767 */     // MIs[0] src2_modifiers
     /*  870767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870770 */     // MIs[0] matrix_a_reuse
     /*  870770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870773 */     // MIs[0] matrix_b_reuse
     /*  870773 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870776 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870783 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr),
     /*  870786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870788 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870790 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870792 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870803 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870805 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870813 */     GIR_RootConstrainSelectedInstOperands,
     /*  870814 */     // GIR_Coverage, 8224,
     /*  870814 */     GIR_EraseRootFromParent_Done,
     /*  870815 */   // Label 13988: @870815
     /*  870815 */   GIM_Try, /*On fail goto*//*Label 13989*/ GIMT_Encode4(870892), // Rule ID 8225 //
     /*  870820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  870823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  870828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  870831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870837 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  870840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  870844 */     // MIs[0] src2_modifiers
     /*  870844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870847 */     // MIs[0] matrix_a_reuse
     /*  870847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870850 */     // MIs[0] matrix_b_reuse
     /*  870850 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870853 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870860 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr),
     /*  870863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870865 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870867 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870869 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870880 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870882 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870890 */     GIR_RootConstrainSelectedInstOperands,
     /*  870891 */     // GIR_Coverage, 8225,
     /*  870891 */     GIR_EraseRootFromParent_Done,
     /*  870892 */   // Label 13989: @870892
     /*  870892 */   GIM_Try, /*On fail goto*//*Label 13990*/ GIMT_Encode4(870969), // Rule ID 8226 //
     /*  870897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  870900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  870905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  870908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870911 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870914 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  870917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  870921 */     // MIs[0] src2_modifiers
     /*  870921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  870924 */     // MIs[0] matrix_a_reuse
     /*  870924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  870927 */     // MIs[0] matrix_b_reuse
     /*  870927 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  870930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  870937 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  870937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr),
     /*  870940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  870942 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  870944 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  870946 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  870952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  870957 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  870959 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  870961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  870967 */     GIR_RootConstrainSelectedInstOperands,
     /*  870968 */     // GIR_Coverage, 8226,
     /*  870968 */     GIR_EraseRootFromParent_Done,
     /*  870969 */   // Label 13990: @870969
     /*  870969 */   GIM_Try, /*On fail goto*//*Label 13991*/ GIMT_Encode4(871046), // Rule ID 8227 //
     /*  870974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  870977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  870982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  870985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  870988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  870991 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  870994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  870998 */     // MIs[0] src2_modifiers
     /*  870998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871001 */     // MIs[0] matrix_a_reuse
     /*  871001 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871004 */     // MIs[0] matrix_b_reuse
     /*  871004 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871007 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871014 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr),
     /*  871017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871019 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871021 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871023 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871034 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871036 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871044 */     GIR_RootConstrainSelectedInstOperands,
     /*  871045 */     // GIR_Coverage, 8227,
     /*  871045 */     GIR_EraseRootFromParent_Done,
     /*  871046 */   // Label 13991: @871046
     /*  871046 */   GIM_Try, /*On fail goto*//*Label 13992*/ GIMT_Encode4(871123), // Rule ID 8233 //
     /*  871051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  871054 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  871059 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871062 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871065 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871068 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871075 */     // MIs[0] src2_modifiers
     /*  871075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871078 */     // MIs[0] matrix_a_reuse
     /*  871078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871081 */     // MIs[0] matrix_b_reuse
     /*  871081 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871084 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871091 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr),
     /*  871094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871096 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871098 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871100 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871106 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871111 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871113 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871121 */     GIR_RootConstrainSelectedInstOperands,
     /*  871122 */     // GIR_Coverage, 8233,
     /*  871122 */     GIR_EraseRootFromParent_Done,
     /*  871123 */   // Label 13992: @871123
     /*  871123 */   GIM_Try, /*On fail goto*//*Label 13993*/ GIMT_Encode4(871200), // Rule ID 8234 //
     /*  871128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  871131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  871136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871145 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871152 */     // MIs[0] src2_modifiers
     /*  871152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871155 */     // MIs[0] matrix_a_reuse
     /*  871155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871158 */     // MIs[0] matrix_b_reuse
     /*  871158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871168 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr),
     /*  871171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871173 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871175 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871177 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871188 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871190 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871192 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871198 */     GIR_RootConstrainSelectedInstOperands,
     /*  871199 */     // GIR_Coverage, 8234,
     /*  871199 */     GIR_EraseRootFromParent_Done,
     /*  871200 */   // Label 13993: @871200
     /*  871200 */   GIM_Try, /*On fail goto*//*Label 13994*/ GIMT_Encode4(871277), // Rule ID 8235 //
     /*  871205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  871208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  871213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871216 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871219 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871222 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871229 */     // MIs[0] src2_modifiers
     /*  871229 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871232 */     // MIs[0] matrix_a_reuse
     /*  871232 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871235 */     // MIs[0] matrix_b_reuse
     /*  871235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871238 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871245 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr),
     /*  871248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871250 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871252 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871254 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871265 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871267 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871275 */     GIR_RootConstrainSelectedInstOperands,
     /*  871276 */     // GIR_Coverage, 8235,
     /*  871276 */     GIR_EraseRootFromParent_Done,
     /*  871277 */   // Label 13994: @871277
     /*  871277 */   GIM_Try, /*On fail goto*//*Label 13995*/ GIMT_Encode4(871354), // Rule ID 8236 //
     /*  871282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  871285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  871290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871299 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871306 */     // MIs[0] src2_modifiers
     /*  871306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871309 */     // MIs[0] matrix_a_reuse
     /*  871309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871312 */     // MIs[0] matrix_b_reuse
     /*  871312 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871322 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr),
     /*  871325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871327 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871329 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871331 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871342 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871344 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871352 */     GIR_RootConstrainSelectedInstOperands,
     /*  871353 */     // GIR_Coverage, 8236,
     /*  871353 */     GIR_EraseRootFromParent_Done,
     /*  871354 */   // Label 13995: @871354
     /*  871354 */   GIM_Try, /*On fail goto*//*Label 13996*/ GIMT_Encode4(871431), // Rule ID 8237 //
     /*  871359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  871362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  871367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871376 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871383 */     // MIs[0] src2_modifiers
     /*  871383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871386 */     // MIs[0] matrix_a_reuse
     /*  871386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871389 */     // MIs[0] matrix_b_reuse
     /*  871389 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871392 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871399 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr),
     /*  871402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871404 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871406 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871408 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871419 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871421 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871423 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871429 */     GIR_RootConstrainSelectedInstOperands,
     /*  871430 */     // GIR_Coverage, 8237,
     /*  871430 */     GIR_EraseRootFromParent_Done,
     /*  871431 */   // Label 13996: @871431
     /*  871431 */   GIM_Try, /*On fail goto*//*Label 13997*/ GIMT_Encode4(871508), // Rule ID 8243 //
     /*  871436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  871439 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  871444 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871447 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871450 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871453 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871460 */     // MIs[0] src2_modifiers
     /*  871460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871463 */     // MIs[0] matrix_a_reuse
     /*  871463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871466 */     // MIs[0] matrix_b_reuse
     /*  871466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871476 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr),
     /*  871479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871481 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871483 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871485 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871496 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871498 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871500 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871506 */     GIR_RootConstrainSelectedInstOperands,
     /*  871507 */     // GIR_Coverage, 8243,
     /*  871507 */     GIR_EraseRootFromParent_Done,
     /*  871508 */   // Label 13997: @871508
     /*  871508 */   GIM_Try, /*On fail goto*//*Label 13998*/ GIMT_Encode4(871585), // Rule ID 8244 //
     /*  871513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  871516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  871521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871530 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871537 */     // MIs[0] src2_modifiers
     /*  871537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871540 */     // MIs[0] matrix_a_reuse
     /*  871540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871543 */     // MIs[0] matrix_b_reuse
     /*  871543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871553 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr),
     /*  871556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871558 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871560 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871562 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871573 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871575 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871583 */     GIR_RootConstrainSelectedInstOperands,
     /*  871584 */     // GIR_Coverage, 8244,
     /*  871584 */     GIR_EraseRootFromParent_Done,
     /*  871585 */   // Label 13998: @871585
     /*  871585 */   GIM_Try, /*On fail goto*//*Label 13999*/ GIMT_Encode4(871662), // Rule ID 8245 //
     /*  871590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  871593 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  871598 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871601 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871604 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871607 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871614 */     // MIs[0] src2_modifiers
     /*  871614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871617 */     // MIs[0] matrix_a_reuse
     /*  871617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871620 */     // MIs[0] matrix_b_reuse
     /*  871620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871630 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr),
     /*  871633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871635 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871637 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871639 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871650 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871652 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871660 */     GIR_RootConstrainSelectedInstOperands,
     /*  871661 */     // GIR_Coverage, 8245,
     /*  871661 */     GIR_EraseRootFromParent_Done,
     /*  871662 */   // Label 13999: @871662
     /*  871662 */   GIM_Try, /*On fail goto*//*Label 14000*/ GIMT_Encode4(871739), // Rule ID 8246 //
     /*  871667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  871670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  871675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871678 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871681 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871684 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871691 */     // MIs[0] src2_modifiers
     /*  871691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871694 */     // MIs[0] matrix_a_reuse
     /*  871694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871697 */     // MIs[0] matrix_b_reuse
     /*  871697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871707 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr),
     /*  871710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871712 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871714 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871716 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871727 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871729 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871734 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871737 */     GIR_RootConstrainSelectedInstOperands,
     /*  871738 */     // GIR_Coverage, 8246,
     /*  871738 */     GIR_EraseRootFromParent_Done,
     /*  871739 */   // Label 14000: @871739
     /*  871739 */   GIM_Try, /*On fail goto*//*Label 14001*/ GIMT_Encode4(871816), // Rule ID 8247 //
     /*  871744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  871747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  871752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871761 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871768 */     // MIs[0] src2_modifiers
     /*  871768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871771 */     // MIs[0] matrix_a_reuse
     /*  871771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871774 */     // MIs[0] matrix_b_reuse
     /*  871774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871784 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr),
     /*  871787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871789 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871791 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871793 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871804 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871806 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871814 */     GIR_RootConstrainSelectedInstOperands,
     /*  871815 */     // GIR_Coverage, 8247,
     /*  871815 */     GIR_EraseRootFromParent_Done,
     /*  871816 */   // Label 14001: @871816
     /*  871816 */   GIM_Try, /*On fail goto*//*Label 14002*/ GIMT_Encode4(871893), // Rule ID 8253 //
     /*  871821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  871824 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  871829 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871832 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871835 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871838 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871845 */     // MIs[0] src2_modifiers
     /*  871845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871848 */     // MIs[0] matrix_a_reuse
     /*  871848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871851 */     // MIs[0] matrix_b_reuse
     /*  871851 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871854 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871861 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr),
     /*  871864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871866 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871868 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871870 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871881 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871883 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871891 */     GIR_RootConstrainSelectedInstOperands,
     /*  871892 */     // GIR_Coverage, 8253,
     /*  871892 */     GIR_EraseRootFromParent_Done,
     /*  871893 */   // Label 14002: @871893
     /*  871893 */   GIM_Try, /*On fail goto*//*Label 14003*/ GIMT_Encode4(871970), // Rule ID 8254 //
     /*  871898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  871901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  871906 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871909 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871912 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871915 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871922 */     // MIs[0] src2_modifiers
     /*  871922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  871925 */     // MIs[0] matrix_a_reuse
     /*  871925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  871928 */     // MIs[0] matrix_b_reuse
     /*  871928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  871931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  871938 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  871938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr),
     /*  871941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  871943 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  871945 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  871947 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  871953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  871958 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  871960 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  871962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  871968 */     GIR_RootConstrainSelectedInstOperands,
     /*  871969 */     // GIR_Coverage, 8254,
     /*  871969 */     GIR_EraseRootFromParent_Done,
     /*  871970 */   // Label 14003: @871970
     /*  871970 */   GIM_Try, /*On fail goto*//*Label 14004*/ GIMT_Encode4(872047), // Rule ID 8255 //
     /*  871975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  871978 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  871983 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  871986 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  871989 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  871992 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  871995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  871999 */     // MIs[0] src2_modifiers
     /*  871999 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872002 */     // MIs[0] matrix_a_reuse
     /*  872002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  872005 */     // MIs[0] matrix_b_reuse
     /*  872005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  872008 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872015 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  872015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr),
     /*  872018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872020 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  872022 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  872024 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  872030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872035 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  872037 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  872039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872045 */     GIR_RootConstrainSelectedInstOperands,
     /*  872046 */     // GIR_Coverage, 8255,
     /*  872046 */     GIR_EraseRootFromParent_Done,
     /*  872047 */   // Label 14004: @872047
     /*  872047 */   GIM_Try, /*On fail goto*//*Label 14005*/ GIMT_Encode4(872124), // Rule ID 8256 //
     /*  872052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  872055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  872060 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872063 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  872066 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  872069 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  872072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872076 */     // MIs[0] src2_modifiers
     /*  872076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872079 */     // MIs[0] matrix_a_reuse
     /*  872079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  872082 */     // MIs[0] matrix_b_reuse
     /*  872082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  872085 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872092 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  872092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr),
     /*  872095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872097 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  872099 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  872101 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  872107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872112 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  872114 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  872116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872122 */     GIR_RootConstrainSelectedInstOperands,
     /*  872123 */     // GIR_Coverage, 8256,
     /*  872123 */     GIR_EraseRootFromParent_Done,
     /*  872124 */   // Label 14005: @872124
     /*  872124 */   GIM_Try, /*On fail goto*//*Label 14006*/ GIMT_Encode4(872201), // Rule ID 8257 //
     /*  872129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  872132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  872137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  872143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  872146 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  872149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872153 */     // MIs[0] src2_modifiers
     /*  872153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872156 */     // MIs[0] matrix_a_reuse
     /*  872156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  872159 */     // MIs[0] matrix_b_reuse
     /*  872159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  872162 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872169 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  872169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr),
     /*  872172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872174 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  872176 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  872178 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  872184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872189 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  872191 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  872193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872199 */     GIR_RootConstrainSelectedInstOperands,
     /*  872200 */     // GIR_Coverage, 8257,
     /*  872200 */     GIR_EraseRootFromParent_Done,
     /*  872201 */   // Label 14006: @872201
     /*  872201 */   GIM_Try, /*On fail goto*//*Label 14007*/ GIMT_Encode4(872276), // Rule ID 7773 //
     /*  872206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  872209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  872214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  872220 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  872223 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872230 */     // MIs[0] src0_modifiers
     /*  872230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872233 */     // MIs[0] src1_modifiers
     /*  872233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872236 */     // MIs[0] clamp
     /*  872236 */     // No operand predicates
     /*  872236 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872243 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr),
     /*  872246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872248 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872254 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872256 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872262 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872269 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872274 */     GIR_RootConstrainSelectedInstOperands,
     /*  872275 */     // GIR_Coverage, 7773,
     /*  872275 */     GIR_EraseRootFromParent_Done,
     /*  872276 */   // Label 14007: @872276
     /*  872276 */   GIM_Try, /*On fail goto*//*Label 14008*/ GIMT_Encode4(872351), // Rule ID 7774 //
     /*  872281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  872284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  872289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  872295 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  872298 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872305 */     // MIs[0] src0_modifiers
     /*  872305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872308 */     // MIs[0] src1_modifiers
     /*  872308 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872311 */     // MIs[0] clamp
     /*  872311 */     // No operand predicates
     /*  872311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872318 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr),
     /*  872321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872323 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872329 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872331 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872337 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872344 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872349 */     GIR_RootConstrainSelectedInstOperands,
     /*  872350 */     // GIR_Coverage, 7774,
     /*  872350 */     GIR_EraseRootFromParent_Done,
     /*  872351 */   // Label 14008: @872351
     /*  872351 */   GIM_Try, /*On fail goto*//*Label 14009*/ GIMT_Encode4(872426), // Rule ID 7775 //
     /*  872356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  872359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  872364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  872370 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  872373 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872380 */     // MIs[0] src0_modifiers
     /*  872380 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872383 */     // MIs[0] src1_modifiers
     /*  872383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872386 */     // MIs[0] clamp
     /*  872386 */     // No operand predicates
     /*  872386 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872393 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr),
     /*  872396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872398 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872404 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872406 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872412 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872419 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872424 */     GIR_RootConstrainSelectedInstOperands,
     /*  872425 */     // GIR_Coverage, 7775,
     /*  872425 */     GIR_EraseRootFromParent_Done,
     /*  872426 */   // Label 14009: @872426
     /*  872426 */   GIM_Try, /*On fail goto*//*Label 14010*/ GIMT_Encode4(872501), // Rule ID 7776 //
     /*  872431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  872434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  872439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  872445 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  872448 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872455 */     // MIs[0] src0_modifiers
     /*  872455 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872458 */     // MIs[0] src1_modifiers
     /*  872458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872461 */     // MIs[0] clamp
     /*  872461 */     // No operand predicates
     /*  872461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872468 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr),
     /*  872471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872473 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872479 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872481 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872487 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872494 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872499 */     GIR_RootConstrainSelectedInstOperands,
     /*  872500 */     // GIR_Coverage, 7776,
     /*  872500 */     GIR_EraseRootFromParent_Done,
     /*  872501 */   // Label 14010: @872501
     /*  872501 */   GIM_Try, /*On fail goto*//*Label 14011*/ GIMT_Encode4(872576), // Rule ID 7777 //
     /*  872506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  872509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  872514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  872520 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  872523 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872530 */     // MIs[0] src0_modifiers
     /*  872530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872533 */     // MIs[0] src1_modifiers
     /*  872533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872536 */     // MIs[0] clamp
     /*  872536 */     // No operand predicates
     /*  872536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872543 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr),
     /*  872546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872548 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872554 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872556 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872562 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872569 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872574 */     GIR_RootConstrainSelectedInstOperands,
     /*  872575 */     // GIR_Coverage, 7777,
     /*  872575 */     GIR_EraseRootFromParent_Done,
     /*  872576 */   // Label 14011: @872576
     /*  872576 */   GIM_Try, /*On fail goto*//*Label 14012*/ GIMT_Encode4(872651), // Rule ID 7783 //
     /*  872581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  872584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  872589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  872595 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  872598 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872605 */     // MIs[0] src0_modifiers
     /*  872605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872608 */     // MIs[0] src1_modifiers
     /*  872608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872611 */     // MIs[0] clamp
     /*  872611 */     // No operand predicates
     /*  872611 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872618 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr),
     /*  872621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872623 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872629 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872631 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872637 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872644 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872649 */     GIR_RootConstrainSelectedInstOperands,
     /*  872650 */     // GIR_Coverage, 7783,
     /*  872650 */     GIR_EraseRootFromParent_Done,
     /*  872651 */   // Label 14012: @872651
     /*  872651 */   GIM_Try, /*On fail goto*//*Label 14013*/ GIMT_Encode4(872726), // Rule ID 7784 //
     /*  872656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  872659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  872664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  872670 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  872673 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872680 */     // MIs[0] src0_modifiers
     /*  872680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872683 */     // MIs[0] src1_modifiers
     /*  872683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872686 */     // MIs[0] clamp
     /*  872686 */     // No operand predicates
     /*  872686 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872693 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr),
     /*  872696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872698 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872704 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872706 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872712 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872714 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872719 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872721 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872724 */     GIR_RootConstrainSelectedInstOperands,
     /*  872725 */     // GIR_Coverage, 7784,
     /*  872725 */     GIR_EraseRootFromParent_Done,
     /*  872726 */   // Label 14013: @872726
     /*  872726 */   GIM_Try, /*On fail goto*//*Label 14014*/ GIMT_Encode4(872801), // Rule ID 7785 //
     /*  872731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  872734 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  872739 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  872745 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  872748 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872755 */     // MIs[0] src0_modifiers
     /*  872755 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872758 */     // MIs[0] src1_modifiers
     /*  872758 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872761 */     // MIs[0] clamp
     /*  872761 */     // No operand predicates
     /*  872761 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872768 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr),
     /*  872771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872773 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872781 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872787 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872794 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872799 */     GIR_RootConstrainSelectedInstOperands,
     /*  872800 */     // GIR_Coverage, 7785,
     /*  872800 */     GIR_EraseRootFromParent_Done,
     /*  872801 */   // Label 14014: @872801
     /*  872801 */   GIM_Try, /*On fail goto*//*Label 14015*/ GIMT_Encode4(872876), // Rule ID 7786 //
     /*  872806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  872809 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  872814 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  872820 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  872823 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872830 */     // MIs[0] src0_modifiers
     /*  872830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872833 */     // MIs[0] src1_modifiers
     /*  872833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872836 */     // MIs[0] clamp
     /*  872836 */     // No operand predicates
     /*  872836 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872843 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr),
     /*  872846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872848 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872854 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872856 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872862 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872869 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872874 */     GIR_RootConstrainSelectedInstOperands,
     /*  872875 */     // GIR_Coverage, 7786,
     /*  872875 */     GIR_EraseRootFromParent_Done,
     /*  872876 */   // Label 14015: @872876
     /*  872876 */   GIM_Try, /*On fail goto*//*Label 14016*/ GIMT_Encode4(872951), // Rule ID 7787 //
     /*  872881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  872884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  872889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  872895 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  872898 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872905 */     // MIs[0] src0_modifiers
     /*  872905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872908 */     // MIs[0] src1_modifiers
     /*  872908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872911 */     // MIs[0] clamp
     /*  872911 */     // No operand predicates
     /*  872911 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872918 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr),
     /*  872921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872923 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  872929 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  872931 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  872937 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  872939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  872944 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  872946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  872949 */     GIR_RootConstrainSelectedInstOperands,
     /*  872950 */     // GIR_Coverage, 7787,
     /*  872950 */     GIR_EraseRootFromParent_Done,
     /*  872951 */   // Label 14016: @872951
     /*  872951 */   GIM_Try, /*On fail goto*//*Label 14017*/ GIMT_Encode4(873026), // Rule ID 7833 //
     /*  872956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  872959 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  872964 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  872967 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  872970 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  872973 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  872976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  872980 */     // MIs[0] src0_modifiers
     /*  872980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  872983 */     // MIs[0] src1_modifiers
     /*  872983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  872986 */     // MIs[0] clamp
     /*  872986 */     // No operand predicates
     /*  872986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  872993 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  872993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr),
     /*  872996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  872998 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873004 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873006 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873012 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873019 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873024 */     GIR_RootConstrainSelectedInstOperands,
     /*  873025 */     // GIR_Coverage, 7833,
     /*  873025 */     GIR_EraseRootFromParent_Done,
     /*  873026 */   // Label 14017: @873026
     /*  873026 */   GIM_Try, /*On fail goto*//*Label 14018*/ GIMT_Encode4(873101), // Rule ID 7834 //
     /*  873031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  873034 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  873039 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  873042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  873045 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  873048 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  873051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  873055 */     // MIs[0] src0_modifiers
     /*  873055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873058 */     // MIs[0] src1_modifiers
     /*  873058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873061 */     // MIs[0] clamp
     /*  873061 */     // No operand predicates
     /*  873061 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873068 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr),
     /*  873071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873073 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873079 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873081 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873087 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873094 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873099 */     GIR_RootConstrainSelectedInstOperands,
     /*  873100 */     // GIR_Coverage, 7834,
     /*  873100 */     GIR_EraseRootFromParent_Done,
     /*  873101 */   // Label 14018: @873101
     /*  873101 */   GIM_Try, /*On fail goto*//*Label 14019*/ GIMT_Encode4(873176), // Rule ID 7835 //
     /*  873106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  873109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  873114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  873117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  873120 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  873123 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  873126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  873130 */     // MIs[0] src0_modifiers
     /*  873130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873133 */     // MIs[0] src1_modifiers
     /*  873133 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873136 */     // MIs[0] clamp
     /*  873136 */     // No operand predicates
     /*  873136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873143 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr),
     /*  873146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873148 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873154 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873156 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873162 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873164 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873169 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873174 */     GIR_RootConstrainSelectedInstOperands,
     /*  873175 */     // GIR_Coverage, 7835,
     /*  873175 */     GIR_EraseRootFromParent_Done,
     /*  873176 */   // Label 14019: @873176
     /*  873176 */   GIM_Try, /*On fail goto*//*Label 14020*/ GIMT_Encode4(873251), // Rule ID 7836 //
     /*  873181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  873184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  873189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  873192 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  873195 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  873198 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  873201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  873205 */     // MIs[0] src0_modifiers
     /*  873205 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873208 */     // MIs[0] src1_modifiers
     /*  873208 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873211 */     // MIs[0] clamp
     /*  873211 */     // No operand predicates
     /*  873211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873218 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr),
     /*  873221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873223 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873229 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873231 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873237 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873244 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873249 */     GIR_RootConstrainSelectedInstOperands,
     /*  873250 */     // GIR_Coverage, 7836,
     /*  873250 */     GIR_EraseRootFromParent_Done,
     /*  873251 */   // Label 14020: @873251
     /*  873251 */   GIM_Try, /*On fail goto*//*Label 14021*/ GIMT_Encode4(873326), // Rule ID 7837 //
     /*  873256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  873259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  873264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  873267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  873270 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  873273 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  873276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  873280 */     // MIs[0] src0_modifiers
     /*  873280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873283 */     // MIs[0] src1_modifiers
     /*  873283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873286 */     // MIs[0] clamp
     /*  873286 */     // No operand predicates
     /*  873286 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873293 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr),
     /*  873296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873298 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873304 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873306 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873312 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873319 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873324 */     GIR_RootConstrainSelectedInstOperands,
     /*  873325 */     // GIR_Coverage, 7837,
     /*  873325 */     GIR_EraseRootFromParent_Done,
     /*  873326 */   // Label 14021: @873326
     /*  873326 */   GIM_Try, /*On fail goto*//*Label 14022*/ GIMT_Encode4(873401), // Rule ID 7938 //
     /*  873331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  873334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  873339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873345 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873348 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873355 */     // MIs[0] src0_modifiers
     /*  873355 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873358 */     // MIs[0] src1_modifiers
     /*  873358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873361 */     // MIs[0] clamp
     /*  873361 */     // No operand predicates
     /*  873361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873368 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr),
     /*  873371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873373 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873379 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873381 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873387 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873394 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873399 */     GIR_RootConstrainSelectedInstOperands,
     /*  873400 */     // GIR_Coverage, 7938,
     /*  873400 */     GIR_EraseRootFromParent_Done,
     /*  873401 */   // Label 14022: @873401
     /*  873401 */   GIM_Try, /*On fail goto*//*Label 14023*/ GIMT_Encode4(873476), // Rule ID 7939 //
     /*  873406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  873409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  873414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873420 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873423 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873430 */     // MIs[0] src0_modifiers
     /*  873430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873433 */     // MIs[0] src1_modifiers
     /*  873433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873436 */     // MIs[0] clamp
     /*  873436 */     // No operand predicates
     /*  873436 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873443 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr),
     /*  873446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873448 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873454 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873456 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873462 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873469 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873474 */     GIR_RootConstrainSelectedInstOperands,
     /*  873475 */     // GIR_Coverage, 7939,
     /*  873475 */     GIR_EraseRootFromParent_Done,
     /*  873476 */   // Label 14023: @873476
     /*  873476 */   GIM_Try, /*On fail goto*//*Label 14024*/ GIMT_Encode4(873551), // Rule ID 7940 //
     /*  873481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  873484 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  873489 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873495 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873498 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873505 */     // MIs[0] src0_modifiers
     /*  873505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873508 */     // MIs[0] src1_modifiers
     /*  873508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873511 */     // MIs[0] clamp
     /*  873511 */     // No operand predicates
     /*  873511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873518 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr),
     /*  873521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873523 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873529 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873531 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873537 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873544 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873549 */     GIR_RootConstrainSelectedInstOperands,
     /*  873550 */     // GIR_Coverage, 7940,
     /*  873550 */     GIR_EraseRootFromParent_Done,
     /*  873551 */   // Label 14024: @873551
     /*  873551 */   GIM_Try, /*On fail goto*//*Label 14025*/ GIMT_Encode4(873626), // Rule ID 7941 //
     /*  873556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  873559 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  873564 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873570 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873573 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873580 */     // MIs[0] src0_modifiers
     /*  873580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873583 */     // MIs[0] src1_modifiers
     /*  873583 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873586 */     // MIs[0] clamp
     /*  873586 */     // No operand predicates
     /*  873586 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873593 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr),
     /*  873596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873598 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873604 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873606 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873612 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873619 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873624 */     GIR_RootConstrainSelectedInstOperands,
     /*  873625 */     // GIR_Coverage, 7941,
     /*  873625 */     GIR_EraseRootFromParent_Done,
     /*  873626 */   // Label 14025: @873626
     /*  873626 */   GIM_Try, /*On fail goto*//*Label 14026*/ GIMT_Encode4(873701), // Rule ID 7942 //
     /*  873631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  873634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  873639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873645 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873648 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873655 */     // MIs[0] src0_modifiers
     /*  873655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873658 */     // MIs[0] src1_modifiers
     /*  873658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873661 */     // MIs[0] clamp
     /*  873661 */     // No operand predicates
     /*  873661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873668 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr),
     /*  873671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873673 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873679 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873681 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873687 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873694 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873699 */     GIR_RootConstrainSelectedInstOperands,
     /*  873700 */     // GIR_Coverage, 7942,
     /*  873700 */     GIR_EraseRootFromParent_Done,
     /*  873701 */   // Label 14026: @873701
     /*  873701 */   GIM_Try, /*On fail goto*//*Label 14027*/ GIMT_Encode4(873776), // Rule ID 7948 //
     /*  873706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  873709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  873714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873720 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873723 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873730 */     // MIs[0] src0_modifiers
     /*  873730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873733 */     // MIs[0] src1_modifiers
     /*  873733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873736 */     // MIs[0] clamp
     /*  873736 */     // No operand predicates
     /*  873736 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873743 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr),
     /*  873746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873748 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873754 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873756 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873762 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873769 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873774 */     GIR_RootConstrainSelectedInstOperands,
     /*  873775 */     // GIR_Coverage, 7948,
     /*  873775 */     GIR_EraseRootFromParent_Done,
     /*  873776 */   // Label 14027: @873776
     /*  873776 */   GIM_Try, /*On fail goto*//*Label 14028*/ GIMT_Encode4(873851), // Rule ID 7949 //
     /*  873781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  873784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  873789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873792 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873795 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873798 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873805 */     // MIs[0] src0_modifiers
     /*  873805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873808 */     // MIs[0] src1_modifiers
     /*  873808 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873811 */     // MIs[0] clamp
     /*  873811 */     // No operand predicates
     /*  873811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873818 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr),
     /*  873821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873823 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873829 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873831 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873837 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873844 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873849 */     GIR_RootConstrainSelectedInstOperands,
     /*  873850 */     // GIR_Coverage, 7949,
     /*  873850 */     GIR_EraseRootFromParent_Done,
     /*  873851 */   // Label 14028: @873851
     /*  873851 */   GIM_Try, /*On fail goto*//*Label 14029*/ GIMT_Encode4(873926), // Rule ID 7950 //
     /*  873856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  873859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  873864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873870 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873873 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873880 */     // MIs[0] src0_modifiers
     /*  873880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873883 */     // MIs[0] src1_modifiers
     /*  873883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873886 */     // MIs[0] clamp
     /*  873886 */     // No operand predicates
     /*  873886 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873893 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr),
     /*  873896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873898 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873904 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873906 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873912 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873919 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873924 */     GIR_RootConstrainSelectedInstOperands,
     /*  873925 */     // GIR_Coverage, 7950,
     /*  873925 */     GIR_EraseRootFromParent_Done,
     /*  873926 */   // Label 14029: @873926
     /*  873926 */   GIM_Try, /*On fail goto*//*Label 14030*/ GIMT_Encode4(874001), // Rule ID 7951 //
     /*  873931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  873934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  873939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  873942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  873945 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  873948 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  873951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  873955 */     // MIs[0] src0_modifiers
     /*  873955 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  873958 */     // MIs[0] src1_modifiers
     /*  873958 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  873961 */     // MIs[0] clamp
     /*  873961 */     // No operand predicates
     /*  873961 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  873968 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  873968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr),
     /*  873971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  873973 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  873979 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  873981 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  873987 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  873989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  873994 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  873996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  873999 */     GIR_RootConstrainSelectedInstOperands,
     /*  874000 */     // GIR_Coverage, 7951,
     /*  874000 */     GIR_EraseRootFromParent_Done,
     /*  874001 */   // Label 14030: @874001
     /*  874001 */   GIM_Try, /*On fail goto*//*Label 14031*/ GIMT_Encode4(874076), // Rule ID 7952 //
     /*  874006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  874009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  874014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  874017 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  874020 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  874023 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  874026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  874030 */     // MIs[0] src0_modifiers
     /*  874030 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  874033 */     // MIs[0] src1_modifiers
     /*  874033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  874036 */     // MIs[0] clamp
     /*  874036 */     // No operand predicates
     /*  874036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  874043 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  874043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr),
     /*  874046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874048 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  874054 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  874056 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  874062 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  874064 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874069 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  874071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  874074 */     GIR_RootConstrainSelectedInstOperands,
     /*  874075 */     // GIR_Coverage, 7952,
     /*  874075 */     GIR_EraseRootFromParent_Done,
     /*  874076 */   // Label 14031: @874076
     /*  874076 */   GIM_Try, /*On fail goto*//*Label 14032*/ GIMT_Encode4(874151), // Rule ID 7998 //
     /*  874081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  874084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  874089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  874092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  874095 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  874098 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  874101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  874105 */     // MIs[0] src0_modifiers
     /*  874105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  874108 */     // MIs[0] src1_modifiers
     /*  874108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  874111 */     // MIs[0] clamp
     /*  874111 */     // No operand predicates
     /*  874111 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  874118 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  874118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr),
     /*  874121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874123 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  874129 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  874131 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  874137 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  874139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874144 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  874146 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  874149 */     GIR_RootConstrainSelectedInstOperands,
     /*  874150 */     // GIR_Coverage, 7998,
     /*  874150 */     GIR_EraseRootFromParent_Done,
     /*  874151 */   // Label 14032: @874151
     /*  874151 */   GIM_Try, /*On fail goto*//*Label 14033*/ GIMT_Encode4(874226), // Rule ID 7999 //
     /*  874156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  874159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  874164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  874167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  874170 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  874173 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  874176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  874180 */     // MIs[0] src0_modifiers
     /*  874180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  874183 */     // MIs[0] src1_modifiers
     /*  874183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  874186 */     // MIs[0] clamp
     /*  874186 */     // No operand predicates
     /*  874186 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  874193 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  874193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr),
     /*  874196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874198 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  874204 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  874206 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  874212 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  874214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874219 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  874221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  874224 */     GIR_RootConstrainSelectedInstOperands,
     /*  874225 */     // GIR_Coverage, 7999,
     /*  874225 */     GIR_EraseRootFromParent_Done,
     /*  874226 */   // Label 14033: @874226
     /*  874226 */   GIM_Try, /*On fail goto*//*Label 14034*/ GIMT_Encode4(874301), // Rule ID 8000 //
     /*  874231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  874234 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  874239 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  874242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  874245 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  874248 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  874251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  874255 */     // MIs[0] src0_modifiers
     /*  874255 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  874258 */     // MIs[0] src1_modifiers
     /*  874258 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  874261 */     // MIs[0] clamp
     /*  874261 */     // No operand predicates
     /*  874261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  874268 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  874268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr),
     /*  874271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874273 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  874279 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  874281 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  874287 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  874289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874294 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  874296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  874299 */     GIR_RootConstrainSelectedInstOperands,
     /*  874300 */     // GIR_Coverage, 8000,
     /*  874300 */     GIR_EraseRootFromParent_Done,
     /*  874301 */   // Label 14034: @874301
     /*  874301 */   GIM_Try, /*On fail goto*//*Label 14035*/ GIMT_Encode4(874376), // Rule ID 8001 //
     /*  874306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  874309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  874314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  874317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  874320 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  874323 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  874326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  874330 */     // MIs[0] src0_modifiers
     /*  874330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  874333 */     // MIs[0] src1_modifiers
     /*  874333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  874336 */     // MIs[0] clamp
     /*  874336 */     // No operand predicates
     /*  874336 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  874343 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  874343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr),
     /*  874346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874348 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  874354 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  874356 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  874362 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  874364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874369 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  874371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  874374 */     GIR_RootConstrainSelectedInstOperands,
     /*  874375 */     // GIR_Coverage, 8001,
     /*  874375 */     GIR_EraseRootFromParent_Done,
     /*  874376 */   // Label 14035: @874376
     /*  874376 */   GIM_Try, /*On fail goto*//*Label 14036*/ GIMT_Encode4(874451), // Rule ID 8002 //
     /*  874381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  874384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  874389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  874392 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  874395 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  874398 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  874401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  874405 */     // MIs[0] src0_modifiers
     /*  874405 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  874408 */     // MIs[0] src1_modifiers
     /*  874408 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  874411 */     // MIs[0] clamp
     /*  874411 */     // No operand predicates
     /*  874411 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  874418 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  874418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr),
     /*  874421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874423 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  874429 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  874431 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  874437 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  874439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874444 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  874446 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  874449 */     GIR_RootConstrainSelectedInstOperands,
     /*  874450 */     // GIR_Coverage, 8002,
     /*  874450 */     GIR_EraseRootFromParent_Done,
     /*  874451 */   // Label 14036: @874451
     /*  874451 */   GIM_Try, /*On fail goto*//*Label 14037*/ GIMT_Encode4(874523), // Rule ID 8558 //
     /*  874456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  874459 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_fp8),
     /*  874464 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874470 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874473 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874476 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874483 */     // MIs[0] matrix_a_reuse
     /*  874483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874486 */     // MIs[0] matrix_b_reuse
     /*  874486 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874496 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3588:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  874499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874501 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874503 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874505 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874517 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874519 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874521 */     GIR_RootConstrainSelectedInstOperands,
     /*  874522 */     // GIR_Coverage, 8558,
     /*  874522 */     GIR_EraseRootFromParent_Done,
     /*  874523 */   // Label 14037: @874523
     /*  874523 */   GIM_Try, /*On fail goto*//*Label 14038*/ GIMT_Encode4(874595), // Rule ID 8559 //
     /*  874528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  874531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_fp8),
     /*  874536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874545 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874548 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874555 */     // MIs[0] matrix_a_reuse
     /*  874555 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874558 */     // MIs[0] matrix_b_reuse
     /*  874558 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874568 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3588:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  874571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874573 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874575 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874577 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874589 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874591 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874593 */     GIR_RootConstrainSelectedInstOperands,
     /*  874594 */     // GIR_Coverage, 8559,
     /*  874594 */     GIR_EraseRootFromParent_Done,
     /*  874595 */   // Label 14038: @874595
     /*  874595 */   GIM_Try, /*On fail goto*//*Label 14039*/ GIMT_Encode4(874667), // Rule ID 8560 //
     /*  874600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  874603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_fp8),
     /*  874608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874620 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874627 */     // MIs[0] matrix_a_reuse
     /*  874627 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874630 */     // MIs[0] matrix_b_reuse
     /*  874630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874640 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3588:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  874643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874645 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874647 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874649 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874651 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874656 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874661 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874663 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874665 */     GIR_RootConstrainSelectedInstOperands,
     /*  874666 */     // GIR_Coverage, 8560,
     /*  874666 */     GIR_EraseRootFromParent_Done,
     /*  874667 */   // Label 14039: @874667
     /*  874667 */   GIM_Try, /*On fail goto*//*Label 14040*/ GIMT_Encode4(874739), // Rule ID 8561 //
     /*  874672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  874675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_fp8),
     /*  874680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874689 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874692 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874699 */     // MIs[0] matrix_a_reuse
     /*  874699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874702 */     // MIs[0] matrix_b_reuse
     /*  874702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874705 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874712 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3588:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  874715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874717 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874719 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874721 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874733 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874735 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874737 */     GIR_RootConstrainSelectedInstOperands,
     /*  874738 */     // GIR_Coverage, 8561,
     /*  874738 */     GIR_EraseRootFromParent_Done,
     /*  874739 */   // Label 14040: @874739
     /*  874739 */   GIM_Try, /*On fail goto*//*Label 14041*/ GIMT_Encode4(874811), // Rule ID 8562 //
     /*  874744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  874747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_fp8),
     /*  874752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874761 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874764 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874771 */     // MIs[0] matrix_a_reuse
     /*  874771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874774 */     // MIs[0] matrix_b_reuse
     /*  874774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874784 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3588:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  874787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874789 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874791 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874793 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874805 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874807 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874809 */     GIR_RootConstrainSelectedInstOperands,
     /*  874810 */     // GIR_Coverage, 8562,
     /*  874810 */     GIR_EraseRootFromParent_Done,
     /*  874811 */   // Label 14041: @874811
     /*  874811 */   GIM_Try, /*On fail goto*//*Label 14042*/ GIMT_Encode4(874883), // Rule ID 8563 //
     /*  874816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  874819 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_bf8),
     /*  874824 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874827 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874830 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874833 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874836 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874843 */     // MIs[0] matrix_a_reuse
     /*  874843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874846 */     // MIs[0] matrix_b_reuse
     /*  874846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874849 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874856 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3587:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  874859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874861 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874863 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874865 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874877 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874879 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874881 */     GIR_RootConstrainSelectedInstOperands,
     /*  874882 */     // GIR_Coverage, 8563,
     /*  874882 */     GIR_EraseRootFromParent_Done,
     /*  874883 */   // Label 14042: @874883
     /*  874883 */   GIM_Try, /*On fail goto*//*Label 14043*/ GIMT_Encode4(874955), // Rule ID 8564 //
     /*  874888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  874891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_bf8),
     /*  874896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874905 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874908 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874915 */     // MIs[0] matrix_a_reuse
     /*  874915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874918 */     // MIs[0] matrix_b_reuse
     /*  874918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  874928 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3587:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  874928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  874931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  874933 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  874935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  874937 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  874939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  874944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  874949 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  874951 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  874953 */     GIR_RootConstrainSelectedInstOperands,
     /*  874954 */     // GIR_Coverage, 8564,
     /*  874954 */     GIR_EraseRootFromParent_Done,
     /*  874955 */   // Label 14043: @874955
     /*  874955 */   GIM_Try, /*On fail goto*//*Label 14044*/ GIMT_Encode4(875027), // Rule ID 8565 //
     /*  874960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  874963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_bf8),
     /*  874968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  874971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  874974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  874977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  874980 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  874983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  874987 */     // MIs[0] matrix_a_reuse
     /*  874987 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  874990 */     // MIs[0] matrix_b_reuse
     /*  874990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  874993 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875000 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3587:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  875003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875005 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875007 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875009 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875021 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875023 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875025 */     GIR_RootConstrainSelectedInstOperands,
     /*  875026 */     // GIR_Coverage, 8565,
     /*  875026 */     GIR_EraseRootFromParent_Done,
     /*  875027 */   // Label 14044: @875027
     /*  875027 */   GIM_Try, /*On fail goto*//*Label 14045*/ GIMT_Encode4(875099), // Rule ID 8566 //
     /*  875032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  875035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_bf8),
     /*  875040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875049 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875052 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875059 */     // MIs[0] matrix_a_reuse
     /*  875059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875062 */     // MIs[0] matrix_b_reuse
     /*  875062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875072 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3587:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  875075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875077 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875079 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875081 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875093 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875095 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875097 */     GIR_RootConstrainSelectedInstOperands,
     /*  875098 */     // GIR_Coverage, 8566,
     /*  875098 */     GIR_EraseRootFromParent_Done,
     /*  875099 */   // Label 14045: @875099
     /*  875099 */   GIM_Try, /*On fail goto*//*Label 14046*/ GIMT_Encode4(875171), // Rule ID 8567 //
     /*  875104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  875107 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_fp8_bf8),
     /*  875112 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875121 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875124 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875131 */     // MIs[0] matrix_a_reuse
     /*  875131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875134 */     // MIs[0] matrix_b_reuse
     /*  875134 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875137 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875144 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3587:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  875147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875149 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875151 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875153 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875165 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875167 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875169 */     GIR_RootConstrainSelectedInstOperands,
     /*  875170 */     // GIR_Coverage, 8567,
     /*  875170 */     GIR_EraseRootFromParent_Done,
     /*  875171 */   // Label 14046: @875171
     /*  875171 */   GIM_Try, /*On fail goto*//*Label 14047*/ GIMT_Encode4(875243), // Rule ID 8568 //
     /*  875176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  875179 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_fp8),
     /*  875184 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875187 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875190 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875193 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875196 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875203 */     // MIs[0] matrix_a_reuse
     /*  875203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875206 */     // MIs[0] matrix_b_reuse
     /*  875206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875209 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875216 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3586:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  875219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875221 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875223 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875225 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875237 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875239 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875241 */     GIR_RootConstrainSelectedInstOperands,
     /*  875242 */     // GIR_Coverage, 8568,
     /*  875242 */     GIR_EraseRootFromParent_Done,
     /*  875243 */   // Label 14047: @875243
     /*  875243 */   GIM_Try, /*On fail goto*//*Label 14048*/ GIMT_Encode4(875315), // Rule ID 8569 //
     /*  875248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  875251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_fp8),
     /*  875256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875265 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875268 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875275 */     // MIs[0] matrix_a_reuse
     /*  875275 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875278 */     // MIs[0] matrix_b_reuse
     /*  875278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875288 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3586:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  875291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875293 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875295 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875297 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875309 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875311 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875313 */     GIR_RootConstrainSelectedInstOperands,
     /*  875314 */     // GIR_Coverage, 8569,
     /*  875314 */     GIR_EraseRootFromParent_Done,
     /*  875315 */   // Label 14048: @875315
     /*  875315 */   GIM_Try, /*On fail goto*//*Label 14049*/ GIMT_Encode4(875387), // Rule ID 8570 //
     /*  875320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  875323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_fp8),
     /*  875328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875340 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875347 */     // MIs[0] matrix_a_reuse
     /*  875347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875350 */     // MIs[0] matrix_b_reuse
     /*  875350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875353 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875360 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3586:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  875363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875365 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875367 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875369 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875381 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875383 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875385 */     GIR_RootConstrainSelectedInstOperands,
     /*  875386 */     // GIR_Coverage, 8570,
     /*  875386 */     GIR_EraseRootFromParent_Done,
     /*  875387 */   // Label 14049: @875387
     /*  875387 */   GIM_Try, /*On fail goto*//*Label 14050*/ GIMT_Encode4(875459), // Rule ID 8571 //
     /*  875392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  875395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_fp8),
     /*  875400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875412 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875419 */     // MIs[0] matrix_a_reuse
     /*  875419 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875422 */     // MIs[0] matrix_b_reuse
     /*  875422 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875425 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875432 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3586:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  875435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875437 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875439 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875441 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875453 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875455 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875457 */     GIR_RootConstrainSelectedInstOperands,
     /*  875458 */     // GIR_Coverage, 8571,
     /*  875458 */     GIR_EraseRootFromParent_Done,
     /*  875459 */   // Label 14050: @875459
     /*  875459 */   GIM_Try, /*On fail goto*//*Label 14051*/ GIMT_Encode4(875531), // Rule ID 8572 //
     /*  875464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  875467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_fp8),
     /*  875472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875478 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875481 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875484 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875491 */     // MIs[0] matrix_a_reuse
     /*  875491 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875494 */     // MIs[0] matrix_b_reuse
     /*  875494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875504 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3586:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  875507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875509 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875511 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875513 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875525 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875527 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875529 */     GIR_RootConstrainSelectedInstOperands,
     /*  875530 */     // GIR_Coverage, 8572,
     /*  875530 */     GIR_EraseRootFromParent_Done,
     /*  875531 */   // Label 14051: @875531
     /*  875531 */   GIM_Try, /*On fail goto*//*Label 14052*/ GIMT_Encode4(875603), // Rule ID 8573 //
     /*  875536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  875539 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_bf8),
     /*  875544 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875547 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875550 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875553 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875556 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875563 */     // MIs[0] matrix_a_reuse
     /*  875563 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875566 */     // MIs[0] matrix_b_reuse
     /*  875566 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875576 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3585:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  875579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875581 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875583 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875585 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875587 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875592 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875597 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875599 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875601 */     GIR_RootConstrainSelectedInstOperands,
     /*  875602 */     // GIR_Coverage, 8573,
     /*  875602 */     GIR_EraseRootFromParent_Done,
     /*  875603 */   // Label 14052: @875603
     /*  875603 */   GIM_Try, /*On fail goto*//*Label 14053*/ GIMT_Encode4(875675), // Rule ID 8574 //
     /*  875608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  875611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_bf8),
     /*  875616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875622 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875625 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875628 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875635 */     // MIs[0] matrix_a_reuse
     /*  875635 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875638 */     // MIs[0] matrix_b_reuse
     /*  875638 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875641 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875648 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3585:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  875651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875653 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875655 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875657 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875669 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875671 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875673 */     GIR_RootConstrainSelectedInstOperands,
     /*  875674 */     // GIR_Coverage, 8574,
     /*  875674 */     GIR_EraseRootFromParent_Done,
     /*  875675 */   // Label 14053: @875675
     /*  875675 */   GIM_Try, /*On fail goto*//*Label 14054*/ GIMT_Encode4(875747), // Rule ID 8575 //
     /*  875680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  875683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_bf8),
     /*  875688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875694 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875697 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875700 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875707 */     // MIs[0] matrix_a_reuse
     /*  875707 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875710 */     // MIs[0] matrix_b_reuse
     /*  875710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875720 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3585:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  875723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875725 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875727 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875729 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875741 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875743 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875745 */     GIR_RootConstrainSelectedInstOperands,
     /*  875746 */     // GIR_Coverage, 8575,
     /*  875746 */     GIR_EraseRootFromParent_Done,
     /*  875747 */   // Label 14054: @875747
     /*  875747 */   GIM_Try, /*On fail goto*//*Label 14055*/ GIMT_Encode4(875819), // Rule ID 8576 //
     /*  875752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  875755 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_bf8),
     /*  875760 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875763 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875766 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875769 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875772 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875779 */     // MIs[0] matrix_a_reuse
     /*  875779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875782 */     // MIs[0] matrix_b_reuse
     /*  875782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875792 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3585:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  875795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875797 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875799 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875801 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875813 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875815 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875817 */     GIR_RootConstrainSelectedInstOperands,
     /*  875818 */     // GIR_Coverage, 8576,
     /*  875818 */     GIR_EraseRootFromParent_Done,
     /*  875819 */   // Label 14055: @875819
     /*  875819 */   GIM_Try, /*On fail goto*//*Label 14056*/ GIMT_Encode4(875891), // Rule ID 8577 //
     /*  875824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  875827 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x128_bf8_bf8),
     /*  875832 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  875835 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875838 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875841 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32,
     /*  875844 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  875851 */     // MIs[0] matrix_a_reuse
     /*  875851 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875854 */     // MIs[0] matrix_b_reuse
     /*  875854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875864 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3585:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  875867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875869 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875871 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875873 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875885 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875887 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875889 */     GIR_RootConstrainSelectedInstOperands,
     /*  875890 */     // GIR_Coverage, 8577,
     /*  875890 */     GIR_EraseRootFromParent_Done,
     /*  875891 */   // Label 14056: @875891
     /*  875891 */   GIM_Try, /*On fail goto*//*Label 14057*/ GIMT_Encode4(875963), // Rule ID 8578 //
     /*  875896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  875899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_fp8),
     /*  875904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  875907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875913 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  875916 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  875923 */     // MIs[0] matrix_a_reuse
     /*  875923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875926 */     // MIs[0] matrix_b_reuse
     /*  875926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  875929 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  875936 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3582:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  875936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  875939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  875941 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  875943 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  875945 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  875947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  875952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  875957 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  875959 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  875961 */     GIR_RootConstrainSelectedInstOperands,
     /*  875962 */     // GIR_Coverage, 8578,
     /*  875962 */     GIR_EraseRootFromParent_Done,
     /*  875963 */   // Label 14057: @875963
     /*  875963 */   GIM_Try, /*On fail goto*//*Label 14058*/ GIMT_Encode4(876035), // Rule ID 8579 //
     /*  875968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  875971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_fp8),
     /*  875976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  875979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  875982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  875985 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  875988 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  875991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  875995 */     // MIs[0] matrix_a_reuse
     /*  875995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  875998 */     // MIs[0] matrix_b_reuse
     /*  875998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876008 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3582:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  876011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876013 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876015 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876017 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876029 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876031 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876033 */     GIR_RootConstrainSelectedInstOperands,
     /*  876034 */     // GIR_Coverage, 8579,
     /*  876034 */     GIR_EraseRootFromParent_Done,
     /*  876035 */   // Label 14058: @876035
     /*  876035 */   GIM_Try, /*On fail goto*//*Label 14059*/ GIMT_Encode4(876107), // Rule ID 8580 //
     /*  876040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  876043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_fp8),
     /*  876048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876057 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876060 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876067 */     // MIs[0] matrix_a_reuse
     /*  876067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876070 */     // MIs[0] matrix_b_reuse
     /*  876070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876080 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3582:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  876083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876085 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876087 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876089 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876101 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876103 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876105 */     GIR_RootConstrainSelectedInstOperands,
     /*  876106 */     // GIR_Coverage, 8580,
     /*  876106 */     GIR_EraseRootFromParent_Done,
     /*  876107 */   // Label 14059: @876107
     /*  876107 */   GIM_Try, /*On fail goto*//*Label 14060*/ GIMT_Encode4(876179), // Rule ID 8581 //
     /*  876112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  876115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_fp8),
     /*  876120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876129 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876132 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876139 */     // MIs[0] matrix_a_reuse
     /*  876139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876142 */     // MIs[0] matrix_b_reuse
     /*  876142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876152 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3582:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  876155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876157 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876159 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876161 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876173 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876175 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876177 */     GIR_RootConstrainSelectedInstOperands,
     /*  876178 */     // GIR_Coverage, 8581,
     /*  876178 */     GIR_EraseRootFromParent_Done,
     /*  876179 */   // Label 14060: @876179
     /*  876179 */   GIM_Try, /*On fail goto*//*Label 14061*/ GIMT_Encode4(876251), // Rule ID 8582 //
     /*  876184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  876187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_fp8),
     /*  876192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876201 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876204 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876211 */     // MIs[0] matrix_a_reuse
     /*  876211 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876214 */     // MIs[0] matrix_b_reuse
     /*  876214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876217 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876224 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3582:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  876227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876229 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876231 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876233 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876245 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876247 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876249 */     GIR_RootConstrainSelectedInstOperands,
     /*  876250 */     // GIR_Coverage, 8582,
     /*  876250 */     GIR_EraseRootFromParent_Done,
     /*  876251 */   // Label 14061: @876251
     /*  876251 */   GIM_Try, /*On fail goto*//*Label 14062*/ GIMT_Encode4(876323), // Rule ID 8583 //
     /*  876256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  876259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_bf8),
     /*  876264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876273 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876276 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876283 */     // MIs[0] matrix_a_reuse
     /*  876283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876286 */     // MIs[0] matrix_b_reuse
     /*  876286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876296 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3581:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  876299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876301 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876303 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876305 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876317 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876319 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876321 */     GIR_RootConstrainSelectedInstOperands,
     /*  876322 */     // GIR_Coverage, 8583,
     /*  876322 */     GIR_EraseRootFromParent_Done,
     /*  876323 */   // Label 14062: @876323
     /*  876323 */   GIM_Try, /*On fail goto*//*Label 14063*/ GIMT_Encode4(876395), // Rule ID 8584 //
     /*  876328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  876331 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_bf8),
     /*  876336 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876339 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876345 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876348 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876355 */     // MIs[0] matrix_a_reuse
     /*  876355 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876358 */     // MIs[0] matrix_b_reuse
     /*  876358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876368 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3581:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  876371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876373 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876375 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876377 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876389 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876391 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876393 */     GIR_RootConstrainSelectedInstOperands,
     /*  876394 */     // GIR_Coverage, 8584,
     /*  876394 */     GIR_EraseRootFromParent_Done,
     /*  876395 */   // Label 14063: @876395
     /*  876395 */   GIM_Try, /*On fail goto*//*Label 14064*/ GIMT_Encode4(876467), // Rule ID 8585 //
     /*  876400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  876403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_bf8),
     /*  876408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876417 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876420 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876427 */     // MIs[0] matrix_a_reuse
     /*  876427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876430 */     // MIs[0] matrix_b_reuse
     /*  876430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876440 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3581:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  876443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876445 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876447 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876449 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876461 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876463 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876465 */     GIR_RootConstrainSelectedInstOperands,
     /*  876466 */     // GIR_Coverage, 8585,
     /*  876466 */     GIR_EraseRootFromParent_Done,
     /*  876467 */   // Label 14064: @876467
     /*  876467 */   GIM_Try, /*On fail goto*//*Label 14065*/ GIMT_Encode4(876539), // Rule ID 8586 //
     /*  876472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  876475 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_bf8),
     /*  876480 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876483 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876486 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876489 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876492 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876499 */     // MIs[0] matrix_a_reuse
     /*  876499 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876502 */     // MIs[0] matrix_b_reuse
     /*  876502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876512 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3581:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  876515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876517 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876519 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876521 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876533 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876535 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876537 */     GIR_RootConstrainSelectedInstOperands,
     /*  876538 */     // GIR_Coverage, 8586,
     /*  876538 */     GIR_EraseRootFromParent_Done,
     /*  876539 */   // Label 14065: @876539
     /*  876539 */   GIM_Try, /*On fail goto*//*Label 14066*/ GIMT_Encode4(876611), // Rule ID 8587 //
     /*  876544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  876547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_fp8_bf8),
     /*  876552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876564 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876571 */     // MIs[0] matrix_a_reuse
     /*  876571 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876574 */     // MIs[0] matrix_b_reuse
     /*  876574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876584 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3581:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  876587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876589 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876591 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876593 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876605 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876607 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876609 */     GIR_RootConstrainSelectedInstOperands,
     /*  876610 */     // GIR_Coverage, 8587,
     /*  876610 */     GIR_EraseRootFromParent_Done,
     /*  876611 */   // Label 14066: @876611
     /*  876611 */   GIM_Try, /*On fail goto*//*Label 14067*/ GIMT_Encode4(876683), // Rule ID 8588 //
     /*  876616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  876619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_fp8),
     /*  876624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876633 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876636 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876643 */     // MIs[0] matrix_a_reuse
     /*  876643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876646 */     // MIs[0] matrix_b_reuse
     /*  876646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876649 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876656 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3580:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  876659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876661 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876663 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876665 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876677 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876679 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876681 */     GIR_RootConstrainSelectedInstOperands,
     /*  876682 */     // GIR_Coverage, 8588,
     /*  876682 */     GIR_EraseRootFromParent_Done,
     /*  876683 */   // Label 14067: @876683
     /*  876683 */   GIM_Try, /*On fail goto*//*Label 14068*/ GIMT_Encode4(876755), // Rule ID 8589 //
     /*  876688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  876691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_fp8),
     /*  876696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876705 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876708 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876715 */     // MIs[0] matrix_a_reuse
     /*  876715 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876718 */     // MIs[0] matrix_b_reuse
     /*  876718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876721 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876728 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3580:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  876731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876733 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876735 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876737 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876749 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876751 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876753 */     GIR_RootConstrainSelectedInstOperands,
     /*  876754 */     // GIR_Coverage, 8589,
     /*  876754 */     GIR_EraseRootFromParent_Done,
     /*  876755 */   // Label 14068: @876755
     /*  876755 */   GIM_Try, /*On fail goto*//*Label 14069*/ GIMT_Encode4(876827), // Rule ID 8590 //
     /*  876760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  876763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_fp8),
     /*  876768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876780 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876787 */     // MIs[0] matrix_a_reuse
     /*  876787 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876790 */     // MIs[0] matrix_b_reuse
     /*  876790 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876800 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3580:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  876803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876805 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876807 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876809 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876821 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876823 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876825 */     GIR_RootConstrainSelectedInstOperands,
     /*  876826 */     // GIR_Coverage, 8590,
     /*  876826 */     GIR_EraseRootFromParent_Done,
     /*  876827 */   // Label 14069: @876827
     /*  876827 */   GIM_Try, /*On fail goto*//*Label 14070*/ GIMT_Encode4(876899), // Rule ID 8591 //
     /*  876832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  876835 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_fp8),
     /*  876840 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876849 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876852 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876859 */     // MIs[0] matrix_a_reuse
     /*  876859 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876862 */     // MIs[0] matrix_b_reuse
     /*  876862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876865 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876872 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3580:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  876875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876877 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876879 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876881 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876893 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876895 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876897 */     GIR_RootConstrainSelectedInstOperands,
     /*  876898 */     // GIR_Coverage, 8591,
     /*  876898 */     GIR_EraseRootFromParent_Done,
     /*  876899 */   // Label 14070: @876899
     /*  876899 */   GIM_Try, /*On fail goto*//*Label 14071*/ GIMT_Encode4(876971), // Rule ID 8592 //
     /*  876904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  876907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_fp8),
     /*  876912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876921 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876924 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  876931 */     // MIs[0] matrix_a_reuse
     /*  876931 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  876934 */     // MIs[0] matrix_b_reuse
     /*  876934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  876937 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  876944 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3580:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  876944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  876947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  876949 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  876951 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  876953 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  876955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  876960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  876965 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  876967 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  876969 */     GIR_RootConstrainSelectedInstOperands,
     /*  876970 */     // GIR_Coverage, 8592,
     /*  876970 */     GIR_EraseRootFromParent_Done,
     /*  876971 */   // Label 14071: @876971
     /*  876971 */   GIM_Try, /*On fail goto*//*Label 14072*/ GIMT_Encode4(877043), // Rule ID 8593 //
     /*  876976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  876979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_bf8),
     /*  876984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  876987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  876990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  876993 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  876996 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  876999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  877003 */     // MIs[0] matrix_a_reuse
     /*  877003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877006 */     // MIs[0] matrix_b_reuse
     /*  877006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  877016 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3579:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  877016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  877019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877021 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  877023 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  877025 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  877027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  877032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  877037 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  877039 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  877041 */     GIR_RootConstrainSelectedInstOperands,
     /*  877042 */     // GIR_Coverage, 8593,
     /*  877042 */     GIR_EraseRootFromParent_Done,
     /*  877043 */   // Label 14072: @877043
     /*  877043 */   GIM_Try, /*On fail goto*//*Label 14073*/ GIMT_Encode4(877115), // Rule ID 8594 //
     /*  877048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  877051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_bf8),
     /*  877056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  877059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  877062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  877065 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  877068 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  877071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  877075 */     // MIs[0] matrix_a_reuse
     /*  877075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877078 */     // MIs[0] matrix_b_reuse
     /*  877078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  877088 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3579:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  877088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  877091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  877095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  877097 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  877099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  877104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  877109 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  877111 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  877113 */     GIR_RootConstrainSelectedInstOperands,
     /*  877114 */     // GIR_Coverage, 8594,
     /*  877114 */     GIR_EraseRootFromParent_Done,
     /*  877115 */   // Label 14073: @877115
     /*  877115 */   GIM_Try, /*On fail goto*//*Label 14074*/ GIMT_Encode4(877187), // Rule ID 8595 //
     /*  877120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  877123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_bf8),
     /*  877128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  877131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  877134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  877137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  877140 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  877143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  877147 */     // MIs[0] matrix_a_reuse
     /*  877147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877150 */     // MIs[0] matrix_b_reuse
     /*  877150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877153 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  877160 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3579:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  877160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  877163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877165 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  877167 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  877169 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  877171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  877176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  877181 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  877183 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  877185 */     GIR_RootConstrainSelectedInstOperands,
     /*  877186 */     // GIR_Coverage, 8595,
     /*  877186 */     GIR_EraseRootFromParent_Done,
     /*  877187 */   // Label 14074: @877187
     /*  877187 */   GIM_Try, /*On fail goto*//*Label 14075*/ GIMT_Encode4(877259), // Rule ID 8596 //
     /*  877192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  877195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_bf8),
     /*  877200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  877203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  877206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  877209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  877212 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  877215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  877219 */     // MIs[0] matrix_a_reuse
     /*  877219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877222 */     // MIs[0] matrix_b_reuse
     /*  877222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  877232 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3579:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  877232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  877235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877237 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  877239 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  877241 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  877243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  877248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  877253 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  877255 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  877257 */     GIR_RootConstrainSelectedInstOperands,
     /*  877258 */     // GIR_Coverage, 8596,
     /*  877258 */     GIR_EraseRootFromParent_Done,
     /*  877259 */   // Label 14075: @877259
     /*  877259 */   GIM_Try, /*On fail goto*//*Label 14076*/ GIMT_Encode4(877331), // Rule ID 8597 //
     /*  877264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  877267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x128_bf8_bf8),
     /*  877272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  877275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  877278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  877281 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /*  877284 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /*  877287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  877291 */     // MIs[0] matrix_a_reuse
     /*  877291 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877294 */     // MIs[0] matrix_b_reuse
     /*  877294 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  877304 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3579:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  877304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  877307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877309 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  877311 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  877313 */     GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef
     /*  877315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  877320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  877325 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  877327 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  877329 */     GIR_RootConstrainSelectedInstOperands,
     /*  877330 */     // GIR_Coverage, 8597,
     /*  877330 */     GIR_EraseRootFromParent_Done,
     /*  877331 */   // Label 14076: @877331
     /*  877331 */   GIM_Try, /*On fail goto*//*Label 14077*/ GIMT_Encode4(877404), // Rule ID 7055 //
     /*  877336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  877347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  877350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  877353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877357 */     // MIs[0] dpp_ctrl
     /*  877357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877360 */     // MIs[0] row_mask
     /*  877360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877363 */     // MIs[0] bank_mask
     /*  877363 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877366 */     // MIs[0] bound_ctrl
     /*  877366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877369 */     // (intrinsic_wo_chain:{ *:[i32] } 3612:{ *:[iPTR] }, i32:{ *:[i32] }:$old, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877374 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877376 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877378 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877384 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877390 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877396 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877402 */     GIR_RootConstrainSelectedInstOperands,
     /*  877403 */     // GIR_Coverage, 7055,
     /*  877403 */     GIR_EraseRootFromParent_Done,
     /*  877404 */   // Label 14077: @877404
     /*  877404 */   GIM_Try, /*On fail goto*//*Label 14078*/ GIMT_Encode4(877477), // Rule ID 7056 //
     /*  877409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  877420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  877423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  877426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877430 */     // MIs[0] dpp_ctrl
     /*  877430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877433 */     // MIs[0] row_mask
     /*  877433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877436 */     // MIs[0] bank_mask
     /*  877436 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877439 */     // MIs[0] bound_ctrl
     /*  877439 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877442 */     // (intrinsic_wo_chain:{ *:[f32] } 3612:{ *:[iPTR] }, f32:{ *:[f32] }:$old, f32:{ *:[f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[f32] } VGPR_32:{ *:[f32] }:$old, VGPR_32:{ *:[f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877447 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877449 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877451 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877457 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877463 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877469 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877475 */     GIR_RootConstrainSelectedInstOperands,
     /*  877476 */     // GIR_Coverage, 7056,
     /*  877476 */     GIR_EraseRootFromParent_Done,
     /*  877477 */   // Label 14078: @877477
     /*  877477 */   GIM_Try, /*On fail goto*//*Label 14079*/ GIMT_Encode4(877550), // Rule ID 7057 //
     /*  877482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  877493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  877496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  877499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877503 */     // MIs[0] dpp_ctrl
     /*  877503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877506 */     // MIs[0] row_mask
     /*  877506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877509 */     // MIs[0] bank_mask
     /*  877509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877512 */     // MIs[0] bound_ctrl
     /*  877512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877515 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3612:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$old, v2i16:{ *:[v2i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[v2i16] } VGPR_32:{ *:[v2i16] }:$old, VGPR_32:{ *:[v2i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877520 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877522 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877524 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877530 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877536 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877542 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877548 */     GIR_RootConstrainSelectedInstOperands,
     /*  877549 */     // GIR_Coverage, 7057,
     /*  877549 */     GIR_EraseRootFromParent_Done,
     /*  877550 */   // Label 14079: @877550
     /*  877550 */   GIM_Try, /*On fail goto*//*Label 14080*/ GIMT_Encode4(877623), // Rule ID 7058 //
     /*  877555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877558 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877563 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  877566 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  877569 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  877572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877576 */     // MIs[0] dpp_ctrl
     /*  877576 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877579 */     // MIs[0] row_mask
     /*  877579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877582 */     // MIs[0] bank_mask
     /*  877582 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877585 */     // MIs[0] bound_ctrl
     /*  877585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877588 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3612:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$old, v2f16:{ *:[v2f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$old, VGPR_32:{ *:[v2f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877593 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877595 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877597 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877603 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877609 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877615 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877621 */     GIR_RootConstrainSelectedInstOperands,
     /*  877622 */     // GIR_Coverage, 7058,
     /*  877622 */     GIR_EraseRootFromParent_Done,
     /*  877623 */   // Label 14080: @877623
     /*  877623 */   GIM_Try, /*On fail goto*//*Label 14081*/ GIMT_Encode4(877696), // Rule ID 7059 //
     /*  877628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  877639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  877642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  877645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877649 */     // MIs[0] dpp_ctrl
     /*  877649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877652 */     // MIs[0] row_mask
     /*  877652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877655 */     // MIs[0] bank_mask
     /*  877655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877658 */     // MIs[0] bound_ctrl
     /*  877658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877661 */     // (intrinsic_wo_chain:{ *:[i32] } 3612:{ *:[iPTR] }, p2:{ *:[i32] }:$old, p2:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877666 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877668 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877670 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877676 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877682 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877688 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877694 */     GIR_RootConstrainSelectedInstOperands,
     /*  877695 */     // GIR_Coverage, 7059,
     /*  877695 */     GIR_EraseRootFromParent_Done,
     /*  877696 */   // Label 14081: @877696
     /*  877696 */   GIM_Try, /*On fail goto*//*Label 14082*/ GIMT_Encode4(877769), // Rule ID 7060 //
     /*  877701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877709 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  877712 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  877715 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  877718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877722 */     // MIs[0] dpp_ctrl
     /*  877722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877725 */     // MIs[0] row_mask
     /*  877725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877728 */     // MIs[0] bank_mask
     /*  877728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877731 */     // MIs[0] bound_ctrl
     /*  877731 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877734 */     // (intrinsic_wo_chain:{ *:[i32] } 3612:{ *:[iPTR] }, p3:{ *:[i32] }:$old, p3:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877739 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877741 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877743 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877749 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877755 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877761 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877767 */     GIR_RootConstrainSelectedInstOperands,
     /*  877768 */     // GIR_Coverage, 7060,
     /*  877768 */     GIR_EraseRootFromParent_Done,
     /*  877769 */   // Label 14082: @877769
     /*  877769 */   GIM_Try, /*On fail goto*//*Label 14083*/ GIMT_Encode4(877842), // Rule ID 7061 //
     /*  877774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  877785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  877788 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  877791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877795 */     // MIs[0] dpp_ctrl
     /*  877795 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877798 */     // MIs[0] row_mask
     /*  877798 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877801 */     // MIs[0] bank_mask
     /*  877801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877804 */     // MIs[0] bound_ctrl
     /*  877804 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877807 */     // (intrinsic_wo_chain:{ *:[i32] } 3612:{ *:[iPTR] }, p5:{ *:[i32] }:$old, p5:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877812 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877814 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877816 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877822 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877828 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877834 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877840 */     GIR_RootConstrainSelectedInstOperands,
     /*  877841 */     // GIR_Coverage, 7061,
     /*  877841 */     GIR_EraseRootFromParent_Done,
     /*  877842 */   // Label 14083: @877842
     /*  877842 */   GIM_Try, /*On fail goto*//*Label 14084*/ GIMT_Encode4(877915), // Rule ID 7062 //
     /*  877847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
     /*  877850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  877858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  877861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  877864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  877868 */     // MIs[0] dpp_ctrl
     /*  877868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877871 */     // MIs[0] row_mask
     /*  877871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877874 */     // MIs[0] bank_mask
     /*  877874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877877 */     // MIs[0] bound_ctrl
     /*  877877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877880 */     // (intrinsic_wo_chain:{ *:[i32] } 3612:{ *:[iPTR] }, p6:{ *:[i32] }:$old, p6:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
     /*  877883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877885 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877887 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877889 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877895 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877901 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877907 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877913 */     GIR_RootConstrainSelectedInstOperands,
     /*  877914 */     // GIR_Coverage, 7062,
     /*  877914 */     GIR_EraseRootFromParent_Done,
     /*  877915 */   // Label 14084: @877915
     /*  877915 */   GIM_Try, /*On fail goto*//*Label 14085*/ GIMT_Encode4(877988), // Rule ID 28435 //
     /*  877920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  877923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  877928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  877931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  877934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  877937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  877941 */     // MIs[0] dpp_ctrl
     /*  877941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  877944 */     // MIs[0] row_mask
     /*  877944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  877947 */     // MIs[0] bank_mask
     /*  877947 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  877950 */     // MIs[0] bound_ctrl
     /*  877950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  877953 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  877953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  877956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  877958 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  877960 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  877962 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  877968 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  877974 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  877980 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  877986 */     GIR_RootConstrainSelectedInstOperands,
     /*  877987 */     // GIR_Coverage, 28435,
     /*  877987 */     GIR_EraseRootFromParent_Done,
     /*  877988 */   // Label 14085: @877988
     /*  877988 */   GIM_Try, /*On fail goto*//*Label 14086*/ GIMT_Encode4(878061), // Rule ID 28436 //
     /*  877993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  877996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878014 */     // MIs[0] dpp_ctrl
     /*  878014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878017 */     // MIs[0] row_mask
     /*  878017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878020 */     // MIs[0] bank_mask
     /*  878020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878023 */     // MIs[0] bound_ctrl
     /*  878023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878026 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878031 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878033 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878035 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878041 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878047 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878053 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878059 */     GIR_RootConstrainSelectedInstOperands,
     /*  878060 */     // GIR_Coverage, 28436,
     /*  878060 */     GIR_EraseRootFromParent_Done,
     /*  878061 */   // Label 14086: @878061
     /*  878061 */   GIM_Try, /*On fail goto*//*Label 14087*/ GIMT_Encode4(878134), // Rule ID 28437 //
     /*  878066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  878069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878087 */     // MIs[0] dpp_ctrl
     /*  878087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878090 */     // MIs[0] row_mask
     /*  878090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878093 */     // MIs[0] bank_mask
     /*  878093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878096 */     // MIs[0] bound_ctrl
     /*  878096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878099 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878104 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878106 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878108 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878114 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878120 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878126 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878132 */     GIR_RootConstrainSelectedInstOperands,
     /*  878133 */     // GIR_Coverage, 28437,
     /*  878133 */     GIR_EraseRootFromParent_Done,
     /*  878134 */   // Label 14087: @878134
     /*  878134 */   GIM_Try, /*On fail goto*//*Label 14088*/ GIMT_Encode4(878207), // Rule ID 28438 //
     /*  878139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  878142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878147 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878150 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878153 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878160 */     // MIs[0] dpp_ctrl
     /*  878160 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878163 */     // MIs[0] row_mask
     /*  878163 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878166 */     // MIs[0] bank_mask
     /*  878166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878169 */     // MIs[0] bound_ctrl
     /*  878169 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878172 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878177 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878179 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878181 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878187 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878193 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878199 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878205 */     GIR_RootConstrainSelectedInstOperands,
     /*  878206 */     // GIR_Coverage, 28438,
     /*  878206 */     GIR_EraseRootFromParent_Done,
     /*  878207 */   // Label 14088: @878207
     /*  878207 */   GIM_Try, /*On fail goto*//*Label 14089*/ GIMT_Encode4(878280), // Rule ID 28439 //
     /*  878212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  878215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878233 */     // MIs[0] dpp_ctrl
     /*  878233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878236 */     // MIs[0] row_mask
     /*  878236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878239 */     // MIs[0] bank_mask
     /*  878239 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878242 */     // MIs[0] bound_ctrl
     /*  878242 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878245 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878250 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878252 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878254 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878260 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878266 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878272 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878278 */     GIR_RootConstrainSelectedInstOperands,
     /*  878279 */     // GIR_Coverage, 28439,
     /*  878279 */     GIR_EraseRootFromParent_Done,
     /*  878280 */   // Label 14089: @878280
     /*  878280 */   GIM_Try, /*On fail goto*//*Label 14090*/ GIMT_Encode4(878353), // Rule ID 28440 //
     /*  878285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  878288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878299 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878306 */     // MIs[0] dpp_ctrl
     /*  878306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878309 */     // MIs[0] row_mask
     /*  878309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878312 */     // MIs[0] bank_mask
     /*  878312 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878315 */     // MIs[0] bound_ctrl
     /*  878315 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878318 */     // (intrinsic_wo_chain:{ *:[f64] } 3612:{ *:[iPTR] }, f64:{ *:[f64] }:$old, f64:{ *:[f64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[f64] } VReg_64_Align2:{ *:[f64] }:$old, VReg_64_Align2:{ *:[f64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878323 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878325 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878327 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878333 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878339 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878345 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878351 */     GIR_RootConstrainSelectedInstOperands,
     /*  878352 */     // GIR_Coverage, 28440,
     /*  878352 */     GIR_EraseRootFromParent_Done,
     /*  878353 */   // Label 14090: @878353
     /*  878353 */   GIM_Try, /*On fail goto*//*Label 14091*/ GIMT_Encode4(878426), // Rule ID 28441 //
     /*  878358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  878361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878379 */     // MIs[0] dpp_ctrl
     /*  878379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878382 */     // MIs[0] row_mask
     /*  878382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878385 */     // MIs[0] bank_mask
     /*  878385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878388 */     // MIs[0] bound_ctrl
     /*  878388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878391 */     // (intrinsic_wo_chain:{ *:[f64] } 3612:{ *:[iPTR] }, f64:{ *:[f64] }:$old, f64:{ *:[f64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[f64] } VReg_64_Align2:{ *:[f64] }:$old, VReg_64_Align2:{ *:[f64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878396 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878398 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878400 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878406 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878412 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878418 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878424 */     GIR_RootConstrainSelectedInstOperands,
     /*  878425 */     // GIR_Coverage, 28441,
     /*  878425 */     GIR_EraseRootFromParent_Done,
     /*  878426 */   // Label 14091: @878426
     /*  878426 */   GIM_Try, /*On fail goto*//*Label 14092*/ GIMT_Encode4(878499), // Rule ID 28442 //
     /*  878431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  878434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878452 */     // MIs[0] dpp_ctrl
     /*  878452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878455 */     // MIs[0] row_mask
     /*  878455 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878458 */     // MIs[0] bank_mask
     /*  878458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878461 */     // MIs[0] bound_ctrl
     /*  878461 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878464 */     // (intrinsic_wo_chain:{ *:[f64] } 3612:{ *:[iPTR] }, f64:{ *:[f64] }:$old, f64:{ *:[f64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[f64] } VReg_64_Align2:{ *:[f64] }:$old, VReg_64_Align2:{ *:[f64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878469 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878471 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878473 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878479 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878485 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878491 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878497 */     GIR_RootConstrainSelectedInstOperands,
     /*  878498 */     // GIR_Coverage, 28442,
     /*  878498 */     GIR_EraseRootFromParent_Done,
     /*  878499 */   // Label 14092: @878499
     /*  878499 */   GIM_Try, /*On fail goto*//*Label 14093*/ GIMT_Encode4(878572), // Rule ID 28443 //
     /*  878504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  878507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878525 */     // MIs[0] dpp_ctrl
     /*  878525 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878528 */     // MIs[0] row_mask
     /*  878528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878531 */     // MIs[0] bank_mask
     /*  878531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878534 */     // MIs[0] bound_ctrl
     /*  878534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878537 */     // (intrinsic_wo_chain:{ *:[f64] } 3612:{ *:[iPTR] }, f64:{ *:[f64] }:$old, f64:{ *:[f64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[f64] } VReg_64_Align2:{ *:[f64] }:$old, VReg_64_Align2:{ *:[f64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878542 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878544 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878546 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878552 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878558 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878564 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878570 */     GIR_RootConstrainSelectedInstOperands,
     /*  878571 */     // GIR_Coverage, 28443,
     /*  878571 */     GIR_EraseRootFromParent_Done,
     /*  878572 */   // Label 14093: @878572
     /*  878572 */   GIM_Try, /*On fail goto*//*Label 14094*/ GIMT_Encode4(878645), // Rule ID 28444 //
     /*  878577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  878580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  878588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  878591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  878594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878598 */     // MIs[0] dpp_ctrl
     /*  878598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878601 */     // MIs[0] row_mask
     /*  878601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878604 */     // MIs[0] bank_mask
     /*  878604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878607 */     // MIs[0] bound_ctrl
     /*  878607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878610 */     // (intrinsic_wo_chain:{ *:[f64] } 3612:{ *:[iPTR] }, f64:{ *:[f64] }:$old, f64:{ *:[f64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[f64] } VReg_64_Align2:{ *:[f64] }:$old, VReg_64_Align2:{ *:[f64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878615 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878617 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878619 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878625 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878631 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878637 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878643 */     GIR_RootConstrainSelectedInstOperands,
     /*  878644 */     // GIR_Coverage, 28444,
     /*  878644 */     GIR_EraseRootFromParent_Done,
     /*  878645 */   // Label 14094: @878645
     /*  878645 */   GIM_Try, /*On fail goto*//*Label 14095*/ GIMT_Encode4(878718), // Rule ID 28445 //
     /*  878650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  878653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  878661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  878664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  878667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878671 */     // MIs[0] dpp_ctrl
     /*  878671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878674 */     // MIs[0] row_mask
     /*  878674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878677 */     // MIs[0] bank_mask
     /*  878677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878680 */     // MIs[0] bound_ctrl
     /*  878680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878683 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3612:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$old, v2i32:{ *:[v2i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2i32] } VReg_64_Align2:{ *:[v2i32] }:$old, VReg_64_Align2:{ *:[v2i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878688 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878690 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878692 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878698 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878704 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878710 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878716 */     GIR_RootConstrainSelectedInstOperands,
     /*  878717 */     // GIR_Coverage, 28445,
     /*  878717 */     GIR_EraseRootFromParent_Done,
     /*  878718 */   // Label 14095: @878718
     /*  878718 */   GIM_Try, /*On fail goto*//*Label 14096*/ GIMT_Encode4(878791), // Rule ID 28446 //
     /*  878723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  878726 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878731 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  878734 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  878737 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  878740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878744 */     // MIs[0] dpp_ctrl
     /*  878744 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878747 */     // MIs[0] row_mask
     /*  878747 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878750 */     // MIs[0] bank_mask
     /*  878750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878753 */     // MIs[0] bound_ctrl
     /*  878753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878756 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3612:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$old, v2i32:{ *:[v2i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2i32] } VReg_64_Align2:{ *:[v2i32] }:$old, VReg_64_Align2:{ *:[v2i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878761 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878763 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878765 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878771 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878777 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878783 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878789 */     GIR_RootConstrainSelectedInstOperands,
     /*  878790 */     // GIR_Coverage, 28446,
     /*  878790 */     GIR_EraseRootFromParent_Done,
     /*  878791 */   // Label 14096: @878791
     /*  878791 */   GIM_Try, /*On fail goto*//*Label 14097*/ GIMT_Encode4(878864), // Rule ID 28447 //
     /*  878796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  878799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  878807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  878810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  878813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878817 */     // MIs[0] dpp_ctrl
     /*  878817 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878820 */     // MIs[0] row_mask
     /*  878820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878823 */     // MIs[0] bank_mask
     /*  878823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878826 */     // MIs[0] bound_ctrl
     /*  878826 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878829 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3612:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$old, v2i32:{ *:[v2i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2i32] } VReg_64_Align2:{ *:[v2i32] }:$old, VReg_64_Align2:{ *:[v2i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878834 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878836 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878838 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878844 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878850 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878856 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878862 */     GIR_RootConstrainSelectedInstOperands,
     /*  878863 */     // GIR_Coverage, 28447,
     /*  878863 */     GIR_EraseRootFromParent_Done,
     /*  878864 */   // Label 14097: @878864
     /*  878864 */   GIM_Try, /*On fail goto*//*Label 14098*/ GIMT_Encode4(878937), // Rule ID 28448 //
     /*  878869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  878872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  878880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  878883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  878886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878890 */     // MIs[0] dpp_ctrl
     /*  878890 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878893 */     // MIs[0] row_mask
     /*  878893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878896 */     // MIs[0] bank_mask
     /*  878896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878899 */     // MIs[0] bound_ctrl
     /*  878899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878902 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3612:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$old, v2i32:{ *:[v2i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2i32] } VReg_64_Align2:{ *:[v2i32] }:$old, VReg_64_Align2:{ *:[v2i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878907 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878909 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878911 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878917 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878923 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  878929 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  878935 */     GIR_RootConstrainSelectedInstOperands,
     /*  878936 */     // GIR_Coverage, 28448,
     /*  878936 */     GIR_EraseRootFromParent_Done,
     /*  878937 */   // Label 14098: @878937
     /*  878937 */   GIM_Try, /*On fail goto*//*Label 14099*/ GIMT_Encode4(879010), // Rule ID 28449 //
     /*  878942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  878945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  878950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  878953 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  878956 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  878959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  878963 */     // MIs[0] dpp_ctrl
     /*  878963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  878966 */     // MIs[0] row_mask
     /*  878966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  878969 */     // MIs[0] bank_mask
     /*  878969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  878972 */     // MIs[0] bound_ctrl
     /*  878972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  878975 */     // (intrinsic_wo_chain:{ *:[v2i32] } 3612:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$old, v2i32:{ *:[v2i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2i32] } VReg_64_Align2:{ *:[v2i32] }:$old, VReg_64_Align2:{ *:[v2i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  878975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  878978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  878980 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  878982 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  878984 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  878990 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  878996 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879002 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879008 */     GIR_RootConstrainSelectedInstOperands,
     /*  879009 */     // GIR_Coverage, 28449,
     /*  879009 */     GIR_EraseRootFromParent_Done,
     /*  879010 */   // Label 14099: @879010
     /*  879010 */   GIM_Try, /*On fail goto*//*Label 14100*/ GIMT_Encode4(879083), // Rule ID 28450 //
     /*  879015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  879018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  879026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  879029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  879032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879036 */     // MIs[0] dpp_ctrl
     /*  879036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879039 */     // MIs[0] row_mask
     /*  879039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879042 */     // MIs[0] bank_mask
     /*  879042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879045 */     // MIs[0] bound_ctrl
     /*  879045 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879048 */     // (intrinsic_wo_chain:{ *:[v2f32] } 3612:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$old, v2f32:{ *:[v2f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2f32] } VReg_64_Align2:{ *:[v2f32] }:$old, VReg_64_Align2:{ *:[v2f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879053 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879055 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879057 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879063 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879069 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879075 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879081 */     GIR_RootConstrainSelectedInstOperands,
     /*  879082 */     // GIR_Coverage, 28450,
     /*  879082 */     GIR_EraseRootFromParent_Done,
     /*  879083 */   // Label 14100: @879083
     /*  879083 */   GIM_Try, /*On fail goto*//*Label 14101*/ GIMT_Encode4(879156), // Rule ID 28451 //
     /*  879088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  879091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  879099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  879102 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  879105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879109 */     // MIs[0] dpp_ctrl
     /*  879109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879112 */     // MIs[0] row_mask
     /*  879112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879115 */     // MIs[0] bank_mask
     /*  879115 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879118 */     // MIs[0] bound_ctrl
     /*  879118 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879121 */     // (intrinsic_wo_chain:{ *:[v2f32] } 3612:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$old, v2f32:{ *:[v2f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2f32] } VReg_64_Align2:{ *:[v2f32] }:$old, VReg_64_Align2:{ *:[v2f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879126 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879128 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879130 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879136 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879142 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879148 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879154 */     GIR_RootConstrainSelectedInstOperands,
     /*  879155 */     // GIR_Coverage, 28451,
     /*  879155 */     GIR_EraseRootFromParent_Done,
     /*  879156 */   // Label 14101: @879156
     /*  879156 */   GIM_Try, /*On fail goto*//*Label 14102*/ GIMT_Encode4(879229), // Rule ID 28452 //
     /*  879161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  879164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  879172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  879175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  879178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879182 */     // MIs[0] dpp_ctrl
     /*  879182 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879185 */     // MIs[0] row_mask
     /*  879185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879188 */     // MIs[0] bank_mask
     /*  879188 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879191 */     // MIs[0] bound_ctrl
     /*  879191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879194 */     // (intrinsic_wo_chain:{ *:[v2f32] } 3612:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$old, v2f32:{ *:[v2f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2f32] } VReg_64_Align2:{ *:[v2f32] }:$old, VReg_64_Align2:{ *:[v2f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879199 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879201 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879203 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879209 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879215 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879221 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879227 */     GIR_RootConstrainSelectedInstOperands,
     /*  879228 */     // GIR_Coverage, 28452,
     /*  879228 */     GIR_EraseRootFromParent_Done,
     /*  879229 */   // Label 14102: @879229
     /*  879229 */   GIM_Try, /*On fail goto*//*Label 14103*/ GIMT_Encode4(879302), // Rule ID 28453 //
     /*  879234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  879237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  879245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  879248 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  879251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879255 */     // MIs[0] dpp_ctrl
     /*  879255 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879258 */     // MIs[0] row_mask
     /*  879258 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879261 */     // MIs[0] bank_mask
     /*  879261 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879264 */     // MIs[0] bound_ctrl
     /*  879264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879267 */     // (intrinsic_wo_chain:{ *:[v2f32] } 3612:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$old, v2f32:{ *:[v2f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2f32] } VReg_64_Align2:{ *:[v2f32] }:$old, VReg_64_Align2:{ *:[v2f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879272 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879274 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879276 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879282 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879288 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879294 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879300 */     GIR_RootConstrainSelectedInstOperands,
     /*  879301 */     // GIR_Coverage, 28453,
     /*  879301 */     GIR_EraseRootFromParent_Done,
     /*  879302 */   // Label 14103: @879302
     /*  879302 */   GIM_Try, /*On fail goto*//*Label 14104*/ GIMT_Encode4(879375), // Rule ID 28454 //
     /*  879307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  879310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  879318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  879321 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  879324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879328 */     // MIs[0] dpp_ctrl
     /*  879328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879331 */     // MIs[0] row_mask
     /*  879331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879334 */     // MIs[0] bank_mask
     /*  879334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879337 */     // MIs[0] bound_ctrl
     /*  879337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879340 */     // (intrinsic_wo_chain:{ *:[v2f32] } 3612:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$old, v2f32:{ *:[v2f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v2f32] } VReg_64_Align2:{ *:[v2f32] }:$old, VReg_64_Align2:{ *:[v2f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879345 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879347 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879349 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879355 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879361 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879367 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879373 */     GIR_RootConstrainSelectedInstOperands,
     /*  879374 */     // GIR_Coverage, 28454,
     /*  879374 */     GIR_EraseRootFromParent_Done,
     /*  879375 */   // Label 14104: @879375
     /*  879375 */   GIM_Try, /*On fail goto*//*Label 14105*/ GIMT_Encode4(879448), // Rule ID 28455 //
     /*  879380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  879383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879401 */     // MIs[0] dpp_ctrl
     /*  879401 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879404 */     // MIs[0] row_mask
     /*  879404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879407 */     // MIs[0] bank_mask
     /*  879407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879410 */     // MIs[0] bound_ctrl
     /*  879410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879413 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3612:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$old, v4i16:{ *:[v4i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4i16] } VReg_64_Align2:{ *:[v4i16] }:$old, VReg_64_Align2:{ *:[v4i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879418 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879420 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879422 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879428 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879434 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879440 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879446 */     GIR_RootConstrainSelectedInstOperands,
     /*  879447 */     // GIR_Coverage, 28455,
     /*  879447 */     GIR_EraseRootFromParent_Done,
     /*  879448 */   // Label 14105: @879448
     /*  879448 */   GIM_Try, /*On fail goto*//*Label 14106*/ GIMT_Encode4(879521), // Rule ID 28456 //
     /*  879453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  879456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879467 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879474 */     // MIs[0] dpp_ctrl
     /*  879474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879477 */     // MIs[0] row_mask
     /*  879477 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879480 */     // MIs[0] bank_mask
     /*  879480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879483 */     // MIs[0] bound_ctrl
     /*  879483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879486 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3612:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$old, v4i16:{ *:[v4i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4i16] } VReg_64_Align2:{ *:[v4i16] }:$old, VReg_64_Align2:{ *:[v4i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879491 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879493 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879495 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879501 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879507 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879513 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879519 */     GIR_RootConstrainSelectedInstOperands,
     /*  879520 */     // GIR_Coverage, 28456,
     /*  879520 */     GIR_EraseRootFromParent_Done,
     /*  879521 */   // Label 14106: @879521
     /*  879521 */   GIM_Try, /*On fail goto*//*Label 14107*/ GIMT_Encode4(879594), // Rule ID 28457 //
     /*  879526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  879529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879540 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879547 */     // MIs[0] dpp_ctrl
     /*  879547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879550 */     // MIs[0] row_mask
     /*  879550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879553 */     // MIs[0] bank_mask
     /*  879553 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879556 */     // MIs[0] bound_ctrl
     /*  879556 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879559 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3612:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$old, v4i16:{ *:[v4i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4i16] } VReg_64_Align2:{ *:[v4i16] }:$old, VReg_64_Align2:{ *:[v4i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879564 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879566 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879568 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879574 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879580 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879586 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879592 */     GIR_RootConstrainSelectedInstOperands,
     /*  879593 */     // GIR_Coverage, 28457,
     /*  879593 */     GIR_EraseRootFromParent_Done,
     /*  879594 */   // Label 14107: @879594
     /*  879594 */   GIM_Try, /*On fail goto*//*Label 14108*/ GIMT_Encode4(879667), // Rule ID 28458 //
     /*  879599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  879602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879620 */     // MIs[0] dpp_ctrl
     /*  879620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879623 */     // MIs[0] row_mask
     /*  879623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879626 */     // MIs[0] bank_mask
     /*  879626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879629 */     // MIs[0] bound_ctrl
     /*  879629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879632 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3612:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$old, v4i16:{ *:[v4i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4i16] } VReg_64_Align2:{ *:[v4i16] }:$old, VReg_64_Align2:{ *:[v4i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879637 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879639 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879641 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879647 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879653 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879659 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879665 */     GIR_RootConstrainSelectedInstOperands,
     /*  879666 */     // GIR_Coverage, 28458,
     /*  879666 */     GIR_EraseRootFromParent_Done,
     /*  879667 */   // Label 14108: @879667
     /*  879667 */   GIM_Try, /*On fail goto*//*Label 14109*/ GIMT_Encode4(879740), // Rule ID 28459 //
     /*  879672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  879675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879693 */     // MIs[0] dpp_ctrl
     /*  879693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879696 */     // MIs[0] row_mask
     /*  879696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879699 */     // MIs[0] bank_mask
     /*  879699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879702 */     // MIs[0] bound_ctrl
     /*  879702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879705 */     // (intrinsic_wo_chain:{ *:[v4i16] } 3612:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$old, v4i16:{ *:[v4i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4i16] } VReg_64_Align2:{ *:[v4i16] }:$old, VReg_64_Align2:{ *:[v4i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879710 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879712 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879714 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879720 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879726 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879732 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879738 */     GIR_RootConstrainSelectedInstOperands,
     /*  879739 */     // GIR_Coverage, 28459,
     /*  879739 */     GIR_EraseRootFromParent_Done,
     /*  879740 */   // Label 14109: @879740
     /*  879740 */   GIM_Try, /*On fail goto*//*Label 14110*/ GIMT_Encode4(879813), // Rule ID 28460 //
     /*  879745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  879748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879766 */     // MIs[0] dpp_ctrl
     /*  879766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879769 */     // MIs[0] row_mask
     /*  879769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879772 */     // MIs[0] bank_mask
     /*  879772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879775 */     // MIs[0] bound_ctrl
     /*  879775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879778 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3612:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$old, v4f16:{ *:[v4f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4f16] } VReg_64_Align2:{ *:[v4f16] }:$old, VReg_64_Align2:{ *:[v4f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879783 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879785 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879787 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879793 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879799 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879805 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879811 */     GIR_RootConstrainSelectedInstOperands,
     /*  879812 */     // GIR_Coverage, 28460,
     /*  879812 */     GIR_EraseRootFromParent_Done,
     /*  879813 */   // Label 14110: @879813
     /*  879813 */   GIM_Try, /*On fail goto*//*Label 14111*/ GIMT_Encode4(879886), // Rule ID 28461 //
     /*  879818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  879821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879839 */     // MIs[0] dpp_ctrl
     /*  879839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879842 */     // MIs[0] row_mask
     /*  879842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879845 */     // MIs[0] bank_mask
     /*  879845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879848 */     // MIs[0] bound_ctrl
     /*  879848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879851 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3612:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$old, v4f16:{ *:[v4f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4f16] } VReg_64_Align2:{ *:[v4f16] }:$old, VReg_64_Align2:{ *:[v4f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879856 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879858 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879860 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879866 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879872 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879878 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879884 */     GIR_RootConstrainSelectedInstOperands,
     /*  879885 */     // GIR_Coverage, 28461,
     /*  879885 */     GIR_EraseRootFromParent_Done,
     /*  879886 */   // Label 14111: @879886
     /*  879886 */   GIM_Try, /*On fail goto*//*Label 14112*/ GIMT_Encode4(879959), // Rule ID 28462 //
     /*  879891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  879894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879912 */     // MIs[0] dpp_ctrl
     /*  879912 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879915 */     // MIs[0] row_mask
     /*  879915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879918 */     // MIs[0] bank_mask
     /*  879918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879921 */     // MIs[0] bound_ctrl
     /*  879921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879924 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3612:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$old, v4f16:{ *:[v4f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4f16] } VReg_64_Align2:{ *:[v4f16] }:$old, VReg_64_Align2:{ *:[v4f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879924 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  879927 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  879929 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  879931 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  879933 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  879939 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  879945 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  879951 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  879957 */     GIR_RootConstrainSelectedInstOperands,
     /*  879958 */     // GIR_Coverage, 28462,
     /*  879958 */     GIR_EraseRootFromParent_Done,
     /*  879959 */   // Label 14112: @879959
     /*  879959 */   GIM_Try, /*On fail goto*//*Label 14113*/ GIMT_Encode4(880032), // Rule ID 28463 //
     /*  879964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  879967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  879972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  879975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  879978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  879981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  879985 */     // MIs[0] dpp_ctrl
     /*  879985 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  879988 */     // MIs[0] row_mask
     /*  879988 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  879991 */     // MIs[0] bank_mask
     /*  879991 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  879994 */     // MIs[0] bound_ctrl
     /*  879994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  879997 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3612:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$old, v4f16:{ *:[v4f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4f16] } VReg_64_Align2:{ *:[v4f16] }:$old, VReg_64_Align2:{ *:[v4f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  879997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880002 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880004 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880006 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880012 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880018 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880024 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880030 */     GIR_RootConstrainSelectedInstOperands,
     /*  880031 */     // GIR_Coverage, 28463,
     /*  880031 */     GIR_EraseRootFromParent_Done,
     /*  880032 */   // Label 14113: @880032
     /*  880032 */   GIM_Try, /*On fail goto*//*Label 14114*/ GIMT_Encode4(880105), // Rule ID 28464 //
     /*  880037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  880040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  880048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  880051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  880054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880058 */     // MIs[0] dpp_ctrl
     /*  880058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880061 */     // MIs[0] row_mask
     /*  880061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880064 */     // MIs[0] bank_mask
     /*  880064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880067 */     // MIs[0] bound_ctrl
     /*  880067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880070 */     // (intrinsic_wo_chain:{ *:[v4f16] } 3612:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$old, v4f16:{ *:[v4f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[v4f16] } VReg_64_Align2:{ *:[v4f16] }:$old, VReg_64_Align2:{ *:[v4f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880075 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880077 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880079 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880085 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880091 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880097 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880103 */     GIR_RootConstrainSelectedInstOperands,
     /*  880104 */     // GIR_Coverage, 28464,
     /*  880104 */     GIR_EraseRootFromParent_Done,
     /*  880105 */   // Label 14114: @880105
     /*  880105 */   GIM_Try, /*On fail goto*//*Label 14115*/ GIMT_Encode4(880178), // Rule ID 28465 //
     /*  880110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  880113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64,
     /*  880121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64,
     /*  880124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64,
     /*  880127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880131 */     // MIs[0] dpp_ctrl
     /*  880131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880134 */     // MIs[0] row_mask
     /*  880134 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880137 */     // MIs[0] bank_mask
     /*  880137 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880140 */     // MIs[0] bound_ctrl
     /*  880140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880143 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p0:{ *:[i64] }:$old, p0:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880148 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880150 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880152 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880158 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880164 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880170 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880176 */     GIR_RootConstrainSelectedInstOperands,
     /*  880177 */     // GIR_Coverage, 28465,
     /*  880177 */     GIR_EraseRootFromParent_Done,
     /*  880178 */   // Label 14115: @880178
     /*  880178 */   GIM_Try, /*On fail goto*//*Label 14116*/ GIMT_Encode4(880251), // Rule ID 28466 //
     /*  880183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  880186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64,
     /*  880194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64,
     /*  880197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64,
     /*  880200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880204 */     // MIs[0] dpp_ctrl
     /*  880204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880207 */     // MIs[0] row_mask
     /*  880207 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880210 */     // MIs[0] bank_mask
     /*  880210 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880213 */     // MIs[0] bound_ctrl
     /*  880213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880216 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p0:{ *:[i64] }:$old, p0:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880221 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880223 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880225 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880231 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880237 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880243 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880249 */     GIR_RootConstrainSelectedInstOperands,
     /*  880250 */     // GIR_Coverage, 28466,
     /*  880250 */     GIR_EraseRootFromParent_Done,
     /*  880251 */   // Label 14116: @880251
     /*  880251 */   GIM_Try, /*On fail goto*//*Label 14117*/ GIMT_Encode4(880324), // Rule ID 28467 //
     /*  880256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  880259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64,
     /*  880267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64,
     /*  880270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64,
     /*  880273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880277 */     // MIs[0] dpp_ctrl
     /*  880277 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880280 */     // MIs[0] row_mask
     /*  880280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880283 */     // MIs[0] bank_mask
     /*  880283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880286 */     // MIs[0] bound_ctrl
     /*  880286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880289 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p0:{ *:[i64] }:$old, p0:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880294 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880296 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880298 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880304 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880310 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880316 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880322 */     GIR_RootConstrainSelectedInstOperands,
     /*  880323 */     // GIR_Coverage, 28467,
     /*  880323 */     GIR_EraseRootFromParent_Done,
     /*  880324 */   // Label 14117: @880324
     /*  880324 */   GIM_Try, /*On fail goto*//*Label 14118*/ GIMT_Encode4(880397), // Rule ID 28468 //
     /*  880329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  880332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64,
     /*  880340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64,
     /*  880343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64,
     /*  880346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880350 */     // MIs[0] dpp_ctrl
     /*  880350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880353 */     // MIs[0] row_mask
     /*  880353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880356 */     // MIs[0] bank_mask
     /*  880356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880359 */     // MIs[0] bound_ctrl
     /*  880359 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880362 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p0:{ *:[i64] }:$old, p0:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880367 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880369 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880371 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880377 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880383 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880389 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880395 */     GIR_RootConstrainSelectedInstOperands,
     /*  880396 */     // GIR_Coverage, 28468,
     /*  880396 */     GIR_EraseRootFromParent_Done,
     /*  880397 */   // Label 14118: @880397
     /*  880397 */   GIM_Try, /*On fail goto*//*Label 14119*/ GIMT_Encode4(880470), // Rule ID 28469 //
     /*  880402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  880405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64,
     /*  880413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64,
     /*  880416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64,
     /*  880419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880423 */     // MIs[0] dpp_ctrl
     /*  880423 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880426 */     // MIs[0] row_mask
     /*  880426 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880429 */     // MIs[0] bank_mask
     /*  880429 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880432 */     // MIs[0] bound_ctrl
     /*  880432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880435 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p0:{ *:[i64] }:$old, p0:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880440 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880442 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880444 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880450 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880456 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880462 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880468 */     GIR_RootConstrainSelectedInstOperands,
     /*  880469 */     // GIR_Coverage, 28469,
     /*  880469 */     GIR_EraseRootFromParent_Done,
     /*  880470 */   // Label 14119: @880470
     /*  880470 */   GIM_Try, /*On fail goto*//*Label 14120*/ GIMT_Encode4(880543), // Rule ID 28470 //
     /*  880475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  880478 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880483 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p1s64,
     /*  880486 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p1s64,
     /*  880489 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p1s64,
     /*  880492 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880496 */     // MIs[0] dpp_ctrl
     /*  880496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880499 */     // MIs[0] row_mask
     /*  880499 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880502 */     // MIs[0] bank_mask
     /*  880502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880505 */     // MIs[0] bound_ctrl
     /*  880505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880508 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p1:{ *:[i64] }:$old, p1:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880513 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880515 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880517 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880523 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880529 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880535 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880541 */     GIR_RootConstrainSelectedInstOperands,
     /*  880542 */     // GIR_Coverage, 28470,
     /*  880542 */     GIR_EraseRootFromParent_Done,
     /*  880543 */   // Label 14120: @880543
     /*  880543 */   GIM_Try, /*On fail goto*//*Label 14121*/ GIMT_Encode4(880616), // Rule ID 28471 //
     /*  880548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  880551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p1s64,
     /*  880559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p1s64,
     /*  880562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p1s64,
     /*  880565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880569 */     // MIs[0] dpp_ctrl
     /*  880569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880572 */     // MIs[0] row_mask
     /*  880572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880575 */     // MIs[0] bank_mask
     /*  880575 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880578 */     // MIs[0] bound_ctrl
     /*  880578 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880581 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p1:{ *:[i64] }:$old, p1:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880586 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880588 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880590 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880596 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880602 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880608 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880614 */     GIR_RootConstrainSelectedInstOperands,
     /*  880615 */     // GIR_Coverage, 28471,
     /*  880615 */     GIR_EraseRootFromParent_Done,
     /*  880616 */   // Label 14121: @880616
     /*  880616 */   GIM_Try, /*On fail goto*//*Label 14122*/ GIMT_Encode4(880689), // Rule ID 28472 //
     /*  880621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  880624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880629 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p1s64,
     /*  880632 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p1s64,
     /*  880635 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p1s64,
     /*  880638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880642 */     // MIs[0] dpp_ctrl
     /*  880642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880645 */     // MIs[0] row_mask
     /*  880645 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880648 */     // MIs[0] bank_mask
     /*  880648 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880651 */     // MIs[0] bound_ctrl
     /*  880651 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880654 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p1:{ *:[i64] }:$old, p1:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880659 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880661 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880663 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880669 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880675 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880681 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880687 */     GIR_RootConstrainSelectedInstOperands,
     /*  880688 */     // GIR_Coverage, 28472,
     /*  880688 */     GIR_EraseRootFromParent_Done,
     /*  880689 */   // Label 14122: @880689
     /*  880689 */   GIM_Try, /*On fail goto*//*Label 14123*/ GIMT_Encode4(880762), // Rule ID 28473 //
     /*  880694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  880697 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880702 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p1s64,
     /*  880705 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p1s64,
     /*  880708 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p1s64,
     /*  880711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880715 */     // MIs[0] dpp_ctrl
     /*  880715 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880718 */     // MIs[0] row_mask
     /*  880718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880721 */     // MIs[0] bank_mask
     /*  880721 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880724 */     // MIs[0] bound_ctrl
     /*  880724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880727 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p1:{ *:[i64] }:$old, p1:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880732 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880734 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880736 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880742 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880748 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880754 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880760 */     GIR_RootConstrainSelectedInstOperands,
     /*  880761 */     // GIR_Coverage, 28473,
     /*  880761 */     GIR_EraseRootFromParent_Done,
     /*  880762 */   // Label 14123: @880762
     /*  880762 */   GIM_Try, /*On fail goto*//*Label 14124*/ GIMT_Encode4(880835), // Rule ID 28474 //
     /*  880767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  880770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p1s64,
     /*  880778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p1s64,
     /*  880781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p1s64,
     /*  880784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880788 */     // MIs[0] dpp_ctrl
     /*  880788 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880791 */     // MIs[0] row_mask
     /*  880791 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880794 */     // MIs[0] bank_mask
     /*  880794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880797 */     // MIs[0] bound_ctrl
     /*  880797 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880800 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p1:{ *:[i64] }:$old, p1:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880805 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880807 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880809 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880815 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880821 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880827 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880833 */     GIR_RootConstrainSelectedInstOperands,
     /*  880834 */     // GIR_Coverage, 28474,
     /*  880834 */     GIR_EraseRootFromParent_Done,
     /*  880835 */   // Label 14124: @880835
     /*  880835 */   GIM_Try, /*On fail goto*//*Label 14125*/ GIMT_Encode4(880908), // Rule ID 28475 //
     /*  880840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  880843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p4s64,
     /*  880851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p4s64,
     /*  880854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p4s64,
     /*  880857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880861 */     // MIs[0] dpp_ctrl
     /*  880861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880864 */     // MIs[0] row_mask
     /*  880864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880867 */     // MIs[0] bank_mask
     /*  880867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880870 */     // MIs[0] bound_ctrl
     /*  880870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880873 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p4:{ *:[i64] }:$old, p4:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880878 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880880 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880882 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880888 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880894 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880900 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880906 */     GIR_RootConstrainSelectedInstOperands,
     /*  880907 */     // GIR_Coverage, 28475,
     /*  880907 */     GIR_EraseRootFromParent_Done,
     /*  880908 */   // Label 14125: @880908
     /*  880908 */   GIM_Try, /*On fail goto*//*Label 14126*/ GIMT_Encode4(880981), // Rule ID 28476 //
     /*  880913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  880916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p4s64,
     /*  880924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p4s64,
     /*  880927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p4s64,
     /*  880930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  880934 */     // MIs[0] dpp_ctrl
     /*  880934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  880937 */     // MIs[0] row_mask
     /*  880937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  880940 */     // MIs[0] bank_mask
     /*  880940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  880943 */     // MIs[0] bound_ctrl
     /*  880943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  880946 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p4:{ *:[i64] }:$old, p4:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  880946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  880949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  880951 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  880953 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  880955 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  880961 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  880967 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  880973 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  880979 */     GIR_RootConstrainSelectedInstOperands,
     /*  880980 */     // GIR_Coverage, 28476,
     /*  880980 */     GIR_EraseRootFromParent_Done,
     /*  880981 */   // Label 14126: @880981
     /*  880981 */   GIM_Try, /*On fail goto*//*Label 14127*/ GIMT_Encode4(881054), // Rule ID 28477 //
     /*  880986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  880989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  880994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p4s64,
     /*  880997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p4s64,
     /*  881000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p4s64,
     /*  881003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  881007 */     // MIs[0] dpp_ctrl
     /*  881007 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881010 */     // MIs[0] row_mask
     /*  881010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  881013 */     // MIs[0] bank_mask
     /*  881013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881016 */     // MIs[0] bound_ctrl
     /*  881016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  881019 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p4:{ *:[i64] }:$old, p4:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  881019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  881022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881024 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  881026 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  881028 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  881034 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  881040 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  881046 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  881052 */     GIR_RootConstrainSelectedInstOperands,
     /*  881053 */     // GIR_Coverage, 28477,
     /*  881053 */     GIR_EraseRootFromParent_Done,
     /*  881054 */   // Label 14127: @881054
     /*  881054 */   GIM_Try, /*On fail goto*//*Label 14128*/ GIMT_Encode4(881127), // Rule ID 28478 //
     /*  881059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  881062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  881067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p4s64,
     /*  881070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p4s64,
     /*  881073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p4s64,
     /*  881076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  881080 */     // MIs[0] dpp_ctrl
     /*  881080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881083 */     // MIs[0] row_mask
     /*  881083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  881086 */     // MIs[0] bank_mask
     /*  881086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881089 */     // MIs[0] bound_ctrl
     /*  881089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  881092 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p4:{ *:[i64] }:$old, p4:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  881092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  881095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881097 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  881099 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  881101 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  881107 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  881113 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  881119 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  881125 */     GIR_RootConstrainSelectedInstOperands,
     /*  881126 */     // GIR_Coverage, 28478,
     /*  881126 */     GIR_EraseRootFromParent_Done,
     /*  881127 */   // Label 14128: @881127
     /*  881127 */   GIM_Try, /*On fail goto*//*Label 14129*/ GIMT_Encode4(881200), // Rule ID 28479 //
     /*  881132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  881135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
     /*  881140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p4s64,
     /*  881143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p4s64,
     /*  881146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p4s64,
     /*  881149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  881153 */     // MIs[0] dpp_ctrl
     /*  881153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881156 */     // MIs[0] row_mask
     /*  881156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  881159 */     // MIs[0] bank_mask
     /*  881159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881162 */     // MIs[0] bound_ctrl
     /*  881162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  881165 */     // (intrinsic_wo_chain:{ *:[i64] } 3612:{ *:[iPTR] }, p4:{ *:[i64] }:$old, p4:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bound_ctrl))
     /*  881165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
     /*  881168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881170 */     GIR_RootToRootCopy, /*OpIdx*/2, // old
     /*  881172 */     GIR_RootToRootCopy, /*OpIdx*/3, // src
     /*  881174 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
     /*  881180 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
     /*  881186 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
     /*  881192 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
     /*  881198 */     GIR_RootConstrainSelectedInstOperands,
     /*  881199 */     // GIR_Coverage, 28479,
     /*  881199 */     GIR_EraseRootFromParent_Done,
     /*  881200 */   // Label 14129: @881200
     /*  881200 */   GIM_Try, /*On fail goto*//*Label 14130*/ GIMT_Encode4(881267), // Rule ID 8288 //
     /*  881205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  881208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881219 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  881222 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881229 */     // MIs[0] matrix_a_fmt
     /*  881229 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881232 */     // MIs[0] matrix_b_fmt
     /*  881232 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881235 */     // MIs[0] src2_modifiers
     /*  881235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881238 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  881241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881243 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881245 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881247 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881253 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881255 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881257 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881262 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881265 */     GIR_RootConstrainSelectedInstOperands,
     /*  881266 */     // GIR_Coverage, 8288,
     /*  881266 */     GIR_EraseRootFromParent_Done,
     /*  881267 */   // Label 14130: @881267
     /*  881267 */   GIM_Try, /*On fail goto*//*Label 14131*/ GIMT_Encode4(881334), // Rule ID 8289 //
     /*  881272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  881275 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881280 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881286 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  881289 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881296 */     // MIs[0] matrix_a_fmt
     /*  881296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881299 */     // MIs[0] matrix_b_fmt
     /*  881299 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881302 */     // MIs[0] src2_modifiers
     /*  881302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881305 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  881308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881310 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881312 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881314 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881320 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881322 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881324 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881332 */     GIR_RootConstrainSelectedInstOperands,
     /*  881333 */     // GIR_Coverage, 8289,
     /*  881333 */     GIR_EraseRootFromParent_Done,
     /*  881334 */   // Label 14131: @881334
     /*  881334 */   GIM_Try, /*On fail goto*//*Label 14132*/ GIMT_Encode4(881401), // Rule ID 8290 //
     /*  881339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  881342 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881347 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881353 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  881356 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881363 */     // MIs[0] matrix_a_fmt
     /*  881363 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881366 */     // MIs[0] matrix_b_fmt
     /*  881366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881369 */     // MIs[0] src2_modifiers
     /*  881369 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881372 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  881375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881377 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881379 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881381 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881387 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881389 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881391 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881399 */     GIR_RootConstrainSelectedInstOperands,
     /*  881400 */     // GIR_Coverage, 8290,
     /*  881400 */     GIR_EraseRootFromParent_Done,
     /*  881401 */   // Label 14132: @881401
     /*  881401 */   GIM_Try, /*On fail goto*//*Label 14133*/ GIMT_Encode4(881468), // Rule ID 8291 //
     /*  881406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  881409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881420 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  881423 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881430 */     // MIs[0] matrix_a_fmt
     /*  881430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881433 */     // MIs[0] matrix_b_fmt
     /*  881433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881436 */     // MIs[0] src2_modifiers
     /*  881436 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881439 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  881442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881444 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881446 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881448 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881454 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881456 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881458 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881466 */     GIR_RootConstrainSelectedInstOperands,
     /*  881467 */     // GIR_Coverage, 8291,
     /*  881467 */     GIR_EraseRootFromParent_Done,
     /*  881468 */   // Label 14133: @881468
     /*  881468 */   GIM_Try, /*On fail goto*//*Label 14134*/ GIMT_Encode4(881535), // Rule ID 8292 //
     /*  881473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  881476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881487 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  881490 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881497 */     // MIs[0] matrix_a_fmt
     /*  881497 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881500 */     // MIs[0] matrix_b_fmt
     /*  881500 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881503 */     // MIs[0] src2_modifiers
     /*  881503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881506 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  881509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881511 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881513 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881515 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881521 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881523 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881525 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881533 */     GIR_RootConstrainSelectedInstOperands,
     /*  881534 */     // GIR_Coverage, 8292,
     /*  881534 */     GIR_EraseRootFromParent_Done,
     /*  881535 */   // Label 14134: @881535
     /*  881535 */   GIM_Try, /*On fail goto*//*Label 14135*/ GIMT_Encode4(881602), // Rule ID 8318 //
     /*  881540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  881543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881554 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  881557 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881564 */     // MIs[0] matrix_a_fmt
     /*  881564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881567 */     // MIs[0] matrix_b_fmt
     /*  881567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881570 */     // MIs[0] src2_modifiers
     /*  881570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881573 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  881576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881578 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881580 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881582 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881588 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881590 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881592 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881600 */     GIR_RootConstrainSelectedInstOperands,
     /*  881601 */     // GIR_Coverage, 8318,
     /*  881601 */     GIR_EraseRootFromParent_Done,
     /*  881602 */   // Label 14135: @881602
     /*  881602 */   GIM_Try, /*On fail goto*//*Label 14136*/ GIMT_Encode4(881669), // Rule ID 8319 //
     /*  881607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  881610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881621 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  881624 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881631 */     // MIs[0] matrix_a_fmt
     /*  881631 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881634 */     // MIs[0] matrix_b_fmt
     /*  881634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881637 */     // MIs[0] src2_modifiers
     /*  881637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881640 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  881643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881645 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881647 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881649 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881655 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881657 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881659 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881667 */     GIR_RootConstrainSelectedInstOperands,
     /*  881668 */     // GIR_Coverage, 8319,
     /*  881668 */     GIR_EraseRootFromParent_Done,
     /*  881669 */   // Label 14136: @881669
     /*  881669 */   GIM_Try, /*On fail goto*//*Label 14137*/ GIMT_Encode4(881736), // Rule ID 8320 //
     /*  881674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  881677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881688 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  881691 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881698 */     // MIs[0] matrix_a_fmt
     /*  881698 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881701 */     // MIs[0] matrix_b_fmt
     /*  881701 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881704 */     // MIs[0] src2_modifiers
     /*  881704 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881707 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  881710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881712 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881714 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881716 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881722 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881724 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881726 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881731 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881734 */     GIR_RootConstrainSelectedInstOperands,
     /*  881735 */     // GIR_Coverage, 8320,
     /*  881735 */     GIR_EraseRootFromParent_Done,
     /*  881736 */   // Label 14137: @881736
     /*  881736 */   GIM_Try, /*On fail goto*//*Label 14138*/ GIMT_Encode4(881803), // Rule ID 8321 //
     /*  881741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  881744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881752 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881755 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  881758 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881765 */     // MIs[0] matrix_a_fmt
     /*  881765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881768 */     // MIs[0] matrix_b_fmt
     /*  881768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881771 */     // MIs[0] src2_modifiers
     /*  881771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881774 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  881777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881781 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881783 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881789 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881791 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881793 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881801 */     GIR_RootConstrainSelectedInstOperands,
     /*  881802 */     // GIR_Coverage, 8321,
     /*  881802 */     GIR_EraseRootFromParent_Done,
     /*  881803 */   // Label 14138: @881803
     /*  881803 */   GIM_Try, /*On fail goto*//*Label 14139*/ GIMT_Encode4(881870), // Rule ID 8322 //
     /*  881808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  881811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881819 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881822 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  881825 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881832 */     // MIs[0] matrix_a_fmt
     /*  881832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881835 */     // MIs[0] matrix_b_fmt
     /*  881835 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881838 */     // MIs[0] src2_modifiers
     /*  881838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881841 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  881844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881846 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881848 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881850 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881856 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881858 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881860 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881862 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881865 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881868 */     GIR_RootConstrainSelectedInstOperands,
     /*  881869 */     // GIR_Coverage, 8322,
     /*  881869 */     GIR_EraseRootFromParent_Done,
     /*  881870 */   // Label 14139: @881870
     /*  881870 */   GIM_Try, /*On fail goto*//*Label 14140*/ GIMT_Encode4(881937), // Rule ID 8348 //
     /*  881875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  881878 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881883 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881886 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881889 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  881892 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881899 */     // MIs[0] matrix_a_fmt
     /*  881899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881902 */     // MIs[0] matrix_b_fmt
     /*  881902 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881905 */     // MIs[0] src2_modifiers
     /*  881905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881908 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  881911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881913 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881915 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881917 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881923 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881925 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881927 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881929 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881932 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881935 */     GIR_RootConstrainSelectedInstOperands,
     /*  881936 */     // GIR_Coverage, 8348,
     /*  881936 */     GIR_EraseRootFromParent_Done,
     /*  881937 */   // Label 14140: @881937
     /*  881937 */   GIM_Try, /*On fail goto*//*Label 14141*/ GIMT_Encode4(882004), // Rule ID 8349 //
     /*  881942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  881945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  881950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  881953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  881956 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  881959 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  881962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  881966 */     // MIs[0] matrix_a_fmt
     /*  881966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  881969 */     // MIs[0] matrix_b_fmt
     /*  881969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  881972 */     // MIs[0] src2_modifiers
     /*  881972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  881975 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  881975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  881978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  881980 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  881982 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  881984 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  881990 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  881992 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  881994 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  881996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  881999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882002 */     GIR_RootConstrainSelectedInstOperands,
     /*  882003 */     // GIR_Coverage, 8349,
     /*  882003 */     GIR_EraseRootFromParent_Done,
     /*  882004 */   // Label 14141: @882004
     /*  882004 */   GIM_Try, /*On fail goto*//*Label 14142*/ GIMT_Encode4(882071), // Rule ID 8350 //
     /*  882009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  882012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  882023 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  882026 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882033 */     // MIs[0] matrix_a_fmt
     /*  882033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882036 */     // MIs[0] matrix_b_fmt
     /*  882036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882039 */     // MIs[0] src2_modifiers
     /*  882039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882042 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  882045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882047 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882049 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882051 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882057 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882059 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882061 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882069 */     GIR_RootConstrainSelectedInstOperands,
     /*  882070 */     // GIR_Coverage, 8350,
     /*  882070 */     GIR_EraseRootFromParent_Done,
     /*  882071 */   // Label 14142: @882071
     /*  882071 */   GIM_Try, /*On fail goto*//*Label 14143*/ GIMT_Encode4(882138), // Rule ID 8351 //
     /*  882076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  882079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  882090 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  882093 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882100 */     // MIs[0] matrix_a_fmt
     /*  882100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882103 */     // MIs[0] matrix_b_fmt
     /*  882103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882106 */     // MIs[0] src2_modifiers
     /*  882106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882109 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  882112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882114 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882116 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882118 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882124 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882126 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882128 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882133 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882136 */     GIR_RootConstrainSelectedInstOperands,
     /*  882137 */     // GIR_Coverage, 8351,
     /*  882137 */     GIR_EraseRootFromParent_Done,
     /*  882138 */   // Label 14143: @882138
     /*  882138 */   GIM_Try, /*On fail goto*//*Label 14144*/ GIMT_Encode4(882205), // Rule ID 8352 //
     /*  882143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  882146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  882157 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  882160 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882167 */     // MIs[0] matrix_a_fmt
     /*  882167 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882170 */     // MIs[0] matrix_b_fmt
     /*  882170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882173 */     // MIs[0] src2_modifiers
     /*  882173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882176 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  882179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882181 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882183 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882185 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882191 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882193 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882195 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882203 */     GIR_RootConstrainSelectedInstOperands,
     /*  882204 */     // GIR_Coverage, 8352,
     /*  882204 */     GIR_EraseRootFromParent_Done,
     /*  882205 */   // Label 14144: @882205
     /*  882205 */   GIM_Try, /*On fail goto*//*Label 14145*/ GIMT_Encode4(882272), // Rule ID 8378 //
     /*  882210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  882213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882224 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  882227 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882234 */     // MIs[0] matrix_a_fmt
     /*  882234 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882237 */     // MIs[0] matrix_b_fmt
     /*  882237 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882240 */     // MIs[0] src2_modifiers
     /*  882240 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882243 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  882246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882248 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882250 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882252 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882258 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882260 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882262 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882270 */     GIR_RootConstrainSelectedInstOperands,
     /*  882271 */     // GIR_Coverage, 8378,
     /*  882271 */     GIR_EraseRootFromParent_Done,
     /*  882272 */   // Label 14145: @882272
     /*  882272 */   GIM_Try, /*On fail goto*//*Label 14146*/ GIMT_Encode4(882339), // Rule ID 8379 //
     /*  882277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  882280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882288 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882291 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  882294 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882301 */     // MIs[0] matrix_a_fmt
     /*  882301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882304 */     // MIs[0] matrix_b_fmt
     /*  882304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882307 */     // MIs[0] src2_modifiers
     /*  882307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882310 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  882313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882315 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882317 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882319 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882325 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882327 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882329 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882334 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882337 */     GIR_RootConstrainSelectedInstOperands,
     /*  882338 */     // GIR_Coverage, 8379,
     /*  882338 */     GIR_EraseRootFromParent_Done,
     /*  882339 */   // Label 14146: @882339
     /*  882339 */   GIM_Try, /*On fail goto*//*Label 14147*/ GIMT_Encode4(882406), // Rule ID 8380 //
     /*  882344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  882347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882355 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882358 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  882361 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882368 */     // MIs[0] matrix_a_fmt
     /*  882368 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882371 */     // MIs[0] matrix_b_fmt
     /*  882371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882374 */     // MIs[0] src2_modifiers
     /*  882374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882377 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  882380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882382 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882384 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882386 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882392 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882394 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882396 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882404 */     GIR_RootConstrainSelectedInstOperands,
     /*  882405 */     // GIR_Coverage, 8380,
     /*  882405 */     GIR_EraseRootFromParent_Done,
     /*  882406 */   // Label 14147: @882406
     /*  882406 */   GIM_Try, /*On fail goto*//*Label 14148*/ GIMT_Encode4(882473), // Rule ID 8381 //
     /*  882411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  882414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882425 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  882428 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882435 */     // MIs[0] matrix_a_fmt
     /*  882435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882438 */     // MIs[0] matrix_b_fmt
     /*  882438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882441 */     // MIs[0] src2_modifiers
     /*  882441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882444 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  882447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882449 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882451 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882453 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882459 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882461 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882463 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882471 */     GIR_RootConstrainSelectedInstOperands,
     /*  882472 */     // GIR_Coverage, 8381,
     /*  882472 */     GIR_EraseRootFromParent_Done,
     /*  882473 */   // Label 14148: @882473
     /*  882473 */   GIM_Try, /*On fail goto*//*Label 14149*/ GIMT_Encode4(882540), // Rule ID 8382 //
     /*  882478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  882481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882489 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882492 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  882495 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882502 */     // MIs[0] matrix_a_fmt
     /*  882502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882505 */     // MIs[0] matrix_b_fmt
     /*  882505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882508 */     // MIs[0] src2_modifiers
     /*  882508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882511 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  882514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882516 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882518 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882520 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882526 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882528 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882530 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882538 */     GIR_RootConstrainSelectedInstOperands,
     /*  882539 */     // GIR_Coverage, 8382,
     /*  882539 */     GIR_EraseRootFromParent_Done,
     /*  882540 */   // Label 14149: @882540
     /*  882540 */   GIM_Try, /*On fail goto*//*Label 14150*/ GIMT_Encode4(882607), // Rule ID 8408 //
     /*  882545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  882548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882556 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882559 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  882562 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882569 */     // MIs[0] matrix_a_fmt
     /*  882569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882572 */     // MIs[0] matrix_b_fmt
     /*  882572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882575 */     // MIs[0] src2_modifiers
     /*  882575 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882578 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  882581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882583 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882585 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882587 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882593 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882595 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882597 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882605 */     GIR_RootConstrainSelectedInstOperands,
     /*  882606 */     // GIR_Coverage, 8408,
     /*  882606 */     GIR_EraseRootFromParent_Done,
     /*  882607 */   // Label 14150: @882607
     /*  882607 */   GIM_Try, /*On fail goto*//*Label 14151*/ GIMT_Encode4(882674), // Rule ID 8409 //
     /*  882612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  882615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882626 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  882629 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882636 */     // MIs[0] matrix_a_fmt
     /*  882636 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882639 */     // MIs[0] matrix_b_fmt
     /*  882639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882642 */     // MIs[0] src2_modifiers
     /*  882642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882645 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  882648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882650 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882652 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882654 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882660 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882662 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882664 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882672 */     GIR_RootConstrainSelectedInstOperands,
     /*  882673 */     // GIR_Coverage, 8409,
     /*  882673 */     GIR_EraseRootFromParent_Done,
     /*  882674 */   // Label 14151: @882674
     /*  882674 */   GIM_Try, /*On fail goto*//*Label 14152*/ GIMT_Encode4(882741), // Rule ID 8410 //
     /*  882679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  882682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882693 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  882696 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882703 */     // MIs[0] matrix_a_fmt
     /*  882703 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882706 */     // MIs[0] matrix_b_fmt
     /*  882706 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882709 */     // MIs[0] src2_modifiers
     /*  882709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882712 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  882715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882717 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882719 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882721 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882727 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882729 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882731 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882739 */     GIR_RootConstrainSelectedInstOperands,
     /*  882740 */     // GIR_Coverage, 8410,
     /*  882740 */     GIR_EraseRootFromParent_Done,
     /*  882741 */   // Label 14152: @882741
     /*  882741 */   GIM_Try, /*On fail goto*//*Label 14153*/ GIMT_Encode4(882808), // Rule ID 8411 //
     /*  882746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  882749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882760 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  882763 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882770 */     // MIs[0] matrix_a_fmt
     /*  882770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882773 */     // MIs[0] matrix_b_fmt
     /*  882773 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882776 */     // MIs[0] src2_modifiers
     /*  882776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882779 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  882782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882784 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882786 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882788 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882794 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882796 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882798 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882806 */     GIR_RootConstrainSelectedInstOperands,
     /*  882807 */     // GIR_Coverage, 8411,
     /*  882807 */     GIR_EraseRootFromParent_Done,
     /*  882808 */   // Label 14153: @882808
     /*  882808 */   GIM_Try, /*On fail goto*//*Label 14154*/ GIMT_Encode4(882875), // Rule ID 8412 //
     /*  882813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  882816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882827 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  882830 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882837 */     // MIs[0] matrix_a_fmt
     /*  882837 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882840 */     // MIs[0] matrix_b_fmt
     /*  882840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882843 */     // MIs[0] src2_modifiers
     /*  882843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882846 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  882849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882851 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882853 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882855 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882861 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882863 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882865 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882873 */     GIR_RootConstrainSelectedInstOperands,
     /*  882874 */     // GIR_Coverage, 8412,
     /*  882874 */     GIR_EraseRootFromParent_Done,
     /*  882875 */   // Label 14154: @882875
     /*  882875 */   GIM_Try, /*On fail goto*//*Label 14155*/ GIMT_Encode4(882942), // Rule ID 8438 //
     /*  882880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  882883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882894 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  882897 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882904 */     // MIs[0] matrix_a_fmt
     /*  882904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882907 */     // MIs[0] matrix_b_fmt
     /*  882907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882910 */     // MIs[0] src2_modifiers
     /*  882910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882913 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  882916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882918 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882920 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882922 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882928 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882930 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882932 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  882934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  882940 */     GIR_RootConstrainSelectedInstOperands,
     /*  882941 */     // GIR_Coverage, 8438,
     /*  882941 */     GIR_EraseRootFromParent_Done,
     /*  882942 */   // Label 14155: @882942
     /*  882942 */   GIM_Try, /*On fail goto*//*Label 14156*/ GIMT_Encode4(883009), // Rule ID 8439 //
     /*  882947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  882950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  882955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  882958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  882961 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  882964 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  882967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  882971 */     // MIs[0] matrix_a_fmt
     /*  882971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  882974 */     // MIs[0] matrix_b_fmt
     /*  882974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  882977 */     // MIs[0] src2_modifiers
     /*  882977 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  882980 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  882980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  882983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  882985 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  882987 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  882989 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  882995 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  882997 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  882999 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883007 */     GIR_RootConstrainSelectedInstOperands,
     /*  883008 */     // GIR_Coverage, 8439,
     /*  883008 */     GIR_EraseRootFromParent_Done,
     /*  883009 */   // Label 14156: @883009
     /*  883009 */   GIM_Try, /*On fail goto*//*Label 14157*/ GIMT_Encode4(883076), // Rule ID 8440 //
     /*  883014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  883017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883025 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  883028 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  883031 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883038 */     // MIs[0] matrix_a_fmt
     /*  883038 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883041 */     // MIs[0] matrix_b_fmt
     /*  883041 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883044 */     // MIs[0] src2_modifiers
     /*  883044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883047 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  883050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883052 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883054 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883056 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883062 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883064 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883066 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883074 */     GIR_RootConstrainSelectedInstOperands,
     /*  883075 */     // GIR_Coverage, 8440,
     /*  883075 */     GIR_EraseRootFromParent_Done,
     /*  883076 */   // Label 14157: @883076
     /*  883076 */   GIM_Try, /*On fail goto*//*Label 14158*/ GIMT_Encode4(883143), // Rule ID 8441 //
     /*  883081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  883084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  883095 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  883098 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883105 */     // MIs[0] matrix_a_fmt
     /*  883105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883108 */     // MIs[0] matrix_b_fmt
     /*  883108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883111 */     // MIs[0] src2_modifiers
     /*  883111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883114 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  883117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883119 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883121 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883123 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883129 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883131 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883133 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883141 */     GIR_RootConstrainSelectedInstOperands,
     /*  883142 */     // GIR_Coverage, 8441,
     /*  883142 */     GIR_EraseRootFromParent_Done,
     /*  883143 */   // Label 14158: @883143
     /*  883143 */   GIM_Try, /*On fail goto*//*Label 14159*/ GIMT_Encode4(883210), // Rule ID 8442 //
     /*  883148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  883151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883159 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  883162 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  883165 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883172 */     // MIs[0] matrix_a_fmt
     /*  883172 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883175 */     // MIs[0] matrix_b_fmt
     /*  883175 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883178 */     // MIs[0] src2_modifiers
     /*  883178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883181 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  883184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883186 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883188 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883190 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883196 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883198 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883200 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883208 */     GIR_RootConstrainSelectedInstOperands,
     /*  883209 */     // GIR_Coverage, 8442,
     /*  883209 */     GIR_EraseRootFromParent_Done,
     /*  883210 */   // Label 14159: @883210
     /*  883210 */   GIM_Try, /*On fail goto*//*Label 14160*/ GIMT_Encode4(883277), // Rule ID 8468 //
     /*  883215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  883218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883223 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883229 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  883232 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883239 */     // MIs[0] matrix_a_fmt
     /*  883239 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883242 */     // MIs[0] matrix_b_fmt
     /*  883242 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883245 */     // MIs[0] src2_modifiers
     /*  883245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883248 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  883251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883253 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883255 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883257 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883263 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883265 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883267 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883269 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883275 */     GIR_RootConstrainSelectedInstOperands,
     /*  883276 */     // GIR_Coverage, 8468,
     /*  883276 */     GIR_EraseRootFromParent_Done,
     /*  883277 */   // Label 14160: @883277
     /*  883277 */   GIM_Try, /*On fail goto*//*Label 14161*/ GIMT_Encode4(883344), // Rule ID 8469 //
     /*  883282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  883285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883296 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  883299 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883306 */     // MIs[0] matrix_a_fmt
     /*  883306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883309 */     // MIs[0] matrix_b_fmt
     /*  883309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883312 */     // MIs[0] src2_modifiers
     /*  883312 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883315 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  883318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883320 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883322 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883324 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883330 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883332 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883334 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883339 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883342 */     GIR_RootConstrainSelectedInstOperands,
     /*  883343 */     // GIR_Coverage, 8469,
     /*  883343 */     GIR_EraseRootFromParent_Done,
     /*  883344 */   // Label 14161: @883344
     /*  883344 */   GIM_Try, /*On fail goto*//*Label 14162*/ GIMT_Encode4(883411), // Rule ID 8470 //
     /*  883349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  883352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883360 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883363 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  883366 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883373 */     // MIs[0] matrix_a_fmt
     /*  883373 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883376 */     // MIs[0] matrix_b_fmt
     /*  883376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883379 */     // MIs[0] src2_modifiers
     /*  883379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883382 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  883385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883387 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883389 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883391 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883397 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883399 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883401 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883403 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883406 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883409 */     GIR_RootConstrainSelectedInstOperands,
     /*  883410 */     // GIR_Coverage, 8470,
     /*  883410 */     GIR_EraseRootFromParent_Done,
     /*  883411 */   // Label 14162: @883411
     /*  883411 */   GIM_Try, /*On fail goto*//*Label 14163*/ GIMT_Encode4(883478), // Rule ID 8471 //
     /*  883416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  883419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883430 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  883433 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883440 */     // MIs[0] matrix_a_fmt
     /*  883440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883443 */     // MIs[0] matrix_b_fmt
     /*  883443 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883446 */     // MIs[0] src2_modifiers
     /*  883446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883449 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  883452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883454 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883456 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883458 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883464 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883466 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883468 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883473 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883476 */     GIR_RootConstrainSelectedInstOperands,
     /*  883477 */     // GIR_Coverage, 8471,
     /*  883477 */     GIR_EraseRootFromParent_Done,
     /*  883478 */   // Label 14163: @883478
     /*  883478 */   GIM_Try, /*On fail goto*//*Label 14164*/ GIMT_Encode4(883545), // Rule ID 8472 //
     /*  883483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  883486 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883491 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883497 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  883500 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883507 */     // MIs[0] matrix_a_fmt
     /*  883507 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883510 */     // MIs[0] matrix_b_fmt
     /*  883510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883513 */     // MIs[0] src2_modifiers
     /*  883513 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883516 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  883519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883521 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883523 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883525 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883531 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883533 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883535 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883540 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883543 */     GIR_RootConstrainSelectedInstOperands,
     /*  883544 */     // GIR_Coverage, 8472,
     /*  883544 */     GIR_EraseRootFromParent_Done,
     /*  883545 */   // Label 14164: @883545
     /*  883545 */   GIM_Try, /*On fail goto*//*Label 14165*/ GIMT_Encode4(883612), // Rule ID 8498 //
     /*  883550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  883553 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883558 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883561 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883564 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  883567 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883574 */     // MIs[0] matrix_a_fmt
     /*  883574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883577 */     // MIs[0] matrix_b_fmt
     /*  883577 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883580 */     // MIs[0] src2_modifiers
     /*  883580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883583 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  883586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883588 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883590 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883592 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883598 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883600 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883602 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883607 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883610 */     GIR_RootConstrainSelectedInstOperands,
     /*  883611 */     // GIR_Coverage, 8498,
     /*  883611 */     GIR_EraseRootFromParent_Done,
     /*  883612 */   // Label 14165: @883612
     /*  883612 */   GIM_Try, /*On fail goto*//*Label 14166*/ GIMT_Encode4(883679), // Rule ID 8499 //
     /*  883617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  883620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883631 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  883634 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883641 */     // MIs[0] matrix_a_fmt
     /*  883641 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883644 */     // MIs[0] matrix_b_fmt
     /*  883644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883647 */     // MIs[0] src2_modifiers
     /*  883647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883650 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  883653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883655 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883657 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883659 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883665 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883667 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883669 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883677 */     GIR_RootConstrainSelectedInstOperands,
     /*  883678 */     // GIR_Coverage, 8499,
     /*  883678 */     GIR_EraseRootFromParent_Done,
     /*  883679 */   // Label 14166: @883679
     /*  883679 */   GIM_Try, /*On fail goto*//*Label 14167*/ GIMT_Encode4(883746), // Rule ID 8500 //
     /*  883684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  883687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883695 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883698 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  883701 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883708 */     // MIs[0] matrix_a_fmt
     /*  883708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883711 */     // MIs[0] matrix_b_fmt
     /*  883711 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883714 */     // MIs[0] src2_modifiers
     /*  883714 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883717 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  883720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883722 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883724 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883726 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883732 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883734 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883736 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883738 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883741 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883744 */     GIR_RootConstrainSelectedInstOperands,
     /*  883745 */     // GIR_Coverage, 8500,
     /*  883745 */     GIR_EraseRootFromParent_Done,
     /*  883746 */   // Label 14167: @883746
     /*  883746 */   GIM_Try, /*On fail goto*//*Label 14168*/ GIMT_Encode4(883813), // Rule ID 8501 //
     /*  883751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  883754 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883759 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883765 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  883768 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883775 */     // MIs[0] matrix_a_fmt
     /*  883775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883778 */     // MIs[0] matrix_b_fmt
     /*  883778 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883781 */     // MIs[0] src2_modifiers
     /*  883781 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883784 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  883787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883789 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883791 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883793 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883799 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883801 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883803 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883808 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883811 */     GIR_RootConstrainSelectedInstOperands,
     /*  883812 */     // GIR_Coverage, 8501,
     /*  883812 */     GIR_EraseRootFromParent_Done,
     /*  883813 */   // Label 14168: @883813
     /*  883813 */   GIM_Try, /*On fail goto*//*Label 14169*/ GIMT_Encode4(883880), // Rule ID 8502 //
     /*  883818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  883821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883829 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883832 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  883835 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883842 */     // MIs[0] matrix_a_fmt
     /*  883842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883845 */     // MIs[0] matrix_b_fmt
     /*  883845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883848 */     // MIs[0] src2_modifiers
     /*  883848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883851 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  883854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883856 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883858 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883860 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883866 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883868 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883870 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883872 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883878 */     GIR_RootConstrainSelectedInstOperands,
     /*  883879 */     // GIR_Coverage, 8502,
     /*  883879 */     GIR_EraseRootFromParent_Done,
     /*  883880 */   // Label 14169: @883880
     /*  883880 */   GIM_Try, /*On fail goto*//*Label 14170*/ GIMT_Encode4(883947), // Rule ID 8528 //
     /*  883885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  883888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883896 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883899 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  883902 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883909 */     // MIs[0] matrix_a_fmt
     /*  883909 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883912 */     // MIs[0] matrix_b_fmt
     /*  883912 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883915 */     // MIs[0] src2_modifiers
     /*  883915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883918 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  883921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883923 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883925 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883927 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  883933 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  883935 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  883937 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  883939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  883945 */     GIR_RootConstrainSelectedInstOperands,
     /*  883946 */     // GIR_Coverage, 8528,
     /*  883946 */     GIR_EraseRootFromParent_Done,
     /*  883947 */   // Label 14170: @883947
     /*  883947 */   GIM_Try, /*On fail goto*//*Label 14171*/ GIMT_Encode4(884014), // Rule ID 8529 //
     /*  883952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  883955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  883960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  883963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  883966 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  883969 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  883972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  883976 */     // MIs[0] matrix_a_fmt
     /*  883976 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  883979 */     // MIs[0] matrix_b_fmt
     /*  883979 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  883982 */     // MIs[0] src2_modifiers
     /*  883982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  883985 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  883985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  883988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  883990 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  883992 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  883994 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  884000 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  884002 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  884004 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  884006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884012 */     GIR_RootConstrainSelectedInstOperands,
     /*  884013 */     // GIR_Coverage, 8529,
     /*  884013 */     GIR_EraseRootFromParent_Done,
     /*  884014 */   // Label 14171: @884014
     /*  884014 */   GIM_Try, /*On fail goto*//*Label 14172*/ GIMT_Encode4(884081), // Rule ID 8530 //
     /*  884019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  884022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  884027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  884033 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  884036 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  884039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884043 */     // MIs[0] matrix_a_fmt
     /*  884043 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884046 */     // MIs[0] matrix_b_fmt
     /*  884046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884049 */     // MIs[0] src2_modifiers
     /*  884049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  884052 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  884052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  884055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884057 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884059 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884061 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  884067 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  884069 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  884071 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  884073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884079 */     GIR_RootConstrainSelectedInstOperands,
     /*  884080 */     // GIR_Coverage, 8530,
     /*  884080 */     GIR_EraseRootFromParent_Done,
     /*  884081 */   // Label 14172: @884081
     /*  884081 */   GIM_Try, /*On fail goto*//*Label 14173*/ GIMT_Encode4(884148), // Rule ID 8531 //
     /*  884086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  884089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  884094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884097 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  884100 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  884103 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  884106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884110 */     // MIs[0] matrix_a_fmt
     /*  884110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884113 */     // MIs[0] matrix_b_fmt
     /*  884113 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884116 */     // MIs[0] src2_modifiers
     /*  884116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  884119 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  884119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  884122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884124 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884126 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884128 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  884134 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  884136 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  884138 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  884140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884146 */     GIR_RootConstrainSelectedInstOperands,
     /*  884147 */     // GIR_Coverage, 8531,
     /*  884147 */     GIR_EraseRootFromParent_Done,
     /*  884148 */   // Label 14173: @884148
     /*  884148 */   GIM_Try, /*On fail goto*//*Label 14174*/ GIMT_Encode4(884215), // Rule ID 8532 //
     /*  884153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  884156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_f8f6f4),
     /*  884161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  884167 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  884170 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  884173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884177 */     // MIs[0] matrix_a_fmt
     /*  884177 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884180 */     // MIs[0] matrix_b_fmt
     /*  884180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884183 */     // MIs[0] src2_modifiers
     /*  884183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  884186 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3647:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)  =>  (V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt)
     /*  884186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  884189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884191 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884193 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884195 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  884201 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  884203 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  884205 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  884207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884213 */     GIR_RootConstrainSelectedInstOperands,
     /*  884214 */     // GIR_Coverage, 8532,
     /*  884214 */     GIR_EraseRootFromParent_Done,
     /*  884215 */   // Label 14174: @884215
     /*  884215 */   GIM_Try, /*On fail goto*//*Label 14175*/ GIMT_Encode4(884289), // Rule ID 7653 //
     /*  884220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  884223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  884228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884231 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  884234 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  884237 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884244 */     // MIs[0] src0_modifiers
     /*  884244 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884247 */     // MIs[0] src1_modifiers
     /*  884247 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884250 */     // MIs[0] clamp
     /*  884250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884253 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32),
     /*  884256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884258 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884264 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884266 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884272 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884277 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884279 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884281 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884287 */     GIR_RootConstrainSelectedInstOperands,
     /*  884288 */     // GIR_Coverage, 7653,
     /*  884288 */     GIR_EraseRootFromParent_Done,
     /*  884289 */   // Label 14175: @884289
     /*  884289 */   GIM_Try, /*On fail goto*//*Label 14176*/ GIMT_Encode4(884363), // Rule ID 7654 //
     /*  884294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  884297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  884302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884305 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  884308 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  884311 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884318 */     // MIs[0] src0_modifiers
     /*  884318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884321 */     // MIs[0] src1_modifiers
     /*  884321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884324 */     // MIs[0] clamp
     /*  884324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884327 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32),
     /*  884330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884332 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884338 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884340 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884346 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884351 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884353 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884361 */     GIR_RootConstrainSelectedInstOperands,
     /*  884362 */     // GIR_Coverage, 7654,
     /*  884362 */     GIR_EraseRootFromParent_Done,
     /*  884363 */   // Label 14176: @884363
     /*  884363 */   GIM_Try, /*On fail goto*//*Label 14177*/ GIMT_Encode4(884437), // Rule ID 7655 //
     /*  884368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  884371 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  884376 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884379 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  884382 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  884385 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884392 */     // MIs[0] src0_modifiers
     /*  884392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884395 */     // MIs[0] src1_modifiers
     /*  884395 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884398 */     // MIs[0] clamp
     /*  884398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884401 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32),
     /*  884404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884406 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884412 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884414 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884420 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884425 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884427 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884435 */     GIR_RootConstrainSelectedInstOperands,
     /*  884436 */     // GIR_Coverage, 7655,
     /*  884436 */     GIR_EraseRootFromParent_Done,
     /*  884437 */   // Label 14177: @884437
     /*  884437 */   GIM_Try, /*On fail goto*//*Label 14178*/ GIMT_Encode4(884511), // Rule ID 7656 //
     /*  884442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  884445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  884450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  884456 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  884459 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884466 */     // MIs[0] src0_modifiers
     /*  884466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884469 */     // MIs[0] src1_modifiers
     /*  884469 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884472 */     // MIs[0] clamp
     /*  884472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884475 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32),
     /*  884478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884480 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884486 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884488 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884494 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884499 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884501 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884509 */     GIR_RootConstrainSelectedInstOperands,
     /*  884510 */     // GIR_Coverage, 7656,
     /*  884510 */     GIR_EraseRootFromParent_Done,
     /*  884511 */   // Label 14178: @884511
     /*  884511 */   GIM_Try, /*On fail goto*//*Label 14179*/ GIMT_Encode4(884585), // Rule ID 7657 //
     /*  884516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  884519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  884524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  884530 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  884533 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884540 */     // MIs[0] src0_modifiers
     /*  884540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884543 */     // MIs[0] src1_modifiers
     /*  884543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884546 */     // MIs[0] clamp
     /*  884546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884549 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32),
     /*  884552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884554 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884560 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884562 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884568 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884573 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884575 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884583 */     GIR_RootConstrainSelectedInstOperands,
     /*  884584 */     // GIR_Coverage, 7657,
     /*  884584 */     GIR_EraseRootFromParent_Done,
     /*  884585 */   // Label 14179: @884585
     /*  884585 */   GIM_Try, /*On fail goto*//*Label 14180*/ GIMT_Encode4(884659), // Rule ID 7683 //
     /*  884590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode0),
     /*  884593 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  884598 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  884604 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  884607 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884614 */     // MIs[0] src0_modifiers
     /*  884614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884617 */     // MIs[0] src1_modifiers
     /*  884617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884620 */     // MIs[0] clamp
     /*  884620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884623 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32),
     /*  884626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884628 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884634 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884636 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884642 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884647 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884649 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884654 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884657 */     GIR_RootConstrainSelectedInstOperands,
     /*  884658 */     // GIR_Coverage, 7683,
     /*  884658 */     GIR_EraseRootFromParent_Done,
     /*  884659 */   // Label 14180: @884659
     /*  884659 */   GIM_Try, /*On fail goto*//*Label 14181*/ GIMT_Encode4(884733), // Rule ID 7684 //
     /*  884664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode1),
     /*  884667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  884672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  884678 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  884681 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884688 */     // MIs[0] src0_modifiers
     /*  884688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884691 */     // MIs[0] src1_modifiers
     /*  884691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884694 */     // MIs[0] clamp
     /*  884694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884697 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32),
     /*  884700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884702 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884708 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884710 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884716 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884718 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884721 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884723 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884731 */     GIR_RootConstrainSelectedInstOperands,
     /*  884732 */     // GIR_Coverage, 7684,
     /*  884732 */     GIR_EraseRootFromParent_Done,
     /*  884733 */   // Label 14181: @884733
     /*  884733 */   GIM_Try, /*On fail goto*//*Label 14182*/ GIMT_Encode4(884807), // Rule ID 7685 //
     /*  884738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode2),
     /*  884741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  884746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  884752 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  884755 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884762 */     // MIs[0] src0_modifiers
     /*  884762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884765 */     // MIs[0] src1_modifiers
     /*  884765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884768 */     // MIs[0] clamp
     /*  884768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884771 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32),
     /*  884774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884776 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884782 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884784 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884790 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884795 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884797 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884805 */     GIR_RootConstrainSelectedInstOperands,
     /*  884806 */     // GIR_Coverage, 7685,
     /*  884806 */     GIR_EraseRootFromParent_Done,
     /*  884807 */   // Label 14182: @884807
     /*  884807 */   GIM_Try, /*On fail goto*//*Label 14183*/ GIMT_Encode4(884881), // Rule ID 7686 //
     /*  884812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode3),
     /*  884815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  884820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884823 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  884826 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  884829 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884836 */     // MIs[0] src0_modifiers
     /*  884836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884839 */     // MIs[0] src1_modifiers
     /*  884839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884842 */     // MIs[0] clamp
     /*  884842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884845 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32),
     /*  884848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884850 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884856 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884858 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884864 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884866 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884869 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884871 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884879 */     GIR_RootConstrainSelectedInstOperands,
     /*  884880 */     // GIR_Coverage, 7686,
     /*  884880 */     GIR_EraseRootFromParent_Done,
     /*  884881 */   // Label 14183: @884881
     /*  884881 */   GIM_Try, /*On fail goto*//*Label 14184*/ GIMT_Encode4(884955), // Rule ID 7687 //
     /*  884886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32_HwMode4),
     /*  884889 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  884894 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  884897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  884900 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  884903 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  884906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  884910 */     // MIs[0] src0_modifiers
     /*  884910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884913 */     // MIs[0] src1_modifiers
     /*  884913 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884916 */     // MIs[0] clamp
     /*  884916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884919 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32),
     /*  884922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884924 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  884930 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  884932 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  884938 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  884940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  884943 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  884945 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  884947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  884953 */     GIR_RootConstrainSelectedInstOperands,
     /*  884954 */     // GIR_Coverage, 7687,
     /*  884954 */     GIR_EraseRootFromParent_Done,
     /*  884955 */   // Label 14184: @884955
     /*  884955 */   GIM_Try, /*On fail goto*//*Label 14185*/ GIMT_Encode4(885029), // Rule ID 7718 //
     /*  884960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  884963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  884968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  884971 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  884974 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  884977 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  884980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  884984 */     // MIs[0] src0_modifiers
     /*  884984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  884987 */     // MIs[0] src1_modifiers
     /*  884987 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  884990 */     // MIs[0] clamp
     /*  884990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  884993 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  884993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64),
     /*  884996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  884998 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885004 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885006 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885012 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885014 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885017 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885019 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885027 */     GIR_RootConstrainSelectedInstOperands,
     /*  885028 */     // GIR_Coverage, 7718,
     /*  885028 */     GIR_EraseRootFromParent_Done,
     /*  885029 */   // Label 14185: @885029
     /*  885029 */   GIM_Try, /*On fail goto*//*Label 14186*/ GIMT_Encode4(885103), // Rule ID 7719 //
     /*  885034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  885037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  885042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885045 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  885048 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  885051 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885058 */     // MIs[0] src0_modifiers
     /*  885058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885061 */     // MIs[0] src1_modifiers
     /*  885061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885064 */     // MIs[0] clamp
     /*  885064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885067 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64),
     /*  885070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885072 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885078 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885080 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885086 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885091 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885093 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885101 */     GIR_RootConstrainSelectedInstOperands,
     /*  885102 */     // GIR_Coverage, 7719,
     /*  885102 */     GIR_EraseRootFromParent_Done,
     /*  885103 */   // Label 14186: @885103
     /*  885103 */   GIM_Try, /*On fail goto*//*Label 14187*/ GIMT_Encode4(885177), // Rule ID 7720 //
     /*  885108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  885111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  885116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885119 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  885122 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  885125 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885132 */     // MIs[0] src0_modifiers
     /*  885132 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885135 */     // MIs[0] src1_modifiers
     /*  885135 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885138 */     // MIs[0] clamp
     /*  885138 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885141 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64),
     /*  885144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885146 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885152 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885154 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885160 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885165 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885167 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885172 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885175 */     GIR_RootConstrainSelectedInstOperands,
     /*  885176 */     // GIR_Coverage, 7720,
     /*  885176 */     GIR_EraseRootFromParent_Done,
     /*  885177 */   // Label 14187: @885177
     /*  885177 */   GIM_Try, /*On fail goto*//*Label 14188*/ GIMT_Encode4(885251), // Rule ID 7721 //
     /*  885182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  885185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  885190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885193 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  885196 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  885199 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885206 */     // MIs[0] src0_modifiers
     /*  885206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885209 */     // MIs[0] src1_modifiers
     /*  885209 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885212 */     // MIs[0] clamp
     /*  885212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885215 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64),
     /*  885218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885220 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885226 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885228 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885234 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885239 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885241 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885249 */     GIR_RootConstrainSelectedInstOperands,
     /*  885250 */     // GIR_Coverage, 7721,
     /*  885250 */     GIR_EraseRootFromParent_Done,
     /*  885251 */   // Label 14188: @885251
     /*  885251 */   GIM_Try, /*On fail goto*//*Label 14189*/ GIMT_Encode4(885325), // Rule ID 7722 //
     /*  885256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  885259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  885264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  885270 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  885273 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885280 */     // MIs[0] src0_modifiers
     /*  885280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885283 */     // MIs[0] src1_modifiers
     /*  885283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885286 */     // MIs[0] clamp
     /*  885286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885289 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64),
     /*  885292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885294 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885300 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885302 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885308 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885313 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885315 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885317 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885323 */     GIR_RootConstrainSelectedInstOperands,
     /*  885324 */     // GIR_Coverage, 7722,
     /*  885324 */     GIR_EraseRootFromParent_Done,
     /*  885325 */   // Label 14189: @885325
     /*  885325 */   GIM_Try, /*On fail goto*//*Label 14190*/ GIMT_Encode4(885399), // Rule ID 7723 //
     /*  885330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode0),
     /*  885333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  885338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885341 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  885344 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  885347 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885354 */     // MIs[0] src0_modifiers
     /*  885354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885357 */     // MIs[0] src1_modifiers
     /*  885357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885360 */     // MIs[0] clamp
     /*  885360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885363 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64),
     /*  885366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885368 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885374 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885376 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885382 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885387 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885389 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885391 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885394 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885397 */     GIR_RootConstrainSelectedInstOperands,
     /*  885398 */     // GIR_Coverage, 7723,
     /*  885398 */     GIR_EraseRootFromParent_Done,
     /*  885399 */   // Label 14190: @885399
     /*  885399 */   GIM_Try, /*On fail goto*//*Label 14191*/ GIMT_Encode4(885473), // Rule ID 7724 //
     /*  885404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode1),
     /*  885407 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  885412 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  885418 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  885421 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885428 */     // MIs[0] src0_modifiers
     /*  885428 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885431 */     // MIs[0] src1_modifiers
     /*  885431 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885434 */     // MIs[0] clamp
     /*  885434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885437 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64),
     /*  885440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885442 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885448 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885450 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885456 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885458 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885461 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885463 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885471 */     GIR_RootConstrainSelectedInstOperands,
     /*  885472 */     // GIR_Coverage, 7724,
     /*  885472 */     GIR_EraseRootFromParent_Done,
     /*  885473 */   // Label 14191: @885473
     /*  885473 */   GIM_Try, /*On fail goto*//*Label 14192*/ GIMT_Encode4(885547), // Rule ID 7725 //
     /*  885478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode2),
     /*  885481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  885486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885489 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  885492 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  885495 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885502 */     // MIs[0] src0_modifiers
     /*  885502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885505 */     // MIs[0] src1_modifiers
     /*  885505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885508 */     // MIs[0] clamp
     /*  885508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885511 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64),
     /*  885514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885516 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885522 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885524 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885530 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885535 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885537 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885545 */     GIR_RootConstrainSelectedInstOperands,
     /*  885546 */     // GIR_Coverage, 7725,
     /*  885546 */     GIR_EraseRootFromParent_Done,
     /*  885547 */   // Label 14192: @885547
     /*  885547 */   GIM_Try, /*On fail goto*//*Label 14193*/ GIMT_Encode4(885621), // Rule ID 7726 //
     /*  885552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode3),
     /*  885555 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  885560 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  885566 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  885569 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885576 */     // MIs[0] src0_modifiers
     /*  885576 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885579 */     // MIs[0] src1_modifiers
     /*  885579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885582 */     // MIs[0] clamp
     /*  885582 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885585 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64),
     /*  885588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885590 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885596 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885598 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885604 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885609 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885611 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885619 */     GIR_RootConstrainSelectedInstOperands,
     /*  885620 */     // GIR_Coverage, 7726,
     /*  885620 */     GIR_EraseRootFromParent_Done,
     /*  885621 */   // Label 14193: @885621
     /*  885621 */   GIM_Try, /*On fail goto*//*Label 14194*/ GIMT_Encode4(885695), // Rule ID 7727 //
     /*  885626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64_HwMode4),
     /*  885629 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  885634 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  885637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  885640 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  885643 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  885646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  885650 */     // MIs[0] src0_modifiers
     /*  885650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  885653 */     // MIs[0] src1_modifiers
     /*  885653 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885656 */     // MIs[0] clamp
     /*  885656 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885659 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  885659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64),
     /*  885662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885664 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  885670 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  885672 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  885678 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  885680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /*  885683 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  885685 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  885687 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885693 */     GIR_RootConstrainSelectedInstOperands,
     /*  885694 */     // GIR_Coverage, 7727,
     /*  885694 */     GIR_EraseRootFromParent_Done,
     /*  885695 */   // Label 14194: @885695
     /*  885695 */   GIM_Try, /*On fail goto*//*Label 14195*/ GIMT_Encode4(885762), // Rule ID 8068 //
     /*  885700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  885703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  885708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  885711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  885714 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  885717 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  885720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  885724 */     // MIs[0] src2_modifiers
     /*  885724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885727 */     // MIs[0] matrix_a_reuse
     /*  885727 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  885730 */     // MIs[0] matrix_b_reuse
     /*  885730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885733 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  885733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr),
     /*  885736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885738 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  885740 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  885742 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  885748 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  885750 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  885752 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  885754 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885760 */     GIR_RootConstrainSelectedInstOperands,
     /*  885761 */     // GIR_Coverage, 8068,
     /*  885761 */     GIR_EraseRootFromParent_Done,
     /*  885762 */   // Label 14195: @885762
     /*  885762 */   GIM_Try, /*On fail goto*//*Label 14196*/ GIMT_Encode4(885829), // Rule ID 8069 //
     /*  885767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  885770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  885775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  885778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  885781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  885784 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  885787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  885791 */     // MIs[0] src2_modifiers
     /*  885791 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885794 */     // MIs[0] matrix_a_reuse
     /*  885794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  885797 */     // MIs[0] matrix_b_reuse
     /*  885797 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885800 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  885800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr),
     /*  885803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885805 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  885807 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  885809 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  885815 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  885817 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  885819 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  885821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885827 */     GIR_RootConstrainSelectedInstOperands,
     /*  885828 */     // GIR_Coverage, 8069,
     /*  885828 */     GIR_EraseRootFromParent_Done,
     /*  885829 */   // Label 14196: @885829
     /*  885829 */   GIM_Try, /*On fail goto*//*Label 14197*/ GIMT_Encode4(885896), // Rule ID 8070 //
     /*  885834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  885837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  885842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  885845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  885848 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  885851 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  885854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  885858 */     // MIs[0] src2_modifiers
     /*  885858 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885861 */     // MIs[0] matrix_a_reuse
     /*  885861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  885864 */     // MIs[0] matrix_b_reuse
     /*  885864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885867 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  885867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr),
     /*  885870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885872 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  885874 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  885876 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  885882 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  885884 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  885886 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  885888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885894 */     GIR_RootConstrainSelectedInstOperands,
     /*  885895 */     // GIR_Coverage, 8070,
     /*  885895 */     GIR_EraseRootFromParent_Done,
     /*  885896 */   // Label 14197: @885896
     /*  885896 */   GIM_Try, /*On fail goto*//*Label 14198*/ GIMT_Encode4(885963), // Rule ID 8071 //
     /*  885901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  885904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  885909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  885912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  885915 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  885918 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  885921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  885925 */     // MIs[0] src2_modifiers
     /*  885925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885928 */     // MIs[0] matrix_a_reuse
     /*  885928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  885931 */     // MIs[0] matrix_b_reuse
     /*  885931 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  885934 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  885934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr),
     /*  885937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  885939 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  885941 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  885943 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  885949 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  885951 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  885953 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  885955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  885961 */     GIR_RootConstrainSelectedInstOperands,
     /*  885962 */     // GIR_Coverage, 8071,
     /*  885962 */     GIR_EraseRootFromParent_Done,
     /*  885963 */   // Label 14198: @885963
     /*  885963 */   GIM_Try, /*On fail goto*//*Label 14199*/ GIMT_Encode4(886030), // Rule ID 8072 //
     /*  885968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  885971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_fp8),
     /*  885976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  885979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  885982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  885985 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  885988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  885992 */     // MIs[0] src2_modifiers
     /*  885992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  885995 */     // MIs[0] matrix_a_reuse
     /*  885995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  885998 */     // MIs[0] matrix_b_reuse
     /*  885998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886001 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3662:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr),
     /*  886004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886006 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886008 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886010 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886016 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886018 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886020 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886022 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886028 */     GIR_RootConstrainSelectedInstOperands,
     /*  886029 */     // GIR_Coverage, 8072,
     /*  886029 */     GIR_EraseRootFromParent_Done,
     /*  886030 */   // Label 14199: @886030
     /*  886030 */   GIM_Try, /*On fail goto*//*Label 14200*/ GIMT_Encode4(886097), // Rule ID 8078 //
     /*  886035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  886038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  886043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886052 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886059 */     // MIs[0] src2_modifiers
     /*  886059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886062 */     // MIs[0] matrix_a_reuse
     /*  886062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886065 */     // MIs[0] matrix_b_reuse
     /*  886065 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886068 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr),
     /*  886071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886073 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886075 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886077 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886083 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886085 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886087 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886095 */     GIR_RootConstrainSelectedInstOperands,
     /*  886096 */     // GIR_Coverage, 8078,
     /*  886096 */     GIR_EraseRootFromParent_Done,
     /*  886097 */   // Label 14200: @886097
     /*  886097 */   GIM_Try, /*On fail goto*//*Label 14201*/ GIMT_Encode4(886164), // Rule ID 8079 //
     /*  886102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  886105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  886110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886119 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886126 */     // MIs[0] src2_modifiers
     /*  886126 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886129 */     // MIs[0] matrix_a_reuse
     /*  886129 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886132 */     // MIs[0] matrix_b_reuse
     /*  886132 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886135 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr),
     /*  886138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886140 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886142 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886144 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886150 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886152 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886154 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886156 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886159 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886162 */     GIR_RootConstrainSelectedInstOperands,
     /*  886163 */     // GIR_Coverage, 8079,
     /*  886163 */     GIR_EraseRootFromParent_Done,
     /*  886164 */   // Label 14201: @886164
     /*  886164 */   GIM_Try, /*On fail goto*//*Label 14202*/ GIMT_Encode4(886231), // Rule ID 8080 //
     /*  886169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  886172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  886177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886186 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886193 */     // MIs[0] src2_modifiers
     /*  886193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886196 */     // MIs[0] matrix_a_reuse
     /*  886196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886199 */     // MIs[0] matrix_b_reuse
     /*  886199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886202 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr),
     /*  886205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886207 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886209 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886217 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886219 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886221 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886229 */     GIR_RootConstrainSelectedInstOperands,
     /*  886230 */     // GIR_Coverage, 8080,
     /*  886230 */     GIR_EraseRootFromParent_Done,
     /*  886231 */   // Label 14202: @886231
     /*  886231 */   GIM_Try, /*On fail goto*//*Label 14203*/ GIMT_Encode4(886298), // Rule ID 8081 //
     /*  886236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  886239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  886244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886253 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886260 */     // MIs[0] src2_modifiers
     /*  886260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886263 */     // MIs[0] matrix_a_reuse
     /*  886263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886266 */     // MIs[0] matrix_b_reuse
     /*  886266 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886269 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr),
     /*  886272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886274 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886276 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886278 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886284 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886286 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886288 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886296 */     GIR_RootConstrainSelectedInstOperands,
     /*  886297 */     // GIR_Coverage, 8081,
     /*  886297 */     GIR_EraseRootFromParent_Done,
     /*  886298 */   // Label 14203: @886298
     /*  886298 */   GIM_Try, /*On fail goto*//*Label 14204*/ GIMT_Encode4(886365), // Rule ID 8082 //
     /*  886303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  886306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_fp8_bf8),
     /*  886311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886320 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886327 */     // MIs[0] src2_modifiers
     /*  886327 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886330 */     // MIs[0] matrix_a_reuse
     /*  886330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886333 */     // MIs[0] matrix_b_reuse
     /*  886333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886336 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3661:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr),
     /*  886339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886341 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886343 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886345 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886351 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886353 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886355 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886363 */     GIR_RootConstrainSelectedInstOperands,
     /*  886364 */     // GIR_Coverage, 8082,
     /*  886364 */     GIR_EraseRootFromParent_Done,
     /*  886365 */   // Label 14204: @886365
     /*  886365 */   GIM_Try, /*On fail goto*//*Label 14205*/ GIMT_Encode4(886432), // Rule ID 8088 //
     /*  886370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  886373 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  886378 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886381 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886384 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886387 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886394 */     // MIs[0] src2_modifiers
     /*  886394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886397 */     // MIs[0] matrix_a_reuse
     /*  886397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886400 */     // MIs[0] matrix_b_reuse
     /*  886400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886403 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr),
     /*  886406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886408 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886410 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886412 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886418 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886420 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886422 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886424 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886430 */     GIR_RootConstrainSelectedInstOperands,
     /*  886431 */     // GIR_Coverage, 8088,
     /*  886431 */     GIR_EraseRootFromParent_Done,
     /*  886432 */   // Label 14205: @886432
     /*  886432 */   GIM_Try, /*On fail goto*//*Label 14206*/ GIMT_Encode4(886499), // Rule ID 8089 //
     /*  886437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  886440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  886445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886454 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886461 */     // MIs[0] src2_modifiers
     /*  886461 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886464 */     // MIs[0] matrix_a_reuse
     /*  886464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886467 */     // MIs[0] matrix_b_reuse
     /*  886467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886470 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr),
     /*  886473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886475 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886477 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886479 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886485 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886487 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886489 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886497 */     GIR_RootConstrainSelectedInstOperands,
     /*  886498 */     // GIR_Coverage, 8089,
     /*  886498 */     GIR_EraseRootFromParent_Done,
     /*  886499 */   // Label 14206: @886499
     /*  886499 */   GIM_Try, /*On fail goto*//*Label 14207*/ GIMT_Encode4(886566), // Rule ID 8090 //
     /*  886504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  886507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  886512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886521 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886528 */     // MIs[0] src2_modifiers
     /*  886528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886531 */     // MIs[0] matrix_a_reuse
     /*  886531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886534 */     // MIs[0] matrix_b_reuse
     /*  886534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886537 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr),
     /*  886540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886542 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886544 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886546 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886552 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886554 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886556 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886564 */     GIR_RootConstrainSelectedInstOperands,
     /*  886565 */     // GIR_Coverage, 8090,
     /*  886565 */     GIR_EraseRootFromParent_Done,
     /*  886566 */   // Label 14207: @886566
     /*  886566 */   GIM_Try, /*On fail goto*//*Label 14208*/ GIMT_Encode4(886633), // Rule ID 8091 //
     /*  886571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  886574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  886579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886588 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886595 */     // MIs[0] src2_modifiers
     /*  886595 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886598 */     // MIs[0] matrix_a_reuse
     /*  886598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886601 */     // MIs[0] matrix_b_reuse
     /*  886601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886604 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr),
     /*  886607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886609 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886611 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886613 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886619 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886621 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886623 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886631 */     GIR_RootConstrainSelectedInstOperands,
     /*  886632 */     // GIR_Coverage, 8091,
     /*  886632 */     GIR_EraseRootFromParent_Done,
     /*  886633 */   // Label 14208: @886633
     /*  886633 */   GIM_Try, /*On fail goto*//*Label 14209*/ GIMT_Encode4(886700), // Rule ID 8092 //
     /*  886638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  886641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_fp8),
     /*  886646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886655 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886662 */     // MIs[0] src2_modifiers
     /*  886662 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886665 */     // MIs[0] matrix_a_reuse
     /*  886665 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886668 */     // MIs[0] matrix_b_reuse
     /*  886668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886671 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3660:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr),
     /*  886674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886676 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886678 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886680 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886686 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886688 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886690 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886698 */     GIR_RootConstrainSelectedInstOperands,
     /*  886699 */     // GIR_Coverage, 8092,
     /*  886699 */     GIR_EraseRootFromParent_Done,
     /*  886700 */   // Label 14209: @886700
     /*  886700 */   GIM_Try, /*On fail goto*//*Label 14210*/ GIMT_Encode4(886767), // Rule ID 8098 //
     /*  886705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  886708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  886713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886719 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886722 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886729 */     // MIs[0] src2_modifiers
     /*  886729 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886732 */     // MIs[0] matrix_a_reuse
     /*  886732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886735 */     // MIs[0] matrix_b_reuse
     /*  886735 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886738 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr),
     /*  886741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886743 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886745 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886747 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886753 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886755 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886757 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886765 */     GIR_RootConstrainSelectedInstOperands,
     /*  886766 */     // GIR_Coverage, 8098,
     /*  886766 */     GIR_EraseRootFromParent_Done,
     /*  886767 */   // Label 14210: @886767
     /*  886767 */   GIM_Try, /*On fail goto*//*Label 14211*/ GIMT_Encode4(886834), // Rule ID 8099 //
     /*  886772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  886775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  886780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886789 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886796 */     // MIs[0] src2_modifiers
     /*  886796 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886799 */     // MIs[0] matrix_a_reuse
     /*  886799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886802 */     // MIs[0] matrix_b_reuse
     /*  886802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886805 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr),
     /*  886808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886810 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886812 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886814 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886820 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886822 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886824 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886829 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886832 */     GIR_RootConstrainSelectedInstOperands,
     /*  886833 */     // GIR_Coverage, 8099,
     /*  886833 */     GIR_EraseRootFromParent_Done,
     /*  886834 */   // Label 14211: @886834
     /*  886834 */   GIM_Try, /*On fail goto*//*Label 14212*/ GIMT_Encode4(886901), // Rule ID 8100 //
     /*  886839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  886842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  886847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886856 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886863 */     // MIs[0] src2_modifiers
     /*  886863 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886866 */     // MIs[0] matrix_a_reuse
     /*  886866 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886869 */     // MIs[0] matrix_b_reuse
     /*  886869 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886872 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr),
     /*  886875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886877 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886879 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886881 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886887 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886889 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886891 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886899 */     GIR_RootConstrainSelectedInstOperands,
     /*  886900 */     // GIR_Coverage, 8100,
     /*  886900 */     GIR_EraseRootFromParent_Done,
     /*  886901 */   // Label 14212: @886901
     /*  886901 */   GIM_Try, /*On fail goto*//*Label 14213*/ GIMT_Encode4(886968), // Rule ID 8101 //
     /*  886906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  886909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  886914 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886917 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886920 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886923 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886930 */     // MIs[0] src2_modifiers
     /*  886930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  886933 */     // MIs[0] matrix_a_reuse
     /*  886933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  886936 */     // MIs[0] matrix_b_reuse
     /*  886936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  886939 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  886939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr),
     /*  886942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  886944 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  886946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  886948 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  886954 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  886956 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  886958 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  886960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886963 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  886966 */     GIR_RootConstrainSelectedInstOperands,
     /*  886967 */     // GIR_Coverage, 8101,
     /*  886967 */     GIR_EraseRootFromParent_Done,
     /*  886968 */   // Label 14213: @886968
     /*  886968 */   GIM_Try, /*On fail goto*//*Label 14214*/ GIMT_Encode4(887035), // Rule ID 8102 //
     /*  886973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  886976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x64_bf8_bf8),
     /*  886981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  886984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  886987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  886990 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  886993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  886997 */     // MIs[0] src2_modifiers
     /*  886997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887000 */     // MIs[0] matrix_a_reuse
     /*  887000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887003 */     // MIs[0] matrix_b_reuse
     /*  887003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887006 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3659:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr),
     /*  887009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887011 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887013 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887015 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887021 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887023 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887025 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887030 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887033 */     GIR_RootConstrainSelectedInstOperands,
     /*  887034 */     // GIR_Coverage, 8102,
     /*  887034 */     GIR_EraseRootFromParent_Done,
     /*  887035 */   // Label 14214: @887035
     /*  887035 */   GIM_Try, /*On fail goto*//*Label 14215*/ GIMT_Encode4(887102), // Rule ID 8108 //
     /*  887040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  887043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  887048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887057 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887064 */     // MIs[0] src2_modifiers
     /*  887064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887067 */     // MIs[0] matrix_a_reuse
     /*  887067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887070 */     // MIs[0] matrix_b_reuse
     /*  887070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887073 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr),
     /*  887076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887078 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887080 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887082 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887088 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887090 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887092 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887100 */     GIR_RootConstrainSelectedInstOperands,
     /*  887101 */     // GIR_Coverage, 8108,
     /*  887101 */     GIR_EraseRootFromParent_Done,
     /*  887102 */   // Label 14215: @887102
     /*  887102 */   GIM_Try, /*On fail goto*//*Label 14216*/ GIMT_Encode4(887169), // Rule ID 8109 //
     /*  887107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  887110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  887115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887121 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887124 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887131 */     // MIs[0] src2_modifiers
     /*  887131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887134 */     // MIs[0] matrix_a_reuse
     /*  887134 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887137 */     // MIs[0] matrix_b_reuse
     /*  887137 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887140 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr),
     /*  887143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887145 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887147 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887149 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887155 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887157 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887159 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887167 */     GIR_RootConstrainSelectedInstOperands,
     /*  887168 */     // GIR_Coverage, 8109,
     /*  887168 */     GIR_EraseRootFromParent_Done,
     /*  887169 */   // Label 14216: @887169
     /*  887169 */   GIM_Try, /*On fail goto*//*Label 14217*/ GIMT_Encode4(887236), // Rule ID 8110 //
     /*  887174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  887177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  887182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887191 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887198 */     // MIs[0] src2_modifiers
     /*  887198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887201 */     // MIs[0] matrix_a_reuse
     /*  887201 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887204 */     // MIs[0] matrix_b_reuse
     /*  887204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887207 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr),
     /*  887210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887212 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887214 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887216 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887222 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887224 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887226 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887234 */     GIR_RootConstrainSelectedInstOperands,
     /*  887235 */     // GIR_Coverage, 8110,
     /*  887235 */     GIR_EraseRootFromParent_Done,
     /*  887236 */   // Label 14217: @887236
     /*  887236 */   GIM_Try, /*On fail goto*//*Label 14218*/ GIMT_Encode4(887303), // Rule ID 8111 //
     /*  887241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  887244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  887249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887258 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887265 */     // MIs[0] src2_modifiers
     /*  887265 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887268 */     // MIs[0] matrix_a_reuse
     /*  887268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887271 */     // MIs[0] matrix_b_reuse
     /*  887271 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887274 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr),
     /*  887277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887279 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887281 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887283 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887289 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887291 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887293 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887298 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887301 */     GIR_RootConstrainSelectedInstOperands,
     /*  887302 */     // GIR_Coverage, 8111,
     /*  887302 */     GIR_EraseRootFromParent_Done,
     /*  887303 */   // Label 14218: @887303
     /*  887303 */   GIM_Try, /*On fail goto*//*Label 14219*/ GIMT_Encode4(887370), // Rule ID 8112 //
     /*  887308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  887311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_fp8),
     /*  887316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887325 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887332 */     // MIs[0] src2_modifiers
     /*  887332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887335 */     // MIs[0] matrix_a_reuse
     /*  887335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887338 */     // MIs[0] matrix_b_reuse
     /*  887338 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887341 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3644:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr),
     /*  887344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887346 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887348 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887350 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887356 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887358 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887360 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887368 */     GIR_RootConstrainSelectedInstOperands,
     /*  887369 */     // GIR_Coverage, 8112,
     /*  887369 */     GIR_EraseRootFromParent_Done,
     /*  887370 */   // Label 14219: @887370
     /*  887370 */   GIM_Try, /*On fail goto*//*Label 14220*/ GIMT_Encode4(887437), // Rule ID 8118 //
     /*  887375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  887378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  887383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887392 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887399 */     // MIs[0] src2_modifiers
     /*  887399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887402 */     // MIs[0] matrix_a_reuse
     /*  887402 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887405 */     // MIs[0] matrix_b_reuse
     /*  887405 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887408 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr),
     /*  887411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887413 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887415 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887417 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887423 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887425 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887427 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887435 */     GIR_RootConstrainSelectedInstOperands,
     /*  887436 */     // GIR_Coverage, 8118,
     /*  887436 */     GIR_EraseRootFromParent_Done,
     /*  887437 */   // Label 14220: @887437
     /*  887437 */   GIM_Try, /*On fail goto*//*Label 14221*/ GIMT_Encode4(887504), // Rule ID 8119 //
     /*  887442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  887445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  887450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887459 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887466 */     // MIs[0] src2_modifiers
     /*  887466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887469 */     // MIs[0] matrix_a_reuse
     /*  887469 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887472 */     // MIs[0] matrix_b_reuse
     /*  887472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887475 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr),
     /*  887478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887480 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887482 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887484 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887490 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887492 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887494 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887502 */     GIR_RootConstrainSelectedInstOperands,
     /*  887503 */     // GIR_Coverage, 8119,
     /*  887503 */     GIR_EraseRootFromParent_Done,
     /*  887504 */   // Label 14221: @887504
     /*  887504 */   GIM_Try, /*On fail goto*//*Label 14222*/ GIMT_Encode4(887571), // Rule ID 8120 //
     /*  887509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  887512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  887517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887526 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887533 */     // MIs[0] src2_modifiers
     /*  887533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887536 */     // MIs[0] matrix_a_reuse
     /*  887536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887539 */     // MIs[0] matrix_b_reuse
     /*  887539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887542 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr),
     /*  887545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887547 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887549 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887551 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887557 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887559 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887561 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887569 */     GIR_RootConstrainSelectedInstOperands,
     /*  887570 */     // GIR_Coverage, 8120,
     /*  887570 */     GIR_EraseRootFromParent_Done,
     /*  887571 */   // Label 14222: @887571
     /*  887571 */   GIM_Try, /*On fail goto*//*Label 14223*/ GIMT_Encode4(887638), // Rule ID 8121 //
     /*  887576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  887579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  887584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887593 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887600 */     // MIs[0] src2_modifiers
     /*  887600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887603 */     // MIs[0] matrix_a_reuse
     /*  887603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887606 */     // MIs[0] matrix_b_reuse
     /*  887606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887609 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr),
     /*  887612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887614 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887616 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887618 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887624 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887626 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887628 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887636 */     GIR_RootConstrainSelectedInstOperands,
     /*  887637 */     // GIR_Coverage, 8121,
     /*  887637 */     GIR_EraseRootFromParent_Done,
     /*  887638 */   // Label 14223: @887638
     /*  887638 */   GIM_Try, /*On fail goto*//*Label 14224*/ GIMT_Encode4(887705), // Rule ID 8122 //
     /*  887643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  887646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_fp8_bf8),
     /*  887651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887660 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887667 */     // MIs[0] src2_modifiers
     /*  887667 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887670 */     // MIs[0] matrix_a_reuse
     /*  887670 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887673 */     // MIs[0] matrix_b_reuse
     /*  887673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887676 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3643:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr),
     /*  887679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887681 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887683 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887685 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887691 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887693 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887695 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887703 */     GIR_RootConstrainSelectedInstOperands,
     /*  887704 */     // GIR_Coverage, 8122,
     /*  887704 */     GIR_EraseRootFromParent_Done,
     /*  887705 */   // Label 14224: @887705
     /*  887705 */   GIM_Try, /*On fail goto*//*Label 14225*/ GIMT_Encode4(887772), // Rule ID 8128 //
     /*  887710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  887713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  887718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887727 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887734 */     // MIs[0] src2_modifiers
     /*  887734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887737 */     // MIs[0] matrix_a_reuse
     /*  887737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887740 */     // MIs[0] matrix_b_reuse
     /*  887740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887743 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr),
     /*  887746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887748 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887750 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887752 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887758 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887760 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887762 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887764 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887770 */     GIR_RootConstrainSelectedInstOperands,
     /*  887771 */     // GIR_Coverage, 8128,
     /*  887771 */     GIR_EraseRootFromParent_Done,
     /*  887772 */   // Label 14225: @887772
     /*  887772 */   GIM_Try, /*On fail goto*//*Label 14226*/ GIMT_Encode4(887839), // Rule ID 8129 //
     /*  887777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  887780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  887785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887791 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887794 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887801 */     // MIs[0] src2_modifiers
     /*  887801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887804 */     // MIs[0] matrix_a_reuse
     /*  887804 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887807 */     // MIs[0] matrix_b_reuse
     /*  887807 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887810 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr),
     /*  887813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887815 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887817 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887819 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887825 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887827 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887829 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887837 */     GIR_RootConstrainSelectedInstOperands,
     /*  887838 */     // GIR_Coverage, 8129,
     /*  887838 */     GIR_EraseRootFromParent_Done,
     /*  887839 */   // Label 14226: @887839
     /*  887839 */   GIM_Try, /*On fail goto*//*Label 14227*/ GIMT_Encode4(887906), // Rule ID 8130 //
     /*  887844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  887847 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  887852 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887855 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887858 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887861 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887868 */     // MIs[0] src2_modifiers
     /*  887868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887871 */     // MIs[0] matrix_a_reuse
     /*  887871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887874 */     // MIs[0] matrix_b_reuse
     /*  887874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887877 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr),
     /*  887880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887882 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887884 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887886 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887892 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887894 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887896 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887904 */     GIR_RootConstrainSelectedInstOperands,
     /*  887905 */     // GIR_Coverage, 8130,
     /*  887905 */     GIR_EraseRootFromParent_Done,
     /*  887906 */   // Label 14227: @887906
     /*  887906 */   GIM_Try, /*On fail goto*//*Label 14228*/ GIMT_Encode4(887973), // Rule ID 8131 //
     /*  887911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  887914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  887919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887925 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887928 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  887935 */     // MIs[0] src2_modifiers
     /*  887935 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  887938 */     // MIs[0] matrix_a_reuse
     /*  887938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  887941 */     // MIs[0] matrix_b_reuse
     /*  887941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  887944 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  887944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr),
     /*  887947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  887949 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  887951 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  887953 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  887959 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  887961 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  887963 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  887965 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  887971 */     GIR_RootConstrainSelectedInstOperands,
     /*  887972 */     // GIR_Coverage, 8131,
     /*  887972 */     GIR_EraseRootFromParent_Done,
     /*  887973 */   // Label 14228: @887973
     /*  887973 */   GIM_Try, /*On fail goto*//*Label 14229*/ GIMT_Encode4(888040), // Rule ID 8132 //
     /*  887978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  887981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_fp8),
     /*  887986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  887989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  887992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  887995 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  887998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888002 */     // MIs[0] src2_modifiers
     /*  888002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888005 */     // MIs[0] matrix_a_reuse
     /*  888005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888008 */     // MIs[0] matrix_b_reuse
     /*  888008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888011 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3642:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr),
     /*  888014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888016 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888018 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888020 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888026 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888028 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888030 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888038 */     GIR_RootConstrainSelectedInstOperands,
     /*  888039 */     // GIR_Coverage, 8132,
     /*  888039 */     GIR_EraseRootFromParent_Done,
     /*  888040 */   // Label 14229: @888040
     /*  888040 */   GIM_Try, /*On fail goto*//*Label 14230*/ GIMT_Encode4(888107), // Rule ID 8138 //
     /*  888045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  888048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  888053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  888059 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  888062 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888069 */     // MIs[0] src2_modifiers
     /*  888069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888072 */     // MIs[0] matrix_a_reuse
     /*  888072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888075 */     // MIs[0] matrix_b_reuse
     /*  888075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888078 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr),
     /*  888081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888083 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888085 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888087 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888093 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888095 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888097 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888105 */     GIR_RootConstrainSelectedInstOperands,
     /*  888106 */     // GIR_Coverage, 8138,
     /*  888106 */     GIR_EraseRootFromParent_Done,
     /*  888107 */   // Label 14230: @888107
     /*  888107 */   GIM_Try, /*On fail goto*//*Label 14231*/ GIMT_Encode4(888174), // Rule ID 8139 //
     /*  888112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  888115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  888120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  888126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  888129 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888136 */     // MIs[0] src2_modifiers
     /*  888136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888139 */     // MIs[0] matrix_a_reuse
     /*  888139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888142 */     // MIs[0] matrix_b_reuse
     /*  888142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888145 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr),
     /*  888148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888150 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888152 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888154 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888160 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888162 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888164 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888166 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888169 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888172 */     GIR_RootConstrainSelectedInstOperands,
     /*  888173 */     // GIR_Coverage, 8139,
     /*  888173 */     GIR_EraseRootFromParent_Done,
     /*  888174 */   // Label 14231: @888174
     /*  888174 */   GIM_Try, /*On fail goto*//*Label 14232*/ GIMT_Encode4(888241), // Rule ID 8140 //
     /*  888179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  888182 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  888187 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  888193 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  888196 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888203 */     // MIs[0] src2_modifiers
     /*  888203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888206 */     // MIs[0] matrix_a_reuse
     /*  888206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888209 */     // MIs[0] matrix_b_reuse
     /*  888209 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888212 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr),
     /*  888215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888217 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888219 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888221 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888227 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888229 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888231 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888236 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888239 */     GIR_RootConstrainSelectedInstOperands,
     /*  888240 */     // GIR_Coverage, 8140,
     /*  888240 */     GIR_EraseRootFromParent_Done,
     /*  888241 */   // Label 14232: @888241
     /*  888241 */   GIM_Try, /*On fail goto*//*Label 14233*/ GIMT_Encode4(888308), // Rule ID 8141 //
     /*  888246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  888249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  888254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  888260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  888263 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888270 */     // MIs[0] src2_modifiers
     /*  888270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888273 */     // MIs[0] matrix_a_reuse
     /*  888273 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888276 */     // MIs[0] matrix_b_reuse
     /*  888276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888279 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr),
     /*  888282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888284 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888286 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888288 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888294 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888296 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888298 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888306 */     GIR_RootConstrainSelectedInstOperands,
     /*  888307 */     // GIR_Coverage, 8141,
     /*  888307 */     GIR_EraseRootFromParent_Done,
     /*  888308 */   // Label 14233: @888308
     /*  888308 */   GIM_Try, /*On fail goto*//*Label 14234*/ GIMT_Encode4(888375), // Rule ID 8142 //
     /*  888313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  888316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x64_bf8_bf8),
     /*  888321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  888327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  888330 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888337 */     // MIs[0] src2_modifiers
     /*  888337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888340 */     // MIs[0] matrix_a_reuse
     /*  888340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888343 */     // MIs[0] matrix_b_reuse
     /*  888343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888346 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3641:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr),
     /*  888349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888351 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888353 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888355 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888361 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888363 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888365 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888367 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888373 */     GIR_RootConstrainSelectedInstOperands,
     /*  888374 */     // GIR_Coverage, 8142,
     /*  888374 */     GIR_EraseRootFromParent_Done,
     /*  888375 */   // Label 14234: @888375
     /*  888375 */   GIM_Try, /*On fail goto*//*Label 14235*/ GIMT_Encode4(888442), // Rule ID 8178 //
     /*  888380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  888383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  888388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888397 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888404 */     // MIs[0] src2_modifiers
     /*  888404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888407 */     // MIs[0] matrix_a_reuse
     /*  888407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888410 */     // MIs[0] matrix_b_reuse
     /*  888410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888413 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  888416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888418 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888420 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888422 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888428 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888430 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888432 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888434 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888440 */     GIR_RootConstrainSelectedInstOperands,
     /*  888441 */     // GIR_Coverage, 8178,
     /*  888441 */     GIR_EraseRootFromParent_Done,
     /*  888442 */   // Label 14235: @888442
     /*  888442 */   GIM_Try, /*On fail goto*//*Label 14236*/ GIMT_Encode4(888509), // Rule ID 8179 //
     /*  888447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  888450 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  888455 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888458 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888461 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888464 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888471 */     // MIs[0] src2_modifiers
     /*  888471 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888474 */     // MIs[0] matrix_a_reuse
     /*  888474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888477 */     // MIs[0] matrix_b_reuse
     /*  888477 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888480 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  888483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888485 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888487 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888489 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888495 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888497 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888499 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888504 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888507 */     GIR_RootConstrainSelectedInstOperands,
     /*  888508 */     // GIR_Coverage, 8179,
     /*  888508 */     GIR_EraseRootFromParent_Done,
     /*  888509 */   // Label 14236: @888509
     /*  888509 */   GIM_Try, /*On fail goto*//*Label 14237*/ GIMT_Encode4(888576), // Rule ID 8180 //
     /*  888514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  888517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  888522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888531 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888538 */     // MIs[0] src2_modifiers
     /*  888538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888541 */     // MIs[0] matrix_a_reuse
     /*  888541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888544 */     // MIs[0] matrix_b_reuse
     /*  888544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888547 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  888550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888552 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888554 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888556 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888562 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888564 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888566 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888571 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888574 */     GIR_RootConstrainSelectedInstOperands,
     /*  888575 */     // GIR_Coverage, 8180,
     /*  888575 */     GIR_EraseRootFromParent_Done,
     /*  888576 */   // Label 14237: @888576
     /*  888576 */   GIM_Try, /*On fail goto*//*Label 14238*/ GIMT_Encode4(888643), // Rule ID 8181 //
     /*  888581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  888584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  888589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888598 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888605 */     // MIs[0] src2_modifiers
     /*  888605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888608 */     // MIs[0] matrix_a_reuse
     /*  888608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888611 */     // MIs[0] matrix_b_reuse
     /*  888611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888614 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  888617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888619 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888621 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888623 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888629 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888631 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888633 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888641 */     GIR_RootConstrainSelectedInstOperands,
     /*  888642 */     // GIR_Coverage, 8181,
     /*  888642 */     GIR_EraseRootFromParent_Done,
     /*  888643 */   // Label 14238: @888643
     /*  888643 */   GIM_Try, /*On fail goto*//*Label 14239*/ GIMT_Encode4(888710), // Rule ID 8182 //
     /*  888648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  888651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_fp8),
     /*  888656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888665 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888672 */     // MIs[0] src2_modifiers
     /*  888672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888675 */     // MIs[0] matrix_a_reuse
     /*  888675 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888678 */     // MIs[0] matrix_b_reuse
     /*  888678 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888681 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3637:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr),
     /*  888684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888686 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888688 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888690 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888696 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888698 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888700 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888708 */     GIR_RootConstrainSelectedInstOperands,
     /*  888709 */     // GIR_Coverage, 8182,
     /*  888709 */     GIR_EraseRootFromParent_Done,
     /*  888710 */   // Label 14239: @888710
     /*  888710 */   GIM_Try, /*On fail goto*//*Label 14240*/ GIMT_Encode4(888777), // Rule ID 8188 //
     /*  888715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  888718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  888723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888726 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888732 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888739 */     // MIs[0] src2_modifiers
     /*  888739 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888742 */     // MIs[0] matrix_a_reuse
     /*  888742 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888745 */     // MIs[0] matrix_b_reuse
     /*  888745 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888748 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  888751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888753 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888755 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888757 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888763 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888765 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888767 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888775 */     GIR_RootConstrainSelectedInstOperands,
     /*  888776 */     // GIR_Coverage, 8188,
     /*  888776 */     GIR_EraseRootFromParent_Done,
     /*  888777 */   // Label 14240: @888777
     /*  888777 */   GIM_Try, /*On fail goto*//*Label 14241*/ GIMT_Encode4(888844), // Rule ID 8189 //
     /*  888782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  888785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  888790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888796 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888799 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888806 */     // MIs[0] src2_modifiers
     /*  888806 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888809 */     // MIs[0] matrix_a_reuse
     /*  888809 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888812 */     // MIs[0] matrix_b_reuse
     /*  888812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888815 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  888818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888820 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888822 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888824 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888830 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888832 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888834 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888839 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888842 */     GIR_RootConstrainSelectedInstOperands,
     /*  888843 */     // GIR_Coverage, 8189,
     /*  888843 */     GIR_EraseRootFromParent_Done,
     /*  888844 */   // Label 14241: @888844
     /*  888844 */   GIM_Try, /*On fail goto*//*Label 14242*/ GIMT_Encode4(888911), // Rule ID 8190 //
     /*  888849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  888852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  888857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888866 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888873 */     // MIs[0] src2_modifiers
     /*  888873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888876 */     // MIs[0] matrix_a_reuse
     /*  888876 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888879 */     // MIs[0] matrix_b_reuse
     /*  888879 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888882 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  888885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888887 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888889 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888891 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888897 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888899 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888901 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888903 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888909 */     GIR_RootConstrainSelectedInstOperands,
     /*  888910 */     // GIR_Coverage, 8190,
     /*  888910 */     GIR_EraseRootFromParent_Done,
     /*  888911 */   // Label 14242: @888911
     /*  888911 */   GIM_Try, /*On fail goto*//*Label 14243*/ GIMT_Encode4(888978), // Rule ID 8191 //
     /*  888916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  888919 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  888924 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888927 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888930 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  888933 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  888936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  888940 */     // MIs[0] src2_modifiers
     /*  888940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  888943 */     // MIs[0] matrix_a_reuse
     /*  888943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  888946 */     // MIs[0] matrix_b_reuse
     /*  888946 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  888949 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  888949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  888952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  888954 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  888956 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  888958 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  888964 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  888966 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  888968 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  888970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  888976 */     GIR_RootConstrainSelectedInstOperands,
     /*  888977 */     // GIR_Coverage, 8191,
     /*  888977 */     GIR_EraseRootFromParent_Done,
     /*  888978 */   // Label 14243: @888978
     /*  888978 */   GIM_Try, /*On fail goto*//*Label 14244*/ GIMT_Encode4(889045), // Rule ID 8192 //
     /*  888983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  888986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_fp8_bf8),
     /*  888991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  888994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  888997 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889000 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889007 */     // MIs[0] src2_modifiers
     /*  889007 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889010 */     // MIs[0] matrix_a_reuse
     /*  889010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889013 */     // MIs[0] matrix_b_reuse
     /*  889013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889016 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3636:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr),
     /*  889019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889021 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889023 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889025 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889031 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889033 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889035 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889043 */     GIR_RootConstrainSelectedInstOperands,
     /*  889044 */     // GIR_Coverage, 8192,
     /*  889044 */     GIR_EraseRootFromParent_Done,
     /*  889045 */   // Label 14244: @889045
     /*  889045 */   GIM_Try, /*On fail goto*//*Label 14245*/ GIMT_Encode4(889112), // Rule ID 8198 //
     /*  889050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  889053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  889058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889067 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889074 */     // MIs[0] src2_modifiers
     /*  889074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889077 */     // MIs[0] matrix_a_reuse
     /*  889077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889080 */     // MIs[0] matrix_b_reuse
     /*  889080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889083 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  889086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889088 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889090 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889092 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889098 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889100 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889102 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889110 */     GIR_RootConstrainSelectedInstOperands,
     /*  889111 */     // GIR_Coverage, 8198,
     /*  889111 */     GIR_EraseRootFromParent_Done,
     /*  889112 */   // Label 14245: @889112
     /*  889112 */   GIM_Try, /*On fail goto*//*Label 14246*/ GIMT_Encode4(889179), // Rule ID 8199 //
     /*  889117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  889120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  889125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889134 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889141 */     // MIs[0] src2_modifiers
     /*  889141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889144 */     // MIs[0] matrix_a_reuse
     /*  889144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889147 */     // MIs[0] matrix_b_reuse
     /*  889147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889150 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  889153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889155 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889157 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889159 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889165 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889167 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889169 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889177 */     GIR_RootConstrainSelectedInstOperands,
     /*  889178 */     // GIR_Coverage, 8199,
     /*  889178 */     GIR_EraseRootFromParent_Done,
     /*  889179 */   // Label 14246: @889179
     /*  889179 */   GIM_Try, /*On fail goto*//*Label 14247*/ GIMT_Encode4(889246), // Rule ID 8200 //
     /*  889184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  889187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  889192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889201 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889208 */     // MIs[0] src2_modifiers
     /*  889208 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889211 */     // MIs[0] matrix_a_reuse
     /*  889211 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889214 */     // MIs[0] matrix_b_reuse
     /*  889214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889217 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  889220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889222 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889224 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889226 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889232 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889234 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889236 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889244 */     GIR_RootConstrainSelectedInstOperands,
     /*  889245 */     // GIR_Coverage, 8200,
     /*  889245 */     GIR_EraseRootFromParent_Done,
     /*  889246 */   // Label 14247: @889246
     /*  889246 */   GIM_Try, /*On fail goto*//*Label 14248*/ GIMT_Encode4(889313), // Rule ID 8201 //
     /*  889251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  889254 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  889259 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889262 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889265 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889268 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889275 */     // MIs[0] src2_modifiers
     /*  889275 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889278 */     // MIs[0] matrix_a_reuse
     /*  889278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889281 */     // MIs[0] matrix_b_reuse
     /*  889281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889284 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  889287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889289 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889291 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889293 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889299 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889301 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889303 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889311 */     GIR_RootConstrainSelectedInstOperands,
     /*  889312 */     // GIR_Coverage, 8201,
     /*  889312 */     GIR_EraseRootFromParent_Done,
     /*  889313 */   // Label 14248: @889313
     /*  889313 */   GIM_Try, /*On fail goto*//*Label 14249*/ GIMT_Encode4(889380), // Rule ID 8202 //
     /*  889318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  889321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_fp8),
     /*  889326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889335 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889342 */     // MIs[0] src2_modifiers
     /*  889342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889345 */     // MIs[0] matrix_a_reuse
     /*  889345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889348 */     // MIs[0] matrix_b_reuse
     /*  889348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889351 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3635:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr),
     /*  889354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889356 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889358 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889360 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889366 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889368 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889370 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889372 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889378 */     GIR_RootConstrainSelectedInstOperands,
     /*  889379 */     // GIR_Coverage, 8202,
     /*  889379 */     GIR_EraseRootFromParent_Done,
     /*  889380 */   // Label 14249: @889380
     /*  889380 */   GIM_Try, /*On fail goto*//*Label 14250*/ GIMT_Encode4(889447), // Rule ID 8208 //
     /*  889385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  889388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  889393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889402 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889409 */     // MIs[0] src2_modifiers
     /*  889409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889412 */     // MIs[0] matrix_a_reuse
     /*  889412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889415 */     // MIs[0] matrix_b_reuse
     /*  889415 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889418 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  889421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889423 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889425 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889427 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889433 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889435 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889437 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889445 */     GIR_RootConstrainSelectedInstOperands,
     /*  889446 */     // GIR_Coverage, 8208,
     /*  889446 */     GIR_EraseRootFromParent_Done,
     /*  889447 */   // Label 14250: @889447
     /*  889447 */   GIM_Try, /*On fail goto*//*Label 14251*/ GIMT_Encode4(889514), // Rule ID 8209 //
     /*  889452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  889455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  889460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889469 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889476 */     // MIs[0] src2_modifiers
     /*  889476 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889479 */     // MIs[0] matrix_a_reuse
     /*  889479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889482 */     // MIs[0] matrix_b_reuse
     /*  889482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889485 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  889488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889490 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889492 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889494 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889500 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889502 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889504 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889506 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889512 */     GIR_RootConstrainSelectedInstOperands,
     /*  889513 */     // GIR_Coverage, 8209,
     /*  889513 */     GIR_EraseRootFromParent_Done,
     /*  889514 */   // Label 14251: @889514
     /*  889514 */   GIM_Try, /*On fail goto*//*Label 14252*/ GIMT_Encode4(889581), // Rule ID 8210 //
     /*  889519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  889522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  889527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889536 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889543 */     // MIs[0] src2_modifiers
     /*  889543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889546 */     // MIs[0] matrix_a_reuse
     /*  889546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889549 */     // MIs[0] matrix_b_reuse
     /*  889549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889552 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  889555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889557 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889559 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889561 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889567 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889569 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889571 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889579 */     GIR_RootConstrainSelectedInstOperands,
     /*  889580 */     // GIR_Coverage, 8210,
     /*  889580 */     GIR_EraseRootFromParent_Done,
     /*  889581 */   // Label 14252: @889581
     /*  889581 */   GIM_Try, /*On fail goto*//*Label 14253*/ GIMT_Encode4(889648), // Rule ID 8211 //
     /*  889586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  889589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  889594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889603 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889610 */     // MIs[0] src2_modifiers
     /*  889610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889613 */     // MIs[0] matrix_a_reuse
     /*  889613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889616 */     // MIs[0] matrix_b_reuse
     /*  889616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889619 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  889622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889624 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889626 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889628 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889634 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889636 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889638 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889643 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889646 */     GIR_RootConstrainSelectedInstOperands,
     /*  889647 */     // GIR_Coverage, 8211,
     /*  889647 */     GIR_EraseRootFromParent_Done,
     /*  889648 */   // Label 14253: @889648
     /*  889648 */   GIM_Try, /*On fail goto*//*Label 14254*/ GIMT_Encode4(889715), // Rule ID 8212 //
     /*  889653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  889656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x128_bf8_bf8),
     /*  889661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  889664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889670 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
     /*  889673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  889677 */     // MIs[0] src2_modifiers
     /*  889677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889680 */     // MIs[0] matrix_a_reuse
     /*  889680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889683 */     // MIs[0] matrix_b_reuse
     /*  889683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889686 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3634:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f16] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr),
     /*  889689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889691 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889693 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889695 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889701 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889703 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889705 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889713 */     GIR_RootConstrainSelectedInstOperands,
     /*  889714 */     // GIR_Coverage, 8212,
     /*  889714 */     GIR_EraseRootFromParent_Done,
     /*  889715 */   // Label 14254: @889715
     /*  889715 */   GIM_Try, /*On fail goto*//*Label 14255*/ GIMT_Encode4(889782), // Rule ID 8218 //
     /*  889720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  889723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  889728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  889731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889737 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  889740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  889744 */     // MIs[0] src2_modifiers
     /*  889744 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889747 */     // MIs[0] matrix_a_reuse
     /*  889747 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889750 */     // MIs[0] matrix_b_reuse
     /*  889750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889753 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  889756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889758 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889760 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889762 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889768 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889770 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889772 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889780 */     GIR_RootConstrainSelectedInstOperands,
     /*  889781 */     // GIR_Coverage, 8218,
     /*  889781 */     GIR_EraseRootFromParent_Done,
     /*  889782 */   // Label 14255: @889782
     /*  889782 */   GIM_Try, /*On fail goto*//*Label 14256*/ GIMT_Encode4(889849), // Rule ID 8219 //
     /*  889787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  889790 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  889795 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  889798 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889801 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889804 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  889807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  889811 */     // MIs[0] src2_modifiers
     /*  889811 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889814 */     // MIs[0] matrix_a_reuse
     /*  889814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889817 */     // MIs[0] matrix_b_reuse
     /*  889817 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889820 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889820 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  889823 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889825 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889827 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889829 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889835 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889837 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889839 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889844 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889847 */     GIR_RootConstrainSelectedInstOperands,
     /*  889848 */     // GIR_Coverage, 8219,
     /*  889848 */     GIR_EraseRootFromParent_Done,
     /*  889849 */   // Label 14256: @889849
     /*  889849 */   GIM_Try, /*On fail goto*//*Label 14257*/ GIMT_Encode4(889916), // Rule ID 8220 //
     /*  889854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  889857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  889862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  889865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889871 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  889874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  889878 */     // MIs[0] src2_modifiers
     /*  889878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889881 */     // MIs[0] matrix_a_reuse
     /*  889881 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889884 */     // MIs[0] matrix_b_reuse
     /*  889884 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889887 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  889890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889892 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889894 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889896 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889902 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889904 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889906 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889914 */     GIR_RootConstrainSelectedInstOperands,
     /*  889915 */     // GIR_Coverage, 8220,
     /*  889915 */     GIR_EraseRootFromParent_Done,
     /*  889916 */   // Label 14257: @889916
     /*  889916 */   GIM_Try, /*On fail goto*//*Label 14258*/ GIMT_Encode4(889983), // Rule ID 8221 //
     /*  889921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  889924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  889929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  889932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  889935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  889938 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  889941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  889945 */     // MIs[0] src2_modifiers
     /*  889945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  889948 */     // MIs[0] matrix_a_reuse
     /*  889948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  889951 */     // MIs[0] matrix_b_reuse
     /*  889951 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  889954 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  889954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  889957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  889959 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  889961 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  889963 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  889969 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  889971 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  889973 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  889975 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889978 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  889981 */     GIR_RootConstrainSelectedInstOperands,
     /*  889982 */     // GIR_Coverage, 8221,
     /*  889982 */     GIR_EraseRootFromParent_Done,
     /*  889983 */   // Label 14258: @889983
     /*  889983 */   GIM_Try, /*On fail goto*//*Label 14259*/ GIMT_Encode4(890050), // Rule ID 8222 //
     /*  889988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  889991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_fp8),
     /*  889996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  889999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890005 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890012 */     // MIs[0] src2_modifiers
     /*  890012 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890015 */     // MIs[0] matrix_a_reuse
     /*  890015 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890018 */     // MIs[0] matrix_b_reuse
     /*  890018 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890021 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3649:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr),
     /*  890024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890026 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890028 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890030 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890036 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890038 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890040 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890048 */     GIR_RootConstrainSelectedInstOperands,
     /*  890049 */     // GIR_Coverage, 8222,
     /*  890049 */     GIR_EraseRootFromParent_Done,
     /*  890050 */   // Label 14259: @890050
     /*  890050 */   GIM_Try, /*On fail goto*//*Label 14260*/ GIMT_Encode4(890117), // Rule ID 8228 //
     /*  890055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  890058 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  890063 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890066 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890069 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890072 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890079 */     // MIs[0] src2_modifiers
     /*  890079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890082 */     // MIs[0] matrix_a_reuse
     /*  890082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890085 */     // MIs[0] matrix_b_reuse
     /*  890085 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890088 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  890091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890097 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890103 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890105 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890107 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890115 */     GIR_RootConstrainSelectedInstOperands,
     /*  890116 */     // GIR_Coverage, 8228,
     /*  890116 */     GIR_EraseRootFromParent_Done,
     /*  890117 */   // Label 14260: @890117
     /*  890117 */   GIM_Try, /*On fail goto*//*Label 14261*/ GIMT_Encode4(890184), // Rule ID 8229 //
     /*  890122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  890125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  890130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890139 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890146 */     // MIs[0] src2_modifiers
     /*  890146 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890149 */     // MIs[0] matrix_a_reuse
     /*  890149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890152 */     // MIs[0] matrix_b_reuse
     /*  890152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890155 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  890158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890160 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890162 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890164 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890170 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890172 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890174 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890182 */     GIR_RootConstrainSelectedInstOperands,
     /*  890183 */     // GIR_Coverage, 8229,
     /*  890183 */     GIR_EraseRootFromParent_Done,
     /*  890184 */   // Label 14261: @890184
     /*  890184 */   GIM_Try, /*On fail goto*//*Label 14262*/ GIMT_Encode4(890251), // Rule ID 8230 //
     /*  890189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  890192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  890197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890206 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890213 */     // MIs[0] src2_modifiers
     /*  890213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890216 */     // MIs[0] matrix_a_reuse
     /*  890216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890219 */     // MIs[0] matrix_b_reuse
     /*  890219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890222 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  890225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890229 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890231 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890237 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890239 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890241 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890243 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890249 */     GIR_RootConstrainSelectedInstOperands,
     /*  890250 */     // GIR_Coverage, 8230,
     /*  890250 */     GIR_EraseRootFromParent_Done,
     /*  890251 */   // Label 14262: @890251
     /*  890251 */   GIM_Try, /*On fail goto*//*Label 14263*/ GIMT_Encode4(890318), // Rule ID 8231 //
     /*  890256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  890259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  890264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890273 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890280 */     // MIs[0] src2_modifiers
     /*  890280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890283 */     // MIs[0] matrix_a_reuse
     /*  890283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890286 */     // MIs[0] matrix_b_reuse
     /*  890286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890289 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  890292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890294 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890296 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890298 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890304 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890306 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890308 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890316 */     GIR_RootConstrainSelectedInstOperands,
     /*  890317 */     // GIR_Coverage, 8231,
     /*  890317 */     GIR_EraseRootFromParent_Done,
     /*  890318 */   // Label 14263: @890318
     /*  890318 */   GIM_Try, /*On fail goto*//*Label 14264*/ GIMT_Encode4(890385), // Rule ID 8232 //
     /*  890323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  890326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_fp8_bf8),
     /*  890331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890337 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890340 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890347 */     // MIs[0] src2_modifiers
     /*  890347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890350 */     // MIs[0] matrix_a_reuse
     /*  890350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890353 */     // MIs[0] matrix_b_reuse
     /*  890353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890356 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3648:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr),
     /*  890359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890361 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890363 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890365 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890371 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890373 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890375 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890383 */     GIR_RootConstrainSelectedInstOperands,
     /*  890384 */     // GIR_Coverage, 8232,
     /*  890384 */     GIR_EraseRootFromParent_Done,
     /*  890385 */   // Label 14264: @890385
     /*  890385 */   GIM_Try, /*On fail goto*//*Label 14265*/ GIMT_Encode4(890452), // Rule ID 8238 //
     /*  890390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  890393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  890398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890407 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890414 */     // MIs[0] src2_modifiers
     /*  890414 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890417 */     // MIs[0] matrix_a_reuse
     /*  890417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890420 */     // MIs[0] matrix_b_reuse
     /*  890420 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890423 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  890426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890428 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890430 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890432 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890438 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890440 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890442 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890444 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890450 */     GIR_RootConstrainSelectedInstOperands,
     /*  890451 */     // GIR_Coverage, 8238,
     /*  890451 */     GIR_EraseRootFromParent_Done,
     /*  890452 */   // Label 14265: @890452
     /*  890452 */   GIM_Try, /*On fail goto*//*Label 14266*/ GIMT_Encode4(890519), // Rule ID 8239 //
     /*  890457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  890460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  890465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890468 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890471 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890474 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890481 */     // MIs[0] src2_modifiers
     /*  890481 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890484 */     // MIs[0] matrix_a_reuse
     /*  890484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890487 */     // MIs[0] matrix_b_reuse
     /*  890487 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890490 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  890493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890495 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890497 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890499 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890505 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890507 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890509 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890514 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890517 */     GIR_RootConstrainSelectedInstOperands,
     /*  890518 */     // GIR_Coverage, 8239,
     /*  890518 */     GIR_EraseRootFromParent_Done,
     /*  890519 */   // Label 14266: @890519
     /*  890519 */   GIM_Try, /*On fail goto*//*Label 14267*/ GIMT_Encode4(890586), // Rule ID 8240 //
     /*  890524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  890527 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  890532 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890535 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890541 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890548 */     // MIs[0] src2_modifiers
     /*  890548 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890551 */     // MIs[0] matrix_a_reuse
     /*  890551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890554 */     // MIs[0] matrix_b_reuse
     /*  890554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890557 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  890560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890562 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890564 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890566 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890572 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890574 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890576 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890578 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890584 */     GIR_RootConstrainSelectedInstOperands,
     /*  890585 */     // GIR_Coverage, 8240,
     /*  890585 */     GIR_EraseRootFromParent_Done,
     /*  890586 */   // Label 14267: @890586
     /*  890586 */   GIM_Try, /*On fail goto*//*Label 14268*/ GIMT_Encode4(890653), // Rule ID 8241 //
     /*  890591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  890594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  890599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890608 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890615 */     // MIs[0] src2_modifiers
     /*  890615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890618 */     // MIs[0] matrix_a_reuse
     /*  890618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890621 */     // MIs[0] matrix_b_reuse
     /*  890621 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890624 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  890627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890629 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890631 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890633 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890639 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890641 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890643 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890651 */     GIR_RootConstrainSelectedInstOperands,
     /*  890652 */     // GIR_Coverage, 8241,
     /*  890652 */     GIR_EraseRootFromParent_Done,
     /*  890653 */   // Label 14268: @890653
     /*  890653 */   GIM_Try, /*On fail goto*//*Label 14269*/ GIMT_Encode4(890720), // Rule ID 8242 //
     /*  890658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  890661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_fp8),
     /*  890666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890675 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890678 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890682 */     // MIs[0] src2_modifiers
     /*  890682 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890685 */     // MIs[0] matrix_a_reuse
     /*  890685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890688 */     // MIs[0] matrix_b_reuse
     /*  890688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890691 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3646:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr),
     /*  890694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890696 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890698 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890700 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890706 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890708 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890710 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890718 */     GIR_RootConstrainSelectedInstOperands,
     /*  890719 */     // GIR_Coverage, 8242,
     /*  890719 */     GIR_EraseRootFromParent_Done,
     /*  890720 */   // Label 14269: @890720
     /*  890720 */   GIM_Try, /*On fail goto*//*Label 14270*/ GIMT_Encode4(890787), // Rule ID 8248 //
     /*  890725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  890728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  890733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890742 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890749 */     // MIs[0] src2_modifiers
     /*  890749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890752 */     // MIs[0] matrix_a_reuse
     /*  890752 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890755 */     // MIs[0] matrix_b_reuse
     /*  890755 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890758 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  890761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890763 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890765 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890767 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890773 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890775 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890777 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890779 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890785 */     GIR_RootConstrainSelectedInstOperands,
     /*  890786 */     // GIR_Coverage, 8248,
     /*  890786 */     GIR_EraseRootFromParent_Done,
     /*  890787 */   // Label 14270: @890787
     /*  890787 */   GIM_Try, /*On fail goto*//*Label 14271*/ GIMT_Encode4(890854), // Rule ID 8249 //
     /*  890792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  890795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  890800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890809 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890816 */     // MIs[0] src2_modifiers
     /*  890816 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890819 */     // MIs[0] matrix_a_reuse
     /*  890819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890822 */     // MIs[0] matrix_b_reuse
     /*  890822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890825 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  890828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890830 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890832 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890834 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890840 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890842 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890844 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890852 */     GIR_RootConstrainSelectedInstOperands,
     /*  890853 */     // GIR_Coverage, 8249,
     /*  890853 */     GIR_EraseRootFromParent_Done,
     /*  890854 */   // Label 14271: @890854
     /*  890854 */   GIM_Try, /*On fail goto*//*Label 14272*/ GIMT_Encode4(890921), // Rule ID 8250 //
     /*  890859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  890862 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  890867 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890870 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890873 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890876 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890883 */     // MIs[0] src2_modifiers
     /*  890883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890886 */     // MIs[0] matrix_a_reuse
     /*  890886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890889 */     // MIs[0] matrix_b_reuse
     /*  890889 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890892 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  890895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890897 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890899 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890901 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890907 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890909 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890911 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890919 */     GIR_RootConstrainSelectedInstOperands,
     /*  890920 */     // GIR_Coverage, 8250,
     /*  890920 */     GIR_EraseRootFromParent_Done,
     /*  890921 */   // Label 14272: @890921
     /*  890921 */   GIM_Try, /*On fail goto*//*Label 14273*/ GIMT_Encode4(890988), // Rule ID 8251 //
     /*  890926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  890929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  890934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  890937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  890940 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  890943 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  890946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  890950 */     // MIs[0] src2_modifiers
     /*  890950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  890953 */     // MIs[0] matrix_a_reuse
     /*  890953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  890956 */     // MIs[0] matrix_b_reuse
     /*  890956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  890959 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  890959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  890962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  890964 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  890966 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  890968 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  890974 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  890976 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  890978 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  890980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  890986 */     GIR_RootConstrainSelectedInstOperands,
     /*  890987 */     // GIR_Coverage, 8251,
     /*  890987 */     GIR_EraseRootFromParent_Done,
     /*  890988 */   // Label 14273: @890988
     /*  890988 */   GIM_Try, /*On fail goto*//*Label 14274*/ GIMT_Encode4(891055), // Rule ID 8252 //
     /*  890993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  890996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x128_bf8_bf8),
     /*  891001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  891007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  891010 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  891013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891017 */     // MIs[0] src2_modifiers
     /*  891017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891020 */     // MIs[0] matrix_a_reuse
     /*  891020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  891023 */     // MIs[0] matrix_b_reuse
     /*  891023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  891026 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3645:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  891026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr),
     /*  891029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891031 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  891033 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  891035 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  891041 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  891043 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_reuse
     /*  891045 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_b_reuse
     /*  891047 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891053 */     GIR_RootConstrainSelectedInstOperands,
     /*  891054 */     // GIR_Coverage, 8252,
     /*  891054 */     GIR_EraseRootFromParent_Done,
     /*  891055 */   // Label 14274: @891055
     /*  891055 */   GIM_Try, /*On fail goto*//*Label 14275*/ GIMT_Encode4(891120), // Rule ID 7768 //
     /*  891060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  891063 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  891068 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891074 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891077 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891084 */     // MIs[0] src0_modifiers
     /*  891084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891087 */     // MIs[0] src1_modifiers
     /*  891087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891090 */     // MIs[0] clamp
     /*  891090 */     // No operand predicates
     /*  891090 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr),
     /*  891093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891095 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891101 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891103 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891109 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891111 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891113 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891118 */     GIR_RootConstrainSelectedInstOperands,
     /*  891119 */     // GIR_Coverage, 7768,
     /*  891119 */     GIR_EraseRootFromParent_Done,
     /*  891120 */   // Label 14275: @891120
     /*  891120 */   GIM_Try, /*On fail goto*//*Label 14276*/ GIMT_Encode4(891185), // Rule ID 7769 //
     /*  891125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  891128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  891133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891139 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891142 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891149 */     // MIs[0] src0_modifiers
     /*  891149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891152 */     // MIs[0] src1_modifiers
     /*  891152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891155 */     // MIs[0] clamp
     /*  891155 */     // No operand predicates
     /*  891155 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr),
     /*  891158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891160 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891166 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891168 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891174 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891176 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891178 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891183 */     GIR_RootConstrainSelectedInstOperands,
     /*  891184 */     // GIR_Coverage, 7769,
     /*  891184 */     GIR_EraseRootFromParent_Done,
     /*  891185 */   // Label 14276: @891185
     /*  891185 */   GIM_Try, /*On fail goto*//*Label 14277*/ GIMT_Encode4(891250), // Rule ID 7770 //
     /*  891190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  891193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  891198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891201 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891204 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891207 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891214 */     // MIs[0] src0_modifiers
     /*  891214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891217 */     // MIs[0] src1_modifiers
     /*  891217 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891220 */     // MIs[0] clamp
     /*  891220 */     // No operand predicates
     /*  891220 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr),
     /*  891223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891225 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891231 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891233 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891239 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891241 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891243 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891248 */     GIR_RootConstrainSelectedInstOperands,
     /*  891249 */     // GIR_Coverage, 7770,
     /*  891249 */     GIR_EraseRootFromParent_Done,
     /*  891250 */   // Label 14277: @891250
     /*  891250 */   GIM_Try, /*On fail goto*//*Label 14278*/ GIMT_Encode4(891315), // Rule ID 7771 //
     /*  891255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  891258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  891263 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891269 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891272 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891279 */     // MIs[0] src0_modifiers
     /*  891279 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891282 */     // MIs[0] src1_modifiers
     /*  891282 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891285 */     // MIs[0] clamp
     /*  891285 */     // No operand predicates
     /*  891285 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr),
     /*  891288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891290 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891296 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891298 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891304 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891306 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891308 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891313 */     GIR_RootConstrainSelectedInstOperands,
     /*  891314 */     // GIR_Coverage, 7771,
     /*  891314 */     GIR_EraseRootFromParent_Done,
     /*  891315 */   // Label 14278: @891315
     /*  891315 */   GIM_Try, /*On fail goto*//*Label 14279*/ GIMT_Encode4(891380), // Rule ID 7772 //
     /*  891320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  891323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  891328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891331 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891334 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891337 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891344 */     // MIs[0] src0_modifiers
     /*  891344 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891347 */     // MIs[0] src1_modifiers
     /*  891347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891350 */     // MIs[0] clamp
     /*  891350 */     // No operand predicates
     /*  891350 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr),
     /*  891353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891355 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891361 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891363 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891369 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891371 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891373 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891378 */     GIR_RootConstrainSelectedInstOperands,
     /*  891379 */     // GIR_Coverage, 7772,
     /*  891379 */     GIR_EraseRootFromParent_Done,
     /*  891380 */   // Label 14279: @891380
     /*  891380 */   GIM_Try, /*On fail goto*//*Label 14280*/ GIMT_Encode4(891445), // Rule ID 7778 //
     /*  891385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  891388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  891393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  891399 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  891402 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891409 */     // MIs[0] src0_modifiers
     /*  891409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891412 */     // MIs[0] src1_modifiers
     /*  891412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891415 */     // MIs[0] clamp
     /*  891415 */     // No operand predicates
     /*  891415 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr),
     /*  891418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891420 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891426 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891428 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891434 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891436 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891438 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891440 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891443 */     GIR_RootConstrainSelectedInstOperands,
     /*  891444 */     // GIR_Coverage, 7778,
     /*  891444 */     GIR_EraseRootFromParent_Done,
     /*  891445 */   // Label 14280: @891445
     /*  891445 */   GIM_Try, /*On fail goto*//*Label 14281*/ GIMT_Encode4(891510), // Rule ID 7779 //
     /*  891450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  891453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  891458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891461 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  891464 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  891467 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891474 */     // MIs[0] src0_modifiers
     /*  891474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891477 */     // MIs[0] src1_modifiers
     /*  891477 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891480 */     // MIs[0] clamp
     /*  891480 */     // No operand predicates
     /*  891480 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr),
     /*  891483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891485 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891491 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891493 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891499 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891501 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891503 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891508 */     GIR_RootConstrainSelectedInstOperands,
     /*  891509 */     // GIR_Coverage, 7779,
     /*  891509 */     GIR_EraseRootFromParent_Done,
     /*  891510 */   // Label 14281: @891510
     /*  891510 */   GIM_Try, /*On fail goto*//*Label 14282*/ GIMT_Encode4(891575), // Rule ID 7780 //
     /*  891515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  891518 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  891523 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  891529 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  891532 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891539 */     // MIs[0] src0_modifiers
     /*  891539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891542 */     // MIs[0] src1_modifiers
     /*  891542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891545 */     // MIs[0] clamp
     /*  891545 */     // No operand predicates
     /*  891545 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr),
     /*  891548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891550 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891556 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891558 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891564 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891566 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891568 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891573 */     GIR_RootConstrainSelectedInstOperands,
     /*  891574 */     // GIR_Coverage, 7780,
     /*  891574 */     GIR_EraseRootFromParent_Done,
     /*  891575 */   // Label 14282: @891575
     /*  891575 */   GIM_Try, /*On fail goto*//*Label 14283*/ GIMT_Encode4(891640), // Rule ID 7781 //
     /*  891580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  891583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  891588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  891594 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  891597 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891604 */     // MIs[0] src0_modifiers
     /*  891604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891607 */     // MIs[0] src1_modifiers
     /*  891607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891610 */     // MIs[0] clamp
     /*  891610 */     // No operand predicates
     /*  891610 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr),
     /*  891613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891615 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891621 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891623 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891629 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891631 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891633 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891638 */     GIR_RootConstrainSelectedInstOperands,
     /*  891639 */     // GIR_Coverage, 7781,
     /*  891639 */     GIR_EraseRootFromParent_Done,
     /*  891640 */   // Label 14283: @891640
     /*  891640 */   GIM_Try, /*On fail goto*//*Label 14284*/ GIMT_Encode4(891705), // Rule ID 7782 //
     /*  891645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  891648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  891653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891656 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  891659 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  891662 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891669 */     // MIs[0] src0_modifiers
     /*  891669 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891672 */     // MIs[0] src1_modifiers
     /*  891672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891675 */     // MIs[0] clamp
     /*  891675 */     // No operand predicates
     /*  891675 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr),
     /*  891678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891680 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891686 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891688 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891694 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891696 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891698 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891703 */     GIR_RootConstrainSelectedInstOperands,
     /*  891704 */     // GIR_Coverage, 7782,
     /*  891704 */     GIR_EraseRootFromParent_Done,
     /*  891705 */   // Label 14284: @891705
     /*  891705 */   GIM_Try, /*On fail goto*//*Label 14285*/ GIMT_Encode4(891770), // Rule ID 7828 //
     /*  891710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  891713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  891718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891724 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891727 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891734 */     // MIs[0] src0_modifiers
     /*  891734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891737 */     // MIs[0] src1_modifiers
     /*  891737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891740 */     // MIs[0] clamp
     /*  891740 */     // No operand predicates
     /*  891740 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr),
     /*  891743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891745 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891751 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891753 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891759 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891761 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891763 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891765 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891768 */     GIR_RootConstrainSelectedInstOperands,
     /*  891769 */     // GIR_Coverage, 7828,
     /*  891769 */     GIR_EraseRootFromParent_Done,
     /*  891770 */   // Label 14285: @891770
     /*  891770 */   GIM_Try, /*On fail goto*//*Label 14286*/ GIMT_Encode4(891835), // Rule ID 7829 //
     /*  891775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  891778 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  891783 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891789 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891792 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891799 */     // MIs[0] src0_modifiers
     /*  891799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891802 */     // MIs[0] src1_modifiers
     /*  891802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891805 */     // MIs[0] clamp
     /*  891805 */     // No operand predicates
     /*  891805 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr),
     /*  891808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891810 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891816 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891818 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891824 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891826 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891828 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891833 */     GIR_RootConstrainSelectedInstOperands,
     /*  891834 */     // GIR_Coverage, 7829,
     /*  891834 */     GIR_EraseRootFromParent_Done,
     /*  891835 */   // Label 14286: @891835
     /*  891835 */   GIM_Try, /*On fail goto*//*Label 14287*/ GIMT_Encode4(891900), // Rule ID 7830 //
     /*  891840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  891843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  891848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891851 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891854 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891857 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891864 */     // MIs[0] src0_modifiers
     /*  891864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891867 */     // MIs[0] src1_modifiers
     /*  891867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891870 */     // MIs[0] clamp
     /*  891870 */     // No operand predicates
     /*  891870 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr),
     /*  891873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891875 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891881 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891883 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891889 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891891 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891893 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891898 */     GIR_RootConstrainSelectedInstOperands,
     /*  891899 */     // GIR_Coverage, 7830,
     /*  891899 */     GIR_EraseRootFromParent_Done,
     /*  891900 */   // Label 14287: @891900
     /*  891900 */   GIM_Try, /*On fail goto*//*Label 14288*/ GIMT_Encode4(891965), // Rule ID 7831 //
     /*  891905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  891908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  891913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891919 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891922 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891929 */     // MIs[0] src0_modifiers
     /*  891929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891932 */     // MIs[0] src1_modifiers
     /*  891932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  891935 */     // MIs[0] clamp
     /*  891935 */     // No operand predicates
     /*  891935 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  891935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr),
     /*  891938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  891940 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  891946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  891948 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  891954 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  891956 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  891958 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  891960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  891963 */     GIR_RootConstrainSelectedInstOperands,
     /*  891964 */     // GIR_Coverage, 7831,
     /*  891964 */     GIR_EraseRootFromParent_Done,
     /*  891965 */   // Label 14288: @891965
     /*  891965 */   GIM_Try, /*On fail goto*//*Label 14289*/ GIMT_Encode4(892030), // Rule ID 7832 //
     /*  891970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  891973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  891978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  891981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  891984 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  891987 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  891990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  891994 */     // MIs[0] src0_modifiers
     /*  891994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  891997 */     // MIs[0] src1_modifiers
     /*  891997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892000 */     // MIs[0] clamp
     /*  892000 */     // No operand predicates
     /*  892000 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr),
     /*  892003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892005 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892011 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892013 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892019 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892021 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892023 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892028 */     GIR_RootConstrainSelectedInstOperands,
     /*  892029 */     // GIR_Coverage, 7832,
     /*  892029 */     GIR_EraseRootFromParent_Done,
     /*  892030 */   // Label 14289: @892030
     /*  892030 */   GIM_Try, /*On fail goto*//*Label 14290*/ GIMT_Encode4(892095), // Rule ID 7933 //
     /*  892035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  892038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  892043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892049 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892052 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892059 */     // MIs[0] src0_modifiers
     /*  892059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892062 */     // MIs[0] src1_modifiers
     /*  892062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892065 */     // MIs[0] clamp
     /*  892065 */     // No operand predicates
     /*  892065 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr),
     /*  892068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892070 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892076 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892078 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892084 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892086 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892088 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892093 */     GIR_RootConstrainSelectedInstOperands,
     /*  892094 */     // GIR_Coverage, 7933,
     /*  892094 */     GIR_EraseRootFromParent_Done,
     /*  892095 */   // Label 14290: @892095
     /*  892095 */   GIM_Try, /*On fail goto*//*Label 14291*/ GIMT_Encode4(892160), // Rule ID 7934 //
     /*  892100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  892103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  892108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892114 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892117 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892124 */     // MIs[0] src0_modifiers
     /*  892124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892127 */     // MIs[0] src1_modifiers
     /*  892127 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892130 */     // MIs[0] clamp
     /*  892130 */     // No operand predicates
     /*  892130 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr),
     /*  892133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892135 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892141 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892143 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892149 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892151 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892153 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892158 */     GIR_RootConstrainSelectedInstOperands,
     /*  892159 */     // GIR_Coverage, 7934,
     /*  892159 */     GIR_EraseRootFromParent_Done,
     /*  892160 */   // Label 14291: @892160
     /*  892160 */   GIM_Try, /*On fail goto*//*Label 14292*/ GIMT_Encode4(892225), // Rule ID 7935 //
     /*  892165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  892168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  892173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892179 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892182 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892189 */     // MIs[0] src0_modifiers
     /*  892189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892192 */     // MIs[0] src1_modifiers
     /*  892192 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892195 */     // MIs[0] clamp
     /*  892195 */     // No operand predicates
     /*  892195 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr),
     /*  892198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892200 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892206 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892208 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892214 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892216 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892218 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892223 */     GIR_RootConstrainSelectedInstOperands,
     /*  892224 */     // GIR_Coverage, 7935,
     /*  892224 */     GIR_EraseRootFromParent_Done,
     /*  892225 */   // Label 14292: @892225
     /*  892225 */   GIM_Try, /*On fail goto*//*Label 14293*/ GIMT_Encode4(892290), // Rule ID 7936 //
     /*  892230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  892233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  892238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892244 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892247 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892254 */     // MIs[0] src0_modifiers
     /*  892254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892257 */     // MIs[0] src1_modifiers
     /*  892257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892260 */     // MIs[0] clamp
     /*  892260 */     // No operand predicates
     /*  892260 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr),
     /*  892263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892265 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892271 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892273 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892279 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892281 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892283 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892288 */     GIR_RootConstrainSelectedInstOperands,
     /*  892289 */     // GIR_Coverage, 7936,
     /*  892289 */     GIR_EraseRootFromParent_Done,
     /*  892290 */   // Label 14293: @892290
     /*  892290 */   GIM_Try, /*On fail goto*//*Label 14294*/ GIMT_Encode4(892355), // Rule ID 7937 //
     /*  892295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  892298 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
     /*  892303 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892306 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892309 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892312 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892319 */     // MIs[0] src0_modifiers
     /*  892319 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892322 */     // MIs[0] src1_modifiers
     /*  892322 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892325 */     // MIs[0] clamp
     /*  892325 */     // No operand predicates
     /*  892325 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3665:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr),
     /*  892328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892330 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892336 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892338 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892344 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892346 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892348 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892350 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892353 */     GIR_RootConstrainSelectedInstOperands,
     /*  892354 */     // GIR_Coverage, 7937,
     /*  892354 */     GIR_EraseRootFromParent_Done,
     /*  892355 */   // Label 14294: @892355
     /*  892355 */   GIM_Try, /*On fail goto*//*Label 14295*/ GIMT_Encode4(892420), // Rule ID 7943 //
     /*  892360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  892363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  892368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892374 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892377 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892384 */     // MIs[0] src0_modifiers
     /*  892384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892387 */     // MIs[0] src1_modifiers
     /*  892387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892390 */     // MIs[0] clamp
     /*  892390 */     // No operand predicates
     /*  892390 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr),
     /*  892393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892395 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892401 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892403 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892409 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892411 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892413 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892418 */     GIR_RootConstrainSelectedInstOperands,
     /*  892419 */     // GIR_Coverage, 7943,
     /*  892419 */     GIR_EraseRootFromParent_Done,
     /*  892420 */   // Label 14295: @892420
     /*  892420 */   GIM_Try, /*On fail goto*//*Label 14296*/ GIMT_Encode4(892485), // Rule ID 7944 //
     /*  892425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  892428 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  892433 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892436 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892439 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892442 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892449 */     // MIs[0] src0_modifiers
     /*  892449 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892452 */     // MIs[0] src1_modifiers
     /*  892452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892455 */     // MIs[0] clamp
     /*  892455 */     // No operand predicates
     /*  892455 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr),
     /*  892458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892460 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892466 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892468 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892474 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892476 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892478 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892483 */     GIR_RootConstrainSelectedInstOperands,
     /*  892484 */     // GIR_Coverage, 7944,
     /*  892484 */     GIR_EraseRootFromParent_Done,
     /*  892485 */   // Label 14296: @892485
     /*  892485 */   GIM_Try, /*On fail goto*//*Label 14297*/ GIMT_Encode4(892550), // Rule ID 7945 //
     /*  892490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  892493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  892498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892504 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892507 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892514 */     // MIs[0] src0_modifiers
     /*  892514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892517 */     // MIs[0] src1_modifiers
     /*  892517 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892520 */     // MIs[0] clamp
     /*  892520 */     // No operand predicates
     /*  892520 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr),
     /*  892523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892525 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892533 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892539 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892541 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892543 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892548 */     GIR_RootConstrainSelectedInstOperands,
     /*  892549 */     // GIR_Coverage, 7945,
     /*  892549 */     GIR_EraseRootFromParent_Done,
     /*  892550 */   // Label 14297: @892550
     /*  892550 */   GIM_Try, /*On fail goto*//*Label 14298*/ GIMT_Encode4(892615), // Rule ID 7946 //
     /*  892555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  892558 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  892563 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892569 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892572 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892579 */     // MIs[0] src0_modifiers
     /*  892579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892582 */     // MIs[0] src1_modifiers
     /*  892582 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892585 */     // MIs[0] clamp
     /*  892585 */     // No operand predicates
     /*  892585 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr),
     /*  892588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892590 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892596 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892598 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892604 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892606 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892608 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892613 */     GIR_RootConstrainSelectedInstOperands,
     /*  892614 */     // GIR_Coverage, 7946,
     /*  892614 */     GIR_EraseRootFromParent_Done,
     /*  892615 */   // Label 14298: @892615
     /*  892615 */   GIM_Try, /*On fail goto*//*Label 14299*/ GIMT_Encode4(892680), // Rule ID 7947 //
     /*  892620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  892623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
     /*  892628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892634 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892637 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892644 */     // MIs[0] src0_modifiers
     /*  892644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892647 */     // MIs[0] src1_modifiers
     /*  892647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892650 */     // MIs[0] clamp
     /*  892650 */     // No operand predicates
     /*  892650 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3664:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr),
     /*  892653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892655 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892661 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892663 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892669 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892671 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892673 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892678 */     GIR_RootConstrainSelectedInstOperands,
     /*  892679 */     // GIR_Coverage, 7947,
     /*  892679 */     GIR_EraseRootFromParent_Done,
     /*  892680 */   // Label 14299: @892680
     /*  892680 */   GIM_Try, /*On fail goto*//*Label 14300*/ GIMT_Encode4(892745), // Rule ID 7993 //
     /*  892685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  892688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  892693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892699 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892702 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892709 */     // MIs[0] src0_modifiers
     /*  892709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892712 */     // MIs[0] src1_modifiers
     /*  892712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892715 */     // MIs[0] clamp
     /*  892715 */     // No operand predicates
     /*  892715 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr),
     /*  892718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892720 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892726 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892728 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892734 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892736 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892738 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892743 */     GIR_RootConstrainSelectedInstOperands,
     /*  892744 */     // GIR_Coverage, 7993,
     /*  892744 */     GIR_EraseRootFromParent_Done,
     /*  892745 */   // Label 14300: @892745
     /*  892745 */   GIM_Try, /*On fail goto*//*Label 14301*/ GIMT_Encode4(892810), // Rule ID 7994 //
     /*  892750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  892753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  892758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892761 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892764 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892767 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892774 */     // MIs[0] src0_modifiers
     /*  892774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892777 */     // MIs[0] src1_modifiers
     /*  892777 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892780 */     // MIs[0] clamp
     /*  892780 */     // No operand predicates
     /*  892780 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr),
     /*  892783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892785 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892791 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892793 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892799 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892801 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892803 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892808 */     GIR_RootConstrainSelectedInstOperands,
     /*  892809 */     // GIR_Coverage, 7994,
     /*  892809 */     GIR_EraseRootFromParent_Done,
     /*  892810 */   // Label 14301: @892810
     /*  892810 */   GIM_Try, /*On fail goto*//*Label 14302*/ GIMT_Encode4(892875), // Rule ID 7995 //
     /*  892815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  892818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  892823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892829 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892832 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892839 */     // MIs[0] src0_modifiers
     /*  892839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892842 */     // MIs[0] src1_modifiers
     /*  892842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892845 */     // MIs[0] clamp
     /*  892845 */     // No operand predicates
     /*  892845 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr),
     /*  892848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892850 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892856 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892858 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892864 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892866 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892868 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892873 */     GIR_RootConstrainSelectedInstOperands,
     /*  892874 */     // GIR_Coverage, 7995,
     /*  892874 */     GIR_EraseRootFromParent_Done,
     /*  892875 */   // Label 14302: @892875
     /*  892875 */   GIM_Try, /*On fail goto*//*Label 14303*/ GIMT_Encode4(892940), // Rule ID 7996 //
     /*  892880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  892883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  892888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892894 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892897 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892904 */     // MIs[0] src0_modifiers
     /*  892904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892907 */     // MIs[0] src1_modifiers
     /*  892907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892910 */     // MIs[0] clamp
     /*  892910 */     // No operand predicates
     /*  892910 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr),
     /*  892913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892915 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892921 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892923 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892929 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892931 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892933 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  892935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  892938 */     GIR_RootConstrainSelectedInstOperands,
     /*  892939 */     // GIR_Coverage, 7996,
     /*  892939 */     GIR_EraseRootFromParent_Done,
     /*  892940 */   // Label 14303: @892940
     /*  892940 */   GIM_Try, /*On fail goto*//*Label 14304*/ GIMT_Encode4(893005), // Rule ID 7997 //
     /*  892945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  892948 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
     /*  892953 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  892956 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  892959 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  892962 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  892965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  892969 */     // MIs[0] src0_modifiers
     /*  892969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  892972 */     // MIs[0] src1_modifiers
     /*  892972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  892975 */     // MIs[0] clamp
     /*  892975 */     // No operand predicates
     /*  892975 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3666:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  892975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr),
     /*  892978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  892980 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  892986 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  892988 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  892994 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  892996 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  892998 */     GIR_RootToRootCopy, /*OpIdx*/7, // clamp
     /*  893000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893003 */     GIR_RootConstrainSelectedInstOperands,
     /*  893004 */     // GIR_Coverage, 7997,
     /*  893004 */     GIR_EraseRootFromParent_Done,
     /*  893005 */   // Label 14304: @893005
     /*  893005 */   GIM_Try, /*On fail goto*//*Label 14305*/ GIMT_Encode4(893076), // Rule ID 7446 //
     /*  893010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  893021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  893024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  893027 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893030 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893037 */     // MIs[0] fi
     /*  893037 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893040 */     // MIs[0] bc
     /*  893040 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893043 */     // (intrinsic_wo_chain:{ *:[i32] } 3346:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893048 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893054 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893056 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893062 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893067 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893069 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893071 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893074 */     GIR_RootConstrainSelectedInstOperands,
     /*  893075 */     // GIR_Coverage, 7446,
     /*  893075 */     GIR_EraseRootFromParent_Done,
     /*  893076 */   // Label 14305: @893076
     /*  893076 */   GIM_Try, /*On fail goto*//*Label 14306*/ GIMT_Encode4(893147), // Rule ID 7447 //
     /*  893081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  893092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  893095 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  893098 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893101 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893108 */     // MIs[0] fi
     /*  893108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893111 */     // MIs[0] bc
     /*  893111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893114 */     // (intrinsic_wo_chain:{ *:[i32] } 3351:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893119 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893125 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893127 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893133 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893138 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893140 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893145 */     GIR_RootConstrainSelectedInstOperands,
     /*  893146 */     // GIR_Coverage, 7447,
     /*  893146 */     GIR_EraseRootFromParent_Done,
     /*  893147 */   // Label 14306: @893147
     /*  893147 */   GIM_Try, /*On fail goto*//*Label 14307*/ GIMT_Encode4(893218), // Rule ID 7448 //
     /*  893152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893155 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893160 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  893163 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  893166 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  893169 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893172 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893179 */     // MIs[0] fi
     /*  893179 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893182 */     // MIs[0] bc
     /*  893182 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893185 */     // (intrinsic_wo_chain:{ *:[f32] } 3346:{ *:[iPTR] }, f32:{ *:[f32] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[f32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[f32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[f32] }:$vdst_in)
     /*  893185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893190 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893196 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893198 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893204 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893209 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893211 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893216 */     GIR_RootConstrainSelectedInstOperands,
     /*  893217 */     // GIR_Coverage, 7448,
     /*  893217 */     GIR_EraseRootFromParent_Done,
     /*  893218 */   // Label 14307: @893218
     /*  893218 */   GIM_Try, /*On fail goto*//*Label 14308*/ GIMT_Encode4(893289), // Rule ID 7449 //
     /*  893223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893226 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893231 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  893234 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  893237 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  893240 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893243 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893250 */     // MIs[0] fi
     /*  893250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893253 */     // MIs[0] bc
     /*  893253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893256 */     // (intrinsic_wo_chain:{ *:[f32] } 3351:{ *:[iPTR] }, f32:{ *:[f32] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[f32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[f32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[f32] }:$vdst_in)
     /*  893256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893261 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893267 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893269 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893275 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893280 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893282 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893287 */     GIR_RootConstrainSelectedInstOperands,
     /*  893288 */     // GIR_Coverage, 7449,
     /*  893288 */     GIR_EraseRootFromParent_Done,
     /*  893289 */   // Label 14308: @893289
     /*  893289 */   GIM_Try, /*On fail goto*//*Label 14309*/ GIMT_Encode4(893360), // Rule ID 7450 //
     /*  893294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  893305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  893308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  893311 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893314 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893321 */     // MIs[0] fi
     /*  893321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893324 */     // MIs[0] bc
     /*  893324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893327 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3346:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[v2i16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2i16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2i16] }:$vdst_in)
     /*  893327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893332 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893338 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893340 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893346 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893351 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893353 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893358 */     GIR_RootConstrainSelectedInstOperands,
     /*  893359 */     // GIR_Coverage, 7450,
     /*  893359 */     GIR_EraseRootFromParent_Done,
     /*  893360 */   // Label 14309: @893360
     /*  893360 */   GIM_Try, /*On fail goto*//*Label 14310*/ GIMT_Encode4(893431), // Rule ID 7451 //
     /*  893365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893368 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893373 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  893376 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  893379 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  893382 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893385 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893392 */     // MIs[0] fi
     /*  893392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893395 */     // MIs[0] bc
     /*  893395 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893398 */     // (intrinsic_wo_chain:{ *:[v2i16] } 3351:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[v2i16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2i16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2i16] }:$vdst_in)
     /*  893398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893403 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893409 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893411 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893417 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893422 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893424 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893426 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893429 */     GIR_RootConstrainSelectedInstOperands,
     /*  893430 */     // GIR_Coverage, 7451,
     /*  893430 */     GIR_EraseRootFromParent_Done,
     /*  893431 */   // Label 14310: @893431
     /*  893431 */   GIM_Try, /*On fail goto*//*Label 14311*/ GIMT_Encode4(893502), // Rule ID 7452 //
     /*  893436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893439 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893444 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  893447 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  893450 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  893453 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893456 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893463 */     // MIs[0] fi
     /*  893463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893466 */     // MIs[0] bc
     /*  893466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893469 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3346:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[v2f16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2f16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  893469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893474 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893480 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893482 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893488 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893493 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893495 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893500 */     GIR_RootConstrainSelectedInstOperands,
     /*  893501 */     // GIR_Coverage, 7452,
     /*  893501 */     GIR_EraseRootFromParent_Done,
     /*  893502 */   // Label 14311: @893502
     /*  893502 */   GIM_Try, /*On fail goto*//*Label 14312*/ GIMT_Encode4(893573), // Rule ID 7453 //
     /*  893507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /*  893518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  893521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  893524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893527 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893534 */     // MIs[0] fi
     /*  893534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893537 */     // MIs[0] bc
     /*  893537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893540 */     // (intrinsic_wo_chain:{ *:[v2f16] } 3351:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[v2f16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2f16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2f16] }:$vdst_in)
     /*  893540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893545 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893551 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893553 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893559 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893564 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893566 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893571 */     GIR_RootConstrainSelectedInstOperands,
     /*  893572 */     // GIR_Coverage, 7453,
     /*  893572 */     GIR_EraseRootFromParent_Done,
     /*  893573 */   // Label 14312: @893573
     /*  893573 */   GIM_Try, /*On fail goto*//*Label 14313*/ GIMT_Encode4(893644), // Rule ID 7454 //
     /*  893578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  893589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  893592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  893595 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893598 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893605 */     // MIs[0] fi
     /*  893605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893608 */     // MIs[0] bc
     /*  893608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893611 */     // (intrinsic_wo_chain:{ *:[i32] } 3346:{ *:[iPTR] }, p2:{ *:[i32] }:$vdst_in, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893616 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893622 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893624 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893630 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893635 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893637 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893642 */     GIR_RootConstrainSelectedInstOperands,
     /*  893643 */     // GIR_Coverage, 7454,
     /*  893643 */     GIR_EraseRootFromParent_Done,
     /*  893644 */   // Label 14313: @893644
     /*  893644 */   GIM_Try, /*On fail goto*//*Label 14314*/ GIMT_Encode4(893715), // Rule ID 7455 //
     /*  893649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32,
     /*  893660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32,
     /*  893663 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32,
     /*  893666 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893669 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893676 */     // MIs[0] fi
     /*  893676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893679 */     // MIs[0] bc
     /*  893679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893682 */     // (intrinsic_wo_chain:{ *:[i32] } 3351:{ *:[iPTR] }, p2:{ *:[i32] }:$vdst_in, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893687 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893693 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893695 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893701 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893706 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893708 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893713 */     GIR_RootConstrainSelectedInstOperands,
     /*  893714 */     // GIR_Coverage, 7455,
     /*  893714 */     GIR_EraseRootFromParent_Done,
     /*  893715 */   // Label 14314: @893715
     /*  893715 */   GIM_Try, /*On fail goto*//*Label 14315*/ GIMT_Encode4(893786), // Rule ID 7456 //
     /*  893720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  893731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  893734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  893737 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893740 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893747 */     // MIs[0] fi
     /*  893747 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893750 */     // MIs[0] bc
     /*  893750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893753 */     // (intrinsic_wo_chain:{ *:[i32] } 3346:{ *:[iPTR] }, p3:{ *:[i32] }:$vdst_in, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893758 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893764 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893766 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893772 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893777 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893779 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893784 */     GIR_RootConstrainSelectedInstOperands,
     /*  893785 */     // GIR_Coverage, 7456,
     /*  893785 */     GIR_EraseRootFromParent_Done,
     /*  893786 */   // Label 14315: @893786
     /*  893786 */   GIM_Try, /*On fail goto*//*Label 14316*/ GIMT_Encode4(893857), // Rule ID 7457 //
     /*  893791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32,
     /*  893802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32,
     /*  893805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32,
     /*  893808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893811 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893818 */     // MIs[0] fi
     /*  893818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893821 */     // MIs[0] bc
     /*  893821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893824 */     // (intrinsic_wo_chain:{ *:[i32] } 3351:{ *:[iPTR] }, p3:{ *:[i32] }:$vdst_in, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893829 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893835 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893837 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893843 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893848 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893850 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893852 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893855 */     GIR_RootConstrainSelectedInstOperands,
     /*  893856 */     // GIR_Coverage, 7457,
     /*  893856 */     GIR_EraseRootFromParent_Done,
     /*  893857 */   // Label 14316: @893857
     /*  893857 */   GIM_Try, /*On fail goto*//*Label 14317*/ GIMT_Encode4(893928), // Rule ID 7458 //
     /*  893862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  893870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  893873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  893876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  893879 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893882 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893889 */     // MIs[0] fi
     /*  893889 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893892 */     // MIs[0] bc
     /*  893892 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893895 */     // (intrinsic_wo_chain:{ *:[i32] } 3346:{ *:[iPTR] }, p5:{ *:[i32] }:$vdst_in, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  893898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893900 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893906 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893908 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893914 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893919 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893921 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893926 */     GIR_RootConstrainSelectedInstOperands,
     /*  893927 */     // GIR_Coverage, 7458,
     /*  893927 */     GIR_EraseRootFromParent_Done,
     /*  893928 */   // Label 14317: @893928
     /*  893928 */   GIM_Try, /*On fail goto*//*Label 14318*/ GIMT_Encode4(893999), // Rule ID 7459 //
     /*  893933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  893936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  893941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32,
     /*  893944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32,
     /*  893947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32,
     /*  893950 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  893953 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  893956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  893960 */     // MIs[0] fi
     /*  893960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  893963 */     // MIs[0] bc
     /*  893963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  893966 */     // (intrinsic_wo_chain:{ *:[i32] } 3351:{ *:[iPTR] }, p5:{ *:[i32] }:$vdst_in, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  893966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  893969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  893971 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  893977 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  893979 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  893985 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  893987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893990 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  893992 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  893994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  893997 */     GIR_RootConstrainSelectedInstOperands,
     /*  893998 */     // GIR_Coverage, 7459,
     /*  893998 */     GIR_EraseRootFromParent_Done,
     /*  893999 */   // Label 14318: @893999
     /*  893999 */   GIM_Try, /*On fail goto*//*Label 14319*/ GIMT_Encode4(894070), // Rule ID 7460 //
     /*  894004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  894007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
     /*  894012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  894015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  894018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  894021 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  894024 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  894027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  894031 */     // MIs[0] fi
     /*  894031 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894034 */     // MIs[0] bc
     /*  894034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894037 */     // (intrinsic_wo_chain:{ *:[i32] } 3346:{ *:[iPTR] }, p6:{ *:[i32] }:$vdst_in, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  894037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
     /*  894040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894042 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  894048 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  894050 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  894056 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  894058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  894061 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  894063 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  894065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  894068 */     GIR_RootConstrainSelectedInstOperands,
     /*  894069 */     // GIR_Coverage, 7460,
     /*  894069 */     GIR_EraseRootFromParent_Done,
     /*  894070 */   // Label 14319: @894070
     /*  894070 */   GIM_Try, /*On fail goto*//*Label 14320*/ GIMT_Encode4(894141), // Rule ID 7461 //
     /*  894075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
     /*  894078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
     /*  894083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32,
     /*  894086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32,
     /*  894089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32,
     /*  894092 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  894095 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  894098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  894102 */     // MIs[0] fi
     /*  894102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894105 */     // MIs[0] bc
     /*  894105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894108 */     // (intrinsic_wo_chain:{ *:[i32] } 3351:{ *:[iPTR] }, p6:{ *:[i32] }:$vdst_in, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
     /*  894108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
     /*  894111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894113 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
     /*  894119 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  894121 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
     /*  894127 */     GIR_RootToRootCopy, /*OpIdx*/4, // src1
     /*  894129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  894132 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  894134 */     GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in
     /*  894136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  894139 */     GIR_RootConstrainSelectedInstOperands,
     /*  894140 */     // GIR_Coverage, 7461,
     /*  894140 */     GIR_EraseRootFromParent_Done,
     /*  894141 */   // Label 14320: @894141
     /*  894141 */   GIM_Try, /*On fail goto*//*Label 14321*/ GIMT_Encode4(894202), // Rule ID 3349 //
     /*  894146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  894149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  894154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894160 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894163 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894170 */     // MIs[0] cbsz
     /*  894170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894173 */     // MIs[0] abid
     /*  894173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894176 */     // MIs[0] blgp
     /*  894176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894179 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31712),
     /*  894183 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31712>>  =>  (V_MFMA_F32_4X4X1F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_e64),
     /*  894186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894188 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894190 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894192 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894194 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894196 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894198 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894200 */     GIR_RootConstrainSelectedInstOperands,
     /*  894201 */     // GIR_Coverage, 3349,
     /*  894201 */     GIR_EraseRootFromParent_Done,
     /*  894202 */   // Label 14321: @894202
     /*  894202 */   GIM_Try, /*On fail goto*//*Label 14322*/ GIMT_Encode4(894263), // Rule ID 3350 //
     /*  894207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  894210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  894215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894224 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894231 */     // MIs[0] cbsz
     /*  894231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894234 */     // MIs[0] abid
     /*  894234 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894237 */     // MIs[0] blgp
     /*  894237 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894240 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31712),
     /*  894244 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31712>>  =>  (V_MFMA_F32_4X4X1F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_e64),
     /*  894247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894249 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894251 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894253 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894255 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894257 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894259 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894261 */     GIR_RootConstrainSelectedInstOperands,
     /*  894262 */     // GIR_Coverage, 3350,
     /*  894262 */     GIR_EraseRootFromParent_Done,
     /*  894263 */   // Label 14322: @894263
     /*  894263 */   GIM_Try, /*On fail goto*//*Label 14323*/ GIMT_Encode4(894324), // Rule ID 3356 //
     /*  894268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  894271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  894276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  894279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894285 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  894288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  894292 */     // MIs[0] cbsz
     /*  894292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894295 */     // MIs[0] abid
     /*  894295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894298 */     // MIs[0] blgp
     /*  894298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894301 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31718),
     /*  894305 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31718>>  =>  (V_MFMA_F32_16X16X1F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_e64),
     /*  894308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894310 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894312 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894314 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894316 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894318 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894320 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894322 */     GIR_RootConstrainSelectedInstOperands,
     /*  894323 */     // GIR_Coverage, 3356,
     /*  894323 */     GIR_EraseRootFromParent_Done,
     /*  894324 */   // Label 14323: @894324
     /*  894324 */   GIM_Try, /*On fail goto*//*Label 14324*/ GIMT_Encode4(894385), // Rule ID 3357 //
     /*  894329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  894332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  894337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  894340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894346 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  894349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  894353 */     // MIs[0] cbsz
     /*  894353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894356 */     // MIs[0] abid
     /*  894356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894359 */     // MIs[0] blgp
     /*  894359 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894362 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31718),
     /*  894366 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31718>>  =>  (V_MFMA_F32_16X16X1F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_e64),
     /*  894369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894371 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894373 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894375 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894377 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894379 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894381 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894383 */     GIR_RootConstrainSelectedInstOperands,
     /*  894384 */     // GIR_Coverage, 3357,
     /*  894384 */     GIR_EraseRootFromParent_Done,
     /*  894385 */   // Label 14324: @894385
     /*  894385 */   GIM_Try, /*On fail goto*//*Label 14325*/ GIMT_Encode4(894446), // Rule ID 3363 //
     /*  894390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  894393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  894398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894407 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894414 */     // MIs[0] cbsz
     /*  894414 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894417 */     // MIs[0] abid
     /*  894417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894420 */     // MIs[0] blgp
     /*  894420 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894423 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31722),
     /*  894427 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31722>>  =>  (V_MFMA_F32_16X16X4F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_e64),
     /*  894430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894432 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894434 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894436 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894438 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894440 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894442 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894444 */     GIR_RootConstrainSelectedInstOperands,
     /*  894445 */     // GIR_Coverage, 3363,
     /*  894445 */     GIR_EraseRootFromParent_Done,
     /*  894446 */   // Label 14325: @894446
     /*  894446 */   GIM_Try, /*On fail goto*//*Label 14326*/ GIMT_Encode4(894507), // Rule ID 3364 //
     /*  894451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  894454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  894459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894468 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894475 */     // MIs[0] cbsz
     /*  894475 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894478 */     // MIs[0] abid
     /*  894478 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894481 */     // MIs[0] blgp
     /*  894481 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894484 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31722),
     /*  894488 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31722>>  =>  (V_MFMA_F32_16X16X4F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_e64),
     /*  894491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894493 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894495 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894497 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894499 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894501 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894503 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894505 */     GIR_RootConstrainSelectedInstOperands,
     /*  894506 */     // GIR_Coverage, 3364,
     /*  894506 */     GIR_EraseRootFromParent_Done,
     /*  894507 */   // Label 14326: @894507
     /*  894507 */   GIM_Try, /*On fail goto*//*Label 14327*/ GIMT_Encode4(894568), // Rule ID 3370 //
     /*  894512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  894515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  894520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  894523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894529 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  894532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  894536 */     // MIs[0] cbsz
     /*  894536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894539 */     // MIs[0] abid
     /*  894539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894542 */     // MIs[0] blgp
     /*  894542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894545 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31728),
     /*  894549 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31728>>  =>  (V_MFMA_F32_32X32X1F32_mac_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_e64),
     /*  894552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894554 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894556 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894558 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894560 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894562 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894564 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894566 */     GIR_RootConstrainSelectedInstOperands,
     /*  894567 */     // GIR_Coverage, 3370,
     /*  894567 */     GIR_EraseRootFromParent_Done,
     /*  894568 */   // Label 14327: @894568
     /*  894568 */   GIM_Try, /*On fail goto*//*Label 14328*/ GIMT_Encode4(894629), // Rule ID 3371 //
     /*  894573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  894576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  894581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  894584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  894593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  894597 */     // MIs[0] cbsz
     /*  894597 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894600 */     // MIs[0] abid
     /*  894600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894603 */     // MIs[0] blgp
     /*  894603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894606 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31728),
     /*  894610 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31728>>  =>  (V_MFMA_F32_32X32X1F32_mac_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_e64),
     /*  894613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894615 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894617 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894619 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894621 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894623 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894625 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894627 */     GIR_RootConstrainSelectedInstOperands,
     /*  894628 */     // GIR_Coverage, 3371,
     /*  894628 */     GIR_EraseRootFromParent_Done,
     /*  894629 */   // Label 14328: @894629
     /*  894629 */   GIM_Try, /*On fail goto*//*Label 14329*/ GIMT_Encode4(894690), // Rule ID 3377 //
     /*  894634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  894637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  894642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  894645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894651 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  894654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  894658 */     // MIs[0] cbsz
     /*  894658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894661 */     // MIs[0] abid
     /*  894661 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894664 */     // MIs[0] blgp
     /*  894664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894667 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31732),
     /*  894671 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31732>>  =>  (V_MFMA_F32_32X32X2F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_e64),
     /*  894674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894676 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894678 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894680 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894682 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894684 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894686 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894688 */     GIR_RootConstrainSelectedInstOperands,
     /*  894689 */     // GIR_Coverage, 3377,
     /*  894689 */     GIR_EraseRootFromParent_Done,
     /*  894690 */   // Label 14329: @894690
     /*  894690 */   GIM_Try, /*On fail goto*//*Label 14330*/ GIMT_Encode4(894751), // Rule ID 3378 //
     /*  894695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  894698 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  894703 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  894706 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  894709 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  894712 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  894715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  894719 */     // MIs[0] cbsz
     /*  894719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894722 */     // MIs[0] abid
     /*  894722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894725 */     // MIs[0] blgp
     /*  894725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894728 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31732),
     /*  894732 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31732>>  =>  (V_MFMA_F32_32X32X2F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_e64),
     /*  894735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894737 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894739 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894741 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894743 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894745 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894747 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894749 */     GIR_RootConstrainSelectedInstOperands,
     /*  894750 */     // GIR_Coverage, 3378,
     /*  894750 */     GIR_EraseRootFromParent_Done,
     /*  894751 */   // Label 14330: @894751
     /*  894751 */   GIM_Try, /*On fail goto*//*Label 14331*/ GIMT_Encode4(894812), // Rule ID 3384 //
     /*  894756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  894759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  894764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  894770 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  894773 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894780 */     // MIs[0] cbsz
     /*  894780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894783 */     // MIs[0] abid
     /*  894783 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894786 */     // MIs[0] blgp
     /*  894786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894789 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31736),
     /*  894793 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31736>>  =>  (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64),
     /*  894796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894798 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894800 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894802 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894804 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894806 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894808 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894810 */     GIR_RootConstrainSelectedInstOperands,
     /*  894811 */     // GIR_Coverage, 3384,
     /*  894811 */     GIR_EraseRootFromParent_Done,
     /*  894812 */   // Label 14331: @894812
     /*  894812 */   GIM_Try, /*On fail goto*//*Label 14332*/ GIMT_Encode4(894873), // Rule ID 3385 //
     /*  894817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode1),
     /*  894820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  894825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  894831 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  894834 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894841 */     // MIs[0] cbsz
     /*  894841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894844 */     // MIs[0] abid
     /*  894844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894847 */     // MIs[0] blgp
     /*  894847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894850 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31736),
     /*  894854 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31736>>  =>  (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64),
     /*  894857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894859 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894861 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894863 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894865 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894867 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894869 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894871 */     GIR_RootConstrainSelectedInstOperands,
     /*  894872 */     // GIR_Coverage, 3385,
     /*  894872 */     GIR_EraseRootFromParent_Done,
     /*  894873 */   // Label 14332: @894873
     /*  894873 */   GIM_Try, /*On fail goto*//*Label 14333*/ GIMT_Encode4(894934), // Rule ID 3386 //
     /*  894878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode2),
     /*  894881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  894886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  894892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  894895 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894902 */     // MIs[0] cbsz
     /*  894902 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894905 */     // MIs[0] abid
     /*  894905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894908 */     // MIs[0] blgp
     /*  894908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894911 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31736),
     /*  894915 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31736>>  =>  (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64),
     /*  894918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894920 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894922 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894924 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894926 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894928 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894930 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894932 */     GIR_RootConstrainSelectedInstOperands,
     /*  894933 */     // GIR_Coverage, 3386,
     /*  894933 */     GIR_EraseRootFromParent_Done,
     /*  894934 */   // Label 14333: @894934
     /*  894934 */   GIM_Try, /*On fail goto*//*Label 14334*/ GIMT_Encode4(894995), // Rule ID 3387 //
     /*  894939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode3),
     /*  894942 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  894947 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  894950 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  894953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  894956 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  894959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  894963 */     // MIs[0] cbsz
     /*  894963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  894966 */     // MIs[0] abid
     /*  894966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  894969 */     // MIs[0] blgp
     /*  894969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  894972 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31736),
     /*  894976 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31736>>  =>  (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  894976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64),
     /*  894979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  894981 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  894983 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  894985 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  894987 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  894989 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  894991 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  894993 */     GIR_RootConstrainSelectedInstOperands,
     /*  894994 */     // GIR_Coverage, 3387,
     /*  894994 */     GIR_EraseRootFromParent_Done,
     /*  894995 */   // Label 14334: @894995
     /*  894995 */   GIM_Try, /*On fail goto*//*Label 14335*/ GIMT_Encode4(895056), // Rule ID 3388 //
     /*  895000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode4),
     /*  895003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  895008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895011 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895014 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895017 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895024 */     // MIs[0] cbsz
     /*  895024 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895027 */     // MIs[0] abid
     /*  895027 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895030 */     // MIs[0] blgp
     /*  895030 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895033 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31736),
     /*  895037 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31736>>  =>  (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64),
     /*  895040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895042 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895044 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895046 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895048 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895050 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895052 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895054 */     GIR_RootConstrainSelectedInstOperands,
     /*  895055 */     // GIR_Coverage, 3388,
     /*  895055 */     GIR_EraseRootFromParent_Done,
     /*  895056 */   // Label 14335: @895056
     /*  895056 */   GIM_Try, /*On fail goto*//*Label 14336*/ GIMT_Encode4(895117), // Rule ID 3394 //
     /*  895061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  895064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  895069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  895075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  895078 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895085 */     // MIs[0] cbsz
     /*  895085 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895088 */     // MIs[0] abid
     /*  895088 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895091 */     // MIs[0] blgp
     /*  895091 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895094 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31740),
     /*  895098 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31740>>  =>  (V_MFMA_I32_4X4X4I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_e64),
     /*  895101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895103 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895105 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895107 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895109 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895111 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895113 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895115 */     GIR_RootConstrainSelectedInstOperands,
     /*  895116 */     // GIR_Coverage, 3394,
     /*  895116 */     GIR_EraseRootFromParent_Done,
     /*  895117 */   // Label 14336: @895117
     /*  895117 */   GIM_Try, /*On fail goto*//*Label 14337*/ GIMT_Encode4(895178), // Rule ID 3395 //
     /*  895122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  895125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  895130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  895136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  895139 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895146 */     // MIs[0] cbsz
     /*  895146 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895149 */     // MIs[0] abid
     /*  895149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895152 */     // MIs[0] blgp
     /*  895152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895155 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31740),
     /*  895159 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31740>>  =>  (V_MFMA_I32_4X4X4I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_e64),
     /*  895162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895164 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895166 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895168 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895170 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895172 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895174 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895176 */     GIR_RootConstrainSelectedInstOperands,
     /*  895177 */     // GIR_Coverage, 3395,
     /*  895177 */     GIR_EraseRootFromParent_Done,
     /*  895178 */   // Label 14337: @895178
     /*  895178 */   GIM_Try, /*On fail goto*//*Label 14338*/ GIMT_Encode4(895239), // Rule ID 3401 //
     /*  895183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  895186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  895191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895200 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895207 */     // MIs[0] cbsz
     /*  895207 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895210 */     // MIs[0] abid
     /*  895210 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895213 */     // MIs[0] blgp
     /*  895213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895216 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31746),
     /*  895220 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31746>>  =>  (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64),
     /*  895223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895225 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895227 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895229 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895231 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895233 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895235 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895237 */     GIR_RootConstrainSelectedInstOperands,
     /*  895238 */     // GIR_Coverage, 3401,
     /*  895238 */     GIR_EraseRootFromParent_Done,
     /*  895239 */   // Label 14338: @895239
     /*  895239 */   GIM_Try, /*On fail goto*//*Label 14339*/ GIMT_Encode4(895300), // Rule ID 3402 //
     /*  895244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode1),
     /*  895247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  895252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895261 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895268 */     // MIs[0] cbsz
     /*  895268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895271 */     // MIs[0] abid
     /*  895271 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895274 */     // MIs[0] blgp
     /*  895274 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895277 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31746),
     /*  895281 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31746>>  =>  (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64),
     /*  895284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895286 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895288 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895290 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895292 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895294 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895296 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895298 */     GIR_RootConstrainSelectedInstOperands,
     /*  895299 */     // GIR_Coverage, 3402,
     /*  895299 */     GIR_EraseRootFromParent_Done,
     /*  895300 */   // Label 14339: @895300
     /*  895300 */   GIM_Try, /*On fail goto*//*Label 14340*/ GIMT_Encode4(895361), // Rule ID 3403 //
     /*  895305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode2),
     /*  895308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  895313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895319 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895322 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895329 */     // MIs[0] cbsz
     /*  895329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895332 */     // MIs[0] abid
     /*  895332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895335 */     // MIs[0] blgp
     /*  895335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895338 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31746),
     /*  895342 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31746>>  =>  (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64),
     /*  895345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895347 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895349 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895351 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895353 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895355 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895357 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895359 */     GIR_RootConstrainSelectedInstOperands,
     /*  895360 */     // GIR_Coverage, 3403,
     /*  895360 */     GIR_EraseRootFromParent_Done,
     /*  895361 */   // Label 14340: @895361
     /*  895361 */   GIM_Try, /*On fail goto*//*Label 14341*/ GIMT_Encode4(895422), // Rule ID 3404 //
     /*  895366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode3),
     /*  895369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  895374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895390 */     // MIs[0] cbsz
     /*  895390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895393 */     // MIs[0] abid
     /*  895393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895396 */     // MIs[0] blgp
     /*  895396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895399 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31746),
     /*  895403 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31746>>  =>  (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64),
     /*  895406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895408 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895410 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895412 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895414 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895416 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895418 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895420 */     GIR_RootConstrainSelectedInstOperands,
     /*  895421 */     // GIR_Coverage, 3404,
     /*  895421 */     GIR_EraseRootFromParent_Done,
     /*  895422 */   // Label 14341: @895422
     /*  895422 */   GIM_Try, /*On fail goto*//*Label 14342*/ GIMT_Encode4(895483), // Rule ID 3405 //
     /*  895427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode4),
     /*  895430 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  895435 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895444 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895451 */     // MIs[0] cbsz
     /*  895451 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895454 */     // MIs[0] abid
     /*  895454 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895457 */     // MIs[0] blgp
     /*  895457 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895460 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31746),
     /*  895464 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31746>>  =>  (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64),
     /*  895467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895469 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895471 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895473 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895475 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895477 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895479 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895481 */     GIR_RootConstrainSelectedInstOperands,
     /*  895482 */     // GIR_Coverage, 3405,
     /*  895482 */     GIR_EraseRootFromParent_Done,
     /*  895483 */   // Label 14342: @895483
     /*  895483 */   GIM_Try, /*On fail goto*//*Label 14343*/ GIMT_Encode4(895544), // Rule ID 3411 //
     /*  895488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  895491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  895496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895499 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895505 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895512 */     // MIs[0] cbsz
     /*  895512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895515 */     // MIs[0] abid
     /*  895515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895518 */     // MIs[0] blgp
     /*  895518 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895521 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31750),
     /*  895525 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31750>>  =>  (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64),
     /*  895528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895530 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895532 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895534 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895536 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895538 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895540 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895542 */     GIR_RootConstrainSelectedInstOperands,
     /*  895543 */     // GIR_Coverage, 3411,
     /*  895543 */     GIR_EraseRootFromParent_Done,
     /*  895544 */   // Label 14343: @895544
     /*  895544 */   GIM_Try, /*On fail goto*//*Label 14344*/ GIMT_Encode4(895605), // Rule ID 3412 //
     /*  895549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode1),
     /*  895552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  895557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895566 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895573 */     // MIs[0] cbsz
     /*  895573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895576 */     // MIs[0] abid
     /*  895576 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895579 */     // MIs[0] blgp
     /*  895579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895582 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31750),
     /*  895586 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31750>>  =>  (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64),
     /*  895589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895591 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895593 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895595 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895597 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895599 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895601 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895603 */     GIR_RootConstrainSelectedInstOperands,
     /*  895604 */     // GIR_Coverage, 3412,
     /*  895604 */     GIR_EraseRootFromParent_Done,
     /*  895605 */   // Label 14344: @895605
     /*  895605 */   GIM_Try, /*On fail goto*//*Label 14345*/ GIMT_Encode4(895666), // Rule ID 3413 //
     /*  895610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode2),
     /*  895613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  895618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895634 */     // MIs[0] cbsz
     /*  895634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895637 */     // MIs[0] abid
     /*  895637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895640 */     // MIs[0] blgp
     /*  895640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895643 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31750),
     /*  895647 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31750>>  =>  (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64),
     /*  895650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895652 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895654 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895656 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895658 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895660 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895662 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895664 */     GIR_RootConstrainSelectedInstOperands,
     /*  895665 */     // GIR_Coverage, 3413,
     /*  895665 */     GIR_EraseRootFromParent_Done,
     /*  895666 */   // Label 14345: @895666
     /*  895666 */   GIM_Try, /*On fail goto*//*Label 14346*/ GIMT_Encode4(895727), // Rule ID 3414 //
     /*  895671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode3),
     /*  895674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  895679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895688 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895695 */     // MIs[0] cbsz
     /*  895695 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895698 */     // MIs[0] abid
     /*  895698 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895701 */     // MIs[0] blgp
     /*  895701 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895704 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31750),
     /*  895708 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31750>>  =>  (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64),
     /*  895711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895713 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895715 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895717 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895719 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895721 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895723 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895725 */     GIR_RootConstrainSelectedInstOperands,
     /*  895726 */     // GIR_Coverage, 3414,
     /*  895726 */     GIR_EraseRootFromParent_Done,
     /*  895727 */   // Label 14346: @895727
     /*  895727 */   GIM_Try, /*On fail goto*//*Label 14347*/ GIMT_Encode4(895788), // Rule ID 3415 //
     /*  895732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode4),
     /*  895735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  895740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  895743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895749 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  895752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  895756 */     // MIs[0] cbsz
     /*  895756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895759 */     // MIs[0] abid
     /*  895759 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895762 */     // MIs[0] blgp
     /*  895762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895765 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31750),
     /*  895769 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31750>>  =>  (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64),
     /*  895772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895774 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895776 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895778 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895780 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895782 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895784 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895786 */     GIR_RootConstrainSelectedInstOperands,
     /*  895787 */     // GIR_Coverage, 3415,
     /*  895787 */     GIR_EraseRootFromParent_Done,
     /*  895788 */   // Label 14347: @895788
     /*  895788 */   GIM_Try, /*On fail goto*//*Label 14348*/ GIMT_Encode4(895849), // Rule ID 3421 //
     /*  895793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  895796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  895801 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895804 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  895807 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  895810 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895817 */     // MIs[0] cbsz
     /*  895817 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895820 */     // MIs[0] abid
     /*  895820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895823 */     // MIs[0] blgp
     /*  895823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895826 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31756),
     /*  895830 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31756>>  =>  (V_MFMA_I32_16X16X4I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_e64),
     /*  895833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895835 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895837 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895839 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895841 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895843 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895845 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895847 */     GIR_RootConstrainSelectedInstOperands,
     /*  895848 */     // GIR_Coverage, 3421,
     /*  895848 */     GIR_EraseRootFromParent_Done,
     /*  895849 */   // Label 14348: @895849
     /*  895849 */   GIM_Try, /*On fail goto*//*Label 14349*/ GIMT_Encode4(895910), // Rule ID 3422 //
     /*  895854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  895857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  895862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  895865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  895868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  895871 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  895874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  895878 */     // MIs[0] cbsz
     /*  895878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895881 */     // MIs[0] abid
     /*  895881 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895884 */     // MIs[0] blgp
     /*  895884 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895887 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31756),
     /*  895891 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31756>>  =>  (V_MFMA_I32_16X16X4I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_e64),
     /*  895894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895896 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895898 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895900 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895902 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895904 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895906 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895908 */     GIR_RootConstrainSelectedInstOperands,
     /*  895909 */     // GIR_Coverage, 3422,
     /*  895909 */     GIR_EraseRootFromParent_Done,
     /*  895910 */   // Label 14349: @895910
     /*  895910 */   GIM_Try, /*On fail goto*//*Label 14350*/ GIMT_Encode4(895971), // Rule ID 3428 //
     /*  895915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  895918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  895923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  895926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895932 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  895935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  895939 */     // MIs[0] cbsz
     /*  895939 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  895942 */     // MIs[0] abid
     /*  895942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  895945 */     // MIs[0] blgp
     /*  895945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  895948 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31762),
     /*  895952 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31762>>  =>  (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  895952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64),
     /*  895955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  895957 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  895959 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  895961 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  895963 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  895965 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  895967 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  895969 */     GIR_RootConstrainSelectedInstOperands,
     /*  895970 */     // GIR_Coverage, 3428,
     /*  895970 */     GIR_EraseRootFromParent_Done,
     /*  895971 */   // Label 14350: @895971
     /*  895971 */   GIM_Try, /*On fail goto*//*Label 14351*/ GIMT_Encode4(896032), // Rule ID 3429 //
     /*  895976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode1),
     /*  895979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  895984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  895987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  895990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  895993 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  895996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  896000 */     // MIs[0] cbsz
     /*  896000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896003 */     // MIs[0] abid
     /*  896003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896006 */     // MIs[0] blgp
     /*  896006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896009 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31762),
     /*  896013 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31762>>  =>  (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64),
     /*  896016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896018 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896020 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896022 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896024 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896026 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896028 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896030 */     GIR_RootConstrainSelectedInstOperands,
     /*  896031 */     // GIR_Coverage, 3429,
     /*  896031 */     GIR_EraseRootFromParent_Done,
     /*  896032 */   // Label 14351: @896032
     /*  896032 */   GIM_Try, /*On fail goto*//*Label 14352*/ GIMT_Encode4(896093), // Rule ID 3430 //
     /*  896037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode2),
     /*  896040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  896045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  896048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896054 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  896057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  896061 */     // MIs[0] cbsz
     /*  896061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896064 */     // MIs[0] abid
     /*  896064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896067 */     // MIs[0] blgp
     /*  896067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896070 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31762),
     /*  896074 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31762>>  =>  (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64),
     /*  896077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896079 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896081 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896083 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896085 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896087 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896089 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896091 */     GIR_RootConstrainSelectedInstOperands,
     /*  896092 */     // GIR_Coverage, 3430,
     /*  896092 */     GIR_EraseRootFromParent_Done,
     /*  896093 */   // Label 14352: @896093
     /*  896093 */   GIM_Try, /*On fail goto*//*Label 14353*/ GIMT_Encode4(896154), // Rule ID 3431 //
     /*  896098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode3),
     /*  896101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  896106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  896109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896115 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  896118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  896122 */     // MIs[0] cbsz
     /*  896122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896125 */     // MIs[0] abid
     /*  896125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896128 */     // MIs[0] blgp
     /*  896128 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896131 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31762),
     /*  896135 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31762>>  =>  (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64),
     /*  896138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896140 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896142 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896144 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896146 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896148 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896150 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896152 */     GIR_RootConstrainSelectedInstOperands,
     /*  896153 */     // GIR_Coverage, 3431,
     /*  896153 */     GIR_EraseRootFromParent_Done,
     /*  896154 */   // Label 14353: @896154
     /*  896154 */   GIM_Try, /*On fail goto*//*Label 14354*/ GIMT_Encode4(896215), // Rule ID 3432 //
     /*  896159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode4),
     /*  896162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  896167 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  896170 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896173 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896176 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  896179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  896183 */     // MIs[0] cbsz
     /*  896183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896186 */     // MIs[0] abid
     /*  896186 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896189 */     // MIs[0] blgp
     /*  896189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896192 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31762),
     /*  896196 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31762>>  =>  (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64),
     /*  896199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896201 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896203 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896205 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896207 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896209 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896211 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896213 */     GIR_RootConstrainSelectedInstOperands,
     /*  896214 */     // GIR_Coverage, 3432,
     /*  896214 */     GIR_EraseRootFromParent_Done,
     /*  896215 */   // Label 14354: @896215
     /*  896215 */   GIM_Try, /*On fail goto*//*Label 14355*/ GIMT_Encode4(896276), // Rule ID 3438 //
     /*  896220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  896223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  896228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896231 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896234 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896237 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896244 */     // MIs[0] cbsz
     /*  896244 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896247 */     // MIs[0] abid
     /*  896247 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896250 */     // MIs[0] blgp
     /*  896250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896253 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31766),
     /*  896257 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31766>>  =>  (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64),
     /*  896260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896262 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896264 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896266 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896268 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896270 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896272 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896274 */     GIR_RootConstrainSelectedInstOperands,
     /*  896275 */     // GIR_Coverage, 3438,
     /*  896275 */     GIR_EraseRootFromParent_Done,
     /*  896276 */   // Label 14355: @896276
     /*  896276 */   GIM_Try, /*On fail goto*//*Label 14356*/ GIMT_Encode4(896337), // Rule ID 3439 //
     /*  896281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode1),
     /*  896284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  896289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896298 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896305 */     // MIs[0] cbsz
     /*  896305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896308 */     // MIs[0] abid
     /*  896308 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896311 */     // MIs[0] blgp
     /*  896311 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896314 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31766),
     /*  896318 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31766>>  =>  (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64),
     /*  896321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896323 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896325 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896327 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896329 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896331 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896333 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896335 */     GIR_RootConstrainSelectedInstOperands,
     /*  896336 */     // GIR_Coverage, 3439,
     /*  896336 */     GIR_EraseRootFromParent_Done,
     /*  896337 */   // Label 14356: @896337
     /*  896337 */   GIM_Try, /*On fail goto*//*Label 14357*/ GIMT_Encode4(896398), // Rule ID 3440 //
     /*  896342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode2),
     /*  896345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  896350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896359 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896366 */     // MIs[0] cbsz
     /*  896366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896369 */     // MIs[0] abid
     /*  896369 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896372 */     // MIs[0] blgp
     /*  896372 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896375 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31766),
     /*  896379 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31766>>  =>  (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64),
     /*  896382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896384 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896386 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896388 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896390 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896392 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896394 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896396 */     GIR_RootConstrainSelectedInstOperands,
     /*  896397 */     // GIR_Coverage, 3440,
     /*  896397 */     GIR_EraseRootFromParent_Done,
     /*  896398 */   // Label 14357: @896398
     /*  896398 */   GIM_Try, /*On fail goto*//*Label 14358*/ GIMT_Encode4(896459), // Rule ID 3441 //
     /*  896403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode3),
     /*  896406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  896411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896420 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896427 */     // MIs[0] cbsz
     /*  896427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896430 */     // MIs[0] abid
     /*  896430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896433 */     // MIs[0] blgp
     /*  896433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896436 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31766),
     /*  896440 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31766>>  =>  (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64),
     /*  896443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896445 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896447 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896449 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896451 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896453 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896455 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896457 */     GIR_RootConstrainSelectedInstOperands,
     /*  896458 */     // GIR_Coverage, 3441,
     /*  896458 */     GIR_EraseRootFromParent_Done,
     /*  896459 */   // Label 14358: @896459
     /*  896459 */   GIM_Try, /*On fail goto*//*Label 14359*/ GIMT_Encode4(896520), // Rule ID 3442 //
     /*  896464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode4),
     /*  896467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  896472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  896478 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  896481 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896488 */     // MIs[0] cbsz
     /*  896488 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896491 */     // MIs[0] abid
     /*  896491 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896494 */     // MIs[0] blgp
     /*  896494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896497 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31766),
     /*  896501 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31766>>  =>  (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64),
     /*  896504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896506 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896508 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896510 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896512 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896514 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896516 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896518 */     GIR_RootConstrainSelectedInstOperands,
     /*  896519 */     // GIR_Coverage, 3442,
     /*  896519 */     GIR_EraseRootFromParent_Done,
     /*  896520 */   // Label 14359: @896520
     /*  896520 */   GIM_Try, /*On fail goto*//*Label 14360*/ GIMT_Encode4(896581), // Rule ID 3448 //
     /*  896525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode0),
     /*  896528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  896533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  896536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  896539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  896542 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  896545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  896549 */     // MIs[0] cbsz
     /*  896549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896552 */     // MIs[0] abid
     /*  896552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896555 */     // MIs[0] blgp
     /*  896555 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896558 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31772),
     /*  896562 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31772>>  =>  (V_MFMA_I32_32X32X4I8_mac_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_e64),
     /*  896565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896567 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896569 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896571 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896573 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896575 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896577 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896579 */     GIR_RootConstrainSelectedInstOperands,
     /*  896580 */     // GIR_Coverage, 3448,
     /*  896580 */     GIR_EraseRootFromParent_Done,
     /*  896581 */   // Label 14360: @896581
     /*  896581 */   GIM_Try, /*On fail goto*//*Label 14361*/ GIMT_Encode4(896642), // Rule ID 3449 //
     /*  896586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_HwMode5),
     /*  896589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  896594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  896597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  896600 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  896603 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  896606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  896610 */     // MIs[0] cbsz
     /*  896610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896613 */     // MIs[0] abid
     /*  896613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896616 */     // MIs[0] blgp
     /*  896616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896619 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31772),
     /*  896623 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31772>>  =>  (V_MFMA_I32_32X32X4I8_mac_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_e64),
     /*  896626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896628 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896630 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896632 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896634 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896636 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896638 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896640 */     GIR_RootConstrainSelectedInstOperands,
     /*  896641 */     // GIR_Coverage, 3449,
     /*  896641 */     GIR_EraseRootFromParent_Done,
     /*  896642 */   // Label 14361: @896642
     /*  896642 */   GIM_Try, /*On fail goto*//*Label 14362*/ GIMT_Encode4(896703), // Rule ID 3455 //
     /*  896647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  896650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  896655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  896658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  896661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  896664 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  896667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  896671 */     // MIs[0] cbsz
     /*  896671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896674 */     // MIs[0] abid
     /*  896674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896677 */     // MIs[0] blgp
     /*  896677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896680 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31776),
     /*  896684 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31776>>  =>  (V_MFMA_I32_16X16X16I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_e64),
     /*  896687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896689 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896691 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896693 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896695 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896697 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896699 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896701 */     GIR_RootConstrainSelectedInstOperands,
     /*  896702 */     // GIR_Coverage, 3455,
     /*  896702 */     GIR_EraseRootFromParent_Done,
     /*  896703 */   // Label 14362: @896703
     /*  896703 */   GIM_Try, /*On fail goto*//*Label 14363*/ GIMT_Encode4(896764), // Rule ID 3456 //
     /*  896708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  896711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  896716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  896719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  896722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  896725 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  896728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  896732 */     // MIs[0] cbsz
     /*  896732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896735 */     // MIs[0] abid
     /*  896735 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896738 */     // MIs[0] blgp
     /*  896738 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896741 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31776),
     /*  896745 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31776>>  =>  (V_MFMA_I32_16X16X16I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_e64),
     /*  896748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896750 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896752 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896754 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896756 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896758 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896760 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896762 */     GIR_RootConstrainSelectedInstOperands,
     /*  896763 */     // GIR_Coverage, 3456,
     /*  896763 */     GIR_EraseRootFromParent_Done,
     /*  896764 */   // Label 14363: @896764
     /*  896764 */   GIM_Try, /*On fail goto*//*Label 14364*/ GIMT_Encode4(896825), // Rule ID 3462 //
     /*  896769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  896772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  896777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  896783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  896786 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896793 */     // MIs[0] cbsz
     /*  896793 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896796 */     // MIs[0] abid
     /*  896796 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896799 */     // MIs[0] blgp
     /*  896799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896802 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31780),
     /*  896806 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31780>>  =>  (V_MFMA_I32_32X32X8I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_e64),
     /*  896809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896811 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896813 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896815 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896817 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896819 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896821 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896823 */     GIR_RootConstrainSelectedInstOperands,
     /*  896824 */     // GIR_Coverage, 3462,
     /*  896824 */     GIR_EraseRootFromParent_Done,
     /*  896825 */   // Label 14364: @896825
     /*  896825 */   GIM_Try, /*On fail goto*//*Label 14365*/ GIMT_Encode4(896886), // Rule ID 3463 //
     /*  896830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  896833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  896838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  896841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  896844 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  896847 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  896850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  896854 */     // MIs[0] cbsz
     /*  896854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896857 */     // MIs[0] abid
     /*  896857 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896860 */     // MIs[0] blgp
     /*  896860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896863 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31780),
     /*  896867 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31780>>  =>  (V_MFMA_I32_32X32X8I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_e64),
     /*  896870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896872 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896874 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896876 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896878 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896880 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896882 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896884 */     GIR_RootConstrainSelectedInstOperands,
     /*  896885 */     // GIR_Coverage, 3463,
     /*  896885 */     GIR_EraseRootFromParent_Done,
     /*  896886 */   // Label 14365: @896886
     /*  896886 */   GIM_Try, /*On fail goto*//*Label 14366*/ GIMT_Encode4(896947), // Rule ID 3469 //
     /*  896891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  896894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  896899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  896902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  896905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  896908 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  896911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  896915 */     // MIs[0] cbsz
     /*  896915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896918 */     // MIs[0] abid
     /*  896918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896921 */     // MIs[0] blgp
     /*  896921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31784),
     /*  896928 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31784>>  =>  (V_MFMA_F32_4X4X2BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_e64),
     /*  896931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896933 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896937 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  896939 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  896941 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  896943 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  896945 */     GIR_RootConstrainSelectedInstOperands,
     /*  896946 */     // GIR_Coverage, 3469,
     /*  896946 */     GIR_EraseRootFromParent_Done,
     /*  896947 */   // Label 14366: @896947
     /*  896947 */   GIM_Try, /*On fail goto*//*Label 14367*/ GIMT_Encode4(897008), // Rule ID 3470 //
     /*  896952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  896955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  896960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  896963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  896966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  896969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  896972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  896976 */     // MIs[0] cbsz
     /*  896976 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  896979 */     // MIs[0] abid
     /*  896979 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  896982 */     // MIs[0] blgp
     /*  896982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  896985 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31784),
     /*  896989 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31784>>  =>  (V_MFMA_F32_4X4X2BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  896989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_e64),
     /*  896992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  896994 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  896996 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  896998 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897000 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897002 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897004 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897006 */     GIR_RootConstrainSelectedInstOperands,
     /*  897007 */     // GIR_Coverage, 3470,
     /*  897007 */     GIR_EraseRootFromParent_Done,
     /*  897008 */   // Label 14367: @897008
     /*  897008 */   GIM_Try, /*On fail goto*//*Label 14368*/ GIMT_Encode4(897069), // Rule ID 3476 //
     /*  897013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  897016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  897021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897030 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897037 */     // MIs[0] cbsz
     /*  897037 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897040 */     // MIs[0] abid
     /*  897040 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897043 */     // MIs[0] blgp
     /*  897043 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897046 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31790),
     /*  897050 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31790>>  =>  (V_MFMA_F32_16X16X2BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_e64),
     /*  897053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897055 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897057 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897059 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897061 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897063 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897065 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897067 */     GIR_RootConstrainSelectedInstOperands,
     /*  897068 */     // GIR_Coverage, 3476,
     /*  897068 */     GIR_EraseRootFromParent_Done,
     /*  897069 */   // Label 14368: @897069
     /*  897069 */   GIM_Try, /*On fail goto*//*Label 14369*/ GIMT_Encode4(897130), // Rule ID 3477 //
     /*  897074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  897077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  897082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897091 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897098 */     // MIs[0] cbsz
     /*  897098 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897101 */     // MIs[0] abid
     /*  897101 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897104 */     // MIs[0] blgp
     /*  897104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897107 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31790),
     /*  897111 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31790>>  =>  (V_MFMA_F32_16X16X2BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_e64),
     /*  897114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897116 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897118 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897120 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897122 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897124 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897126 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897128 */     GIR_RootConstrainSelectedInstOperands,
     /*  897129 */     // GIR_Coverage, 3477,
     /*  897129 */     GIR_EraseRootFromParent_Done,
     /*  897130 */   // Label 14369: @897130
     /*  897130 */   GIM_Try, /*On fail goto*//*Label 14370*/ GIMT_Encode4(897191), // Rule ID 3483 //
     /*  897135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  897138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  897143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897159 */     // MIs[0] cbsz
     /*  897159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897162 */     // MIs[0] abid
     /*  897162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897165 */     // MIs[0] blgp
     /*  897165 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897168 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31794),
     /*  897172 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31794>>  =>  (V_MFMA_F32_16X16X8BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_e64),
     /*  897175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897177 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897179 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897181 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897183 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897185 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897187 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897189 */     GIR_RootConstrainSelectedInstOperands,
     /*  897190 */     // GIR_Coverage, 3483,
     /*  897190 */     GIR_EraseRootFromParent_Done,
     /*  897191 */   // Label 14370: @897191
     /*  897191 */   GIM_Try, /*On fail goto*//*Label 14371*/ GIMT_Encode4(897252), // Rule ID 3484 //
     /*  897196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  897199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  897204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897220 */     // MIs[0] cbsz
     /*  897220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897223 */     // MIs[0] abid
     /*  897223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897226 */     // MIs[0] blgp
     /*  897226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897229 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31794),
     /*  897233 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31794>>  =>  (V_MFMA_F32_16X16X8BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_e64),
     /*  897236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897238 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897240 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897242 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897244 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897246 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897248 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897250 */     GIR_RootConstrainSelectedInstOperands,
     /*  897251 */     // GIR_Coverage, 3484,
     /*  897251 */     GIR_EraseRootFromParent_Done,
     /*  897252 */   // Label 14371: @897252
     /*  897252 */   GIM_Try, /*On fail goto*//*Label 14372*/ GIMT_Encode4(897313), // Rule ID 3490 //
     /*  897257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  897260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  897265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  897268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897274 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  897277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  897281 */     // MIs[0] cbsz
     /*  897281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897284 */     // MIs[0] abid
     /*  897284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897287 */     // MIs[0] blgp
     /*  897287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897290 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31800),
     /*  897294 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31800>>  =>  (V_MFMA_F32_32X32X2BF16_mac_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_e64),
     /*  897297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897299 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897301 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897303 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897305 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897307 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897309 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897311 */     GIR_RootConstrainSelectedInstOperands,
     /*  897312 */     // GIR_Coverage, 3490,
     /*  897312 */     GIR_EraseRootFromParent_Done,
     /*  897313 */   // Label 14372: @897313
     /*  897313 */   GIM_Try, /*On fail goto*//*Label 14373*/ GIMT_Encode4(897374), // Rule ID 3491 //
     /*  897318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  897321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  897326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  897329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897335 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  897338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  897342 */     // MIs[0] cbsz
     /*  897342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897345 */     // MIs[0] abid
     /*  897345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897348 */     // MIs[0] blgp
     /*  897348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897351 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31800),
     /*  897355 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31800>>  =>  (V_MFMA_F32_32X32X2BF16_mac_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_e64),
     /*  897358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897360 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897362 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897364 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897366 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897368 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897370 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897372 */     GIR_RootConstrainSelectedInstOperands,
     /*  897373 */     // GIR_Coverage, 3491,
     /*  897373 */     GIR_EraseRootFromParent_Done,
     /*  897374 */   // Label 14373: @897374
     /*  897374 */   GIM_Try, /*On fail goto*//*Label 14374*/ GIMT_Encode4(897435), // Rule ID 3497 //
     /*  897379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode0),
     /*  897382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  897387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897396 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897403 */     // MIs[0] cbsz
     /*  897403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897406 */     // MIs[0] abid
     /*  897406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897409 */     // MIs[0] blgp
     /*  897409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897412 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31804),
     /*  897416 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31804>>  =>  (V_MFMA_F32_32X32X4BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_e64),
     /*  897419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897421 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897423 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897425 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897427 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897429 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897431 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897433 */     GIR_RootConstrainSelectedInstOperands,
     /*  897434 */     // GIR_Coverage, 3497,
     /*  897434 */     GIR_EraseRootFromParent_Done,
     /*  897435 */   // Label 14374: @897435
     /*  897435 */   GIM_Try, /*On fail goto*//*Label 14375*/ GIMT_Encode4(897496), // Rule ID 3498 //
     /*  897440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A_HwMode5),
     /*  897443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  897448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  897454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  897457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897464 */     // MIs[0] cbsz
     /*  897464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897467 */     // MIs[0] abid
     /*  897467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897470 */     // MIs[0] blgp
     /*  897470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897473 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31804),
     /*  897477 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31804>>  =>  (V_MFMA_F32_32X32X4BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_e64),
     /*  897480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897482 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897484 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897486 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897488 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897490 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897492 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897494 */     GIR_RootConstrainSelectedInstOperands,
     /*  897495 */     // GIR_Coverage, 3498,
     /*  897495 */     GIR_EraseRootFromParent_Done,
     /*  897496 */   // Label 14375: @897496
     /*  897496 */   GIM_Try, /*On fail goto*//*Label 14376*/ GIMT_Encode4(897557), // Rule ID 3504 //
     /*  897501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  897504 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  897509 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897512 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897515 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897518 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897525 */     // MIs[0] cbsz
     /*  897525 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897528 */     // MIs[0] abid
     /*  897528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897531 */     // MIs[0] blgp
     /*  897531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897534 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31808),
     /*  897538 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31808>>  =>  (V_MFMA_F32_16X16X32_F16_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_e64),
     /*  897541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897543 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897545 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897547 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897549 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897551 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897553 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897555 */     GIR_RootConstrainSelectedInstOperands,
     /*  897556 */     // GIR_Coverage, 3504,
     /*  897556 */     GIR_EraseRootFromParent_Done,
     /*  897557 */   // Label 14376: @897557
     /*  897557 */   GIM_Try, /*On fail goto*//*Label 14377*/ GIMT_Encode4(897618), // Rule ID 3505 //
     /*  897562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  897565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  897570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897586 */     // MIs[0] cbsz
     /*  897586 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897589 */     // MIs[0] abid
     /*  897589 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897592 */     // MIs[0] blgp
     /*  897592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897595 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31808),
     /*  897599 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31808>>  =>  (V_MFMA_F32_16X16X32_F16_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_e64),
     /*  897602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897604 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897606 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897608 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897610 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897612 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897614 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897616 */     GIR_RootConstrainSelectedInstOperands,
     /*  897617 */     // GIR_Coverage, 3505,
     /*  897617 */     GIR_EraseRootFromParent_Done,
     /*  897618 */   // Label 14377: @897618
     /*  897618 */   GIM_Try, /*On fail goto*//*Label 14378*/ GIMT_Encode4(897679), // Rule ID 3506 //
     /*  897623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  897626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  897631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897640 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897647 */     // MIs[0] cbsz
     /*  897647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897650 */     // MIs[0] abid
     /*  897650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897653 */     // MIs[0] blgp
     /*  897653 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897656 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31808),
     /*  897660 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31808>>  =>  (V_MFMA_F32_16X16X32_F16_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_e64),
     /*  897663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897665 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897667 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897669 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897671 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897673 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897675 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897677 */     GIR_RootConstrainSelectedInstOperands,
     /*  897678 */     // GIR_Coverage, 3506,
     /*  897678 */     GIR_EraseRootFromParent_Done,
     /*  897679 */   // Label 14378: @897679
     /*  897679 */   GIM_Try, /*On fail goto*//*Label 14379*/ GIMT_Encode4(897740), // Rule ID 3507 //
     /*  897684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  897687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  897692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897701 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897708 */     // MIs[0] cbsz
     /*  897708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897711 */     // MIs[0] abid
     /*  897711 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897714 */     // MIs[0] blgp
     /*  897714 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897717 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31808),
     /*  897721 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31808>>  =>  (V_MFMA_F32_16X16X32_F16_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_e64),
     /*  897724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897726 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897728 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897730 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897732 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897734 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897736 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897738 */     GIR_RootConstrainSelectedInstOperands,
     /*  897739 */     // GIR_Coverage, 3507,
     /*  897739 */     GIR_EraseRootFromParent_Done,
     /*  897740 */   // Label 14379: @897740
     /*  897740 */   GIM_Try, /*On fail goto*//*Label 14380*/ GIMT_Encode4(897801), // Rule ID 3508 //
     /*  897745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  897748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  897753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  897756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897762 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  897765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  897769 */     // MIs[0] cbsz
     /*  897769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897772 */     // MIs[0] abid
     /*  897772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897775 */     // MIs[0] blgp
     /*  897775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897778 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31808),
     /*  897782 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31808>>  =>  (V_MFMA_F32_16X16X32_F16_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_e64),
     /*  897785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897787 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897789 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897791 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897793 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897795 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897797 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897799 */     GIR_RootConstrainSelectedInstOperands,
     /*  897800 */     // GIR_Coverage, 3508,
     /*  897800 */     GIR_EraseRootFromParent_Done,
     /*  897801 */   // Label 14380: @897801
     /*  897801 */   GIM_Try, /*On fail goto*//*Label 14381*/ GIMT_Encode4(897862), // Rule ID 3514 //
     /*  897806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  897809 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  897814 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897817 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897820 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897823 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897830 */     // MIs[0] cbsz
     /*  897830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897833 */     // MIs[0] abid
     /*  897833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897836 */     // MIs[0] blgp
     /*  897836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897839 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31814),
     /*  897843 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31814>>  =>  (V_MFMA_F32_32X32X16_F16_mac_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_e64),
     /*  897846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897848 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897850 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897852 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897854 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897856 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897858 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897860 */     GIR_RootConstrainSelectedInstOperands,
     /*  897861 */     // GIR_Coverage, 3514,
     /*  897861 */     GIR_EraseRootFromParent_Done,
     /*  897862 */   // Label 14381: @897862
     /*  897862 */   GIM_Try, /*On fail goto*//*Label 14382*/ GIMT_Encode4(897923), // Rule ID 3515 //
     /*  897867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  897870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  897875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897881 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897884 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897891 */     // MIs[0] cbsz
     /*  897891 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897894 */     // MIs[0] abid
     /*  897894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897897 */     // MIs[0] blgp
     /*  897897 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897900 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31814),
     /*  897904 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31814>>  =>  (V_MFMA_F32_32X32X16_F16_mac_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_e64),
     /*  897907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897909 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897911 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897913 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897915 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897917 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897919 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897921 */     GIR_RootConstrainSelectedInstOperands,
     /*  897922 */     // GIR_Coverage, 3515,
     /*  897922 */     GIR_EraseRootFromParent_Done,
     /*  897923 */   // Label 14382: @897923
     /*  897923 */   GIM_Try, /*On fail goto*//*Label 14383*/ GIMT_Encode4(897984), // Rule ID 3516 //
     /*  897928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  897931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  897936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  897939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  897942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  897945 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  897948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  897952 */     // MIs[0] cbsz
     /*  897952 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  897955 */     // MIs[0] abid
     /*  897955 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  897958 */     // MIs[0] blgp
     /*  897958 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  897961 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31814),
     /*  897965 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31814>>  =>  (V_MFMA_F32_32X32X16_F16_mac_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  897965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_e64),
     /*  897968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  897970 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  897972 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  897974 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  897976 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  897978 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  897980 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  897982 */     GIR_RootConstrainSelectedInstOperands,
     /*  897983 */     // GIR_Coverage, 3516,
     /*  897983 */     GIR_EraseRootFromParent_Done,
     /*  897984 */   // Label 14383: @897984
     /*  897984 */   GIM_Try, /*On fail goto*//*Label 14384*/ GIMT_Encode4(898045), // Rule ID 3517 //
     /*  897989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  897992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  897997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  898003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  898006 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898013 */     // MIs[0] cbsz
     /*  898013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898016 */     // MIs[0] abid
     /*  898016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898019 */     // MIs[0] blgp
     /*  898019 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898022 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31814),
     /*  898026 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31814>>  =>  (V_MFMA_F32_32X32X16_F16_mac_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_e64),
     /*  898029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898031 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898033 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898035 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898037 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898039 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898041 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898043 */     GIR_RootConstrainSelectedInstOperands,
     /*  898044 */     // GIR_Coverage, 3517,
     /*  898044 */     GIR_EraseRootFromParent_Done,
     /*  898045 */   // Label 14384: @898045
     /*  898045 */   GIM_Try, /*On fail goto*//*Label 14385*/ GIMT_Encode4(898106), // Rule ID 3518 //
     /*  898050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  898053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  898058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  898064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  898067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898074 */     // MIs[0] cbsz
     /*  898074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898077 */     // MIs[0] abid
     /*  898077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898080 */     // MIs[0] blgp
     /*  898080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898083 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31814),
     /*  898087 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31814>>  =>  (V_MFMA_F32_32X32X16_F16_mac_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_e64),
     /*  898090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898092 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898094 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898096 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898098 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898100 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898102 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898104 */     GIR_RootConstrainSelectedInstOperands,
     /*  898105 */     // GIR_Coverage, 3518,
     /*  898105 */     GIR_EraseRootFromParent_Done,
     /*  898106 */   // Label 14385: @898106
     /*  898106 */   GIM_Try, /*On fail goto*//*Label 14386*/ GIMT_Encode4(898167), // Rule ID 3524 //
     /*  898111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  898114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  898119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  898122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898125 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898128 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  898131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  898135 */     // MIs[0] cbsz
     /*  898135 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898138 */     // MIs[0] abid
     /*  898138 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898141 */     // MIs[0] blgp
     /*  898141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898144 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31822),
     /*  898148 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31822>>  =>  (V_MFMA_I32_16X16X64_I8_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_e64),
     /*  898151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898153 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898155 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898157 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898159 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898161 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898163 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898165 */     GIR_RootConstrainSelectedInstOperands,
     /*  898166 */     // GIR_Coverage, 3524,
     /*  898166 */     GIR_EraseRootFromParent_Done,
     /*  898167 */   // Label 14386: @898167
     /*  898167 */   GIM_Try, /*On fail goto*//*Label 14387*/ GIMT_Encode4(898228), // Rule ID 3525 //
     /*  898172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  898175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  898180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  898183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898189 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  898192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  898196 */     // MIs[0] cbsz
     /*  898196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898199 */     // MIs[0] abid
     /*  898199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898202 */     // MIs[0] blgp
     /*  898202 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898205 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31822),
     /*  898209 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31822>>  =>  (V_MFMA_I32_16X16X64_I8_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_e64),
     /*  898212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898214 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898216 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898218 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898220 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898222 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898224 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898226 */     GIR_RootConstrainSelectedInstOperands,
     /*  898227 */     // GIR_Coverage, 3525,
     /*  898227 */     GIR_EraseRootFromParent_Done,
     /*  898228 */   // Label 14387: @898228
     /*  898228 */   GIM_Try, /*On fail goto*//*Label 14388*/ GIMT_Encode4(898289), // Rule ID 3526 //
     /*  898233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  898236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  898241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  898244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898250 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  898253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  898257 */     // MIs[0] cbsz
     /*  898257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898260 */     // MIs[0] abid
     /*  898260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898263 */     // MIs[0] blgp
     /*  898263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898266 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31822),
     /*  898270 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31822>>  =>  (V_MFMA_I32_16X16X64_I8_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_e64),
     /*  898273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898275 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898277 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898279 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898281 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898283 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898285 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898287 */     GIR_RootConstrainSelectedInstOperands,
     /*  898288 */     // GIR_Coverage, 3526,
     /*  898288 */     GIR_EraseRootFromParent_Done,
     /*  898289 */   // Label 14388: @898289
     /*  898289 */   GIM_Try, /*On fail goto*//*Label 14389*/ GIMT_Encode4(898350), // Rule ID 3527 //
     /*  898294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  898297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  898302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  898305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898311 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  898314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  898318 */     // MIs[0] cbsz
     /*  898318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898321 */     // MIs[0] abid
     /*  898321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898324 */     // MIs[0] blgp
     /*  898324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898327 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31822),
     /*  898331 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31822>>  =>  (V_MFMA_I32_16X16X64_I8_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_e64),
     /*  898334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898336 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898338 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898340 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898342 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898344 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898346 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898348 */     GIR_RootConstrainSelectedInstOperands,
     /*  898349 */     // GIR_Coverage, 3527,
     /*  898349 */     GIR_EraseRootFromParent_Done,
     /*  898350 */   // Label 14389: @898350
     /*  898350 */   GIM_Try, /*On fail goto*//*Label 14390*/ GIMT_Encode4(898411), // Rule ID 3528 //
     /*  898355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  898358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  898363 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  898366 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898369 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898372 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  898375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  898379 */     // MIs[0] cbsz
     /*  898379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898382 */     // MIs[0] abid
     /*  898382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898385 */     // MIs[0] blgp
     /*  898385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898388 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31822),
     /*  898392 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31822>>  =>  (V_MFMA_I32_16X16X64_I8_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_e64),
     /*  898395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898397 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898399 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898401 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898403 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898405 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898407 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898409 */     GIR_RootConstrainSelectedInstOperands,
     /*  898410 */     // GIR_Coverage, 3528,
     /*  898410 */     GIR_EraseRootFromParent_Done,
     /*  898411 */   // Label 14390: @898411
     /*  898411 */   GIM_Try, /*On fail goto*//*Label 14391*/ GIMT_Encode4(898472), // Rule ID 3534 //
     /*  898416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  898419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  898424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898430 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898433 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898440 */     // MIs[0] cbsz
     /*  898440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898443 */     // MIs[0] abid
     /*  898443 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898446 */     // MIs[0] blgp
     /*  898446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898449 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31834),
     /*  898453 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31834>>  =>  (V_MFMA_I32_32X32X32_I8_mac_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_e64),
     /*  898456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898458 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898460 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898462 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898464 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898466 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898468 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898470 */     GIR_RootConstrainSelectedInstOperands,
     /*  898471 */     // GIR_Coverage, 3534,
     /*  898471 */     GIR_EraseRootFromParent_Done,
     /*  898472 */   // Label 14391: @898472
     /*  898472 */   GIM_Try, /*On fail goto*//*Label 14392*/ GIMT_Encode4(898533), // Rule ID 3535 //
     /*  898477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  898480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  898485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898494 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898501 */     // MIs[0] cbsz
     /*  898501 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898504 */     // MIs[0] abid
     /*  898504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898507 */     // MIs[0] blgp
     /*  898507 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898510 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31834),
     /*  898514 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31834>>  =>  (V_MFMA_I32_32X32X32_I8_mac_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_e64),
     /*  898517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898519 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898521 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898523 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898525 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898527 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898529 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898531 */     GIR_RootConstrainSelectedInstOperands,
     /*  898532 */     // GIR_Coverage, 3535,
     /*  898532 */     GIR_EraseRootFromParent_Done,
     /*  898533 */   // Label 14392: @898533
     /*  898533 */   GIM_Try, /*On fail goto*//*Label 14393*/ GIMT_Encode4(898594), // Rule ID 3536 //
     /*  898538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  898541 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  898546 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898549 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898552 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898555 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898562 */     // MIs[0] cbsz
     /*  898562 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898565 */     // MIs[0] abid
     /*  898565 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898568 */     // MIs[0] blgp
     /*  898568 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898571 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31834),
     /*  898575 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31834>>  =>  (V_MFMA_I32_32X32X32_I8_mac_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_e64),
     /*  898578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898580 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898582 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898584 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898586 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898588 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898590 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898592 */     GIR_RootConstrainSelectedInstOperands,
     /*  898593 */     // GIR_Coverage, 3536,
     /*  898593 */     GIR_EraseRootFromParent_Done,
     /*  898594 */   // Label 14393: @898594
     /*  898594 */   GIM_Try, /*On fail goto*//*Label 14394*/ GIMT_Encode4(898655), // Rule ID 3537 //
     /*  898599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  898602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  898607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898616 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898623 */     // MIs[0] cbsz
     /*  898623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898626 */     // MIs[0] abid
     /*  898626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898629 */     // MIs[0] blgp
     /*  898629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898632 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31834),
     /*  898636 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31834>>  =>  (V_MFMA_I32_32X32X32_I8_mac_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_e64),
     /*  898639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898641 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898643 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898645 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898647 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898649 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898651 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898653 */     GIR_RootConstrainSelectedInstOperands,
     /*  898654 */     // GIR_Coverage, 3537,
     /*  898654 */     GIR_EraseRootFromParent_Done,
     /*  898655 */   // Label 14394: @898655
     /*  898655 */   GIM_Try, /*On fail goto*//*Label 14395*/ GIMT_Encode4(898716), // Rule ID 3538 //
     /*  898660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  898663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  898668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  898671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  898674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  898677 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  898680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  898684 */     // MIs[0] cbsz
     /*  898684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898687 */     // MIs[0] abid
     /*  898687 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898690 */     // MIs[0] blgp
     /*  898690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898693 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31834),
     /*  898697 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31834>>  =>  (V_MFMA_I32_32X32X32_I8_mac_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_e64),
     /*  898700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898702 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898704 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898706 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898708 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898710 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898712 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898714 */     GIR_RootConstrainSelectedInstOperands,
     /*  898715 */     // GIR_Coverage, 3538,
     /*  898715 */     GIR_EraseRootFromParent_Done,
     /*  898716 */   // Label 14395: @898716
     /*  898716 */   GIM_Try, /*On fail goto*//*Label 14396*/ GIMT_Encode4(898777), // Rule ID 3904 //
     /*  898721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  898724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  898729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  898732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  898735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  898738 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  898741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  898745 */     // MIs[0] cbsz
     /*  898745 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898748 */     // MIs[0] abid
     /*  898748 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898751 */     // MIs[0] blgp
     /*  898751 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898754 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31958),
     /*  898758 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31958>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64),
     /*  898761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898763 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898765 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898767 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898769 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898771 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898773 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898775 */     GIR_RootConstrainSelectedInstOperands,
     /*  898776 */     // GIR_Coverage, 3904,
     /*  898776 */     GIR_EraseRootFromParent_Done,
     /*  898777 */   // Label 14396: @898777
     /*  898777 */   GIM_Try, /*On fail goto*//*Label 14397*/ GIMT_Encode4(898838), // Rule ID 3905 //
     /*  898782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  898785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  898790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  898793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  898796 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  898799 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  898802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  898806 */     // MIs[0] cbsz
     /*  898806 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898809 */     // MIs[0] abid
     /*  898809 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898812 */     // MIs[0] blgp
     /*  898812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898815 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31958),
     /*  898819 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31958>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64),
     /*  898822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898824 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898826 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898828 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898830 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898832 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898834 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898836 */     GIR_RootConstrainSelectedInstOperands,
     /*  898837 */     // GIR_Coverage, 3905,
     /*  898837 */     GIR_EraseRootFromParent_Done,
     /*  898838 */   // Label 14397: @898838
     /*  898838 */   GIM_Try, /*On fail goto*//*Label 14398*/ GIMT_Encode4(898899), // Rule ID 3906 //
     /*  898843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  898846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  898851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  898854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  898857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  898860 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  898863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  898867 */     // MIs[0] cbsz
     /*  898867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898870 */     // MIs[0] abid
     /*  898870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898873 */     // MIs[0] blgp
     /*  898873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898876 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31958),
     /*  898880 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31958>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64),
     /*  898883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898885 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898887 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898889 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898891 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898893 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898895 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898897 */     GIR_RootConstrainSelectedInstOperands,
     /*  898898 */     // GIR_Coverage, 3906,
     /*  898898 */     GIR_EraseRootFromParent_Done,
     /*  898899 */   // Label 14398: @898899
     /*  898899 */   GIM_Try, /*On fail goto*//*Label 14399*/ GIMT_Encode4(898960), // Rule ID 3907 //
     /*  898904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  898907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  898912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  898915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  898918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  898921 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  898924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  898928 */     // MIs[0] cbsz
     /*  898928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898931 */     // MIs[0] abid
     /*  898931 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898934 */     // MIs[0] blgp
     /*  898934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898937 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31958),
     /*  898941 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31958>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  898941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64),
     /*  898944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  898946 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  898948 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  898950 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  898952 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  898954 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  898956 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  898958 */     GIR_RootConstrainSelectedInstOperands,
     /*  898959 */     // GIR_Coverage, 3907,
     /*  898959 */     GIR_EraseRootFromParent_Done,
     /*  898960 */   // Label 14399: @898960
     /*  898960 */   GIM_Try, /*On fail goto*//*Label 14400*/ GIMT_Encode4(899021), // Rule ID 3908 //
     /*  898965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  898968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  898973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  898976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  898979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  898982 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  898985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
     /*  898989 */     // MIs[0] cbsz
     /*  898989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  898992 */     // MIs[0] abid
     /*  898992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  898995 */     // MIs[0] blgp
     /*  898995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  898998 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31958),
     /*  899002 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31958>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64),
     /*  899005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899007 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899009 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899011 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899013 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899015 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899017 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899019 */     GIR_RootConstrainSelectedInstOperands,
     /*  899020 */     // GIR_Coverage, 3908,
     /*  899020 */     GIR_EraseRootFromParent_Done,
     /*  899021 */   // Label 14400: @899021
     /*  899021 */   GIM_Try, /*On fail goto*//*Label 14401*/ GIMT_Encode4(899082), // Rule ID 3914 //
     /*  899026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  899029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  899034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899043 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899050 */     // MIs[0] cbsz
     /*  899050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899053 */     // MIs[0] abid
     /*  899053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899056 */     // MIs[0] blgp
     /*  899056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899059 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31964),
     /*  899063 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31964>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64),
     /*  899066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899068 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899070 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899072 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899074 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899076 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899078 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899080 */     GIR_RootConstrainSelectedInstOperands,
     /*  899081 */     // GIR_Coverage, 3914,
     /*  899081 */     GIR_EraseRootFromParent_Done,
     /*  899082 */   // Label 14401: @899082
     /*  899082 */   GIM_Try, /*On fail goto*//*Label 14402*/ GIMT_Encode4(899143), // Rule ID 3915 //
     /*  899087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  899090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  899095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899104 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899111 */     // MIs[0] cbsz
     /*  899111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899114 */     // MIs[0] abid
     /*  899114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899117 */     // MIs[0] blgp
     /*  899117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899120 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31964),
     /*  899124 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31964>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64),
     /*  899127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899129 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899131 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899133 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899135 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899137 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899139 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899141 */     GIR_RootConstrainSelectedInstOperands,
     /*  899142 */     // GIR_Coverage, 3915,
     /*  899142 */     GIR_EraseRootFromParent_Done,
     /*  899143 */   // Label 14402: @899143
     /*  899143 */   GIM_Try, /*On fail goto*//*Label 14403*/ GIMT_Encode4(899204), // Rule ID 3916 //
     /*  899148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  899151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  899156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899165 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899172 */     // MIs[0] cbsz
     /*  899172 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899175 */     // MIs[0] abid
     /*  899175 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899178 */     // MIs[0] blgp
     /*  899178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899181 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31964),
     /*  899185 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31964>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64),
     /*  899188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899190 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899192 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899194 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899196 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899198 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899200 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899202 */     GIR_RootConstrainSelectedInstOperands,
     /*  899203 */     // GIR_Coverage, 3916,
     /*  899203 */     GIR_EraseRootFromParent_Done,
     /*  899204 */   // Label 14403: @899204
     /*  899204 */   GIM_Try, /*On fail goto*//*Label 14404*/ GIMT_Encode4(899265), // Rule ID 3917 //
     /*  899209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  899212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  899217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899226 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899233 */     // MIs[0] cbsz
     /*  899233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899236 */     // MIs[0] abid
     /*  899236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899239 */     // MIs[0] blgp
     /*  899239 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899242 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31964),
     /*  899246 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31964>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64),
     /*  899249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899251 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899253 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899255 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899257 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899259 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899261 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899263 */     GIR_RootConstrainSelectedInstOperands,
     /*  899264 */     // GIR_Coverage, 3917,
     /*  899264 */     GIR_EraseRootFromParent_Done,
     /*  899265 */   // Label 14404: @899265
     /*  899265 */   GIM_Try, /*On fail goto*//*Label 14405*/ GIMT_Encode4(899326), // Rule ID 3918 //
     /*  899270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  899273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  899278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899287 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899294 */     // MIs[0] cbsz
     /*  899294 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899297 */     // MIs[0] abid
     /*  899297 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899300 */     // MIs[0] blgp
     /*  899300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899303 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31964),
     /*  899307 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31964>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64),
     /*  899310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899312 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899314 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899316 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899318 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899320 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899322 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899324 */     GIR_RootConstrainSelectedInstOperands,
     /*  899325 */     // GIR_Coverage, 3918,
     /*  899325 */     GIR_EraseRootFromParent_Done,
     /*  899326 */   // Label 14405: @899326
     /*  899326 */   GIM_Try, /*On fail goto*//*Label 14406*/ GIMT_Encode4(899387), // Rule ID 3924 //
     /*  899331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  899334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  899339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  899342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899348 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  899351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  899355 */     // MIs[0] cbsz
     /*  899355 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899358 */     // MIs[0] abid
     /*  899358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899361 */     // MIs[0] blgp
     /*  899361 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899364 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31968),
     /*  899368 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31968>>  =>  (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64),
     /*  899371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899373 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899375 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899377 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899379 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899381 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899383 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899385 */     GIR_RootConstrainSelectedInstOperands,
     /*  899386 */     // GIR_Coverage, 3924,
     /*  899386 */     GIR_EraseRootFromParent_Done,
     /*  899387 */   // Label 14406: @899387
     /*  899387 */   GIM_Try, /*On fail goto*//*Label 14407*/ GIMT_Encode4(899448), // Rule ID 3925 //
     /*  899392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  899395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  899400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  899403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  899412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  899416 */     // MIs[0] cbsz
     /*  899416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899419 */     // MIs[0] abid
     /*  899419 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899422 */     // MIs[0] blgp
     /*  899422 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899425 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31968),
     /*  899429 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31968>>  =>  (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64),
     /*  899432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899434 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899436 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899438 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899440 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899442 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899444 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899446 */     GIR_RootConstrainSelectedInstOperands,
     /*  899447 */     // GIR_Coverage, 3925,
     /*  899447 */     GIR_EraseRootFromParent_Done,
     /*  899448 */   // Label 14407: @899448
     /*  899448 */   GIM_Try, /*On fail goto*//*Label 14408*/ GIMT_Encode4(899509), // Rule ID 3926 //
     /*  899453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  899456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  899461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  899464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899467 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899470 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  899473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  899477 */     // MIs[0] cbsz
     /*  899477 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899480 */     // MIs[0] abid
     /*  899480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899483 */     // MIs[0] blgp
     /*  899483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899486 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31968),
     /*  899490 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31968>>  =>  (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64),
     /*  899493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899495 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899497 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899499 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899501 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899503 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899505 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899507 */     GIR_RootConstrainSelectedInstOperands,
     /*  899508 */     // GIR_Coverage, 3926,
     /*  899508 */     GIR_EraseRootFromParent_Done,
     /*  899509 */   // Label 14408: @899509
     /*  899509 */   GIM_Try, /*On fail goto*//*Label 14409*/ GIMT_Encode4(899570), // Rule ID 3927 //
     /*  899514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  899517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  899522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  899525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899531 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  899534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  899538 */     // MIs[0] cbsz
     /*  899538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899541 */     // MIs[0] abid
     /*  899541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899544 */     // MIs[0] blgp
     /*  899544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899547 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31968),
     /*  899551 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31968>>  =>  (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64),
     /*  899554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899556 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899558 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899560 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899562 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899564 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899566 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899568 */     GIR_RootConstrainSelectedInstOperands,
     /*  899569 */     // GIR_Coverage, 3927,
     /*  899569 */     GIR_EraseRootFromParent_Done,
     /*  899570 */   // Label 14409: @899570
     /*  899570 */   GIM_Try, /*On fail goto*//*Label 14410*/ GIMT_Encode4(899631), // Rule ID 3928 //
     /*  899575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  899578 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  899583 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  899586 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899589 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899592 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  899595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  899599 */     // MIs[0] cbsz
     /*  899599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899602 */     // MIs[0] abid
     /*  899602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899605 */     // MIs[0] blgp
     /*  899605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899608 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31968),
     /*  899612 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31968>>  =>  (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64),
     /*  899615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899617 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899619 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899621 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899623 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899625 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899627 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899629 */     GIR_RootConstrainSelectedInstOperands,
     /*  899630 */     // GIR_Coverage, 3928,
     /*  899630 */     GIR_EraseRootFromParent_Done,
     /*  899631 */   // Label 14410: @899631
     /*  899631 */   GIM_Try, /*On fail goto*//*Label 14411*/ GIMT_Encode4(899692), // Rule ID 3934 //
     /*  899636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  899639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  899644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899653 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899660 */     // MIs[0] cbsz
     /*  899660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899663 */     // MIs[0] abid
     /*  899663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899666 */     // MIs[0] blgp
     /*  899666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899669 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31972),
     /*  899673 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31972>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64),
     /*  899676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899678 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899680 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899682 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899684 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899686 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899688 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899690 */     GIR_RootConstrainSelectedInstOperands,
     /*  899691 */     // GIR_Coverage, 3934,
     /*  899691 */     GIR_EraseRootFromParent_Done,
     /*  899692 */   // Label 14411: @899692
     /*  899692 */   GIM_Try, /*On fail goto*//*Label 14412*/ GIMT_Encode4(899753), // Rule ID 3935 //
     /*  899697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  899700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  899705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899721 */     // MIs[0] cbsz
     /*  899721 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899724 */     // MIs[0] abid
     /*  899724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899727 */     // MIs[0] blgp
     /*  899727 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899730 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31972),
     /*  899734 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31972>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64),
     /*  899737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899739 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899741 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899743 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899745 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899747 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899749 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899751 */     GIR_RootConstrainSelectedInstOperands,
     /*  899752 */     // GIR_Coverage, 3935,
     /*  899752 */     GIR_EraseRootFromParent_Done,
     /*  899753 */   // Label 14412: @899753
     /*  899753 */   GIM_Try, /*On fail goto*//*Label 14413*/ GIMT_Encode4(899814), // Rule ID 3936 //
     /*  899758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  899761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  899766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899775 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899782 */     // MIs[0] cbsz
     /*  899782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899785 */     // MIs[0] abid
     /*  899785 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899788 */     // MIs[0] blgp
     /*  899788 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899791 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31972),
     /*  899795 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31972>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64),
     /*  899798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899800 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899802 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899804 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899806 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899808 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899810 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899812 */     GIR_RootConstrainSelectedInstOperands,
     /*  899813 */     // GIR_Coverage, 3936,
     /*  899813 */     GIR_EraseRootFromParent_Done,
     /*  899814 */   // Label 14413: @899814
     /*  899814 */   GIM_Try, /*On fail goto*//*Label 14414*/ GIMT_Encode4(899875), // Rule ID 3937 //
     /*  899819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  899822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  899827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899836 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899843 */     // MIs[0] cbsz
     /*  899843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899846 */     // MIs[0] abid
     /*  899846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899849 */     // MIs[0] blgp
     /*  899849 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899852 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31972),
     /*  899856 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31972>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64),
     /*  899859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899861 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899863 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899865 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899867 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899869 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899871 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899873 */     GIR_RootConstrainSelectedInstOperands,
     /*  899874 */     // GIR_Coverage, 3937,
     /*  899874 */     GIR_EraseRootFromParent_Done,
     /*  899875 */   // Label 14414: @899875
     /*  899875 */   GIM_Try, /*On fail goto*//*Label 14415*/ GIMT_Encode4(899936), // Rule ID 3938 //
     /*  899880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  899883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  899888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  899891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  899900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  899904 */     // MIs[0] cbsz
     /*  899904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899907 */     // MIs[0] abid
     /*  899907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899910 */     // MIs[0] blgp
     /*  899910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899913 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31972),
     /*  899917 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31972>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64),
     /*  899920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899922 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899924 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899926 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899928 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899930 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899932 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899934 */     GIR_RootConstrainSelectedInstOperands,
     /*  899935 */     // GIR_Coverage, 3938,
     /*  899935 */     GIR_EraseRootFromParent_Done,
     /*  899936 */   // Label 14415: @899936
     /*  899936 */   GIM_Try, /*On fail goto*//*Label 14416*/ GIMT_Encode4(899997), // Rule ID 3944 //
     /*  899941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  899944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  899949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  899952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  899955 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  899958 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  899961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  899965 */     // MIs[0] cbsz
     /*  899965 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  899968 */     // MIs[0] abid
     /*  899968 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  899971 */     // MIs[0] blgp
     /*  899971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  899974 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31976),
     /*  899978 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31976>>  =>  (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  899978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64),
     /*  899981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  899983 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  899985 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  899987 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  899989 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  899991 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  899993 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  899995 */     GIR_RootConstrainSelectedInstOperands,
     /*  899996 */     // GIR_Coverage, 3944,
     /*  899996 */     GIR_EraseRootFromParent_Done,
     /*  899997 */   // Label 14416: @899997
     /*  899997 */   GIM_Try, /*On fail goto*//*Label 14417*/ GIMT_Encode4(900058), // Rule ID 3945 //
     /*  900002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  900005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  900010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  900013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  900016 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  900019 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  900022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  900026 */     // MIs[0] cbsz
     /*  900026 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900029 */     // MIs[0] abid
     /*  900029 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900032 */     // MIs[0] blgp
     /*  900032 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900035 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31976),
     /*  900039 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31976>>  =>  (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64),
     /*  900042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900044 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900046 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900048 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900050 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900052 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900054 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900056 */     GIR_RootConstrainSelectedInstOperands,
     /*  900057 */     // GIR_Coverage, 3945,
     /*  900057 */     GIR_EraseRootFromParent_Done,
     /*  900058 */   // Label 14417: @900058
     /*  900058 */   GIM_Try, /*On fail goto*//*Label 14418*/ GIMT_Encode4(900119), // Rule ID 3946 //
     /*  900063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  900066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  900071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  900074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  900077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  900080 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  900083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  900087 */     // MIs[0] cbsz
     /*  900087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900090 */     // MIs[0] abid
     /*  900090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900093 */     // MIs[0] blgp
     /*  900093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900096 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31976),
     /*  900100 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31976>>  =>  (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64),
     /*  900103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900105 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900107 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900109 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900111 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900113 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900115 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900117 */     GIR_RootConstrainSelectedInstOperands,
     /*  900118 */     // GIR_Coverage, 3946,
     /*  900118 */     GIR_EraseRootFromParent_Done,
     /*  900119 */   // Label 14418: @900119
     /*  900119 */   GIM_Try, /*On fail goto*//*Label 14419*/ GIMT_Encode4(900180), // Rule ID 3947 //
     /*  900124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  900127 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  900132 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  900135 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  900138 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  900141 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  900144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  900148 */     // MIs[0] cbsz
     /*  900148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900151 */     // MIs[0] abid
     /*  900151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900154 */     // MIs[0] blgp
     /*  900154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900157 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31976),
     /*  900161 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31976>>  =>  (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64),
     /*  900164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900166 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900168 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900170 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900172 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900174 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900176 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900178 */     GIR_RootConstrainSelectedInstOperands,
     /*  900179 */     // GIR_Coverage, 3947,
     /*  900179 */     GIR_EraseRootFromParent_Done,
     /*  900180 */   // Label 14419: @900180
     /*  900180 */   GIM_Try, /*On fail goto*//*Label 14420*/ GIMT_Encode4(900241), // Rule ID 3948 //
     /*  900185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  900188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  900193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  900196 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  900199 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  900202 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  900205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  900209 */     // MIs[0] cbsz
     /*  900209 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900212 */     // MIs[0] abid
     /*  900212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900215 */     // MIs[0] blgp
     /*  900215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900218 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31976),
     /*  900222 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31976>>  =>  (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64),
     /*  900225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900229 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900231 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900233 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900235 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900237 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900239 */     GIR_RootConstrainSelectedInstOperands,
     /*  900240 */     // GIR_Coverage, 3948,
     /*  900240 */     GIR_EraseRootFromParent_Done,
     /*  900241 */   // Label 14420: @900241
     /*  900241 */   GIM_Try, /*On fail goto*//*Label 14421*/ GIMT_Encode4(900302), // Rule ID 3954 //
     /*  900246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  900249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  900254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  900257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900263 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  900266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID),
     /*  900270 */     // MIs[0] cbsz
     /*  900270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900273 */     // MIs[0] abid
     /*  900273 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900276 */     // MIs[0] blgp
     /*  900276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900279 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31982),
     /*  900283 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31982>>  =>  (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64),
     /*  900286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900288 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900290 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900292 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900294 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900296 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900298 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900300 */     GIR_RootConstrainSelectedInstOperands,
     /*  900301 */     // GIR_Coverage, 3954,
     /*  900301 */     GIR_EraseRootFromParent_Done,
     /*  900302 */   // Label 14421: @900302
     /*  900302 */   GIM_Try, /*On fail goto*//*Label 14422*/ GIMT_Encode4(900363), // Rule ID 3955 //
     /*  900307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  900310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  900315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  900318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900321 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900324 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  900327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID),
     /*  900331 */     // MIs[0] cbsz
     /*  900331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900334 */     // MIs[0] abid
     /*  900334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900337 */     // MIs[0] blgp
     /*  900337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900340 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31982),
     /*  900344 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31982>>  =>  (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64),
     /*  900347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900349 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900351 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900353 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900355 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900357 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900359 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900361 */     GIR_RootConstrainSelectedInstOperands,
     /*  900362 */     // GIR_Coverage, 3955,
     /*  900362 */     GIR_EraseRootFromParent_Done,
     /*  900363 */   // Label 14422: @900363
     /*  900363 */   GIM_Try, /*On fail goto*//*Label 14423*/ GIMT_Encode4(900424), // Rule ID 3956 //
     /*  900368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  900371 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  900376 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  900379 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900382 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900385 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  900388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID),
     /*  900392 */     // MIs[0] cbsz
     /*  900392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900395 */     // MIs[0] abid
     /*  900395 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900398 */     // MIs[0] blgp
     /*  900398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900401 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31982),
     /*  900405 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31982>>  =>  (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64),
     /*  900408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900410 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900412 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900414 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900416 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900418 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900420 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900422 */     GIR_RootConstrainSelectedInstOperands,
     /*  900423 */     // GIR_Coverage, 3956,
     /*  900423 */     GIR_EraseRootFromParent_Done,
     /*  900424 */   // Label 14423: @900424
     /*  900424 */   GIM_Try, /*On fail goto*//*Label 14424*/ GIMT_Encode4(900485), // Rule ID 3957 //
     /*  900429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  900432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  900437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  900440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  900449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID),
     /*  900453 */     // MIs[0] cbsz
     /*  900453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900456 */     // MIs[0] abid
     /*  900456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900459 */     // MIs[0] blgp
     /*  900459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900462 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31982),
     /*  900466 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31982>>  =>  (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64),
     /*  900469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900471 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900473 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900475 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900477 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900479 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900481 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900483 */     GIR_RootConstrainSelectedInstOperands,
     /*  900484 */     // GIR_Coverage, 3957,
     /*  900484 */     GIR_EraseRootFromParent_Done,
     /*  900485 */   // Label 14424: @900485
     /*  900485 */   GIM_Try, /*On fail goto*//*Label 14425*/ GIMT_Encode4(900546), // Rule ID 3958 //
     /*  900490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  900493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  900498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  900501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900507 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  900510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID),
     /*  900514 */     // MIs[0] cbsz
     /*  900514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900517 */     // MIs[0] abid
     /*  900517 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900520 */     // MIs[0] blgp
     /*  900520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900523 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31982),
     /*  900527 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31982>>  =>  (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64),
     /*  900530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900532 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900534 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900536 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900538 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900540 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900542 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900544 */     GIR_RootConstrainSelectedInstOperands,
     /*  900545 */     // GIR_Coverage, 3958,
     /*  900545 */     GIR_EraseRootFromParent_Done,
     /*  900546 */   // Label 14425: @900546
     /*  900546 */   GIM_Try, /*On fail goto*//*Label 14426*/ GIMT_Encode4(900607), // Rule ID 3964 //
     /*  900551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  900554 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  900559 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  900562 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900565 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900568 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  900571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID),
     /*  900575 */     // MIs[0] cbsz
     /*  900575 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900578 */     // MIs[0] abid
     /*  900578 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900581 */     // MIs[0] blgp
     /*  900581 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900584 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31986),
     /*  900588 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31986>>  =>  (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64),
     /*  900591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900593 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900595 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900597 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900599 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900601 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900603 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900605 */     GIR_RootConstrainSelectedInstOperands,
     /*  900606 */     // GIR_Coverage, 3964,
     /*  900606 */     GIR_EraseRootFromParent_Done,
     /*  900607 */   // Label 14426: @900607
     /*  900607 */   GIM_Try, /*On fail goto*//*Label 14427*/ GIMT_Encode4(900668), // Rule ID 3965 //
     /*  900612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  900615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  900620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  900623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900629 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  900632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID),
     /*  900636 */     // MIs[0] cbsz
     /*  900636 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900639 */     // MIs[0] abid
     /*  900639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900642 */     // MIs[0] blgp
     /*  900642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900645 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31986),
     /*  900649 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31986>>  =>  (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64),
     /*  900652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900654 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900656 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900658 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900660 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900662 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900664 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900666 */     GIR_RootConstrainSelectedInstOperands,
     /*  900667 */     // GIR_Coverage, 3965,
     /*  900667 */     GIR_EraseRootFromParent_Done,
     /*  900668 */   // Label 14427: @900668
     /*  900668 */   GIM_Try, /*On fail goto*//*Label 14428*/ GIMT_Encode4(900729), // Rule ID 3966 //
     /*  900673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  900676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  900681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  900684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900690 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  900693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID),
     /*  900697 */     // MIs[0] cbsz
     /*  900697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900700 */     // MIs[0] abid
     /*  900700 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900703 */     // MIs[0] blgp
     /*  900703 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900706 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31986),
     /*  900710 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31986>>  =>  (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64),
     /*  900713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900715 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900717 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900719 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900721 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900723 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900725 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900727 */     GIR_RootConstrainSelectedInstOperands,
     /*  900728 */     // GIR_Coverage, 3966,
     /*  900728 */     GIR_EraseRootFromParent_Done,
     /*  900729 */   // Label 14428: @900729
     /*  900729 */   GIM_Try, /*On fail goto*//*Label 14429*/ GIMT_Encode4(900790), // Rule ID 3967 //
     /*  900734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  900737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  900742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  900745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900751 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  900754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID),
     /*  900758 */     // MIs[0] cbsz
     /*  900758 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900761 */     // MIs[0] abid
     /*  900761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900764 */     // MIs[0] blgp
     /*  900764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900767 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31986),
     /*  900771 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31986>>  =>  (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64),
     /*  900774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900776 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900778 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900780 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900782 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900784 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900786 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900788 */     GIR_RootConstrainSelectedInstOperands,
     /*  900789 */     // GIR_Coverage, 3967,
     /*  900789 */     GIR_EraseRootFromParent_Done,
     /*  900790 */   // Label 14429: @900790
     /*  900790 */   GIM_Try, /*On fail goto*//*Label 14430*/ GIMT_Encode4(900851), // Rule ID 3968 //
     /*  900795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  900798 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  900803 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  900806 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900809 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900812 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  900815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID),
     /*  900819 */     // MIs[0] cbsz
     /*  900819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900822 */     // MIs[0] abid
     /*  900822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900825 */     // MIs[0] blgp
     /*  900825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900828 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31986),
     /*  900832 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31986>>  =>  (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64),
     /*  900835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900837 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900839 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900841 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900843 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900845 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900847 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900849 */     GIR_RootConstrainSelectedInstOperands,
     /*  900850 */     // GIR_Coverage, 3968,
     /*  900850 */     GIR_EraseRootFromParent_Done,
     /*  900851 */   // Label 14430: @900851
     /*  900851 */   GIM_Try, /*On fail goto*//*Label 14431*/ GIMT_Encode4(900912), // Rule ID 3974 //
     /*  900856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode0),
     /*  900859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  900864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  900867 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900870 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900873 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  900876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  900880 */     // MIs[0] cbsz
     /*  900880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900883 */     // MIs[0] abid
     /*  900883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900886 */     // MIs[0] blgp
     /*  900886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900889 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31992),
     /*  900893 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31992>>  =>  (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64),
     /*  900896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900898 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900900 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900902 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900904 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900906 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900908 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900910 */     GIR_RootConstrainSelectedInstOperands,
     /*  900911 */     // GIR_Coverage, 3974,
     /*  900911 */     GIR_EraseRootFromParent_Done,
     /*  900912 */   // Label 14431: @900912
     /*  900912 */   GIM_Try, /*On fail goto*//*Label 14432*/ GIMT_Encode4(900973), // Rule ID 3975 //
     /*  900917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode1),
     /*  900920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  900925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  900928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900934 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  900937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  900941 */     // MIs[0] cbsz
     /*  900941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  900944 */     // MIs[0] abid
     /*  900944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  900947 */     // MIs[0] blgp
     /*  900947 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  900950 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31992),
     /*  900954 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31992>>  =>  (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  900954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64),
     /*  900957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  900959 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  900961 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  900963 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  900965 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  900967 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  900969 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  900971 */     GIR_RootConstrainSelectedInstOperands,
     /*  900972 */     // GIR_Coverage, 3975,
     /*  900972 */     GIR_EraseRootFromParent_Done,
     /*  900973 */   // Label 14432: @900973
     /*  900973 */   GIM_Try, /*On fail goto*//*Label 14433*/ GIMT_Encode4(901034), // Rule ID 3976 //
     /*  900978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode2),
     /*  900981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  900986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  900989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  900992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  900995 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  900998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901002 */     // MIs[0] cbsz
     /*  901002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901005 */     // MIs[0] abid
     /*  901005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901008 */     // MIs[0] blgp
     /*  901008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901011 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31992),
     /*  901015 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31992>>  =>  (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64),
     /*  901018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901020 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901022 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901024 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901026 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901028 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901030 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901032 */     GIR_RootConstrainSelectedInstOperands,
     /*  901033 */     // GIR_Coverage, 3976,
     /*  901033 */     GIR_EraseRootFromParent_Done,
     /*  901034 */   // Label 14433: @901034
     /*  901034 */   GIM_Try, /*On fail goto*//*Label 14434*/ GIMT_Encode4(901095), // Rule ID 3977 //
     /*  901039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode3),
     /*  901042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  901047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  901050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901056 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  901059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901063 */     // MIs[0] cbsz
     /*  901063 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901066 */     // MIs[0] abid
     /*  901066 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901069 */     // MIs[0] blgp
     /*  901069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901072 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31992),
     /*  901076 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31992>>  =>  (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64),
     /*  901079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901081 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901083 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901085 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901087 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901089 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901091 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901093 */     GIR_RootConstrainSelectedInstOperands,
     /*  901094 */     // GIR_Coverage, 3977,
     /*  901094 */     GIR_EraseRootFromParent_Done,
     /*  901095 */   // Label 14434: @901095
     /*  901095 */   GIM_Try, /*On fail goto*//*Label 14435*/ GIMT_Encode4(901156), // Rule ID 3978 //
     /*  901100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode4),
     /*  901103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  901108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  901111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  901120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901124 */     // MIs[0] cbsz
     /*  901124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901127 */     // MIs[0] abid
     /*  901127 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901130 */     // MIs[0] blgp
     /*  901130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901133 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31992),
     /*  901137 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31992>>  =>  (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64),
     /*  901140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901142 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901144 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901146 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901148 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901150 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901152 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901154 */     GIR_RootConstrainSelectedInstOperands,
     /*  901155 */     // GIR_Coverage, 3978,
     /*  901155 */     GIR_EraseRootFromParent_Done,
     /*  901156 */   // Label 14435: @901156
     /*  901156 */   GIM_Try, /*On fail goto*//*Label 14436*/ GIMT_Encode4(901217), // Rule ID 3984 //
     /*  901161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode0),
     /*  901164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  901169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901178 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901185 */     // MIs[0] cbsz
     /*  901185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901188 */     // MIs[0] abid
     /*  901188 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901191 */     // MIs[0] blgp
     /*  901191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901194 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31996),
     /*  901198 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31996>>  =>  (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64),
     /*  901201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901203 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901205 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901207 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901209 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901211 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901213 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901215 */     GIR_RootConstrainSelectedInstOperands,
     /*  901216 */     // GIR_Coverage, 3984,
     /*  901216 */     GIR_EraseRootFromParent_Done,
     /*  901217 */   // Label 14436: @901217
     /*  901217 */   GIM_Try, /*On fail goto*//*Label 14437*/ GIMT_Encode4(901278), // Rule ID 3985 //
     /*  901222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode1),
     /*  901225 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  901230 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901233 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901236 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901239 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901246 */     // MIs[0] cbsz
     /*  901246 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901249 */     // MIs[0] abid
     /*  901249 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901252 */     // MIs[0] blgp
     /*  901252 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901255 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31996),
     /*  901259 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31996>>  =>  (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64),
     /*  901262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901264 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901266 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901268 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901270 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901272 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901274 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901276 */     GIR_RootConstrainSelectedInstOperands,
     /*  901277 */     // GIR_Coverage, 3985,
     /*  901277 */     GIR_EraseRootFromParent_Done,
     /*  901278 */   // Label 14437: @901278
     /*  901278 */   GIM_Try, /*On fail goto*//*Label 14438*/ GIMT_Encode4(901339), // Rule ID 3986 //
     /*  901283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode2),
     /*  901286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  901291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901300 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901307 */     // MIs[0] cbsz
     /*  901307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901310 */     // MIs[0] abid
     /*  901310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901313 */     // MIs[0] blgp
     /*  901313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901316 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31996),
     /*  901320 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31996>>  =>  (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64),
     /*  901323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901325 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901327 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901329 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901331 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901333 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901335 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901337 */     GIR_RootConstrainSelectedInstOperands,
     /*  901338 */     // GIR_Coverage, 3986,
     /*  901338 */     GIR_EraseRootFromParent_Done,
     /*  901339 */   // Label 14438: @901339
     /*  901339 */   GIM_Try, /*On fail goto*//*Label 14439*/ GIMT_Encode4(901400), // Rule ID 3987 //
     /*  901344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode3),
     /*  901347 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  901352 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901361 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901368 */     // MIs[0] cbsz
     /*  901368 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901371 */     // MIs[0] abid
     /*  901371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901374 */     // MIs[0] blgp
     /*  901374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901377 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31996),
     /*  901381 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31996>>  =>  (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64),
     /*  901384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901386 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901388 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901390 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901392 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901394 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901396 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901398 */     GIR_RootConstrainSelectedInstOperands,
     /*  901399 */     // GIR_Coverage, 3987,
     /*  901399 */     GIR_EraseRootFromParent_Done,
     /*  901400 */   // Label 14439: @901400
     /*  901400 */   GIM_Try, /*On fail goto*//*Label 14440*/ GIMT_Encode4(901461), // Rule ID 3988 //
     /*  901405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus_HwMode4),
     /*  901408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  901413 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901416 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  901419 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  901422 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901429 */     // MIs[0] cbsz
     /*  901429 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901432 */     // MIs[0] abid
     /*  901432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901435 */     // MIs[0] blgp
     /*  901435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901438 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31996),
     /*  901442 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_31996>>  =>  (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64),
     /*  901445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901447 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901449 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901451 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901453 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901455 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901457 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901459 */     GIR_RootConstrainSelectedInstOperands,
     /*  901460 */     // GIR_Coverage, 3988,
     /*  901460 */     GIR_EraseRootFromParent_Done,
     /*  901461 */   // Label 14440: @901461
     /*  901461 */   GIM_Try, /*On fail goto*//*Label 14441*/ GIMT_Encode4(901522), // Rule ID 3994 //
     /*  901466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode0),
     /*  901469 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  901474 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901477 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901480 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901483 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901490 */     // MIs[0] cbsz
     /*  901490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901493 */     // MIs[0] abid
     /*  901493 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901496 */     // MIs[0] blgp
     /*  901496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901499 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32000),
     /*  901503 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32000>>  =>  (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64),
     /*  901506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901508 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901510 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901512 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901514 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901516 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901518 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901520 */     GIR_RootConstrainSelectedInstOperands,
     /*  901521 */     // GIR_Coverage, 3994,
     /*  901521 */     GIR_EraseRootFromParent_Done,
     /*  901522 */   // Label 14441: @901522
     /*  901522 */   GIM_Try, /*On fail goto*//*Label 14442*/ GIMT_Encode4(901583), // Rule ID 3995 //
     /*  901527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode1),
     /*  901530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  901535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901538 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901541 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901544 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901551 */     // MIs[0] cbsz
     /*  901551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901554 */     // MIs[0] abid
     /*  901554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901557 */     // MIs[0] blgp
     /*  901557 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901560 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32000),
     /*  901564 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32000>>  =>  (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64),
     /*  901567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901569 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901571 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901573 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901575 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901577 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901579 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901581 */     GIR_RootConstrainSelectedInstOperands,
     /*  901582 */     // GIR_Coverage, 3995,
     /*  901582 */     GIR_EraseRootFromParent_Done,
     /*  901583 */   // Label 14442: @901583
     /*  901583 */   GIM_Try, /*On fail goto*//*Label 14443*/ GIMT_Encode4(901644), // Rule ID 3996 //
     /*  901588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode2),
     /*  901591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  901596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901605 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901612 */     // MIs[0] cbsz
     /*  901612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901615 */     // MIs[0] abid
     /*  901615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901618 */     // MIs[0] blgp
     /*  901618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901621 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32000),
     /*  901625 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32000>>  =>  (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64),
     /*  901628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901630 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901632 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901634 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901636 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901638 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901640 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901642 */     GIR_RootConstrainSelectedInstOperands,
     /*  901643 */     // GIR_Coverage, 3996,
     /*  901643 */     GIR_EraseRootFromParent_Done,
     /*  901644 */   // Label 14443: @901644
     /*  901644 */   GIM_Try, /*On fail goto*//*Label 14444*/ GIMT_Encode4(901705), // Rule ID 3997 //
     /*  901649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode3),
     /*  901652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  901657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901663 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901666 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901673 */     // MIs[0] cbsz
     /*  901673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901676 */     // MIs[0] abid
     /*  901676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901679 */     // MIs[0] blgp
     /*  901679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901682 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32000),
     /*  901686 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32000>>  =>  (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64),
     /*  901689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901691 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901693 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901695 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901697 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901699 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901701 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901703 */     GIR_RootConstrainSelectedInstOperands,
     /*  901704 */     // GIR_Coverage, 3997,
     /*  901704 */     GIR_EraseRootFromParent_Done,
     /*  901705 */   // Label 14444: @901705
     /*  901705 */   GIM_Try, /*On fail goto*//*Label 14445*/ GIMT_Encode4(901766), // Rule ID 3998 //
     /*  901710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode4),
     /*  901713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  901718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  901721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  901730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  901734 */     // MIs[0] cbsz
     /*  901734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901737 */     // MIs[0] abid
     /*  901737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901740 */     // MIs[0] blgp
     /*  901740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901743 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32000),
     /*  901747 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32000>>  =>  (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64),
     /*  901750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901752 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901754 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901756 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901758 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901760 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901762 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901764 */     GIR_RootConstrainSelectedInstOperands,
     /*  901765 */     // GIR_Coverage, 3998,
     /*  901765 */     GIR_EraseRootFromParent_Done,
     /*  901766 */   // Label 14445: @901766
     /*  901766 */   GIM_Try, /*On fail goto*//*Label 14446*/ GIMT_Encode4(901827), // Rule ID 4004 //
     /*  901771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode0),
     /*  901774 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  901779 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  901782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901785 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901788 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  901791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901795 */     // MIs[0] cbsz
     /*  901795 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901798 */     // MIs[0] abid
     /*  901798 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901801 */     // MIs[0] blgp
     /*  901801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901804 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32006),
     /*  901808 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32006>>  =>  (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64),
     /*  901811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901813 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901815 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901817 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901819 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901821 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901823 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901825 */     GIR_RootConstrainSelectedInstOperands,
     /*  901826 */     // GIR_Coverage, 4004,
     /*  901826 */     GIR_EraseRootFromParent_Done,
     /*  901827 */   // Label 14446: @901827
     /*  901827 */   GIM_Try, /*On fail goto*//*Label 14447*/ GIMT_Encode4(901888), // Rule ID 4005 //
     /*  901832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode1),
     /*  901835 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  901840 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  901843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901849 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  901852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901856 */     // MIs[0] cbsz
     /*  901856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901859 */     // MIs[0] abid
     /*  901859 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901862 */     // MIs[0] blgp
     /*  901862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901865 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32006),
     /*  901869 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32006>>  =>  (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64),
     /*  901872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901874 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901876 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901878 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901880 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901882 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901884 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901886 */     GIR_RootConstrainSelectedInstOperands,
     /*  901887 */     // GIR_Coverage, 4005,
     /*  901887 */     GIR_EraseRootFromParent_Done,
     /*  901888 */   // Label 14447: @901888
     /*  901888 */   GIM_Try, /*On fail goto*//*Label 14448*/ GIMT_Encode4(901949), // Rule ID 4006 //
     /*  901893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode2),
     /*  901896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  901901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  901904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901910 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  901913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901917 */     // MIs[0] cbsz
     /*  901917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901920 */     // MIs[0] abid
     /*  901920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901923 */     // MIs[0] blgp
     /*  901923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901926 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32006),
     /*  901930 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32006>>  =>  (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64),
     /*  901933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901935 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901937 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  901939 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  901941 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  901943 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  901945 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  901947 */     GIR_RootConstrainSelectedInstOperands,
     /*  901948 */     // GIR_Coverage, 4006,
     /*  901948 */     GIR_EraseRootFromParent_Done,
     /*  901949 */   // Label 14448: @901949
     /*  901949 */   GIM_Try, /*On fail goto*//*Label 14449*/ GIMT_Encode4(902010), // Rule ID 4007 //
     /*  901954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode3),
     /*  901957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  901962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  901965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  901968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  901971 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  901974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  901978 */     // MIs[0] cbsz
     /*  901978 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  901981 */     // MIs[0] abid
     /*  901981 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  901984 */     // MIs[0] blgp
     /*  901984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  901987 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32006),
     /*  901991 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32006>>  =>  (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  901991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64),
     /*  901994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  901996 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  901998 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902000 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902002 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902004 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902006 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902008 */     GIR_RootConstrainSelectedInstOperands,
     /*  902009 */     // GIR_Coverage, 4007,
     /*  902009 */     GIR_EraseRootFromParent_Done,
     /*  902010 */   // Label 14449: @902010
     /*  902010 */   GIM_Try, /*On fail goto*//*Label 14450*/ GIMT_Encode4(902071), // Rule ID 4008 //
     /*  902015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_HwMode4),
     /*  902018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  902023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  902026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  902029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  902032 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  902035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  902039 */     // MIs[0] cbsz
     /*  902039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902042 */     // MIs[0] abid
     /*  902042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902045 */     // MIs[0] blgp
     /*  902045 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902048 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32006),
     /*  902052 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32006>>  =>  (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64),
     /*  902055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902057 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902059 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902061 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902063 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902065 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902067 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902069 */     GIR_RootConstrainSelectedInstOperands,
     /*  902070 */     // GIR_Coverage, 4008,
     /*  902070 */     GIR_EraseRootFromParent_Done,
     /*  902071 */   // Label 14450: @902071
     /*  902071 */   GIM_Try, /*On fail goto*//*Label 14451*/ GIMT_Encode4(902132), // Rule ID 4014 //
     /*  902076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  902079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  902084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902093 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902100 */     // MIs[0] cbsz
     /*  902100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902103 */     // MIs[0] abid
     /*  902103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902106 */     // MIs[0] blgp
     /*  902106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902109 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32010),
     /*  902113 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32010>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64),
     /*  902116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902118 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902120 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902122 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902124 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902126 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902128 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902130 */     GIR_RootConstrainSelectedInstOperands,
     /*  902131 */     // GIR_Coverage, 4014,
     /*  902131 */     GIR_EraseRootFromParent_Done,
     /*  902132 */   // Label 14451: @902132
     /*  902132 */   GIM_Try, /*On fail goto*//*Label 14452*/ GIMT_Encode4(902193), // Rule ID 4015 //
     /*  902137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  902140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  902145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902154 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902161 */     // MIs[0] cbsz
     /*  902161 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902164 */     // MIs[0] abid
     /*  902164 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902167 */     // MIs[0] blgp
     /*  902167 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902170 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32010),
     /*  902174 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32010>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64),
     /*  902177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902179 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902181 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902183 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902185 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902187 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902189 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902191 */     GIR_RootConstrainSelectedInstOperands,
     /*  902192 */     // GIR_Coverage, 4015,
     /*  902192 */     GIR_EraseRootFromParent_Done,
     /*  902193 */   // Label 14452: @902193
     /*  902193 */   GIM_Try, /*On fail goto*//*Label 14453*/ GIMT_Encode4(902254), // Rule ID 4016 //
     /*  902198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  902201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  902206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902215 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902222 */     // MIs[0] cbsz
     /*  902222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902225 */     // MIs[0] abid
     /*  902225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902228 */     // MIs[0] blgp
     /*  902228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902231 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32010),
     /*  902235 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32010>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64),
     /*  902238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902240 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902242 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902244 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902246 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902248 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902250 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902252 */     GIR_RootConstrainSelectedInstOperands,
     /*  902253 */     // GIR_Coverage, 4016,
     /*  902253 */     GIR_EraseRootFromParent_Done,
     /*  902254 */   // Label 14453: @902254
     /*  902254 */   GIM_Try, /*On fail goto*//*Label 14454*/ GIMT_Encode4(902315), // Rule ID 4017 //
     /*  902259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  902262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  902267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902270 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902276 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902283 */     // MIs[0] cbsz
     /*  902283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902286 */     // MIs[0] abid
     /*  902286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902289 */     // MIs[0] blgp
     /*  902289 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902292 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32010),
     /*  902296 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32010>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64),
     /*  902299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902301 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902303 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902305 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902307 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902309 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902311 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902313 */     GIR_RootConstrainSelectedInstOperands,
     /*  902314 */     // GIR_Coverage, 4017,
     /*  902314 */     GIR_EraseRootFromParent_Done,
     /*  902315 */   // Label 14454: @902315
     /*  902315 */   GIM_Try, /*On fail goto*//*Label 14455*/ GIMT_Encode4(902376), // Rule ID 4018 //
     /*  902320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  902323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  902328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902344 */     // MIs[0] cbsz
     /*  902344 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902347 */     // MIs[0] abid
     /*  902347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902350 */     // MIs[0] blgp
     /*  902350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902353 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32010),
     /*  902357 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32010>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64),
     /*  902360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902362 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902364 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902366 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902368 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902370 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902372 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902374 */     GIR_RootConstrainSelectedInstOperands,
     /*  902375 */     // GIR_Coverage, 4018,
     /*  902375 */     GIR_EraseRootFromParent_Done,
     /*  902376 */   // Label 14455: @902376
     /*  902376 */   GIM_Try, /*On fail goto*//*Label 14456*/ GIMT_Encode4(902437), // Rule ID 4024 //
     /*  902381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  902384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  902389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902392 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902395 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902398 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902405 */     // MIs[0] cbsz
     /*  902405 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902408 */     // MIs[0] abid
     /*  902408 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902411 */     // MIs[0] blgp
     /*  902411 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902414 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32014),
     /*  902418 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32014>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64),
     /*  902421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902423 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902425 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902427 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902429 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902431 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902433 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902435 */     GIR_RootConstrainSelectedInstOperands,
     /*  902436 */     // GIR_Coverage, 4024,
     /*  902436 */     GIR_EraseRootFromParent_Done,
     /*  902437 */   // Label 14456: @902437
     /*  902437 */   GIM_Try, /*On fail goto*//*Label 14457*/ GIMT_Encode4(902498), // Rule ID 4025 //
     /*  902442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  902445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  902450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902459 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902466 */     // MIs[0] cbsz
     /*  902466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902469 */     // MIs[0] abid
     /*  902469 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902472 */     // MIs[0] blgp
     /*  902472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902475 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32014),
     /*  902479 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32014>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64),
     /*  902482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902484 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902486 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902488 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902490 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902492 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902494 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902496 */     GIR_RootConstrainSelectedInstOperands,
     /*  902497 */     // GIR_Coverage, 4025,
     /*  902497 */     GIR_EraseRootFromParent_Done,
     /*  902498 */   // Label 14457: @902498
     /*  902498 */   GIM_Try, /*On fail goto*//*Label 14458*/ GIMT_Encode4(902559), // Rule ID 4026 //
     /*  902503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  902506 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  902511 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902514 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902520 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902527 */     // MIs[0] cbsz
     /*  902527 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902530 */     // MIs[0] abid
     /*  902530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902533 */     // MIs[0] blgp
     /*  902533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902536 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32014),
     /*  902540 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32014>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64),
     /*  902543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902545 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902547 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902549 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902551 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902553 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902555 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902557 */     GIR_RootConstrainSelectedInstOperands,
     /*  902558 */     // GIR_Coverage, 4026,
     /*  902558 */     GIR_EraseRootFromParent_Done,
     /*  902559 */   // Label 14458: @902559
     /*  902559 */   GIM_Try, /*On fail goto*//*Label 14459*/ GIMT_Encode4(902620), // Rule ID 4027 //
     /*  902564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  902567 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  902572 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902575 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902578 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902581 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902588 */     // MIs[0] cbsz
     /*  902588 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902591 */     // MIs[0] abid
     /*  902591 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902594 */     // MIs[0] blgp
     /*  902594 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902597 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32014),
     /*  902601 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32014>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64),
     /*  902604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902606 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902608 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902610 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902612 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902614 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902616 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902618 */     GIR_RootConstrainSelectedInstOperands,
     /*  902619 */     // GIR_Coverage, 4027,
     /*  902619 */     GIR_EraseRootFromParent_Done,
     /*  902620 */   // Label 14459: @902620
     /*  902620 */   GIM_Try, /*On fail goto*//*Label 14460*/ GIMT_Encode4(902681), // Rule ID 4028 //
     /*  902625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  902628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  902633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902639 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902642 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902649 */     // MIs[0] cbsz
     /*  902649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902652 */     // MIs[0] abid
     /*  902652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902655 */     // MIs[0] blgp
     /*  902655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902658 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32014),
     /*  902662 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32014>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64),
     /*  902665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902667 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902669 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902671 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902673 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902675 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902677 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902679 */     GIR_RootConstrainSelectedInstOperands,
     /*  902680 */     // GIR_Coverage, 4028,
     /*  902680 */     GIR_EraseRootFromParent_Done,
     /*  902681 */   // Label 14460: @902681
     /*  902681 */   GIM_Try, /*On fail goto*//*Label 14461*/ GIMT_Encode4(902742), // Rule ID 4034 //
     /*  902686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  902689 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  902694 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902700 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902703 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902710 */     // MIs[0] cbsz
     /*  902710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902713 */     // MIs[0] abid
     /*  902713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902716 */     // MIs[0] blgp
     /*  902716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902719 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32018),
     /*  902723 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32018>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64),
     /*  902726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902728 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902730 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902732 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902734 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902736 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902738 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902740 */     GIR_RootConstrainSelectedInstOperands,
     /*  902741 */     // GIR_Coverage, 4034,
     /*  902741 */     GIR_EraseRootFromParent_Done,
     /*  902742 */   // Label 14461: @902742
     /*  902742 */   GIM_Try, /*On fail goto*//*Label 14462*/ GIMT_Encode4(902803), // Rule ID 4035 //
     /*  902747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  902750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  902755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902761 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902764 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902771 */     // MIs[0] cbsz
     /*  902771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902774 */     // MIs[0] abid
     /*  902774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902777 */     // MIs[0] blgp
     /*  902777 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902780 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32018),
     /*  902784 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32018>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64),
     /*  902787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902789 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902791 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902793 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902795 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902797 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902799 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902801 */     GIR_RootConstrainSelectedInstOperands,
     /*  902802 */     // GIR_Coverage, 4035,
     /*  902802 */     GIR_EraseRootFromParent_Done,
     /*  902803 */   // Label 14462: @902803
     /*  902803 */   GIM_Try, /*On fail goto*//*Label 14463*/ GIMT_Encode4(902864), // Rule ID 4036 //
     /*  902808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  902811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  902816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902822 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902825 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902832 */     // MIs[0] cbsz
     /*  902832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902835 */     // MIs[0] abid
     /*  902835 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902838 */     // MIs[0] blgp
     /*  902838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902841 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32018),
     /*  902845 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32018>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64),
     /*  902848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902850 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902852 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902854 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902856 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902858 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902860 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902862 */     GIR_RootConstrainSelectedInstOperands,
     /*  902863 */     // GIR_Coverage, 4036,
     /*  902863 */     GIR_EraseRootFromParent_Done,
     /*  902864 */   // Label 14463: @902864
     /*  902864 */   GIM_Try, /*On fail goto*//*Label 14464*/ GIMT_Encode4(902925), // Rule ID 4037 //
     /*  902869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  902872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  902877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902886 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902893 */     // MIs[0] cbsz
     /*  902893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902896 */     // MIs[0] abid
     /*  902896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902899 */     // MIs[0] blgp
     /*  902899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902902 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32018),
     /*  902906 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32018>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64),
     /*  902909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902911 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902913 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902915 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902917 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902919 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902921 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902923 */     GIR_RootConstrainSelectedInstOperands,
     /*  902924 */     // GIR_Coverage, 4037,
     /*  902924 */     GIR_EraseRootFromParent_Done,
     /*  902925 */   // Label 14464: @902925
     /*  902925 */   GIM_Try, /*On fail goto*//*Label 14465*/ GIMT_Encode4(902986), // Rule ID 4038 //
     /*  902930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  902933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  902938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  902941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  902944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  902947 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  902950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  902954 */     // MIs[0] cbsz
     /*  902954 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  902957 */     // MIs[0] abid
     /*  902957 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  902960 */     // MIs[0] blgp
     /*  902960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  902963 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32018),
     /*  902967 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32018>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  902967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64),
     /*  902970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  902972 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  902974 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  902976 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  902978 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  902980 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  902982 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  902984 */     GIR_RootConstrainSelectedInstOperands,
     /*  902985 */     // GIR_Coverage, 4038,
     /*  902985 */     GIR_EraseRootFromParent_Done,
     /*  902986 */   // Label 14465: @902986
     /*  902986 */   GIM_Try, /*On fail goto*//*Label 14466*/ GIMT_Encode4(903047), // Rule ID 4044 //
     /*  902991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  902994 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  902999 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  903002 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903005 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903008 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  903011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  903015 */     // MIs[0] cbsz
     /*  903015 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903018 */     // MIs[0] abid
     /*  903018 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903021 */     // MIs[0] blgp
     /*  903021 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903024 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32022),
     /*  903028 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32022>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64),
     /*  903031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903033 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903035 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903037 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903039 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903041 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903043 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903045 */     GIR_RootConstrainSelectedInstOperands,
     /*  903046 */     // GIR_Coverage, 4044,
     /*  903046 */     GIR_EraseRootFromParent_Done,
     /*  903047 */   // Label 14466: @903047
     /*  903047 */   GIM_Try, /*On fail goto*//*Label 14467*/ GIMT_Encode4(903108), // Rule ID 4045 //
     /*  903052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  903055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  903060 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  903063 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903066 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903069 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  903072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  903076 */     // MIs[0] cbsz
     /*  903076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903079 */     // MIs[0] abid
     /*  903079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903082 */     // MIs[0] blgp
     /*  903082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903085 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32022),
     /*  903089 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32022>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64),
     /*  903092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903094 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903096 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903098 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903100 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903102 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903104 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903106 */     GIR_RootConstrainSelectedInstOperands,
     /*  903107 */     // GIR_Coverage, 4045,
     /*  903107 */     GIR_EraseRootFromParent_Done,
     /*  903108 */   // Label 14467: @903108
     /*  903108 */   GIM_Try, /*On fail goto*//*Label 14468*/ GIMT_Encode4(903169), // Rule ID 4046 //
     /*  903113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  903116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  903121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  903124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903130 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  903133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  903137 */     // MIs[0] cbsz
     /*  903137 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903140 */     // MIs[0] abid
     /*  903140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903143 */     // MIs[0] blgp
     /*  903143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903146 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32022),
     /*  903150 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32022>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64),
     /*  903153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903155 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903157 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903159 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903161 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903163 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903165 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903167 */     GIR_RootConstrainSelectedInstOperands,
     /*  903168 */     // GIR_Coverage, 4046,
     /*  903168 */     GIR_EraseRootFromParent_Done,
     /*  903169 */   // Label 14468: @903169
     /*  903169 */   GIM_Try, /*On fail goto*//*Label 14469*/ GIMT_Encode4(903230), // Rule ID 4047 //
     /*  903174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  903177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  903182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  903185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903191 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  903194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  903198 */     // MIs[0] cbsz
     /*  903198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903201 */     // MIs[0] abid
     /*  903201 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903204 */     // MIs[0] blgp
     /*  903204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903207 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32022),
     /*  903211 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32022>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64),
     /*  903214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903216 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903218 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903220 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903222 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903224 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903226 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903228 */     GIR_RootConstrainSelectedInstOperands,
     /*  903229 */     // GIR_Coverage, 4047,
     /*  903229 */     GIR_EraseRootFromParent_Done,
     /*  903230 */   // Label 14469: @903230
     /*  903230 */   GIM_Try, /*On fail goto*//*Label 14470*/ GIMT_Encode4(903291), // Rule ID 4048 //
     /*  903235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  903238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  903243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  903246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903249 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903252 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  903255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  903259 */     // MIs[0] cbsz
     /*  903259 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903262 */     // MIs[0] abid
     /*  903262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903265 */     // MIs[0] blgp
     /*  903265 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903268 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32022),
     /*  903272 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32022>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64),
     /*  903275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903277 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903279 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903281 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903283 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903285 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903287 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903289 */     GIR_RootConstrainSelectedInstOperands,
     /*  903290 */     // GIR_Coverage, 4048,
     /*  903290 */     GIR_EraseRootFromParent_Done,
     /*  903291 */   // Label 14470: @903291
     /*  903291 */   GIM_Try, /*On fail goto*//*Label 14471*/ GIMT_Encode4(903352), // Rule ID 4054 //
     /*  903296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  903299 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  903304 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903313 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903320 */     // MIs[0] cbsz
     /*  903320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903323 */     // MIs[0] abid
     /*  903323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903326 */     // MIs[0] blgp
     /*  903326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903329 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32028),
     /*  903333 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32028>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64),
     /*  903336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903338 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903340 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903342 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903344 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903346 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903348 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903350 */     GIR_RootConstrainSelectedInstOperands,
     /*  903351 */     // GIR_Coverage, 4054,
     /*  903351 */     GIR_EraseRootFromParent_Done,
     /*  903352 */   // Label 14471: @903352
     /*  903352 */   GIM_Try, /*On fail goto*//*Label 14472*/ GIMT_Encode4(903413), // Rule ID 4055 //
     /*  903357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  903360 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  903365 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903374 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903381 */     // MIs[0] cbsz
     /*  903381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903384 */     // MIs[0] abid
     /*  903384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903387 */     // MIs[0] blgp
     /*  903387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903390 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32028),
     /*  903394 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32028>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64),
     /*  903397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903399 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903401 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903403 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903405 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903407 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903409 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903411 */     GIR_RootConstrainSelectedInstOperands,
     /*  903412 */     // GIR_Coverage, 4055,
     /*  903412 */     GIR_EraseRootFromParent_Done,
     /*  903413 */   // Label 14472: @903413
     /*  903413 */   GIM_Try, /*On fail goto*//*Label 14473*/ GIMT_Encode4(903474), // Rule ID 4056 //
     /*  903418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  903421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  903426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903435 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903442 */     // MIs[0] cbsz
     /*  903442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903445 */     // MIs[0] abid
     /*  903445 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903448 */     // MIs[0] blgp
     /*  903448 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903451 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32028),
     /*  903455 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32028>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64),
     /*  903458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903460 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903462 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903464 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903466 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903468 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903470 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903472 */     GIR_RootConstrainSelectedInstOperands,
     /*  903473 */     // GIR_Coverage, 4056,
     /*  903473 */     GIR_EraseRootFromParent_Done,
     /*  903474 */   // Label 14473: @903474
     /*  903474 */   GIM_Try, /*On fail goto*//*Label 14474*/ GIMT_Encode4(903535), // Rule ID 4057 //
     /*  903479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  903482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  903487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903493 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903496 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903503 */     // MIs[0] cbsz
     /*  903503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903506 */     // MIs[0] abid
     /*  903506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903509 */     // MIs[0] blgp
     /*  903509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903512 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32028),
     /*  903516 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32028>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64),
     /*  903519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903521 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903523 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903525 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903527 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903529 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903531 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903533 */     GIR_RootConstrainSelectedInstOperands,
     /*  903534 */     // GIR_Coverage, 4057,
     /*  903534 */     GIR_EraseRootFromParent_Done,
     /*  903535 */   // Label 14474: @903535
     /*  903535 */   GIM_Try, /*On fail goto*//*Label 14475*/ GIMT_Encode4(903596), // Rule ID 4058 //
     /*  903540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  903543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  903548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903557 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903564 */     // MIs[0] cbsz
     /*  903564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903567 */     // MIs[0] abid
     /*  903567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903570 */     // MIs[0] blgp
     /*  903570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903573 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32028),
     /*  903577 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32028>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64),
     /*  903580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903582 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903584 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903586 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903588 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903590 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903592 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903594 */     GIR_RootConstrainSelectedInstOperands,
     /*  903595 */     // GIR_Coverage, 4058,
     /*  903595 */     GIR_EraseRootFromParent_Done,
     /*  903596 */   // Label 14475: @903596
     /*  903596 */   GIM_Try, /*On fail goto*//*Label 14476*/ GIMT_Encode4(903657), // Rule ID 4064 //
     /*  903601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  903604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  903609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903612 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903615 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903618 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903625 */     // MIs[0] cbsz
     /*  903625 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903628 */     // MIs[0] abid
     /*  903628 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903631 */     // MIs[0] blgp
     /*  903631 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903634 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32032),
     /*  903638 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32032>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64),
     /*  903641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903643 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903645 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903647 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903649 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903651 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903653 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903655 */     GIR_RootConstrainSelectedInstOperands,
     /*  903656 */     // GIR_Coverage, 4064,
     /*  903656 */     GIR_EraseRootFromParent_Done,
     /*  903657 */   // Label 14476: @903657
     /*  903657 */   GIM_Try, /*On fail goto*//*Label 14477*/ GIMT_Encode4(903718), // Rule ID 4065 //
     /*  903662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  903665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  903670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903679 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903686 */     // MIs[0] cbsz
     /*  903686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903689 */     // MIs[0] abid
     /*  903689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903692 */     // MIs[0] blgp
     /*  903692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903695 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32032),
     /*  903699 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32032>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64),
     /*  903702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903704 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903706 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903708 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903710 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903712 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903714 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903716 */     GIR_RootConstrainSelectedInstOperands,
     /*  903717 */     // GIR_Coverage, 4065,
     /*  903717 */     GIR_EraseRootFromParent_Done,
     /*  903718 */   // Label 14477: @903718
     /*  903718 */   GIM_Try, /*On fail goto*//*Label 14478*/ GIMT_Encode4(903779), // Rule ID 4066 //
     /*  903723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  903726 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  903731 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903734 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903737 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903740 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903747 */     // MIs[0] cbsz
     /*  903747 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903750 */     // MIs[0] abid
     /*  903750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903753 */     // MIs[0] blgp
     /*  903753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903756 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32032),
     /*  903760 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32032>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64),
     /*  903763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903765 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903767 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903769 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903771 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903773 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903775 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903777 */     GIR_RootConstrainSelectedInstOperands,
     /*  903778 */     // GIR_Coverage, 4066,
     /*  903778 */     GIR_EraseRootFromParent_Done,
     /*  903779 */   // Label 14478: @903779
     /*  903779 */   GIM_Try, /*On fail goto*//*Label 14479*/ GIMT_Encode4(903840), // Rule ID 4067 //
     /*  903784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  903787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  903792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903801 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903808 */     // MIs[0] cbsz
     /*  903808 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903811 */     // MIs[0] abid
     /*  903811 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903814 */     // MIs[0] blgp
     /*  903814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903817 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32032),
     /*  903821 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32032>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64),
     /*  903824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903826 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903828 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903830 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903832 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903834 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903836 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903838 */     GIR_RootConstrainSelectedInstOperands,
     /*  903839 */     // GIR_Coverage, 4067,
     /*  903839 */     GIR_EraseRootFromParent_Done,
     /*  903840 */   // Label 14479: @903840
     /*  903840 */   GIM_Try, /*On fail goto*//*Label 14480*/ GIMT_Encode4(903901), // Rule ID 4068 //
     /*  903845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  903848 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  903853 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903856 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903859 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903862 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903869 */     // MIs[0] cbsz
     /*  903869 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903872 */     // MIs[0] abid
     /*  903872 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903875 */     // MIs[0] blgp
     /*  903875 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903878 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32032),
     /*  903882 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32032>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64),
     /*  903885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903887 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903889 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903891 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903893 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903895 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903897 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903899 */     GIR_RootConstrainSelectedInstOperands,
     /*  903900 */     // GIR_Coverage, 4068,
     /*  903900 */     GIR_EraseRootFromParent_Done,
     /*  903901 */   // Label 14480: @903901
     /*  903901 */   GIM_Try, /*On fail goto*//*Label 14481*/ GIMT_Encode4(903962), // Rule ID 4074 //
     /*  903906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  903909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  903914 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903917 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903920 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903923 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903930 */     // MIs[0] cbsz
     /*  903930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903933 */     // MIs[0] abid
     /*  903933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903936 */     // MIs[0] blgp
     /*  903936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  903939 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32036),
     /*  903943 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32036>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  903943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64),
     /*  903946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  903948 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  903950 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  903952 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  903954 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  903956 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  903958 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  903960 */     GIR_RootConstrainSelectedInstOperands,
     /*  903961 */     // GIR_Coverage, 4074,
     /*  903961 */     GIR_EraseRootFromParent_Done,
     /*  903962 */   // Label 14481: @903962
     /*  903962 */   GIM_Try, /*On fail goto*//*Label 14482*/ GIMT_Encode4(904023), // Rule ID 4075 //
     /*  903967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  903970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  903975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  903978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  903981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  903984 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  903987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  903991 */     // MIs[0] cbsz
     /*  903991 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  903994 */     // MIs[0] abid
     /*  903994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  903997 */     // MIs[0] blgp
     /*  903997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904000 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32036),
     /*  904004 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32036>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64),
     /*  904007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904009 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904011 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904013 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904015 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904017 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904019 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904021 */     GIR_RootConstrainSelectedInstOperands,
     /*  904022 */     // GIR_Coverage, 4075,
     /*  904022 */     GIR_EraseRootFromParent_Done,
     /*  904023 */   // Label 14482: @904023
     /*  904023 */   GIM_Try, /*On fail goto*//*Label 14483*/ GIMT_Encode4(904084), // Rule ID 4076 //
     /*  904028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  904031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  904036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904045 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904052 */     // MIs[0] cbsz
     /*  904052 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904055 */     // MIs[0] abid
     /*  904055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904058 */     // MIs[0] blgp
     /*  904058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904061 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32036),
     /*  904065 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32036>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64),
     /*  904068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904070 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904072 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904074 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904076 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904078 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904080 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904082 */     GIR_RootConstrainSelectedInstOperands,
     /*  904083 */     // GIR_Coverage, 4076,
     /*  904083 */     GIR_EraseRootFromParent_Done,
     /*  904084 */   // Label 14483: @904084
     /*  904084 */   GIM_Try, /*On fail goto*//*Label 14484*/ GIMT_Encode4(904145), // Rule ID 4077 //
     /*  904089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  904092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  904097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904103 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904106 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904113 */     // MIs[0] cbsz
     /*  904113 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904116 */     // MIs[0] abid
     /*  904116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904119 */     // MIs[0] blgp
     /*  904119 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904122 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32036),
     /*  904126 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32036>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64),
     /*  904129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904131 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904133 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904135 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904137 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904139 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904141 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904143 */     GIR_RootConstrainSelectedInstOperands,
     /*  904144 */     // GIR_Coverage, 4077,
     /*  904144 */     GIR_EraseRootFromParent_Done,
     /*  904145 */   // Label 14484: @904145
     /*  904145 */   GIM_Try, /*On fail goto*//*Label 14485*/ GIMT_Encode4(904206), // Rule ID 4078 //
     /*  904150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  904153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  904158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904167 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904174 */     // MIs[0] cbsz
     /*  904174 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904177 */     // MIs[0] abid
     /*  904177 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904180 */     // MIs[0] blgp
     /*  904180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904183 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32036),
     /*  904187 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32036>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64),
     /*  904190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904192 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904194 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904196 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904198 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904200 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904202 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904204 */     GIR_RootConstrainSelectedInstOperands,
     /*  904205 */     // GIR_Coverage, 4078,
     /*  904205 */     GIR_EraseRootFromParent_Done,
     /*  904206 */   // Label 14485: @904206
     /*  904206 */   GIM_Try, /*On fail goto*//*Label 14486*/ GIMT_Encode4(904267), // Rule ID 4084 //
     /*  904211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode0),
     /*  904214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  904219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904228 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904235 */     // MIs[0] cbsz
     /*  904235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904238 */     // MIs[0] abid
     /*  904238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904241 */     // MIs[0] blgp
     /*  904241 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904244 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32040),
     /*  904248 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32040>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64),
     /*  904251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904253 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904255 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904257 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904259 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904261 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904263 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904265 */     GIR_RootConstrainSelectedInstOperands,
     /*  904266 */     // GIR_Coverage, 4084,
     /*  904266 */     GIR_EraseRootFromParent_Done,
     /*  904267 */   // Label 14486: @904267
     /*  904267 */   GIM_Try, /*On fail goto*//*Label 14487*/ GIMT_Encode4(904328), // Rule ID 4085 //
     /*  904272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode1),
     /*  904275 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  904280 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904283 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904286 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904289 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904296 */     // MIs[0] cbsz
     /*  904296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904299 */     // MIs[0] abid
     /*  904299 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904302 */     // MIs[0] blgp
     /*  904302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904305 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32040),
     /*  904309 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32040>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64),
     /*  904312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904314 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904316 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904318 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904320 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904322 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904324 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904326 */     GIR_RootConstrainSelectedInstOperands,
     /*  904327 */     // GIR_Coverage, 4085,
     /*  904327 */     GIR_EraseRootFromParent_Done,
     /*  904328 */   // Label 14487: @904328
     /*  904328 */   GIM_Try, /*On fail goto*//*Label 14488*/ GIMT_Encode4(904389), // Rule ID 4086 //
     /*  904333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode2),
     /*  904336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  904341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904350 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904357 */     // MIs[0] cbsz
     /*  904357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904360 */     // MIs[0] abid
     /*  904360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904363 */     // MIs[0] blgp
     /*  904363 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904366 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32040),
     /*  904370 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32040>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64),
     /*  904373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904375 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904377 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904379 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904381 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904383 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904385 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904387 */     GIR_RootConstrainSelectedInstOperands,
     /*  904388 */     // GIR_Coverage, 4086,
     /*  904388 */     GIR_EraseRootFromParent_Done,
     /*  904389 */   // Label 14488: @904389
     /*  904389 */   GIM_Try, /*On fail goto*//*Label 14489*/ GIMT_Encode4(904450), // Rule ID 4087 //
     /*  904394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode3),
     /*  904397 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  904402 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904405 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904408 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904411 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904418 */     // MIs[0] cbsz
     /*  904418 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904421 */     // MIs[0] abid
     /*  904421 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904424 */     // MIs[0] blgp
     /*  904424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904427 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32040),
     /*  904431 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32040>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64),
     /*  904434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904436 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904438 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904440 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904442 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904444 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904446 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904448 */     GIR_RootConstrainSelectedInstOperands,
     /*  904449 */     // GIR_Coverage, 4087,
     /*  904449 */     GIR_EraseRootFromParent_Done,
     /*  904450 */   // Label 14489: @904450
     /*  904450 */   GIM_Try, /*On fail goto*//*Label 14490*/ GIMT_Encode4(904511), // Rule ID 4088 //
     /*  904455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_HwMode4),
     /*  904458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  904463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  904469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  904472 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  904479 */     // MIs[0] cbsz
     /*  904479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904482 */     // MIs[0] abid
     /*  904482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904485 */     // MIs[0] blgp
     /*  904485 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904488 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_32040),
     /*  904492 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_32040>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64),
     /*  904495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904497 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904499 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904501 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904503 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904505 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904507 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904509 */     GIR_RootConstrainSelectedInstOperands,
     /*  904510 */     // GIR_Coverage, 4088,
     /*  904510 */     GIR_EraseRootFromParent_Done,
     /*  904511 */   // Label 14490: @904511
     /*  904511 */   GIM_Try, /*On fail goto*//*Label 14491*/ GIMT_Encode4(904568), // Rule ID 3351 //
     /*  904516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  904519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  904524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  904527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904530 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904533 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  904536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  904540 */     // MIs[0] cbsz
     /*  904540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904543 */     // MIs[0] abid
     /*  904543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904546 */     // MIs[0] blgp
     /*  904546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904549 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64),
     /*  904552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904554 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904556 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904558 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904560 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904562 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904564 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904566 */     GIR_RootConstrainSelectedInstOperands,
     /*  904567 */     // GIR_Coverage, 3351,
     /*  904567 */     GIR_EraseRootFromParent_Done,
     /*  904568 */   // Label 14491: @904568
     /*  904568 */   GIM_Try, /*On fail goto*//*Label 14492*/ GIMT_Encode4(904625), // Rule ID 3352 //
     /*  904573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  904576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  904581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  904584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  904593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  904597 */     // MIs[0] cbsz
     /*  904597 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904600 */     // MIs[0] abid
     /*  904600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904603 */     // MIs[0] blgp
     /*  904603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904606 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64),
     /*  904609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904611 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904613 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904615 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904617 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904619 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904621 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904623 */     GIR_RootConstrainSelectedInstOperands,
     /*  904624 */     // GIR_Coverage, 3352,
     /*  904624 */     GIR_EraseRootFromParent_Done,
     /*  904625 */   // Label 14492: @904625
     /*  904625 */   GIM_Try, /*On fail goto*//*Label 14493*/ GIMT_Encode4(904682), // Rule ID 3353 //
     /*  904630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  904633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  904638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  904641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904647 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  904650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  904654 */     // MIs[0] cbsz
     /*  904654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904657 */     // MIs[0] abid
     /*  904657 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904660 */     // MIs[0] blgp
     /*  904660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904663 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64),
     /*  904666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904668 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904670 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904672 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904674 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904676 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904678 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904680 */     GIR_RootConstrainSelectedInstOperands,
     /*  904681 */     // GIR_Coverage, 3353,
     /*  904681 */     GIR_EraseRootFromParent_Done,
     /*  904682 */   // Label 14493: @904682
     /*  904682 */   GIM_Try, /*On fail goto*//*Label 14494*/ GIMT_Encode4(904739), // Rule ID 3354 //
     /*  904687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  904690 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  904695 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  904698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904704 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  904707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  904711 */     // MIs[0] cbsz
     /*  904711 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904714 */     // MIs[0] abid
     /*  904714 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904717 */     // MIs[0] blgp
     /*  904717 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904720 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64),
     /*  904723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904725 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904727 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904729 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904731 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904733 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904735 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904737 */     GIR_RootConstrainSelectedInstOperands,
     /*  904738 */     // GIR_Coverage, 3354,
     /*  904738 */     GIR_EraseRootFromParent_Done,
     /*  904739 */   // Label 14494: @904739
     /*  904739 */   GIM_Try, /*On fail goto*//*Label 14495*/ GIMT_Encode4(904796), // Rule ID 3355 //
     /*  904744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  904747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
     /*  904752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  904755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904761 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  904764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  904768 */     // MIs[0] cbsz
     /*  904768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904771 */     // MIs[0] abid
     /*  904771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904774 */     // MIs[0] blgp
     /*  904774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904777 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3311:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64),
     /*  904780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904782 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904784 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904786 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904788 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904790 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904792 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904794 */     GIR_RootConstrainSelectedInstOperands,
     /*  904795 */     // GIR_Coverage, 3355,
     /*  904795 */     GIR_EraseRootFromParent_Done,
     /*  904796 */   // Label 14495: @904796
     /*  904796 */   GIM_Try, /*On fail goto*//*Label 14496*/ GIMT_Encode4(904853), // Rule ID 3358 //
     /*  904801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  904804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  904809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904818 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  904825 */     // MIs[0] cbsz
     /*  904825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904828 */     // MIs[0] abid
     /*  904828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904831 */     // MIs[0] blgp
     /*  904831 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904834 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64),
     /*  904837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904839 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904841 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904843 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904845 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904847 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904849 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904851 */     GIR_RootConstrainSelectedInstOperands,
     /*  904852 */     // GIR_Coverage, 3358,
     /*  904852 */     GIR_EraseRootFromParent_Done,
     /*  904853 */   // Label 14496: @904853
     /*  904853 */   GIM_Try, /*On fail goto*//*Label 14497*/ GIMT_Encode4(904910), // Rule ID 3359 //
     /*  904858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  904861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  904866 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904869 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904872 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904875 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  904882 */     // MIs[0] cbsz
     /*  904882 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904885 */     // MIs[0] abid
     /*  904885 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904888 */     // MIs[0] blgp
     /*  904888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904891 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64),
     /*  904894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904896 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904898 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904900 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904902 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904904 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904906 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904908 */     GIR_RootConstrainSelectedInstOperands,
     /*  904909 */     // GIR_Coverage, 3359,
     /*  904909 */     GIR_EraseRootFromParent_Done,
     /*  904910 */   // Label 14497: @904910
     /*  904910 */   GIM_Try, /*On fail goto*//*Label 14498*/ GIMT_Encode4(904967), // Rule ID 3360 //
     /*  904915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  904918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  904923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904932 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  904939 */     // MIs[0] cbsz
     /*  904939 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904942 */     // MIs[0] abid
     /*  904942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  904945 */     // MIs[0] blgp
     /*  904945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  904948 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  904948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64),
     /*  904951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  904953 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  904955 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  904957 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  904959 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  904961 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  904963 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  904965 */     GIR_RootConstrainSelectedInstOperands,
     /*  904966 */     // GIR_Coverage, 3360,
     /*  904966 */     GIR_EraseRootFromParent_Done,
     /*  904967 */   // Label 14498: @904967
     /*  904967 */   GIM_Try, /*On fail goto*//*Label 14499*/ GIMT_Encode4(905024), // Rule ID 3361 //
     /*  904972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  904975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  904980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  904983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  904986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  904989 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  904992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  904996 */     // MIs[0] cbsz
     /*  904996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  904999 */     // MIs[0] abid
     /*  904999 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905002 */     // MIs[0] blgp
     /*  905002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905005 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64),
     /*  905008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905010 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905012 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905014 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905016 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905018 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905020 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905022 */     GIR_RootConstrainSelectedInstOperands,
     /*  905023 */     // GIR_Coverage, 3361,
     /*  905023 */     GIR_EraseRootFromParent_Done,
     /*  905024 */   // Label 14499: @905024
     /*  905024 */   GIM_Try, /*On fail goto*//*Label 14500*/ GIMT_Encode4(905081), // Rule ID 3362 //
     /*  905029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  905032 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
     /*  905037 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  905040 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905043 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905046 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  905049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  905053 */     // MIs[0] cbsz
     /*  905053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905056 */     // MIs[0] abid
     /*  905056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905059 */     // MIs[0] blgp
     /*  905059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905062 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3283:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64),
     /*  905065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905067 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905069 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905071 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905073 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905075 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905077 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905079 */     GIR_RootConstrainSelectedInstOperands,
     /*  905080 */     // GIR_Coverage, 3362,
     /*  905080 */     GIR_EraseRootFromParent_Done,
     /*  905081 */   // Label 14500: @905081
     /*  905081 */   GIM_Try, /*On fail goto*//*Label 14501*/ GIMT_Encode4(905138), // Rule ID 3365 //
     /*  905086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  905089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  905094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  905097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905103 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  905106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  905110 */     // MIs[0] cbsz
     /*  905110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905113 */     // MIs[0] abid
     /*  905113 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905116 */     // MIs[0] blgp
     /*  905116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905119 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64),
     /*  905122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905124 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905126 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905128 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905130 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905132 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905134 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905136 */     GIR_RootConstrainSelectedInstOperands,
     /*  905137 */     // GIR_Coverage, 3365,
     /*  905137 */     GIR_EraseRootFromParent_Done,
     /*  905138 */   // Label 14501: @905138
     /*  905138 */   GIM_Try, /*On fail goto*//*Label 14502*/ GIMT_Encode4(905195), // Rule ID 3366 //
     /*  905143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  905146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  905151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  905154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905160 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  905163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  905167 */     // MIs[0] cbsz
     /*  905167 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905170 */     // MIs[0] abid
     /*  905170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905173 */     // MIs[0] blgp
     /*  905173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905176 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64),
     /*  905179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905181 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905183 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905185 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905187 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905189 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905191 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905193 */     GIR_RootConstrainSelectedInstOperands,
     /*  905194 */     // GIR_Coverage, 3366,
     /*  905194 */     GIR_EraseRootFromParent_Done,
     /*  905195 */   // Label 14502: @905195
     /*  905195 */   GIM_Try, /*On fail goto*//*Label 14503*/ GIMT_Encode4(905252), // Rule ID 3367 //
     /*  905200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  905203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  905208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  905211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905217 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  905220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  905224 */     // MIs[0] cbsz
     /*  905224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905227 */     // MIs[0] abid
     /*  905227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905230 */     // MIs[0] blgp
     /*  905230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905233 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64),
     /*  905236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905238 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905240 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905242 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905244 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905246 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905248 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905250 */     GIR_RootConstrainSelectedInstOperands,
     /*  905251 */     // GIR_Coverage, 3367,
     /*  905251 */     GIR_EraseRootFromParent_Done,
     /*  905252 */   // Label 14503: @905252
     /*  905252 */   GIM_Try, /*On fail goto*//*Label 14504*/ GIMT_Encode4(905309), // Rule ID 3368 //
     /*  905257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  905260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  905265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  905268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905274 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  905277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  905281 */     // MIs[0] cbsz
     /*  905281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905284 */     // MIs[0] abid
     /*  905284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905287 */     // MIs[0] blgp
     /*  905287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905290 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64),
     /*  905293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905295 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905297 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905299 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905301 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905303 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905305 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905307 */     GIR_RootConstrainSelectedInstOperands,
     /*  905308 */     // GIR_Coverage, 3368,
     /*  905308 */     GIR_EraseRootFromParent_Done,
     /*  905309 */   // Label 14504: @905309
     /*  905309 */   GIM_Try, /*On fail goto*//*Label 14505*/ GIMT_Encode4(905366), // Rule ID 3369 //
     /*  905314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  905317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
     /*  905322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  905325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905331 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  905334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  905338 */     // MIs[0] cbsz
     /*  905338 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905341 */     // MIs[0] abid
     /*  905341 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905344 */     // MIs[0] blgp
     /*  905344 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905347 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3293:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64),
     /*  905350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905352 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905354 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905356 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905358 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905360 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905362 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905364 */     GIR_RootConstrainSelectedInstOperands,
     /*  905365 */     // GIR_Coverage, 3369,
     /*  905365 */     GIR_EraseRootFromParent_Done,
     /*  905366 */   // Label 14505: @905366
     /*  905366 */   GIM_Try, /*On fail goto*//*Label 14506*/ GIMT_Encode4(905423), // Rule ID 3372 //
     /*  905371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  905374 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  905379 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  905382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905385 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905388 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  905391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  905395 */     // MIs[0] cbsz
     /*  905395 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905398 */     // MIs[0] abid
     /*  905398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905401 */     // MIs[0] blgp
     /*  905401 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905404 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64),
     /*  905407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905409 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905411 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905413 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905415 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905417 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905419 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905421 */     GIR_RootConstrainSelectedInstOperands,
     /*  905422 */     // GIR_Coverage, 3372,
     /*  905422 */     GIR_EraseRootFromParent_Done,
     /*  905423 */   // Label 14506: @905423
     /*  905423 */   GIM_Try, /*On fail goto*//*Label 14507*/ GIMT_Encode4(905480), // Rule ID 3373 //
     /*  905428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  905431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  905436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  905439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905445 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  905448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  905452 */     // MIs[0] cbsz
     /*  905452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905455 */     // MIs[0] abid
     /*  905455 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905458 */     // MIs[0] blgp
     /*  905458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905461 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64),
     /*  905464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905466 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905468 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905470 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905472 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905474 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905476 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905478 */     GIR_RootConstrainSelectedInstOperands,
     /*  905479 */     // GIR_Coverage, 3373,
     /*  905479 */     GIR_EraseRootFromParent_Done,
     /*  905480 */   // Label 14507: @905480
     /*  905480 */   GIM_Try, /*On fail goto*//*Label 14508*/ GIMT_Encode4(905537), // Rule ID 3374 //
     /*  905485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  905488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  905493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  905496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905499 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905502 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  905505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  905509 */     // MIs[0] cbsz
     /*  905509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905512 */     // MIs[0] abid
     /*  905512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905515 */     // MIs[0] blgp
     /*  905515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905518 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64),
     /*  905521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905523 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905525 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905527 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905529 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905531 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905533 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905535 */     GIR_RootConstrainSelectedInstOperands,
     /*  905536 */     // GIR_Coverage, 3374,
     /*  905536 */     GIR_EraseRootFromParent_Done,
     /*  905537 */   // Label 14508: @905537
     /*  905537 */   GIM_Try, /*On fail goto*//*Label 14509*/ GIMT_Encode4(905594), // Rule ID 3375 //
     /*  905542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  905545 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  905550 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  905553 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905556 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905559 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  905562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  905566 */     // MIs[0] cbsz
     /*  905566 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905569 */     // MIs[0] abid
     /*  905569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905572 */     // MIs[0] blgp
     /*  905572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905575 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64),
     /*  905578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905580 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905582 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905584 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905586 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905588 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905590 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905592 */     GIR_RootConstrainSelectedInstOperands,
     /*  905593 */     // GIR_Coverage, 3375,
     /*  905593 */     GIR_EraseRootFromParent_Done,
     /*  905594 */   // Label 14509: @905594
     /*  905594 */   GIM_Try, /*On fail goto*//*Label 14510*/ GIMT_Encode4(905651), // Rule ID 3376 //
     /*  905599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  905602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
     /*  905607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  905610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905616 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  905619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  905623 */     // MIs[0] cbsz
     /*  905623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905626 */     // MIs[0] abid
     /*  905626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905629 */     // MIs[0] blgp
     /*  905629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905632 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3302:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64),
     /*  905635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905637 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905639 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905641 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905643 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905645 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905647 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905649 */     GIR_RootConstrainSelectedInstOperands,
     /*  905650 */     // GIR_Coverage, 3376,
     /*  905650 */     GIR_EraseRootFromParent_Done,
     /*  905651 */   // Label 14510: @905651
     /*  905651 */   GIM_Try, /*On fail goto*//*Label 14511*/ GIMT_Encode4(905708), // Rule ID 3379 //
     /*  905656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  905659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  905664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  905667 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905673 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  905676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  905680 */     // MIs[0] cbsz
     /*  905680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905683 */     // MIs[0] abid
     /*  905683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905686 */     // MIs[0] blgp
     /*  905686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905689 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64),
     /*  905692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905694 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905696 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905698 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905700 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905702 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905704 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905706 */     GIR_RootConstrainSelectedInstOperands,
     /*  905707 */     // GIR_Coverage, 3379,
     /*  905707 */     GIR_EraseRootFromParent_Done,
     /*  905708 */   // Label 14511: @905708
     /*  905708 */   GIM_Try, /*On fail goto*//*Label 14512*/ GIMT_Encode4(905765), // Rule ID 3380 //
     /*  905713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  905716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  905721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  905724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905730 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  905733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  905737 */     // MIs[0] cbsz
     /*  905737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905740 */     // MIs[0] abid
     /*  905740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905743 */     // MIs[0] blgp
     /*  905743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905746 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64),
     /*  905749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905751 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905753 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905755 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905757 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905759 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905761 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905763 */     GIR_RootConstrainSelectedInstOperands,
     /*  905764 */     // GIR_Coverage, 3380,
     /*  905764 */     GIR_EraseRootFromParent_Done,
     /*  905765 */   // Label 14512: @905765
     /*  905765 */   GIM_Try, /*On fail goto*//*Label 14513*/ GIMT_Encode4(905822), // Rule ID 3381 //
     /*  905770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  905773 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  905778 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  905781 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905784 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905787 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  905790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  905794 */     // MIs[0] cbsz
     /*  905794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905797 */     // MIs[0] abid
     /*  905797 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905800 */     // MIs[0] blgp
     /*  905800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905803 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64),
     /*  905806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905808 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905810 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905812 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905814 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905816 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905818 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905820 */     GIR_RootConstrainSelectedInstOperands,
     /*  905821 */     // GIR_Coverage, 3381,
     /*  905821 */     GIR_EraseRootFromParent_Done,
     /*  905822 */   // Label 14513: @905822
     /*  905822 */   GIM_Try, /*On fail goto*//*Label 14514*/ GIMT_Encode4(905879), // Rule ID 3382 //
     /*  905827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  905830 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  905835 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  905838 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905841 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905844 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  905847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  905851 */     // MIs[0] cbsz
     /*  905851 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905854 */     // MIs[0] abid
     /*  905854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905857 */     // MIs[0] blgp
     /*  905857 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905860 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64),
     /*  905863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905865 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905867 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905869 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905871 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905873 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905875 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905877 */     GIR_RootConstrainSelectedInstOperands,
     /*  905878 */     // GIR_Coverage, 3382,
     /*  905878 */     GIR_EraseRootFromParent_Done,
     /*  905879 */   // Label 14514: @905879
     /*  905879 */   GIM_Try, /*On fail goto*//*Label 14515*/ GIMT_Encode4(905936), // Rule ID 3383 //
     /*  905884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  905887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
     /*  905892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  905895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  905898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  905901 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  905904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  905908 */     // MIs[0] cbsz
     /*  905908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905911 */     // MIs[0] abid
     /*  905911 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905914 */     // MIs[0] blgp
     /*  905914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905917 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3304:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64),
     /*  905920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905922 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905924 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905926 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905928 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905930 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905932 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905934 */     GIR_RootConstrainSelectedInstOperands,
     /*  905935 */     // GIR_Coverage, 3383,
     /*  905935 */     GIR_EraseRootFromParent_Done,
     /*  905936 */   // Label 14515: @905936
     /*  905936 */   GIM_Try, /*On fail goto*//*Label 14516*/ GIMT_Encode4(905993), // Rule ID 3389 //
     /*  905941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  905944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  905949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  905952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  905955 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  905958 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  905961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  905965 */     // MIs[0] cbsz
     /*  905965 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  905968 */     // MIs[0] abid
     /*  905968 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  905971 */     // MIs[0] blgp
     /*  905971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  905974 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  905974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64),
     /*  905977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  905979 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  905981 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  905983 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  905985 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  905987 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  905989 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  905991 */     GIR_RootConstrainSelectedInstOperands,
     /*  905992 */     // GIR_Coverage, 3389,
     /*  905992 */     GIR_EraseRootFromParent_Done,
     /*  905993 */   // Label 14516: @905993
     /*  905993 */   GIM_Try, /*On fail goto*//*Label 14517*/ GIMT_Encode4(906050), // Rule ID 3390 //
     /*  905998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  906001 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  906006 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906009 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906012 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906015 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906022 */     // MIs[0] cbsz
     /*  906022 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906025 */     // MIs[0] abid
     /*  906025 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906028 */     // MIs[0] blgp
     /*  906028 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906031 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64),
     /*  906034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906036 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906038 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906040 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906042 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906044 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906046 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906048 */     GIR_RootConstrainSelectedInstOperands,
     /*  906049 */     // GIR_Coverage, 3390,
     /*  906049 */     GIR_EraseRootFromParent_Done,
     /*  906050 */   // Label 14517: @906050
     /*  906050 */   GIM_Try, /*On fail goto*//*Label 14518*/ GIMT_Encode4(906107), // Rule ID 3391 //
     /*  906055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  906058 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  906063 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906066 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906069 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906072 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906079 */     // MIs[0] cbsz
     /*  906079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906082 */     // MIs[0] abid
     /*  906082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906085 */     // MIs[0] blgp
     /*  906085 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906088 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64),
     /*  906091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906097 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906099 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906101 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906103 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906105 */     GIR_RootConstrainSelectedInstOperands,
     /*  906106 */     // GIR_Coverage, 3391,
     /*  906106 */     GIR_EraseRootFromParent_Done,
     /*  906107 */   // Label 14518: @906107
     /*  906107 */   GIM_Try, /*On fail goto*//*Label 14519*/ GIMT_Encode4(906164), // Rule ID 3392 //
     /*  906112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  906115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  906120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906129 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906136 */     // MIs[0] cbsz
     /*  906136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906139 */     // MIs[0] abid
     /*  906139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906142 */     // MIs[0] blgp
     /*  906142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906145 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64),
     /*  906148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906150 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906152 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906154 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906156 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906158 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906160 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906162 */     GIR_RootConstrainSelectedInstOperands,
     /*  906163 */     // GIR_Coverage, 3392,
     /*  906163 */     GIR_EraseRootFromParent_Done,
     /*  906164 */   // Label 14519: @906164
     /*  906164 */   GIM_Try, /*On fail goto*//*Label 14520*/ GIMT_Encode4(906221), // Rule ID 3393 //
     /*  906169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  906172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
     /*  906177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906186 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906193 */     // MIs[0] cbsz
     /*  906193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906196 */     // MIs[0] abid
     /*  906196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906199 */     // MIs[0] blgp
     /*  906199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906202 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3314:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64),
     /*  906205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906207 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906209 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906211 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906213 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906215 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906217 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906219 */     GIR_RootConstrainSelectedInstOperands,
     /*  906220 */     // GIR_Coverage, 3393,
     /*  906220 */     GIR_EraseRootFromParent_Done,
     /*  906221 */   // Label 14520: @906221
     /*  906221 */   GIM_Try, /*On fail goto*//*Label 14521*/ GIMT_Encode4(906278), // Rule ID 3396 //
     /*  906226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  906229 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  906234 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906237 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  906240 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  906243 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906250 */     // MIs[0] cbsz
     /*  906250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906253 */     // MIs[0] abid
     /*  906253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906256 */     // MIs[0] blgp
     /*  906256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906259 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64),
     /*  906262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906264 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906266 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906268 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906270 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906272 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906274 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906276 */     GIR_RootConstrainSelectedInstOperands,
     /*  906277 */     // GIR_Coverage, 3396,
     /*  906277 */     GIR_EraseRootFromParent_Done,
     /*  906278 */   // Label 14521: @906278
     /*  906278 */   GIM_Try, /*On fail goto*//*Label 14522*/ GIMT_Encode4(906335), // Rule ID 3397 //
     /*  906283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  906286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  906291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  906297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  906300 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906307 */     // MIs[0] cbsz
     /*  906307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906310 */     // MIs[0] abid
     /*  906310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906313 */     // MIs[0] blgp
     /*  906313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906316 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64),
     /*  906319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906321 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906323 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906325 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906327 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906329 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906331 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906333 */     GIR_RootConstrainSelectedInstOperands,
     /*  906334 */     // GIR_Coverage, 3397,
     /*  906334 */     GIR_EraseRootFromParent_Done,
     /*  906335 */   // Label 14522: @906335
     /*  906335 */   GIM_Try, /*On fail goto*//*Label 14523*/ GIMT_Encode4(906392), // Rule ID 3398 //
     /*  906340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  906343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  906348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  906354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  906357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906364 */     // MIs[0] cbsz
     /*  906364 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906367 */     // MIs[0] abid
     /*  906367 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906370 */     // MIs[0] blgp
     /*  906370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906373 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64),
     /*  906376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906378 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906380 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906382 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906384 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906386 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906388 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906390 */     GIR_RootConstrainSelectedInstOperands,
     /*  906391 */     // GIR_Coverage, 3398,
     /*  906391 */     GIR_EraseRootFromParent_Done,
     /*  906392 */   // Label 14523: @906392
     /*  906392 */   GIM_Try, /*On fail goto*//*Label 14524*/ GIMT_Encode4(906449), // Rule ID 3399 //
     /*  906397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  906400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  906405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  906411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  906414 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906421 */     // MIs[0] cbsz
     /*  906421 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906424 */     // MIs[0] abid
     /*  906424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906427 */     // MIs[0] blgp
     /*  906427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906430 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64),
     /*  906433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906437 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906439 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906441 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906443 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906445 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906447 */     GIR_RootConstrainSelectedInstOperands,
     /*  906448 */     // GIR_Coverage, 3399,
     /*  906448 */     GIR_EraseRootFromParent_Done,
     /*  906449 */   // Label 14524: @906449
     /*  906449 */   GIM_Try, /*On fail goto*//*Label 14525*/ GIMT_Encode4(906506), // Rule ID 3400 //
     /*  906454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  906457 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
     /*  906462 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906465 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  906468 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  906471 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906478 */     // MIs[0] cbsz
     /*  906478 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906481 */     // MIs[0] abid
     /*  906481 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906484 */     // MIs[0] blgp
     /*  906484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906487 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3325:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64),
     /*  906490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906492 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906494 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906496 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906498 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906500 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906502 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906504 */     GIR_RootConstrainSelectedInstOperands,
     /*  906505 */     // GIR_Coverage, 3400,
     /*  906505 */     GIR_EraseRootFromParent_Done,
     /*  906506 */   // Label 14525: @906506
     /*  906506 */   GIM_Try, /*On fail goto*//*Label 14526*/ GIMT_Encode4(906563), // Rule ID 3406 //
     /*  906511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  906514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  906519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  906522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906525 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906528 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  906531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  906535 */     // MIs[0] cbsz
     /*  906535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906538 */     // MIs[0] abid
     /*  906538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906541 */     // MIs[0] blgp
     /*  906541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906544 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64),
     /*  906547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906549 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906551 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906553 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906555 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906557 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906559 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906561 */     GIR_RootConstrainSelectedInstOperands,
     /*  906562 */     // GIR_Coverage, 3406,
     /*  906562 */     GIR_EraseRootFromParent_Done,
     /*  906563 */   // Label 14526: @906563
     /*  906563 */   GIM_Try, /*On fail goto*//*Label 14527*/ GIMT_Encode4(906620), // Rule ID 3407 //
     /*  906568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  906571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  906576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  906579 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906582 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906585 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  906588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  906592 */     // MIs[0] cbsz
     /*  906592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906595 */     // MIs[0] abid
     /*  906595 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906598 */     // MIs[0] blgp
     /*  906598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906601 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64),
     /*  906604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906606 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906608 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906610 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906612 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906614 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906616 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906618 */     GIR_RootConstrainSelectedInstOperands,
     /*  906619 */     // GIR_Coverage, 3407,
     /*  906619 */     GIR_EraseRootFromParent_Done,
     /*  906620 */   // Label 14527: @906620
     /*  906620 */   GIM_Try, /*On fail goto*//*Label 14528*/ GIMT_Encode4(906677), // Rule ID 3408 //
     /*  906625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  906628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  906633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  906636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906639 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906642 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  906645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  906649 */     // MIs[0] cbsz
     /*  906649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906652 */     // MIs[0] abid
     /*  906652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906655 */     // MIs[0] blgp
     /*  906655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906658 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64),
     /*  906661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906663 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906665 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906667 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906669 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906671 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906673 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906675 */     GIR_RootConstrainSelectedInstOperands,
     /*  906676 */     // GIR_Coverage, 3408,
     /*  906676 */     GIR_EraseRootFromParent_Done,
     /*  906677 */   // Label 14528: @906677
     /*  906677 */   GIM_Try, /*On fail goto*//*Label 14529*/ GIMT_Encode4(906734), // Rule ID 3409 //
     /*  906682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  906685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  906690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  906693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906699 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  906702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  906706 */     // MIs[0] cbsz
     /*  906706 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906709 */     // MIs[0] abid
     /*  906709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906712 */     // MIs[0] blgp
     /*  906712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906715 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64),
     /*  906718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906720 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906722 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906724 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906726 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906728 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906730 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906732 */     GIR_RootConstrainSelectedInstOperands,
     /*  906733 */     // GIR_Coverage, 3409,
     /*  906733 */     GIR_EraseRootFromParent_Done,
     /*  906734 */   // Label 14529: @906734
     /*  906734 */   GIM_Try, /*On fail goto*//*Label 14530*/ GIMT_Encode4(906791), // Rule ID 3410 //
     /*  906739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  906742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
     /*  906747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  906750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906756 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  906759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  906763 */     // MIs[0] cbsz
     /*  906763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906766 */     // MIs[0] abid
     /*  906766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906769 */     // MIs[0] blgp
     /*  906769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906772 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3292:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64),
     /*  906775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906777 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906781 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906783 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906785 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906787 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906789 */     GIR_RootConstrainSelectedInstOperands,
     /*  906790 */     // GIR_Coverage, 3410,
     /*  906790 */     GIR_EraseRootFromParent_Done,
     /*  906791 */   // Label 14530: @906791
     /*  906791 */   GIM_Try, /*On fail goto*//*Label 14531*/ GIMT_Encode4(906848), // Rule ID 3416 //
     /*  906796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  906799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  906804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906813 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906820 */     // MIs[0] cbsz
     /*  906820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906823 */     // MIs[0] abid
     /*  906823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906826 */     // MIs[0] blgp
     /*  906826 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906829 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64),
     /*  906832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906834 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906836 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906838 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906840 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906842 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906844 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906846 */     GIR_RootConstrainSelectedInstOperands,
     /*  906847 */     // GIR_Coverage, 3416,
     /*  906847 */     GIR_EraseRootFromParent_Done,
     /*  906848 */   // Label 14531: @906848
     /*  906848 */   GIM_Try, /*On fail goto*//*Label 14532*/ GIMT_Encode4(906905), // Rule ID 3417 //
     /*  906853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  906856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  906861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906870 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906877 */     // MIs[0] cbsz
     /*  906877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906880 */     // MIs[0] abid
     /*  906880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906883 */     // MIs[0] blgp
     /*  906883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906886 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64),
     /*  906889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906891 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906893 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906895 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906897 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906899 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906901 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906903 */     GIR_RootConstrainSelectedInstOperands,
     /*  906904 */     // GIR_Coverage, 3417,
     /*  906904 */     GIR_EraseRootFromParent_Done,
     /*  906905 */   // Label 14532: @906905
     /*  906905 */   GIM_Try, /*On fail goto*//*Label 14533*/ GIMT_Encode4(906962), // Rule ID 3418 //
     /*  906910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  906913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  906918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906927 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906934 */     // MIs[0] cbsz
     /*  906934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906937 */     // MIs[0] abid
     /*  906937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906940 */     // MIs[0] blgp
     /*  906940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  906943 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  906943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64),
     /*  906946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  906948 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  906950 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  906952 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  906954 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  906956 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  906958 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  906960 */     GIR_RootConstrainSelectedInstOperands,
     /*  906961 */     // GIR_Coverage, 3418,
     /*  906961 */     GIR_EraseRootFromParent_Done,
     /*  906962 */   // Label 14533: @906962
     /*  906962 */   GIM_Try, /*On fail goto*//*Label 14534*/ GIMT_Encode4(907019), // Rule ID 3419 //
     /*  906967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  906970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  906975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  906978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  906981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  906984 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  906987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  906991 */     // MIs[0] cbsz
     /*  906991 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  906994 */     // MIs[0] abid
     /*  906994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  906997 */     // MIs[0] blgp
     /*  906997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907000 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64),
     /*  907003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907005 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907007 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907009 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907011 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907013 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907015 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907017 */     GIR_RootConstrainSelectedInstOperands,
     /*  907018 */     // GIR_Coverage, 3419,
     /*  907018 */     GIR_EraseRootFromParent_Done,
     /*  907019 */   // Label 14534: @907019
     /*  907019 */   GIM_Try, /*On fail goto*//*Label 14535*/ GIMT_Encode4(907076), // Rule ID 3420 //
     /*  907024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  907027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
     /*  907032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  907035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907041 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  907044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  907048 */     // MIs[0] cbsz
     /*  907048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907051 */     // MIs[0] abid
     /*  907051 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907054 */     // MIs[0] blgp
     /*  907054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907057 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3282:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64),
     /*  907060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907062 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907064 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907066 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907068 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907070 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907072 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907074 */     GIR_RootConstrainSelectedInstOperands,
     /*  907075 */     // GIR_Coverage, 3420,
     /*  907075 */     GIR_EraseRootFromParent_Done,
     /*  907076 */   // Label 14535: @907076
     /*  907076 */   GIM_Try, /*On fail goto*//*Label 14536*/ GIMT_Encode4(907133), // Rule ID 3423 //
     /*  907081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  907084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  907089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  907095 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  907098 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907105 */     // MIs[0] cbsz
     /*  907105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907108 */     // MIs[0] abid
     /*  907108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907111 */     // MIs[0] blgp
     /*  907111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907114 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64),
     /*  907117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907119 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907121 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907123 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907125 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907127 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907129 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907131 */     GIR_RootConstrainSelectedInstOperands,
     /*  907132 */     // GIR_Coverage, 3423,
     /*  907132 */     GIR_EraseRootFromParent_Done,
     /*  907133 */   // Label 14536: @907133
     /*  907133 */   GIM_Try, /*On fail goto*//*Label 14537*/ GIMT_Encode4(907190), // Rule ID 3424 //
     /*  907138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  907141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  907146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  907152 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  907155 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907162 */     // MIs[0] cbsz
     /*  907162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907165 */     // MIs[0] abid
     /*  907165 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907168 */     // MIs[0] blgp
     /*  907168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907171 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64),
     /*  907174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907176 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907178 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907180 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907182 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907184 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907186 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907188 */     GIR_RootConstrainSelectedInstOperands,
     /*  907189 */     // GIR_Coverage, 3424,
     /*  907189 */     GIR_EraseRootFromParent_Done,
     /*  907190 */   // Label 14537: @907190
     /*  907190 */   GIM_Try, /*On fail goto*//*Label 14538*/ GIMT_Encode4(907247), // Rule ID 3425 //
     /*  907195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  907198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  907203 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907206 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  907209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  907212 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907219 */     // MIs[0] cbsz
     /*  907219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907222 */     // MIs[0] abid
     /*  907222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907225 */     // MIs[0] blgp
     /*  907225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907228 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64),
     /*  907231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907233 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907235 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907237 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907239 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907241 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907243 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907245 */     GIR_RootConstrainSelectedInstOperands,
     /*  907246 */     // GIR_Coverage, 3425,
     /*  907246 */     GIR_EraseRootFromParent_Done,
     /*  907247 */   // Label 14538: @907247
     /*  907247 */   GIM_Try, /*On fail goto*//*Label 14539*/ GIMT_Encode4(907304), // Rule ID 3426 //
     /*  907252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  907255 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  907260 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907263 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  907266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  907269 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907276 */     // MIs[0] cbsz
     /*  907276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907279 */     // MIs[0] abid
     /*  907279 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907282 */     // MIs[0] blgp
     /*  907282 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907285 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64),
     /*  907288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907290 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907292 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907294 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907296 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907298 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907300 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907302 */     GIR_RootConstrainSelectedInstOperands,
     /*  907303 */     // GIR_Coverage, 3426,
     /*  907303 */     GIR_EraseRootFromParent_Done,
     /*  907304 */   // Label 14539: @907304
     /*  907304 */   GIM_Try, /*On fail goto*//*Label 14540*/ GIMT_Encode4(907361), // Rule ID 3427 //
     /*  907309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  907312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
     /*  907317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  907323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  907326 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907333 */     // MIs[0] cbsz
     /*  907333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907336 */     // MIs[0] abid
     /*  907336 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907339 */     // MIs[0] blgp
     /*  907339 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907342 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3319:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64),
     /*  907345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907347 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907349 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907351 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907353 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907355 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907357 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907359 */     GIR_RootConstrainSelectedInstOperands,
     /*  907360 */     // GIR_Coverage, 3427,
     /*  907360 */     GIR_EraseRootFromParent_Done,
     /*  907361 */   // Label 14540: @907361
     /*  907361 */   GIM_Try, /*On fail goto*//*Label 14541*/ GIMT_Encode4(907418), // Rule ID 3433 //
     /*  907366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  907369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  907374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  907377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  907386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  907390 */     // MIs[0] cbsz
     /*  907390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907393 */     // MIs[0] abid
     /*  907393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907396 */     // MIs[0] blgp
     /*  907396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907399 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64),
     /*  907402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907404 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907406 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907408 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907410 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907412 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907414 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907416 */     GIR_RootConstrainSelectedInstOperands,
     /*  907417 */     // GIR_Coverage, 3433,
     /*  907417 */     GIR_EraseRootFromParent_Done,
     /*  907418 */   // Label 14541: @907418
     /*  907418 */   GIM_Try, /*On fail goto*//*Label 14542*/ GIMT_Encode4(907475), // Rule ID 3434 //
     /*  907423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  907426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  907431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  907434 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907440 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  907443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  907447 */     // MIs[0] cbsz
     /*  907447 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907450 */     // MIs[0] abid
     /*  907450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907453 */     // MIs[0] blgp
     /*  907453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907456 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64),
     /*  907459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907461 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907463 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907465 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907467 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907469 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907471 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907473 */     GIR_RootConstrainSelectedInstOperands,
     /*  907474 */     // GIR_Coverage, 3434,
     /*  907474 */     GIR_EraseRootFromParent_Done,
     /*  907475 */   // Label 14542: @907475
     /*  907475 */   GIM_Try, /*On fail goto*//*Label 14543*/ GIMT_Encode4(907532), // Rule ID 3435 //
     /*  907480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  907483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  907488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  907491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907497 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  907500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  907504 */     // MIs[0] cbsz
     /*  907504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907507 */     // MIs[0] abid
     /*  907507 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907510 */     // MIs[0] blgp
     /*  907510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907513 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64),
     /*  907516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907518 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907520 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907522 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907524 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907526 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907528 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907530 */     GIR_RootConstrainSelectedInstOperands,
     /*  907531 */     // GIR_Coverage, 3435,
     /*  907531 */     GIR_EraseRootFromParent_Done,
     /*  907532 */   // Label 14543: @907532
     /*  907532 */   GIM_Try, /*On fail goto*//*Label 14544*/ GIMT_Encode4(907589), // Rule ID 3436 //
     /*  907537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  907540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  907545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  907548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907554 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  907557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  907561 */     // MIs[0] cbsz
     /*  907561 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907564 */     // MIs[0] abid
     /*  907564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907567 */     // MIs[0] blgp
     /*  907567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907570 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64),
     /*  907573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907575 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907577 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907579 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907581 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907583 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907585 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907587 */     GIR_RootConstrainSelectedInstOperands,
     /*  907588 */     // GIR_Coverage, 3436,
     /*  907588 */     GIR_EraseRootFromParent_Done,
     /*  907589 */   // Label 14544: @907589
     /*  907589 */   GIM_Try, /*On fail goto*//*Label 14545*/ GIMT_Encode4(907646), // Rule ID 3437 //
     /*  907594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  907597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
     /*  907602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  907605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907611 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  907614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  907618 */     // MIs[0] cbsz
     /*  907618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907621 */     // MIs[0] abid
     /*  907621 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907624 */     // MIs[0] blgp
     /*  907624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907627 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3308:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64),
     /*  907630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907632 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907634 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907636 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907638 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907640 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907642 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907644 */     GIR_RootConstrainSelectedInstOperands,
     /*  907645 */     // GIR_Coverage, 3437,
     /*  907645 */     GIR_EraseRootFromParent_Done,
     /*  907646 */   // Label 14545: @907646
     /*  907646 */   GIM_Try, /*On fail goto*//*Label 14546*/ GIMT_Encode4(907703), // Rule ID 3443 //
     /*  907651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  907654 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  907659 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907668 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907675 */     // MIs[0] cbsz
     /*  907675 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907678 */     // MIs[0] abid
     /*  907678 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907681 */     // MIs[0] blgp
     /*  907681 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907684 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64),
     /*  907687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907689 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907691 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907693 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907695 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907697 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907699 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907701 */     GIR_RootConstrainSelectedInstOperands,
     /*  907702 */     // GIR_Coverage, 3443,
     /*  907702 */     GIR_EraseRootFromParent_Done,
     /*  907703 */   // Label 14546: @907703
     /*  907703 */   GIM_Try, /*On fail goto*//*Label 14547*/ GIMT_Encode4(907760), // Rule ID 3444 //
     /*  907708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  907711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  907716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907725 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907732 */     // MIs[0] cbsz
     /*  907732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907735 */     // MIs[0] abid
     /*  907735 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907738 */     // MIs[0] blgp
     /*  907738 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907741 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64),
     /*  907744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907746 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907748 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907750 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907752 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907754 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907756 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907758 */     GIR_RootConstrainSelectedInstOperands,
     /*  907759 */     // GIR_Coverage, 3444,
     /*  907759 */     GIR_EraseRootFromParent_Done,
     /*  907760 */   // Label 14547: @907760
     /*  907760 */   GIM_Try, /*On fail goto*//*Label 14548*/ GIMT_Encode4(907817), // Rule ID 3445 //
     /*  907765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  907768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  907773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907782 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907789 */     // MIs[0] cbsz
     /*  907789 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907792 */     // MIs[0] abid
     /*  907792 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907795 */     // MIs[0] blgp
     /*  907795 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907798 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64),
     /*  907801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907803 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907805 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907807 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907809 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907811 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907813 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907815 */     GIR_RootConstrainSelectedInstOperands,
     /*  907816 */     // GIR_Coverage, 3445,
     /*  907816 */     GIR_EraseRootFromParent_Done,
     /*  907817 */   // Label 14548: @907817
     /*  907817 */   GIM_Try, /*On fail goto*//*Label 14549*/ GIMT_Encode4(907874), // Rule ID 3446 //
     /*  907822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  907825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  907830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907836 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907839 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907846 */     // MIs[0] cbsz
     /*  907846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907849 */     // MIs[0] abid
     /*  907849 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907852 */     // MIs[0] blgp
     /*  907852 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907855 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64),
     /*  907858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907860 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907862 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907864 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907866 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907868 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907870 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907872 */     GIR_RootConstrainSelectedInstOperands,
     /*  907873 */     // GIR_Coverage, 3446,
     /*  907873 */     GIR_EraseRootFromParent_Done,
     /*  907874 */   // Label 14549: @907874
     /*  907874 */   GIM_Try, /*On fail goto*//*Label 14550*/ GIMT_Encode4(907931), // Rule ID 3447 //
     /*  907879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  907882 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
     /*  907887 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  907890 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  907893 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  907896 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  907899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  907903 */     // MIs[0] cbsz
     /*  907903 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907906 */     // MIs[0] abid
     /*  907906 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907909 */     // MIs[0] blgp
     /*  907909 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907912 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3310:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64),
     /*  907915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907917 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907919 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907921 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907923 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907925 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907927 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907929 */     GIR_RootConstrainSelectedInstOperands,
     /*  907930 */     // GIR_Coverage, 3447,
     /*  907930 */     GIR_EraseRootFromParent_Done,
     /*  907931 */   // Label 14550: @907931
     /*  907931 */   GIM_Try, /*On fail goto*//*Label 14551*/ GIMT_Encode4(907988), // Rule ID 3450 //
     /*  907936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode0),
     /*  907939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  907944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  907947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  907950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  907953 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  907956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  907960 */     // MIs[0] cbsz
     /*  907960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  907963 */     // MIs[0] abid
     /*  907963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  907966 */     // MIs[0] blgp
     /*  907966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  907969 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  907969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64),
     /*  907972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  907974 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  907976 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  907978 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  907980 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  907982 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  907984 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  907986 */     GIR_RootConstrainSelectedInstOperands,
     /*  907987 */     // GIR_Coverage, 3450,
     /*  907987 */     GIR_EraseRootFromParent_Done,
     /*  907988 */   // Label 14551: @907988
     /*  907988 */   GIM_Try, /*On fail goto*//*Label 14552*/ GIMT_Encode4(908045), // Rule ID 3451 //
     /*  907993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode1),
     /*  907996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  908001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  908004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908010 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  908013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  908017 */     // MIs[0] cbsz
     /*  908017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908020 */     // MIs[0] abid
     /*  908020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908023 */     // MIs[0] blgp
     /*  908023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908026 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64),
     /*  908029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908031 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908033 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908035 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908037 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908039 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908041 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908043 */     GIR_RootConstrainSelectedInstOperands,
     /*  908044 */     // GIR_Coverage, 3451,
     /*  908044 */     GIR_EraseRootFromParent_Done,
     /*  908045 */   // Label 14552: @908045
     /*  908045 */   GIM_Try, /*On fail goto*//*Label 14553*/ GIMT_Encode4(908102), // Rule ID 3452 //
     /*  908050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode2),
     /*  908053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  908058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  908061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  908070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  908074 */     // MIs[0] cbsz
     /*  908074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908077 */     // MIs[0] abid
     /*  908077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908080 */     // MIs[0] blgp
     /*  908080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908083 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64),
     /*  908086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908088 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908090 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908092 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908094 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908096 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908098 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908100 */     GIR_RootConstrainSelectedInstOperands,
     /*  908101 */     // GIR_Coverage, 3452,
     /*  908101 */     GIR_EraseRootFromParent_Done,
     /*  908102 */   // Label 14553: @908102
     /*  908102 */   GIM_Try, /*On fail goto*//*Label 14554*/ GIMT_Encode4(908159), // Rule ID 3453 //
     /*  908107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode3),
     /*  908110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  908115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  908118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908121 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908124 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  908127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  908131 */     // MIs[0] cbsz
     /*  908131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908134 */     // MIs[0] abid
     /*  908134 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908137 */     // MIs[0] blgp
     /*  908137 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908140 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64),
     /*  908143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908145 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908147 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908149 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908151 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908153 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908155 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908157 */     GIR_RootConstrainSelectedInstOperands,
     /*  908158 */     // GIR_Coverage, 3453,
     /*  908158 */     GIR_EraseRootFromParent_Done,
     /*  908159 */   // Label 14554: @908159
     /*  908159 */   GIM_Try, /*On fail goto*//*Label 14555*/ GIMT_Encode4(908216), // Rule ID 3454 //
     /*  908164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts_isGFX90APlus_HwMode4),
     /*  908167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
     /*  908172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  908175 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908178 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908181 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  908184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  908188 */     // MIs[0] cbsz
     /*  908188 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908191 */     // MIs[0] abid
     /*  908191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908194 */     // MIs[0] blgp
     /*  908194 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908197 */     // (intrinsic_wo_chain:{ *:[v32i32] } 3323:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64),
     /*  908200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908202 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908204 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908206 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908208 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908210 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908212 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908214 */     GIR_RootConstrainSelectedInstOperands,
     /*  908215 */     // GIR_Coverage, 3454,
     /*  908215 */     GIR_EraseRootFromParent_Done,
     /*  908216 */   // Label 14555: @908216
     /*  908216 */   GIM_Try, /*On fail goto*//*Label 14556*/ GIMT_Encode4(908273), // Rule ID 3457 //
     /*  908221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  908224 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  908229 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908232 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908235 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908238 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908245 */     // MIs[0] cbsz
     /*  908245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908248 */     // MIs[0] abid
     /*  908248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908251 */     // MIs[0] blgp
     /*  908251 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908254 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64),
     /*  908257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908259 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908261 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908263 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908265 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908267 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908269 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908271 */     GIR_RootConstrainSelectedInstOperands,
     /*  908272 */     // GIR_Coverage, 3457,
     /*  908272 */     GIR_EraseRootFromParent_Done,
     /*  908273 */   // Label 14556: @908273
     /*  908273 */   GIM_Try, /*On fail goto*//*Label 14557*/ GIMT_Encode4(908330), // Rule ID 3458 //
     /*  908278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  908281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  908286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908295 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908302 */     // MIs[0] cbsz
     /*  908302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908305 */     // MIs[0] abid
     /*  908305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908308 */     // MIs[0] blgp
     /*  908308 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908311 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64),
     /*  908314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908316 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908318 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908320 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908322 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908324 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908326 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908328 */     GIR_RootConstrainSelectedInstOperands,
     /*  908329 */     // GIR_Coverage, 3458,
     /*  908329 */     GIR_EraseRootFromParent_Done,
     /*  908330 */   // Label 14557: @908330
     /*  908330 */   GIM_Try, /*On fail goto*//*Label 14558*/ GIMT_Encode4(908387), // Rule ID 3459 //
     /*  908335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  908338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  908343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908346 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908349 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908352 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908359 */     // MIs[0] cbsz
     /*  908359 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908362 */     // MIs[0] abid
     /*  908362 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908365 */     // MIs[0] blgp
     /*  908365 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908368 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64),
     /*  908371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908373 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908375 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908377 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908379 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908381 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908383 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908385 */     GIR_RootConstrainSelectedInstOperands,
     /*  908386 */     // GIR_Coverage, 3459,
     /*  908386 */     GIR_EraseRootFromParent_Done,
     /*  908387 */   // Label 14558: @908387
     /*  908387 */   GIM_Try, /*On fail goto*//*Label 14559*/ GIMT_Encode4(908444), // Rule ID 3460 //
     /*  908392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  908395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  908400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908416 */     // MIs[0] cbsz
     /*  908416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908419 */     // MIs[0] abid
     /*  908419 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908422 */     // MIs[0] blgp
     /*  908422 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908425 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64),
     /*  908428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908430 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908432 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908434 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908436 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908438 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908440 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908442 */     GIR_RootConstrainSelectedInstOperands,
     /*  908443 */     // GIR_Coverage, 3460,
     /*  908443 */     GIR_EraseRootFromParent_Done,
     /*  908444 */   // Label 14559: @908444
     /*  908444 */   GIM_Try, /*On fail goto*//*Label 14560*/ GIMT_Encode4(908501), // Rule ID 3461 //
     /*  908449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  908452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
     /*  908457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908466 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908473 */     // MIs[0] cbsz
     /*  908473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908476 */     // MIs[0] abid
     /*  908476 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908479 */     // MIs[0] blgp
     /*  908479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908482 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3317:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64),
     /*  908485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908487 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908489 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908491 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908493 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908495 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908497 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908499 */     GIR_RootConstrainSelectedInstOperands,
     /*  908500 */     // GIR_Coverage, 3461,
     /*  908500 */     GIR_EraseRootFromParent_Done,
     /*  908501 */   // Label 14560: @908501
     /*  908501 */   GIM_Try, /*On fail goto*//*Label 14561*/ GIMT_Encode4(908558), // Rule ID 3464 //
     /*  908506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  908509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  908514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  908517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908523 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  908526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  908530 */     // MIs[0] cbsz
     /*  908530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908533 */     // MIs[0] abid
     /*  908533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908536 */     // MIs[0] blgp
     /*  908536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908539 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64),
     /*  908542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908544 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908546 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908548 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908550 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908552 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908554 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908556 */     GIR_RootConstrainSelectedInstOperands,
     /*  908557 */     // GIR_Coverage, 3464,
     /*  908557 */     GIR_EraseRootFromParent_Done,
     /*  908558 */   // Label 14561: @908558
     /*  908558 */   GIM_Try, /*On fail goto*//*Label 14562*/ GIMT_Encode4(908615), // Rule ID 3465 //
     /*  908563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  908566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  908571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  908574 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908577 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908580 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  908583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  908587 */     // MIs[0] cbsz
     /*  908587 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908590 */     // MIs[0] abid
     /*  908590 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908593 */     // MIs[0] blgp
     /*  908593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908596 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64),
     /*  908599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908601 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908603 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908605 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908607 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908609 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908611 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908613 */     GIR_RootConstrainSelectedInstOperands,
     /*  908614 */     // GIR_Coverage, 3465,
     /*  908614 */     GIR_EraseRootFromParent_Done,
     /*  908615 */   // Label 14562: @908615
     /*  908615 */   GIM_Try, /*On fail goto*//*Label 14563*/ GIMT_Encode4(908672), // Rule ID 3466 //
     /*  908620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  908623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  908628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  908631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  908640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  908644 */     // MIs[0] cbsz
     /*  908644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908647 */     // MIs[0] abid
     /*  908647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908650 */     // MIs[0] blgp
     /*  908650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908653 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64),
     /*  908656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908658 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908660 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908662 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908664 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908666 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908668 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908670 */     GIR_RootConstrainSelectedInstOperands,
     /*  908671 */     // GIR_Coverage, 3466,
     /*  908671 */     GIR_EraseRootFromParent_Done,
     /*  908672 */   // Label 14563: @908672
     /*  908672 */   GIM_Try, /*On fail goto*//*Label 14564*/ GIMT_Encode4(908729), // Rule ID 3467 //
     /*  908677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  908680 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  908685 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  908688 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908691 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908694 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  908697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  908701 */     // MIs[0] cbsz
     /*  908701 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908704 */     // MIs[0] abid
     /*  908704 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908707 */     // MIs[0] blgp
     /*  908707 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908710 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64),
     /*  908713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908715 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908717 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908719 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908721 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908723 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908725 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908727 */     GIR_RootConstrainSelectedInstOperands,
     /*  908728 */     // GIR_Coverage, 3467,
     /*  908728 */     GIR_EraseRootFromParent_Done,
     /*  908729 */   // Label 14564: @908729
     /*  908729 */   GIM_Try, /*On fail goto*//*Label 14565*/ GIMT_Encode4(908786), // Rule ID 3468 //
     /*  908734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  908737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
     /*  908742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  908745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  908748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  908751 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  908754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  908758 */     // MIs[0] cbsz
     /*  908758 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908761 */     // MIs[0] abid
     /*  908761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908764 */     // MIs[0] blgp
     /*  908764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908767 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3324:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64),
     /*  908770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908772 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908774 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908776 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908778 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908780 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908782 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908784 */     GIR_RootConstrainSelectedInstOperands,
     /*  908785 */     // GIR_Coverage, 3468,
     /*  908785 */     GIR_EraseRootFromParent_Done,
     /*  908786 */   // Label 14565: @908786
     /*  908786 */   GIM_Try, /*On fail goto*//*Label 14566*/ GIMT_Encode4(908843), // Rule ID 3471 //
     /*  908791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  908794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  908799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  908805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  908808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908815 */     // MIs[0] cbsz
     /*  908815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908818 */     // MIs[0] abid
     /*  908818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908821 */     // MIs[0] blgp
     /*  908821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908824 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64),
     /*  908827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908829 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908831 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908833 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908835 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908837 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908839 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908841 */     GIR_RootConstrainSelectedInstOperands,
     /*  908842 */     // GIR_Coverage, 3471,
     /*  908842 */     GIR_EraseRootFromParent_Done,
     /*  908843 */   // Label 14566: @908843
     /*  908843 */   GIM_Try, /*On fail goto*//*Label 14567*/ GIMT_Encode4(908900), // Rule ID 3472 //
     /*  908848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  908851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  908856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  908862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  908865 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908872 */     // MIs[0] cbsz
     /*  908872 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908875 */     // MIs[0] abid
     /*  908875 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908878 */     // MIs[0] blgp
     /*  908878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908881 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64),
     /*  908884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908886 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908888 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908890 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908892 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908894 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908896 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908898 */     GIR_RootConstrainSelectedInstOperands,
     /*  908899 */     // GIR_Coverage, 3472,
     /*  908899 */     GIR_EraseRootFromParent_Done,
     /*  908900 */   // Label 14567: @908900
     /*  908900 */   GIM_Try, /*On fail goto*//*Label 14568*/ GIMT_Encode4(908957), // Rule ID 3473 //
     /*  908905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  908908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  908913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  908919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  908922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908929 */     // MIs[0] cbsz
     /*  908929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908932 */     // MIs[0] abid
     /*  908932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908935 */     // MIs[0] blgp
     /*  908935 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908938 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64),
     /*  908941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  908943 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  908945 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  908947 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  908949 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  908951 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  908953 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  908955 */     GIR_RootConstrainSelectedInstOperands,
     /*  908956 */     // GIR_Coverage, 3473,
     /*  908956 */     GIR_EraseRootFromParent_Done,
     /*  908957 */   // Label 14568: @908957
     /*  908957 */   GIM_Try, /*On fail goto*//*Label 14569*/ GIMT_Encode4(909014), // Rule ID 3474 //
     /*  908962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  908965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  908970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  908973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  908976 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  908979 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  908982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  908986 */     // MIs[0] cbsz
     /*  908986 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  908989 */     // MIs[0] abid
     /*  908989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  908992 */     // MIs[0] blgp
     /*  908992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  908995 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  908995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64),
     /*  908998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909000 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909002 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909004 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909006 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909008 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909010 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909012 */     GIR_RootConstrainSelectedInstOperands,
     /*  909013 */     // GIR_Coverage, 3474,
     /*  909013 */     GIR_EraseRootFromParent_Done,
     /*  909014 */   // Label 14569: @909014
     /*  909014 */   GIM_Try, /*On fail goto*//*Label 14570*/ GIMT_Encode4(909071), // Rule ID 3475 //
     /*  909019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  909022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
     /*  909027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  909030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909036 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  909039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  909043 */     // MIs[0] cbsz
     /*  909043 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909046 */     // MIs[0] abid
     /*  909046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909049 */     // MIs[0] blgp
     /*  909049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909052 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3312:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64),
     /*  909055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909057 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909059 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909061 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909063 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909065 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909067 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909069 */     GIR_RootConstrainSelectedInstOperands,
     /*  909070 */     // GIR_Coverage, 3475,
     /*  909070 */     GIR_EraseRootFromParent_Done,
     /*  909071 */   // Label 14570: @909071
     /*  909071 */   GIM_Try, /*On fail goto*//*Label 14571*/ GIMT_Encode4(909128), // Rule ID 3478 //
     /*  909076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  909079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  909084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909093 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  909096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  909100 */     // MIs[0] cbsz
     /*  909100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909103 */     // MIs[0] abid
     /*  909103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909106 */     // MIs[0] blgp
     /*  909106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909109 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64),
     /*  909112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909114 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909116 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909118 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909120 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909122 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909124 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909126 */     GIR_RootConstrainSelectedInstOperands,
     /*  909127 */     // GIR_Coverage, 3478,
     /*  909127 */     GIR_EraseRootFromParent_Done,
     /*  909128 */   // Label 14571: @909128
     /*  909128 */   GIM_Try, /*On fail goto*//*Label 14572*/ GIMT_Encode4(909185), // Rule ID 3479 //
     /*  909133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  909136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  909141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909147 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909150 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  909153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  909157 */     // MIs[0] cbsz
     /*  909157 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909160 */     // MIs[0] abid
     /*  909160 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909163 */     // MIs[0] blgp
     /*  909163 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909166 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64),
     /*  909169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909171 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909173 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909175 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909177 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909179 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909181 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909183 */     GIR_RootConstrainSelectedInstOperands,
     /*  909184 */     // GIR_Coverage, 3479,
     /*  909184 */     GIR_EraseRootFromParent_Done,
     /*  909185 */   // Label 14572: @909185
     /*  909185 */   GIM_Try, /*On fail goto*//*Label 14573*/ GIMT_Encode4(909242), // Rule ID 3480 //
     /*  909190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  909193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  909198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  909210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  909214 */     // MIs[0] cbsz
     /*  909214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909217 */     // MIs[0] abid
     /*  909217 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909220 */     // MIs[0] blgp
     /*  909220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909223 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64),
     /*  909226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909228 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909230 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909232 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909234 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909236 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909238 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909240 */     GIR_RootConstrainSelectedInstOperands,
     /*  909241 */     // GIR_Coverage, 3480,
     /*  909241 */     GIR_EraseRootFromParent_Done,
     /*  909242 */   // Label 14573: @909242
     /*  909242 */   GIM_Try, /*On fail goto*//*Label 14574*/ GIMT_Encode4(909299), // Rule ID 3481 //
     /*  909247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  909250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  909255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909264 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  909267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  909271 */     // MIs[0] cbsz
     /*  909271 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909274 */     // MIs[0] abid
     /*  909274 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909277 */     // MIs[0] blgp
     /*  909277 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909280 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64),
     /*  909283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909285 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909287 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909289 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909291 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909293 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909295 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909297 */     GIR_RootConstrainSelectedInstOperands,
     /*  909298 */     // GIR_Coverage, 3481,
     /*  909298 */     GIR_EraseRootFromParent_Done,
     /*  909299 */   // Label 14574: @909299
     /*  909299 */   GIM_Try, /*On fail goto*//*Label 14575*/ GIMT_Encode4(909356), // Rule ID 3482 //
     /*  909304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  909307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
     /*  909312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909321 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  909324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  909328 */     // MIs[0] cbsz
     /*  909328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909331 */     // MIs[0] abid
     /*  909331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909334 */     // MIs[0] blgp
     /*  909334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909337 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3284:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64),
     /*  909340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909342 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909344 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909346 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909348 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909350 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909352 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909354 */     GIR_RootConstrainSelectedInstOperands,
     /*  909355 */     // GIR_Coverage, 3482,
     /*  909355 */     GIR_EraseRootFromParent_Done,
     /*  909356 */   // Label 14575: @909356
     /*  909356 */   GIM_Try, /*On fail goto*//*Label 14576*/ GIMT_Encode4(909413), // Rule ID 3485 //
     /*  909361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  909364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  909369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  909372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909378 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  909381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  909385 */     // MIs[0] cbsz
     /*  909385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909388 */     // MIs[0] abid
     /*  909388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909391 */     // MIs[0] blgp
     /*  909391 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909394 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64),
     /*  909397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909399 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909401 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909403 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909405 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909407 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909409 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909411 */     GIR_RootConstrainSelectedInstOperands,
     /*  909412 */     // GIR_Coverage, 3485,
     /*  909412 */     GIR_EraseRootFromParent_Done,
     /*  909413 */   // Label 14576: @909413
     /*  909413 */   GIM_Try, /*On fail goto*//*Label 14577*/ GIMT_Encode4(909470), // Rule ID 3486 //
     /*  909418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  909421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  909426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  909429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909435 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  909438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  909442 */     // MIs[0] cbsz
     /*  909442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909445 */     // MIs[0] abid
     /*  909445 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909448 */     // MIs[0] blgp
     /*  909448 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909451 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64),
     /*  909454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909456 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909458 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909460 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909462 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909464 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909466 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909468 */     GIR_RootConstrainSelectedInstOperands,
     /*  909469 */     // GIR_Coverage, 3486,
     /*  909469 */     GIR_EraseRootFromParent_Done,
     /*  909470 */   // Label 14577: @909470
     /*  909470 */   GIM_Try, /*On fail goto*//*Label 14578*/ GIMT_Encode4(909527), // Rule ID 3487 //
     /*  909475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  909478 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  909483 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  909486 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909489 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909492 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  909495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  909499 */     // MIs[0] cbsz
     /*  909499 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909502 */     // MIs[0] abid
     /*  909502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909505 */     // MIs[0] blgp
     /*  909505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909508 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64),
     /*  909511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909513 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909515 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909517 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909519 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909521 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909523 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909525 */     GIR_RootConstrainSelectedInstOperands,
     /*  909526 */     // GIR_Coverage, 3487,
     /*  909526 */     GIR_EraseRootFromParent_Done,
     /*  909527 */   // Label 14578: @909527
     /*  909527 */   GIM_Try, /*On fail goto*//*Label 14579*/ GIMT_Encode4(909584), // Rule ID 3488 //
     /*  909532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  909535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  909540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  909543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909549 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  909552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  909556 */     // MIs[0] cbsz
     /*  909556 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909559 */     // MIs[0] abid
     /*  909559 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909562 */     // MIs[0] blgp
     /*  909562 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909565 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64),
     /*  909568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909570 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909572 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909574 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909576 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909578 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909580 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909582 */     GIR_RootConstrainSelectedInstOperands,
     /*  909583 */     // GIR_Coverage, 3488,
     /*  909583 */     GIR_EraseRootFromParent_Done,
     /*  909584 */   // Label 14579: @909584
     /*  909584 */   GIM_Try, /*On fail goto*//*Label 14580*/ GIMT_Encode4(909641), // Rule ID 3489 //
     /*  909589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  909592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
     /*  909597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  909600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909606 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  909609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  909613 */     // MIs[0] cbsz
     /*  909613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909616 */     // MIs[0] abid
     /*  909616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909619 */     // MIs[0] blgp
     /*  909619 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909622 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3295:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64),
     /*  909625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909627 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909629 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909631 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909633 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909635 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909637 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909639 */     GIR_RootConstrainSelectedInstOperands,
     /*  909640 */     // GIR_Coverage, 3489,
     /*  909640 */     GIR_EraseRootFromParent_Done,
     /*  909641 */   // Label 14580: @909641
     /*  909641 */   GIM_Try, /*On fail goto*//*Label 14581*/ GIMT_Encode4(909698), // Rule ID 3492 //
     /*  909646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  909649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  909654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  909657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909660 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909663 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  909666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  909670 */     // MIs[0] cbsz
     /*  909670 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909673 */     // MIs[0] abid
     /*  909673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909676 */     // MIs[0] blgp
     /*  909676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909679 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64),
     /*  909682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909684 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909686 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909688 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909690 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909692 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909694 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909696 */     GIR_RootConstrainSelectedInstOperands,
     /*  909697 */     // GIR_Coverage, 3492,
     /*  909697 */     GIR_EraseRootFromParent_Done,
     /*  909698 */   // Label 14581: @909698
     /*  909698 */   GIM_Try, /*On fail goto*//*Label 14582*/ GIMT_Encode4(909755), // Rule ID 3493 //
     /*  909703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  909706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  909711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  909714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909720 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  909723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  909727 */     // MIs[0] cbsz
     /*  909727 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909730 */     // MIs[0] abid
     /*  909730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909733 */     // MIs[0] blgp
     /*  909733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909736 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64),
     /*  909739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909741 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909743 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909745 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909747 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909749 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909751 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909753 */     GIR_RootConstrainSelectedInstOperands,
     /*  909754 */     // GIR_Coverage, 3493,
     /*  909754 */     GIR_EraseRootFromParent_Done,
     /*  909755 */   // Label 14582: @909755
     /*  909755 */   GIM_Try, /*On fail goto*//*Label 14583*/ GIMT_Encode4(909812), // Rule ID 3494 //
     /*  909760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  909763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  909768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  909771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  909780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  909784 */     // MIs[0] cbsz
     /*  909784 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909787 */     // MIs[0] abid
     /*  909787 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909790 */     // MIs[0] blgp
     /*  909790 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909793 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64),
     /*  909796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909798 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909800 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909802 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909804 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909806 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909808 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909810 */     GIR_RootConstrainSelectedInstOperands,
     /*  909811 */     // GIR_Coverage, 3494,
     /*  909811 */     GIR_EraseRootFromParent_Done,
     /*  909812 */   // Label 14583: @909812
     /*  909812 */   GIM_Try, /*On fail goto*//*Label 14584*/ GIMT_Encode4(909869), // Rule ID 3495 //
     /*  909817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  909820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  909825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  909828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909831 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909834 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  909837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  909841 */     // MIs[0] cbsz
     /*  909841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909844 */     // MIs[0] abid
     /*  909844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909847 */     // MIs[0] blgp
     /*  909847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909850 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64),
     /*  909853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909855 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909857 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909859 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909861 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909863 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909865 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909867 */     GIR_RootConstrainSelectedInstOperands,
     /*  909868 */     // GIR_Coverage, 3495,
     /*  909868 */     GIR_EraseRootFromParent_Done,
     /*  909869 */   // Label 14584: @909869
     /*  909869 */   GIM_Try, /*On fail goto*//*Label 14585*/ GIMT_Encode4(909926), // Rule ID 3496 //
     /*  909874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  909877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
     /*  909882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  909885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909891 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  909894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  909898 */     // MIs[0] cbsz
     /*  909898 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909901 */     // MIs[0] abid
     /*  909901 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909904 */     // MIs[0] blgp
     /*  909904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909907 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3303:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64),
     /*  909910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909912 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909914 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909916 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909918 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909920 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909922 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909924 */     GIR_RootConstrainSelectedInstOperands,
     /*  909925 */     // GIR_Coverage, 3496,
     /*  909925 */     GIR_EraseRootFromParent_Done,
     /*  909926 */   // Label 14585: @909926
     /*  909926 */   GIM_Try, /*On fail goto*//*Label 14586*/ GIMT_Encode4(909983), // Rule ID 3499 //
     /*  909931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode0),
     /*  909934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  909939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  909945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  909948 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  909951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  909955 */     // MIs[0] cbsz
     /*  909955 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  909958 */     // MIs[0] abid
     /*  909958 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  909961 */     // MIs[0] blgp
     /*  909961 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  909964 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  909964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64),
     /*  909967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  909969 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  909971 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  909973 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  909975 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  909977 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  909979 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  909981 */     GIR_RootConstrainSelectedInstOperands,
     /*  909982 */     // GIR_Coverage, 3499,
     /*  909982 */     GIR_EraseRootFromParent_Done,
     /*  909983 */   // Label 14586: @909983
     /*  909983 */   GIM_Try, /*On fail goto*//*Label 14587*/ GIMT_Encode4(910040), // Rule ID 3500 //
     /*  909988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode1),
     /*  909991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  909996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  909999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  910002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  910005 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910012 */     // MIs[0] cbsz
     /*  910012 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910015 */     // MIs[0] abid
     /*  910015 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910018 */     // MIs[0] blgp
     /*  910018 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910021 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64),
     /*  910024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910026 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910028 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910030 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910032 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910034 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910036 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910038 */     GIR_RootConstrainSelectedInstOperands,
     /*  910039 */     // GIR_Coverage, 3500,
     /*  910039 */     GIR_EraseRootFromParent_Done,
     /*  910040 */   // Label 14587: @910040
     /*  910040 */   GIM_Try, /*On fail goto*//*Label 14588*/ GIMT_Encode4(910097), // Rule ID 3501 //
     /*  910045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode2),
     /*  910048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  910053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  910059 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  910062 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910069 */     // MIs[0] cbsz
     /*  910069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910072 */     // MIs[0] abid
     /*  910072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910075 */     // MIs[0] blgp
     /*  910075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910078 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64),
     /*  910081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910083 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910085 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910087 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910089 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910091 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910093 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910095 */     GIR_RootConstrainSelectedInstOperands,
     /*  910096 */     // GIR_Coverage, 3501,
     /*  910096 */     GIR_EraseRootFromParent_Done,
     /*  910097 */   // Label 14588: @910097
     /*  910097 */   GIM_Try, /*On fail goto*//*Label 14589*/ GIMT_Encode4(910154), // Rule ID 3502 //
     /*  910102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode3),
     /*  910105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  910110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  910116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  910119 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910126 */     // MIs[0] cbsz
     /*  910126 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910129 */     // MIs[0] abid
     /*  910129 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910132 */     // MIs[0] blgp
     /*  910132 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910135 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64),
     /*  910138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910140 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910142 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910144 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910146 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910148 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910150 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910152 */     GIR_RootConstrainSelectedInstOperands,
     /*  910153 */     // GIR_Coverage, 3502,
     /*  910153 */     GIR_EraseRootFromParent_Done,
     /*  910154 */   // Label 14589: @910154
     /*  910154 */   GIM_Try, /*On fail goto*//*Label 14590*/ GIMT_Encode4(910211), // Rule ID 3503 //
     /*  910159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX908orGFX90A_HwMode4),
     /*  910162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
     /*  910167 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910170 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  910173 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /*  910176 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910183 */     // MIs[0] cbsz
     /*  910183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910186 */     // MIs[0] abid
     /*  910186 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910189 */     // MIs[0] blgp
     /*  910189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910192 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3306:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64),
     /*  910195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910197 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910199 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910201 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910203 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910205 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910207 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910209 */     GIR_RootConstrainSelectedInstOperands,
     /*  910210 */     // GIR_Coverage, 3503,
     /*  910210 */     GIR_EraseRootFromParent_Done,
     /*  910211 */   // Label 14590: @910211
     /*  910211 */   GIM_Try, /*On fail goto*//*Label 14591*/ GIMT_Encode4(910268), // Rule ID 3509 //
     /*  910216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  910219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  910224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910233 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910240 */     // MIs[0] cbsz
     /*  910240 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910243 */     // MIs[0] abid
     /*  910243 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910246 */     // MIs[0] blgp
     /*  910246 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910249 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_F16_vgprcd_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_vgprcd_e64),
     /*  910252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910254 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910256 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910258 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910260 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910262 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910264 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910266 */     GIR_RootConstrainSelectedInstOperands,
     /*  910267 */     // GIR_Coverage, 3509,
     /*  910267 */     GIR_EraseRootFromParent_Done,
     /*  910268 */   // Label 14591: @910268
     /*  910268 */   GIM_Try, /*On fail goto*//*Label 14592*/ GIMT_Encode4(910325), // Rule ID 3510 //
     /*  910273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  910276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  910281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910290 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910297 */     // MIs[0] cbsz
     /*  910297 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910300 */     // MIs[0] abid
     /*  910300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910303 */     // MIs[0] blgp
     /*  910303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910306 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_F16_vgprcd_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_vgprcd_e64),
     /*  910309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910311 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910313 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910315 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910317 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910319 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910321 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910323 */     GIR_RootConstrainSelectedInstOperands,
     /*  910324 */     // GIR_Coverage, 3510,
     /*  910324 */     GIR_EraseRootFromParent_Done,
     /*  910325 */   // Label 14592: @910325
     /*  910325 */   GIM_Try, /*On fail goto*//*Label 14593*/ GIMT_Encode4(910382), // Rule ID 3511 //
     /*  910330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  910333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  910338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910354 */     // MIs[0] cbsz
     /*  910354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910357 */     // MIs[0] abid
     /*  910357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910360 */     // MIs[0] blgp
     /*  910360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910363 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_F16_vgprcd_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_vgprcd_e64),
     /*  910366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910368 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910370 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910372 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910374 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910376 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910378 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910380 */     GIR_RootConstrainSelectedInstOperands,
     /*  910381 */     // GIR_Coverage, 3511,
     /*  910381 */     GIR_EraseRootFromParent_Done,
     /*  910382 */   // Label 14593: @910382
     /*  910382 */   GIM_Try, /*On fail goto*//*Label 14594*/ GIMT_Encode4(910439), // Rule ID 3512 //
     /*  910387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  910390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  910395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910398 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910401 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910404 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910411 */     // MIs[0] cbsz
     /*  910411 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910414 */     // MIs[0] abid
     /*  910414 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910417 */     // MIs[0] blgp
     /*  910417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910420 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_F16_vgprcd_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_vgprcd_e64),
     /*  910423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910425 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910427 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910429 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910431 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910433 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910435 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910437 */     GIR_RootConstrainSelectedInstOperands,
     /*  910438 */     // GIR_Coverage, 3512,
     /*  910438 */     GIR_EraseRootFromParent_Done,
     /*  910439 */   // Label 14594: @910439
     /*  910439 */   GIM_Try, /*On fail goto*//*Label 14595*/ GIMT_Encode4(910496), // Rule ID 3513 //
     /*  910444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  910447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_f16),
     /*  910452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910461 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910468 */     // MIs[0] cbsz
     /*  910468 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910471 */     // MIs[0] abid
     /*  910471 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910474 */     // MIs[0] blgp
     /*  910474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910477 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3288:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_F16_vgprcd_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_F16_vgprcd_e64),
     /*  910480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910482 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910484 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910486 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910488 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910490 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910492 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910494 */     GIR_RootConstrainSelectedInstOperands,
     /*  910495 */     // GIR_Coverage, 3513,
     /*  910495 */     GIR_EraseRootFromParent_Done,
     /*  910496 */   // Label 14595: @910496
     /*  910496 */   GIM_Try, /*On fail goto*//*Label 14596*/ GIMT_Encode4(910553), // Rule ID 3519 //
     /*  910501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  910504 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  910509 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910512 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910515 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910518 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910525 */     // MIs[0] cbsz
     /*  910525 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910528 */     // MIs[0] abid
     /*  910528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910531 */     // MIs[0] blgp
     /*  910531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910534 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64),
     /*  910537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910539 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910541 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910543 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910545 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910547 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910549 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910551 */     GIR_RootConstrainSelectedInstOperands,
     /*  910552 */     // GIR_Coverage, 3519,
     /*  910552 */     GIR_EraseRootFromParent_Done,
     /*  910553 */   // Label 14596: @910553
     /*  910553 */   GIM_Try, /*On fail goto*//*Label 14597*/ GIMT_Encode4(910610), // Rule ID 3520 //
     /*  910558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  910561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  910566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910575 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910578 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910582 */     // MIs[0] cbsz
     /*  910582 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910585 */     // MIs[0] abid
     /*  910585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910588 */     // MIs[0] blgp
     /*  910588 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910591 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64),
     /*  910594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910596 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910598 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910600 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910602 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910604 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910606 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910608 */     GIR_RootConstrainSelectedInstOperands,
     /*  910609 */     // GIR_Coverage, 3520,
     /*  910609 */     GIR_EraseRootFromParent_Done,
     /*  910610 */   // Label 14597: @910610
     /*  910610 */   GIM_Try, /*On fail goto*//*Label 14598*/ GIMT_Encode4(910667), // Rule ID 3521 //
     /*  910615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  910618 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  910623 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910626 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910629 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910632 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910639 */     // MIs[0] cbsz
     /*  910639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910642 */     // MIs[0] abid
     /*  910642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910645 */     // MIs[0] blgp
     /*  910645 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910648 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64),
     /*  910651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910653 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910655 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910657 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910659 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910661 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910663 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910665 */     GIR_RootConstrainSelectedInstOperands,
     /*  910666 */     // GIR_Coverage, 3521,
     /*  910666 */     GIR_EraseRootFromParent_Done,
     /*  910667 */   // Label 14598: @910667
     /*  910667 */   GIM_Try, /*On fail goto*//*Label 14599*/ GIMT_Encode4(910724), // Rule ID 3522 //
     /*  910672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  910675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  910680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910689 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910696 */     // MIs[0] cbsz
     /*  910696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910699 */     // MIs[0] abid
     /*  910699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910702 */     // MIs[0] blgp
     /*  910702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910705 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64),
     /*  910708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910710 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910712 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910714 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910716 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910718 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910720 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910722 */     GIR_RootConstrainSelectedInstOperands,
     /*  910723 */     // GIR_Coverage, 3522,
     /*  910723 */     GIR_EraseRootFromParent_Done,
     /*  910724 */   // Label 14599: @910724
     /*  910724 */   GIM_Try, /*On fail goto*//*Label 14600*/ GIMT_Encode4(910781), // Rule ID 3523 //
     /*  910729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  910732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_f16),
     /*  910737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  910740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  910743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  910746 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  910749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  910753 */     // MIs[0] cbsz
     /*  910753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910756 */     // MIs[0] abid
     /*  910756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910759 */     // MIs[0] blgp
     /*  910759 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910762 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3299:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64),
     /*  910765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910767 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910769 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910771 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910773 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910775 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910777 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910779 */     GIR_RootConstrainSelectedInstOperands,
     /*  910780 */     // GIR_Coverage, 3523,
     /*  910780 */     GIR_EraseRootFromParent_Done,
     /*  910781 */   // Label 14600: @910781
     /*  910781 */   GIM_Try, /*On fail goto*//*Label 14601*/ GIMT_Encode4(910838), // Rule ID 3529 //
     /*  910786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  910789 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  910794 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910797 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  910800 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  910803 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910810 */     // MIs[0] cbsz
     /*  910810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910813 */     // MIs[0] abid
     /*  910813 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910816 */     // MIs[0] blgp
     /*  910816 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910819 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X64_I8_vgprcd_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_vgprcd_e64),
     /*  910822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910824 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910826 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910828 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910830 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910832 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910834 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910836 */     GIR_RootConstrainSelectedInstOperands,
     /*  910837 */     // GIR_Coverage, 3529,
     /*  910837 */     GIR_EraseRootFromParent_Done,
     /*  910838 */   // Label 14601: @910838
     /*  910838 */   GIM_Try, /*On fail goto*//*Label 14602*/ GIMT_Encode4(910895), // Rule ID 3530 //
     /*  910843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  910846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  910851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  910857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  910860 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910867 */     // MIs[0] cbsz
     /*  910867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910870 */     // MIs[0] abid
     /*  910870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910873 */     // MIs[0] blgp
     /*  910873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910876 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X64_I8_vgprcd_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_vgprcd_e64),
     /*  910879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910881 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910883 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910885 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910887 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910889 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910891 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910893 */     GIR_RootConstrainSelectedInstOperands,
     /*  910894 */     // GIR_Coverage, 3530,
     /*  910894 */     GIR_EraseRootFromParent_Done,
     /*  910895 */   // Label 14602: @910895
     /*  910895 */   GIM_Try, /*On fail goto*//*Label 14603*/ GIMT_Encode4(910952), // Rule ID 3531 //
     /*  910900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  910903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  910908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  910914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  910917 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910924 */     // MIs[0] cbsz
     /*  910924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910927 */     // MIs[0] abid
     /*  910927 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910930 */     // MIs[0] blgp
     /*  910930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910933 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X64_I8_vgprcd_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_vgprcd_e64),
     /*  910936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910938 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910940 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910942 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  910944 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  910946 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  910948 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  910950 */     GIR_RootConstrainSelectedInstOperands,
     /*  910951 */     // GIR_Coverage, 3531,
     /*  910951 */     GIR_EraseRootFromParent_Done,
     /*  910952 */   // Label 14603: @910952
     /*  910952 */   GIM_Try, /*On fail goto*//*Label 14604*/ GIMT_Encode4(911009), // Rule ID 3532 //
     /*  910957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  910960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  910965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  910968 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  910971 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  910974 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  910977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  910981 */     // MIs[0] cbsz
     /*  910981 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  910984 */     // MIs[0] abid
     /*  910984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  910987 */     // MIs[0] blgp
     /*  910987 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  910990 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X64_I8_vgprcd_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  910990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_vgprcd_e64),
     /*  910993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  910995 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  910997 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  910999 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911001 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911003 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911005 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911007 */     GIR_RootConstrainSelectedInstOperands,
     /*  911008 */     // GIR_Coverage, 3532,
     /*  911008 */     GIR_EraseRootFromParent_Done,
     /*  911009 */   // Label 14604: @911009
     /*  911009 */   GIM_Try, /*On fail goto*//*Label 14605*/ GIMT_Encode4(911066), // Rule ID 3533 //
     /*  911014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  911017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x64_i8),
     /*  911022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  911025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  911028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  911031 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  911034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  911038 */     // MIs[0] cbsz
     /*  911038 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911041 */     // MIs[0] abid
     /*  911041 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911044 */     // MIs[0] blgp
     /*  911044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911047 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3320:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X64_I8_vgprcd_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X64_I8_vgprcd_e64),
     /*  911050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911052 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911054 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911056 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911058 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911060 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911062 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911064 */     GIR_RootConstrainSelectedInstOperands,
     /*  911065 */     // GIR_Coverage, 3533,
     /*  911065 */     GIR_EraseRootFromParent_Done,
     /*  911066 */   // Label 14605: @911066
     /*  911066 */   GIM_Try, /*On fail goto*//*Label 14606*/ GIMT_Encode4(911123), // Rule ID 3539 //
     /*  911071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  911074 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  911079 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911082 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  911085 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  911088 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911095 */     // MIs[0] cbsz
     /*  911095 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911098 */     // MIs[0] abid
     /*  911098 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911101 */     // MIs[0] blgp
     /*  911101 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911104 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64),
     /*  911107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911109 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911111 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911113 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911115 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911117 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911119 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911121 */     GIR_RootConstrainSelectedInstOperands,
     /*  911122 */     // GIR_Coverage, 3539,
     /*  911122 */     GIR_EraseRootFromParent_Done,
     /*  911123 */   // Label 14606: @911123
     /*  911123 */   GIM_Try, /*On fail goto*//*Label 14607*/ GIMT_Encode4(911180), // Rule ID 3540 //
     /*  911128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  911131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  911136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  911142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  911145 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911152 */     // MIs[0] cbsz
     /*  911152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911155 */     // MIs[0] abid
     /*  911155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911158 */     // MIs[0] blgp
     /*  911158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911161 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64),
     /*  911164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911166 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911168 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911170 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911172 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911174 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911176 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911178 */     GIR_RootConstrainSelectedInstOperands,
     /*  911179 */     // GIR_Coverage, 3540,
     /*  911179 */     GIR_EraseRootFromParent_Done,
     /*  911180 */   // Label 14607: @911180
     /*  911180 */   GIM_Try, /*On fail goto*//*Label 14608*/ GIMT_Encode4(911237), // Rule ID 3541 //
     /*  911185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  911188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  911193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911196 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  911199 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  911202 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911209 */     // MIs[0] cbsz
     /*  911209 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911212 */     // MIs[0] abid
     /*  911212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911215 */     // MIs[0] blgp
     /*  911215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911218 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64),
     /*  911221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911223 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911225 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911227 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911229 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911231 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911233 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911235 */     GIR_RootConstrainSelectedInstOperands,
     /*  911236 */     // GIR_Coverage, 3541,
     /*  911236 */     GIR_EraseRootFromParent_Done,
     /*  911237 */   // Label 14608: @911237
     /*  911237 */   GIM_Try, /*On fail goto*//*Label 14609*/ GIMT_Encode4(911294), // Rule ID 3542 //
     /*  911242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  911245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  911250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  911256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  911259 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911266 */     // MIs[0] cbsz
     /*  911266 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911269 */     // MIs[0] abid
     /*  911269 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911272 */     // MIs[0] blgp
     /*  911272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911275 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64),
     /*  911278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911280 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911282 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911284 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911286 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911288 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911290 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911292 */     GIR_RootConstrainSelectedInstOperands,
     /*  911293 */     // GIR_Coverage, 3542,
     /*  911293 */     GIR_EraseRootFromParent_Done,
     /*  911294 */   // Label 14609: @911294
     /*  911294 */   GIM_Try, /*On fail goto*//*Label 14610*/ GIMT_Encode4(911351), // Rule ID 3543 //
     /*  911299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  911302 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x32_i8),
     /*  911307 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  911313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  911316 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911323 */     // MIs[0] cbsz
     /*  911323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911326 */     // MIs[0] abid
     /*  911326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911329 */     // MIs[0] blgp
     /*  911329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911332 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3322:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64),
     /*  911335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911337 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911339 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911341 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911343 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911345 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911347 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911349 */     GIR_RootConstrainSelectedInstOperands,
     /*  911350 */     // GIR_Coverage, 3543,
     /*  911350 */     GIR_EraseRootFromParent_Done,
     /*  911351 */   // Label 14610: @911351
     /*  911351 */   GIM_Try, /*On fail goto*//*Label 14611*/ GIMT_Encode4(911408), // Rule ID 3909 //
     /*  911356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  911359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  911364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  911367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911373 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  911376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  911380 */     // MIs[0] cbsz
     /*  911380 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911383 */     // MIs[0] abid
     /*  911383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911386 */     // MIs[0] blgp
     /*  911386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911389 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64),
     /*  911392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911394 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911396 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911398 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911400 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911402 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911404 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911406 */     GIR_RootConstrainSelectedInstOperands,
     /*  911407 */     // GIR_Coverage, 3909,
     /*  911407 */     GIR_EraseRootFromParent_Done,
     /*  911408 */   // Label 14611: @911408
     /*  911408 */   GIM_Try, /*On fail goto*//*Label 14612*/ GIMT_Encode4(911465), // Rule ID 3910 //
     /*  911413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  911416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  911421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  911424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911430 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  911433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  911437 */     // MIs[0] cbsz
     /*  911437 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911440 */     // MIs[0] abid
     /*  911440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911443 */     // MIs[0] blgp
     /*  911443 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911446 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64),
     /*  911449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911451 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911453 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911455 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911457 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911459 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911461 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911463 */     GIR_RootConstrainSelectedInstOperands,
     /*  911464 */     // GIR_Coverage, 3910,
     /*  911464 */     GIR_EraseRootFromParent_Done,
     /*  911465 */   // Label 14612: @911465
     /*  911465 */   GIM_Try, /*On fail goto*//*Label 14613*/ GIMT_Encode4(911522), // Rule ID 3911 //
     /*  911470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  911473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  911478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  911481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911487 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  911490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  911494 */     // MIs[0] cbsz
     /*  911494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911497 */     // MIs[0] abid
     /*  911497 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911500 */     // MIs[0] blgp
     /*  911500 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911503 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64),
     /*  911506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911508 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911510 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911512 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911514 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911516 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911518 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911520 */     GIR_RootConstrainSelectedInstOperands,
     /*  911521 */     // GIR_Coverage, 3911,
     /*  911521 */     GIR_EraseRootFromParent_Done,
     /*  911522 */   // Label 14613: @911522
     /*  911522 */   GIM_Try, /*On fail goto*//*Label 14614*/ GIMT_Encode4(911579), // Rule ID 3912 //
     /*  911527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  911530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  911535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  911538 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911541 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911544 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  911547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  911551 */     // MIs[0] cbsz
     /*  911551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911554 */     // MIs[0] abid
     /*  911554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911557 */     // MIs[0] blgp
     /*  911557 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911560 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64),
     /*  911563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911565 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911567 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911569 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911571 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911573 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911575 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911577 */     GIR_RootConstrainSelectedInstOperands,
     /*  911578 */     // GIR_Coverage, 3912,
     /*  911578 */     GIR_EraseRootFromParent_Done,
     /*  911579 */   // Label 14614: @911579
     /*  911579 */   GIM_Try, /*On fail goto*//*Label 14615*/ GIMT_Encode4(911636), // Rule ID 3913 //
     /*  911584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  911587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
     /*  911592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32,
     /*  911595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911601 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32,
     /*  911604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
     /*  911608 */     // MIs[0] cbsz
     /*  911608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911611 */     // MIs[0] abid
     /*  911611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911614 */     // MIs[0] blgp
     /*  911614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911617 */     // (intrinsic_wo_chain:{ *:[v32f32] } 3307:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64),
     /*  911620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911622 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911624 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911626 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911628 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911630 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911632 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911634 */     GIR_RootConstrainSelectedInstOperands,
     /*  911635 */     // GIR_Coverage, 3913,
     /*  911635 */     GIR_EraseRootFromParent_Done,
     /*  911636 */   // Label 14615: @911636
     /*  911636 */   GIM_Try, /*On fail goto*//*Label 14616*/ GIMT_Encode4(911693), // Rule ID 3919 //
     /*  911641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  911644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  911649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911655 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911658 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911665 */     // MIs[0] cbsz
     /*  911665 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911668 */     // MIs[0] abid
     /*  911668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911671 */     // MIs[0] blgp
     /*  911671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911674 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64),
     /*  911677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911679 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911681 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911683 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911685 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911687 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911689 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911691 */     GIR_RootConstrainSelectedInstOperands,
     /*  911692 */     // GIR_Coverage, 3919,
     /*  911692 */     GIR_EraseRootFromParent_Done,
     /*  911693 */   // Label 14616: @911693
     /*  911693 */   GIM_Try, /*On fail goto*//*Label 14617*/ GIMT_Encode4(911750), // Rule ID 3920 //
     /*  911698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  911701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  911706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911712 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911715 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911722 */     // MIs[0] cbsz
     /*  911722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911725 */     // MIs[0] abid
     /*  911725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911728 */     // MIs[0] blgp
     /*  911728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911731 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64),
     /*  911734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911736 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911738 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911740 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911742 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911744 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911746 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911748 */     GIR_RootConstrainSelectedInstOperands,
     /*  911749 */     // GIR_Coverage, 3920,
     /*  911749 */     GIR_EraseRootFromParent_Done,
     /*  911750 */   // Label 14617: @911750
     /*  911750 */   GIM_Try, /*On fail goto*//*Label 14618*/ GIMT_Encode4(911807), // Rule ID 3921 //
     /*  911755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  911758 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  911763 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911766 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911772 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911779 */     // MIs[0] cbsz
     /*  911779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911782 */     // MIs[0] abid
     /*  911782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911785 */     // MIs[0] blgp
     /*  911785 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911788 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64),
     /*  911791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911793 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911795 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911797 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911799 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911801 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911803 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911805 */     GIR_RootConstrainSelectedInstOperands,
     /*  911806 */     // GIR_Coverage, 3921,
     /*  911806 */     GIR_EraseRootFromParent_Done,
     /*  911807 */   // Label 14618: @911807
     /*  911807 */   GIM_Try, /*On fail goto*//*Label 14619*/ GIMT_Encode4(911864), // Rule ID 3922 //
     /*  911812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  911815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  911820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911829 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911836 */     // MIs[0] cbsz
     /*  911836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911839 */     // MIs[0] abid
     /*  911839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911842 */     // MIs[0] blgp
     /*  911842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911845 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64),
     /*  911848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911850 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911852 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911854 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911856 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911858 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911860 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911862 */     GIR_RootConstrainSelectedInstOperands,
     /*  911863 */     // GIR_Coverage, 3922,
     /*  911863 */     GIR_EraseRootFromParent_Done,
     /*  911864 */   // Label 14619: @911864
     /*  911864 */   GIM_Try, /*On fail goto*//*Label 14620*/ GIMT_Encode4(911921), // Rule ID 3923 //
     /*  911869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  911872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
     /*  911877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  911880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911886 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  911889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  911893 */     // MIs[0] cbsz
     /*  911893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911896 */     // MIs[0] abid
     /*  911896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911899 */     // MIs[0] blgp
     /*  911899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911902 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3291:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64),
     /*  911905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911907 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911909 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911911 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911913 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911915 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911917 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911919 */     GIR_RootConstrainSelectedInstOperands,
     /*  911920 */     // GIR_Coverage, 3923,
     /*  911920 */     GIR_EraseRootFromParent_Done,
     /*  911921 */   // Label 14620: @911921
     /*  911921 */   GIM_Try, /*On fail goto*//*Label 14621*/ GIMT_Encode4(911978), // Rule ID 3929 //
     /*  911926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  911929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  911934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  911937 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911940 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  911943 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  911946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  911950 */     // MIs[0] cbsz
     /*  911950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  911953 */     // MIs[0] abid
     /*  911953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  911956 */     // MIs[0] blgp
     /*  911956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  911959 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  911959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64),
     /*  911962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  911964 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  911966 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  911968 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  911970 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  911972 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  911974 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  911976 */     GIR_RootConstrainSelectedInstOperands,
     /*  911977 */     // GIR_Coverage, 3929,
     /*  911977 */     GIR_EraseRootFromParent_Done,
     /*  911978 */   // Label 14621: @911978
     /*  911978 */   GIM_Try, /*On fail goto*//*Label 14622*/ GIMT_Encode4(912035), // Rule ID 3930 //
     /*  911983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  911986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  911991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  911994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  911997 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912000 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912007 */     // MIs[0] cbsz
     /*  912007 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912010 */     // MIs[0] abid
     /*  912010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912013 */     // MIs[0] blgp
     /*  912013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912016 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64),
     /*  912019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912021 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912023 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912025 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912027 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912029 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912031 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912033 */     GIR_RootConstrainSelectedInstOperands,
     /*  912034 */     // GIR_Coverage, 3930,
     /*  912034 */     GIR_EraseRootFromParent_Done,
     /*  912035 */   // Label 14622: @912035
     /*  912035 */   GIM_Try, /*On fail goto*//*Label 14623*/ GIMT_Encode4(912092), // Rule ID 3931 //
     /*  912040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  912043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  912048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912057 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912064 */     // MIs[0] cbsz
     /*  912064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912067 */     // MIs[0] abid
     /*  912067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912070 */     // MIs[0] blgp
     /*  912070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912073 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64),
     /*  912076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912078 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912080 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912082 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912084 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912086 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912088 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912090 */     GIR_RootConstrainSelectedInstOperands,
     /*  912091 */     // GIR_Coverage, 3931,
     /*  912091 */     GIR_EraseRootFromParent_Done,
     /*  912092 */   // Label 14623: @912092
     /*  912092 */   GIM_Try, /*On fail goto*//*Label 14624*/ GIMT_Encode4(912149), // Rule ID 3932 //
     /*  912097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  912100 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  912105 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912108 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912114 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912121 */     // MIs[0] cbsz
     /*  912121 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912124 */     // MIs[0] abid
     /*  912124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912127 */     // MIs[0] blgp
     /*  912127 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912130 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64),
     /*  912133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912135 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912137 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912139 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912141 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912143 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912145 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912147 */     GIR_RootConstrainSelectedInstOperands,
     /*  912148 */     // GIR_Coverage, 3932,
     /*  912148 */     GIR_EraseRootFromParent_Done,
     /*  912149 */   // Label 14624: @912149
     /*  912149 */   GIM_Try, /*On fail goto*//*Label 14625*/ GIMT_Encode4(912206), // Rule ID 3933 //
     /*  912154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  912157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
     /*  912162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912165 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912168 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912171 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912178 */     // MIs[0] cbsz
     /*  912178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912181 */     // MIs[0] abid
     /*  912181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912184 */     // MIs[0] blgp
     /*  912184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912187 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3313:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64),
     /*  912190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912192 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912194 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912196 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912198 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912200 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912202 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912204 */     GIR_RootConstrainSelectedInstOperands,
     /*  912205 */     // GIR_Coverage, 3933,
     /*  912205 */     GIR_EraseRootFromParent_Done,
     /*  912206 */   // Label 14625: @912206
     /*  912206 */   GIM_Try, /*On fail goto*//*Label 14626*/ GIMT_Encode4(912263), // Rule ID 3939 //
     /*  912211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  912214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  912219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  912222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912228 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  912231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  912235 */     // MIs[0] cbsz
     /*  912235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912238 */     // MIs[0] abid
     /*  912238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912241 */     // MIs[0] blgp
     /*  912241 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912244 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64),
     /*  912247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912249 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912251 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912253 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912255 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912257 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912259 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912261 */     GIR_RootConstrainSelectedInstOperands,
     /*  912262 */     // GIR_Coverage, 3939,
     /*  912262 */     GIR_EraseRootFromParent_Done,
     /*  912263 */   // Label 14626: @912263
     /*  912263 */   GIM_Try, /*On fail goto*//*Label 14627*/ GIMT_Encode4(912320), // Rule ID 3940 //
     /*  912268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  912271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  912276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  912279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912285 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  912288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  912292 */     // MIs[0] cbsz
     /*  912292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912295 */     // MIs[0] abid
     /*  912295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912298 */     // MIs[0] blgp
     /*  912298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912301 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64),
     /*  912304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912306 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912308 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912310 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912312 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912314 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912316 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912318 */     GIR_RootConstrainSelectedInstOperands,
     /*  912319 */     // GIR_Coverage, 3940,
     /*  912319 */     GIR_EraseRootFromParent_Done,
     /*  912320 */   // Label 14627: @912320
     /*  912320 */   GIM_Try, /*On fail goto*//*Label 14628*/ GIMT_Encode4(912377), // Rule ID 3941 //
     /*  912325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  912328 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  912333 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  912336 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912339 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912342 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  912345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  912349 */     // MIs[0] cbsz
     /*  912349 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912352 */     // MIs[0] abid
     /*  912352 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912355 */     // MIs[0] blgp
     /*  912355 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912358 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64),
     /*  912361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912363 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912365 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912367 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912369 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912371 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912373 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912375 */     GIR_RootConstrainSelectedInstOperands,
     /*  912376 */     // GIR_Coverage, 3941,
     /*  912376 */     GIR_EraseRootFromParent_Done,
     /*  912377 */   // Label 14628: @912377
     /*  912377 */   GIM_Try, /*On fail goto*//*Label 14629*/ GIMT_Encode4(912434), // Rule ID 3942 //
     /*  912382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  912385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  912390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  912393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912399 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  912402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  912406 */     // MIs[0] cbsz
     /*  912406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912409 */     // MIs[0] abid
     /*  912409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912412 */     // MIs[0] blgp
     /*  912412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912415 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64),
     /*  912418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912420 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912422 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912424 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912426 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912428 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912430 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912432 */     GIR_RootConstrainSelectedInstOperands,
     /*  912433 */     // GIR_Coverage, 3942,
     /*  912433 */     GIR_EraseRootFromParent_Done,
     /*  912434 */   // Label 14629: @912434
     /*  912434 */   GIM_Try, /*On fail goto*//*Label 14630*/ GIMT_Encode4(912491), // Rule ID 3943 //
     /*  912439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  912442 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
     /*  912447 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  912450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912456 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  912459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  912463 */     // MIs[0] cbsz
     /*  912463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912466 */     // MIs[0] abid
     /*  912466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912469 */     // MIs[0] blgp
     /*  912469 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912472 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3309:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64),
     /*  912475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912477 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912479 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912481 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912483 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912485 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912487 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912489 */     GIR_RootConstrainSelectedInstOperands,
     /*  912490 */     // GIR_Coverage, 3943,
     /*  912490 */     GIR_EraseRootFromParent_Done,
     /*  912491 */   // Label 14630: @912491
     /*  912491 */   GIM_Try, /*On fail goto*//*Label 14631*/ GIMT_Encode4(912548), // Rule ID 3949 //
     /*  912496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  912499 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  912504 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912507 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912510 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912513 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912520 */     // MIs[0] cbsz
     /*  912520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912523 */     // MIs[0] abid
     /*  912523 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912526 */     // MIs[0] blgp
     /*  912526 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912529 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64),
     /*  912532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912534 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912536 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912538 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912540 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912542 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912544 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912546 */     GIR_RootConstrainSelectedInstOperands,
     /*  912547 */     // GIR_Coverage, 3949,
     /*  912547 */     GIR_EraseRootFromParent_Done,
     /*  912548 */   // Label 14631: @912548
     /*  912548 */   GIM_Try, /*On fail goto*//*Label 14632*/ GIMT_Encode4(912605), // Rule ID 3950 //
     /*  912553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  912556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  912561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912570 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912577 */     // MIs[0] cbsz
     /*  912577 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912580 */     // MIs[0] abid
     /*  912580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912583 */     // MIs[0] blgp
     /*  912583 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912586 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64),
     /*  912589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912591 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912593 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912595 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912597 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912599 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912601 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912603 */     GIR_RootConstrainSelectedInstOperands,
     /*  912604 */     // GIR_Coverage, 3950,
     /*  912604 */     GIR_EraseRootFromParent_Done,
     /*  912605 */   // Label 14632: @912605
     /*  912605 */   GIM_Try, /*On fail goto*//*Label 14633*/ GIMT_Encode4(912662), // Rule ID 3951 //
     /*  912610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  912613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  912618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912634 */     // MIs[0] cbsz
     /*  912634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912637 */     // MIs[0] abid
     /*  912637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912640 */     // MIs[0] blgp
     /*  912640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912643 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64),
     /*  912646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912648 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912650 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912652 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912654 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912656 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912658 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912660 */     GIR_RootConstrainSelectedInstOperands,
     /*  912661 */     // GIR_Coverage, 3951,
     /*  912661 */     GIR_EraseRootFromParent_Done,
     /*  912662 */   // Label 14633: @912662
     /*  912662 */   GIM_Try, /*On fail goto*//*Label 14634*/ GIMT_Encode4(912719), // Rule ID 3952 //
     /*  912667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  912670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  912675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912678 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912681 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912684 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912691 */     // MIs[0] cbsz
     /*  912691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912694 */     // MIs[0] abid
     /*  912694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912697 */     // MIs[0] blgp
     /*  912697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912700 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64),
     /*  912703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912705 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912707 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912709 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912711 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912713 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912715 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912717 */     GIR_RootConstrainSelectedInstOperands,
     /*  912718 */     // GIR_Coverage, 3952,
     /*  912718 */     GIR_EraseRootFromParent_Done,
     /*  912719 */   // Label 14634: @912719
     /*  912719 */   GIM_Try, /*On fail goto*//*Label 14635*/ GIMT_Encode4(912776), // Rule ID 3953 //
     /*  912724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  912727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
     /*  912732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  912735 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  912738 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  912741 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  912744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  912748 */     // MIs[0] cbsz
     /*  912748 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912751 */     // MIs[0] abid
     /*  912751 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912754 */     // MIs[0] blgp
     /*  912754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912757 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3281:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64),
     /*  912760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912762 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912764 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912766 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912768 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912770 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912772 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912774 */     GIR_RootConstrainSelectedInstOperands,
     /*  912775 */     // GIR_Coverage, 3953,
     /*  912775 */     GIR_EraseRootFromParent_Done,
     /*  912776 */   // Label 14635: @912776
     /*  912776 */   GIM_Try, /*On fail goto*//*Label 14636*/ GIMT_Encode4(912833), // Rule ID 3959 //
     /*  912781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  912784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  912789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  912792 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  912795 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  912798 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  912801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  912805 */     // MIs[0] cbsz
     /*  912805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912808 */     // MIs[0] abid
     /*  912808 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912811 */     // MIs[0] blgp
     /*  912811 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912814 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64),
     /*  912817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912819 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912821 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912823 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912825 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912827 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912829 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912831 */     GIR_RootConstrainSelectedInstOperands,
     /*  912832 */     // GIR_Coverage, 3959,
     /*  912832 */     GIR_EraseRootFromParent_Done,
     /*  912833 */   // Label 14636: @912833
     /*  912833 */   GIM_Try, /*On fail goto*//*Label 14637*/ GIMT_Encode4(912890), // Rule ID 3960 //
     /*  912838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  912841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  912846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  912849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  912852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  912855 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  912858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  912862 */     // MIs[0] cbsz
     /*  912862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912865 */     // MIs[0] abid
     /*  912865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912868 */     // MIs[0] blgp
     /*  912868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912871 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64),
     /*  912874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912876 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912878 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912880 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912882 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912884 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912886 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912888 */     GIR_RootConstrainSelectedInstOperands,
     /*  912889 */     // GIR_Coverage, 3960,
     /*  912889 */     GIR_EraseRootFromParent_Done,
     /*  912890 */   // Label 14637: @912890
     /*  912890 */   GIM_Try, /*On fail goto*//*Label 14638*/ GIMT_Encode4(912947), // Rule ID 3961 //
     /*  912895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  912898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  912903 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  912906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  912909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  912912 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  912915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  912919 */     // MIs[0] cbsz
     /*  912919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912922 */     // MIs[0] abid
     /*  912922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912925 */     // MIs[0] blgp
     /*  912925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912928 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64),
     /*  912931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912933 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912937 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912939 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912941 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  912943 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  912945 */     GIR_RootConstrainSelectedInstOperands,
     /*  912946 */     // GIR_Coverage, 3961,
     /*  912946 */     GIR_EraseRootFromParent_Done,
     /*  912947 */   // Label 14638: @912947
     /*  912947 */   GIM_Try, /*On fail goto*//*Label 14639*/ GIMT_Encode4(913004), // Rule ID 3962 //
     /*  912952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  912955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  912960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  912963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  912966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  912969 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  912972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  912976 */     // MIs[0] cbsz
     /*  912976 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  912979 */     // MIs[0] abid
     /*  912979 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  912982 */     // MIs[0] blgp
     /*  912982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  912985 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  912985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64),
     /*  912988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  912990 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  912992 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  912994 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  912996 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  912998 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913000 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913002 */     GIR_RootConstrainSelectedInstOperands,
     /*  913003 */     // GIR_Coverage, 3962,
     /*  913003 */     GIR_EraseRootFromParent_Done,
     /*  913004 */   // Label 14639: @913004
     /*  913004 */   GIM_Try, /*On fail goto*//*Label 14640*/ GIMT_Encode4(913061), // Rule ID 3963 //
     /*  913009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  913012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
     /*  913017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64,
     /*  913020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913026 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64,
     /*  913029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  913033 */     // MIs[0] cbsz
     /*  913033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913036 */     // MIs[0] abid
     /*  913036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913039 */     // MIs[0] blgp
     /*  913039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913042 */     // (intrinsic_wo_chain:{ *:[v4f64] } 3315:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64),
     /*  913045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913047 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913049 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913051 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913053 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913055 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913057 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913059 */     GIR_RootConstrainSelectedInstOperands,
     /*  913060 */     // GIR_Coverage, 3963,
     /*  913060 */     GIR_EraseRootFromParent_Done,
     /*  913061 */   // Label 14640: @913061
     /*  913061 */   GIM_Try, /*On fail goto*//*Label 14641*/ GIMT_Encode4(913118), // Rule ID 3969 //
     /*  913066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode0),
     /*  913069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  913074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  913077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913083 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  913086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  913090 */     // MIs[0] cbsz
     /*  913090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913093 */     // MIs[0] abid
     /*  913093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913096 */     // MIs[0] blgp
     /*  913096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913099 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64),
     /*  913102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913104 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913106 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913108 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913110 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913112 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913114 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913116 */     GIR_RootConstrainSelectedInstOperands,
     /*  913117 */     // GIR_Coverage, 3969,
     /*  913117 */     GIR_EraseRootFromParent_Done,
     /*  913118 */   // Label 14641: @913118
     /*  913118 */   GIM_Try, /*On fail goto*//*Label 14642*/ GIMT_Encode4(913175), // Rule ID 3970 //
     /*  913123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode1),
     /*  913126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  913131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  913134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913140 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  913143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  913147 */     // MIs[0] cbsz
     /*  913147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913150 */     // MIs[0] abid
     /*  913150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913153 */     // MIs[0] blgp
     /*  913153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913156 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64),
     /*  913159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913161 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913163 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913165 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913167 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913169 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913171 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913173 */     GIR_RootConstrainSelectedInstOperands,
     /*  913174 */     // GIR_Coverage, 3970,
     /*  913174 */     GIR_EraseRootFromParent_Done,
     /*  913175 */   // Label 14642: @913175
     /*  913175 */   GIM_Try, /*On fail goto*//*Label 14643*/ GIMT_Encode4(913232), // Rule ID 3971 //
     /*  913180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode2),
     /*  913183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  913188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  913191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913197 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  913200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  913204 */     // MIs[0] cbsz
     /*  913204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913207 */     // MIs[0] abid
     /*  913207 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913210 */     // MIs[0] blgp
     /*  913210 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913213 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64),
     /*  913216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913218 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913220 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913222 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913224 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913226 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913228 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913230 */     GIR_RootConstrainSelectedInstOperands,
     /*  913231 */     // GIR_Coverage, 3971,
     /*  913231 */     GIR_EraseRootFromParent_Done,
     /*  913232 */   // Label 14643: @913232
     /*  913232 */   GIM_Try, /*On fail goto*//*Label 14644*/ GIMT_Encode4(913289), // Rule ID 3972 //
     /*  913237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode3),
     /*  913240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  913245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  913248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913251 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913254 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  913257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  913261 */     // MIs[0] cbsz
     /*  913261 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913264 */     // MIs[0] abid
     /*  913264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913267 */     // MIs[0] blgp
     /*  913267 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913270 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64),
     /*  913273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913275 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913277 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913279 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913281 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913283 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913285 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913287 */     GIR_RootConstrainSelectedInstOperands,
     /*  913288 */     // GIR_Coverage, 3972,
     /*  913288 */     GIR_EraseRootFromParent_Done,
     /*  913289 */   // Label 14644: @913289
     /*  913289 */   GIM_Try, /*On fail goto*//*Label 14645*/ GIMT_Encode4(913346), // Rule ID 3973 //
     /*  913294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_HwMode4),
     /*  913297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
     /*  913302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  913305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913311 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /*  913314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  913318 */     // MIs[0] cbsz
     /*  913318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913321 */     // MIs[0] abid
     /*  913321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913324 */     // MIs[0] blgp
     /*  913324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913327 */     // (intrinsic_wo_chain:{ *:[f64] } 3316:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64),
     /*  913330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913332 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913334 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913336 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913338 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913340 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913342 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913344 */     GIR_RootConstrainSelectedInstOperands,
     /*  913345 */     // GIR_Coverage, 3973,
     /*  913345 */     GIR_EraseRootFromParent_Done,
     /*  913346 */   // Label 14645: @913346
     /*  913346 */   GIM_Try, /*On fail goto*//*Label 14646*/ GIMT_Encode4(913403), // Rule ID 3979 //
     /*  913351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode0),
     /*  913354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  913359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  913362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  913371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  913375 */     // MIs[0] cbsz
     /*  913375 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913378 */     // MIs[0] abid
     /*  913378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913381 */     // MIs[0] blgp
     /*  913381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913384 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64),
     /*  913387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913389 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913391 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913393 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913395 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913397 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913399 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913401 */     GIR_RootConstrainSelectedInstOperands,
     /*  913402 */     // GIR_Coverage, 3979,
     /*  913402 */     GIR_EraseRootFromParent_Done,
     /*  913403 */   // Label 14646: @913403
     /*  913403 */   GIM_Try, /*On fail goto*//*Label 14647*/ GIMT_Encode4(913460), // Rule ID 3980 //
     /*  913408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode1),
     /*  913411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  913416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  913419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913425 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  913428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  913432 */     // MIs[0] cbsz
     /*  913432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913435 */     // MIs[0] abid
     /*  913435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913438 */     // MIs[0] blgp
     /*  913438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913441 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64),
     /*  913444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913446 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913448 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913450 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913452 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913454 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913456 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913458 */     GIR_RootConstrainSelectedInstOperands,
     /*  913459 */     // GIR_Coverage, 3980,
     /*  913459 */     GIR_EraseRootFromParent_Done,
     /*  913460 */   // Label 14647: @913460
     /*  913460 */   GIM_Try, /*On fail goto*//*Label 14648*/ GIMT_Encode4(913517), // Rule ID 3981 //
     /*  913465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode2),
     /*  913468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  913473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  913476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913482 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  913485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  913489 */     // MIs[0] cbsz
     /*  913489 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913492 */     // MIs[0] abid
     /*  913492 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913495 */     // MIs[0] blgp
     /*  913495 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913498 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64),
     /*  913501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913503 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913505 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913507 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913509 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913511 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913513 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913515 */     GIR_RootConstrainSelectedInstOperands,
     /*  913516 */     // GIR_Coverage, 3981,
     /*  913516 */     GIR_EraseRootFromParent_Done,
     /*  913517 */   // Label 14648: @913517
     /*  913517 */   GIM_Try, /*On fail goto*//*Label 14649*/ GIMT_Encode4(913574), // Rule ID 3982 //
     /*  913522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode3),
     /*  913525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  913530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  913533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913536 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913539 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  913542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  913546 */     // MIs[0] cbsz
     /*  913546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913549 */     // MIs[0] abid
     /*  913549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913552 */     // MIs[0] blgp
     /*  913552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913555 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64),
     /*  913558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913560 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913562 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913564 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913566 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913568 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913570 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913572 */     GIR_RootConstrainSelectedInstOperands,
     /*  913573 */     // GIR_Coverage, 3982,
     /*  913573 */     GIR_EraseRootFromParent_Done,
     /*  913574 */   // Label 14649: @913574
     /*  913574 */   GIM_Try, /*On fail goto*//*Label 14650*/ GIMT_Encode4(913631), // Rule ID 3983 //
     /*  913579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode4),
     /*  913582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
     /*  913587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  913590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913596 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  913599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  913603 */     // MIs[0] cbsz
     /*  913603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913606 */     // MIs[0] abid
     /*  913606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913609 */     // MIs[0] blgp
     /*  913609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913612 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3321:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64),
     /*  913615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913617 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913619 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913621 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913623 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913625 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913627 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913629 */     GIR_RootConstrainSelectedInstOperands,
     /*  913630 */     // GIR_Coverage, 3983,
     /*  913630 */     GIR_EraseRootFromParent_Done,
     /*  913631 */   // Label 14650: @913631
     /*  913631 */   GIM_Try, /*On fail goto*//*Label 14651*/ GIMT_Encode4(913688), // Rule ID 3989 //
     /*  913636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode0),
     /*  913639 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  913644 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913647 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913650 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913653 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  913660 */     // MIs[0] cbsz
     /*  913660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913663 */     // MIs[0] abid
     /*  913663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913666 */     // MIs[0] blgp
     /*  913666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913669 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64),
     /*  913672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913674 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913676 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913678 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913680 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913682 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913684 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913686 */     GIR_RootConstrainSelectedInstOperands,
     /*  913687 */     // GIR_Coverage, 3989,
     /*  913687 */     GIR_EraseRootFromParent_Done,
     /*  913688 */   // Label 14651: @913688
     /*  913688 */   GIM_Try, /*On fail goto*//*Label 14652*/ GIMT_Encode4(913745), // Rule ID 3990 //
     /*  913693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode1),
     /*  913696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  913701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913710 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  913717 */     // MIs[0] cbsz
     /*  913717 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913720 */     // MIs[0] abid
     /*  913720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913723 */     // MIs[0] blgp
     /*  913723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913726 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64),
     /*  913729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913731 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913733 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913735 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913737 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913739 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913741 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913743 */     GIR_RootConstrainSelectedInstOperands,
     /*  913744 */     // GIR_Coverage, 3990,
     /*  913744 */     GIR_EraseRootFromParent_Done,
     /*  913745 */   // Label 14652: @913745
     /*  913745 */   GIM_Try, /*On fail goto*//*Label 14653*/ GIMT_Encode4(913802), // Rule ID 3991 //
     /*  913750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode2),
     /*  913753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  913758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  913774 */     // MIs[0] cbsz
     /*  913774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913777 */     // MIs[0] abid
     /*  913777 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913780 */     // MIs[0] blgp
     /*  913780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913783 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64),
     /*  913786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913788 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913790 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913792 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913794 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913796 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913798 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913800 */     GIR_RootConstrainSelectedInstOperands,
     /*  913801 */     // GIR_Coverage, 3991,
     /*  913801 */     GIR_EraseRootFromParent_Done,
     /*  913802 */   // Label 14653: @913802
     /*  913802 */   GIM_Try, /*On fail goto*//*Label 14654*/ GIMT_Encode4(913859), // Rule ID 3992 //
     /*  913807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode3),
     /*  913810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  913815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913824 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  913831 */     // MIs[0] cbsz
     /*  913831 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913834 */     // MIs[0] abid
     /*  913834 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913837 */     // MIs[0] blgp
     /*  913837 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913840 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64),
     /*  913843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913845 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913847 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913849 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913851 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913853 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913855 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913857 */     GIR_RootConstrainSelectedInstOperands,
     /*  913858 */     // GIR_Coverage, 3992,
     /*  913858 */     GIR_EraseRootFromParent_Done,
     /*  913859 */   // Label 14654: @913859
     /*  913859 */   GIM_Try, /*On fail goto*//*Label 14655*/ GIMT_Encode4(913916), // Rule ID 3993 //
     /*  913864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus_isGFX940Plus_HwMode4),
     /*  913867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
     /*  913872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  913878 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  913881 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  913888 */     // MIs[0] cbsz
     /*  913888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913891 */     // MIs[0] abid
     /*  913891 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913894 */     // MIs[0] blgp
     /*  913894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913897 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3318:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64),
     /*  913900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913902 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913904 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913906 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913908 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913910 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913912 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913914 */     GIR_RootConstrainSelectedInstOperands,
     /*  913915 */     // GIR_Coverage, 3993,
     /*  913915 */     GIR_EraseRootFromParent_Done,
     /*  913916 */   // Label 14655: @913916
     /*  913916 */   GIM_Try, /*On fail goto*//*Label 14656*/ GIMT_Encode4(913973), // Rule ID 3999 //
     /*  913921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode0),
     /*  913924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  913929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  913935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  913938 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913941 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  913945 */     // MIs[0] cbsz
     /*  913945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  913948 */     // MIs[0] abid
     /*  913948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  913951 */     // MIs[0] blgp
     /*  913951 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  913954 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  913954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64),
     /*  913957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  913959 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  913961 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  913963 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  913965 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  913967 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  913969 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  913971 */     GIR_RootConstrainSelectedInstOperands,
     /*  913972 */     // GIR_Coverage, 3999,
     /*  913972 */     GIR_EraseRootFromParent_Done,
     /*  913973 */   // Label 14656: @913973
     /*  913973 */   GIM_Try, /*On fail goto*//*Label 14657*/ GIMT_Encode4(914030), // Rule ID 4000 //
     /*  913978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode1),
     /*  913981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  913986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  913989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  913992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  913995 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  913998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914002 */     // MIs[0] cbsz
     /*  914002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914005 */     // MIs[0] abid
     /*  914005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914008 */     // MIs[0] blgp
     /*  914008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914011 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64),
     /*  914014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914016 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914018 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914020 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914022 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914024 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914026 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914028 */     GIR_RootConstrainSelectedInstOperands,
     /*  914029 */     // GIR_Coverage, 4000,
     /*  914029 */     GIR_EraseRootFromParent_Done,
     /*  914030 */   // Label 14657: @914030
     /*  914030 */   GIM_Try, /*On fail goto*//*Label 14658*/ GIMT_Encode4(914087), // Rule ID 4001 //
     /*  914035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode2),
     /*  914038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  914043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914052 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914059 */     // MIs[0] cbsz
     /*  914059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914062 */     // MIs[0] abid
     /*  914062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914065 */     // MIs[0] blgp
     /*  914065 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914068 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64),
     /*  914071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914073 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914075 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914077 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914079 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914081 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914083 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914085 */     GIR_RootConstrainSelectedInstOperands,
     /*  914086 */     // GIR_Coverage, 4001,
     /*  914086 */     GIR_EraseRootFromParent_Done,
     /*  914087 */   // Label 14658: @914087
     /*  914087 */   GIM_Try, /*On fail goto*//*Label 14659*/ GIMT_Encode4(914144), // Rule ID 4002 //
     /*  914092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode3),
     /*  914095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  914100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914109 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914116 */     // MIs[0] cbsz
     /*  914116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914119 */     // MIs[0] abid
     /*  914119 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914122 */     // MIs[0] blgp
     /*  914122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914125 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64),
     /*  914128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914130 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914132 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914134 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914136 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914138 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914140 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914142 */     GIR_RootConstrainSelectedInstOperands,
     /*  914143 */     // GIR_Coverage, 4002,
     /*  914143 */     GIR_EraseRootFromParent_Done,
     /*  914144 */   // Label 14659: @914144
     /*  914144 */   GIM_Try, /*On fail goto*//*Label 14660*/ GIMT_Encode4(914201), // Rule ID 4003 //
     /*  914149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode4),
     /*  914152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
     /*  914157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914163 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914166 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914173 */     // MIs[0] cbsz
     /*  914173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914176 */     // MIs[0] abid
     /*  914176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914179 */     // MIs[0] blgp
     /*  914179 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914182 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3294:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64),
     /*  914185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914187 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914189 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914191 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914193 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914195 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914197 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914199 */     GIR_RootConstrainSelectedInstOperands,
     /*  914200 */     // GIR_Coverage, 4003,
     /*  914200 */     GIR_EraseRootFromParent_Done,
     /*  914201 */   // Label 14660: @914201
     /*  914201 */   GIM_Try, /*On fail goto*//*Label 14661*/ GIMT_Encode4(914258), // Rule ID 4009 //
     /*  914206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode0),
     /*  914209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  914214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  914217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914220 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914223 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  914226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  914230 */     // MIs[0] cbsz
     /*  914230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914233 */     // MIs[0] abid
     /*  914233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914236 */     // MIs[0] blgp
     /*  914236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914239 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64),
     /*  914242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914244 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914246 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914248 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914250 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914252 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914254 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914256 */     GIR_RootConstrainSelectedInstOperands,
     /*  914257 */     // GIR_Coverage, 4009,
     /*  914257 */     GIR_EraseRootFromParent_Done,
     /*  914258 */   // Label 14661: @914258
     /*  914258 */   GIM_Try, /*On fail goto*//*Label 14662*/ GIMT_Encode4(914315), // Rule ID 4010 //
     /*  914263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode1),
     /*  914266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  914271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  914274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914280 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  914283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  914287 */     // MIs[0] cbsz
     /*  914287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914290 */     // MIs[0] abid
     /*  914290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914293 */     // MIs[0] blgp
     /*  914293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914296 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64),
     /*  914299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914301 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914303 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914305 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914307 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914309 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914311 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914313 */     GIR_RootConstrainSelectedInstOperands,
     /*  914314 */     // GIR_Coverage, 4010,
     /*  914314 */     GIR_EraseRootFromParent_Done,
     /*  914315 */   // Label 14662: @914315
     /*  914315 */   GIM_Try, /*On fail goto*//*Label 14663*/ GIMT_Encode4(914372), // Rule ID 4011 //
     /*  914320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode2),
     /*  914323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  914328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  914331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  914340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  914344 */     // MIs[0] cbsz
     /*  914344 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914347 */     // MIs[0] abid
     /*  914347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914350 */     // MIs[0] blgp
     /*  914350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914353 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64),
     /*  914356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914358 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914360 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914362 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914364 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914366 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914368 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914370 */     GIR_RootConstrainSelectedInstOperands,
     /*  914371 */     // GIR_Coverage, 4011,
     /*  914371 */     GIR_EraseRootFromParent_Done,
     /*  914372 */   // Label 14663: @914372
     /*  914372 */   GIM_Try, /*On fail goto*//*Label 14664*/ GIMT_Encode4(914429), // Rule ID 4012 //
     /*  914377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode3),
     /*  914380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  914385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  914388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914391 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914394 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  914397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  914401 */     // MIs[0] cbsz
     /*  914401 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914404 */     // MIs[0] abid
     /*  914404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914407 */     // MIs[0] blgp
     /*  914407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914410 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64),
     /*  914413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914415 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914417 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914419 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914421 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914423 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914425 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914427 */     GIR_RootConstrainSelectedInstOperands,
     /*  914428 */     // GIR_Coverage, 4012,
     /*  914428 */     GIR_EraseRootFromParent_Done,
     /*  914429 */   // Label 14664: @914429
     /*  914429 */   GIM_Try, /*On fail goto*//*Label 14665*/ GIMT_Encode4(914486), // Rule ID 4013 //
     /*  914434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXF32Insts_isGFX90APlus_HwMode4),
     /*  914437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
     /*  914442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  914445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  914448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  914451 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  914454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  914458 */     // MIs[0] cbsz
     /*  914458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914461 */     // MIs[0] abid
     /*  914461 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914464 */     // MIs[0] blgp
     /*  914464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914467 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3305:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64),
     /*  914470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914472 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914474 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914476 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914478 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914480 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914482 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914484 */     GIR_RootConstrainSelectedInstOperands,
     /*  914485 */     // GIR_Coverage, 4013,
     /*  914485 */     GIR_EraseRootFromParent_Done,
     /*  914486 */   // Label 14665: @914486
     /*  914486 */   GIM_Try, /*On fail goto*//*Label 14666*/ GIMT_Encode4(914543), // Rule ID 4019 //
     /*  914491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  914494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  914499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914508 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914515 */     // MIs[0] cbsz
     /*  914515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914518 */     // MIs[0] abid
     /*  914518 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914521 */     // MIs[0] blgp
     /*  914521 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914524 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64),
     /*  914527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914529 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914533 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914535 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914537 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914539 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914541 */     GIR_RootConstrainSelectedInstOperands,
     /*  914542 */     // GIR_Coverage, 4019,
     /*  914542 */     GIR_EraseRootFromParent_Done,
     /*  914543 */   // Label 14666: @914543
     /*  914543 */   GIM_Try, /*On fail goto*//*Label 14667*/ GIMT_Encode4(914600), // Rule ID 4020 //
     /*  914548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  914551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  914556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914565 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914572 */     // MIs[0] cbsz
     /*  914572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914575 */     // MIs[0] abid
     /*  914575 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914578 */     // MIs[0] blgp
     /*  914578 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914581 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64),
     /*  914584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914586 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914588 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914590 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914592 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914594 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914596 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914598 */     GIR_RootConstrainSelectedInstOperands,
     /*  914599 */     // GIR_Coverage, 4020,
     /*  914599 */     GIR_EraseRootFromParent_Done,
     /*  914600 */   // Label 14667: @914600
     /*  914600 */   GIM_Try, /*On fail goto*//*Label 14668*/ GIMT_Encode4(914657), // Rule ID 4021 //
     /*  914605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  914608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  914613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914616 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914619 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914622 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914629 */     // MIs[0] cbsz
     /*  914629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914632 */     // MIs[0] abid
     /*  914632 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914635 */     // MIs[0] blgp
     /*  914635 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914638 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64),
     /*  914641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914643 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914645 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914647 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914649 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914651 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914653 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914655 */     GIR_RootConstrainSelectedInstOperands,
     /*  914656 */     // GIR_Coverage, 4021,
     /*  914656 */     GIR_EraseRootFromParent_Done,
     /*  914657 */   // Label 14668: @914657
     /*  914657 */   GIM_Try, /*On fail goto*//*Label 14669*/ GIMT_Encode4(914714), // Rule ID 4022 //
     /*  914662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  914665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  914670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914679 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914686 */     // MIs[0] cbsz
     /*  914686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914689 */     // MIs[0] abid
     /*  914689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914692 */     // MIs[0] blgp
     /*  914692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914695 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64),
     /*  914698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914700 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914702 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914704 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914706 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914708 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914710 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914712 */     GIR_RootConstrainSelectedInstOperands,
     /*  914713 */     // GIR_Coverage, 4022,
     /*  914713 */     GIR_EraseRootFromParent_Done,
     /*  914714 */   // Label 14669: @914714
     /*  914714 */   GIM_Try, /*On fail goto*//*Label 14670*/ GIMT_Encode4(914771), // Rule ID 4023 //
     /*  914719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  914722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
     /*  914727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914736 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914743 */     // MIs[0] cbsz
     /*  914743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914746 */     // MIs[0] abid
     /*  914746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914749 */     // MIs[0] blgp
     /*  914749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914752 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3286:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64),
     /*  914755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914757 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914759 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914761 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914763 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914765 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914767 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914769 */     GIR_RootConstrainSelectedInstOperands,
     /*  914770 */     // GIR_Coverage, 4023,
     /*  914770 */     GIR_EraseRootFromParent_Done,
     /*  914771 */   // Label 14670: @914771
     /*  914771 */   GIM_Try, /*On fail goto*//*Label 14671*/ GIMT_Encode4(914828), // Rule ID 4029 //
     /*  914776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  914779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  914784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914793 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914800 */     // MIs[0] cbsz
     /*  914800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914803 */     // MIs[0] abid
     /*  914803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914806 */     // MIs[0] blgp
     /*  914806 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914809 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64),
     /*  914812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914814 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914816 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914818 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914820 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914822 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914824 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914826 */     GIR_RootConstrainSelectedInstOperands,
     /*  914827 */     // GIR_Coverage, 4029,
     /*  914827 */     GIR_EraseRootFromParent_Done,
     /*  914828 */   // Label 14671: @914828
     /*  914828 */   GIM_Try, /*On fail goto*//*Label 14672*/ GIMT_Encode4(914885), // Rule ID 4030 //
     /*  914833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  914836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  914841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914850 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914857 */     // MIs[0] cbsz
     /*  914857 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914860 */     // MIs[0] abid
     /*  914860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914863 */     // MIs[0] blgp
     /*  914863 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914866 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64),
     /*  914869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914871 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914873 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914875 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914877 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914879 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914881 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914883 */     GIR_RootConstrainSelectedInstOperands,
     /*  914884 */     // GIR_Coverage, 4030,
     /*  914884 */     GIR_EraseRootFromParent_Done,
     /*  914885 */   // Label 14672: @914885
     /*  914885 */   GIM_Try, /*On fail goto*//*Label 14673*/ GIMT_Encode4(914942), // Rule ID 4031 //
     /*  914890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  914893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  914898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914907 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914914 */     // MIs[0] cbsz
     /*  914914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914917 */     // MIs[0] abid
     /*  914917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914920 */     // MIs[0] blgp
     /*  914920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914923 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64),
     /*  914926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914928 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914930 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914932 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914934 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914936 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914938 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914940 */     GIR_RootConstrainSelectedInstOperands,
     /*  914941 */     // GIR_Coverage, 4031,
     /*  914941 */     GIR_EraseRootFromParent_Done,
     /*  914942 */   // Label 14673: @914942
     /*  914942 */   GIM_Try, /*On fail goto*//*Label 14674*/ GIMT_Encode4(914999), // Rule ID 4032 //
     /*  914947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  914950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  914955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  914958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  914961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  914964 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  914967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  914971 */     // MIs[0] cbsz
     /*  914971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  914974 */     // MIs[0] abid
     /*  914974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  914977 */     // MIs[0] blgp
     /*  914977 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  914980 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  914980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64),
     /*  914983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  914985 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  914987 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  914989 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  914991 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  914993 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  914995 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  914997 */     GIR_RootConstrainSelectedInstOperands,
     /*  914998 */     // GIR_Coverage, 4032,
     /*  914998 */     GIR_EraseRootFromParent_Done,
     /*  914999 */   // Label 14674: @914999
     /*  914999 */   GIM_Try, /*On fail goto*//*Label 14675*/ GIMT_Encode4(915056), // Rule ID 4033 //
     /*  915004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  915007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
     /*  915012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915021 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915028 */     // MIs[0] cbsz
     /*  915028 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915031 */     // MIs[0] abid
     /*  915031 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915034 */     // MIs[0] blgp
     /*  915034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915037 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3287:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64),
     /*  915040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915042 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915044 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915046 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915048 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915050 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915052 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915054 */     GIR_RootConstrainSelectedInstOperands,
     /*  915055 */     // GIR_Coverage, 4033,
     /*  915055 */     GIR_EraseRootFromParent_Done,
     /*  915056 */   // Label 14675: @915056
     /*  915056 */   GIM_Try, /*On fail goto*//*Label 14676*/ GIMT_Encode4(915113), // Rule ID 4039 //
     /*  915061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  915064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  915069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915078 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915085 */     // MIs[0] cbsz
     /*  915085 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915088 */     // MIs[0] abid
     /*  915088 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915091 */     // MIs[0] blgp
     /*  915091 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915094 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64),
     /*  915097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915099 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915101 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915103 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915105 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915107 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915109 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915111 */     GIR_RootConstrainSelectedInstOperands,
     /*  915112 */     // GIR_Coverage, 4039,
     /*  915112 */     GIR_EraseRootFromParent_Done,
     /*  915113 */   // Label 14676: @915113
     /*  915113 */   GIM_Try, /*On fail goto*//*Label 14677*/ GIMT_Encode4(915170), // Rule ID 4040 //
     /*  915118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  915121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  915126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915135 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915142 */     // MIs[0] cbsz
     /*  915142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915145 */     // MIs[0] abid
     /*  915145 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915148 */     // MIs[0] blgp
     /*  915148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915151 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64),
     /*  915154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915156 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915158 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915160 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915162 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915164 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915166 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915168 */     GIR_RootConstrainSelectedInstOperands,
     /*  915169 */     // GIR_Coverage, 4040,
     /*  915169 */     GIR_EraseRootFromParent_Done,
     /*  915170 */   // Label 14677: @915170
     /*  915170 */   GIM_Try, /*On fail goto*//*Label 14678*/ GIMT_Encode4(915227), // Rule ID 4041 //
     /*  915175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  915178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  915183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915192 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915199 */     // MIs[0] cbsz
     /*  915199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915202 */     // MIs[0] abid
     /*  915202 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915205 */     // MIs[0] blgp
     /*  915205 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915208 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64),
     /*  915211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915213 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915215 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915217 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915219 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915221 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915223 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915225 */     GIR_RootConstrainSelectedInstOperands,
     /*  915226 */     // GIR_Coverage, 4041,
     /*  915226 */     GIR_EraseRootFromParent_Done,
     /*  915227 */   // Label 14678: @915227
     /*  915227 */   GIM_Try, /*On fail goto*//*Label 14679*/ GIMT_Encode4(915284), // Rule ID 4042 //
     /*  915232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  915235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  915240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915246 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915249 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915256 */     // MIs[0] cbsz
     /*  915256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915259 */     // MIs[0] abid
     /*  915259 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915262 */     // MIs[0] blgp
     /*  915262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915265 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64),
     /*  915268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915270 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915272 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915274 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915276 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915278 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915280 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915282 */     GIR_RootConstrainSelectedInstOperands,
     /*  915283 */     // GIR_Coverage, 4042,
     /*  915283 */     GIR_EraseRootFromParent_Done,
     /*  915284 */   // Label 14679: @915284
     /*  915284 */   GIM_Try, /*On fail goto*//*Label 14680*/ GIMT_Encode4(915341), // Rule ID 4043 //
     /*  915289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  915292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
     /*  915297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915306 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915313 */     // MIs[0] cbsz
     /*  915313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915316 */     // MIs[0] abid
     /*  915316 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915319 */     // MIs[0] blgp
     /*  915319 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915322 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3289:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64),
     /*  915325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915327 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915329 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915331 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915333 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915335 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915337 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915339 */     GIR_RootConstrainSelectedInstOperands,
     /*  915340 */     // GIR_Coverage, 4043,
     /*  915340 */     GIR_EraseRootFromParent_Done,
     /*  915341 */   // Label 14680: @915341
     /*  915341 */   GIM_Try, /*On fail goto*//*Label 14681*/ GIMT_Encode4(915398), // Rule ID 4049 //
     /*  915346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  915349 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  915354 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915357 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915360 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915363 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915370 */     // MIs[0] cbsz
     /*  915370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915373 */     // MIs[0] abid
     /*  915373 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915376 */     // MIs[0] blgp
     /*  915376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915379 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64),
     /*  915382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915384 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915386 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915388 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915390 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915392 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915394 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915396 */     GIR_RootConstrainSelectedInstOperands,
     /*  915397 */     // GIR_Coverage, 4049,
     /*  915397 */     GIR_EraseRootFromParent_Done,
     /*  915398 */   // Label 14681: @915398
     /*  915398 */   GIM_Try, /*On fail goto*//*Label 14682*/ GIMT_Encode4(915455), // Rule ID 4050 //
     /*  915403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  915406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  915411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915420 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915427 */     // MIs[0] cbsz
     /*  915427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915430 */     // MIs[0] abid
     /*  915430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915433 */     // MIs[0] blgp
     /*  915433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915436 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64),
     /*  915439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915441 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915443 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915445 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915447 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915449 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915451 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915453 */     GIR_RootConstrainSelectedInstOperands,
     /*  915454 */     // GIR_Coverage, 4050,
     /*  915454 */     GIR_EraseRootFromParent_Done,
     /*  915455 */   // Label 14682: @915455
     /*  915455 */   GIM_Try, /*On fail goto*//*Label 14683*/ GIMT_Encode4(915512), // Rule ID 4051 //
     /*  915460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  915463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  915468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915484 */     // MIs[0] cbsz
     /*  915484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915487 */     // MIs[0] abid
     /*  915487 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915490 */     // MIs[0] blgp
     /*  915490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915493 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64),
     /*  915496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915498 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915500 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915502 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915504 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915506 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915508 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915510 */     GIR_RootConstrainSelectedInstOperands,
     /*  915511 */     // GIR_Coverage, 4051,
     /*  915511 */     GIR_EraseRootFromParent_Done,
     /*  915512 */   // Label 14683: @915512
     /*  915512 */   GIM_Try, /*On fail goto*//*Label 14684*/ GIMT_Encode4(915569), // Rule ID 4052 //
     /*  915517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  915520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  915525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915528 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915531 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915534 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915541 */     // MIs[0] cbsz
     /*  915541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915544 */     // MIs[0] abid
     /*  915544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915547 */     // MIs[0] blgp
     /*  915547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915550 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64),
     /*  915553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915555 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915557 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915559 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915561 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915563 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915565 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915567 */     GIR_RootConstrainSelectedInstOperands,
     /*  915568 */     // GIR_Coverage, 4052,
     /*  915568 */     GIR_EraseRootFromParent_Done,
     /*  915569 */   // Label 14684: @915569
     /*  915569 */   GIM_Try, /*On fail goto*//*Label 14685*/ GIMT_Encode4(915626), // Rule ID 4053 //
     /*  915574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  915577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
     /*  915582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  915585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915591 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  915594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  915598 */     // MIs[0] cbsz
     /*  915598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915601 */     // MIs[0] abid
     /*  915601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915604 */     // MIs[0] blgp
     /*  915604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915607 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3290:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64),
     /*  915610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915612 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915614 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915616 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915618 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915620 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915622 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915624 */     GIR_RootConstrainSelectedInstOperands,
     /*  915625 */     // GIR_Coverage, 4053,
     /*  915625 */     GIR_EraseRootFromParent_Done,
     /*  915626 */   // Label 14685: @915626
     /*  915626 */   GIM_Try, /*On fail goto*//*Label 14686*/ GIMT_Encode4(915683), // Rule ID 4059 //
     /*  915631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  915634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  915639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915645 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915648 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915655 */     // MIs[0] cbsz
     /*  915655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915658 */     // MIs[0] abid
     /*  915658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915661 */     // MIs[0] blgp
     /*  915661 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915664 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64),
     /*  915667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915669 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915671 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915673 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915675 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915677 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915679 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915681 */     GIR_RootConstrainSelectedInstOperands,
     /*  915682 */     // GIR_Coverage, 4059,
     /*  915682 */     GIR_EraseRootFromParent_Done,
     /*  915683 */   // Label 14686: @915683
     /*  915683 */   GIM_Try, /*On fail goto*//*Label 14687*/ GIMT_Encode4(915740), // Rule ID 4060 //
     /*  915688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  915691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  915696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915705 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915712 */     // MIs[0] cbsz
     /*  915712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915715 */     // MIs[0] abid
     /*  915715 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915718 */     // MIs[0] blgp
     /*  915718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915721 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64),
     /*  915724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915726 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915728 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915730 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915732 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915734 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915736 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915738 */     GIR_RootConstrainSelectedInstOperands,
     /*  915739 */     // GIR_Coverage, 4060,
     /*  915739 */     GIR_EraseRootFromParent_Done,
     /*  915740 */   // Label 14687: @915740
     /*  915740 */   GIM_Try, /*On fail goto*//*Label 14688*/ GIMT_Encode4(915797), // Rule ID 4061 //
     /*  915745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  915748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  915753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915762 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915769 */     // MIs[0] cbsz
     /*  915769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915772 */     // MIs[0] abid
     /*  915772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915775 */     // MIs[0] blgp
     /*  915775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915778 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64),
     /*  915781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915783 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915785 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915787 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915789 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915791 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915793 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915795 */     GIR_RootConstrainSelectedInstOperands,
     /*  915796 */     // GIR_Coverage, 4061,
     /*  915796 */     GIR_EraseRootFromParent_Done,
     /*  915797 */   // Label 14688: @915797
     /*  915797 */   GIM_Try, /*On fail goto*//*Label 14689*/ GIMT_Encode4(915854), // Rule ID 4062 //
     /*  915802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  915805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  915810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915819 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915826 */     // MIs[0] cbsz
     /*  915826 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915829 */     // MIs[0] abid
     /*  915829 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915832 */     // MIs[0] blgp
     /*  915832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915835 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64),
     /*  915838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915840 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915842 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915844 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915846 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915848 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915850 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915852 */     GIR_RootConstrainSelectedInstOperands,
     /*  915853 */     // GIR_Coverage, 4062,
     /*  915853 */     GIR_EraseRootFromParent_Done,
     /*  915854 */   // Label 14689: @915854
     /*  915854 */   GIM_Try, /*On fail goto*//*Label 14690*/ GIMT_Encode4(915911), // Rule ID 4063 //
     /*  915859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  915862 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
     /*  915867 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915870 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915873 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915876 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915883 */     // MIs[0] cbsz
     /*  915883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915886 */     // MIs[0] abid
     /*  915886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915889 */     // MIs[0] blgp
     /*  915889 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915892 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3297:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64),
     /*  915895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915897 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915899 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915901 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915903 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915905 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915907 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915909 */     GIR_RootConstrainSelectedInstOperands,
     /*  915910 */     // GIR_Coverage, 4063,
     /*  915910 */     GIR_EraseRootFromParent_Done,
     /*  915911 */   // Label 14690: @915911
     /*  915911 */   GIM_Try, /*On fail goto*//*Label 14691*/ GIMT_Encode4(915968), // Rule ID 4069 //
     /*  915916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  915919 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  915924 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915927 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915930 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915933 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915940 */     // MIs[0] cbsz
     /*  915940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  915943 */     // MIs[0] abid
     /*  915943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  915946 */     // MIs[0] blgp
     /*  915946 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  915949 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  915949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64),
     /*  915952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  915954 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  915956 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  915958 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  915960 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  915962 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  915964 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  915966 */     GIR_RootConstrainSelectedInstOperands,
     /*  915967 */     // GIR_Coverage, 4069,
     /*  915967 */     GIR_EraseRootFromParent_Done,
     /*  915968 */   // Label 14691: @915968
     /*  915968 */   GIM_Try, /*On fail goto*//*Label 14692*/ GIMT_Encode4(916025), // Rule ID 4070 //
     /*  915973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  915976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  915981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  915984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  915987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  915990 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  915993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  915997 */     // MIs[0] cbsz
     /*  915997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916000 */     // MIs[0] abid
     /*  916000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916003 */     // MIs[0] blgp
     /*  916003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916006 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64),
     /*  916009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916011 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916013 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916015 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916017 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916019 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916021 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916023 */     GIR_RootConstrainSelectedInstOperands,
     /*  916024 */     // GIR_Coverage, 4070,
     /*  916024 */     GIR_EraseRootFromParent_Done,
     /*  916025 */   // Label 14692: @916025
     /*  916025 */   GIM_Try, /*On fail goto*//*Label 14693*/ GIMT_Encode4(916082), // Rule ID 4071 //
     /*  916030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  916033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  916038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916047 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916054 */     // MIs[0] cbsz
     /*  916054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916057 */     // MIs[0] abid
     /*  916057 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916060 */     // MIs[0] blgp
     /*  916060 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916063 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64),
     /*  916066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916068 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916070 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916072 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916074 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916076 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916078 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916080 */     GIR_RootConstrainSelectedInstOperands,
     /*  916081 */     // GIR_Coverage, 4071,
     /*  916081 */     GIR_EraseRootFromParent_Done,
     /*  916082 */   // Label 14693: @916082
     /*  916082 */   GIM_Try, /*On fail goto*//*Label 14694*/ GIMT_Encode4(916139), // Rule ID 4072 //
     /*  916087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  916090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  916095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916104 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916111 */     // MIs[0] cbsz
     /*  916111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916114 */     // MIs[0] abid
     /*  916114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916117 */     // MIs[0] blgp
     /*  916117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916120 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64),
     /*  916123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916125 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916127 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916129 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916131 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916133 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916135 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916137 */     GIR_RootConstrainSelectedInstOperands,
     /*  916138 */     // GIR_Coverage, 4072,
     /*  916138 */     GIR_EraseRootFromParent_Done,
     /*  916139 */   // Label 14694: @916139
     /*  916139 */   GIM_Try, /*On fail goto*//*Label 14695*/ GIMT_Encode4(916196), // Rule ID 4073 //
     /*  916144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  916147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
     /*  916152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916161 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916168 */     // MIs[0] cbsz
     /*  916168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916171 */     // MIs[0] abid
     /*  916171 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916174 */     // MIs[0] blgp
     /*  916174 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916177 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3298:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64),
     /*  916180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916182 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916184 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916186 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916188 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916190 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916192 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916194 */     GIR_RootConstrainSelectedInstOperands,
     /*  916195 */     // GIR_Coverage, 4073,
     /*  916195 */     GIR_EraseRootFromParent_Done,
     /*  916196 */   // Label 14695: @916196
     /*  916196 */   GIM_Try, /*On fail goto*//*Label 14696*/ GIMT_Encode4(916253), // Rule ID 4079 //
     /*  916201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  916204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  916209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916218 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916225 */     // MIs[0] cbsz
     /*  916225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916228 */     // MIs[0] abid
     /*  916228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916231 */     // MIs[0] blgp
     /*  916231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916234 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64),
     /*  916237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916239 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916241 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916243 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916245 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916247 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916249 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916251 */     GIR_RootConstrainSelectedInstOperands,
     /*  916252 */     // GIR_Coverage, 4079,
     /*  916252 */     GIR_EraseRootFromParent_Done,
     /*  916253 */   // Label 14696: @916253
     /*  916253 */   GIM_Try, /*On fail goto*//*Label 14697*/ GIMT_Encode4(916310), // Rule ID 4080 //
     /*  916258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  916261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  916266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916275 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916282 */     // MIs[0] cbsz
     /*  916282 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916285 */     // MIs[0] abid
     /*  916285 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916288 */     // MIs[0] blgp
     /*  916288 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916291 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64),
     /*  916294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916296 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916298 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916300 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916302 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916304 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916306 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916308 */     GIR_RootConstrainSelectedInstOperands,
     /*  916309 */     // GIR_Coverage, 4080,
     /*  916309 */     GIR_EraseRootFromParent_Done,
     /*  916310 */   // Label 14697: @916310
     /*  916310 */   GIM_Try, /*On fail goto*//*Label 14698*/ GIMT_Encode4(916367), // Rule ID 4081 //
     /*  916315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  916318 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  916323 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916326 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916329 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916332 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916339 */     // MIs[0] cbsz
     /*  916339 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916342 */     // MIs[0] abid
     /*  916342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916345 */     // MIs[0] blgp
     /*  916345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916348 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64),
     /*  916351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916353 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916355 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916357 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916359 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916361 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916363 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916365 */     GIR_RootConstrainSelectedInstOperands,
     /*  916366 */     // GIR_Coverage, 4081,
     /*  916366 */     GIR_EraseRootFromParent_Done,
     /*  916367 */   // Label 14698: @916367
     /*  916367 */   GIM_Try, /*On fail goto*//*Label 14699*/ GIMT_Encode4(916424), // Rule ID 4082 //
     /*  916372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  916375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  916380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916389 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916396 */     // MIs[0] cbsz
     /*  916396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916399 */     // MIs[0] abid
     /*  916399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916402 */     // MIs[0] blgp
     /*  916402 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916405 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64),
     /*  916408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916410 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916412 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916414 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916416 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916418 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916420 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916422 */     GIR_RootConstrainSelectedInstOperands,
     /*  916423 */     // GIR_Coverage, 4082,
     /*  916423 */     GIR_EraseRootFromParent_Done,
     /*  916424 */   // Label 14699: @916424
     /*  916424 */   GIM_Try, /*On fail goto*//*Label 14700*/ GIMT_Encode4(916481), // Rule ID 4083 //
     /*  916429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  916432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
     /*  916437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916453 */     // MIs[0] cbsz
     /*  916453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916456 */     // MIs[0] abid
     /*  916456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916459 */     // MIs[0] blgp
     /*  916459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916462 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3300:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64),
     /*  916465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916467 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916469 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916471 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916473 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916475 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916477 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916479 */     GIR_RootConstrainSelectedInstOperands,
     /*  916480 */     // GIR_Coverage, 4083,
     /*  916480 */     GIR_EraseRootFromParent_Done,
     /*  916481 */   // Label 14700: @916481
     /*  916481 */   GIM_Try, /*On fail goto*//*Label 14701*/ GIMT_Encode4(916538), // Rule ID 4089 //
     /*  916486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode0),
     /*  916489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  916494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916500 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916503 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916510 */     // MIs[0] cbsz
     /*  916510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916513 */     // MIs[0] abid
     /*  916513 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916516 */     // MIs[0] blgp
     /*  916516 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916519 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64),
     /*  916522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916524 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916526 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916528 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916530 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916532 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916534 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916536 */     GIR_RootConstrainSelectedInstOperands,
     /*  916537 */     // GIR_Coverage, 4089,
     /*  916537 */     GIR_EraseRootFromParent_Done,
     /*  916538 */   // Label 14701: @916538
     /*  916538 */   GIM_Try, /*On fail goto*//*Label 14702*/ GIMT_Encode4(916595), // Rule ID 4090 //
     /*  916543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode1),
     /*  916546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  916551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916557 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916560 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916567 */     // MIs[0] cbsz
     /*  916567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916570 */     // MIs[0] abid
     /*  916570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916573 */     // MIs[0] blgp
     /*  916573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916576 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64),
     /*  916579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916581 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916583 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916585 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916587 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916589 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916591 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916593 */     GIR_RootConstrainSelectedInstOperands,
     /*  916594 */     // GIR_Coverage, 4090,
     /*  916594 */     GIR_EraseRootFromParent_Done,
     /*  916595 */   // Label 14702: @916595
     /*  916595 */   GIM_Try, /*On fail goto*//*Label 14703*/ GIMT_Encode4(916652), // Rule ID 4091 //
     /*  916600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode2),
     /*  916603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  916608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916624 */     // MIs[0] cbsz
     /*  916624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916627 */     // MIs[0] abid
     /*  916627 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916630 */     // MIs[0] blgp
     /*  916630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916633 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64),
     /*  916636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916638 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916640 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916642 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916644 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916646 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916648 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916650 */     GIR_RootConstrainSelectedInstOperands,
     /*  916651 */     // GIR_Coverage, 4091,
     /*  916651 */     GIR_EraseRootFromParent_Done,
     /*  916652 */   // Label 14703: @916652
     /*  916652 */   GIM_Try, /*On fail goto*//*Label 14704*/ GIMT_Encode4(916709), // Rule ID 4092 //
     /*  916657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode3),
     /*  916660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  916665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916674 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916681 */     // MIs[0] cbsz
     /*  916681 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916684 */     // MIs[0] abid
     /*  916684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916687 */     // MIs[0] blgp
     /*  916687 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916690 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64),
     /*  916693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916695 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916697 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916699 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916701 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916703 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916705 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916707 */     GIR_RootConstrainSelectedInstOperands,
     /*  916708 */     // GIR_Coverage, 4092,
     /*  916708 */     GIR_EraseRootFromParent_Done,
     /*  916709 */   // Label 14704: @916709
     /*  916709 */   GIM_Try, /*On fail goto*//*Label 14705*/ GIMT_Encode4(916766), // Rule ID 4093 //
     /*  916714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts_isGFX90APlus_HwMode4),
     /*  916717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
     /*  916722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  916728 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  916731 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  916738 */     // MIs[0] cbsz
     /*  916738 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  916741 */     // MIs[0] abid
     /*  916741 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916744 */     // MIs[0] blgp
     /*  916744 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916747 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3301:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
     /*  916747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64),
     /*  916750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916752 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916754 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916756 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916758 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  916760 */     GIR_RootToRootCopy, /*OpIdx*/6, // abid
     /*  916762 */     GIR_RootToRootCopy, /*OpIdx*/7, // blgp
     /*  916764 */     GIR_RootConstrainSelectedInstOperands,
     /*  916765 */     // GIR_Coverage, 4093,
     /*  916765 */     GIR_EraseRootFromParent_Done,
     /*  916766 */   // Label 14705: @916766
     /*  916766 */   GIM_Try, /*On fail goto*//*Label 14706*/ GIMT_Encode4(916823), // Rule ID 4094 //
     /*  916771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
     /*  916774 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x32_f16),
     /*  916779 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  916782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  916785 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  916788 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  916791 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  916794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  916798 */     // MIs[0] cbsz
     /*  916798 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916801 */     // MIs[0] abid
     /*  916801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916804 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3495:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X32_F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  916804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X32_F16_e64),
     /*  916807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916809 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916811 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916813 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  916815 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  916817 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  916819 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916821 */     GIR_RootConstrainSelectedInstOperands,
     /*  916822 */     // GIR_Coverage, 4094,
     /*  916822 */     GIR_EraseRootFromParent_Done,
     /*  916823 */   // Label 14706: @916823
     /*  916823 */   GIM_Try, /*On fail goto*//*Label 14707*/ GIMT_Encode4(916880), // Rule ID 4095 //
     /*  916828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
     /*  916831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x16_f16),
     /*  916836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  916842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  916845 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916848 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  916851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  916855 */     // MIs[0] cbsz
     /*  916855 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916858 */     // MIs[0] abid
     /*  916858 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916861 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3503:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X16_F16_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  916861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X16_F16_e64),
     /*  916864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916866 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916868 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916870 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  916872 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  916874 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  916876 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916878 */     GIR_RootConstrainSelectedInstOperands,
     /*  916879 */     // GIR_Coverage, 4095,
     /*  916879 */     GIR_EraseRootFromParent_Done,
     /*  916880 */   // Label 14707: @916880
     /*  916880 */   GIM_Try, /*On fail goto*//*Label 14708*/ GIMT_Encode4(916937), // Rule ID 4096 //
     /*  916885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
     /*  916888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x32_bf16),
     /*  916893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  916896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  916899 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  916902 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  916905 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  916908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  916912 */     // MIs[0] cbsz
     /*  916912 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916915 */     // MIs[0] abid
     /*  916915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916918 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3494:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X32_BF16_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  916918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X32_BF16_e64),
     /*  916921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916923 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916925 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916927 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  916929 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  916931 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  916933 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916935 */     GIR_RootConstrainSelectedInstOperands,
     /*  916936 */     // GIR_Coverage, 4096,
     /*  916936 */     GIR_EraseRootFromParent_Done,
     /*  916937 */   // Label 14708: @916937
     /*  916937 */   GIM_Try, /*On fail goto*//*Label 14709*/ GIMT_Encode4(916994), // Rule ID 4097 //
     /*  916942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
     /*  916945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x16_bf16),
     /*  916950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  916953 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  916956 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  916959 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  916962 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  916965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  916969 */     // MIs[0] cbsz
     /*  916969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  916972 */     // MIs[0] abid
     /*  916972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  916975 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3502:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X16_BF16_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  916975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X16_BF16_e64),
     /*  916978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  916980 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  916982 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  916984 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  916986 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  916988 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  916990 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  916992 */     GIR_RootConstrainSelectedInstOperands,
     /*  916993 */     // GIR_Coverage, 4097,
     /*  916993 */     GIR_EraseRootFromParent_Done,
     /*  916994 */   // Label 14709: @916994
     /*  916994 */   GIM_Try, /*On fail goto*//*Label 14710*/ GIMT_Encode4(917051), // Rule ID 4098 //
     /*  916999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
     /*  917002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_16x16x64_i8),
     /*  917007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917016 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917019 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917026 */     // MIs[0] cbsz
     /*  917026 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917029 */     // MIs[0] abid
     /*  917029 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917032 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3515:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_I32_16X16X64_I8_e64:{ *:[v4i32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4i32:{ *:[v4i32] }:$src2)
     /*  917032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_16X16X64_I8_e64),
     /*  917035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917037 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917039 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917041 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917043 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917045 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917047 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917049 */     GIR_RootConstrainSelectedInstOperands,
     /*  917050 */     // GIR_Coverage, 4098,
     /*  917050 */     GIR_EraseRootFromParent_Done,
     /*  917051 */   // Label 14710: @917051
     /*  917051 */   GIM_Try, /*On fail goto*//*Label 14711*/ GIMT_Encode4(917108), // Rule ID 4099 //
     /*  917056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
     /*  917059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_32x32x32_i8),
     /*  917064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917070 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917073 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917076 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917083 */     // MIs[0] cbsz
     /*  917083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917086 */     // MIs[0] abid
     /*  917086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917089 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3516:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_I32_32X32X32_I8_e64:{ *:[v16i32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16i32:{ *:[v16i32] }:$src2)
     /*  917089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_32X32X32_I8_e64),
     /*  917092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917094 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917096 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917098 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917100 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917102 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917104 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917106 */     GIR_RootConstrainSelectedInstOperands,
     /*  917107 */     // GIR_Coverage, 4099,
     /*  917107 */     GIR_EraseRootFromParent_Done,
     /*  917108 */   // Label 14711: @917108
     /*  917108 */   GIM_Try, /*On fail goto*//*Label 14712*/ GIMT_Encode4(917165), // Rule ID 4100 //
     /*  917113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_bf8_bf8),
     /*  917121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917130 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917133 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917140 */     // MIs[0] cbsz
     /*  917140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917143 */     // MIs[0] abid
     /*  917143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917146 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3497:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_BF8_BF8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_BF8_BF8_e64),
     /*  917149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917151 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917153 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917155 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917157 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917159 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917161 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917163 */     GIR_RootConstrainSelectedInstOperands,
     /*  917164 */     // GIR_Coverage, 4100,
     /*  917164 */     GIR_EraseRootFromParent_Done,
     /*  917165 */   // Label 14712: @917165
     /*  917165 */   GIM_Try, /*On fail goto*//*Label 14713*/ GIMT_Encode4(917222), // Rule ID 4101 //
     /*  917170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_bf8_fp8),
     /*  917178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917187 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917190 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917197 */     // MIs[0] cbsz
     /*  917197 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917200 */     // MIs[0] abid
     /*  917200 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917203 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3498:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_BF8_FP8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_BF8_FP8_e64),
     /*  917206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917208 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917210 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917212 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917214 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917216 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917218 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917220 */     GIR_RootConstrainSelectedInstOperands,
     /*  917221 */     // GIR_Coverage, 4101,
     /*  917221 */     GIR_EraseRootFromParent_Done,
     /*  917222 */   // Label 14713: @917222
     /*  917222 */   GIM_Try, /*On fail goto*//*Label 14714*/ GIMT_Encode4(917279), // Rule ID 4102 //
     /*  917227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_fp8_bf8),
     /*  917235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917244 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917247 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917254 */     // MIs[0] cbsz
     /*  917254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917257 */     // MIs[0] abid
     /*  917257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917260 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3500:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_FP8_BF8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_FP8_BF8_e64),
     /*  917263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917265 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917267 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917269 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917271 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917273 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917275 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917277 */     GIR_RootConstrainSelectedInstOperands,
     /*  917278 */     // GIR_Coverage, 4102,
     /*  917278 */     GIR_EraseRootFromParent_Done,
     /*  917279 */   // Label 14714: @917279
     /*  917279 */   GIM_Try, /*On fail goto*//*Label 14715*/ GIMT_Encode4(917336), // Rule ID 4103 //
     /*  917284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_fp8_fp8),
     /*  917292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917298 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917301 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917304 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917311 */     // MIs[0] cbsz
     /*  917311 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917314 */     // MIs[0] abid
     /*  917314 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917317 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3501:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_FP8_FP8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_FP8_FP8_e64),
     /*  917320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917322 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917324 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917326 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917328 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917330 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917332 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917334 */     GIR_RootConstrainSelectedInstOperands,
     /*  917335 */     // GIR_Coverage, 4103,
     /*  917335 */     GIR_EraseRootFromParent_Done,
     /*  917336 */   // Label 14715: @917336
     /*  917336 */   GIM_Try, /*On fail goto*//*Label 14716*/ GIMT_Encode4(917393), // Rule ID 4104 //
     /*  917341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_bf8_bf8),
     /*  917349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917352 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917355 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917358 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917361 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917368 */     // MIs[0] cbsz
     /*  917368 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917371 */     // MIs[0] abid
     /*  917371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917374 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3505:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_BF8_BF8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  917374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_BF8_BF8_e64),
     /*  917377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917379 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917381 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917383 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917385 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917387 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917389 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917391 */     GIR_RootConstrainSelectedInstOperands,
     /*  917392 */     // GIR_Coverage, 4104,
     /*  917392 */     GIR_EraseRootFromParent_Done,
     /*  917393 */   // Label 14716: @917393
     /*  917393 */   GIM_Try, /*On fail goto*//*Label 14717*/ GIMT_Encode4(917450), // Rule ID 4105 //
     /*  917398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_bf8_fp8),
     /*  917406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917415 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917418 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917425 */     // MIs[0] cbsz
     /*  917425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917428 */     // MIs[0] abid
     /*  917428 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917431 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3506:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_BF8_FP8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  917431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_BF8_FP8_e64),
     /*  917434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917436 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917438 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917440 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917442 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917444 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917446 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917448 */     GIR_RootConstrainSelectedInstOperands,
     /*  917449 */     // GIR_Coverage, 4105,
     /*  917449 */     GIR_EraseRootFromParent_Done,
     /*  917450 */   // Label 14717: @917450
     /*  917450 */   GIM_Try, /*On fail goto*//*Label 14718*/ GIMT_Encode4(917507), // Rule ID 4106 //
     /*  917455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_fp8_bf8),
     /*  917463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917472 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917475 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917482 */     // MIs[0] cbsz
     /*  917482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917485 */     // MIs[0] abid
     /*  917485 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917488 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3508:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_FP8_BF8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  917488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_FP8_BF8_e64),
     /*  917491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917493 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917495 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917497 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917499 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917501 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917503 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917505 */     GIR_RootConstrainSelectedInstOperands,
     /*  917506 */     // GIR_Coverage, 4106,
     /*  917506 */     GIR_EraseRootFromParent_Done,
     /*  917507 */   // Label 14718: @917507
     /*  917507 */   GIM_Try, /*On fail goto*//*Label 14719*/ GIMT_Encode4(917564), // Rule ID 4107 //
     /*  917512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8Insts),
     /*  917515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_fp8_fp8),
     /*  917520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  917526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  917529 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917532 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917539 */     // MIs[0] cbsz
     /*  917539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917542 */     // MIs[0] abid
     /*  917542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917545 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3509:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_FP8_FP8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  917545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_FP8_FP8_e64),
     /*  917548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917550 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917552 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917554 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917556 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917558 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917560 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917562 */     GIR_RootConstrainSelectedInstOperands,
     /*  917563 */     // GIR_Coverage, 4107,
     /*  917563 */     GIR_EraseRootFromParent_Done,
     /*  917564 */   // Label 14719: @917564
     /*  917564 */   GIM_Try, /*On fail goto*//*Label 14720*/ GIMT_Encode4(917621), // Rule ID 4108 //
     /*  917569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_f16),
     /*  917577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  917583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  917586 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917589 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917596 */     // MIs[0] cbsz
     /*  917596 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917599 */     // MIs[0] abid
     /*  917599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917602 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3499:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_F16_e64:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_F16_e64),
     /*  917605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917607 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917609 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917611 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917613 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917615 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917617 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917619 */     GIR_RootConstrainSelectedInstOperands,
     /*  917620 */     // GIR_Coverage, 4108,
     /*  917620 */     GIR_EraseRootFromParent_Done,
     /*  917621 */   // Label 14720: @917621
     /*  917621 */   GIM_Try, /*On fail goto*//*Label 14721*/ GIMT_Encode4(917678), // Rule ID 4109 //
     /*  917626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917629 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_f16),
     /*  917634 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917637 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  917640 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  917643 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917646 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917653 */     // MIs[0] cbsz
     /*  917653 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917656 */     // MIs[0] abid
     /*  917656 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917659 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3507:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_F16_e64:{ *:[v16f32] } v8f16:{ *:[v8f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  917659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_F16_e64),
     /*  917662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917664 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917666 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917668 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917670 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917672 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917674 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917676 */     GIR_RootConstrainSelectedInstOperands,
     /*  917677 */     // GIR_Coverage, 4109,
     /*  917677 */     GIR_EraseRootFromParent_Done,
     /*  917678 */   // Label 14721: @917678
     /*  917678 */   GIM_Try, /*On fail goto*//*Label 14722*/ GIMT_Encode4(917735), // Rule ID 4110 //
     /*  917683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_16x16x128_i8),
     /*  917691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917694 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  917697 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  917700 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917703 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917710 */     // MIs[0] cbsz
     /*  917710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917713 */     // MIs[0] abid
     /*  917713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917716 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3514:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_I32_16X16X128_I8_e64:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4i32:{ *:[v4i32] }:$src2)
     /*  917716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_16X16X128_I8_e64),
     /*  917719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917721 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917723 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917725 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917727 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917729 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917731 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917733 */     GIR_RootConstrainSelectedInstOperands,
     /*  917734 */     // GIR_Coverage, 4110,
     /*  917734 */     GIR_EraseRootFromParent_Done,
     /*  917735 */   // Label 14722: @917735
     /*  917735 */   GIM_Try, /*On fail goto*//*Label 14723*/ GIMT_Encode4(917792), // Rule ID 4111 //
     /*  917740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_32x32x64_i8),
     /*  917748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  917751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  917754 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  917757 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  917760 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  917767 */     // MIs[0] cbsz
     /*  917767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917770 */     // MIs[0] abid
     /*  917770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917773 */     // (intrinsic_wo_chain:{ *:[v16i32] } 3517:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_I32_32X32X64_I8_e64:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16i32:{ *:[v16i32] }:$src2)
     /*  917773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_32X32X64_I8_e64),
     /*  917776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917778 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917780 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917782 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917784 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917786 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917788 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917790 */     GIR_RootConstrainSelectedInstOperands,
     /*  917791 */     // GIR_Coverage, 4111,
     /*  917791 */     GIR_EraseRootFromParent_Done,
     /*  917792 */   // Label 14723: @917792
     /*  917792 */   GIM_Try, /*On fail goto*//*Label 14724*/ GIMT_Encode4(917849), // Rule ID 4112 //
     /*  917797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x128_bf8_bf8),
     /*  917805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  917811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  917814 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917817 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917824 */     // MIs[0] cbsz
     /*  917824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917827 */     // MIs[0] abid
     /*  917827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917830 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3490:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X128_BF8_BF8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X128_BF8_BF8_e64),
     /*  917833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917835 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917837 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917839 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917841 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917843 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917845 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917847 */     GIR_RootConstrainSelectedInstOperands,
     /*  917848 */     // GIR_Coverage, 4112,
     /*  917848 */     GIR_EraseRootFromParent_Done,
     /*  917849 */   // Label 14724: @917849
     /*  917849 */   GIM_Try, /*On fail goto*//*Label 14725*/ GIMT_Encode4(917906), // Rule ID 4113 //
     /*  917854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x128_bf8_fp8),
     /*  917862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  917868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  917871 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917874 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917881 */     // MIs[0] cbsz
     /*  917881 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917884 */     // MIs[0] abid
     /*  917884 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917887 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3491:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X128_BF8_FP8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X128_BF8_FP8_e64),
     /*  917890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917892 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917894 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917896 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917898 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917900 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917902 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917904 */     GIR_RootConstrainSelectedInstOperands,
     /*  917905 */     // GIR_Coverage, 4113,
     /*  917905 */     GIR_EraseRootFromParent_Done,
     /*  917906 */   // Label 14725: @917906
     /*  917906 */   GIM_Try, /*On fail goto*//*Label 14726*/ GIMT_Encode4(917963), // Rule ID 4114 //
     /*  917911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x128_fp8_bf8),
     /*  917919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  917925 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  917928 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917931 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917938 */     // MIs[0] cbsz
     /*  917938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917941 */     // MIs[0] abid
     /*  917941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  917944 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3492:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X128_FP8_BF8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  917944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X128_FP8_BF8_e64),
     /*  917947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  917949 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  917951 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  917953 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  917955 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  917957 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  917959 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  917961 */     GIR_RootConstrainSelectedInstOperands,
     /*  917962 */     // GIR_Coverage, 4114,
     /*  917962 */     GIR_EraseRootFromParent_Done,
     /*  917963 */   // Label 14726: @917963
     /*  917963 */   GIM_Try, /*On fail goto*//*Label 14727*/ GIMT_Encode4(918020), // Rule ID 4115 //
     /*  917968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  917971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x128_fp8_fp8),
     /*  917976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  917979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  917982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  917985 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  917988 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  917991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128_Align2RegClassID),
     /*  917995 */     // MIs[0] cbsz
     /*  917995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  917998 */     // MIs[0] abid
     /*  917998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  918001 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3493:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X128_FP8_FP8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
     /*  918001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X128_FP8_FP8_e64),
     /*  918004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918006 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  918008 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  918010 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  918012 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  918014 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  918016 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  918018 */     GIR_RootConstrainSelectedInstOperands,
     /*  918019 */     // GIR_Coverage, 4115,
     /*  918019 */     GIR_EraseRootFromParent_Done,
     /*  918020 */   // Label 14727: @918020
     /*  918020 */   GIM_Try, /*On fail goto*//*Label 14728*/ GIMT_Encode4(918077), // Rule ID 4116 //
     /*  918025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  918028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x64_bf8_bf8),
     /*  918033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  918036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  918039 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  918042 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  918045 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  918048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  918052 */     // MIs[0] cbsz
     /*  918052 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  918055 */     // MIs[0] abid
     /*  918055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  918058 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3510:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X64_BF8_BF8_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  918058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X64_BF8_BF8_e64),
     /*  918061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918063 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  918065 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  918067 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  918069 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  918071 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  918073 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  918075 */     GIR_RootConstrainSelectedInstOperands,
     /*  918076 */     // GIR_Coverage, 4116,
     /*  918076 */     GIR_EraseRootFromParent_Done,
     /*  918077 */   // Label 14728: @918077
     /*  918077 */   GIM_Try, /*On fail goto*//*Label 14729*/ GIMT_Encode4(918134), // Rule ID 4117 //
     /*  918082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  918085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x64_bf8_fp8),
     /*  918090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  918093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  918096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  918099 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  918102 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  918105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  918109 */     // MIs[0] cbsz
     /*  918109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  918112 */     // MIs[0] abid
     /*  918112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  918115 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3511:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X64_BF8_FP8_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  918115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X64_BF8_FP8_e64),
     /*  918118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918120 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  918122 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  918124 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  918126 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  918128 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  918130 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  918132 */     GIR_RootConstrainSelectedInstOperands,
     /*  918133 */     // GIR_Coverage, 4117,
     /*  918133 */     GIR_EraseRootFromParent_Done,
     /*  918134 */   // Label 14729: @918134
     /*  918134 */   GIM_Try, /*On fail goto*//*Label 14730*/ GIMT_Encode4(918191), // Rule ID 4118 //
     /*  918139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  918142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x64_fp8_bf8),
     /*  918147 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  918150 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  918153 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  918156 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  918159 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  918162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  918166 */     // MIs[0] cbsz
     /*  918166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  918169 */     // MIs[0] abid
     /*  918169 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  918172 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3512:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X64_FP8_BF8_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  918172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X64_FP8_BF8_e64),
     /*  918175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918177 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  918179 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  918181 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  918183 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  918185 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  918187 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  918189 */     GIR_RootConstrainSelectedInstOperands,
     /*  918190 */     // GIR_Coverage, 4118,
     /*  918190 */     GIR_EraseRootFromParent_Done,
     /*  918191 */   // Label 14730: @918191
     /*  918191 */   GIM_Try, /*On fail goto*//*Label 14731*/ GIMT_Encode4(918248), // Rule ID 4119 //
     /*  918196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts),
     /*  918199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x64_fp8_fp8),
     /*  918204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  918207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  918210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  918213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  918216 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  918219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512_Align2RegClassID),
     /*  918223 */     // MIs[0] cbsz
     /*  918223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  918226 */     // MIs[0] abid
     /*  918226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  918229 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3513:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X64_FP8_FP8_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
     /*  918229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X64_FP8_FP8_e64),
     /*  918232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918234 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  918236 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  918238 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /*  918240 */     GIR_RootToRootCopy, /*OpIdx*/6, // cbsz
     /*  918242 */     GIR_RootToRootCopy, /*OpIdx*/7, // abid
     /*  918244 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  918246 */     GIR_RootConstrainSelectedInstOperands,
     /*  918247 */     // GIR_Coverage, 4119,
     /*  918247 */     GIR_EraseRootFromParent_Done,
     /*  918248 */   // Label 14731: @918248
     /*  918248 */   GIM_Reject,
     /*  918249 */ // Label 13881: @918249
     /*  918249 */ GIM_Try, /*On fail goto*//*Label 14732*/ GIMT_Encode4(920733),
     /*  918254 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
     /*  918257 */   GIM_Try, /*On fail goto*//*Label 14733*/ GIMT_Encode4(918342), // Rule ID 7858 //
     /*  918262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  918265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  918270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  918276 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  918279 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918282 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918289 */     // MIs[0] src0_modifiers
     /*  918289 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918292 */     // MIs[0] src1_modifiers
     /*  918292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918295 */     // MIs[0] clamp
     /*  918295 */     // No operand predicates
     /*  918295 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918302 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr),
     /*  918305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918307 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918313 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918315 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918321 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918323 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918335 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918337 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918340 */     GIR_RootConstrainSelectedInstOperands,
     /*  918341 */     // GIR_Coverage, 7858,
     /*  918341 */     GIR_EraseRootFromParent_Done,
     /*  918342 */   // Label 14733: @918342
     /*  918342 */   GIM_Try, /*On fail goto*//*Label 14734*/ GIMT_Encode4(918427), // Rule ID 7859 //
     /*  918347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  918350 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  918355 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  918361 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  918364 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918367 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918374 */     // MIs[0] src0_modifiers
     /*  918374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918377 */     // MIs[0] src1_modifiers
     /*  918377 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918380 */     // MIs[0] clamp
     /*  918380 */     // No operand predicates
     /*  918380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918387 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr),
     /*  918390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918392 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918398 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918400 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918406 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918408 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918415 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918420 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918425 */     GIR_RootConstrainSelectedInstOperands,
     /*  918426 */     // GIR_Coverage, 7859,
     /*  918426 */     GIR_EraseRootFromParent_Done,
     /*  918427 */   // Label 14734: @918427
     /*  918427 */   GIM_Try, /*On fail goto*//*Label 14735*/ GIMT_Encode4(918512), // Rule ID 7860 //
     /*  918432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  918435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  918440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  918446 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  918449 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918452 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918459 */     // MIs[0] src0_modifiers
     /*  918459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918462 */     // MIs[0] src1_modifiers
     /*  918462 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918465 */     // MIs[0] clamp
     /*  918465 */     // No operand predicates
     /*  918465 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918472 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr),
     /*  918475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918477 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918483 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918485 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918491 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918493 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918505 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918510 */     GIR_RootConstrainSelectedInstOperands,
     /*  918511 */     // GIR_Coverage, 7860,
     /*  918511 */     GIR_EraseRootFromParent_Done,
     /*  918512 */   // Label 14735: @918512
     /*  918512 */   GIM_Try, /*On fail goto*//*Label 14736*/ GIMT_Encode4(918597), // Rule ID 7861 //
     /*  918517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  918520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  918525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  918531 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  918534 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918537 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918544 */     // MIs[0] src0_modifiers
     /*  918544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918547 */     // MIs[0] src1_modifiers
     /*  918547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918550 */     // MIs[0] clamp
     /*  918550 */     // No operand predicates
     /*  918550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918557 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr),
     /*  918560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918562 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918568 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918570 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918576 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918578 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918590 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918595 */     GIR_RootConstrainSelectedInstOperands,
     /*  918596 */     // GIR_Coverage, 7861,
     /*  918596 */     GIR_EraseRootFromParent_Done,
     /*  918597 */   // Label 14736: @918597
     /*  918597 */   GIM_Try, /*On fail goto*//*Label 14737*/ GIMT_Encode4(918682), // Rule ID 7862 //
     /*  918602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  918605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  918610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  918616 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  918619 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918622 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918629 */     // MIs[0] src0_modifiers
     /*  918629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918632 */     // MIs[0] src1_modifiers
     /*  918632 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918635 */     // MIs[0] clamp
     /*  918635 */     // No operand predicates
     /*  918635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918642 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr),
     /*  918645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918647 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918653 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918655 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918661 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918663 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918675 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918677 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918680 */     GIR_RootConstrainSelectedInstOperands,
     /*  918681 */     // GIR_Coverage, 7862,
     /*  918681 */     GIR_EraseRootFromParent_Done,
     /*  918682 */   // Label 14737: @918682
     /*  918682 */   GIM_Try, /*On fail goto*//*Label 14738*/ GIMT_Encode4(918767), // Rule ID 7863 //
     /*  918687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  918690 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  918695 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  918701 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  918704 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918707 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918714 */     // MIs[0] src0_modifiers
     /*  918714 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918717 */     // MIs[0] src1_modifiers
     /*  918717 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918720 */     // MIs[0] clamp
     /*  918720 */     // No operand predicates
     /*  918720 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918727 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr),
     /*  918730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918732 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918738 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918740 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918746 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918748 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918755 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918760 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918762 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918765 */     GIR_RootConstrainSelectedInstOperands,
     /*  918766 */     // GIR_Coverage, 7863,
     /*  918766 */     GIR_EraseRootFromParent_Done,
     /*  918767 */   // Label 14738: @918767
     /*  918767 */   GIM_Try, /*On fail goto*//*Label 14739*/ GIMT_Encode4(918852), // Rule ID 7864 //
     /*  918772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  918775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  918780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  918786 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  918789 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918792 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918799 */     // MIs[0] src0_modifiers
     /*  918799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918802 */     // MIs[0] src1_modifiers
     /*  918802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918805 */     // MIs[0] clamp
     /*  918805 */     // No operand predicates
     /*  918805 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918812 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr),
     /*  918815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918817 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918823 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918825 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918831 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918833 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918835 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918845 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918850 */     GIR_RootConstrainSelectedInstOperands,
     /*  918851 */     // GIR_Coverage, 7864,
     /*  918851 */     GIR_EraseRootFromParent_Done,
     /*  918852 */   // Label 14739: @918852
     /*  918852 */   GIM_Try, /*On fail goto*//*Label 14740*/ GIMT_Encode4(918937), // Rule ID 7865 //
     /*  918857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  918860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  918865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  918871 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  918874 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918877 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918884 */     // MIs[0] src0_modifiers
     /*  918884 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918887 */     // MIs[0] src1_modifiers
     /*  918887 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918890 */     // MIs[0] clamp
     /*  918890 */     // No operand predicates
     /*  918890 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918897 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr),
     /*  918900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918902 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918908 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918910 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  918916 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  918918 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  918920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  918925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  918930 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  918932 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  918935 */     GIR_RootConstrainSelectedInstOperands,
     /*  918936 */     // GIR_Coverage, 7865,
     /*  918936 */     GIR_EraseRootFromParent_Done,
     /*  918937 */   // Label 14740: @918937
     /*  918937 */   GIM_Try, /*On fail goto*//*Label 14741*/ GIMT_Encode4(919022), // Rule ID 7866 //
     /*  918942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  918945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  918950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  918953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  918956 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  918959 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  918962 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  918965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  918969 */     // MIs[0] src0_modifiers
     /*  918969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  918972 */     // MIs[0] src1_modifiers
     /*  918972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  918975 */     // MIs[0] clamp
     /*  918975 */     // No operand predicates
     /*  918975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  918982 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  918982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr),
     /*  918985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  918987 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  918993 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  918995 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919001 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919003 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919015 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919017 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919020 */     GIR_RootConstrainSelectedInstOperands,
     /*  919021 */     // GIR_Coverage, 7866,
     /*  919021 */     GIR_EraseRootFromParent_Done,
     /*  919022 */   // Label 14741: @919022
     /*  919022 */   GIM_Try, /*On fail goto*//*Label 14742*/ GIMT_Encode4(919107), // Rule ID 7867 //
     /*  919027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  919030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  919035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  919038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919041 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919044 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  919047 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  919054 */     // MIs[0] src0_modifiers
     /*  919054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919057 */     // MIs[0] src1_modifiers
     /*  919057 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919060 */     // MIs[0] clamp
     /*  919060 */     // No operand predicates
     /*  919060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  919067 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  919067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr),
     /*  919070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919072 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919078 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919080 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919086 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919088 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919090 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919100 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919105 */     GIR_RootConstrainSelectedInstOperands,
     /*  919106 */     // GIR_Coverage, 7867,
     /*  919106 */     GIR_EraseRootFromParent_Done,
     /*  919107 */   // Label 14742: @919107
     /*  919107 */   GIM_Try, /*On fail goto*//*Label 14743*/ GIMT_Encode4(919192), // Rule ID 8023 //
     /*  919112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  919115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  919120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919126 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919129 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919132 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919139 */     // MIs[0] src0_modifiers
     /*  919139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919142 */     // MIs[0] src1_modifiers
     /*  919142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919145 */     // MIs[0] clamp
     /*  919145 */     // No operand predicates
     /*  919145 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  919152 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp)
     /*  919152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr),
     /*  919155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919157 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919163 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919165 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919171 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919173 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  919185 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919190 */     GIR_RootConstrainSelectedInstOperands,
     /*  919191 */     // GIR_Coverage, 8023,
     /*  919191 */     GIR_EraseRootFromParent_Done,
     /*  919192 */   // Label 14743: @919192
     /*  919192 */   GIM_Try, /*On fail goto*//*Label 14744*/ GIMT_Encode4(919277), // Rule ID 8024 //
     /*  919197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  919200 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  919205 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919211 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919214 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919217 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919224 */     // MIs[0] src0_modifiers
     /*  919224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919227 */     // MIs[0] src1_modifiers
     /*  919227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919230 */     // MIs[0] clamp
     /*  919230 */     // No operand predicates
     /*  919230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  919237 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp)
     /*  919237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr),
     /*  919240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919242 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919248 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919250 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919256 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919258 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919260 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  919270 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919272 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919275 */     GIR_RootConstrainSelectedInstOperands,
     /*  919276 */     // GIR_Coverage, 8024,
     /*  919276 */     GIR_EraseRootFromParent_Done,
     /*  919277 */   // Label 14744: @919277
     /*  919277 */   GIM_Try, /*On fail goto*//*Label 14745*/ GIMT_Encode4(919362), // Rule ID 8025 //
     /*  919282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  919285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  919290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919296 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919299 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919302 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919309 */     // MIs[0] src0_modifiers
     /*  919309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919312 */     // MIs[0] src1_modifiers
     /*  919312 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919315 */     // MIs[0] clamp
     /*  919315 */     // No operand predicates
     /*  919315 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  919322 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp)
     /*  919322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr),
     /*  919325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919327 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919333 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919335 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919341 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919343 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  919355 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919360 */     GIR_RootConstrainSelectedInstOperands,
     /*  919361 */     // GIR_Coverage, 8025,
     /*  919361 */     GIR_EraseRootFromParent_Done,
     /*  919362 */   // Label 14745: @919362
     /*  919362 */   GIM_Try, /*On fail goto*//*Label 14746*/ GIMT_Encode4(919447), // Rule ID 8026 //
     /*  919367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  919370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  919375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919378 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919381 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919384 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919387 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919394 */     // MIs[0] src0_modifiers
     /*  919394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919397 */     // MIs[0] src1_modifiers
     /*  919397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919400 */     // MIs[0] clamp
     /*  919400 */     // No operand predicates
     /*  919400 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  919407 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp)
     /*  919407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr),
     /*  919410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919412 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919418 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919420 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919426 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919428 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  919440 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919445 */     GIR_RootConstrainSelectedInstOperands,
     /*  919446 */     // GIR_Coverage, 8026,
     /*  919446 */     GIR_EraseRootFromParent_Done,
     /*  919447 */   // Label 14746: @919447
     /*  919447 */   GIM_Try, /*On fail goto*//*Label 14747*/ GIMT_Encode4(919532), // Rule ID 8027 //
     /*  919452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  919455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
     /*  919460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919466 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919469 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919472 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919479 */     // MIs[0] src0_modifiers
     /*  919479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919482 */     // MIs[0] src1_modifiers
     /*  919482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919485 */     // MIs[0] clamp
     /*  919485 */     // No operand predicates
     /*  919485 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
     /*  919492 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3599:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp)
     /*  919492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr),
     /*  919495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919497 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919503 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919505 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919511 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919513 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919515 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
     /*  919525 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919530 */     GIR_RootConstrainSelectedInstOperands,
     /*  919531 */     // GIR_Coverage, 8027,
     /*  919531 */     GIR_EraseRootFromParent_Done,
     /*  919532 */   // Label 14747: @919532
     /*  919532 */   GIM_Try, /*On fail goto*//*Label 14748*/ GIMT_Encode4(919617), // Rule ID 8028 //
     /*  919537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  919540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  919545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919551 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  919554 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919557 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919564 */     // MIs[0] src0_modifiers
     /*  919564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919567 */     // MIs[0] src1_modifiers
     /*  919567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919570 */     // MIs[0] clamp
     /*  919570 */     // No operand predicates
     /*  919570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  919577 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  919577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr),
     /*  919580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919582 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919588 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919590 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919596 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919598 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919610 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919615 */     GIR_RootConstrainSelectedInstOperands,
     /*  919616 */     // GIR_Coverage, 8028,
     /*  919616 */     GIR_EraseRootFromParent_Done,
     /*  919617 */   // Label 14748: @919617
     /*  919617 */   GIM_Try, /*On fail goto*//*Label 14749*/ GIMT_Encode4(919702), // Rule ID 8029 //
     /*  919622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  919625 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  919630 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919636 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  919639 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919642 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919649 */     // MIs[0] src0_modifiers
     /*  919649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919652 */     // MIs[0] src1_modifiers
     /*  919652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919655 */     // MIs[0] clamp
     /*  919655 */     // No operand predicates
     /*  919655 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  919662 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  919662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr),
     /*  919665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919667 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919673 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919675 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919681 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919683 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919695 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919700 */     GIR_RootConstrainSelectedInstOperands,
     /*  919701 */     // GIR_Coverage, 8029,
     /*  919701 */     GIR_EraseRootFromParent_Done,
     /*  919702 */   // Label 14749: @919702
     /*  919702 */   GIM_Try, /*On fail goto*//*Label 14750*/ GIMT_Encode4(919787), // Rule ID 8030 //
     /*  919707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  919710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  919715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919718 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919721 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  919724 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919727 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919734 */     // MIs[0] src0_modifiers
     /*  919734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919737 */     // MIs[0] src1_modifiers
     /*  919737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919740 */     // MIs[0] clamp
     /*  919740 */     // No operand predicates
     /*  919740 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  919747 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  919747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr),
     /*  919750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919752 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919758 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919760 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919766 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919768 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919780 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919785 */     GIR_RootConstrainSelectedInstOperands,
     /*  919786 */     // GIR_Coverage, 8030,
     /*  919786 */     GIR_EraseRootFromParent_Done,
     /*  919787 */   // Label 14750: @919787
     /*  919787 */   GIM_Try, /*On fail goto*//*Label 14751*/ GIMT_Encode4(919872), // Rule ID 8031 //
     /*  919792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  919795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  919800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919806 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  919809 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919812 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919819 */     // MIs[0] src0_modifiers
     /*  919819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919822 */     // MIs[0] src1_modifiers
     /*  919822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919825 */     // MIs[0] clamp
     /*  919825 */     // No operand predicates
     /*  919825 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  919832 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  919832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr),
     /*  919835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919837 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919843 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919845 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919851 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919853 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919865 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919870 */     GIR_RootConstrainSelectedInstOperands,
     /*  919871 */     // GIR_Coverage, 8031,
     /*  919871 */     GIR_EraseRootFromParent_Done,
     /*  919872 */   // Label 14751: @919872
     /*  919872 */   GIM_Try, /*On fail goto*//*Label 14752*/ GIMT_Encode4(919957), // Rule ID 8032 //
     /*  919877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  919880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
     /*  919885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919891 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
     /*  919894 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919897 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919904 */     // MIs[0] src0_modifiers
     /*  919904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919907 */     // MIs[0] src1_modifiers
     /*  919907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919910 */     // MIs[0] clamp
     /*  919910 */     // No operand predicates
     /*  919910 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  919917 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3598:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  919917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr),
     /*  919920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  919922 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  919928 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  919930 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  919936 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  919938 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  919940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  919945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  919950 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  919952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  919955 */     GIR_RootConstrainSelectedInstOperands,
     /*  919956 */     // GIR_Coverage, 8032,
     /*  919956 */     GIR_EraseRootFromParent_Done,
     /*  919957 */   // Label 14752: @919957
     /*  919957 */   GIM_Try, /*On fail goto*//*Label 14753*/ GIMT_Encode4(920042), // Rule ID 8033 //
     /*  919962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  919965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  919970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  919973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  919976 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  919979 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  919982 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  919985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  919989 */     // MIs[0] src0_modifiers
     /*  919989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  919992 */     // MIs[0] src1_modifiers
     /*  919992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  919995 */     // MIs[0] clamp
     /*  919995 */     // No operand predicates
     /*  919995 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  920002 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  920002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr),
     /*  920005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920007 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920013 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920015 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920021 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920023 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  920035 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920040 */     GIR_RootConstrainSelectedInstOperands,
     /*  920041 */     // GIR_Coverage, 8033,
     /*  920041 */     GIR_EraseRootFromParent_Done,
     /*  920042 */   // Label 14753: @920042
     /*  920042 */   GIM_Try, /*On fail goto*//*Label 14754*/ GIMT_Encode4(920127), // Rule ID 8034 //
     /*  920047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  920050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  920058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  920061 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920064 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  920067 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  920074 */     // MIs[0] src0_modifiers
     /*  920074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920077 */     // MIs[0] src1_modifiers
     /*  920077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920080 */     // MIs[0] clamp
     /*  920080 */     // No operand predicates
     /*  920080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  920087 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  920087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr),
     /*  920090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920092 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920098 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920100 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920106 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920108 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  920120 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920125 */     GIR_RootConstrainSelectedInstOperands,
     /*  920126 */     // GIR_Coverage, 8034,
     /*  920126 */     GIR_EraseRootFromParent_Done,
     /*  920127 */   // Label 14754: @920127
     /*  920127 */   GIM_Try, /*On fail goto*//*Label 14755*/ GIMT_Encode4(920212), // Rule ID 8035 //
     /*  920132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  920135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  920143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  920146 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920149 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  920152 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  920159 */     // MIs[0] src0_modifiers
     /*  920159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920162 */     // MIs[0] src1_modifiers
     /*  920162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920165 */     // MIs[0] clamp
     /*  920165 */     // No operand predicates
     /*  920165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  920172 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  920172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr),
     /*  920175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920177 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920183 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920185 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920191 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920193 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  920205 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920210 */     GIR_RootConstrainSelectedInstOperands,
     /*  920211 */     // GIR_Coverage, 8035,
     /*  920211 */     GIR_EraseRootFromParent_Done,
     /*  920212 */   // Label 14755: @920212
     /*  920212 */   GIM_Try, /*On fail goto*//*Label 14756*/ GIMT_Encode4(920297), // Rule ID 8036 //
     /*  920217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  920220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  920228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  920231 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920234 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  920237 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  920244 */     // MIs[0] src0_modifiers
     /*  920244 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920247 */     // MIs[0] src1_modifiers
     /*  920247 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920250 */     // MIs[0] clamp
     /*  920250 */     // No operand predicates
     /*  920250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  920257 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  920257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr),
     /*  920260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920262 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920268 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920270 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920276 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920278 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  920290 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920295 */     GIR_RootConstrainSelectedInstOperands,
     /*  920296 */     // GIR_Coverage, 8036,
     /*  920296 */     GIR_EraseRootFromParent_Done,
     /*  920297 */   // Label 14756: @920297
     /*  920297 */   GIM_Try, /*On fail goto*//*Label 14757*/ GIMT_Encode4(920382), // Rule ID 8037 //
     /*  920302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  920305 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920310 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  920313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /*  920316 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920319 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
     /*  920322 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  920329 */     // MIs[0] src0_modifiers
     /*  920329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920332 */     // MIs[0] src1_modifiers
     /*  920332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920335 */     // MIs[0] clamp
     /*  920335 */     // No operand predicates
     /*  920335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  920342 */     // (intrinsic_wo_chain:{ *:[v4i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, i32:{ *:[i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
     /*  920342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr),
     /*  920345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920347 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920353 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920355 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920361 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920363 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920365 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  920375 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920380 */     GIR_RootConstrainSelectedInstOperands,
     /*  920381 */     // GIR_Coverage, 8037,
     /*  920381 */     GIR_EraseRootFromParent_Done,
     /*  920382 */   // Label 14757: @920382
     /*  920382 */   GIM_Try, /*On fail goto*//*Label 14758*/ GIMT_Encode4(920452), // Rule ID 7868 //
     /*  920387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode0),
     /*  920390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920401 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  920404 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  920407 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920414 */     // MIs[0] src0_modifiers
     /*  920414 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920417 */     // MIs[0] src1_modifiers
     /*  920417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920420 */     // MIs[0] clamp
     /*  920420 */     // No operand predicates
     /*  920420 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  920420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr),
     /*  920423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920425 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920431 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920433 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920439 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920441 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920443 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  920445 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920450 */     GIR_RootConstrainSelectedInstOperands,
     /*  920451 */     // GIR_Coverage, 7868,
     /*  920451 */     GIR_EraseRootFromParent_Done,
     /*  920452 */   // Label 14758: @920452
     /*  920452 */   GIM_Try, /*On fail goto*//*Label 14759*/ GIMT_Encode4(920522), // Rule ID 7869 //
     /*  920457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode1),
     /*  920460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920468 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920471 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  920474 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  920477 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920484 */     // MIs[0] src0_modifiers
     /*  920484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920487 */     // MIs[0] src1_modifiers
     /*  920487 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920490 */     // MIs[0] clamp
     /*  920490 */     // No operand predicates
     /*  920490 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  920490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr),
     /*  920493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920495 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920501 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920503 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920509 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920511 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920513 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  920515 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920517 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920520 */     GIR_RootConstrainSelectedInstOperands,
     /*  920521 */     // GIR_Coverage, 7869,
     /*  920521 */     GIR_EraseRootFromParent_Done,
     /*  920522 */   // Label 14759: @920522
     /*  920522 */   GIM_Try, /*On fail goto*//*Label 14760*/ GIMT_Encode4(920592), // Rule ID 7870 //
     /*  920527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode2),
     /*  920530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920538 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920541 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  920544 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  920547 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920554 */     // MIs[0] src0_modifiers
     /*  920554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920557 */     // MIs[0] src1_modifiers
     /*  920557 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920560 */     // MIs[0] clamp
     /*  920560 */     // No operand predicates
     /*  920560 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  920560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr),
     /*  920563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920565 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920571 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920573 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920579 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920581 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920583 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  920585 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920590 */     GIR_RootConstrainSelectedInstOperands,
     /*  920591 */     // GIR_Coverage, 7870,
     /*  920591 */     GIR_EraseRootFromParent_Done,
     /*  920592 */   // Label 14760: @920592
     /*  920592 */   GIM_Try, /*On fail goto*//*Label 14761*/ GIMT_Encode4(920662), // Rule ID 7871 //
     /*  920597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode3),
     /*  920600 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920605 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920608 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920611 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  920614 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  920617 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920624 */     // MIs[0] src0_modifiers
     /*  920624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920627 */     // MIs[0] src1_modifiers
     /*  920627 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920630 */     // MIs[0] clamp
     /*  920630 */     // No operand predicates
     /*  920630 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  920630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr),
     /*  920633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920635 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920641 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920643 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920649 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920651 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920653 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  920655 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920657 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920660 */     GIR_RootConstrainSelectedInstOperands,
     /*  920661 */     // GIR_Coverage, 7871,
     /*  920661 */     GIR_EraseRootFromParent_Done,
     /*  920662 */   // Label 14761: @920662
     /*  920662 */   GIM_Try, /*On fail goto*//*Label 14762*/ GIMT_Encode4(920732), // Rule ID 7872 //
     /*  920667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave32_HwMode4),
     /*  920670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
     /*  920675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920681 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
     /*  920684 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  920687 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  920690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920694 */     // MIs[0] src0_modifiers
     /*  920694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920697 */     // MIs[0] src1_modifiers
     /*  920697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920700 */     // MIs[0] clamp
     /*  920700 */     // No operand predicates
     /*  920700 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3600:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
     /*  920700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr),
     /*  920703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920705 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920711 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920713 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920719 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920721 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  920723 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  920725 */     GIR_RootToRootCopy, /*OpIdx*/8, // clamp
     /*  920727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920730 */     GIR_RootConstrainSelectedInstOperands,
     /*  920731 */     // GIR_Coverage, 7872,
     /*  920731 */     GIR_EraseRootFromParent_Done,
     /*  920732 */   // Label 14762: @920732
     /*  920732 */   GIM_Reject,
     /*  920733 */ // Label 14732: @920733
     /*  920733 */ GIM_Try, /*On fail goto*//*Label 14763*/ GIMT_Encode4(925202),
     /*  920738 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
     /*  920741 */   GIM_Try, /*On fail goto*//*Label 14764*/ GIMT_Encode4(920836), // Rule ID 8063 //
     /*  920746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  920749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  920754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920760 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920763 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  920766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920770 */     // MIs[0] src0_modifiers
     /*  920770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920773 */     // MIs[0] src1_modifiers
     /*  920773 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920776 */     // MIs[0] src2_modifiers
     /*  920776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  920779 */     // MIs[0] matrix_a_reuse
     /*  920779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  920782 */     // MIs[0] matrix_b_reuse
     /*  920782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  920785 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  920792 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  920792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_threeaddr),
     /*  920795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920797 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920803 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920805 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920811 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920813 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  920819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920824 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  920826 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  920828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920834 */     GIR_RootConstrainSelectedInstOperands,
     /*  920835 */     // GIR_Coverage, 8063,
     /*  920835 */     GIR_EraseRootFromParent_Done,
     /*  920836 */   // Label 14764: @920836
     /*  920836 */   GIM_Try, /*On fail goto*//*Label 14765*/ GIMT_Encode4(920931), // Rule ID 8064 //
     /*  920841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  920844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  920849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920855 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920858 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  920861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920865 */     // MIs[0] src0_modifiers
     /*  920865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920868 */     // MIs[0] src1_modifiers
     /*  920868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920871 */     // MIs[0] src2_modifiers
     /*  920871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  920874 */     // MIs[0] matrix_a_reuse
     /*  920874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  920877 */     // MIs[0] matrix_b_reuse
     /*  920877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  920880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  920887 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  920887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_threeaddr),
     /*  920890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920892 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920898 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920900 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  920906 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  920908 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  920914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  920919 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  920921 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  920923 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920926 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  920929 */     GIR_RootConstrainSelectedInstOperands,
     /*  920930 */     // GIR_Coverage, 8064,
     /*  920930 */     GIR_EraseRootFromParent_Done,
     /*  920931 */   // Label 14765: @920931
     /*  920931 */   GIM_Try, /*On fail goto*//*Label 14766*/ GIMT_Encode4(921026), // Rule ID 8065 //
     /*  920936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  920939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  920944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  920947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  920950 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  920953 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  920956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  920960 */     // MIs[0] src0_modifiers
     /*  920960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  920963 */     // MIs[0] src1_modifiers
     /*  920963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  920966 */     // MIs[0] src2_modifiers
     /*  920966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  920969 */     // MIs[0] matrix_a_reuse
     /*  920969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  920972 */     // MIs[0] matrix_b_reuse
     /*  920972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  920975 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  920982 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  920982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_threeaddr),
     /*  920985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  920987 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  920993 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  920995 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  921001 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921003 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921014 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921016 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921018 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921024 */     GIR_RootConstrainSelectedInstOperands,
     /*  921025 */     // GIR_Coverage, 8065,
     /*  921025 */     GIR_EraseRootFromParent_Done,
     /*  921026 */   // Label 14766: @921026
     /*  921026 */   GIM_Try, /*On fail goto*//*Label 14767*/ GIMT_Encode4(921121), // Rule ID 8066 //
     /*  921031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  921034 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  921039 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  921045 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  921048 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921055 */     // MIs[0] src0_modifiers
     /*  921055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921058 */     // MIs[0] src1_modifiers
     /*  921058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921061 */     // MIs[0] src2_modifiers
     /*  921061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921064 */     // MIs[0] matrix_a_reuse
     /*  921064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921067 */     // MIs[0] matrix_b_reuse
     /*  921067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921070 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921077 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_threeaddr),
     /*  921080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921082 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  921088 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921090 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  921096 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921098 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921109 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921111 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921113 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921119 */     GIR_RootConstrainSelectedInstOperands,
     /*  921120 */     // GIR_Coverage, 8066,
     /*  921120 */     GIR_EraseRootFromParent_Done,
     /*  921121 */   // Label 14767: @921121
     /*  921121 */   GIM_Try, /*On fail goto*//*Label 14768*/ GIMT_Encode4(921216), // Rule ID 8067 //
     /*  921126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  921129 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  921134 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  921140 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  921143 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921150 */     // MIs[0] src0_modifiers
     /*  921150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921153 */     // MIs[0] src1_modifiers
     /*  921153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921156 */     // MIs[0] src2_modifiers
     /*  921156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921159 */     // MIs[0] matrix_a_reuse
     /*  921159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921162 */     // MIs[0] matrix_b_reuse
     /*  921162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921165 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921172 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_threeaddr),
     /*  921175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921177 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  921183 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921185 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  921191 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921193 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921204 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921206 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921214 */     GIR_RootConstrainSelectedInstOperands,
     /*  921215 */     // GIR_Coverage, 8067,
     /*  921215 */     GIR_EraseRootFromParent_Done,
     /*  921216 */   // Label 14768: @921216
     /*  921216 */   GIM_Try, /*On fail goto*//*Label 14769*/ GIMT_Encode4(921311), // Rule ID 8163 //
     /*  921221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  921224 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  921229 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921235 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921238 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921245 */     // MIs[0] src0_modifiers
     /*  921245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921248 */     // MIs[0] src1_modifiers
     /*  921248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921251 */     // MIs[0] src2_modifiers
     /*  921251 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921254 */     // MIs[0] matrix_a_reuse
     /*  921254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921257 */     // MIs[0] matrix_b_reuse
     /*  921257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921260 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921267 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_threeaddr),
     /*  921270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921272 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921278 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921280 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921286 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921288 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921294 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921299 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921301 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921303 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921306 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921309 */     GIR_RootConstrainSelectedInstOperands,
     /*  921310 */     // GIR_Coverage, 8163,
     /*  921310 */     GIR_EraseRootFromParent_Done,
     /*  921311 */   // Label 14769: @921311
     /*  921311 */   GIM_Try, /*On fail goto*//*Label 14770*/ GIMT_Encode4(921406), // Rule ID 8164 //
     /*  921316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  921319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  921324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921330 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921333 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921340 */     // MIs[0] src0_modifiers
     /*  921340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921343 */     // MIs[0] src1_modifiers
     /*  921343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921346 */     // MIs[0] src2_modifiers
     /*  921346 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921349 */     // MIs[0] matrix_a_reuse
     /*  921349 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921352 */     // MIs[0] matrix_b_reuse
     /*  921352 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921362 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_threeaddr),
     /*  921365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921367 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921373 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921375 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921381 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921383 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921394 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921396 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921398 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921401 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921404 */     GIR_RootConstrainSelectedInstOperands,
     /*  921405 */     // GIR_Coverage, 8164,
     /*  921405 */     GIR_EraseRootFromParent_Done,
     /*  921406 */   // Label 14770: @921406
     /*  921406 */   GIM_Try, /*On fail goto*//*Label 14771*/ GIMT_Encode4(921501), // Rule ID 8165 //
     /*  921411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  921414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  921419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921425 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921428 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921435 */     // MIs[0] src0_modifiers
     /*  921435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921438 */     // MIs[0] src1_modifiers
     /*  921438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921441 */     // MIs[0] src2_modifiers
     /*  921441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921444 */     // MIs[0] matrix_a_reuse
     /*  921444 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921447 */     // MIs[0] matrix_b_reuse
     /*  921447 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921450 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921457 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_threeaddr),
     /*  921460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921462 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921468 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921470 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921476 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921478 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921489 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921491 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921499 */     GIR_RootConstrainSelectedInstOperands,
     /*  921500 */     // GIR_Coverage, 8165,
     /*  921500 */     GIR_EraseRootFromParent_Done,
     /*  921501 */   // Label 14771: @921501
     /*  921501 */   GIM_Try, /*On fail goto*//*Label 14772*/ GIMT_Encode4(921596), // Rule ID 8166 //
     /*  921506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  921509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  921514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921520 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921523 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921530 */     // MIs[0] src0_modifiers
     /*  921530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921533 */     // MIs[0] src1_modifiers
     /*  921533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921536 */     // MIs[0] src2_modifiers
     /*  921536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921539 */     // MIs[0] matrix_a_reuse
     /*  921539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921542 */     // MIs[0] matrix_b_reuse
     /*  921542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921545 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921552 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_threeaddr),
     /*  921555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921557 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921563 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921565 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921571 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921573 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921584 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921586 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921594 */     GIR_RootConstrainSelectedInstOperands,
     /*  921595 */     // GIR_Coverage, 8166,
     /*  921595 */     GIR_EraseRootFromParent_Done,
     /*  921596 */   // Label 14772: @921596
     /*  921596 */   GIM_Try, /*On fail goto*//*Label 14773*/ GIMT_Encode4(921691), // Rule ID 8167 //
     /*  921601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  921604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  921609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  921612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921615 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921618 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  921621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  921625 */     // MIs[0] src0_modifiers
     /*  921625 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921628 */     // MIs[0] src1_modifiers
     /*  921628 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921631 */     // MIs[0] src2_modifiers
     /*  921631 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921634 */     // MIs[0] matrix_a_reuse
     /*  921634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921637 */     // MIs[0] matrix_b_reuse
     /*  921637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921640 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921647 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_threeaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_threeaddr),
     /*  921650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921652 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921658 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921660 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921666 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921668 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921679 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921681 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921689 */     GIR_RootConstrainSelectedInstOperands,
     /*  921690 */     // GIR_Coverage, 8167,
     /*  921690 */     GIR_EraseRootFromParent_Done,
     /*  921691 */   // Label 14773: @921691
     /*  921691 */   GIM_Try, /*On fail goto*//*Label 14774*/ GIMT_Encode4(921786), // Rule ID 8173 //
     /*  921696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  921699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  921704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  921707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921710 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921713 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  921716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  921720 */     // MIs[0] src0_modifiers
     /*  921720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921723 */     // MIs[0] src1_modifiers
     /*  921723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921726 */     // MIs[0] src2_modifiers
     /*  921726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921729 */     // MIs[0] matrix_a_reuse
     /*  921729 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921732 */     // MIs[0] matrix_b_reuse
     /*  921732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921735 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921742 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_threeaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_threeaddr),
     /*  921745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921747 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921753 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921755 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921761 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921763 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921769 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921774 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921776 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921784 */     GIR_RootConstrainSelectedInstOperands,
     /*  921785 */     // GIR_Coverage, 8173,
     /*  921785 */     GIR_EraseRootFromParent_Done,
     /*  921786 */   // Label 14774: @921786
     /*  921786 */   GIM_Try, /*On fail goto*//*Label 14775*/ GIMT_Encode4(921881), // Rule ID 8174 //
     /*  921791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  921794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  921799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  921802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921805 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921808 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  921811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  921815 */     // MIs[0] src0_modifiers
     /*  921815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921818 */     // MIs[0] src1_modifiers
     /*  921818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921821 */     // MIs[0] src2_modifiers
     /*  921821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921824 */     // MIs[0] matrix_a_reuse
     /*  921824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921827 */     // MIs[0] matrix_b_reuse
     /*  921827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921830 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921837 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_threeaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_threeaddr),
     /*  921840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921842 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921848 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921850 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921856 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921858 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921869 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921871 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921873 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921879 */     GIR_RootConstrainSelectedInstOperands,
     /*  921880 */     // GIR_Coverage, 8174,
     /*  921880 */     GIR_EraseRootFromParent_Done,
     /*  921881 */   // Label 14775: @921881
     /*  921881 */   GIM_Try, /*On fail goto*//*Label 14776*/ GIMT_Encode4(921976), // Rule ID 8175 //
     /*  921886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  921889 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  921894 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  921897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921900 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921903 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  921906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  921910 */     // MIs[0] src0_modifiers
     /*  921910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  921913 */     // MIs[0] src1_modifiers
     /*  921913 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  921916 */     // MIs[0] src2_modifiers
     /*  921916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  921919 */     // MIs[0] matrix_a_reuse
     /*  921919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  921922 */     // MIs[0] matrix_b_reuse
     /*  921922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  921925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  921932 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_threeaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  921932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_threeaddr),
     /*  921935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  921937 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  921943 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  921945 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  921951 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  921953 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  921959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  921964 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  921966 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  921968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  921974 */     GIR_RootConstrainSelectedInstOperands,
     /*  921975 */     // GIR_Coverage, 8175,
     /*  921975 */     GIR_EraseRootFromParent_Done,
     /*  921976 */   // Label 14776: @921976
     /*  921976 */   GIM_Try, /*On fail goto*//*Label 14777*/ GIMT_Encode4(922071), // Rule ID 8176 //
     /*  921981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  921984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  921989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  921992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  921995 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  921998 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  922001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  922005 */     // MIs[0] src0_modifiers
     /*  922005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922008 */     // MIs[0] src1_modifiers
     /*  922008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922011 */     // MIs[0] src2_modifiers
     /*  922011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  922014 */     // MIs[0] matrix_a_reuse
     /*  922014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922017 */     // MIs[0] matrix_b_reuse
     /*  922017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  922020 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922027 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_threeaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_threeaddr),
     /*  922030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922032 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  922038 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922040 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  922046 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922048 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  922054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922059 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  922061 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  922063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922069 */     GIR_RootConstrainSelectedInstOperands,
     /*  922070 */     // GIR_Coverage, 8176,
     /*  922070 */     GIR_EraseRootFromParent_Done,
     /*  922071 */   // Label 14777: @922071
     /*  922071 */   GIM_Try, /*On fail goto*//*Label 14778*/ GIMT_Encode4(922166), // Rule ID 8177 //
     /*  922076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  922079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  922084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  922087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  922090 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  922093 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  922096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  922100 */     // MIs[0] src0_modifiers
     /*  922100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922103 */     // MIs[0] src1_modifiers
     /*  922103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922106 */     // MIs[0] src2_modifiers
     /*  922106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  922109 */     // MIs[0] matrix_a_reuse
     /*  922109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922112 */     // MIs[0] matrix_b_reuse
     /*  922112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  922115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922122 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_threeaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_threeaddr),
     /*  922125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922127 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  922133 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922135 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  922141 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922143 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  922149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922154 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  922156 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  922158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922164 */     GIR_RootConstrainSelectedInstOperands,
     /*  922165 */     // GIR_Coverage, 8177,
     /*  922165 */     GIR_EraseRootFromParent_Done,
     /*  922166 */   // Label 14778: @922166
     /*  922166 */   GIM_Try, /*On fail goto*//*Label 14779*/ GIMT_Encode4(922251), // Rule ID 8153 //
     /*  922171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  922174 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  922179 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922182 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  922185 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  922188 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922195 */     // MIs[0] src0_modifiers
     /*  922195 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922198 */     // MIs[0] src1_modifiers
     /*  922198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922201 */     // MIs[0] matrix_a_reuse
     /*  922201 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  922204 */     // MIs[0] matrix_b_reuse
     /*  922204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922207 */     // MIs[0] clamp
     /*  922207 */     // No operand predicates
     /*  922207 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922214 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_threeaddr),
     /*  922217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922219 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  922225 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922227 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  922233 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922240 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  922242 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  922244 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  922246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922249 */     GIR_RootConstrainSelectedInstOperands,
     /*  922250 */     // GIR_Coverage, 8153,
     /*  922250 */     GIR_EraseRootFromParent_Done,
     /*  922251 */   // Label 14779: @922251
     /*  922251 */   GIM_Try, /*On fail goto*//*Label 14780*/ GIMT_Encode4(922336), // Rule ID 8154 //
     /*  922256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  922259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  922264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  922270 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  922273 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922280 */     // MIs[0] src0_modifiers
     /*  922280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922283 */     // MIs[0] src1_modifiers
     /*  922283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922286 */     // MIs[0] matrix_a_reuse
     /*  922286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  922289 */     // MIs[0] matrix_b_reuse
     /*  922289 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922292 */     // MIs[0] clamp
     /*  922292 */     // No operand predicates
     /*  922292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922299 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_threeaddr),
     /*  922302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922304 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  922310 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922312 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  922318 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922325 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  922327 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  922329 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  922331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922334 */     GIR_RootConstrainSelectedInstOperands,
     /*  922335 */     // GIR_Coverage, 8154,
     /*  922335 */     GIR_EraseRootFromParent_Done,
     /*  922336 */   // Label 14780: @922336
     /*  922336 */   GIM_Try, /*On fail goto*//*Label 14781*/ GIMT_Encode4(922421), // Rule ID 8155 //
     /*  922341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  922344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  922349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  922355 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  922358 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922365 */     // MIs[0] src0_modifiers
     /*  922365 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922368 */     // MIs[0] src1_modifiers
     /*  922368 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922371 */     // MIs[0] matrix_a_reuse
     /*  922371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  922374 */     // MIs[0] matrix_b_reuse
     /*  922374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922377 */     // MIs[0] clamp
     /*  922377 */     // No operand predicates
     /*  922377 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922384 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_threeaddr),
     /*  922387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922389 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  922395 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922397 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  922403 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922410 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  922412 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  922414 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  922416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922419 */     GIR_RootConstrainSelectedInstOperands,
     /*  922420 */     // GIR_Coverage, 8155,
     /*  922420 */     GIR_EraseRootFromParent_Done,
     /*  922421 */   // Label 14781: @922421
     /*  922421 */   GIM_Try, /*On fail goto*//*Label 14782*/ GIMT_Encode4(922506), // Rule ID 8156 //
     /*  922426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  922429 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  922434 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  922440 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  922443 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922450 */     // MIs[0] src0_modifiers
     /*  922450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922453 */     // MIs[0] src1_modifiers
     /*  922453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922456 */     // MIs[0] matrix_a_reuse
     /*  922456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  922459 */     // MIs[0] matrix_b_reuse
     /*  922459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922462 */     // MIs[0] clamp
     /*  922462 */     // No operand predicates
     /*  922462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922469 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_threeaddr),
     /*  922472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922474 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  922480 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922482 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  922488 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922495 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  922497 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  922499 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  922501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922504 */     GIR_RootConstrainSelectedInstOperands,
     /*  922505 */     // GIR_Coverage, 8156,
     /*  922505 */     GIR_EraseRootFromParent_Done,
     /*  922506 */   // Label 14782: @922506
     /*  922506 */   GIM_Try, /*On fail goto*//*Label 14783*/ GIMT_Encode4(922591), // Rule ID 8157 //
     /*  922511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  922514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  922519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  922525 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  922528 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922535 */     // MIs[0] src0_modifiers
     /*  922535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922538 */     // MIs[0] src1_modifiers
     /*  922538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922541 */     // MIs[0] matrix_a_reuse
     /*  922541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  922544 */     // MIs[0] matrix_b_reuse
     /*  922544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922547 */     // MIs[0] clamp
     /*  922547 */     // No operand predicates
     /*  922547 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  922554 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_threeaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_threeaddr),
     /*  922557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922559 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  922565 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922567 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  922573 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922575 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922580 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  922582 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  922584 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  922586 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922589 */     GIR_RootConstrainSelectedInstOperands,
     /*  922590 */     // GIR_Coverage, 8157,
     /*  922590 */     GIR_EraseRootFromParent_Done,
     /*  922591 */   // Label 14783: @922591
     /*  922591 */   GIM_Try, /*On fail goto*//*Label 14784*/ GIMT_Encode4(922687), // Rule ID 8603 //
     /*  922596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  922599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x64_f16),
     /*  922604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  922610 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  922613 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922616 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  922619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922623 */     // MIs[0] src0_modifiers
     /*  922623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922626 */     // MIs[0] src1_modifiers
     /*  922626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922629 */     // MIs[0] matrix_a_reuse
     /*  922629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922632 */     // MIs[0] matrix_b_reuse
     /*  922632 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  922635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  922642 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3596:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X64_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr),
     /*  922645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922647 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  922653 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922655 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  922661 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922663 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  922665 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  922675 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  922677 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  922679 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922685 */     GIR_RootConstrainSelectedInstOperands,
     /*  922686 */     // GIR_Coverage, 8603,
     /*  922686 */     GIR_EraseRootFromParent_Done,
     /*  922687 */   // Label 14784: @922687
     /*  922687 */   GIM_Try, /*On fail goto*//*Label 14785*/ GIMT_Encode4(922783), // Rule ID 8604 //
     /*  922692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  922695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x64_f16),
     /*  922700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922703 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  922706 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  922709 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922712 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  922715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922719 */     // MIs[0] src0_modifiers
     /*  922719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922722 */     // MIs[0] src1_modifiers
     /*  922722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922725 */     // MIs[0] matrix_a_reuse
     /*  922725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922728 */     // MIs[0] matrix_b_reuse
     /*  922728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  922731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  922738 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3596:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X64_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr),
     /*  922741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922743 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  922749 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922751 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  922757 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922759 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  922761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  922771 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  922773 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  922775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922781 */     GIR_RootConstrainSelectedInstOperands,
     /*  922782 */     // GIR_Coverage, 8604,
     /*  922782 */     GIR_EraseRootFromParent_Done,
     /*  922783 */   // Label 14785: @922783
     /*  922783 */   GIM_Try, /*On fail goto*//*Label 14786*/ GIMT_Encode4(922879), // Rule ID 8605 //
     /*  922788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  922791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x64_f16),
     /*  922796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922799 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  922802 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  922805 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922808 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  922811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922815 */     // MIs[0] src0_modifiers
     /*  922815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922818 */     // MIs[0] src1_modifiers
     /*  922818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922821 */     // MIs[0] matrix_a_reuse
     /*  922821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922824 */     // MIs[0] matrix_b_reuse
     /*  922824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  922827 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  922834 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3596:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X64_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr),
     /*  922837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922839 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  922845 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922847 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  922853 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922855 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  922857 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  922867 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  922869 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  922871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922877 */     GIR_RootConstrainSelectedInstOperands,
     /*  922878 */     // GIR_Coverage, 8605,
     /*  922878 */     GIR_EraseRootFromParent_Done,
     /*  922879 */   // Label 14786: @922879
     /*  922879 */   GIM_Try, /*On fail goto*//*Label 14787*/ GIMT_Encode4(922975), // Rule ID 8606 //
     /*  922884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  922887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x64_f16),
     /*  922892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  922898 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  922901 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  922904 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  922907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  922911 */     // MIs[0] src0_modifiers
     /*  922911 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  922914 */     // MIs[0] src1_modifiers
     /*  922914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  922917 */     // MIs[0] matrix_a_reuse
     /*  922917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  922920 */     // MIs[0] matrix_b_reuse
     /*  922920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  922923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  922930 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3596:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X64_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  922930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr),
     /*  922933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  922935 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  922941 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  922943 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  922949 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  922951 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  922953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  922958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  922963 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  922965 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  922967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  922973 */     GIR_RootConstrainSelectedInstOperands,
     /*  922974 */     // GIR_Coverage, 8606,
     /*  922974 */     GIR_EraseRootFromParent_Done,
     /*  922975 */   // Label 14787: @922975
     /*  922975 */   GIM_Try, /*On fail goto*//*Label 14788*/ GIMT_Encode4(923071), // Rule ID 8607 //
     /*  922980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  922983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x64_f16),
     /*  922988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  922991 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  922994 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  922997 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  923000 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  923003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  923007 */     // MIs[0] src0_modifiers
     /*  923007 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923010 */     // MIs[0] src1_modifiers
     /*  923010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923013 */     // MIs[0] matrix_a_reuse
     /*  923013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923016 */     // MIs[0] matrix_b_reuse
     /*  923016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923019 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  923026 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3596:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F32_16X16X64_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X64_F16_w32_twoaddr),
     /*  923029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923031 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  923037 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923039 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  923045 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923047 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  923049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  923054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  923059 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923061 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923069 */     GIR_RootConstrainSelectedInstOperands,
     /*  923070 */     // GIR_Coverage, 8607,
     /*  923070 */     GIR_EraseRootFromParent_Done,
     /*  923071 */   // Label 14788: @923071
     /*  923071 */   GIM_Try, /*On fail goto*//*Label 14789*/ GIMT_Encode4(923167), // Rule ID 8608 //
     /*  923076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  923079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x64_f16),
     /*  923084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  923087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  923090 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  923093 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
     /*  923096 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  923099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  923103 */     // MIs[0] src0_modifiers
     /*  923103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923106 */     // MIs[0] src1_modifiers
     /*  923106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923109 */     // MIs[0] matrix_a_reuse
     /*  923109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923112 */     // MIs[0] matrix_b_reuse
     /*  923112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  923122 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3584:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X64_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr),
     /*  923125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923127 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  923133 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923135 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  923141 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923143 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  923145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  923150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  923155 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923157 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923159 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923165 */     GIR_RootConstrainSelectedInstOperands,
     /*  923166 */     // GIR_Coverage, 8608,
     /*  923166 */     GIR_EraseRootFromParent_Done,
     /*  923167 */   // Label 14789: @923167
     /*  923167 */   GIM_Try, /*On fail goto*//*Label 14790*/ GIMT_Encode4(923263), // Rule ID 8609 //
     /*  923172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  923175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x64_f16),
     /*  923180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  923183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  923186 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  923189 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
     /*  923192 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  923195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  923199 */     // MIs[0] src0_modifiers
     /*  923199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923202 */     // MIs[0] src1_modifiers
     /*  923202 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923205 */     // MIs[0] matrix_a_reuse
     /*  923205 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923208 */     // MIs[0] matrix_b_reuse
     /*  923208 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923211 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  923218 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3584:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X64_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr),
     /*  923221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923223 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  923229 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923231 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  923237 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923239 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  923241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  923246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  923251 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923253 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923261 */     GIR_RootConstrainSelectedInstOperands,
     /*  923262 */     // GIR_Coverage, 8609,
     /*  923262 */     GIR_EraseRootFromParent_Done,
     /*  923263 */   // Label 14790: @923263
     /*  923263 */   GIM_Try, /*On fail goto*//*Label 14791*/ GIMT_Encode4(923359), // Rule ID 8610 //
     /*  923268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  923271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x64_f16),
     /*  923276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  923279 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  923282 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  923285 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
     /*  923288 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  923291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  923295 */     // MIs[0] src0_modifiers
     /*  923295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923298 */     // MIs[0] src1_modifiers
     /*  923298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923301 */     // MIs[0] matrix_a_reuse
     /*  923301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923304 */     // MIs[0] matrix_b_reuse
     /*  923304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  923314 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3584:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X64_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr),
     /*  923317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923319 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  923325 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923327 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  923333 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923335 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  923337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  923342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  923347 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923349 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923357 */     GIR_RootConstrainSelectedInstOperands,
     /*  923358 */     // GIR_Coverage, 8610,
     /*  923358 */     GIR_EraseRootFromParent_Done,
     /*  923359 */   // Label 14791: @923359
     /*  923359 */   GIM_Try, /*On fail goto*//*Label 14792*/ GIMT_Encode4(923455), // Rule ID 8611 //
     /*  923364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  923367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x64_f16),
     /*  923372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  923375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  923378 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  923381 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
     /*  923384 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  923387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  923391 */     // MIs[0] src0_modifiers
     /*  923391 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923394 */     // MIs[0] src1_modifiers
     /*  923394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923397 */     // MIs[0] matrix_a_reuse
     /*  923397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923400 */     // MIs[0] matrix_b_reuse
     /*  923400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923403 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  923410 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3584:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X64_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr),
     /*  923413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923415 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  923421 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923423 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  923429 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923431 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  923433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  923438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  923443 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923445 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923453 */     GIR_RootConstrainSelectedInstOperands,
     /*  923454 */     // GIR_Coverage, 8611,
     /*  923454 */     GIR_EraseRootFromParent_Done,
     /*  923455 */   // Label 14792: @923455
     /*  923455 */   GIM_Try, /*On fail goto*//*Label 14793*/ GIMT_Encode4(923551), // Rule ID 8612 //
     /*  923460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  923463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x64_f16),
     /*  923468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  923471 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  923474 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v32s16,
     /*  923477 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
     /*  923480 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
     /*  923483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  923487 */     // MIs[0] src0_modifiers
     /*  923487 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923490 */     // MIs[0] src1_modifiers
     /*  923490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923493 */     // MIs[0] matrix_a_reuse
     /*  923493 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923496 */     // MIs[0] matrix_b_reuse
     /*  923496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
     /*  923506 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3584:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_SWMMAC_F16_16X16X64_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v32f16:{ *:[v32f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X64_F16_w32_twoaddr),
     /*  923509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923511 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  923517 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923519 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  923525 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923527 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  923529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  923534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
     /*  923539 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923541 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923543 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923546 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923549 */     GIR_RootConstrainSelectedInstOperands,
     /*  923550 */     // GIR_Coverage, 8612,
     /*  923550 */     GIR_EraseRootFromParent_Done,
     /*  923551 */   // Label 14793: @923551
     /*  923551 */   GIM_Try, /*On fail goto*//*Label 14794*/ GIMT_Encode4(923636), // Rule ID 8058 //
     /*  923556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  923559 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  923564 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  923567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  923570 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  923573 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  923576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  923580 */     // MIs[0] src0_modifiers
     /*  923580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923583 */     // MIs[0] src1_modifiers
     /*  923583 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923586 */     // MIs[0] src2_modifiers
     /*  923586 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  923589 */     // MIs[0] matrix_a_reuse
     /*  923589 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923592 */     // MIs[0] matrix_b_reuse
     /*  923592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923595 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr),
     /*  923598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923600 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  923606 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923608 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  923614 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923616 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  923622 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  923624 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923626 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923634 */     GIR_RootConstrainSelectedInstOperands,
     /*  923635 */     // GIR_Coverage, 8058,
     /*  923635 */     GIR_EraseRootFromParent_Done,
     /*  923636 */   // Label 14794: @923636
     /*  923636 */   GIM_Try, /*On fail goto*//*Label 14795*/ GIMT_Encode4(923721), // Rule ID 8059 //
     /*  923641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  923644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  923649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  923652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  923655 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  923658 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  923661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  923665 */     // MIs[0] src0_modifiers
     /*  923665 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923668 */     // MIs[0] src1_modifiers
     /*  923668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923671 */     // MIs[0] src2_modifiers
     /*  923671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  923674 */     // MIs[0] matrix_a_reuse
     /*  923674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923677 */     // MIs[0] matrix_b_reuse
     /*  923677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923680 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr),
     /*  923683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923685 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  923691 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923693 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  923699 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923701 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  923707 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  923709 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923711 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923719 */     GIR_RootConstrainSelectedInstOperands,
     /*  923720 */     // GIR_Coverage, 8059,
     /*  923720 */     GIR_EraseRootFromParent_Done,
     /*  923721 */   // Label 14795: @923721
     /*  923721 */   GIM_Try, /*On fail goto*//*Label 14796*/ GIMT_Encode4(923806), // Rule ID 8060 //
     /*  923726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  923729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  923734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  923737 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  923740 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  923743 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  923746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  923750 */     // MIs[0] src0_modifiers
     /*  923750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923753 */     // MIs[0] src1_modifiers
     /*  923753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923756 */     // MIs[0] src2_modifiers
     /*  923756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  923759 */     // MIs[0] matrix_a_reuse
     /*  923759 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923762 */     // MIs[0] matrix_b_reuse
     /*  923762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923765 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr),
     /*  923768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923770 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  923776 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923778 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  923784 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923786 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  923792 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  923794 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923796 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923804 */     GIR_RootConstrainSelectedInstOperands,
     /*  923805 */     // GIR_Coverage, 8060,
     /*  923805 */     GIR_EraseRootFromParent_Done,
     /*  923806 */   // Label 14796: @923806
     /*  923806 */   GIM_Try, /*On fail goto*//*Label 14797*/ GIMT_Encode4(923891), // Rule ID 8061 //
     /*  923811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  923814 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  923819 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  923822 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  923825 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  923828 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  923831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  923835 */     // MIs[0] src0_modifiers
     /*  923835 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923838 */     // MIs[0] src1_modifiers
     /*  923838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923841 */     // MIs[0] src2_modifiers
     /*  923841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  923844 */     // MIs[0] matrix_a_reuse
     /*  923844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923847 */     // MIs[0] matrix_b_reuse
     /*  923847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923850 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr),
     /*  923853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923855 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  923861 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923863 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  923869 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923871 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  923877 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  923879 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923881 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923889 */     GIR_RootConstrainSelectedInstOperands,
     /*  923890 */     // GIR_Coverage, 8061,
     /*  923890 */     GIR_EraseRootFromParent_Done,
     /*  923891 */   // Label 14797: @923891
     /*  923891 */   GIM_Try, /*On fail goto*//*Label 14798*/ GIMT_Encode4(923976), // Rule ID 8062 //
     /*  923896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  923899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x4_f32),
     /*  923904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  923907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  923910 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32,
     /*  923913 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  923916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  923920 */     // MIs[0] src0_modifiers
     /*  923920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  923923 */     // MIs[0] src1_modifiers
     /*  923923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  923926 */     // MIs[0] src2_modifiers
     /*  923926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  923929 */     // MIs[0] matrix_a_reuse
     /*  923929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  923932 */     // MIs[0] matrix_b_reuse
     /*  923932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  923935 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3658:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X4_F32_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v2f32:{ *:[v2f32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v2f32:{ *:[v2f32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  923935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X4_F32_w32_twoaddr),
     /*  923938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  923940 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  923946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  923948 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  923954 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  923956 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  923962 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  923964 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  923966 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  923968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  923974 */     GIR_RootConstrainSelectedInstOperands,
     /*  923975 */     // GIR_Coverage, 8062,
     /*  923975 */     GIR_EraseRootFromParent_Done,
     /*  923976 */   // Label 14798: @923976
     /*  923976 */   GIM_Try, /*On fail goto*//*Label 14799*/ GIMT_Encode4(924061), // Rule ID 8158 //
     /*  923981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  923984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  923989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  923992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  923995 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  923998 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  924001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924005 */     // MIs[0] src0_modifiers
     /*  924005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924008 */     // MIs[0] src1_modifiers
     /*  924008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924011 */     // MIs[0] src2_modifiers
     /*  924011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924014 */     // MIs[0] matrix_a_reuse
     /*  924014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924017 */     // MIs[0] matrix_b_reuse
     /*  924017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924020 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr),
     /*  924023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924025 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924031 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924033 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924039 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924041 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924047 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924049 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924051 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924059 */     GIR_RootConstrainSelectedInstOperands,
     /*  924060 */     // GIR_Coverage, 8158,
     /*  924060 */     GIR_EraseRootFromParent_Done,
     /*  924061 */   // Label 14799: @924061
     /*  924061 */   GIM_Try, /*On fail goto*//*Label 14800*/ GIMT_Encode4(924146), // Rule ID 8159 //
     /*  924066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  924069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  924074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924080 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924083 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  924086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924090 */     // MIs[0] src0_modifiers
     /*  924090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924093 */     // MIs[0] src1_modifiers
     /*  924093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924096 */     // MIs[0] src2_modifiers
     /*  924096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924099 */     // MIs[0] matrix_a_reuse
     /*  924099 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924102 */     // MIs[0] matrix_b_reuse
     /*  924102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924105 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr),
     /*  924108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924110 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924116 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924118 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924124 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924126 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924132 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924134 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924136 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924144 */     GIR_RootConstrainSelectedInstOperands,
     /*  924145 */     // GIR_Coverage, 8159,
     /*  924145 */     GIR_EraseRootFromParent_Done,
     /*  924146 */   // Label 14800: @924146
     /*  924146 */   GIM_Try, /*On fail goto*//*Label 14801*/ GIMT_Encode4(924231), // Rule ID 8160 //
     /*  924151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  924154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  924159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924165 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924168 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  924171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924175 */     // MIs[0] src0_modifiers
     /*  924175 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924178 */     // MIs[0] src1_modifiers
     /*  924178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924181 */     // MIs[0] src2_modifiers
     /*  924181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924184 */     // MIs[0] matrix_a_reuse
     /*  924184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924187 */     // MIs[0] matrix_b_reuse
     /*  924187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924190 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr),
     /*  924193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924195 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924201 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924203 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924209 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924217 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924219 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924221 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924223 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924229 */     GIR_RootConstrainSelectedInstOperands,
     /*  924230 */     // GIR_Coverage, 8160,
     /*  924230 */     GIR_EraseRootFromParent_Done,
     /*  924231 */   // Label 14801: @924231
     /*  924231 */   GIM_Try, /*On fail goto*//*Label 14802*/ GIMT_Encode4(924316), // Rule ID 8161 //
     /*  924236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  924239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  924244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924250 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924253 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  924256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924260 */     // MIs[0] src0_modifiers
     /*  924260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924263 */     // MIs[0] src1_modifiers
     /*  924263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924266 */     // MIs[0] src2_modifiers
     /*  924266 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924269 */     // MIs[0] matrix_a_reuse
     /*  924269 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924272 */     // MIs[0] matrix_b_reuse
     /*  924272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924275 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr),
     /*  924278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924280 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924286 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924288 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924294 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924296 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924302 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924304 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924306 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924314 */     GIR_RootConstrainSelectedInstOperands,
     /*  924315 */     // GIR_Coverage, 8161,
     /*  924315 */     GIR_EraseRootFromParent_Done,
     /*  924316 */   // Label 14802: @924316
     /*  924316 */   GIM_Try, /*On fail goto*//*Label 14803*/ GIMT_Encode4(924401), // Rule ID 8162 //
     /*  924321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  924324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x32_f16),
     /*  924329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924335 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924338 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  924341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924345 */     // MIs[0] src0_modifiers
     /*  924345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924348 */     // MIs[0] src1_modifiers
     /*  924348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924351 */     // MIs[0] src2_modifiers
     /*  924351 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924354 */     // MIs[0] matrix_a_reuse
     /*  924354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924357 */     // MIs[0] matrix_b_reuse
     /*  924357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924360 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3657:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X32_F16_w32_twoaddr),
     /*  924363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924365 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924371 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924373 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924379 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924381 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924387 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924389 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924391 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924399 */     GIR_RootConstrainSelectedInstOperands,
     /*  924400 */     // GIR_Coverage, 8162,
     /*  924400 */     GIR_EraseRootFromParent_Done,
     /*  924401 */   // Label 14803: @924401
     /*  924401 */   GIM_Try, /*On fail goto*//*Label 14804*/ GIMT_Encode4(924486), // Rule ID 8168 //
     /*  924406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  924409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  924414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  924417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924420 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924423 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  924426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  924430 */     // MIs[0] src0_modifiers
     /*  924430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924433 */     // MIs[0] src1_modifiers
     /*  924433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924436 */     // MIs[0] src2_modifiers
     /*  924436 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924439 */     // MIs[0] matrix_a_reuse
     /*  924439 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924442 */     // MIs[0] matrix_b_reuse
     /*  924442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924445 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr),
     /*  924448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924450 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924456 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924458 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924464 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924466 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924472 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924474 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924476 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924478 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924484 */     GIR_RootConstrainSelectedInstOperands,
     /*  924485 */     // GIR_Coverage, 8168,
     /*  924485 */     GIR_EraseRootFromParent_Done,
     /*  924486 */   // Label 14804: @924486
     /*  924486 */   GIM_Try, /*On fail goto*//*Label 14805*/ GIMT_Encode4(924571), // Rule ID 8169 //
     /*  924491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  924494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  924499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  924502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924505 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924508 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  924511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  924515 */     // MIs[0] src0_modifiers
     /*  924515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924518 */     // MIs[0] src1_modifiers
     /*  924518 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924521 */     // MIs[0] src2_modifiers
     /*  924521 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924524 */     // MIs[0] matrix_a_reuse
     /*  924524 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924527 */     // MIs[0] matrix_b_reuse
     /*  924527 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924530 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr),
     /*  924533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924535 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924541 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924543 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924549 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924551 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924557 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924559 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924561 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924569 */     GIR_RootConstrainSelectedInstOperands,
     /*  924570 */     // GIR_Coverage, 8169,
     /*  924570 */     GIR_EraseRootFromParent_Done,
     /*  924571 */   // Label 14805: @924571
     /*  924571 */   GIM_Try, /*On fail goto*//*Label 14806*/ GIMT_Encode4(924656), // Rule ID 8170 //
     /*  924576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  924579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  924584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  924587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924590 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924593 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  924596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  924600 */     // MIs[0] src0_modifiers
     /*  924600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924603 */     // MIs[0] src1_modifiers
     /*  924603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924606 */     // MIs[0] src2_modifiers
     /*  924606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924609 */     // MIs[0] matrix_a_reuse
     /*  924609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924612 */     // MIs[0] matrix_b_reuse
     /*  924612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924615 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr),
     /*  924618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924620 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924626 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924628 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924634 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924636 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924642 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924644 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924646 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924654 */     GIR_RootConstrainSelectedInstOperands,
     /*  924655 */     // GIR_Coverage, 8170,
     /*  924655 */     GIR_EraseRootFromParent_Done,
     /*  924656 */   // Label 14806: @924656
     /*  924656 */   GIM_Try, /*On fail goto*//*Label 14807*/ GIMT_Encode4(924741), // Rule ID 8171 //
     /*  924661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  924664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  924669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  924672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924675 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924678 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  924681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  924685 */     // MIs[0] src0_modifiers
     /*  924685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924688 */     // MIs[0] src1_modifiers
     /*  924688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924691 */     // MIs[0] src2_modifiers
     /*  924691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924694 */     // MIs[0] matrix_a_reuse
     /*  924694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924697 */     // MIs[0] matrix_b_reuse
     /*  924697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924700 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr),
     /*  924703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924705 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924711 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924713 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924719 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924721 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924727 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924729 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924731 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924739 */     GIR_RootConstrainSelectedInstOperands,
     /*  924740 */     // GIR_Coverage, 8171,
     /*  924740 */     GIR_EraseRootFromParent_Done,
     /*  924741 */   // Label 14807: @924741
     /*  924741 */   GIM_Try, /*On fail goto*//*Label 14808*/ GIMT_Encode4(924826), // Rule ID 8172 //
     /*  924746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  924749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x32_f16),
     /*  924754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  924757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16,
     /*  924760 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s16,
     /*  924763 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
     /*  924766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  924770 */     // MIs[0] src0_modifiers
     /*  924770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924773 */     // MIs[0] src1_modifiers
     /*  924773 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924776 */     // MIs[0] src2_modifiers
     /*  924776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  924779 */     // MIs[0] matrix_a_reuse
     /*  924779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924782 */     // MIs[0] matrix_b_reuse
     /*  924782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  924785 */     // (intrinsic_wo_chain:{ *:[v8f16] } 3640:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f16:{ *:[v8f16] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v16f16:{ *:[v16f16] }:$src0, (VOP3PModsNegs:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16f16:{ *:[v16f16] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f16:{ *:[v8f16] }:$src2, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X32_F16_w32_twoaddr),
     /*  924788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924790 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src0_modifiers
     /*  924796 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924798 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegs), // src1_modifiers
     /*  924804 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924806 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  924812 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  924814 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  924816 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  924818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924824 */     GIR_RootConstrainSelectedInstOperands,
     /*  924825 */     // GIR_Coverage, 8172,
     /*  924825 */     GIR_EraseRootFromParent_Done,
     /*  924826 */   // Label 14808: @924826
     /*  924826 */   GIM_Try, /*On fail goto*//*Label 14809*/ GIMT_Encode4(924901), // Rule ID 8148 //
     /*  924831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  924834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  924839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  924845 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  924848 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  924851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924855 */     // MIs[0] src0_modifiers
     /*  924855 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924858 */     // MIs[0] src1_modifiers
     /*  924858 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924861 */     // MIs[0] matrix_a_reuse
     /*  924861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  924864 */     // MIs[0] matrix_b_reuse
     /*  924864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924867 */     // MIs[0] clamp
     /*  924867 */     // No operand predicates
     /*  924867 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr),
     /*  924870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924872 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  924878 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924880 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  924886 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924888 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  924890 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  924892 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  924894 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  924896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924899 */     GIR_RootConstrainSelectedInstOperands,
     /*  924900 */     // GIR_Coverage, 8148,
     /*  924900 */     GIR_EraseRootFromParent_Done,
     /*  924901 */   // Label 14809: @924901
     /*  924901 */   GIM_Try, /*On fail goto*//*Label 14810*/ GIMT_Encode4(924976), // Rule ID 8149 //
     /*  924906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  924909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  924914 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924917 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  924920 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  924923 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  924926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  924930 */     // MIs[0] src0_modifiers
     /*  924930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  924933 */     // MIs[0] src1_modifiers
     /*  924933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  924936 */     // MIs[0] matrix_a_reuse
     /*  924936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  924939 */     // MIs[0] matrix_b_reuse
     /*  924939 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  924942 */     // MIs[0] clamp
     /*  924942 */     // No operand predicates
     /*  924942 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  924942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr),
     /*  924945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  924947 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  924953 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  924955 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  924961 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  924963 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  924965 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  924967 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  924969 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  924971 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  924974 */     GIR_RootConstrainSelectedInstOperands,
     /*  924975 */     // GIR_Coverage, 8149,
     /*  924975 */     GIR_EraseRootFromParent_Done,
     /*  924976 */   // Label 14810: @924976
     /*  924976 */   GIM_Try, /*On fail goto*//*Label 14811*/ GIMT_Encode4(925051), // Rule ID 8150 //
     /*  924981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  924984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  924989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  924992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  924995 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  924998 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925005 */     // MIs[0] src0_modifiers
     /*  925005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925008 */     // MIs[0] src1_modifiers
     /*  925008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925011 */     // MIs[0] matrix_a_reuse
     /*  925011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  925014 */     // MIs[0] matrix_b_reuse
     /*  925014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925017 */     // MIs[0] clamp
     /*  925017 */     // No operand predicates
     /*  925017 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr),
     /*  925020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925022 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925028 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925030 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925036 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925038 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  925040 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  925042 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  925044 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  925046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925049 */     GIR_RootConstrainSelectedInstOperands,
     /*  925050 */     // GIR_Coverage, 8150,
     /*  925050 */     GIR_EraseRootFromParent_Done,
     /*  925051 */   // Label 14811: @925051
     /*  925051 */   GIM_Try, /*On fail goto*//*Label 14812*/ GIMT_Encode4(925126), // Rule ID 8151 //
     /*  925056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  925059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  925064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925070 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  925073 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925080 */     // MIs[0] src0_modifiers
     /*  925080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925083 */     // MIs[0] src1_modifiers
     /*  925083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925086 */     // MIs[0] matrix_a_reuse
     /*  925086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  925089 */     // MIs[0] matrix_b_reuse
     /*  925089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925092 */     // MIs[0] clamp
     /*  925092 */     // No operand predicates
     /*  925092 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr),
     /*  925095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925097 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925103 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925105 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925111 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925113 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  925115 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  925117 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  925119 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  925121 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925124 */     GIR_RootConstrainSelectedInstOperands,
     /*  925125 */     // GIR_Coverage, 8151,
     /*  925125 */     GIR_EraseRootFromParent_Done,
     /*  925126 */   // Label 14812: @925126
     /*  925126 */   GIM_Try, /*On fail goto*//*Label 14813*/ GIMT_Encode4(925201), // Rule ID 8152 //
     /*  925131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  925134 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x64_iu8),
     /*  925139 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925145 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  925148 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925155 */     // MIs[0] src0_modifiers
     /*  925155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925158 */     // MIs[0] src1_modifiers
     /*  925158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925161 */     // MIs[0] matrix_a_reuse
     /*  925161 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  925164 */     // MIs[0] matrix_b_reuse
     /*  925164 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925167 */     // MIs[0] clamp
     /*  925167 */     // No operand predicates
     /*  925167 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3667:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X64_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v8i32:{ *:[v8i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X64_IU8_w32_twoaddr),
     /*  925170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925172 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925178 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925180 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925186 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925188 */     GIR_RootToRootCopy, /*OpIdx*/6, // src2
     /*  925190 */     GIR_RootToRootCopy, /*OpIdx*/9, // clamp
     /*  925192 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_reuse
     /*  925194 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_b_reuse
     /*  925196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925199 */     GIR_RootConstrainSelectedInstOperands,
     /*  925200 */     // GIR_Coverage, 8152,
     /*  925200 */     GIR_EraseRootFromParent_Done,
     /*  925201 */   // Label 14813: @925201
     /*  925201 */   GIM_Reject,
     /*  925202 */ // Label 14763: @925202
     /*  925202 */ GIM_Try, /*On fail goto*//*Label 14814*/ GIMT_Encode4(954486),
     /*  925207 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/11,
     /*  925210 */   GIM_Try, /*On fail goto*//*Label 14815*/ GIMT_Encode4(925305), // Rule ID 8598 //
     /*  925215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  925218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x128_iu8),
     /*  925223 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925229 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  925232 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925235 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s64,
     /*  925238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925242 */     // MIs[0] src0_modifiers
     /*  925242 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925245 */     // MIs[0] src1_modifiers
     /*  925245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925248 */     // MIs[0] matrix_a_reuse
     /*  925248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925251 */     // MIs[0] matrix_b_reuse
     /*  925251 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  925254 */     // MIs[0] clamp
     /*  925254 */     // No operand predicates
     /*  925254 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  925261 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3597:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr),
     /*  925264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925266 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925272 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925274 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925280 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925282 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  925284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  925289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  925294 */     GIR_RootToRootCopy, /*OpIdx*/10, // clamp
     /*  925296 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  925298 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  925300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925303 */     GIR_RootConstrainSelectedInstOperands,
     /*  925304 */     // GIR_Coverage, 8598,
     /*  925304 */     GIR_EraseRootFromParent_Done,
     /*  925305 */   // Label 14815: @925305
     /*  925305 */   GIM_Try, /*On fail goto*//*Label 14816*/ GIMT_Encode4(925400), // Rule ID 8599 //
     /*  925310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  925313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x128_iu8),
     /*  925318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925321 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925324 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  925327 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925330 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s64,
     /*  925333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925337 */     // MIs[0] src0_modifiers
     /*  925337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925340 */     // MIs[0] src1_modifiers
     /*  925340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925343 */     // MIs[0] matrix_a_reuse
     /*  925343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925346 */     // MIs[0] matrix_b_reuse
     /*  925346 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  925349 */     // MIs[0] clamp
     /*  925349 */     // No operand predicates
     /*  925349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  925356 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3597:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr),
     /*  925359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925361 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925367 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925369 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925375 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925377 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  925379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  925384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  925389 */     GIR_RootToRootCopy, /*OpIdx*/10, // clamp
     /*  925391 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  925393 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  925395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925398 */     GIR_RootConstrainSelectedInstOperands,
     /*  925399 */     // GIR_Coverage, 8599,
     /*  925399 */     GIR_EraseRootFromParent_Done,
     /*  925400 */   // Label 14816: @925400
     /*  925400 */   GIM_Try, /*On fail goto*//*Label 14817*/ GIMT_Encode4(925495), // Rule ID 8600 //
     /*  925405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  925408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x128_iu8),
     /*  925413 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925419 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  925422 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925425 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s64,
     /*  925428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925432 */     // MIs[0] src0_modifiers
     /*  925432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925435 */     // MIs[0] src1_modifiers
     /*  925435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925438 */     // MIs[0] matrix_a_reuse
     /*  925438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925441 */     // MIs[0] matrix_b_reuse
     /*  925441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  925444 */     // MIs[0] clamp
     /*  925444 */     // No operand predicates
     /*  925444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  925451 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3597:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr),
     /*  925454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925456 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925462 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925464 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925470 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925472 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  925474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  925479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  925484 */     GIR_RootToRootCopy, /*OpIdx*/10, // clamp
     /*  925486 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  925488 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  925490 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925493 */     GIR_RootConstrainSelectedInstOperands,
     /*  925494 */     // GIR_Coverage, 8600,
     /*  925494 */     GIR_EraseRootFromParent_Done,
     /*  925495 */   // Label 14817: @925495
     /*  925495 */   GIM_Try, /*On fail goto*//*Label 14818*/ GIMT_Encode4(925590), // Rule ID 8601 //
     /*  925500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  925503 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x128_iu8),
     /*  925508 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925514 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  925517 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925520 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s64,
     /*  925523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925527 */     // MIs[0] src0_modifiers
     /*  925527 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925530 */     // MIs[0] src1_modifiers
     /*  925530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925533 */     // MIs[0] matrix_a_reuse
     /*  925533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925536 */     // MIs[0] matrix_b_reuse
     /*  925536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  925539 */     // MIs[0] clamp
     /*  925539 */     // No operand predicates
     /*  925539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  925546 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3597:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr),
     /*  925549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925551 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925557 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925559 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925565 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925567 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  925569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  925574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  925579 */     GIR_RootToRootCopy, /*OpIdx*/10, // clamp
     /*  925581 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  925583 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  925585 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925588 */     GIR_RootConstrainSelectedInstOperands,
     /*  925589 */     // GIR_Coverage, 8601,
     /*  925589 */     GIR_EraseRootFromParent_Done,
     /*  925590 */   // Label 14818: @925590
     /*  925590 */   GIM_Try, /*On fail goto*//*Label 14819*/ GIMT_Encode4(925685), // Rule ID 8602 //
     /*  925595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  925598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x128_iu8),
     /*  925603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  925606 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925609 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  925612 */     GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32,
     /*  925615 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s64,
     /*  925618 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  925622 */     // MIs[0] src0_modifiers
     /*  925622 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  925625 */     // MIs[0] src1_modifiers
     /*  925625 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  925628 */     // MIs[0] matrix_a_reuse
     /*  925628 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  925631 */     // MIs[0] matrix_b_reuse
     /*  925631 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  925634 */     // MIs[0] clamp
     /*  925634 */     // No operand predicates
     /*  925634 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex32),
     /*  925641 */     // (intrinsic_wo_chain:{ *:[v8i32] } 3597:{ *:[iPTR] }, (timm:{ *:[i1] }):$src0_modifiers, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i1] }):$src1_modifiers, v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex32:{ *:[i64] } i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit), (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr:{ *:[v8i32] } (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src0_modifiers), v8i32:{ *:[v8i32] }:$src0, (VOP3PModsNeg:{ *:[i32] } ?:{ *:[i1] }:$src1_modifiers), v16i32:{ *:[v16i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i64:{ *:[i64] }:$src2, i32:{ *:[i32] }:$index_key_32bit, i1:{ *:[i1] }:$clamp, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  925641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr),
     /*  925644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925646 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src0_modifiers
     /*  925652 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  925654 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNeg), // src1_modifiers
     /*  925660 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  925662 */     GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef
     /*  925664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  925669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_32bit
     /*  925674 */     GIR_RootToRootCopy, /*OpIdx*/10, // clamp
     /*  925676 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_reuse
     /*  925678 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_reuse
     /*  925680 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  925683 */     GIR_RootConstrainSelectedInstOperands,
     /*  925684 */     // GIR_Coverage, 8602,
     /*  925684 */     GIR_EraseRootFromParent_Done,
     /*  925685 */   // Label 14819: @925685
     /*  925685 */   GIM_Try, /*On fail goto*//*Label 14820*/ GIMT_Encode4(925755), // Rule ID 3544 //
     /*  925690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  925693 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  925698 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  925701 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  925704 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925707 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  925710 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  925713 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  925716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  925720 */     // MIs[0] cbsz
     /*  925720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  925723 */     // MIs[0] blgp
     /*  925723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  925726 */     // MIs[0] Operand 7
     /*  925726 */     // No operand predicates
     /*  925726 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  925730 */     // MIs[0] Operand 9
     /*  925730 */     // No operand predicates
     /*  925730 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  925734 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  925738 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  925738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  925741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925743 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  925745 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  925747 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  925749 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  925751 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  925753 */     GIR_RootConstrainSelectedInstOperands,
     /*  925754 */     // GIR_Coverage, 3544,
     /*  925754 */     GIR_EraseRootFromParent_Done,
     /*  925755 */   // Label 14820: @925755
     /*  925755 */   GIM_Try, /*On fail goto*//*Label 14821*/ GIMT_Encode4(925825), // Rule ID 3545 //
     /*  925760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  925763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  925768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  925771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  925774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  925780 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  925783 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  925786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  925790 */     // MIs[0] cbsz
     /*  925790 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  925793 */     // MIs[0] blgp
     /*  925793 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  925796 */     // MIs[0] Operand 7
     /*  925796 */     // No operand predicates
     /*  925796 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  925800 */     // MIs[0] Operand 9
     /*  925800 */     // No operand predicates
     /*  925800 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  925804 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  925808 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  925808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  925811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925813 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  925815 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  925817 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  925819 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  925821 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  925823 */     GIR_RootConstrainSelectedInstOperands,
     /*  925824 */     // GIR_Coverage, 3545,
     /*  925824 */     GIR_EraseRootFromParent_Done,
     /*  925825 */   // Label 14821: @925825
     /*  925825 */   GIM_Try, /*On fail goto*//*Label 14822*/ GIMT_Encode4(925895), // Rule ID 3546 //
     /*  925830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  925833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  925838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  925841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  925844 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925847 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  925850 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  925853 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  925856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  925860 */     // MIs[0] cbsz
     /*  925860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  925863 */     // MIs[0] blgp
     /*  925863 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  925866 */     // MIs[0] Operand 7
     /*  925866 */     // No operand predicates
     /*  925866 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  925870 */     // MIs[0] Operand 9
     /*  925870 */     // No operand predicates
     /*  925870 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  925874 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  925878 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  925878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  925881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925883 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  925885 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  925887 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  925889 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  925891 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  925893 */     GIR_RootConstrainSelectedInstOperands,
     /*  925894 */     // GIR_Coverage, 3546,
     /*  925894 */     GIR_EraseRootFromParent_Done,
     /*  925895 */   // Label 14822: @925895
     /*  925895 */   GIM_Try, /*On fail goto*//*Label 14823*/ GIMT_Encode4(925965), // Rule ID 3547 //
     /*  925900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  925903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  925908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  925911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  925914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925917 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  925920 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  925923 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  925926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  925930 */     // MIs[0] cbsz
     /*  925930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  925933 */     // MIs[0] blgp
     /*  925933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  925936 */     // MIs[0] Operand 7
     /*  925936 */     // No operand predicates
     /*  925936 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  925940 */     // MIs[0] Operand 9
     /*  925940 */     // No operand predicates
     /*  925940 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  925944 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  925948 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  925948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  925951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  925953 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  925955 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  925957 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  925959 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  925961 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  925963 */     GIR_RootConstrainSelectedInstOperands,
     /*  925964 */     // GIR_Coverage, 3547,
     /*  925964 */     GIR_EraseRootFromParent_Done,
     /*  925965 */   // Label 14823: @925965
     /*  925965 */   GIM_Try, /*On fail goto*//*Label 14824*/ GIMT_Encode4(926035), // Rule ID 3548 //
     /*  925970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  925973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  925978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  925981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  925984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  925987 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  925990 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  925993 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  925996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926000 */     // MIs[0] cbsz
     /*  926000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926003 */     // MIs[0] blgp
     /*  926003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926006 */     // MIs[0] Operand 7
     /*  926006 */     // No operand predicates
     /*  926006 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926010 */     // MIs[0] Operand 9
     /*  926010 */     // No operand predicates
     /*  926010 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926014 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926018 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  926021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926023 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926025 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926027 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926029 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926031 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926033 */     GIR_RootConstrainSelectedInstOperands,
     /*  926034 */     // GIR_Coverage, 3548,
     /*  926034 */     GIR_EraseRootFromParent_Done,
     /*  926035 */   // Label 14824: @926035
     /*  926035 */   GIM_Try, /*On fail goto*//*Label 14825*/ GIMT_Encode4(926105), // Rule ID 3554 //
     /*  926040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  926043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  926054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926057 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926060 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926063 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926070 */     // MIs[0] cbsz
     /*  926070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926073 */     // MIs[0] blgp
     /*  926073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926076 */     // MIs[0] Operand 7
     /*  926076 */     // No operand predicates
     /*  926076 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926080 */     // MIs[0] Operand 9
     /*  926080 */     // No operand predicates
     /*  926080 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926084 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926088 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  926091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926097 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926099 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926101 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926103 */     GIR_RootConstrainSelectedInstOperands,
     /*  926104 */     // GIR_Coverage, 3554,
     /*  926104 */     GIR_EraseRootFromParent_Done,
     /*  926105 */   // Label 14825: @926105
     /*  926105 */   GIM_Try, /*On fail goto*//*Label 14826*/ GIMT_Encode4(926175), // Rule ID 3555 //
     /*  926110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  926113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  926124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926127 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926130 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926133 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926140 */     // MIs[0] cbsz
     /*  926140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926143 */     // MIs[0] blgp
     /*  926143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926146 */     // MIs[0] Operand 7
     /*  926146 */     // No operand predicates
     /*  926146 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926150 */     // MIs[0] Operand 9
     /*  926150 */     // No operand predicates
     /*  926150 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926154 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926158 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  926161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926163 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926165 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926167 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926169 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926171 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926173 */     GIR_RootConstrainSelectedInstOperands,
     /*  926174 */     // GIR_Coverage, 3555,
     /*  926174 */     GIR_EraseRootFromParent_Done,
     /*  926175 */   // Label 14826: @926175
     /*  926175 */   GIM_Try, /*On fail goto*//*Label 14827*/ GIMT_Encode4(926245), // Rule ID 3556 //
     /*  926180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  926183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  926194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926197 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926200 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926203 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926210 */     // MIs[0] cbsz
     /*  926210 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926213 */     // MIs[0] blgp
     /*  926213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926216 */     // MIs[0] Operand 7
     /*  926216 */     // No operand predicates
     /*  926216 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926220 */     // MIs[0] Operand 9
     /*  926220 */     // No operand predicates
     /*  926220 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926224 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926228 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  926231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926233 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926235 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926237 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926239 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926241 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926243 */     GIR_RootConstrainSelectedInstOperands,
     /*  926244 */     // GIR_Coverage, 3556,
     /*  926244 */     GIR_EraseRootFromParent_Done,
     /*  926245 */   // Label 14827: @926245
     /*  926245 */   GIM_Try, /*On fail goto*//*Label 14828*/ GIMT_Encode4(926315), // Rule ID 3557 //
     /*  926250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  926253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  926264 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926267 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926270 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926273 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926280 */     // MIs[0] cbsz
     /*  926280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926283 */     // MIs[0] blgp
     /*  926283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926286 */     // MIs[0] Operand 7
     /*  926286 */     // No operand predicates
     /*  926286 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926290 */     // MIs[0] Operand 9
     /*  926290 */     // No operand predicates
     /*  926290 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926294 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926298 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  926301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926303 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926305 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926307 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926309 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926311 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926313 */     GIR_RootConstrainSelectedInstOperands,
     /*  926314 */     // GIR_Coverage, 3557,
     /*  926314 */     GIR_EraseRootFromParent_Done,
     /*  926315 */   // Label 14828: @926315
     /*  926315 */   GIM_Try, /*On fail goto*//*Label 14829*/ GIMT_Encode4(926385), // Rule ID 3558 //
     /*  926320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  926323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  926334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926340 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926343 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926350 */     // MIs[0] cbsz
     /*  926350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926353 */     // MIs[0] blgp
     /*  926353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926356 */     // MIs[0] Operand 7
     /*  926356 */     // No operand predicates
     /*  926356 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926360 */     // MIs[0] Operand 9
     /*  926360 */     // No operand predicates
     /*  926360 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926364 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926368 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  926371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926373 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926375 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926377 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926379 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926381 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926383 */     GIR_RootConstrainSelectedInstOperands,
     /*  926384 */     // GIR_Coverage, 3558,
     /*  926384 */     GIR_EraseRootFromParent_Done,
     /*  926385 */   // Label 14829: @926385
     /*  926385 */   GIM_Try, /*On fail goto*//*Label 14830*/ GIMT_Encode4(926455), // Rule ID 3564 //
     /*  926390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  926393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  926407 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926410 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926413 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926420 */     // MIs[0] cbsz
     /*  926420 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926423 */     // MIs[0] blgp
     /*  926423 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926426 */     // MIs[0] Operand 7
     /*  926426 */     // No operand predicates
     /*  926426 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926430 */     // MIs[0] Operand 9
     /*  926430 */     // No operand predicates
     /*  926430 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926434 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926438 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  926441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926443 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926445 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926447 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926449 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926451 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926453 */     GIR_RootConstrainSelectedInstOperands,
     /*  926454 */     // GIR_Coverage, 3564,
     /*  926454 */     GIR_EraseRootFromParent_Done,
     /*  926455 */   // Label 14830: @926455
     /*  926455 */   GIM_Try, /*On fail goto*//*Label 14831*/ GIMT_Encode4(926525), // Rule ID 3565 //
     /*  926460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  926463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  926477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926480 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926483 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926490 */     // MIs[0] cbsz
     /*  926490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926493 */     // MIs[0] blgp
     /*  926493 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926496 */     // MIs[0] Operand 7
     /*  926496 */     // No operand predicates
     /*  926496 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926500 */     // MIs[0] Operand 9
     /*  926500 */     // No operand predicates
     /*  926500 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926504 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926508 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  926511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926513 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926515 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926517 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926519 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926521 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926523 */     GIR_RootConstrainSelectedInstOperands,
     /*  926524 */     // GIR_Coverage, 3565,
     /*  926524 */     GIR_EraseRootFromParent_Done,
     /*  926525 */   // Label 14831: @926525
     /*  926525 */   GIM_Try, /*On fail goto*//*Label 14832*/ GIMT_Encode4(926595), // Rule ID 3566 //
     /*  926530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  926533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926544 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  926547 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926550 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926553 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926560 */     // MIs[0] cbsz
     /*  926560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926563 */     // MIs[0] blgp
     /*  926563 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926566 */     // MIs[0] Operand 7
     /*  926566 */     // No operand predicates
     /*  926566 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926570 */     // MIs[0] Operand 9
     /*  926570 */     // No operand predicates
     /*  926570 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926574 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926578 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  926581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926583 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926585 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926587 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926589 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926591 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926593 */     GIR_RootConstrainSelectedInstOperands,
     /*  926594 */     // GIR_Coverage, 3566,
     /*  926594 */     GIR_EraseRootFromParent_Done,
     /*  926595 */   // Label 14832: @926595
     /*  926595 */   GIM_Try, /*On fail goto*//*Label 14833*/ GIMT_Encode4(926665), // Rule ID 3567 //
     /*  926600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  926603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  926617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926620 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926623 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926630 */     // MIs[0] cbsz
     /*  926630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926633 */     // MIs[0] blgp
     /*  926633 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926636 */     // MIs[0] Operand 7
     /*  926636 */     // No operand predicates
     /*  926636 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926640 */     // MIs[0] Operand 9
     /*  926640 */     // No operand predicates
     /*  926640 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926644 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926648 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  926651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926653 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926655 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926657 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926659 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926661 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926663 */     GIR_RootConstrainSelectedInstOperands,
     /*  926664 */     // GIR_Coverage, 3567,
     /*  926664 */     GIR_EraseRootFromParent_Done,
     /*  926665 */   // Label 14833: @926665
     /*  926665 */   GIM_Try, /*On fail goto*//*Label 14834*/ GIMT_Encode4(926735), // Rule ID 3568 //
     /*  926670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  926673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  926687 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926690 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926693 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926700 */     // MIs[0] cbsz
     /*  926700 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926703 */     // MIs[0] blgp
     /*  926703 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926706 */     // MIs[0] Operand 7
     /*  926706 */     // No operand predicates
     /*  926706 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926710 */     // MIs[0] Operand 9
     /*  926710 */     // No operand predicates
     /*  926710 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926714 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926718 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  926721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926723 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926725 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926727 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926729 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926731 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926733 */     GIR_RootConstrainSelectedInstOperands,
     /*  926734 */     // GIR_Coverage, 3568,
     /*  926734 */     GIR_EraseRootFromParent_Done,
     /*  926735 */   // Label 14834: @926735
     /*  926735 */   GIM_Try, /*On fail goto*//*Label 14835*/ GIMT_Encode4(926805), // Rule ID 3574 //
     /*  926740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  926743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926754 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926757 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926760 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926763 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926770 */     // MIs[0] cbsz
     /*  926770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926773 */     // MIs[0] blgp
     /*  926773 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926776 */     // MIs[0] Operand 7
     /*  926776 */     // No operand predicates
     /*  926776 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926780 */     // MIs[0] Operand 9
     /*  926780 */     // No operand predicates
     /*  926780 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926784 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926788 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  926791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926793 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926795 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926797 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926799 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926801 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926803 */     GIR_RootConstrainSelectedInstOperands,
     /*  926804 */     // GIR_Coverage, 3574,
     /*  926804 */     GIR_EraseRootFromParent_Done,
     /*  926805 */   // Label 14835: @926805
     /*  926805 */   GIM_Try, /*On fail goto*//*Label 14836*/ GIMT_Encode4(926875), // Rule ID 3575 //
     /*  926810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  926813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926827 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926830 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926833 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926840 */     // MIs[0] cbsz
     /*  926840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926843 */     // MIs[0] blgp
     /*  926843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926846 */     // MIs[0] Operand 7
     /*  926846 */     // No operand predicates
     /*  926846 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926850 */     // MIs[0] Operand 9
     /*  926850 */     // No operand predicates
     /*  926850 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926854 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926858 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  926861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926863 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926865 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926867 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926869 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926871 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926873 */     GIR_RootConstrainSelectedInstOperands,
     /*  926874 */     // GIR_Coverage, 3575,
     /*  926874 */     GIR_EraseRootFromParent_Done,
     /*  926875 */   // Label 14836: @926875
     /*  926875 */   GIM_Try, /*On fail goto*//*Label 14837*/ GIMT_Encode4(926945), // Rule ID 3576 //
     /*  926880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  926883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926900 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926903 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926910 */     // MIs[0] cbsz
     /*  926910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926913 */     // MIs[0] blgp
     /*  926913 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926916 */     // MIs[0] Operand 7
     /*  926916 */     // No operand predicates
     /*  926916 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926920 */     // MIs[0] Operand 9
     /*  926920 */     // No operand predicates
     /*  926920 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926928 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  926931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  926933 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  926935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  926937 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  926939 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  926941 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  926943 */     GIR_RootConstrainSelectedInstOperands,
     /*  926944 */     // GIR_Coverage, 3576,
     /*  926944 */     GIR_EraseRootFromParent_Done,
     /*  926945 */   // Label 14837: @926945
     /*  926945 */   GIM_Try, /*On fail goto*//*Label 14838*/ GIMT_Encode4(927015), // Rule ID 3577 //
     /*  926950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  926953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  926958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  926961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  926964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  926967 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  926970 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  926973 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  926976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  926980 */     // MIs[0] cbsz
     /*  926980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  926983 */     // MIs[0] blgp
     /*  926983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  926986 */     // MIs[0] Operand 7
     /*  926986 */     // No operand predicates
     /*  926986 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  926990 */     // MIs[0] Operand 9
     /*  926990 */     // No operand predicates
     /*  926990 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  926994 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  926998 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  926998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  927001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927003 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927005 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927007 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927009 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927011 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927013 */     GIR_RootConstrainSelectedInstOperands,
     /*  927014 */     // GIR_Coverage, 3577,
     /*  927014 */     GIR_EraseRootFromParent_Done,
     /*  927015 */   // Label 14838: @927015
     /*  927015 */   GIM_Try, /*On fail goto*//*Label 14839*/ GIMT_Encode4(927085), // Rule ID 3578 //
     /*  927020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  927023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  927034 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  927037 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927040 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927043 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927050 */     // MIs[0] cbsz
     /*  927050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927053 */     // MIs[0] blgp
     /*  927053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927056 */     // MIs[0] Operand 7
     /*  927056 */     // No operand predicates
     /*  927056 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927060 */     // MIs[0] Operand 9
     /*  927060 */     // No operand predicates
     /*  927060 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927064 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927068 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  927071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927073 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927075 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927077 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927079 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927081 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927083 */     GIR_RootConstrainSelectedInstOperands,
     /*  927084 */     // GIR_Coverage, 3578,
     /*  927084 */     GIR_EraseRootFromParent_Done,
     /*  927085 */   // Label 14839: @927085
     /*  927085 */   GIM_Try, /*On fail goto*//*Label 14840*/ GIMT_Encode4(927155), // Rule ID 3584 //
     /*  927090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  927093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  927104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927107 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927110 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927113 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927120 */     // MIs[0] cbsz
     /*  927120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927123 */     // MIs[0] blgp
     /*  927123 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927126 */     // MIs[0] Operand 7
     /*  927126 */     // No operand predicates
     /*  927126 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927130 */     // MIs[0] Operand 9
     /*  927130 */     // No operand predicates
     /*  927130 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927134 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927138 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  927141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927143 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927145 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927147 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927149 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927151 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927153 */     GIR_RootConstrainSelectedInstOperands,
     /*  927154 */     // GIR_Coverage, 3584,
     /*  927154 */     GIR_EraseRootFromParent_Done,
     /*  927155 */   // Label 14840: @927155
     /*  927155 */   GIM_Try, /*On fail goto*//*Label 14841*/ GIMT_Encode4(927225), // Rule ID 3585 //
     /*  927160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  927163 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927168 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927171 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  927174 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927177 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927180 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927183 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927190 */     // MIs[0] cbsz
     /*  927190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927193 */     // MIs[0] blgp
     /*  927193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927196 */     // MIs[0] Operand 7
     /*  927196 */     // No operand predicates
     /*  927196 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927200 */     // MIs[0] Operand 9
     /*  927200 */     // No operand predicates
     /*  927200 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927204 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927208 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  927211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927213 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927215 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927217 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927219 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927221 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927223 */     GIR_RootConstrainSelectedInstOperands,
     /*  927224 */     // GIR_Coverage, 3585,
     /*  927224 */     GIR_EraseRootFromParent_Done,
     /*  927225 */   // Label 14841: @927225
     /*  927225 */   GIM_Try, /*On fail goto*//*Label 14842*/ GIMT_Encode4(927295), // Rule ID 3586 //
     /*  927230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  927233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  927244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927247 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927250 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927253 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927260 */     // MIs[0] cbsz
     /*  927260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927263 */     // MIs[0] blgp
     /*  927263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927266 */     // MIs[0] Operand 7
     /*  927266 */     // No operand predicates
     /*  927266 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927270 */     // MIs[0] Operand 9
     /*  927270 */     // No operand predicates
     /*  927270 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927274 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927278 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  927281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927283 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927285 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927287 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927289 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927291 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927293 */     GIR_RootConstrainSelectedInstOperands,
     /*  927294 */     // GIR_Coverage, 3586,
     /*  927294 */     GIR_EraseRootFromParent_Done,
     /*  927295 */   // Label 14842: @927295
     /*  927295 */   GIM_Try, /*On fail goto*//*Label 14843*/ GIMT_Encode4(927365), // Rule ID 3587 //
     /*  927300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  927303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  927314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927320 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927323 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927330 */     // MIs[0] cbsz
     /*  927330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927333 */     // MIs[0] blgp
     /*  927333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927336 */     // MIs[0] Operand 7
     /*  927336 */     // No operand predicates
     /*  927336 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927340 */     // MIs[0] Operand 9
     /*  927340 */     // No operand predicates
     /*  927340 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927344 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927348 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  927351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927353 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927355 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927357 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927359 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927361 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927363 */     GIR_RootConstrainSelectedInstOperands,
     /*  927364 */     // GIR_Coverage, 3587,
     /*  927364 */     GIR_EraseRootFromParent_Done,
     /*  927365 */   // Label 14843: @927365
     /*  927365 */   GIM_Try, /*On fail goto*//*Label 14844*/ GIMT_Encode4(927435), // Rule ID 3588 //
     /*  927370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  927373 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927378 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927381 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  927384 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927387 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927390 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927393 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927400 */     // MIs[0] cbsz
     /*  927400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927403 */     // MIs[0] blgp
     /*  927403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927406 */     // MIs[0] Operand 7
     /*  927406 */     // No operand predicates
     /*  927406 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927410 */     // MIs[0] Operand 9
     /*  927410 */     // No operand predicates
     /*  927410 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927414 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927418 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  927421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927423 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927425 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927427 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927429 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927431 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927433 */     GIR_RootConstrainSelectedInstOperands,
     /*  927434 */     // GIR_Coverage, 3588,
     /*  927434 */     GIR_EraseRootFromParent_Done,
     /*  927435 */   // Label 14844: @927435
     /*  927435 */   GIM_Try, /*On fail goto*//*Label 14845*/ GIMT_Encode4(927505), // Rule ID 3594 //
     /*  927440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  927443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  927454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  927457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927460 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927463 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927470 */     // MIs[0] cbsz
     /*  927470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927473 */     // MIs[0] blgp
     /*  927473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927476 */     // MIs[0] Operand 7
     /*  927476 */     // No operand predicates
     /*  927476 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927480 */     // MIs[0] Operand 9
     /*  927480 */     // No operand predicates
     /*  927480 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927484 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927488 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  927491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927493 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927495 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927497 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927499 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927501 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927503 */     GIR_RootConstrainSelectedInstOperands,
     /*  927504 */     // GIR_Coverage, 3594,
     /*  927504 */     GIR_EraseRootFromParent_Done,
     /*  927505 */   // Label 14845: @927505
     /*  927505 */   GIM_Try, /*On fail goto*//*Label 14846*/ GIMT_Encode4(927575), // Rule ID 3595 //
     /*  927510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  927513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  927524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  927527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927530 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927533 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927540 */     // MIs[0] cbsz
     /*  927540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927543 */     // MIs[0] blgp
     /*  927543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927546 */     // MIs[0] Operand 7
     /*  927546 */     // No operand predicates
     /*  927546 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927550 */     // MIs[0] Operand 9
     /*  927550 */     // No operand predicates
     /*  927550 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927554 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927558 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  927561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927563 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927565 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927567 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927569 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927571 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927573 */     GIR_RootConstrainSelectedInstOperands,
     /*  927574 */     // GIR_Coverage, 3595,
     /*  927574 */     GIR_EraseRootFromParent_Done,
     /*  927575 */   // Label 14846: @927575
     /*  927575 */   GIM_Try, /*On fail goto*//*Label 14847*/ GIMT_Encode4(927645), // Rule ID 3596 //
     /*  927580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  927583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  927594 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  927597 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927600 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927603 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927610 */     // MIs[0] cbsz
     /*  927610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927613 */     // MIs[0] blgp
     /*  927613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927616 */     // MIs[0] Operand 7
     /*  927616 */     // No operand predicates
     /*  927616 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927620 */     // MIs[0] Operand 9
     /*  927620 */     // No operand predicates
     /*  927620 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927624 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927628 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  927631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927633 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927635 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927637 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927639 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927641 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927643 */     GIR_RootConstrainSelectedInstOperands,
     /*  927644 */     // GIR_Coverage, 3596,
     /*  927644 */     GIR_EraseRootFromParent_Done,
     /*  927645 */   // Label 14847: @927645
     /*  927645 */   GIM_Try, /*On fail goto*//*Label 14848*/ GIMT_Encode4(927715), // Rule ID 3597 //
     /*  927650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  927653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  927664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  927667 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927670 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927673 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927680 */     // MIs[0] cbsz
     /*  927680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927683 */     // MIs[0] blgp
     /*  927683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927686 */     // MIs[0] Operand 7
     /*  927686 */     // No operand predicates
     /*  927686 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927690 */     // MIs[0] Operand 9
     /*  927690 */     // No operand predicates
     /*  927690 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927694 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927698 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  927701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927703 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927705 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927707 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927709 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927711 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927713 */     GIR_RootConstrainSelectedInstOperands,
     /*  927714 */     // GIR_Coverage, 3597,
     /*  927714 */     GIR_EraseRootFromParent_Done,
     /*  927715 */   // Label 14848: @927715
     /*  927715 */   GIM_Try, /*On fail goto*//*Label 14849*/ GIMT_Encode4(927785), // Rule ID 3598 //
     /*  927720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  927723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  927734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  927737 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927740 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927743 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927750 */     // MIs[0] cbsz
     /*  927750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927753 */     // MIs[0] blgp
     /*  927753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927756 */     // MIs[0] Operand 7
     /*  927756 */     // No operand predicates
     /*  927756 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927760 */     // MIs[0] Operand 9
     /*  927760 */     // No operand predicates
     /*  927760 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927764 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927768 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  927771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927773 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927775 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927777 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927779 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927781 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927783 */     GIR_RootConstrainSelectedInstOperands,
     /*  927784 */     // GIR_Coverage, 3598,
     /*  927784 */     GIR_EraseRootFromParent_Done,
     /*  927785 */   // Label 14849: @927785
     /*  927785 */   GIM_Try, /*On fail goto*//*Label 14850*/ GIMT_Encode4(927855), // Rule ID 3604 //
     /*  927790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  927793 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927798 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927801 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  927804 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927807 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927810 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927813 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927820 */     // MIs[0] cbsz
     /*  927820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927823 */     // MIs[0] blgp
     /*  927823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927826 */     // MIs[0] Operand 7
     /*  927826 */     // No operand predicates
     /*  927826 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927830 */     // MIs[0] Operand 9
     /*  927830 */     // No operand predicates
     /*  927830 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927834 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927838 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  927841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927843 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927845 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927847 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927849 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927851 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927853 */     GIR_RootConstrainSelectedInstOperands,
     /*  927854 */     // GIR_Coverage, 3604,
     /*  927854 */     GIR_EraseRootFromParent_Done,
     /*  927855 */   // Label 14850: @927855
     /*  927855 */   GIM_Try, /*On fail goto*//*Label 14851*/ GIMT_Encode4(927925), // Rule ID 3605 //
     /*  927860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  927863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  927874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927877 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927880 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927883 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927890 */     // MIs[0] cbsz
     /*  927890 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927893 */     // MIs[0] blgp
     /*  927893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927896 */     // MIs[0] Operand 7
     /*  927896 */     // No operand predicates
     /*  927896 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927900 */     // MIs[0] Operand 9
     /*  927900 */     // No operand predicates
     /*  927900 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927904 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927908 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  927911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927913 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927915 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927917 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927919 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927921 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927923 */     GIR_RootConstrainSelectedInstOperands,
     /*  927924 */     // GIR_Coverage, 3605,
     /*  927924 */     GIR_EraseRootFromParent_Done,
     /*  927925 */   // Label 14851: @927925
     /*  927925 */   GIM_Try, /*On fail goto*//*Label 14852*/ GIMT_Encode4(927995), // Rule ID 3606 //
     /*  927930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  927933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  927938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  927941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  927944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  927947 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  927950 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  927953 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  927956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  927960 */     // MIs[0] cbsz
     /*  927960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  927963 */     // MIs[0] blgp
     /*  927963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  927966 */     // MIs[0] Operand 7
     /*  927966 */     // No operand predicates
     /*  927966 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  927970 */     // MIs[0] Operand 9
     /*  927970 */     // No operand predicates
     /*  927970 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  927974 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  927978 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  927978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  927981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  927983 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  927985 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  927987 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  927989 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  927991 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  927993 */     GIR_RootConstrainSelectedInstOperands,
     /*  927994 */     // GIR_Coverage, 3606,
     /*  927994 */     GIR_EraseRootFromParent_Done,
     /*  927995 */   // Label 14852: @927995
     /*  927995 */   GIM_Try, /*On fail goto*//*Label 14853*/ GIMT_Encode4(928065), // Rule ID 3607 //
     /*  928000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  928003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928011 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  928014 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928017 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928020 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928023 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928030 */     // MIs[0] cbsz
     /*  928030 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928033 */     // MIs[0] blgp
     /*  928033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928036 */     // MIs[0] Operand 7
     /*  928036 */     // No operand predicates
     /*  928036 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928040 */     // MIs[0] Operand 9
     /*  928040 */     // No operand predicates
     /*  928040 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928044 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928048 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  928051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928053 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928055 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928057 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928059 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928061 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928063 */     GIR_RootConstrainSelectedInstOperands,
     /*  928064 */     // GIR_Coverage, 3607,
     /*  928064 */     GIR_EraseRootFromParent_Done,
     /*  928065 */   // Label 14853: @928065
     /*  928065 */   GIM_Try, /*On fail goto*//*Label 14854*/ GIMT_Encode4(928135), // Rule ID 3608 //
     /*  928070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  928073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  928084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928087 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928090 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928093 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928100 */     // MIs[0] cbsz
     /*  928100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928103 */     // MIs[0] blgp
     /*  928103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928106 */     // MIs[0] Operand 7
     /*  928106 */     // No operand predicates
     /*  928106 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928110 */     // MIs[0] Operand 9
     /*  928110 */     // No operand predicates
     /*  928110 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928114 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928118 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  928121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928123 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928125 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928127 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928129 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928131 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928133 */     GIR_RootConstrainSelectedInstOperands,
     /*  928134 */     // GIR_Coverage, 3608,
     /*  928134 */     GIR_EraseRootFromParent_Done,
     /*  928135 */   // Label 14854: @928135
     /*  928135 */   GIM_Try, /*On fail goto*//*Label 14855*/ GIMT_Encode4(928205), // Rule ID 3614 //
     /*  928140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  928143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928151 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  928157 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928160 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928163 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928170 */     // MIs[0] cbsz
     /*  928170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928173 */     // MIs[0] blgp
     /*  928173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928176 */     // MIs[0] Operand 7
     /*  928176 */     // No operand predicates
     /*  928176 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928180 */     // MIs[0] Operand 9
     /*  928180 */     // No operand predicates
     /*  928180 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928184 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928188 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  928191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928193 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928195 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928197 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928199 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928201 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928203 */     GIR_RootConstrainSelectedInstOperands,
     /*  928204 */     // GIR_Coverage, 3614,
     /*  928204 */     GIR_EraseRootFromParent_Done,
     /*  928205 */   // Label 14855: @928205
     /*  928205 */   GIM_Try, /*On fail goto*//*Label 14856*/ GIMT_Encode4(928275), // Rule ID 3615 //
     /*  928210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  928213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928221 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928224 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  928227 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928230 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928233 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928240 */     // MIs[0] cbsz
     /*  928240 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928243 */     // MIs[0] blgp
     /*  928243 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928246 */     // MIs[0] Operand 7
     /*  928246 */     // No operand predicates
     /*  928246 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928250 */     // MIs[0] Operand 9
     /*  928250 */     // No operand predicates
     /*  928250 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928254 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928258 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  928261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928263 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928265 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928267 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928269 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928271 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928273 */     GIR_RootConstrainSelectedInstOperands,
     /*  928274 */     // GIR_Coverage, 3615,
     /*  928274 */     GIR_EraseRootFromParent_Done,
     /*  928275 */   // Label 14856: @928275
     /*  928275 */   GIM_Try, /*On fail goto*//*Label 14857*/ GIMT_Encode4(928345), // Rule ID 3616 //
     /*  928280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  928283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  928297 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928300 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928303 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928310 */     // MIs[0] cbsz
     /*  928310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928313 */     // MIs[0] blgp
     /*  928313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928316 */     // MIs[0] Operand 7
     /*  928316 */     // No operand predicates
     /*  928316 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928320 */     // MIs[0] Operand 9
     /*  928320 */     // No operand predicates
     /*  928320 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928324 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928328 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  928331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928333 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928335 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928337 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928339 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928341 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928343 */     GIR_RootConstrainSelectedInstOperands,
     /*  928344 */     // GIR_Coverage, 3616,
     /*  928344 */     GIR_EraseRootFromParent_Done,
     /*  928345 */   // Label 14857: @928345
     /*  928345 */   GIM_Try, /*On fail goto*//*Label 14858*/ GIMT_Encode4(928415), // Rule ID 3617 //
     /*  928350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  928353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  928367 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928370 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928373 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928380 */     // MIs[0] cbsz
     /*  928380 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928383 */     // MIs[0] blgp
     /*  928383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928386 */     // MIs[0] Operand 7
     /*  928386 */     // No operand predicates
     /*  928386 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928390 */     // MIs[0] Operand 9
     /*  928390 */     // No operand predicates
     /*  928390 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928394 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928398 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  928401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928403 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928405 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928407 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928409 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928411 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928413 */     GIR_RootConstrainSelectedInstOperands,
     /*  928414 */     // GIR_Coverage, 3617,
     /*  928414 */     GIR_EraseRootFromParent_Done,
     /*  928415 */   // Label 14858: @928415
     /*  928415 */   GIM_Try, /*On fail goto*//*Label 14859*/ GIMT_Encode4(928485), // Rule ID 3618 //
     /*  928420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  928423 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928428 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928431 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928434 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  928437 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928440 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928443 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928450 */     // MIs[0] cbsz
     /*  928450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928453 */     // MIs[0] blgp
     /*  928453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928456 */     // MIs[0] Operand 7
     /*  928456 */     // No operand predicates
     /*  928456 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928460 */     // MIs[0] Operand 9
     /*  928460 */     // No operand predicates
     /*  928460 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928464 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928468 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  928471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928473 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928475 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928477 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928479 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928481 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928483 */     GIR_RootConstrainSelectedInstOperands,
     /*  928484 */     // GIR_Coverage, 3618,
     /*  928484 */     GIR_EraseRootFromParent_Done,
     /*  928485 */   // Label 14859: @928485
     /*  928485 */   GIM_Try, /*On fail goto*//*Label 14860*/ GIMT_Encode4(928555), // Rule ID 3624 //
     /*  928490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  928493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928507 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928510 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928513 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928520 */     // MIs[0] cbsz
     /*  928520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928523 */     // MIs[0] blgp
     /*  928523 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928526 */     // MIs[0] Operand 7
     /*  928526 */     // No operand predicates
     /*  928526 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928530 */     // MIs[0] Operand 9
     /*  928530 */     // No operand predicates
     /*  928530 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928534 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928538 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  928541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928543 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928545 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928547 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928549 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928551 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928553 */     GIR_RootConstrainSelectedInstOperands,
     /*  928554 */     // GIR_Coverage, 3624,
     /*  928554 */     GIR_EraseRootFromParent_Done,
     /*  928555 */   // Label 14860: @928555
     /*  928555 */   GIM_Try, /*On fail goto*//*Label 14861*/ GIMT_Encode4(928625), // Rule ID 3625 //
     /*  928560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  928563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928580 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928583 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928590 */     // MIs[0] cbsz
     /*  928590 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928593 */     // MIs[0] blgp
     /*  928593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928596 */     // MIs[0] Operand 7
     /*  928596 */     // No operand predicates
     /*  928596 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928600 */     // MIs[0] Operand 9
     /*  928600 */     // No operand predicates
     /*  928600 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928604 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928608 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  928611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928613 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928615 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928617 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928619 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928621 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928623 */     GIR_RootConstrainSelectedInstOperands,
     /*  928624 */     // GIR_Coverage, 3625,
     /*  928624 */     GIR_EraseRootFromParent_Done,
     /*  928625 */   // Label 14861: @928625
     /*  928625 */   GIM_Try, /*On fail goto*//*Label 14862*/ GIMT_Encode4(928695), // Rule ID 3626 //
     /*  928630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  928633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928647 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928650 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928653 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928660 */     // MIs[0] cbsz
     /*  928660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928663 */     // MIs[0] blgp
     /*  928663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928666 */     // MIs[0] Operand 7
     /*  928666 */     // No operand predicates
     /*  928666 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928670 */     // MIs[0] Operand 9
     /*  928670 */     // No operand predicates
     /*  928670 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928674 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928678 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  928681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928683 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928685 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928687 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928689 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928691 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928693 */     GIR_RootConstrainSelectedInstOperands,
     /*  928694 */     // GIR_Coverage, 3626,
     /*  928694 */     GIR_EraseRootFromParent_Done,
     /*  928695 */   // Label 14862: @928695
     /*  928695 */   GIM_Try, /*On fail goto*//*Label 14863*/ GIMT_Encode4(928765), // Rule ID 3627 //
     /*  928700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  928703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928714 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928717 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928720 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928723 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928730 */     // MIs[0] cbsz
     /*  928730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928733 */     // MIs[0] blgp
     /*  928733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928736 */     // MIs[0] Operand 7
     /*  928736 */     // No operand predicates
     /*  928736 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928740 */     // MIs[0] Operand 9
     /*  928740 */     // No operand predicates
     /*  928740 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928744 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928748 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  928751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928753 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928755 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928757 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928759 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928761 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928763 */     GIR_RootConstrainSelectedInstOperands,
     /*  928764 */     // GIR_Coverage, 3627,
     /*  928764 */     GIR_EraseRootFromParent_Done,
     /*  928765 */   // Label 14863: @928765
     /*  928765 */   GIM_Try, /*On fail goto*//*Label 14864*/ GIMT_Encode4(928835), // Rule ID 3628 //
     /*  928770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  928773 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  928778 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  928781 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  928784 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  928787 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  928790 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928793 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  928800 */     // MIs[0] cbsz
     /*  928800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928803 */     // MIs[0] blgp
     /*  928803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928806 */     // MIs[0] Operand 7
     /*  928806 */     // No operand predicates
     /*  928806 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928810 */     // MIs[0] Operand 9
     /*  928810 */     // No operand predicates
     /*  928810 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928814 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31838),
     /*  928818 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31838>>  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  928821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928823 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928825 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928827 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928829 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928831 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928833 */     GIR_RootConstrainSelectedInstOperands,
     /*  928834 */     // GIR_Coverage, 3628,
     /*  928834 */     GIR_EraseRootFromParent_Done,
     /*  928835 */   // Label 14864: @928835
     /*  928835 */   GIM_Try, /*On fail goto*//*Label 14865*/ GIMT_Encode4(928905), // Rule ID 3634 //
     /*  928840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  928843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  928848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  928851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  928854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  928857 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  928860 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928863 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  928870 */     // MIs[0] cbsz
     /*  928870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928873 */     // MIs[0] blgp
     /*  928873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928876 */     // MIs[0] Operand 7
     /*  928876 */     // No operand predicates
     /*  928876 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928880 */     // MIs[0] Operand 9
     /*  928880 */     // No operand predicates
     /*  928880 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928884 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  928888 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  928891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928893 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928895 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928897 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928899 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928901 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928903 */     GIR_RootConstrainSelectedInstOperands,
     /*  928904 */     // GIR_Coverage, 3634,
     /*  928904 */     GIR_EraseRootFromParent_Done,
     /*  928905 */   // Label 14865: @928905
     /*  928905 */   GIM_Try, /*On fail goto*//*Label 14866*/ GIMT_Encode4(928975), // Rule ID 3635 //
     /*  928910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  928913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  928918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  928921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  928924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  928927 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  928930 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  928933 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  928936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  928940 */     // MIs[0] cbsz
     /*  928940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  928943 */     // MIs[0] blgp
     /*  928943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  928946 */     // MIs[0] Operand 7
     /*  928946 */     // No operand predicates
     /*  928946 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  928950 */     // MIs[0] Operand 9
     /*  928950 */     // No operand predicates
     /*  928950 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  928954 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  928958 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  928958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  928961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  928963 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  928965 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  928967 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  928969 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  928971 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  928973 */     GIR_RootConstrainSelectedInstOperands,
     /*  928974 */     // GIR_Coverage, 3635,
     /*  928974 */     GIR_EraseRootFromParent_Done,
     /*  928975 */   // Label 14866: @928975
     /*  928975 */   GIM_Try, /*On fail goto*//*Label 14867*/ GIMT_Encode4(929045), // Rule ID 3636 //
     /*  928980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  928983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  928988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  928991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  928994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  928997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929000 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929003 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929010 */     // MIs[0] cbsz
     /*  929010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929013 */     // MIs[0] blgp
     /*  929013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929016 */     // MIs[0] Operand 7
     /*  929016 */     // No operand predicates
     /*  929016 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929020 */     // MIs[0] Operand 9
     /*  929020 */     // No operand predicates
     /*  929020 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929024 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929028 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  929031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929033 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929035 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929037 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929039 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929041 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929043 */     GIR_RootConstrainSelectedInstOperands,
     /*  929044 */     // GIR_Coverage, 3636,
     /*  929044 */     GIR_EraseRootFromParent_Done,
     /*  929045 */   // Label 14867: @929045
     /*  929045 */   GIM_Try, /*On fail goto*//*Label 14868*/ GIMT_Encode4(929115), // Rule ID 3637 //
     /*  929050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  929053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929070 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929073 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929080 */     // MIs[0] cbsz
     /*  929080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929083 */     // MIs[0] blgp
     /*  929083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929086 */     // MIs[0] Operand 7
     /*  929086 */     // No operand predicates
     /*  929086 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929090 */     // MIs[0] Operand 9
     /*  929090 */     // No operand predicates
     /*  929090 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929094 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929098 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  929101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929103 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929105 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929107 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929109 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929111 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929113 */     GIR_RootConstrainSelectedInstOperands,
     /*  929114 */     // GIR_Coverage, 3637,
     /*  929114 */     GIR_EraseRootFromParent_Done,
     /*  929115 */   // Label 14868: @929115
     /*  929115 */   GIM_Try, /*On fail goto*//*Label 14869*/ GIMT_Encode4(929185), // Rule ID 3638 //
     /*  929120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  929123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929140 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929143 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929150 */     // MIs[0] cbsz
     /*  929150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929153 */     // MIs[0] blgp
     /*  929153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929156 */     // MIs[0] Operand 7
     /*  929156 */     // No operand predicates
     /*  929156 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929160 */     // MIs[0] Operand 9
     /*  929160 */     // No operand predicates
     /*  929160 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929164 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929168 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  929171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929173 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929175 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929177 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929179 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929181 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929183 */     GIR_RootConstrainSelectedInstOperands,
     /*  929184 */     // GIR_Coverage, 3638,
     /*  929184 */     GIR_EraseRootFromParent_Done,
     /*  929185 */   // Label 14869: @929185
     /*  929185 */   GIM_Try, /*On fail goto*//*Label 14870*/ GIMT_Encode4(929255), // Rule ID 3644 //
     /*  929190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  929193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929210 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929213 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929220 */     // MIs[0] cbsz
     /*  929220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929223 */     // MIs[0] blgp
     /*  929223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929226 */     // MIs[0] Operand 7
     /*  929226 */     // No operand predicates
     /*  929226 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929230 */     // MIs[0] Operand 9
     /*  929230 */     // No operand predicates
     /*  929230 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929234 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929238 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  929241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929243 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929245 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929247 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929249 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929251 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929253 */     GIR_RootConstrainSelectedInstOperands,
     /*  929254 */     // GIR_Coverage, 3644,
     /*  929254 */     GIR_EraseRootFromParent_Done,
     /*  929255 */   // Label 14870: @929255
     /*  929255 */   GIM_Try, /*On fail goto*//*Label 14871*/ GIMT_Encode4(929325), // Rule ID 3645 //
     /*  929260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  929263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929268 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929271 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929274 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929277 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929280 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929283 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929290 */     // MIs[0] cbsz
     /*  929290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929293 */     // MIs[0] blgp
     /*  929293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929296 */     // MIs[0] Operand 7
     /*  929296 */     // No operand predicates
     /*  929296 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929300 */     // MIs[0] Operand 9
     /*  929300 */     // No operand predicates
     /*  929300 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929304 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929308 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  929311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929313 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929315 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929317 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929319 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929321 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929323 */     GIR_RootConstrainSelectedInstOperands,
     /*  929324 */     // GIR_Coverage, 3645,
     /*  929324 */     GIR_EraseRootFromParent_Done,
     /*  929325 */   // Label 14871: @929325
     /*  929325 */   GIM_Try, /*On fail goto*//*Label 14872*/ GIMT_Encode4(929395), // Rule ID 3646 //
     /*  929330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  929333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929350 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929353 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929360 */     // MIs[0] cbsz
     /*  929360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929363 */     // MIs[0] blgp
     /*  929363 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929366 */     // MIs[0] Operand 7
     /*  929366 */     // No operand predicates
     /*  929366 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929370 */     // MIs[0] Operand 9
     /*  929370 */     // No operand predicates
     /*  929370 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929374 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929378 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  929381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929383 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929385 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929387 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929389 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929391 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929393 */     GIR_RootConstrainSelectedInstOperands,
     /*  929394 */     // GIR_Coverage, 3646,
     /*  929394 */     GIR_EraseRootFromParent_Done,
     /*  929395 */   // Label 14872: @929395
     /*  929395 */   GIM_Try, /*On fail goto*//*Label 14873*/ GIMT_Encode4(929465), // Rule ID 3647 //
     /*  929400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  929403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929417 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929420 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929423 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929430 */     // MIs[0] cbsz
     /*  929430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929433 */     // MIs[0] blgp
     /*  929433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929436 */     // MIs[0] Operand 7
     /*  929436 */     // No operand predicates
     /*  929436 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929440 */     // MIs[0] Operand 9
     /*  929440 */     // No operand predicates
     /*  929440 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929444 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929448 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  929451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929453 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929455 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929457 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929459 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929461 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929463 */     GIR_RootConstrainSelectedInstOperands,
     /*  929464 */     // GIR_Coverage, 3647,
     /*  929464 */     GIR_EraseRootFromParent_Done,
     /*  929465 */   // Label 14873: @929465
     /*  929465 */   GIM_Try, /*On fail goto*//*Label 14874*/ GIMT_Encode4(929535), // Rule ID 3648 //
     /*  929470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  929473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  929484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929487 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929490 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929493 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929500 */     // MIs[0] cbsz
     /*  929500 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929503 */     // MIs[0] blgp
     /*  929503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929506 */     // MIs[0] Operand 7
     /*  929506 */     // No operand predicates
     /*  929506 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929510 */     // MIs[0] Operand 9
     /*  929510 */     // No operand predicates
     /*  929510 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929514 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929518 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  929521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929523 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929525 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929527 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929529 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929531 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929533 */     GIR_RootConstrainSelectedInstOperands,
     /*  929534 */     // GIR_Coverage, 3648,
     /*  929534 */     GIR_EraseRootFromParent_Done,
     /*  929535 */   // Label 14874: @929535
     /*  929535 */   GIM_Try, /*On fail goto*//*Label 14875*/ GIMT_Encode4(929605), // Rule ID 3654 //
     /*  929540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  929543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929557 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929560 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929563 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929570 */     // MIs[0] cbsz
     /*  929570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929573 */     // MIs[0] blgp
     /*  929573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929576 */     // MIs[0] Operand 7
     /*  929576 */     // No operand predicates
     /*  929576 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929580 */     // MIs[0] Operand 9
     /*  929580 */     // No operand predicates
     /*  929580 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929584 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929588 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  929591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929593 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929595 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929597 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929599 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929601 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929603 */     GIR_RootConstrainSelectedInstOperands,
     /*  929604 */     // GIR_Coverage, 3654,
     /*  929604 */     GIR_EraseRootFromParent_Done,
     /*  929605 */   // Label 14875: @929605
     /*  929605 */   GIM_Try, /*On fail goto*//*Label 14876*/ GIMT_Encode4(929675), // Rule ID 3655 //
     /*  929610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  929613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929630 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929633 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929640 */     // MIs[0] cbsz
     /*  929640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929643 */     // MIs[0] blgp
     /*  929643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929646 */     // MIs[0] Operand 7
     /*  929646 */     // No operand predicates
     /*  929646 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929650 */     // MIs[0] Operand 9
     /*  929650 */     // No operand predicates
     /*  929650 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929654 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929658 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  929661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929663 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929665 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929667 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929669 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929671 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929673 */     GIR_RootConstrainSelectedInstOperands,
     /*  929674 */     // GIR_Coverage, 3655,
     /*  929674 */     GIR_EraseRootFromParent_Done,
     /*  929675 */   // Label 14876: @929675
     /*  929675 */   GIM_Try, /*On fail goto*//*Label 14877*/ GIMT_Encode4(929745), // Rule ID 3656 //
     /*  929680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  929683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929694 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929697 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929700 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929703 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929710 */     // MIs[0] cbsz
     /*  929710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929713 */     // MIs[0] blgp
     /*  929713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929716 */     // MIs[0] Operand 7
     /*  929716 */     // No operand predicates
     /*  929716 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929720 */     // MIs[0] Operand 9
     /*  929720 */     // No operand predicates
     /*  929720 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929724 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929728 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  929731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929733 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929735 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929737 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929739 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929741 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929743 */     GIR_RootConstrainSelectedInstOperands,
     /*  929744 */     // GIR_Coverage, 3656,
     /*  929744 */     GIR_EraseRootFromParent_Done,
     /*  929745 */   // Label 14877: @929745
     /*  929745 */   GIM_Try, /*On fail goto*//*Label 14878*/ GIMT_Encode4(929815), // Rule ID 3657 //
     /*  929750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  929753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929770 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929773 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929780 */     // MIs[0] cbsz
     /*  929780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929783 */     // MIs[0] blgp
     /*  929783 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929786 */     // MIs[0] Operand 7
     /*  929786 */     // No operand predicates
     /*  929786 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929790 */     // MIs[0] Operand 9
     /*  929790 */     // No operand predicates
     /*  929790 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929794 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929798 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  929801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929803 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929805 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929807 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929809 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929811 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929813 */     GIR_RootConstrainSelectedInstOperands,
     /*  929814 */     // GIR_Coverage, 3657,
     /*  929814 */     GIR_EraseRootFromParent_Done,
     /*  929815 */   // Label 14878: @929815
     /*  929815 */   GIM_Try, /*On fail goto*//*Label 14879*/ GIMT_Encode4(929885), // Rule ID 3658 //
     /*  929820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  929823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  929837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929840 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929843 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929850 */     // MIs[0] cbsz
     /*  929850 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929853 */     // MIs[0] blgp
     /*  929853 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929856 */     // MIs[0] Operand 7
     /*  929856 */     // No operand predicates
     /*  929856 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929860 */     // MIs[0] Operand 9
     /*  929860 */     // No operand predicates
     /*  929860 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929864 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929868 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  929871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929873 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929875 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929877 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929879 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929881 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929883 */     GIR_RootConstrainSelectedInstOperands,
     /*  929884 */     // GIR_Coverage, 3658,
     /*  929884 */     GIR_EraseRootFromParent_Done,
     /*  929885 */   // Label 14879: @929885
     /*  929885 */   GIM_Try, /*On fail goto*//*Label 14880*/ GIMT_Encode4(929955), // Rule ID 3664 //
     /*  929890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  929893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929907 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929910 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929913 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929920 */     // MIs[0] cbsz
     /*  929920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929923 */     // MIs[0] blgp
     /*  929923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929926 */     // MIs[0] Operand 7
     /*  929926 */     // No operand predicates
     /*  929926 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  929930 */     // MIs[0] Operand 9
     /*  929930 */     // No operand predicates
     /*  929930 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  929934 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  929938 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  929938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  929941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  929943 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  929945 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  929947 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  929949 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  929951 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  929953 */     GIR_RootConstrainSelectedInstOperands,
     /*  929954 */     // GIR_Coverage, 3664,
     /*  929954 */     GIR_EraseRootFromParent_Done,
     /*  929955 */   // Label 14880: @929955
     /*  929955 */   GIM_Try, /*On fail goto*//*Label 14881*/ GIMT_Encode4(930025), // Rule ID 3665 //
     /*  929960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  929963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  929968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  929971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  929974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  929977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  929980 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  929983 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  929986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  929990 */     // MIs[0] cbsz
     /*  929990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  929993 */     // MIs[0] blgp
     /*  929993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  929996 */     // MIs[0] Operand 7
     /*  929996 */     // No operand predicates
     /*  929996 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930000 */     // MIs[0] Operand 9
     /*  930000 */     // No operand predicates
     /*  930000 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930004 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930008 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  930011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930013 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930015 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930017 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930019 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930021 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930023 */     GIR_RootConstrainSelectedInstOperands,
     /*  930024 */     // GIR_Coverage, 3665,
     /*  930024 */     GIR_EraseRootFromParent_Done,
     /*  930025 */   // Label 14881: @930025
     /*  930025 */   GIM_Try, /*On fail goto*//*Label 14882*/ GIMT_Encode4(930095), // Rule ID 3666 //
     /*  930030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  930033 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930038 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  930044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  930047 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930050 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930053 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930060 */     // MIs[0] cbsz
     /*  930060 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930063 */     // MIs[0] blgp
     /*  930063 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930066 */     // MIs[0] Operand 7
     /*  930066 */     // No operand predicates
     /*  930066 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930070 */     // MIs[0] Operand 9
     /*  930070 */     // No operand predicates
     /*  930070 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930074 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930078 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  930081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930083 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930085 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930087 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930089 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930091 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930093 */     GIR_RootConstrainSelectedInstOperands,
     /*  930094 */     // GIR_Coverage, 3666,
     /*  930094 */     GIR_EraseRootFromParent_Done,
     /*  930095 */   // Label 14882: @930095
     /*  930095 */   GIM_Try, /*On fail goto*//*Label 14883*/ GIMT_Encode4(930165), // Rule ID 3667 //
     /*  930100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  930103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  930114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  930117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930120 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930123 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930130 */     // MIs[0] cbsz
     /*  930130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930133 */     // MIs[0] blgp
     /*  930133 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930136 */     // MIs[0] Operand 7
     /*  930136 */     // No operand predicates
     /*  930136 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930140 */     // MIs[0] Operand 9
     /*  930140 */     // No operand predicates
     /*  930140 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930144 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930148 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  930151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930153 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930155 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930157 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930159 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930161 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930163 */     GIR_RootConstrainSelectedInstOperands,
     /*  930164 */     // GIR_Coverage, 3667,
     /*  930164 */     GIR_EraseRootFromParent_Done,
     /*  930165 */   // Label 14883: @930165
     /*  930165 */   GIM_Try, /*On fail goto*//*Label 14884*/ GIMT_Encode4(930235), // Rule ID 3668 //
     /*  930170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  930173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  930184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  930187 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930190 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930193 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930200 */     // MIs[0] cbsz
     /*  930200 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930203 */     // MIs[0] blgp
     /*  930203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930206 */     // MIs[0] Operand 7
     /*  930206 */     // No operand predicates
     /*  930206 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930210 */     // MIs[0] Operand 9
     /*  930210 */     // No operand predicates
     /*  930210 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930214 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930218 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  930221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930223 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930225 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930227 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930229 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930231 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930233 */     GIR_RootConstrainSelectedInstOperands,
     /*  930234 */     // GIR_Coverage, 3668,
     /*  930234 */     GIR_EraseRootFromParent_Done,
     /*  930235 */   // Label 14884: @930235
     /*  930235 */   GIM_Try, /*On fail goto*//*Label 14885*/ GIMT_Encode4(930305), // Rule ID 3674 //
     /*  930240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  930243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  930254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  930257 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930260 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930263 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930270 */     // MIs[0] cbsz
     /*  930270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930273 */     // MIs[0] blgp
     /*  930273 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930276 */     // MIs[0] Operand 7
     /*  930276 */     // No operand predicates
     /*  930276 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930280 */     // MIs[0] Operand 9
     /*  930280 */     // No operand predicates
     /*  930280 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930284 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930288 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  930291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930293 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930295 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930297 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930299 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930301 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930303 */     GIR_RootConstrainSelectedInstOperands,
     /*  930304 */     // GIR_Coverage, 3674,
     /*  930304 */     GIR_EraseRootFromParent_Done,
     /*  930305 */   // Label 14885: @930305
     /*  930305 */   GIM_Try, /*On fail goto*//*Label 14886*/ GIMT_Encode4(930375), // Rule ID 3675 //
     /*  930310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  930313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  930324 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  930327 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930330 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930333 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930340 */     // MIs[0] cbsz
     /*  930340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930343 */     // MIs[0] blgp
     /*  930343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930346 */     // MIs[0] Operand 7
     /*  930346 */     // No operand predicates
     /*  930346 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930350 */     // MIs[0] Operand 9
     /*  930350 */     // No operand predicates
     /*  930350 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930354 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930358 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  930361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930363 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930365 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930367 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930369 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930371 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930373 */     GIR_RootConstrainSelectedInstOperands,
     /*  930374 */     // GIR_Coverage, 3675,
     /*  930374 */     GIR_EraseRootFromParent_Done,
     /*  930375 */   // Label 14886: @930375
     /*  930375 */   GIM_Try, /*On fail goto*//*Label 14887*/ GIMT_Encode4(930445), // Rule ID 3676 //
     /*  930380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  930383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  930394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  930397 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930400 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930403 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930410 */     // MIs[0] cbsz
     /*  930410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930413 */     // MIs[0] blgp
     /*  930413 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930416 */     // MIs[0] Operand 7
     /*  930416 */     // No operand predicates
     /*  930416 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930420 */     // MIs[0] Operand 9
     /*  930420 */     // No operand predicates
     /*  930420 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930424 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930428 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  930431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930433 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930435 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930437 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930439 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930441 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930443 */     GIR_RootConstrainSelectedInstOperands,
     /*  930444 */     // GIR_Coverage, 3676,
     /*  930444 */     GIR_EraseRootFromParent_Done,
     /*  930445 */   // Label 14887: @930445
     /*  930445 */   GIM_Try, /*On fail goto*//*Label 14888*/ GIMT_Encode4(930515), // Rule ID 3677 //
     /*  930450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  930453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  930464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  930467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930470 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930473 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930480 */     // MIs[0] cbsz
     /*  930480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930483 */     // MIs[0] blgp
     /*  930483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930486 */     // MIs[0] Operand 7
     /*  930486 */     // No operand predicates
     /*  930486 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930490 */     // MIs[0] Operand 9
     /*  930490 */     // No operand predicates
     /*  930490 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930494 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930498 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  930501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930503 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930505 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930507 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930509 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930511 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930513 */     GIR_RootConstrainSelectedInstOperands,
     /*  930514 */     // GIR_Coverage, 3677,
     /*  930514 */     GIR_EraseRootFromParent_Done,
     /*  930515 */   // Label 14888: @930515
     /*  930515 */   GIM_Try, /*On fail goto*//*Label 14889*/ GIMT_Encode4(930585), // Rule ID 3678 //
     /*  930520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  930523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930528 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  930534 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  930537 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930540 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930543 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930550 */     // MIs[0] cbsz
     /*  930550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930553 */     // MIs[0] blgp
     /*  930553 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930556 */     // MIs[0] Operand 7
     /*  930556 */     // No operand predicates
     /*  930556 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930560 */     // MIs[0] Operand 9
     /*  930560 */     // No operand predicates
     /*  930560 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930564 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930568 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  930571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930573 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930575 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930577 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930579 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930581 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930583 */     GIR_RootConstrainSelectedInstOperands,
     /*  930584 */     // GIR_Coverage, 3678,
     /*  930584 */     GIR_EraseRootFromParent_Done,
     /*  930585 */   // Label 14889: @930585
     /*  930585 */   GIM_Try, /*On fail goto*//*Label 14890*/ GIMT_Encode4(930655), // Rule ID 3684 //
     /*  930590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  930593 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930598 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930601 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  930604 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  930607 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930610 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930613 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930620 */     // MIs[0] cbsz
     /*  930620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930623 */     // MIs[0] blgp
     /*  930623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930626 */     // MIs[0] Operand 7
     /*  930626 */     // No operand predicates
     /*  930626 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930630 */     // MIs[0] Operand 9
     /*  930630 */     // No operand predicates
     /*  930630 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930634 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930638 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  930641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930643 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930645 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930647 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930649 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930651 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930653 */     GIR_RootConstrainSelectedInstOperands,
     /*  930654 */     // GIR_Coverage, 3684,
     /*  930654 */     GIR_EraseRootFromParent_Done,
     /*  930655 */   // Label 14890: @930655
     /*  930655 */   GIM_Try, /*On fail goto*//*Label 14891*/ GIMT_Encode4(930725), // Rule ID 3685 //
     /*  930660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  930663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  930674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  930677 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930680 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930683 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930690 */     // MIs[0] cbsz
     /*  930690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930693 */     // MIs[0] blgp
     /*  930693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930696 */     // MIs[0] Operand 7
     /*  930696 */     // No operand predicates
     /*  930696 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930700 */     // MIs[0] Operand 9
     /*  930700 */     // No operand predicates
     /*  930700 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930704 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930708 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  930711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930713 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930715 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930717 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930719 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930721 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930723 */     GIR_RootConstrainSelectedInstOperands,
     /*  930724 */     // GIR_Coverage, 3685,
     /*  930724 */     GIR_EraseRootFromParent_Done,
     /*  930725 */   // Label 14891: @930725
     /*  930725 */   GIM_Try, /*On fail goto*//*Label 14892*/ GIMT_Encode4(930795), // Rule ID 3686 //
     /*  930730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  930733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  930744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  930747 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930750 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930753 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930760 */     // MIs[0] cbsz
     /*  930760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930763 */     // MIs[0] blgp
     /*  930763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930766 */     // MIs[0] Operand 7
     /*  930766 */     // No operand predicates
     /*  930766 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930770 */     // MIs[0] Operand 9
     /*  930770 */     // No operand predicates
     /*  930770 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930774 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930778 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  930781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930783 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930785 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930787 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930789 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930791 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930793 */     GIR_RootConstrainSelectedInstOperands,
     /*  930794 */     // GIR_Coverage, 3686,
     /*  930794 */     GIR_EraseRootFromParent_Done,
     /*  930795 */   // Label 14892: @930795
     /*  930795 */   GIM_Try, /*On fail goto*//*Label 14893*/ GIMT_Encode4(930865), // Rule ID 3687 //
     /*  930800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  930803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  930814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  930817 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930820 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930823 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930830 */     // MIs[0] cbsz
     /*  930830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930833 */     // MIs[0] blgp
     /*  930833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930836 */     // MIs[0] Operand 7
     /*  930836 */     // No operand predicates
     /*  930836 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930840 */     // MIs[0] Operand 9
     /*  930840 */     // No operand predicates
     /*  930840 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930844 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930848 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  930851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930853 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930855 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930857 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930859 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930861 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930863 */     GIR_RootConstrainSelectedInstOperands,
     /*  930864 */     // GIR_Coverage, 3687,
     /*  930864 */     GIR_EraseRootFromParent_Done,
     /*  930865 */   // Label 14893: @930865
     /*  930865 */   GIM_Try, /*On fail goto*//*Label 14894*/ GIMT_Encode4(930935), // Rule ID 3688 //
     /*  930870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  930873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  930884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  930887 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930890 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930893 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930900 */     // MIs[0] cbsz
     /*  930900 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930903 */     // MIs[0] blgp
     /*  930903 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930906 */     // MIs[0] Operand 7
     /*  930906 */     // No operand predicates
     /*  930906 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930910 */     // MIs[0] Operand 9
     /*  930910 */     // No operand predicates
     /*  930910 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930914 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930918 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  930921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930923 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930925 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930927 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930929 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  930931 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  930933 */     GIR_RootConstrainSelectedInstOperands,
     /*  930934 */     // GIR_Coverage, 3688,
     /*  930934 */     GIR_EraseRootFromParent_Done,
     /*  930935 */   // Label 14894: @930935
     /*  930935 */   GIM_Try, /*On fail goto*//*Label 14895*/ GIMT_Encode4(931005), // Rule ID 3694 //
     /*  930940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  930943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  930948 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  930951 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  930954 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  930957 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  930960 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  930963 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  930966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  930970 */     // MIs[0] cbsz
     /*  930970 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  930973 */     // MIs[0] blgp
     /*  930973 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  930976 */     // MIs[0] Operand 7
     /*  930976 */     // No operand predicates
     /*  930976 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  930980 */     // MIs[0] Operand 9
     /*  930980 */     // No operand predicates
     /*  930980 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  930984 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  930988 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  930988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  930991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  930993 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  930995 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  930997 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  930999 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931001 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931003 */     GIR_RootConstrainSelectedInstOperands,
     /*  931004 */     // GIR_Coverage, 3694,
     /*  931004 */     GIR_EraseRootFromParent_Done,
     /*  931005 */   // Label 14895: @931005
     /*  931005 */   GIM_Try, /*On fail goto*//*Label 14896*/ GIMT_Encode4(931075), // Rule ID 3695 //
     /*  931010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  931013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  931024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931027 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931030 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931033 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931040 */     // MIs[0] cbsz
     /*  931040 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931043 */     // MIs[0] blgp
     /*  931043 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931046 */     // MIs[0] Operand 7
     /*  931046 */     // No operand predicates
     /*  931046 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931050 */     // MIs[0] Operand 9
     /*  931050 */     // No operand predicates
     /*  931050 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931054 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931058 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  931061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931063 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931065 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931067 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931069 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931071 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931073 */     GIR_RootConstrainSelectedInstOperands,
     /*  931074 */     // GIR_Coverage, 3695,
     /*  931074 */     GIR_EraseRootFromParent_Done,
     /*  931075 */   // Label 14896: @931075
     /*  931075 */   GIM_Try, /*On fail goto*//*Label 14897*/ GIMT_Encode4(931145), // Rule ID 3696 //
     /*  931080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  931083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  931094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931097 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931100 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931103 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931110 */     // MIs[0] cbsz
     /*  931110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931113 */     // MIs[0] blgp
     /*  931113 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931116 */     // MIs[0] Operand 7
     /*  931116 */     // No operand predicates
     /*  931116 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931120 */     // MIs[0] Operand 9
     /*  931120 */     // No operand predicates
     /*  931120 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931124 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931128 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  931131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931133 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931135 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931137 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931139 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931141 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931143 */     GIR_RootConstrainSelectedInstOperands,
     /*  931144 */     // GIR_Coverage, 3696,
     /*  931144 */     GIR_EraseRootFromParent_Done,
     /*  931145 */   // Label 14897: @931145
     /*  931145 */   GIM_Try, /*On fail goto*//*Label 14898*/ GIMT_Encode4(931215), // Rule ID 3697 //
     /*  931150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  931153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  931164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931167 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931170 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931173 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931180 */     // MIs[0] cbsz
     /*  931180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931183 */     // MIs[0] blgp
     /*  931183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931186 */     // MIs[0] Operand 7
     /*  931186 */     // No operand predicates
     /*  931186 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931190 */     // MIs[0] Operand 9
     /*  931190 */     // No operand predicates
     /*  931190 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931194 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931198 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  931201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931203 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931205 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931207 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931209 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931211 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931213 */     GIR_RootConstrainSelectedInstOperands,
     /*  931214 */     // GIR_Coverage, 3697,
     /*  931214 */     GIR_EraseRootFromParent_Done,
     /*  931215 */   // Label 14898: @931215
     /*  931215 */   GIM_Try, /*On fail goto*//*Label 14899*/ GIMT_Encode4(931285), // Rule ID 3698 //
     /*  931220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  931223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931231 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  931234 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931237 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931240 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931243 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931250 */     // MIs[0] cbsz
     /*  931250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931253 */     // MIs[0] blgp
     /*  931253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931256 */     // MIs[0] Operand 7
     /*  931256 */     // No operand predicates
     /*  931256 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931260 */     // MIs[0] Operand 9
     /*  931260 */     // No operand predicates
     /*  931260 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931264 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931268 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  931271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931273 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931275 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931277 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931279 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931281 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931283 */     GIR_RootConstrainSelectedInstOperands,
     /*  931284 */     // GIR_Coverage, 3698,
     /*  931284 */     GIR_EraseRootFromParent_Done,
     /*  931285 */   // Label 14899: @931285
     /*  931285 */   GIM_Try, /*On fail goto*//*Label 14900*/ GIMT_Encode4(931355), // Rule ID 3704 //
     /*  931290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  931293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  931307 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931310 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931313 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931320 */     // MIs[0] cbsz
     /*  931320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931323 */     // MIs[0] blgp
     /*  931323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931326 */     // MIs[0] Operand 7
     /*  931326 */     // No operand predicates
     /*  931326 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931330 */     // MIs[0] Operand 9
     /*  931330 */     // No operand predicates
     /*  931330 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931334 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931338 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  931341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931343 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931345 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931347 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931349 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931351 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931353 */     GIR_RootConstrainSelectedInstOperands,
     /*  931354 */     // GIR_Coverage, 3704,
     /*  931354 */     GIR_EraseRootFromParent_Done,
     /*  931355 */   // Label 14900: @931355
     /*  931355 */   GIM_Try, /*On fail goto*//*Label 14901*/ GIMT_Encode4(931425), // Rule ID 3705 //
     /*  931360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  931363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931374 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  931377 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931380 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931383 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931390 */     // MIs[0] cbsz
     /*  931390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931393 */     // MIs[0] blgp
     /*  931393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931396 */     // MIs[0] Operand 7
     /*  931396 */     // No operand predicates
     /*  931396 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931400 */     // MIs[0] Operand 9
     /*  931400 */     // No operand predicates
     /*  931400 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931404 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931408 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  931411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931413 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931415 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931417 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931419 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931421 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931423 */     GIR_RootConstrainSelectedInstOperands,
     /*  931424 */     // GIR_Coverage, 3705,
     /*  931424 */     GIR_EraseRootFromParent_Done,
     /*  931425 */   // Label 14901: @931425
     /*  931425 */   GIM_Try, /*On fail goto*//*Label 14902*/ GIMT_Encode4(931495), // Rule ID 3706 //
     /*  931430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  931433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  931447 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931450 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931453 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931460 */     // MIs[0] cbsz
     /*  931460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931463 */     // MIs[0] blgp
     /*  931463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931466 */     // MIs[0] Operand 7
     /*  931466 */     // No operand predicates
     /*  931466 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931470 */     // MIs[0] Operand 9
     /*  931470 */     // No operand predicates
     /*  931470 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931474 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931478 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  931481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931483 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931485 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931487 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931489 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931491 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931493 */     GIR_RootConstrainSelectedInstOperands,
     /*  931494 */     // GIR_Coverage, 3706,
     /*  931494 */     GIR_EraseRootFromParent_Done,
     /*  931495 */   // Label 14902: @931495
     /*  931495 */   GIM_Try, /*On fail goto*//*Label 14903*/ GIMT_Encode4(931565), // Rule ID 3707 //
     /*  931500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  931503 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931508 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931511 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931514 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  931517 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931520 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931523 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931530 */     // MIs[0] cbsz
     /*  931530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931533 */     // MIs[0] blgp
     /*  931533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931536 */     // MIs[0] Operand 7
     /*  931536 */     // No operand predicates
     /*  931536 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931540 */     // MIs[0] Operand 9
     /*  931540 */     // No operand predicates
     /*  931540 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931544 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931548 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  931551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931553 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931555 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931557 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931559 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931561 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931563 */     GIR_RootConstrainSelectedInstOperands,
     /*  931564 */     // GIR_Coverage, 3707,
     /*  931564 */     GIR_EraseRootFromParent_Done,
     /*  931565 */   // Label 14903: @931565
     /*  931565 */   GIM_Try, /*On fail goto*//*Label 14904*/ GIMT_Encode4(931635), // Rule ID 3708 //
     /*  931570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  931573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931578 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931581 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931584 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  931587 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931590 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931593 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931600 */     // MIs[0] cbsz
     /*  931600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931603 */     // MIs[0] blgp
     /*  931603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931606 */     // MIs[0] Operand 7
     /*  931606 */     // No operand predicates
     /*  931606 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931610 */     // MIs[0] Operand 9
     /*  931610 */     // No operand predicates
     /*  931610 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931614 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931618 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  931621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931623 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931625 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931627 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931629 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931631 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931633 */     GIR_RootConstrainSelectedInstOperands,
     /*  931634 */     // GIR_Coverage, 3708,
     /*  931634 */     GIR_EraseRootFromParent_Done,
     /*  931635 */   // Label 14904: @931635
     /*  931635 */   GIM_Try, /*On fail goto*//*Label 14905*/ GIMT_Encode4(931705), // Rule ID 3714 //
     /*  931640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  931643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931657 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931660 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931663 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931670 */     // MIs[0] cbsz
     /*  931670 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931673 */     // MIs[0] blgp
     /*  931673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931676 */     // MIs[0] Operand 7
     /*  931676 */     // No operand predicates
     /*  931676 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931680 */     // MIs[0] Operand 9
     /*  931680 */     // No operand predicates
     /*  931680 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931684 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931688 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  931691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931693 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931695 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931697 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931699 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931701 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931703 */     GIR_RootConstrainSelectedInstOperands,
     /*  931704 */     // GIR_Coverage, 3714,
     /*  931704 */     GIR_EraseRootFromParent_Done,
     /*  931705 */   // Label 14905: @931705
     /*  931705 */   GIM_Try, /*On fail goto*//*Label 14906*/ GIMT_Encode4(931775), // Rule ID 3715 //
     /*  931710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  931713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931730 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931733 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931740 */     // MIs[0] cbsz
     /*  931740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931743 */     // MIs[0] blgp
     /*  931743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931746 */     // MIs[0] Operand 7
     /*  931746 */     // No operand predicates
     /*  931746 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931750 */     // MIs[0] Operand 9
     /*  931750 */     // No operand predicates
     /*  931750 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931754 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931758 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  931761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931763 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931765 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931767 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931769 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931771 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931773 */     GIR_RootConstrainSelectedInstOperands,
     /*  931774 */     // GIR_Coverage, 3715,
     /*  931774 */     GIR_EraseRootFromParent_Done,
     /*  931775 */   // Label 14906: @931775
     /*  931775 */   GIM_Try, /*On fail goto*//*Label 14907*/ GIMT_Encode4(931845), // Rule ID 3716 //
     /*  931780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  931783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931794 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931797 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931800 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931803 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931810 */     // MIs[0] cbsz
     /*  931810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931813 */     // MIs[0] blgp
     /*  931813 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931816 */     // MIs[0] Operand 7
     /*  931816 */     // No operand predicates
     /*  931816 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931820 */     // MIs[0] Operand 9
     /*  931820 */     // No operand predicates
     /*  931820 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931824 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931828 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  931831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931833 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931835 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931837 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931839 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931841 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931843 */     GIR_RootConstrainSelectedInstOperands,
     /*  931844 */     // GIR_Coverage, 3716,
     /*  931844 */     GIR_EraseRootFromParent_Done,
     /*  931845 */   // Label 14907: @931845
     /*  931845 */   GIM_Try, /*On fail goto*//*Label 14908*/ GIMT_Encode4(931915), // Rule ID 3717 //
     /*  931850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  931853 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931858 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931861 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931864 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931867 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931870 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931873 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931880 */     // MIs[0] cbsz
     /*  931880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931883 */     // MIs[0] blgp
     /*  931883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931886 */     // MIs[0] Operand 7
     /*  931886 */     // No operand predicates
     /*  931886 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931890 */     // MIs[0] Operand 9
     /*  931890 */     // No operand predicates
     /*  931890 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931894 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931898 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  931901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931903 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931905 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931907 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931909 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931911 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931913 */     GIR_RootConstrainSelectedInstOperands,
     /*  931914 */     // GIR_Coverage, 3717,
     /*  931914 */     GIR_EraseRootFromParent_Done,
     /*  931915 */   // Label 14908: @931915
     /*  931915 */   GIM_Try, /*On fail goto*//*Label 14909*/ GIMT_Encode4(931985), // Rule ID 3718 //
     /*  931920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  931923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  931928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  931931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  931934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  931937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  931940 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  931943 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  931946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  931950 */     // MIs[0] cbsz
     /*  931950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  931953 */     // MIs[0] blgp
     /*  931953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  931956 */     // MIs[0] Operand 7
     /*  931956 */     // No operand predicates
     /*  931956 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  931960 */     // MIs[0] Operand 9
     /*  931960 */     // No operand predicates
     /*  931960 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  931964 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31860),
     /*  931968 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })<<P:Predicate_anonymous_31860>>  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  931968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  931971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  931973 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  931975 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  931977 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  931979 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  931981 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  931983 */     GIR_RootConstrainSelectedInstOperands,
     /*  931984 */     // GIR_Coverage, 3718,
     /*  931984 */     GIR_EraseRootFromParent_Done,
     /*  931985 */   // Label 14909: @931985
     /*  931985 */   GIM_Try, /*On fail goto*//*Label 14910*/ GIMT_Encode4(932051), // Rule ID 3549 //
     /*  931990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  931993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  931998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932007 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932010 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932013 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932020 */     // MIs[0] cbsz
     /*  932020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932023 */     // MIs[0] blgp
     /*  932023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932026 */     // MIs[0] Operand 7
     /*  932026 */     // No operand predicates
     /*  932026 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932030 */     // MIs[0] Operand 9
     /*  932030 */     // No operand predicates
     /*  932030 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932034 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  932037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932039 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932041 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932043 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932045 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932047 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932049 */     GIR_RootConstrainSelectedInstOperands,
     /*  932050 */     // GIR_Coverage, 3549,
     /*  932050 */     GIR_EraseRootFromParent_Done,
     /*  932051 */   // Label 14910: @932051
     /*  932051 */   GIM_Try, /*On fail goto*//*Label 14911*/ GIMT_Encode4(932117), // Rule ID 3550 //
     /*  932056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  932059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932070 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932073 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932076 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932079 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932086 */     // MIs[0] cbsz
     /*  932086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932089 */     // MIs[0] blgp
     /*  932089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932092 */     // MIs[0] Operand 7
     /*  932092 */     // No operand predicates
     /*  932092 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932096 */     // MIs[0] Operand 9
     /*  932096 */     // No operand predicates
     /*  932096 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932100 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  932103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932105 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932107 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932109 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932111 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932113 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932115 */     GIR_RootConstrainSelectedInstOperands,
     /*  932116 */     // GIR_Coverage, 3550,
     /*  932116 */     GIR_EraseRootFromParent_Done,
     /*  932117 */   // Label 14911: @932117
     /*  932117 */   GIM_Try, /*On fail goto*//*Label 14912*/ GIMT_Encode4(932183), // Rule ID 3551 //
     /*  932122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  932125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932139 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932142 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932145 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932152 */     // MIs[0] cbsz
     /*  932152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932155 */     // MIs[0] blgp
     /*  932155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932158 */     // MIs[0] Operand 7
     /*  932158 */     // No operand predicates
     /*  932158 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932162 */     // MIs[0] Operand 9
     /*  932162 */     // No operand predicates
     /*  932162 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932166 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  932169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932171 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932173 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932175 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932177 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932179 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932181 */     GIR_RootConstrainSelectedInstOperands,
     /*  932182 */     // GIR_Coverage, 3551,
     /*  932182 */     GIR_EraseRootFromParent_Done,
     /*  932183 */   // Label 14912: @932183
     /*  932183 */   GIM_Try, /*On fail goto*//*Label 14913*/ GIMT_Encode4(932249), // Rule ID 3552 //
     /*  932188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  932191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932208 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932211 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932218 */     // MIs[0] cbsz
     /*  932218 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932221 */     // MIs[0] blgp
     /*  932221 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932224 */     // MIs[0] Operand 7
     /*  932224 */     // No operand predicates
     /*  932224 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932228 */     // MIs[0] Operand 9
     /*  932228 */     // No operand predicates
     /*  932228 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932232 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  932235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932237 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932239 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932241 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932243 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932245 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932247 */     GIR_RootConstrainSelectedInstOperands,
     /*  932248 */     // GIR_Coverage, 3552,
     /*  932248 */     GIR_EraseRootFromParent_Done,
     /*  932249 */   // Label 14913: @932249
     /*  932249 */   GIM_Try, /*On fail goto*//*Label 14914*/ GIMT_Encode4(932315), // Rule ID 3553 //
     /*  932254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  932257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932271 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932274 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932277 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932284 */     // MIs[0] cbsz
     /*  932284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932287 */     // MIs[0] blgp
     /*  932287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932290 */     // MIs[0] Operand 7
     /*  932290 */     // No operand predicates
     /*  932290 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932294 */     // MIs[0] Operand 9
     /*  932294 */     // No operand predicates
     /*  932294 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932298 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  932301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932303 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932305 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932307 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932309 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932311 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932313 */     GIR_RootConstrainSelectedInstOperands,
     /*  932314 */     // GIR_Coverage, 3553,
     /*  932314 */     GIR_EraseRootFromParent_Done,
     /*  932315 */   // Label 14914: @932315
     /*  932315 */   GIM_Try, /*On fail goto*//*Label 14915*/ GIMT_Encode4(932381), // Rule ID 3559 //
     /*  932320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  932323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  932337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932340 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932343 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932350 */     // MIs[0] cbsz
     /*  932350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932353 */     // MIs[0] blgp
     /*  932353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932356 */     // MIs[0] Operand 7
     /*  932356 */     // No operand predicates
     /*  932356 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932360 */     // MIs[0] Operand 9
     /*  932360 */     // No operand predicates
     /*  932360 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932364 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  932367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932369 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932371 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932373 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932375 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932377 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932379 */     GIR_RootConstrainSelectedInstOperands,
     /*  932380 */     // GIR_Coverage, 3559,
     /*  932380 */     GIR_EraseRootFromParent_Done,
     /*  932381 */   // Label 14915: @932381
     /*  932381 */   GIM_Try, /*On fail goto*//*Label 14916*/ GIMT_Encode4(932447), // Rule ID 3560 //
     /*  932386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  932389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932400 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  932403 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932406 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932409 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932416 */     // MIs[0] cbsz
     /*  932416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932419 */     // MIs[0] blgp
     /*  932419 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932422 */     // MIs[0] Operand 7
     /*  932422 */     // No operand predicates
     /*  932422 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932426 */     // MIs[0] Operand 9
     /*  932426 */     // No operand predicates
     /*  932426 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932430 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  932433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932437 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932439 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932441 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932443 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932445 */     GIR_RootConstrainSelectedInstOperands,
     /*  932446 */     // GIR_Coverage, 3560,
     /*  932446 */     GIR_EraseRootFromParent_Done,
     /*  932447 */   // Label 14916: @932447
     /*  932447 */   GIM_Try, /*On fail goto*//*Label 14917*/ GIMT_Encode4(932513), // Rule ID 3561 //
     /*  932452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  932455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  932469 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932472 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932475 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932482 */     // MIs[0] cbsz
     /*  932482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932485 */     // MIs[0] blgp
     /*  932485 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932488 */     // MIs[0] Operand 7
     /*  932488 */     // No operand predicates
     /*  932488 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932492 */     // MIs[0] Operand 9
     /*  932492 */     // No operand predicates
     /*  932492 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932496 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  932499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932501 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932503 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932505 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932507 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932509 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932511 */     GIR_RootConstrainSelectedInstOperands,
     /*  932512 */     // GIR_Coverage, 3561,
     /*  932512 */     GIR_EraseRootFromParent_Done,
     /*  932513 */   // Label 14917: @932513
     /*  932513 */   GIM_Try, /*On fail goto*//*Label 14918*/ GIMT_Encode4(932579), // Rule ID 3562 //
     /*  932518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  932521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  932535 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932538 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932541 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932548 */     // MIs[0] cbsz
     /*  932548 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932551 */     // MIs[0] blgp
     /*  932551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932554 */     // MIs[0] Operand 7
     /*  932554 */     // No operand predicates
     /*  932554 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932558 */     // MIs[0] Operand 9
     /*  932558 */     // No operand predicates
     /*  932558 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932562 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  932565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932567 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932569 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932571 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932573 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932575 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932577 */     GIR_RootConstrainSelectedInstOperands,
     /*  932578 */     // GIR_Coverage, 3562,
     /*  932578 */     GIR_EraseRootFromParent_Done,
     /*  932579 */   // Label 14918: @932579
     /*  932579 */   GIM_Try, /*On fail goto*//*Label 14919*/ GIMT_Encode4(932645), // Rule ID 3563 //
     /*  932584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  932587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  932598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  932601 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932604 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932607 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932614 */     // MIs[0] cbsz
     /*  932614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932617 */     // MIs[0] blgp
     /*  932617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932620 */     // MIs[0] Operand 7
     /*  932620 */     // No operand predicates
     /*  932620 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932624 */     // MIs[0] Operand 9
     /*  932624 */     // No operand predicates
     /*  932624 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932628 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  932631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932633 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932635 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932637 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932639 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932641 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932643 */     GIR_RootConstrainSelectedInstOperands,
     /*  932644 */     // GIR_Coverage, 3563,
     /*  932644 */     GIR_EraseRootFromParent_Done,
     /*  932645 */   // Label 14919: @932645
     /*  932645 */   GIM_Try, /*On fail goto*//*Label 14920*/ GIMT_Encode4(932711), // Rule ID 3569 //
     /*  932650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  932653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  932664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932667 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932670 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932673 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932680 */     // MIs[0] cbsz
     /*  932680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932683 */     // MIs[0] blgp
     /*  932683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932686 */     // MIs[0] Operand 7
     /*  932686 */     // No operand predicates
     /*  932686 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932690 */     // MIs[0] Operand 9
     /*  932690 */     // No operand predicates
     /*  932690 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932694 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  932697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932699 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932701 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932703 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932705 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932707 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932709 */     GIR_RootConstrainSelectedInstOperands,
     /*  932710 */     // GIR_Coverage, 3569,
     /*  932710 */     GIR_EraseRootFromParent_Done,
     /*  932711 */   // Label 14920: @932711
     /*  932711 */   GIM_Try, /*On fail goto*//*Label 14921*/ GIMT_Encode4(932777), // Rule ID 3570 //
     /*  932716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  932719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932727 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  932730 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932733 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932736 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932739 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932746 */     // MIs[0] cbsz
     /*  932746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932749 */     // MIs[0] blgp
     /*  932749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932752 */     // MIs[0] Operand 7
     /*  932752 */     // No operand predicates
     /*  932752 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932756 */     // MIs[0] Operand 9
     /*  932756 */     // No operand predicates
     /*  932756 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932760 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  932763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932765 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932767 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932769 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932771 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932773 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932775 */     GIR_RootConstrainSelectedInstOperands,
     /*  932776 */     // GIR_Coverage, 3570,
     /*  932776 */     GIR_EraseRootFromParent_Done,
     /*  932777 */   // Label 14921: @932777
     /*  932777 */   GIM_Try, /*On fail goto*//*Label 14922*/ GIMT_Encode4(932843), // Rule ID 3571 //
     /*  932782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  932785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  932796 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932799 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932802 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932805 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932812 */     // MIs[0] cbsz
     /*  932812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932815 */     // MIs[0] blgp
     /*  932815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932818 */     // MIs[0] Operand 7
     /*  932818 */     // No operand predicates
     /*  932818 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932822 */     // MIs[0] Operand 9
     /*  932822 */     // No operand predicates
     /*  932822 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932826 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  932829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932831 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932833 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932835 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932837 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932839 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932841 */     GIR_RootConstrainSelectedInstOperands,
     /*  932842 */     // GIR_Coverage, 3571,
     /*  932842 */     GIR_EraseRootFromParent_Done,
     /*  932843 */   // Label 14922: @932843
     /*  932843 */   GIM_Try, /*On fail goto*//*Label 14923*/ GIMT_Encode4(932909), // Rule ID 3572 //
     /*  932848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  932851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  932862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932865 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932868 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932871 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932878 */     // MIs[0] cbsz
     /*  932878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932881 */     // MIs[0] blgp
     /*  932881 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932884 */     // MIs[0] Operand 7
     /*  932884 */     // No operand predicates
     /*  932884 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932888 */     // MIs[0] Operand 9
     /*  932888 */     // No operand predicates
     /*  932888 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932892 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  932895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932897 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932899 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932901 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932903 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932905 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932907 */     GIR_RootConstrainSelectedInstOperands,
     /*  932908 */     // GIR_Coverage, 3572,
     /*  932908 */     GIR_EraseRootFromParent_Done,
     /*  932909 */   // Label 14923: @932909
     /*  932909 */   GIM_Try, /*On fail goto*//*Label 14924*/ GIMT_Encode4(932975), // Rule ID 3573 //
     /*  932914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  932917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  932928 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  932931 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  932934 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  932937 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  932940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  932944 */     // MIs[0] cbsz
     /*  932944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  932947 */     // MIs[0] blgp
     /*  932947 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  932950 */     // MIs[0] Operand 7
     /*  932950 */     // No operand predicates
     /*  932950 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  932954 */     // MIs[0] Operand 9
     /*  932954 */     // No operand predicates
     /*  932954 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  932958 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  932958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  932961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  932963 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  932965 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  932967 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  932969 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  932971 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  932973 */     GIR_RootConstrainSelectedInstOperands,
     /*  932974 */     // GIR_Coverage, 3573,
     /*  932974 */     GIR_EraseRootFromParent_Done,
     /*  932975 */   // Label 14924: @932975
     /*  932975 */   GIM_Try, /*On fail goto*//*Label 14925*/ GIMT_Encode4(933041), // Rule ID 3579 //
     /*  932980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  932983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  932988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  932991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  932994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  932997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933000 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933003 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933010 */     // MIs[0] cbsz
     /*  933010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933013 */     // MIs[0] blgp
     /*  933013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933016 */     // MIs[0] Operand 7
     /*  933016 */     // No operand predicates
     /*  933016 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933020 */     // MIs[0] Operand 9
     /*  933020 */     // No operand predicates
     /*  933020 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933024 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  933027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933029 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933031 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933033 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933035 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933037 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933039 */     GIR_RootConstrainSelectedInstOperands,
     /*  933040 */     // GIR_Coverage, 3579,
     /*  933040 */     GIR_EraseRootFromParent_Done,
     /*  933041 */   // Label 14925: @933041
     /*  933041 */   GIM_Try, /*On fail goto*//*Label 14926*/ GIMT_Encode4(933107), // Rule ID 3580 //
     /*  933046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  933049 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933054 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933057 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  933060 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  933063 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933066 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933069 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933076 */     // MIs[0] cbsz
     /*  933076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933079 */     // MIs[0] blgp
     /*  933079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933082 */     // MIs[0] Operand 7
     /*  933082 */     // No operand predicates
     /*  933082 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933086 */     // MIs[0] Operand 9
     /*  933086 */     // No operand predicates
     /*  933086 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933090 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  933093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933095 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933097 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933099 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933101 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933103 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933105 */     GIR_RootConstrainSelectedInstOperands,
     /*  933106 */     // GIR_Coverage, 3580,
     /*  933106 */     GIR_EraseRootFromParent_Done,
     /*  933107 */   // Label 14926: @933107
     /*  933107 */   GIM_Try, /*On fail goto*//*Label 14927*/ GIMT_Encode4(933173), // Rule ID 3581 //
     /*  933112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  933115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  933126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  933129 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933132 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933135 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933142 */     // MIs[0] cbsz
     /*  933142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933145 */     // MIs[0] blgp
     /*  933145 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933148 */     // MIs[0] Operand 7
     /*  933148 */     // No operand predicates
     /*  933148 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933152 */     // MIs[0] Operand 9
     /*  933152 */     // No operand predicates
     /*  933152 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933156 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  933159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933161 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933163 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933165 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933167 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933169 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933171 */     GIR_RootConstrainSelectedInstOperands,
     /*  933172 */     // GIR_Coverage, 3581,
     /*  933172 */     GIR_EraseRootFromParent_Done,
     /*  933173 */   // Label 14927: @933173
     /*  933173 */   GIM_Try, /*On fail goto*//*Label 14928*/ GIMT_Encode4(933239), // Rule ID 3582 //
     /*  933178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  933181 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933186 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933189 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  933192 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  933195 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933198 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933201 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933208 */     // MIs[0] cbsz
     /*  933208 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933211 */     // MIs[0] blgp
     /*  933211 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933214 */     // MIs[0] Operand 7
     /*  933214 */     // No operand predicates
     /*  933214 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933218 */     // MIs[0] Operand 9
     /*  933218 */     // No operand predicates
     /*  933218 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933222 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  933225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933229 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933231 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933233 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933235 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933237 */     GIR_RootConstrainSelectedInstOperands,
     /*  933238 */     // GIR_Coverage, 3582,
     /*  933238 */     GIR_EraseRootFromParent_Done,
     /*  933239 */   // Label 14928: @933239
     /*  933239 */   GIM_Try, /*On fail goto*//*Label 14929*/ GIMT_Encode4(933305), // Rule ID 3583 //
     /*  933244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  933247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  933258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  933261 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933264 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933267 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933274 */     // MIs[0] cbsz
     /*  933274 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933277 */     // MIs[0] blgp
     /*  933277 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933280 */     // MIs[0] Operand 7
     /*  933280 */     // No operand predicates
     /*  933280 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933284 */     // MIs[0] Operand 9
     /*  933284 */     // No operand predicates
     /*  933284 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933288 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  933291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933293 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933295 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933297 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933299 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933301 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933303 */     GIR_RootConstrainSelectedInstOperands,
     /*  933304 */     // GIR_Coverage, 3583,
     /*  933304 */     GIR_EraseRootFromParent_Done,
     /*  933305 */   // Label 14929: @933305
     /*  933305 */   GIM_Try, /*On fail goto*//*Label 14930*/ GIMT_Encode4(933371), // Rule ID 3589 //
     /*  933310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  933313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  933324 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  933327 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933330 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933333 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933340 */     // MIs[0] cbsz
     /*  933340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933343 */     // MIs[0] blgp
     /*  933343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933346 */     // MIs[0] Operand 7
     /*  933346 */     // No operand predicates
     /*  933346 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933350 */     // MIs[0] Operand 9
     /*  933350 */     // No operand predicates
     /*  933350 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933354 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  933357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933359 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933361 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933363 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933365 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933367 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933369 */     GIR_RootConstrainSelectedInstOperands,
     /*  933370 */     // GIR_Coverage, 3589,
     /*  933370 */     GIR_EraseRootFromParent_Done,
     /*  933371 */   // Label 14930: @933371
     /*  933371 */   GIM_Try, /*On fail goto*//*Label 14931*/ GIMT_Encode4(933437), // Rule ID 3590 //
     /*  933376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  933379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933387 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  933390 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  933393 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933396 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933399 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933406 */     // MIs[0] cbsz
     /*  933406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933409 */     // MIs[0] blgp
     /*  933409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933412 */     // MIs[0] Operand 7
     /*  933412 */     // No operand predicates
     /*  933412 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933416 */     // MIs[0] Operand 9
     /*  933416 */     // No operand predicates
     /*  933416 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933420 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  933423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933425 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933427 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933429 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933431 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933433 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933435 */     GIR_RootConstrainSelectedInstOperands,
     /*  933436 */     // GIR_Coverage, 3590,
     /*  933436 */     GIR_EraseRootFromParent_Done,
     /*  933437 */   // Label 14931: @933437
     /*  933437 */   GIM_Try, /*On fail goto*//*Label 14932*/ GIMT_Encode4(933503), // Rule ID 3591 //
     /*  933442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  933445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  933456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  933459 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933462 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933465 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933472 */     // MIs[0] cbsz
     /*  933472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933475 */     // MIs[0] blgp
     /*  933475 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933478 */     // MIs[0] Operand 7
     /*  933478 */     // No operand predicates
     /*  933478 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933482 */     // MIs[0] Operand 9
     /*  933482 */     // No operand predicates
     /*  933482 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933486 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  933489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933491 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933493 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933495 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933497 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933499 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933501 */     GIR_RootConstrainSelectedInstOperands,
     /*  933502 */     // GIR_Coverage, 3591,
     /*  933502 */     GIR_EraseRootFromParent_Done,
     /*  933503 */   // Label 14932: @933503
     /*  933503 */   GIM_Try, /*On fail goto*//*Label 14933*/ GIMT_Encode4(933569), // Rule ID 3592 //
     /*  933508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  933511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  933522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  933525 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933528 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933531 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933538 */     // MIs[0] cbsz
     /*  933538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933541 */     // MIs[0] blgp
     /*  933541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933544 */     // MIs[0] Operand 7
     /*  933544 */     // No operand predicates
     /*  933544 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933548 */     // MIs[0] Operand 9
     /*  933548 */     // No operand predicates
     /*  933548 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933552 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  933555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933557 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933559 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933561 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933563 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933565 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933567 */     GIR_RootConstrainSelectedInstOperands,
     /*  933568 */     // GIR_Coverage, 3592,
     /*  933568 */     GIR_EraseRootFromParent_Done,
     /*  933569 */   // Label 14933: @933569
     /*  933569 */   GIM_Try, /*On fail goto*//*Label 14934*/ GIMT_Encode4(933635), // Rule ID 3593 //
     /*  933574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  933577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  933588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  933591 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933594 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933597 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933604 */     // MIs[0] cbsz
     /*  933604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933607 */     // MIs[0] blgp
     /*  933607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933610 */     // MIs[0] Operand 7
     /*  933610 */     // No operand predicates
     /*  933610 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933614 */     // MIs[0] Operand 9
     /*  933614 */     // No operand predicates
     /*  933614 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933618 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  933621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933623 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933625 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933627 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933629 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933631 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933633 */     GIR_RootConstrainSelectedInstOperands,
     /*  933634 */     // GIR_Coverage, 3593,
     /*  933634 */     GIR_EraseRootFromParent_Done,
     /*  933635 */   // Label 14934: @933635
     /*  933635 */   GIM_Try, /*On fail goto*//*Label 14935*/ GIMT_Encode4(933701), // Rule ID 3599 //
     /*  933640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  933643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  933654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  933657 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933660 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933663 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933670 */     // MIs[0] cbsz
     /*  933670 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933673 */     // MIs[0] blgp
     /*  933673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933676 */     // MIs[0] Operand 7
     /*  933676 */     // No operand predicates
     /*  933676 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933680 */     // MIs[0] Operand 9
     /*  933680 */     // No operand predicates
     /*  933680 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933684 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  933687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933689 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933691 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933693 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933695 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933697 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933699 */     GIR_RootConstrainSelectedInstOperands,
     /*  933700 */     // GIR_Coverage, 3599,
     /*  933700 */     GIR_EraseRootFromParent_Done,
     /*  933701 */   // Label 14935: @933701
     /*  933701 */   GIM_Try, /*On fail goto*//*Label 14936*/ GIMT_Encode4(933767), // Rule ID 3600 //
     /*  933706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  933709 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933714 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933717 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  933720 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  933723 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933726 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933729 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933736 */     // MIs[0] cbsz
     /*  933736 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933739 */     // MIs[0] blgp
     /*  933739 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933742 */     // MIs[0] Operand 7
     /*  933742 */     // No operand predicates
     /*  933742 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933746 */     // MIs[0] Operand 9
     /*  933746 */     // No operand predicates
     /*  933746 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933750 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  933753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933755 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933757 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933759 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933761 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933763 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933765 */     GIR_RootConstrainSelectedInstOperands,
     /*  933766 */     // GIR_Coverage, 3600,
     /*  933766 */     GIR_EraseRootFromParent_Done,
     /*  933767 */   // Label 14936: @933767
     /*  933767 */   GIM_Try, /*On fail goto*//*Label 14937*/ GIMT_Encode4(933833), // Rule ID 3601 //
     /*  933772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  933775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  933786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  933789 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933792 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933795 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933802 */     // MIs[0] cbsz
     /*  933802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933805 */     // MIs[0] blgp
     /*  933805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933808 */     // MIs[0] Operand 7
     /*  933808 */     // No operand predicates
     /*  933808 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933812 */     // MIs[0] Operand 9
     /*  933812 */     // No operand predicates
     /*  933812 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933816 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  933819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933821 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933823 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933825 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933827 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933829 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933831 */     GIR_RootConstrainSelectedInstOperands,
     /*  933832 */     // GIR_Coverage, 3601,
     /*  933832 */     GIR_EraseRootFromParent_Done,
     /*  933833 */   // Label 14937: @933833
     /*  933833 */   GIM_Try, /*On fail goto*//*Label 14938*/ GIMT_Encode4(933899), // Rule ID 3602 //
     /*  933838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  933841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  933852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  933855 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933858 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933861 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933868 */     // MIs[0] cbsz
     /*  933868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933871 */     // MIs[0] blgp
     /*  933871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933874 */     // MIs[0] Operand 7
     /*  933874 */     // No operand predicates
     /*  933874 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933878 */     // MIs[0] Operand 9
     /*  933878 */     // No operand predicates
     /*  933878 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933882 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  933885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933887 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933889 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933891 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933893 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933895 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933897 */     GIR_RootConstrainSelectedInstOperands,
     /*  933898 */     // GIR_Coverage, 3602,
     /*  933898 */     GIR_EraseRootFromParent_Done,
     /*  933899 */   // Label 14938: @933899
     /*  933899 */   GIM_Try, /*On fail goto*//*Label 14939*/ GIMT_Encode4(933965), // Rule ID 3603 //
     /*  933904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  933907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  933918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  933921 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933924 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933927 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  933934 */     // MIs[0] cbsz
     /*  933934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  933937 */     // MIs[0] blgp
     /*  933937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  933940 */     // MIs[0] Operand 7
     /*  933940 */     // No operand predicates
     /*  933940 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  933944 */     // MIs[0] Operand 9
     /*  933944 */     // No operand predicates
     /*  933944 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  933948 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  933948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  933951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  933953 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  933955 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  933957 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  933959 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  933961 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  933963 */     GIR_RootConstrainSelectedInstOperands,
     /*  933964 */     // GIR_Coverage, 3603,
     /*  933964 */     GIR_EraseRootFromParent_Done,
     /*  933965 */   // Label 14939: @933965
     /*  933965 */   GIM_Try, /*On fail goto*//*Label 14940*/ GIMT_Encode4(934031), // Rule ID 3609 //
     /*  933970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  933973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  933978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  933981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  933984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  933987 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  933990 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  933993 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  933996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934000 */     // MIs[0] cbsz
     /*  934000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934003 */     // MIs[0] blgp
     /*  934003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934006 */     // MIs[0] Operand 7
     /*  934006 */     // No operand predicates
     /*  934006 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934010 */     // MIs[0] Operand 9
     /*  934010 */     // No operand predicates
     /*  934010 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934014 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  934017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934019 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934021 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934023 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934025 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934027 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934029 */     GIR_RootConstrainSelectedInstOperands,
     /*  934030 */     // GIR_Coverage, 3609,
     /*  934030 */     GIR_EraseRootFromParent_Done,
     /*  934031 */   // Label 14940: @934031
     /*  934031 */   GIM_Try, /*On fail goto*//*Label 14941*/ GIMT_Encode4(934097), // Rule ID 3610 //
     /*  934036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  934039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  934050 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934053 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934056 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934059 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934066 */     // MIs[0] cbsz
     /*  934066 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934069 */     // MIs[0] blgp
     /*  934069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934072 */     // MIs[0] Operand 7
     /*  934072 */     // No operand predicates
     /*  934072 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934076 */     // MIs[0] Operand 9
     /*  934076 */     // No operand predicates
     /*  934076 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934080 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  934083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934085 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934087 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934089 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934091 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934093 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934095 */     GIR_RootConstrainSelectedInstOperands,
     /*  934096 */     // GIR_Coverage, 3610,
     /*  934096 */     GIR_EraseRootFromParent_Done,
     /*  934097 */   // Label 14941: @934097
     /*  934097 */   GIM_Try, /*On fail goto*//*Label 14942*/ GIMT_Encode4(934163), // Rule ID 3611 //
     /*  934102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  934105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  934116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934119 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934122 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934125 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934132 */     // MIs[0] cbsz
     /*  934132 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934135 */     // MIs[0] blgp
     /*  934135 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934138 */     // MIs[0] Operand 7
     /*  934138 */     // No operand predicates
     /*  934138 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934142 */     // MIs[0] Operand 9
     /*  934142 */     // No operand predicates
     /*  934142 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934146 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  934149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934151 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934153 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934155 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934157 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934159 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934161 */     GIR_RootConstrainSelectedInstOperands,
     /*  934162 */     // GIR_Coverage, 3611,
     /*  934162 */     GIR_EraseRootFromParent_Done,
     /*  934163 */   // Label 14942: @934163
     /*  934163 */   GIM_Try, /*On fail goto*//*Label 14943*/ GIMT_Encode4(934229), // Rule ID 3612 //
     /*  934168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  934171 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934176 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934179 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  934182 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934185 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934188 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934191 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934198 */     // MIs[0] cbsz
     /*  934198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934201 */     // MIs[0] blgp
     /*  934201 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934204 */     // MIs[0] Operand 7
     /*  934204 */     // No operand predicates
     /*  934204 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934208 */     // MIs[0] Operand 9
     /*  934208 */     // No operand predicates
     /*  934208 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934212 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  934215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934217 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934219 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934221 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934223 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934225 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934227 */     GIR_RootConstrainSelectedInstOperands,
     /*  934228 */     // GIR_Coverage, 3612,
     /*  934228 */     GIR_EraseRootFromParent_Done,
     /*  934229 */   // Label 14943: @934229
     /*  934229 */   GIM_Try, /*On fail goto*//*Label 14944*/ GIMT_Encode4(934295), // Rule ID 3613 //
     /*  934234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  934237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  934248 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934251 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934254 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934257 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934264 */     // MIs[0] cbsz
     /*  934264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934267 */     // MIs[0] blgp
     /*  934267 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934270 */     // MIs[0] Operand 7
     /*  934270 */     // No operand predicates
     /*  934270 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934274 */     // MIs[0] Operand 9
     /*  934274 */     // No operand predicates
     /*  934274 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934278 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  934281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934283 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934285 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934287 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934289 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934291 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934293 */     GIR_RootConstrainSelectedInstOperands,
     /*  934294 */     // GIR_Coverage, 3613,
     /*  934294 */     GIR_EraseRootFromParent_Done,
     /*  934295 */   // Label 14944: @934295
     /*  934295 */   GIM_Try, /*On fail goto*//*Label 14945*/ GIMT_Encode4(934361), // Rule ID 3619 //
     /*  934300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  934303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  934317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934320 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934323 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934330 */     // MIs[0] cbsz
     /*  934330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934333 */     // MIs[0] blgp
     /*  934333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934336 */     // MIs[0] Operand 7
     /*  934336 */     // No operand predicates
     /*  934336 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934340 */     // MIs[0] Operand 9
     /*  934340 */     // No operand predicates
     /*  934340 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934344 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  934347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934349 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934351 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934353 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934355 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934357 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934359 */     GIR_RootConstrainSelectedInstOperands,
     /*  934360 */     // GIR_Coverage, 3619,
     /*  934360 */     GIR_EraseRootFromParent_Done,
     /*  934361 */   // Label 14945: @934361
     /*  934361 */   GIM_Try, /*On fail goto*//*Label 14946*/ GIMT_Encode4(934427), // Rule ID 3620 //
     /*  934366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  934369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  934383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934386 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934389 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934396 */     // MIs[0] cbsz
     /*  934396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934399 */     // MIs[0] blgp
     /*  934399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934402 */     // MIs[0] Operand 7
     /*  934402 */     // No operand predicates
     /*  934402 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934406 */     // MIs[0] Operand 9
     /*  934406 */     // No operand predicates
     /*  934406 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934410 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  934413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934415 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934417 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934419 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934421 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934423 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934425 */     GIR_RootConstrainSelectedInstOperands,
     /*  934426 */     // GIR_Coverage, 3620,
     /*  934426 */     GIR_EraseRootFromParent_Done,
     /*  934427 */   // Label 14946: @934427
     /*  934427 */   GIM_Try, /*On fail goto*//*Label 14947*/ GIMT_Encode4(934493), // Rule ID 3621 //
     /*  934432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  934435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  934449 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934452 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934455 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934462 */     // MIs[0] cbsz
     /*  934462 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934465 */     // MIs[0] blgp
     /*  934465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934468 */     // MIs[0] Operand 7
     /*  934468 */     // No operand predicates
     /*  934468 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934472 */     // MIs[0] Operand 9
     /*  934472 */     // No operand predicates
     /*  934472 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934476 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  934479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934481 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934483 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934485 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934487 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934489 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934491 */     GIR_RootConstrainSelectedInstOperands,
     /*  934492 */     // GIR_Coverage, 3621,
     /*  934492 */     GIR_EraseRootFromParent_Done,
     /*  934493 */   // Label 14947: @934493
     /*  934493 */   GIM_Try, /*On fail goto*//*Label 14948*/ GIMT_Encode4(934559), // Rule ID 3622 //
     /*  934498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  934501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  934515 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934518 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934521 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934528 */     // MIs[0] cbsz
     /*  934528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934531 */     // MIs[0] blgp
     /*  934531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934534 */     // MIs[0] Operand 7
     /*  934534 */     // No operand predicates
     /*  934534 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934538 */     // MIs[0] Operand 9
     /*  934538 */     // No operand predicates
     /*  934538 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934542 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  934545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934547 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934549 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934551 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934553 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934555 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934557 */     GIR_RootConstrainSelectedInstOperands,
     /*  934558 */     // GIR_Coverage, 3622,
     /*  934558 */     GIR_EraseRootFromParent_Done,
     /*  934559 */   // Label 14948: @934559
     /*  934559 */   GIM_Try, /*On fail goto*//*Label 14949*/ GIMT_Encode4(934625), // Rule ID 3623 //
     /*  934564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  934567 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934572 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934575 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934578 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  934581 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934584 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934587 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934594 */     // MIs[0] cbsz
     /*  934594 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934597 */     // MIs[0] blgp
     /*  934597 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934600 */     // MIs[0] Operand 7
     /*  934600 */     // No operand predicates
     /*  934600 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934604 */     // MIs[0] Operand 9
     /*  934604 */     // No operand predicates
     /*  934604 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934608 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  934611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934613 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934615 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934617 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934619 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934621 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934623 */     GIR_RootConstrainSelectedInstOperands,
     /*  934624 */     // GIR_Coverage, 3623,
     /*  934624 */     GIR_EraseRootFromParent_Done,
     /*  934625 */   // Label 14949: @934625
     /*  934625 */   GIM_Try, /*On fail goto*//*Label 14950*/ GIMT_Encode4(934691), // Rule ID 3629 //
     /*  934630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  934633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934647 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934650 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934653 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934660 */     // MIs[0] cbsz
     /*  934660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934663 */     // MIs[0] blgp
     /*  934663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934666 */     // MIs[0] Operand 7
     /*  934666 */     // No operand predicates
     /*  934666 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934670 */     // MIs[0] Operand 9
     /*  934670 */     // No operand predicates
     /*  934670 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934674 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  934677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934679 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934681 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934683 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934685 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934687 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934689 */     GIR_RootConstrainSelectedInstOperands,
     /*  934690 */     // GIR_Coverage, 3629,
     /*  934690 */     GIR_EraseRootFromParent_Done,
     /*  934691 */   // Label 14950: @934691
     /*  934691 */   GIM_Try, /*On fail goto*//*Label 14951*/ GIMT_Encode4(934757), // Rule ID 3630 //
     /*  934696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  934699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934707 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934710 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934713 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934716 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934719 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934726 */     // MIs[0] cbsz
     /*  934726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934729 */     // MIs[0] blgp
     /*  934729 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934732 */     // MIs[0] Operand 7
     /*  934732 */     // No operand predicates
     /*  934732 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934736 */     // MIs[0] Operand 9
     /*  934736 */     // No operand predicates
     /*  934736 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934740 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  934743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934745 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934747 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934749 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934751 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934753 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934755 */     GIR_RootConstrainSelectedInstOperands,
     /*  934756 */     // GIR_Coverage, 3630,
     /*  934756 */     GIR_EraseRootFromParent_Done,
     /*  934757 */   // Label 14951: @934757
     /*  934757 */   GIM_Try, /*On fail goto*//*Label 14952*/ GIMT_Encode4(934823), // Rule ID 3631 //
     /*  934762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  934765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934773 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934776 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934779 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934782 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934785 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934792 */     // MIs[0] cbsz
     /*  934792 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934795 */     // MIs[0] blgp
     /*  934795 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934798 */     // MIs[0] Operand 7
     /*  934798 */     // No operand predicates
     /*  934798 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934802 */     // MIs[0] Operand 9
     /*  934802 */     // No operand predicates
     /*  934802 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934806 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  934809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934811 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934813 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934815 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934817 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934819 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934821 */     GIR_RootConstrainSelectedInstOperands,
     /*  934822 */     // GIR_Coverage, 3631,
     /*  934822 */     GIR_EraseRootFromParent_Done,
     /*  934823 */   // Label 14952: @934823
     /*  934823 */   GIM_Try, /*On fail goto*//*Label 14953*/ GIMT_Encode4(934889), // Rule ID 3632 //
     /*  934828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  934831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934845 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934848 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934851 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934858 */     // MIs[0] cbsz
     /*  934858 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934861 */     // MIs[0] blgp
     /*  934861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934864 */     // MIs[0] Operand 7
     /*  934864 */     // No operand predicates
     /*  934864 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934868 */     // MIs[0] Operand 9
     /*  934868 */     // No operand predicates
     /*  934868 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934872 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  934875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934877 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934879 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934881 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934883 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934885 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934887 */     GIR_RootConstrainSelectedInstOperands,
     /*  934888 */     // GIR_Coverage, 3632,
     /*  934888 */     GIR_EraseRootFromParent_Done,
     /*  934889 */   // Label 14953: @934889
     /*  934889 */   GIM_Try, /*On fail goto*//*Label 14954*/ GIMT_Encode4(934955), // Rule ID 3633 //
     /*  934894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  934897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  934902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  934905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  934908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  934911 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  934914 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934917 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  934924 */     // MIs[0] cbsz
     /*  934924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934927 */     // MIs[0] blgp
     /*  934927 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934930 */     // MIs[0] Operand 7
     /*  934930 */     // No operand predicates
     /*  934930 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  934934 */     // MIs[0] Operand 9
     /*  934934 */     // No operand predicates
     /*  934934 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  934938 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  934938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  934941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  934943 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  934945 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  934947 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  934949 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  934951 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  934953 */     GIR_RootConstrainSelectedInstOperands,
     /*  934954 */     // GIR_Coverage, 3633,
     /*  934954 */     GIR_EraseRootFromParent_Done,
     /*  934955 */   // Label 14954: @934955
     /*  934955 */   GIM_Try, /*On fail goto*//*Label 14955*/ GIMT_Encode4(935021), // Rule ID 3639 //
     /*  934960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  934963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  934968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  934971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  934974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  934977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  934980 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  934983 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  934986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  934990 */     // MIs[0] cbsz
     /*  934990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  934993 */     // MIs[0] blgp
     /*  934993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  934996 */     // MIs[0] Operand 7
     /*  934996 */     // No operand predicates
     /*  934996 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935000 */     // MIs[0] Operand 9
     /*  935000 */     // No operand predicates
     /*  935000 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935004 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  935007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935009 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935011 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935013 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935015 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935017 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935019 */     GIR_RootConstrainSelectedInstOperands,
     /*  935020 */     // GIR_Coverage, 3639,
     /*  935020 */     GIR_EraseRootFromParent_Done,
     /*  935021 */   // Label 14955: @935021
     /*  935021 */   GIM_Try, /*On fail goto*//*Label 14956*/ GIMT_Encode4(935087), // Rule ID 3640 //
     /*  935026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  935029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935043 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935046 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935049 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935056 */     // MIs[0] cbsz
     /*  935056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935059 */     // MIs[0] blgp
     /*  935059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935062 */     // MIs[0] Operand 7
     /*  935062 */     // No operand predicates
     /*  935062 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935066 */     // MIs[0] Operand 9
     /*  935066 */     // No operand predicates
     /*  935066 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935070 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  935073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935075 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935077 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935079 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935081 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935083 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935085 */     GIR_RootConstrainSelectedInstOperands,
     /*  935086 */     // GIR_Coverage, 3640,
     /*  935086 */     GIR_EraseRootFromParent_Done,
     /*  935087 */   // Label 14956: @935087
     /*  935087 */   GIM_Try, /*On fail goto*//*Label 14957*/ GIMT_Encode4(935153), // Rule ID 3641 //
     /*  935092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  935095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935109 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935112 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935115 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935122 */     // MIs[0] cbsz
     /*  935122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935125 */     // MIs[0] blgp
     /*  935125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935128 */     // MIs[0] Operand 7
     /*  935128 */     // No operand predicates
     /*  935128 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935132 */     // MIs[0] Operand 9
     /*  935132 */     // No operand predicates
     /*  935132 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935136 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  935139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935141 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935143 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935145 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935147 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935149 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935151 */     GIR_RootConstrainSelectedInstOperands,
     /*  935152 */     // GIR_Coverage, 3641,
     /*  935152 */     GIR_EraseRootFromParent_Done,
     /*  935153 */   // Label 14957: @935153
     /*  935153 */   GIM_Try, /*On fail goto*//*Label 14958*/ GIMT_Encode4(935219), // Rule ID 3642 //
     /*  935158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  935161 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935166 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935169 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935172 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935175 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935178 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935181 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935188 */     // MIs[0] cbsz
     /*  935188 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935191 */     // MIs[0] blgp
     /*  935191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935194 */     // MIs[0] Operand 7
     /*  935194 */     // No operand predicates
     /*  935194 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935198 */     // MIs[0] Operand 9
     /*  935198 */     // No operand predicates
     /*  935198 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935202 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  935205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935207 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935209 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935211 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935213 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935215 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935217 */     GIR_RootConstrainSelectedInstOperands,
     /*  935218 */     // GIR_Coverage, 3642,
     /*  935218 */     GIR_EraseRootFromParent_Done,
     /*  935219 */   // Label 14958: @935219
     /*  935219 */   GIM_Try, /*On fail goto*//*Label 14959*/ GIMT_Encode4(935285), // Rule ID 3643 //
     /*  935224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  935227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935241 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935244 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935247 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935254 */     // MIs[0] cbsz
     /*  935254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935257 */     // MIs[0] blgp
     /*  935257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935260 */     // MIs[0] Operand 7
     /*  935260 */     // No operand predicates
     /*  935260 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935264 */     // MIs[0] Operand 9
     /*  935264 */     // No operand predicates
     /*  935264 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935268 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  935271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935273 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935275 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935277 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935279 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935281 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935283 */     GIR_RootConstrainSelectedInstOperands,
     /*  935284 */     // GIR_Coverage, 3643,
     /*  935284 */     GIR_EraseRootFromParent_Done,
     /*  935285 */   // Label 14959: @935285
     /*  935285 */   GIM_Try, /*On fail goto*//*Label 14960*/ GIMT_Encode4(935351), // Rule ID 3649 //
     /*  935290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  935293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  935307 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935310 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935313 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935320 */     // MIs[0] cbsz
     /*  935320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935323 */     // MIs[0] blgp
     /*  935323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935326 */     // MIs[0] Operand 7
     /*  935326 */     // No operand predicates
     /*  935326 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935330 */     // MIs[0] Operand 9
     /*  935330 */     // No operand predicates
     /*  935330 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935334 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  935337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935339 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935341 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935343 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935345 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935347 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935349 */     GIR_RootConstrainSelectedInstOperands,
     /*  935350 */     // GIR_Coverage, 3649,
     /*  935350 */     GIR_EraseRootFromParent_Done,
     /*  935351 */   // Label 14960: @935351
     /*  935351 */   GIM_Try, /*On fail goto*//*Label 14961*/ GIMT_Encode4(935417), // Rule ID 3650 //
     /*  935356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  935359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  935373 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935376 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935379 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935386 */     // MIs[0] cbsz
     /*  935386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935389 */     // MIs[0] blgp
     /*  935389 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935392 */     // MIs[0] Operand 7
     /*  935392 */     // No operand predicates
     /*  935392 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935396 */     // MIs[0] Operand 9
     /*  935396 */     // No operand predicates
     /*  935396 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935400 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  935403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935405 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935407 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935409 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935411 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935413 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935415 */     GIR_RootConstrainSelectedInstOperands,
     /*  935416 */     // GIR_Coverage, 3650,
     /*  935416 */     GIR_EraseRootFromParent_Done,
     /*  935417 */   // Label 14961: @935417
     /*  935417 */   GIM_Try, /*On fail goto*//*Label 14962*/ GIMT_Encode4(935483), // Rule ID 3651 //
     /*  935422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  935425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935436 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  935439 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935442 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935445 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935452 */     // MIs[0] cbsz
     /*  935452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935455 */     // MIs[0] blgp
     /*  935455 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935458 */     // MIs[0] Operand 7
     /*  935458 */     // No operand predicates
     /*  935458 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935462 */     // MIs[0] Operand 9
     /*  935462 */     // No operand predicates
     /*  935462 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935466 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  935469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935471 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935473 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935475 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935477 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935479 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935481 */     GIR_RootConstrainSelectedInstOperands,
     /*  935482 */     // GIR_Coverage, 3651,
     /*  935482 */     GIR_EraseRootFromParent_Done,
     /*  935483 */   // Label 14962: @935483
     /*  935483 */   GIM_Try, /*On fail goto*//*Label 14963*/ GIMT_Encode4(935549), // Rule ID 3652 //
     /*  935488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  935491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935499 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  935505 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935508 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935511 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935518 */     // MIs[0] cbsz
     /*  935518 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935521 */     // MIs[0] blgp
     /*  935521 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935524 */     // MIs[0] Operand 7
     /*  935524 */     // No operand predicates
     /*  935524 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935528 */     // MIs[0] Operand 9
     /*  935528 */     // No operand predicates
     /*  935528 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935532 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  935535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935537 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935539 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935541 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935543 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935545 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935547 */     GIR_RootConstrainSelectedInstOperands,
     /*  935548 */     // GIR_Coverage, 3652,
     /*  935548 */     GIR_EraseRootFromParent_Done,
     /*  935549 */   // Label 14963: @935549
     /*  935549 */   GIM_Try, /*On fail goto*//*Label 14964*/ GIMT_Encode4(935615), // Rule ID 3653 //
     /*  935554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  935557 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935562 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935565 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  935568 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  935571 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935574 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935577 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935584 */     // MIs[0] cbsz
     /*  935584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935587 */     // MIs[0] blgp
     /*  935587 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935590 */     // MIs[0] Operand 7
     /*  935590 */     // No operand predicates
     /*  935590 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935594 */     // MIs[0] Operand 9
     /*  935594 */     // No operand predicates
     /*  935594 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935598 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  935601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935603 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935605 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935607 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935609 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935611 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935613 */     GIR_RootConstrainSelectedInstOperands,
     /*  935614 */     // GIR_Coverage, 3653,
     /*  935614 */     GIR_EraseRootFromParent_Done,
     /*  935615 */   // Label 14964: @935615
     /*  935615 */   GIM_Try, /*On fail goto*//*Label 14965*/ GIMT_Encode4(935681), // Rule ID 3659 //
     /*  935620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  935623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  935634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935640 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935643 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935650 */     // MIs[0] cbsz
     /*  935650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935653 */     // MIs[0] blgp
     /*  935653 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935656 */     // MIs[0] Operand 7
     /*  935656 */     // No operand predicates
     /*  935656 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935660 */     // MIs[0] Operand 9
     /*  935660 */     // No operand predicates
     /*  935660 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935664 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  935667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935669 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935671 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935673 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935675 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935677 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935679 */     GIR_RootConstrainSelectedInstOperands,
     /*  935680 */     // GIR_Coverage, 3659,
     /*  935680 */     GIR_EraseRootFromParent_Done,
     /*  935681 */   // Label 14965: @935681
     /*  935681 */   GIM_Try, /*On fail goto*//*Label 14966*/ GIMT_Encode4(935747), // Rule ID 3660 //
     /*  935686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  935689 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935694 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  935700 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935703 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935706 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935709 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935716 */     // MIs[0] cbsz
     /*  935716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935719 */     // MIs[0] blgp
     /*  935719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935722 */     // MIs[0] Operand 7
     /*  935722 */     // No operand predicates
     /*  935722 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935726 */     // MIs[0] Operand 9
     /*  935726 */     // No operand predicates
     /*  935726 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935730 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  935733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935735 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935737 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935739 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935741 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935743 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935745 */     GIR_RootConstrainSelectedInstOperands,
     /*  935746 */     // GIR_Coverage, 3660,
     /*  935746 */     GIR_EraseRootFromParent_Done,
     /*  935747 */   // Label 14966: @935747
     /*  935747 */   GIM_Try, /*On fail goto*//*Label 14967*/ GIMT_Encode4(935813), // Rule ID 3661 //
     /*  935752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  935755 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935760 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935763 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  935766 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935769 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935772 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935775 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935782 */     // MIs[0] cbsz
     /*  935782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935785 */     // MIs[0] blgp
     /*  935785 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935788 */     // MIs[0] Operand 7
     /*  935788 */     // No operand predicates
     /*  935788 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935792 */     // MIs[0] Operand 9
     /*  935792 */     // No operand predicates
     /*  935792 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935796 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  935799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935801 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935803 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935805 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935807 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935809 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935811 */     GIR_RootConstrainSelectedInstOperands,
     /*  935812 */     // GIR_Coverage, 3661,
     /*  935812 */     GIR_EraseRootFromParent_Done,
     /*  935813 */   // Label 14967: @935813
     /*  935813 */   GIM_Try, /*On fail goto*//*Label 14968*/ GIMT_Encode4(935879), // Rule ID 3662 //
     /*  935818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  935821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  935832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935835 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935838 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935841 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935848 */     // MIs[0] cbsz
     /*  935848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935851 */     // MIs[0] blgp
     /*  935851 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935854 */     // MIs[0] Operand 7
     /*  935854 */     // No operand predicates
     /*  935854 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935858 */     // MIs[0] Operand 9
     /*  935858 */     // No operand predicates
     /*  935858 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935862 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  935865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935867 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935869 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935871 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935873 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935875 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935877 */     GIR_RootConstrainSelectedInstOperands,
     /*  935878 */     // GIR_Coverage, 3662,
     /*  935878 */     GIR_EraseRootFromParent_Done,
     /*  935879 */   // Label 14968: @935879
     /*  935879 */   GIM_Try, /*On fail goto*//*Label 14969*/ GIMT_Encode4(935945), // Rule ID 3663 //
     /*  935884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  935887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  935898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  935901 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935904 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935907 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935914 */     // MIs[0] cbsz
     /*  935914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935917 */     // MIs[0] blgp
     /*  935917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935920 */     // MIs[0] Operand 7
     /*  935920 */     // No operand predicates
     /*  935920 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935924 */     // MIs[0] Operand 9
     /*  935924 */     // No operand predicates
     /*  935924 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935928 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  935931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935933 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  935935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  935937 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  935939 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  935941 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  935943 */     GIR_RootConstrainSelectedInstOperands,
     /*  935944 */     // GIR_Coverage, 3663,
     /*  935944 */     GIR_EraseRootFromParent_Done,
     /*  935945 */   // Label 14969: @935945
     /*  935945 */   GIM_Try, /*On fail goto*//*Label 14970*/ GIMT_Encode4(936011), // Rule ID 3669 //
     /*  935950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  935953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  935958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  935961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  935964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  935967 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  935970 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  935973 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  935976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  935980 */     // MIs[0] cbsz
     /*  935980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  935983 */     // MIs[0] blgp
     /*  935983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  935986 */     // MIs[0] Operand 7
     /*  935986 */     // No operand predicates
     /*  935986 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  935990 */     // MIs[0] Operand 9
     /*  935990 */     // No operand predicates
     /*  935990 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  935994 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  935994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  935997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  935999 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936001 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936003 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936005 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936007 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936009 */     GIR_RootConstrainSelectedInstOperands,
     /*  936010 */     // GIR_Coverage, 3669,
     /*  936010 */     GIR_EraseRootFromParent_Done,
     /*  936011 */   // Label 14970: @936011
     /*  936011 */   GIM_Try, /*On fail goto*//*Label 14971*/ GIMT_Encode4(936077), // Rule ID 3670 //
     /*  936016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  936019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  936030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  936033 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936036 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936039 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936046 */     // MIs[0] cbsz
     /*  936046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936049 */     // MIs[0] blgp
     /*  936049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936052 */     // MIs[0] Operand 7
     /*  936052 */     // No operand predicates
     /*  936052 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936056 */     // MIs[0] Operand 9
     /*  936056 */     // No operand predicates
     /*  936056 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936060 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  936063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936065 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936067 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936069 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936071 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936073 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936075 */     GIR_RootConstrainSelectedInstOperands,
     /*  936076 */     // GIR_Coverage, 3670,
     /*  936076 */     GIR_EraseRootFromParent_Done,
     /*  936077 */   // Label 14971: @936077
     /*  936077 */   GIM_Try, /*On fail goto*//*Label 14972*/ GIMT_Encode4(936143), // Rule ID 3671 //
     /*  936082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  936085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  936096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  936099 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936102 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936105 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936112 */     // MIs[0] cbsz
     /*  936112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936115 */     // MIs[0] blgp
     /*  936115 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936118 */     // MIs[0] Operand 7
     /*  936118 */     // No operand predicates
     /*  936118 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936122 */     // MIs[0] Operand 9
     /*  936122 */     // No operand predicates
     /*  936122 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936126 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  936129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936131 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936133 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936135 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936137 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936139 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936141 */     GIR_RootConstrainSelectedInstOperands,
     /*  936142 */     // GIR_Coverage, 3671,
     /*  936142 */     GIR_EraseRootFromParent_Done,
     /*  936143 */   // Label 14972: @936143
     /*  936143 */   GIM_Try, /*On fail goto*//*Label 14973*/ GIMT_Encode4(936209), // Rule ID 3672 //
     /*  936148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  936151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  936162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  936165 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936168 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936171 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936178 */     // MIs[0] cbsz
     /*  936178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936181 */     // MIs[0] blgp
     /*  936181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936184 */     // MIs[0] Operand 7
     /*  936184 */     // No operand predicates
     /*  936184 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936188 */     // MIs[0] Operand 9
     /*  936188 */     // No operand predicates
     /*  936188 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936192 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  936195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936197 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936199 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936201 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936203 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936205 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936207 */     GIR_RootConstrainSelectedInstOperands,
     /*  936208 */     // GIR_Coverage, 3672,
     /*  936208 */     GIR_EraseRootFromParent_Done,
     /*  936209 */   // Label 14973: @936209
     /*  936209 */   GIM_Try, /*On fail goto*//*Label 14974*/ GIMT_Encode4(936275), // Rule ID 3673 //
     /*  936214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  936217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936225 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  936228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  936231 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936234 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936237 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936244 */     // MIs[0] cbsz
     /*  936244 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936247 */     // MIs[0] blgp
     /*  936247 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936250 */     // MIs[0] Operand 7
     /*  936250 */     // No operand predicates
     /*  936250 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936254 */     // MIs[0] Operand 9
     /*  936254 */     // No operand predicates
     /*  936254 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936258 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  936261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936263 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936265 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936267 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936269 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936271 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936273 */     GIR_RootConstrainSelectedInstOperands,
     /*  936274 */     // GIR_Coverage, 3673,
     /*  936274 */     GIR_EraseRootFromParent_Done,
     /*  936275 */   // Label 14974: @936275
     /*  936275 */   GIM_Try, /*On fail goto*//*Label 14975*/ GIMT_Encode4(936341), // Rule ID 3679 //
     /*  936280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  936283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  936294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  936297 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936300 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936303 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936310 */     // MIs[0] cbsz
     /*  936310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936313 */     // MIs[0] blgp
     /*  936313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936316 */     // MIs[0] Operand 7
     /*  936316 */     // No operand predicates
     /*  936316 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936320 */     // MIs[0] Operand 9
     /*  936320 */     // No operand predicates
     /*  936320 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936324 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  936327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936329 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936331 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936333 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936335 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936337 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936339 */     GIR_RootConstrainSelectedInstOperands,
     /*  936340 */     // GIR_Coverage, 3679,
     /*  936340 */     GIR_EraseRootFromParent_Done,
     /*  936341 */   // Label 14975: @936341
     /*  936341 */   GIM_Try, /*On fail goto*//*Label 14976*/ GIMT_Encode4(936407), // Rule ID 3680 //
     /*  936346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  936349 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936354 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936357 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  936360 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  936363 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936366 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936369 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936376 */     // MIs[0] cbsz
     /*  936376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936379 */     // MIs[0] blgp
     /*  936379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936382 */     // MIs[0] Operand 7
     /*  936382 */     // No operand predicates
     /*  936382 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936386 */     // MIs[0] Operand 9
     /*  936386 */     // No operand predicates
     /*  936386 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936390 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  936393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936395 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936397 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936399 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936401 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936403 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936405 */     GIR_RootConstrainSelectedInstOperands,
     /*  936406 */     // GIR_Coverage, 3680,
     /*  936406 */     GIR_EraseRootFromParent_Done,
     /*  936407 */   // Label 14976: @936407
     /*  936407 */   GIM_Try, /*On fail goto*//*Label 14977*/ GIMT_Encode4(936473), // Rule ID 3681 //
     /*  936412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  936415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  936426 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  936429 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936432 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936435 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936442 */     // MIs[0] cbsz
     /*  936442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936445 */     // MIs[0] blgp
     /*  936445 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936448 */     // MIs[0] Operand 7
     /*  936448 */     // No operand predicates
     /*  936448 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936452 */     // MIs[0] Operand 9
     /*  936452 */     // No operand predicates
     /*  936452 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936456 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  936459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936461 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936463 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936465 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936467 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936469 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936471 */     GIR_RootConstrainSelectedInstOperands,
     /*  936472 */     // GIR_Coverage, 3681,
     /*  936472 */     GIR_EraseRootFromParent_Done,
     /*  936473 */   // Label 14977: @936473
     /*  936473 */   GIM_Try, /*On fail goto*//*Label 14978*/ GIMT_Encode4(936539), // Rule ID 3682 //
     /*  936478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  936481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  936492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  936495 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936498 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936501 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936508 */     // MIs[0] cbsz
     /*  936508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936511 */     // MIs[0] blgp
     /*  936511 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936514 */     // MIs[0] Operand 7
     /*  936514 */     // No operand predicates
     /*  936514 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936518 */     // MIs[0] Operand 9
     /*  936518 */     // No operand predicates
     /*  936518 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936522 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  936525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936527 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936529 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936531 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936533 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936535 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936537 */     GIR_RootConstrainSelectedInstOperands,
     /*  936538 */     // GIR_Coverage, 3682,
     /*  936538 */     GIR_EraseRootFromParent_Done,
     /*  936539 */   // Label 14978: @936539
     /*  936539 */   GIM_Try, /*On fail goto*//*Label 14979*/ GIMT_Encode4(936605), // Rule ID 3683 //
     /*  936544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  936547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  936558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  936561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936564 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936567 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936574 */     // MIs[0] cbsz
     /*  936574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936577 */     // MIs[0] blgp
     /*  936577 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936580 */     // MIs[0] Operand 7
     /*  936580 */     // No operand predicates
     /*  936580 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936584 */     // MIs[0] Operand 9
     /*  936584 */     // No operand predicates
     /*  936584 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936588 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  936591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936593 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936595 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936597 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936599 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936601 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936603 */     GIR_RootConstrainSelectedInstOperands,
     /*  936604 */     // GIR_Coverage, 3683,
     /*  936604 */     GIR_EraseRootFromParent_Done,
     /*  936605 */   // Label 14979: @936605
     /*  936605 */   GIM_Try, /*On fail goto*//*Label 14980*/ GIMT_Encode4(936671), // Rule ID 3689 //
     /*  936610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  936613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  936624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  936627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936630 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936633 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936640 */     // MIs[0] cbsz
     /*  936640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936643 */     // MIs[0] blgp
     /*  936643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936646 */     // MIs[0] Operand 7
     /*  936646 */     // No operand predicates
     /*  936646 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936650 */     // MIs[0] Operand 9
     /*  936650 */     // No operand predicates
     /*  936650 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936654 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  936657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936659 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936661 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936663 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936665 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936667 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936669 */     GIR_RootConstrainSelectedInstOperands,
     /*  936670 */     // GIR_Coverage, 3689,
     /*  936670 */     GIR_EraseRootFromParent_Done,
     /*  936671 */   // Label 14980: @936671
     /*  936671 */   GIM_Try, /*On fail goto*//*Label 14981*/ GIMT_Encode4(936737), // Rule ID 3690 //
     /*  936676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  936679 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936684 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936687 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  936690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  936693 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936696 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936699 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936706 */     // MIs[0] cbsz
     /*  936706 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936709 */     // MIs[0] blgp
     /*  936709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936712 */     // MIs[0] Operand 7
     /*  936712 */     // No operand predicates
     /*  936712 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936716 */     // MIs[0] Operand 9
     /*  936716 */     // No operand predicates
     /*  936716 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936720 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  936723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936725 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936727 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936729 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936731 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936733 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936735 */     GIR_RootConstrainSelectedInstOperands,
     /*  936736 */     // GIR_Coverage, 3690,
     /*  936736 */     GIR_EraseRootFromParent_Done,
     /*  936737 */   // Label 14981: @936737
     /*  936737 */   GIM_Try, /*On fail goto*//*Label 14982*/ GIMT_Encode4(936803), // Rule ID 3691 //
     /*  936742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  936745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  936756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  936759 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936762 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936765 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936772 */     // MIs[0] cbsz
     /*  936772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936775 */     // MIs[0] blgp
     /*  936775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936778 */     // MIs[0] Operand 7
     /*  936778 */     // No operand predicates
     /*  936778 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936782 */     // MIs[0] Operand 9
     /*  936782 */     // No operand predicates
     /*  936782 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936786 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  936789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936791 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936793 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936795 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936797 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936799 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936801 */     GIR_RootConstrainSelectedInstOperands,
     /*  936802 */     // GIR_Coverage, 3691,
     /*  936802 */     GIR_EraseRootFromParent_Done,
     /*  936803 */   // Label 14982: @936803
     /*  936803 */   GIM_Try, /*On fail goto*//*Label 14983*/ GIMT_Encode4(936869), // Rule ID 3692 //
     /*  936808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  936811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  936822 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  936825 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936828 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936831 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936838 */     // MIs[0] cbsz
     /*  936838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936841 */     // MIs[0] blgp
     /*  936841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936844 */     // MIs[0] Operand 7
     /*  936844 */     // No operand predicates
     /*  936844 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936848 */     // MIs[0] Operand 9
     /*  936848 */     // No operand predicates
     /*  936848 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936852 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  936855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936857 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936859 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936861 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936863 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936865 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936867 */     GIR_RootConstrainSelectedInstOperands,
     /*  936868 */     // GIR_Coverage, 3692,
     /*  936868 */     GIR_EraseRootFromParent_Done,
     /*  936869 */   // Label 14983: @936869
     /*  936869 */   GIM_Try, /*On fail goto*//*Label 14984*/ GIMT_Encode4(936935), // Rule ID 3693 //
     /*  936874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  936877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  936888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  936891 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936894 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936897 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936904 */     // MIs[0] cbsz
     /*  936904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936907 */     // MIs[0] blgp
     /*  936907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936910 */     // MIs[0] Operand 7
     /*  936910 */     // No operand predicates
     /*  936910 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936914 */     // MIs[0] Operand 9
     /*  936914 */     // No operand predicates
     /*  936914 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936918 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  936921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936923 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936925 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936927 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936929 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936931 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936933 */     GIR_RootConstrainSelectedInstOperands,
     /*  936934 */     // GIR_Coverage, 3693,
     /*  936934 */     GIR_EraseRootFromParent_Done,
     /*  936935 */   // Label 14984: @936935
     /*  936935 */   GIM_Try, /*On fail goto*//*Label 14985*/ GIMT_Encode4(937001), // Rule ID 3699 //
     /*  936940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  936943 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  936948 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  936951 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  936954 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  936957 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  936960 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  936963 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  936966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  936970 */     // MIs[0] cbsz
     /*  936970 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  936973 */     // MIs[0] blgp
     /*  936973 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  936976 */     // MIs[0] Operand 7
     /*  936976 */     // No operand predicates
     /*  936976 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  936980 */     // MIs[0] Operand 9
     /*  936980 */     // No operand predicates
     /*  936980 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  936984 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  936984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  936987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  936989 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  936991 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  936993 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  936995 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  936997 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  936999 */     GIR_RootConstrainSelectedInstOperands,
     /*  937000 */     // GIR_Coverage, 3699,
     /*  937000 */     GIR_EraseRootFromParent_Done,
     /*  937001 */   // Label 14985: @937001
     /*  937001 */   GIM_Try, /*On fail goto*//*Label 14986*/ GIMT_Encode4(937067), // Rule ID 3700 //
     /*  937006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  937009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  937020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937023 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937026 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937029 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937036 */     // MIs[0] cbsz
     /*  937036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937039 */     // MIs[0] blgp
     /*  937039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937042 */     // MIs[0] Operand 7
     /*  937042 */     // No operand predicates
     /*  937042 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937046 */     // MIs[0] Operand 9
     /*  937046 */     // No operand predicates
     /*  937046 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937050 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  937053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937055 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937057 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937059 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937061 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937063 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937065 */     GIR_RootConstrainSelectedInstOperands,
     /*  937066 */     // GIR_Coverage, 3700,
     /*  937066 */     GIR_EraseRootFromParent_Done,
     /*  937067 */   // Label 14986: @937067
     /*  937067 */   GIM_Try, /*On fail goto*//*Label 14987*/ GIMT_Encode4(937133), // Rule ID 3701 //
     /*  937072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  937075 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937080 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937083 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  937086 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937089 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937092 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937095 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937102 */     // MIs[0] cbsz
     /*  937102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937105 */     // MIs[0] blgp
     /*  937105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937108 */     // MIs[0] Operand 7
     /*  937108 */     // No operand predicates
     /*  937108 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937112 */     // MIs[0] Operand 9
     /*  937112 */     // No operand predicates
     /*  937112 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937116 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  937119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937121 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937123 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937125 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937127 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937129 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937131 */     GIR_RootConstrainSelectedInstOperands,
     /*  937132 */     // GIR_Coverage, 3701,
     /*  937132 */     GIR_EraseRootFromParent_Done,
     /*  937133 */   // Label 14987: @937133
     /*  937133 */   GIM_Try, /*On fail goto*//*Label 14988*/ GIMT_Encode4(937199), // Rule ID 3702 //
     /*  937138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  937141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  937152 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937155 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937158 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937161 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937168 */     // MIs[0] cbsz
     /*  937168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937171 */     // MIs[0] blgp
     /*  937171 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937174 */     // MIs[0] Operand 7
     /*  937174 */     // No operand predicates
     /*  937174 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937178 */     // MIs[0] Operand 9
     /*  937178 */     // No operand predicates
     /*  937178 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937182 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  937185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937187 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937189 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937191 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937193 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937195 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937197 */     GIR_RootConstrainSelectedInstOperands,
     /*  937198 */     // GIR_Coverage, 3702,
     /*  937198 */     GIR_EraseRootFromParent_Done,
     /*  937199 */   // Label 14988: @937199
     /*  937199 */   GIM_Try, /*On fail goto*//*Label 14989*/ GIMT_Encode4(937265), // Rule ID 3703 //
     /*  937204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  937207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  937218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937221 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937224 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937227 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937234 */     // MIs[0] cbsz
     /*  937234 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937237 */     // MIs[0] blgp
     /*  937237 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937240 */     // MIs[0] Operand 7
     /*  937240 */     // No operand predicates
     /*  937240 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937244 */     // MIs[0] Operand 9
     /*  937244 */     // No operand predicates
     /*  937244 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937248 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  937251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937253 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937255 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937257 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937259 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937261 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937263 */     GIR_RootConstrainSelectedInstOperands,
     /*  937264 */     // GIR_Coverage, 3703,
     /*  937264 */     GIR_EraseRootFromParent_Done,
     /*  937265 */   // Label 14989: @937265
     /*  937265 */   GIM_Try, /*On fail goto*//*Label 14990*/ GIMT_Encode4(937331), // Rule ID 3709 //
     /*  937270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  937273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  937287 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937290 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937293 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937300 */     // MIs[0] cbsz
     /*  937300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937303 */     // MIs[0] blgp
     /*  937303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937306 */     // MIs[0] Operand 7
     /*  937306 */     // No operand predicates
     /*  937306 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937310 */     // MIs[0] Operand 9
     /*  937310 */     // No operand predicates
     /*  937310 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937314 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  937317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937319 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937321 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937323 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937325 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937327 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937329 */     GIR_RootConstrainSelectedInstOperands,
     /*  937330 */     // GIR_Coverage, 3709,
     /*  937330 */     GIR_EraseRootFromParent_Done,
     /*  937331 */   // Label 14990: @937331
     /*  937331 */   GIM_Try, /*On fail goto*//*Label 14991*/ GIMT_Encode4(937397), // Rule ID 3710 //
     /*  937336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  937339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  937353 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937356 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937359 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937366 */     // MIs[0] cbsz
     /*  937366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937369 */     // MIs[0] blgp
     /*  937369 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937372 */     // MIs[0] Operand 7
     /*  937372 */     // No operand predicates
     /*  937372 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937376 */     // MIs[0] Operand 9
     /*  937376 */     // No operand predicates
     /*  937376 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937380 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  937383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937385 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937387 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937389 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937391 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937393 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937395 */     GIR_RootConstrainSelectedInstOperands,
     /*  937396 */     // GIR_Coverage, 3710,
     /*  937396 */     GIR_EraseRootFromParent_Done,
     /*  937397 */   // Label 14991: @937397
     /*  937397 */   GIM_Try, /*On fail goto*//*Label 14992*/ GIMT_Encode4(937463), // Rule ID 3711 //
     /*  937402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  937405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  937419 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937422 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937425 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937432 */     // MIs[0] cbsz
     /*  937432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937435 */     // MIs[0] blgp
     /*  937435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937438 */     // MIs[0] Operand 7
     /*  937438 */     // No operand predicates
     /*  937438 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937442 */     // MIs[0] Operand 9
     /*  937442 */     // No operand predicates
     /*  937442 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937446 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  937449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937451 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937453 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937455 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937457 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937459 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937461 */     GIR_RootConstrainSelectedInstOperands,
     /*  937462 */     // GIR_Coverage, 3711,
     /*  937462 */     GIR_EraseRootFromParent_Done,
     /*  937463 */   // Label 14992: @937463
     /*  937463 */   GIM_Try, /*On fail goto*//*Label 14993*/ GIMT_Encode4(937529), // Rule ID 3712 //
     /*  937468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  937471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  937485 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937488 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937491 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937498 */     // MIs[0] cbsz
     /*  937498 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937501 */     // MIs[0] blgp
     /*  937501 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937504 */     // MIs[0] Operand 7
     /*  937504 */     // No operand predicates
     /*  937504 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937508 */     // MIs[0] Operand 9
     /*  937508 */     // No operand predicates
     /*  937508 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937512 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  937515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937517 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937519 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937521 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937523 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937525 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937527 */     GIR_RootConstrainSelectedInstOperands,
     /*  937528 */     // GIR_Coverage, 3712,
     /*  937528 */     GIR_EraseRootFromParent_Done,
     /*  937529 */   // Label 14993: @937529
     /*  937529 */   GIM_Try, /*On fail goto*//*Label 14994*/ GIMT_Encode4(937595), // Rule ID 3713 //
     /*  937534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  937537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937542 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  937551 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937554 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937557 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937564 */     // MIs[0] cbsz
     /*  937564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937567 */     // MIs[0] blgp
     /*  937567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937570 */     // MIs[0] Operand 7
     /*  937570 */     // No operand predicates
     /*  937570 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937574 */     // MIs[0] Operand 9
     /*  937574 */     // No operand predicates
     /*  937574 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937578 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  937581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937583 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937585 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937587 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937589 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937591 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937593 */     GIR_RootConstrainSelectedInstOperands,
     /*  937594 */     // GIR_Coverage, 3713,
     /*  937594 */     GIR_EraseRootFromParent_Done,
     /*  937595 */   // Label 14994: @937595
     /*  937595 */   GIM_Try, /*On fail goto*//*Label 14995*/ GIMT_Encode4(937661), // Rule ID 3719 //
     /*  937600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode0),
     /*  937603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937620 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937623 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937630 */     // MIs[0] cbsz
     /*  937630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937633 */     // MIs[0] blgp
     /*  937633 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937636 */     // MIs[0] Operand 7
     /*  937636 */     // No operand predicates
     /*  937636 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937640 */     // MIs[0] Operand 9
     /*  937640 */     // No operand predicates
     /*  937640 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937644 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  937647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937649 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937651 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937653 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937655 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937657 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937659 */     GIR_RootConstrainSelectedInstOperands,
     /*  937660 */     // GIR_Coverage, 3719,
     /*  937660 */     GIR_EraseRootFromParent_Done,
     /*  937661 */   // Label 14995: @937661
     /*  937661 */   GIM_Try, /*On fail goto*//*Label 14996*/ GIMT_Encode4(937727), // Rule ID 3720 //
     /*  937666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode1),
     /*  937669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937683 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937686 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937689 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937696 */     // MIs[0] cbsz
     /*  937696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937699 */     // MIs[0] blgp
     /*  937699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937702 */     // MIs[0] Operand 7
     /*  937702 */     // No operand predicates
     /*  937702 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937706 */     // MIs[0] Operand 9
     /*  937706 */     // No operand predicates
     /*  937706 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937710 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  937713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937715 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937717 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937719 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937721 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937723 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937725 */     GIR_RootConstrainSelectedInstOperands,
     /*  937726 */     // GIR_Coverage, 3720,
     /*  937726 */     GIR_EraseRootFromParent_Done,
     /*  937727 */   // Label 14996: @937727
     /*  937727 */   GIM_Try, /*On fail goto*//*Label 14997*/ GIMT_Encode4(937793), // Rule ID 3721 //
     /*  937732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode2),
     /*  937735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937749 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937752 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937755 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937762 */     // MIs[0] cbsz
     /*  937762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937765 */     // MIs[0] blgp
     /*  937765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937768 */     // MIs[0] Operand 7
     /*  937768 */     // No operand predicates
     /*  937768 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937772 */     // MIs[0] Operand 9
     /*  937772 */     // No operand predicates
     /*  937772 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937776 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  937779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937781 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937783 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937785 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937787 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937789 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937791 */     GIR_RootConstrainSelectedInstOperands,
     /*  937792 */     // GIR_Coverage, 3721,
     /*  937792 */     GIR_EraseRootFromParent_Done,
     /*  937793 */   // Label 14997: @937793
     /*  937793 */   GIM_Try, /*On fail goto*//*Label 14998*/ GIMT_Encode4(937859), // Rule ID 3722 //
     /*  937798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode3),
     /*  937801 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937806 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937809 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937812 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937815 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937818 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937821 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937828 */     // MIs[0] cbsz
     /*  937828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937831 */     // MIs[0] blgp
     /*  937831 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937834 */     // MIs[0] Operand 7
     /*  937834 */     // No operand predicates
     /*  937834 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937838 */     // MIs[0] Operand 9
     /*  937838 */     // No operand predicates
     /*  937838 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937842 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  937845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937847 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937849 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937851 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937853 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937855 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937857 */     GIR_RootConstrainSelectedInstOperands,
     /*  937858 */     // GIR_Coverage, 3722,
     /*  937858 */     GIR_EraseRootFromParent_Done,
     /*  937859 */   // Label 14998: @937859
     /*  937859 */   GIM_Try, /*On fail goto*//*Label 14999*/ GIMT_Encode4(937925), // Rule ID 3723 //
     /*  937864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_isGFX90APlus_HwMode4),
     /*  937867 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  937872 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  937875 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  937878 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  937881 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  937884 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937887 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  937894 */     // MIs[0] cbsz
     /*  937894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937897 */     // MIs[0] blgp
     /*  937897 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937900 */     // MIs[0] Operand 7
     /*  937900 */     // No operand predicates
     /*  937900 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
     /*  937904 */     // MIs[0] Operand 9
     /*  937904 */     // No operand predicates
     /*  937904 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/10, 0,
     /*  937908 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, srcvalue:{ *:[i32] }, 0:{ *:[i32] }, srcvalue:{ *:[i32] }, 0:{ *:[i32] })  =>  (V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp)
     /*  937908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  937911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937913 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937915 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937917 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937919 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937921 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  937923 */     GIR_RootConstrainSelectedInstOperands,
     /*  937924 */     // GIR_Coverage, 3723,
     /*  937924 */     GIR_EraseRootFromParent_Done,
     /*  937925 */   // Label 14999: @937925
     /*  937925 */   GIM_Try, /*On fail goto*//*Label 15000*/ GIMT_Encode4(938019), // Rule ID 3724 //
     /*  937930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  937933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  937938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  937941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  937944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  937947 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  937950 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  937953 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  937956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  937960 */     // MIs[0] cbsz
     /*  937960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  937963 */     // MIs[0] blgp
     /*  937963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  937966 */     // MIs[0] src0_modifiers
     /*  937966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  937969 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  937974 */     // MIs[0] src1_modifiers
     /*  937974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  937977 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  937982 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  937986 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  937986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  937989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  937991 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  937993 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  937995 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  937997 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  937999 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938001 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938003 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938005 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938011 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938017 */     GIR_RootConstrainSelectedInstOperands,
     /*  938018 */     // GIR_Coverage, 3724,
     /*  938018 */     GIR_EraseRootFromParent_Done,
     /*  938019 */   // Label 15000: @938019
     /*  938019 */   GIM_Try, /*On fail goto*//*Label 15001*/ GIMT_Encode4(938113), // Rule ID 3725 //
     /*  938024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  938027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  938041 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938044 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938047 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938054 */     // MIs[0] cbsz
     /*  938054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938057 */     // MIs[0] blgp
     /*  938057 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938060 */     // MIs[0] src0_modifiers
     /*  938060 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938063 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938068 */     // MIs[0] src1_modifiers
     /*  938068 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938071 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938076 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938080 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  938083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938085 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938087 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938089 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938091 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938093 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938095 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938097 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938099 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938105 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938111 */     GIR_RootConstrainSelectedInstOperands,
     /*  938112 */     // GIR_Coverage, 3725,
     /*  938112 */     GIR_EraseRootFromParent_Done,
     /*  938113 */   // Label 15001: @938113
     /*  938113 */   GIM_Try, /*On fail goto*//*Label 15002*/ GIMT_Encode4(938207), // Rule ID 3726 //
     /*  938118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  938121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  938135 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938138 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938141 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938148 */     // MIs[0] cbsz
     /*  938148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938151 */     // MIs[0] blgp
     /*  938151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938154 */     // MIs[0] src0_modifiers
     /*  938154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938157 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938162 */     // MIs[0] src1_modifiers
     /*  938162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938165 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938170 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938174 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  938177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938179 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938181 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938183 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938185 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938187 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938189 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938191 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938193 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938199 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938205 */     GIR_RootConstrainSelectedInstOperands,
     /*  938206 */     // GIR_Coverage, 3726,
     /*  938206 */     GIR_EraseRootFromParent_Done,
     /*  938207 */   // Label 15002: @938207
     /*  938207 */   GIM_Try, /*On fail goto*//*Label 15003*/ GIMT_Encode4(938301), // Rule ID 3727 //
     /*  938212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  938215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  938229 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938232 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938235 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938242 */     // MIs[0] cbsz
     /*  938242 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938245 */     // MIs[0] blgp
     /*  938245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938248 */     // MIs[0] src0_modifiers
     /*  938248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938251 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938256 */     // MIs[0] src1_modifiers
     /*  938256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938259 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938264 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938268 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  938271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938273 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938275 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938277 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938279 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938281 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938283 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938285 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938287 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938293 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938299 */     GIR_RootConstrainSelectedInstOperands,
     /*  938300 */     // GIR_Coverage, 3727,
     /*  938300 */     GIR_EraseRootFromParent_Done,
     /*  938301 */   // Label 15003: @938301
     /*  938301 */   GIM_Try, /*On fail goto*//*Label 15004*/ GIMT_Encode4(938395), // Rule ID 3728 //
     /*  938306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  938309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938320 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  938323 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938326 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938329 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938336 */     // MIs[0] cbsz
     /*  938336 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938339 */     // MIs[0] blgp
     /*  938339 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938342 */     // MIs[0] src0_modifiers
     /*  938342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938345 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938350 */     // MIs[0] src1_modifiers
     /*  938350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938353 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938358 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938362 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64),
     /*  938365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938367 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938369 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938371 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938373 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938375 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938377 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938379 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938381 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938387 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938393 */     GIR_RootConstrainSelectedInstOperands,
     /*  938394 */     // GIR_Coverage, 3728,
     /*  938394 */     GIR_EraseRootFromParent_Done,
     /*  938395 */   // Label 15004: @938395
     /*  938395 */   GIM_Try, /*On fail goto*//*Label 15005*/ GIMT_Encode4(938489), // Rule ID 3734 //
     /*  938400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  938403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  938417 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938420 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938423 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938430 */     // MIs[0] cbsz
     /*  938430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938433 */     // MIs[0] blgp
     /*  938433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938436 */     // MIs[0] src0_modifiers
     /*  938436 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938439 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938444 */     // MIs[0] src1_modifiers
     /*  938444 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938447 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938452 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938456 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  938459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938461 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938463 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938465 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938467 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938469 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938471 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938473 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938475 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938481 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938487 */     GIR_RootConstrainSelectedInstOperands,
     /*  938488 */     // GIR_Coverage, 3734,
     /*  938488 */     GIR_EraseRootFromParent_Done,
     /*  938489 */   // Label 15005: @938489
     /*  938489 */   GIM_Try, /*On fail goto*//*Label 15006*/ GIMT_Encode4(938583), // Rule ID 3735 //
     /*  938494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  938497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938508 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  938511 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938514 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938517 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938524 */     // MIs[0] cbsz
     /*  938524 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938527 */     // MIs[0] blgp
     /*  938527 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938530 */     // MIs[0] src0_modifiers
     /*  938530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938533 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938538 */     // MIs[0] src1_modifiers
     /*  938538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938541 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938546 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938550 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  938553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938555 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938557 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938559 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938561 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938563 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938565 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938567 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938569 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938575 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938581 */     GIR_RootConstrainSelectedInstOperands,
     /*  938582 */     // GIR_Coverage, 3735,
     /*  938582 */     GIR_EraseRootFromParent_Done,
     /*  938583 */   // Label 15006: @938583
     /*  938583 */   GIM_Try, /*On fail goto*//*Label 15007*/ GIMT_Encode4(938677), // Rule ID 3736 //
     /*  938588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  938591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  938605 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938608 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938611 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938618 */     // MIs[0] cbsz
     /*  938618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938621 */     // MIs[0] blgp
     /*  938621 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938624 */     // MIs[0] src0_modifiers
     /*  938624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938627 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938632 */     // MIs[0] src1_modifiers
     /*  938632 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938635 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938640 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938644 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  938647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938649 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938651 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938653 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938655 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938657 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938659 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938661 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938663 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938669 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938675 */     GIR_RootConstrainSelectedInstOperands,
     /*  938676 */     // GIR_Coverage, 3736,
     /*  938676 */     GIR_EraseRootFromParent_Done,
     /*  938677 */   // Label 15007: @938677
     /*  938677 */   GIM_Try, /*On fail goto*//*Label 15008*/ GIMT_Encode4(938771), // Rule ID 3737 //
     /*  938682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  938685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  938699 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938702 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938705 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938712 */     // MIs[0] cbsz
     /*  938712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938715 */     // MIs[0] blgp
     /*  938715 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938718 */     // MIs[0] src0_modifiers
     /*  938718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938721 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938726 */     // MIs[0] src1_modifiers
     /*  938726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938729 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938734 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938738 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  938741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938743 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938745 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938747 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938749 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938751 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938753 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938755 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938757 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938763 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938769 */     GIR_RootConstrainSelectedInstOperands,
     /*  938770 */     // GIR_Coverage, 3737,
     /*  938770 */     GIR_EraseRootFromParent_Done,
     /*  938771 */   // Label 15008: @938771
     /*  938771 */   GIM_Try, /*On fail goto*//*Label 15009*/ GIMT_Encode4(938865), // Rule ID 3738 //
     /*  938776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  938779 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938784 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  938790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  938793 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938796 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938799 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938806 */     // MIs[0] cbsz
     /*  938806 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938809 */     // MIs[0] blgp
     /*  938809 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938812 */     // MIs[0] src0_modifiers
     /*  938812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938815 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938820 */     // MIs[0] src1_modifiers
     /*  938820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938823 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938828 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938832 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64),
     /*  938835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938837 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938839 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938841 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938843 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938845 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938847 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938849 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938851 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938857 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938863 */     GIR_RootConstrainSelectedInstOperands,
     /*  938864 */     // GIR_Coverage, 3738,
     /*  938864 */     GIR_EraseRootFromParent_Done,
     /*  938865 */   // Label 15009: @938865
     /*  938865 */   GIM_Try, /*On fail goto*//*Label 15010*/ GIMT_Encode4(938959), // Rule ID 3744 //
     /*  938870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  938873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  938884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  938887 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938890 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938893 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938900 */     // MIs[0] cbsz
     /*  938900 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938903 */     // MIs[0] blgp
     /*  938903 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  938906 */     // MIs[0] src0_modifiers
     /*  938906 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  938909 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938914 */     // MIs[0] src1_modifiers
     /*  938914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  938917 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  938922 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  938926 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  938926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  938929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  938931 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  938933 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  938935 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  938937 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  938939 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  938941 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  938943 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  938945 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  938951 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  938957 */     GIR_RootConstrainSelectedInstOperands,
     /*  938958 */     // GIR_Coverage, 3744,
     /*  938958 */     GIR_EraseRootFromParent_Done,
     /*  938959 */   // Label 15010: @938959
     /*  938959 */   GIM_Try, /*On fail goto*//*Label 15011*/ GIMT_Encode4(939053), // Rule ID 3745 //
     /*  938964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  938967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  938972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  938975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  938978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  938981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  938984 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  938987 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  938990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  938994 */     // MIs[0] cbsz
     /*  938994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  938997 */     // MIs[0] blgp
     /*  938997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939000 */     // MIs[0] src0_modifiers
     /*  939000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939003 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939008 */     // MIs[0] src1_modifiers
     /*  939008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939011 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939016 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939020 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  939023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939025 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939027 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939029 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939031 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939033 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939035 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939037 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939039 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939045 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939051 */     GIR_RootConstrainSelectedInstOperands,
     /*  939052 */     // GIR_Coverage, 3745,
     /*  939052 */     GIR_EraseRootFromParent_Done,
     /*  939053 */   // Label 15011: @939053
     /*  939053 */   GIM_Try, /*On fail goto*//*Label 15012*/ GIMT_Encode4(939147), // Rule ID 3746 //
     /*  939058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  939061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939066 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939069 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939072 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  939075 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939078 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939081 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939088 */     // MIs[0] cbsz
     /*  939088 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939091 */     // MIs[0] blgp
     /*  939091 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939094 */     // MIs[0] src0_modifiers
     /*  939094 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939097 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939102 */     // MIs[0] src1_modifiers
     /*  939102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939105 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939110 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939114 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  939117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939119 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939121 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939123 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939125 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939127 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939129 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939131 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939133 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939139 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939145 */     GIR_RootConstrainSelectedInstOperands,
     /*  939146 */     // GIR_Coverage, 3746,
     /*  939146 */     GIR_EraseRootFromParent_Done,
     /*  939147 */   // Label 15012: @939147
     /*  939147 */   GIM_Try, /*On fail goto*//*Label 15013*/ GIMT_Encode4(939241), // Rule ID 3747 //
     /*  939152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  939155 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939160 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939163 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939166 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  939169 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939172 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939175 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939182 */     // MIs[0] cbsz
     /*  939182 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939185 */     // MIs[0] blgp
     /*  939185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939188 */     // MIs[0] src0_modifiers
     /*  939188 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939191 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939196 */     // MIs[0] src1_modifiers
     /*  939196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939199 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939204 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939208 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  939211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939213 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939215 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939217 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939219 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939221 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939223 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939225 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939227 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939233 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939239 */     GIR_RootConstrainSelectedInstOperands,
     /*  939240 */     // GIR_Coverage, 3747,
     /*  939240 */     GIR_EraseRootFromParent_Done,
     /*  939241 */   // Label 15013: @939241
     /*  939241 */   GIM_Try, /*On fail goto*//*Label 15014*/ GIMT_Encode4(939335), // Rule ID 3748 //
     /*  939246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  939249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  939263 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939266 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939269 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939276 */     // MIs[0] cbsz
     /*  939276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939279 */     // MIs[0] blgp
     /*  939279 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939282 */     // MIs[0] src0_modifiers
     /*  939282 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939285 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939290 */     // MIs[0] src1_modifiers
     /*  939290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939293 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939298 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939302 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64),
     /*  939305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939307 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939309 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939311 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939313 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939315 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939317 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939319 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939321 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939327 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939333 */     GIR_RootConstrainSelectedInstOperands,
     /*  939334 */     // GIR_Coverage, 3748,
     /*  939334 */     GIR_EraseRootFromParent_Done,
     /*  939335 */   // Label 15014: @939335
     /*  939335 */   GIM_Try, /*On fail goto*//*Label 15015*/ GIMT_Encode4(939429), // Rule ID 3754 //
     /*  939340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  939343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  939357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939360 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939363 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939370 */     // MIs[0] cbsz
     /*  939370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939373 */     // MIs[0] blgp
     /*  939373 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939376 */     // MIs[0] src0_modifiers
     /*  939376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939379 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939384 */     // MIs[0] src1_modifiers
     /*  939384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939387 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939392 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939396 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  939399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939401 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939403 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939405 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939407 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939409 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939411 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939413 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939415 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939421 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939427 */     GIR_RootConstrainSelectedInstOperands,
     /*  939428 */     // GIR_Coverage, 3754,
     /*  939428 */     GIR_EraseRootFromParent_Done,
     /*  939429 */   // Label 15015: @939429
     /*  939429 */   GIM_Try, /*On fail goto*//*Label 15016*/ GIMT_Encode4(939523), // Rule ID 3755 //
     /*  939434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  939437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  939451 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939454 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939457 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939464 */     // MIs[0] cbsz
     /*  939464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939467 */     // MIs[0] blgp
     /*  939467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939470 */     // MIs[0] src0_modifiers
     /*  939470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939473 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939478 */     // MIs[0] src1_modifiers
     /*  939478 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939481 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939486 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939490 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  939493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939495 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939497 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939499 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939501 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939503 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939505 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939507 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939509 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939515 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939521 */     GIR_RootConstrainSelectedInstOperands,
     /*  939522 */     // GIR_Coverage, 3755,
     /*  939522 */     GIR_EraseRootFromParent_Done,
     /*  939523 */   // Label 15016: @939523
     /*  939523 */   GIM_Try, /*On fail goto*//*Label 15017*/ GIMT_Encode4(939617), // Rule ID 3756 //
     /*  939528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  939531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  939545 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939548 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939551 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939558 */     // MIs[0] cbsz
     /*  939558 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939561 */     // MIs[0] blgp
     /*  939561 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939564 */     // MIs[0] src0_modifiers
     /*  939564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939567 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939572 */     // MIs[0] src1_modifiers
     /*  939572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939575 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939580 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939584 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  939587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939589 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939591 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939593 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939595 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939597 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939599 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939601 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939603 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939609 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939615 */     GIR_RootConstrainSelectedInstOperands,
     /*  939616 */     // GIR_Coverage, 3756,
     /*  939616 */     GIR_EraseRootFromParent_Done,
     /*  939617 */   // Label 15017: @939617
     /*  939617 */   GIM_Try, /*On fail goto*//*Label 15018*/ GIMT_Encode4(939711), // Rule ID 3757 //
     /*  939622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  939625 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939630 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939633 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939636 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  939639 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939642 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939645 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939652 */     // MIs[0] cbsz
     /*  939652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939655 */     // MIs[0] blgp
     /*  939655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939658 */     // MIs[0] src0_modifiers
     /*  939658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939661 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939666 */     // MIs[0] src1_modifiers
     /*  939666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939669 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939674 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939678 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  939681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939683 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939685 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939687 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939689 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939691 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939693 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939695 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939697 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939703 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939709 */     GIR_RootConstrainSelectedInstOperands,
     /*  939710 */     // GIR_Coverage, 3757,
     /*  939710 */     GIR_EraseRootFromParent_Done,
     /*  939711 */   // Label 15018: @939711
     /*  939711 */   GIM_Try, /*On fail goto*//*Label 15019*/ GIMT_Encode4(939805), // Rule ID 3758 //
     /*  939716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  939719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939727 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  939730 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  939733 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939736 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939739 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939746 */     // MIs[0] cbsz
     /*  939746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939749 */     // MIs[0] blgp
     /*  939749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939752 */     // MIs[0] src0_modifiers
     /*  939752 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939755 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939760 */     // MIs[0] src1_modifiers
     /*  939760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939763 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939768 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939772 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64),
     /*  939775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939777 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939781 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939783 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939785 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939787 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939789 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939791 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939797 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939803 */     GIR_RootConstrainSelectedInstOperands,
     /*  939804 */     // GIR_Coverage, 3758,
     /*  939804 */     GIR_EraseRootFromParent_Done,
     /*  939805 */   // Label 15019: @939805
     /*  939805 */   GIM_Try, /*On fail goto*//*Label 15020*/ GIMT_Encode4(939899), // Rule ID 3764 //
     /*  939810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  939813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  939824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  939827 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939830 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939833 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939840 */     // MIs[0] cbsz
     /*  939840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939843 */     // MIs[0] blgp
     /*  939843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939846 */     // MIs[0] src0_modifiers
     /*  939846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939849 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939854 */     // MIs[0] src1_modifiers
     /*  939854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939857 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939862 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939866 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  939869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939871 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939873 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939875 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939877 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939879 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939881 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939883 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939885 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939891 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939897 */     GIR_RootConstrainSelectedInstOperands,
     /*  939898 */     // GIR_Coverage, 3764,
     /*  939898 */     GIR_EraseRootFromParent_Done,
     /*  939899 */   // Label 15020: @939899
     /*  939899 */   GIM_Try, /*On fail goto*//*Label 15021*/ GIMT_Encode4(939993), // Rule ID 3765 //
     /*  939904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  939907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  939912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  939915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  939918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  939921 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  939924 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  939927 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  939930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  939934 */     // MIs[0] cbsz
     /*  939934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  939937 */     // MIs[0] blgp
     /*  939937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  939940 */     // MIs[0] src0_modifiers
     /*  939940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  939943 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939948 */     // MIs[0] src1_modifiers
     /*  939948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  939951 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  939956 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  939960 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  939960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  939963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  939965 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  939967 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  939969 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  939971 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  939973 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  939975 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  939977 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  939979 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  939985 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  939991 */     GIR_RootConstrainSelectedInstOperands,
     /*  939992 */     // GIR_Coverage, 3765,
     /*  939992 */     GIR_EraseRootFromParent_Done,
     /*  939993 */   // Label 15021: @939993
     /*  939993 */   GIM_Try, /*On fail goto*//*Label 15022*/ GIMT_Encode4(940087), // Rule ID 3766 //
     /*  939998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  940001 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940006 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940009 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  940012 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  940015 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940018 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940021 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940028 */     // MIs[0] cbsz
     /*  940028 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940031 */     // MIs[0] blgp
     /*  940031 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940034 */     // MIs[0] src0_modifiers
     /*  940034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940037 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940042 */     // MIs[0] src1_modifiers
     /*  940042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940045 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940050 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940054 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  940057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940059 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940061 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940063 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940065 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940067 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940069 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940071 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940073 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940079 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940085 */     GIR_RootConstrainSelectedInstOperands,
     /*  940086 */     // GIR_Coverage, 3766,
     /*  940086 */     GIR_EraseRootFromParent_Done,
     /*  940087 */   // Label 15022: @940087
     /*  940087 */   GIM_Try, /*On fail goto*//*Label 15023*/ GIMT_Encode4(940181), // Rule ID 3767 //
     /*  940092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  940095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  940106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  940109 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940112 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940115 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940122 */     // MIs[0] cbsz
     /*  940122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940125 */     // MIs[0] blgp
     /*  940125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940128 */     // MIs[0] src0_modifiers
     /*  940128 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940131 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940136 */     // MIs[0] src1_modifiers
     /*  940136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940139 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940144 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940148 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  940151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940153 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940155 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940157 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940159 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940161 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940163 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940165 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940167 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940173 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940179 */     GIR_RootConstrainSelectedInstOperands,
     /*  940180 */     // GIR_Coverage, 3767,
     /*  940180 */     GIR_EraseRootFromParent_Done,
     /*  940181 */   // Label 15023: @940181
     /*  940181 */   GIM_Try, /*On fail goto*//*Label 15024*/ GIMT_Encode4(940275), // Rule ID 3768 //
     /*  940186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  940189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940197 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  940200 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  940203 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940206 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940209 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940216 */     // MIs[0] cbsz
     /*  940216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940219 */     // MIs[0] blgp
     /*  940219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940222 */     // MIs[0] src0_modifiers
     /*  940222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940225 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940230 */     // MIs[0] src1_modifiers
     /*  940230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940233 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940238 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940242 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64),
     /*  940245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940247 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940249 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940251 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940253 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940255 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940257 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940259 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940261 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940267 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940273 */     GIR_RootConstrainSelectedInstOperands,
     /*  940274 */     // GIR_Coverage, 3768,
     /*  940274 */     GIR_EraseRootFromParent_Done,
     /*  940275 */   // Label 15024: @940275
     /*  940275 */   GIM_Try, /*On fail goto*//*Label 15025*/ GIMT_Encode4(940369), // Rule ID 3774 //
     /*  940280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  940283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  940294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  940297 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940300 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940303 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940310 */     // MIs[0] cbsz
     /*  940310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940313 */     // MIs[0] blgp
     /*  940313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940316 */     // MIs[0] src0_modifiers
     /*  940316 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940319 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940324 */     // MIs[0] src1_modifiers
     /*  940324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940327 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940332 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940336 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  940339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940341 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940343 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940345 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940347 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940349 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940351 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940353 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940355 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940361 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940367 */     GIR_RootConstrainSelectedInstOperands,
     /*  940368 */     // GIR_Coverage, 3774,
     /*  940368 */     GIR_EraseRootFromParent_Done,
     /*  940369 */   // Label 15025: @940369
     /*  940369 */   GIM_Try, /*On fail goto*//*Label 15026*/ GIMT_Encode4(940463), // Rule ID 3775 //
     /*  940374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  940377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  940388 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  940391 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940394 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940397 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940404 */     // MIs[0] cbsz
     /*  940404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940407 */     // MIs[0] blgp
     /*  940407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940410 */     // MIs[0] src0_modifiers
     /*  940410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940413 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940418 */     // MIs[0] src1_modifiers
     /*  940418 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940421 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940426 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940430 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  940433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940435 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940437 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940439 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940441 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940443 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940445 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940447 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940449 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940455 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940461 */     GIR_RootConstrainSelectedInstOperands,
     /*  940462 */     // GIR_Coverage, 3775,
     /*  940462 */     GIR_EraseRootFromParent_Done,
     /*  940463 */   // Label 15026: @940463
     /*  940463 */   GIM_Try, /*On fail goto*//*Label 15027*/ GIMT_Encode4(940557), // Rule ID 3776 //
     /*  940468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  940471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  940482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  940485 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940488 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940491 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940498 */     // MIs[0] cbsz
     /*  940498 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940501 */     // MIs[0] blgp
     /*  940501 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940504 */     // MIs[0] src0_modifiers
     /*  940504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940507 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940512 */     // MIs[0] src1_modifiers
     /*  940512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940515 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940520 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940524 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  940527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940529 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940533 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940535 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940537 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940539 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940541 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940543 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940549 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940555 */     GIR_RootConstrainSelectedInstOperands,
     /*  940556 */     // GIR_Coverage, 3776,
     /*  940556 */     GIR_EraseRootFromParent_Done,
     /*  940557 */   // Label 15027: @940557
     /*  940557 */   GIM_Try, /*On fail goto*//*Label 15028*/ GIMT_Encode4(940651), // Rule ID 3777 //
     /*  940562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  940565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  940576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  940579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940582 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940585 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940592 */     // MIs[0] cbsz
     /*  940592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940595 */     // MIs[0] blgp
     /*  940595 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940598 */     // MIs[0] src0_modifiers
     /*  940598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940601 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940606 */     // MIs[0] src1_modifiers
     /*  940606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940609 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940614 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940618 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  940621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940623 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940625 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940627 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940629 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940631 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940633 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940635 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940637 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940643 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940649 */     GIR_RootConstrainSelectedInstOperands,
     /*  940650 */     // GIR_Coverage, 3777,
     /*  940650 */     GIR_EraseRootFromParent_Done,
     /*  940651 */   // Label 15028: @940651
     /*  940651 */   GIM_Try, /*On fail goto*//*Label 15029*/ GIMT_Encode4(940745), // Rule ID 3778 //
     /*  940656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  940659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940667 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  940670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  940673 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940676 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940679 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940686 */     // MIs[0] cbsz
     /*  940686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940689 */     // MIs[0] blgp
     /*  940689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940692 */     // MIs[0] src0_modifiers
     /*  940692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940695 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940700 */     // MIs[0] src1_modifiers
     /*  940700 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940703 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940708 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940712 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64),
     /*  940715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940717 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940719 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940721 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940723 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940725 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940727 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940729 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940731 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940737 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940743 */     GIR_RootConstrainSelectedInstOperands,
     /*  940744 */     // GIR_Coverage, 3778,
     /*  940744 */     GIR_EraseRootFromParent_Done,
     /*  940745 */   // Label 15029: @940745
     /*  940745 */   GIM_Try, /*On fail goto*//*Label 15030*/ GIMT_Encode4(940839), // Rule ID 3784 //
     /*  940750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  940753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  940764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  940767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940770 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940773 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940780 */     // MIs[0] cbsz
     /*  940780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940783 */     // MIs[0] blgp
     /*  940783 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940786 */     // MIs[0] src0_modifiers
     /*  940786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940789 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940794 */     // MIs[0] src1_modifiers
     /*  940794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940797 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940802 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940806 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  940809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940811 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940813 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940815 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940817 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940819 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940821 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940823 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940825 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940831 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940837 */     GIR_RootConstrainSelectedInstOperands,
     /*  940838 */     // GIR_Coverage, 3784,
     /*  940838 */     GIR_EraseRootFromParent_Done,
     /*  940839 */   // Label 15030: @940839
     /*  940839 */   GIM_Try, /*On fail goto*//*Label 15031*/ GIMT_Encode4(940933), // Rule ID 3785 //
     /*  940844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  940847 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940852 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940855 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  940858 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  940861 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940864 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940867 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940874 */     // MIs[0] cbsz
     /*  940874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940877 */     // MIs[0] blgp
     /*  940877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940880 */     // MIs[0] src0_modifiers
     /*  940880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940883 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940888 */     // MIs[0] src1_modifiers
     /*  940888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940891 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940896 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940900 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  940903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940905 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  940907 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  940909 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  940911 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  940913 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  940915 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  940917 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  940919 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  940925 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  940931 */     GIR_RootConstrainSelectedInstOperands,
     /*  940932 */     // GIR_Coverage, 3785,
     /*  940932 */     GIR_EraseRootFromParent_Done,
     /*  940933 */   // Label 15031: @940933
     /*  940933 */   GIM_Try, /*On fail goto*//*Label 15032*/ GIMT_Encode4(941027), // Rule ID 3786 //
     /*  940938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  940941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  940946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  940949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  940952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  940955 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  940958 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  940961 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  940964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  940968 */     // MIs[0] cbsz
     /*  940968 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  940971 */     // MIs[0] blgp
     /*  940971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  940974 */     // MIs[0] src0_modifiers
     /*  940974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  940977 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940982 */     // MIs[0] src1_modifiers
     /*  940982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  940985 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  940990 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  940994 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  940994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  940997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  940999 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941001 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941003 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941005 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941007 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941009 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941011 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941013 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941019 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941025 */     GIR_RootConstrainSelectedInstOperands,
     /*  941026 */     // GIR_Coverage, 3786,
     /*  941026 */     GIR_EraseRootFromParent_Done,
     /*  941027 */   // Label 15032: @941027
     /*  941027 */   GIM_Try, /*On fail goto*//*Label 15033*/ GIMT_Encode4(941121), // Rule ID 3787 //
     /*  941032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  941035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  941046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  941049 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941052 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941055 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941062 */     // MIs[0] cbsz
     /*  941062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941065 */     // MIs[0] blgp
     /*  941065 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941068 */     // MIs[0] src0_modifiers
     /*  941068 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941071 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941076 */     // MIs[0] src1_modifiers
     /*  941076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941079 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941084 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941088 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  941091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941093 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941097 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941099 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941101 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941103 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941105 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941107 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941113 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941119 */     GIR_RootConstrainSelectedInstOperands,
     /*  941120 */     // GIR_Coverage, 3787,
     /*  941120 */     GIR_EraseRootFromParent_Done,
     /*  941121 */   // Label 15033: @941121
     /*  941121 */   GIM_Try, /*On fail goto*//*Label 15034*/ GIMT_Encode4(941215), // Rule ID 3788 //
     /*  941126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  941129 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941134 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941137 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  941140 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  941143 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941146 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941149 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941156 */     // MIs[0] cbsz
     /*  941156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941159 */     // MIs[0] blgp
     /*  941159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941162 */     // MIs[0] src0_modifiers
     /*  941162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941165 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941170 */     // MIs[0] src1_modifiers
     /*  941170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941173 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941178 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941182 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64),
     /*  941185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941187 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941189 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941191 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941193 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941195 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941197 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941199 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941201 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941207 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941213 */     GIR_RootConstrainSelectedInstOperands,
     /*  941214 */     // GIR_Coverage, 3788,
     /*  941214 */     GIR_EraseRootFromParent_Done,
     /*  941215 */   // Label 15034: @941215
     /*  941215 */   GIM_Try, /*On fail goto*//*Label 15035*/ GIMT_Encode4(941309), // Rule ID 3794 //
     /*  941220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  941223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941231 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941234 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  941237 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941240 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941243 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941250 */     // MIs[0] cbsz
     /*  941250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941253 */     // MIs[0] blgp
     /*  941253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941256 */     // MIs[0] src0_modifiers
     /*  941256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941259 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941264 */     // MIs[0] src1_modifiers
     /*  941264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941267 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941272 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941276 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  941279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941281 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941283 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941285 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941287 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941289 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941291 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941293 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941295 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941301 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941307 */     GIR_RootConstrainSelectedInstOperands,
     /*  941308 */     // GIR_Coverage, 3794,
     /*  941308 */     GIR_EraseRootFromParent_Done,
     /*  941309 */   // Label 15035: @941309
     /*  941309 */   GIM_Try, /*On fail goto*//*Label 15036*/ GIMT_Encode4(941403), // Rule ID 3795 //
     /*  941314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  941317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  941331 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941334 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941337 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941344 */     // MIs[0] cbsz
     /*  941344 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941347 */     // MIs[0] blgp
     /*  941347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941350 */     // MIs[0] src0_modifiers
     /*  941350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941353 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941358 */     // MIs[0] src1_modifiers
     /*  941358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941361 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941366 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941370 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  941373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941375 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941377 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941379 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941381 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941383 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941385 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941387 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941389 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941395 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941401 */     GIR_RootConstrainSelectedInstOperands,
     /*  941402 */     // GIR_Coverage, 3795,
     /*  941402 */     GIR_EraseRootFromParent_Done,
     /*  941403 */   // Label 15036: @941403
     /*  941403 */   GIM_Try, /*On fail goto*//*Label 15037*/ GIMT_Encode4(941497), // Rule ID 3796 //
     /*  941408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  941411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  941425 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941428 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941431 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941438 */     // MIs[0] cbsz
     /*  941438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941441 */     // MIs[0] blgp
     /*  941441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941444 */     // MIs[0] src0_modifiers
     /*  941444 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941447 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941452 */     // MIs[0] src1_modifiers
     /*  941452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941455 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941460 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941464 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  941467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941469 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941471 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941473 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941475 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941477 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941479 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941481 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941483 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941489 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941495 */     GIR_RootConstrainSelectedInstOperands,
     /*  941496 */     // GIR_Coverage, 3796,
     /*  941496 */     GIR_EraseRootFromParent_Done,
     /*  941497 */   // Label 15037: @941497
     /*  941497 */   GIM_Try, /*On fail goto*//*Label 15038*/ GIMT_Encode4(941591), // Rule ID 3797 //
     /*  941502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  941505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  941519 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941522 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941525 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941532 */     // MIs[0] cbsz
     /*  941532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941535 */     // MIs[0] blgp
     /*  941535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941538 */     // MIs[0] src0_modifiers
     /*  941538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941541 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941546 */     // MIs[0] src1_modifiers
     /*  941546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941549 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941554 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941558 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  941561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941563 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941565 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941567 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941569 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941571 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941573 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941575 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941577 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941583 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941589 */     GIR_RootConstrainSelectedInstOperands,
     /*  941590 */     // GIR_Coverage, 3797,
     /*  941590 */     GIR_EraseRootFromParent_Done,
     /*  941591 */   // Label 15038: @941591
     /*  941591 */   GIM_Try, /*On fail goto*//*Label 15039*/ GIMT_Encode4(941685), // Rule ID 3798 //
     /*  941596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  941599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941610 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  941613 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941616 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941619 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941626 */     // MIs[0] cbsz
     /*  941626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941629 */     // MIs[0] blgp
     /*  941629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941632 */     // MIs[0] src0_modifiers
     /*  941632 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941635 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941640 */     // MIs[0] src1_modifiers
     /*  941640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941643 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941648 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941652 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64),
     /*  941655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941657 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941659 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941661 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941663 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941665 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941667 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941669 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941671 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941677 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941683 */     GIR_RootConstrainSelectedInstOperands,
     /*  941684 */     // GIR_Coverage, 3798,
     /*  941684 */     GIR_EraseRootFromParent_Done,
     /*  941685 */   // Label 15039: @941685
     /*  941685 */   GIM_Try, /*On fail goto*//*Label 15040*/ GIMT_Encode4(941779), // Rule ID 3804 //
     /*  941690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  941693 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941698 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941701 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941704 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  941707 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941710 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941713 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941720 */     // MIs[0] cbsz
     /*  941720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941723 */     // MIs[0] blgp
     /*  941723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941726 */     // MIs[0] src0_modifiers
     /*  941726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941729 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941734 */     // MIs[0] src1_modifiers
     /*  941734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941737 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941742 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941746 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  941749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941751 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941753 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941755 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941757 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941759 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941761 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941763 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941765 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941771 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941777 */     GIR_RootConstrainSelectedInstOperands,
     /*  941778 */     // GIR_Coverage, 3804,
     /*  941778 */     GIR_EraseRootFromParent_Done,
     /*  941779 */   // Label 15040: @941779
     /*  941779 */   GIM_Try, /*On fail goto*//*Label 15041*/ GIMT_Encode4(941873), // Rule ID 3805 //
     /*  941784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  941787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  941801 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941804 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941807 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941814 */     // MIs[0] cbsz
     /*  941814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941817 */     // MIs[0] blgp
     /*  941817 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941820 */     // MIs[0] src0_modifiers
     /*  941820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941823 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941828 */     // MIs[0] src1_modifiers
     /*  941828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941831 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941836 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941840 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  941843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941845 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941847 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941849 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941851 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941853 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941855 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941857 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941859 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941865 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941871 */     GIR_RootConstrainSelectedInstOperands,
     /*  941872 */     // GIR_Coverage, 3805,
     /*  941872 */     GIR_EraseRootFromParent_Done,
     /*  941873 */   // Label 15041: @941873
     /*  941873 */   GIM_Try, /*On fail goto*//*Label 15042*/ GIMT_Encode4(941967), // Rule ID 3806 //
     /*  941878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  941881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  941895 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941898 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941901 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  941908 */     // MIs[0] cbsz
     /*  941908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  941911 */     // MIs[0] blgp
     /*  941911 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  941914 */     // MIs[0] src0_modifiers
     /*  941914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  941917 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941922 */     // MIs[0] src1_modifiers
     /*  941922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  941925 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  941930 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  941934 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  941934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  941937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  941939 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  941941 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  941943 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  941945 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  941947 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  941949 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  941951 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  941953 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  941959 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  941965 */     GIR_RootConstrainSelectedInstOperands,
     /*  941966 */     // GIR_Coverage, 3806,
     /*  941966 */     GIR_EraseRootFromParent_Done,
     /*  941967 */   // Label 15042: @941967
     /*  941967 */   GIM_Try, /*On fail goto*//*Label 15043*/ GIMT_Encode4(942061), // Rule ID 3807 //
     /*  941972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  941975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  941980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  941983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  941986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  941989 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  941992 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  941995 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  941998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  942002 */     // MIs[0] cbsz
     /*  942002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942005 */     // MIs[0] blgp
     /*  942005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942008 */     // MIs[0] src0_modifiers
     /*  942008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942011 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942016 */     // MIs[0] src1_modifiers
     /*  942016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942019 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942024 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  942028 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  942031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942033 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942035 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942037 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942039 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942041 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942043 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942045 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942047 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942053 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942059 */     GIR_RootConstrainSelectedInstOperands,
     /*  942060 */     // GIR_Coverage, 3807,
     /*  942060 */     GIR_EraseRootFromParent_Done,
     /*  942061 */   // Label 15043: @942061
     /*  942061 */   GIM_Try, /*On fail goto*//*Label 15044*/ GIMT_Encode4(942155), // Rule ID 3808 //
     /*  942066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  942069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  942074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  942077 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  942080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  942083 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  942086 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942089 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
     /*  942096 */     // MIs[0] cbsz
     /*  942096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942099 */     // MIs[0] blgp
     /*  942099 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942102 */     // MIs[0] src0_modifiers
     /*  942102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942105 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942110 */     // MIs[0] src1_modifiers
     /*  942110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942113 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942118 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31896),
     /*  942122 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31896>>  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64),
     /*  942125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942127 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942129 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942131 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942133 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942135 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942137 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942139 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942141 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942147 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942153 */     GIR_RootConstrainSelectedInstOperands,
     /*  942154 */     // GIR_Coverage, 3808,
     /*  942154 */     GIR_EraseRootFromParent_Done,
     /*  942155 */   // Label 15044: @942155
     /*  942155 */   GIM_Try, /*On fail goto*//*Label 15045*/ GIMT_Encode4(942249), // Rule ID 3814 //
     /*  942160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  942163 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942168 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942171 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942174 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  942177 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942180 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942183 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942190 */     // MIs[0] cbsz
     /*  942190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942193 */     // MIs[0] blgp
     /*  942193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942196 */     // MIs[0] src0_modifiers
     /*  942196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942199 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942204 */     // MIs[0] src1_modifiers
     /*  942204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942207 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942212 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942216 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  942219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942221 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942223 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942225 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942227 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942229 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942231 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942233 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942235 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942241 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942247 */     GIR_RootConstrainSelectedInstOperands,
     /*  942248 */     // GIR_Coverage, 3814,
     /*  942248 */     GIR_EraseRootFromParent_Done,
     /*  942249 */   // Label 15045: @942249
     /*  942249 */   GIM_Try, /*On fail goto*//*Label 15046*/ GIMT_Encode4(942343), // Rule ID 3815 //
     /*  942254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  942257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  942271 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942274 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942277 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942284 */     // MIs[0] cbsz
     /*  942284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942287 */     // MIs[0] blgp
     /*  942287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942290 */     // MIs[0] src0_modifiers
     /*  942290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942293 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942298 */     // MIs[0] src1_modifiers
     /*  942298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942301 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942306 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942310 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  942313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942315 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942317 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942319 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942321 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942323 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942325 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942327 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942329 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942335 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942341 */     GIR_RootConstrainSelectedInstOperands,
     /*  942342 */     // GIR_Coverage, 3815,
     /*  942342 */     GIR_EraseRootFromParent_Done,
     /*  942343 */   // Label 15046: @942343
     /*  942343 */   GIM_Try, /*On fail goto*//*Label 15047*/ GIMT_Encode4(942437), // Rule ID 3816 //
     /*  942348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  942351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  942365 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942368 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942371 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942378 */     // MIs[0] cbsz
     /*  942378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942381 */     // MIs[0] blgp
     /*  942381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942384 */     // MIs[0] src0_modifiers
     /*  942384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942387 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942392 */     // MIs[0] src1_modifiers
     /*  942392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942395 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942400 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942404 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  942407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942409 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942411 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942413 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942415 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942417 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942419 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942421 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942423 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942429 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942435 */     GIR_RootConstrainSelectedInstOperands,
     /*  942436 */     // GIR_Coverage, 3816,
     /*  942436 */     GIR_EraseRootFromParent_Done,
     /*  942437 */   // Label 15047: @942437
     /*  942437 */   GIM_Try, /*On fail goto*//*Label 15048*/ GIMT_Encode4(942531), // Rule ID 3817 //
     /*  942442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  942445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  942459 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942462 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942465 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942472 */     // MIs[0] cbsz
     /*  942472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942475 */     // MIs[0] blgp
     /*  942475 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942478 */     // MIs[0] src0_modifiers
     /*  942478 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942481 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942486 */     // MIs[0] src1_modifiers
     /*  942486 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942489 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942494 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942498 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  942501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942503 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942505 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942507 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942509 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942511 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942513 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942515 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942517 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942523 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942529 */     GIR_RootConstrainSelectedInstOperands,
     /*  942530 */     // GIR_Coverage, 3817,
     /*  942530 */     GIR_EraseRootFromParent_Done,
     /*  942531 */   // Label 15048: @942531
     /*  942531 */   GIM_Try, /*On fail goto*//*Label 15049*/ GIMT_Encode4(942625), // Rule ID 3818 //
     /*  942536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  942539 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942544 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942547 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942550 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  942553 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942556 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942559 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942566 */     // MIs[0] cbsz
     /*  942566 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942569 */     // MIs[0] blgp
     /*  942569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942572 */     // MIs[0] src0_modifiers
     /*  942572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942575 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942580 */     // MIs[0] src1_modifiers
     /*  942580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942583 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942588 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942592 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64),
     /*  942595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942597 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942599 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942601 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942603 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942605 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942607 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942609 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942611 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942617 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942623 */     GIR_RootConstrainSelectedInstOperands,
     /*  942624 */     // GIR_Coverage, 3818,
     /*  942624 */     GIR_EraseRootFromParent_Done,
     /*  942625 */   // Label 15049: @942625
     /*  942625 */   GIM_Try, /*On fail goto*//*Label 15050*/ GIMT_Encode4(942719), // Rule ID 3824 //
     /*  942630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  942633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  942647 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942650 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942653 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942660 */     // MIs[0] cbsz
     /*  942660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942663 */     // MIs[0] blgp
     /*  942663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942666 */     // MIs[0] src0_modifiers
     /*  942666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942669 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942674 */     // MIs[0] src1_modifiers
     /*  942674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942677 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942682 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942686 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  942689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942691 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942693 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942695 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942697 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942699 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942701 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942703 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942705 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942711 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942717 */     GIR_RootConstrainSelectedInstOperands,
     /*  942718 */     // GIR_Coverage, 3824,
     /*  942718 */     GIR_EraseRootFromParent_Done,
     /*  942719 */   // Label 15050: @942719
     /*  942719 */   GIM_Try, /*On fail goto*//*Label 15051*/ GIMT_Encode4(942813), // Rule ID 3825 //
     /*  942724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  942727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942735 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942738 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  942741 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942744 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942747 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942754 */     // MIs[0] cbsz
     /*  942754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942757 */     // MIs[0] blgp
     /*  942757 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942760 */     // MIs[0] src0_modifiers
     /*  942760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942763 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942768 */     // MIs[0] src1_modifiers
     /*  942768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942776 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942780 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  942783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942785 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942787 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942789 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942791 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942793 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942795 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942797 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942799 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942805 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942811 */     GIR_RootConstrainSelectedInstOperands,
     /*  942812 */     // GIR_Coverage, 3825,
     /*  942812 */     GIR_EraseRootFromParent_Done,
     /*  942813 */   // Label 15051: @942813
     /*  942813 */   GIM_Try, /*On fail goto*//*Label 15052*/ GIMT_Encode4(942907), // Rule ID 3826 //
     /*  942818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  942821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  942835 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942838 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942841 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942848 */     // MIs[0] cbsz
     /*  942848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942851 */     // MIs[0] blgp
     /*  942851 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942854 */     // MIs[0] src0_modifiers
     /*  942854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942857 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942862 */     // MIs[0] src1_modifiers
     /*  942862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942865 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942870 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942874 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  942877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942879 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942881 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942883 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942885 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942887 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942889 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942891 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942893 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942899 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942905 */     GIR_RootConstrainSelectedInstOperands,
     /*  942906 */     // GIR_Coverage, 3826,
     /*  942906 */     GIR_EraseRootFromParent_Done,
     /*  942907 */   // Label 15052: @942907
     /*  942907 */   GIM_Try, /*On fail goto*//*Label 15053*/ GIMT_Encode4(943001), // Rule ID 3827 //
     /*  942912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  942915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  942920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  942923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  942926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  942929 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  942932 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  942935 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  942938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  942942 */     // MIs[0] cbsz
     /*  942942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  942945 */     // MIs[0] blgp
     /*  942945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  942948 */     // MIs[0] src0_modifiers
     /*  942948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  942951 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942956 */     // MIs[0] src1_modifiers
     /*  942956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  942959 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  942964 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  942968 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  942968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  942971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  942973 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  942975 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  942977 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  942979 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  942981 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  942983 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  942985 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  942987 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  942993 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  942999 */     GIR_RootConstrainSelectedInstOperands,
     /*  943000 */     // GIR_Coverage, 3827,
     /*  943000 */     GIR_EraseRootFromParent_Done,
     /*  943001 */   // Label 15053: @943001
     /*  943001 */   GIM_Try, /*On fail goto*//*Label 15054*/ GIMT_Encode4(943095), // Rule ID 3828 //
     /*  943006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  943009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  943020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  943023 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943026 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943029 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943036 */     // MIs[0] cbsz
     /*  943036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943039 */     // MIs[0] blgp
     /*  943039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943042 */     // MIs[0] src0_modifiers
     /*  943042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943045 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943050 */     // MIs[0] src1_modifiers
     /*  943050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943053 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943058 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943062 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64),
     /*  943065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943067 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943069 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943071 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943073 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943075 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943077 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943079 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943081 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943087 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943093 */     GIR_RootConstrainSelectedInstOperands,
     /*  943094 */     // GIR_Coverage, 3828,
     /*  943094 */     GIR_EraseRootFromParent_Done,
     /*  943095 */   // Label 15054: @943095
     /*  943095 */   GIM_Try, /*On fail goto*//*Label 15055*/ GIMT_Encode4(943189), // Rule ID 3834 //
     /*  943100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  943103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  943117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943120 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943123 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943130 */     // MIs[0] cbsz
     /*  943130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943133 */     // MIs[0] blgp
     /*  943133 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943136 */     // MIs[0] src0_modifiers
     /*  943136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943139 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943144 */     // MIs[0] src1_modifiers
     /*  943144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943147 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943152 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943156 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  943159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943161 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943163 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943165 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943167 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943169 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943171 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943173 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943175 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943181 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943187 */     GIR_RootConstrainSelectedInstOperands,
     /*  943188 */     // GIR_Coverage, 3834,
     /*  943188 */     GIR_EraseRootFromParent_Done,
     /*  943189 */   // Label 15055: @943189
     /*  943189 */   GIM_Try, /*On fail goto*//*Label 15056*/ GIMT_Encode4(943283), // Rule ID 3835 //
     /*  943194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  943197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  943211 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943214 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943217 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943224 */     // MIs[0] cbsz
     /*  943224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943227 */     // MIs[0] blgp
     /*  943227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943230 */     // MIs[0] src0_modifiers
     /*  943230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943233 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943238 */     // MIs[0] src1_modifiers
     /*  943238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943241 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943246 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943250 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  943253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943255 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943257 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943259 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943261 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943263 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943265 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943267 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943269 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943275 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943281 */     GIR_RootConstrainSelectedInstOperands,
     /*  943282 */     // GIR_Coverage, 3835,
     /*  943282 */     GIR_EraseRootFromParent_Done,
     /*  943283 */   // Label 15056: @943283
     /*  943283 */   GIM_Try, /*On fail goto*//*Label 15057*/ GIMT_Encode4(943377), // Rule ID 3836 //
     /*  943288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  943291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  943305 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943308 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943311 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943318 */     // MIs[0] cbsz
     /*  943318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943321 */     // MIs[0] blgp
     /*  943321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943324 */     // MIs[0] src0_modifiers
     /*  943324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943327 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943332 */     // MIs[0] src1_modifiers
     /*  943332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943335 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943340 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943344 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  943347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943349 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943351 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943353 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943355 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943357 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943359 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943361 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943363 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943369 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943375 */     GIR_RootConstrainSelectedInstOperands,
     /*  943376 */     // GIR_Coverage, 3836,
     /*  943376 */     GIR_EraseRootFromParent_Done,
     /*  943377 */   // Label 15057: @943377
     /*  943377 */   GIM_Try, /*On fail goto*//*Label 15058*/ GIMT_Encode4(943471), // Rule ID 3837 //
     /*  943382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  943385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  943399 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943402 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943405 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943412 */     // MIs[0] cbsz
     /*  943412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943415 */     // MIs[0] blgp
     /*  943415 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943418 */     // MIs[0] src0_modifiers
     /*  943418 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943421 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943426 */     // MIs[0] src1_modifiers
     /*  943426 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943429 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943434 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943438 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  943441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943443 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943445 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943447 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943449 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943451 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943453 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943455 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943457 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943463 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943469 */     GIR_RootConstrainSelectedInstOperands,
     /*  943470 */     // GIR_Coverage, 3837,
     /*  943470 */     GIR_EraseRootFromParent_Done,
     /*  943471 */   // Label 15058: @943471
     /*  943471 */   GIM_Try, /*On fail goto*//*Label 15059*/ GIMT_Encode4(943565), // Rule ID 3838 //
     /*  943476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  943479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943484 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  943493 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943496 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943499 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943506 */     // MIs[0] cbsz
     /*  943506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943509 */     // MIs[0] blgp
     /*  943509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943512 */     // MIs[0] src0_modifiers
     /*  943512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943515 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943520 */     // MIs[0] src1_modifiers
     /*  943520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943523 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943528 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943532 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64),
     /*  943535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943537 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943539 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943541 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943543 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943545 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943547 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943549 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943551 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943557 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943563 */     GIR_RootConstrainSelectedInstOperands,
     /*  943564 */     // GIR_Coverage, 3838,
     /*  943564 */     GIR_EraseRootFromParent_Done,
     /*  943565 */   // Label 15059: @943565
     /*  943565 */   GIM_Try, /*On fail goto*//*Label 15060*/ GIMT_Encode4(943659), // Rule ID 3844 //
     /*  943570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  943573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943578 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943581 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943584 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  943587 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943590 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943593 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943600 */     // MIs[0] cbsz
     /*  943600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943603 */     // MIs[0] blgp
     /*  943603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943606 */     // MIs[0] src0_modifiers
     /*  943606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943609 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943614 */     // MIs[0] src1_modifiers
     /*  943614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943617 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943622 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943626 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  943629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943631 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943633 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943635 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943637 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943639 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943641 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943643 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943645 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943651 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943657 */     GIR_RootConstrainSelectedInstOperands,
     /*  943658 */     // GIR_Coverage, 3844,
     /*  943658 */     GIR_EraseRootFromParent_Done,
     /*  943659 */   // Label 15060: @943659
     /*  943659 */   GIM_Try, /*On fail goto*//*Label 15061*/ GIMT_Encode4(943753), // Rule ID 3845 //
     /*  943664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  943667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  943681 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943684 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943687 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943694 */     // MIs[0] cbsz
     /*  943694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943697 */     // MIs[0] blgp
     /*  943697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943700 */     // MIs[0] src0_modifiers
     /*  943700 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943703 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943708 */     // MIs[0] src1_modifiers
     /*  943708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943711 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943716 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943720 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  943723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943725 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943727 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943729 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943731 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943733 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943735 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943737 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943739 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943745 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943751 */     GIR_RootConstrainSelectedInstOperands,
     /*  943752 */     // GIR_Coverage, 3845,
     /*  943752 */     GIR_EraseRootFromParent_Done,
     /*  943753 */   // Label 15061: @943753
     /*  943753 */   GIM_Try, /*On fail goto*//*Label 15062*/ GIMT_Encode4(943847), // Rule ID 3846 //
     /*  943758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  943761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  943775 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943778 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943781 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943788 */     // MIs[0] cbsz
     /*  943788 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943791 */     // MIs[0] blgp
     /*  943791 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943794 */     // MIs[0] src0_modifiers
     /*  943794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943797 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943802 */     // MIs[0] src1_modifiers
     /*  943802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943805 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943810 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943814 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  943817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943819 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943821 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943823 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943825 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943827 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943829 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943831 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943833 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943839 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943845 */     GIR_RootConstrainSelectedInstOperands,
     /*  943846 */     // GIR_Coverage, 3846,
     /*  943846 */     GIR_EraseRootFromParent_Done,
     /*  943847 */   // Label 15062: @943847
     /*  943847 */   GIM_Try, /*On fail goto*//*Label 15063*/ GIMT_Encode4(943941), // Rule ID 3847 //
     /*  943852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  943855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  943869 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943872 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943875 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943882 */     // MIs[0] cbsz
     /*  943882 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943885 */     // MIs[0] blgp
     /*  943885 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943888 */     // MIs[0] src0_modifiers
     /*  943888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943891 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943896 */     // MIs[0] src1_modifiers
     /*  943896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943899 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943904 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  943908 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  943908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  943911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  943913 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  943915 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  943917 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  943919 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  943921 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  943923 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  943925 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  943927 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  943933 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  943939 */     GIR_RootConstrainSelectedInstOperands,
     /*  943940 */     // GIR_Coverage, 3847,
     /*  943940 */     GIR_EraseRootFromParent_Done,
     /*  943941 */   // Label 15063: @943941
     /*  943941 */   GIM_Try, /*On fail goto*//*Label 15064*/ GIMT_Encode4(944035), // Rule ID 3848 //
     /*  943946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  943949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  943954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  943957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  943960 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  943963 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  943966 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  943969 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  943972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  943976 */     // MIs[0] cbsz
     /*  943976 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  943979 */     // MIs[0] blgp
     /*  943979 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  943982 */     // MIs[0] src0_modifiers
     /*  943982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  943985 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943990 */     // MIs[0] src1_modifiers
     /*  943990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  943993 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  943998 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944002 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64),
     /*  944005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944007 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944009 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944011 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944013 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944015 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944017 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944019 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944021 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944027 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944033 */     GIR_RootConstrainSelectedInstOperands,
     /*  944034 */     // GIR_Coverage, 3848,
     /*  944034 */     GIR_EraseRootFromParent_Done,
     /*  944035 */   // Label 15064: @944035
     /*  944035 */   GIM_Try, /*On fail goto*//*Label 15065*/ GIMT_Encode4(944129), // Rule ID 3854 //
     /*  944040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  944043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  944054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  944057 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944060 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944063 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944070 */     // MIs[0] cbsz
     /*  944070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944073 */     // MIs[0] blgp
     /*  944073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944076 */     // MIs[0] src0_modifiers
     /*  944076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944079 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944084 */     // MIs[0] src1_modifiers
     /*  944084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944087 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944092 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944096 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  944099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944101 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944103 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944105 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944107 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944109 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944111 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944113 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944115 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944121 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944127 */     GIR_RootConstrainSelectedInstOperands,
     /*  944128 */     // GIR_Coverage, 3854,
     /*  944128 */     GIR_EraseRootFromParent_Done,
     /*  944129 */   // Label 15065: @944129
     /*  944129 */   GIM_Try, /*On fail goto*//*Label 15066*/ GIMT_Encode4(944223), // Rule ID 3855 //
     /*  944134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  944137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  944148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  944151 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944154 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944157 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944164 */     // MIs[0] cbsz
     /*  944164 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944167 */     // MIs[0] blgp
     /*  944167 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944170 */     // MIs[0] src0_modifiers
     /*  944170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944173 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944178 */     // MIs[0] src1_modifiers
     /*  944178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944181 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944186 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944190 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  944193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944195 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944197 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944199 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944201 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944203 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944205 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944207 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944209 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944215 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944221 */     GIR_RootConstrainSelectedInstOperands,
     /*  944222 */     // GIR_Coverage, 3855,
     /*  944222 */     GIR_EraseRootFromParent_Done,
     /*  944223 */   // Label 15066: @944223
     /*  944223 */   GIM_Try, /*On fail goto*//*Label 15067*/ GIMT_Encode4(944317), // Rule ID 3856 //
     /*  944228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  944231 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944236 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944239 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  944242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  944245 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944248 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944251 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944258 */     // MIs[0] cbsz
     /*  944258 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944261 */     // MIs[0] blgp
     /*  944261 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944264 */     // MIs[0] src0_modifiers
     /*  944264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944267 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944272 */     // MIs[0] src1_modifiers
     /*  944272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944275 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944280 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944284 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  944287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944289 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944291 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944293 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944295 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944297 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944299 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944301 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944303 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944309 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944315 */     GIR_RootConstrainSelectedInstOperands,
     /*  944316 */     // GIR_Coverage, 3856,
     /*  944316 */     GIR_EraseRootFromParent_Done,
     /*  944317 */   // Label 15067: @944317
     /*  944317 */   GIM_Try, /*On fail goto*//*Label 15068*/ GIMT_Encode4(944411), // Rule ID 3857 //
     /*  944322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  944325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  944336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  944339 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944342 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944345 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944352 */     // MIs[0] cbsz
     /*  944352 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944355 */     // MIs[0] blgp
     /*  944355 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944358 */     // MIs[0] src0_modifiers
     /*  944358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944361 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944366 */     // MIs[0] src1_modifiers
     /*  944366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944369 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944374 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944378 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  944381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944383 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944385 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944387 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944389 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944391 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944393 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944395 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944397 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944403 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944409 */     GIR_RootConstrainSelectedInstOperands,
     /*  944410 */     // GIR_Coverage, 3857,
     /*  944410 */     GIR_EraseRootFromParent_Done,
     /*  944411 */   // Label 15068: @944411
     /*  944411 */   GIM_Try, /*On fail goto*//*Label 15069*/ GIMT_Encode4(944505), // Rule ID 3858 //
     /*  944416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  944419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  944430 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  944433 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944436 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944439 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944446 */     // MIs[0] cbsz
     /*  944446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944449 */     // MIs[0] blgp
     /*  944449 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944452 */     // MIs[0] src0_modifiers
     /*  944452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944455 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944460 */     // MIs[0] src1_modifiers
     /*  944460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944463 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944468 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944472 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64),
     /*  944475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944477 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944479 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944481 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944483 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944485 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944487 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944489 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944491 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944497 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944503 */     GIR_RootConstrainSelectedInstOperands,
     /*  944504 */     // GIR_Coverage, 3858,
     /*  944504 */     GIR_EraseRootFromParent_Done,
     /*  944505 */   // Label 15069: @944505
     /*  944505 */   GIM_Try, /*On fail goto*//*Label 15070*/ GIMT_Encode4(944599), // Rule ID 3864 //
     /*  944510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  944513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  944524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  944527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944530 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944533 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944540 */     // MIs[0] cbsz
     /*  944540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944543 */     // MIs[0] blgp
     /*  944543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944546 */     // MIs[0] src0_modifiers
     /*  944546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944549 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944554 */     // MIs[0] src1_modifiers
     /*  944554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944557 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944562 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944566 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  944569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944571 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944573 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944575 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944577 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944579 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944581 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944583 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944585 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944591 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944597 */     GIR_RootConstrainSelectedInstOperands,
     /*  944598 */     // GIR_Coverage, 3864,
     /*  944598 */     GIR_EraseRootFromParent_Done,
     /*  944599 */   // Label 15070: @944599
     /*  944599 */   GIM_Try, /*On fail goto*//*Label 15071*/ GIMT_Encode4(944693), // Rule ID 3865 //
     /*  944604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  944607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  944618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  944621 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944624 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944627 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944634 */     // MIs[0] cbsz
     /*  944634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944637 */     // MIs[0] blgp
     /*  944637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944640 */     // MIs[0] src0_modifiers
     /*  944640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944643 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944648 */     // MIs[0] src1_modifiers
     /*  944648 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944651 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944656 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944660 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  944663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944665 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944667 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944669 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944671 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944673 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944675 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944677 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944679 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944685 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944691 */     GIR_RootConstrainSelectedInstOperands,
     /*  944692 */     // GIR_Coverage, 3865,
     /*  944692 */     GIR_EraseRootFromParent_Done,
     /*  944693 */   // Label 15071: @944693
     /*  944693 */   GIM_Try, /*On fail goto*//*Label 15072*/ GIMT_Encode4(944787), // Rule ID 3866 //
     /*  944698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  944701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  944712 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  944715 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944718 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944721 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944728 */     // MIs[0] cbsz
     /*  944728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944731 */     // MIs[0] blgp
     /*  944731 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944734 */     // MIs[0] src0_modifiers
     /*  944734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944737 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944742 */     // MIs[0] src1_modifiers
     /*  944742 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944745 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944750 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944754 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  944757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944759 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944761 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944763 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944765 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944767 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944769 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944771 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944773 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944779 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944785 */     GIR_RootConstrainSelectedInstOperands,
     /*  944786 */     // GIR_Coverage, 3866,
     /*  944786 */     GIR_EraseRootFromParent_Done,
     /*  944787 */   // Label 15072: @944787
     /*  944787 */   GIM_Try, /*On fail goto*//*Label 15073*/ GIMT_Encode4(944881), // Rule ID 3867 //
     /*  944792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  944795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  944806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  944809 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944812 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944815 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944822 */     // MIs[0] cbsz
     /*  944822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944825 */     // MIs[0] blgp
     /*  944825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944828 */     // MIs[0] src0_modifiers
     /*  944828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944831 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944836 */     // MIs[0] src1_modifiers
     /*  944836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944839 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944844 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944848 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  944851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944853 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944855 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944857 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944859 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944861 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944863 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944865 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944867 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944873 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944879 */     GIR_RootConstrainSelectedInstOperands,
     /*  944880 */     // GIR_Coverage, 3867,
     /*  944880 */     GIR_EraseRootFromParent_Done,
     /*  944881 */   // Label 15073: @944881
     /*  944881 */   GIM_Try, /*On fail goto*//*Label 15074*/ GIMT_Encode4(944975), // Rule ID 3868 //
     /*  944886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  944889 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944894 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944897 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  944900 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  944903 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  944906 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  944909 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  944912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  944916 */     // MIs[0] cbsz
     /*  944916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  944919 */     // MIs[0] blgp
     /*  944919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  944922 */     // MIs[0] src0_modifiers
     /*  944922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  944925 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944930 */     // MIs[0] src1_modifiers
     /*  944930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  944933 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  944938 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  944942 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  944942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64),
     /*  944945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  944947 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  944949 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  944951 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  944953 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  944955 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  944957 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  944959 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  944961 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  944967 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  944973 */     GIR_RootConstrainSelectedInstOperands,
     /*  944974 */     // GIR_Coverage, 3868,
     /*  944974 */     GIR_EraseRootFromParent_Done,
     /*  944975 */   // Label 15074: @944975
     /*  944975 */   GIM_Try, /*On fail goto*//*Label 15075*/ GIMT_Encode4(945069), // Rule ID 3874 //
     /*  944980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  944983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  944988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  944991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  944994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  944997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945000 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945003 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945010 */     // MIs[0] cbsz
     /*  945010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945013 */     // MIs[0] blgp
     /*  945013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945016 */     // MIs[0] src0_modifiers
     /*  945016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945019 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945024 */     // MIs[0] src1_modifiers
     /*  945024 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945027 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945032 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945036 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  945039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945041 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945043 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945045 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945047 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945049 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945051 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945053 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945055 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945061 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945067 */     GIR_RootConstrainSelectedInstOperands,
     /*  945068 */     // GIR_Coverage, 3874,
     /*  945068 */     GIR_EraseRootFromParent_Done,
     /*  945069 */   // Label 15075: @945069
     /*  945069 */   GIM_Try, /*On fail goto*//*Label 15076*/ GIMT_Encode4(945163), // Rule ID 3875 //
     /*  945074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  945077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  945088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  945091 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945094 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945097 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945104 */     // MIs[0] cbsz
     /*  945104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945107 */     // MIs[0] blgp
     /*  945107 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945110 */     // MIs[0] src0_modifiers
     /*  945110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945113 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945118 */     // MIs[0] src1_modifiers
     /*  945118 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945121 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945126 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945130 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  945133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945135 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945137 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945139 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945141 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945143 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945145 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945147 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945149 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945155 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945161 */     GIR_RootConstrainSelectedInstOperands,
     /*  945162 */     // GIR_Coverage, 3875,
     /*  945162 */     GIR_EraseRootFromParent_Done,
     /*  945163 */   // Label 15076: @945163
     /*  945163 */   GIM_Try, /*On fail goto*//*Label 15077*/ GIMT_Encode4(945257), // Rule ID 3876 //
     /*  945168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  945171 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945176 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945179 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  945182 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  945185 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945188 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945191 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945198 */     // MIs[0] cbsz
     /*  945198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945201 */     // MIs[0] blgp
     /*  945201 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945204 */     // MIs[0] src0_modifiers
     /*  945204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945207 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945212 */     // MIs[0] src1_modifiers
     /*  945212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945215 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945220 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945224 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  945227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945229 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945231 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945233 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945235 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945237 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945239 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945241 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945243 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945249 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945255 */     GIR_RootConstrainSelectedInstOperands,
     /*  945256 */     // GIR_Coverage, 3876,
     /*  945256 */     GIR_EraseRootFromParent_Done,
     /*  945257 */   // Label 15077: @945257
     /*  945257 */   GIM_Try, /*On fail goto*//*Label 15078*/ GIMT_Encode4(945351), // Rule ID 3877 //
     /*  945262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  945265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  945276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  945279 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945282 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945285 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945292 */     // MIs[0] cbsz
     /*  945292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945295 */     // MIs[0] blgp
     /*  945295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945298 */     // MIs[0] src0_modifiers
     /*  945298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945301 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945306 */     // MIs[0] src1_modifiers
     /*  945306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945309 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945314 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945318 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  945321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945323 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945325 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945327 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945329 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945331 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945333 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945335 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945337 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945343 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945349 */     GIR_RootConstrainSelectedInstOperands,
     /*  945350 */     // GIR_Coverage, 3877,
     /*  945350 */     GIR_EraseRootFromParent_Done,
     /*  945351 */   // Label 15078: @945351
     /*  945351 */   GIM_Try, /*On fail goto*//*Label 15079*/ GIMT_Encode4(945445), // Rule ID 3878 //
     /*  945356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  945359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  945370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  945373 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945376 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945379 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945386 */     // MIs[0] cbsz
     /*  945386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945389 */     // MIs[0] blgp
     /*  945389 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945392 */     // MIs[0] src0_modifiers
     /*  945392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945395 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945400 */     // MIs[0] src1_modifiers
     /*  945400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945403 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945408 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945412 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64),
     /*  945415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945417 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945419 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945421 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945423 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945425 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945427 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945429 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945431 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945437 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945443 */     GIR_RootConstrainSelectedInstOperands,
     /*  945444 */     // GIR_Coverage, 3878,
     /*  945444 */     GIR_EraseRootFromParent_Done,
     /*  945445 */   // Label 15079: @945445
     /*  945445 */   GIM_Try, /*On fail goto*//*Label 15080*/ GIMT_Encode4(945539), // Rule ID 3884 //
     /*  945450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  945453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  945464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  945467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945470 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945473 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945480 */     // MIs[0] cbsz
     /*  945480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945483 */     // MIs[0] blgp
     /*  945483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945486 */     // MIs[0] src0_modifiers
     /*  945486 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945489 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945494 */     // MIs[0] src1_modifiers
     /*  945494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945497 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945502 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945506 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  945509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945511 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945513 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945515 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945517 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945519 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945521 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945523 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945525 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945531 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945537 */     GIR_RootConstrainSelectedInstOperands,
     /*  945538 */     // GIR_Coverage, 3884,
     /*  945538 */     GIR_EraseRootFromParent_Done,
     /*  945539 */   // Label 15080: @945539
     /*  945539 */   GIM_Try, /*On fail goto*//*Label 15081*/ GIMT_Encode4(945633), // Rule ID 3885 //
     /*  945544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  945547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  945558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  945561 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945564 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945567 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945574 */     // MIs[0] cbsz
     /*  945574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945577 */     // MIs[0] blgp
     /*  945577 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945580 */     // MIs[0] src0_modifiers
     /*  945580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945583 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945588 */     // MIs[0] src1_modifiers
     /*  945588 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945591 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945596 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945600 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  945603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945605 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945607 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945609 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945611 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945613 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945615 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945617 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945619 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945625 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945631 */     GIR_RootConstrainSelectedInstOperands,
     /*  945632 */     // GIR_Coverage, 3885,
     /*  945632 */     GIR_EraseRootFromParent_Done,
     /*  945633 */   // Label 15081: @945633
     /*  945633 */   GIM_Try, /*On fail goto*//*Label 15082*/ GIMT_Encode4(945727), // Rule ID 3886 //
     /*  945638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  945641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  945652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  945655 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945658 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945661 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945668 */     // MIs[0] cbsz
     /*  945668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945671 */     // MIs[0] blgp
     /*  945671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945674 */     // MIs[0] src0_modifiers
     /*  945674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945677 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945682 */     // MIs[0] src1_modifiers
     /*  945682 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945685 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945690 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945694 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  945697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945699 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945701 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945703 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945705 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945707 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945709 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945711 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945713 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945719 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945725 */     GIR_RootConstrainSelectedInstOperands,
     /*  945726 */     // GIR_Coverage, 3886,
     /*  945726 */     GIR_EraseRootFromParent_Done,
     /*  945727 */   // Label 15082: @945727
     /*  945727 */   GIM_Try, /*On fail goto*//*Label 15083*/ GIMT_Encode4(945821), // Rule ID 3887 //
     /*  945732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  945735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  945746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  945749 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945752 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945755 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945762 */     // MIs[0] cbsz
     /*  945762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945765 */     // MIs[0] blgp
     /*  945765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945768 */     // MIs[0] src0_modifiers
     /*  945768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945776 */     // MIs[0] src1_modifiers
     /*  945776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945779 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945784 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945788 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  945791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945793 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945795 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945797 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945799 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945801 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945803 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945805 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945807 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945813 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945819 */     GIR_RootConstrainSelectedInstOperands,
     /*  945820 */     // GIR_Coverage, 3887,
     /*  945820 */     GIR_EraseRootFromParent_Done,
     /*  945821 */   // Label 15083: @945821
     /*  945821 */   GIM_Try, /*On fail goto*//*Label 15084*/ GIMT_Encode4(945915), // Rule ID 3888 //
     /*  945826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  945829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  945840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  945843 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945846 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945849 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945856 */     // MIs[0] cbsz
     /*  945856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945859 */     // MIs[0] blgp
     /*  945859 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945862 */     // MIs[0] src0_modifiers
     /*  945862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945865 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945870 */     // MIs[0] src1_modifiers
     /*  945870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945873 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945878 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945882 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64),
     /*  945885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945887 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945889 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945891 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945893 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945895 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945897 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945899 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945901 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  945907 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  945913 */     GIR_RootConstrainSelectedInstOperands,
     /*  945914 */     // GIR_Coverage, 3888,
     /*  945914 */     GIR_EraseRootFromParent_Done,
     /*  945915 */   // Label 15084: @945915
     /*  945915 */   GIM_Try, /*On fail goto*//*Label 15085*/ GIMT_Encode4(946009), // Rule ID 3894 //
     /*  945920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  945923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  945928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  945931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  945934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  945937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  945940 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  945943 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  945946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  945950 */     // MIs[0] cbsz
     /*  945950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  945953 */     // MIs[0] blgp
     /*  945953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  945956 */     // MIs[0] src0_modifiers
     /*  945956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  945959 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945964 */     // MIs[0] src1_modifiers
     /*  945964 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  945967 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  945972 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  945976 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  945976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  945979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  945981 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  945983 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  945985 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  945987 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  945989 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  945991 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  945993 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  945995 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946001 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946007 */     GIR_RootConstrainSelectedInstOperands,
     /*  946008 */     // GIR_Coverage, 3894,
     /*  946008 */     GIR_EraseRootFromParent_Done,
     /*  946009 */   // Label 15085: @946009
     /*  946009 */   GIM_Try, /*On fail goto*//*Label 15086*/ GIMT_Encode4(946103), // Rule ID 3895 //
     /*  946014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  946017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  946022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  946025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  946028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  946031 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  946034 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946037 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  946044 */     // MIs[0] cbsz
     /*  946044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946047 */     // MIs[0] blgp
     /*  946047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946050 */     // MIs[0] src0_modifiers
     /*  946050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946053 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946058 */     // MIs[0] src1_modifiers
     /*  946058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946061 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946066 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  946070 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  946073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946075 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946077 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946079 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946081 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946083 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946085 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946087 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946089 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946095 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946101 */     GIR_RootConstrainSelectedInstOperands,
     /*  946102 */     // GIR_Coverage, 3895,
     /*  946102 */     GIR_EraseRootFromParent_Done,
     /*  946103 */   // Label 15086: @946103
     /*  946103 */   GIM_Try, /*On fail goto*//*Label 15087*/ GIMT_Encode4(946197), // Rule ID 3896 //
     /*  946108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  946111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  946116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  946119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  946122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  946125 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  946128 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946131 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  946138 */     // MIs[0] cbsz
     /*  946138 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946141 */     // MIs[0] blgp
     /*  946141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946144 */     // MIs[0] src0_modifiers
     /*  946144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946147 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946152 */     // MIs[0] src1_modifiers
     /*  946152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946155 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946160 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  946164 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  946167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946169 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946171 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946173 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946175 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946177 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946179 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946181 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946183 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946189 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946195 */     GIR_RootConstrainSelectedInstOperands,
     /*  946196 */     // GIR_Coverage, 3896,
     /*  946196 */     GIR_EraseRootFromParent_Done,
     /*  946197 */   // Label 15087: @946197
     /*  946197 */   GIM_Try, /*On fail goto*//*Label 15088*/ GIMT_Encode4(946291), // Rule ID 3897 //
     /*  946202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  946205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  946210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  946213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  946216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  946219 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  946222 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946225 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  946232 */     // MIs[0] cbsz
     /*  946232 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946235 */     // MIs[0] blgp
     /*  946235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946238 */     // MIs[0] src0_modifiers
     /*  946238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946241 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946246 */     // MIs[0] src1_modifiers
     /*  946246 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946249 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946254 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  946258 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  946261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946263 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946265 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946267 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946269 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946271 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946273 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946275 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946277 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946283 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946289 */     GIR_RootConstrainSelectedInstOperands,
     /*  946290 */     // GIR_Coverage, 3897,
     /*  946290 */     GIR_EraseRootFromParent_Done,
     /*  946291 */   // Label 15088: @946291
     /*  946291 */   GIM_Try, /*On fail goto*//*Label 15089*/ GIMT_Encode4(946385), // Rule ID 3898 //
     /*  946296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  946299 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  946304 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  946307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  946310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  946313 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  946316 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946319 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
     /*  946326 */     // MIs[0] cbsz
     /*  946326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946329 */     // MIs[0] blgp
     /*  946329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946332 */     // MIs[0] src0_modifiers
     /*  946332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946335 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946340 */     // MIs[0] src1_modifiers
     /*  946340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946343 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946348 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_31918),
     /*  946352 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)<<P:Predicate_anonymous_31918>>  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64),
     /*  946355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946357 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946359 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946361 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946363 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946365 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946367 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946369 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946371 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946377 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946383 */     GIR_RootConstrainSelectedInstOperands,
     /*  946384 */     // GIR_Coverage, 3898,
     /*  946384 */     GIR_EraseRootFromParent_Done,
     /*  946385 */   // Label 15089: @946385
     /*  946385 */   GIM_Try, /*On fail goto*//*Label 15090*/ GIMT_Encode4(946475), // Rule ID 3729 //
     /*  946390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  946393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  946407 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946410 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946413 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946416 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946420 */     // MIs[0] cbsz
     /*  946420 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946423 */     // MIs[0] blgp
     /*  946423 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946426 */     // MIs[0] src0_modifiers
     /*  946426 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946429 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946434 */     // MIs[0] src1_modifiers
     /*  946434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946437 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946442 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  946445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946447 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946449 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946451 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946453 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946455 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946457 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946459 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946461 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946467 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946473 */     GIR_RootConstrainSelectedInstOperands,
     /*  946474 */     // GIR_Coverage, 3729,
     /*  946474 */     GIR_EraseRootFromParent_Done,
     /*  946475 */   // Label 15090: @946475
     /*  946475 */   GIM_Try, /*On fail goto*//*Label 15091*/ GIMT_Encode4(946565), // Rule ID 3730 //
     /*  946480 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  946483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  946497 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946500 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946503 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946510 */     // MIs[0] cbsz
     /*  946510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946513 */     // MIs[0] blgp
     /*  946513 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946516 */     // MIs[0] src0_modifiers
     /*  946516 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946519 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946524 */     // MIs[0] src1_modifiers
     /*  946524 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946527 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946532 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  946535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946537 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946539 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946541 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946543 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946545 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946547 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946549 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946551 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946557 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946563 */     GIR_RootConstrainSelectedInstOperands,
     /*  946564 */     // GIR_Coverage, 3730,
     /*  946564 */     GIR_EraseRootFromParent_Done,
     /*  946565 */   // Label 15091: @946565
     /*  946565 */   GIM_Try, /*On fail goto*//*Label 15092*/ GIMT_Encode4(946655), // Rule ID 3731 //
     /*  946570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  946573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946578 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946581 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946584 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  946587 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946590 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946593 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946600 */     // MIs[0] cbsz
     /*  946600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946603 */     // MIs[0] blgp
     /*  946603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946606 */     // MIs[0] src0_modifiers
     /*  946606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946609 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946614 */     // MIs[0] src1_modifiers
     /*  946614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946617 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946622 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  946625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946627 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946629 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946631 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946633 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946635 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946637 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946639 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946641 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946647 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946653 */     GIR_RootConstrainSelectedInstOperands,
     /*  946654 */     // GIR_Coverage, 3731,
     /*  946654 */     GIR_EraseRootFromParent_Done,
     /*  946655 */   // Label 15092: @946655
     /*  946655 */   GIM_Try, /*On fail goto*//*Label 15093*/ GIMT_Encode4(946745), // Rule ID 3732 //
     /*  946660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  946663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  946677 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946680 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946683 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946690 */     // MIs[0] cbsz
     /*  946690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946693 */     // MIs[0] blgp
     /*  946693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946696 */     // MIs[0] src0_modifiers
     /*  946696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946699 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946704 */     // MIs[0] src1_modifiers
     /*  946704 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946707 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946712 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  946715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946717 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946719 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946721 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946723 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946725 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946727 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946729 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946731 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946737 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946743 */     GIR_RootConstrainSelectedInstOperands,
     /*  946744 */     // GIR_Coverage, 3732,
     /*  946744 */     GIR_EraseRootFromParent_Done,
     /*  946745 */   // Label 15093: @946745
     /*  946745 */   GIM_Try, /*On fail goto*//*Label 15094*/ GIMT_Encode4(946835), // Rule ID 3733 //
     /*  946750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  946753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  946767 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946770 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946773 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946780 */     // MIs[0] cbsz
     /*  946780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946783 */     // MIs[0] blgp
     /*  946783 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946786 */     // MIs[0] src0_modifiers
     /*  946786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946789 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946794 */     // MIs[0] src1_modifiers
     /*  946794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946797 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946802 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64),
     /*  946805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946807 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946809 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946811 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946813 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946815 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946817 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946819 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946821 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946827 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946833 */     GIR_RootConstrainSelectedInstOperands,
     /*  946834 */     // GIR_Coverage, 3733,
     /*  946834 */     GIR_EraseRootFromParent_Done,
     /*  946835 */   // Label 15094: @946835
     /*  946835 */   GIM_Try, /*On fail goto*//*Label 15095*/ GIMT_Encode4(946925), // Rule ID 3739 //
     /*  946840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  946843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  946857 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946860 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946863 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946870 */     // MIs[0] cbsz
     /*  946870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946873 */     // MIs[0] blgp
     /*  946873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946876 */     // MIs[0] src0_modifiers
     /*  946876 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946879 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946884 */     // MIs[0] src1_modifiers
     /*  946884 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946887 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946892 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  946895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946897 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946899 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946901 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946903 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946905 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946907 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946909 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  946911 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  946917 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  946923 */     GIR_RootConstrainSelectedInstOperands,
     /*  946924 */     // GIR_Coverage, 3739,
     /*  946924 */     GIR_EraseRootFromParent_Done,
     /*  946925 */   // Label 15095: @946925
     /*  946925 */   GIM_Try, /*On fail goto*//*Label 15096*/ GIMT_Encode4(947015), // Rule ID 3740 //
     /*  946930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  946933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  946938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  946941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  946944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  946947 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  946950 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  946953 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  946956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  946960 */     // MIs[0] cbsz
     /*  946960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  946963 */     // MIs[0] blgp
     /*  946963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  946966 */     // MIs[0] src0_modifiers
     /*  946966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  946969 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946974 */     // MIs[0] src1_modifiers
     /*  946974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  946977 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  946982 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  946982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  946985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  946987 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  946989 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  946991 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  946993 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  946995 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  946997 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  946999 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947001 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947007 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947013 */     GIR_RootConstrainSelectedInstOperands,
     /*  947014 */     // GIR_Coverage, 3740,
     /*  947014 */     GIR_EraseRootFromParent_Done,
     /*  947015 */   // Label 15096: @947015
     /*  947015 */   GIM_Try, /*On fail goto*//*Label 15097*/ GIMT_Encode4(947105), // Rule ID 3741 //
     /*  947020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  947023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  947034 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  947037 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947040 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947043 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947050 */     // MIs[0] cbsz
     /*  947050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947053 */     // MIs[0] blgp
     /*  947053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947056 */     // MIs[0] src0_modifiers
     /*  947056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947059 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947064 */     // MIs[0] src1_modifiers
     /*  947064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947067 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947072 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  947075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947077 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947079 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947081 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947083 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947085 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947087 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947089 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947091 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947097 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947103 */     GIR_RootConstrainSelectedInstOperands,
     /*  947104 */     // GIR_Coverage, 3741,
     /*  947104 */     GIR_EraseRootFromParent_Done,
     /*  947105 */   // Label 15097: @947105
     /*  947105 */   GIM_Try, /*On fail goto*//*Label 15098*/ GIMT_Encode4(947195), // Rule ID 3742 //
     /*  947110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  947113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  947124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  947127 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947130 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947133 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947140 */     // MIs[0] cbsz
     /*  947140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947143 */     // MIs[0] blgp
     /*  947143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947146 */     // MIs[0] src0_modifiers
     /*  947146 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947149 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947154 */     // MIs[0] src1_modifiers
     /*  947154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947157 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947162 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  947165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947167 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947169 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947171 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947173 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947175 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947177 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947179 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947181 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947187 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947193 */     GIR_RootConstrainSelectedInstOperands,
     /*  947194 */     // GIR_Coverage, 3742,
     /*  947194 */     GIR_EraseRootFromParent_Done,
     /*  947195 */   // Label 15098: @947195
     /*  947195 */   GIM_Try, /*On fail goto*//*Label 15099*/ GIMT_Encode4(947285), // Rule ID 3743 //
     /*  947200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  947203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  947214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  947217 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947220 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947223 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947230 */     // MIs[0] cbsz
     /*  947230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947233 */     // MIs[0] blgp
     /*  947233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947236 */     // MIs[0] src0_modifiers
     /*  947236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947239 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947244 */     // MIs[0] src1_modifiers
     /*  947244 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947247 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947252 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64),
     /*  947255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947257 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947259 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947261 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947263 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947265 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947267 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947269 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947271 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947277 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947283 */     GIR_RootConstrainSelectedInstOperands,
     /*  947284 */     // GIR_Coverage, 3743,
     /*  947284 */     GIR_EraseRootFromParent_Done,
     /*  947285 */   // Label 15099: @947285
     /*  947285 */   GIM_Try, /*On fail goto*//*Label 15100*/ GIMT_Encode4(947375), // Rule ID 3749 //
     /*  947290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  947293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  947307 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947310 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947313 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947320 */     // MIs[0] cbsz
     /*  947320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947323 */     // MIs[0] blgp
     /*  947323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947326 */     // MIs[0] src0_modifiers
     /*  947326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947329 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947334 */     // MIs[0] src1_modifiers
     /*  947334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947337 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947342 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  947345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947347 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947349 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947351 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947353 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947355 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947357 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947359 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947361 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947367 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947373 */     GIR_RootConstrainSelectedInstOperands,
     /*  947374 */     // GIR_Coverage, 3749,
     /*  947374 */     GIR_EraseRootFromParent_Done,
     /*  947375 */   // Label 15100: @947375
     /*  947375 */   GIM_Try, /*On fail goto*//*Label 15101*/ GIMT_Encode4(947465), // Rule ID 3750 //
     /*  947380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  947383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  947397 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947400 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947403 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947410 */     // MIs[0] cbsz
     /*  947410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947413 */     // MIs[0] blgp
     /*  947413 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947416 */     // MIs[0] src0_modifiers
     /*  947416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947419 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947424 */     // MIs[0] src1_modifiers
     /*  947424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947427 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947432 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  947435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947437 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947439 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947441 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947443 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947445 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947447 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947449 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947451 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947457 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947463 */     GIR_RootConstrainSelectedInstOperands,
     /*  947464 */     // GIR_Coverage, 3750,
     /*  947464 */     GIR_EraseRootFromParent_Done,
     /*  947465 */   // Label 15101: @947465
     /*  947465 */   GIM_Try, /*On fail goto*//*Label 15102*/ GIMT_Encode4(947555), // Rule ID 3751 //
     /*  947470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  947473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  947487 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947490 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947493 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947500 */     // MIs[0] cbsz
     /*  947500 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947503 */     // MIs[0] blgp
     /*  947503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947506 */     // MIs[0] src0_modifiers
     /*  947506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947509 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947514 */     // MIs[0] src1_modifiers
     /*  947514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947517 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947522 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  947525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947527 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947529 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947531 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947533 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947535 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947537 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947539 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947541 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947547 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947553 */     GIR_RootConstrainSelectedInstOperands,
     /*  947554 */     // GIR_Coverage, 3751,
     /*  947554 */     GIR_EraseRootFromParent_Done,
     /*  947555 */   // Label 15102: @947555
     /*  947555 */   GIM_Try, /*On fail goto*//*Label 15103*/ GIMT_Encode4(947645), // Rule ID 3752 //
     /*  947560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  947563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  947577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947580 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947583 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947590 */     // MIs[0] cbsz
     /*  947590 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947593 */     // MIs[0] blgp
     /*  947593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947596 */     // MIs[0] src0_modifiers
     /*  947596 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947599 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947604 */     // MIs[0] src1_modifiers
     /*  947604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947607 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947612 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  947615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947617 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947619 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947621 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947623 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947625 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947627 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947629 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947631 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947637 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947643 */     GIR_RootConstrainSelectedInstOperands,
     /*  947644 */     // GIR_Coverage, 3752,
     /*  947644 */     GIR_EraseRootFromParent_Done,
     /*  947645 */   // Label 15103: @947645
     /*  947645 */   GIM_Try, /*On fail goto*//*Label 15104*/ GIMT_Encode4(947735), // Rule ID 3753 //
     /*  947650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  947653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  947667 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947670 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947673 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947680 */     // MIs[0] cbsz
     /*  947680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947683 */     // MIs[0] blgp
     /*  947683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947686 */     // MIs[0] src0_modifiers
     /*  947686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947689 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947694 */     // MIs[0] src1_modifiers
     /*  947694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947697 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947702 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64),
     /*  947705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947707 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947709 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947711 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947713 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947715 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947717 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947719 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947721 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947727 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947733 */     GIR_RootConstrainSelectedInstOperands,
     /*  947734 */     // GIR_Coverage, 3753,
     /*  947734 */     GIR_EraseRootFromParent_Done,
     /*  947735 */   // Label 15104: @947735
     /*  947735 */   GIM_Try, /*On fail goto*//*Label 15105*/ GIMT_Encode4(947825), // Rule ID 3759 //
     /*  947740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  947743 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947748 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947751 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947754 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  947757 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947760 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947763 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947770 */     // MIs[0] cbsz
     /*  947770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947773 */     // MIs[0] blgp
     /*  947773 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947776 */     // MIs[0] src0_modifiers
     /*  947776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947779 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947784 */     // MIs[0] src1_modifiers
     /*  947784 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947787 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947792 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  947795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947797 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947799 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947801 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947803 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947805 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947807 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947809 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947811 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947817 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947823 */     GIR_RootConstrainSelectedInstOperands,
     /*  947824 */     // GIR_Coverage, 3759,
     /*  947824 */     GIR_EraseRootFromParent_Done,
     /*  947825 */   // Label 15105: @947825
     /*  947825 */   GIM_Try, /*On fail goto*//*Label 15106*/ GIMT_Encode4(947915), // Rule ID 3760 //
     /*  947830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  947833 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947838 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947841 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947844 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  947847 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947850 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947853 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947860 */     // MIs[0] cbsz
     /*  947860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947863 */     // MIs[0] blgp
     /*  947863 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947866 */     // MIs[0] src0_modifiers
     /*  947866 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947869 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947874 */     // MIs[0] src1_modifiers
     /*  947874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947877 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947882 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  947885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947887 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947889 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947891 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947893 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947895 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947897 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947899 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947901 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947907 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  947913 */     GIR_RootConstrainSelectedInstOperands,
     /*  947914 */     // GIR_Coverage, 3760,
     /*  947914 */     GIR_EraseRootFromParent_Done,
     /*  947915 */   // Label 15106: @947915
     /*  947915 */   GIM_Try, /*On fail goto*//*Label 15107*/ GIMT_Encode4(948005), // Rule ID 3761 //
     /*  947920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  947923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  947928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  947931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  947934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  947937 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  947940 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  947943 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  947946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  947950 */     // MIs[0] cbsz
     /*  947950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  947953 */     // MIs[0] blgp
     /*  947953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  947956 */     // MIs[0] src0_modifiers
     /*  947956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  947959 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947964 */     // MIs[0] src1_modifiers
     /*  947964 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  947967 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  947972 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  947972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  947975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  947977 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  947979 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  947981 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  947983 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  947985 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  947987 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  947989 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  947991 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  947997 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948003 */     GIR_RootConstrainSelectedInstOperands,
     /*  948004 */     // GIR_Coverage, 3761,
     /*  948004 */     GIR_EraseRootFromParent_Done,
     /*  948005 */   // Label 15107: @948005
     /*  948005 */   GIM_Try, /*On fail goto*//*Label 15108*/ GIMT_Encode4(948095), // Rule ID 3762 //
     /*  948010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  948013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  948024 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  948027 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948030 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948033 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948040 */     // MIs[0] cbsz
     /*  948040 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948043 */     // MIs[0] blgp
     /*  948043 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948046 */     // MIs[0] src0_modifiers
     /*  948046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948049 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948054 */     // MIs[0] src1_modifiers
     /*  948054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948057 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948062 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  948065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948067 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948069 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948071 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948073 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948075 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948077 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948079 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948081 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948087 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948093 */     GIR_RootConstrainSelectedInstOperands,
     /*  948094 */     // GIR_Coverage, 3762,
     /*  948094 */     GIR_EraseRootFromParent_Done,
     /*  948095 */   // Label 15108: @948095
     /*  948095 */   GIM_Try, /*On fail goto*//*Label 15109*/ GIMT_Encode4(948185), // Rule ID 3763 //
     /*  948100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  948103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  948114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  948117 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948120 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948123 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948130 */     // MIs[0] cbsz
     /*  948130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948133 */     // MIs[0] blgp
     /*  948133 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948136 */     // MIs[0] src0_modifiers
     /*  948136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948139 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948144 */     // MIs[0] src1_modifiers
     /*  948144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948147 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948152 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64),
     /*  948155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948157 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948159 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948161 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948163 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948165 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948167 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948169 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948171 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948177 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948183 */     GIR_RootConstrainSelectedInstOperands,
     /*  948184 */     // GIR_Coverage, 3763,
     /*  948184 */     GIR_EraseRootFromParent_Done,
     /*  948185 */   // Label 15109: @948185
     /*  948185 */   GIM_Try, /*On fail goto*//*Label 15110*/ GIMT_Encode4(948275), // Rule ID 3769 //
     /*  948190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  948193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  948204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  948207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948210 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948213 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948220 */     // MIs[0] cbsz
     /*  948220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948223 */     // MIs[0] blgp
     /*  948223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948226 */     // MIs[0] src0_modifiers
     /*  948226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948229 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948234 */     // MIs[0] src1_modifiers
     /*  948234 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948237 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948242 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  948245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948247 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948249 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948251 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948253 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948255 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948257 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948259 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948261 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948267 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948273 */     GIR_RootConstrainSelectedInstOperands,
     /*  948274 */     // GIR_Coverage, 3769,
     /*  948274 */     GIR_EraseRootFromParent_Done,
     /*  948275 */   // Label 15110: @948275
     /*  948275 */   GIM_Try, /*On fail goto*//*Label 15111*/ GIMT_Encode4(948365), // Rule ID 3770 //
     /*  948280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  948283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  948294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  948297 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948300 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948303 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948310 */     // MIs[0] cbsz
     /*  948310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948313 */     // MIs[0] blgp
     /*  948313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948316 */     // MIs[0] src0_modifiers
     /*  948316 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948319 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948324 */     // MIs[0] src1_modifiers
     /*  948324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948327 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948332 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  948335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948337 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948339 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948341 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948343 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948345 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948347 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948349 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948351 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948357 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948363 */     GIR_RootConstrainSelectedInstOperands,
     /*  948364 */     // GIR_Coverage, 3770,
     /*  948364 */     GIR_EraseRootFromParent_Done,
     /*  948365 */   // Label 15111: @948365
     /*  948365 */   GIM_Try, /*On fail goto*//*Label 15112*/ GIMT_Encode4(948455), // Rule ID 3771 //
     /*  948370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  948373 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948378 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948381 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  948384 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  948387 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948390 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948393 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948396 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948400 */     // MIs[0] cbsz
     /*  948400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948403 */     // MIs[0] blgp
     /*  948403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948406 */     // MIs[0] src0_modifiers
     /*  948406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948409 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948414 */     // MIs[0] src1_modifiers
     /*  948414 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948417 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948422 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  948425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948427 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948429 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948431 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948433 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948435 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948437 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948439 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948441 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948447 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948453 */     GIR_RootConstrainSelectedInstOperands,
     /*  948454 */     // GIR_Coverage, 3771,
     /*  948454 */     GIR_EraseRootFromParent_Done,
     /*  948455 */   // Label 15112: @948455
     /*  948455 */   GIM_Try, /*On fail goto*//*Label 15113*/ GIMT_Encode4(948545), // Rule ID 3772 //
     /*  948460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  948463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  948474 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  948477 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948480 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948483 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948490 */     // MIs[0] cbsz
     /*  948490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948493 */     // MIs[0] blgp
     /*  948493 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948496 */     // MIs[0] src0_modifiers
     /*  948496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948499 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948504 */     // MIs[0] src1_modifiers
     /*  948504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948507 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948512 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  948515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948517 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948519 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948521 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948523 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948525 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948527 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948529 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948531 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948537 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948543 */     GIR_RootConstrainSelectedInstOperands,
     /*  948544 */     // GIR_Coverage, 3772,
     /*  948544 */     GIR_EraseRootFromParent_Done,
     /*  948545 */   // Label 15113: @948545
     /*  948545 */   GIM_Try, /*On fail goto*//*Label 15114*/ GIMT_Encode4(948635), // Rule ID 3773 //
     /*  948550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  948553 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948558 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948561 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  948564 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  948567 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948570 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948573 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948580 */     // MIs[0] cbsz
     /*  948580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948583 */     // MIs[0] blgp
     /*  948583 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948586 */     // MIs[0] src0_modifiers
     /*  948586 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948589 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948594 */     // MIs[0] src1_modifiers
     /*  948594 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948597 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948602 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64:{ *:[v4f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64),
     /*  948605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948607 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948609 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948611 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948613 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948615 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948617 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948619 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948621 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948627 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948633 */     GIR_RootConstrainSelectedInstOperands,
     /*  948634 */     // GIR_Coverage, 3773,
     /*  948634 */     GIR_EraseRootFromParent_Done,
     /*  948635 */   // Label 15114: @948635
     /*  948635 */   GIM_Try, /*On fail goto*//*Label 15115*/ GIMT_Encode4(948725), // Rule ID 3779 //
     /*  948640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  948643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  948654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  948657 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948660 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948663 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948670 */     // MIs[0] cbsz
     /*  948670 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948673 */     // MIs[0] blgp
     /*  948673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948676 */     // MIs[0] src0_modifiers
     /*  948676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948679 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948684 */     // MIs[0] src1_modifiers
     /*  948684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948687 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948692 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  948695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948697 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948699 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948701 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948703 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948705 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948707 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948709 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948711 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948717 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948723 */     GIR_RootConstrainSelectedInstOperands,
     /*  948724 */     // GIR_Coverage, 3779,
     /*  948724 */     GIR_EraseRootFromParent_Done,
     /*  948725 */   // Label 15115: @948725
     /*  948725 */   GIM_Try, /*On fail goto*//*Label 15116*/ GIMT_Encode4(948815), // Rule ID 3780 //
     /*  948730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  948733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  948744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  948747 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948750 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948753 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948760 */     // MIs[0] cbsz
     /*  948760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948763 */     // MIs[0] blgp
     /*  948763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948766 */     // MIs[0] src0_modifiers
     /*  948766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948769 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948774 */     // MIs[0] src1_modifiers
     /*  948774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948777 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948782 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  948785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948787 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948789 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948791 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948793 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948795 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948797 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948799 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948801 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948807 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948813 */     GIR_RootConstrainSelectedInstOperands,
     /*  948814 */     // GIR_Coverage, 3780,
     /*  948814 */     GIR_EraseRootFromParent_Done,
     /*  948815 */   // Label 15116: @948815
     /*  948815 */   GIM_Try, /*On fail goto*//*Label 15117*/ GIMT_Encode4(948905), // Rule ID 3781 //
     /*  948820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  948823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  948834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  948837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948840 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948843 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948850 */     // MIs[0] cbsz
     /*  948850 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948853 */     // MIs[0] blgp
     /*  948853 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948856 */     // MIs[0] src0_modifiers
     /*  948856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948859 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948864 */     // MIs[0] src1_modifiers
     /*  948864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948867 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948872 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  948875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948877 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948879 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948881 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948883 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948885 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948887 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948889 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948891 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948897 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948903 */     GIR_RootConstrainSelectedInstOperands,
     /*  948904 */     // GIR_Coverage, 3781,
     /*  948904 */     GIR_EraseRootFromParent_Done,
     /*  948905 */   // Label 15117: @948905
     /*  948905 */   GIM_Try, /*On fail goto*//*Label 15118*/ GIMT_Encode4(948995), // Rule ID 3782 //
     /*  948910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  948913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  948918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  948921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  948924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  948927 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  948930 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  948933 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  948936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  948940 */     // MIs[0] cbsz
     /*  948940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  948943 */     // MIs[0] blgp
     /*  948943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  948946 */     // MIs[0] src0_modifiers
     /*  948946 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  948949 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948954 */     // MIs[0] src1_modifiers
     /*  948954 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  948957 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  948962 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  948962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  948965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  948967 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  948969 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  948971 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  948973 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  948975 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  948977 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  948979 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  948981 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  948987 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  948993 */     GIR_RootConstrainSelectedInstOperands,
     /*  948994 */     // GIR_Coverage, 3782,
     /*  948994 */     GIR_EraseRootFromParent_Done,
     /*  948995 */   // Label 15118: @948995
     /*  948995 */   GIM_Try, /*On fail goto*//*Label 15119*/ GIMT_Encode4(949085), // Rule ID 3783 //
     /*  949000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  949003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949011 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  949014 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  949017 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949020 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949023 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949030 */     // MIs[0] cbsz
     /*  949030 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949033 */     // MIs[0] blgp
     /*  949033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949036 */     // MIs[0] src0_modifiers
     /*  949036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949039 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949044 */     // MIs[0] src1_modifiers
     /*  949044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949047 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949052 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64),
     /*  949055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949057 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949059 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949061 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949063 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949065 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949067 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949069 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949071 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949077 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949083 */     GIR_RootConstrainSelectedInstOperands,
     /*  949084 */     // GIR_Coverage, 3783,
     /*  949084 */     GIR_EraseRootFromParent_Done,
     /*  949085 */   // Label 15119: @949085
     /*  949085 */   GIM_Try, /*On fail goto*//*Label 15120*/ GIMT_Encode4(949175), // Rule ID 3789 //
     /*  949090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  949093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  949104 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  949107 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949110 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949113 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949120 */     // MIs[0] cbsz
     /*  949120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949123 */     // MIs[0] blgp
     /*  949123 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949126 */     // MIs[0] src0_modifiers
     /*  949126 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949129 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949134 */     // MIs[0] src1_modifiers
     /*  949134 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949137 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949142 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  949145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949147 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949149 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949151 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949153 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949155 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949157 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949159 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949161 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949167 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949173 */     GIR_RootConstrainSelectedInstOperands,
     /*  949174 */     // GIR_Coverage, 3789,
     /*  949174 */     GIR_EraseRootFromParent_Done,
     /*  949175 */   // Label 15120: @949175
     /*  949175 */   GIM_Try, /*On fail goto*//*Label 15121*/ GIMT_Encode4(949265), // Rule ID 3790 //
     /*  949180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  949183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  949194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  949197 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949200 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949203 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949210 */     // MIs[0] cbsz
     /*  949210 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949213 */     // MIs[0] blgp
     /*  949213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949216 */     // MIs[0] src0_modifiers
     /*  949216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949219 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949224 */     // MIs[0] src1_modifiers
     /*  949224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949227 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949232 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  949235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949237 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949239 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949241 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949243 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949245 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949247 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949249 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949251 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949257 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949263 */     GIR_RootConstrainSelectedInstOperands,
     /*  949264 */     // GIR_Coverage, 3790,
     /*  949264 */     GIR_EraseRootFromParent_Done,
     /*  949265 */   // Label 15121: @949265
     /*  949265 */   GIM_Try, /*On fail goto*//*Label 15122*/ GIMT_Encode4(949355), // Rule ID 3791 //
     /*  949270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  949273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  949284 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  949287 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949290 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949293 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949300 */     // MIs[0] cbsz
     /*  949300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949303 */     // MIs[0] blgp
     /*  949303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949306 */     // MIs[0] src0_modifiers
     /*  949306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949309 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949314 */     // MIs[0] src1_modifiers
     /*  949314 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949317 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949322 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  949325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949327 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949329 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949331 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949333 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949335 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949337 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949339 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949341 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949347 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949353 */     GIR_RootConstrainSelectedInstOperands,
     /*  949354 */     // GIR_Coverage, 3791,
     /*  949354 */     GIR_EraseRootFromParent_Done,
     /*  949355 */   // Label 15122: @949355
     /*  949355 */   GIM_Try, /*On fail goto*//*Label 15123*/ GIMT_Encode4(949445), // Rule ID 3792 //
     /*  949360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  949363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  949374 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  949377 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949380 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949383 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949390 */     // MIs[0] cbsz
     /*  949390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949393 */     // MIs[0] blgp
     /*  949393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949396 */     // MIs[0] src0_modifiers
     /*  949396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949399 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949404 */     // MIs[0] src1_modifiers
     /*  949404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949407 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949412 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  949415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949417 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949419 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949421 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949423 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949425 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949427 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949429 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949431 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949437 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949443 */     GIR_RootConstrainSelectedInstOperands,
     /*  949444 */     // GIR_Coverage, 3792,
     /*  949444 */     GIR_EraseRootFromParent_Done,
     /*  949445 */   // Label 15123: @949445
     /*  949445 */   GIM_Try, /*On fail goto*//*Label 15124*/ GIMT_Encode4(949535), // Rule ID 3793 //
     /*  949450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  949453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  949464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  949467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949470 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949473 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949480 */     // MIs[0] cbsz
     /*  949480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949483 */     // MIs[0] blgp
     /*  949483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949486 */     // MIs[0] src0_modifiers
     /*  949486 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949489 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949494 */     // MIs[0] src1_modifiers
     /*  949494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949497 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949502 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64:{ *:[v4f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64),
     /*  949505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949507 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949509 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949511 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949513 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949515 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949517 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949519 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949521 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949527 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949533 */     GIR_RootConstrainSelectedInstOperands,
     /*  949534 */     // GIR_Coverage, 3793,
     /*  949534 */     GIR_EraseRootFromParent_Done,
     /*  949535 */   // Label 15124: @949535
     /*  949535 */   GIM_Try, /*On fail goto*//*Label 15125*/ GIMT_Encode4(949625), // Rule ID 3799 //
     /*  949540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  949543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  949554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  949557 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949560 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949563 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949570 */     // MIs[0] cbsz
     /*  949570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949573 */     // MIs[0] blgp
     /*  949573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949576 */     // MIs[0] src0_modifiers
     /*  949576 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949579 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949584 */     // MIs[0] src1_modifiers
     /*  949584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949587 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949592 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  949595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949597 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949599 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949601 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949603 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949605 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949607 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949609 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949611 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949617 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949623 */     GIR_RootConstrainSelectedInstOperands,
     /*  949624 */     // GIR_Coverage, 3799,
     /*  949624 */     GIR_EraseRootFromParent_Done,
     /*  949625 */   // Label 15125: @949625
     /*  949625 */   GIM_Try, /*On fail goto*//*Label 15126*/ GIMT_Encode4(949715), // Rule ID 3800 //
     /*  949630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  949633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  949644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  949647 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949650 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949653 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949660 */     // MIs[0] cbsz
     /*  949660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949663 */     // MIs[0] blgp
     /*  949663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949666 */     // MIs[0] src0_modifiers
     /*  949666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949669 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949674 */     // MIs[0] src1_modifiers
     /*  949674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949677 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949682 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  949685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949687 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949689 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949691 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949693 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949695 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949697 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949699 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949701 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949707 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949713 */     GIR_RootConstrainSelectedInstOperands,
     /*  949714 */     // GIR_Coverage, 3800,
     /*  949714 */     GIR_EraseRootFromParent_Done,
     /*  949715 */   // Label 15126: @949715
     /*  949715 */   GIM_Try, /*On fail goto*//*Label 15127*/ GIMT_Encode4(949805), // Rule ID 3801 //
     /*  949720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  949723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  949734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  949737 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949740 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949743 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949750 */     // MIs[0] cbsz
     /*  949750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949753 */     // MIs[0] blgp
     /*  949753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949756 */     // MIs[0] src0_modifiers
     /*  949756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949759 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949764 */     // MIs[0] src1_modifiers
     /*  949764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949767 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949772 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  949775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949777 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949779 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949781 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949783 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949785 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949787 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949789 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949791 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949797 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949803 */     GIR_RootConstrainSelectedInstOperands,
     /*  949804 */     // GIR_Coverage, 3801,
     /*  949804 */     GIR_EraseRootFromParent_Done,
     /*  949805 */   // Label 15127: @949805
     /*  949805 */   GIM_Try, /*On fail goto*//*Label 15128*/ GIMT_Encode4(949895), // Rule ID 3802 //
     /*  949810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  949813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  949824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  949827 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949830 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949833 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949840 */     // MIs[0] cbsz
     /*  949840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949843 */     // MIs[0] blgp
     /*  949843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949846 */     // MIs[0] src0_modifiers
     /*  949846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949849 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949854 */     // MIs[0] src1_modifiers
     /*  949854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949857 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949862 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  949865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949867 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949869 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949871 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949873 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949875 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949877 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949879 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949881 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949887 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949893 */     GIR_RootConstrainSelectedInstOperands,
     /*  949894 */     // GIR_Coverage, 3802,
     /*  949894 */     GIR_EraseRootFromParent_Done,
     /*  949895 */   // Label 15128: @949895
     /*  949895 */   GIM_Try, /*On fail goto*//*Label 15129*/ GIMT_Encode4(949985), // Rule ID 3803 //
     /*  949900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  949903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949908 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  949911 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  949914 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  949917 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  949920 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  949923 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  949926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  949930 */     // MIs[0] cbsz
     /*  949930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  949933 */     // MIs[0] blgp
     /*  949933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  949936 */     // MIs[0] src0_modifiers
     /*  949936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  949939 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949944 */     // MIs[0] src1_modifiers
     /*  949944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  949947 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  949952 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  949952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64),
     /*  949955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  949957 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  949959 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  949961 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  949963 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  949965 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  949967 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  949969 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  949971 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  949977 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  949983 */     GIR_RootConstrainSelectedInstOperands,
     /*  949984 */     // GIR_Coverage, 3803,
     /*  949984 */     GIR_EraseRootFromParent_Done,
     /*  949985 */   // Label 15129: @949985
     /*  949985 */   GIM_Try, /*On fail goto*//*Label 15130*/ GIMT_Encode4(950075), // Rule ID 3809 //
     /*  949990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  949993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  949998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  950001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  950004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  950007 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  950010 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950013 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  950020 */     // MIs[0] cbsz
     /*  950020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950023 */     // MIs[0] blgp
     /*  950023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950026 */     // MIs[0] src0_modifiers
     /*  950026 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950029 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950034 */     // MIs[0] src1_modifiers
     /*  950034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950037 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950042 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  950045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950047 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950049 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950051 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950053 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950055 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950057 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950059 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950061 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950067 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950073 */     GIR_RootConstrainSelectedInstOperands,
     /*  950074 */     // GIR_Coverage, 3809,
     /*  950074 */     GIR_EraseRootFromParent_Done,
     /*  950075 */   // Label 15130: @950075
     /*  950075 */   GIM_Try, /*On fail goto*//*Label 15131*/ GIMT_Encode4(950165), // Rule ID 3810 //
     /*  950080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  950083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  950088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  950091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  950094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  950097 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  950100 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950103 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  950110 */     // MIs[0] cbsz
     /*  950110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950113 */     // MIs[0] blgp
     /*  950113 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950116 */     // MIs[0] src0_modifiers
     /*  950116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950119 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950124 */     // MIs[0] src1_modifiers
     /*  950124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950127 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950132 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  950135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950137 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950139 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950141 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950143 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950145 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950147 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950149 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950151 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950157 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950163 */     GIR_RootConstrainSelectedInstOperands,
     /*  950164 */     // GIR_Coverage, 3810,
     /*  950164 */     GIR_EraseRootFromParent_Done,
     /*  950165 */   // Label 15131: @950165
     /*  950165 */   GIM_Try, /*On fail goto*//*Label 15132*/ GIMT_Encode4(950255), // Rule ID 3811 //
     /*  950170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  950173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  950178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  950181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  950184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  950187 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  950190 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950193 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950196 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  950200 */     // MIs[0] cbsz
     /*  950200 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950203 */     // MIs[0] blgp
     /*  950203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950206 */     // MIs[0] src0_modifiers
     /*  950206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950209 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950214 */     // MIs[0] src1_modifiers
     /*  950214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950217 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950222 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  950225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950229 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950231 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950233 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950235 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950237 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950239 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950241 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950247 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950253 */     GIR_RootConstrainSelectedInstOperands,
     /*  950254 */     // GIR_Coverage, 3811,
     /*  950254 */     GIR_EraseRootFromParent_Done,
     /*  950255 */   // Label 15132: @950255
     /*  950255 */   GIM_Try, /*On fail goto*//*Label 15133*/ GIMT_Encode4(950345), // Rule ID 3812 //
     /*  950260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  950263 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  950268 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  950271 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  950274 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  950277 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  950280 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950283 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  950290 */     // MIs[0] cbsz
     /*  950290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950293 */     // MIs[0] blgp
     /*  950293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950296 */     // MIs[0] src0_modifiers
     /*  950296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950299 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950304 */     // MIs[0] src1_modifiers
     /*  950304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950307 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950312 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  950315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950317 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950319 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950321 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950323 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950325 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950327 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950329 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950331 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950337 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950343 */     GIR_RootConstrainSelectedInstOperands,
     /*  950344 */     // GIR_Coverage, 3812,
     /*  950344 */     GIR_EraseRootFromParent_Done,
     /*  950345 */   // Label 15133: @950345
     /*  950345 */   GIM_Try, /*On fail goto*//*Label 15134*/ GIMT_Encode4(950435), // Rule ID 3813 //
     /*  950350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  950353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_16x16x128_f8f6f4),
     /*  950358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  950361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  950364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  950367 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  950370 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950373 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  950380 */     // MIs[0] cbsz
     /*  950380 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950383 */     // MIs[0] blgp
     /*  950383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950386 */     // MIs[0] src0_modifiers
     /*  950386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950389 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950394 */     // MIs[0] src1_modifiers
     /*  950394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950397 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950402 */     // (intrinsic_wo_chain:{ *:[v4f32] } 3326:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64),
     /*  950405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950407 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950409 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950411 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950413 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950415 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950417 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950419 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950421 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950427 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950433 */     GIR_RootConstrainSelectedInstOperands,
     /*  950434 */     // GIR_Coverage, 3813,
     /*  950434 */     GIR_EraseRootFromParent_Done,
     /*  950435 */   // Label 15134: @950435
     /*  950435 */   GIM_Try, /*On fail goto*//*Label 15135*/ GIMT_Encode4(950525), // Rule ID 3819 //
     /*  950440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  950443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  950457 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  950460 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950463 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  950470 */     // MIs[0] cbsz
     /*  950470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950473 */     // MIs[0] blgp
     /*  950473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950476 */     // MIs[0] src0_modifiers
     /*  950476 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950479 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950484 */     // MIs[0] src1_modifiers
     /*  950484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950487 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950492 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  950495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950497 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950499 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950501 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950503 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950505 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950507 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950509 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950511 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950517 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950523 */     GIR_RootConstrainSelectedInstOperands,
     /*  950524 */     // GIR_Coverage, 3819,
     /*  950524 */     GIR_EraseRootFromParent_Done,
     /*  950525 */   // Label 15135: @950525
     /*  950525 */   GIM_Try, /*On fail goto*//*Label 15136*/ GIMT_Encode4(950615), // Rule ID 3820 //
     /*  950530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  950533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950544 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  950547 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  950550 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950553 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  950560 */     // MIs[0] cbsz
     /*  950560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950563 */     // MIs[0] blgp
     /*  950563 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950566 */     // MIs[0] src0_modifiers
     /*  950566 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950569 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950574 */     // MIs[0] src1_modifiers
     /*  950574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950577 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950582 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  950585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950587 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950589 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950591 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950593 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950595 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950597 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950599 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950601 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950607 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950613 */     GIR_RootConstrainSelectedInstOperands,
     /*  950614 */     // GIR_Coverage, 3820,
     /*  950614 */     GIR_EraseRootFromParent_Done,
     /*  950615 */   // Label 15136: @950615
     /*  950615 */   GIM_Try, /*On fail goto*//*Label 15137*/ GIMT_Encode4(950705), // Rule ID 3821 //
     /*  950620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  950623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  950637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  950640 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950643 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  950650 */     // MIs[0] cbsz
     /*  950650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950653 */     // MIs[0] blgp
     /*  950653 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950656 */     // MIs[0] src0_modifiers
     /*  950656 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950659 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950664 */     // MIs[0] src1_modifiers
     /*  950664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950667 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950672 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  950675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950677 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950679 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950681 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950683 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950685 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950687 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950689 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950691 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950697 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950703 */     GIR_RootConstrainSelectedInstOperands,
     /*  950704 */     // GIR_Coverage, 3821,
     /*  950704 */     GIR_EraseRootFromParent_Done,
     /*  950705 */   // Label 15137: @950705
     /*  950705 */   GIM_Try, /*On fail goto*//*Label 15138*/ GIMT_Encode4(950795), // Rule ID 3822 //
     /*  950710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  950713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  950727 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  950730 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950733 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  950740 */     // MIs[0] cbsz
     /*  950740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950743 */     // MIs[0] blgp
     /*  950743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950746 */     // MIs[0] src0_modifiers
     /*  950746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950749 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950754 */     // MIs[0] src1_modifiers
     /*  950754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950757 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950762 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  950765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950767 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950769 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950771 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950773 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950775 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950777 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950779 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950781 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950787 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950793 */     GIR_RootConstrainSelectedInstOperands,
     /*  950794 */     // GIR_Coverage, 3822,
     /*  950794 */     GIR_EraseRootFromParent_Done,
     /*  950795 */   // Label 15138: @950795
     /*  950795 */   GIM_Try, /*On fail goto*//*Label 15139*/ GIMT_Encode4(950885), // Rule ID 3823 //
     /*  950800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  950803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  950817 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  950820 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950823 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950826 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  950830 */     // MIs[0] cbsz
     /*  950830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950833 */     // MIs[0] blgp
     /*  950833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950836 */     // MIs[0] src0_modifiers
     /*  950836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950839 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950844 */     // MIs[0] src1_modifiers
     /*  950844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950847 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950852 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64),
     /*  950855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950857 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950859 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950861 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950863 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950865 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950867 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950869 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950871 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950877 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950883 */     GIR_RootConstrainSelectedInstOperands,
     /*  950884 */     // GIR_Coverage, 3823,
     /*  950884 */     GIR_EraseRootFromParent_Done,
     /*  950885 */   // Label 15139: @950885
     /*  950885 */   GIM_Try, /*On fail goto*//*Label 15140*/ GIMT_Encode4(950975), // Rule ID 3829 //
     /*  950890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  950893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  950907 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  950910 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  950913 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  950916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  950920 */     // MIs[0] cbsz
     /*  950920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  950923 */     // MIs[0] blgp
     /*  950923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  950926 */     // MIs[0] src0_modifiers
     /*  950926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  950929 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950934 */     // MIs[0] src1_modifiers
     /*  950934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  950937 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  950942 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  950942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  950945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  950947 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  950949 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  950951 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  950953 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  950955 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  950957 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  950959 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  950961 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  950967 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  950973 */     GIR_RootConstrainSelectedInstOperands,
     /*  950974 */     // GIR_Coverage, 3829,
     /*  950974 */     GIR_EraseRootFromParent_Done,
     /*  950975 */   // Label 15140: @950975
     /*  950975 */   GIM_Try, /*On fail goto*//*Label 15141*/ GIMT_Encode4(951065), // Rule ID 3830 //
     /*  950980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  950983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  950988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  950991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  950994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  950997 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951000 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951003 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951010 */     // MIs[0] cbsz
     /*  951010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951013 */     // MIs[0] blgp
     /*  951013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951016 */     // MIs[0] src0_modifiers
     /*  951016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951019 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951024 */     // MIs[0] src1_modifiers
     /*  951024 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951027 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951032 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  951035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951037 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951039 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951041 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951043 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951045 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951047 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951049 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951051 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951057 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951063 */     GIR_RootConstrainSelectedInstOperands,
     /*  951064 */     // GIR_Coverage, 3830,
     /*  951064 */     GIR_EraseRootFromParent_Done,
     /*  951065 */   // Label 15141: @951065
     /*  951065 */   GIM_Try, /*On fail goto*//*Label 15142*/ GIMT_Encode4(951155), // Rule ID 3831 //
     /*  951070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  951073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  951084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  951087 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951090 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951093 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951100 */     // MIs[0] cbsz
     /*  951100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951103 */     // MIs[0] blgp
     /*  951103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951106 */     // MIs[0] src0_modifiers
     /*  951106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951109 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951114 */     // MIs[0] src1_modifiers
     /*  951114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951117 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951122 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  951125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951127 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951129 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951131 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951133 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951135 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951137 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951139 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951141 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951147 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951153 */     GIR_RootConstrainSelectedInstOperands,
     /*  951154 */     // GIR_Coverage, 3831,
     /*  951154 */     GIR_EraseRootFromParent_Done,
     /*  951155 */   // Label 15142: @951155
     /*  951155 */   GIM_Try, /*On fail goto*//*Label 15143*/ GIMT_Encode4(951245), // Rule ID 3832 //
     /*  951160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  951163 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951168 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951171 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  951174 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  951177 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951180 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951183 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951190 */     // MIs[0] cbsz
     /*  951190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951193 */     // MIs[0] blgp
     /*  951193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951196 */     // MIs[0] src0_modifiers
     /*  951196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951199 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951204 */     // MIs[0] src1_modifiers
     /*  951204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951207 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951212 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  951215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951217 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951219 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951221 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951223 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951225 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951227 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951229 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951231 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951237 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951243 */     GIR_RootConstrainSelectedInstOperands,
     /*  951244 */     // GIR_Coverage, 3832,
     /*  951244 */     GIR_EraseRootFromParent_Done,
     /*  951245 */   // Label 15143: @951245
     /*  951245 */   GIM_Try, /*On fail goto*//*Label 15144*/ GIMT_Encode4(951335), // Rule ID 3833 //
     /*  951250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  951253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  951264 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  951267 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951270 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951273 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951280 */     // MIs[0] cbsz
     /*  951280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951283 */     // MIs[0] blgp
     /*  951283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951286 */     // MIs[0] src0_modifiers
     /*  951286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951289 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951294 */     // MIs[0] src1_modifiers
     /*  951294 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951297 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951302 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64),
     /*  951305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951307 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951309 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951311 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951313 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951315 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951317 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951319 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951321 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951327 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951333 */     GIR_RootConstrainSelectedInstOperands,
     /*  951334 */     // GIR_Coverage, 3833,
     /*  951334 */     GIR_EraseRootFromParent_Done,
     /*  951335 */   // Label 15144: @951335
     /*  951335 */   GIM_Try, /*On fail goto*//*Label 15145*/ GIMT_Encode4(951425), // Rule ID 3839 //
     /*  951340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  951343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  951357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951360 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951363 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951370 */     // MIs[0] cbsz
     /*  951370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951373 */     // MIs[0] blgp
     /*  951373 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951376 */     // MIs[0] src0_modifiers
     /*  951376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951379 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951384 */     // MIs[0] src1_modifiers
     /*  951384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951387 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951392 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  951395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951397 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951399 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951401 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951403 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951405 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951407 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951409 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951411 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951417 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951423 */     GIR_RootConstrainSelectedInstOperands,
     /*  951424 */     // GIR_Coverage, 3839,
     /*  951424 */     GIR_EraseRootFromParent_Done,
     /*  951425 */   // Label 15145: @951425
     /*  951425 */   GIM_Try, /*On fail goto*//*Label 15146*/ GIMT_Encode4(951515), // Rule ID 3840 //
     /*  951430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  951433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  951447 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951450 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951453 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951460 */     // MIs[0] cbsz
     /*  951460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951463 */     // MIs[0] blgp
     /*  951463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951466 */     // MIs[0] src0_modifiers
     /*  951466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951469 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951474 */     // MIs[0] src1_modifiers
     /*  951474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951477 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951482 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  951485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951487 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951489 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951491 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951493 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951495 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951497 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951499 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951501 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951507 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951513 */     GIR_RootConstrainSelectedInstOperands,
     /*  951514 */     // GIR_Coverage, 3840,
     /*  951514 */     GIR_EraseRootFromParent_Done,
     /*  951515 */   // Label 15146: @951515
     /*  951515 */   GIM_Try, /*On fail goto*//*Label 15147*/ GIMT_Encode4(951605), // Rule ID 3841 //
     /*  951520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  951523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951528 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951534 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  951537 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951540 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951543 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951550 */     // MIs[0] cbsz
     /*  951550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951553 */     // MIs[0] blgp
     /*  951553 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951556 */     // MIs[0] src0_modifiers
     /*  951556 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951559 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951564 */     // MIs[0] src1_modifiers
     /*  951564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951567 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951572 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  951575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951577 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951579 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951581 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951583 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951585 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951587 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951589 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951591 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951597 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951603 */     GIR_RootConstrainSelectedInstOperands,
     /*  951604 */     // GIR_Coverage, 3841,
     /*  951604 */     GIR_EraseRootFromParent_Done,
     /*  951605 */   // Label 15147: @951605
     /*  951605 */   GIM_Try, /*On fail goto*//*Label 15148*/ GIMT_Encode4(951695), // Rule ID 3842 //
     /*  951610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  951613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  951627 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951630 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951633 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951640 */     // MIs[0] cbsz
     /*  951640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951643 */     // MIs[0] blgp
     /*  951643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951646 */     // MIs[0] src0_modifiers
     /*  951646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951649 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951654 */     // MIs[0] src1_modifiers
     /*  951654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951657 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951662 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  951665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951667 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951669 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951671 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951673 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951675 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951677 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951679 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951681 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951687 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951693 */     GIR_RootConstrainSelectedInstOperands,
     /*  951694 */     // GIR_Coverage, 3842,
     /*  951694 */     GIR_EraseRootFromParent_Done,
     /*  951695 */   // Label 15148: @951695
     /*  951695 */   GIM_Try, /*On fail goto*//*Label 15149*/ GIMT_Encode4(951785), // Rule ID 3843 //
     /*  951700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  951703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951714 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  951717 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951720 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951723 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951730 */     // MIs[0] cbsz
     /*  951730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951733 */     // MIs[0] blgp
     /*  951733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951736 */     // MIs[0] src0_modifiers
     /*  951736 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951739 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951744 */     // MIs[0] src1_modifiers
     /*  951744 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951747 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951752 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64),
     /*  951755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951757 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951759 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951761 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951763 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951765 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951767 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951769 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951771 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951777 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951783 */     GIR_RootConstrainSelectedInstOperands,
     /*  951784 */     // GIR_Coverage, 3843,
     /*  951784 */     GIR_EraseRootFromParent_Done,
     /*  951785 */   // Label 15149: @951785
     /*  951785 */   GIM_Try, /*On fail goto*//*Label 15150*/ GIMT_Encode4(951875), // Rule ID 3849 //
     /*  951790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  951793 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951798 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951801 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951804 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  951807 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951810 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951813 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951820 */     // MIs[0] cbsz
     /*  951820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951823 */     // MIs[0] blgp
     /*  951823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951826 */     // MIs[0] src0_modifiers
     /*  951826 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951829 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951834 */     // MIs[0] src1_modifiers
     /*  951834 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951837 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951842 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  951845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951847 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951849 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951851 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951853 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951855 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951857 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951859 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951861 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951867 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951873 */     GIR_RootConstrainSelectedInstOperands,
     /*  951874 */     // GIR_Coverage, 3849,
     /*  951874 */     GIR_EraseRootFromParent_Done,
     /*  951875 */   // Label 15150: @951875
     /*  951875 */   GIM_Try, /*On fail goto*//*Label 15151*/ GIMT_Encode4(951965), // Rule ID 3850 //
     /*  951880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  951883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  951897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951900 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951903 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  951910 */     // MIs[0] cbsz
     /*  951910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  951913 */     // MIs[0] blgp
     /*  951913 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  951916 */     // MIs[0] src0_modifiers
     /*  951916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  951919 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951924 */     // MIs[0] src1_modifiers
     /*  951924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  951927 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  951932 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  951932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  951935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  951937 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  951939 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  951941 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  951943 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  951945 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  951947 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  951949 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  951951 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  951957 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  951963 */     GIR_RootConstrainSelectedInstOperands,
     /*  951964 */     // GIR_Coverage, 3850,
     /*  951964 */     GIR_EraseRootFromParent_Done,
     /*  951965 */   // Label 15151: @951965
     /*  951965 */   GIM_Try, /*On fail goto*//*Label 15152*/ GIMT_Encode4(952055), // Rule ID 3851 //
     /*  951970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  951973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  951978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  951981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  951984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  951987 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  951990 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  951993 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  951996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952000 */     // MIs[0] cbsz
     /*  952000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952003 */     // MIs[0] blgp
     /*  952003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952006 */     // MIs[0] src0_modifiers
     /*  952006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952009 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952014 */     // MIs[0] src1_modifiers
     /*  952014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952017 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952022 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  952025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952027 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952029 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952031 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952033 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952035 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952037 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952039 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952041 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952047 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952053 */     GIR_RootConstrainSelectedInstOperands,
     /*  952054 */     // GIR_Coverage, 3851,
     /*  952054 */     GIR_EraseRootFromParent_Done,
     /*  952055 */   // Label 15152: @952055
     /*  952055 */   GIM_Try, /*On fail goto*//*Label 15153*/ GIMT_Encode4(952145), // Rule ID 3852 //
     /*  952060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  952063 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952068 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952071 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  952074 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  952077 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952080 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952083 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952090 */     // MIs[0] cbsz
     /*  952090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952093 */     // MIs[0] blgp
     /*  952093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952096 */     // MIs[0] src0_modifiers
     /*  952096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952099 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952104 */     // MIs[0] src1_modifiers
     /*  952104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952107 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952112 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  952115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952117 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952119 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952121 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952123 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952125 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952127 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952129 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952131 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952137 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952143 */     GIR_RootConstrainSelectedInstOperands,
     /*  952144 */     // GIR_Coverage, 3852,
     /*  952144 */     GIR_EraseRootFromParent_Done,
     /*  952145 */   // Label 15153: @952145
     /*  952145 */   GIM_Try, /*On fail goto*//*Label 15154*/ GIMT_Encode4(952235), // Rule ID 3853 //
     /*  952150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  952153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  952164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  952167 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952170 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952173 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952180 */     // MIs[0] cbsz
     /*  952180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952183 */     // MIs[0] blgp
     /*  952183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952186 */     // MIs[0] src0_modifiers
     /*  952186 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952189 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952194 */     // MIs[0] src1_modifiers
     /*  952194 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952197 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952202 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64),
     /*  952205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952207 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952209 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952211 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952213 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952215 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952217 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952219 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952221 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952227 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952233 */     GIR_RootConstrainSelectedInstOperands,
     /*  952234 */     // GIR_Coverage, 3853,
     /*  952234 */     GIR_EraseRootFromParent_Done,
     /*  952235 */   // Label 15154: @952235
     /*  952235 */   GIM_Try, /*On fail goto*//*Label 15155*/ GIMT_Encode4(952325), // Rule ID 3859 //
     /*  952240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  952243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  952254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  952257 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952260 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952263 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952270 */     // MIs[0] cbsz
     /*  952270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952273 */     // MIs[0] blgp
     /*  952273 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952276 */     // MIs[0] src0_modifiers
     /*  952276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952279 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952284 */     // MIs[0] src1_modifiers
     /*  952284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952287 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952292 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  952295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952297 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952299 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952301 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952303 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952305 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952307 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952309 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952311 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952317 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952323 */     GIR_RootConstrainSelectedInstOperands,
     /*  952324 */     // GIR_Coverage, 3859,
     /*  952324 */     GIR_EraseRootFromParent_Done,
     /*  952325 */   // Label 15155: @952325
     /*  952325 */   GIM_Try, /*On fail goto*//*Label 15156*/ GIMT_Encode4(952415), // Rule ID 3860 //
     /*  952330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  952333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  952344 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  952347 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952350 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952353 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952360 */     // MIs[0] cbsz
     /*  952360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952363 */     // MIs[0] blgp
     /*  952363 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952366 */     // MIs[0] src0_modifiers
     /*  952366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952369 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952374 */     // MIs[0] src1_modifiers
     /*  952374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952377 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952382 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  952385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952387 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952389 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952391 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952393 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952395 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952397 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952399 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952401 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952407 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952413 */     GIR_RootConstrainSelectedInstOperands,
     /*  952414 */     // GIR_Coverage, 3860,
     /*  952414 */     GIR_EraseRootFromParent_Done,
     /*  952415 */   // Label 15156: @952415
     /*  952415 */   GIM_Try, /*On fail goto*//*Label 15157*/ GIMT_Encode4(952505), // Rule ID 3861 //
     /*  952420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  952423 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952428 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952431 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  952434 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  952437 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952440 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952443 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952450 */     // MIs[0] cbsz
     /*  952450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952453 */     // MIs[0] blgp
     /*  952453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952456 */     // MIs[0] src0_modifiers
     /*  952456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952459 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952464 */     // MIs[0] src1_modifiers
     /*  952464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952467 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952472 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  952475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952477 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952479 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952481 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952483 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952485 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952487 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952489 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952491 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952497 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952503 */     GIR_RootConstrainSelectedInstOperands,
     /*  952504 */     // GIR_Coverage, 3861,
     /*  952504 */     GIR_EraseRootFromParent_Done,
     /*  952505 */   // Label 15157: @952505
     /*  952505 */   GIM_Try, /*On fail goto*//*Label 15158*/ GIMT_Encode4(952595), // Rule ID 3862 //
     /*  952510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  952513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  952524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  952527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952530 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952533 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952540 */     // MIs[0] cbsz
     /*  952540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952543 */     // MIs[0] blgp
     /*  952543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952546 */     // MIs[0] src0_modifiers
     /*  952546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952549 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952554 */     // MIs[0] src1_modifiers
     /*  952554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952557 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952562 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  952565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952567 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952569 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952571 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952573 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952575 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952577 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952579 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952581 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952587 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952593 */     GIR_RootConstrainSelectedInstOperands,
     /*  952594 */     // GIR_Coverage, 3862,
     /*  952594 */     GIR_EraseRootFromParent_Done,
     /*  952595 */   // Label 15158: @952595
     /*  952595 */   GIM_Try, /*On fail goto*//*Label 15159*/ GIMT_Encode4(952685), // Rule ID 3863 //
     /*  952600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  952603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  952614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  952617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952620 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952623 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952630 */     // MIs[0] cbsz
     /*  952630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952633 */     // MIs[0] blgp
     /*  952633 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952636 */     // MIs[0] src0_modifiers
     /*  952636 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952639 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952644 */     // MIs[0] src1_modifiers
     /*  952644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952647 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952652 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64:{ *:[v16f32] } v8i32:{ *:[v8i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64),
     /*  952655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952657 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952659 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952661 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952663 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952665 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952667 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952669 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952671 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952677 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952683 */     GIR_RootConstrainSelectedInstOperands,
     /*  952684 */     // GIR_Coverage, 3863,
     /*  952684 */     GIR_EraseRootFromParent_Done,
     /*  952685 */   // Label 15159: @952685
     /*  952685 */   GIM_Try, /*On fail goto*//*Label 15160*/ GIMT_Encode4(952775), // Rule ID 3869 //
     /*  952690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  952693 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952698 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952701 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  952704 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  952707 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952710 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952713 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952720 */     // MIs[0] cbsz
     /*  952720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952723 */     // MIs[0] blgp
     /*  952723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952726 */     // MIs[0] src0_modifiers
     /*  952726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952729 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952734 */     // MIs[0] src1_modifiers
     /*  952734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952737 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952742 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  952745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952747 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952749 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952751 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952753 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952755 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952757 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952759 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952761 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952767 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952773 */     GIR_RootConstrainSelectedInstOperands,
     /*  952774 */     // GIR_Coverage, 3869,
     /*  952774 */     GIR_EraseRootFromParent_Done,
     /*  952775 */   // Label 15160: @952775
     /*  952775 */   GIM_Try, /*On fail goto*//*Label 15161*/ GIMT_Encode4(952865), // Rule ID 3870 //
     /*  952780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  952783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  952794 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  952797 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952800 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952803 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952810 */     // MIs[0] cbsz
     /*  952810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952813 */     // MIs[0] blgp
     /*  952813 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952816 */     // MIs[0] src0_modifiers
     /*  952816 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952819 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952824 */     // MIs[0] src1_modifiers
     /*  952824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952827 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952832 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  952835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952837 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952839 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952841 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952843 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952845 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952847 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952849 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952851 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952857 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952863 */     GIR_RootConstrainSelectedInstOperands,
     /*  952864 */     // GIR_Coverage, 3870,
     /*  952864 */     GIR_EraseRootFromParent_Done,
     /*  952865 */   // Label 15161: @952865
     /*  952865 */   GIM_Try, /*On fail goto*//*Label 15162*/ GIMT_Encode4(952955), // Rule ID 3871 //
     /*  952870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  952873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  952884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  952887 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952890 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952893 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952900 */     // MIs[0] cbsz
     /*  952900 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952903 */     // MIs[0] blgp
     /*  952903 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952906 */     // MIs[0] src0_modifiers
     /*  952906 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952909 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952914 */     // MIs[0] src1_modifiers
     /*  952914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  952917 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  952922 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  952922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  952925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  952927 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  952929 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  952931 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  952933 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  952935 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  952937 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  952939 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  952941 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  952947 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  952953 */     GIR_RootConstrainSelectedInstOperands,
     /*  952954 */     // GIR_Coverage, 3871,
     /*  952954 */     GIR_EraseRootFromParent_Done,
     /*  952955 */   // Label 15162: @952955
     /*  952955 */   GIM_Try, /*On fail goto*//*Label 15163*/ GIMT_Encode4(953045), // Rule ID 3872 //
     /*  952960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  952963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  952968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  952971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  952974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  952977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  952980 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  952983 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  952986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  952990 */     // MIs[0] cbsz
     /*  952990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  952993 */     // MIs[0] blgp
     /*  952993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  952996 */     // MIs[0] src0_modifiers
     /*  952996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  952999 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953004 */     // MIs[0] src1_modifiers
     /*  953004 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953007 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953012 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  953015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953017 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953019 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953021 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953023 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953025 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953027 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953029 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953031 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953037 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953043 */     GIR_RootConstrainSelectedInstOperands,
     /*  953044 */     // GIR_Coverage, 3872,
     /*  953044 */     GIR_EraseRootFromParent_Done,
     /*  953045 */   // Label 15163: @953045
     /*  953045 */   GIM_Try, /*On fail goto*//*Label 15164*/ GIMT_Encode4(953135), // Rule ID 3873 //
     /*  953050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  953053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  953064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  953067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953070 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953073 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953080 */     // MIs[0] cbsz
     /*  953080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953083 */     // MIs[0] blgp
     /*  953083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953086 */     // MIs[0] src0_modifiers
     /*  953086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953089 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953094 */     // MIs[0] src1_modifiers
     /*  953094 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953097 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953102 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64),
     /*  953105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953107 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953109 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953111 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953113 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953115 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953117 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953119 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953121 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953127 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953133 */     GIR_RootConstrainSelectedInstOperands,
     /*  953134 */     // GIR_Coverage, 3873,
     /*  953134 */     GIR_EraseRootFromParent_Done,
     /*  953135 */   // Label 15164: @953135
     /*  953135 */   GIM_Try, /*On fail goto*//*Label 15165*/ GIMT_Encode4(953225), // Rule ID 3879 //
     /*  953140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  953143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953151 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  953154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  953157 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953160 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953163 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953170 */     // MIs[0] cbsz
     /*  953170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953173 */     // MIs[0] blgp
     /*  953173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953176 */     // MIs[0] src0_modifiers
     /*  953176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953179 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953184 */     // MIs[0] src1_modifiers
     /*  953184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953187 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953192 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  953195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953197 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953199 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953201 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953203 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953205 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953207 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953209 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953217 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953223 */     GIR_RootConstrainSelectedInstOperands,
     /*  953224 */     // GIR_Coverage, 3879,
     /*  953224 */     GIR_EraseRootFromParent_Done,
     /*  953225 */   // Label 15165: @953225
     /*  953225 */   GIM_Try, /*On fail goto*//*Label 15166*/ GIMT_Encode4(953315), // Rule ID 3880 //
     /*  953230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  953233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  953244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  953247 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953250 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953253 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953260 */     // MIs[0] cbsz
     /*  953260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953263 */     // MIs[0] blgp
     /*  953263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953266 */     // MIs[0] src0_modifiers
     /*  953266 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953269 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953274 */     // MIs[0] src1_modifiers
     /*  953274 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953277 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953282 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  953285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953287 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953289 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953291 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953293 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953295 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953297 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953299 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953301 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953307 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953313 */     GIR_RootConstrainSelectedInstOperands,
     /*  953314 */     // GIR_Coverage, 3880,
     /*  953314 */     GIR_EraseRootFromParent_Done,
     /*  953315 */   // Label 15166: @953315
     /*  953315 */   GIM_Try, /*On fail goto*//*Label 15167*/ GIMT_Encode4(953405), // Rule ID 3881 //
     /*  953320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  953323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  953334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  953337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953340 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953343 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953350 */     // MIs[0] cbsz
     /*  953350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953353 */     // MIs[0] blgp
     /*  953353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953356 */     // MIs[0] src0_modifiers
     /*  953356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953359 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953364 */     // MIs[0] src1_modifiers
     /*  953364 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953367 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953372 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  953375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953377 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953379 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953381 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953383 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953385 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953387 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953389 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953391 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953397 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953403 */     GIR_RootConstrainSelectedInstOperands,
     /*  953404 */     // GIR_Coverage, 3881,
     /*  953404 */     GIR_EraseRootFromParent_Done,
     /*  953405 */   // Label 15167: @953405
     /*  953405 */   GIM_Try, /*On fail goto*//*Label 15168*/ GIMT_Encode4(953495), // Rule ID 3882 //
     /*  953410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  953413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953418 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953421 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  953424 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  953427 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953430 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953433 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953440 */     // MIs[0] cbsz
     /*  953440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953443 */     // MIs[0] blgp
     /*  953443 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953446 */     // MIs[0] src0_modifiers
     /*  953446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953449 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953454 */     // MIs[0] src1_modifiers
     /*  953454 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953457 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953462 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  953465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953467 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953469 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953471 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953473 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953475 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953477 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953479 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953481 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953487 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953493 */     GIR_RootConstrainSelectedInstOperands,
     /*  953494 */     // GIR_Coverage, 3882,
     /*  953494 */     GIR_EraseRootFromParent_Done,
     /*  953495 */   // Label 15168: @953495
     /*  953495 */   GIM_Try, /*On fail goto*//*Label 15169*/ GIMT_Encode4(953585), // Rule ID 3883 //
     /*  953500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  953503 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953508 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953511 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v6s32,
     /*  953514 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  953517 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953520 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953523 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953530 */     // MIs[0] cbsz
     /*  953530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953533 */     // MIs[0] blgp
     /*  953533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953536 */     // MIs[0] src0_modifiers
     /*  953536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953539 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953544 */     // MIs[0] src1_modifiers
     /*  953544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953547 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953552 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64:{ *:[v16f32] } v6i32:{ *:[v6i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64),
     /*  953555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953557 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953559 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953561 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953563 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953565 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953567 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953569 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953571 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953577 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953583 */     GIR_RootConstrainSelectedInstOperands,
     /*  953584 */     // GIR_Coverage, 3883,
     /*  953584 */     GIR_EraseRootFromParent_Done,
     /*  953585 */   // Label 15169: @953585
     /*  953585 */   GIM_Try, /*On fail goto*//*Label 15170*/ GIMT_Encode4(953675), // Rule ID 3889 //
     /*  953590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  953593 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953598 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953601 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  953604 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  953607 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953610 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953613 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953620 */     // MIs[0] cbsz
     /*  953620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953623 */     // MIs[0] blgp
     /*  953623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953626 */     // MIs[0] src0_modifiers
     /*  953626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953629 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953634 */     // MIs[0] src1_modifiers
     /*  953634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953637 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953642 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  953645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953647 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953649 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953651 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953653 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953655 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953657 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953659 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953661 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953667 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953673 */     GIR_RootConstrainSelectedInstOperands,
     /*  953674 */     // GIR_Coverage, 3889,
     /*  953674 */     GIR_EraseRootFromParent_Done,
     /*  953675 */   // Label 15170: @953675
     /*  953675 */   GIM_Try, /*On fail goto*//*Label 15171*/ GIMT_Encode4(953765), // Rule ID 3890 //
     /*  953680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  953683 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953688 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953691 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  953694 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  953697 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953700 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953703 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953710 */     // MIs[0] cbsz
     /*  953710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953713 */     // MIs[0] blgp
     /*  953713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953716 */     // MIs[0] src0_modifiers
     /*  953716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953719 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953724 */     // MIs[0] src1_modifiers
     /*  953724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953727 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953732 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  953735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953737 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953739 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953741 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953743 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953745 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953747 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953749 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953751 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953757 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953763 */     GIR_RootConstrainSelectedInstOperands,
     /*  953764 */     // GIR_Coverage, 3890,
     /*  953764 */     GIR_EraseRootFromParent_Done,
     /*  953765 */   // Label 15171: @953765
     /*  953765 */   GIM_Try, /*On fail goto*//*Label 15172*/ GIMT_Encode4(953855), // Rule ID 3891 //
     /*  953770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  953773 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953778 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953781 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  953784 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  953787 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953790 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953793 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953800 */     // MIs[0] cbsz
     /*  953800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953803 */     // MIs[0] blgp
     /*  953803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953806 */     // MIs[0] src0_modifiers
     /*  953806 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953809 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953814 */     // MIs[0] src1_modifiers
     /*  953814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953817 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953822 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  953825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953827 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953829 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953831 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953833 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953835 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953837 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953839 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953841 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953847 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953853 */     GIR_RootConstrainSelectedInstOperands,
     /*  953854 */     // GIR_Coverage, 3891,
     /*  953854 */     GIR_EraseRootFromParent_Done,
     /*  953855 */   // Label 15172: @953855
     /*  953855 */   GIM_Try, /*On fail goto*//*Label 15173*/ GIMT_Encode4(953945), // Rule ID 3892 //
     /*  953860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  953863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  953874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  953877 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953880 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953883 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953890 */     // MIs[0] cbsz
     /*  953890 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953893 */     // MIs[0] blgp
     /*  953893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953896 */     // MIs[0] src0_modifiers
     /*  953896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953899 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953904 */     // MIs[0] src1_modifiers
     /*  953904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953907 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953912 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  953912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  953915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  953917 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  953919 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  953921 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  953923 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  953925 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  953927 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  953929 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  953931 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  953937 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  953943 */     GIR_RootConstrainSelectedInstOperands,
     /*  953944 */     // GIR_Coverage, 3892,
     /*  953944 */     GIR_EraseRootFromParent_Done,
     /*  953945 */   // Label 15173: @953945
     /*  953945 */   GIM_Try, /*On fail goto*//*Label 15174*/ GIMT_Encode4(954035), // Rule ID 3893 //
     /*  953950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  953953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  953958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  953961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  953964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v6s32,
     /*  953967 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  953970 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  953973 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  953976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  953980 */     // MIs[0] cbsz
     /*  953980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  953983 */     // MIs[0] blgp
     /*  953983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  953986 */     // MIs[0] src0_modifiers
     /*  953986 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  953989 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  953994 */     // MIs[0] src1_modifiers
     /*  953994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  953997 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954002 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v6i32:{ *:[v6i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  954002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64),
     /*  954005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954007 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954009 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954011 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  954013 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  954015 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  954017 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954019 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  954021 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  954027 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  954033 */     GIR_RootConstrainSelectedInstOperands,
     /*  954034 */     // GIR_Coverage, 3893,
     /*  954034 */     GIR_EraseRootFromParent_Done,
     /*  954035 */   // Label 15174: @954035
     /*  954035 */   GIM_Try, /*On fail goto*//*Label 15175*/ GIMT_Encode4(954125), // Rule ID 3899 //
     /*  954040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  954043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  954048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  954054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  954057 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  954060 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954063 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  954066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954070 */     // MIs[0] cbsz
     /*  954070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  954073 */     // MIs[0] blgp
     /*  954073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954076 */     // MIs[0] src0_modifiers
     /*  954076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954079 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954084 */     // MIs[0] src1_modifiers
     /*  954084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954087 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954092 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  954092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  954095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954097 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954099 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954101 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  954103 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  954105 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  954107 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954109 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  954111 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  954117 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  954123 */     GIR_RootConstrainSelectedInstOperands,
     /*  954124 */     // GIR_Coverage, 3899,
     /*  954124 */     GIR_EraseRootFromParent_Done,
     /*  954125 */   // Label 15175: @954125
     /*  954125 */   GIM_Try, /*On fail goto*//*Label 15176*/ GIMT_Encode4(954215), // Rule ID 3900 //
     /*  954130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  954133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  954138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  954144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  954147 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  954150 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954153 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  954156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954160 */     // MIs[0] cbsz
     /*  954160 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  954163 */     // MIs[0] blgp
     /*  954163 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954166 */     // MIs[0] src0_modifiers
     /*  954166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954169 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954174 */     // MIs[0] src1_modifiers
     /*  954174 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954177 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954182 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  954182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  954185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954187 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954189 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954191 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  954193 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  954195 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  954197 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954199 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  954201 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  954207 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  954213 */     GIR_RootConstrainSelectedInstOperands,
     /*  954214 */     // GIR_Coverage, 3900,
     /*  954214 */     GIR_EraseRootFromParent_Done,
     /*  954215 */   // Label 15176: @954215
     /*  954215 */   GIM_Try, /*On fail goto*//*Label 15177*/ GIMT_Encode4(954305), // Rule ID 3901 //
     /*  954220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  954223 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  954228 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954231 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  954234 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  954237 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  954240 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954243 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  954246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954250 */     // MIs[0] cbsz
     /*  954250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  954253 */     // MIs[0] blgp
     /*  954253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954256 */     // MIs[0] src0_modifiers
     /*  954256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954259 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954264 */     // MIs[0] src1_modifiers
     /*  954264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954267 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954272 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  954272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  954275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954277 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954279 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954281 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  954283 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  954285 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  954287 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954289 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  954291 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  954297 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  954303 */     GIR_RootConstrainSelectedInstOperands,
     /*  954304 */     // GIR_Coverage, 3901,
     /*  954304 */     GIR_EraseRootFromParent_Done,
     /*  954305 */   // Label 15177: @954305
     /*  954305 */   GIM_Try, /*On fail goto*//*Label 15178*/ GIMT_Encode4(954395), // Rule ID 3902 //
     /*  954310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  954313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  954318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  954324 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  954327 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  954330 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954333 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  954336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954340 */     // MIs[0] cbsz
     /*  954340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  954343 */     // MIs[0] blgp
     /*  954343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954346 */     // MIs[0] src0_modifiers
     /*  954346 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954349 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954354 */     // MIs[0] src1_modifiers
     /*  954354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954357 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954362 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  954362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  954365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954367 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954369 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954371 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  954373 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  954375 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  954377 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954379 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  954381 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  954387 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  954393 */     GIR_RootConstrainSelectedInstOperands,
     /*  954394 */     // GIR_Coverage, 3902,
     /*  954394 */     GIR_EraseRootFromParent_Done,
     /*  954395 */   // Label 15178: @954395
     /*  954395 */   GIM_Try, /*On fail goto*//*Label 15179*/ GIMT_Encode4(954485), // Rule ID 3903 //
     /*  954400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  954403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_scale_f32_32x32x64_f8f6f4),
     /*  954408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  954414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  954417 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32,
     /*  954420 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954423 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  954426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954430 */     // MIs[0] cbsz
     /*  954430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  954433 */     // MIs[0] blgp
     /*  954433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954436 */     // MIs[0] src0_modifiers
     /*  954436 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954439 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954444 */     // MIs[0] src1_modifiers
     /*  954444 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954447 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_MFMALdScaleModifierOp),
     /*  954452 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3327:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src0_modifiers, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] })<<P:Predicate_MFMALdScaleModifierOp>><<X:MFMALdScaleXForm>>:$src1_modifiers, i32:{ *:[i32] }:$scale_src1)  =>  (V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$blgp, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src0_modifiers), (MFMALdScaleXForm:{ *:[i32] } (timm:{ *:[i32] }):$src1_modifiers))
     /*  954452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64),
     /*  954455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954457 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954459 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954461 */     GIR_RootToRootCopy, /*OpIdx*/4, // src2
     /*  954463 */     GIR_RootToRootCopy, /*OpIdx*/5, // cbsz
     /*  954465 */     GIR_RootToRootCopy, /*OpIdx*/6, // blgp
     /*  954467 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954469 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src1
     /*  954471 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src0_modifiers
     /*  954477 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/9, /*OperandRenderer*/GIMT_Encode2(GICR_renderScaledMAIIntrinsicOperand), // src1_modifiers
     /*  954483 */     GIR_RootConstrainSelectedInstOperands,
     /*  954484 */     // GIR_Coverage, 3903,
     /*  954484 */     GIR_EraseRootFromParent_Done,
     /*  954485 */   // Label 15179: @954485
     /*  954485 */   GIM_Reject,
     /*  954486 */ // Label 14814: @954486
     /*  954486 */ GIM_Try, /*On fail goto*//*Label 15180*/ GIMT_Encode4(956535),
     /*  954491 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/14,
     /*  954494 */   GIM_Try, /*On fail goto*//*Label 15181*/ GIMT_Encode4(954601), // Rule ID 8273 //
     /*  954499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  954502 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  954507 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  954513 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  954516 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  954519 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954522 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  954525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954529 */     // MIs[0] src2_modifiers
     /*  954529 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  954532 */     // MIs[0] matrix_a_scale
     /*  954532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954535 */     // MIs[0] matrix_a_scale_fmt
     /*  954535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954538 */     // MIs[0] matrix_b_scale
     /*  954538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954541 */     // MIs[0] matrix_b_scale_fmt
     /*  954541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  954544 */     // MIs[0] matrix_a_reuse
     /*  954544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  954547 */     // MIs[0] matrix_b_reuse
     /*  954547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  954550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  954557 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  954557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr),
     /*  954560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954562 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954564 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954566 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  954572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  954577 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954579 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  954581 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  954583 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  954585 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  954587 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  954589 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  954591 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  954593 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954599 */     GIR_RootConstrainSelectedInstOperands,
     /*  954600 */     // GIR_Coverage, 8273,
     /*  954600 */     GIR_EraseRootFromParent_Done,
     /*  954601 */   // Label 15181: @954601
     /*  954601 */   GIM_Try, /*On fail goto*//*Label 15182*/ GIMT_Encode4(954708), // Rule ID 8274 //
     /*  954606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  954609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  954614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954617 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  954620 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  954623 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  954626 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954629 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  954632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954636 */     // MIs[0] src2_modifiers
     /*  954636 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  954639 */     // MIs[0] matrix_a_scale
     /*  954639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954642 */     // MIs[0] matrix_a_scale_fmt
     /*  954642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954645 */     // MIs[0] matrix_b_scale
     /*  954645 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954648 */     // MIs[0] matrix_b_scale_fmt
     /*  954648 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  954651 */     // MIs[0] matrix_a_reuse
     /*  954651 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  954654 */     // MIs[0] matrix_b_reuse
     /*  954654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  954657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  954664 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  954664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr),
     /*  954667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954669 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954671 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954673 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  954679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  954684 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954686 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  954688 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  954690 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  954692 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  954694 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  954696 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  954698 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  954700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954706 */     GIR_RootConstrainSelectedInstOperands,
     /*  954707 */     // GIR_Coverage, 8274,
     /*  954707 */     GIR_EraseRootFromParent_Done,
     /*  954708 */   // Label 15182: @954708
     /*  954708 */   GIM_Try, /*On fail goto*//*Label 15183*/ GIMT_Encode4(954815), // Rule ID 8275 //
     /*  954713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  954716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  954721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  954727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  954730 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  954733 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954736 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  954739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954743 */     // MIs[0] src2_modifiers
     /*  954743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  954746 */     // MIs[0] matrix_a_scale
     /*  954746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954749 */     // MIs[0] matrix_a_scale_fmt
     /*  954749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954752 */     // MIs[0] matrix_b_scale
     /*  954752 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954755 */     // MIs[0] matrix_b_scale_fmt
     /*  954755 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  954758 */     // MIs[0] matrix_a_reuse
     /*  954758 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  954761 */     // MIs[0] matrix_b_reuse
     /*  954761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  954764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  954771 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  954771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr),
     /*  954774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954776 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954778 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954780 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  954786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  954791 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954793 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  954795 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  954797 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  954799 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  954801 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  954803 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  954805 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  954807 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954813 */     GIR_RootConstrainSelectedInstOperands,
     /*  954814 */     // GIR_Coverage, 8275,
     /*  954814 */     GIR_EraseRootFromParent_Done,
     /*  954815 */   // Label 15183: @954815
     /*  954815 */   GIM_Try, /*On fail goto*//*Label 15184*/ GIMT_Encode4(954922), // Rule ID 8276 //
     /*  954820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  954823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  954828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  954834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  954837 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  954840 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954843 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  954846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954850 */     // MIs[0] src2_modifiers
     /*  954850 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  954853 */     // MIs[0] matrix_a_scale
     /*  954853 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954856 */     // MIs[0] matrix_a_scale_fmt
     /*  954856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954859 */     // MIs[0] matrix_b_scale
     /*  954859 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954862 */     // MIs[0] matrix_b_scale_fmt
     /*  954862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  954865 */     // MIs[0] matrix_a_reuse
     /*  954865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  954868 */     // MIs[0] matrix_b_reuse
     /*  954868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  954871 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  954878 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  954878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr),
     /*  954881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954883 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954885 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954887 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  954893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  954898 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  954900 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  954902 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  954904 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  954906 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  954908 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  954910 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  954912 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  954914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  954920 */     GIR_RootConstrainSelectedInstOperands,
     /*  954921 */     // GIR_Coverage, 8276,
     /*  954921 */     GIR_EraseRootFromParent_Done,
     /*  954922 */   // Label 15184: @954922
     /*  954922 */   GIM_Try, /*On fail goto*//*Label 15185*/ GIMT_Encode4(955029), // Rule ID 8277 //
     /*  954927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  954930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  954935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  954938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  954941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  954944 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  954947 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  954950 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  954953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  954957 */     // MIs[0] src2_modifiers
     /*  954957 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  954960 */     // MIs[0] matrix_a_scale
     /*  954960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  954963 */     // MIs[0] matrix_a_scale_fmt
     /*  954963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  954966 */     // MIs[0] matrix_b_scale
     /*  954966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  954969 */     // MIs[0] matrix_b_scale_fmt
     /*  954969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  954972 */     // MIs[0] matrix_a_reuse
     /*  954972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  954975 */     // MIs[0] matrix_b_reuse
     /*  954975 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  954978 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  954985 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  954985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr),
     /*  954988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  954990 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  954992 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  954994 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955000 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  955005 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955007 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955009 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955011 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955013 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955015 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955017 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955019 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955021 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955027 */     GIR_RootConstrainSelectedInstOperands,
     /*  955028 */     // GIR_Coverage, 8277,
     /*  955028 */     GIR_EraseRootFromParent_Done,
     /*  955029 */   // Label 15185: @955029
     /*  955029 */   GIM_Try, /*On fail goto*//*Label 15186*/ GIMT_Encode4(955136), // Rule ID 8283 //
     /*  955034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  955037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  955042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955051 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955054 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  955057 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  955060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955064 */     // MIs[0] src2_modifiers
     /*  955064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955067 */     // MIs[0] matrix_a_scale
     /*  955067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955070 */     // MIs[0] matrix_a_scale_fmt
     /*  955070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955073 */     // MIs[0] matrix_b_scale
     /*  955073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955076 */     // MIs[0] matrix_b_scale_fmt
     /*  955076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955079 */     // MIs[0] matrix_a_reuse
     /*  955079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955082 */     // MIs[0] matrix_b_reuse
     /*  955082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955085 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  955092 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr),
     /*  955095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955097 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955099 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955101 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  955112 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955114 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955116 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955118 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955120 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955122 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955124 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955126 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955134 */     GIR_RootConstrainSelectedInstOperands,
     /*  955135 */     // GIR_Coverage, 8283,
     /*  955135 */     GIR_EraseRootFromParent_Done,
     /*  955136 */   // Label 15186: @955136
     /*  955136 */   GIM_Try, /*On fail goto*//*Label 15187*/ GIMT_Encode4(955243), // Rule ID 8284 //
     /*  955141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  955144 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  955149 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955152 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955155 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955158 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955161 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  955164 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  955167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955171 */     // MIs[0] src2_modifiers
     /*  955171 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955174 */     // MIs[0] matrix_a_scale
     /*  955174 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955177 */     // MIs[0] matrix_a_scale_fmt
     /*  955177 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955180 */     // MIs[0] matrix_b_scale
     /*  955180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955183 */     // MIs[0] matrix_b_scale_fmt
     /*  955183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955186 */     // MIs[0] matrix_a_reuse
     /*  955186 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955189 */     // MIs[0] matrix_b_reuse
     /*  955189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955192 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  955199 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr),
     /*  955202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955204 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955206 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955208 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  955219 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955221 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955223 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955225 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955227 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955229 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955231 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955233 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955241 */     GIR_RootConstrainSelectedInstOperands,
     /*  955242 */     // GIR_Coverage, 8284,
     /*  955242 */     GIR_EraseRootFromParent_Done,
     /*  955243 */   // Label 15187: @955243
     /*  955243 */   GIM_Try, /*On fail goto*//*Label 15188*/ GIMT_Encode4(955350), // Rule ID 8285 //
     /*  955248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  955251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  955256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955265 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955268 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  955271 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  955274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955278 */     // MIs[0] src2_modifiers
     /*  955278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955281 */     // MIs[0] matrix_a_scale
     /*  955281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955284 */     // MIs[0] matrix_a_scale_fmt
     /*  955284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955287 */     // MIs[0] matrix_b_scale
     /*  955287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955290 */     // MIs[0] matrix_b_scale_fmt
     /*  955290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955293 */     // MIs[0] matrix_a_reuse
     /*  955293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955296 */     // MIs[0] matrix_b_reuse
     /*  955296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955299 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  955306 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr),
     /*  955309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955311 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955313 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955315 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  955326 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955328 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955330 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955332 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955334 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955336 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955338 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955340 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955342 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955348 */     GIR_RootConstrainSelectedInstOperands,
     /*  955349 */     // GIR_Coverage, 8285,
     /*  955349 */     GIR_EraseRootFromParent_Done,
     /*  955350 */   // Label 15188: @955350
     /*  955350 */   GIM_Try, /*On fail goto*//*Label 15189*/ GIMT_Encode4(955457), // Rule ID 8286 //
     /*  955355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  955358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  955363 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955366 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955369 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955372 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955375 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  955378 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  955381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955385 */     // MIs[0] src2_modifiers
     /*  955385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955388 */     // MIs[0] matrix_a_scale
     /*  955388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955391 */     // MIs[0] matrix_a_scale_fmt
     /*  955391 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955394 */     // MIs[0] matrix_b_scale
     /*  955394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955397 */     // MIs[0] matrix_b_scale_fmt
     /*  955397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955400 */     // MIs[0] matrix_a_reuse
     /*  955400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955403 */     // MIs[0] matrix_b_reuse
     /*  955403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955406 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  955413 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr),
     /*  955416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955418 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955420 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955422 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  955433 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955435 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955437 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955439 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955441 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955443 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955445 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955447 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955455 */     GIR_RootConstrainSelectedInstOperands,
     /*  955456 */     // GIR_Coverage, 8286,
     /*  955456 */     GIR_EraseRootFromParent_Done,
     /*  955457 */   // Label 15189: @955457
     /*  955457 */   GIM_Try, /*On fail goto*//*Label 15190*/ GIMT_Encode4(955564), // Rule ID 8287 //
     /*  955462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  955465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  955470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955479 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955482 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  955485 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  955488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955492 */     // MIs[0] src2_modifiers
     /*  955492 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955495 */     // MIs[0] matrix_a_scale
     /*  955495 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955498 */     // MIs[0] matrix_a_scale_fmt
     /*  955498 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955501 */     // MIs[0] matrix_b_scale
     /*  955501 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955504 */     // MIs[0] matrix_b_scale_fmt
     /*  955504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955507 */     // MIs[0] matrix_a_reuse
     /*  955507 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955510 */     // MIs[0] matrix_b_reuse
     /*  955510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955513 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  955520 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v16f32] } v16f32:{ *:[v16f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr),
     /*  955523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955525 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955527 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955529 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  955540 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955542 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955544 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955546 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955548 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955550 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955552 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955554 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955562 */     GIR_RootConstrainSelectedInstOperands,
     /*  955563 */     // GIR_Coverage, 8287,
     /*  955563 */     GIR_EraseRootFromParent_Done,
     /*  955564 */   // Label 15190: @955564
     /*  955564 */   GIM_Try, /*On fail goto*//*Label 15191*/ GIMT_Encode4(955661), // Rule ID 8268 //
     /*  955569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  955572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  955577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955586 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955589 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  955592 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  955595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955599 */     // MIs[0] src2_modifiers
     /*  955599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955602 */     // MIs[0] matrix_a_scale
     /*  955602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955605 */     // MIs[0] matrix_a_scale_fmt
     /*  955605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955608 */     // MIs[0] matrix_b_scale
     /*  955608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955611 */     // MIs[0] matrix_b_scale_fmt
     /*  955611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955614 */     // MIs[0] matrix_a_reuse
     /*  955614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955617 */     // MIs[0] matrix_b_reuse
     /*  955617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955620 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr),
     /*  955623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955625 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955627 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955629 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955635 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  955637 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955639 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955641 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955643 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955645 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955647 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955649 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955651 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955656 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955659 */     GIR_RootConstrainSelectedInstOperands,
     /*  955660 */     // GIR_Coverage, 8268,
     /*  955660 */     GIR_EraseRootFromParent_Done,
     /*  955661 */   // Label 15191: @955661
     /*  955661 */   GIM_Try, /*On fail goto*//*Label 15192*/ GIMT_Encode4(955758), // Rule ID 8269 //
     /*  955666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  955669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  955674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955683 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955686 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  955689 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  955692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955696 */     // MIs[0] src2_modifiers
     /*  955696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955699 */     // MIs[0] matrix_a_scale
     /*  955699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955702 */     // MIs[0] matrix_a_scale_fmt
     /*  955702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955705 */     // MIs[0] matrix_b_scale
     /*  955705 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955708 */     // MIs[0] matrix_b_scale_fmt
     /*  955708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955711 */     // MIs[0] matrix_a_reuse
     /*  955711 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955714 */     // MIs[0] matrix_b_reuse
     /*  955714 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955717 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr),
     /*  955720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955722 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955724 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955726 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955732 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  955734 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955736 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955738 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955740 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955742 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955744 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955746 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955748 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955756 */     GIR_RootConstrainSelectedInstOperands,
     /*  955757 */     // GIR_Coverage, 8269,
     /*  955757 */     GIR_EraseRootFromParent_Done,
     /*  955758 */   // Label 15192: @955758
     /*  955758 */   GIM_Try, /*On fail goto*//*Label 15193*/ GIMT_Encode4(955855), // Rule ID 8270 //
     /*  955763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  955766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  955771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955780 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955783 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  955786 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  955789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955793 */     // MIs[0] src2_modifiers
     /*  955793 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955796 */     // MIs[0] matrix_a_scale
     /*  955796 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955799 */     // MIs[0] matrix_a_scale_fmt
     /*  955799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955802 */     // MIs[0] matrix_b_scale
     /*  955802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955805 */     // MIs[0] matrix_b_scale_fmt
     /*  955805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955808 */     // MIs[0] matrix_a_reuse
     /*  955808 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955811 */     // MIs[0] matrix_b_reuse
     /*  955811 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955814 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr),
     /*  955817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955819 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955821 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955823 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955829 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  955831 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955833 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955835 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955837 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955839 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955841 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955843 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955845 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955853 */     GIR_RootConstrainSelectedInstOperands,
     /*  955854 */     // GIR_Coverage, 8270,
     /*  955854 */     GIR_EraseRootFromParent_Done,
     /*  955855 */   // Label 15193: @955855
     /*  955855 */   GIM_Try, /*On fail goto*//*Label 15194*/ GIMT_Encode4(955952), // Rule ID 8271 //
     /*  955860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  955863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  955868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955877 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955880 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  955883 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  955886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955890 */     // MIs[0] src2_modifiers
     /*  955890 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955893 */     // MIs[0] matrix_a_scale
     /*  955893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955896 */     // MIs[0] matrix_a_scale_fmt
     /*  955896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955899 */     // MIs[0] matrix_b_scale
     /*  955899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955902 */     // MIs[0] matrix_b_scale_fmt
     /*  955902 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  955905 */     // MIs[0] matrix_a_reuse
     /*  955905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  955908 */     // MIs[0] matrix_b_reuse
     /*  955908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  955911 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  955911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr),
     /*  955914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  955916 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  955918 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  955920 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  955926 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  955928 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  955930 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  955932 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  955934 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  955936 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  955938 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  955940 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  955942 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  955944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  955950 */     GIR_RootConstrainSelectedInstOperands,
     /*  955951 */     // GIR_Coverage, 8271,
     /*  955951 */     GIR_EraseRootFromParent_Done,
     /*  955952 */   // Label 15194: @955952
     /*  955952 */   GIM_Try, /*On fail goto*//*Label 15195*/ GIMT_Encode4(956049), // Rule ID 8272 //
     /*  955957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  955960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_32x16x128_f4),
     /*  955965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  955968 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  955971 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  955974 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  955977 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
     /*  955980 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s32,
     /*  955983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  955987 */     // MIs[0] src2_modifiers
     /*  955987 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  955990 */     // MIs[0] matrix_a_scale
     /*  955990 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  955993 */     // MIs[0] matrix_a_scale_fmt
     /*  955993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  955996 */     // MIs[0] matrix_b_scale
     /*  955996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  955999 */     // MIs[0] matrix_b_scale_fmt
     /*  955999 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  956002 */     // MIs[0] matrix_a_reuse
     /*  956002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956005 */     // MIs[0] matrix_b_reuse
     /*  956005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  956008 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3669:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr),
     /*  956011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956013 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  956015 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  956017 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956023 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  956025 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  956027 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  956029 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  956031 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  956033 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  956035 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  956037 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  956039 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  956041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956047 */     GIR_RootConstrainSelectedInstOperands,
     /*  956048 */     // GIR_Coverage, 8272,
     /*  956048 */     GIR_EraseRootFromParent_Done,
     /*  956049 */   // Label 15195: @956049
     /*  956049 */   GIM_Try, /*On fail goto*//*Label 15196*/ GIMT_Encode4(956146), // Rule ID 8278 //
     /*  956054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  956057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  956062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  956065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  956068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  956071 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956074 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  956077 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  956080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  956084 */     // MIs[0] src2_modifiers
     /*  956084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956087 */     // MIs[0] matrix_a_scale
     /*  956087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956090 */     // MIs[0] matrix_a_scale_fmt
     /*  956090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  956093 */     // MIs[0] matrix_b_scale
     /*  956093 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956096 */     // MIs[0] matrix_b_scale_fmt
     /*  956096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  956099 */     // MIs[0] matrix_a_reuse
     /*  956099 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956102 */     // MIs[0] matrix_b_reuse
     /*  956102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  956105 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr),
     /*  956108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956110 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  956112 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  956114 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956120 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  956122 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  956124 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  956126 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  956128 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  956130 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  956132 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  956134 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  956136 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  956138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956141 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956144 */     GIR_RootConstrainSelectedInstOperands,
     /*  956145 */     // GIR_Coverage, 8278,
     /*  956145 */     GIR_EraseRootFromParent_Done,
     /*  956146 */   // Label 15196: @956146
     /*  956146 */   GIM_Try, /*On fail goto*//*Label 15197*/ GIMT_Encode4(956243), // Rule ID 8279 //
     /*  956151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  956154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  956159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  956162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  956165 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  956168 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956171 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  956174 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  956177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  956181 */     // MIs[0] src2_modifiers
     /*  956181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956184 */     // MIs[0] matrix_a_scale
     /*  956184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956187 */     // MIs[0] matrix_a_scale_fmt
     /*  956187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  956190 */     // MIs[0] matrix_b_scale
     /*  956190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956193 */     // MIs[0] matrix_b_scale_fmt
     /*  956193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  956196 */     // MIs[0] matrix_a_reuse
     /*  956196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956199 */     // MIs[0] matrix_b_reuse
     /*  956199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  956202 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr),
     /*  956205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956207 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  956209 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  956211 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956217 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  956219 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  956221 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  956223 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  956225 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  956227 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  956229 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  956231 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  956233 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  956235 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956241 */     GIR_RootConstrainSelectedInstOperands,
     /*  956242 */     // GIR_Coverage, 8279,
     /*  956242 */     GIR_EraseRootFromParent_Done,
     /*  956243 */   // Label 15197: @956243
     /*  956243 */   GIM_Try, /*On fail goto*//*Label 15198*/ GIMT_Encode4(956340), // Rule ID 8280 //
     /*  956248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  956251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  956256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  956259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  956262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  956265 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956268 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  956271 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  956274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  956278 */     // MIs[0] src2_modifiers
     /*  956278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956281 */     // MIs[0] matrix_a_scale
     /*  956281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956284 */     // MIs[0] matrix_a_scale_fmt
     /*  956284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  956287 */     // MIs[0] matrix_b_scale
     /*  956287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956290 */     // MIs[0] matrix_b_scale_fmt
     /*  956290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  956293 */     // MIs[0] matrix_a_reuse
     /*  956293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956296 */     // MIs[0] matrix_b_reuse
     /*  956296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  956299 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr),
     /*  956302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956304 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  956306 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  956308 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956314 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  956316 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  956318 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  956320 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  956322 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  956324 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  956326 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  956328 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  956330 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  956332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956338 */     GIR_RootConstrainSelectedInstOperands,
     /*  956339 */     // GIR_Coverage, 8280,
     /*  956339 */     GIR_EraseRootFromParent_Done,
     /*  956340 */   // Label 15198: @956340
     /*  956340 */   GIM_Try, /*On fail goto*//*Label 15199*/ GIMT_Encode4(956437), // Rule ID 8281 //
     /*  956345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  956348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  956353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  956356 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  956359 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  956362 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956365 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  956368 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  956371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  956375 */     // MIs[0] src2_modifiers
     /*  956375 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956378 */     // MIs[0] matrix_a_scale
     /*  956378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956381 */     // MIs[0] matrix_a_scale_fmt
     /*  956381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  956384 */     // MIs[0] matrix_b_scale
     /*  956384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956387 */     // MIs[0] matrix_b_scale_fmt
     /*  956387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  956390 */     // MIs[0] matrix_a_reuse
     /*  956390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956393 */     // MIs[0] matrix_b_reuse
     /*  956393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  956396 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr),
     /*  956399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956401 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  956403 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  956405 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956411 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  956413 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  956415 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  956417 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  956419 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  956421 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  956423 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  956425 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  956427 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  956429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956435 */     GIR_RootConstrainSelectedInstOperands,
     /*  956436 */     // GIR_Coverage, 8281,
     /*  956436 */     GIR_EraseRootFromParent_Done,
     /*  956437 */   // Label 15199: @956437
     /*  956437 */   GIM_Try, /*On fail goto*//*Label 15200*/ GIMT_Encode4(956534), // Rule ID 8282 //
     /*  956442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  956445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_32x16x128_f4),
     /*  956450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32,
     /*  956453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s32,
     /*  956456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  956459 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956462 */     GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s64,
     /*  956465 */     GIM_RootCheckType, /*Op*/11, /*Type*/GILLT_s64,
     /*  956468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
     /*  956472 */     // MIs[0] src2_modifiers
     /*  956472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956475 */     // MIs[0] matrix_a_scale
     /*  956475 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956478 */     // MIs[0] matrix_a_scale_fmt
     /*  956478 */     GIM_CheckIsImm, /*MI*/0, /*Op*/7,
     /*  956481 */     // MIs[0] matrix_b_scale
     /*  956481 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956484 */     // MIs[0] matrix_b_scale_fmt
     /*  956484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/10,
     /*  956487 */     // MIs[0] matrix_a_reuse
     /*  956487 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956490 */     // MIs[0] matrix_b_reuse
     /*  956490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/13,
     /*  956493 */     // (intrinsic_wo_chain:{ *:[v16f32] } 3671:{ *:[iPTR] }, v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr:{ *:[v16f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v16f32:{ *:[v16f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr),
     /*  956496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956498 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  956500 */     GIR_RootToRootCopy, /*OpIdx*/3, // src1
     /*  956502 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956508 */     GIR_RootToRootCopy, /*OpIdx*/5, // src2
     /*  956510 */     GIR_RootToRootCopy, /*OpIdx*/8, // scale_src0
     /*  956512 */     GIR_RootToRootCopy, /*OpIdx*/11, // scale_src1
     /*  956514 */     GIR_RootToRootCopy, /*OpIdx*/6, // matrix_a_scale
     /*  956516 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_b_scale
     /*  956518 */     GIR_RootToRootCopy, /*OpIdx*/7, // matrix_a_scale_fmt
     /*  956520 */     GIR_RootToRootCopy, /*OpIdx*/10, // matrix_b_scale_fmt
     /*  956522 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_a_reuse
     /*  956524 */     GIR_RootToRootCopy, /*OpIdx*/13, // matrix_b_reuse
     /*  956526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956532 */     GIR_RootConstrainSelectedInstOperands,
     /*  956533 */     // GIR_Coverage, 8282,
     /*  956533 */     GIR_EraseRootFromParent_Done,
     /*  956534 */   // Label 15200: @956534
     /*  956534 */   GIM_Reject,
     /*  956535 */ // Label 15180: @956535
     /*  956535 */ GIM_Try, /*On fail goto*//*Label 15201*/ GIMT_Encode4(976704),
     /*  956540 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/16,
     /*  956543 */   GIM_Try, /*On fail goto*//*Label 15202*/ GIMT_Encode4(956660), // Rule ID 8303 //
     /*  956548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  956551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  956556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  956559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  956562 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956565 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  956568 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  956571 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  956574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  956578 */     // MIs[0] matrix_a_fmt
     /*  956578 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  956581 */     // MIs[0] matrix_b_fmt
     /*  956581 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956584 */     // MIs[0] src2_modifiers
     /*  956584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956587 */     // MIs[0] matrix_a_scale
     /*  956587 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  956590 */     // MIs[0] matrix_a_scale_fmt
     /*  956590 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956593 */     // MIs[0] matrix_b_scale
     /*  956593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  956596 */     // MIs[0] matrix_b_scale_fmt
     /*  956596 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956599 */     // MIs[0] matrix_a_reuse
     /*  956599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  956602 */     // MIs[0] matrix_b_reuse
     /*  956602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  956605 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  956612 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  956615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956617 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  956619 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  956621 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956627 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  956632 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  956634 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  956636 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  956638 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  956640 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  956642 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  956644 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  956646 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  956648 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  956650 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  956652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956658 */     GIR_RootConstrainSelectedInstOperands,
     /*  956659 */     // GIR_Coverage, 8303,
     /*  956659 */     GIR_EraseRootFromParent_Done,
     /*  956660 */   // Label 15202: @956660
     /*  956660 */   GIM_Try, /*On fail goto*//*Label 15203*/ GIMT_Encode4(956777), // Rule ID 8304 //
     /*  956665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  956668 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  956673 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  956676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  956679 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956682 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  956685 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  956688 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  956691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  956695 */     // MIs[0] matrix_a_fmt
     /*  956695 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  956698 */     // MIs[0] matrix_b_fmt
     /*  956698 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956701 */     // MIs[0] src2_modifiers
     /*  956701 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956704 */     // MIs[0] matrix_a_scale
     /*  956704 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  956707 */     // MIs[0] matrix_a_scale_fmt
     /*  956707 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956710 */     // MIs[0] matrix_b_scale
     /*  956710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  956713 */     // MIs[0] matrix_b_scale_fmt
     /*  956713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956716 */     // MIs[0] matrix_a_reuse
     /*  956716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  956719 */     // MIs[0] matrix_b_reuse
     /*  956719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  956722 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  956729 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  956732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956734 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  956736 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  956738 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  956749 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  956751 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  956753 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  956755 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  956757 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  956759 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  956761 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  956763 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  956765 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  956767 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  956769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956775 */     GIR_RootConstrainSelectedInstOperands,
     /*  956776 */     // GIR_Coverage, 8304,
     /*  956776 */     GIR_EraseRootFromParent_Done,
     /*  956777 */   // Label 15203: @956777
     /*  956777 */   GIM_Try, /*On fail goto*//*Label 15204*/ GIMT_Encode4(956894), // Rule ID 8305 //
     /*  956782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  956785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  956790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  956793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  956796 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956799 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  956802 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  956805 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  956808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  956812 */     // MIs[0] matrix_a_fmt
     /*  956812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  956815 */     // MIs[0] matrix_b_fmt
     /*  956815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956818 */     // MIs[0] src2_modifiers
     /*  956818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956821 */     // MIs[0] matrix_a_scale
     /*  956821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  956824 */     // MIs[0] matrix_a_scale_fmt
     /*  956824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956827 */     // MIs[0] matrix_b_scale
     /*  956827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  956830 */     // MIs[0] matrix_b_scale_fmt
     /*  956830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956833 */     // MIs[0] matrix_a_reuse
     /*  956833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  956836 */     // MIs[0] matrix_b_reuse
     /*  956836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  956839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  956846 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  956849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956851 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  956853 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  956855 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  956866 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  956868 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  956870 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  956872 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  956874 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  956876 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  956878 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  956880 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  956882 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  956884 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  956886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  956892 */     GIR_RootConstrainSelectedInstOperands,
     /*  956893 */     // GIR_Coverage, 8305,
     /*  956893 */     GIR_EraseRootFromParent_Done,
     /*  956894 */   // Label 15204: @956894
     /*  956894 */   GIM_Try, /*On fail goto*//*Label 15205*/ GIMT_Encode4(957011), // Rule ID 8306 //
     /*  956899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  956902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  956907 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  956910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  956913 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  956916 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  956919 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  956922 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  956925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  956929 */     // MIs[0] matrix_a_fmt
     /*  956929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  956932 */     // MIs[0] matrix_b_fmt
     /*  956932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  956935 */     // MIs[0] src2_modifiers
     /*  956935 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  956938 */     // MIs[0] matrix_a_scale
     /*  956938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  956941 */     // MIs[0] matrix_a_scale_fmt
     /*  956941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  956944 */     // MIs[0] matrix_b_scale
     /*  956944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  956947 */     // MIs[0] matrix_b_scale_fmt
     /*  956947 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  956950 */     // MIs[0] matrix_a_reuse
     /*  956950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  956953 */     // MIs[0] matrix_b_reuse
     /*  956953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  956956 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  956963 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  956963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  956966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  956968 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  956970 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  956972 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  956978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  956983 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  956985 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  956987 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  956989 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  956991 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  956993 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  956995 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  956997 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  956999 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957001 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957009 */     GIR_RootConstrainSelectedInstOperands,
     /*  957010 */     // GIR_Coverage, 8306,
     /*  957010 */     GIR_EraseRootFromParent_Done,
     /*  957011 */   // Label 15205: @957011
     /*  957011 */   GIM_Try, /*On fail goto*//*Label 15206*/ GIMT_Encode4(957128), // Rule ID 8307 //
     /*  957016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  957019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  957024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957030 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  957033 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957036 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  957039 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  957042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957046 */     // MIs[0] matrix_a_fmt
     /*  957046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957049 */     // MIs[0] matrix_b_fmt
     /*  957049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957052 */     // MIs[0] src2_modifiers
     /*  957052 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957055 */     // MIs[0] matrix_a_scale
     /*  957055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957058 */     // MIs[0] matrix_a_scale_fmt
     /*  957058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957061 */     // MIs[0] matrix_b_scale
     /*  957061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957064 */     // MIs[0] matrix_b_scale_fmt
     /*  957064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957067 */     // MIs[0] matrix_a_reuse
     /*  957067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957070 */     // MIs[0] matrix_b_reuse
     /*  957070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957073 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957080 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  957083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957085 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957087 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957089 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957100 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957102 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957104 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957106 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957108 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957110 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957112 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957114 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957116 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957118 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957126 */     GIR_RootConstrainSelectedInstOperands,
     /*  957127 */     // GIR_Coverage, 8307,
     /*  957127 */     GIR_EraseRootFromParent_Done,
     /*  957128 */   // Label 15206: @957128
     /*  957128 */   GIM_Try, /*On fail goto*//*Label 15207*/ GIMT_Encode4(957245), // Rule ID 8313 //
     /*  957133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  957136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  957141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957147 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  957150 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957153 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  957156 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  957159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957163 */     // MIs[0] matrix_a_fmt
     /*  957163 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957166 */     // MIs[0] matrix_b_fmt
     /*  957166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957169 */     // MIs[0] src2_modifiers
     /*  957169 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957172 */     // MIs[0] matrix_a_scale
     /*  957172 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957175 */     // MIs[0] matrix_a_scale_fmt
     /*  957175 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957178 */     // MIs[0] matrix_b_scale
     /*  957178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957181 */     // MIs[0] matrix_b_scale_fmt
     /*  957181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957184 */     // MIs[0] matrix_a_reuse
     /*  957184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957187 */     // MIs[0] matrix_b_reuse
     /*  957187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957190 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957197 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  957200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957202 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957204 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957206 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957212 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957217 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957219 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957221 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957223 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957225 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957227 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957229 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957231 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957233 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957235 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957243 */     GIR_RootConstrainSelectedInstOperands,
     /*  957244 */     // GIR_Coverage, 8313,
     /*  957244 */     GIR_EraseRootFromParent_Done,
     /*  957245 */   // Label 15207: @957245
     /*  957245 */   GIM_Try, /*On fail goto*//*Label 15208*/ GIMT_Encode4(957362), // Rule ID 8314 //
     /*  957250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  957253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  957258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957264 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  957267 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957270 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  957273 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  957276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957280 */     // MIs[0] matrix_a_fmt
     /*  957280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957283 */     // MIs[0] matrix_b_fmt
     /*  957283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957286 */     // MIs[0] src2_modifiers
     /*  957286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957289 */     // MIs[0] matrix_a_scale
     /*  957289 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957292 */     // MIs[0] matrix_a_scale_fmt
     /*  957292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957295 */     // MIs[0] matrix_b_scale
     /*  957295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957298 */     // MIs[0] matrix_b_scale_fmt
     /*  957298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957301 */     // MIs[0] matrix_a_reuse
     /*  957301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957304 */     // MIs[0] matrix_b_reuse
     /*  957304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957314 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  957317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957319 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957321 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957323 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957334 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957336 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957338 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957340 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957342 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957344 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957346 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957348 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957350 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957352 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957354 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957357 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957360 */     GIR_RootConstrainSelectedInstOperands,
     /*  957361 */     // GIR_Coverage, 8314,
     /*  957361 */     GIR_EraseRootFromParent_Done,
     /*  957362 */   // Label 15208: @957362
     /*  957362 */   GIM_Try, /*On fail goto*//*Label 15209*/ GIMT_Encode4(957479), // Rule ID 8315 //
     /*  957367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  957370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  957375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957378 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957381 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  957384 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957387 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  957390 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  957393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957397 */     // MIs[0] matrix_a_fmt
     /*  957397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957400 */     // MIs[0] matrix_b_fmt
     /*  957400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957403 */     // MIs[0] src2_modifiers
     /*  957403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957406 */     // MIs[0] matrix_a_scale
     /*  957406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957409 */     // MIs[0] matrix_a_scale_fmt
     /*  957409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957412 */     // MIs[0] matrix_b_scale
     /*  957412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957415 */     // MIs[0] matrix_b_scale_fmt
     /*  957415 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957418 */     // MIs[0] matrix_a_reuse
     /*  957418 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957421 */     // MIs[0] matrix_b_reuse
     /*  957421 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957424 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957431 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  957434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957436 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957438 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957440 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957451 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957453 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957455 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957457 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957459 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957461 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957463 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957465 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957467 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957469 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957477 */     GIR_RootConstrainSelectedInstOperands,
     /*  957478 */     // GIR_Coverage, 8315,
     /*  957478 */     GIR_EraseRootFromParent_Done,
     /*  957479 */   // Label 15209: @957479
     /*  957479 */   GIM_Try, /*On fail goto*//*Label 15210*/ GIMT_Encode4(957596), // Rule ID 8316 //
     /*  957484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  957487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  957492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957495 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957498 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  957501 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957504 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  957507 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  957510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957514 */     // MIs[0] matrix_a_fmt
     /*  957514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957517 */     // MIs[0] matrix_b_fmt
     /*  957517 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957520 */     // MIs[0] src2_modifiers
     /*  957520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957523 */     // MIs[0] matrix_a_scale
     /*  957523 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957526 */     // MIs[0] matrix_a_scale_fmt
     /*  957526 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957529 */     // MIs[0] matrix_b_scale
     /*  957529 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957532 */     // MIs[0] matrix_b_scale_fmt
     /*  957532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957535 */     // MIs[0] matrix_a_reuse
     /*  957535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957538 */     // MIs[0] matrix_b_reuse
     /*  957538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957541 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957548 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  957551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957553 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957555 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957557 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957568 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957570 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957572 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957574 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957576 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957578 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957580 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957582 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957584 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957586 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957594 */     GIR_RootConstrainSelectedInstOperands,
     /*  957595 */     // GIR_Coverage, 8316,
     /*  957595 */     GIR_EraseRootFromParent_Done,
     /*  957596 */   // Label 15210: @957596
     /*  957596 */   GIM_Try, /*On fail goto*//*Label 15211*/ GIMT_Encode4(957713), // Rule ID 8317 //
     /*  957601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  957604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  957609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957615 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  957618 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957621 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  957624 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  957627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957631 */     // MIs[0] matrix_a_fmt
     /*  957631 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957634 */     // MIs[0] matrix_b_fmt
     /*  957634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957637 */     // MIs[0] src2_modifiers
     /*  957637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957640 */     // MIs[0] matrix_a_scale
     /*  957640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957643 */     // MIs[0] matrix_a_scale_fmt
     /*  957643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957646 */     // MIs[0] matrix_b_scale
     /*  957646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957649 */     // MIs[0] matrix_b_scale_fmt
     /*  957649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957652 */     // MIs[0] matrix_a_reuse
     /*  957652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957655 */     // MIs[0] matrix_b_reuse
     /*  957655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957665 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr),
     /*  957668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957670 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957672 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957674 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957685 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957687 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957689 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957691 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957693 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957695 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957697 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957699 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957701 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957703 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957705 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957708 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957711 */     GIR_RootConstrainSelectedInstOperands,
     /*  957712 */     // GIR_Coverage, 8317,
     /*  957712 */     GIR_EraseRootFromParent_Done,
     /*  957713 */   // Label 15211: @957713
     /*  957713 */   GIM_Try, /*On fail goto*//*Label 15212*/ GIMT_Encode4(957830), // Rule ID 8333 //
     /*  957718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  957721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  957726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957732 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  957735 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957738 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  957741 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  957744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957748 */     // MIs[0] matrix_a_fmt
     /*  957748 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957751 */     // MIs[0] matrix_b_fmt
     /*  957751 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957754 */     // MIs[0] src2_modifiers
     /*  957754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957757 */     // MIs[0] matrix_a_scale
     /*  957757 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957760 */     // MIs[0] matrix_a_scale_fmt
     /*  957760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957763 */     // MIs[0] matrix_b_scale
     /*  957763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957766 */     // MIs[0] matrix_b_scale_fmt
     /*  957766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957769 */     // MIs[0] matrix_a_reuse
     /*  957769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957772 */     // MIs[0] matrix_b_reuse
     /*  957772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957775 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957782 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  957785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957787 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957789 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957791 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957802 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957804 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957806 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957808 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957810 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957812 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957814 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957816 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957818 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957820 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957822 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957825 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957828 */     GIR_RootConstrainSelectedInstOperands,
     /*  957829 */     // GIR_Coverage, 8333,
     /*  957829 */     GIR_EraseRootFromParent_Done,
     /*  957830 */   // Label 15212: @957830
     /*  957830 */   GIM_Try, /*On fail goto*//*Label 15213*/ GIMT_Encode4(957947), // Rule ID 8334 //
     /*  957835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  957838 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  957843 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957849 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  957852 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957855 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  957858 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  957861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957865 */     // MIs[0] matrix_a_fmt
     /*  957865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957868 */     // MIs[0] matrix_b_fmt
     /*  957868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957871 */     // MIs[0] src2_modifiers
     /*  957871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957874 */     // MIs[0] matrix_a_scale
     /*  957874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957877 */     // MIs[0] matrix_a_scale_fmt
     /*  957877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957880 */     // MIs[0] matrix_b_scale
     /*  957880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  957883 */     // MIs[0] matrix_b_scale_fmt
     /*  957883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  957886 */     // MIs[0] matrix_a_reuse
     /*  957886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  957889 */     // MIs[0] matrix_b_reuse
     /*  957889 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  957892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  957899 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  957899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  957902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  957904 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  957906 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  957908 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  957914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  957919 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  957921 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  957923 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  957925 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  957927 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  957929 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  957931 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  957933 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  957935 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  957937 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  957939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  957945 */     GIR_RootConstrainSelectedInstOperands,
     /*  957946 */     // GIR_Coverage, 8334,
     /*  957946 */     GIR_EraseRootFromParent_Done,
     /*  957947 */   // Label 15213: @957947
     /*  957947 */   GIM_Try, /*On fail goto*//*Label 15214*/ GIMT_Encode4(958064), // Rule ID 8335 //
     /*  957952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  957955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  957960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  957963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  957966 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  957969 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  957972 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  957975 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  957978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  957982 */     // MIs[0] matrix_a_fmt
     /*  957982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  957985 */     // MIs[0] matrix_b_fmt
     /*  957985 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  957988 */     // MIs[0] src2_modifiers
     /*  957988 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  957991 */     // MIs[0] matrix_a_scale
     /*  957991 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  957994 */     // MIs[0] matrix_a_scale_fmt
     /*  957994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  957997 */     // MIs[0] matrix_b_scale
     /*  957997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958000 */     // MIs[0] matrix_b_scale_fmt
     /*  958000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958003 */     // MIs[0] matrix_a_reuse
     /*  958003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958006 */     // MIs[0] matrix_b_reuse
     /*  958006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958009 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958016 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958021 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958023 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958025 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958036 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958038 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958040 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958042 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958044 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958046 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958048 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958050 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958052 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958054 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958062 */     GIR_RootConstrainSelectedInstOperands,
     /*  958063 */     // GIR_Coverage, 8335,
     /*  958063 */     GIR_EraseRootFromParent_Done,
     /*  958064 */   // Label 15214: @958064
     /*  958064 */   GIM_Try, /*On fail goto*//*Label 15215*/ GIMT_Encode4(958181), // Rule ID 8336 //
     /*  958069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  958072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  958077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958083 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958086 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958089 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  958092 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  958095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958099 */     // MIs[0] matrix_a_fmt
     /*  958099 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958102 */     // MIs[0] matrix_b_fmt
     /*  958102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958105 */     // MIs[0] src2_modifiers
     /*  958105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958108 */     // MIs[0] matrix_a_scale
     /*  958108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958111 */     // MIs[0] matrix_a_scale_fmt
     /*  958111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958114 */     // MIs[0] matrix_b_scale
     /*  958114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958117 */     // MIs[0] matrix_b_scale_fmt
     /*  958117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958120 */     // MIs[0] matrix_a_reuse
     /*  958120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958123 */     // MIs[0] matrix_b_reuse
     /*  958123 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958126 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958133 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958138 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958140 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958142 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958153 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958155 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958157 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958159 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958161 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958163 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958165 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958167 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958169 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958171 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958173 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958179 */     GIR_RootConstrainSelectedInstOperands,
     /*  958180 */     // GIR_Coverage, 8336,
     /*  958180 */     GIR_EraseRootFromParent_Done,
     /*  958181 */   // Label 15215: @958181
     /*  958181 */   GIM_Try, /*On fail goto*//*Label 15216*/ GIMT_Encode4(958298), // Rule ID 8337 //
     /*  958186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  958189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  958194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958200 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958203 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958206 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  958209 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  958212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958216 */     // MIs[0] matrix_a_fmt
     /*  958216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958219 */     // MIs[0] matrix_b_fmt
     /*  958219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958222 */     // MIs[0] src2_modifiers
     /*  958222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958225 */     // MIs[0] matrix_a_scale
     /*  958225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958228 */     // MIs[0] matrix_a_scale_fmt
     /*  958228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958231 */     // MIs[0] matrix_b_scale
     /*  958231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958234 */     // MIs[0] matrix_b_scale_fmt
     /*  958234 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958237 */     // MIs[0] matrix_a_reuse
     /*  958237 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958240 */     // MIs[0] matrix_b_reuse
     /*  958240 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958250 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958255 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958257 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958259 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958270 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958272 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958274 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958276 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958278 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958280 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958282 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958284 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958286 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958288 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958296 */     GIR_RootConstrainSelectedInstOperands,
     /*  958297 */     // GIR_Coverage, 8337,
     /*  958297 */     GIR_EraseRootFromParent_Done,
     /*  958298 */   // Label 15216: @958298
     /*  958298 */   GIM_Try, /*On fail goto*//*Label 15217*/ GIMT_Encode4(958415), // Rule ID 8343 //
     /*  958303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  958306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  958311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958317 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958320 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958323 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  958326 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  958329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958333 */     // MIs[0] matrix_a_fmt
     /*  958333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958336 */     // MIs[0] matrix_b_fmt
     /*  958336 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958339 */     // MIs[0] src2_modifiers
     /*  958339 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958342 */     // MIs[0] matrix_a_scale
     /*  958342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958345 */     // MIs[0] matrix_a_scale_fmt
     /*  958345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958348 */     // MIs[0] matrix_b_scale
     /*  958348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958351 */     // MIs[0] matrix_b_scale_fmt
     /*  958351 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958354 */     // MIs[0] matrix_a_reuse
     /*  958354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958357 */     // MIs[0] matrix_b_reuse
     /*  958357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958360 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958367 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958372 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958374 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958376 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958387 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958389 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958391 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958393 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958395 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958397 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958399 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958401 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958403 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958405 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958413 */     GIR_RootConstrainSelectedInstOperands,
     /*  958414 */     // GIR_Coverage, 8343,
     /*  958414 */     GIR_EraseRootFromParent_Done,
     /*  958415 */   // Label 15217: @958415
     /*  958415 */   GIM_Try, /*On fail goto*//*Label 15218*/ GIMT_Encode4(958532), // Rule ID 8344 //
     /*  958420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  958423 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  958428 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958431 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958434 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958437 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958440 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  958443 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  958446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958450 */     // MIs[0] matrix_a_fmt
     /*  958450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958453 */     // MIs[0] matrix_b_fmt
     /*  958453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958456 */     // MIs[0] src2_modifiers
     /*  958456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958459 */     // MIs[0] matrix_a_scale
     /*  958459 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958462 */     // MIs[0] matrix_a_scale_fmt
     /*  958462 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958465 */     // MIs[0] matrix_b_scale
     /*  958465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958468 */     // MIs[0] matrix_b_scale_fmt
     /*  958468 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958471 */     // MIs[0] matrix_a_reuse
     /*  958471 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958474 */     // MIs[0] matrix_b_reuse
     /*  958474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958477 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958484 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958489 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958491 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958493 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958499 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958504 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958506 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958508 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958510 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958512 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958514 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958516 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958518 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958520 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958522 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958524 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958530 */     GIR_RootConstrainSelectedInstOperands,
     /*  958531 */     // GIR_Coverage, 8344,
     /*  958531 */     GIR_EraseRootFromParent_Done,
     /*  958532 */   // Label 15218: @958532
     /*  958532 */   GIM_Try, /*On fail goto*//*Label 15219*/ GIMT_Encode4(958649), // Rule ID 8345 //
     /*  958537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  958540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  958545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958551 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958554 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958557 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  958560 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  958563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958567 */     // MIs[0] matrix_a_fmt
     /*  958567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958570 */     // MIs[0] matrix_b_fmt
     /*  958570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958573 */     // MIs[0] src2_modifiers
     /*  958573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958576 */     // MIs[0] matrix_a_scale
     /*  958576 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958579 */     // MIs[0] matrix_a_scale_fmt
     /*  958579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958582 */     // MIs[0] matrix_b_scale
     /*  958582 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958585 */     // MIs[0] matrix_b_scale_fmt
     /*  958585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958588 */     // MIs[0] matrix_a_reuse
     /*  958588 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958591 */     // MIs[0] matrix_b_reuse
     /*  958591 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958601 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958606 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958608 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958610 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958621 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958623 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958625 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958627 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958629 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958631 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958633 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958635 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958637 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958639 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958644 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958647 */     GIR_RootConstrainSelectedInstOperands,
     /*  958648 */     // GIR_Coverage, 8345,
     /*  958648 */     GIR_EraseRootFromParent_Done,
     /*  958649 */   // Label 15219: @958649
     /*  958649 */   GIM_Try, /*On fail goto*//*Label 15220*/ GIMT_Encode4(958766), // Rule ID 8346 //
     /*  958654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  958657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  958662 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958668 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958671 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958674 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  958677 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  958680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958684 */     // MIs[0] matrix_a_fmt
     /*  958684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958687 */     // MIs[0] matrix_b_fmt
     /*  958687 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958690 */     // MIs[0] src2_modifiers
     /*  958690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958693 */     // MIs[0] matrix_a_scale
     /*  958693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958696 */     // MIs[0] matrix_a_scale_fmt
     /*  958696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958699 */     // MIs[0] matrix_b_scale
     /*  958699 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958702 */     // MIs[0] matrix_b_scale_fmt
     /*  958702 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958705 */     // MIs[0] matrix_a_reuse
     /*  958705 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958708 */     // MIs[0] matrix_b_reuse
     /*  958708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958718 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958723 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958725 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958727 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958738 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958740 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958742 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958744 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958746 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958748 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958750 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958752 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958754 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958756 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958758 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958764 */     GIR_RootConstrainSelectedInstOperands,
     /*  958765 */     // GIR_Coverage, 8346,
     /*  958765 */     GIR_EraseRootFromParent_Done,
     /*  958766 */   // Label 15220: @958766
     /*  958766 */   GIM_Try, /*On fail goto*//*Label 15221*/ GIMT_Encode4(958883), // Rule ID 8347 //
     /*  958771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  958774 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  958779 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958785 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  958788 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958791 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  958794 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  958797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958801 */     // MIs[0] matrix_a_fmt
     /*  958801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958804 */     // MIs[0] matrix_b_fmt
     /*  958804 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958807 */     // MIs[0] src2_modifiers
     /*  958807 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958810 */     // MIs[0] matrix_a_scale
     /*  958810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958813 */     // MIs[0] matrix_a_scale_fmt
     /*  958813 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958816 */     // MIs[0] matrix_b_scale
     /*  958816 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958819 */     // MIs[0] matrix_b_scale_fmt
     /*  958819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958822 */     // MIs[0] matrix_a_reuse
     /*  958822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958825 */     // MIs[0] matrix_b_reuse
     /*  958825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958828 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958835 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr),
     /*  958838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958840 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958842 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958844 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958855 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958857 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958859 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958861 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958863 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958865 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958867 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958869 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958871 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958873 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958881 */     GIR_RootConstrainSelectedInstOperands,
     /*  958882 */     // GIR_Coverage, 8347,
     /*  958882 */     GIR_EraseRootFromParent_Done,
     /*  958883 */   // Label 15221: @958883
     /*  958883 */   GIM_Try, /*On fail goto*//*Label 15222*/ GIMT_Encode4(959000), // Rule ID 8363 //
     /*  958888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  958891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  958896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  958899 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  958902 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  958905 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  958908 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  958911 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  958914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  958918 */     // MIs[0] matrix_a_fmt
     /*  958918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  958921 */     // MIs[0] matrix_b_fmt
     /*  958921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  958924 */     // MIs[0] src2_modifiers
     /*  958924 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  958927 */     // MIs[0] matrix_a_scale
     /*  958927 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  958930 */     // MIs[0] matrix_a_scale_fmt
     /*  958930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  958933 */     // MIs[0] matrix_b_scale
     /*  958933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  958936 */     // MIs[0] matrix_b_scale_fmt
     /*  958936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  958939 */     // MIs[0] matrix_a_reuse
     /*  958939 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  958942 */     // MIs[0] matrix_b_reuse
     /*  958942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  958945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  958952 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  958952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  958955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  958957 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  958959 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  958961 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  958967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  958972 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  958974 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  958976 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  958978 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  958980 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  958982 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  958984 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  958986 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  958988 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  958990 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  958992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  958998 */     GIR_RootConstrainSelectedInstOperands,
     /*  958999 */     // GIR_Coverage, 8363,
     /*  958999 */     GIR_EraseRootFromParent_Done,
     /*  959000 */   // Label 15222: @959000
     /*  959000 */   GIM_Try, /*On fail goto*//*Label 15223*/ GIMT_Encode4(959117), // Rule ID 8364 //
     /*  959005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  959008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  959013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959016 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959019 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959022 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959025 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  959028 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  959031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959035 */     // MIs[0] matrix_a_fmt
     /*  959035 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959038 */     // MIs[0] matrix_b_fmt
     /*  959038 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959041 */     // MIs[0] src2_modifiers
     /*  959041 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959044 */     // MIs[0] matrix_a_scale
     /*  959044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959047 */     // MIs[0] matrix_a_scale_fmt
     /*  959047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959050 */     // MIs[0] matrix_b_scale
     /*  959050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959053 */     // MIs[0] matrix_b_scale_fmt
     /*  959053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959056 */     // MIs[0] matrix_a_reuse
     /*  959056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959059 */     // MIs[0] matrix_b_reuse
     /*  959059 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959062 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959069 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959074 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959076 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959078 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959089 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959091 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959093 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959095 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959097 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959099 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959101 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959103 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959105 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959107 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959109 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959112 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959115 */     GIR_RootConstrainSelectedInstOperands,
     /*  959116 */     // GIR_Coverage, 8364,
     /*  959116 */     GIR_EraseRootFromParent_Done,
     /*  959117 */   // Label 15223: @959117
     /*  959117 */   GIM_Try, /*On fail goto*//*Label 15224*/ GIMT_Encode4(959234), // Rule ID 8365 //
     /*  959122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  959125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  959130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959136 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959139 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959142 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  959145 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  959148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959152 */     // MIs[0] matrix_a_fmt
     /*  959152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959155 */     // MIs[0] matrix_b_fmt
     /*  959155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959158 */     // MIs[0] src2_modifiers
     /*  959158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959161 */     // MIs[0] matrix_a_scale
     /*  959161 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959164 */     // MIs[0] matrix_a_scale_fmt
     /*  959164 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959167 */     // MIs[0] matrix_b_scale
     /*  959167 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959170 */     // MIs[0] matrix_b_scale_fmt
     /*  959170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959173 */     // MIs[0] matrix_a_reuse
     /*  959173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959176 */     // MIs[0] matrix_b_reuse
     /*  959176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959179 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959186 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959191 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959193 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959195 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959206 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959208 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959210 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959212 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959214 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959216 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959218 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959220 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959222 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959224 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959226 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959229 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959232 */     GIR_RootConstrainSelectedInstOperands,
     /*  959233 */     // GIR_Coverage, 8365,
     /*  959233 */     GIR_EraseRootFromParent_Done,
     /*  959234 */   // Label 15224: @959234
     /*  959234 */   GIM_Try, /*On fail goto*//*Label 15225*/ GIMT_Encode4(959351), // Rule ID 8366 //
     /*  959239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  959242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  959247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959253 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959256 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959259 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  959262 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  959265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959269 */     // MIs[0] matrix_a_fmt
     /*  959269 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959272 */     // MIs[0] matrix_b_fmt
     /*  959272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959275 */     // MIs[0] src2_modifiers
     /*  959275 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959278 */     // MIs[0] matrix_a_scale
     /*  959278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959281 */     // MIs[0] matrix_a_scale_fmt
     /*  959281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959284 */     // MIs[0] matrix_b_scale
     /*  959284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959287 */     // MIs[0] matrix_b_scale_fmt
     /*  959287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959290 */     // MIs[0] matrix_a_reuse
     /*  959290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959293 */     // MIs[0] matrix_b_reuse
     /*  959293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959303 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959308 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959310 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959312 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959323 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959325 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959327 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959329 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959331 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959333 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959335 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959337 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959339 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959341 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959343 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959349 */     GIR_RootConstrainSelectedInstOperands,
     /*  959350 */     // GIR_Coverage, 8366,
     /*  959350 */     GIR_EraseRootFromParent_Done,
     /*  959351 */   // Label 15225: @959351
     /*  959351 */   GIM_Try, /*On fail goto*//*Label 15226*/ GIMT_Encode4(959468), // Rule ID 8367 //
     /*  959356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  959359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  959364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959370 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959373 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959376 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  959379 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  959382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959386 */     // MIs[0] matrix_a_fmt
     /*  959386 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959389 */     // MIs[0] matrix_b_fmt
     /*  959389 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959392 */     // MIs[0] src2_modifiers
     /*  959392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959395 */     // MIs[0] matrix_a_scale
     /*  959395 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959398 */     // MIs[0] matrix_a_scale_fmt
     /*  959398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959401 */     // MIs[0] matrix_b_scale
     /*  959401 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959404 */     // MIs[0] matrix_b_scale_fmt
     /*  959404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959407 */     // MIs[0] matrix_a_reuse
     /*  959407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959410 */     // MIs[0] matrix_b_reuse
     /*  959410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959413 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959420 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959425 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959427 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959429 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959440 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959442 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959444 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959446 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959448 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959450 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959452 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959454 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959456 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959458 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959463 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959466 */     GIR_RootConstrainSelectedInstOperands,
     /*  959467 */     // GIR_Coverage, 8367,
     /*  959467 */     GIR_EraseRootFromParent_Done,
     /*  959468 */   // Label 15226: @959468
     /*  959468 */   GIM_Try, /*On fail goto*//*Label 15227*/ GIMT_Encode4(959585), // Rule ID 8373 //
     /*  959473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  959476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  959481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959487 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959490 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959493 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  959496 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  959499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959503 */     // MIs[0] matrix_a_fmt
     /*  959503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959506 */     // MIs[0] matrix_b_fmt
     /*  959506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959509 */     // MIs[0] src2_modifiers
     /*  959509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959512 */     // MIs[0] matrix_a_scale
     /*  959512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959515 */     // MIs[0] matrix_a_scale_fmt
     /*  959515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959518 */     // MIs[0] matrix_b_scale
     /*  959518 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959521 */     // MIs[0] matrix_b_scale_fmt
     /*  959521 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959524 */     // MIs[0] matrix_a_reuse
     /*  959524 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959527 */     // MIs[0] matrix_b_reuse
     /*  959527 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959530 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959537 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959542 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959544 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959546 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959557 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959559 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959561 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959563 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959565 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959567 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959569 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959571 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959573 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959575 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959577 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959583 */     GIR_RootConstrainSelectedInstOperands,
     /*  959584 */     // GIR_Coverage, 8373,
     /*  959584 */     GIR_EraseRootFromParent_Done,
     /*  959585 */   // Label 15227: @959585
     /*  959585 */   GIM_Try, /*On fail goto*//*Label 15228*/ GIMT_Encode4(959702), // Rule ID 8374 //
     /*  959590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  959593 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  959598 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959604 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959607 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959610 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  959613 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  959616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959620 */     // MIs[0] matrix_a_fmt
     /*  959620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959623 */     // MIs[0] matrix_b_fmt
     /*  959623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959626 */     // MIs[0] src2_modifiers
     /*  959626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959629 */     // MIs[0] matrix_a_scale
     /*  959629 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959632 */     // MIs[0] matrix_a_scale_fmt
     /*  959632 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959635 */     // MIs[0] matrix_b_scale
     /*  959635 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959638 */     // MIs[0] matrix_b_scale_fmt
     /*  959638 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959641 */     // MIs[0] matrix_a_reuse
     /*  959641 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959644 */     // MIs[0] matrix_b_reuse
     /*  959644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959654 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959659 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959661 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959663 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959674 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959676 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959678 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959680 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959682 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959684 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959686 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959688 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959690 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959692 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959694 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959700 */     GIR_RootConstrainSelectedInstOperands,
     /*  959701 */     // GIR_Coverage, 8374,
     /*  959701 */     GIR_EraseRootFromParent_Done,
     /*  959702 */   // Label 15228: @959702
     /*  959702 */   GIM_Try, /*On fail goto*//*Label 15229*/ GIMT_Encode4(959819), // Rule ID 8375 //
     /*  959707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  959710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  959715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959718 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959721 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959724 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959727 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  959730 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  959733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959737 */     // MIs[0] matrix_a_fmt
     /*  959737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959740 */     // MIs[0] matrix_b_fmt
     /*  959740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959743 */     // MIs[0] src2_modifiers
     /*  959743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959746 */     // MIs[0] matrix_a_scale
     /*  959746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959749 */     // MIs[0] matrix_a_scale_fmt
     /*  959749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959752 */     // MIs[0] matrix_b_scale
     /*  959752 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959755 */     // MIs[0] matrix_b_scale_fmt
     /*  959755 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959758 */     // MIs[0] matrix_a_reuse
     /*  959758 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959761 */     // MIs[0] matrix_b_reuse
     /*  959761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959764 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959771 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959776 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959778 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959780 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959786 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959791 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959793 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959795 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959797 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959799 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959801 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959803 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959805 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959807 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959809 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959817 */     GIR_RootConstrainSelectedInstOperands,
     /*  959818 */     // GIR_Coverage, 8375,
     /*  959818 */     GIR_EraseRootFromParent_Done,
     /*  959819 */   // Label 15229: @959819
     /*  959819 */   GIM_Try, /*On fail goto*//*Label 15230*/ GIMT_Encode4(959936), // Rule ID 8376 //
     /*  959824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  959827 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  959832 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959835 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959838 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959841 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959844 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  959847 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  959850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959854 */     // MIs[0] matrix_a_fmt
     /*  959854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959857 */     // MIs[0] matrix_b_fmt
     /*  959857 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959860 */     // MIs[0] src2_modifiers
     /*  959860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959863 */     // MIs[0] matrix_a_scale
     /*  959863 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959866 */     // MIs[0] matrix_a_scale_fmt
     /*  959866 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959869 */     // MIs[0] matrix_b_scale
     /*  959869 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959872 */     // MIs[0] matrix_b_scale_fmt
     /*  959872 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959875 */     // MIs[0] matrix_a_reuse
     /*  959875 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959878 */     // MIs[0] matrix_b_reuse
     /*  959878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  959888 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  959888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  959891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  959893 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  959895 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  959897 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  959903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  959908 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  959910 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  959912 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  959914 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  959916 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  959918 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  959920 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  959922 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  959924 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  959926 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  959928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959931 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  959934 */     GIR_RootConstrainSelectedInstOperands,
     /*  959935 */     // GIR_Coverage, 8376,
     /*  959935 */     GIR_EraseRootFromParent_Done,
     /*  959936 */   // Label 15230: @959936
     /*  959936 */   GIM_Try, /*On fail goto*//*Label 15231*/ GIMT_Encode4(960053), // Rule ID 8377 //
     /*  959941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  959944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  959949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  959952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  959955 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  959958 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  959961 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  959964 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  959967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  959971 */     // MIs[0] matrix_a_fmt
     /*  959971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  959974 */     // MIs[0] matrix_b_fmt
     /*  959974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  959977 */     // MIs[0] src2_modifiers
     /*  959977 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  959980 */     // MIs[0] matrix_a_scale
     /*  959980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  959983 */     // MIs[0] matrix_a_scale_fmt
     /*  959983 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  959986 */     // MIs[0] matrix_b_scale
     /*  959986 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  959989 */     // MIs[0] matrix_b_scale_fmt
     /*  959989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  959992 */     // MIs[0] matrix_a_reuse
     /*  959992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  959995 */     // MIs[0] matrix_b_reuse
     /*  959995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  959998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960005 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr),
     /*  960008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960010 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960012 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960014 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960025 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960027 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960029 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960031 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960033 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960035 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960037 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960039 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960041 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960043 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960051 */     GIR_RootConstrainSelectedInstOperands,
     /*  960052 */     // GIR_Coverage, 8377,
     /*  960052 */     GIR_EraseRootFromParent_Done,
     /*  960053 */   // Label 15231: @960053
     /*  960053 */   GIM_Try, /*On fail goto*//*Label 15232*/ GIMT_Encode4(960170), // Rule ID 8393 //
     /*  960058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  960061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  960066 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960069 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960072 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960075 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960078 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  960081 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  960084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960088 */     // MIs[0] matrix_a_fmt
     /*  960088 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960091 */     // MIs[0] matrix_b_fmt
     /*  960091 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960094 */     // MIs[0] src2_modifiers
     /*  960094 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960097 */     // MIs[0] matrix_a_scale
     /*  960097 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960100 */     // MIs[0] matrix_a_scale_fmt
     /*  960100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960103 */     // MIs[0] matrix_b_scale
     /*  960103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960106 */     // MIs[0] matrix_b_scale_fmt
     /*  960106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960109 */     // MIs[0] matrix_a_reuse
     /*  960109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960112 */     // MIs[0] matrix_b_reuse
     /*  960112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960115 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960122 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960127 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960129 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960131 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960142 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960144 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960146 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960148 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960150 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960152 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960154 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960156 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960158 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960160 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960162 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960165 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960168 */     GIR_RootConstrainSelectedInstOperands,
     /*  960169 */     // GIR_Coverage, 8393,
     /*  960169 */     GIR_EraseRootFromParent_Done,
     /*  960170 */   // Label 15232: @960170
     /*  960170 */   GIM_Try, /*On fail goto*//*Label 15233*/ GIMT_Encode4(960287), // Rule ID 8394 //
     /*  960175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  960178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  960183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960189 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960192 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960195 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  960198 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  960201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960205 */     // MIs[0] matrix_a_fmt
     /*  960205 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960208 */     // MIs[0] matrix_b_fmt
     /*  960208 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960211 */     // MIs[0] src2_modifiers
     /*  960211 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960214 */     // MIs[0] matrix_a_scale
     /*  960214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960217 */     // MIs[0] matrix_a_scale_fmt
     /*  960217 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960220 */     // MIs[0] matrix_b_scale
     /*  960220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960223 */     // MIs[0] matrix_b_scale_fmt
     /*  960223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960226 */     // MIs[0] matrix_a_reuse
     /*  960226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960229 */     // MIs[0] matrix_b_reuse
     /*  960229 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960239 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960244 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960246 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960248 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960259 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960261 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960263 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960265 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960267 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960269 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960271 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960273 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960275 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960277 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960282 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960285 */     GIR_RootConstrainSelectedInstOperands,
     /*  960286 */     // GIR_Coverage, 8394,
     /*  960286 */     GIR_EraseRootFromParent_Done,
     /*  960287 */   // Label 15233: @960287
     /*  960287 */   GIM_Try, /*On fail goto*//*Label 15234*/ GIMT_Encode4(960404), // Rule ID 8395 //
     /*  960292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  960295 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  960300 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960306 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960309 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960312 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  960315 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  960318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960322 */     // MIs[0] matrix_a_fmt
     /*  960322 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960325 */     // MIs[0] matrix_b_fmt
     /*  960325 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960328 */     // MIs[0] src2_modifiers
     /*  960328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960331 */     // MIs[0] matrix_a_scale
     /*  960331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960334 */     // MIs[0] matrix_a_scale_fmt
     /*  960334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960337 */     // MIs[0] matrix_b_scale
     /*  960337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960340 */     // MIs[0] matrix_b_scale_fmt
     /*  960340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960343 */     // MIs[0] matrix_a_reuse
     /*  960343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960346 */     // MIs[0] matrix_b_reuse
     /*  960346 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960349 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960356 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960361 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960363 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960365 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960376 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960378 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960380 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960382 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960384 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960386 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960388 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960390 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960392 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960394 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960396 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960399 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960402 */     GIR_RootConstrainSelectedInstOperands,
     /*  960403 */     // GIR_Coverage, 8395,
     /*  960403 */     GIR_EraseRootFromParent_Done,
     /*  960404 */   // Label 15234: @960404
     /*  960404 */   GIM_Try, /*On fail goto*//*Label 15235*/ GIMT_Encode4(960521), // Rule ID 8396 //
     /*  960409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  960412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  960417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960420 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960423 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960426 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960429 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  960432 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  960435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960439 */     // MIs[0] matrix_a_fmt
     /*  960439 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960442 */     // MIs[0] matrix_b_fmt
     /*  960442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960445 */     // MIs[0] src2_modifiers
     /*  960445 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960448 */     // MIs[0] matrix_a_scale
     /*  960448 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960451 */     // MIs[0] matrix_a_scale_fmt
     /*  960451 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960454 */     // MIs[0] matrix_b_scale
     /*  960454 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960457 */     // MIs[0] matrix_b_scale_fmt
     /*  960457 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960460 */     // MIs[0] matrix_a_reuse
     /*  960460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960463 */     // MIs[0] matrix_b_reuse
     /*  960463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960466 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960473 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960478 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960480 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960482 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960493 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960495 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960497 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960499 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960501 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960503 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960505 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960507 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960509 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960511 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960513 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960519 */     GIR_RootConstrainSelectedInstOperands,
     /*  960520 */     // GIR_Coverage, 8396,
     /*  960520 */     GIR_EraseRootFromParent_Done,
     /*  960521 */   // Label 15235: @960521
     /*  960521 */   GIM_Try, /*On fail goto*//*Label 15236*/ GIMT_Encode4(960638), // Rule ID 8397 //
     /*  960526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  960529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  960534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960540 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960543 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960546 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  960549 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  960552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960556 */     // MIs[0] matrix_a_fmt
     /*  960556 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960559 */     // MIs[0] matrix_b_fmt
     /*  960559 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960562 */     // MIs[0] src2_modifiers
     /*  960562 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960565 */     // MIs[0] matrix_a_scale
     /*  960565 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960568 */     // MIs[0] matrix_a_scale_fmt
     /*  960568 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960571 */     // MIs[0] matrix_b_scale
     /*  960571 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960574 */     // MIs[0] matrix_b_scale_fmt
     /*  960574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960577 */     // MIs[0] matrix_a_reuse
     /*  960577 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960580 */     // MIs[0] matrix_b_reuse
     /*  960580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960590 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960595 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960597 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960599 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960605 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960610 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960612 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960614 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960616 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960618 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960620 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960622 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960624 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960626 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960628 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960636 */     GIR_RootConstrainSelectedInstOperands,
     /*  960637 */     // GIR_Coverage, 8397,
     /*  960637 */     GIR_EraseRootFromParent_Done,
     /*  960638 */   // Label 15236: @960638
     /*  960638 */   GIM_Try, /*On fail goto*//*Label 15237*/ GIMT_Encode4(960755), // Rule ID 8403 //
     /*  960643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  960646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  960651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960657 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960660 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960663 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  960666 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  960669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960673 */     // MIs[0] matrix_a_fmt
     /*  960673 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960676 */     // MIs[0] matrix_b_fmt
     /*  960676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960679 */     // MIs[0] src2_modifiers
     /*  960679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960682 */     // MIs[0] matrix_a_scale
     /*  960682 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960685 */     // MIs[0] matrix_a_scale_fmt
     /*  960685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960688 */     // MIs[0] matrix_b_scale
     /*  960688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960691 */     // MIs[0] matrix_b_scale_fmt
     /*  960691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960694 */     // MIs[0] matrix_a_reuse
     /*  960694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960697 */     // MIs[0] matrix_b_reuse
     /*  960697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960700 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960707 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960712 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960714 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960716 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960722 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960727 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960729 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960731 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960733 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960735 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960737 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960739 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960741 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960743 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960745 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960753 */     GIR_RootConstrainSelectedInstOperands,
     /*  960754 */     // GIR_Coverage, 8403,
     /*  960754 */     GIR_EraseRootFromParent_Done,
     /*  960755 */   // Label 15237: @960755
     /*  960755 */   GIM_Try, /*On fail goto*//*Label 15238*/ GIMT_Encode4(960872), // Rule ID 8404 //
     /*  960760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  960763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  960768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960774 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960777 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960780 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  960783 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  960786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960790 */     // MIs[0] matrix_a_fmt
     /*  960790 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960793 */     // MIs[0] matrix_b_fmt
     /*  960793 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960796 */     // MIs[0] src2_modifiers
     /*  960796 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960799 */     // MIs[0] matrix_a_scale
     /*  960799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960802 */     // MIs[0] matrix_a_scale_fmt
     /*  960802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960805 */     // MIs[0] matrix_b_scale
     /*  960805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960808 */     // MIs[0] matrix_b_scale_fmt
     /*  960808 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960811 */     // MIs[0] matrix_a_reuse
     /*  960811 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960814 */     // MIs[0] matrix_b_reuse
     /*  960814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960817 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960824 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960829 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960831 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960833 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960839 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960844 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960846 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960848 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960850 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960852 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960854 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960856 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960858 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960860 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960862 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960870 */     GIR_RootConstrainSelectedInstOperands,
     /*  960871 */     // GIR_Coverage, 8404,
     /*  960871 */     GIR_EraseRootFromParent_Done,
     /*  960872 */   // Label 15238: @960872
     /*  960872 */   GIM_Try, /*On fail goto*//*Label 15239*/ GIMT_Encode4(960989), // Rule ID 8405 //
     /*  960877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  960880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  960885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  960888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  960891 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  960894 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  960897 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  960900 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  960903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  960907 */     // MIs[0] matrix_a_fmt
     /*  960907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  960910 */     // MIs[0] matrix_b_fmt
     /*  960910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  960913 */     // MIs[0] src2_modifiers
     /*  960913 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  960916 */     // MIs[0] matrix_a_scale
     /*  960916 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  960919 */     // MIs[0] matrix_a_scale_fmt
     /*  960919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  960922 */     // MIs[0] matrix_b_scale
     /*  960922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  960925 */     // MIs[0] matrix_b_scale_fmt
     /*  960925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  960928 */     // MIs[0] matrix_a_reuse
     /*  960928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  960931 */     // MIs[0] matrix_b_reuse
     /*  960931 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  960934 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  960941 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  960941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  960944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  960946 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  960948 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  960950 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  960956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  960961 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  960963 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  960965 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  960967 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  960969 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  960971 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  960973 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  960975 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  960977 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  960979 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  960981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  960987 */     GIR_RootConstrainSelectedInstOperands,
     /*  960988 */     // GIR_Coverage, 8405,
     /*  960988 */     GIR_EraseRootFromParent_Done,
     /*  960989 */   // Label 15239: @960989
     /*  960989 */   GIM_Try, /*On fail goto*//*Label 15240*/ GIMT_Encode4(961106), // Rule ID 8406 //
     /*  960994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  960997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  961002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961005 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961008 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  961011 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961014 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  961017 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  961020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961024 */     // MIs[0] matrix_a_fmt
     /*  961024 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961027 */     // MIs[0] matrix_b_fmt
     /*  961027 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961030 */     // MIs[0] src2_modifiers
     /*  961030 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961033 */     // MIs[0] matrix_a_scale
     /*  961033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961036 */     // MIs[0] matrix_a_scale_fmt
     /*  961036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961039 */     // MIs[0] matrix_b_scale
     /*  961039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961042 */     // MIs[0] matrix_b_scale_fmt
     /*  961042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961045 */     // MIs[0] matrix_a_reuse
     /*  961045 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961048 */     // MIs[0] matrix_b_reuse
     /*  961048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961051 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961058 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  961061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961063 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961065 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961067 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961073 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961078 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961080 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961082 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961084 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961086 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961088 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961090 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961092 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961094 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961096 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961104 */     GIR_RootConstrainSelectedInstOperands,
     /*  961105 */     // GIR_Coverage, 8406,
     /*  961105 */     GIR_EraseRootFromParent_Done,
     /*  961106 */   // Label 15240: @961106
     /*  961106 */   GIM_Try, /*On fail goto*//*Label 15241*/ GIMT_Encode4(961223), // Rule ID 8407 //
     /*  961111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  961114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  961119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961125 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  961128 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961131 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  961134 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  961137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961141 */     // MIs[0] matrix_a_fmt
     /*  961141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961144 */     // MIs[0] matrix_b_fmt
     /*  961144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961147 */     // MIs[0] src2_modifiers
     /*  961147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961150 */     // MIs[0] matrix_a_scale
     /*  961150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961153 */     // MIs[0] matrix_a_scale_fmt
     /*  961153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961156 */     // MIs[0] matrix_b_scale
     /*  961156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961159 */     // MIs[0] matrix_b_scale_fmt
     /*  961159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961162 */     // MIs[0] matrix_a_reuse
     /*  961162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961165 */     // MIs[0] matrix_b_reuse
     /*  961165 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961175 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr),
     /*  961178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961180 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961182 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961184 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961195 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961197 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961199 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961201 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961203 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961205 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961207 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961209 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961211 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961213 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961215 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961221 */     GIR_RootConstrainSelectedInstOperands,
     /*  961222 */     // GIR_Coverage, 8407,
     /*  961222 */     GIR_EraseRootFromParent_Done,
     /*  961223 */   // Label 15241: @961223
     /*  961223 */   GIM_Try, /*On fail goto*//*Label 15242*/ GIMT_Encode4(961340), // Rule ID 8423 //
     /*  961228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  961231 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  961236 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961239 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961242 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961245 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961248 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  961251 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  961254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961258 */     // MIs[0] matrix_a_fmt
     /*  961258 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961261 */     // MIs[0] matrix_b_fmt
     /*  961261 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961264 */     // MIs[0] src2_modifiers
     /*  961264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961267 */     // MIs[0] matrix_a_scale
     /*  961267 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961270 */     // MIs[0] matrix_a_scale_fmt
     /*  961270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961273 */     // MIs[0] matrix_b_scale
     /*  961273 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961276 */     // MIs[0] matrix_b_scale_fmt
     /*  961276 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961279 */     // MIs[0] matrix_a_reuse
     /*  961279 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961282 */     // MIs[0] matrix_b_reuse
     /*  961282 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961285 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961292 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961297 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961299 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961301 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961312 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961314 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961316 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961318 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961320 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961322 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961324 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961326 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961328 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961330 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961338 */     GIR_RootConstrainSelectedInstOperands,
     /*  961339 */     // GIR_Coverage, 8423,
     /*  961339 */     GIR_EraseRootFromParent_Done,
     /*  961340 */   // Label 15242: @961340
     /*  961340 */   GIM_Try, /*On fail goto*//*Label 15243*/ GIMT_Encode4(961457), // Rule ID 8424 //
     /*  961345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  961348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  961353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961359 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961362 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961365 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  961368 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  961371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961375 */     // MIs[0] matrix_a_fmt
     /*  961375 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961378 */     // MIs[0] matrix_b_fmt
     /*  961378 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961381 */     // MIs[0] src2_modifiers
     /*  961381 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961384 */     // MIs[0] matrix_a_scale
     /*  961384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961387 */     // MIs[0] matrix_a_scale_fmt
     /*  961387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961390 */     // MIs[0] matrix_b_scale
     /*  961390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961393 */     // MIs[0] matrix_b_scale_fmt
     /*  961393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961396 */     // MIs[0] matrix_a_reuse
     /*  961396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961399 */     // MIs[0] matrix_b_reuse
     /*  961399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961402 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961409 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961414 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961416 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961418 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961429 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961431 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961433 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961435 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961437 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961439 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961441 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961443 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961445 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961447 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961449 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961455 */     GIR_RootConstrainSelectedInstOperands,
     /*  961456 */     // GIR_Coverage, 8424,
     /*  961456 */     GIR_EraseRootFromParent_Done,
     /*  961457 */   // Label 15243: @961457
     /*  961457 */   GIM_Try, /*On fail goto*//*Label 15244*/ GIMT_Encode4(961574), // Rule ID 8425 //
     /*  961462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  961465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  961470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961473 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961476 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961479 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961482 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  961485 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  961488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961492 */     // MIs[0] matrix_a_fmt
     /*  961492 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961495 */     // MIs[0] matrix_b_fmt
     /*  961495 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961498 */     // MIs[0] src2_modifiers
     /*  961498 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961501 */     // MIs[0] matrix_a_scale
     /*  961501 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961504 */     // MIs[0] matrix_a_scale_fmt
     /*  961504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961507 */     // MIs[0] matrix_b_scale
     /*  961507 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961510 */     // MIs[0] matrix_b_scale_fmt
     /*  961510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961513 */     // MIs[0] matrix_a_reuse
     /*  961513 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961516 */     // MIs[0] matrix_b_reuse
     /*  961516 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961519 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961526 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961533 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961535 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961546 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961548 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961550 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961552 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961554 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961556 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961558 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961560 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961562 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961564 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961569 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961572 */     GIR_RootConstrainSelectedInstOperands,
     /*  961573 */     // GIR_Coverage, 8425,
     /*  961573 */     GIR_EraseRootFromParent_Done,
     /*  961574 */   // Label 15244: @961574
     /*  961574 */   GIM_Try, /*On fail goto*//*Label 15245*/ GIMT_Encode4(961691), // Rule ID 8426 //
     /*  961579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  961582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  961587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961593 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961596 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961599 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  961602 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  961605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961609 */     // MIs[0] matrix_a_fmt
     /*  961609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961612 */     // MIs[0] matrix_b_fmt
     /*  961612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961615 */     // MIs[0] src2_modifiers
     /*  961615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961618 */     // MIs[0] matrix_a_scale
     /*  961618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961621 */     // MIs[0] matrix_a_scale_fmt
     /*  961621 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961624 */     // MIs[0] matrix_b_scale
     /*  961624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961627 */     // MIs[0] matrix_b_scale_fmt
     /*  961627 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961630 */     // MIs[0] matrix_a_reuse
     /*  961630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961633 */     // MIs[0] matrix_b_reuse
     /*  961633 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961643 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961648 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961650 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961652 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961663 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961665 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961667 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961669 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961671 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961673 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961675 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961677 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961679 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961681 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961686 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961689 */     GIR_RootConstrainSelectedInstOperands,
     /*  961690 */     // GIR_Coverage, 8426,
     /*  961690 */     GIR_EraseRootFromParent_Done,
     /*  961691 */   // Label 15245: @961691
     /*  961691 */   GIM_Try, /*On fail goto*//*Label 15246*/ GIMT_Encode4(961808), // Rule ID 8427 //
     /*  961696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  961699 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  961704 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961710 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961713 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961716 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  961719 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  961722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961726 */     // MIs[0] matrix_a_fmt
     /*  961726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961729 */     // MIs[0] matrix_b_fmt
     /*  961729 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961732 */     // MIs[0] src2_modifiers
     /*  961732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961735 */     // MIs[0] matrix_a_scale
     /*  961735 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961738 */     // MIs[0] matrix_a_scale_fmt
     /*  961738 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961741 */     // MIs[0] matrix_b_scale
     /*  961741 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961744 */     // MIs[0] matrix_b_scale_fmt
     /*  961744 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961747 */     // MIs[0] matrix_a_reuse
     /*  961747 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961750 */     // MIs[0] matrix_b_reuse
     /*  961750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961760 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961765 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961767 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961769 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961780 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961782 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961784 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961786 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961788 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961790 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961792 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961794 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961796 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961798 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961800 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961803 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961806 */     GIR_RootConstrainSelectedInstOperands,
     /*  961807 */     // GIR_Coverage, 8427,
     /*  961807 */     GIR_EraseRootFromParent_Done,
     /*  961808 */   // Label 15246: @961808
     /*  961808 */   GIM_Try, /*On fail goto*//*Label 15247*/ GIMT_Encode4(961925), // Rule ID 8433 //
     /*  961813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  961816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  961821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961827 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961830 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961833 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  961836 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  961839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961843 */     // MIs[0] matrix_a_fmt
     /*  961843 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961846 */     // MIs[0] matrix_b_fmt
     /*  961846 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961849 */     // MIs[0] src2_modifiers
     /*  961849 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961852 */     // MIs[0] matrix_a_scale
     /*  961852 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961855 */     // MIs[0] matrix_a_scale_fmt
     /*  961855 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961858 */     // MIs[0] matrix_b_scale
     /*  961858 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961861 */     // MIs[0] matrix_b_scale_fmt
     /*  961861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961864 */     // MIs[0] matrix_a_reuse
     /*  961864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961867 */     // MIs[0] matrix_b_reuse
     /*  961867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961877 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961882 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  961884 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  961886 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  961892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  961897 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  961899 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  961901 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  961903 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  961905 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  961907 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  961909 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  961911 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  961913 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  961915 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  961917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  961923 */     GIR_RootConstrainSelectedInstOperands,
     /*  961924 */     // GIR_Coverage, 8433,
     /*  961924 */     GIR_EraseRootFromParent_Done,
     /*  961925 */   // Label 15247: @961925
     /*  961925 */   GIM_Try, /*On fail goto*//*Label 15248*/ GIMT_Encode4(962042), // Rule ID 8434 //
     /*  961930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  961933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  961938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  961941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  961944 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  961947 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  961950 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  961953 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  961956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  961960 */     // MIs[0] matrix_a_fmt
     /*  961960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  961963 */     // MIs[0] matrix_b_fmt
     /*  961963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  961966 */     // MIs[0] src2_modifiers
     /*  961966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  961969 */     // MIs[0] matrix_a_scale
     /*  961969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  961972 */     // MIs[0] matrix_a_scale_fmt
     /*  961972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  961975 */     // MIs[0] matrix_b_scale
     /*  961975 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  961978 */     // MIs[0] matrix_b_scale_fmt
     /*  961978 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  961981 */     // MIs[0] matrix_a_reuse
     /*  961981 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  961984 */     // MIs[0] matrix_b_reuse
     /*  961984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  961987 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  961994 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  961994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  961997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  961999 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962001 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962003 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962014 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962016 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962018 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962020 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962022 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962024 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962026 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962028 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962030 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962032 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962040 */     GIR_RootConstrainSelectedInstOperands,
     /*  962041 */     // GIR_Coverage, 8434,
     /*  962041 */     GIR_EraseRootFromParent_Done,
     /*  962042 */   // Label 15248: @962042
     /*  962042 */   GIM_Try, /*On fail goto*//*Label 15249*/ GIMT_Encode4(962159), // Rule ID 8435 //
     /*  962047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  962050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  962055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962058 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962061 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  962064 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962067 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  962070 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  962073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962077 */     // MIs[0] matrix_a_fmt
     /*  962077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962080 */     // MIs[0] matrix_b_fmt
     /*  962080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962083 */     // MIs[0] src2_modifiers
     /*  962083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962086 */     // MIs[0] matrix_a_scale
     /*  962086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962089 */     // MIs[0] matrix_a_scale_fmt
     /*  962089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962092 */     // MIs[0] matrix_b_scale
     /*  962092 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962095 */     // MIs[0] matrix_b_scale_fmt
     /*  962095 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962098 */     // MIs[0] matrix_a_reuse
     /*  962098 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962101 */     // MIs[0] matrix_b_reuse
     /*  962101 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962111 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  962114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962116 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962118 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962120 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962131 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962133 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962135 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962137 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962139 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962141 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962143 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962145 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962147 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962149 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962151 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962157 */     GIR_RootConstrainSelectedInstOperands,
     /*  962158 */     // GIR_Coverage, 8435,
     /*  962158 */     GIR_EraseRootFromParent_Done,
     /*  962159 */   // Label 15249: @962159
     /*  962159 */   GIM_Try, /*On fail goto*//*Label 15250*/ GIMT_Encode4(962276), // Rule ID 8436 //
     /*  962164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  962167 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  962172 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962178 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  962181 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962184 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  962187 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  962190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962194 */     // MIs[0] matrix_a_fmt
     /*  962194 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962197 */     // MIs[0] matrix_b_fmt
     /*  962197 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962200 */     // MIs[0] src2_modifiers
     /*  962200 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962203 */     // MIs[0] matrix_a_scale
     /*  962203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962206 */     // MIs[0] matrix_a_scale_fmt
     /*  962206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962209 */     // MIs[0] matrix_b_scale
     /*  962209 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962212 */     // MIs[0] matrix_b_scale_fmt
     /*  962212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962215 */     // MIs[0] matrix_a_reuse
     /*  962215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962218 */     // MIs[0] matrix_b_reuse
     /*  962218 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962221 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962228 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  962231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962233 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962235 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962237 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962248 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962250 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962252 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962254 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962256 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962258 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962260 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962262 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962264 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962266 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962274 */     GIR_RootConstrainSelectedInstOperands,
     /*  962275 */     // GIR_Coverage, 8436,
     /*  962275 */     GIR_EraseRootFromParent_Done,
     /*  962276 */   // Label 15250: @962276
     /*  962276 */   GIM_Try, /*On fail goto*//*Label 15251*/ GIMT_Encode4(962393), // Rule ID 8437 //
     /*  962281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  962284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  962289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962295 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  962298 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962301 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  962304 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  962307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962311 */     // MIs[0] matrix_a_fmt
     /*  962311 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962314 */     // MIs[0] matrix_b_fmt
     /*  962314 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962317 */     // MIs[0] src2_modifiers
     /*  962317 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962320 */     // MIs[0] matrix_a_scale
     /*  962320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962323 */     // MIs[0] matrix_a_scale_fmt
     /*  962323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962326 */     // MIs[0] matrix_b_scale
     /*  962326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962329 */     // MIs[0] matrix_b_scale_fmt
     /*  962329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962332 */     // MIs[0] matrix_a_reuse
     /*  962332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962335 */     // MIs[0] matrix_b_reuse
     /*  962335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962345 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr),
     /*  962348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962350 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962352 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962354 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962360 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962365 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962367 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962369 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962371 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962373 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962375 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962377 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962379 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962381 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962383 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962391 */     GIR_RootConstrainSelectedInstOperands,
     /*  962392 */     // GIR_Coverage, 8437,
     /*  962392 */     GIR_EraseRootFromParent_Done,
     /*  962393 */   // Label 15251: @962393
     /*  962393 */   GIM_Try, /*On fail goto*//*Label 15252*/ GIMT_Encode4(962510), // Rule ID 8453 //
     /*  962398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  962401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  962406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962409 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962412 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  962415 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962418 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  962421 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  962424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962428 */     // MIs[0] matrix_a_fmt
     /*  962428 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962431 */     // MIs[0] matrix_b_fmt
     /*  962431 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962434 */     // MIs[0] src2_modifiers
     /*  962434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962437 */     // MIs[0] matrix_a_scale
     /*  962437 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962440 */     // MIs[0] matrix_a_scale_fmt
     /*  962440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962443 */     // MIs[0] matrix_b_scale
     /*  962443 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962446 */     // MIs[0] matrix_b_scale_fmt
     /*  962446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962449 */     // MIs[0] matrix_a_reuse
     /*  962449 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962452 */     // MIs[0] matrix_b_reuse
     /*  962452 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962462 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  962465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962467 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962469 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962471 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962482 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962484 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962486 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962488 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962490 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962492 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962494 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962496 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962498 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962500 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962502 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962508 */     GIR_RootConstrainSelectedInstOperands,
     /*  962509 */     // GIR_Coverage, 8453,
     /*  962509 */     GIR_EraseRootFromParent_Done,
     /*  962510 */   // Label 15252: @962510
     /*  962510 */   GIM_Try, /*On fail goto*//*Label 15253*/ GIMT_Encode4(962627), // Rule ID 8454 //
     /*  962515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  962518 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  962523 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962529 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  962532 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962535 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  962538 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  962541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962545 */     // MIs[0] matrix_a_fmt
     /*  962545 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962548 */     // MIs[0] matrix_b_fmt
     /*  962548 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962551 */     // MIs[0] src2_modifiers
     /*  962551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962554 */     // MIs[0] matrix_a_scale
     /*  962554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962557 */     // MIs[0] matrix_a_scale_fmt
     /*  962557 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962560 */     // MIs[0] matrix_b_scale
     /*  962560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962563 */     // MIs[0] matrix_b_scale_fmt
     /*  962563 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962566 */     // MIs[0] matrix_a_reuse
     /*  962566 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962569 */     // MIs[0] matrix_b_reuse
     /*  962569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962579 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  962582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962584 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962586 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962588 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962599 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962601 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962603 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962605 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962607 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962609 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962611 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962613 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962615 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962617 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962619 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962622 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962625 */     GIR_RootConstrainSelectedInstOperands,
     /*  962626 */     // GIR_Coverage, 8454,
     /*  962626 */     GIR_EraseRootFromParent_Done,
     /*  962627 */   // Label 15253: @962627
     /*  962627 */   GIM_Try, /*On fail goto*//*Label 15254*/ GIMT_Encode4(962744), // Rule ID 8455 //
     /*  962632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  962635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  962640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962646 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  962649 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962652 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  962655 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  962658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962662 */     // MIs[0] matrix_a_fmt
     /*  962662 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962665 */     // MIs[0] matrix_b_fmt
     /*  962665 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962668 */     // MIs[0] src2_modifiers
     /*  962668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962671 */     // MIs[0] matrix_a_scale
     /*  962671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962674 */     // MIs[0] matrix_a_scale_fmt
     /*  962674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962677 */     // MIs[0] matrix_b_scale
     /*  962677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962680 */     // MIs[0] matrix_b_scale_fmt
     /*  962680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962683 */     // MIs[0] matrix_a_reuse
     /*  962683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962686 */     // MIs[0] matrix_b_reuse
     /*  962686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962689 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962696 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  962699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962701 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962703 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962705 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962716 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962718 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962720 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962722 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962724 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962726 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962728 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962730 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962732 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962734 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962742 */     GIR_RootConstrainSelectedInstOperands,
     /*  962743 */     // GIR_Coverage, 8455,
     /*  962743 */     GIR_EraseRootFromParent_Done,
     /*  962744 */   // Label 15254: @962744
     /*  962744 */   GIM_Try, /*On fail goto*//*Label 15255*/ GIMT_Encode4(962861), // Rule ID 8456 //
     /*  962749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  962752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  962757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962760 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962763 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  962766 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962769 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  962772 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  962775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962779 */     // MIs[0] matrix_a_fmt
     /*  962779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962782 */     // MIs[0] matrix_b_fmt
     /*  962782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962785 */     // MIs[0] src2_modifiers
     /*  962785 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962788 */     // MIs[0] matrix_a_scale
     /*  962788 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962791 */     // MIs[0] matrix_a_scale_fmt
     /*  962791 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962794 */     // MIs[0] matrix_b_scale
     /*  962794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962797 */     // MIs[0] matrix_b_scale_fmt
     /*  962797 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962800 */     // MIs[0] matrix_a_reuse
     /*  962800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962803 */     // MIs[0] matrix_b_reuse
     /*  962803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962813 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  962816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962818 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962820 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962822 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962833 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962835 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962837 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962839 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962841 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962843 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962845 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962847 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962849 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962851 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962859 */     GIR_RootConstrainSelectedInstOperands,
     /*  962860 */     // GIR_Coverage, 8456,
     /*  962860 */     GIR_EraseRootFromParent_Done,
     /*  962861 */   // Label 15255: @962861
     /*  962861 */   GIM_Try, /*On fail goto*//*Label 15256*/ GIMT_Encode4(962978), // Rule ID 8457 //
     /*  962866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  962869 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  962874 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962877 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962880 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  962883 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  962886 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  962889 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  962892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  962896 */     // MIs[0] matrix_a_fmt
     /*  962896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  962899 */     // MIs[0] matrix_b_fmt
     /*  962899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  962902 */     // MIs[0] src2_modifiers
     /*  962902 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  962905 */     // MIs[0] matrix_a_scale
     /*  962905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  962908 */     // MIs[0] matrix_a_scale_fmt
     /*  962908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  962911 */     // MIs[0] matrix_b_scale
     /*  962911 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  962914 */     // MIs[0] matrix_b_scale_fmt
     /*  962914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  962917 */     // MIs[0] matrix_a_reuse
     /*  962917 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  962920 */     // MIs[0] matrix_b_reuse
     /*  962920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  962923 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  962930 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  962930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  962933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  962935 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  962937 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  962939 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  962945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  962950 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  962952 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  962954 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  962956 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  962958 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  962960 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  962962 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  962964 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  962966 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  962968 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  962970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  962976 */     GIR_RootConstrainSelectedInstOperands,
     /*  962977 */     // GIR_Coverage, 8457,
     /*  962977 */     GIR_EraseRootFromParent_Done,
     /*  962978 */   // Label 15256: @962978
     /*  962978 */   GIM_Try, /*On fail goto*//*Label 15257*/ GIMT_Encode4(963095), // Rule ID 8463 //
     /*  962983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  962986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  962991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  962994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  962997 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  963000 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963003 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  963006 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  963009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963013 */     // MIs[0] matrix_a_fmt
     /*  963013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963016 */     // MIs[0] matrix_b_fmt
     /*  963016 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963019 */     // MIs[0] src2_modifiers
     /*  963019 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963022 */     // MIs[0] matrix_a_scale
     /*  963022 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963025 */     // MIs[0] matrix_a_scale_fmt
     /*  963025 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963028 */     // MIs[0] matrix_b_scale
     /*  963028 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963031 */     // MIs[0] matrix_b_scale_fmt
     /*  963031 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963034 */     // MIs[0] matrix_a_reuse
     /*  963034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963037 */     // MIs[0] matrix_b_reuse
     /*  963037 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963040 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963047 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  963050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963052 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963054 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963056 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963062 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963067 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963069 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963071 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963073 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963075 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963077 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963079 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963081 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963083 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963085 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963093 */     GIR_RootConstrainSelectedInstOperands,
     /*  963094 */     // GIR_Coverage, 8463,
     /*  963094 */     GIR_EraseRootFromParent_Done,
     /*  963095 */   // Label 15257: @963095
     /*  963095 */   GIM_Try, /*On fail goto*//*Label 15258*/ GIMT_Encode4(963212), // Rule ID 8464 //
     /*  963100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  963103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  963108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  963114 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  963117 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963120 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  963123 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  963126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963130 */     // MIs[0] matrix_a_fmt
     /*  963130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963133 */     // MIs[0] matrix_b_fmt
     /*  963133 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963136 */     // MIs[0] src2_modifiers
     /*  963136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963139 */     // MIs[0] matrix_a_scale
     /*  963139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963142 */     // MIs[0] matrix_a_scale_fmt
     /*  963142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963145 */     // MIs[0] matrix_b_scale
     /*  963145 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963148 */     // MIs[0] matrix_b_scale_fmt
     /*  963148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963151 */     // MIs[0] matrix_a_reuse
     /*  963151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963154 */     // MIs[0] matrix_b_reuse
     /*  963154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963164 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  963167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963169 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963171 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963173 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963184 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963186 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963188 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963190 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963192 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963194 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963196 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963198 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963200 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963202 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963207 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963210 */     GIR_RootConstrainSelectedInstOperands,
     /*  963211 */     // GIR_Coverage, 8464,
     /*  963211 */     GIR_EraseRootFromParent_Done,
     /*  963212 */   // Label 15258: @963212
     /*  963212 */   GIM_Try, /*On fail goto*//*Label 15259*/ GIMT_Encode4(963329), // Rule ID 8465 //
     /*  963217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  963220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  963225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963228 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  963231 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  963234 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963237 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  963240 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  963243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963247 */     // MIs[0] matrix_a_fmt
     /*  963247 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963250 */     // MIs[0] matrix_b_fmt
     /*  963250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963253 */     // MIs[0] src2_modifiers
     /*  963253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963256 */     // MIs[0] matrix_a_scale
     /*  963256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963259 */     // MIs[0] matrix_a_scale_fmt
     /*  963259 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963262 */     // MIs[0] matrix_b_scale
     /*  963262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963265 */     // MIs[0] matrix_b_scale_fmt
     /*  963265 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963268 */     // MIs[0] matrix_a_reuse
     /*  963268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963271 */     // MIs[0] matrix_b_reuse
     /*  963271 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963274 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963281 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  963284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963286 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963288 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963290 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963301 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963303 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963305 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963307 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963309 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963311 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963313 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963315 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963317 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963319 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963321 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963324 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963327 */     GIR_RootConstrainSelectedInstOperands,
     /*  963328 */     // GIR_Coverage, 8465,
     /*  963328 */     GIR_EraseRootFromParent_Done,
     /*  963329 */   // Label 15259: @963329
     /*  963329 */   GIM_Try, /*On fail goto*//*Label 15260*/ GIMT_Encode4(963446), // Rule ID 8466 //
     /*  963334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  963337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  963342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  963348 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  963351 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963354 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  963357 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  963360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963364 */     // MIs[0] matrix_a_fmt
     /*  963364 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963367 */     // MIs[0] matrix_b_fmt
     /*  963367 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963370 */     // MIs[0] src2_modifiers
     /*  963370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963373 */     // MIs[0] matrix_a_scale
     /*  963373 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963376 */     // MIs[0] matrix_a_scale_fmt
     /*  963376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963379 */     // MIs[0] matrix_b_scale
     /*  963379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963382 */     // MIs[0] matrix_b_scale_fmt
     /*  963382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963385 */     // MIs[0] matrix_a_reuse
     /*  963385 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963388 */     // MIs[0] matrix_b_reuse
     /*  963388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963391 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963398 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  963401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963403 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963405 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963407 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963418 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963420 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963422 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963424 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963426 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963428 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963430 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963432 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963434 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963436 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963441 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963444 */     GIR_RootConstrainSelectedInstOperands,
     /*  963445 */     // GIR_Coverage, 8466,
     /*  963445 */     GIR_EraseRootFromParent_Done,
     /*  963446 */   // Label 15260: @963446
     /*  963446 */   GIM_Try, /*On fail goto*//*Label 15261*/ GIMT_Encode4(963563), // Rule ID 8467 //
     /*  963451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  963454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  963459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963462 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  963465 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  963468 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963471 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  963474 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  963477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963481 */     // MIs[0] matrix_a_fmt
     /*  963481 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963484 */     // MIs[0] matrix_b_fmt
     /*  963484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963487 */     // MIs[0] src2_modifiers
     /*  963487 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963490 */     // MIs[0] matrix_a_scale
     /*  963490 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963493 */     // MIs[0] matrix_a_scale_fmt
     /*  963493 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963496 */     // MIs[0] matrix_b_scale
     /*  963496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963499 */     // MIs[0] matrix_b_scale_fmt
     /*  963499 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963502 */     // MIs[0] matrix_a_reuse
     /*  963502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963505 */     // MIs[0] matrix_b_reuse
     /*  963505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963515 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr),
     /*  963518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963520 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963522 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963524 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963535 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963537 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963539 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963541 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963543 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963545 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963547 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963549 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963551 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963553 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963561 */     GIR_RootConstrainSelectedInstOperands,
     /*  963562 */     // GIR_Coverage, 8467,
     /*  963562 */     GIR_EraseRootFromParent_Done,
     /*  963563 */   // Label 15261: @963563
     /*  963563 */   GIM_Try, /*On fail goto*//*Label 15262*/ GIMT_Encode4(963680), // Rule ID 8483 //
     /*  963568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  963571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  963576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  963582 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  963585 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963588 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  963591 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  963594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963598 */     // MIs[0] matrix_a_fmt
     /*  963598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963601 */     // MIs[0] matrix_b_fmt
     /*  963601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963604 */     // MIs[0] src2_modifiers
     /*  963604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963607 */     // MIs[0] matrix_a_scale
     /*  963607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963610 */     // MIs[0] matrix_a_scale_fmt
     /*  963610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963613 */     // MIs[0] matrix_b_scale
     /*  963613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963616 */     // MIs[0] matrix_b_scale_fmt
     /*  963616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963619 */     // MIs[0] matrix_a_reuse
     /*  963619 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963622 */     // MIs[0] matrix_b_reuse
     /*  963622 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963632 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  963635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963637 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963639 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963641 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963652 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963654 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963656 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963658 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963660 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963662 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963664 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963666 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963668 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963670 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963675 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963678 */     GIR_RootConstrainSelectedInstOperands,
     /*  963679 */     // GIR_Coverage, 8483,
     /*  963679 */     GIR_EraseRootFromParent_Done,
     /*  963680 */   // Label 15262: @963680
     /*  963680 */   GIM_Try, /*On fail goto*//*Label 15263*/ GIMT_Encode4(963797), // Rule ID 8484 //
     /*  963685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  963688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  963693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  963699 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  963702 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963705 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  963708 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  963711 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963715 */     // MIs[0] matrix_a_fmt
     /*  963715 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963718 */     // MIs[0] matrix_b_fmt
     /*  963718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963721 */     // MIs[0] src2_modifiers
     /*  963721 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963724 */     // MIs[0] matrix_a_scale
     /*  963724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963727 */     // MIs[0] matrix_a_scale_fmt
     /*  963727 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963730 */     // MIs[0] matrix_b_scale
     /*  963730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963733 */     // MIs[0] matrix_b_scale_fmt
     /*  963733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963736 */     // MIs[0] matrix_a_reuse
     /*  963736 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963739 */     // MIs[0] matrix_b_reuse
     /*  963739 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963742 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963749 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  963752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963754 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963756 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963758 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963769 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963771 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963773 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963775 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963777 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963779 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963781 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963783 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963785 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963787 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963789 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963795 */     GIR_RootConstrainSelectedInstOperands,
     /*  963796 */     // GIR_Coverage, 8484,
     /*  963796 */     GIR_EraseRootFromParent_Done,
     /*  963797 */   // Label 15263: @963797
     /*  963797 */   GIM_Try, /*On fail goto*//*Label 15264*/ GIMT_Encode4(963914), // Rule ID 8485 //
     /*  963802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  963805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  963810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963813 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  963816 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  963819 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963822 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  963825 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  963828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963832 */     // MIs[0] matrix_a_fmt
     /*  963832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963835 */     // MIs[0] matrix_b_fmt
     /*  963835 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963838 */     // MIs[0] src2_modifiers
     /*  963838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963841 */     // MIs[0] matrix_a_scale
     /*  963841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963844 */     // MIs[0] matrix_a_scale_fmt
     /*  963844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963847 */     // MIs[0] matrix_b_scale
     /*  963847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963850 */     // MIs[0] matrix_b_scale_fmt
     /*  963850 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963853 */     // MIs[0] matrix_a_reuse
     /*  963853 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963856 */     // MIs[0] matrix_b_reuse
     /*  963856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963866 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  963869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963871 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963873 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963875 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  963886 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  963888 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  963890 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  963892 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  963894 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  963896 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  963898 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  963900 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  963902 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  963904 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  963906 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  963912 */     GIR_RootConstrainSelectedInstOperands,
     /*  963913 */     // GIR_Coverage, 8485,
     /*  963913 */     GIR_EraseRootFromParent_Done,
     /*  963914 */   // Label 15264: @963914
     /*  963914 */   GIM_Try, /*On fail goto*//*Label 15265*/ GIMT_Encode4(964031), // Rule ID 8486 //
     /*  963919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  963922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  963927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  963930 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  963933 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  963936 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  963939 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  963942 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  963945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  963949 */     // MIs[0] matrix_a_fmt
     /*  963949 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  963952 */     // MIs[0] matrix_b_fmt
     /*  963952 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  963955 */     // MIs[0] src2_modifiers
     /*  963955 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  963958 */     // MIs[0] matrix_a_scale
     /*  963958 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  963961 */     // MIs[0] matrix_a_scale_fmt
     /*  963961 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  963964 */     // MIs[0] matrix_b_scale
     /*  963964 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  963967 */     // MIs[0] matrix_b_scale_fmt
     /*  963967 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  963970 */     // MIs[0] matrix_a_reuse
     /*  963970 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  963973 */     // MIs[0] matrix_b_reuse
     /*  963973 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  963976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  963983 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  963983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  963986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  963988 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  963990 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  963992 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  963998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964003 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964005 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964007 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964009 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964011 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964013 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964015 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964017 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964019 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964021 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964026 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964029 */     GIR_RootConstrainSelectedInstOperands,
     /*  964030 */     // GIR_Coverage, 8486,
     /*  964030 */     GIR_EraseRootFromParent_Done,
     /*  964031 */   // Label 15265: @964031
     /*  964031 */   GIM_Try, /*On fail goto*//*Label 15266*/ GIMT_Encode4(964148), // Rule ID 8487 //
     /*  964036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  964039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  964044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964050 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  964053 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964056 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  964059 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  964062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964066 */     // MIs[0] matrix_a_fmt
     /*  964066 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964069 */     // MIs[0] matrix_b_fmt
     /*  964069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964072 */     // MIs[0] src2_modifiers
     /*  964072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964075 */     // MIs[0] matrix_a_scale
     /*  964075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964078 */     // MIs[0] matrix_a_scale_fmt
     /*  964078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964081 */     // MIs[0] matrix_b_scale
     /*  964081 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964084 */     // MIs[0] matrix_b_scale_fmt
     /*  964084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964087 */     // MIs[0] matrix_a_reuse
     /*  964087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964090 */     // MIs[0] matrix_b_reuse
     /*  964090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964093 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964100 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  964103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964105 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964107 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964109 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964120 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964122 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964124 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964126 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964128 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964130 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964132 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964134 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964136 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964138 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964146 */     GIR_RootConstrainSelectedInstOperands,
     /*  964147 */     // GIR_Coverage, 8487,
     /*  964147 */     GIR_EraseRootFromParent_Done,
     /*  964148 */   // Label 15266: @964148
     /*  964148 */   GIM_Try, /*On fail goto*//*Label 15267*/ GIMT_Encode4(964265), // Rule ID 8493 //
     /*  964153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  964156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  964161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964167 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  964170 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964173 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  964176 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  964179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964183 */     // MIs[0] matrix_a_fmt
     /*  964183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964186 */     // MIs[0] matrix_b_fmt
     /*  964186 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964189 */     // MIs[0] src2_modifiers
     /*  964189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964192 */     // MIs[0] matrix_a_scale
     /*  964192 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964195 */     // MIs[0] matrix_a_scale_fmt
     /*  964195 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964198 */     // MIs[0] matrix_b_scale
     /*  964198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964201 */     // MIs[0] matrix_b_scale_fmt
     /*  964201 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964204 */     // MIs[0] matrix_a_reuse
     /*  964204 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964207 */     // MIs[0] matrix_b_reuse
     /*  964207 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964217 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  964220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964222 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964224 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964226 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964237 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964239 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964241 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964243 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964245 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964247 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964249 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964251 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964253 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964255 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964263 */     GIR_RootConstrainSelectedInstOperands,
     /*  964264 */     // GIR_Coverage, 8493,
     /*  964264 */     GIR_EraseRootFromParent_Done,
     /*  964265 */   // Label 15267: @964265
     /*  964265 */   GIM_Try, /*On fail goto*//*Label 15268*/ GIMT_Encode4(964382), // Rule ID 8494 //
     /*  964270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  964273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  964278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964281 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964284 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  964287 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964290 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  964293 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  964296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964300 */     // MIs[0] matrix_a_fmt
     /*  964300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964303 */     // MIs[0] matrix_b_fmt
     /*  964303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964306 */     // MIs[0] src2_modifiers
     /*  964306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964309 */     // MIs[0] matrix_a_scale
     /*  964309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964312 */     // MIs[0] matrix_a_scale_fmt
     /*  964312 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964315 */     // MIs[0] matrix_b_scale
     /*  964315 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964318 */     // MIs[0] matrix_b_scale_fmt
     /*  964318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964321 */     // MIs[0] matrix_a_reuse
     /*  964321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964324 */     // MIs[0] matrix_b_reuse
     /*  964324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964334 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  964337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964339 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964341 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964343 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964354 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964356 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964358 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964360 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964362 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964364 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964366 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964368 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964370 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964372 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964380 */     GIR_RootConstrainSelectedInstOperands,
     /*  964381 */     // GIR_Coverage, 8494,
     /*  964381 */     GIR_EraseRootFromParent_Done,
     /*  964382 */   // Label 15268: @964382
     /*  964382 */   GIM_Try, /*On fail goto*//*Label 15269*/ GIMT_Encode4(964499), // Rule ID 8495 //
     /*  964387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  964390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  964395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964401 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  964404 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964407 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  964410 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  964413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964417 */     // MIs[0] matrix_a_fmt
     /*  964417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964420 */     // MIs[0] matrix_b_fmt
     /*  964420 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964423 */     // MIs[0] src2_modifiers
     /*  964423 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964426 */     // MIs[0] matrix_a_scale
     /*  964426 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964429 */     // MIs[0] matrix_a_scale_fmt
     /*  964429 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964432 */     // MIs[0] matrix_b_scale
     /*  964432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964435 */     // MIs[0] matrix_b_scale_fmt
     /*  964435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964438 */     // MIs[0] matrix_a_reuse
     /*  964438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964441 */     // MIs[0] matrix_b_reuse
     /*  964441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964444 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964451 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  964454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964456 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964458 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964460 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964471 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964473 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964475 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964477 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964479 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964481 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964483 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964485 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964487 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964489 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964491 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964497 */     GIR_RootConstrainSelectedInstOperands,
     /*  964498 */     // GIR_Coverage, 8495,
     /*  964498 */     GIR_EraseRootFromParent_Done,
     /*  964499 */   // Label 15269: @964499
     /*  964499 */   GIM_Try, /*On fail goto*//*Label 15270*/ GIMT_Encode4(964616), // Rule ID 8496 //
     /*  964504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  964507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  964512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964515 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964518 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  964521 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964524 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  964527 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  964530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964534 */     // MIs[0] matrix_a_fmt
     /*  964534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964537 */     // MIs[0] matrix_b_fmt
     /*  964537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964540 */     // MIs[0] src2_modifiers
     /*  964540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964543 */     // MIs[0] matrix_a_scale
     /*  964543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964546 */     // MIs[0] matrix_a_scale_fmt
     /*  964546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964549 */     // MIs[0] matrix_b_scale
     /*  964549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964552 */     // MIs[0] matrix_b_scale_fmt
     /*  964552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964555 */     // MIs[0] matrix_a_reuse
     /*  964555 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964558 */     // MIs[0] matrix_b_reuse
     /*  964558 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964561 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964568 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  964571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964573 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964575 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964577 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964588 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964590 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964592 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964594 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964596 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964598 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964600 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964602 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964604 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964606 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964611 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964614 */     GIR_RootConstrainSelectedInstOperands,
     /*  964615 */     // GIR_Coverage, 8496,
     /*  964615 */     GIR_EraseRootFromParent_Done,
     /*  964616 */   // Label 15270: @964616
     /*  964616 */   GIM_Try, /*On fail goto*//*Label 15271*/ GIMT_Encode4(964733), // Rule ID 8497 //
     /*  964621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  964624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  964629 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964635 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  964638 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964641 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  964644 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  964647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964651 */     // MIs[0] matrix_a_fmt
     /*  964651 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964654 */     // MIs[0] matrix_b_fmt
     /*  964654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964657 */     // MIs[0] src2_modifiers
     /*  964657 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964660 */     // MIs[0] matrix_a_scale
     /*  964660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964663 */     // MIs[0] matrix_a_scale_fmt
     /*  964663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964666 */     // MIs[0] matrix_b_scale
     /*  964666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964669 */     // MIs[0] matrix_b_scale_fmt
     /*  964669 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964672 */     // MIs[0] matrix_a_reuse
     /*  964672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964675 */     // MIs[0] matrix_b_reuse
     /*  964675 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964678 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964685 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr),
     /*  964688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964690 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964692 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964694 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964705 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964707 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964709 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964711 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964713 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964715 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964717 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964719 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964721 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964723 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964725 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964731 */     GIR_RootConstrainSelectedInstOperands,
     /*  964732 */     // GIR_Coverage, 8497,
     /*  964732 */     GIR_EraseRootFromParent_Done,
     /*  964733 */   // Label 15271: @964733
     /*  964733 */   GIM_Try, /*On fail goto*//*Label 15272*/ GIMT_Encode4(964850), // Rule ID 8513 //
     /*  964738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  964741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  964746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964752 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  964755 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964758 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  964761 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  964764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964768 */     // MIs[0] matrix_a_fmt
     /*  964768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964771 */     // MIs[0] matrix_b_fmt
     /*  964771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964774 */     // MIs[0] src2_modifiers
     /*  964774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964777 */     // MIs[0] matrix_a_scale
     /*  964777 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964780 */     // MIs[0] matrix_a_scale_fmt
     /*  964780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964783 */     // MIs[0] matrix_b_scale
     /*  964783 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964786 */     // MIs[0] matrix_b_scale_fmt
     /*  964786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964789 */     // MIs[0] matrix_a_reuse
     /*  964789 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964792 */     // MIs[0] matrix_b_reuse
     /*  964792 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964795 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964802 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  964805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964807 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964809 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964811 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964822 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964824 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964826 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964828 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964830 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964832 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964834 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964836 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964838 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964840 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964845 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964848 */     GIR_RootConstrainSelectedInstOperands,
     /*  964849 */     // GIR_Coverage, 8513,
     /*  964849 */     GIR_EraseRootFromParent_Done,
     /*  964850 */   // Label 15272: @964850
     /*  964850 */   GIM_Try, /*On fail goto*//*Label 15273*/ GIMT_Encode4(964967), // Rule ID 8514 //
     /*  964855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  964858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  964863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964869 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  964872 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964875 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  964878 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  964881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  964885 */     // MIs[0] matrix_a_fmt
     /*  964885 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  964888 */     // MIs[0] matrix_b_fmt
     /*  964888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  964891 */     // MIs[0] src2_modifiers
     /*  964891 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  964894 */     // MIs[0] matrix_a_scale
     /*  964894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  964897 */     // MIs[0] matrix_a_scale_fmt
     /*  964897 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  964900 */     // MIs[0] matrix_b_scale
     /*  964900 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  964903 */     // MIs[0] matrix_b_scale_fmt
     /*  964903 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  964906 */     // MIs[0] matrix_a_reuse
     /*  964906 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  964909 */     // MIs[0] matrix_b_reuse
     /*  964909 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  964912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  964919 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  964919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  964922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  964924 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  964926 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  964928 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  964934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  964939 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  964941 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  964943 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  964945 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  964947 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  964949 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  964951 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  964953 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  964955 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  964957 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  964959 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964962 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  964965 */     GIR_RootConstrainSelectedInstOperands,
     /*  964966 */     // GIR_Coverage, 8514,
     /*  964966 */     GIR_EraseRootFromParent_Done,
     /*  964967 */   // Label 15273: @964967
     /*  964967 */   GIM_Try, /*On fail goto*//*Label 15274*/ GIMT_Encode4(965084), // Rule ID 8515 //
     /*  964972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  964975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  964980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  964983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  964986 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  964989 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  964992 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  964995 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  964998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965002 */     // MIs[0] matrix_a_fmt
     /*  965002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965005 */     // MIs[0] matrix_b_fmt
     /*  965005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965008 */     // MIs[0] src2_modifiers
     /*  965008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965011 */     // MIs[0] matrix_a_scale
     /*  965011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965014 */     // MIs[0] matrix_a_scale_fmt
     /*  965014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965017 */     // MIs[0] matrix_b_scale
     /*  965017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965020 */     // MIs[0] matrix_b_scale_fmt
     /*  965020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965023 */     // MIs[0] matrix_a_reuse
     /*  965023 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965026 */     // MIs[0] matrix_b_reuse
     /*  965026 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965029 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965036 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965041 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965043 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965045 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965056 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965058 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965060 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965062 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965064 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965066 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965068 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965070 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965072 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965074 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965082 */     GIR_RootConstrainSelectedInstOperands,
     /*  965083 */     // GIR_Coverage, 8515,
     /*  965083 */     GIR_EraseRootFromParent_Done,
     /*  965084 */   // Label 15274: @965084
     /*  965084 */   GIM_Try, /*On fail goto*//*Label 15275*/ GIMT_Encode4(965201), // Rule ID 8516 //
     /*  965089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  965092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  965097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965103 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965106 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965109 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  965112 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  965115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965119 */     // MIs[0] matrix_a_fmt
     /*  965119 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965122 */     // MIs[0] matrix_b_fmt
     /*  965122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965125 */     // MIs[0] src2_modifiers
     /*  965125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965128 */     // MIs[0] matrix_a_scale
     /*  965128 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965131 */     // MIs[0] matrix_a_scale_fmt
     /*  965131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965134 */     // MIs[0] matrix_b_scale
     /*  965134 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965137 */     // MIs[0] matrix_b_scale_fmt
     /*  965137 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965140 */     // MIs[0] matrix_a_reuse
     /*  965140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965143 */     // MIs[0] matrix_b_reuse
     /*  965143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965146 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965153 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965158 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965160 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965162 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965173 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965175 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965177 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965179 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965181 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965183 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965185 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965187 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965189 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965191 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965196 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965199 */     GIR_RootConstrainSelectedInstOperands,
     /*  965200 */     // GIR_Coverage, 8516,
     /*  965200 */     GIR_EraseRootFromParent_Done,
     /*  965201 */   // Label 15275: @965201
     /*  965201 */   GIM_Try, /*On fail goto*//*Label 15276*/ GIMT_Encode4(965318), // Rule ID 8517 //
     /*  965206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  965209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  965214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965220 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965223 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965226 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  965229 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  965232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965236 */     // MIs[0] matrix_a_fmt
     /*  965236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965239 */     // MIs[0] matrix_b_fmt
     /*  965239 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965242 */     // MIs[0] src2_modifiers
     /*  965242 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965245 */     // MIs[0] matrix_a_scale
     /*  965245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965248 */     // MIs[0] matrix_a_scale_fmt
     /*  965248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965251 */     // MIs[0] matrix_b_scale
     /*  965251 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965254 */     // MIs[0] matrix_b_scale_fmt
     /*  965254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965257 */     // MIs[0] matrix_a_reuse
     /*  965257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965260 */     // MIs[0] matrix_b_reuse
     /*  965260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965270 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965275 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965277 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965279 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965290 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965292 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965294 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965296 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965298 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965300 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965302 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965304 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965306 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965308 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965316 */     GIR_RootConstrainSelectedInstOperands,
     /*  965317 */     // GIR_Coverage, 8517,
     /*  965317 */     GIR_EraseRootFromParent_Done,
     /*  965318 */   // Label 15276: @965318
     /*  965318 */   GIM_Try, /*On fail goto*//*Label 15277*/ GIMT_Encode4(965435), // Rule ID 8523 //
     /*  965323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  965326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  965331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965337 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965340 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965343 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  965346 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  965349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965353 */     // MIs[0] matrix_a_fmt
     /*  965353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965356 */     // MIs[0] matrix_b_fmt
     /*  965356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965359 */     // MIs[0] src2_modifiers
     /*  965359 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965362 */     // MIs[0] matrix_a_scale
     /*  965362 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965365 */     // MIs[0] matrix_a_scale_fmt
     /*  965365 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965368 */     // MIs[0] matrix_b_scale
     /*  965368 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965371 */     // MIs[0] matrix_b_scale_fmt
     /*  965371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965374 */     // MIs[0] matrix_a_reuse
     /*  965374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965377 */     // MIs[0] matrix_b_reuse
     /*  965377 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965380 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965387 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965392 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965394 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965396 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965402 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965407 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965409 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965411 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965413 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965415 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965417 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965419 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965421 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965423 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965425 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965433 */     GIR_RootConstrainSelectedInstOperands,
     /*  965434 */     // GIR_Coverage, 8523,
     /*  965434 */     GIR_EraseRootFromParent_Done,
     /*  965435 */   // Label 15277: @965435
     /*  965435 */   GIM_Try, /*On fail goto*//*Label 15278*/ GIMT_Encode4(965552), // Rule ID 8524 //
     /*  965440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  965443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  965448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965454 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965457 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965460 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  965463 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  965466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965470 */     // MIs[0] matrix_a_fmt
     /*  965470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965473 */     // MIs[0] matrix_b_fmt
     /*  965473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965476 */     // MIs[0] src2_modifiers
     /*  965476 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965479 */     // MIs[0] matrix_a_scale
     /*  965479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965482 */     // MIs[0] matrix_a_scale_fmt
     /*  965482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965485 */     // MIs[0] matrix_b_scale
     /*  965485 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965488 */     // MIs[0] matrix_b_scale_fmt
     /*  965488 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965491 */     // MIs[0] matrix_a_reuse
     /*  965491 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965494 */     // MIs[0] matrix_b_reuse
     /*  965494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965497 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965504 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965509 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965511 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965513 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965524 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965526 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965528 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965530 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965532 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965534 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965536 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965538 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965540 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965542 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965544 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965550 */     GIR_RootConstrainSelectedInstOperands,
     /*  965551 */     // GIR_Coverage, 8524,
     /*  965551 */     GIR_EraseRootFromParent_Done,
     /*  965552 */   // Label 15278: @965552
     /*  965552 */   GIM_Try, /*On fail goto*//*Label 15279*/ GIMT_Encode4(965669), // Rule ID 8525 //
     /*  965557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  965560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  965565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965568 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965571 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965574 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965577 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  965580 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  965583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965587 */     // MIs[0] matrix_a_fmt
     /*  965587 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965590 */     // MIs[0] matrix_b_fmt
     /*  965590 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965593 */     // MIs[0] src2_modifiers
     /*  965593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965596 */     // MIs[0] matrix_a_scale
     /*  965596 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965599 */     // MIs[0] matrix_a_scale_fmt
     /*  965599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965602 */     // MIs[0] matrix_b_scale
     /*  965602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965605 */     // MIs[0] matrix_b_scale_fmt
     /*  965605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965608 */     // MIs[0] matrix_a_reuse
     /*  965608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965611 */     // MIs[0] matrix_b_reuse
     /*  965611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965621 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965626 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965628 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965630 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965641 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965643 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965645 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965647 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965649 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965651 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965653 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965655 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965657 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965659 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965667 */     GIR_RootConstrainSelectedInstOperands,
     /*  965668 */     // GIR_Coverage, 8525,
     /*  965668 */     GIR_EraseRootFromParent_Done,
     /*  965669 */   // Label 15279: @965669
     /*  965669 */   GIM_Try, /*On fail goto*//*Label 15280*/ GIMT_Encode4(965786), // Rule ID 8526 //
     /*  965674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  965677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  965682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965688 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965691 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965694 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  965697 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  965700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965704 */     // MIs[0] matrix_a_fmt
     /*  965704 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965707 */     // MIs[0] matrix_b_fmt
     /*  965707 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965710 */     // MIs[0] src2_modifiers
     /*  965710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965713 */     // MIs[0] matrix_a_scale
     /*  965713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965716 */     // MIs[0] matrix_a_scale_fmt
     /*  965716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965719 */     // MIs[0] matrix_b_scale
     /*  965719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965722 */     // MIs[0] matrix_b_scale_fmt
     /*  965722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965725 */     // MIs[0] matrix_a_reuse
     /*  965725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965728 */     // MIs[0] matrix_b_reuse
     /*  965728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965731 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965738 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965743 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965745 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965747 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965758 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965760 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965762 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965764 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965766 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965768 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965770 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965772 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965774 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965776 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965784 */     GIR_RootConstrainSelectedInstOperands,
     /*  965785 */     // GIR_Coverage, 8526,
     /*  965785 */     GIR_EraseRootFromParent_Done,
     /*  965786 */   // Label 15280: @965786
     /*  965786 */   GIM_Try, /*On fail goto*//*Label 15281*/ GIMT_Encode4(965903), // Rule ID 8527 //
     /*  965791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  965794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  965799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965805 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  965808 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965811 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  965814 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  965817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965821 */     // MIs[0] matrix_a_fmt
     /*  965821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965824 */     // MIs[0] matrix_b_fmt
     /*  965824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965827 */     // MIs[0] src2_modifiers
     /*  965827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965830 */     // MIs[0] matrix_a_scale
     /*  965830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965833 */     // MIs[0] matrix_a_scale_fmt
     /*  965833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965836 */     // MIs[0] matrix_b_scale
     /*  965836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965839 */     // MIs[0] matrix_b_scale_fmt
     /*  965839 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965842 */     // MIs[0] matrix_a_reuse
     /*  965842 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965845 */     // MIs[0] matrix_b_reuse
     /*  965845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965848 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965855 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr),
     /*  965858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965860 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965862 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965864 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965875 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965877 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965879 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965881 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  965883 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  965885 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  965887 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  965889 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  965891 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  965893 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  965895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  965901 */     GIR_RootConstrainSelectedInstOperands,
     /*  965902 */     // GIR_Coverage, 8527,
     /*  965902 */     GIR_EraseRootFromParent_Done,
     /*  965903 */   // Label 15281: @965903
     /*  965903 */   GIM_Try, /*On fail goto*//*Label 15282*/ GIMT_Encode4(966020), // Rule ID 8543 //
     /*  965908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  965911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  965916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  965919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  965922 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  965925 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  965928 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  965931 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  965934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  965938 */     // MIs[0] matrix_a_fmt
     /*  965938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  965941 */     // MIs[0] matrix_b_fmt
     /*  965941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  965944 */     // MIs[0] src2_modifiers
     /*  965944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  965947 */     // MIs[0] matrix_a_scale
     /*  965947 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  965950 */     // MIs[0] matrix_a_scale_fmt
     /*  965950 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  965953 */     // MIs[0] matrix_b_scale
     /*  965953 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  965956 */     // MIs[0] matrix_b_scale_fmt
     /*  965956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  965959 */     // MIs[0] matrix_a_reuse
     /*  965959 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  965962 */     // MIs[0] matrix_b_reuse
     /*  965962 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  965965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  965972 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  965972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  965975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  965977 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  965979 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  965981 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  965987 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  965992 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  965994 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  965996 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  965998 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966000 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966002 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966004 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966006 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966008 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966010 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966012 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966015 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966018 */     GIR_RootConstrainSelectedInstOperands,
     /*  966019 */     // GIR_Coverage, 8543,
     /*  966019 */     GIR_EraseRootFromParent_Done,
     /*  966020 */   // Label 15282: @966020
     /*  966020 */   GIM_Try, /*On fail goto*//*Label 15283*/ GIMT_Encode4(966137), // Rule ID 8544 //
     /*  966025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  966028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  966033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966039 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966042 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966045 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  966048 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  966051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966055 */     // MIs[0] matrix_a_fmt
     /*  966055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966058 */     // MIs[0] matrix_b_fmt
     /*  966058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966061 */     // MIs[0] src2_modifiers
     /*  966061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966064 */     // MIs[0] matrix_a_scale
     /*  966064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966067 */     // MIs[0] matrix_a_scale_fmt
     /*  966067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966070 */     // MIs[0] matrix_b_scale
     /*  966070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966073 */     // MIs[0] matrix_b_scale_fmt
     /*  966073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966076 */     // MIs[0] matrix_a_reuse
     /*  966076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966079 */     // MIs[0] matrix_b_reuse
     /*  966079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966082 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966089 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966094 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966096 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966098 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966109 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966111 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966113 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966115 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966117 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966119 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966121 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966123 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966125 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966127 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966132 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966135 */     GIR_RootConstrainSelectedInstOperands,
     /*  966136 */     // GIR_Coverage, 8544,
     /*  966136 */     GIR_EraseRootFromParent_Done,
     /*  966137 */   // Label 15283: @966137
     /*  966137 */   GIM_Try, /*On fail goto*//*Label 15284*/ GIMT_Encode4(966254), // Rule ID 8545 //
     /*  966142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  966145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  966150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966153 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966156 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966159 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966162 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  966165 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  966168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966172 */     // MIs[0] matrix_a_fmt
     /*  966172 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966175 */     // MIs[0] matrix_b_fmt
     /*  966175 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966178 */     // MIs[0] src2_modifiers
     /*  966178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966181 */     // MIs[0] matrix_a_scale
     /*  966181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966184 */     // MIs[0] matrix_a_scale_fmt
     /*  966184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966187 */     // MIs[0] matrix_b_scale
     /*  966187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966190 */     // MIs[0] matrix_b_scale_fmt
     /*  966190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966193 */     // MIs[0] matrix_a_reuse
     /*  966193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966196 */     // MIs[0] matrix_b_reuse
     /*  966196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966206 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966211 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966213 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966215 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966226 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966228 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966230 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966232 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966234 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966236 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966238 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966240 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966242 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966244 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966246 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966249 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966252 */     GIR_RootConstrainSelectedInstOperands,
     /*  966253 */     // GIR_Coverage, 8545,
     /*  966253 */     GIR_EraseRootFromParent_Done,
     /*  966254 */   // Label 15284: @966254
     /*  966254 */   GIM_Try, /*On fail goto*//*Label 15285*/ GIMT_Encode4(966371), // Rule ID 8546 //
     /*  966259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  966262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  966267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966273 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966276 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966279 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  966282 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  966285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966289 */     // MIs[0] matrix_a_fmt
     /*  966289 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966292 */     // MIs[0] matrix_b_fmt
     /*  966292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966295 */     // MIs[0] src2_modifiers
     /*  966295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966298 */     // MIs[0] matrix_a_scale
     /*  966298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966301 */     // MIs[0] matrix_a_scale_fmt
     /*  966301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966304 */     // MIs[0] matrix_b_scale
     /*  966304 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966307 */     // MIs[0] matrix_b_scale_fmt
     /*  966307 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966310 */     // MIs[0] matrix_a_reuse
     /*  966310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966313 */     // MIs[0] matrix_b_reuse
     /*  966313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966316 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966323 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966328 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966330 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966332 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966343 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966345 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966347 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966349 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966351 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966353 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966355 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966357 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966359 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966361 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966366 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966369 */     GIR_RootConstrainSelectedInstOperands,
     /*  966370 */     // GIR_Coverage, 8546,
     /*  966370 */     GIR_EraseRootFromParent_Done,
     /*  966371 */   // Label 15285: @966371
     /*  966371 */   GIM_Try, /*On fail goto*//*Label 15286*/ GIMT_Encode4(966488), // Rule ID 8547 //
     /*  966376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  966379 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  966384 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966390 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966393 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966396 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  966399 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  966402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966406 */     // MIs[0] matrix_a_fmt
     /*  966406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966409 */     // MIs[0] matrix_b_fmt
     /*  966409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966412 */     // MIs[0] src2_modifiers
     /*  966412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966415 */     // MIs[0] matrix_a_scale
     /*  966415 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966418 */     // MIs[0] matrix_a_scale_fmt
     /*  966418 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966421 */     // MIs[0] matrix_b_scale
     /*  966421 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966424 */     // MIs[0] matrix_b_scale_fmt
     /*  966424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966427 */     // MIs[0] matrix_a_reuse
     /*  966427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966430 */     // MIs[0] matrix_b_reuse
     /*  966430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966440 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966445 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966447 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966449 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966455 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966460 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966462 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966464 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966466 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966468 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966470 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966472 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966474 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966476 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966478 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966480 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966486 */     GIR_RootConstrainSelectedInstOperands,
     /*  966487 */     // GIR_Coverage, 8547,
     /*  966487 */     GIR_EraseRootFromParent_Done,
     /*  966488 */   // Label 15286: @966488
     /*  966488 */   GIM_Try, /*On fail goto*//*Label 15287*/ GIMT_Encode4(966605), // Rule ID 8553 //
     /*  966493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  966496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  966501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966504 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966507 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966510 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966513 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  966516 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  966519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966523 */     // MIs[0] matrix_a_fmt
     /*  966523 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966526 */     // MIs[0] matrix_b_fmt
     /*  966526 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966529 */     // MIs[0] src2_modifiers
     /*  966529 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966532 */     // MIs[0] matrix_a_scale
     /*  966532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966535 */     // MIs[0] matrix_a_scale_fmt
     /*  966535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966538 */     // MIs[0] matrix_b_scale
     /*  966538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966541 */     // MIs[0] matrix_b_scale_fmt
     /*  966541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966544 */     // MIs[0] matrix_a_reuse
     /*  966544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966547 */     // MIs[0] matrix_b_reuse
     /*  966547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966550 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966557 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966562 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966564 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966566 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966572 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966577 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966579 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966581 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966583 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966585 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966587 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966589 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966591 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966593 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966595 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966597 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966603 */     GIR_RootConstrainSelectedInstOperands,
     /*  966604 */     // GIR_Coverage, 8553,
     /*  966604 */     GIR_EraseRootFromParent_Done,
     /*  966605 */   // Label 15287: @966605
     /*  966605 */   GIM_Try, /*On fail goto*//*Label 15288*/ GIMT_Encode4(966722), // Rule ID 8554 //
     /*  966610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  966613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  966618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966621 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966624 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966627 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966630 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  966633 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  966636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966640 */     // MIs[0] matrix_a_fmt
     /*  966640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966643 */     // MIs[0] matrix_b_fmt
     /*  966643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966646 */     // MIs[0] src2_modifiers
     /*  966646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966649 */     // MIs[0] matrix_a_scale
     /*  966649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966652 */     // MIs[0] matrix_a_scale_fmt
     /*  966652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966655 */     // MIs[0] matrix_b_scale
     /*  966655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966658 */     // MIs[0] matrix_b_scale_fmt
     /*  966658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966661 */     // MIs[0] matrix_a_reuse
     /*  966661 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966664 */     // MIs[0] matrix_b_reuse
     /*  966664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966674 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966679 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966681 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966683 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966694 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966696 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966698 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966700 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966702 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966704 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966706 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966708 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966710 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966712 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966720 */     GIR_RootConstrainSelectedInstOperands,
     /*  966721 */     // GIR_Coverage, 8554,
     /*  966721 */     GIR_EraseRootFromParent_Done,
     /*  966722 */   // Label 15288: @966722
     /*  966722 */   GIM_Try, /*On fail goto*//*Label 15289*/ GIMT_Encode4(966839), // Rule ID 8555 //
     /*  966727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  966730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  966735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966738 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966741 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966744 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966747 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  966750 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  966753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966757 */     // MIs[0] matrix_a_fmt
     /*  966757 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966760 */     // MIs[0] matrix_b_fmt
     /*  966760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966763 */     // MIs[0] src2_modifiers
     /*  966763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966766 */     // MIs[0] matrix_a_scale
     /*  966766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966769 */     // MIs[0] matrix_a_scale_fmt
     /*  966769 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966772 */     // MIs[0] matrix_b_scale
     /*  966772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966775 */     // MIs[0] matrix_b_scale_fmt
     /*  966775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966778 */     // MIs[0] matrix_a_reuse
     /*  966778 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966781 */     // MIs[0] matrix_b_reuse
     /*  966781 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966784 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966791 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966796 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966798 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966800 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966811 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966813 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966815 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966817 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966819 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966821 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966823 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966825 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966827 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966829 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966837 */     GIR_RootConstrainSelectedInstOperands,
     /*  966838 */     // GIR_Coverage, 8555,
     /*  966838 */     GIR_EraseRootFromParent_Done,
     /*  966839 */   // Label 15289: @966839
     /*  966839 */   GIM_Try, /*On fail goto*//*Label 15290*/ GIMT_Encode4(966956), // Rule ID 8556 //
     /*  966844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  966847 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  966852 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966858 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966861 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966864 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  966867 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  966870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966874 */     // MIs[0] matrix_a_fmt
     /*  966874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966877 */     // MIs[0] matrix_b_fmt
     /*  966877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966880 */     // MIs[0] src2_modifiers
     /*  966880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  966883 */     // MIs[0] matrix_a_scale
     /*  966883 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  966886 */     // MIs[0] matrix_a_scale_fmt
     /*  966886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  966889 */     // MIs[0] matrix_b_scale
     /*  966889 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  966892 */     // MIs[0] matrix_b_scale_fmt
     /*  966892 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  966895 */     // MIs[0] matrix_a_reuse
     /*  966895 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  966898 */     // MIs[0] matrix_b_reuse
     /*  966898 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  966901 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  966908 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  966908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  966911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  966913 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  966915 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  966917 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  966923 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  966928 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  966930 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  966932 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  966934 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  966936 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  966938 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  966940 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  966942 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  966944 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  966946 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  966948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  966954 */     GIR_RootConstrainSelectedInstOperands,
     /*  966955 */     // GIR_Coverage, 8556,
     /*  966955 */     GIR_EraseRootFromParent_Done,
     /*  966956 */   // Label 15290: @966956
     /*  966956 */   GIM_Try, /*On fail goto*//*Label 15291*/ GIMT_Encode4(967073), // Rule ID 8557 //
     /*  966961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  966964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  966969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  966972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  966975 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  966978 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  966981 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  966984 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  966987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  966991 */     // MIs[0] matrix_a_fmt
     /*  966991 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  966994 */     // MIs[0] matrix_b_fmt
     /*  966994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  966997 */     // MIs[0] src2_modifiers
     /*  966997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967000 */     // MIs[0] matrix_a_scale
     /*  967000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967003 */     // MIs[0] matrix_a_scale_fmt
     /*  967003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967006 */     // MIs[0] matrix_b_scale
     /*  967006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967009 */     // MIs[0] matrix_b_scale_fmt
     /*  967009 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967012 */     // MIs[0] matrix_a_reuse
     /*  967012 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967015 */     // MIs[0] matrix_b_reuse
     /*  967015 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967018 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
     /*  967025 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2), (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr),
     /*  967028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967030 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967032 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967034 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
     /*  967045 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967047 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967049 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967051 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967053 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967055 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967057 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967059 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967061 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967063 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967071 */     GIR_RootConstrainSelectedInstOperands,
     /*  967072 */     // GIR_Coverage, 8557,
     /*  967072 */     GIR_EraseRootFromParent_Done,
     /*  967073 */   // Label 15291: @967073
     /*  967073 */   GIM_Try, /*On fail goto*//*Label 15292*/ GIMT_Encode4(967180), // Rule ID 8298 //
     /*  967078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  967081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  967086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967092 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967095 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967098 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  967101 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  967104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967108 */     // MIs[0] matrix_a_fmt
     /*  967108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967111 */     // MIs[0] matrix_b_fmt
     /*  967111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967114 */     // MIs[0] src2_modifiers
     /*  967114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967117 */     // MIs[0] matrix_a_scale
     /*  967117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967120 */     // MIs[0] matrix_a_scale_fmt
     /*  967120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967123 */     // MIs[0] matrix_b_scale
     /*  967123 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967126 */     // MIs[0] matrix_b_scale_fmt
     /*  967126 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967129 */     // MIs[0] matrix_a_reuse
     /*  967129 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967132 */     // MIs[0] matrix_b_reuse
     /*  967132 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967135 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967140 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967142 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967144 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967150 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967152 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967154 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967156 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967158 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967160 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967162 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967164 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967166 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967168 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967170 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967172 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967178 */     GIR_RootConstrainSelectedInstOperands,
     /*  967179 */     // GIR_Coverage, 8298,
     /*  967179 */     GIR_EraseRootFromParent_Done,
     /*  967180 */   // Label 15292: @967180
     /*  967180 */   GIM_Try, /*On fail goto*//*Label 15293*/ GIMT_Encode4(967287), // Rule ID 8299 //
     /*  967185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  967188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  967193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967199 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967202 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967205 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  967208 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  967211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967215 */     // MIs[0] matrix_a_fmt
     /*  967215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967218 */     // MIs[0] matrix_b_fmt
     /*  967218 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967221 */     // MIs[0] src2_modifiers
     /*  967221 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967224 */     // MIs[0] matrix_a_scale
     /*  967224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967227 */     // MIs[0] matrix_a_scale_fmt
     /*  967227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967230 */     // MIs[0] matrix_b_scale
     /*  967230 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967233 */     // MIs[0] matrix_b_scale_fmt
     /*  967233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967236 */     // MIs[0] matrix_a_reuse
     /*  967236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967239 */     // MIs[0] matrix_b_reuse
     /*  967239 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967242 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967247 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967249 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967251 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967257 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967259 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967261 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967263 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967265 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967267 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967269 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967271 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967273 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967275 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967277 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967282 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967285 */     GIR_RootConstrainSelectedInstOperands,
     /*  967286 */     // GIR_Coverage, 8299,
     /*  967286 */     GIR_EraseRootFromParent_Done,
     /*  967287 */   // Label 15293: @967287
     /*  967287 */   GIM_Try, /*On fail goto*//*Label 15294*/ GIMT_Encode4(967394), // Rule ID 8300 //
     /*  967292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  967295 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  967300 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967306 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967309 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967312 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  967315 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  967318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967322 */     // MIs[0] matrix_a_fmt
     /*  967322 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967325 */     // MIs[0] matrix_b_fmt
     /*  967325 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967328 */     // MIs[0] src2_modifiers
     /*  967328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967331 */     // MIs[0] matrix_a_scale
     /*  967331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967334 */     // MIs[0] matrix_a_scale_fmt
     /*  967334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967337 */     // MIs[0] matrix_b_scale
     /*  967337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967340 */     // MIs[0] matrix_b_scale_fmt
     /*  967340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967343 */     // MIs[0] matrix_a_reuse
     /*  967343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967346 */     // MIs[0] matrix_b_reuse
     /*  967346 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967349 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967354 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967356 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967358 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967364 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967366 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967368 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967370 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967372 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967374 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967376 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967378 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967380 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967382 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967384 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967392 */     GIR_RootConstrainSelectedInstOperands,
     /*  967393 */     // GIR_Coverage, 8300,
     /*  967393 */     GIR_EraseRootFromParent_Done,
     /*  967394 */   // Label 15294: @967394
     /*  967394 */   GIM_Try, /*On fail goto*//*Label 15295*/ GIMT_Encode4(967501), // Rule ID 8301 //
     /*  967399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  967402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  967407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967413 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967416 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967419 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  967422 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  967425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967429 */     // MIs[0] matrix_a_fmt
     /*  967429 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967432 */     // MIs[0] matrix_b_fmt
     /*  967432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967435 */     // MIs[0] src2_modifiers
     /*  967435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967438 */     // MIs[0] matrix_a_scale
     /*  967438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967441 */     // MIs[0] matrix_a_scale_fmt
     /*  967441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967444 */     // MIs[0] matrix_b_scale
     /*  967444 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967447 */     // MIs[0] matrix_b_scale_fmt
     /*  967447 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967450 */     // MIs[0] matrix_a_reuse
     /*  967450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967453 */     // MIs[0] matrix_b_reuse
     /*  967453 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967456 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967461 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967463 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967465 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967471 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967473 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967475 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967477 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967479 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967481 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967483 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967485 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967487 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967489 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967491 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967496 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967499 */     GIR_RootConstrainSelectedInstOperands,
     /*  967500 */     // GIR_Coverage, 8301,
     /*  967500 */     GIR_EraseRootFromParent_Done,
     /*  967501 */   // Label 15295: @967501
     /*  967501 */   GIM_Try, /*On fail goto*//*Label 15296*/ GIMT_Encode4(967608), // Rule ID 8302 //
     /*  967506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  967509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  967514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967520 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967523 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967526 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  967529 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  967532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967536 */     // MIs[0] matrix_a_fmt
     /*  967536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967539 */     // MIs[0] matrix_b_fmt
     /*  967539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967542 */     // MIs[0] src2_modifiers
     /*  967542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967545 */     // MIs[0] matrix_a_scale
     /*  967545 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967548 */     // MIs[0] matrix_a_scale_fmt
     /*  967548 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967551 */     // MIs[0] matrix_b_scale
     /*  967551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967554 */     // MIs[0] matrix_b_scale_fmt
     /*  967554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967557 */     // MIs[0] matrix_a_reuse
     /*  967557 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967560 */     // MIs[0] matrix_b_reuse
     /*  967560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967563 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967568 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967570 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967572 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967578 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967580 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967582 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967584 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967586 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967588 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967590 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967592 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967594 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967596 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967598 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967600 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967606 */     GIR_RootConstrainSelectedInstOperands,
     /*  967607 */     // GIR_Coverage, 8302,
     /*  967607 */     GIR_EraseRootFromParent_Done,
     /*  967608 */   // Label 15296: @967608
     /*  967608 */   GIM_Try, /*On fail goto*//*Label 15297*/ GIMT_Encode4(967715), // Rule ID 8308 //
     /*  967613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  967616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  967621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967627 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967630 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967633 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  967636 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  967639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967643 */     // MIs[0] matrix_a_fmt
     /*  967643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967646 */     // MIs[0] matrix_b_fmt
     /*  967646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967649 */     // MIs[0] src2_modifiers
     /*  967649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967652 */     // MIs[0] matrix_a_scale
     /*  967652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967655 */     // MIs[0] matrix_a_scale_fmt
     /*  967655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967658 */     // MIs[0] matrix_b_scale
     /*  967658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967661 */     // MIs[0] matrix_b_scale_fmt
     /*  967661 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967664 */     // MIs[0] matrix_a_reuse
     /*  967664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967667 */     // MIs[0] matrix_b_reuse
     /*  967667 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967670 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967675 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967677 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967679 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967685 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967687 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967689 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967691 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967693 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967695 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967697 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967699 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967701 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967703 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967705 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967710 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967713 */     GIR_RootConstrainSelectedInstOperands,
     /*  967714 */     // GIR_Coverage, 8308,
     /*  967714 */     GIR_EraseRootFromParent_Done,
     /*  967715 */   // Label 15297: @967715
     /*  967715 */   GIM_Try, /*On fail goto*//*Label 15298*/ GIMT_Encode4(967822), // Rule ID 8309 //
     /*  967720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  967723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  967728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967731 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967734 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967737 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967740 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  967743 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  967746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967750 */     // MIs[0] matrix_a_fmt
     /*  967750 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967753 */     // MIs[0] matrix_b_fmt
     /*  967753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967756 */     // MIs[0] src2_modifiers
     /*  967756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967759 */     // MIs[0] matrix_a_scale
     /*  967759 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967762 */     // MIs[0] matrix_a_scale_fmt
     /*  967762 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967765 */     // MIs[0] matrix_b_scale
     /*  967765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967768 */     // MIs[0] matrix_b_scale_fmt
     /*  967768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967771 */     // MIs[0] matrix_a_reuse
     /*  967771 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967774 */     // MIs[0] matrix_b_reuse
     /*  967774 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967777 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967782 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967784 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967786 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967792 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967794 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967796 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967798 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967800 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967802 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967804 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967806 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967808 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967810 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967812 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967817 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967820 */     GIR_RootConstrainSelectedInstOperands,
     /*  967821 */     // GIR_Coverage, 8309,
     /*  967821 */     GIR_EraseRootFromParent_Done,
     /*  967822 */   // Label 15298: @967822
     /*  967822 */   GIM_Try, /*On fail goto*//*Label 15299*/ GIMT_Encode4(967929), // Rule ID 8310 //
     /*  967827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  967830 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  967835 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967838 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967841 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967844 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967847 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  967850 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  967853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967857 */     // MIs[0] matrix_a_fmt
     /*  967857 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967860 */     // MIs[0] matrix_b_fmt
     /*  967860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967863 */     // MIs[0] src2_modifiers
     /*  967863 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967866 */     // MIs[0] matrix_a_scale
     /*  967866 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967869 */     // MIs[0] matrix_a_scale_fmt
     /*  967869 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967872 */     // MIs[0] matrix_b_scale
     /*  967872 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967875 */     // MIs[0] matrix_b_scale_fmt
     /*  967875 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967878 */     // MIs[0] matrix_a_reuse
     /*  967878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967881 */     // MIs[0] matrix_b_reuse
     /*  967881 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967884 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967889 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967891 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  967893 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  967899 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  967901 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  967903 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  967905 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  967907 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  967909 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  967911 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  967913 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  967915 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  967917 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  967919 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  967921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  967927 */     GIR_RootConstrainSelectedInstOperands,
     /*  967928 */     // GIR_Coverage, 8310,
     /*  967928 */     GIR_EraseRootFromParent_Done,
     /*  967929 */   // Label 15299: @967929
     /*  967929 */   GIM_Try, /*On fail goto*//*Label 15300*/ GIMT_Encode4(968036), // Rule ID 8311 //
     /*  967934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  967937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  967942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  967945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  967948 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  967951 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  967954 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  967957 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  967960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  967964 */     // MIs[0] matrix_a_fmt
     /*  967964 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  967967 */     // MIs[0] matrix_b_fmt
     /*  967967 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  967970 */     // MIs[0] src2_modifiers
     /*  967970 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  967973 */     // MIs[0] matrix_a_scale
     /*  967973 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  967976 */     // MIs[0] matrix_a_scale_fmt
     /*  967976 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  967979 */     // MIs[0] matrix_b_scale
     /*  967979 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  967982 */     // MIs[0] matrix_b_scale_fmt
     /*  967982 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  967985 */     // MIs[0] matrix_a_reuse
     /*  967985 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  967988 */     // MIs[0] matrix_b_reuse
     /*  967988 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  967991 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  967991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  967994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  967996 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  967998 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968000 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968006 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968008 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968010 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968012 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968014 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968016 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968018 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968020 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968022 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968024 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968026 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968034 */     GIR_RootConstrainSelectedInstOperands,
     /*  968035 */     // GIR_Coverage, 8311,
     /*  968035 */     GIR_EraseRootFromParent_Done,
     /*  968036 */   // Label 15300: @968036
     /*  968036 */   GIM_Try, /*On fail goto*//*Label 15301*/ GIMT_Encode4(968143), // Rule ID 8312 //
     /*  968041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  968044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  968049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968055 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  968058 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968061 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  968064 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  968067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968071 */     // MIs[0] matrix_a_fmt
     /*  968071 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968074 */     // MIs[0] matrix_b_fmt
     /*  968074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968077 */     // MIs[0] src2_modifiers
     /*  968077 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968080 */     // MIs[0] matrix_a_scale
     /*  968080 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968083 */     // MIs[0] matrix_a_scale_fmt
     /*  968083 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968086 */     // MIs[0] matrix_b_scale
     /*  968086 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968089 */     // MIs[0] matrix_b_scale_fmt
     /*  968089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968092 */     // MIs[0] matrix_a_reuse
     /*  968092 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968095 */     // MIs[0] matrix_b_reuse
     /*  968095 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968098 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr),
     /*  968101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968103 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968105 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968107 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968113 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968115 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968117 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968119 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968121 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968123 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968125 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968127 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968129 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968131 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968133 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968135 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968138 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968141 */     GIR_RootConstrainSelectedInstOperands,
     /*  968142 */     // GIR_Coverage, 8312,
     /*  968142 */     GIR_EraseRootFromParent_Done,
     /*  968143 */   // Label 15301: @968143
     /*  968143 */   GIM_Try, /*On fail goto*//*Label 15302*/ GIMT_Encode4(968250), // Rule ID 8328 //
     /*  968148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  968151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  968156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968159 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968162 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968165 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968168 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  968171 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  968174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968178 */     // MIs[0] matrix_a_fmt
     /*  968178 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968181 */     // MIs[0] matrix_b_fmt
     /*  968181 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968184 */     // MIs[0] src2_modifiers
     /*  968184 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968187 */     // MIs[0] matrix_a_scale
     /*  968187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968190 */     // MIs[0] matrix_a_scale_fmt
     /*  968190 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968193 */     // MIs[0] matrix_b_scale
     /*  968193 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968196 */     // MIs[0] matrix_b_scale_fmt
     /*  968196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968199 */     // MIs[0] matrix_a_reuse
     /*  968199 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968202 */     // MIs[0] matrix_b_reuse
     /*  968202 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968205 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968210 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968212 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968214 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968220 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968222 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968224 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968226 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968228 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968230 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968232 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968234 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968236 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968238 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968240 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968245 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968248 */     GIR_RootConstrainSelectedInstOperands,
     /*  968249 */     // GIR_Coverage, 8328,
     /*  968249 */     GIR_EraseRootFromParent_Done,
     /*  968250 */   // Label 15302: @968250
     /*  968250 */   GIM_Try, /*On fail goto*//*Label 15303*/ GIMT_Encode4(968357), // Rule ID 8329 //
     /*  968255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  968258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  968263 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968269 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968272 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968275 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  968278 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  968281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968285 */     // MIs[0] matrix_a_fmt
     /*  968285 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968288 */     // MIs[0] matrix_b_fmt
     /*  968288 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968291 */     // MIs[0] src2_modifiers
     /*  968291 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968294 */     // MIs[0] matrix_a_scale
     /*  968294 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968297 */     // MIs[0] matrix_a_scale_fmt
     /*  968297 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968300 */     // MIs[0] matrix_b_scale
     /*  968300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968303 */     // MIs[0] matrix_b_scale_fmt
     /*  968303 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968306 */     // MIs[0] matrix_a_reuse
     /*  968306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968309 */     // MIs[0] matrix_b_reuse
     /*  968309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968312 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968317 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968319 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968321 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968327 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968329 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968331 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968333 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968335 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968337 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968339 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968341 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968343 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968345 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968347 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968349 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968352 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968355 */     GIR_RootConstrainSelectedInstOperands,
     /*  968356 */     // GIR_Coverage, 8329,
     /*  968356 */     GIR_EraseRootFromParent_Done,
     /*  968357 */   // Label 15303: @968357
     /*  968357 */   GIM_Try, /*On fail goto*//*Label 15304*/ GIMT_Encode4(968464), // Rule ID 8330 //
     /*  968362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  968365 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  968370 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968376 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968379 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968382 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  968385 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  968388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968392 */     // MIs[0] matrix_a_fmt
     /*  968392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968395 */     // MIs[0] matrix_b_fmt
     /*  968395 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968398 */     // MIs[0] src2_modifiers
     /*  968398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968401 */     // MIs[0] matrix_a_scale
     /*  968401 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968404 */     // MIs[0] matrix_a_scale_fmt
     /*  968404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968407 */     // MIs[0] matrix_b_scale
     /*  968407 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968410 */     // MIs[0] matrix_b_scale_fmt
     /*  968410 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968413 */     // MIs[0] matrix_a_reuse
     /*  968413 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968416 */     // MIs[0] matrix_b_reuse
     /*  968416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968419 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968424 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968426 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968428 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968434 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968436 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968438 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968440 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968442 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968444 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968446 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968448 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968450 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968452 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968454 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968462 */     GIR_RootConstrainSelectedInstOperands,
     /*  968463 */     // GIR_Coverage, 8330,
     /*  968463 */     GIR_EraseRootFromParent_Done,
     /*  968464 */   // Label 15304: @968464
     /*  968464 */   GIM_Try, /*On fail goto*//*Label 15305*/ GIMT_Encode4(968571), // Rule ID 8331 //
     /*  968469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  968472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  968477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968480 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968483 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968486 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968489 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  968492 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  968495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968499 */     // MIs[0] matrix_a_fmt
     /*  968499 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968502 */     // MIs[0] matrix_b_fmt
     /*  968502 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968505 */     // MIs[0] src2_modifiers
     /*  968505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968508 */     // MIs[0] matrix_a_scale
     /*  968508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968511 */     // MIs[0] matrix_a_scale_fmt
     /*  968511 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968514 */     // MIs[0] matrix_b_scale
     /*  968514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968517 */     // MIs[0] matrix_b_scale_fmt
     /*  968517 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968520 */     // MIs[0] matrix_a_reuse
     /*  968520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968523 */     // MIs[0] matrix_b_reuse
     /*  968523 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968526 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968531 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968533 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968535 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968541 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968543 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968545 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968547 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968549 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968551 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968553 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968555 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968557 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968559 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968561 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968566 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968569 */     GIR_RootConstrainSelectedInstOperands,
     /*  968570 */     // GIR_Coverage, 8331,
     /*  968570 */     GIR_EraseRootFromParent_Done,
     /*  968571 */   // Label 15305: @968571
     /*  968571 */   GIM_Try, /*On fail goto*//*Label 15306*/ GIMT_Encode4(968678), // Rule ID 8332 //
     /*  968576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  968579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  968584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968590 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968593 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968596 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  968599 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  968602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968606 */     // MIs[0] matrix_a_fmt
     /*  968606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968609 */     // MIs[0] matrix_b_fmt
     /*  968609 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968612 */     // MIs[0] src2_modifiers
     /*  968612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968615 */     // MIs[0] matrix_a_scale
     /*  968615 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968618 */     // MIs[0] matrix_a_scale_fmt
     /*  968618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968621 */     // MIs[0] matrix_b_scale
     /*  968621 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968624 */     // MIs[0] matrix_b_scale_fmt
     /*  968624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968627 */     // MIs[0] matrix_a_reuse
     /*  968627 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968630 */     // MIs[0] matrix_b_reuse
     /*  968630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968633 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968638 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968640 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968642 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968648 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968650 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968652 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968654 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968656 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968658 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968660 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968662 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968664 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968666 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968668 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968673 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968676 */     GIR_RootConstrainSelectedInstOperands,
     /*  968677 */     // GIR_Coverage, 8332,
     /*  968677 */     GIR_EraseRootFromParent_Done,
     /*  968678 */   // Label 15306: @968678
     /*  968678 */   GIM_Try, /*On fail goto*//*Label 15307*/ GIMT_Encode4(968785), // Rule ID 8338 //
     /*  968683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  968686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  968691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968694 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968697 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968700 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968703 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  968706 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  968709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968713 */     // MIs[0] matrix_a_fmt
     /*  968713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968716 */     // MIs[0] matrix_b_fmt
     /*  968716 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968719 */     // MIs[0] src2_modifiers
     /*  968719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968722 */     // MIs[0] matrix_a_scale
     /*  968722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968725 */     // MIs[0] matrix_a_scale_fmt
     /*  968725 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968728 */     // MIs[0] matrix_b_scale
     /*  968728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968731 */     // MIs[0] matrix_b_scale_fmt
     /*  968731 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968734 */     // MIs[0] matrix_a_reuse
     /*  968734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968737 */     // MIs[0] matrix_b_reuse
     /*  968737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968740 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968745 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968747 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968749 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968755 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968757 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968759 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968761 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968763 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968765 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968767 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968769 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968771 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968773 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968775 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968783 */     GIR_RootConstrainSelectedInstOperands,
     /*  968784 */     // GIR_Coverage, 8338,
     /*  968784 */     GIR_EraseRootFromParent_Done,
     /*  968785 */   // Label 15307: @968785
     /*  968785 */   GIM_Try, /*On fail goto*//*Label 15308*/ GIMT_Encode4(968892), // Rule ID 8339 //
     /*  968790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  968793 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  968798 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968801 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968804 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968807 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968810 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  968813 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  968816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968820 */     // MIs[0] matrix_a_fmt
     /*  968820 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968823 */     // MIs[0] matrix_b_fmt
     /*  968823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968826 */     // MIs[0] src2_modifiers
     /*  968826 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968829 */     // MIs[0] matrix_a_scale
     /*  968829 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968832 */     // MIs[0] matrix_a_scale_fmt
     /*  968832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968835 */     // MIs[0] matrix_b_scale
     /*  968835 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968838 */     // MIs[0] matrix_b_scale_fmt
     /*  968838 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968841 */     // MIs[0] matrix_a_reuse
     /*  968841 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968844 */     // MIs[0] matrix_b_reuse
     /*  968844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968847 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968852 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968854 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968856 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968862 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968864 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968866 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968868 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968870 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968872 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968874 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968876 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968878 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968880 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968882 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968890 */     GIR_RootConstrainSelectedInstOperands,
     /*  968891 */     // GIR_Coverage, 8339,
     /*  968891 */     GIR_EraseRootFromParent_Done,
     /*  968892 */   // Label 15308: @968892
     /*  968892 */   GIM_Try, /*On fail goto*//*Label 15309*/ GIMT_Encode4(968999), // Rule ID 8340 //
     /*  968897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  968900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  968905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  968908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  968911 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  968914 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  968917 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  968920 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  968923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  968927 */     // MIs[0] matrix_a_fmt
     /*  968927 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  968930 */     // MIs[0] matrix_b_fmt
     /*  968930 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  968933 */     // MIs[0] src2_modifiers
     /*  968933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  968936 */     // MIs[0] matrix_a_scale
     /*  968936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  968939 */     // MIs[0] matrix_a_scale_fmt
     /*  968939 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  968942 */     // MIs[0] matrix_b_scale
     /*  968942 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  968945 */     // MIs[0] matrix_b_scale_fmt
     /*  968945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  968948 */     // MIs[0] matrix_a_reuse
     /*  968948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  968951 */     // MIs[0] matrix_b_reuse
     /*  968951 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  968954 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  968954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  968957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  968959 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  968961 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  968963 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  968969 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  968971 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  968973 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  968975 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  968977 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  968979 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  968981 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  968983 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  968985 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  968987 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  968989 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  968991 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968994 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  968997 */     GIR_RootConstrainSelectedInstOperands,
     /*  968998 */     // GIR_Coverage, 8340,
     /*  968998 */     GIR_EraseRootFromParent_Done,
     /*  968999 */   // Label 15309: @968999
     /*  968999 */   GIM_Try, /*On fail goto*//*Label 15310*/ GIMT_Encode4(969106), // Rule ID 8341 //
     /*  969004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  969007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  969012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969018 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  969021 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969024 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  969027 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  969030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969034 */     // MIs[0] matrix_a_fmt
     /*  969034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969037 */     // MIs[0] matrix_b_fmt
     /*  969037 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969040 */     // MIs[0] src2_modifiers
     /*  969040 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969043 */     // MIs[0] matrix_a_scale
     /*  969043 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969046 */     // MIs[0] matrix_a_scale_fmt
     /*  969046 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969049 */     // MIs[0] matrix_b_scale
     /*  969049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969052 */     // MIs[0] matrix_b_scale_fmt
     /*  969052 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969055 */     // MIs[0] matrix_a_reuse
     /*  969055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969058 */     // MIs[0] matrix_b_reuse
     /*  969058 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969061 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  969064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969066 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969068 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969070 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969076 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969078 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969080 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969082 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969084 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969086 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969088 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969090 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969092 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969094 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969096 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969098 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969104 */     GIR_RootConstrainSelectedInstOperands,
     /*  969105 */     // GIR_Coverage, 8341,
     /*  969105 */     GIR_EraseRootFromParent_Done,
     /*  969106 */   // Label 15310: @969106
     /*  969106 */   GIM_Try, /*On fail goto*//*Label 15311*/ GIMT_Encode4(969213), // Rule ID 8342 //
     /*  969111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  969114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  969119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969125 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  969128 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969131 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  969134 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  969137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969141 */     // MIs[0] matrix_a_fmt
     /*  969141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969144 */     // MIs[0] matrix_b_fmt
     /*  969144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969147 */     // MIs[0] src2_modifiers
     /*  969147 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969150 */     // MIs[0] matrix_a_scale
     /*  969150 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969153 */     // MIs[0] matrix_a_scale_fmt
     /*  969153 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969156 */     // MIs[0] matrix_b_scale
     /*  969156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969159 */     // MIs[0] matrix_b_scale_fmt
     /*  969159 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969162 */     // MIs[0] matrix_a_reuse
     /*  969162 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969165 */     // MIs[0] matrix_b_reuse
     /*  969165 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969168 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr),
     /*  969171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969173 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969175 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969177 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969183 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969185 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969187 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969189 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969191 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969193 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969195 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969197 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969199 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969201 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969203 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969211 */     GIR_RootConstrainSelectedInstOperands,
     /*  969212 */     // GIR_Coverage, 8342,
     /*  969212 */     GIR_EraseRootFromParent_Done,
     /*  969213 */   // Label 15311: @969213
     /*  969213 */   GIM_Try, /*On fail goto*//*Label 15312*/ GIMT_Encode4(969320), // Rule ID 8358 //
     /*  969218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  969221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  969226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969229 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969232 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969235 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969238 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  969241 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  969244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969248 */     // MIs[0] matrix_a_fmt
     /*  969248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969251 */     // MIs[0] matrix_b_fmt
     /*  969251 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969254 */     // MIs[0] src2_modifiers
     /*  969254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969257 */     // MIs[0] matrix_a_scale
     /*  969257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969260 */     // MIs[0] matrix_a_scale_fmt
     /*  969260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969263 */     // MIs[0] matrix_b_scale
     /*  969263 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969266 */     // MIs[0] matrix_b_scale_fmt
     /*  969266 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969269 */     // MIs[0] matrix_a_reuse
     /*  969269 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969272 */     // MIs[0] matrix_b_reuse
     /*  969272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969275 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969280 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969282 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969284 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969290 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969292 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969294 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969296 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969298 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969300 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969302 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969304 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969306 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969308 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969310 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969315 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969318 */     GIR_RootConstrainSelectedInstOperands,
     /*  969319 */     // GIR_Coverage, 8358,
     /*  969319 */     GIR_EraseRootFromParent_Done,
     /*  969320 */   // Label 15312: @969320
     /*  969320 */   GIM_Try, /*On fail goto*//*Label 15313*/ GIMT_Encode4(969427), // Rule ID 8359 //
     /*  969325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  969328 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  969333 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969339 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969342 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969345 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  969348 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  969351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969355 */     // MIs[0] matrix_a_fmt
     /*  969355 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969358 */     // MIs[0] matrix_b_fmt
     /*  969358 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969361 */     // MIs[0] src2_modifiers
     /*  969361 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969364 */     // MIs[0] matrix_a_scale
     /*  969364 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969367 */     // MIs[0] matrix_a_scale_fmt
     /*  969367 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969370 */     // MIs[0] matrix_b_scale
     /*  969370 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969373 */     // MIs[0] matrix_b_scale_fmt
     /*  969373 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969376 */     // MIs[0] matrix_a_reuse
     /*  969376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969379 */     // MIs[0] matrix_b_reuse
     /*  969379 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969382 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969387 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969389 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969391 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969397 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969399 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969401 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969403 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969405 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969407 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969409 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969411 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969413 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969415 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969417 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969422 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969425 */     GIR_RootConstrainSelectedInstOperands,
     /*  969426 */     // GIR_Coverage, 8359,
     /*  969426 */     GIR_EraseRootFromParent_Done,
     /*  969427 */   // Label 15313: @969427
     /*  969427 */   GIM_Try, /*On fail goto*//*Label 15314*/ GIMT_Encode4(969534), // Rule ID 8360 //
     /*  969432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  969435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  969440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969446 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969449 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969452 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  969455 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  969458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969462 */     // MIs[0] matrix_a_fmt
     /*  969462 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969465 */     // MIs[0] matrix_b_fmt
     /*  969465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969468 */     // MIs[0] src2_modifiers
     /*  969468 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969471 */     // MIs[0] matrix_a_scale
     /*  969471 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969474 */     // MIs[0] matrix_a_scale_fmt
     /*  969474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969477 */     // MIs[0] matrix_b_scale
     /*  969477 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969480 */     // MIs[0] matrix_b_scale_fmt
     /*  969480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969483 */     // MIs[0] matrix_a_reuse
     /*  969483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969486 */     // MIs[0] matrix_b_reuse
     /*  969486 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969489 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969494 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969496 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969498 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969504 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969506 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969508 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969510 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969512 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969514 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969516 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969518 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969520 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969522 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969524 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969532 */     GIR_RootConstrainSelectedInstOperands,
     /*  969533 */     // GIR_Coverage, 8360,
     /*  969533 */     GIR_EraseRootFromParent_Done,
     /*  969534 */   // Label 15314: @969534
     /*  969534 */   GIM_Try, /*On fail goto*//*Label 15315*/ GIMT_Encode4(969641), // Rule ID 8361 //
     /*  969539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  969542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  969547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969550 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969553 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969556 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969559 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  969562 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  969565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969569 */     // MIs[0] matrix_a_fmt
     /*  969569 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969572 */     // MIs[0] matrix_b_fmt
     /*  969572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969575 */     // MIs[0] src2_modifiers
     /*  969575 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969578 */     // MIs[0] matrix_a_scale
     /*  969578 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969581 */     // MIs[0] matrix_a_scale_fmt
     /*  969581 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969584 */     // MIs[0] matrix_b_scale
     /*  969584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969587 */     // MIs[0] matrix_b_scale_fmt
     /*  969587 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969590 */     // MIs[0] matrix_a_reuse
     /*  969590 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969593 */     // MIs[0] matrix_b_reuse
     /*  969593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969596 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969601 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969603 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969605 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969611 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969613 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969615 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969617 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969619 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969621 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969623 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969625 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969627 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969629 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969631 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969639 */     GIR_RootConstrainSelectedInstOperands,
     /*  969640 */     // GIR_Coverage, 8361,
     /*  969640 */     GIR_EraseRootFromParent_Done,
     /*  969641 */   // Label 15315: @969641
     /*  969641 */   GIM_Try, /*On fail goto*//*Label 15316*/ GIMT_Encode4(969748), // Rule ID 8362 //
     /*  969646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  969649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  969654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969660 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969663 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969666 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  969669 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  969672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969676 */     // MIs[0] matrix_a_fmt
     /*  969676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969679 */     // MIs[0] matrix_b_fmt
     /*  969679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969682 */     // MIs[0] src2_modifiers
     /*  969682 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969685 */     // MIs[0] matrix_a_scale
     /*  969685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969688 */     // MIs[0] matrix_a_scale_fmt
     /*  969688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969691 */     // MIs[0] matrix_b_scale
     /*  969691 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969694 */     // MIs[0] matrix_b_scale_fmt
     /*  969694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969697 */     // MIs[0] matrix_a_reuse
     /*  969697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969700 */     // MIs[0] matrix_b_reuse
     /*  969700 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969703 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969708 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969710 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969712 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969718 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969720 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969722 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969724 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969726 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969728 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969730 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969732 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969734 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969736 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969738 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969740 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969746 */     GIR_RootConstrainSelectedInstOperands,
     /*  969747 */     // GIR_Coverage, 8362,
     /*  969747 */     GIR_EraseRootFromParent_Done,
     /*  969748 */   // Label 15316: @969748
     /*  969748 */   GIM_Try, /*On fail goto*//*Label 15317*/ GIMT_Encode4(969855), // Rule ID 8368 //
     /*  969753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  969756 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  969761 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969764 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969767 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969770 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969773 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  969776 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  969779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969783 */     // MIs[0] matrix_a_fmt
     /*  969783 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969786 */     // MIs[0] matrix_b_fmt
     /*  969786 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969789 */     // MIs[0] src2_modifiers
     /*  969789 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969792 */     // MIs[0] matrix_a_scale
     /*  969792 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969795 */     // MIs[0] matrix_a_scale_fmt
     /*  969795 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969798 */     // MIs[0] matrix_b_scale
     /*  969798 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969801 */     // MIs[0] matrix_b_scale_fmt
     /*  969801 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969804 */     // MIs[0] matrix_a_reuse
     /*  969804 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969807 */     // MIs[0] matrix_b_reuse
     /*  969807 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969810 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969815 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969817 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969819 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969825 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969827 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969829 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969831 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969833 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969835 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969837 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969839 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969841 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969843 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969845 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969847 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969853 */     GIR_RootConstrainSelectedInstOperands,
     /*  969854 */     // GIR_Coverage, 8368,
     /*  969854 */     GIR_EraseRootFromParent_Done,
     /*  969855 */   // Label 15317: @969855
     /*  969855 */   GIM_Try, /*On fail goto*//*Label 15318*/ GIMT_Encode4(969962), // Rule ID 8369 //
     /*  969860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  969863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  969868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969874 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969877 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969880 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  969883 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  969886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969890 */     // MIs[0] matrix_a_fmt
     /*  969890 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  969893 */     // MIs[0] matrix_b_fmt
     /*  969893 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  969896 */     // MIs[0] src2_modifiers
     /*  969896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  969899 */     // MIs[0] matrix_a_scale
     /*  969899 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  969902 */     // MIs[0] matrix_a_scale_fmt
     /*  969902 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  969905 */     // MIs[0] matrix_b_scale
     /*  969905 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  969908 */     // MIs[0] matrix_b_scale_fmt
     /*  969908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  969911 */     // MIs[0] matrix_a_reuse
     /*  969911 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  969914 */     // MIs[0] matrix_b_reuse
     /*  969914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  969917 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  969917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  969920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  969922 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  969924 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  969926 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  969932 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  969934 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  969936 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  969938 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  969940 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  969942 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  969944 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  969946 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  969948 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  969950 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  969952 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  969954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  969960 */     GIR_RootConstrainSelectedInstOperands,
     /*  969961 */     // GIR_Coverage, 8369,
     /*  969961 */     GIR_EraseRootFromParent_Done,
     /*  969962 */   // Label 15318: @969962
     /*  969962 */   GIM_Try, /*On fail goto*//*Label 15319*/ GIMT_Encode4(970069), // Rule ID 8370 //
     /*  969967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  969970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  969975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  969978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  969981 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  969984 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  969987 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  969990 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  969993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  969997 */     // MIs[0] matrix_a_fmt
     /*  969997 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970000 */     // MIs[0] matrix_b_fmt
     /*  970000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970003 */     // MIs[0] src2_modifiers
     /*  970003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970006 */     // MIs[0] matrix_a_scale
     /*  970006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970009 */     // MIs[0] matrix_a_scale_fmt
     /*  970009 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970012 */     // MIs[0] matrix_b_scale
     /*  970012 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970015 */     // MIs[0] matrix_b_scale_fmt
     /*  970015 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970018 */     // MIs[0] matrix_a_reuse
     /*  970018 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970021 */     // MIs[0] matrix_b_reuse
     /*  970021 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970024 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  970027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970029 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970031 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970033 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970039 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970041 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970043 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970045 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970047 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970049 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970051 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970053 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970055 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970057 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970059 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970067 */     GIR_RootConstrainSelectedInstOperands,
     /*  970068 */     // GIR_Coverage, 8370,
     /*  970068 */     GIR_EraseRootFromParent_Done,
     /*  970069 */   // Label 15319: @970069
     /*  970069 */   GIM_Try, /*On fail goto*//*Label 15320*/ GIMT_Encode4(970176), // Rule ID 8371 //
     /*  970074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  970077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  970082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970085 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  970088 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  970091 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970094 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  970097 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  970100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970104 */     // MIs[0] matrix_a_fmt
     /*  970104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970107 */     // MIs[0] matrix_b_fmt
     /*  970107 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970110 */     // MIs[0] src2_modifiers
     /*  970110 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970113 */     // MIs[0] matrix_a_scale
     /*  970113 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970116 */     // MIs[0] matrix_a_scale_fmt
     /*  970116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970119 */     // MIs[0] matrix_b_scale
     /*  970119 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970122 */     // MIs[0] matrix_b_scale_fmt
     /*  970122 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970125 */     // MIs[0] matrix_a_reuse
     /*  970125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970128 */     // MIs[0] matrix_b_reuse
     /*  970128 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970131 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  970134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970136 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970138 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970140 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970146 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970148 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970150 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970152 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970154 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970156 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970158 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970160 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970162 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970164 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970166 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970171 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970174 */     GIR_RootConstrainSelectedInstOperands,
     /*  970175 */     // GIR_Coverage, 8371,
     /*  970175 */     GIR_EraseRootFromParent_Done,
     /*  970176 */   // Label 15320: @970176
     /*  970176 */   GIM_Try, /*On fail goto*//*Label 15321*/ GIMT_Encode4(970283), // Rule ID 8372 //
     /*  970181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  970184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  970189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970192 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s32,
     /*  970195 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  970198 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970201 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  970204 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  970207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970211 */     // MIs[0] matrix_a_fmt
     /*  970211 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970214 */     // MIs[0] matrix_b_fmt
     /*  970214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970217 */     // MIs[0] src2_modifiers
     /*  970217 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970220 */     // MIs[0] matrix_a_scale
     /*  970220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970223 */     // MIs[0] matrix_a_scale_fmt
     /*  970223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970226 */     // MIs[0] matrix_b_scale
     /*  970226 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970229 */     // MIs[0] matrix_b_scale_fmt
     /*  970229 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970232 */     // MIs[0] matrix_a_reuse
     /*  970232 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970235 */     // MIs[0] matrix_b_reuse
     /*  970235 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970238 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v16i32:{ *:[v16i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr:{ *:[v8f32] } v16i32:{ *:[v16i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr),
     /*  970241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970243 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970245 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970247 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970253 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970255 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970257 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970259 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970261 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970263 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970265 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970267 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970269 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970271 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970273 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970275 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970278 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970281 */     GIR_RootConstrainSelectedInstOperands,
     /*  970282 */     // GIR_Coverage, 8372,
     /*  970282 */     GIR_EraseRootFromParent_Done,
     /*  970283 */   // Label 15321: @970283
     /*  970283 */   GIM_Try, /*On fail goto*//*Label 15322*/ GIMT_Encode4(970390), // Rule ID 8388 //
     /*  970288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  970291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  970296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970299 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970302 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970305 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970308 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  970311 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  970314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970318 */     // MIs[0] matrix_a_fmt
     /*  970318 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970321 */     // MIs[0] matrix_b_fmt
     /*  970321 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970324 */     // MIs[0] src2_modifiers
     /*  970324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970327 */     // MIs[0] matrix_a_scale
     /*  970327 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970330 */     // MIs[0] matrix_a_scale_fmt
     /*  970330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970333 */     // MIs[0] matrix_b_scale
     /*  970333 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970336 */     // MIs[0] matrix_b_scale_fmt
     /*  970336 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970339 */     // MIs[0] matrix_a_reuse
     /*  970339 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970342 */     // MIs[0] matrix_b_reuse
     /*  970342 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970345 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970350 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970352 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970354 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970360 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970362 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970364 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970366 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970368 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970370 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970372 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970374 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970376 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970378 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970380 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970385 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970388 */     GIR_RootConstrainSelectedInstOperands,
     /*  970389 */     // GIR_Coverage, 8388,
     /*  970389 */     GIR_EraseRootFromParent_Done,
     /*  970390 */   // Label 15322: @970390
     /*  970390 */   GIM_Try, /*On fail goto*//*Label 15323*/ GIMT_Encode4(970497), // Rule ID 8389 //
     /*  970395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  970398 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  970403 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970409 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970412 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970415 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  970418 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  970421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970425 */     // MIs[0] matrix_a_fmt
     /*  970425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970428 */     // MIs[0] matrix_b_fmt
     /*  970428 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970431 */     // MIs[0] src2_modifiers
     /*  970431 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970434 */     // MIs[0] matrix_a_scale
     /*  970434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970437 */     // MIs[0] matrix_a_scale_fmt
     /*  970437 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970440 */     // MIs[0] matrix_b_scale
     /*  970440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970443 */     // MIs[0] matrix_b_scale_fmt
     /*  970443 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970446 */     // MIs[0] matrix_a_reuse
     /*  970446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970449 */     // MIs[0] matrix_b_reuse
     /*  970449 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970452 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970457 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970459 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970461 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970467 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970469 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970471 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970473 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970475 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970477 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970479 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970481 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970483 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970485 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970487 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970489 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970495 */     GIR_RootConstrainSelectedInstOperands,
     /*  970496 */     // GIR_Coverage, 8389,
     /*  970496 */     GIR_EraseRootFromParent_Done,
     /*  970497 */   // Label 15323: @970497
     /*  970497 */   GIM_Try, /*On fail goto*//*Label 15324*/ GIMT_Encode4(970604), // Rule ID 8390 //
     /*  970502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  970505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  970510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970513 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970516 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970519 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970522 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  970525 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  970528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970532 */     // MIs[0] matrix_a_fmt
     /*  970532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970535 */     // MIs[0] matrix_b_fmt
     /*  970535 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970538 */     // MIs[0] src2_modifiers
     /*  970538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970541 */     // MIs[0] matrix_a_scale
     /*  970541 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970544 */     // MIs[0] matrix_a_scale_fmt
     /*  970544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970547 */     // MIs[0] matrix_b_scale
     /*  970547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970550 */     // MIs[0] matrix_b_scale_fmt
     /*  970550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970553 */     // MIs[0] matrix_a_reuse
     /*  970553 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970556 */     // MIs[0] matrix_b_reuse
     /*  970556 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970559 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970564 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970566 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970568 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970574 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970576 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970578 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970580 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970582 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970584 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970586 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970588 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970590 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970592 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970594 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970602 */     GIR_RootConstrainSelectedInstOperands,
     /*  970603 */     // GIR_Coverage, 8390,
     /*  970603 */     GIR_EraseRootFromParent_Done,
     /*  970604 */   // Label 15324: @970604
     /*  970604 */   GIM_Try, /*On fail goto*//*Label 15325*/ GIMT_Encode4(970711), // Rule ID 8391 //
     /*  970609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  970612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  970617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970620 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970623 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970626 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970629 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  970632 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  970635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970639 */     // MIs[0] matrix_a_fmt
     /*  970639 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970642 */     // MIs[0] matrix_b_fmt
     /*  970642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970645 */     // MIs[0] src2_modifiers
     /*  970645 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970648 */     // MIs[0] matrix_a_scale
     /*  970648 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970651 */     // MIs[0] matrix_a_scale_fmt
     /*  970651 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970654 */     // MIs[0] matrix_b_scale
     /*  970654 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970657 */     // MIs[0] matrix_b_scale_fmt
     /*  970657 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970660 */     // MIs[0] matrix_a_reuse
     /*  970660 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970663 */     // MIs[0] matrix_b_reuse
     /*  970663 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970666 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970671 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970673 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970675 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970681 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970683 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970685 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970687 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970689 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970691 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970693 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970695 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970697 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970699 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970701 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970709 */     GIR_RootConstrainSelectedInstOperands,
     /*  970710 */     // GIR_Coverage, 8391,
     /*  970710 */     GIR_EraseRootFromParent_Done,
     /*  970711 */   // Label 15325: @970711
     /*  970711 */   GIM_Try, /*On fail goto*//*Label 15326*/ GIMT_Encode4(970818), // Rule ID 8392 //
     /*  970716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  970719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  970724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970730 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970733 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970736 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  970739 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  970742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970746 */     // MIs[0] matrix_a_fmt
     /*  970746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970749 */     // MIs[0] matrix_b_fmt
     /*  970749 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970752 */     // MIs[0] src2_modifiers
     /*  970752 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970755 */     // MIs[0] matrix_a_scale
     /*  970755 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970758 */     // MIs[0] matrix_a_scale_fmt
     /*  970758 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970761 */     // MIs[0] matrix_b_scale
     /*  970761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970764 */     // MIs[0] matrix_b_scale_fmt
     /*  970764 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970767 */     // MIs[0] matrix_a_reuse
     /*  970767 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970770 */     // MIs[0] matrix_b_reuse
     /*  970770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970773 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970778 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970780 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970782 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970788 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970790 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970792 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970794 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970796 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970798 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970800 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970802 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970804 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970806 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970808 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970810 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970813 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970816 */     GIR_RootConstrainSelectedInstOperands,
     /*  970817 */     // GIR_Coverage, 8392,
     /*  970817 */     GIR_EraseRootFromParent_Done,
     /*  970818 */   // Label 15326: @970818
     /*  970818 */   GIM_Try, /*On fail goto*//*Label 15327*/ GIMT_Encode4(970925), // Rule ID 8398 //
     /*  970823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  970826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  970831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970837 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970840 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970843 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  970846 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  970849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970853 */     // MIs[0] matrix_a_fmt
     /*  970853 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970856 */     // MIs[0] matrix_b_fmt
     /*  970856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970859 */     // MIs[0] src2_modifiers
     /*  970859 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970862 */     // MIs[0] matrix_a_scale
     /*  970862 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970865 */     // MIs[0] matrix_a_scale_fmt
     /*  970865 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970868 */     // MIs[0] matrix_b_scale
     /*  970868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970871 */     // MIs[0] matrix_b_scale_fmt
     /*  970871 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970874 */     // MIs[0] matrix_a_reuse
     /*  970874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970877 */     // MIs[0] matrix_b_reuse
     /*  970877 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970880 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970885 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970887 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970889 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  970895 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  970897 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  970899 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  970901 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  970903 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  970905 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  970907 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  970909 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  970911 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  970913 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  970915 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  970917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  970923 */     GIR_RootConstrainSelectedInstOperands,
     /*  970924 */     // GIR_Coverage, 8398,
     /*  970924 */     GIR_EraseRootFromParent_Done,
     /*  970925 */   // Label 15327: @970925
     /*  970925 */   GIM_Try, /*On fail goto*//*Label 15328*/ GIMT_Encode4(971032), // Rule ID 8399 //
     /*  970930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  970933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  970938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  970941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  970944 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  970947 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  970950 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  970953 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  970956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  970960 */     // MIs[0] matrix_a_fmt
     /*  970960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  970963 */     // MIs[0] matrix_b_fmt
     /*  970963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  970966 */     // MIs[0] src2_modifiers
     /*  970966 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  970969 */     // MIs[0] matrix_a_scale
     /*  970969 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  970972 */     // MIs[0] matrix_a_scale_fmt
     /*  970972 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  970975 */     // MIs[0] matrix_b_scale
     /*  970975 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  970978 */     // MIs[0] matrix_b_scale_fmt
     /*  970978 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  970981 */     // MIs[0] matrix_a_reuse
     /*  970981 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  970984 */     // MIs[0] matrix_b_reuse
     /*  970984 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  970987 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  970987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  970990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  970992 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  970994 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  970996 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971002 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971004 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971006 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971008 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971010 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971012 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971014 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971016 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971018 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971020 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971022 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971027 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971030 */     GIR_RootConstrainSelectedInstOperands,
     /*  971031 */     // GIR_Coverage, 8399,
     /*  971031 */     GIR_EraseRootFromParent_Done,
     /*  971032 */   // Label 15328: @971032
     /*  971032 */   GIM_Try, /*On fail goto*//*Label 15329*/ GIMT_Encode4(971139), // Rule ID 8400 //
     /*  971037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  971040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  971045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971051 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  971054 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971057 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  971060 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  971063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971067 */     // MIs[0] matrix_a_fmt
     /*  971067 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971070 */     // MIs[0] matrix_b_fmt
     /*  971070 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971073 */     // MIs[0] src2_modifiers
     /*  971073 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971076 */     // MIs[0] matrix_a_scale
     /*  971076 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971079 */     // MIs[0] matrix_a_scale_fmt
     /*  971079 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971082 */     // MIs[0] matrix_b_scale
     /*  971082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971085 */     // MIs[0] matrix_b_scale_fmt
     /*  971085 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971088 */     // MIs[0] matrix_a_reuse
     /*  971088 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971091 */     // MIs[0] matrix_b_reuse
     /*  971091 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971094 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  971097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971099 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971101 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971103 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971109 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971111 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971113 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971115 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971117 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971119 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971121 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971123 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971125 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971127 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971129 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971137 */     GIR_RootConstrainSelectedInstOperands,
     /*  971138 */     // GIR_Coverage, 8400,
     /*  971138 */     GIR_EraseRootFromParent_Done,
     /*  971139 */   // Label 15329: @971139
     /*  971139 */   GIM_Try, /*On fail goto*//*Label 15330*/ GIMT_Encode4(971246), // Rule ID 8401 //
     /*  971144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  971147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  971152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971155 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971158 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  971161 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971164 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  971167 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  971170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971174 */     // MIs[0] matrix_a_fmt
     /*  971174 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971177 */     // MIs[0] matrix_b_fmt
     /*  971177 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971180 */     // MIs[0] src2_modifiers
     /*  971180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971183 */     // MIs[0] matrix_a_scale
     /*  971183 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971186 */     // MIs[0] matrix_a_scale_fmt
     /*  971186 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971189 */     // MIs[0] matrix_b_scale
     /*  971189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971192 */     // MIs[0] matrix_b_scale_fmt
     /*  971192 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971195 */     // MIs[0] matrix_a_reuse
     /*  971195 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971198 */     // MIs[0] matrix_b_reuse
     /*  971198 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971201 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  971204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971206 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971208 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971210 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971216 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971218 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971220 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971222 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971224 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971226 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971228 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971230 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971232 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971234 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971236 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971238 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971244 */     GIR_RootConstrainSelectedInstOperands,
     /*  971245 */     // GIR_Coverage, 8401,
     /*  971245 */     GIR_EraseRootFromParent_Done,
     /*  971246 */   // Label 15330: @971246
     /*  971246 */   GIM_Try, /*On fail goto*//*Label 15331*/ GIMT_Encode4(971353), // Rule ID 8402 //
     /*  971251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  971254 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  971259 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971265 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  971268 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971271 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  971274 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  971277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971281 */     // MIs[0] matrix_a_fmt
     /*  971281 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971284 */     // MIs[0] matrix_b_fmt
     /*  971284 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971287 */     // MIs[0] src2_modifiers
     /*  971287 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971290 */     // MIs[0] matrix_a_scale
     /*  971290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971293 */     // MIs[0] matrix_a_scale_fmt
     /*  971293 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971296 */     // MIs[0] matrix_b_scale
     /*  971296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971299 */     // MIs[0] matrix_b_scale_fmt
     /*  971299 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971302 */     // MIs[0] matrix_a_reuse
     /*  971302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971305 */     // MIs[0] matrix_b_reuse
     /*  971305 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971308 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr),
     /*  971311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971313 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971315 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971317 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971323 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971325 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971327 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971329 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971331 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971333 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971335 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971337 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971339 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971341 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971343 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971351 */     GIR_RootConstrainSelectedInstOperands,
     /*  971352 */     // GIR_Coverage, 8402,
     /*  971352 */     GIR_EraseRootFromParent_Done,
     /*  971353 */   // Label 15331: @971353
     /*  971353 */   GIM_Try, /*On fail goto*//*Label 15332*/ GIMT_Encode4(971460), // Rule ID 8418 //
     /*  971358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  971361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  971366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971369 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971372 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  971375 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971378 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  971381 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  971384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971388 */     // MIs[0] matrix_a_fmt
     /*  971388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971391 */     // MIs[0] matrix_b_fmt
     /*  971391 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971394 */     // MIs[0] src2_modifiers
     /*  971394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971397 */     // MIs[0] matrix_a_scale
     /*  971397 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971400 */     // MIs[0] matrix_a_scale_fmt
     /*  971400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971403 */     // MIs[0] matrix_b_scale
     /*  971403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971406 */     // MIs[0] matrix_b_scale_fmt
     /*  971406 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971409 */     // MIs[0] matrix_a_reuse
     /*  971409 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971412 */     // MIs[0] matrix_b_reuse
     /*  971412 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971415 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  971418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971420 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971422 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971424 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971430 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971432 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971434 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971436 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971438 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971440 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971442 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971444 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971446 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971448 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971450 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971455 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971458 */     GIR_RootConstrainSelectedInstOperands,
     /*  971459 */     // GIR_Coverage, 8418,
     /*  971459 */     GIR_EraseRootFromParent_Done,
     /*  971460 */   // Label 15332: @971460
     /*  971460 */   GIM_Try, /*On fail goto*//*Label 15333*/ GIMT_Encode4(971567), // Rule ID 8419 //
     /*  971465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  971468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  971473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971479 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  971482 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971485 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  971488 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  971491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971495 */     // MIs[0] matrix_a_fmt
     /*  971495 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971498 */     // MIs[0] matrix_b_fmt
     /*  971498 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971501 */     // MIs[0] src2_modifiers
     /*  971501 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971504 */     // MIs[0] matrix_a_scale
     /*  971504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971507 */     // MIs[0] matrix_a_scale_fmt
     /*  971507 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971510 */     // MIs[0] matrix_b_scale
     /*  971510 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971513 */     // MIs[0] matrix_b_scale_fmt
     /*  971513 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971516 */     // MIs[0] matrix_a_reuse
     /*  971516 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971519 */     // MIs[0] matrix_b_reuse
     /*  971519 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971522 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  971525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971527 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971529 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971531 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971537 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971539 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971541 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971543 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971545 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971547 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971549 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971551 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971553 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971555 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971557 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971565 */     GIR_RootConstrainSelectedInstOperands,
     /*  971566 */     // GIR_Coverage, 8419,
     /*  971566 */     GIR_EraseRootFromParent_Done,
     /*  971567 */   // Label 15333: @971567
     /*  971567 */   GIM_Try, /*On fail goto*//*Label 15334*/ GIMT_Encode4(971674), // Rule ID 8420 //
     /*  971572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  971575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  971580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971586 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  971589 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971592 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  971595 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  971598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971602 */     // MIs[0] matrix_a_fmt
     /*  971602 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971605 */     // MIs[0] matrix_b_fmt
     /*  971605 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971608 */     // MIs[0] src2_modifiers
     /*  971608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971611 */     // MIs[0] matrix_a_scale
     /*  971611 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971614 */     // MIs[0] matrix_a_scale_fmt
     /*  971614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971617 */     // MIs[0] matrix_b_scale
     /*  971617 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971620 */     // MIs[0] matrix_b_scale_fmt
     /*  971620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971623 */     // MIs[0] matrix_a_reuse
     /*  971623 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971626 */     // MIs[0] matrix_b_reuse
     /*  971626 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971629 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  971632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971634 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971636 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971638 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971644 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971646 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971648 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971650 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971652 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971654 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971656 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971658 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971660 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971662 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971664 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971672 */     GIR_RootConstrainSelectedInstOperands,
     /*  971673 */     // GIR_Coverage, 8420,
     /*  971673 */     GIR_EraseRootFromParent_Done,
     /*  971674 */   // Label 15334: @971674
     /*  971674 */   GIM_Try, /*On fail goto*//*Label 15335*/ GIMT_Encode4(971781), // Rule ID 8421 //
     /*  971679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  971682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  971687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971690 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971693 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  971696 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971699 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  971702 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  971705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971709 */     // MIs[0] matrix_a_fmt
     /*  971709 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971712 */     // MIs[0] matrix_b_fmt
     /*  971712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971715 */     // MIs[0] src2_modifiers
     /*  971715 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971718 */     // MIs[0] matrix_a_scale
     /*  971718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971721 */     // MIs[0] matrix_a_scale_fmt
     /*  971721 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971724 */     // MIs[0] matrix_b_scale
     /*  971724 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971727 */     // MIs[0] matrix_b_scale_fmt
     /*  971727 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971730 */     // MIs[0] matrix_a_reuse
     /*  971730 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971733 */     // MIs[0] matrix_b_reuse
     /*  971733 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971736 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  971739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971741 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971743 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971745 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971751 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971753 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971755 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971757 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971759 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971761 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971763 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971765 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971767 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971769 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971771 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971779 */     GIR_RootConstrainSelectedInstOperands,
     /*  971780 */     // GIR_Coverage, 8421,
     /*  971780 */     GIR_EraseRootFromParent_Done,
     /*  971781 */   // Label 15335: @971781
     /*  971781 */   GIM_Try, /*On fail goto*//*Label 15336*/ GIMT_Encode4(971888), // Rule ID 8422 //
     /*  971786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  971789 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  971794 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971800 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  971803 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971806 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  971809 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  971812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971816 */     // MIs[0] matrix_a_fmt
     /*  971816 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971819 */     // MIs[0] matrix_b_fmt
     /*  971819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971822 */     // MIs[0] src2_modifiers
     /*  971822 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971825 */     // MIs[0] matrix_a_scale
     /*  971825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971828 */     // MIs[0] matrix_a_scale_fmt
     /*  971828 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971831 */     // MIs[0] matrix_b_scale
     /*  971831 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971834 */     // MIs[0] matrix_b_scale_fmt
     /*  971834 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971837 */     // MIs[0] matrix_a_reuse
     /*  971837 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971840 */     // MIs[0] matrix_b_reuse
     /*  971840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971843 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  971846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971848 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971850 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971852 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971858 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971860 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971862 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971864 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971866 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971868 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971870 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971872 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971874 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971876 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971878 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971886 */     GIR_RootConstrainSelectedInstOperands,
     /*  971887 */     // GIR_Coverage, 8422,
     /*  971887 */     GIR_EraseRootFromParent_Done,
     /*  971888 */   // Label 15336: @971888
     /*  971888 */   GIM_Try, /*On fail goto*//*Label 15337*/ GIMT_Encode4(971995), // Rule ID 8428 //
     /*  971893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  971896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  971901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  971904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  971907 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  971910 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  971913 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  971916 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  971919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  971923 */     // MIs[0] matrix_a_fmt
     /*  971923 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  971926 */     // MIs[0] matrix_b_fmt
     /*  971926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  971929 */     // MIs[0] src2_modifiers
     /*  971929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  971932 */     // MIs[0] matrix_a_scale
     /*  971932 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  971935 */     // MIs[0] matrix_a_scale_fmt
     /*  971935 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  971938 */     // MIs[0] matrix_b_scale
     /*  971938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  971941 */     // MIs[0] matrix_b_scale_fmt
     /*  971941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  971944 */     // MIs[0] matrix_a_reuse
     /*  971944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  971947 */     // MIs[0] matrix_b_reuse
     /*  971947 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  971950 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  971950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  971953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  971955 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  971957 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  971959 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  971965 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  971967 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  971969 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  971971 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  971973 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  971975 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  971977 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  971979 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  971981 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  971983 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  971985 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  971987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  971993 */     GIR_RootConstrainSelectedInstOperands,
     /*  971994 */     // GIR_Coverage, 8428,
     /*  971994 */     GIR_EraseRootFromParent_Done,
     /*  971995 */   // Label 15337: @971995
     /*  971995 */   GIM_Try, /*On fail goto*//*Label 15338*/ GIMT_Encode4(972102), // Rule ID 8429 //
     /*  972000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  972003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  972008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972014 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  972017 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972020 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  972023 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  972026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972030 */     // MIs[0] matrix_a_fmt
     /*  972030 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972033 */     // MIs[0] matrix_b_fmt
     /*  972033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972036 */     // MIs[0] src2_modifiers
     /*  972036 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972039 */     // MIs[0] matrix_a_scale
     /*  972039 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972042 */     // MIs[0] matrix_a_scale_fmt
     /*  972042 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972045 */     // MIs[0] matrix_b_scale
     /*  972045 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972048 */     // MIs[0] matrix_b_scale_fmt
     /*  972048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972051 */     // MIs[0] matrix_a_reuse
     /*  972051 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972054 */     // MIs[0] matrix_b_reuse
     /*  972054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972057 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  972060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972062 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972064 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972066 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972072 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972074 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972076 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972078 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972080 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972082 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972084 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972086 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972088 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972090 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972092 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972094 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972100 */     GIR_RootConstrainSelectedInstOperands,
     /*  972101 */     // GIR_Coverage, 8429,
     /*  972101 */     GIR_EraseRootFromParent_Done,
     /*  972102 */   // Label 15338: @972102
     /*  972102 */   GIM_Try, /*On fail goto*//*Label 15339*/ GIMT_Encode4(972209), // Rule ID 8430 //
     /*  972107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  972110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  972115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972121 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  972124 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972127 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  972130 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  972133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972137 */     // MIs[0] matrix_a_fmt
     /*  972137 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972140 */     // MIs[0] matrix_b_fmt
     /*  972140 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972143 */     // MIs[0] src2_modifiers
     /*  972143 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972146 */     // MIs[0] matrix_a_scale
     /*  972146 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972149 */     // MIs[0] matrix_a_scale_fmt
     /*  972149 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972152 */     // MIs[0] matrix_b_scale
     /*  972152 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972155 */     // MIs[0] matrix_b_scale_fmt
     /*  972155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972158 */     // MIs[0] matrix_a_reuse
     /*  972158 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972161 */     // MIs[0] matrix_b_reuse
     /*  972161 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972164 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  972167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972169 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972171 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972173 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972179 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972181 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972183 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972185 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972187 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972189 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972191 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972193 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972195 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972197 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972199 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972201 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972207 */     GIR_RootConstrainSelectedInstOperands,
     /*  972208 */     // GIR_Coverage, 8430,
     /*  972208 */     GIR_EraseRootFromParent_Done,
     /*  972209 */   // Label 15339: @972209
     /*  972209 */   GIM_Try, /*On fail goto*//*Label 15340*/ GIMT_Encode4(972316), // Rule ID 8431 //
     /*  972214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  972217 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  972222 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972228 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  972231 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972234 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  972237 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  972240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972244 */     // MIs[0] matrix_a_fmt
     /*  972244 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972247 */     // MIs[0] matrix_b_fmt
     /*  972247 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972250 */     // MIs[0] src2_modifiers
     /*  972250 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972253 */     // MIs[0] matrix_a_scale
     /*  972253 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972256 */     // MIs[0] matrix_a_scale_fmt
     /*  972256 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972259 */     // MIs[0] matrix_b_scale
     /*  972259 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972262 */     // MIs[0] matrix_b_scale_fmt
     /*  972262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972265 */     // MIs[0] matrix_a_reuse
     /*  972265 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972268 */     // MIs[0] matrix_b_reuse
     /*  972268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972271 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  972274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972276 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972278 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972280 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972286 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972288 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972290 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972292 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972294 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972296 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972298 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972300 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972302 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972304 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972306 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972314 */     GIR_RootConstrainSelectedInstOperands,
     /*  972315 */     // GIR_Coverage, 8431,
     /*  972315 */     GIR_EraseRootFromParent_Done,
     /*  972316 */   // Label 15340: @972316
     /*  972316 */   GIM_Try, /*On fail goto*//*Label 15341*/ GIMT_Encode4(972423), // Rule ID 8432 //
     /*  972321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  972324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  972329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972335 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  972338 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972341 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  972344 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  972347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972351 */     // MIs[0] matrix_a_fmt
     /*  972351 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972354 */     // MIs[0] matrix_b_fmt
     /*  972354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972357 */     // MIs[0] src2_modifiers
     /*  972357 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972360 */     // MIs[0] matrix_a_scale
     /*  972360 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972363 */     // MIs[0] matrix_a_scale_fmt
     /*  972363 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972366 */     // MIs[0] matrix_b_scale
     /*  972366 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972369 */     // MIs[0] matrix_b_scale_fmt
     /*  972369 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972372 */     // MIs[0] matrix_a_reuse
     /*  972372 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972375 */     // MIs[0] matrix_b_reuse
     /*  972375 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972378 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr),
     /*  972381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972383 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972385 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972387 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972393 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972395 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972397 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972399 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972401 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972403 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972405 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972407 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972409 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972411 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972413 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972415 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972421 */     GIR_RootConstrainSelectedInstOperands,
     /*  972422 */     // GIR_Coverage, 8432,
     /*  972422 */     GIR_EraseRootFromParent_Done,
     /*  972423 */   // Label 15341: @972423
     /*  972423 */   GIM_Try, /*On fail goto*//*Label 15342*/ GIMT_Encode4(972530), // Rule ID 8448 //
     /*  972428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  972431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  972436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972442 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  972445 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972448 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  972451 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  972454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972458 */     // MIs[0] matrix_a_fmt
     /*  972458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972461 */     // MIs[0] matrix_b_fmt
     /*  972461 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972464 */     // MIs[0] src2_modifiers
     /*  972464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972467 */     // MIs[0] matrix_a_scale
     /*  972467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972470 */     // MIs[0] matrix_a_scale_fmt
     /*  972470 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972473 */     // MIs[0] matrix_b_scale
     /*  972473 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972476 */     // MIs[0] matrix_b_scale_fmt
     /*  972476 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972479 */     // MIs[0] matrix_a_reuse
     /*  972479 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972482 */     // MIs[0] matrix_b_reuse
     /*  972482 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972485 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  972488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972490 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972492 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972494 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972500 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972502 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972504 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972506 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972508 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972510 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972512 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972514 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972516 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972518 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972520 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972528 */     GIR_RootConstrainSelectedInstOperands,
     /*  972529 */     // GIR_Coverage, 8448,
     /*  972529 */     GIR_EraseRootFromParent_Done,
     /*  972530 */   // Label 15342: @972530
     /*  972530 */   GIM_Try, /*On fail goto*//*Label 15343*/ GIMT_Encode4(972637), // Rule ID 8449 //
     /*  972535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  972538 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  972543 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972549 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  972552 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972555 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  972558 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  972561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972565 */     // MIs[0] matrix_a_fmt
     /*  972565 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972568 */     // MIs[0] matrix_b_fmt
     /*  972568 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972571 */     // MIs[0] src2_modifiers
     /*  972571 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972574 */     // MIs[0] matrix_a_scale
     /*  972574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972577 */     // MIs[0] matrix_a_scale_fmt
     /*  972577 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972580 */     // MIs[0] matrix_b_scale
     /*  972580 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972583 */     // MIs[0] matrix_b_scale_fmt
     /*  972583 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972586 */     // MIs[0] matrix_a_reuse
     /*  972586 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972589 */     // MIs[0] matrix_b_reuse
     /*  972589 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972592 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  972595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972597 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972599 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972601 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972607 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972609 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972611 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972613 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972615 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972617 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972619 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972621 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972623 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972625 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972627 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972629 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972632 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972635 */     GIR_RootConstrainSelectedInstOperands,
     /*  972636 */     // GIR_Coverage, 8449,
     /*  972636 */     GIR_EraseRootFromParent_Done,
     /*  972637 */   // Label 15343: @972637
     /*  972637 */   GIM_Try, /*On fail goto*//*Label 15344*/ GIMT_Encode4(972744), // Rule ID 8450 //
     /*  972642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  972645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  972650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972656 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  972659 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972662 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  972665 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  972668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972672 */     // MIs[0] matrix_a_fmt
     /*  972672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972675 */     // MIs[0] matrix_b_fmt
     /*  972675 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972678 */     // MIs[0] src2_modifiers
     /*  972678 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972681 */     // MIs[0] matrix_a_scale
     /*  972681 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972684 */     // MIs[0] matrix_a_scale_fmt
     /*  972684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972687 */     // MIs[0] matrix_b_scale
     /*  972687 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972690 */     // MIs[0] matrix_b_scale_fmt
     /*  972690 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972693 */     // MIs[0] matrix_a_reuse
     /*  972693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972696 */     // MIs[0] matrix_b_reuse
     /*  972696 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972699 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  972702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972704 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972706 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972708 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972714 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972716 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972718 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972720 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972722 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972724 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972726 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972728 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972730 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972732 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972734 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972739 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972742 */     GIR_RootConstrainSelectedInstOperands,
     /*  972743 */     // GIR_Coverage, 8450,
     /*  972743 */     GIR_EraseRootFromParent_Done,
     /*  972744 */   // Label 15344: @972744
     /*  972744 */   GIM_Try, /*On fail goto*//*Label 15345*/ GIMT_Encode4(972851), // Rule ID 8451 //
     /*  972749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  972752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  972757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972760 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972763 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  972766 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972769 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  972772 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  972775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972779 */     // MIs[0] matrix_a_fmt
     /*  972779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972782 */     // MIs[0] matrix_b_fmt
     /*  972782 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972785 */     // MIs[0] src2_modifiers
     /*  972785 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972788 */     // MIs[0] matrix_a_scale
     /*  972788 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972791 */     // MIs[0] matrix_a_scale_fmt
     /*  972791 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972794 */     // MIs[0] matrix_b_scale
     /*  972794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972797 */     // MIs[0] matrix_b_scale_fmt
     /*  972797 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972800 */     // MIs[0] matrix_a_reuse
     /*  972800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972803 */     // MIs[0] matrix_b_reuse
     /*  972803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972806 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  972809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972811 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972813 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972815 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972821 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972823 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972825 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972827 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972829 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972831 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972833 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972835 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972837 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972839 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972841 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972849 */     GIR_RootConstrainSelectedInstOperands,
     /*  972850 */     // GIR_Coverage, 8451,
     /*  972850 */     GIR_EraseRootFromParent_Done,
     /*  972851 */   // Label 15345: @972851
     /*  972851 */   GIM_Try, /*On fail goto*//*Label 15346*/ GIMT_Encode4(972958), // Rule ID 8452 //
     /*  972856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  972859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  972864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972870 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  972873 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972876 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  972879 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  972882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972886 */     // MIs[0] matrix_a_fmt
     /*  972886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972889 */     // MIs[0] matrix_b_fmt
     /*  972889 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972892 */     // MIs[0] src2_modifiers
     /*  972892 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  972895 */     // MIs[0] matrix_a_scale
     /*  972895 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  972898 */     // MIs[0] matrix_a_scale_fmt
     /*  972898 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  972901 */     // MIs[0] matrix_b_scale
     /*  972901 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  972904 */     // MIs[0] matrix_b_scale_fmt
     /*  972904 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  972907 */     // MIs[0] matrix_a_reuse
     /*  972907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  972910 */     // MIs[0] matrix_b_reuse
     /*  972910 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  972913 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  972913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  972916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  972918 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  972920 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  972922 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  972928 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  972930 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  972932 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  972934 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  972936 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  972938 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  972940 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  972942 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  972944 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  972946 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  972948 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  972950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  972956 */     GIR_RootConstrainSelectedInstOperands,
     /*  972957 */     // GIR_Coverage, 8452,
     /*  972957 */     GIR_EraseRootFromParent_Done,
     /*  972958 */   // Label 15346: @972958
     /*  972958 */   GIM_Try, /*On fail goto*//*Label 15347*/ GIMT_Encode4(973065), // Rule ID 8458 //
     /*  972963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  972966 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  972971 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  972974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  972977 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  972980 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  972983 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  972986 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  972989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  972993 */     // MIs[0] matrix_a_fmt
     /*  972993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  972996 */     // MIs[0] matrix_b_fmt
     /*  972996 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  972999 */     // MIs[0] src2_modifiers
     /*  972999 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973002 */     // MIs[0] matrix_a_scale
     /*  973002 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973005 */     // MIs[0] matrix_a_scale_fmt
     /*  973005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973008 */     // MIs[0] matrix_b_scale
     /*  973008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973011 */     // MIs[0] matrix_b_scale_fmt
     /*  973011 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973014 */     // MIs[0] matrix_a_reuse
     /*  973014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973017 */     // MIs[0] matrix_b_reuse
     /*  973017 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973020 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  973023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973025 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973027 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973029 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973035 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973037 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973039 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973041 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973043 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973045 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973047 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973049 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973051 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973053 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973055 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973063 */     GIR_RootConstrainSelectedInstOperands,
     /*  973064 */     // GIR_Coverage, 8458,
     /*  973064 */     GIR_EraseRootFromParent_Done,
     /*  973065 */   // Label 15347: @973065
     /*  973065 */   GIM_Try, /*On fail goto*//*Label 15348*/ GIMT_Encode4(973172), // Rule ID 8459 //
     /*  973070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  973073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  973078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973081 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  973084 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  973087 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973090 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  973093 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  973096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973100 */     // MIs[0] matrix_a_fmt
     /*  973100 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973103 */     // MIs[0] matrix_b_fmt
     /*  973103 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973106 */     // MIs[0] src2_modifiers
     /*  973106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973109 */     // MIs[0] matrix_a_scale
     /*  973109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973112 */     // MIs[0] matrix_a_scale_fmt
     /*  973112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973115 */     // MIs[0] matrix_b_scale
     /*  973115 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973118 */     // MIs[0] matrix_b_scale_fmt
     /*  973118 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973121 */     // MIs[0] matrix_a_reuse
     /*  973121 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973124 */     // MIs[0] matrix_b_reuse
     /*  973124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973127 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  973130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973132 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973134 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973136 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973142 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973144 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973146 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973148 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973150 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973152 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973154 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973156 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973158 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973160 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973162 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973167 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973170 */     GIR_RootConstrainSelectedInstOperands,
     /*  973171 */     // GIR_Coverage, 8459,
     /*  973171 */     GIR_EraseRootFromParent_Done,
     /*  973172 */   // Label 15348: @973172
     /*  973172 */   GIM_Try, /*On fail goto*//*Label 15349*/ GIMT_Encode4(973279), // Rule ID 8460 //
     /*  973177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  973180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  973185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  973191 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  973194 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973197 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  973200 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  973203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973207 */     // MIs[0] matrix_a_fmt
     /*  973207 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973210 */     // MIs[0] matrix_b_fmt
     /*  973210 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973213 */     // MIs[0] src2_modifiers
     /*  973213 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973216 */     // MIs[0] matrix_a_scale
     /*  973216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973219 */     // MIs[0] matrix_a_scale_fmt
     /*  973219 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973222 */     // MIs[0] matrix_b_scale
     /*  973222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973225 */     // MIs[0] matrix_b_scale_fmt
     /*  973225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973228 */     // MIs[0] matrix_a_reuse
     /*  973228 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973231 */     // MIs[0] matrix_b_reuse
     /*  973231 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973234 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  973237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973239 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973241 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973243 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973249 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973251 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973253 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973255 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973257 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973259 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973261 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973263 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973265 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973267 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973269 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973271 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973277 */     GIR_RootConstrainSelectedInstOperands,
     /*  973278 */     // GIR_Coverage, 8460,
     /*  973278 */     GIR_EraseRootFromParent_Done,
     /*  973279 */   // Label 15349: @973279
     /*  973279 */   GIM_Try, /*On fail goto*//*Label 15350*/ GIMT_Encode4(973386), // Rule ID 8461 //
     /*  973284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  973287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  973292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  973298 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  973301 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973304 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  973307 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  973310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973314 */     // MIs[0] matrix_a_fmt
     /*  973314 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973317 */     // MIs[0] matrix_b_fmt
     /*  973317 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973320 */     // MIs[0] src2_modifiers
     /*  973320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973323 */     // MIs[0] matrix_a_scale
     /*  973323 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973326 */     // MIs[0] matrix_a_scale_fmt
     /*  973326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973329 */     // MIs[0] matrix_b_scale
     /*  973329 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973332 */     // MIs[0] matrix_b_scale_fmt
     /*  973332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973335 */     // MIs[0] matrix_a_reuse
     /*  973335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973338 */     // MIs[0] matrix_b_reuse
     /*  973338 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973341 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  973344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973346 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973348 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973350 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973356 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973358 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973360 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973362 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973364 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973366 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973368 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973370 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973372 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973374 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973376 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973378 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973381 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973384 */     GIR_RootConstrainSelectedInstOperands,
     /*  973385 */     // GIR_Coverage, 8461,
     /*  973385 */     GIR_EraseRootFromParent_Done,
     /*  973386 */   // Label 15350: @973386
     /*  973386 */   GIM_Try, /*On fail goto*//*Label 15351*/ GIMT_Encode4(973493), // Rule ID 8462 //
     /*  973391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  973394 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  973399 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v12s32,
     /*  973405 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  973408 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973411 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  973414 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  973417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973421 */     // MIs[0] matrix_a_fmt
     /*  973421 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973424 */     // MIs[0] matrix_b_fmt
     /*  973424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973427 */     // MIs[0] src2_modifiers
     /*  973427 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973430 */     // MIs[0] matrix_a_scale
     /*  973430 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973433 */     // MIs[0] matrix_a_scale_fmt
     /*  973433 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973436 */     // MIs[0] matrix_b_scale
     /*  973436 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973439 */     // MIs[0] matrix_b_scale_fmt
     /*  973439 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973442 */     // MIs[0] matrix_a_reuse
     /*  973442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973445 */     // MIs[0] matrix_b_reuse
     /*  973445 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973448 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v12i32:{ *:[v12i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr:{ *:[v8f32] } v12i32:{ *:[v12i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr),
     /*  973451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973453 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973455 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973457 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973463 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973465 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973467 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973469 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973471 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973473 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973475 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973477 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973479 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973481 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973483 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973488 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973491 */     GIR_RootConstrainSelectedInstOperands,
     /*  973492 */     // GIR_Coverage, 8462,
     /*  973492 */     GIR_EraseRootFromParent_Done,
     /*  973493 */   // Label 15351: @973493
     /*  973493 */   GIM_Try, /*On fail goto*//*Label 15352*/ GIMT_Encode4(973600), // Rule ID 8478 //
     /*  973498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  973501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  973506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973509 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  973512 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  973515 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973518 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  973521 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  973524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973528 */     // MIs[0] matrix_a_fmt
     /*  973528 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973531 */     // MIs[0] matrix_b_fmt
     /*  973531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973534 */     // MIs[0] src2_modifiers
     /*  973534 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973537 */     // MIs[0] matrix_a_scale
     /*  973537 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973540 */     // MIs[0] matrix_a_scale_fmt
     /*  973540 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973543 */     // MIs[0] matrix_b_scale
     /*  973543 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973546 */     // MIs[0] matrix_b_scale_fmt
     /*  973546 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973549 */     // MIs[0] matrix_a_reuse
     /*  973549 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973552 */     // MIs[0] matrix_b_reuse
     /*  973552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973555 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  973558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973560 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973562 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973564 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973570 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973572 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973574 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973576 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973578 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973580 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973582 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973584 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973586 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973588 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973590 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973598 */     GIR_RootConstrainSelectedInstOperands,
     /*  973599 */     // GIR_Coverage, 8478,
     /*  973599 */     GIR_EraseRootFromParent_Done,
     /*  973600 */   // Label 15352: @973600
     /*  973600 */   GIM_Try, /*On fail goto*//*Label 15353*/ GIMT_Encode4(973707), // Rule ID 8479 //
     /*  973605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  973608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  973613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973616 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  973619 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  973622 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973625 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  973628 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  973631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973635 */     // MIs[0] matrix_a_fmt
     /*  973635 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973638 */     // MIs[0] matrix_b_fmt
     /*  973638 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973641 */     // MIs[0] src2_modifiers
     /*  973641 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973644 */     // MIs[0] matrix_a_scale
     /*  973644 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973647 */     // MIs[0] matrix_a_scale_fmt
     /*  973647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973650 */     // MIs[0] matrix_b_scale
     /*  973650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973653 */     // MIs[0] matrix_b_scale_fmt
     /*  973653 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973656 */     // MIs[0] matrix_a_reuse
     /*  973656 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973659 */     // MIs[0] matrix_b_reuse
     /*  973659 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973662 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  973665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973667 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973669 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973671 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973677 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973679 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973681 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973683 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973685 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973687 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973689 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973691 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973693 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973695 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973697 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973699 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973705 */     GIR_RootConstrainSelectedInstOperands,
     /*  973706 */     // GIR_Coverage, 8479,
     /*  973706 */     GIR_EraseRootFromParent_Done,
     /*  973707 */   // Label 15353: @973707
     /*  973707 */   GIM_Try, /*On fail goto*//*Label 15354*/ GIMT_Encode4(973814), // Rule ID 8480 //
     /*  973712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  973715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  973720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  973726 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  973729 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973732 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  973735 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  973738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973742 */     // MIs[0] matrix_a_fmt
     /*  973742 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973745 */     // MIs[0] matrix_b_fmt
     /*  973745 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973748 */     // MIs[0] src2_modifiers
     /*  973748 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973751 */     // MIs[0] matrix_a_scale
     /*  973751 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973754 */     // MIs[0] matrix_a_scale_fmt
     /*  973754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973757 */     // MIs[0] matrix_b_scale
     /*  973757 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973760 */     // MIs[0] matrix_b_scale_fmt
     /*  973760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973763 */     // MIs[0] matrix_a_reuse
     /*  973763 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973766 */     // MIs[0] matrix_b_reuse
     /*  973766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973769 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  973772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973774 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973776 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973778 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973784 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973786 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973788 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973790 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973792 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973794 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973796 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973798 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973800 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973802 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973804 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973806 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973809 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973812 */     GIR_RootConstrainSelectedInstOperands,
     /*  973813 */     // GIR_Coverage, 8480,
     /*  973813 */     GIR_EraseRootFromParent_Done,
     /*  973814 */   // Label 15354: @973814
     /*  973814 */   GIM_Try, /*On fail goto*//*Label 15355*/ GIMT_Encode4(973921), // Rule ID 8481 //
     /*  973819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  973822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  973827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973830 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  973833 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  973836 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973839 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  973842 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  973845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973849 */     // MIs[0] matrix_a_fmt
     /*  973849 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973852 */     // MIs[0] matrix_b_fmt
     /*  973852 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973855 */     // MIs[0] src2_modifiers
     /*  973855 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973858 */     // MIs[0] matrix_a_scale
     /*  973858 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973861 */     // MIs[0] matrix_a_scale_fmt
     /*  973861 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973864 */     // MIs[0] matrix_b_scale
     /*  973864 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973867 */     // MIs[0] matrix_b_scale_fmt
     /*  973867 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973870 */     // MIs[0] matrix_a_reuse
     /*  973870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973873 */     // MIs[0] matrix_b_reuse
     /*  973873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973876 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  973879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973881 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973883 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973885 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973891 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  973893 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  973895 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  973897 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  973899 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  973901 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  973903 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  973905 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  973907 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  973909 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  973911 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  973913 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973916 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  973919 */     GIR_RootConstrainSelectedInstOperands,
     /*  973920 */     // GIR_Coverage, 8481,
     /*  973920 */     GIR_EraseRootFromParent_Done,
     /*  973921 */   // Label 15355: @973921
     /*  973921 */   GIM_Try, /*On fail goto*//*Label 15356*/ GIMT_Encode4(974028), // Rule ID 8482 //
     /*  973926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  973929 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  973934 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  973937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  973940 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  973943 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  973946 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  973949 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  973952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  973956 */     // MIs[0] matrix_a_fmt
     /*  973956 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  973959 */     // MIs[0] matrix_b_fmt
     /*  973959 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  973962 */     // MIs[0] src2_modifiers
     /*  973962 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  973965 */     // MIs[0] matrix_a_scale
     /*  973965 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  973968 */     // MIs[0] matrix_a_scale_fmt
     /*  973968 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  973971 */     // MIs[0] matrix_b_scale
     /*  973971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  973974 */     // MIs[0] matrix_b_scale_fmt
     /*  973974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  973977 */     // MIs[0] matrix_a_reuse
     /*  973977 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  973980 */     // MIs[0] matrix_b_reuse
     /*  973980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  973983 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  973983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  973986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  973988 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  973990 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  973992 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  973998 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974000 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974002 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974004 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974006 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974008 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974010 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974012 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974014 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974016 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974018 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974026 */     GIR_RootConstrainSelectedInstOperands,
     /*  974027 */     // GIR_Coverage, 8482,
     /*  974027 */     GIR_EraseRootFromParent_Done,
     /*  974028 */   // Label 15356: @974028
     /*  974028 */   GIM_Try, /*On fail goto*//*Label 15357*/ GIMT_Encode4(974135), // Rule ID 8488 //
     /*  974033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  974036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  974041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974047 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  974050 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974053 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  974056 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  974059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974063 */     // MIs[0] matrix_a_fmt
     /*  974063 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974066 */     // MIs[0] matrix_b_fmt
     /*  974066 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974069 */     // MIs[0] src2_modifiers
     /*  974069 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974072 */     // MIs[0] matrix_a_scale
     /*  974072 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974075 */     // MIs[0] matrix_a_scale_fmt
     /*  974075 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974078 */     // MIs[0] matrix_b_scale
     /*  974078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974081 */     // MIs[0] matrix_b_scale_fmt
     /*  974081 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974084 */     // MIs[0] matrix_a_reuse
     /*  974084 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974087 */     // MIs[0] matrix_b_reuse
     /*  974087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974090 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  974093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974095 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974097 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974099 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974105 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974107 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974109 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974111 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974113 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974115 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974117 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974119 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974121 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974123 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974125 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974133 */     GIR_RootConstrainSelectedInstOperands,
     /*  974134 */     // GIR_Coverage, 8488,
     /*  974134 */     GIR_EraseRootFromParent_Done,
     /*  974135 */   // Label 15357: @974135
     /*  974135 */   GIM_Try, /*On fail goto*//*Label 15358*/ GIMT_Encode4(974242), // Rule ID 8489 //
     /*  974140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  974143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  974148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974154 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  974157 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974160 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  974163 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  974166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974170 */     // MIs[0] matrix_a_fmt
     /*  974170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974173 */     // MIs[0] matrix_b_fmt
     /*  974173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974176 */     // MIs[0] src2_modifiers
     /*  974176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974179 */     // MIs[0] matrix_a_scale
     /*  974179 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974182 */     // MIs[0] matrix_a_scale_fmt
     /*  974182 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974185 */     // MIs[0] matrix_b_scale
     /*  974185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974188 */     // MIs[0] matrix_b_scale_fmt
     /*  974188 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974191 */     // MIs[0] matrix_a_reuse
     /*  974191 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974194 */     // MIs[0] matrix_b_reuse
     /*  974194 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974197 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  974200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974202 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974204 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974206 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974212 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974214 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974216 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974218 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974220 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974222 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974224 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974226 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974228 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974230 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974232 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974240 */     GIR_RootConstrainSelectedInstOperands,
     /*  974241 */     // GIR_Coverage, 8489,
     /*  974241 */     GIR_EraseRootFromParent_Done,
     /*  974242 */   // Label 15358: @974242
     /*  974242 */   GIM_Try, /*On fail goto*//*Label 15359*/ GIMT_Encode4(974349), // Rule ID 8490 //
     /*  974247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  974250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  974255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974261 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  974264 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974267 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  974270 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  974273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974277 */     // MIs[0] matrix_a_fmt
     /*  974277 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974280 */     // MIs[0] matrix_b_fmt
     /*  974280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974283 */     // MIs[0] src2_modifiers
     /*  974283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974286 */     // MIs[0] matrix_a_scale
     /*  974286 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974289 */     // MIs[0] matrix_a_scale_fmt
     /*  974289 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974292 */     // MIs[0] matrix_b_scale
     /*  974292 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974295 */     // MIs[0] matrix_b_scale_fmt
     /*  974295 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974298 */     // MIs[0] matrix_a_reuse
     /*  974298 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974301 */     // MIs[0] matrix_b_reuse
     /*  974301 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974304 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  974307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974309 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974311 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974313 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974319 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974321 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974323 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974325 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974327 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974329 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974331 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974333 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974335 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974337 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974339 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974347 */     GIR_RootConstrainSelectedInstOperands,
     /*  974348 */     // GIR_Coverage, 8490,
     /*  974348 */     GIR_EraseRootFromParent_Done,
     /*  974349 */   // Label 15359: @974349
     /*  974349 */   GIM_Try, /*On fail goto*//*Label 15360*/ GIMT_Encode4(974456), // Rule ID 8491 //
     /*  974354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  974357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  974362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974368 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  974371 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974374 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  974377 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  974380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974384 */     // MIs[0] matrix_a_fmt
     /*  974384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974387 */     // MIs[0] matrix_b_fmt
     /*  974387 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974390 */     // MIs[0] src2_modifiers
     /*  974390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974393 */     // MIs[0] matrix_a_scale
     /*  974393 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974396 */     // MIs[0] matrix_a_scale_fmt
     /*  974396 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974399 */     // MIs[0] matrix_b_scale
     /*  974399 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974402 */     // MIs[0] matrix_b_scale_fmt
     /*  974402 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974405 */     // MIs[0] matrix_a_reuse
     /*  974405 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974408 */     // MIs[0] matrix_b_reuse
     /*  974408 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974411 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  974414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974416 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974418 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974420 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974426 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974428 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974430 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974432 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974434 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974436 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974438 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974440 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974442 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974444 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974446 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974454 */     GIR_RootConstrainSelectedInstOperands,
     /*  974455 */     // GIR_Coverage, 8491,
     /*  974455 */     GIR_EraseRootFromParent_Done,
     /*  974456 */   // Label 15360: @974456
     /*  974456 */   GIM_Try, /*On fail goto*//*Label 15361*/ GIMT_Encode4(974563), // Rule ID 8492 //
     /*  974461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  974464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  974469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974475 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s32,
     /*  974478 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974481 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  974484 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  974487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974491 */     // MIs[0] matrix_a_fmt
     /*  974491 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974494 */     // MIs[0] matrix_b_fmt
     /*  974494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974497 */     // MIs[0] src2_modifiers
     /*  974497 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974500 */     // MIs[0] matrix_a_scale
     /*  974500 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974503 */     // MIs[0] matrix_a_scale_fmt
     /*  974503 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974506 */     // MIs[0] matrix_b_scale
     /*  974506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974509 */     // MIs[0] matrix_b_scale_fmt
     /*  974509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974512 */     // MIs[0] matrix_a_reuse
     /*  974512 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974515 */     // MIs[0] matrix_b_reuse
     /*  974515 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974518 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v16i32:{ *:[v16i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v16i32:{ *:[v16i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr),
     /*  974521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974523 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974525 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974527 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974533 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974535 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974537 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974539 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974541 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974543 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974545 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974547 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974549 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974551 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974553 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974561 */     GIR_RootConstrainSelectedInstOperands,
     /*  974562 */     // GIR_Coverage, 8492,
     /*  974562 */     GIR_EraseRootFromParent_Done,
     /*  974563 */   // Label 15361: @974563
     /*  974563 */   GIM_Try, /*On fail goto*//*Label 15362*/ GIMT_Encode4(974670), // Rule ID 8508 //
     /*  974568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  974571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  974576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974582 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  974585 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974588 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  974591 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  974594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974598 */     // MIs[0] matrix_a_fmt
     /*  974598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974601 */     // MIs[0] matrix_b_fmt
     /*  974601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974604 */     // MIs[0] src2_modifiers
     /*  974604 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974607 */     // MIs[0] matrix_a_scale
     /*  974607 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974610 */     // MIs[0] matrix_a_scale_fmt
     /*  974610 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974613 */     // MIs[0] matrix_b_scale
     /*  974613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974616 */     // MIs[0] matrix_b_scale_fmt
     /*  974616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974619 */     // MIs[0] matrix_a_reuse
     /*  974619 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974622 */     // MIs[0] matrix_b_reuse
     /*  974622 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974625 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  974628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974630 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974632 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974634 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974640 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974642 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974644 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974646 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974648 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974650 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974652 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974654 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974656 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974658 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974660 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974662 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974668 */     GIR_RootConstrainSelectedInstOperands,
     /*  974669 */     // GIR_Coverage, 8508,
     /*  974669 */     GIR_EraseRootFromParent_Done,
     /*  974670 */   // Label 15362: @974670
     /*  974670 */   GIM_Try, /*On fail goto*//*Label 15363*/ GIMT_Encode4(974777), // Rule ID 8509 //
     /*  974675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  974678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  974683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974689 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  974692 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974695 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  974698 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  974701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974705 */     // MIs[0] matrix_a_fmt
     /*  974705 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974708 */     // MIs[0] matrix_b_fmt
     /*  974708 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974711 */     // MIs[0] src2_modifiers
     /*  974711 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974714 */     // MIs[0] matrix_a_scale
     /*  974714 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974717 */     // MIs[0] matrix_a_scale_fmt
     /*  974717 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974720 */     // MIs[0] matrix_b_scale
     /*  974720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974723 */     // MIs[0] matrix_b_scale_fmt
     /*  974723 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974726 */     // MIs[0] matrix_a_reuse
     /*  974726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974729 */     // MIs[0] matrix_b_reuse
     /*  974729 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974732 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  974735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974737 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974739 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974741 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974747 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974749 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974751 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974753 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974755 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974757 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974759 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974761 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974763 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974765 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974767 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974772 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974775 */     GIR_RootConstrainSelectedInstOperands,
     /*  974776 */     // GIR_Coverage, 8509,
     /*  974776 */     GIR_EraseRootFromParent_Done,
     /*  974777 */   // Label 15363: @974777
     /*  974777 */   GIM_Try, /*On fail goto*//*Label 15364*/ GIMT_Encode4(974884), // Rule ID 8510 //
     /*  974782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  974785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  974790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974796 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  974799 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974802 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  974805 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  974808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974812 */     // MIs[0] matrix_a_fmt
     /*  974812 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974815 */     // MIs[0] matrix_b_fmt
     /*  974815 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974818 */     // MIs[0] src2_modifiers
     /*  974818 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974821 */     // MIs[0] matrix_a_scale
     /*  974821 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974824 */     // MIs[0] matrix_a_scale_fmt
     /*  974824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974827 */     // MIs[0] matrix_b_scale
     /*  974827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974830 */     // MIs[0] matrix_b_scale_fmt
     /*  974830 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974833 */     // MIs[0] matrix_a_reuse
     /*  974833 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974836 */     // MIs[0] matrix_b_reuse
     /*  974836 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974839 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  974842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974844 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974846 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974848 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974854 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974856 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974858 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974860 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974862 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974864 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974866 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974868 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974870 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974872 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974874 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974882 */     GIR_RootConstrainSelectedInstOperands,
     /*  974883 */     // GIR_Coverage, 8510,
     /*  974883 */     GIR_EraseRootFromParent_Done,
     /*  974884 */   // Label 15364: @974884
     /*  974884 */   GIM_Try, /*On fail goto*//*Label 15365*/ GIMT_Encode4(974991), // Rule ID 8511 //
     /*  974889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  974892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  974897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  974900 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  974903 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  974906 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  974909 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  974912 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  974915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  974919 */     // MIs[0] matrix_a_fmt
     /*  974919 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  974922 */     // MIs[0] matrix_b_fmt
     /*  974922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  974925 */     // MIs[0] src2_modifiers
     /*  974925 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  974928 */     // MIs[0] matrix_a_scale
     /*  974928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  974931 */     // MIs[0] matrix_a_scale_fmt
     /*  974931 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  974934 */     // MIs[0] matrix_b_scale
     /*  974934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  974937 */     // MIs[0] matrix_b_scale_fmt
     /*  974937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  974940 */     // MIs[0] matrix_a_reuse
     /*  974940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  974943 */     // MIs[0] matrix_b_reuse
     /*  974943 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  974946 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  974946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  974949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  974951 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  974953 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  974955 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  974961 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  974963 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  974965 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  974967 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  974969 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  974971 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  974973 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  974975 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  974977 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  974979 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  974981 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  974983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  974989 */     GIR_RootConstrainSelectedInstOperands,
     /*  974990 */     // GIR_Coverage, 8511,
     /*  974990 */     GIR_EraseRootFromParent_Done,
     /*  974991 */   // Label 15365: @974991
     /*  974991 */   GIM_Try, /*On fail goto*//*Label 15366*/ GIMT_Encode4(975098), // Rule ID 8512 //
     /*  974996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  974999 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  975004 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975010 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  975013 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975016 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  975019 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  975022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975026 */     // MIs[0] matrix_a_fmt
     /*  975026 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975029 */     // MIs[0] matrix_b_fmt
     /*  975029 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975032 */     // MIs[0] src2_modifiers
     /*  975032 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975035 */     // MIs[0] matrix_a_scale
     /*  975035 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975038 */     // MIs[0] matrix_a_scale_fmt
     /*  975038 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975041 */     // MIs[0] matrix_b_scale
     /*  975041 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975044 */     // MIs[0] matrix_b_scale_fmt
     /*  975044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975047 */     // MIs[0] matrix_a_reuse
     /*  975047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975050 */     // MIs[0] matrix_b_reuse
     /*  975050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975053 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  975056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975058 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975060 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975062 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975068 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975070 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975072 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975074 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975076 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975078 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975080 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975082 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975084 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975086 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975088 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975096 */     GIR_RootConstrainSelectedInstOperands,
     /*  975097 */     // GIR_Coverage, 8512,
     /*  975097 */     GIR_EraseRootFromParent_Done,
     /*  975098 */   // Label 15366: @975098
     /*  975098 */   GIM_Try, /*On fail goto*//*Label 15367*/ GIMT_Encode4(975205), // Rule ID 8518 //
     /*  975103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  975106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  975111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975117 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  975120 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975123 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  975126 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  975129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975133 */     // MIs[0] matrix_a_fmt
     /*  975133 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975136 */     // MIs[0] matrix_b_fmt
     /*  975136 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975139 */     // MIs[0] src2_modifiers
     /*  975139 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975142 */     // MIs[0] matrix_a_scale
     /*  975142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975145 */     // MIs[0] matrix_a_scale_fmt
     /*  975145 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975148 */     // MIs[0] matrix_b_scale
     /*  975148 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975151 */     // MIs[0] matrix_b_scale_fmt
     /*  975151 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975154 */     // MIs[0] matrix_a_reuse
     /*  975154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975157 */     // MIs[0] matrix_b_reuse
     /*  975157 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975160 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  975163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975165 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975167 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975169 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975175 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975177 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975179 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975181 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975183 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975185 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975187 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975189 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975191 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975193 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975195 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975197 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975203 */     GIR_RootConstrainSelectedInstOperands,
     /*  975204 */     // GIR_Coverage, 8518,
     /*  975204 */     GIR_EraseRootFromParent_Done,
     /*  975205 */   // Label 15367: @975205
     /*  975205 */   GIM_Try, /*On fail goto*//*Label 15368*/ GIMT_Encode4(975312), // Rule ID 8519 //
     /*  975210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  975213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  975218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975224 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  975227 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975230 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  975233 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  975236 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975240 */     // MIs[0] matrix_a_fmt
     /*  975240 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975243 */     // MIs[0] matrix_b_fmt
     /*  975243 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975246 */     // MIs[0] src2_modifiers
     /*  975246 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975249 */     // MIs[0] matrix_a_scale
     /*  975249 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975252 */     // MIs[0] matrix_a_scale_fmt
     /*  975252 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975255 */     // MIs[0] matrix_b_scale
     /*  975255 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975258 */     // MIs[0] matrix_b_scale_fmt
     /*  975258 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975261 */     // MIs[0] matrix_a_reuse
     /*  975261 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975264 */     // MIs[0] matrix_b_reuse
     /*  975264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975267 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  975270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975272 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975274 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975276 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975282 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975284 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975286 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975288 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975290 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975292 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975294 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975296 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975298 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975300 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975302 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975310 */     GIR_RootConstrainSelectedInstOperands,
     /*  975311 */     // GIR_Coverage, 8519,
     /*  975311 */     GIR_EraseRootFromParent_Done,
     /*  975312 */   // Label 15368: @975312
     /*  975312 */   GIM_Try, /*On fail goto*//*Label 15369*/ GIMT_Encode4(975419), // Rule ID 8520 //
     /*  975317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  975320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  975325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975331 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  975334 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975337 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  975340 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  975343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975347 */     // MIs[0] matrix_a_fmt
     /*  975347 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975350 */     // MIs[0] matrix_b_fmt
     /*  975350 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975353 */     // MIs[0] src2_modifiers
     /*  975353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975356 */     // MIs[0] matrix_a_scale
     /*  975356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975359 */     // MIs[0] matrix_a_scale_fmt
     /*  975359 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975362 */     // MIs[0] matrix_b_scale
     /*  975362 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975365 */     // MIs[0] matrix_b_scale_fmt
     /*  975365 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975368 */     // MIs[0] matrix_a_reuse
     /*  975368 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975371 */     // MIs[0] matrix_b_reuse
     /*  975371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975374 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  975377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975379 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975381 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975383 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975389 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975391 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975393 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975395 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975397 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975399 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975401 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975403 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975405 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975407 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975409 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975414 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975417 */     GIR_RootConstrainSelectedInstOperands,
     /*  975418 */     // GIR_Coverage, 8520,
     /*  975418 */     GIR_EraseRootFromParent_Done,
     /*  975419 */   // Label 15369: @975419
     /*  975419 */   GIM_Try, /*On fail goto*//*Label 15370*/ GIMT_Encode4(975526), // Rule ID 8521 //
     /*  975424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  975427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  975432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975435 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975438 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  975441 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975444 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  975447 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  975450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975454 */     // MIs[0] matrix_a_fmt
     /*  975454 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975457 */     // MIs[0] matrix_b_fmt
     /*  975457 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975460 */     // MIs[0] src2_modifiers
     /*  975460 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975463 */     // MIs[0] matrix_a_scale
     /*  975463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975466 */     // MIs[0] matrix_a_scale_fmt
     /*  975466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975469 */     // MIs[0] matrix_b_scale
     /*  975469 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975472 */     // MIs[0] matrix_b_scale_fmt
     /*  975472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975475 */     // MIs[0] matrix_a_reuse
     /*  975475 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975478 */     // MIs[0] matrix_b_reuse
     /*  975478 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975481 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  975484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975486 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975488 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975490 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975496 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975498 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975500 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975502 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975504 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975506 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975508 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975510 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975512 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975514 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975516 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975518 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975524 */     GIR_RootConstrainSelectedInstOperands,
     /*  975525 */     // GIR_Coverage, 8521,
     /*  975525 */     GIR_EraseRootFromParent_Done,
     /*  975526 */   // Label 15370: @975526
     /*  975526 */   GIM_Try, /*On fail goto*//*Label 15371*/ GIMT_Encode4(975633), // Rule ID 8522 //
     /*  975531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  975534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  975539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975545 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v12s32,
     /*  975548 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975551 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  975554 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  975557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975561 */     // MIs[0] matrix_a_fmt
     /*  975561 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975564 */     // MIs[0] matrix_b_fmt
     /*  975564 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975567 */     // MIs[0] src2_modifiers
     /*  975567 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975570 */     // MIs[0] matrix_a_scale
     /*  975570 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975573 */     // MIs[0] matrix_a_scale_fmt
     /*  975573 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975576 */     // MIs[0] matrix_b_scale
     /*  975576 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975579 */     // MIs[0] matrix_b_scale_fmt
     /*  975579 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975582 */     // MIs[0] matrix_a_reuse
     /*  975582 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975585 */     // MIs[0] matrix_b_reuse
     /*  975585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975588 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v12i32:{ *:[v12i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v12i32:{ *:[v12i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr),
     /*  975591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975593 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975595 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975597 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975603 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975605 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975607 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975609 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975611 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975613 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975615 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975617 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975619 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975621 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975623 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975625 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975628 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975631 */     GIR_RootConstrainSelectedInstOperands,
     /*  975632 */     // GIR_Coverage, 8522,
     /*  975632 */     GIR_EraseRootFromParent_Done,
     /*  975633 */   // Label 15371: @975633
     /*  975633 */   GIM_Try, /*On fail goto*//*Label 15372*/ GIMT_Encode4(975740), // Rule ID 8538 //
     /*  975638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  975641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  975646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975649 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975652 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  975655 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975658 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  975661 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  975664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975668 */     // MIs[0] matrix_a_fmt
     /*  975668 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975671 */     // MIs[0] matrix_b_fmt
     /*  975671 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975674 */     // MIs[0] src2_modifiers
     /*  975674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975677 */     // MIs[0] matrix_a_scale
     /*  975677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975680 */     // MIs[0] matrix_a_scale_fmt
     /*  975680 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975683 */     // MIs[0] matrix_b_scale
     /*  975683 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975686 */     // MIs[0] matrix_b_scale_fmt
     /*  975686 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975689 */     // MIs[0] matrix_a_reuse
     /*  975689 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975692 */     // MIs[0] matrix_b_reuse
     /*  975692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975695 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  975698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975700 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975702 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975704 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975710 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975712 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975714 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975716 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975718 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975720 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975722 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975724 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975726 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975728 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975730 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975735 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975738 */     GIR_RootConstrainSelectedInstOperands,
     /*  975739 */     // GIR_Coverage, 8538,
     /*  975739 */     GIR_EraseRootFromParent_Done,
     /*  975740 */   // Label 15372: @975740
     /*  975740 */   GIM_Try, /*On fail goto*//*Label 15373*/ GIMT_Encode4(975847), // Rule ID 8539 //
     /*  975745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  975748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  975753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975756 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975759 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  975762 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975765 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  975768 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  975771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975775 */     // MIs[0] matrix_a_fmt
     /*  975775 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975778 */     // MIs[0] matrix_b_fmt
     /*  975778 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975781 */     // MIs[0] src2_modifiers
     /*  975781 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975784 */     // MIs[0] matrix_a_scale
     /*  975784 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975787 */     // MIs[0] matrix_a_scale_fmt
     /*  975787 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975790 */     // MIs[0] matrix_b_scale
     /*  975790 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975793 */     // MIs[0] matrix_b_scale_fmt
     /*  975793 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975796 */     // MIs[0] matrix_a_reuse
     /*  975796 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975799 */     // MIs[0] matrix_b_reuse
     /*  975799 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975802 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  975805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975807 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975809 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975811 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975817 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975819 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975821 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975823 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975825 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975827 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975829 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975831 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975833 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975835 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975837 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975839 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975845 */     GIR_RootConstrainSelectedInstOperands,
     /*  975846 */     // GIR_Coverage, 8539,
     /*  975846 */     GIR_EraseRootFromParent_Done,
     /*  975847 */   // Label 15373: @975847
     /*  975847 */   GIM_Try, /*On fail goto*//*Label 15374*/ GIMT_Encode4(975954), // Rule ID 8540 //
     /*  975852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  975855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  975860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975866 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  975869 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975872 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  975875 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  975878 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975882 */     // MIs[0] matrix_a_fmt
     /*  975882 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975885 */     // MIs[0] matrix_b_fmt
     /*  975885 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975888 */     // MIs[0] src2_modifiers
     /*  975888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975891 */     // MIs[0] matrix_a_scale
     /*  975891 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  975894 */     // MIs[0] matrix_a_scale_fmt
     /*  975894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  975897 */     // MIs[0] matrix_b_scale
     /*  975897 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  975900 */     // MIs[0] matrix_b_scale_fmt
     /*  975900 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  975903 */     // MIs[0] matrix_a_reuse
     /*  975903 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  975906 */     // MIs[0] matrix_b_reuse
     /*  975906 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  975909 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  975909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  975912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  975914 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  975916 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  975918 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  975924 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  975926 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  975928 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  975930 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  975932 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  975934 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  975936 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  975938 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  975940 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  975942 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  975944 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  975946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  975952 */     GIR_RootConstrainSelectedInstOperands,
     /*  975953 */     // GIR_Coverage, 8540,
     /*  975953 */     GIR_EraseRootFromParent_Done,
     /*  975954 */   // Label 15374: @975954
     /*  975954 */   GIM_Try, /*On fail goto*//*Label 15375*/ GIMT_Encode4(976061), // Rule ID 8541 //
     /*  975959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  975962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  975967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  975970 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  975973 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  975976 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  975979 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  975982 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  975985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  975989 */     // MIs[0] matrix_a_fmt
     /*  975989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  975992 */     // MIs[0] matrix_b_fmt
     /*  975992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  975995 */     // MIs[0] src2_modifiers
     /*  975995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  975998 */     // MIs[0] matrix_a_scale
     /*  975998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976001 */     // MIs[0] matrix_a_scale_fmt
     /*  976001 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976004 */     // MIs[0] matrix_b_scale
     /*  976004 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976007 */     // MIs[0] matrix_b_scale_fmt
     /*  976007 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976010 */     // MIs[0] matrix_a_reuse
     /*  976010 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976013 */     // MIs[0] matrix_b_reuse
     /*  976013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976016 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976021 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976023 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976025 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976031 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976033 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976035 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976037 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976039 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976041 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976043 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976045 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976047 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976049 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976051 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976059 */     GIR_RootConstrainSelectedInstOperands,
     /*  976060 */     // GIR_Coverage, 8541,
     /*  976060 */     GIR_EraseRootFromParent_Done,
     /*  976061 */   // Label 15375: @976061
     /*  976061 */   GIM_Try, /*On fail goto*//*Label 15376*/ GIMT_Encode4(976168), // Rule ID 8542 //
     /*  976066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  976069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale_f32_16x16x128_f8f6f4),
     /*  976074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  976077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  976080 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  976083 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  976086 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s32,
     /*  976089 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s32,
     /*  976092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  976096 */     // MIs[0] matrix_a_fmt
     /*  976096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  976099 */     // MIs[0] matrix_b_fmt
     /*  976099 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  976102 */     // MIs[0] src2_modifiers
     /*  976102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  976105 */     // MIs[0] matrix_a_scale
     /*  976105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976108 */     // MIs[0] matrix_a_scale_fmt
     /*  976108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976111 */     // MIs[0] matrix_b_scale
     /*  976111 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976114 */     // MIs[0] matrix_b_scale_fmt
     /*  976114 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976117 */     // MIs[0] matrix_a_reuse
     /*  976117 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976120 */     // MIs[0] matrix_b_reuse
     /*  976120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976123 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3668:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i32:{ *:[i32] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i32:{ *:[i32] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$scale_src0, i32:{ *:[i32] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976128 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976130 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976132 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976138 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976140 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976142 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976144 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976146 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976148 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976150 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976152 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976154 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976156 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976158 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976166 */     GIR_RootConstrainSelectedInstOperands,
     /*  976167 */     // GIR_Coverage, 8542,
     /*  976167 */     GIR_EraseRootFromParent_Done,
     /*  976168 */   // Label 15376: @976168
     /*  976168 */   GIM_Try, /*On fail goto*//*Label 15377*/ GIMT_Encode4(976275), // Rule ID 8548 //
     /*  976173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode0),
     /*  976176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  976181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  976184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  976187 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  976190 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  976193 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  976196 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  976199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  976203 */     // MIs[0] matrix_a_fmt
     /*  976203 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  976206 */     // MIs[0] matrix_b_fmt
     /*  976206 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  976209 */     // MIs[0] src2_modifiers
     /*  976209 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  976212 */     // MIs[0] matrix_a_scale
     /*  976212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976215 */     // MIs[0] matrix_a_scale_fmt
     /*  976215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976218 */     // MIs[0] matrix_b_scale
     /*  976218 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976221 */     // MIs[0] matrix_b_scale_fmt
     /*  976221 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976224 */     // MIs[0] matrix_a_reuse
     /*  976224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976227 */     // MIs[0] matrix_b_reuse
     /*  976227 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976230 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976235 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976237 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976239 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976245 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976247 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976249 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976251 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976253 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976255 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976257 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976259 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976261 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976263 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976265 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976267 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976273 */     GIR_RootConstrainSelectedInstOperands,
     /*  976274 */     // GIR_Coverage, 8548,
     /*  976274 */     GIR_EraseRootFromParent_Done,
     /*  976275 */   // Label 15377: @976275
     /*  976275 */   GIM_Try, /*On fail goto*//*Label 15378*/ GIMT_Encode4(976382), // Rule ID 8549 //
     /*  976280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode1),
     /*  976283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  976288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  976291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  976294 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  976297 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  976300 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  976303 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  976306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  976310 */     // MIs[0] matrix_a_fmt
     /*  976310 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  976313 */     // MIs[0] matrix_b_fmt
     /*  976313 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  976316 */     // MIs[0] src2_modifiers
     /*  976316 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  976319 */     // MIs[0] matrix_a_scale
     /*  976319 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976322 */     // MIs[0] matrix_a_scale_fmt
     /*  976322 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976325 */     // MIs[0] matrix_b_scale
     /*  976325 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976328 */     // MIs[0] matrix_b_scale_fmt
     /*  976328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976331 */     // MIs[0] matrix_a_reuse
     /*  976331 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976334 */     // MIs[0] matrix_b_reuse
     /*  976334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976337 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976342 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976344 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976346 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976352 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976354 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976356 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976358 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976360 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976362 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976364 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976366 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976368 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976370 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976372 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976377 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976380 */     GIR_RootConstrainSelectedInstOperands,
     /*  976381 */     // GIR_Coverage, 8549,
     /*  976381 */     GIR_EraseRootFromParent_Done,
     /*  976382 */   // Label 15378: @976382
     /*  976382 */   GIM_Try, /*On fail goto*//*Label 15379*/ GIMT_Encode4(976489), // Rule ID 8550 //
     /*  976387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode2),
     /*  976390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  976395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  976398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  976401 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  976404 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  976407 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  976410 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  976413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  976417 */     // MIs[0] matrix_a_fmt
     /*  976417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  976420 */     // MIs[0] matrix_b_fmt
     /*  976420 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  976423 */     // MIs[0] src2_modifiers
     /*  976423 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  976426 */     // MIs[0] matrix_a_scale
     /*  976426 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976429 */     // MIs[0] matrix_a_scale_fmt
     /*  976429 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976432 */     // MIs[0] matrix_b_scale
     /*  976432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976435 */     // MIs[0] matrix_b_scale_fmt
     /*  976435 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976438 */     // MIs[0] matrix_a_reuse
     /*  976438 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976441 */     // MIs[0] matrix_b_reuse
     /*  976441 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976444 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976449 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976451 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976453 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976459 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976461 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976463 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976465 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976467 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976469 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976471 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976473 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976475 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976477 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976479 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976481 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976484 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976487 */     GIR_RootConstrainSelectedInstOperands,
     /*  976488 */     // GIR_Coverage, 8550,
     /*  976488 */     GIR_EraseRootFromParent_Done,
     /*  976489 */   // Label 15379: @976489
     /*  976489 */   GIM_Try, /*On fail goto*//*Label 15380*/ GIMT_Encode4(976596), // Rule ID 8551 //
     /*  976494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode3),
     /*  976497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  976502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  976505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  976508 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  976511 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  976514 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  976517 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  976520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  976524 */     // MIs[0] matrix_a_fmt
     /*  976524 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  976527 */     // MIs[0] matrix_b_fmt
     /*  976527 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  976530 */     // MIs[0] src2_modifiers
     /*  976530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  976533 */     // MIs[0] matrix_a_scale
     /*  976533 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976536 */     // MIs[0] matrix_a_scale_fmt
     /*  976536 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976539 */     // MIs[0] matrix_b_scale
     /*  976539 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976542 */     // MIs[0] matrix_b_scale_fmt
     /*  976542 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976545 */     // MIs[0] matrix_a_reuse
     /*  976545 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976548 */     // MIs[0] matrix_b_reuse
     /*  976548 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976551 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976556 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976558 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976560 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976566 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976568 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976570 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976572 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976574 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976576 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976578 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976580 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976582 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976584 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976586 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976591 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976594 */     GIR_RootConstrainSelectedInstOperands,
     /*  976595 */     // GIR_Coverage, 8551,
     /*  976595 */     GIR_EraseRootFromParent_Done,
     /*  976596 */   // Label 15380: @976596
     /*  976596 */   GIM_Try, /*On fail goto*//*Label 15381*/ GIMT_Encode4(976703), // Rule ID 8552 //
     /*  976601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_isWave32_HwMode4),
     /*  976604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_scale16_f32_16x16x128_f8f6f4),
     /*  976609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32,
     /*  976612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s32,
     /*  976615 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s32,
     /*  976618 */     GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s32,
     /*  976621 */     GIM_RootCheckType, /*Op*/10, /*Type*/GILLT_s64,
     /*  976624 */     GIM_RootCheckType, /*Op*/13, /*Type*/GILLT_s64,
     /*  976627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
     /*  976631 */     // MIs[0] matrix_a_fmt
     /*  976631 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  976634 */     // MIs[0] matrix_b_fmt
     /*  976634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /*  976637 */     // MIs[0] src2_modifiers
     /*  976637 */     GIM_CheckIsImm, /*MI*/0, /*Op*/6,
     /*  976640 */     // MIs[0] matrix_a_scale
     /*  976640 */     GIM_CheckIsImm, /*MI*/0, /*Op*/8,
     /*  976643 */     // MIs[0] matrix_a_scale_fmt
     /*  976643 */     GIM_CheckIsImm, /*MI*/0, /*Op*/9,
     /*  976646 */     // MIs[0] matrix_b_scale
     /*  976646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/11,
     /*  976649 */     // MIs[0] matrix_b_scale_fmt
     /*  976649 */     GIM_CheckIsImm, /*MI*/0, /*Op*/12,
     /*  976652 */     // MIs[0] matrix_a_reuse
     /*  976652 */     GIM_CheckIsImm, /*MI*/0, /*Op*/14,
     /*  976655 */     // MIs[0] matrix_b_reuse
     /*  976655 */     GIM_CheckIsImm, /*MI*/0, /*Op*/15,
     /*  976658 */     // (intrinsic_wo_chain:{ *:[v8f32] } 3670:{ *:[iPTR] }, (timm:{ *:[i32] }):$matrix_a_fmt, v8i32:{ *:[v8i32] }:$src0, (timm:{ *:[i32] }):$matrix_b_fmt, v8i32:{ *:[v8i32] }:$src1, (timm:{ *:[i16] }):$src2_modifiers, v8f32:{ *:[v8f32] }:$src2, (timm:{ *:[i32] }):$matrix_a_scale, (timm:{ *:[i32] }):$matrix_a_scale_fmt, i64:{ *:[i64] }:$scale_src0, (timm:{ *:[i32] }):$matrix_b_scale, (timm:{ *:[i32] }):$matrix_b_scale_fmt, i64:{ *:[i64] }:$scale_src1, (timm:{ *:[i1] }):$matrix_a_reuse, (timm:{ *:[i1] }):$matrix_b_reuse)  =>  (V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr:{ *:[v8f32] } v8i32:{ *:[v8i32] }:$src0, v8i32:{ *:[v8i32] }:$src1, (VOP3PModsNegAbs:{ *:[i32] } ?:{ *:[i16] }:$src2_modifiers), v8f32:{ *:[v8f32] }:$src2, i64:{ *:[i64] }:$scale_src0, i64:{ *:[i64] }:$scale_src1, i32:{ *:[i32] }:$matrix_a_fmt, i32:{ *:[i32] }:$matrix_b_fmt, i32:{ *:[i32] }:$matrix_a_scale, i32:{ *:[i32] }:$matrix_b_scale, i32:{ *:[i32] }:$matrix_a_scale_fmt, i32:{ *:[i32] }:$matrix_b_scale_fmt, i1:{ *:[i1] }:$matrix_a_reuse, i1:{ *:[i1] }:$matrix_b_reuse)
     /*  976658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr),
     /*  976661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  976663 */     GIR_RootToRootCopy, /*OpIdx*/3, // src0
     /*  976665 */     GIR_RootToRootCopy, /*OpIdx*/5, // src1
     /*  976667 */     GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderVOP3PModsNegAbs), // src2_modifiers
     /*  976673 */     GIR_RootToRootCopy, /*OpIdx*/7, // src2
     /*  976675 */     GIR_RootToRootCopy, /*OpIdx*/10, // scale_src0
     /*  976677 */     GIR_RootToRootCopy, /*OpIdx*/13, // scale_src1
     /*  976679 */     GIR_RootToRootCopy, /*OpIdx*/2, // matrix_a_fmt
     /*  976681 */     GIR_RootToRootCopy, /*OpIdx*/4, // matrix_b_fmt
     /*  976683 */     GIR_RootToRootCopy, /*OpIdx*/8, // matrix_a_scale
     /*  976685 */     GIR_RootToRootCopy, /*OpIdx*/11, // matrix_b_scale
     /*  976687 */     GIR_RootToRootCopy, /*OpIdx*/9, // matrix_a_scale_fmt
     /*  976689 */     GIR_RootToRootCopy, /*OpIdx*/12, // matrix_b_scale_fmt
     /*  976691 */     GIR_RootToRootCopy, /*OpIdx*/14, // matrix_a_reuse
     /*  976693 */     GIR_RootToRootCopy, /*OpIdx*/15, // matrix_b_reuse
     /*  976695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976698 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976701 */     GIR_RootConstrainSelectedInstOperands,
     /*  976702 */     // GIR_Coverage, 8552,
     /*  976702 */     GIR_EraseRootFromParent_Done,
     /*  976703 */   // Label 15381: @976703
     /*  976703 */   GIM_Reject,
     /*  976704 */ // Label 15201: @976704
     /*  976704 */ GIM_Reject,
     /*  976705 */ // Label 41: @976705
     /*  976705 */ GIM_Try, /*On fail goto*//*Label 15382*/ GIMT_Encode4(976781),
     /*  976710 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
     /*  976713 */   GIM_Try, /*On fail goto*//*Label 15383*/ GIMT_Encode4(976728), // Rule ID 182 //
     /*  976718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier),
     /*  976723 */     // (intrinsic_void 3422:{ *:[iPTR] })  =>  (S_BARRIER)
     /*  976723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER),
     /*  976726 */     GIR_RootConstrainSelectedInstOperands,
     /*  976727 */     // GIR_Coverage, 182,
     /*  976727 */     GIR_EraseRootFromParent_Done,
     /*  976728 */   // Label 15383: @976728
     /*  976728 */   GIM_Try, /*On fail goto*//*Label 15384*/ GIMT_Encode4(976743), // Rule ID 4241 //
     /*  976733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wave_barrier),
     /*  976738 */     // (intrinsic_void 3613:{ *:[iPTR] })  =>  (WAVE_BARRIER)
     /*  976738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_BARRIER),
     /*  976741 */     GIR_RootConstrainSelectedInstOperands,
     /*  976742 */     // GIR_Coverage, 4241,
     /*  976742 */     GIR_EraseRootFromParent_Done,
     /*  976743 */   // Label 15384: @976743
     /*  976743 */   GIM_Try, /*On fail goto*//*Label 15385*/ GIMT_Encode4(976762), // Rule ID 4265 //
     /*  976748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_unreachable),
     /*  976753 */     // (intrinsic_void 3611:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
     /*  976753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_MASKED_UNREACHABLE),
     /*  976756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  976760 */     GIR_RootConstrainSelectedInstOperands,
     /*  976761 */     // GIR_Coverage, 4265,
     /*  976761 */     GIR_EraseRootFromParent_Done,
     /*  976762 */   // Label 15385: @976762
     /*  976762 */   GIM_Try, /*On fail goto*//*Label 15386*/ GIMT_Encode4(976780), // Rule ID 4795 //
     /*  976767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_endpgm),
     /*  976772 */     // (intrinsic_void 2437:{ *:[iPTR] })  =>  (S_ENDPGM 0:{ *:[i16] })
     /*  976772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ENDPGM),
     /*  976775 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976778 */     GIR_RootConstrainSelectedInstOperands,
     /*  976779 */     // GIR_Coverage, 4795,
     /*  976779 */     GIR_EraseRootFromParent_Done,
     /*  976780 */   // Label 15386: @976780
     /*  976780 */   GIM_Reject,
     /*  976781 */ // Label 15382: @976781
     /*  976781 */ GIM_Try, /*On fail goto*//*Label 15387*/ GIMT_Encode4(977110),
     /*  976786 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     /*  976789 */   GIM_Try, /*On fail goto*//*Label 15388*/ GIMT_Encode4(976838), // Rule ID 28762 //
     /*  976794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus),
     /*  976797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_ds_atomic_async_barrier_arrive_b64),
     /*  976802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /*  976806 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  976813 */     // (intrinsic_void 2407:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 VGPR_32:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  976813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64),
     /*  976816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  976821 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  976826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  976829 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::ASYNCcnt*/0,
     /*  976832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  976836 */     GIR_RootConstrainSelectedInstOperands,
     /*  976837 */     // GIR_Coverage, 28762,
     /*  976837 */     GIR_EraseRootFromParent_Done,
     /*  976838 */   // Label 15388: @976838
     /*  976838 */   GIM_Try, /*On fail goto*//*Label 15389*/ GIMT_Encode4(976858), // Rule ID 41 //
     /*  976843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_signal),
     /*  976848 */     // MIs[0] src0
     /*  976848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  976851 */     // (intrinsic_void 3426:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0)  =>  (S_BARRIER_SIGNAL_IMM (timm:{ *:[i32] }):$src0)
     /*  976851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_SIGNAL_IMM),
     /*  976854 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  976856 */     GIR_RootConstrainSelectedInstOperands,
     /*  976857 */     // GIR_Coverage, 41,
     /*  976857 */     GIR_EraseRootFromParent_Done,
     /*  976858 */   // Label 15389: @976858
     /*  976858 */   GIM_Try, /*On fail goto*//*Label 15390*/ GIMT_Encode4(976878), // Rule ID 183 //
     /*  976863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_wait),
     /*  976868 */     // MIs[0] simm16
     /*  976868 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  976871 */     // (intrinsic_void 3429:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_BARRIER_WAIT (timm:{ *:[i16] }):$simm16)
     /*  976871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_WAIT),
     /*  976874 */     GIR_RootToRootCopy, /*OpIdx*/1, // simm16
     /*  976876 */     GIR_RootConstrainSelectedInstOperands,
     /*  976877 */     // GIR_Coverage, 183,
     /*  976877 */     GIR_EraseRootFromParent_Done,
     /*  976878 */   // Label 15390: @976878
     /*  976878 */   GIM_Try, /*On fail goto*//*Label 15391*/ GIMT_Encode4(976898), // Rule ID 4242 //
     /*  976883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_sched_barrier),
     /*  976888 */     // MIs[0] mask
     /*  976888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  976891 */     // (intrinsic_void 3481:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask)  =>  (SCHED_BARRIER (timm:{ *:[i32] }):$mask)
     /*  976891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCHED_BARRIER),
     /*  976894 */     GIR_RootToRootCopy, /*OpIdx*/1, // mask
     /*  976896 */     GIR_RootConstrainSelectedInstOperands,
     /*  976897 */     // GIR_Coverage, 4242,
     /*  976897 */     GIR_EraseRootFromParent_Done,
     /*  976898 */   // Label 15391: @976898
     /*  976898 */   GIM_Try, /*On fail goto*//*Label 15392*/ GIMT_Encode4(976918), // Rule ID 4244 //
     /*  976903 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_iglp_opt),
     /*  976908 */     // MIs[0] mask
     /*  976908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  976911 */     // (intrinsic_void 2486:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask)  =>  (IGLP_OPT (timm:{ *:[i32] }):$mask)
     /*  976911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::IGLP_OPT),
     /*  976914 */     GIR_RootToRootCopy, /*OpIdx*/1, // mask
     /*  976916 */     GIR_RootConstrainSelectedInstOperands,
     /*  976917 */     // GIR_Coverage, 4244,
     /*  976917 */     GIR_EraseRootFromParent_Done,
     /*  976918 */   // Label 15392: @976918
     /*  976918 */   GIM_Try, /*On fail goto*//*Label 15393*/ GIMT_Encode4(976941), // Rule ID 4266 //
     /*  976923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_init_exec),
     /*  976928 */     // MIs[0] src
     /*  976928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  976931 */     // (intrinsic_void 3250:{ *:[iPTR] }, (timm:{ *:[i64] }):$src)  =>  (SI_INIT_EXEC (timm:{ *:[i64] }):$src)
     /*  976931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_EXEC),
     /*  976934 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  976936 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  976939 */     GIR_RootConstrainSelectedInstOperands,
     /*  976940 */     // GIR_Coverage, 4266,
     /*  976940 */     GIR_EraseRootFromParent_Done,
     /*  976941 */   // Label 15393: @976941
     /*  976941 */   GIM_Try, /*On fail goto*//*Label 15394*/ GIMT_Encode4(976971), // Rule ID 4268 //
     /*  976946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  976949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_init_whole_wave),
     /*  976954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  976957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  976961 */     // (intrinsic_w_chain:{ *:[i1] } 3252:{ *:[iPTR] })  =>  (SI_INIT_WHOLE_WAVE:{ *:[i1] })
     /*  976961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_WHOLE_WAVE),
     /*  976964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  976966 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  976969 */     GIR_RootConstrainSelectedInstOperands,
     /*  976970 */     // GIR_Coverage, 4268,
     /*  976970 */     GIR_EraseRootFromParent_Done,
     /*  976971 */   // Label 15394: @976971
     /*  976971 */   GIM_Try, /*On fail goto*//*Label 15395*/ GIMT_Encode4(977001), // Rule ID 4269 //
     /*  976976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  976979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_init_whole_wave),
     /*  976984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  976987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  976991 */     // (intrinsic_w_chain:{ *:[i1] } 3252:{ *:[iPTR] })  =>  (SI_INIT_WHOLE_WAVE:{ *:[i1] })
     /*  976991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_WHOLE_WAVE),
     /*  976994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  976996 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  976999 */     GIR_RootConstrainSelectedInstOperands,
     /*  977000 */     // GIR_Coverage, 4269,
     /*  977000 */     GIR_EraseRootFromParent_Done,
     /*  977001 */   // Label 15395: @977001
     /*  977001 */   GIM_Try, /*On fail goto*//*Label 15396*/ GIMT_Encode4(977031), // Rule ID 4270 //
     /*  977006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  977009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_init_whole_wave),
     /*  977014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  977017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  977021 */     // (intrinsic_w_chain:{ *:[i1] } 3252:{ *:[iPTR] })  =>  (SI_INIT_WHOLE_WAVE:{ *:[i1] })
     /*  977021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_WHOLE_WAVE),
     /*  977024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  977026 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  977029 */     GIR_RootConstrainSelectedInstOperands,
     /*  977030 */     // GIR_Coverage, 4270,
     /*  977030 */     GIR_EraseRootFromParent_Done,
     /*  977031 */   // Label 15396: @977031
     /*  977031 */   GIM_Try, /*On fail goto*//*Label 15397*/ GIMT_Encode4(977061), // Rule ID 4271 //
     /*  977036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  977039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_init_whole_wave),
     /*  977044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  977047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  977051 */     // (intrinsic_w_chain:{ *:[i1] } 3252:{ *:[iPTR] })  =>  (SI_INIT_WHOLE_WAVE:{ *:[i1] })
     /*  977051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_WHOLE_WAVE),
     /*  977054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  977056 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  977059 */     GIR_RootConstrainSelectedInstOperands,
     /*  977060 */     // GIR_Coverage, 4271,
     /*  977060 */     GIR_EraseRootFromParent_Done,
     /*  977061 */   // Label 15397: @977061
     /*  977061 */   GIM_Try, /*On fail goto*//*Label 15398*/ GIMT_Encode4(977091), // Rule ID 4272 //
     /*  977066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  977069 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_init_whole_wave),
     /*  977074 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  977077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  977081 */     // (intrinsic_w_chain:{ *:[i1] } 3252:{ *:[iPTR] })  =>  (SI_INIT_WHOLE_WAVE:{ *:[i1] })
     /*  977081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_WHOLE_WAVE),
     /*  977084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  977086 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  977089 */     GIR_RootConstrainSelectedInstOperands,
     /*  977090 */     // GIR_Coverage, 4272,
     /*  977090 */     GIR_EraseRootFromParent_Done,
     /*  977091 */   // Label 15398: @977091
     /*  977091 */   GIM_Try, /*On fail goto*//*Label 15399*/ GIMT_Encode4(977109), // Rule ID 184 //
     /*  977096 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_leave),
     /*  977101 */     // MIs[0] Operand 1
     /*  977101 */     // No operand predicates
     /*  977101 */     // (intrinsic_void 3425:{ *:[iPTR] }, srcvalue:{ *:[i16] })  =>  (S_BARRIER_LEAVE:{ *:[i1] })
     /*  977101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_LEAVE),
     /*  977104 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  977107 */     GIR_RootConstrainSelectedInstOperands,
     /*  977108 */     // GIR_Coverage, 184,
     /*  977108 */     GIR_EraseRootFromParent_Done,
     /*  977109 */   // Label 15399: @977109
     /*  977109 */   GIM_Reject,
     /*  977110 */ // Label 15387: @977110
     /*  977110 */ GIM_Try, /*On fail goto*//*Label 15400*/ GIMT_Encode4(983861),
     /*  977115 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*  977118 */   GIM_Try, /*On fail goto*//*Label 15401*/ GIMT_Encode4(977173), // Rule ID 31041 //
     /*  977123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode0),
     /*  977126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr4_b64),
     /*  977131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977138 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977142 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977149 */     // (intrinsic_w_chain:{ *:[v2i32] } 2423:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR4_B64),
     /*  977152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977171 */     GIR_RootConstrainSelectedInstOperands,
     /*  977172 */     // GIR_Coverage, 31041,
     /*  977172 */     GIR_EraseRootFromParent_Done,
     /*  977173 */   // Label 15401: @977173
     /*  977173 */   GIM_Try, /*On fail goto*//*Label 15402*/ GIMT_Encode4(977228), // Rule ID 31042 //
     /*  977178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode1),
     /*  977181 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr4_b64),
     /*  977186 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977197 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977204 */     // (intrinsic_w_chain:{ *:[v2i32] } 2423:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR4_B64),
     /*  977207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977226 */     GIR_RootConstrainSelectedInstOperands,
     /*  977227 */     // GIR_Coverage, 31042,
     /*  977227 */     GIR_EraseRootFromParent_Done,
     /*  977228 */   // Label 15402: @977228
     /*  977228 */   GIM_Try, /*On fail goto*//*Label 15403*/ GIMT_Encode4(977283), // Rule ID 31043 //
     /*  977233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode2),
     /*  977236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr4_b64),
     /*  977241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977259 */     // (intrinsic_w_chain:{ *:[v2i32] } 2423:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR4_B64),
     /*  977262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977274 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977277 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977281 */     GIR_RootConstrainSelectedInstOperands,
     /*  977282 */     // GIR_Coverage, 31043,
     /*  977282 */     GIR_EraseRootFromParent_Done,
     /*  977283 */   // Label 15403: @977283
     /*  977283 */   GIM_Try, /*On fail goto*//*Label 15404*/ GIMT_Encode4(977338), // Rule ID 31044 //
     /*  977288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode3),
     /*  977291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr4_b64),
     /*  977296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977307 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977314 */     // (intrinsic_w_chain:{ *:[v2i32] } 2423:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR4_B64),
     /*  977317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977329 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977332 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977336 */     GIR_RootConstrainSelectedInstOperands,
     /*  977337 */     // GIR_Coverage, 31044,
     /*  977337 */     GIR_EraseRootFromParent_Done,
     /*  977338 */   // Label 15404: @977338
     /*  977338 */   GIM_Try, /*On fail goto*//*Label 15405*/ GIMT_Encode4(977393), // Rule ID 31045 //
     /*  977343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32_HwMode4),
     /*  977346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr4_b64),
     /*  977351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977369 */     // (intrinsic_w_chain:{ *:[v2i32] } 2423:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR4_B64),
     /*  977372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977379 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977384 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977387 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977391 */     GIR_RootConstrainSelectedInstOperands,
     /*  977392 */     // GIR_Coverage, 31045,
     /*  977392 */     GIR_EraseRootFromParent_Done,
     /*  977393 */   // Label 15405: @977393
     /*  977393 */   GIM_Try, /*On fail goto*//*Label 15406*/ GIMT_Encode4(977448), // Rule ID 31046 //
     /*  977398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isGFX1250Plus_isWave32),
     /*  977401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr6_b96),
     /*  977406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  977409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  977413 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977417 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977424 */     // (intrinsic_w_chain:{ *:[v3i32] } 2424:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR6_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR6_B96),
     /*  977427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977439 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977446 */     GIR_RootConstrainSelectedInstOperands,
     /*  977447 */     // GIR_Coverage, 31046,
     /*  977447 */     GIR_EraseRootFromParent_Done,
     /*  977448 */   // Label 15406: @977448
     /*  977448 */   GIM_Try, /*On fail goto*//*Label 15407*/ GIMT_Encode4(977503), // Rule ID 31047 //
     /*  977453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  977456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr8_b64),
     /*  977461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977472 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977479 */     // (intrinsic_w_chain:{ *:[v2i32] } 2425:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR8_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR8_B64),
     /*  977482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977489 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977501 */     GIR_RootConstrainSelectedInstOperands,
     /*  977502 */     // GIR_Coverage, 31047,
     /*  977502 */     GIR_EraseRootFromParent_Done,
     /*  977503 */   // Label 15407: @977503
     /*  977503 */   GIM_Try, /*On fail goto*//*Label 15408*/ GIMT_Encode4(977558), // Rule ID 31048 //
     /*  977508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  977511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr8_b64),
     /*  977516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977523 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977534 */     // (intrinsic_w_chain:{ *:[v2i32] } 2425:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR8_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR8_B64),
     /*  977537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977549 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977552 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977556 */     GIR_RootConstrainSelectedInstOperands,
     /*  977557 */     // GIR_Coverage, 31048,
     /*  977557 */     GIR_EraseRootFromParent_Done,
     /*  977558 */   // Label 15408: @977558
     /*  977558 */   GIM_Try, /*On fail goto*//*Label 15409*/ GIMT_Encode4(977613), // Rule ID 31049 //
     /*  977563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  977566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr8_b64),
     /*  977571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977578 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977589 */     // (intrinsic_w_chain:{ *:[v2i32] } 2425:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR8_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR8_B64),
     /*  977592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977611 */     GIR_RootConstrainSelectedInstOperands,
     /*  977612 */     // GIR_Coverage, 31049,
     /*  977612 */     GIR_EraseRootFromParent_Done,
     /*  977613 */   // Label 15409: @977613
     /*  977613 */   GIM_Try, /*On fail goto*//*Label 15410*/ GIMT_Encode4(977668), // Rule ID 31050 //
     /*  977618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  977621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr8_b64),
     /*  977626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977633 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977637 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977644 */     // (intrinsic_w_chain:{ *:[v2i32] } 2425:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR8_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR8_B64),
     /*  977647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977662 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977666 */     GIR_RootConstrainSelectedInstOperands,
     /*  977667 */     // GIR_Coverage, 31050,
     /*  977667 */     GIR_EraseRootFromParent_Done,
     /*  977668 */   // Label 15410: @977668
     /*  977668 */   GIM_Try, /*On fail goto*//*Label 15411*/ GIMT_Encode4(977723), // Rule ID 31051 //
     /*  977673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  977676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr8_b64),
     /*  977681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  977684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  977688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977692 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977699 */     // (intrinsic_w_chain:{ *:[v2i32] } 2425:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR8_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR8_B64),
     /*  977702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977714 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977717 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977721 */     GIR_RootConstrainSelectedInstOperands,
     /*  977722 */     // GIR_Coverage, 31051,
     /*  977722 */     GIR_EraseRootFromParent_Done,
     /*  977723 */   // Label 15411: @977723
     /*  977723 */   GIM_Try, /*On fail goto*//*Label 15412*/ GIMT_Encode4(977778), // Rule ID 31052 //
     /*  977728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  977731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  977736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  977739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  977743 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977747 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977754 */     // (intrinsic_w_chain:{ *:[v8i16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  977757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977764 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977769 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977772 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977776 */     GIR_RootConstrainSelectedInstOperands,
     /*  977777 */     // GIR_Coverage, 31052,
     /*  977777 */     GIR_EraseRootFromParent_Done,
     /*  977778 */   // Label 15412: @977778
     /*  977778 */   GIM_Try, /*On fail goto*//*Label 15413*/ GIMT_Encode4(977833), // Rule ID 31053 //
     /*  977783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  977786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  977791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  977794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  977798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977802 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977809 */     // (intrinsic_w_chain:{ *:[v8i16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  977812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977819 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977831 */     GIR_RootConstrainSelectedInstOperands,
     /*  977832 */     // GIR_Coverage, 31053,
     /*  977832 */     GIR_EraseRootFromParent_Done,
     /*  977833 */   // Label 15413: @977833
     /*  977833 */   GIM_Try, /*On fail goto*//*Label 15414*/ GIMT_Encode4(977888), // Rule ID 31054 //
     /*  977838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  977841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  977846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  977849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  977853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977864 */     // (intrinsic_w_chain:{ *:[v8i16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  977867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977886 */     GIR_RootConstrainSelectedInstOperands,
     /*  977887 */     // GIR_Coverage, 31054,
     /*  977887 */     GIR_EraseRootFromParent_Done,
     /*  977888 */   // Label 15414: @977888
     /*  977888 */   GIM_Try, /*On fail goto*//*Label 15415*/ GIMT_Encode4(977943), // Rule ID 31055 //
     /*  977893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  977896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  977901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  977904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  977908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977919 */     // (intrinsic_w_chain:{ *:[v8i16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  977922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977941 */     GIR_RootConstrainSelectedInstOperands,
     /*  977942 */     // GIR_Coverage, 31055,
     /*  977942 */     GIR_EraseRootFromParent_Done,
     /*  977943 */   // Label 15415: @977943
     /*  977943 */   GIM_Try, /*On fail goto*//*Label 15416*/ GIMT_Encode4(977998), // Rule ID 31056 //
     /*  977948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  977951 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  977956 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  977959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  977963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  977967 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  977974 */     // (intrinsic_w_chain:{ *:[v8i16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  977974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  977977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  977979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  977984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  977989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  977992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  977996 */     GIR_RootConstrainSelectedInstOperands,
     /*  977997 */     // GIR_Coverage, 31056,
     /*  977997 */     GIR_EraseRootFromParent_Done,
     /*  977998 */   // Label 15416: @977998
     /*  977998 */   GIM_Try, /*On fail goto*//*Label 15417*/ GIMT_Encode4(978053), // Rule ID 31057 //
     /*  978003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode0),
     /*  978006 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  978011 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  978014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  978018 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978029 */     // (intrinsic_w_chain:{ *:[v8f16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  978032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978047 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978051 */     GIR_RootConstrainSelectedInstOperands,
     /*  978052 */     // GIR_Coverage, 31057,
     /*  978052 */     GIR_EraseRootFromParent_Done,
     /*  978053 */   // Label 15417: @978053
     /*  978053 */   GIM_Try, /*On fail goto*//*Label 15418*/ GIMT_Encode4(978108), // Rule ID 31058 //
     /*  978058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode1),
     /*  978061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  978066 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  978069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  978073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978084 */     // (intrinsic_w_chain:{ *:[v8f16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  978087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978106 */     GIR_RootConstrainSelectedInstOperands,
     /*  978107 */     // GIR_Coverage, 31058,
     /*  978107 */     GIR_EraseRootFromParent_Done,
     /*  978108 */   // Label 15418: @978108
     /*  978108 */   GIM_Try, /*On fail goto*//*Label 15419*/ GIMT_Encode4(978163), // Rule ID 31059 //
     /*  978113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode2),
     /*  978116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  978121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  978124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  978128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978139 */     // (intrinsic_w_chain:{ *:[v8f16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  978142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978161 */     GIR_RootConstrainSelectedInstOperands,
     /*  978162 */     // GIR_Coverage, 31059,
     /*  978162 */     GIR_EraseRootFromParent_Done,
     /*  978163 */   // Label 15419: @978163
     /*  978163 */   GIM_Try, /*On fail goto*//*Label 15420*/ GIMT_Encode4(978218), // Rule ID 31060 //
     /*  978168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode3),
     /*  978171 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  978176 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  978179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  978183 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978187 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978194 */     // (intrinsic_w_chain:{ *:[v8f16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  978197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978209 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978212 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978216 */     GIR_RootConstrainSelectedInstOperands,
     /*  978217 */     // GIR_Coverage, 31060,
     /*  978217 */     GIR_EraseRootFromParent_Done,
     /*  978218 */   // Label 15420: @978218
     /*  978218 */   GIM_Try, /*On fail goto*//*Label 15421*/ GIMT_Encode4(978273), // Rule ID 31061 //
     /*  978223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_isWave32_HwMode4),
     /*  978226 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_load_tr16_b128),
     /*  978231 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  978234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  978238 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978242 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978249 */     // (intrinsic_w_chain:{ *:[v8f16] } 2422:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_LOAD_TR16_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_LOAD_TR16_B128),
     /*  978252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978267 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978271 */     GIR_RootConstrainSelectedInstOperands,
     /*  978272 */     // GIR_Coverage, 31061,
     /*  978272 */     GIR_EraseRootFromParent_Done,
     /*  978273 */   // Label 15421: @978273
     /*  978273 */   GIM_Try, /*On fail goto*//*Label 15422*/ GIMT_Encode4(978328), // Rule ID 31062 //
     /*  978278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  978281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr4_b64),
     /*  978286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978297 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978304 */     // (intrinsic_w_chain:{ *:[v2i32] } 2430:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B4:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B4),
     /*  978307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978319 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978326 */     GIR_RootConstrainSelectedInstOperands,
     /*  978327 */     // GIR_Coverage, 31062,
     /*  978327 */     GIR_EraseRootFromParent_Done,
     /*  978328 */   // Label 15422: @978328
     /*  978328 */   GIM_Try, /*On fail goto*//*Label 15423*/ GIMT_Encode4(978383), // Rule ID 31063 //
     /*  978333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  978336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr4_b64),
     /*  978341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978359 */     // (intrinsic_w_chain:{ *:[v2i32] } 2430:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B4:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B4),
     /*  978362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978381 */     GIR_RootConstrainSelectedInstOperands,
     /*  978382 */     // GIR_Coverage, 31063,
     /*  978382 */     GIR_EraseRootFromParent_Done,
     /*  978383 */   // Label 15423: @978383
     /*  978383 */   GIM_Try, /*On fail goto*//*Label 15424*/ GIMT_Encode4(978438), // Rule ID 31064 //
     /*  978388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  978391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr4_b64),
     /*  978396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978403 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978407 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978414 */     // (intrinsic_w_chain:{ *:[v2i32] } 2430:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B4:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B4),
     /*  978417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978429 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978436 */     GIR_RootConstrainSelectedInstOperands,
     /*  978437 */     // GIR_Coverage, 31064,
     /*  978437 */     GIR_EraseRootFromParent_Done,
     /*  978438 */   // Label 15424: @978438
     /*  978438 */   GIM_Try, /*On fail goto*//*Label 15425*/ GIMT_Encode4(978493), // Rule ID 31065 //
     /*  978443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  978446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr4_b64),
     /*  978451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978458 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978462 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978469 */     // (intrinsic_w_chain:{ *:[v2i32] } 2430:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B4:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B4),
     /*  978472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978484 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978487 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978491 */     GIR_RootConstrainSelectedInstOperands,
     /*  978492 */     // GIR_Coverage, 31065,
     /*  978492 */     GIR_EraseRootFromParent_Done,
     /*  978493 */   // Label 15425: @978493
     /*  978493 */   GIM_Try, /*On fail goto*//*Label 15426*/ GIMT_Encode4(978548), // Rule ID 31066 //
     /*  978498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  978501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr4_b64),
     /*  978506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978517 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978524 */     // (intrinsic_w_chain:{ *:[v2i32] } 2430:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B4:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B4),
     /*  978527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978542 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978546 */     GIR_RootConstrainSelectedInstOperands,
     /*  978547 */     // GIR_Coverage, 31066,
     /*  978547 */     GIR_EraseRootFromParent_Done,
     /*  978548 */   // Label 15426: @978548
     /*  978548 */   GIM_Try, /*On fail goto*//*Label 15427*/ GIMT_Encode4(978603), // Rule ID 31067 //
     /*  978553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  978556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr8_b64),
     /*  978561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978572 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978579 */     // (intrinsic_w_chain:{ *:[v2i32] } 2432:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B8:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B8),
     /*  978582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978601 */     GIR_RootConstrainSelectedInstOperands,
     /*  978602 */     // GIR_Coverage, 31067,
     /*  978602 */     GIR_EraseRootFromParent_Done,
     /*  978603 */   // Label 15427: @978603
     /*  978603 */   GIM_Try, /*On fail goto*//*Label 15428*/ GIMT_Encode4(978658), // Rule ID 31068 //
     /*  978608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  978611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr8_b64),
     /*  978616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978623 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978627 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978634 */     // (intrinsic_w_chain:{ *:[v2i32] } 2432:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B8:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B8),
     /*  978637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978656 */     GIR_RootConstrainSelectedInstOperands,
     /*  978657 */     // GIR_Coverage, 31068,
     /*  978657 */     GIR_EraseRootFromParent_Done,
     /*  978658 */   // Label 15428: @978658
     /*  978658 */   GIM_Try, /*On fail goto*//*Label 15429*/ GIMT_Encode4(978713), // Rule ID 31069 //
     /*  978663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  978666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr8_b64),
     /*  978671 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978682 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978689 */     // (intrinsic_w_chain:{ *:[v2i32] } 2432:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B8:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B8),
     /*  978692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978704 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978711 */     GIR_RootConstrainSelectedInstOperands,
     /*  978712 */     // GIR_Coverage, 31069,
     /*  978712 */     GIR_EraseRootFromParent_Done,
     /*  978713 */   // Label 15429: @978713
     /*  978713 */   GIM_Try, /*On fail goto*//*Label 15430*/ GIMT_Encode4(978768), // Rule ID 31070 //
     /*  978718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  978721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr8_b64),
     /*  978726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978733 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978737 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978744 */     // (intrinsic_w_chain:{ *:[v2i32] } 2432:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B8:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B8),
     /*  978747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978749 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978762 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978766 */     GIR_RootConstrainSelectedInstOperands,
     /*  978767 */     // GIR_Coverage, 31070,
     /*  978767 */     GIR_EraseRootFromParent_Done,
     /*  978768 */   // Label 15430: @978768
     /*  978768 */   GIM_Try, /*On fail goto*//*Label 15431*/ GIMT_Encode4(978823), // Rule ID 31071 //
     /*  978773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  978776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr8_b64),
     /*  978781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  978784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  978788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978792 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978799 */     // (intrinsic_w_chain:{ *:[v2i32] } 2432:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B8:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B8),
     /*  978802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978814 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978821 */     GIR_RootConstrainSelectedInstOperands,
     /*  978822 */     // GIR_Coverage, 31071,
     /*  978822 */     GIR_EraseRootFromParent_Done,
     /*  978823 */   // Label 15431: @978823
     /*  978823 */   GIM_Try, /*On fail goto*//*Label 15432*/ GIMT_Encode4(978878), // Rule ID 31072 //
     /*  978828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  978831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr6_b96),
     /*  978836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  978839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  978843 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978847 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978854 */     // (intrinsic_w_chain:{ *:[v3i32] } 2431:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B96_TR_B6:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_TR_B6),
     /*  978857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978859 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978876 */     GIR_RootConstrainSelectedInstOperands,
     /*  978877 */     // GIR_Coverage, 31072,
     /*  978877 */     GIR_EraseRootFromParent_Done,
     /*  978878 */   // Label 15432: @978878
     /*  978878 */   GIM_Try, /*On fail goto*//*Label 15433*/ GIMT_Encode4(978933), // Rule ID 31073 //
     /*  978883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  978886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr6_b96),
     /*  978891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  978894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  978898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978909 */     // (intrinsic_w_chain:{ *:[v3i32] } 2431:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B96_TR_B6:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_TR_B6),
     /*  978912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978924 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978927 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978931 */     GIR_RootConstrainSelectedInstOperands,
     /*  978932 */     // GIR_Coverage, 31073,
     /*  978932 */     GIR_EraseRootFromParent_Done,
     /*  978933 */   // Label 15433: @978933
     /*  978933 */   GIM_Try, /*On fail goto*//*Label 15434*/ GIMT_Encode4(978988), // Rule ID 31074 //
     /*  978938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  978941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr6_b96),
     /*  978946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  978949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  978953 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  978957 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  978964 */     // (intrinsic_w_chain:{ *:[v3i32] } 2431:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B96_TR_B6:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  978964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_TR_B6),
     /*  978967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  978969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  978974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  978979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  978982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  978986 */     GIR_RootConstrainSelectedInstOperands,
     /*  978987 */     // GIR_Coverage, 31074,
     /*  978987 */     GIR_EraseRootFromParent_Done,
     /*  978988 */   // Label 15434: @978988
     /*  978988 */   GIM_Try, /*On fail goto*//*Label 15435*/ GIMT_Encode4(979043), // Rule ID 31075 //
     /*  978993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  978996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr6_b96),
     /*  979001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  979004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  979008 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979012 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979019 */     // (intrinsic_w_chain:{ *:[v3i32] } 2431:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B96_TR_B6:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_TR_B6),
     /*  979022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979037 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979041 */     GIR_RootConstrainSelectedInstOperands,
     /*  979042 */     // GIR_Coverage, 31075,
     /*  979042 */     GIR_EraseRootFromParent_Done,
     /*  979043 */   // Label 15435: @979043
     /*  979043 */   GIM_Try, /*On fail goto*//*Label 15436*/ GIMT_Encode4(979098), // Rule ID 31076 //
     /*  979048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  979051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr6_b96),
     /*  979056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  979059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  979063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979074 */     // (intrinsic_w_chain:{ *:[v3i32] } 2431:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B96_TR_B6:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_TR_B6),
     /*  979077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979089 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979096 */     GIR_RootConstrainSelectedInstOperands,
     /*  979097 */     // GIR_Coverage, 31076,
     /*  979097 */     GIR_EraseRootFromParent_Done,
     /*  979098 */   // Label 15436: @979098
     /*  979098 */   GIM_Try, /*On fail goto*//*Label 15437*/ GIMT_Encode4(979153), // Rule ID 31077 //
     /*  979103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  979106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979118 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979122 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979129 */     // (intrinsic_w_chain:{ *:[v4i16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979139 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979144 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979147 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979151 */     GIR_RootConstrainSelectedInstOperands,
     /*  979152 */     // GIR_Coverage, 31077,
     /*  979152 */     GIR_EraseRootFromParent_Done,
     /*  979153 */   // Label 15437: @979153
     /*  979153 */   GIM_Try, /*On fail goto*//*Label 15438*/ GIMT_Encode4(979208), // Rule ID 31078 //
     /*  979158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  979161 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979166 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979184 */     // (intrinsic_w_chain:{ *:[v4i16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979206 */     GIR_RootConstrainSelectedInstOperands,
     /*  979207 */     // GIR_Coverage, 31078,
     /*  979207 */     GIR_EraseRootFromParent_Done,
     /*  979208 */   // Label 15438: @979208
     /*  979208 */   GIM_Try, /*On fail goto*//*Label 15439*/ GIMT_Encode4(979263), // Rule ID 31079 //
     /*  979213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  979216 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979221 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979228 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979232 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979239 */     // (intrinsic_w_chain:{ *:[v4i16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979261 */     GIR_RootConstrainSelectedInstOperands,
     /*  979262 */     // GIR_Coverage, 31079,
     /*  979262 */     GIR_EraseRootFromParent_Done,
     /*  979263 */   // Label 15439: @979263
     /*  979263 */   GIM_Try, /*On fail goto*//*Label 15440*/ GIMT_Encode4(979318), // Rule ID 31080 //
     /*  979268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  979271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979294 */     // (intrinsic_w_chain:{ *:[v4i16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979309 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979316 */     GIR_RootConstrainSelectedInstOperands,
     /*  979317 */     // GIR_Coverage, 31080,
     /*  979317 */     GIR_EraseRootFromParent_Done,
     /*  979318 */   // Label 15440: @979318
     /*  979318 */   GIM_Try, /*On fail goto*//*Label 15441*/ GIMT_Encode4(979373), // Rule ID 31081 //
     /*  979323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  979326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979338 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979349 */     // (intrinsic_w_chain:{ *:[v4i16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979367 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979371 */     GIR_RootConstrainSelectedInstOperands,
     /*  979372 */     // GIR_Coverage, 31081,
     /*  979372 */     GIR_EraseRootFromParent_Done,
     /*  979373 */   // Label 15441: @979373
     /*  979373 */   GIM_Try, /*On fail goto*//*Label 15442*/ GIMT_Encode4(979428), // Rule ID 31082 //
     /*  979378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode0),
     /*  979381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979404 */     // (intrinsic_w_chain:{ *:[v4f16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979419 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979426 */     GIR_RootConstrainSelectedInstOperands,
     /*  979427 */     // GIR_Coverage, 31082,
     /*  979427 */     GIR_EraseRootFromParent_Done,
     /*  979428 */   // Label 15442: @979428
     /*  979428 */   GIM_Try, /*On fail goto*//*Label 15443*/ GIMT_Encode4(979483), // Rule ID 31083 //
     /*  979433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode1),
     /*  979436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979459 */     // (intrinsic_w_chain:{ *:[v4f16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979474 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979481 */     GIR_RootConstrainSelectedInstOperands,
     /*  979482 */     // GIR_Coverage, 31083,
     /*  979482 */     GIR_EraseRootFromParent_Done,
     /*  979483 */   // Label 15443: @979483
     /*  979483 */   GIM_Try, /*On fail goto*//*Label 15444*/ GIMT_Encode4(979538), // Rule ID 31084 //
     /*  979488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode2),
     /*  979491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979503 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979507 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979514 */     // (intrinsic_w_chain:{ *:[v4f16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979529 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979532 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979536 */     GIR_RootConstrainSelectedInstOperands,
     /*  979537 */     // GIR_Coverage, 31084,
     /*  979537 */     GIR_EraseRootFromParent_Done,
     /*  979538 */   // Label 15444: @979538
     /*  979538 */   GIM_Try, /*On fail goto*//*Label 15445*/ GIMT_Encode4(979593), // Rule ID 31085 //
     /*  979543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode3),
     /*  979546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979569 */     // (intrinsic_w_chain:{ *:[v4f16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979584 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979587 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979591 */     GIR_RootConstrainSelectedInstOperands,
     /*  979592 */     // GIR_Coverage, 31085,
     /*  979592 */     GIR_EraseRootFromParent_Done,
     /*  979593 */   // Label 15445: @979593
     /*  979593 */   GIM_Try, /*On fail goto*//*Label 15446*/ GIMT_Encode4(979648), // Rule ID 31086 //
     /*  979598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX950Insts_HwMode4),
     /*  979601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_read_tr16_b64),
     /*  979606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  979609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979613 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  979624 */     // (intrinsic_w_chain:{ *:[v4f16] } 2429:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))  =>  (DS_READ_B64_TR_B16:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  979624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_TR_B16),
     /*  979627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  979634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  979639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  979642 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979646 */     GIR_RootConstrainSelectedInstOperands,
     /*  979647 */     // GIR_Coverage, 31086,
     /*  979647 */     GIR_EraseRootFromParent_Done,
     /*  979648 */   // Label 15446: @979648
     /*  979648 */   GIM_Try, /*On fail goto*//*Label 15447*/ GIMT_Encode4(979710), // Rule ID 13387 //
     /*  979653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode0),
     /*  979656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  979661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  979664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979668 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979672 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  979679 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  979679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR),
     /*  979682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  979689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  979694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  979699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  979704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979708 */     GIR_RootConstrainSelectedInstOperands,
     /*  979709 */     // GIR_Coverage, 13387,
     /*  979709 */     GIR_EraseRootFromParent_Done,
     /*  979710 */   // Label 15447: @979710
     /*  979710 */   GIM_Try, /*On fail goto*//*Label 15448*/ GIMT_Encode4(979772), // Rule ID 13388 //
     /*  979715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode1),
     /*  979718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  979723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  979726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979730 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  979741 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  979741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR),
     /*  979744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  979751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  979756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  979761 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  979766 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979770 */     GIR_RootConstrainSelectedInstOperands,
     /*  979771 */     // GIR_Coverage, 13388,
     /*  979771 */     GIR_EraseRootFromParent_Done,
     /*  979772 */   // Label 15448: @979772
     /*  979772 */   GIM_Try, /*On fail goto*//*Label 15449*/ GIMT_Encode4(979834), // Rule ID 13389 //
     /*  979777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode2),
     /*  979780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  979785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  979788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979792 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979796 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  979803 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  979803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR),
     /*  979806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  979813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  979818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  979823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  979828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979832 */     GIR_RootConstrainSelectedInstOperands,
     /*  979833 */     // GIR_Coverage, 13389,
     /*  979833 */     GIR_EraseRootFromParent_Done,
     /*  979834 */   // Label 15449: @979834
     /*  979834 */   GIM_Try, /*On fail goto*//*Label 15450*/ GIMT_Encode4(979896), // Rule ID 13390 //
     /*  979839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode3),
     /*  979842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  979847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  979850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979854 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979858 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  979865 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  979865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR),
     /*  979868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  979875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  979880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  979885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  979890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979894 */     GIR_RootConstrainSelectedInstOperands,
     /*  979895 */     // GIR_Coverage, 13390,
     /*  979895 */     GIR_EraseRootFromParent_Done,
     /*  979896 */   // Label 15450: @979896
     /*  979896 */   GIM_Try, /*On fail goto*//*Label 15451*/ GIMT_Encode4(979958), // Rule ID 13391 //
     /*  979901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode4),
     /*  979904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  979909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  979912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  979916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979920 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  979927 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  979927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR),
     /*  979930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  979937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  979942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  979947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  979952 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  979956 */     GIR_RootConstrainSelectedInstOperands,
     /*  979957 */     // GIR_Coverage, 13391,
     /*  979957 */     GIR_EraseRootFromParent_Done,
     /*  979958 */   // Label 15451: @979958
     /*  979958 */   GIM_Try, /*On fail goto*//*Label 15452*/ GIMT_Encode4(980020), // Rule ID 13397 //
     /*  979963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode0),
     /*  979966 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  979971 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  979974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  979978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  979982 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  979989 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  979989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  979992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  979994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  979999 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980018 */     GIR_RootConstrainSelectedInstOperands,
     /*  980019 */     // GIR_Coverage, 13397,
     /*  980019 */     GIR_EraseRootFromParent_Done,
     /*  980020 */   // Label 15452: @980020
     /*  980020 */   GIM_Try, /*On fail goto*//*Label 15453*/ GIMT_Encode4(980082), // Rule ID 13398 //
     /*  980025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode1),
     /*  980028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980040 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980044 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980051 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980076 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980080 */     GIR_RootConstrainSelectedInstOperands,
     /*  980081 */     // GIR_Coverage, 13398,
     /*  980081 */     GIR_EraseRootFromParent_Done,
     /*  980082 */   // Label 15453: @980082
     /*  980082 */   GIM_Try, /*On fail goto*//*Label 15454*/ GIMT_Encode4(980144), // Rule ID 13399 //
     /*  980087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode2),
     /*  980090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980098 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980102 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980106 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980113 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980118 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980142 */     GIR_RootConstrainSelectedInstOperands,
     /*  980143 */     // GIR_Coverage, 13399,
     /*  980143 */     GIR_EraseRootFromParent_Done,
     /*  980144 */   // Label 15454: @980144
     /*  980144 */   GIM_Try, /*On fail goto*//*Label 15455*/ GIMT_Encode4(980206), // Rule ID 13400 //
     /*  980149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode3),
     /*  980152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980164 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980168 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980175 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980185 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980204 */     GIR_RootConstrainSelectedInstOperands,
     /*  980205 */     // GIR_Coverage, 13400,
     /*  980205 */     GIR_EraseRootFromParent_Done,
     /*  980206 */   // Label 15455: @980206
     /*  980206 */   GIM_Try, /*On fail goto*//*Label 15456*/ GIMT_Encode4(980268), // Rule ID 13401 //
     /*  980211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode4),
     /*  980214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980237 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980266 */     GIR_RootConstrainSelectedInstOperands,
     /*  980267 */     // GIR_Coverage, 13401,
     /*  980267 */     GIR_EraseRootFromParent_Done,
     /*  980268 */   // Label 15456: @980268
     /*  980268 */   GIM_Try, /*On fail goto*//*Label 15457*/ GIMT_Encode4(980330), // Rule ID 13407 //
     /*  980273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode0),
     /*  980276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980288 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980292 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980299 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980319 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980324 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980328 */     GIR_RootConstrainSelectedInstOperands,
     /*  980329 */     // GIR_Coverage, 13407,
     /*  980329 */     GIR_EraseRootFromParent_Done,
     /*  980330 */   // Label 15457: @980330
     /*  980330 */   GIM_Try, /*On fail goto*//*Label 15458*/ GIMT_Encode4(980392), // Rule ID 13408 //
     /*  980335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode1),
     /*  980338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980350 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980354 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980361 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980366 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980371 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980390 */     GIR_RootConstrainSelectedInstOperands,
     /*  980391 */     // GIR_Coverage, 13408,
     /*  980391 */     GIR_EraseRootFromParent_Done,
     /*  980392 */   // Label 15458: @980392
     /*  980392 */   GIM_Try, /*On fail goto*//*Label 15459*/ GIMT_Encode4(980454), // Rule ID 13409 //
     /*  980397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode2),
     /*  980400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980423 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980452 */     GIR_RootConstrainSelectedInstOperands,
     /*  980453 */     // GIR_Coverage, 13409,
     /*  980453 */     GIR_EraseRootFromParent_Done,
     /*  980454 */   // Label 15459: @980454
     /*  980454 */   GIM_Try, /*On fail goto*//*Label 15460*/ GIMT_Encode4(980516), // Rule ID 13410 //
     /*  980459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode3),
     /*  980462 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980467 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980478 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980485 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980490 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980495 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980500 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980510 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980514 */     GIR_RootConstrainSelectedInstOperands,
     /*  980515 */     // GIR_Coverage, 13410,
     /*  980515 */     GIR_EraseRootFromParent_Done,
     /*  980516 */   // Label 15460: @980516
     /*  980516 */   GIM_Try, /*On fail goto*//*Label 15461*/ GIMT_Encode4(980578), // Rule ID 13411 //
     /*  980521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode4),
     /*  980524 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980529 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  980532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  980536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980540 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980547 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
     /*  980550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980562 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980567 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980572 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980576 */     GIR_RootConstrainSelectedInstOperands,
     /*  980577 */     // GIR_Coverage, 13411,
     /*  980577 */     GIR_EraseRootFromParent_Done,
     /*  980578 */   // Label 15461: @980578
     /*  980578 */   GIM_Try, /*On fail goto*//*Label 15462*/ GIMT_Encode4(980640), // Rule ID 13417 //
     /*  980583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64),
     /*  980586 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  980591 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  980594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  980598 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980602 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980609 */     // (intrinsic_w_chain:{ *:[i32] } 2474:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B64_w64_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64_SADDR),
     /*  980612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980638 */     GIR_RootConstrainSelectedInstOperands,
     /*  980639 */     // GIR_Coverage, 13417,
     /*  980639 */     GIR_EraseRootFromParent_Done,
     /*  980640 */   // Label 15462: @980640
     /*  980640 */   GIM_Try, /*On fail goto*//*Label 15463*/ GIMT_Encode4(980702), // Rule ID 13423 //
     /*  980645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  980648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  980656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  980660 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980671 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  980674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980681 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980696 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980700 */     GIR_RootConstrainSelectedInstOperands,
     /*  980701 */     // GIR_Coverage, 13423,
     /*  980701 */     GIR_EraseRootFromParent_Done,
     /*  980702 */   // Label 15463: @980702
     /*  980702 */   GIM_Try, /*On fail goto*//*Label 15464*/ GIMT_Encode4(980764), // Rule ID 13424 //
     /*  980707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  980710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  980718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  980722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980733 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  980736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980758 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980762 */     GIR_RootConstrainSelectedInstOperands,
     /*  980763 */     // GIR_Coverage, 13424,
     /*  980763 */     GIR_EraseRootFromParent_Done,
     /*  980764 */   // Label 15464: @980764
     /*  980764 */   GIM_Try, /*On fail goto*//*Label 15465*/ GIMT_Encode4(980826), // Rule ID 13425 //
     /*  980769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  980772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  980780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  980784 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980788 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980795 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  980798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980815 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980824 */     GIR_RootConstrainSelectedInstOperands,
     /*  980825 */     // GIR_Coverage, 13425,
     /*  980825 */     GIR_EraseRootFromParent_Done,
     /*  980826 */   // Label 15465: @980826
     /*  980826 */   GIM_Try, /*On fail goto*//*Label 15466*/ GIMT_Encode4(980888), // Rule ID 13426 //
     /*  980831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  980834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  980842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  980846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980850 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980857 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  980860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980867 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980872 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980877 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980882 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980886 */     GIR_RootConstrainSelectedInstOperands,
     /*  980887 */     // GIR_Coverage, 13426,
     /*  980887 */     GIR_EraseRootFromParent_Done,
     /*  980888 */   // Label 15466: @980888
     /*  980888 */   GIM_Try, /*On fail goto*//*Label 15467*/ GIMT_Encode4(980950), // Rule ID 13427 //
     /*  980893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  980896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  980904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  980908 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980912 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980919 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  980922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  980939 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  980944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  980948 */     GIR_RootConstrainSelectedInstOperands,
     /*  980949 */     // GIR_Coverage, 13427,
     /*  980949 */     GIR_EraseRootFromParent_Done,
     /*  980950 */   // Label 15467: @980950
     /*  980950 */   GIM_Try, /*On fail goto*//*Label 15468*/ GIMT_Encode4(981012), // Rule ID 13433 //
     /*  980955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  980958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  980963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  980966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  980970 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  980974 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  980981 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  980981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  980984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  980986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  980991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  980996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981001 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981010 */     GIR_RootConstrainSelectedInstOperands,
     /*  981011 */     // GIR_Coverage, 13433,
     /*  981011 */     GIR_EraseRootFromParent_Done,
     /*  981012 */   // Label 15468: @981012
     /*  981012 */   GIM_Try, /*On fail goto*//*Label 15469*/ GIMT_Encode4(981074), // Rule ID 13434 //
     /*  981017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  981020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  981025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  981028 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981032 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981043 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  981046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981072 */     GIR_RootConstrainSelectedInstOperands,
     /*  981073 */     // GIR_Coverage, 13434,
     /*  981073 */     GIR_EraseRootFromParent_Done,
     /*  981074 */   // Label 15469: @981074
     /*  981074 */   GIM_Try, /*On fail goto*//*Label 15470*/ GIMT_Encode4(981136), // Rule ID 13435 //
     /*  981079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  981082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  981087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  981090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981094 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981105 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  981108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981134 */     GIR_RootConstrainSelectedInstOperands,
     /*  981135 */     // GIR_Coverage, 13435,
     /*  981135 */     GIR_EraseRootFromParent_Done,
     /*  981136 */   // Label 15470: @981136
     /*  981136 */   GIM_Try, /*On fail goto*//*Label 15471*/ GIMT_Encode4(981198), // Rule ID 13436 //
     /*  981141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  981144 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  981149 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  981152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981156 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981160 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981167 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  981170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981177 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981182 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981187 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981192 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981196 */     GIR_RootConstrainSelectedInstOperands,
     /*  981197 */     // GIR_Coverage, 13436,
     /*  981197 */     GIR_EraseRootFromParent_Done,
     /*  981198 */   // Label 15471: @981198
     /*  981198 */   GIM_Try, /*On fail goto*//*Label 15472*/ GIMT_Encode4(981260), // Rule ID 13437 //
     /*  981203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  981206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  981211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  981214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981222 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981229 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
     /*  981232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981258 */     GIR_RootConstrainSelectedInstOperands,
     /*  981259 */     // GIR_Coverage, 13437,
     /*  981259 */     GIR_EraseRootFromParent_Done,
     /*  981260 */   // Label 15472: @981260
     /*  981260 */   GIM_Try, /*On fail goto*//*Label 15473*/ GIMT_Encode4(981322), // Rule ID 13443 //
     /*  981265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode0),
     /*  981268 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  981273 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981280 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981284 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981291 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR4_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR),
     /*  981294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981320 */     GIR_RootConstrainSelectedInstOperands,
     /*  981321 */     // GIR_Coverage, 13443,
     /*  981321 */     GIR_EraseRootFromParent_Done,
     /*  981322 */   // Label 15473: @981322
     /*  981322 */   GIM_Try, /*On fail goto*//*Label 15474*/ GIMT_Encode4(981384), // Rule ID 13444 //
     /*  981327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode1),
     /*  981330 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  981335 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981342 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981346 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981353 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR4_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR),
     /*  981356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981363 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981382 */     GIR_RootConstrainSelectedInstOperands,
     /*  981383 */     // GIR_Coverage, 13444,
     /*  981383 */     GIR_EraseRootFromParent_Done,
     /*  981384 */   // Label 15474: @981384
     /*  981384 */   GIM_Try, /*On fail goto*//*Label 15475*/ GIMT_Encode4(981446), // Rule ID 13445 //
     /*  981389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode2),
     /*  981392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  981397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981415 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR4_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR),
     /*  981418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981435 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981440 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981444 */     GIR_RootConstrainSelectedInstOperands,
     /*  981445 */     // GIR_Coverage, 13445,
     /*  981445 */     GIR_EraseRootFromParent_Done,
     /*  981446 */   // Label 15475: @981446
     /*  981446 */   GIM_Try, /*On fail goto*//*Label 15476*/ GIMT_Encode4(981508), // Rule ID 13446 //
     /*  981451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode3),
     /*  981454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  981459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981466 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981470 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981477 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR4_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR),
     /*  981480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981492 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981506 */     GIR_RootConstrainSelectedInstOperands,
     /*  981507 */     // GIR_Coverage, 13446,
     /*  981507 */     GIR_EraseRootFromParent_Done,
     /*  981508 */   // Label 15476: @981508
     /*  981508 */   GIM_Try, /*On fail goto*//*Label 15477*/ GIMT_Encode4(981570), // Rule ID 13447 //
     /*  981513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode4),
     /*  981516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  981521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981539 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR4_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64_SADDR),
     /*  981542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981544 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981564 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981568 */     GIR_RootConstrainSelectedInstOperands,
     /*  981569 */     // GIR_Coverage, 13447,
     /*  981569 */     GIR_EraseRootFromParent_Done,
     /*  981570 */   // Label 15477: @981570
     /*  981570 */   GIM_Try, /*On fail goto*//*Label 15478*/ GIMT_Encode4(981632), // Rule ID 13453 //
     /*  981575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32),
     /*  981578 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr6_b96),
     /*  981583 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  981586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  981590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981594 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
     /*  981601 */     // (intrinsic_w_chain:{ *:[v3i32] } 2476:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol))  =>  (GLOBAL_LOAD_TR6_B96_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  981601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR6_B96_SADDR),
     /*  981604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  981611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  981616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  981621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  981626 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981630 */     GIR_RootConstrainSelectedInstOperands,
     /*  981631 */     // GIR_Coverage, 13453,
     /*  981631 */     GIR_EraseRootFromParent_Done,
     /*  981632 */   // Label 15478: @981632
     /*  981632 */   GIM_Try, /*On fail goto*//*Label 15479*/ GIMT_Encode4(981687), // Rule ID 13382 //
     /*  981637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode0),
     /*  981640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  981645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981663 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32),
     /*  981666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  981673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  981678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  981681 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981685 */     GIR_RootConstrainSelectedInstOperands,
     /*  981686 */     // GIR_Coverage, 13382,
     /*  981686 */     GIR_EraseRootFromParent_Done,
     /*  981687 */   // Label 15479: @981687
     /*  981687 */   GIM_Try, /*On fail goto*//*Label 15480*/ GIMT_Encode4(981742), // Rule ID 13383 //
     /*  981692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode1),
     /*  981695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  981700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981707 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981711 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981718 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32),
     /*  981721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  981728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  981733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  981736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981740 */     GIR_RootConstrainSelectedInstOperands,
     /*  981741 */     // GIR_Coverage, 13383,
     /*  981741 */     GIR_EraseRootFromParent_Done,
     /*  981742 */   // Label 15480: @981742
     /*  981742 */   GIM_Try, /*On fail goto*//*Label 15481*/ GIMT_Encode4(981797), // Rule ID 13384 //
     /*  981747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode2),
     /*  981750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  981755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981766 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981773 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32),
     /*  981776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  981783 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  981788 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  981791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981795 */     GIR_RootConstrainSelectedInstOperands,
     /*  981796 */     // GIR_Coverage, 13384,
     /*  981796 */     GIR_EraseRootFromParent_Done,
     /*  981797 */   // Label 15481: @981797
     /*  981797 */   GIM_Try, /*On fail goto*//*Label 15482*/ GIMT_Encode4(981852), // Rule ID 13385 //
     /*  981802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode3),
     /*  981805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  981810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981817 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981821 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981828 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32),
     /*  981831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  981838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  981843 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  981846 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981850 */     GIR_RootConstrainSelectedInstOperands,
     /*  981851 */     // GIR_Coverage, 13385,
     /*  981851 */     GIR_EraseRootFromParent_Done,
     /*  981852 */   // Label 15482: @981852
     /*  981852 */   GIM_Try, /*On fail goto*//*Label 15483*/ GIMT_Encode4(981907), // Rule ID 13386 //
     /*  981857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode4),
     /*  981860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  981865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  981868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  981872 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981883 */     // (intrinsic_w_chain:{ *:[v2i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32),
     /*  981886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  981893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  981898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  981901 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981905 */     GIR_RootConstrainSelectedInstOperands,
     /*  981906 */     // GIR_Coverage, 13386,
     /*  981906 */     GIR_EraseRootFromParent_Done,
     /*  981907 */   // Label 15483: @981907
     /*  981907 */   GIM_Try, /*On fail goto*//*Label 15484*/ GIMT_Encode4(981962), // Rule ID 13392 //
     /*  981912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode0),
     /*  981915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  981920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  981923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  981927 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981938 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  981941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  981948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  981953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  981956 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  981960 */     GIR_RootConstrainSelectedInstOperands,
     /*  981961 */     // GIR_Coverage, 13392,
     /*  981961 */     GIR_EraseRootFromParent_Done,
     /*  981962 */   // Label 15484: @981962
     /*  981962 */   GIM_Try, /*On fail goto*//*Label 15485*/ GIMT_Encode4(982017), // Rule ID 13393 //
     /*  981967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode1),
     /*  981970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  981975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  981978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  981982 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  981986 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  981993 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  981993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  981996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  981998 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982011 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982015 */     GIR_RootConstrainSelectedInstOperands,
     /*  982016 */     // GIR_Coverage, 13393,
     /*  982016 */     GIR_EraseRootFromParent_Done,
     /*  982017 */   // Label 15485: @982017
     /*  982017 */   GIM_Try, /*On fail goto*//*Label 15486*/ GIMT_Encode4(982072), // Rule ID 13394 //
     /*  982022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode2),
     /*  982025 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982030 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982037 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982041 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982048 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982066 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982070 */     GIR_RootConstrainSelectedInstOperands,
     /*  982071 */     // GIR_Coverage, 13394,
     /*  982071 */     GIR_EraseRootFromParent_Done,
     /*  982072 */   // Label 15486: @982072
     /*  982072 */   GIM_Try, /*On fail goto*//*Label 15487*/ GIMT_Encode4(982127), // Rule ID 13395 //
     /*  982077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode3),
     /*  982080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982092 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982096 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982103 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982108 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982113 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982118 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982121 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982125 */     GIR_RootConstrainSelectedInstOperands,
     /*  982126 */     // GIR_Coverage, 13395,
     /*  982126 */     GIR_EraseRootFromParent_Done,
     /*  982127 */   // Label 15487: @982127
     /*  982127 */   GIM_Try, /*On fail goto*//*Label 15488*/ GIMT_Encode4(982182), // Rule ID 13396 //
     /*  982132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode4),
     /*  982135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982147 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982158 */     // (intrinsic_w_chain:{ *:[v8i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982168 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982173 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982176 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982180 */     GIR_RootConstrainSelectedInstOperands,
     /*  982181 */     // GIR_Coverage, 13396,
     /*  982181 */     GIR_EraseRootFromParent_Done,
     /*  982182 */   // Label 15488: @982182
     /*  982182 */   GIM_Try, /*On fail goto*//*Label 15489*/ GIMT_Encode4(982237), // Rule ID 13402 //
     /*  982187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode0),
     /*  982190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982202 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982206 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982213 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982218 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982223 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982231 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982235 */     GIR_RootConstrainSelectedInstOperands,
     /*  982236 */     // GIR_Coverage, 13402,
     /*  982236 */     GIR_EraseRootFromParent_Done,
     /*  982237 */   // Label 15489: @982237
     /*  982237 */   GIM_Try, /*On fail goto*//*Label 15490*/ GIMT_Encode4(982292), // Rule ID 13403 //
     /*  982242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode1),
     /*  982245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982257 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982261 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982268 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982273 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982278 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982283 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982286 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982290 */     GIR_RootConstrainSelectedInstOperands,
     /*  982291 */     // GIR_Coverage, 13403,
     /*  982291 */     GIR_EraseRootFromParent_Done,
     /*  982292 */   // Label 15490: @982292
     /*  982292 */   GIM_Try, /*On fail goto*//*Label 15491*/ GIMT_Encode4(982347), // Rule ID 13404 //
     /*  982297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode2),
     /*  982300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982312 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982316 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982323 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982345 */     GIR_RootConstrainSelectedInstOperands,
     /*  982346 */     // GIR_Coverage, 13404,
     /*  982346 */     GIR_EraseRootFromParent_Done,
     /*  982347 */   // Label 15491: @982347
     /*  982347 */   GIM_Try, /*On fail goto*//*Label 15492*/ GIMT_Encode4(982402), // Rule ID 13405 //
     /*  982352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode3),
     /*  982355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982371 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982378 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982396 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982400 */     GIR_RootConstrainSelectedInstOperands,
     /*  982401 */     // GIR_Coverage, 13405,
     /*  982401 */     GIR_EraseRootFromParent_Done,
     /*  982402 */   // Label 15492: @982402
     /*  982402 */   GIM_Try, /*On fail goto*//*Label 15493*/ GIMT_Encode4(982457), // Rule ID 13406 //
     /*  982407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32_HwMode4),
     /*  982410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  982418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  982422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982426 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982433 */     // (intrinsic_w_chain:{ *:[v8f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
     /*  982436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982455 */     GIR_RootConstrainSelectedInstOperands,
     /*  982456 */     // GIR_Coverage, 13406,
     /*  982456 */     GIR_EraseRootFromParent_Done,
     /*  982457 */   // Label 15493: @982457
     /*  982457 */   GIM_Try, /*On fail goto*//*Label 15494*/ GIMT_Encode4(982512), // Rule ID 13412 //
     /*  982462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  982465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  982470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  982473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  982477 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982481 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982488 */     // (intrinsic_w_chain:{ *:[i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64),
     /*  982491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982503 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982506 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982510 */     GIR_RootConstrainSelectedInstOperands,
     /*  982511 */     // GIR_Coverage, 13412,
     /*  982511 */     GIR_EraseRootFromParent_Done,
     /*  982512 */   // Label 15494: @982512
     /*  982512 */   GIM_Try, /*On fail goto*//*Label 15495*/ GIMT_Encode4(982567), // Rule ID 13413 //
     /*  982517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  982520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  982525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  982528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  982532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982536 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982543 */     // (intrinsic_w_chain:{ *:[i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64),
     /*  982546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982561 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982565 */     GIR_RootConstrainSelectedInstOperands,
     /*  982566 */     // GIR_Coverage, 13413,
     /*  982566 */     GIR_EraseRootFromParent_Done,
     /*  982567 */   // Label 15495: @982567
     /*  982567 */   GIM_Try, /*On fail goto*//*Label 15496*/ GIMT_Encode4(982622), // Rule ID 13414 //
     /*  982572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  982575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  982580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  982583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  982587 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982591 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982598 */     // (intrinsic_w_chain:{ *:[i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64),
     /*  982601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982616 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982620 */     GIR_RootConstrainSelectedInstOperands,
     /*  982621 */     // GIR_Coverage, 13414,
     /*  982621 */     GIR_EraseRootFromParent_Done,
     /*  982622 */   // Label 15496: @982622
     /*  982622 */   GIM_Try, /*On fail goto*//*Label 15497*/ GIMT_Encode4(982677), // Rule ID 13415 //
     /*  982627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  982630 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  982635 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  982638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  982642 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982646 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982653 */     // (intrinsic_w_chain:{ *:[i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64),
     /*  982656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982658 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982663 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982671 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982675 */     GIR_RootConstrainSelectedInstOperands,
     /*  982676 */     // GIR_Coverage, 13415,
     /*  982676 */     GIR_EraseRootFromParent_Done,
     /*  982677 */   // Label 15497: @982677
     /*  982677 */   GIM_Try, /*On fail goto*//*Label 15498*/ GIMT_Encode4(982732), // Rule ID 13416 //
     /*  982682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  982685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64),
     /*  982690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  982693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  982697 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982708 */     // (intrinsic_w_chain:{ *:[i32] } 2474:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64),
     /*  982711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982718 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982726 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982730 */     GIR_RootConstrainSelectedInstOperands,
     /*  982731 */     // GIR_Coverage, 13416,
     /*  982731 */     GIR_EraseRootFromParent_Done,
     /*  982732 */   // Label 15498: @982732
     /*  982732 */   GIM_Try, /*On fail goto*//*Label 15499*/ GIMT_Encode4(982787), // Rule ID 13418 //
     /*  982737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  982740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  982748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  982752 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982756 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982763 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  982766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982778 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982785 */     GIR_RootConstrainSelectedInstOperands,
     /*  982786 */     // GIR_Coverage, 13418,
     /*  982786 */     GIR_EraseRootFromParent_Done,
     /*  982787 */   // Label 15499: @982787
     /*  982787 */   GIM_Try, /*On fail goto*//*Label 15500*/ GIMT_Encode4(982842), // Rule ID 13419 //
     /*  982792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  982795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  982803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  982807 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982818 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  982821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982833 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982840 */     GIR_RootConstrainSelectedInstOperands,
     /*  982841 */     // GIR_Coverage, 13419,
     /*  982841 */     GIR_EraseRootFromParent_Done,
     /*  982842 */   // Label 15500: @982842
     /*  982842 */   GIM_Try, /*On fail goto*//*Label 15501*/ GIMT_Encode4(982897), // Rule ID 13420 //
     /*  982847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  982850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  982858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  982862 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982873 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  982876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982895 */     GIR_RootConstrainSelectedInstOperands,
     /*  982896 */     // GIR_Coverage, 13420,
     /*  982896 */     GIR_EraseRootFromParent_Done,
     /*  982897 */   // Label 15501: @982897
     /*  982897 */   GIM_Try, /*On fail goto*//*Label 15502*/ GIMT_Encode4(982952), // Rule ID 13421 //
     /*  982902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  982905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  982913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  982917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982928 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  982931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  982946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  982950 */     GIR_RootConstrainSelectedInstOperands,
     /*  982951 */     // GIR_Coverage, 13421,
     /*  982951 */     GIR_EraseRootFromParent_Done,
     /*  982952 */   // Label 15502: @982952
     /*  982952 */   GIM_Try, /*On fail goto*//*Label 15503*/ GIMT_Encode4(983007), // Rule ID 13422 //
     /*  982957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  982960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  982965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  982968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  982972 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  982976 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  982983 */     // (intrinsic_w_chain:{ *:[v4i16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  982983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  982986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  982988 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  982993 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  982998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983005 */     GIR_RootConstrainSelectedInstOperands,
     /*  983006 */     // GIR_Coverage, 13422,
     /*  983006 */     GIR_EraseRootFromParent_Done,
     /*  983007 */   // Label 15503: @983007
     /*  983007 */   GIM_Try, /*On fail goto*//*Label 15504*/ GIMT_Encode4(983062), // Rule ID 13428 //
     /*  983012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode0),
     /*  983015 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  983020 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  983023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983027 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983031 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983038 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  983041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983043 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983053 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983060 */     GIR_RootConstrainSelectedInstOperands,
     /*  983061 */     // GIR_Coverage, 13428,
     /*  983061 */     GIR_EraseRootFromParent_Done,
     /*  983062 */   // Label 15504: @983062
     /*  983062 */   GIM_Try, /*On fail goto*//*Label 15505*/ GIMT_Encode4(983117), // Rule ID 13429 //
     /*  983067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode1),
     /*  983070 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  983075 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  983078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983082 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983093 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  983096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983108 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983115 */     GIR_RootConstrainSelectedInstOperands,
     /*  983116 */     // GIR_Coverage, 13429,
     /*  983116 */     GIR_EraseRootFromParent_Done,
     /*  983117 */   // Label 15505: @983117
     /*  983117 */   GIM_Try, /*On fail goto*//*Label 15506*/ GIMT_Encode4(983172), // Rule ID 13430 //
     /*  983122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode2),
     /*  983125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  983130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  983133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983141 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983148 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  983151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983170 */     GIR_RootConstrainSelectedInstOperands,
     /*  983171 */     // GIR_Coverage, 13430,
     /*  983171 */     GIR_EraseRootFromParent_Done,
     /*  983172 */   // Label 15506: @983172
     /*  983172 */   GIM_Try, /*On fail goto*//*Label 15507*/ GIMT_Encode4(983227), // Rule ID 13431 //
     /*  983177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode3),
     /*  983180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  983185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  983188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983192 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983196 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983203 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  983206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983208 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983213 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983218 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983221 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983225 */     GIR_RootConstrainSelectedInstOperands,
     /*  983226 */     // GIR_Coverage, 13431,
     /*  983226 */     GIR_EraseRootFromParent_Done,
     /*  983227 */   // Label 15507: @983227
     /*  983227 */   GIM_Try, /*On fail goto*//*Label 15508*/ GIMT_Encode4(983282), // Rule ID 13432 //
     /*  983232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12PlusNot12_50_isWave64_HwMode4),
     /*  983235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128),
     /*  983240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /*  983243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983251 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983258 */     // (intrinsic_w_chain:{ *:[v4f16] } 2473:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
     /*  983261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983263 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983268 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983273 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983276 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983280 */     GIR_RootConstrainSelectedInstOperands,
     /*  983281 */     // GIR_Coverage, 13432,
     /*  983281 */     GIR_EraseRootFromParent_Done,
     /*  983282 */   // Label 15508: @983282
     /*  983282 */   GIM_Try, /*On fail goto*//*Label 15509*/ GIMT_Encode4(983337), // Rule ID 13438 //
     /*  983287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode0),
     /*  983290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  983295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  983298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983302 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983313 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64),
     /*  983316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983328 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983331 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983335 */     GIR_RootConstrainSelectedInstOperands,
     /*  983336 */     // GIR_Coverage, 13438,
     /*  983336 */     GIR_EraseRootFromParent_Done,
     /*  983337 */   // Label 15509: @983337
     /*  983337 */   GIM_Try, /*On fail goto*//*Label 15510*/ GIMT_Encode4(983392), // Rule ID 13439 //
     /*  983342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode1),
     /*  983345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  983350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  983353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983361 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983368 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64),
     /*  983371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983383 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983390 */     GIR_RootConstrainSelectedInstOperands,
     /*  983391 */     // GIR_Coverage, 13439,
     /*  983391 */     GIR_EraseRootFromParent_Done,
     /*  983392 */   // Label 15510: @983392
     /*  983392 */   GIM_Try, /*On fail goto*//*Label 15511*/ GIMT_Encode4(983447), // Rule ID 13440 //
     /*  983397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode2),
     /*  983400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  983405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  983408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983412 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983416 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983423 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64),
     /*  983426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983438 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983445 */     GIR_RootConstrainSelectedInstOperands,
     /*  983446 */     // GIR_Coverage, 13440,
     /*  983446 */     GIR_EraseRootFromParent_Done,
     /*  983447 */   // Label 15511: @983447
     /*  983447 */   GIM_Try, /*On fail goto*//*Label 15512*/ GIMT_Encode4(983502), // Rule ID 13441 //
     /*  983452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode3),
     /*  983455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  983460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  983463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983467 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983471 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983478 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64),
     /*  983481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983500 */     GIR_RootConstrainSelectedInstOperands,
     /*  983501 */     // GIR_Coverage, 13441,
     /*  983501 */     GIR_EraseRootFromParent_Done,
     /*  983502 */   // Label 15512: @983502
     /*  983502 */   GIM_Try, /*On fail goto*//*Label 15513*/ GIMT_Encode4(983557), // Rule ID 13442 //
     /*  983507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode4),
     /*  983510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr4_b64),
     /*  983515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  983518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983522 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983533 */     // (intrinsic_w_chain:{ *:[v2i32] } 2475:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR4_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR4_B64),
     /*  983536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983555 */     GIR_RootConstrainSelectedInstOperands,
     /*  983556 */     // GIR_Coverage, 13442,
     /*  983556 */     GIR_EraseRootFromParent_Done,
     /*  983557 */   // Label 15513: @983557
     /*  983557 */   GIM_Try, /*On fail goto*//*Label 15514*/ GIMT_Encode4(983612), // Rule ID 13448 //
     /*  983562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode0),
     /*  983565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr6_b96),
     /*  983570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  983573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  983577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983581 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983588 */     // (intrinsic_w_chain:{ *:[v3i32] } 2476:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR6_B96:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR6_B96),
     /*  983591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983603 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983610 */     GIR_RootConstrainSelectedInstOperands,
     /*  983611 */     // GIR_Coverage, 13448,
     /*  983611 */     GIR_EraseRootFromParent_Done,
     /*  983612 */   // Label 15514: @983612
     /*  983612 */   GIM_Try, /*On fail goto*//*Label 15515*/ GIMT_Encode4(983667), // Rule ID 13449 //
     /*  983617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode1),
     /*  983620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr6_b96),
     /*  983625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  983628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  983632 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983636 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983643 */     // (intrinsic_w_chain:{ *:[v3i32] } 2476:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR6_B96:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR6_B96),
     /*  983646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983648 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983653 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983658 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983661 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983665 */     GIR_RootConstrainSelectedInstOperands,
     /*  983666 */     // GIR_Coverage, 13449,
     /*  983666 */     GIR_EraseRootFromParent_Done,
     /*  983667 */   // Label 15515: @983667
     /*  983667 */   GIM_Try, /*On fail goto*//*Label 15516*/ GIMT_Encode4(983722), // Rule ID 13450 //
     /*  983672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode2),
     /*  983675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr6_b96),
     /*  983680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  983683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  983687 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983691 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983698 */     // (intrinsic_w_chain:{ *:[v3i32] } 2476:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR6_B96:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR6_B96),
     /*  983701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983716 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983720 */     GIR_RootConstrainSelectedInstOperands,
     /*  983721 */     // GIR_Coverage, 13450,
     /*  983721 */     GIR_EraseRootFromParent_Done,
     /*  983722 */   // Label 15516: @983722
     /*  983722 */   GIM_Try, /*On fail goto*//*Label 15517*/ GIMT_Encode4(983777), // Rule ID 13451 //
     /*  983727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode3),
     /*  983730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr6_b96),
     /*  983735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  983738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  983742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983753 */     // (intrinsic_w_chain:{ *:[v3i32] } 2476:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR6_B96:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR6_B96),
     /*  983756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983771 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983775 */     GIR_RootConstrainSelectedInstOperands,
     /*  983776 */     // GIR_Coverage, 13451,
     /*  983776 */     GIR_EraseRootFromParent_Done,
     /*  983777 */   // Label 15517: @983777
     /*  983777 */   GIM_Try, /*On fail goto*//*Label 15518*/ GIMT_Encode4(983832), // Rule ID 13452 //
     /*  983782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTransposeLoadF4F6Insts_isWave32_HwMode4),
     /*  983785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr6_b96),
     /*  983790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v3s32,
     /*  983793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_96RegClassID),
     /*  983797 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983801 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  983808 */     // (intrinsic_w_chain:{ *:[v3i32] } 2476:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR6_B96:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
     /*  983808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR6_B96),
     /*  983811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  983818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983823 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983826 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983830 */     GIR_RootConstrainSelectedInstOperands,
     /*  983831 */     // GIR_Coverage, 13452,
     /*  983831 */     GIR_EraseRootFromParent_Done,
     /*  983832 */   // Label 15518: @983832
     /*  983832 */   GIM_Try, /*On fail goto*//*Label 15519*/ GIMT_Encode4(983860), // Rule ID 4267 //
     /*  983837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_init_exec_from_input),
     /*  983842 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  983845 */     // MIs[0] shift
     /*  983845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  983848 */     // (intrinsic_void 3251:{ *:[iPTR] }, i32:{ *:[i32] }:$input, (timm:{ *:[i32] }):$shift)  =>  (SI_INIT_EXEC_FROM_INPUT i32:{ *:[i32] }:$input, (timm:{ *:[i32] }):$shift)
     /*  983848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_EXEC_FROM_INPUT),
     /*  983851 */     GIR_RootToRootCopy, /*OpIdx*/1, // input
     /*  983853 */     GIR_RootToRootCopy, /*OpIdx*/2, // shift
     /*  983855 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
     /*  983858 */     GIR_RootConstrainSelectedInstOperands,
     /*  983859 */     // GIR_Coverage, 4267,
     /*  983859 */     GIR_EraseRootFromParent_Done,
     /*  983860 */   // Label 15519: @983860
     /*  983860 */   GIM_Reject,
     /*  983861 */ // Label 15400: @983861
     /*  983861 */ GIM_Try, /*On fail goto*//*Label 15520*/ GIMT_Encode4(986711),
     /*  983866 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /*  983869 */   GIM_Try, /*On fail goto*//*Label 15521*/ GIMT_Encode4(983929), // Rule ID 28763 //
     /*  983874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode0),
     /*  983877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64),
     /*  983882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  983885 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  983888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983892 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983896 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  983903 */     // (intrinsic_w_chain:{ *:[i64] } 2408:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i64] }:$data, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  983903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64),
     /*  983906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  983913 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  983915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983923 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983927 */     GIR_RootConstrainSelectedInstOperands,
     /*  983928 */     // GIR_Coverage, 28763,
     /*  983928 */     GIR_EraseRootFromParent_Done,
     /*  983929 */   // Label 15521: @983929
     /*  983929 */   GIM_Try, /*On fail goto*//*Label 15522*/ GIMT_Encode4(983989), // Rule ID 28764 //
     /*  983934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode1),
     /*  983937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64),
     /*  983942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  983945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  983948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  983952 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  983956 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  983963 */     // (intrinsic_w_chain:{ *:[i64] } 2408:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i64] }:$data, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  983963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64),
     /*  983966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  983968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  983973 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  983975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  983980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  983983 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  983987 */     GIR_RootConstrainSelectedInstOperands,
     /*  983988 */     // GIR_Coverage, 28764,
     /*  983988 */     GIR_EraseRootFromParent_Done,
     /*  983989 */   // Label 15522: @983989
     /*  983989 */   GIM_Try, /*On fail goto*//*Label 15523*/ GIMT_Encode4(984049), // Rule ID 28765 //
     /*  983994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode2),
     /*  983997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64),
     /*  984002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  984005 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  984008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984012 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984016 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  984023 */     // (intrinsic_w_chain:{ *:[i64] } 2408:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i64] }:$data, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  984023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64),
     /*  984026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  984033 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  984035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  984040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  984043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984047 */     GIR_RootConstrainSelectedInstOperands,
     /*  984048 */     // GIR_Coverage, 28765,
     /*  984048 */     GIR_EraseRootFromParent_Done,
     /*  984049 */   // Label 15523: @984049
     /*  984049 */   GIM_Try, /*On fail goto*//*Label 15524*/ GIMT_Encode4(984109), // Rule ID 28766 //
     /*  984054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode3),
     /*  984057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64),
     /*  984062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  984065 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  984068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984072 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984076 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  984083 */     // (intrinsic_w_chain:{ *:[i64] } 2408:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i64] }:$data, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  984083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64),
     /*  984086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  984093 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  984095 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  984100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  984103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984107 */     GIR_RootConstrainSelectedInstOperands,
     /*  984108 */     // GIR_Coverage, 28766,
     /*  984108 */     GIR_EraseRootFromParent_Done,
     /*  984109 */   // Label 15524: @984109
     /*  984109 */   GIM_Try, /*On fail goto*//*Label 15525*/ GIMT_Encode4(984169), // Rule ID 28767 //
     /*  984114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsBarrierArriveAtomic_isGFX1250Plus_HwMode4),
     /*  984117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64),
     /*  984122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  984125 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /*  984128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984136 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
     /*  984143 */     // (intrinsic_w_chain:{ *:[i64] } 2408:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (DS_ATOMIC_BARRIER_ARRIVE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i64] }:$data, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
     /*  984143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ATOMIC_BARRIER_ARRIVE_RTN_B64),
     /*  984146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
     /*  984153 */     GIR_RootToRootCopy, /*OpIdx*/3, // data
     /*  984155 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  984160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  984163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984167 */     GIR_RootConstrainSelectedInstOperands,
     /*  984168 */     // GIR_Coverage, 28767,
     /*  984168 */     GIR_EraseRootFromParent_Done,
     /*  984169 */   // Label 15525: @984169
     /*  984169 */   GIM_Try, /*On fail goto*//*Label 15526*/ GIMT_Encode4(984199), // Rule ID 4243 //
     /*  984174 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_sched_group_barrier),
     /*  984179 */     // MIs[0] mask
     /*  984179 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /*  984182 */     // MIs[0] size
     /*  984182 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /*  984185 */     // MIs[0] syncid
     /*  984185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984188 */     // (intrinsic_void 3482:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask, (timm:{ *:[i32] }):$size, (timm:{ *:[i32] }):$syncid)  =>  (SCHED_GROUP_BARRIER (timm:{ *:[i32] }):$mask, (timm:{ *:[i32] }):$size, (timm:{ *:[i32] }):$syncid)
     /*  984188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCHED_GROUP_BARRIER),
     /*  984191 */     GIR_RootToRootCopy, /*OpIdx*/1, // mask
     /*  984193 */     GIR_RootToRootCopy, /*OpIdx*/2, // size
     /*  984195 */     GIR_RootToRootCopy, /*OpIdx*/3, // syncid
     /*  984197 */     GIR_RootConstrainSelectedInstOperands,
     /*  984198 */     // GIR_Coverage, 4243,
     /*  984198 */     GIR_EraseRootFromParent_Done,
     /*  984199 */   // Label 15526: @984199
     /*  984199 */   GIM_Try, /*On fail goto*//*Label 15527*/ GIMT_Encode4(984264), // Rule ID 9349 //
     /*  984204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly),
     /*  984207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b32),
     /*  984212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  984215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  984219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984223 */     // MIs[0] Operand 3
     /*  984223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984233 */     // (intrinsic_w_chain:{ *:[i32] } 2471:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B32_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B32_SADDR),
     /*  984236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984248 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984258 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984262 */     GIR_RootConstrainSelectedInstOperands,
     /*  984263 */     // GIR_Coverage, 9349,
     /*  984263 */     GIR_EraseRootFromParent_Done,
     /*  984264 */   // Label 15527: @984264
     /*  984264 */   GIM_Try, /*On fail goto*//*Label 15528*/ GIMT_Encode4(984329), // Rule ID 13474 //
     /*  984269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  984272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  984277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  984280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984284 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984288 */     // MIs[0] Operand 3
     /*  984288 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984291 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984298 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR),
     /*  984301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984303 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984327 */     GIR_RootConstrainSelectedInstOperands,
     /*  984328 */     // GIR_Coverage, 13474,
     /*  984328 */     GIR_EraseRootFromParent_Done,
     /*  984329 */   // Label 15528: @984329
     /*  984329 */   GIM_Try, /*On fail goto*//*Label 15529*/ GIMT_Encode4(984394), // Rule ID 13475 //
     /*  984334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  984337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  984342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  984345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984349 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984353 */     // MIs[0] Operand 3
     /*  984353 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984356 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984363 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR),
     /*  984366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984368 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984373 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984378 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984388 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984392 */     GIR_RootConstrainSelectedInstOperands,
     /*  984393 */     // GIR_Coverage, 13475,
     /*  984393 */     GIR_EraseRootFromParent_Done,
     /*  984394 */   // Label 15529: @984394
     /*  984394 */   GIM_Try, /*On fail goto*//*Label 15530*/ GIMT_Encode4(984459), // Rule ID 13476 //
     /*  984399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  984402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  984407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  984410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984418 */     // MIs[0] Operand 3
     /*  984418 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984428 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR),
     /*  984431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984457 */     GIR_RootConstrainSelectedInstOperands,
     /*  984458 */     // GIR_Coverage, 13476,
     /*  984458 */     GIR_EraseRootFromParent_Done,
     /*  984459 */   // Label 15530: @984459
     /*  984459 */   GIM_Try, /*On fail goto*//*Label 15531*/ GIMT_Encode4(984524), // Rule ID 13477 //
     /*  984464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  984467 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  984472 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  984475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984483 */     // MIs[0] Operand 3
     /*  984483 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984493 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR),
     /*  984496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984522 */     GIR_RootConstrainSelectedInstOperands,
     /*  984523 */     // GIR_Coverage, 13477,
     /*  984523 */     GIR_EraseRootFromParent_Done,
     /*  984524 */   // Label 15531: @984524
     /*  984524 */   GIM_Try, /*On fail goto*//*Label 15532*/ GIMT_Encode4(984589), // Rule ID 13478 //
     /*  984529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  984532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  984537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  984540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  984544 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984548 */     // MIs[0] Operand 3
     /*  984548 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984551 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984558 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR),
     /*  984561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984583 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984587 */     GIR_RootConstrainSelectedInstOperands,
     /*  984588 */     // GIR_Coverage, 13478,
     /*  984588 */     GIR_EraseRootFromParent_Done,
     /*  984589 */   // Label 15532: @984589
     /*  984589 */   GIM_Try, /*On fail goto*//*Label 15533*/ GIMT_Encode4(984654), // Rule ID 13484 //
     /*  984594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  984597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  984602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  984605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  984609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984613 */     // MIs[0] Operand 3
     /*  984613 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984623 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR),
     /*  984626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984652 */     GIR_RootConstrainSelectedInstOperands,
     /*  984653 */     // GIR_Coverage, 13484,
     /*  984653 */     GIR_EraseRootFromParent_Done,
     /*  984654 */   // Label 15533: @984654
     /*  984654 */   GIM_Try, /*On fail goto*//*Label 15534*/ GIMT_Encode4(984719), // Rule ID 13485 //
     /*  984659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  984662 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  984667 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  984670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  984674 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984678 */     // MIs[0] Operand 3
     /*  984678 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984681 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984688 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR),
     /*  984691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984693 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984713 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984717 */     GIR_RootConstrainSelectedInstOperands,
     /*  984718 */     // GIR_Coverage, 13485,
     /*  984718 */     GIR_EraseRootFromParent_Done,
     /*  984719 */   // Label 15534: @984719
     /*  984719 */   GIM_Try, /*On fail goto*//*Label 15535*/ GIMT_Encode4(984784), // Rule ID 13486 //
     /*  984724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  984727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  984732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  984735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  984739 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984743 */     // MIs[0] Operand 3
     /*  984743 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984746 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984753 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR),
     /*  984756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984782 */     GIR_RootConstrainSelectedInstOperands,
     /*  984783 */     // GIR_Coverage, 13486,
     /*  984783 */     GIR_EraseRootFromParent_Done,
     /*  984784 */   // Label 15535: @984784
     /*  984784 */   GIM_Try, /*On fail goto*//*Label 15536*/ GIMT_Encode4(984849), // Rule ID 13487 //
     /*  984789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  984792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  984797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  984800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  984804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984808 */     // MIs[0] Operand 3
     /*  984808 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984811 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984818 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR),
     /*  984821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984823 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984828 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984843 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984847 */     GIR_RootConstrainSelectedInstOperands,
     /*  984848 */     // GIR_Coverage, 13487,
     /*  984848 */     GIR_EraseRootFromParent_Done,
     /*  984849 */   // Label 15536: @984849
     /*  984849 */   GIM_Try, /*On fail goto*//*Label 15537*/ GIMT_Encode4(984914), // Rule ID 13488 //
     /*  984854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  984857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  984862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  984865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  984869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984873 */     // MIs[0] Operand 3
     /*  984873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol),
     /*  984883 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalSAddrCPol:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }))  =>  (GLOBAL_LOAD_MONITOR_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR),
     /*  984886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  984893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  984898 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  984903 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  984908 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984912 */     GIR_RootConstrainSelectedInstOperands,
     /*  984913 */     // GIR_Coverage, 13488,
     /*  984913 */     GIR_EraseRootFromParent_Done,
     /*  984914 */   // Label 15537: @984914
     /*  984914 */   GIM_Try, /*On fail goto*//*Label 15538*/ GIMT_Encode4(984971), // Rule ID 9344 //
     /*  984919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  984922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b32),
     /*  984927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  984930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  984934 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984938 */     // MIs[0] cpol
     /*  984938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  984948 */     // (intrinsic_w_chain:{ *:[i32] } 2471:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  984948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B32),
     /*  984951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  984953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  984958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  984963 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  984965 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  984969 */     GIR_RootConstrainSelectedInstOperands,
     /*  984970 */     // GIR_Coverage, 9344,
     /*  984970 */     GIR_EraseRootFromParent_Done,
     /*  984971 */   // Label 15538: @984971
     /*  984971 */   GIM_Try, /*On fail goto*//*Label 15539*/ GIMT_Encode4(985028), // Rule ID 9345 //
     /*  984976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  984979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b32),
     /*  984984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  984987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  984991 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  984995 */     // MIs[0] cpol
     /*  984995 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  984998 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985005 */     // (intrinsic_w_chain:{ *:[i32] } 2471:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B32),
     /*  985008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985015 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985020 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985026 */     GIR_RootConstrainSelectedInstOperands,
     /*  985027 */     // GIR_Coverage, 9345,
     /*  985027 */     GIR_EraseRootFromParent_Done,
     /*  985028 */   // Label 15539: @985028
     /*  985028 */   GIM_Try, /*On fail goto*//*Label 15540*/ GIMT_Encode4(985085), // Rule ID 9346 //
     /*  985033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  985036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b32),
     /*  985041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  985044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  985048 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985052 */     // MIs[0] cpol
     /*  985052 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985055 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985062 */     // (intrinsic_w_chain:{ *:[i32] } 2471:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B32),
     /*  985065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985077 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985079 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985083 */     GIR_RootConstrainSelectedInstOperands,
     /*  985084 */     // GIR_Coverage, 9346,
     /*  985084 */     GIR_EraseRootFromParent_Done,
     /*  985085 */   // Label 15540: @985085
     /*  985085 */   GIM_Try, /*On fail goto*//*Label 15541*/ GIMT_Encode4(985142), // Rule ID 9347 //
     /*  985090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  985093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b32),
     /*  985098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  985101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  985105 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985109 */     // MIs[0] cpol
     /*  985109 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985119 */     // (intrinsic_w_chain:{ *:[i32] } 2471:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B32),
     /*  985122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985134 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985136 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985140 */     GIR_RootConstrainSelectedInstOperands,
     /*  985141 */     // GIR_Coverage, 9347,
     /*  985141 */     GIR_EraseRootFromParent_Done,
     /*  985142 */   // Label 15541: @985142
     /*  985142 */   GIM_Try, /*On fail goto*//*Label 15542*/ GIMT_Encode4(985199), // Rule ID 9348 //
     /*  985147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  985150 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b32),
     /*  985155 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  985158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  985162 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985166 */     // MIs[0] cpol
     /*  985166 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985169 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985176 */     // (intrinsic_w_chain:{ *:[i32] } 2471:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B32),
     /*  985179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985181 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985191 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985193 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985197 */     GIR_RootConstrainSelectedInstOperands,
     /*  985198 */     // GIR_Coverage, 9348,
     /*  985198 */     GIR_EraseRootFromParent_Done,
     /*  985199 */   // Label 15542: @985199
     /*  985199 */   GIM_Try, /*On fail goto*//*Label 15543*/ GIMT_Encode4(985256), // Rule ID 13469 //
     /*  985204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  985207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  985212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  985215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  985219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985223 */     // MIs[0] cpol
     /*  985223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985226 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985233 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64),
     /*  985236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985238 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985243 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985248 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985250 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985254 */     GIR_RootConstrainSelectedInstOperands,
     /*  985255 */     // GIR_Coverage, 13469,
     /*  985255 */     GIR_EraseRootFromParent_Done,
     /*  985256 */   // Label 15543: @985256
     /*  985256 */   GIM_Try, /*On fail goto*//*Label 15544*/ GIMT_Encode4(985313), // Rule ID 13470 //
     /*  985261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  985264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  985269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  985272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  985276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985280 */     // MIs[0] cpol
     /*  985280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985283 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985290 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64),
     /*  985293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985305 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985311 */     GIR_RootConstrainSelectedInstOperands,
     /*  985312 */     // GIR_Coverage, 13470,
     /*  985312 */     GIR_EraseRootFromParent_Done,
     /*  985313 */   // Label 15544: @985313
     /*  985313 */   GIM_Try, /*On fail goto*//*Label 15545*/ GIMT_Encode4(985370), // Rule ID 13471 //
     /*  985318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  985321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  985326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  985329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  985333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985337 */     // MIs[0] cpol
     /*  985337 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985347 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64),
     /*  985350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985362 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985368 */     GIR_RootConstrainSelectedInstOperands,
     /*  985369 */     // GIR_Coverage, 13471,
     /*  985369 */     GIR_EraseRootFromParent_Done,
     /*  985370 */   // Label 15545: @985370
     /*  985370 */   GIM_Try, /*On fail goto*//*Label 15546*/ GIMT_Encode4(985427), // Rule ID 13472 //
     /*  985375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  985378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  985383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  985386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  985390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985394 */     // MIs[0] cpol
     /*  985394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985397 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985404 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64),
     /*  985407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985419 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985421 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985425 */     GIR_RootConstrainSelectedInstOperands,
     /*  985426 */     // GIR_Coverage, 13472,
     /*  985426 */     GIR_EraseRootFromParent_Done,
     /*  985427 */   // Label 15546: @985427
     /*  985427 */   GIM_Try, /*On fail goto*//*Label 15547*/ GIMT_Encode4(985484), // Rule ID 13473 //
     /*  985432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  985435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b64),
     /*  985440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  985443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  985447 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985451 */     // MIs[0] cpol
     /*  985451 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985454 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985461 */     // (intrinsic_w_chain:{ *:[v2i32] } 2472:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B64),
     /*  985464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985466 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985476 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985482 */     GIR_RootConstrainSelectedInstOperands,
     /*  985483 */     // GIR_Coverage, 13473,
     /*  985483 */     GIR_EraseRootFromParent_Done,
     /*  985484 */   // Label 15547: @985484
     /*  985484 */   GIM_Try, /*On fail goto*//*Label 15548*/ GIMT_Encode4(985541), // Rule ID 13479 //
     /*  985489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  985492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  985497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  985500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  985504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985508 */     // MIs[0] cpol
     /*  985508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985518 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128),
     /*  985521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985528 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985533 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985539 */     GIR_RootConstrainSelectedInstOperands,
     /*  985540 */     // GIR_Coverage, 13479,
     /*  985540 */     GIR_EraseRootFromParent_Done,
     /*  985541 */   // Label 15548: @985541
     /*  985541 */   GIM_Try, /*On fail goto*//*Label 15549*/ GIMT_Encode4(985598), // Rule ID 13480 //
     /*  985546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  985549 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  985554 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  985557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  985561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985565 */     // MIs[0] cpol
     /*  985565 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985568 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985575 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128),
     /*  985578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985580 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985585 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985590 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985596 */     GIR_RootConstrainSelectedInstOperands,
     /*  985597 */     // GIR_Coverage, 13480,
     /*  985597 */     GIR_EraseRootFromParent_Done,
     /*  985598 */   // Label 15549: @985598
     /*  985598 */   GIM_Try, /*On fail goto*//*Label 15550*/ GIMT_Encode4(985655), // Rule ID 13481 //
     /*  985603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  985606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  985611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  985614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  985618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985622 */     // MIs[0] cpol
     /*  985622 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985625 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985632 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128),
     /*  985635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985647 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985653 */     GIR_RootConstrainSelectedInstOperands,
     /*  985654 */     // GIR_Coverage, 13481,
     /*  985654 */     GIR_EraseRootFromParent_Done,
     /*  985655 */   // Label 15550: @985655
     /*  985655 */   GIM_Try, /*On fail goto*//*Label 15551*/ GIMT_Encode4(985712), // Rule ID 13482 //
     /*  985660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  985663 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  985668 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  985671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  985675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985679 */     // MIs[0] cpol
     /*  985679 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985682 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985689 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128),
     /*  985692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985704 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985710 */     GIR_RootConstrainSelectedInstOperands,
     /*  985711 */     // GIR_Coverage, 13482,
     /*  985711 */     GIR_EraseRootFromParent_Done,
     /*  985712 */   // Label 15551: @985712
     /*  985712 */   GIM_Try, /*On fail goto*//*Label 15552*/ GIMT_Encode4(985769), // Rule ID 13483 //
     /*  985717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  985720 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_monitor_b128),
     /*  985725 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  985728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  985732 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985736 */     // MIs[0] cpol
     /*  985736 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  985746 */     // (intrinsic_w_chain:{ *:[v4i32] } 2470:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (GLOBAL_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_MONITOR_B128),
     /*  985749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985761 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985767 */     GIR_RootConstrainSelectedInstOperands,
     /*  985768 */     // GIR_Coverage, 13483,
     /*  985768 */     GIR_EraseRootFromParent_Done,
     /*  985769 */   // Label 15552: @985769
     /*  985769 */   GIM_Try, /*On fail goto*//*Label 15553*/ GIMT_Encode4(985812), // Rule ID 31089 //
     /*  985774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  985777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_tensor_load_to_lds_d2),
     /*  985782 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  985785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  985788 */     // MIs[0] cpol
     /*  985788 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985791 */     // (intrinsic_void 3603:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vaddr0, v8i32:{ *:[v8i32] }:$vaddr1, (timm:{ *:[i32] }):$cpol)  =>  (TENSOR_LOAD_TO_LDS_D2 ?:{ *:[v4i32] }:$vaddr0, ?:{ *:[v8i32] }:$vaddr1, 0:{ *:[i1] }, ?:{ *:[i32] }:$cpol)
     /*  985791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TENSOR_LOAD_TO_LDS_D2),
     /*  985794 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr0
     /*  985796 */     GIR_RootToRootCopy, /*OpIdx*/2, // vaddr1
     /*  985798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  985801 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985803 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::TENSORcnt*/0,
     /*  985806 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985810 */     GIR_RootConstrainSelectedInstOperands,
     /*  985811 */     // GIR_Coverage, 31089,
     /*  985811 */     GIR_EraseRootFromParent_Done,
     /*  985812 */   // Label 15553: @985812
     /*  985812 */   GIM_Try, /*On fail goto*//*Label 15554*/ GIMT_Encode4(985855), // Rule ID 31090 //
     /*  985817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  985820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_tensor_store_from_lds_d2),
     /*  985825 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  985828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  985831 */     // MIs[0] cpol
     /*  985831 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985834 */     // (intrinsic_void 3605:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vaddr0, v8i32:{ *:[v8i32] }:$vaddr1, (timm:{ *:[i32] }):$cpol)  =>  (TENSOR_STORE_FROM_LDS_D2 ?:{ *:[v4i32] }:$vaddr0, ?:{ *:[v8i32] }:$vaddr1, 0:{ *:[i1] }, ?:{ *:[i32] }:$cpol)
     /*  985834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TENSOR_STORE_FROM_LDS_D2),
     /*  985837 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr0
     /*  985839 */     GIR_RootToRootCopy, /*OpIdx*/2, // vaddr1
     /*  985841 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  985844 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985846 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::TENSORcnt*/0,
     /*  985849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985853 */     GIR_RootConstrainSelectedInstOperands,
     /*  985854 */     // GIR_Coverage, 31090,
     /*  985854 */     GIR_EraseRootFromParent_Done,
     /*  985855 */   // Label 15554: @985855
     /*  985855 */   GIM_Try, /*On fail goto*//*Label 15555*/ GIMT_Encode4(985912), // Rule ID 13454 //
     /*  985860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  985863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b32),
     /*  985868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  985871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  985875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985879 */     // MIs[0] cpol
     /*  985879 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  985889 */     // (intrinsic_w_chain:{ *:[i32] } 2452:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B32),
     /*  985892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985904 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985906 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985910 */     GIR_RootConstrainSelectedInstOperands,
     /*  985911 */     // GIR_Coverage, 13454,
     /*  985911 */     GIR_EraseRootFromParent_Done,
     /*  985912 */   // Label 15555: @985912
     /*  985912 */   GIM_Try, /*On fail goto*//*Label 15556*/ GIMT_Encode4(985969), // Rule ID 13455 //
     /*  985917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  985920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b32),
     /*  985925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  985928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  985932 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985936 */     // MIs[0] cpol
     /*  985936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985939 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  985946 */     // (intrinsic_w_chain:{ *:[i32] } 2452:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  985946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B32),
     /*  985949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  985951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  985956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  985961 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  985963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  985967 */     GIR_RootConstrainSelectedInstOperands,
     /*  985968 */     // GIR_Coverage, 13455,
     /*  985968 */     GIR_EraseRootFromParent_Done,
     /*  985969 */   // Label 15556: @985969
     /*  985969 */   GIM_Try, /*On fail goto*//*Label 15557*/ GIMT_Encode4(986026), // Rule ID 13456 //
     /*  985974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  985977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b32),
     /*  985982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  985985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  985989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  985993 */     // MIs[0] cpol
     /*  985993 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  985996 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986003 */     // (intrinsic_w_chain:{ *:[i32] } 2452:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B32),
     /*  986006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986018 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986020 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986024 */     GIR_RootConstrainSelectedInstOperands,
     /*  986025 */     // GIR_Coverage, 13456,
     /*  986025 */     GIR_EraseRootFromParent_Done,
     /*  986026 */   // Label 15557: @986026
     /*  986026 */   GIM_Try, /*On fail goto*//*Label 15558*/ GIMT_Encode4(986083), // Rule ID 13457 //
     /*  986031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  986034 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b32),
     /*  986039 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  986042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  986046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986050 */     // MIs[0] cpol
     /*  986050 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986053 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986060 */     // (intrinsic_w_chain:{ *:[i32] } 2452:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B32),
     /*  986063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986065 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986075 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986077 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986081 */     GIR_RootConstrainSelectedInstOperands,
     /*  986082 */     // GIR_Coverage, 13457,
     /*  986082 */     GIR_EraseRootFromParent_Done,
     /*  986083 */   // Label 15558: @986083
     /*  986083 */   GIM_Try, /*On fail goto*//*Label 15559*/ GIMT_Encode4(986140), // Rule ID 13458 //
     /*  986088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  986091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b32),
     /*  986096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  986099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  986103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986107 */     // MIs[0] cpol
     /*  986107 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986110 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986117 */     // (intrinsic_w_chain:{ *:[i32] } 2452:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B32),
     /*  986120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986122 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986132 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986138 */     GIR_RootConstrainSelectedInstOperands,
     /*  986139 */     // GIR_Coverage, 13458,
     /*  986139 */     GIR_EraseRootFromParent_Done,
     /*  986140 */   // Label 15559: @986140
     /*  986140 */   GIM_Try, /*On fail goto*//*Label 15560*/ GIMT_Encode4(986197), // Rule ID 13459 //
     /*  986145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  986148 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b64),
     /*  986153 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986160 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986164 */     // MIs[0] cpol
     /*  986164 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986174 */     // (intrinsic_w_chain:{ *:[v2i32] } 2453:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B64),
     /*  986177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986189 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986195 */     GIR_RootConstrainSelectedInstOperands,
     /*  986196 */     // GIR_Coverage, 13459,
     /*  986196 */     GIR_EraseRootFromParent_Done,
     /*  986197 */   // Label 15560: @986197
     /*  986197 */   GIM_Try, /*On fail goto*//*Label 15561*/ GIMT_Encode4(986254), // Rule ID 13460 //
     /*  986202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  986205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b64),
     /*  986210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986217 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986221 */     // MIs[0] cpol
     /*  986221 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986231 */     // (intrinsic_w_chain:{ *:[v2i32] } 2453:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B64),
     /*  986234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986246 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986248 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986252 */     GIR_RootConstrainSelectedInstOperands,
     /*  986253 */     // GIR_Coverage, 13460,
     /*  986253 */     GIR_EraseRootFromParent_Done,
     /*  986254 */   // Label 15561: @986254
     /*  986254 */   GIM_Try, /*On fail goto*//*Label 15562*/ GIMT_Encode4(986311), // Rule ID 13461 //
     /*  986259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  986262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b64),
     /*  986267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986278 */     // MIs[0] cpol
     /*  986278 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986281 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986288 */     // (intrinsic_w_chain:{ *:[v2i32] } 2453:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B64),
     /*  986291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986298 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986303 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986305 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986309 */     GIR_RootConstrainSelectedInstOperands,
     /*  986310 */     // GIR_Coverage, 13461,
     /*  986310 */     GIR_EraseRootFromParent_Done,
     /*  986311 */   // Label 15562: @986311
     /*  986311 */   GIM_Try, /*On fail goto*//*Label 15563*/ GIMT_Encode4(986368), // Rule ID 13462 //
     /*  986316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  986319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b64),
     /*  986324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986335 */     // MIs[0] cpol
     /*  986335 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986338 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986345 */     // (intrinsic_w_chain:{ *:[v2i32] } 2453:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B64),
     /*  986348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986350 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986355 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986360 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986362 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986366 */     GIR_RootConstrainSelectedInstOperands,
     /*  986367 */     // GIR_Coverage, 13462,
     /*  986367 */     GIR_EraseRootFromParent_Done,
     /*  986368 */   // Label 15563: @986368
     /*  986368 */   GIM_Try, /*On fail goto*//*Label 15564*/ GIMT_Encode4(986425), // Rule ID 13463 //
     /*  986373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  986376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b64),
     /*  986381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986388 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986392 */     // MIs[0] cpol
     /*  986392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986402 */     // (intrinsic_w_chain:{ *:[v2i32] } 2453:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B64),
     /*  986405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986412 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986417 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986423 */     GIR_RootConstrainSelectedInstOperands,
     /*  986424 */     // GIR_Coverage, 13463,
     /*  986424 */     GIR_EraseRootFromParent_Done,
     /*  986425 */   // Label 15564: @986425
     /*  986425 */   GIM_Try, /*On fail goto*//*Label 15565*/ GIMT_Encode4(986482), // Rule ID 13464 //
     /*  986430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode0),
     /*  986433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b128),
     /*  986438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  986441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  986445 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986449 */     // MIs[0] cpol
     /*  986449 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986452 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986459 */     // (intrinsic_w_chain:{ *:[v4i32] } 2451:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B128),
     /*  986462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986464 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986469 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986474 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986476 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986480 */     GIR_RootConstrainSelectedInstOperands,
     /*  986481 */     // GIR_Coverage, 13464,
     /*  986481 */     GIR_EraseRootFromParent_Done,
     /*  986482 */   // Label 15565: @986482
     /*  986482 */   GIM_Try, /*On fail goto*//*Label 15566*/ GIMT_Encode4(986539), // Rule ID 13465 //
     /*  986487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode1),
     /*  986490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b128),
     /*  986495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  986498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  986502 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986506 */     // MIs[0] cpol
     /*  986506 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986509 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986516 */     // (intrinsic_w_chain:{ *:[v4i32] } 2451:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B128),
     /*  986519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986526 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986531 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986537 */     GIR_RootConstrainSelectedInstOperands,
     /*  986538 */     // GIR_Coverage, 13465,
     /*  986538 */     GIR_EraseRootFromParent_Done,
     /*  986539 */   // Label 15566: @986539
     /*  986539 */   GIM_Try, /*On fail goto*//*Label 15567*/ GIMT_Encode4(986596), // Rule ID 13466 //
     /*  986544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode2),
     /*  986547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b128),
     /*  986552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  986555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  986559 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986563 */     // MIs[0] cpol
     /*  986563 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986566 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986573 */     // (intrinsic_w_chain:{ *:[v4i32] } 2451:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B128),
     /*  986576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986588 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986594 */     GIR_RootConstrainSelectedInstOperands,
     /*  986595 */     // GIR_Coverage, 13466,
     /*  986595 */     GIR_EraseRootFromParent_Done,
     /*  986596 */   // Label 15567: @986596
     /*  986596 */   GIM_Try, /*On fail goto*//*Label 15568*/ GIMT_Encode4(986653), // Rule ID 13467 //
     /*  986601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode3),
     /*  986604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b128),
     /*  986609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  986612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  986616 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986620 */     // MIs[0] cpol
     /*  986620 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986623 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986630 */     // (intrinsic_w_chain:{ *:[v4i32] } 2451:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B128),
     /*  986633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986645 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986651 */     GIR_RootConstrainSelectedInstOperands,
     /*  986652 */     // GIR_Coverage, 13467,
     /*  986652 */     GIR_EraseRootFromParent_Done,
     /*  986653 */   // Label 15568: @986653
     /*  986653 */   GIM_Try, /*On fail goto*//*Label 15569*/ GIMT_Encode4(986710), // Rule ID 13468 //
     /*  986658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX125xOnly_HwMode4),
     /*  986661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_load_monitor_b128),
     /*  986666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  986669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  986673 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986677 */     // MIs[0] cpol
     /*  986677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
     /*  986687 */     // (intrinsic_w_chain:{ *:[v4i32] } 2451:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol)  =>  (FLAT_LOAD_MONITOR_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_MONITOR_B128),
     /*  986690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  986697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  986702 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  986704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986708 */     GIR_RootConstrainSelectedInstOperands,
     /*  986709 */     // GIR_Coverage, 13468,
     /*  986709 */     GIR_EraseRootFromParent_Done,
     /*  986710 */   // Label 15569: @986710
     /*  986710 */   GIM_Reject,
     /*  986711 */ // Label 15520: @986711
     /*  986711 */ GIM_Try, /*On fail goto*//*Label 15570*/ GIMT_Encode4(988836),
     /*  986716 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /*  986719 */   GIM_Try, /*On fail goto*//*Label 15571*/ GIMT_Encode4(986805), // Rule ID 9343 //
     /*  986724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  986727 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b32),
     /*  986732 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  986735 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  986738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  986742 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986746 */     // MIs[0] Operand 3
     /*  986746 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986749 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  986753 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  986760 */     // (intrinsic_w_chain:{ *:[i32] } 2249:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B32_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986760 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  986764 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  986770 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  986774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B32_SADDR),
     /*  986777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  986784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  986789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  986794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  986799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986803 */     GIR_RootConstrainSelectedInstOperands,
     /*  986804 */     // GIR_Coverage, 9343,
     /*  986804 */     GIR_EraseRootFromParent_Done,
     /*  986805 */   // Label 15571: @986805
     /*  986805 */   GIM_Try, /*On fail goto*//*Label 15572*/ GIMT_Encode4(986891), // Rule ID 13494 //
     /*  986810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  986813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  986818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986821 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  986824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986828 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986832 */     // MIs[0] Operand 3
     /*  986832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986835 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  986839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  986846 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986846 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  986850 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  986856 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  986860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64_SADDR),
     /*  986863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  986870 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  986875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  986880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  986885 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986889 */     GIR_RootConstrainSelectedInstOperands,
     /*  986890 */     // GIR_Coverage, 13494,
     /*  986890 */     GIR_EraseRootFromParent_Done,
     /*  986891 */   // Label 15572: @986891
     /*  986891 */   GIM_Try, /*On fail goto*//*Label 15573*/ GIMT_Encode4(986977), // Rule ID 13495 //
     /*  986896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  986899 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  986904 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986907 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  986910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  986914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  986918 */     // MIs[0] Operand 3
     /*  986918 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  986921 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  986925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  986932 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  986932 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  986936 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  986942 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  986946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64_SADDR),
     /*  986949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  986951 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  986956 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  986961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  986966 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  986971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  986975 */     GIR_RootConstrainSelectedInstOperands,
     /*  986976 */     // GIR_Coverage, 13495,
     /*  986976 */     GIR_EraseRootFromParent_Done,
     /*  986977 */   // Label 15573: @986977
     /*  986977 */   GIM_Try, /*On fail goto*//*Label 15574*/ GIMT_Encode4(987063), // Rule ID 13496 //
     /*  986982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  986985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  986990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  986993 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  986996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  987000 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987004 */     // MIs[0] Operand 3
     /*  987004 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987007 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987018 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987018 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987022 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987028 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64_SADDR),
     /*  987035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987047 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987052 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987061 */     GIR_RootConstrainSelectedInstOperands,
     /*  987062 */     // GIR_Coverage, 13496,
     /*  987062 */     GIR_EraseRootFromParent_Done,
     /*  987063 */   // Label 15574: @987063
     /*  987063 */   GIM_Try, /*On fail goto*//*Label 15575*/ GIMT_Encode4(987149), // Rule ID 13497 //
     /*  987068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  987071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  987076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  987079 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  987086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987090 */     // MIs[0] Operand 3
     /*  987090 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987093 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987104 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987104 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987108 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987114 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64_SADDR),
     /*  987121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987128 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987147 */     GIR_RootConstrainSelectedInstOperands,
     /*  987148 */     // GIR_Coverage, 13497,
     /*  987148 */     GIR_EraseRootFromParent_Done,
     /*  987149 */   // Label 15575: @987149
     /*  987149 */   GIM_Try, /*On fail goto*//*Label 15576*/ GIMT_Encode4(987235), // Rule ID 13498 //
     /*  987154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  987157 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  987162 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  987165 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  987172 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987176 */     // MIs[0] Operand 3
     /*  987176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987179 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987190 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987190 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987194 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987200 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64_SADDR),
     /*  987207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987214 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987219 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987229 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987233 */     GIR_RootConstrainSelectedInstOperands,
     /*  987234 */     // GIR_Coverage, 13498,
     /*  987234 */     GIR_EraseRootFromParent_Done,
     /*  987235 */   // Label 15576: @987235
     /*  987235 */   GIM_Try, /*On fail goto*//*Label 15577*/ GIMT_Encode4(987321), // Rule ID 13504 //
     /*  987240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  987243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  987248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  987251 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  987258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987262 */     // MIs[0] Operand 3
     /*  987262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987265 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987269 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987276 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987276 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987280 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987286 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128_SADDR),
     /*  987293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987315 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987319 */     GIR_RootConstrainSelectedInstOperands,
     /*  987320 */     // GIR_Coverage, 13504,
     /*  987320 */     GIR_EraseRootFromParent_Done,
     /*  987321 */   // Label 15577: @987321
     /*  987321 */   GIM_Try, /*On fail goto*//*Label 15578*/ GIMT_Encode4(987407), // Rule ID 13505 //
     /*  987326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  987329 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  987334 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  987337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  987344 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987348 */     // MIs[0] Operand 3
     /*  987348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987351 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987355 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987362 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987362 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987366 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987372 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128_SADDR),
     /*  987379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987405 */     GIR_RootConstrainSelectedInstOperands,
     /*  987406 */     // GIR_Coverage, 13505,
     /*  987406 */     GIR_EraseRootFromParent_Done,
     /*  987407 */   // Label 15578: @987407
     /*  987407 */   GIM_Try, /*On fail goto*//*Label 15579*/ GIMT_Encode4(987493), // Rule ID 13506 //
     /*  987412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  987415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  987420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  987423 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  987430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987434 */     // MIs[0] Operand 3
     /*  987434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987437 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987448 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987448 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987452 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987458 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128_SADDR),
     /*  987465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987487 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987491 */     GIR_RootConstrainSelectedInstOperands,
     /*  987492 */     // GIR_Coverage, 13506,
     /*  987492 */     GIR_EraseRootFromParent_Done,
     /*  987493 */   // Label 15579: @987493
     /*  987493 */   GIM_Try, /*On fail goto*//*Label 15580*/ GIMT_Encode4(987579), // Rule ID 13507 //
     /*  987498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  987501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  987506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  987509 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  987516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987520 */     // MIs[0] Operand 3
     /*  987520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987523 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987534 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987534 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987538 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987544 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128_SADDR),
     /*  987551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987568 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987573 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987577 */     GIR_RootConstrainSelectedInstOperands,
     /*  987578 */     // GIR_Coverage, 13507,
     /*  987578 */     GIR_EraseRootFromParent_Done,
     /*  987579 */   // Label 15580: @987579
     /*  987579 */   GIM_Try, /*On fail goto*//*Label 15581*/ GIMT_Encode4(987665), // Rule ID 13508 //
     /*  987584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  987587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  987592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  987595 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  987602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987606 */     // MIs[0] Operand 3
     /*  987606 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987609 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr_cpol_m0),
     /*  987620 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalSAddrCPolM0:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset, CPol:{ *:[i32] }:$cpol), (timm:{ *:[i32] }), M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987620 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987624 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987630 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128_SADDR),
     /*  987637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
     /*  987644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
     /*  987649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /*  987654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // cpol
     /*  987659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987663 */     GIR_RootConstrainSelectedInstOperands,
     /*  987664 */     // GIR_Coverage, 13508,
     /*  987664 */     GIR_EraseRootFromParent_Done,
     /*  987665 */   // Label 15581: @987665
     /*  987665 */   GIM_Try, /*On fail goto*//*Label 15582*/ GIMT_Encode4(987743), // Rule ID 9338 //
     /*  987670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  987673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b32),
     /*  987678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  987681 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  987688 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987692 */     // MIs[0] cpol
     /*  987692 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987695 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  987706 */     // (intrinsic_w_chain:{ *:[i32] } 2249:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987706 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987710 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987716 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B32),
     /*  987723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  987730 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  987735 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  987737 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987741 */     GIR_RootConstrainSelectedInstOperands,
     /*  987742 */     // GIR_Coverage, 9338,
     /*  987742 */     GIR_EraseRootFromParent_Done,
     /*  987743 */   // Label 15582: @987743
     /*  987743 */   GIM_Try, /*On fail goto*//*Label 15583*/ GIMT_Encode4(987821), // Rule ID 9339 //
     /*  987748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  987751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b32),
     /*  987756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  987759 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  987766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987770 */     // MIs[0] cpol
     /*  987770 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987773 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  987784 */     // (intrinsic_w_chain:{ *:[i32] } 2249:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987784 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987788 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987794 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B32),
     /*  987801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  987808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  987813 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  987815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987819 */     GIR_RootConstrainSelectedInstOperands,
     /*  987820 */     // GIR_Coverage, 9339,
     /*  987820 */     GIR_EraseRootFromParent_Done,
     /*  987821 */   // Label 15583: @987821
     /*  987821 */   GIM_Try, /*On fail goto*//*Label 15584*/ GIMT_Encode4(987899), // Rule ID 9340 //
     /*  987826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  987829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b32),
     /*  987834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  987837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  987844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987848 */     // MIs[0] cpol
     /*  987848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987851 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987855 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  987862 */     // (intrinsic_w_chain:{ *:[i32] } 2249:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987862 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987866 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987872 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B32),
     /*  987879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  987886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  987891 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  987893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987897 */     GIR_RootConstrainSelectedInstOperands,
     /*  987898 */     // GIR_Coverage, 9340,
     /*  987898 */     GIR_EraseRootFromParent_Done,
     /*  987899 */   // Label 15584: @987899
     /*  987899 */   GIM_Try, /*On fail goto*//*Label 15585*/ GIMT_Encode4(987977), // Rule ID 9341 //
     /*  987904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  987907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b32),
     /*  987912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  987915 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  987922 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  987926 */     // MIs[0] cpol
     /*  987926 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  987929 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  987933 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  987940 */     // (intrinsic_w_chain:{ *:[i32] } 2249:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  987940 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  987944 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  987950 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  987954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B32),
     /*  987957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  987959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  987964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  987969 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  987971 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  987975 */     GIR_RootConstrainSelectedInstOperands,
     /*  987976 */     // GIR_Coverage, 9341,
     /*  987976 */     GIR_EraseRootFromParent_Done,
     /*  987977 */   // Label 15585: @987977
     /*  987977 */   GIM_Try, /*On fail goto*//*Label 15586*/ GIMT_Encode4(988055), // Rule ID 9342 //
     /*  987982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  987985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b32),
     /*  987990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /*  987993 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  987996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  988000 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988004 */     // MIs[0] cpol
     /*  988004 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988007 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988011 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988018 */     // (intrinsic_w_chain:{ *:[i32] } 2249:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B32:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988018 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988022 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988028 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B32),
     /*  988035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988042 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988047 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988049 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988053 */     GIR_RootConstrainSelectedInstOperands,
     /*  988054 */     // GIR_Coverage, 9342,
     /*  988054 */     GIR_EraseRootFromParent_Done,
     /*  988055 */   // Label 15586: @988055
     /*  988055 */   GIM_Try, /*On fail goto*//*Label 15587*/ GIMT_Encode4(988133), // Rule ID 13489 //
     /*  988060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  988063 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  988068 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  988071 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  988078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988082 */     // MIs[0] cpol
     /*  988082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988085 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988089 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988096 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988100 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988106 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64),
     /*  988113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988125 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988131 */     GIR_RootConstrainSelectedInstOperands,
     /*  988132 */     // GIR_Coverage, 13489,
     /*  988132 */     GIR_EraseRootFromParent_Done,
     /*  988133 */   // Label 15587: @988133
     /*  988133 */   GIM_Try, /*On fail goto*//*Label 15588*/ GIMT_Encode4(988211), // Rule ID 13490 //
     /*  988138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  988141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  988146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  988149 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  988156 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988160 */     // MIs[0] cpol
     /*  988160 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988163 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988167 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988174 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988174 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988178 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988184 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64),
     /*  988191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988203 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988209 */     GIR_RootConstrainSelectedInstOperands,
     /*  988210 */     // GIR_Coverage, 13490,
     /*  988210 */     GIR_EraseRootFromParent_Done,
     /*  988211 */   // Label 15588: @988211
     /*  988211 */   GIM_Try, /*On fail goto*//*Label 15589*/ GIMT_Encode4(988289), // Rule ID 13491 //
     /*  988216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  988219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  988224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  988227 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  988234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988238 */     // MIs[0] cpol
     /*  988238 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988241 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988245 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988252 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988252 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988256 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988262 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64),
     /*  988269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988281 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988287 */     GIR_RootConstrainSelectedInstOperands,
     /*  988288 */     // GIR_Coverage, 13491,
     /*  988288 */     GIR_EraseRootFromParent_Done,
     /*  988289 */   // Label 15589: @988289
     /*  988289 */   GIM_Try, /*On fail goto*//*Label 15590*/ GIMT_Encode4(988367), // Rule ID 13492 //
     /*  988294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  988297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  988302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  988305 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  988312 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988316 */     // MIs[0] cpol
     /*  988316 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988319 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988323 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988330 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988330 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988334 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988340 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64),
     /*  988347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988359 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988365 */     GIR_RootConstrainSelectedInstOperands,
     /*  988366 */     // GIR_Coverage, 13492,
     /*  988366 */     GIR_EraseRootFromParent_Done,
     /*  988367 */   // Label 15590: @988367
     /*  988367 */   GIM_Try, /*On fail goto*//*Label 15591*/ GIMT_Encode4(988445), // Rule ID 13493 //
     /*  988372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  988375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b64),
     /*  988380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /*  988383 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  988390 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988394 */     // MIs[0] cpol
     /*  988394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988397 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988401 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988408 */     // (intrinsic_w_chain:{ *:[v2i32] } 2250:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B64:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988408 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988412 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988418 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B64),
     /*  988425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988437 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988439 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988443 */     GIR_RootConstrainSelectedInstOperands,
     /*  988444 */     // GIR_Coverage, 13493,
     /*  988444 */     GIR_EraseRootFromParent_Done,
     /*  988445 */   // Label 15591: @988445
     /*  988445 */   GIM_Try, /*On fail goto*//*Label 15592*/ GIMT_Encode4(988523), // Rule ID 13499 //
     /*  988450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode0),
     /*  988453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  988458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  988461 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  988468 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988472 */     // MIs[0] cpol
     /*  988472 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988475 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988486 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988486 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988490 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988496 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128),
     /*  988503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988505 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988510 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988515 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988521 */     GIR_RootConstrainSelectedInstOperands,
     /*  988522 */     // GIR_Coverage, 13499,
     /*  988522 */     GIR_EraseRootFromParent_Done,
     /*  988523 */   // Label 15592: @988523
     /*  988523 */   GIM_Try, /*On fail goto*//*Label 15593*/ GIMT_Encode4(988601), // Rule ID 13500 //
     /*  988528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode1),
     /*  988531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  988536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  988539 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  988546 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988550 */     // MIs[0] cpol
     /*  988550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988553 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988557 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988564 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988564 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988568 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988574 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128),
     /*  988581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988588 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988593 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988595 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988599 */     GIR_RootConstrainSelectedInstOperands,
     /*  988600 */     // GIR_Coverage, 13500,
     /*  988600 */     GIR_EraseRootFromParent_Done,
     /*  988601 */   // Label 15593: @988601
     /*  988601 */   GIM_Try, /*On fail goto*//*Label 15594*/ GIMT_Encode4(988679), // Rule ID 13501 //
     /*  988606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode2),
     /*  988609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  988614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  988617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  988624 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988628 */     // MIs[0] cpol
     /*  988628 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988631 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988635 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988642 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988642 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988646 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988652 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128),
     /*  988659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988661 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988666 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988671 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988677 */     GIR_RootConstrainSelectedInstOperands,
     /*  988678 */     // GIR_Coverage, 13501,
     /*  988678 */     GIR_EraseRootFromParent_Done,
     /*  988679 */   // Label 15594: @988679
     /*  988679 */   GIM_Try, /*On fail goto*//*Label 15595*/ GIMT_Encode4(988757), // Rule ID 13502 //
     /*  988684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode3),
     /*  988687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  988692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  988695 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  988702 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988706 */     // MIs[0] cpol
     /*  988706 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988709 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988713 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988720 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988720 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988724 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988730 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128),
     /*  988737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988739 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988744 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988749 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988751 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988755 */     GIR_RootConstrainSelectedInstOperands,
     /*  988756 */     // GIR_Coverage, 13502,
     /*  988756 */     GIR_EraseRootFromParent_Done,
     /*  988757 */   // Label 15595: @988757
     /*  988757 */   GIM_Try, /*On fail goto*//*Label 15596*/ GIMT_Encode4(988835), // Rule ID 13503 //
     /*  988762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus_HwMode4),
     /*  988765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cluster_load_b128),
     /*  988770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  988773 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /*  988776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
     /*  988780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /*  988784 */     // MIs[0] cpol
     /*  988784 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /*  988787 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
     /*  988791 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
     /*  988798 */     // (intrinsic_w_chain:{ *:[v4i32] } 2248:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cpol, M0:{ *:[i32] })  =>  (CLUSTER_LOAD_B128:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset, ?:{ *:[i32] }:$cpol)
     /*  988798 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  988802 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /*  988808 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
     /*  988812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::CLUSTER_LOAD_B128),
     /*  988815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  988817 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
     /*  988822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /*  988827 */     GIR_RootToRootCopy, /*OpIdx*/3, // cpol
     /*  988829 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988833 */     GIR_RootConstrainSelectedInstOperands,
     /*  988834 */     // GIR_Coverage, 13503,
     /*  988834 */     GIR_EraseRootFromParent_Done,
     /*  988835 */   // Label 15596: @988835
     /*  988835 */   GIM_Reject,
     /*  988836 */ // Label 15570: @988836
     /*  988836 */ GIM_Try, /*On fail goto*//*Label 15597*/ GIMT_Encode4(988951),
     /*  988841 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /*  988844 */   GIM_Try, /*On fail goto*//*Label 15598*/ GIMT_Encode4(988897), // Rule ID 31087 //
     /*  988849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  988852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_tensor_load_to_lds),
     /*  988857 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  988860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  988863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  988866 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  988869 */     // MIs[0] cpol
     /*  988869 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  988872 */     // (intrinsic_void 3602:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vaddr0, v8i32:{ *:[v8i32] }:$vaddr1, v4i32:{ *:[v4i32] }:$vaddr2, v4i32:{ *:[v4i32] }:$vaddr3, (timm:{ *:[i32] }):$cpol)  =>  (TENSOR_LOAD_TO_LDS ?:{ *:[v4i32] }:$vaddr0, ?:{ *:[v8i32] }:$vaddr1, ?:{ *:[v4i32] }:$vaddr2, ?:{ *:[v4i32] }:$vaddr3, 0:{ *:[i1] }, ?:{ *:[i32] }:$cpol)
     /*  988872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TENSOR_LOAD_TO_LDS),
     /*  988875 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr0
     /*  988877 */     GIR_RootToRootCopy, /*OpIdx*/2, // vaddr1
     /*  988879 */     GIR_RootToRootCopy, /*OpIdx*/3, // vaddr2
     /*  988881 */     GIR_RootToRootCopy, /*OpIdx*/4, // vaddr3
     /*  988883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  988886 */     GIR_RootToRootCopy, /*OpIdx*/5, // cpol
     /*  988888 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::TENSORcnt*/0,
     /*  988891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988895 */     GIR_RootConstrainSelectedInstOperands,
     /*  988896 */     // GIR_Coverage, 31087,
     /*  988896 */     GIR_EraseRootFromParent_Done,
     /*  988897 */   // Label 15598: @988897
     /*  988897 */   GIM_Try, /*On fail goto*//*Label 15599*/ GIMT_Encode4(988950), // Rule ID 31088 //
     /*  988902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX1250Plus),
     /*  988905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_tensor_store_from_lds),
     /*  988910 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  988913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s32,
     /*  988916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  988919 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /*  988922 */     // MIs[0] cpol
     /*  988922 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /*  988925 */     // (intrinsic_void 3604:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vaddr0, v8i32:{ *:[v8i32] }:$vaddr1, v4i32:{ *:[v4i32] }:$vaddr2, v4i32:{ *:[v4i32] }:$vaddr3, (timm:{ *:[i32] }):$cpol)  =>  (TENSOR_STORE_FROM_LDS ?:{ *:[v4i32] }:$vaddr0, ?:{ *:[v8i32] }:$vaddr1, ?:{ *:[v4i32] }:$vaddr2, ?:{ *:[v4i32] }:$vaddr3, 0:{ *:[i1] }, ?:{ *:[i32] }:$cpol)
     /*  988925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TENSOR_STORE_FROM_LDS),
     /*  988928 */     GIR_RootToRootCopy, /*OpIdx*/1, // vaddr0
     /*  988930 */     GIR_RootToRootCopy, /*OpIdx*/2, // vaddr1
     /*  988932 */     GIR_RootToRootCopy, /*OpIdx*/3, // vaddr2
     /*  988934 */     GIR_RootToRootCopy, /*OpIdx*/4, // vaddr3
     /*  988936 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  988939 */     GIR_RootToRootCopy, /*OpIdx*/5, // cpol
     /*  988941 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::TENSORcnt*/0,
     /*  988944 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /*  988948 */     GIR_RootConstrainSelectedInstOperands,
     /*  988949 */     // GIR_Coverage, 31088,
     /*  988949 */     GIR_EraseRootFromParent_Done,
     /*  988950 */   // Label 15599: @988950
     /*  988950 */   GIM_Reject,
     /*  988951 */ // Label 15597: @988951
     /*  988951 */ GIM_Reject,
     /*  988952 */ // Label 42: @988952
     /*  988952 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 15603*/ GIMT_Encode4(990236),
     /*  988963 */ /*GILLT_s16*//*Label 15600*/ GIMT_Encode4(988975),
     /*  988967 */ /*GILLT_s32*//*Label 15601*/ GIMT_Encode4(989134),
     /*  988971 */ /*GILLT_s64*//*Label 15602*/ GIMT_Encode4(989380),
     /*  988975 */ // Label 15600: @988975
     /*  988975 */ GIM_Try, /*On fail goto*//*Label 15604*/ GIMT_Encode4(989133),
     /*  988980 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  988983 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  988987 */   GIM_Try, /*On fail goto*//*Label 15605*/ GIMT_Encode4(989016), // Rule ID 7199 //
     /*  988992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  988995 */     // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  988995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  988998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989000 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989003 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989006 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989012 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989014 */     GIR_RootConstrainSelectedInstOperands,
     /*  989015 */     // GIR_Coverage, 7199,
     /*  989015 */     GIR_EraseRootFromParent_Done,
     /*  989016 */   // Label 15605: @989016
     /*  989016 */   GIM_Try, /*On fail goto*//*Label 15606*/ GIMT_Encode4(989045), // Rule ID 7200 //
     /*  989021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  989024 */     // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  989024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989029 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989035 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989038 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989041 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989043 */     GIR_RootConstrainSelectedInstOperands,
     /*  989044 */     // GIR_Coverage, 7200,
     /*  989044 */     GIR_EraseRootFromParent_Done,
     /*  989045 */   // Label 15606: @989045
     /*  989045 */   GIM_Try, /*On fail goto*//*Label 15607*/ GIMT_Encode4(989074), // Rule ID 7201 //
     /*  989050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  989053 */     // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  989053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989061 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989067 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989070 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989072 */     GIR_RootConstrainSelectedInstOperands,
     /*  989073 */     // GIR_Coverage, 7201,
     /*  989073 */     GIR_EraseRootFromParent_Done,
     /*  989074 */   // Label 15607: @989074
     /*  989074 */   GIM_Try, /*On fail goto*//*Label 15608*/ GIMT_Encode4(989103), // Rule ID 7202 //
     /*  989079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  989082 */     // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  989082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989093 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989099 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989101 */     GIR_RootConstrainSelectedInstOperands,
     /*  989102 */     // GIR_Coverage, 7202,
     /*  989102 */     GIR_EraseRootFromParent_Done,
     /*  989103 */   // Label 15608: @989103
     /*  989103 */   GIM_Try, /*On fail goto*//*Label 15609*/ GIMT_Encode4(989132), // Rule ID 7203 //
     /*  989108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  989111 */     // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  989111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989116 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989119 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989125 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989128 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989130 */     GIR_RootConstrainSelectedInstOperands,
     /*  989131 */     // GIR_Coverage, 7203,
     /*  989131 */     GIR_EraseRootFromParent_Done,
     /*  989132 */   // Label 15609: @989132
     /*  989132 */   GIM_Reject,
     /*  989133 */ // Label 15604: @989133
     /*  989133 */ GIM_Reject,
     /*  989134 */ // Label 15601: @989134
     /*  989134 */ GIM_Try, /*On fail goto*//*Label 15610*/ GIMT_Encode4(989199), // Rule ID 7068 //
     /*  989139 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  989142 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  989145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989149 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26715),
     /*  989153 */   // (anyext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_26715>>  =>  (REG_SEQUENCE:{ *:[i32] } VGPR_32:{ *:[i32] }, ?:{ *:[i16] }:$src, lo16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), hi16:{ *:[i32] })
     /*  989153 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  989156 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  989160 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989165 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989170 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989172 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989174 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*  989177 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989180 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*  989183 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989188 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  989193 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  989198 */   // GIR_Coverage, 7068,
     /*  989198 */   GIR_EraseRootFromParent_Done,
     /*  989199 */ // Label 15610: @989199
     /*  989199 */ GIM_Try, /*On fail goto*//*Label 15611*/ GIMT_Encode4(989235), // Rule ID 28011 //
     /*  989204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  989207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989214 */   // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  989214 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989217 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989219 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989222 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989225 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989228 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989231 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  989233 */   GIR_RootConstrainSelectedInstOperands,
     /*  989234 */   // GIR_Coverage, 28011,
     /*  989234 */   GIR_EraseRootFromParent_Done,
     /*  989235 */ // Label 15611: @989235
     /*  989235 */ GIM_Try, /*On fail goto*//*Label 15612*/ GIMT_Encode4(989271), // Rule ID 28012 //
     /*  989240 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  989243 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989250 */   // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  989250 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989253 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989255 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989258 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989261 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989264 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989267 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  989269 */   GIR_RootConstrainSelectedInstOperands,
     /*  989270 */   // GIR_Coverage, 28012,
     /*  989270 */   GIR_EraseRootFromParent_Done,
     /*  989271 */ // Label 15612: @989271
     /*  989271 */ GIM_Try, /*On fail goto*//*Label 15613*/ GIMT_Encode4(989307), // Rule ID 28013 //
     /*  989276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  989279 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989286 */   // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  989286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989291 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989294 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989297 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989300 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989303 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  989305 */   GIR_RootConstrainSelectedInstOperands,
     /*  989306 */   // GIR_Coverage, 28013,
     /*  989306 */   GIR_EraseRootFromParent_Done,
     /*  989307 */ // Label 15613: @989307
     /*  989307 */ GIM_Try, /*On fail goto*//*Label 15614*/ GIMT_Encode4(989343), // Rule ID 28014 //
     /*  989312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  989315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989322 */   // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  989322 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989325 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989327 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989330 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989333 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989336 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989339 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  989341 */   GIR_RootConstrainSelectedInstOperands,
     /*  989342 */   // GIR_Coverage, 28014,
     /*  989342 */   GIR_EraseRootFromParent_Done,
     /*  989343 */ // Label 15614: @989343
     /*  989343 */ GIM_Try, /*On fail goto*//*Label 15615*/ GIMT_Encode4(989379), // Rule ID 28015 //
     /*  989348 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  989351 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989354 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989358 */   // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  989358 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989361 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  989363 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989366 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989369 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  989372 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  989375 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  989377 */   GIR_RootConstrainSelectedInstOperands,
     /*  989378 */   // GIR_Coverage, 28015,
     /*  989378 */   GIR_EraseRootFromParent_Done,
     /*  989379 */ // Label 15615: @989379
     /*  989379 */ GIM_Reject,
     /*  989380 */ // Label 15602: @989380
     /*  989380 */ GIM_Try, /*On fail goto*//*Label 15616*/ GIMT_Encode4(989467), // Rule ID 7069 //
     /*  989385 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  989388 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  989391 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989395 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26713),
     /*  989399 */   // (anyext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_26713>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (COPY:{ *:[i32] } ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989399 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  989402 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  989406 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989411 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  989414 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  989416 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  989419 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  989423 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989428 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  989432 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989439 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989442 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  989445 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  989448 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989451 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989456 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989461 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989466 */   // GIR_Coverage, 7069,
     /*  989466 */   GIR_EraseRootFromParent_Done,
     /*  989467 */ // Label 15616: @989467
     /*  989467 */ GIM_Try, /*On fail goto*//*Label 15617*/ GIMT_Encode4(989557), // Rule ID 7070 //
     /*  989472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  989475 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  989478 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989482 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26715),
     /*  989486 */   // (anyext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_26715>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i16] }:$src, lo16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), hi16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989486 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  989489 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  989493 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989498 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  989500 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  989503 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  989507 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989512 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989514 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989517 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989519 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989521 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*  989524 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989527 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*  989530 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  989533 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989536 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989541 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  989546 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  989551 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/5, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989556 */   // GIR_Coverage, 7070,
     /*  989556 */   GIR_EraseRootFromParent_Done,
     /*  989557 */ // Label 15617: @989557
     /*  989557 */ GIM_Try, /*On fail goto*//*Label 15618*/ GIMT_Encode4(989619), // Rule ID 28123 //
     /*  989562 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  989565 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  989569 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26713),
     /*  989573 */   // (anyext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_26713>>  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989573 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  989576 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  989580 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989585 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989592 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989594 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  989597 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989600 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989603 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  989608 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  989613 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  989618 */   // GIR_Coverage, 28123,
     /*  989618 */   GIR_EraseRootFromParent_Done,
     /*  989619 */ // Label 15618: @989619
     /*  989619 */ GIM_Try, /*On fail goto*//*Label 15619*/ GIMT_Encode4(989702), // Rule ID 7064 //
     /*  989624 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_isGFX8Plus),
     /*  989627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  989630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989634 */   // (anyext:{ *:[i64] } i16:{ *:[i16] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (COPY:{ *:[i32] } ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989634 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  989637 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  989641 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989646 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  989649 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  989651 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  989654 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  989658 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989663 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  989667 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989669 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989672 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989674 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989677 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  989680 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  989683 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989686 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989691 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989696 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989701 */   // GIR_Coverage, 7064,
     /*  989701 */   GIR_EraseRootFromParent_Done,
     /*  989702 */ // Label 15619: @989702
     /*  989702 */ GIM_Try, /*On fail goto*//*Label 15620*/ GIMT_Encode4(989760), // Rule ID 28124 //
     /*  989707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  989710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989714 */   // (anyext:{ *:[i64] } i32:{ *:[i32] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989714 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  989717 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  989721 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989726 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989731 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989733 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  989735 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  989738 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989741 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989744 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989749 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989754 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989759 */   // GIR_Coverage, 28124,
     /*  989759 */   GIR_EraseRootFromParent_Done,
     /*  989760 */ // Label 15620: @989760
     /*  989760 */ GIM_Try, /*On fail goto*//*Label 15621*/ GIMT_Encode4(989855), // Rule ID 28130 //
     /*  989765 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  989768 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989771 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989775 */   // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989775 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  989778 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  989782 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989787 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  989790 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  989792 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  989795 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989799 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989804 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989807 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989810 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989813 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  989816 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  989820 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989825 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989827 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989830 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  989833 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  989836 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989839 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989844 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989849 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989854 */   // GIR_Coverage, 28130,
     /*  989854 */   GIR_EraseRootFromParent_Done,
     /*  989855 */ // Label 15621: @989855
     /*  989855 */ GIM_Try, /*On fail goto*//*Label 15622*/ GIMT_Encode4(989950), // Rule ID 28131 //
     /*  989860 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  989863 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989870 */   // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989870 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  989873 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  989877 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989882 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  989885 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  989887 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  989890 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989894 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989899 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989902 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989905 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989908 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  989911 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  989915 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  989917 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  989920 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  989922 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  989925 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  989928 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  989931 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  989934 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989939 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989944 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  989949 */   // GIR_Coverage, 28131,
     /*  989949 */   GIR_EraseRootFromParent_Done,
     /*  989950 */ // Label 15622: @989950
     /*  989950 */ GIM_Try, /*On fail goto*//*Label 15623*/ GIMT_Encode4(990045), // Rule ID 28132 //
     /*  989955 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  989958 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  989961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  989965 */   // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  989965 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  989968 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  989972 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989977 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  989980 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  989982 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  989985 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  989989 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  989994 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  989997 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990000 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990003 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990006 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  990010 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990012 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  990015 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  990017 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990020 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  990023 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  990026 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  990029 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  990034 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  990039 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  990044 */   // GIR_Coverage, 28132,
     /*  990044 */   GIR_EraseRootFromParent_Done,
     /*  990045 */ // Label 15623: @990045
     /*  990045 */ GIM_Try, /*On fail goto*//*Label 15624*/ GIMT_Encode4(990140), // Rule ID 28133 //
     /*  990050 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  990053 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  990056 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  990060 */   // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  990060 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  990063 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  990067 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990072 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  990075 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  990077 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990080 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  990084 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990089 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990092 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990095 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990098 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990101 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  990105 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  990110 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  990112 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990115 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  990118 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  990121 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  990124 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  990129 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  990134 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  990139 */   // GIR_Coverage, 28133,
     /*  990139 */   GIR_EraseRootFromParent_Done,
     /*  990140 */ // Label 15624: @990140
     /*  990140 */ GIM_Try, /*On fail goto*//*Label 15625*/ GIMT_Encode4(990235), // Rule ID 28134 //
     /*  990145 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  990148 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  990151 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  990155 */   // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  990155 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  990158 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  990162 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990167 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  990170 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  990172 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990175 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  990179 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990184 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990187 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990190 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990193 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990196 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  990200 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990202 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  990205 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  990207 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990210 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  990213 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  990216 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  990219 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  990224 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  990229 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  990234 */   // GIR_Coverage, 28134,
     /*  990234 */   GIR_EraseRootFromParent_Done,
     /*  990235 */ // Label 15625: @990235
     /*  990235 */ GIM_Reject,
     /*  990236 */ // Label 15603: @990236
     /*  990236 */ GIM_Reject,
     /*  990237 */ // Label 43: @990237
     /*  990237 */ GIM_Try, /*On fail goto*//*Label 15626*/ GIMT_Encode4(991138),
     /*  990242 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /*  990245 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 15629*/ GIMT_Encode4(991087),
     /*  990256 */   /*GILLT_s16*//*Label 15627*/ GIMT_Encode4(990264),
     /*  990260 */   /*GILLT_s32*//*Label 15628*/ GIMT_Encode4(990789),
     /*  990264 */   // Label 15627: @990264
     /*  990264 */   GIM_Try, /*On fail goto*//*Label 15630*/ GIMT_Encode4(990788),
     /*  990269 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26721),
     /*  990273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  990277 */     GIM_Try, /*On fail goto*//*Label 15631*/ GIMT_Encode4(990319), // Rule ID 28263 //
     /*  990282 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_HwMode0),
     /*  990285 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
     /*  990285 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990288 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990292 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990297 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990300 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990304 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990306 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990309 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990311 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990314 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990317 */       GIR_RootConstrainSelectedInstOperands,
     /*  990318 */       // GIR_Coverage, 28263,
     /*  990318 */       GIR_EraseRootFromParent_Done,
     /*  990319 */     // Label 15631: @990319
     /*  990319 */     GIM_Try, /*On fail goto*//*Label 15632*/ GIMT_Encode4(990361), // Rule ID 28264 //
     /*  990324 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_HwMode1),
     /*  990327 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
     /*  990327 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990330 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990334 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990339 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990342 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990346 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990348 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990351 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990353 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990356 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990359 */       GIR_RootConstrainSelectedInstOperands,
     /*  990360 */       // GIR_Coverage, 28264,
     /*  990360 */       GIR_EraseRootFromParent_Done,
     /*  990361 */     // Label 15632: @990361
     /*  990361 */     GIM_Try, /*On fail goto*//*Label 15633*/ GIMT_Encode4(990403), // Rule ID 28265 //
     /*  990366 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_HwMode2),
     /*  990369 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
     /*  990369 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990372 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990376 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990381 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990384 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990388 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990390 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990393 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990395 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990398 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990401 */       GIR_RootConstrainSelectedInstOperands,
     /*  990402 */       // GIR_Coverage, 28265,
     /*  990402 */       GIR_EraseRootFromParent_Done,
     /*  990403 */     // Label 15633: @990403
     /*  990403 */     GIM_Try, /*On fail goto*//*Label 15634*/ GIMT_Encode4(990445), // Rule ID 28266 //
     /*  990408 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_HwMode3),
     /*  990411 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
     /*  990411 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990414 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990418 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990423 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990426 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990430 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990432 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990435 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990437 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990440 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990443 */       GIR_RootConstrainSelectedInstOperands,
     /*  990444 */       // GIR_Coverage, 28266,
     /*  990444 */       GIR_EraseRootFromParent_Done,
     /*  990445 */     // Label 15634: @990445
     /*  990445 */     GIM_Try, /*On fail goto*//*Label 15635*/ GIMT_Encode4(990487), // Rule ID 28267 //
     /*  990450 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_HwMode4),
     /*  990453 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
     /*  990453 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990456 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990460 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990465 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990468 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990472 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990474 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990477 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990479 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990482 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990485 */       GIR_RootConstrainSelectedInstOperands,
     /*  990486 */       // GIR_Coverage, 28267,
     /*  990486 */       GIR_EraseRootFromParent_Done,
     /*  990487 */     // Label 15635: @990487
     /*  990487 */     GIM_Try, /*On fail goto*//*Label 15636*/ GIMT_Encode4(990547), // Rule ID 28271 //
     /*  990492 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode0),
     /*  990495 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, (V_AND_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] }, ?:{ *:[i16] }:$a), 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] })
     /*  990495 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990498 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
     /*  990502 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990507 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990510 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990513 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990516 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990520 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990523 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990525 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /*  990528 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990530 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990533 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990536 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990539 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990542 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990545 */       GIR_RootConstrainSelectedInstOperands,
     /*  990546 */       // GIR_Coverage, 28271,
     /*  990546 */       GIR_EraseRootFromParent_Done,
     /*  990547 */     // Label 15636: @990547
     /*  990547 */     GIM_Try, /*On fail goto*//*Label 15637*/ GIMT_Encode4(990607), // Rule ID 28272 //
     /*  990552 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode1),
     /*  990555 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, (V_AND_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] }, ?:{ *:[i16] }:$a), 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] })
     /*  990555 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990558 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
     /*  990562 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990567 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990570 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990573 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990576 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990580 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990583 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990585 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /*  990588 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990590 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990593 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990596 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990599 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990602 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990605 */       GIR_RootConstrainSelectedInstOperands,
     /*  990606 */       // GIR_Coverage, 28272,
     /*  990606 */       GIR_EraseRootFromParent_Done,
     /*  990607 */     // Label 15637: @990607
     /*  990607 */     GIM_Try, /*On fail goto*//*Label 15638*/ GIMT_Encode4(990667), // Rule ID 28273 //
     /*  990612 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode2),
     /*  990615 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, (V_AND_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] }, ?:{ *:[i16] }:$a), 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] })
     /*  990615 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990618 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
     /*  990622 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990627 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990630 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990633 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990636 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990640 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990643 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990645 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /*  990648 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990650 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990653 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990656 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990659 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990662 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990665 */       GIR_RootConstrainSelectedInstOperands,
     /*  990666 */       // GIR_Coverage, 28273,
     /*  990666 */       GIR_EraseRootFromParent_Done,
     /*  990667 */     // Label 15638: @990667
     /*  990667 */     GIM_Try, /*On fail goto*//*Label 15639*/ GIMT_Encode4(990727), // Rule ID 28274 //
     /*  990672 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode3),
     /*  990675 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, (V_AND_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] }, ?:{ *:[i16] }:$a), 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] })
     /*  990675 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990678 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
     /*  990682 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990687 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990690 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990693 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990696 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990700 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990703 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990705 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /*  990708 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990710 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990713 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990716 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990719 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990722 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990725 */       GIR_RootConstrainSelectedInstOperands,
     /*  990726 */       // GIR_Coverage, 28274,
     /*  990726 */       GIR_EraseRootFromParent_Done,
     /*  990727 */     // Label 15639: @990727
     /*  990727 */     GIM_Try, /*On fail goto*//*Label 15640*/ GIMT_Encode4(990787), // Rule ID 28275 //
     /*  990732 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_HwMode4),
     /*  990735 */       // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, (V_AND_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] }, ?:{ *:[i16] }:$a), 0:{ *:[i32] }, 1:{ *:[i16] }, 0:{ *:[i32] })
     /*  990735 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990738 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
     /*  990742 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990747 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990750 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990753 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990756 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990760 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  990763 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990765 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /*  990768 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990770 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990773 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990776 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990779 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990782 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  990785 */       GIR_RootConstrainSelectedInstOperands,
     /*  990786 */       // GIR_Coverage, 28275,
     /*  990786 */       GIR_EraseRootFromParent_Done,
     /*  990787 */     // Label 15640: @990787
     /*  990787 */     GIM_Reject,
     /*  990788 */   // Label 15630: @990788
     /*  990788 */   GIM_Reject,
     /*  990789 */   // Label 15628: @990789
     /*  990789 */   GIM_Try, /*On fail goto*//*Label 15641*/ GIMT_Encode4(990839), // Rule ID 28280 //
     /*  990794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  990797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  990801 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26721),
     /*  990805 */     // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*  990805 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990808 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990812 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990817 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990820 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990824 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990831 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990837 */     GIR_RootConstrainSelectedInstOperands,
     /*  990838 */     // GIR_Coverage, 28280,
     /*  990838 */     GIR_EraseRootFromParent_Done,
     /*  990839 */   // Label 15641: @990839
     /*  990839 */   GIM_Try, /*On fail goto*//*Label 15642*/ GIMT_Encode4(990889), // Rule ID 28281 //
     /*  990844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  990847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  990851 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26721),
     /*  990855 */     // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*  990855 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990858 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990862 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990867 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990870 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990874 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990881 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990887 */     GIR_RootConstrainSelectedInstOperands,
     /*  990888 */     // GIR_Coverage, 28281,
     /*  990888 */     GIR_EraseRootFromParent_Done,
     /*  990889 */   // Label 15642: @990889
     /*  990889 */   GIM_Try, /*On fail goto*//*Label 15643*/ GIMT_Encode4(990939), // Rule ID 28282 //
     /*  990894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  990897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  990901 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26721),
     /*  990905 */     // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*  990905 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990908 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990912 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990917 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990920 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990924 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990931 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990937 */     GIR_RootConstrainSelectedInstOperands,
     /*  990938 */     // GIR_Coverage, 28282,
     /*  990938 */     GIR_EraseRootFromParent_Done,
     /*  990939 */   // Label 15643: @990939
     /*  990939 */   GIM_Try, /*On fail goto*//*Label 15644*/ GIMT_Encode4(990989), // Rule ID 28283 //
     /*  990944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  990947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  990951 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26721),
     /*  990955 */     // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*  990955 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  990958 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  990962 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  990967 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  990970 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  990974 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  990976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  990979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  990981 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  990984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  990987 */     GIR_RootConstrainSelectedInstOperands,
     /*  990988 */     // GIR_Coverage, 28283,
     /*  990988 */     GIR_EraseRootFromParent_Done,
     /*  990989 */   // Label 15644: @990989
     /*  990989 */   GIM_Try, /*On fail goto*//*Label 15645*/ GIMT_Encode4(991039), // Rule ID 28284 //
     /*  990994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  990997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  991001 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26721),
     /*  991005 */     // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_26721>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*  991005 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  991008 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  991012 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  991017 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  991020 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  991024 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  991026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
     /*  991029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991031 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  991034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  991037 */     GIR_RootConstrainSelectedInstOperands,
     /*  991038 */     // GIR_Coverage, 28284,
     /*  991038 */     GIR_EraseRootFromParent_Done,
     /*  991039 */   // Label 15645: @991039
     /*  991039 */   GIM_Try, /*On fail goto*//*Label 15646*/ GIMT_Encode4(991086), // Rule ID 28277 //
     /*  991044 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26719),
     /*  991048 */     // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_26719>>  =>  (S_CMP_EQ_U32:{ *:[i1] } (S_AND_B32:{ *:[i1] }:{ *:[i1] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
     /*  991048 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  991051 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*  991055 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  991060 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  991063 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  991067 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AMDGPU::SCC*/0,
     /*  991070 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  991072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_CMP_EQ_U32),
     /*  991075 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  991078 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  991081 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  991084 */     GIR_RootConstrainSelectedInstOperands,
     /*  991085 */     // GIR_Coverage, 28277,
     /*  991085 */     GIR_EraseRootFromParent_Done,
     /*  991086 */   // Label 15646: @991086
     /*  991086 */   GIM_Reject,
     /*  991087 */   // Label 15629: @991087
     /*  991087 */   GIM_Try, /*On fail goto*//*Label 15647*/ GIMT_Encode4(991137), // Rule ID 28278 //
     /*  991092 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  991095 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_26719),
     /*  991099 */     // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_26719>>  =>  (S_CMP_EQ_U32:{ *:[i1] } (S_AND_B32:{ *:[i1] }:{ *:[i1] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
     /*  991099 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  991102 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*  991106 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  991111 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  991114 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
     /*  991118 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AMDGPU::SCC*/0,
     /*  991121 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  991123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_CMP_EQ_U32),
     /*  991126 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  991129 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  991132 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  991135 */     GIR_RootConstrainSelectedInstOperands,
     /*  991136 */     // GIR_Coverage, 28278,
     /*  991136 */     GIR_EraseRootFromParent_Done,
     /*  991137 */   // Label 15647: @991137
     /*  991137 */   GIM_Reject,
     /*  991138 */ // Label 15626: @991138
     /*  991138 */ GIM_Reject,
     /*  991139 */ // Label 44: @991139
     /*  991139 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(11), /*)*//*default:*//*Label 15659*/ GIMT_Encode4(992373),
     /*  991150 */ /*GILLT_p0s64*//*Label 15648*/ GIMT_Encode4(991194),
     /*  991154 */ /*GILLT_p1s64*//*Label 15649*/ GIMT_Encode4(991344),
     /*  991158 */ /*GILLT_p2s32*//*Label 15650*/ GIMT_Encode4(991494),
     /*  991162 */ /*GILLT_p3s32*//*Label 15651*/ GIMT_Encode4(991537),
     /*  991166 */ /*GILLT_p4s64*//*Label 15652*/ GIMT_Encode4(991580),
     /*  991170 */ /*GILLT_p5s32*//*Label 15653*/ GIMT_Encode4(991730),
     /*  991174 */ /*GILLT_p6s32*//*Label 15654*/ GIMT_Encode4(991773),
     /*  991178 */ /*GILLT_s1*//*Label 15655*/ GIMT_Encode4(991816),
     /*  991182 */ /*GILLT_s16*//*Label 15656*/ GIMT_Encode4(991861),
     /*  991186 */ /*GILLT_s32*//*Label 15657*/ GIMT_Encode4(991939),
     /*  991190 */ /*GILLT_s64*//*Label 15658*/ GIMT_Encode4(991982),
     /*  991194 */ // Label 15648: @991194
     /*  991194 */ GIM_Try, /*On fail goto*//*Label 15660*/ GIMT_Encode4(991220), // Rule ID 27976 //
     /*  991199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  991202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991206 */   // MIs[0] Operand 1
     /*  991206 */   // No operand predicates
     /*  991206 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45080),
     /*  991210 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45080>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991215 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991218 */   GIR_RootConstrainSelectedInstOperands,
     /*  991219 */   // GIR_Coverage, 27976,
     /*  991219 */   GIR_EraseRootFromParent_Done,
     /*  991220 */ // Label 15660: @991220
     /*  991220 */ GIM_Try, /*On fail goto*//*Label 15661*/ GIMT_Encode4(991246), // Rule ID 27977 //
     /*  991225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  991228 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991232 */   // MIs[0] Operand 1
     /*  991232 */   // No operand predicates
     /*  991232 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45080),
     /*  991236 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45080>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991236 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991239 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991241 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991244 */   GIR_RootConstrainSelectedInstOperands,
     /*  991245 */   // GIR_Coverage, 27977,
     /*  991245 */   GIR_EraseRootFromParent_Done,
     /*  991246 */ // Label 15661: @991246
     /*  991246 */ GIM_Try, /*On fail goto*//*Label 15662*/ GIMT_Encode4(991272), // Rule ID 27978 //
     /*  991251 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  991254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991258 */   // MIs[0] Operand 1
     /*  991258 */   // No operand predicates
     /*  991258 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45080),
     /*  991262 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45080>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991267 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991270 */   GIR_RootConstrainSelectedInstOperands,
     /*  991271 */   // GIR_Coverage, 27978,
     /*  991271 */   GIR_EraseRootFromParent_Done,
     /*  991272 */ // Label 15662: @991272
     /*  991272 */ GIM_Try, /*On fail goto*//*Label 15663*/ GIMT_Encode4(991298), // Rule ID 27979 //
     /*  991277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  991280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991284 */   // MIs[0] Operand 1
     /*  991284 */   // No operand predicates
     /*  991284 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45080),
     /*  991288 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45080>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991288 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991291 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991293 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991296 */   GIR_RootConstrainSelectedInstOperands,
     /*  991297 */   // GIR_Coverage, 27979,
     /*  991297 */   GIR_EraseRootFromParent_Done,
     /*  991298 */ // Label 15663: @991298
     /*  991298 */ GIM_Try, /*On fail goto*//*Label 15664*/ GIMT_Encode4(991324), // Rule ID 27980 //
     /*  991303 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  991306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991310 */   // MIs[0] Operand 1
     /*  991310 */   // No operand predicates
     /*  991310 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45080),
     /*  991314 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45080>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991314 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991317 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991319 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991322 */   GIR_RootConstrainSelectedInstOperands,
     /*  991323 */   // GIR_Coverage, 27980,
     /*  991323 */   GIR_EraseRootFromParent_Done,
     /*  991324 */ // Label 15664: @991324
     /*  991324 */ GIM_Try, /*On fail goto*//*Label 15665*/ GIMT_Encode4(991343), // Rule ID 27982 //
     /*  991329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  991333 */   // MIs[0] Operand 1
     /*  991333 */   // No operand predicates
     /*  991333 */   // (imm:{ *:[i64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991333 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  991336 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991338 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991341 */   GIR_RootConstrainSelectedInstOperands,
     /*  991342 */   // GIR_Coverage, 27982,
     /*  991342 */   GIR_EraseRootFromParent_Done,
     /*  991343 */ // Label 15665: @991343
     /*  991343 */ GIM_Reject,
     /*  991344 */ // Label 15649: @991344
     /*  991344 */ GIM_Try, /*On fail goto*//*Label 15666*/ GIMT_Encode4(991370), // Rule ID 27969 //
     /*  991349 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  991352 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991356 */   // MIs[0] Operand 1
     /*  991356 */   // No operand predicates
     /*  991356 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45076),
     /*  991360 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45076>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991365 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991368 */   GIR_RootConstrainSelectedInstOperands,
     /*  991369 */   // GIR_Coverage, 27969,
     /*  991369 */   GIR_EraseRootFromParent_Done,
     /*  991370 */ // Label 15666: @991370
     /*  991370 */ GIM_Try, /*On fail goto*//*Label 15667*/ GIMT_Encode4(991396), // Rule ID 27970 //
     /*  991375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  991378 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991382 */   // MIs[0] Operand 1
     /*  991382 */   // No operand predicates
     /*  991382 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45076),
     /*  991386 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45076>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991386 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991389 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991391 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991394 */   GIR_RootConstrainSelectedInstOperands,
     /*  991395 */   // GIR_Coverage, 27970,
     /*  991395 */   GIR_EraseRootFromParent_Done,
     /*  991396 */ // Label 15667: @991396
     /*  991396 */ GIM_Try, /*On fail goto*//*Label 15668*/ GIMT_Encode4(991422), // Rule ID 27971 //
     /*  991401 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  991404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991408 */   // MIs[0] Operand 1
     /*  991408 */   // No operand predicates
     /*  991408 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45076),
     /*  991412 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45076>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991415 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991417 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991420 */   GIR_RootConstrainSelectedInstOperands,
     /*  991421 */   // GIR_Coverage, 27971,
     /*  991421 */   GIR_EraseRootFromParent_Done,
     /*  991422 */ // Label 15668: @991422
     /*  991422 */ GIM_Try, /*On fail goto*//*Label 15669*/ GIMT_Encode4(991448), // Rule ID 27972 //
     /*  991427 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  991430 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991434 */   // MIs[0] Operand 1
     /*  991434 */   // No operand predicates
     /*  991434 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45076),
     /*  991438 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45076>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991441 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991443 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991446 */   GIR_RootConstrainSelectedInstOperands,
     /*  991447 */   // GIR_Coverage, 27972,
     /*  991447 */   GIR_EraseRootFromParent_Done,
     /*  991448 */ // Label 15669: @991448
     /*  991448 */ GIM_Try, /*On fail goto*//*Label 15670*/ GIMT_Encode4(991474), // Rule ID 27973 //
     /*  991453 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  991456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991460 */   // MIs[0] Operand 1
     /*  991460 */   // No operand predicates
     /*  991460 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45076),
     /*  991464 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45076>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991467 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991469 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991472 */   GIR_RootConstrainSelectedInstOperands,
     /*  991473 */   // GIR_Coverage, 27973,
     /*  991473 */   GIR_EraseRootFromParent_Done,
     /*  991474 */ // Label 15670: @991474
     /*  991474 */ GIM_Try, /*On fail goto*//*Label 15671*/ GIMT_Encode4(991493), // Rule ID 27975 //
     /*  991479 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  991483 */   // MIs[0] Operand 1
     /*  991483 */   // No operand predicates
     /*  991483 */   // (imm:{ *:[i64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991483 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  991486 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991488 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991491 */   GIR_RootConstrainSelectedInstOperands,
     /*  991492 */   // GIR_Coverage, 27975,
     /*  991492 */   GIR_EraseRootFromParent_Done,
     /*  991493 */ // Label 15671: @991493
     /*  991493 */ GIM_Reject,
     /*  991494 */ // Label 15650: @991494
     /*  991494 */ GIM_Try, /*On fail goto*//*Label 15672*/ GIMT_Encode4(991517), // Rule ID 27930 //
     /*  991499 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  991503 */   // MIs[0] Operand 1
     /*  991503 */   // No operand predicates
     /*  991503 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45033),
     /*  991507 */   // (imm:{ *:[i32] })<<P:Predicate_anonymous_45033>>:$imm  =>  (V_MOV_B32_e32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991507 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  991510 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991512 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991515 */   GIR_RootConstrainSelectedInstOperands,
     /*  991516 */   // GIR_Coverage, 27930,
     /*  991516 */   GIR_EraseRootFromParent_Done,
     /*  991517 */ // Label 15672: @991517
     /*  991517 */ GIM_Try, /*On fail goto*//*Label 15673*/ GIMT_Encode4(991536), // Rule ID 27931 //
     /*  991522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991526 */   // MIs[0] Operand 1
     /*  991526 */   // No operand predicates
     /*  991526 */   // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991526 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991529 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991531 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991534 */   GIR_RootConstrainSelectedInstOperands,
     /*  991535 */   // GIR_Coverage, 27931,
     /*  991535 */   GIR_EraseRootFromParent_Done,
     /*  991536 */ // Label 15673: @991536
     /*  991536 */ GIM_Reject,
     /*  991537 */ // Label 15651: @991537
     /*  991537 */ GIM_Try, /*On fail goto*//*Label 15674*/ GIMT_Encode4(991560), // Rule ID 27932 //
     /*  991542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  991546 */   // MIs[0] Operand 1
     /*  991546 */   // No operand predicates
     /*  991546 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45036),
     /*  991550 */   // (imm:{ *:[i32] })<<P:Predicate_anonymous_45036>>:$imm  =>  (V_MOV_B32_e32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  991553 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991555 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991558 */   GIR_RootConstrainSelectedInstOperands,
     /*  991559 */   // GIR_Coverage, 27932,
     /*  991559 */   GIR_EraseRootFromParent_Done,
     /*  991560 */ // Label 15674: @991560
     /*  991560 */ GIM_Try, /*On fail goto*//*Label 15675*/ GIMT_Encode4(991579), // Rule ID 27933 //
     /*  991565 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991569 */   // MIs[0] Operand 1
     /*  991569 */   // No operand predicates
     /*  991569 */   // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991569 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991572 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991574 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991577 */   GIR_RootConstrainSelectedInstOperands,
     /*  991578 */   // GIR_Coverage, 27933,
     /*  991578 */   GIR_EraseRootFromParent_Done,
     /*  991579 */ // Label 15675: @991579
     /*  991579 */ GIM_Reject,
     /*  991580 */ // Label 15652: @991580
     /*  991580 */ GIM_Try, /*On fail goto*//*Label 15676*/ GIMT_Encode4(991606), // Rule ID 27983 //
     /*  991585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  991588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991592 */   // MIs[0] Operand 1
     /*  991592 */   // No operand predicates
     /*  991592 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45084),
     /*  991596 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45084>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991599 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991601 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991604 */   GIR_RootConstrainSelectedInstOperands,
     /*  991605 */   // GIR_Coverage, 27983,
     /*  991605 */   GIR_EraseRootFromParent_Done,
     /*  991606 */ // Label 15676: @991606
     /*  991606 */ GIM_Try, /*On fail goto*//*Label 15677*/ GIMT_Encode4(991632), // Rule ID 27984 //
     /*  991611 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  991614 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991618 */   // MIs[0] Operand 1
     /*  991618 */   // No operand predicates
     /*  991618 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45084),
     /*  991622 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45084>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991622 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991625 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991627 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991630 */   GIR_RootConstrainSelectedInstOperands,
     /*  991631 */   // GIR_Coverage, 27984,
     /*  991631 */   GIR_EraseRootFromParent_Done,
     /*  991632 */ // Label 15677: @991632
     /*  991632 */ GIM_Try, /*On fail goto*//*Label 15678*/ GIMT_Encode4(991658), // Rule ID 27985 //
     /*  991637 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  991640 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991644 */   // MIs[0] Operand 1
     /*  991644 */   // No operand predicates
     /*  991644 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45084),
     /*  991648 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45084>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991648 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991651 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991653 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991656 */   GIR_RootConstrainSelectedInstOperands,
     /*  991657 */   // GIR_Coverage, 27985,
     /*  991657 */   GIR_EraseRootFromParent_Done,
     /*  991658 */ // Label 15678: @991658
     /*  991658 */ GIM_Try, /*On fail goto*//*Label 15679*/ GIMT_Encode4(991684), // Rule ID 27986 //
     /*  991663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  991666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991670 */   // MIs[0] Operand 1
     /*  991670 */   // No operand predicates
     /*  991670 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45084),
     /*  991674 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45084>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991674 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991677 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991679 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991682 */   GIR_RootConstrainSelectedInstOperands,
     /*  991683 */   // GIR_Coverage, 27986,
     /*  991683 */   GIR_EraseRootFromParent_Done,
     /*  991684 */ // Label 15679: @991684
     /*  991684 */ GIM_Try, /*On fail goto*//*Label 15680*/ GIMT_Encode4(991710), // Rule ID 27987 //
     /*  991689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  991692 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991696 */   // MIs[0] Operand 1
     /*  991696 */   // No operand predicates
     /*  991696 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45084),
     /*  991700 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45084>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  991703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991705 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991708 */   GIR_RootConstrainSelectedInstOperands,
     /*  991709 */   // GIR_Coverage, 27987,
     /*  991709 */   GIR_EraseRootFromParent_Done,
     /*  991710 */ // Label 15680: @991710
     /*  991710 */ GIM_Try, /*On fail goto*//*Label 15681*/ GIMT_Encode4(991729), // Rule ID 27989 //
     /*  991715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  991719 */   // MIs[0] Operand 1
     /*  991719 */   // No operand predicates
     /*  991719 */   // (imm:{ *:[i64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  991722 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991724 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991727 */   GIR_RootConstrainSelectedInstOperands,
     /*  991728 */   // GIR_Coverage, 27989,
     /*  991728 */   GIR_EraseRootFromParent_Done,
     /*  991729 */ // Label 15681: @991729
     /*  991729 */ GIM_Reject,
     /*  991730 */ // Label 15653: @991730
     /*  991730 */ GIM_Try, /*On fail goto*//*Label 15682*/ GIMT_Encode4(991753), // Rule ID 27934 //
     /*  991735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  991739 */   // MIs[0] Operand 1
     /*  991739 */   // No operand predicates
     /*  991739 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45039),
     /*  991743 */   // (imm:{ *:[i32] })<<P:Predicate_anonymous_45039>>:$imm  =>  (V_MOV_B32_e32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  991746 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991748 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991751 */   GIR_RootConstrainSelectedInstOperands,
     /*  991752 */   // GIR_Coverage, 27934,
     /*  991752 */   GIR_EraseRootFromParent_Done,
     /*  991753 */ // Label 15682: @991753
     /*  991753 */ GIM_Try, /*On fail goto*//*Label 15683*/ GIMT_Encode4(991772), // Rule ID 27935 //
     /*  991758 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991762 */   // MIs[0] Operand 1
     /*  991762 */   // No operand predicates
     /*  991762 */   // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991762 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991765 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991767 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991770 */   GIR_RootConstrainSelectedInstOperands,
     /*  991771 */   // GIR_Coverage, 27935,
     /*  991771 */   GIR_EraseRootFromParent_Done,
     /*  991772 */ // Label 15683: @991772
     /*  991772 */ GIM_Reject,
     /*  991773 */ // Label 15654: @991773
     /*  991773 */ GIM_Try, /*On fail goto*//*Label 15684*/ GIMT_Encode4(991796), // Rule ID 27936 //
     /*  991778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  991782 */   // MIs[0] Operand 1
     /*  991782 */   // No operand predicates
     /*  991782 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45042),
     /*  991786 */   // (imm:{ *:[i32] })<<P:Predicate_anonymous_45042>>:$imm  =>  (V_MOV_B32_e32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  991789 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991791 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991794 */   GIR_RootConstrainSelectedInstOperands,
     /*  991795 */   // GIR_Coverage, 27936,
     /*  991795 */   GIR_EraseRootFromParent_Done,
     /*  991796 */ // Label 15684: @991796
     /*  991796 */ GIM_Try, /*On fail goto*//*Label 15685*/ GIMT_Encode4(991815), // Rule ID 27937 //
     /*  991801 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991805 */   // MIs[0] Operand 1
     /*  991805 */   // No operand predicates
     /*  991805 */   // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991808 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991810 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991813 */   GIR_RootConstrainSelectedInstOperands,
     /*  991814 */   // GIR_Coverage, 27937,
     /*  991814 */   GIR_EraseRootFromParent_Done,
     /*  991815 */ // Label 15685: @991815
     /*  991815 */ GIM_Reject,
     /*  991816 */ // Label 15655: @991816
     /*  991816 */ GIM_Try, /*On fail goto*//*Label 15686*/ GIMT_Encode4(991838), // Rule ID 27997 //
     /*  991821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
     /*  991824 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  991828 */   // MIs[0] Operand 1
     /*  991828 */   // No operand predicates
     /*  991828 */   // (imm:{ *:[i1] }):$imm  =>  (S_MOV_B64:{ *:[i1] } (imm:{ *:[i1] }):$imm)
     /*  991828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
     /*  991831 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991833 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991836 */   GIR_RootConstrainSelectedInstOperands,
     /*  991837 */   // GIR_Coverage, 27997,
     /*  991837 */   GIR_EraseRootFromParent_Done,
     /*  991838 */ // Label 15686: @991838
     /*  991838 */ GIM_Try, /*On fail goto*//*Label 15687*/ GIMT_Encode4(991860), // Rule ID 27998 //
     /*  991843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
     /*  991846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991850 */   // MIs[0] Operand 1
     /*  991850 */   // No operand predicates
     /*  991850 */   // (imm:{ *:[i1] }):$imm  =>  (S_MOV_B32:{ *:[i1] } (imm:{ *:[i1] }):$imm)
     /*  991850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991855 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991858 */   GIR_RootConstrainSelectedInstOperands,
     /*  991859 */   // GIR_Coverage, 27998,
     /*  991859 */   GIR_EraseRootFromParent_Done,
     /*  991860 */ // Label 15687: @991860
     /*  991860 */ GIM_Reject,
     /*  991861 */ // Label 15656: @991861
     /*  991861 */ GIM_Try, /*On fail goto*//*Label 15688*/ GIMT_Encode4(991887), // Rule ID 27942 //
     /*  991866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*  991869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  991873 */   // MIs[0] Operand 1
     /*  991873 */   // No operand predicates
     /*  991873 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45052),
     /*  991877 */   // (imm:{ *:[i16] })<<P:Predicate_anonymous_45052>>:$imm  =>  (V_MOV_B32_e32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
     /*  991877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  991880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991882 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991885 */   GIR_RootConstrainSelectedInstOperands,
     /*  991886 */   // GIR_Coverage, 27942,
     /*  991886 */   GIR_EraseRootFromParent_Done,
     /*  991887 */ // Label 15688: @991887
     /*  991887 */ GIM_Try, /*On fail goto*//*Label 15689*/ GIMT_Encode4(991919), // Rule ID 27944 //
     /*  991892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  991895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  991899 */   // MIs[0] Operand 1
     /*  991899 */   // No operand predicates
     /*  991899 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45052),
     /*  991903 */   // (imm:{ *:[i16] })<<P:Predicate_anonymous_45052>>:$imm  =>  (V_MOV_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, (imm:{ *:[i16] }):$imm, 0:{ *:[i32] })
     /*  991903 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B16_t16_e64),
     /*  991906 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991908 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  991911 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991914 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  991917 */   GIR_RootConstrainSelectedInstOperands,
     /*  991918 */   // GIR_Coverage, 27944,
     /*  991918 */   GIR_EraseRootFromParent_Done,
     /*  991919 */ // Label 15689: @991919
     /*  991919 */ GIM_Try, /*On fail goto*//*Label 15690*/ GIMT_Encode4(991938), // Rule ID 4798 //
     /*  991924 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991928 */   // MIs[0] Operand 1
     /*  991928 */   // No operand predicates
     /*  991928 */   // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
     /*  991928 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991931 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991933 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991936 */   GIR_RootConstrainSelectedInstOperands,
     /*  991937 */   // GIR_Coverage, 4798,
     /*  991937 */   GIR_EraseRootFromParent_Done,
     /*  991938 */ // Label 15690: @991938
     /*  991938 */ GIM_Reject,
     /*  991939 */ // Label 15657: @991939
     /*  991939 */ GIM_Try, /*On fail goto*//*Label 15691*/ GIMT_Encode4(991962), // Rule ID 27928 //
     /*  991944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  991948 */   // MIs[0] Operand 1
     /*  991948 */   // No operand predicates
     /*  991948 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45032),
     /*  991952 */   // (imm:{ *:[i32] })<<P:Predicate_anonymous_45032>>:$imm  =>  (V_MOV_B32_e32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  991955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  991957 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991960 */   GIR_RootConstrainSelectedInstOperands,
     /*  991961 */   // GIR_Coverage, 27928,
     /*  991961 */   GIR_EraseRootFromParent_Done,
     /*  991962 */ // Label 15691: @991962
     /*  991962 */ GIM_Try, /*On fail goto*//*Label 15692*/ GIMT_Encode4(991981), // Rule ID 27929 //
     /*  991967 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  991971 */   // MIs[0] Operand 1
     /*  991971 */   // No operand predicates
     /*  991971 */   // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
     /*  991971 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  991974 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  991976 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  991979 */   GIR_RootConstrainSelectedInstOperands,
     /*  991980 */   // GIR_Coverage, 27929,
     /*  991980 */   GIR_EraseRootFromParent_Done,
     /*  991981 */ // Label 15692: @991981
     /*  991981 */ GIM_Reject,
     /*  991982 */ // Label 15658: @991982
     /*  991982 */ GIM_Try, /*On fail goto*//*Label 15693*/ GIMT_Encode4(992008), // Rule ID 27946 //
     /*  991987 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  991990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  991994 */   // MIs[0] Operand 1
     /*  991994 */   // No operand predicates
     /*  991994 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  991998 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  991998 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992001 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992003 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992006 */   GIR_RootConstrainSelectedInstOperands,
     /*  992007 */   // GIR_Coverage, 27946,
     /*  992007 */   GIR_EraseRootFromParent_Done,
     /*  992008 */ // Label 15693: @992008
     /*  992008 */ GIM_Try, /*On fail goto*//*Label 15694*/ GIMT_Encode4(992034), // Rule ID 27947 //
     /*  992013 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  992016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992020 */   // MIs[0] Operand 1
     /*  992020 */   // No operand predicates
     /*  992020 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992024 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992029 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992032 */   GIR_RootConstrainSelectedInstOperands,
     /*  992033 */   // GIR_Coverage, 27947,
     /*  992033 */   GIR_EraseRootFromParent_Done,
     /*  992034 */ // Label 15694: @992034
     /*  992034 */ GIM_Try, /*On fail goto*//*Label 15695*/ GIMT_Encode4(992060), // Rule ID 27948 //
     /*  992039 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  992042 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992046 */   // MIs[0] Operand 1
     /*  992046 */   // No operand predicates
     /*  992046 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992050 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992050 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992053 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992055 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992058 */   GIR_RootConstrainSelectedInstOperands,
     /*  992059 */   // GIR_Coverage, 27948,
     /*  992059 */   GIR_EraseRootFromParent_Done,
     /*  992060 */ // Label 15695: @992060
     /*  992060 */ GIM_Try, /*On fail goto*//*Label 15696*/ GIMT_Encode4(992086), // Rule ID 27949 //
     /*  992065 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  992068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992072 */   // MIs[0] Operand 1
     /*  992072 */   // No operand predicates
     /*  992072 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992076 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992076 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992079 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992081 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992084 */   GIR_RootConstrainSelectedInstOperands,
     /*  992085 */   // GIR_Coverage, 27949,
     /*  992085 */   GIR_EraseRootFromParent_Done,
     /*  992086 */ // Label 15696: @992086
     /*  992086 */ GIM_Try, /*On fail goto*//*Label 15697*/ GIMT_Encode4(992112), // Rule ID 27950 //
     /*  992091 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  992094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992098 */   // MIs[0] Operand 1
     /*  992098 */   // No operand predicates
     /*  992098 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992102 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992105 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992107 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992110 */   GIR_RootConstrainSelectedInstOperands,
     /*  992111 */   // GIR_Coverage, 27950,
     /*  992111 */   GIR_EraseRootFromParent_Done,
     /*  992112 */ // Label 15697: @992112
     /*  992112 */ GIM_Try, /*On fail goto*//*Label 15698*/ GIMT_Encode4(992135), // Rule ID 27967 //
     /*  992117 */   GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_InlineImm64),
     /*  992121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992125 */   // MIs[0] Operand 1
     /*  992125 */   // No operand predicates
     /*  992125 */   // (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm  =>  (S_MOV_B64:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm)
     /*  992125 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
     /*  992128 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992130 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992133 */   GIR_RootConstrainSelectedInstOperands,
     /*  992134 */   // GIR_Coverage, 27967,
     /*  992134 */   GIR_EraseRootFromParent_Done,
     /*  992135 */ // Label 15698: @992135
     /*  992135 */ GIM_Try, /*On fail goto*//*Label 15699*/ GIMT_Encode4(992158), // Rule ID 27974 //
     /*  992140 */   GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_InlineImm64),
     /*  992144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992148 */   // MIs[0] Operand 1
     /*  992148 */   // No operand predicates
     /*  992148 */   // (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm  =>  (S_MOV_B64:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm)
     /*  992148 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
     /*  992151 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992153 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992156 */   GIR_RootConstrainSelectedInstOperands,
     /*  992157 */   // GIR_Coverage, 27974,
     /*  992157 */   GIR_EraseRootFromParent_Done,
     /*  992158 */ // Label 15699: @992158
     /*  992158 */ GIM_Try, /*On fail goto*//*Label 15700*/ GIMT_Encode4(992181), // Rule ID 27981 //
     /*  992163 */   GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_InlineImm64),
     /*  992167 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992171 */   // MIs[0] Operand 1
     /*  992171 */   // No operand predicates
     /*  992171 */   // (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm  =>  (S_MOV_B64:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm)
     /*  992171 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
     /*  992174 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992176 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992179 */   GIR_RootConstrainSelectedInstOperands,
     /*  992180 */   // GIR_Coverage, 27981,
     /*  992180 */   GIR_EraseRootFromParent_Done,
     /*  992181 */ // Label 15700: @992181
     /*  992181 */ GIM_Try, /*On fail goto*//*Label 15701*/ GIMT_Encode4(992204), // Rule ID 27988 //
     /*  992186 */   GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_InlineImm64),
     /*  992190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992194 */   // MIs[0] Operand 1
     /*  992194 */   // No operand predicates
     /*  992194 */   // (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm  =>  (S_MOV_B64:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm)
     /*  992194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
     /*  992197 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992199 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992202 */   GIR_RootConstrainSelectedInstOperands,
     /*  992203 */   // GIR_Coverage, 27988,
     /*  992203 */   GIR_EraseRootFromParent_Done,
     /*  992204 */ // Label 15701: @992204
     /*  992204 */ GIM_Try, /*On fail goto*//*Label 15702*/ GIMT_Encode4(992230), // Rule ID 27962 //
     /*  992209 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  992212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992216 */   // MIs[0] Operand 1
     /*  992216 */   // No operand predicates
     /*  992216 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992220 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992223 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992225 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992228 */   GIR_RootConstrainSelectedInstOperands,
     /*  992229 */   // GIR_Coverage, 27962,
     /*  992229 */   GIR_EraseRootFromParent_Done,
     /*  992230 */ // Label 15702: @992230
     /*  992230 */ GIM_Try, /*On fail goto*//*Label 15703*/ GIMT_Encode4(992256), // Rule ID 27963 //
     /*  992235 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  992238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992242 */   // MIs[0] Operand 1
     /*  992242 */   // No operand predicates
     /*  992242 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992246 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992246 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992249 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992251 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992254 */   GIR_RootConstrainSelectedInstOperands,
     /*  992255 */   // GIR_Coverage, 27963,
     /*  992255 */   GIR_EraseRootFromParent_Done,
     /*  992256 */ // Label 15703: @992256
     /*  992256 */ GIM_Try, /*On fail goto*//*Label 15704*/ GIMT_Encode4(992282), // Rule ID 27964 //
     /*  992261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  992264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992268 */   // MIs[0] Operand 1
     /*  992268 */   // No operand predicates
     /*  992268 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992272 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992272 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992275 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992277 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992280 */   GIR_RootConstrainSelectedInstOperands,
     /*  992281 */   // GIR_Coverage, 27964,
     /*  992281 */   GIR_EraseRootFromParent_Done,
     /*  992282 */ // Label 15704: @992282
     /*  992282 */ GIM_Try, /*On fail goto*//*Label 15705*/ GIMT_Encode4(992308), // Rule ID 27965 //
     /*  992287 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  992290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992294 */   // MIs[0] Operand 1
     /*  992294 */   // No operand predicates
     /*  992294 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992298 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992303 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992306 */   GIR_RootConstrainSelectedInstOperands,
     /*  992307 */   // GIR_Coverage, 27965,
     /*  992307 */   GIR_EraseRootFromParent_Done,
     /*  992308 */ // Label 15705: @992308
     /*  992308 */ GIM_Try, /*On fail goto*//*Label 15706*/ GIMT_Encode4(992334), // Rule ID 27966 //
     /*  992313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  992316 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992320 */   // MIs[0] Operand 1
     /*  992320 */   // No operand predicates
     /*  992320 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45061),
     /*  992324 */   // (imm:{ *:[i64] })<<P:Predicate_anonymous_45061>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992327 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992329 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992332 */   GIR_RootConstrainSelectedInstOperands,
     /*  992333 */   // GIR_Coverage, 27966,
     /*  992333 */   GIR_EraseRootFromParent_Done,
     /*  992334 */ // Label 15706: @992334
     /*  992334 */ GIM_Try, /*On fail goto*//*Label 15707*/ GIMT_Encode4(992353), // Rule ID 27956 //
     /*  992339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992343 */   // MIs[0] Operand 1
     /*  992343 */   // No operand predicates
     /*  992343 */   // (imm:{ *:[i64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  992346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992348 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992351 */   GIR_RootConstrainSelectedInstOperands,
     /*  992352 */   // GIR_Coverage, 27956,
     /*  992352 */   GIR_EraseRootFromParent_Done,
     /*  992353 */ // Label 15707: @992353
     /*  992353 */ GIM_Try, /*On fail goto*//*Label 15708*/ GIMT_Encode4(992372), // Rule ID 27968 //
     /*  992358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992362 */   // MIs[0] Operand 1
     /*  992362 */   // No operand predicates
     /*  992362 */   // (imm:{ *:[i64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
     /*  992362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  992365 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992367 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /*  992370 */   GIR_RootConstrainSelectedInstOperands,
     /*  992371 */   // GIR_Coverage, 27968,
     /*  992371 */   GIR_EraseRootFromParent_Done,
     /*  992372 */ // Label 15708: @992372
     /*  992372 */ GIM_Reject,
     /*  992373 */ // Label 15659: @992373
     /*  992373 */ GIM_Reject,
     /*  992374 */ // Label 45: @992374
     /*  992374 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 15712*/ GIMT_Encode4(992863),
     /*  992385 */ /*GILLT_s16*//*Label 15709*/ GIMT_Encode4(992397),
     /*  992389 */ /*GILLT_s32*//*Label 15710*/ GIMT_Encode4(992447),
     /*  992393 */ /*GILLT_s64*//*Label 15711*/ GIMT_Encode4(992515),
     /*  992397 */ // Label 15709: @992397
     /*  992397 */ GIM_Try, /*On fail goto*//*Label 15713*/ GIMT_Encode4(992425), // Rule ID 27943 //
     /*  992402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*  992405 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  992409 */   // MIs[0] Operand 1
     /*  992409 */   // No operand predicates
     /*  992409 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45054),
     /*  992413 */   // (fpimm:{ *:[f16] })<<P:Predicate_anonymous_45054>>:$imm  =>  (V_MOV_B32_e32:{ *:[f16] } (bitcast_fpimm_to_i32:{ *:[f16] } ?:{ *:[f16] }:$imm))
     /*  992413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  992416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992418 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm32), // imm
     /*  992423 */   GIR_RootConstrainSelectedInstOperands,
     /*  992424 */   // GIR_Coverage, 27943,
     /*  992424 */   GIR_EraseRootFromParent_Done,
     /*  992425 */ // Label 15713: @992425
     /*  992425 */ GIM_Try, /*On fail goto*//*Label 15714*/ GIMT_Encode4(992446), // Rule ID 27959 //
     /*  992430 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  992434 */   // MIs[0] Operand 1
     /*  992434 */   // No operand predicates
     /*  992434 */   // (fpimm:{ *:[f16] }):$imm  =>  (S_MOV_B32:{ *:[f16] } (bitcast_fpimm_to_i32:{ *:[i32] } ?:{ *:[f16] }:$imm))
     /*  992434 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  992437 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992439 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm32), // imm
     /*  992444 */   GIR_RootConstrainSelectedInstOperands,
     /*  992445 */   // GIR_Coverage, 27959,
     /*  992445 */   GIR_EraseRootFromParent_Done,
     /*  992446 */ // Label 15714: @992446
     /*  992446 */ GIM_Reject,
     /*  992447 */ // Label 15710: @992447
     /*  992447 */ GIM_Try, /*On fail goto*//*Label 15715*/ GIMT_Encode4(992472), // Rule ID 27960 //
     /*  992452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  992456 */   // MIs[0] Operand 1
     /*  992456 */   // No operand predicates
     /*  992456 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45071),
     /*  992460 */   // (fpimm:{ *:[f32] })<<P:Predicate_anonymous_45071>>:$imm  =>  (V_MOV_B32_e32:{ *:[f32] } (bitcast_fpimm_to_i32:{ *:[f32] } ?:{ *:[f32] }:$imm))
     /*  992460 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  992463 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992465 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm32), // imm
     /*  992470 */   GIR_RootConstrainSelectedInstOperands,
     /*  992471 */   // GIR_Coverage, 27960,
     /*  992471 */   GIR_EraseRootFromParent_Done,
     /*  992472 */ // Label 15715: @992472
     /*  992472 */ GIM_Try, /*On fail goto*//*Label 15716*/ GIMT_Encode4(992493), // Rule ID 27958 //
     /*  992477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  992481 */   // MIs[0] Operand 1
     /*  992481 */   // No operand predicates
     /*  992481 */   // (fpimm:{ *:[f32] }):$imm  =>  (S_MOV_B32:{ *:[f32] } (bitcast_fpimm_to_i32:{ *:[f32] } ?:{ *:[f32] }:$imm))
     /*  992481 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  992484 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992486 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm32), // imm
     /*  992491 */   GIR_RootConstrainSelectedInstOperands,
     /*  992492 */   // GIR_Coverage, 27958,
     /*  992492 */   GIR_EraseRootFromParent_Done,
     /*  992493 */ // Label 15716: @992493
     /*  992493 */ GIM_Try, /*On fail goto*//*Label 15717*/ GIMT_Encode4(992514), // Rule ID 27961 //
     /*  992498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  992502 */   // MIs[0] Operand 1
     /*  992502 */   // No operand predicates
     /*  992502 */   // (fpimm:{ *:[f32] }):$imm  =>  (S_MOV_B32:{ *:[f32] } (bitcast_fpimm_to_i32:{ *:[f32] } ?:{ *:[f32] }:$imm))
     /*  992502 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  992505 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992507 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm32), // imm
     /*  992512 */   GIR_RootConstrainSelectedInstOperands,
     /*  992513 */   // GIR_Coverage, 27961,
     /*  992513 */   GIR_EraseRootFromParent_Done,
     /*  992514 */ // Label 15717: @992514
     /*  992514 */ GIM_Reject,
     /*  992515 */ // Label 15711: @992515
     /*  992515 */ GIM_Try, /*On fail goto*//*Label 15718*/ GIMT_Encode4(992543), // Rule ID 27951 //
     /*  992520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  992523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992527 */   // MIs[0] Operand 1
     /*  992527 */   // No operand predicates
     /*  992527 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992531 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992531 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992534 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992536 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992541 */   GIR_RootConstrainSelectedInstOperands,
     /*  992542 */   // GIR_Coverage, 27951,
     /*  992542 */   GIR_EraseRootFromParent_Done,
     /*  992543 */ // Label 15718: @992543
     /*  992543 */ GIM_Try, /*On fail goto*//*Label 15719*/ GIMT_Encode4(992571), // Rule ID 27952 //
     /*  992548 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  992551 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992555 */   // MIs[0] Operand 1
     /*  992555 */   // No operand predicates
     /*  992555 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992559 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992559 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992562 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992564 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992569 */   GIR_RootConstrainSelectedInstOperands,
     /*  992570 */   // GIR_Coverage, 27952,
     /*  992570 */   GIR_EraseRootFromParent_Done,
     /*  992571 */ // Label 15719: @992571
     /*  992571 */ GIM_Try, /*On fail goto*//*Label 15720*/ GIMT_Encode4(992599), // Rule ID 27953 //
     /*  992576 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  992579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992583 */   // MIs[0] Operand 1
     /*  992583 */   // No operand predicates
     /*  992583 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992587 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992592 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992597 */   GIR_RootConstrainSelectedInstOperands,
     /*  992598 */   // GIR_Coverage, 27953,
     /*  992598 */   GIR_EraseRootFromParent_Done,
     /*  992599 */ // Label 15720: @992599
     /*  992599 */ GIM_Try, /*On fail goto*//*Label 15721*/ GIMT_Encode4(992627), // Rule ID 27954 //
     /*  992604 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  992607 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992611 */   // MIs[0] Operand 1
     /*  992611 */   // No operand predicates
     /*  992611 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992615 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992615 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992618 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992620 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992625 */   GIR_RootConstrainSelectedInstOperands,
     /*  992626 */   // GIR_Coverage, 27954,
     /*  992626 */   GIR_EraseRootFromParent_Done,
     /*  992627 */ // Label 15721: @992627
     /*  992627 */ GIM_Try, /*On fail goto*//*Label 15722*/ GIMT_Encode4(992655), // Rule ID 27955 //
     /*  992632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  992635 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992639 */   // MIs[0] Operand 1
     /*  992639 */   // No operand predicates
     /*  992639 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992643 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992646 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992648 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992653 */   GIR_RootConstrainSelectedInstOperands,
     /*  992654 */   // GIR_Coverage, 27955,
     /*  992654 */   GIR_EraseRootFromParent_Done,
     /*  992655 */ // Label 15722: @992655
     /*  992655 */ GIM_Try, /*On fail goto*//*Label 15723*/ GIMT_Encode4(992680), // Rule ID 27995 //
     /*  992660 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_InlineImmFP64),
     /*  992664 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992668 */   // MIs[0] Operand 1
     /*  992668 */   // No operand predicates
     /*  992668 */   // (fpimm:{ *:[f64] })<<P:Predicate_InlineImmFP64>>:$imm  =>  (S_MOV_B64:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[i64] } ?:{ *:[f64] }:$imm))
     /*  992668 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
     /*  992671 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992673 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992678 */   GIR_RootConstrainSelectedInstOperands,
     /*  992679 */   // GIR_Coverage, 27995,
     /*  992679 */   GIR_EraseRootFromParent_Done,
     /*  992680 */ // Label 15723: @992680
     /*  992680 */ GIM_Try, /*On fail goto*//*Label 15724*/ GIMT_Encode4(992708), // Rule ID 27990 //
     /*  992685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  992688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992692 */   // MIs[0] Operand 1
     /*  992692 */   // No operand predicates
     /*  992692 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992696 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992701 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992706 */   GIR_RootConstrainSelectedInstOperands,
     /*  992707 */   // GIR_Coverage, 27990,
     /*  992707 */   GIR_EraseRootFromParent_Done,
     /*  992708 */ // Label 15724: @992708
     /*  992708 */ GIM_Try, /*On fail goto*//*Label 15725*/ GIMT_Encode4(992736), // Rule ID 27991 //
     /*  992713 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  992716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992720 */   // MIs[0] Operand 1
     /*  992720 */   // No operand predicates
     /*  992720 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992724 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992727 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992729 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992734 */   GIR_RootConstrainSelectedInstOperands,
     /*  992735 */   // GIR_Coverage, 27991,
     /*  992735 */   GIR_EraseRootFromParent_Done,
     /*  992736 */ // Label 15725: @992736
     /*  992736 */ GIM_Try, /*On fail goto*//*Label 15726*/ GIMT_Encode4(992764), // Rule ID 27992 //
     /*  992741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  992744 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992748 */   // MIs[0] Operand 1
     /*  992748 */   // No operand predicates
     /*  992748 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992752 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992752 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992755 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992757 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992762 */   GIR_RootConstrainSelectedInstOperands,
     /*  992763 */   // GIR_Coverage, 27992,
     /*  992763 */   GIR_EraseRootFromParent_Done,
     /*  992764 */ // Label 15726: @992764
     /*  992764 */ GIM_Try, /*On fail goto*//*Label 15727*/ GIMT_Encode4(992792), // Rule ID 27993 //
     /*  992769 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  992772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992776 */   // MIs[0] Operand 1
     /*  992776 */   // No operand predicates
     /*  992776 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992780 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992780 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992783 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992785 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992790 */   GIR_RootConstrainSelectedInstOperands,
     /*  992791 */   // GIR_Coverage, 27993,
     /*  992791 */   GIR_EraseRootFromParent_Done,
     /*  992792 */ // Label 15727: @992792
     /*  992792 */ GIM_Try, /*On fail goto*//*Label 15728*/ GIMT_Encode4(992820), // Rule ID 27994 //
     /*  992797 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  992800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  992804 */   // MIs[0] Operand 1
     /*  992804 */   // No operand predicates
     /*  992804 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45063),
     /*  992808 */   // (fpimm:{ *:[f64] })<<P:Predicate_anonymous_45063>>:$imm  =>  (V_MOV_B64_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[f64] } ?:{ *:[f64] }:$imm))
     /*  992808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
     /*  992811 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992813 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992818 */   GIR_RootConstrainSelectedInstOperands,
     /*  992819 */   // GIR_Coverage, 27994,
     /*  992819 */   GIR_EraseRootFromParent_Done,
     /*  992820 */ // Label 15728: @992820
     /*  992820 */ GIM_Try, /*On fail goto*//*Label 15729*/ GIMT_Encode4(992841), // Rule ID 27957 //
     /*  992825 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992829 */   // MIs[0] Operand 1
     /*  992829 */   // No operand predicates
     /*  992829 */   // (fpimm:{ *:[f64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[i64] } (fpimm:{ *:[f64] }):$imm))
     /*  992829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  992832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992834 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992839 */   GIR_RootConstrainSelectedInstOperands,
     /*  992840 */   // GIR_Coverage, 27957,
     /*  992840 */   GIR_EraseRootFromParent_Done,
     /*  992841 */ // Label 15729: @992841
     /*  992841 */ GIM_Try, /*On fail goto*//*Label 15730*/ GIMT_Encode4(992862), // Rule ID 27996 //
     /*  992846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  992850 */   // MIs[0] Operand 1
     /*  992850 */   // No operand predicates
     /*  992850 */   // (fpimm:{ *:[f64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[f64] } (bitcast_fpimm_to_i64:{ *:[i64] } (fpimm:{ *:[f64] }):$imm))
     /*  992850 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
     /*  992853 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  992855 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastFPImm64), // imm
     /*  992860 */   GIR_RootConstrainSelectedInstOperands,
     /*  992861 */   // GIR_Coverage, 27996,
     /*  992861 */   GIR_EraseRootFromParent_Done,
     /*  992862 */ // Label 15730: @992862
     /*  992862 */ GIM_Reject,
     /*  992863 */ // Label 15712: @992863
     /*  992863 */ GIM_Reject,
     /*  992864 */ // Label 46: @992864
     /*  992864 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 15734*/ GIMT_Encode4(994743),
     /*  992875 */ /*GILLT_s16*//*Label 15731*/ GIMT_Encode4(992887),
     /*  992879 */ /*GILLT_s32*//*Label 15732*/ GIMT_Encode4(993046),
     /*  992883 */ /*GILLT_s64*//*Label 15733*/ GIMT_Encode4(993373),
     /*  992887 */ // Label 15731: @992887
     /*  992887 */ GIM_Try, /*On fail goto*//*Label 15735*/ GIMT_Encode4(993045),
     /*  992892 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  992895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  992899 */   GIM_Try, /*On fail goto*//*Label 15736*/ GIMT_Encode4(992928), // Rule ID 7204 //
     /*  992904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  992907 */     // (sext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  992907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  992910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992912 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992915 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  992924 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  992926 */     GIR_RootConstrainSelectedInstOperands,
     /*  992927 */     // GIR_Coverage, 7204,
     /*  992927 */     GIR_EraseRootFromParent_Done,
     /*  992928 */   // Label 15736: @992928
     /*  992928 */   GIM_Try, /*On fail goto*//*Label 15737*/ GIMT_Encode4(992957), // Rule ID 7205 //
     /*  992933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  992936 */     // (sext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  992936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  992939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992950 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  992953 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  992955 */     GIR_RootConstrainSelectedInstOperands,
     /*  992956 */     // GIR_Coverage, 7205,
     /*  992956 */     GIR_EraseRootFromParent_Done,
     /*  992957 */   // Label 15737: @992957
     /*  992957 */   GIM_Try, /*On fail goto*//*Label 15738*/ GIMT_Encode4(992986), // Rule ID 7206 //
     /*  992962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  992965 */     // (sext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  992965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  992968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992973 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  992979 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  992982 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  992984 */     GIR_RootConstrainSelectedInstOperands,
     /*  992985 */     // GIR_Coverage, 7206,
     /*  992985 */     GIR_EraseRootFromParent_Done,
     /*  992986 */   // Label 15738: @992986
     /*  992986 */   GIM_Try, /*On fail goto*//*Label 15739*/ GIMT_Encode4(993015), // Rule ID 7207 //
     /*  992991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  992994 */     // (sext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  992994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  992997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  992999 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993002 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993005 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993008 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993011 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  993013 */     GIR_RootConstrainSelectedInstOperands,
     /*  993014 */     // GIR_Coverage, 7207,
     /*  993014 */     GIR_EraseRootFromParent_Done,
     /*  993015 */   // Label 15739: @993015
     /*  993015 */   GIM_Try, /*On fail goto*//*Label 15740*/ GIMT_Encode4(993044), // Rule ID 7208 //
     /*  993020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  993023 */     // (sext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  993023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  993026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993040 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  993042 */     GIR_RootConstrainSelectedInstOperands,
     /*  993043 */     // GIR_Coverage, 7208,
     /*  993043 */     GIR_EraseRootFromParent_Done,
     /*  993044 */   // Label 15740: @993044
     /*  993044 */   GIM_Reject,
     /*  993045 */ // Label 15735: @993045
     /*  993045 */ GIM_Reject,
     /*  993046 */ // Label 15732: @993046
     /*  993046 */ GIM_Try, /*On fail goto*//*Label 15741*/ GIMT_Encode4(993069), // Rule ID 4802 //
     /*  993051 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  993054 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  993058 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20813),
     /*  993062 */   // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_20813>>  =>  (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src)
     /*  993062 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16),
     /*  993067 */   GIR_RootConstrainSelectedInstOperands,
     /*  993068 */   // GIR_Coverage, 4802,
     /*  993068 */   GIR_Done,
     /*  993069 */ // Label 15741: @993069
     /*  993069 */ GIM_Try, /*On fail goto*//*Label 15742*/ GIMT_Encode4(993103), // Rule ID 7226 //
     /*  993074 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*  993077 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  993080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993084 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27871),
     /*  993088 */   // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_27871>>  =>  (V_BFE_I32_e64:{ *:[i32] } i16:{ *:[i16] }:$src, 0:{ *:[i32] }, 16:{ *:[i32] })
     /*  993088 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  993091 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993093 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  993095 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993098 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*  993101 */   GIR_RootConstrainSelectedInstOperands,
     /*  993102 */   // GIR_Coverage, 7226,
     /*  993102 */   GIR_EraseRootFromParent_Done,
     /*  993103 */ // Label 15742: @993103
     /*  993103 */ GIM_Try, /*On fail goto*//*Label 15743*/ GIMT_Encode4(993192), // Rule ID 7227 //
     /*  993108 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  993111 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  993114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993118 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27871),
     /*  993122 */   // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_27871>>  =>  (V_BFE_I32_e64:{ *:[i32] } (REG_SEQUENCE:{ *:[i16] } VGPR_32:{ *:[i32] }, VGPR_16:{ *:[i16] }:$src, lo16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), hi16:{ *:[i32] }), 0:{ *:[i32] }, 16:{ *:[i32] })
     /*  993122 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  993125 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  993129 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993134 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  993136 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  993139 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  993143 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993148 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993152 */   GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
     /*  993155 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  993158 */   GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
     /*  993161 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993166 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  993171 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  993176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  993179 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993181 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  993184 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993187 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /*  993190 */   GIR_RootConstrainSelectedInstOperands,
     /*  993191 */   // GIR_Coverage, 7227,
     /*  993191 */   GIR_EraseRootFromParent_Done,
     /*  993192 */ // Label 15743: @993192
     /*  993192 */ GIM_Try, /*On fail goto*//*Label 15744*/ GIMT_Encode4(993228), // Rule ID 28001 //
     /*  993197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  993200 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  993203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993207 */   // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  993207 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  993210 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993212 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993215 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993218 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993221 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993224 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  993226 */   GIR_RootConstrainSelectedInstOperands,
     /*  993227 */   // GIR_Coverage, 28001,
     /*  993227 */   GIR_EraseRootFromParent_Done,
     /*  993228 */ // Label 15744: @993228
     /*  993228 */ GIM_Try, /*On fail goto*//*Label 15745*/ GIMT_Encode4(993264), // Rule ID 28002 //
     /*  993233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  993236 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  993239 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993243 */   // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  993243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  993246 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993248 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993251 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993254 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993257 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993260 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  993262 */   GIR_RootConstrainSelectedInstOperands,
     /*  993263 */   // GIR_Coverage, 28002,
     /*  993263 */   GIR_EraseRootFromParent_Done,
     /*  993264 */ // Label 15745: @993264
     /*  993264 */ GIM_Try, /*On fail goto*//*Label 15746*/ GIMT_Encode4(993300), // Rule ID 28003 //
     /*  993269 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  993272 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  993275 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993279 */   // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  993279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  993282 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993287 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993290 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993293 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993296 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  993298 */   GIR_RootConstrainSelectedInstOperands,
     /*  993299 */   // GIR_Coverage, 28003,
     /*  993299 */   GIR_EraseRootFromParent_Done,
     /*  993300 */ // Label 15746: @993300
     /*  993300 */ GIM_Try, /*On fail goto*//*Label 15747*/ GIMT_Encode4(993336), // Rule ID 28004 //
     /*  993305 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  993308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  993311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993315 */   // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  993315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  993318 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993323 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993326 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993329 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993332 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  993334 */   GIR_RootConstrainSelectedInstOperands,
     /*  993335 */   // GIR_Coverage, 28004,
     /*  993335 */   GIR_EraseRootFromParent_Done,
     /*  993336 */ // Label 15747: @993336
     /*  993336 */ GIM_Try, /*On fail goto*//*Label 15748*/ GIMT_Encode4(993372), // Rule ID 28005 //
     /*  993341 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  993344 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  993347 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993351 */   // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  993351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  993354 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  993356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993359 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993362 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  993365 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /*  993368 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  993370 */   GIR_RootConstrainSelectedInstOperands,
     /*  993371 */   // GIR_Coverage, 28005,
     /*  993371 */   GIR_EraseRootFromParent_Done,
     /*  993372 */ // Label 15748: @993372
     /*  993372 */ GIM_Reject,
     /*  993373 */ // Label 15733: @993373
     /*  993373 */ GIM_Try, /*On fail goto*//*Label 15749*/ GIMT_Encode4(993518), // Rule ID 4812 //
     /*  993378 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  993381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  993385 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20813),
     /*  993389 */   // (sext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_20813>>  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_ASHR_I32:{ *:[i1] }:{ *:[i1] } (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src), (S_MOV_B32:{ *:[i1] } 31:{ *:[i32] })), SGPR_32:{ *:[i32] }), sub1:{ *:[i32] })
     /*  993389 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1,
     /*  993392 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993396 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993401 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/31,
     /*  993404 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  993406 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*  993409 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16),
     /*  993413 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993418 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993422 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*  993424 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1,
     /*  993427 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32),
     /*  993431 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993436 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /*  993439 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /*  993442 */   GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for AMDGPU::SCC*/0,
     /*  993445 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  993447 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  993450 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  993454 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993459 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  993462 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  993467 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  993470 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16),
     /*  993474 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993479 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993483 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  993485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  993488 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  993490 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  993493 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  993496 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  993499 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  993502 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  993507 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  993512 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  993517 */   // GIR_Coverage, 4812,
     /*  993517 */   GIR_EraseRootFromParent_Done,
     /*  993518 */ // Label 15749: @993518
     /*  993518 */ GIM_Try, /*On fail goto*//*Label 15750*/ GIMT_Encode4(993743), // Rule ID 7228 //
     /*  993523 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*  993526 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  993529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  993533 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27871),
     /*  993537 */   // (sext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_27871>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] })), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e32:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 31:{ *:[i32] }), (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] }))), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] })
     /*  993537 */   GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s16,
     /*  993540 */   GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993544 */   GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993549 */   GIR_AddImm8, /*InsnID*/9, /*Imm*/16,
     /*  993552 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /*  993554 */   GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*  993557 */   GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993561 */   GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993566 */   GIR_AddImm8, /*InsnID*/8, /*Imm*/0,
     /*  993569 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*  993571 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
     /*  993574 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  993578 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993583 */   GIR_Copy, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993587 */   GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*  993590 */   GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
     /*  993593 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  993595 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16,
     /*  993598 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993602 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993607 */   GIR_AddImm8, /*InsnID*/6, /*Imm*/31,
     /*  993610 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /*  993612 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*  993615 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e32),
     /*  993619 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993624 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /*  993627 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /*  993630 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  993632 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /*  993635 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  993639 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993644 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  993647 */   GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993652 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*  993655 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993659 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993664 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/16,
     /*  993667 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  993669 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  993672 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993676 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993681 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  993684 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  993686 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  993689 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  993693 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993698 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993702 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  993705 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /*  993708 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  993710 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  993713 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  993715 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  993718 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  993721 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*  993724 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  993727 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  993732 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993737 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993742 */   // GIR_Coverage, 7228,
     /*  993742 */   GIR_EraseRootFromParent_Done,
     /*  993743 */ // Label 15750: @993743
     /*  993743 */ GIM_Try, /*On fail goto*//*Label 15751*/ GIMT_Encode4(994021), // Rule ID 7229 //
     /*  993748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  993751 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  993754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  993758 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27871),
     /*  993762 */   // (sext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_27871>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFE_I32_e64:{ *:[i32] } (REG_SEQUENCE:{ *:[i16] } VGPR_32:{ *:[i32] }, VGPR_16:{ *:[i16] }:$src, lo16:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i16] }), hi16:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] })), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e32:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 31:{ *:[i32] }), (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] }))), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] })
     /*  993762 */   GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s16,
     /*  993765 */   GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993769 */   GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993774 */   GIR_AddImm8, /*InsnID*/11, /*Imm*/16,
     /*  993777 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /*  993779 */   GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s16,
     /*  993782 */   GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993786 */   GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993791 */   GIR_AddImm8, /*InsnID*/10, /*Imm*/0,
     /*  993794 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /*  993796 */   GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
     /*  993799 */   GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  993803 */   GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993808 */   GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993812 */   GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /*  993815 */   GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /*  993818 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /*  993820 */   GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
     /*  993823 */   GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993827 */   GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993832 */   GIR_AddImm8, /*InsnID*/8, /*Imm*/31,
     /*  993835 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /*  993837 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /*  993840 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e32),
     /*  993844 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993849 */   GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /*  993852 */   GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
     /*  993855 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  993857 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
     /*  993860 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  993864 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993869 */   GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  993872 */   GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993877 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /*  993880 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993884 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993889 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/16,
     /*  993892 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  993894 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /*  993897 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  993901 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993906 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /*  993909 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*  993911 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /*  993914 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  993918 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993923 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  993925 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  993928 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  993932 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993937 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  993941 */   GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/2,
     /*  993944 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  993947 */   GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/1,
     /*  993950 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  993955 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  993960 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  993965 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  993968 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
     /*  993972 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  993977 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  993980 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  993983 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
     /*  993986 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  993988 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  993991 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  993993 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  993996 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  993999 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/5,
     /*  994002 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994005 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994010 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994015 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994020 */   // GIR_Coverage, 7229,
     /*  994020 */   GIR_EraseRootFromParent_Done,
     /*  994021 */ // Label 15751: @994021
     /*  994021 */ GIM_Try, /*On fail goto*//*Label 15752*/ GIMT_Encode4(994113), // Rule ID 28135 //
     /*  994026 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  994029 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  994033 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20813),
     /*  994037 */   // (sext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_20813>>  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_ASHR_I32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i32] }:$src, 31:{ *:[i32] }), SReg_32_XM0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  994037 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  994040 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32),
     /*  994044 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994049 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994053 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /*  994056 */   GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for AMDGPU::SCC*/0,
     /*  994059 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994061 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  994064 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  994068 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994073 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  994076 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  994081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994086 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994088 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994091 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994094 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994097 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  994102 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  994107 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  994112 */   // GIR_Coverage, 28135,
     /*  994112 */   GIR_EraseRootFromParent_Done,
     /*  994113 */ // Label 15752: @994113
     /*  994113 */ GIM_Try, /*On fail goto*//*Label 15753*/ GIMT_Encode4(994202), // Rule ID 28136 //
     /*  994118 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  994121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994125 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27871),
     /*  994129 */   // (sext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_27871>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e64:{ *:[i16] } 31:{ *:[i32] }, ?:{ *:[i32] }:$src), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] })
     /*  994129 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  994132 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
     /*  994136 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994141 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /*  994144 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994148 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994150 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  994153 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  994157 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994162 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  994165 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994170 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994173 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994175 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994177 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994180 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994183 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994186 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994191 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994196 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994201 */   // GIR_Coverage, 28136,
     /*  994201 */   GIR_EraseRootFromParent_Done,
     /*  994202 */ // Label 15753: @994202
     /*  994202 */ GIM_Try, /*On fail goto*//*Label 15754*/ GIMT_Encode4(994310), // Rule ID 28137 //
     /*  994207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  994210 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  994213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994217 */   // (sext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] })
     /*  994217 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  994220 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994224 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994229 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994232 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994235 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994238 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/255,
     /*  994241 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994245 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994247 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  994250 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994254 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994259 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994262 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994265 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994268 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*  994271 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994275 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  994277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994280 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994282 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994285 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994288 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  994291 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994294 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994299 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994304 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994309 */   // GIR_Coverage, 28137,
     /*  994309 */   GIR_EraseRootFromParent_Done,
     /*  994310 */ // Label 15754: @994310
     /*  994310 */ GIM_Try, /*On fail goto*//*Label 15755*/ GIMT_Encode4(994418), // Rule ID 28138 //
     /*  994315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  994318 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  994321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994325 */   // (sext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] })
     /*  994325 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  994328 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994332 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994337 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994340 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994343 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994346 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/255,
     /*  994349 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994353 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994355 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  994358 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994362 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994367 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994370 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994373 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994376 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*  994379 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994383 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  994385 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994388 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994390 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994393 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994396 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  994399 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994402 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994407 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994412 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994417 */   // GIR_Coverage, 28138,
     /*  994417 */   GIR_EraseRootFromParent_Done,
     /*  994418 */ // Label 15755: @994418
     /*  994418 */ GIM_Try, /*On fail goto*//*Label 15756*/ GIMT_Encode4(994526), // Rule ID 28139 //
     /*  994423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  994426 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  994429 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994433 */   // (sext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] })
     /*  994433 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  994436 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994440 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994445 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994448 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994451 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994454 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/255,
     /*  994457 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994461 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994463 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  994466 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994470 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994475 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994478 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994481 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994484 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*  994487 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994491 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  994493 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994496 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994498 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994501 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994504 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  994507 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994510 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994515 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994520 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994525 */   // GIR_Coverage, 28139,
     /*  994525 */   GIR_EraseRootFromParent_Done,
     /*  994526 */ // Label 15756: @994526
     /*  994526 */ GIM_Try, /*On fail goto*//*Label 15757*/ GIMT_Encode4(994634), // Rule ID 28140 //
     /*  994531 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  994534 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  994537 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994541 */   // (sext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] })
     /*  994541 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  994544 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994548 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994553 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994556 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994559 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994562 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/255,
     /*  994565 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994569 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994571 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  994574 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994578 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994583 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994586 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994589 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994592 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*  994595 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994599 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  994601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994604 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994606 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994609 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994612 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  994615 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994618 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994623 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994628 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994633 */   // GIR_Coverage, 28140,
     /*  994633 */   GIR_EraseRootFromParent_Done,
     /*  994634 */ // Label 15757: @994634
     /*  994634 */ GIM_Try, /*On fail goto*//*Label 15758*/ GIMT_Encode4(994742), // Rule ID 28141 //
     /*  994639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  994642 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  994645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994649 */   // (sext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] })
     /*  994649 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  994652 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994656 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994661 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994664 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994667 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  994670 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/255,
     /*  994673 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994677 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  994679 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  994682 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994686 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  994691 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994694 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994697 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  994700 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/255,
     /*  994703 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  994707 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  994709 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  994712 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  994714 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  994717 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  994720 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  994723 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  994726 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  994731 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994736 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994741 */   // GIR_Coverage, 28141,
     /*  994741 */   GIR_EraseRootFromParent_Done,
     /*  994742 */ // Label 15758: @994742
     /*  994742 */ GIM_Reject,
     /*  994743 */ // Label 15734: @994743
     /*  994743 */ GIM_Reject,
     /*  994744 */ // Label 47: @994744
     /*  994744 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 15762*/ GIMT_Encode4(998775),
     /*  994755 */ /*GILLT_s16*//*Label 15759*/ GIMT_Encode4(994767),
     /*  994759 */ /*GILLT_s32*//*Label 15760*/ GIMT_Encode4(994926),
     /*  994763 */ /*GILLT_s64*//*Label 15761*/ GIMT_Encode4(996368),
     /*  994767 */ // Label 15759: @994767
     /*  994767 */ GIM_Try, /*On fail goto*//*Label 15763*/ GIMT_Encode4(994925),
     /*  994772 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  994775 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994779 */   GIM_Try, /*On fail goto*//*Label 15764*/ GIMT_Encode4(994808), // Rule ID 7194 //
     /*  994784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode0),
     /*  994787 */     // (zext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  994787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  994792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994798 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  994804 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994806 */     GIR_RootConstrainSelectedInstOperands,
     /*  994807 */     // GIR_Coverage, 7194,
     /*  994807 */     GIR_EraseRootFromParent_Done,
     /*  994808 */   // Label 15764: @994808
     /*  994808 */   GIM_Try, /*On fail goto*//*Label 15765*/ GIMT_Encode4(994837), // Rule ID 7195 //
     /*  994813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode1),
     /*  994816 */     // (zext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  994816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  994821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994830 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  994833 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994835 */     GIR_RootConstrainSelectedInstOperands,
     /*  994836 */     // GIR_Coverage, 7195,
     /*  994836 */     GIR_EraseRootFromParent_Done,
     /*  994837 */   // Label 15765: @994837
     /*  994837 */   GIM_Try, /*On fail goto*//*Label 15766*/ GIMT_Encode4(994866), // Rule ID 7196 //
     /*  994842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode2),
     /*  994845 */     // (zext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  994845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  994850 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994853 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994856 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994859 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  994862 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994864 */     GIR_RootConstrainSelectedInstOperands,
     /*  994865 */     // GIR_Coverage, 7196,
     /*  994865 */     GIR_EraseRootFromParent_Done,
     /*  994866 */   // Label 15766: @994866
     /*  994866 */   GIM_Try, /*On fail goto*//*Label 15767*/ GIMT_Encode4(994895), // Rule ID 7197 //
     /*  994871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode3),
     /*  994874 */     // (zext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  994874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  994879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994888 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  994891 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994893 */     GIR_RootConstrainSelectedInstOperands,
     /*  994894 */     // GIR_Coverage, 7197,
     /*  994894 */     GIR_EraseRootFromParent_Done,
     /*  994895 */   // Label 15767: @994895
     /*  994895 */   GIM_Try, /*On fail goto*//*Label 15768*/ GIMT_Encode4(994924), // Rule ID 7198 //
     /*  994900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HwMode4),
     /*  994903 */     // (zext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
     /*  994903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  994906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  994908 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994911 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  994917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  994920 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  994922 */     GIR_RootConstrainSelectedInstOperands,
     /*  994923 */     // GIR_Coverage, 7198,
     /*  994923 */     GIR_EraseRootFromParent_Done,
     /*  994924 */   // Label 15768: @994924
     /*  994924 */   GIM_Reject,
     /*  994925 */ // Label 15763: @994925
     /*  994925 */ GIM_Reject,
     /*  994926 */ // Label 15760: @994926
     /*  994926 */ GIM_Try, /*On fail goto*//*Label 15769*/ GIMT_Encode4(995002), // Rule ID 7191 //
     /*  994931 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  994934 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  994937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  994941 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  994945 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*  994949 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  994953 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  994957 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  994961 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  994965 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  994969 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  994973 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  994977 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  994981 */   // MIs[3] Operand 1
     /*  994981 */   // No operand predicates
     /*  994981 */   GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  994985 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  994987 */   // (zext:{ *:[i32] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (V_ASHRREV_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  994987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
     /*  994990 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  994992 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  994996 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  995000 */   GIR_RootConstrainSelectedInstOperands,
     /*  995001 */   // GIR_Coverage, 7191,
     /*  995001 */   GIR_EraseRootFromParent_Done,
     /*  995002 */ // Label 15769: @995002
     /*  995002 */ GIM_Try, /*On fail goto*//*Label 15770*/ GIMT_Encode4(995078), // Rule ID 7187 //
     /*  995007 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995010 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995013 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995017 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995021 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  995025 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995029 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995033 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  995037 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  995041 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  995045 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  995049 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  995053 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  995057 */   // MIs[3] Operand 1
     /*  995057 */   // No operand predicates
     /*  995057 */   GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  995061 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  995063 */   // (zext:{ *:[i32] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (V_LSHRREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
     /*  995066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995068 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  995072 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  995076 */   GIR_RootConstrainSelectedInstOperands,
     /*  995077 */   // GIR_Coverage, 7187,
     /*  995077 */   GIR_EraseRootFromParent_Done,
     /*  995078 */ // Label 15770: @995078
     /*  995078 */ GIM_Try, /*On fail goto*//*Label 15771*/ GIMT_Encode4(995154), // Rule ID 7183 //
     /*  995083 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995086 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995093 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995097 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  995101 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995105 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995109 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  995113 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  995117 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  995121 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  995125 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  995129 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  995133 */   // MIs[3] Operand 1
     /*  995133 */   // No operand predicates
     /*  995133 */   GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  995137 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  995139 */   // (zext:{ *:[i32] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (V_LSHLREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995139 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
     /*  995142 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995144 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  995148 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  995152 */   GIR_RootConstrainSelectedInstOperands,
     /*  995153 */   // GIR_Coverage, 7183,
     /*  995153 */   GIR_EraseRootFromParent_Done,
     /*  995154 */ // Label 15771: @995154
     /*  995154 */ GIM_Try, /*On fail goto*//*Label 15772*/ GIMT_Encode4(995218), // Rule ID 7169 //
     /*  995159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995162 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995169 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995173 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  995177 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995181 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995185 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  995189 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  995193 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
     /*  995197 */   // MIs[2] Operand 1
     /*  995197 */   // No operand predicates
     /*  995197 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  995199 */   // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1))  =>  (V_SUB_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1))
     /*  995199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
     /*  995202 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995204 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995208 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
     /*  995213 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995216 */   GIR_RootConstrainSelectedInstOperands,
     /*  995217 */   // GIR_Coverage, 7169,
     /*  995217 */   GIR_EraseRootFromParent_Done,
     /*  995218 */ // Label 15772: @995218
     /*  995218 */ GIM_Try, /*On fail goto*//*Label 15773*/ GIMT_Encode4(995289), // Rule ID 7230 //
     /*  995223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995233 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995237 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  995241 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995245 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995249 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  995253 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  995257 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  995261 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  995265 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  995267 */   // (zext:{ *:[i32] } (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MAD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, VSrc_b16:{ *:[i16] }:$src2)
     /*  995267 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
     /*  995270 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995272 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  995276 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
     /*  995280 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /*  995284 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995287 */   GIR_RootConstrainSelectedInstOperands,
     /*  995288 */   // GIR_Coverage, 7230,
     /*  995288 */   GIR_EraseRootFromParent_Done,
     /*  995289 */ // Label 15773: @995289
     /*  995289 */ GIM_Try, /*On fail goto*//*Label 15774*/ GIMT_Encode4(995360), // Rule ID 31336 //
     /*  995294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995297 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995304 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995308 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  995312 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995316 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995320 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  995324 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  995328 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  995332 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  995336 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  995338 */   // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MAD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, VSrc_b16:{ *:[i16] }:$src2)
     /*  995338 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
     /*  995341 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995343 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  995347 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
     /*  995351 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
     /*  995355 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995358 */   GIR_RootConstrainSelectedInstOperands,
     /*  995359 */   // GIR_Coverage, 31336,
     /*  995359 */   GIR_EraseRootFromParent_Done,
     /*  995360 */ // Label 15774: @995360
     /*  995360 */ GIM_Try, /*On fail goto*//*Label 15775*/ GIMT_Encode4(995430), // Rule ID 28313 //
     /*  995365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts_isGFX8Plus),
     /*  995368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995375 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995379 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /*  995383 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995387 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995389 */   // (zext:{ *:[i32] } (bswap:{ *:[i16] } i16:{ *:[i16] }:$a))  =>  (V_PERM_B32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 202113025:{ *:[i32] }))
     /*  995389 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  995392 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  995396 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  995401 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(202113025),
     /*  995411 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  995413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*  995416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995418 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995421 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*  995425 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  995428 */   GIR_RootConstrainSelectedInstOperands,
     /*  995429 */   // GIR_Coverage, 28313,
     /*  995429 */   GIR_EraseRootFromParent_Done,
     /*  995430 */ // Label 15775: @995430
     /*  995430 */ GIM_Try, /*On fail goto*//*Label 15776*/ GIMT_Encode4(995517), // Rule ID 28315 //
     /*  995435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts_isGFX8Plus),
     /*  995438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995445 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995449 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /*  995453 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995457 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995459 */   // (zext:{ *:[i32] } (bswap:{ *:[i16] } i16:{ *:[i16] }:$a))  =>  (V_PERM_B32_e64:{ *:[i32] } 0:{ *:[i32] }, (COPY:{ *:[i16] } VGPR_16:{ *:[i16] }:$a), (S_MOV_B32:{ *:[i16] } 202113025:{ *:[i32] }))
     /*  995459 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  995462 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  995466 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  995471 */   GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(202113025),
     /*  995481 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  995483 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  995486 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  995490 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  995495 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
     /*  995499 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  995501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
     /*  995504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995506 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995509 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  995512 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  995515 */   GIR_RootConstrainSelectedInstOperands,
     /*  995516 */   // GIR_Coverage, 28315,
     /*  995516 */   GIR_EraseRootFromParent_Done,
     /*  995517 */ // Label 15776: @995517
     /*  995517 */ GIM_Try, /*On fail goto*//*Label 15777*/ GIMT_Encode4(995568), // Rule ID 7160 //
     /*  995522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995532 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995536 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  995540 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995544 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995548 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995550 */   // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_ADD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995550 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64),
     /*  995553 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995555 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995559 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  995563 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995566 */   GIR_RootConstrainSelectedInstOperands,
     /*  995567 */   // GIR_Coverage, 7160,
     /*  995567 */   GIR_EraseRootFromParent_Done,
     /*  995568 */ // Label 15777: @995568
     /*  995568 */ GIM_Try, /*On fail goto*//*Label 15778*/ GIMT_Encode4(995616), // Rule ID 7190 //
     /*  995573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995576 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995583 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995587 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*  995591 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995595 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995599 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995601 */   // (zext:{ *:[i32] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_ASHRREV_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
     /*  995604 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995606 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*  995610 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  995614 */   GIR_RootConstrainSelectedInstOperands,
     /*  995615 */   // GIR_Coverage, 7190,
     /*  995615 */   GIR_EraseRootFromParent_Done,
     /*  995616 */ // Label 15778: @995616
     /*  995616 */ GIM_Try, /*On fail goto*//*Label 15779*/ GIMT_Encode4(995664), // Rule ID 7186 //
     /*  995621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995631 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995635 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  995639 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995643 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995647 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995649 */   // (zext:{ *:[i32] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_LSHRREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995649 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
     /*  995652 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995654 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*  995658 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  995662 */   GIR_RootConstrainSelectedInstOperands,
     /*  995663 */   // GIR_Coverage, 7186,
     /*  995663 */   GIR_EraseRootFromParent_Done,
     /*  995664 */ // Label 15779: @995664
     /*  995664 */ GIM_Try, /*On fail goto*//*Label 15780*/ GIMT_Encode4(995712), // Rule ID 7170 //
     /*  995669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995679 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995683 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  995687 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995691 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995695 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995697 */   // (zext:{ *:[i32] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MUL_LO_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995697 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64),
     /*  995700 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995702 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995706 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  995710 */   GIR_RootConstrainSelectedInstOperands,
     /*  995711 */   // GIR_Coverage, 7170,
     /*  995711 */   GIR_EraseRootFromParent_Done,
     /*  995712 */ // Label 15780: @995712
     /*  995712 */ GIM_Try, /*On fail goto*//*Label 15781*/ GIMT_Encode4(995760), // Rule ID 7182 //
     /*  995717 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995720 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995727 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995731 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  995735 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995739 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995743 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995745 */   // (zext:{ *:[i32] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_LSHLREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995745 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
     /*  995748 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995750 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*  995754 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  995758 */   GIR_RootConstrainSelectedInstOperands,
     /*  995759 */   // GIR_Coverage, 7182,
     /*  995759 */   GIR_EraseRootFromParent_Done,
     /*  995760 */ // Label 15781: @995760
     /*  995760 */ GIM_Try, /*On fail goto*//*Label 15782*/ GIMT_Encode4(995808), // Rule ID 7176 //
     /*  995765 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995768 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995771 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995775 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995779 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
     /*  995783 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995787 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995791 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995793 */   // (zext:{ *:[i32] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAX_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995793 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_e64),
     /*  995796 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995798 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995802 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  995806 */   GIR_RootConstrainSelectedInstOperands,
     /*  995807 */   // GIR_Coverage, 7176,
     /*  995807 */   GIR_EraseRootFromParent_Done,
     /*  995808 */ // Label 15782: @995808
     /*  995808 */ GIM_Try, /*On fail goto*//*Label 15783*/ GIMT_Encode4(995856), // Rule ID 7174 //
     /*  995813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995823 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995827 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
     /*  995831 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995835 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995839 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995841 */   // (zext:{ *:[i32] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MIN_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_e64),
     /*  995844 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995846 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995850 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  995854 */   GIR_RootConstrainSelectedInstOperands,
     /*  995855 */   // GIR_Coverage, 7174,
     /*  995855 */   GIR_EraseRootFromParent_Done,
     /*  995856 */ // Label 15783: @995856
     /*  995856 */ GIM_Try, /*On fail goto*//*Label 15784*/ GIMT_Encode4(995907), // Rule ID 7172 //
     /*  995861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995871 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995875 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  995879 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995883 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995887 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995889 */   // (zext:{ *:[i32] } (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_SUB_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995889 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
     /*  995892 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995894 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995898 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  995902 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  995905 */   GIR_RootConstrainSelectedInstOperands,
     /*  995906 */   // GIR_Coverage, 7172,
     /*  995906 */   GIR_EraseRootFromParent_Done,
     /*  995907 */ // Label 15784: @995907
     /*  995907 */ GIM_Try, /*On fail goto*//*Label 15785*/ GIMT_Encode4(995955), // Rule ID 7180 //
     /*  995912 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995915 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995918 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995922 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995926 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*  995930 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995934 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995938 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995940 */   // (zext:{ *:[i32] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAX_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_e64),
     /*  995943 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995945 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995949 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  995953 */   GIR_RootConstrainSelectedInstOperands,
     /*  995954 */   // GIR_Coverage, 7180,
     /*  995954 */   GIR_EraseRootFromParent_Done,
     /*  995955 */ // Label 15785: @995955
     /*  995955 */ GIM_Try, /*On fail goto*//*Label 15786*/ GIMT_Encode4(996003), // Rule ID 7178 //
     /*  995960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  995963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  995966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  995970 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  995974 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*  995978 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  995982 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  995986 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  995988 */   // (zext:{ *:[i32] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MIN_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
     /*  995988 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_e64),
     /*  995991 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  995993 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  995997 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  996001 */   GIR_RootConstrainSelectedInstOperands,
     /*  996002 */   // GIR_Coverage, 7178,
     /*  996002 */   GIR_EraseRootFromParent_Done,
     /*  996003 */ // Label 15786: @996003
     /*  996003 */ GIM_Try, /*On fail goto*//*Label 15787*/ GIMT_Encode4(996058), // Rule ID 4813 //
     /*  996008 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  996015 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20825),
     /*  996019 */   // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_20825>>  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src)
     /*  996019 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  996022 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  996026 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996031 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
     /*  996041 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*  996046 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  996048 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996051 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  996053 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  996056 */   GIR_RootConstrainSelectedInstOperands,
     /*  996057 */   // GIR_Coverage, 4813,
     /*  996057 */   GIR_EraseRootFromParent_Done,
     /*  996058 */ // Label 15787: @996058
     /*  996058 */ GIM_Try, /*On fail goto*//*Label 15788*/ GIMT_Encode4(996113), // Rule ID 28260 //
     /*  996063 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*  996066 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996069 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996073 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45283),
     /*  996077 */   // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_45283>>  =>  (V_AND_B32_e64:{ *:[i32] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src)
     /*  996077 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996080 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  996084 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996089 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
     /*  996099 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  996104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  996106 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996109 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  996111 */   GIR_RootConstrainSelectedInstOperands,
     /*  996112 */   // GIR_Coverage, 28260,
     /*  996112 */   GIR_EraseRootFromParent_Done,
     /*  996113 */ // Label 15788: @996113
     /*  996113 */ GIM_Try, /*On fail goto*//*Label 15789*/ GIMT_Encode4(996187), // Rule ID 28268 //
     /*  996118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  996121 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996128 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45283),
     /*  996132 */   // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_45283>>  =>  (REG_SEQUENCE:{ *:[i32] } VGPR_32:{ *:[i32] }, VGPR_16:{ *:[i16] }:$src, lo16:{ *:[i32] }, (V_MOV_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i16] }, 0:{ *:[i32] }), hi16:{ *:[i32] })
     /*  996132 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996135 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B16_t16_e64),
     /*  996139 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996144 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  996147 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  996150 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  996153 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  996158 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  996160 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  996162 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*  996165 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996168 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*  996171 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996176 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  996181 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  996186 */   // GIR_Coverage, 28268,
     /*  996186 */   GIR_EraseRootFromParent_Done,
     /*  996187 */ // Label 15789: @996187
     /*  996187 */ GIM_Try, /*On fail goto*//*Label 15790*/ GIMT_Encode4(996223), // Rule ID 28006 //
     /*  996192 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  996195 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  996198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996202 */   // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  996202 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  996205 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  996207 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996210 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996213 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996216 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  996219 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  996221 */   GIR_RootConstrainSelectedInstOperands,
     /*  996222 */   // GIR_Coverage, 28006,
     /*  996222 */   GIR_EraseRootFromParent_Done,
     /*  996223 */ // Label 15790: @996223
     /*  996223 */ GIM_Try, /*On fail goto*//*Label 15791*/ GIMT_Encode4(996259), // Rule ID 28007 //
     /*  996228 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  996231 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  996234 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996238 */   // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  996238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  996241 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  996243 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996246 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996249 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996252 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  996255 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  996257 */   GIR_RootConstrainSelectedInstOperands,
     /*  996258 */   // GIR_Coverage, 28007,
     /*  996258 */   GIR_EraseRootFromParent_Done,
     /*  996259 */ // Label 15791: @996259
     /*  996259 */ GIM_Try, /*On fail goto*//*Label 15792*/ GIMT_Encode4(996295), // Rule ID 28008 //
     /*  996264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  996267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  996270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996274 */   // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  996274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  996277 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  996279 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996282 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996285 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996288 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  996291 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  996293 */   GIR_RootConstrainSelectedInstOperands,
     /*  996294 */   // GIR_Coverage, 28008,
     /*  996294 */   GIR_EraseRootFromParent_Done,
     /*  996295 */ // Label 15792: @996295
     /*  996295 */ GIM_Try, /*On fail goto*//*Label 15793*/ GIMT_Encode4(996331), // Rule ID 28009 //
     /*  996300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  996303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  996306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996310 */   // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  996310 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  996313 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  996315 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996318 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996321 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996324 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  996327 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  996329 */   GIR_RootConstrainSelectedInstOperands,
     /*  996330 */   // GIR_Coverage, 28009,
     /*  996330 */   GIR_EraseRootFromParent_Done,
     /*  996331 */ // Label 15793: @996331
     /*  996331 */ GIM_Try, /*On fail goto*//*Label 15794*/ GIMT_Encode4(996367), // Rule ID 28010 //
     /*  996336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  996339 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  996342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996346 */   // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
     /*  996346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  996349 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  996351 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996354 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996357 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  996360 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  996363 */   GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  996365 */   GIR_RootConstrainSelectedInstOperands,
     /*  996366 */   // GIR_Coverage, 28010,
     /*  996366 */   GIR_EraseRootFromParent_Done,
     /*  996367 */ // Label 15794: @996367
     /*  996367 */ GIM_Reject,
     /*  996368 */ // Label 15761: @996368
     /*  996368 */ GIM_Try, /*On fail goto*//*Label 15795*/ GIMT_Encode4(996501), // Rule ID 7193 //
     /*  996373 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  996376 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996383 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  996387 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*  996391 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  996395 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  996399 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  996403 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  996407 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  996411 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  996415 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  996419 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  996423 */   // MIs[3] Operand 1
     /*  996423 */   // No operand predicates
     /*  996423 */   GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  996427 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  996429 */   // (zext:{ *:[i64] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_ASHRREV_I16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  996429 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  996432 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  996436 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996441 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  996444 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  996446 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996449 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
     /*  996453 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996458 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  996462 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  996466 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996468 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  996471 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  996473 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996476 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  996479 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  996482 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  996485 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996490 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996495 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996500 */   // GIR_Coverage, 7193,
     /*  996500 */   GIR_EraseRootFromParent_Done,
     /*  996501 */ // Label 15795: @996501
     /*  996501 */ GIM_Try, /*On fail goto*//*Label 15796*/ GIMT_Encode4(996634), // Rule ID 7189 //
     /*  996506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  996509 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996516 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  996520 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  996524 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  996528 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  996532 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  996536 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  996540 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  996544 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  996548 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  996552 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  996556 */   // MIs[3] Operand 1
     /*  996556 */   // No operand predicates
     /*  996556 */   GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  996560 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  996562 */   // (zext:{ *:[i64] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_LSHRREV_B16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  996562 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  996565 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  996569 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996574 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  996577 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  996579 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996582 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
     /*  996586 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996591 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  996595 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  996599 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  996604 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  996606 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996609 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  996612 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  996615 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  996618 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996623 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996628 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996633 */   // GIR_Coverage, 7189,
     /*  996633 */   GIR_EraseRootFromParent_Done,
     /*  996634 */ // Label 15796: @996634
     /*  996634 */ GIM_Try, /*On fail goto*//*Label 15797*/ GIMT_Encode4(996767), // Rule ID 7185 //
     /*  996639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  996642 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996649 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  996653 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  996657 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  996661 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  996665 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  996669 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  996673 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /*  996677 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
     /*  996681 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  996685 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  996689 */   // MIs[3] Operand 1
     /*  996689 */   // No operand predicates
     /*  996689 */   GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  996693 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  996695 */   // (zext:{ *:[i64] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_LSHLREV_B16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  996695 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  996698 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  996702 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996707 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  996710 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  996712 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996715 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
     /*  996719 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996724 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src0
     /*  996728 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  996732 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  996737 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  996739 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996742 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  996745 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  996748 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  996751 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996756 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996761 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996766 */   // GIR_Coverage, 7185,
     /*  996766 */   GIR_EraseRootFromParent_Done,
     /*  996767 */ // Label 15797: @996767
     /*  996767 */ GIM_Try, /*On fail goto*//*Label 15798*/ GIMT_Encode4(996875), // Rule ID 7161 //
     /*  996772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  996775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996782 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  996786 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  996790 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  996794 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  996798 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  996800 */   // (zext:{ *:[i64] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_ADD_U16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  996800 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  996803 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  996807 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996812 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  996815 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  996817 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996820 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64),
     /*  996824 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996829 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  996833 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  996837 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  996840 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  996845 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  996847 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996850 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  996853 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  996856 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  996859 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996864 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996869 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996874 */   // GIR_Coverage, 7161,
     /*  996874 */   GIR_EraseRootFromParent_Done,
     /*  996875 */ // Label 15798: @996875
     /*  996875 */ GIM_Try, /*On fail goto*//*Label 15799*/ GIMT_Encode4(996980), // Rule ID 7192 //
     /*  996880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  996883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996890 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  996894 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
     /*  996898 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  996902 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  996906 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  996908 */   // (zext:{ *:[i64] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_ASHRREV_I16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  996908 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  996911 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  996915 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996920 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  996923 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  996925 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  996928 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
     /*  996932 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  996937 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*  996941 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  996945 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  996947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  996950 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  996952 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  996955 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  996958 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  996961 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  996964 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996969 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996974 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  996979 */   // GIR_Coverage, 7192,
     /*  996979 */   GIR_EraseRootFromParent_Done,
     /*  996980 */ // Label 15799: @996980
     /*  996980 */ GIM_Try, /*On fail goto*//*Label 15800*/ GIMT_Encode4(997085), // Rule ID 7188 //
     /*  996985 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  996988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  996991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  996995 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  996999 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  997003 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997007 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997011 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997013 */   // (zext:{ *:[i64] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_LSHRREV_B16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997013 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997016 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997020 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997025 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997028 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997030 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997033 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
     /*  997037 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997042 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*  997046 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  997050 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997052 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997055 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997057 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997060 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997063 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997066 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997069 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997074 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997079 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997084 */   // GIR_Coverage, 7188,
     /*  997084 */   GIR_EraseRootFromParent_Done,
     /*  997085 */ // Label 15800: @997085
     /*  997085 */ GIM_Try, /*On fail goto*//*Label 15801*/ GIMT_Encode4(997190), // Rule ID 7171 //
     /*  997090 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997100 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997104 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  997108 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997112 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997116 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997118 */   // (zext:{ *:[i64] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_LO_U16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997118 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997121 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997125 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997130 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997133 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997135 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997138 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64),
     /*  997142 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997147 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  997151 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  997155 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997162 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997165 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997168 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997171 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997174 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997179 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997184 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997189 */   // GIR_Coverage, 7171,
     /*  997189 */   GIR_EraseRootFromParent_Done,
     /*  997190 */ // Label 15801: @997190
     /*  997190 */ GIM_Try, /*On fail goto*//*Label 15802*/ GIMT_Encode4(997295), // Rule ID 7184 //
     /*  997195 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997198 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997205 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997209 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  997213 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997217 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997221 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997223 */   // (zext:{ *:[i64] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_LSHLREV_B16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997223 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997226 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997230 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997235 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997238 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997240 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997243 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
     /*  997247 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997252 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src0
     /*  997256 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  997260 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997262 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997265 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997267 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997270 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997273 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997276 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997279 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997284 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997289 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997294 */   // GIR_Coverage, 7184,
     /*  997294 */   GIR_EraseRootFromParent_Done,
     /*  997295 */ // Label 15802: @997295
     /*  997295 */ GIM_Try, /*On fail goto*//*Label 15803*/ GIMT_Encode4(997400), // Rule ID 7177 //
     /*  997300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997306 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997310 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997314 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
     /*  997318 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997322 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997326 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997328 */   // (zext:{ *:[i64] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MAX_I16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997328 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997331 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997335 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997340 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997343 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997345 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997348 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_e64),
     /*  997352 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997357 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  997361 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  997365 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997367 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997370 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997372 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997375 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997378 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997381 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997384 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997389 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997394 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997399 */   // GIR_Coverage, 7177,
     /*  997399 */   GIR_EraseRootFromParent_Done,
     /*  997400 */ // Label 15803: @997400
     /*  997400 */ GIM_Try, /*On fail goto*//*Label 15804*/ GIMT_Encode4(997505), // Rule ID 7175 //
     /*  997405 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997408 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997415 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997419 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
     /*  997423 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997427 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997431 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997433 */   // (zext:{ *:[i64] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MIN_I16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997433 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997436 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997440 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997445 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997448 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997450 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997453 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_e64),
     /*  997457 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997462 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  997466 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  997470 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997477 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997480 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997483 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997486 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997489 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997494 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997499 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997504 */   // GIR_Coverage, 7175,
     /*  997504 */   GIR_EraseRootFromParent_Done,
     /*  997505 */ // Label 15804: @997505
     /*  997505 */ GIM_Try, /*On fail goto*//*Label 15805*/ GIMT_Encode4(997613), // Rule ID 7173 //
     /*  997510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997520 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997524 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  997528 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997532 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997536 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997538 */   // (zext:{ *:[i64] } (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_SUB_U16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997538 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997541 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997545 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997550 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997553 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997555 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997558 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
     /*  997562 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997567 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  997571 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  997575 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  997578 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997580 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997583 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997585 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997588 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997591 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997594 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997597 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997602 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997607 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997612 */   // GIR_Coverage, 7173,
     /*  997612 */   GIR_EraseRootFromParent_Done,
     /*  997613 */ // Label 15805: @997613
     /*  997613 */ GIM_Try, /*On fail goto*//*Label 15806*/ GIMT_Encode4(997718), // Rule ID 7181 //
     /*  997618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997621 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997628 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997632 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
     /*  997636 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997640 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997644 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997646 */   // (zext:{ *:[i64] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MAX_U16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997646 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997649 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997653 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997658 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997661 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997663 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997666 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_e64),
     /*  997670 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997675 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  997679 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  997683 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997690 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997693 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997696 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997699 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997702 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997707 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997712 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997717 */   // GIR_Coverage, 7181,
     /*  997717 */   GIR_EraseRootFromParent_Done,
     /*  997718 */ // Label 15806: @997718
     /*  997718 */ GIM_Try, /*On fail goto*//*Label 15807*/ GIMT_Encode4(997823), // Rule ID 7179 //
     /*  997723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
     /*  997726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997733 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  997737 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
     /*  997741 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  997745 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  997749 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  997751 */   // (zext:{ *:[i64] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MIN_U16_e64:{ *:[i16] } ?:{ *:[i16] }:$src0, ?:{ *:[i16] }:$src1), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997751 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  997754 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  997758 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997763 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  997766 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997768 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  997771 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_e64),
     /*  997775 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997780 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  997784 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  997788 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997793 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997795 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997798 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997801 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  997804 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997807 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  997812 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997817 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  997822 */   // GIR_Coverage, 7179,
     /*  997822 */   GIR_EraseRootFromParent_Done,
     /*  997823 */ // Label 15807: @997823
     /*  997823 */ GIM_Try, /*On fail goto*//*Label 15808*/ GIMT_Encode4(997957), // Rule ID 4811 //
     /*  997828 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  997831 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  997835 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20825),
     /*  997839 */   // (zext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_20825>>  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_AND_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] })), SGPR_32:{ *:[i32] }), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997839 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s1,
     /*  997842 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  997846 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997851 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /*  997854 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /*  997856 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1,
     /*  997859 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  997863 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997868 */   GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(65535),
     /*  997878 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  997880 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  997883 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /*  997887 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997892 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  997896 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  997899 */   GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for AMDGPU::SCC*/0,
     /*  997902 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  997904 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  997907 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  997911 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997916 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  997919 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
     /*  997924 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997927 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997929 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  997932 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  997935 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /*  997938 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  997941 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  997946 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  997951 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  997956 */   // GIR_Coverage, 4811,
     /*  997956 */   GIR_EraseRootFromParent_Done,
     /*  997957 */ // Label 15808: @997957
     /*  997957 */ GIM_Try, /*On fail goto*//*Label 15809*/ GIMT_Encode4(998022), // Rule ID 28121 //
     /*  997962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  997965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  997969 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20825),
     /*  997973 */   // (zext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_20825>>  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  997973 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /*  997976 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  997980 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  997985 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  997988 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  997990 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  997993 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  997995 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  997997 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998000 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998003 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998006 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  998011 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /*  998016 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /*  998021 */   // GIR_Coverage, 28121,
     /*  998021 */   GIR_EraseRootFromParent_Done,
     /*  998022 */ // Label 15809: @998022
     /*  998022 */ GIM_Try, /*On fail goto*//*Label 15810*/ GIMT_Encode4(998136), // Rule ID 28261 //
     /*  998027 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotUseRealTrue16Insts),
     /*  998030 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  998033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998037 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45283),
     /*  998041 */   // (zext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_45283>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_AND_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998041 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1,
     /*  998044 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998048 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998053 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /*  998056 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  998058 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  998061 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998065 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998070 */   GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(65535),
     /*  998080 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998082 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998085 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
     /*  998089 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998094 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  998097 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  998101 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998106 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998108 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998111 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998114 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /*  998117 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998120 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998125 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998130 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998135 */   // GIR_Coverage, 28261,
     /*  998135 */   GIR_EraseRootFromParent_Done,
     /*  998136 */ // Label 15810: @998136
     /*  998136 */ GIM_Try, /*On fail goto*//*Label 15811*/ GIMT_Encode4(998238), // Rule ID 28269 //
     /*  998141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  998144 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  998147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998151 */   GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45283),
     /*  998155 */   // (zext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_45283>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i16] }:$src, lo16:{ *:[i32] }, (V_MOV_B16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i16] }, 0:{ *:[i32] }), hi16:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998155 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /*  998158 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  998162 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998167 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  998170 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998172 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998175 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B16_t16_e64),
     /*  998179 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998184 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998187 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998190 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998193 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998200 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  998202 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
     /*  998205 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998208 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
     /*  998211 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  998214 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998217 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998222 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  998227 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  998232 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/5, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998237 */   // GIR_Coverage, 28269,
     /*  998237 */   GIR_EraseRootFromParent_Done,
     /*  998238 */ // Label 15811: @998238
     /*  998238 */ GIM_Try, /*On fail goto*//*Label 15812*/ GIMT_Encode4(998299), // Rule ID 28122 //
     /*  998243 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  998246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998250 */   // (zext:{ *:[i64] } i32:{ *:[i32] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998250 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998253 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
     /*  998257 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998262 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998265 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998267 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998270 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998272 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  998274 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998277 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998280 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998283 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998288 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998293 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998298 */   // GIR_Coverage, 28122,
     /*  998298 */   GIR_EraseRootFromParent_Done,
     /*  998299 */ // Label 15812: @998299
     /*  998299 */ GIM_Try, /*On fail goto*//*Label 15813*/ GIMT_Encode4(998394), // Rule ID 28125 //
     /*  998304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0),
     /*  998307 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  998310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998314 */   // (zext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998314 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  998317 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998321 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998326 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  998329 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998331 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998334 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  998338 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998343 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998346 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998349 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998352 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  998355 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  998359 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998361 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998364 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998366 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998369 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998372 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  998375 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998378 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998383 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998388 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998393 */   // GIR_Coverage, 28125,
     /*  998393 */   GIR_EraseRootFromParent_Done,
     /*  998394 */ // Label 15813: @998394
     /*  998394 */ GIM_Try, /*On fail goto*//*Label 15814*/ GIMT_Encode4(998489), // Rule ID 28126 //
     /*  998399 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1),
     /*  998402 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  998405 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998409 */   // (zext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998409 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  998412 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998416 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998421 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  998424 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998426 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998429 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  998433 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998438 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998441 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998444 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998447 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  998450 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  998454 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998456 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998459 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998461 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998464 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998467 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  998470 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998473 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998478 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998483 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998488 */   // GIR_Coverage, 28126,
     /*  998488 */   GIR_EraseRootFromParent_Done,
     /*  998489 */ // Label 15814: @998489
     /*  998489 */ GIM_Try, /*On fail goto*//*Label 15815*/ GIMT_Encode4(998584), // Rule ID 28127 //
     /*  998494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode2),
     /*  998497 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  998500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998504 */   // (zext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998504 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  998507 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998511 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998516 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  998519 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998521 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998524 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  998528 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998533 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998536 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998539 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998542 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  998545 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  998549 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998551 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998554 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998556 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998559 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998562 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  998565 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998568 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998573 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998578 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998583 */   // GIR_Coverage, 28127,
     /*  998583 */   GIR_EraseRootFromParent_Done,
     /*  998584 */ // Label 15815: @998584
     /*  998584 */ GIM_Try, /*On fail goto*//*Label 15816*/ GIMT_Encode4(998679), // Rule ID 28128 //
     /*  998589 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode3),
     /*  998592 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  998595 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998599 */   // (zext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998599 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  998602 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998606 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998611 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  998614 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998616 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998619 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  998623 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998628 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998631 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998634 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998637 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  998640 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  998644 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998651 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998654 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998657 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  998660 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998663 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998668 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998673 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998678 */   // GIR_Coverage, 28128,
     /*  998678 */   GIR_EraseRootFromParent_Done,
     /*  998679 */ // Label 15816: @998679
     /*  998679 */ GIM_Try, /*On fail goto*//*Label 15817*/ GIMT_Encode4(998774), // Rule ID 28129 //
     /*  998684 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode4),
     /*  998687 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1,
     /*  998690 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998694 */   // (zext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
     /*  998694 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /*  998697 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
     /*  998701 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998706 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  998709 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  998711 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /*  998714 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
     /*  998718 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  998723 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998726 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998729 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  998732 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  998735 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  998739 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  998741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /*  998744 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  998746 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  998749 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
     /*  998752 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  998755 */   GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
     /*  998758 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /*  998763 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998768 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998773 */   // GIR_Coverage, 28129,
     /*  998773 */   GIR_EraseRootFromParent_Done,
     /*  998774 */ // Label 15817: @998774
     /*  998774 */ GIM_Reject,
     /*  998775 */ // Label 15762: @998775
     /*  998775 */ GIM_Reject,
     /*  998776 */ // Label 48: @998776
     /*  998776 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 15822*/ GIMT_Encode4(1001547),
     /*  998787 */ /*GILLT_s16*//*Label 15818*/ GIMT_Encode4(998803),
     /*  998791 */ /*GILLT_s32*//*Label 15819*/ GIMT_Encode4(999262),
     /*  998795 */ /*GILLT_s64*//*Label 15820*/ GIMT_Encode4(999903),
     /*  998799 */ /*GILLT_v2s16*//*Label 15821*/ GIMT_Encode4(1001378),
     /*  998803 */ // Label 15818: @998803
     /*  998803 */ GIM_Try, /*On fail goto*//*Label 15823*/ GIMT_Encode4(999261),
     /*  998808 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /*  998811 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /*  998814 */   GIM_Try, /*On fail goto*//*Label 15824*/ GIMT_Encode4(998903), // Rule ID 2656 //
     /*  998819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /*  998822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  998826 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  998830 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  998834 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  998838 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  998842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  998846 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  998850 */     // MIs[2] Operand 1
     /*  998850 */     // No operand predicates
     /*  998850 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  998854 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  998856 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /*  998863 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /*  998870 */     // (shl:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHLREV_B16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*  998870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_opsel_e64),
     /*  998873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  998875 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  998880 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  998885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /*  998890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /*  998895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  998898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  998901 */     GIR_RootConstrainSelectedInstOperands,
     /*  998902 */     // GIR_Coverage, 2656,
     /*  998902 */     GIR_EraseRootFromParent_Done,
     /*  998903 */   // Label 15824: @998903
     /*  998903 */   GIM_Try, /*On fail goto*//*Label 15825*/ GIMT_Encode4(998989), // Rule ID 2658 //
     /*  998908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  998911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  998915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  998919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  998923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  998927 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  998931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  998935 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  998939 */     // MIs[2] Operand 1
     /*  998939 */     // No operand predicates
     /*  998939 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  998943 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  998945 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  998952 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  998959 */     // (shl:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHLREV_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*  998959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_t16_e64),
     /*  998962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  998964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  998969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  998974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /*  998979 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /*  998984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  998987 */     GIR_RootConstrainSelectedInstOperands,
     /*  998988 */     // GIR_Coverage, 2658,
     /*  998988 */     GIR_EraseRootFromParent_Done,
     /*  998989 */   // Label 15825: @998989
     /*  998989 */   GIM_Try, /*On fail goto*//*Label 15826*/ GIMT_Encode4(999048), // Rule ID 2655 //
     /*  998994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /*  998997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999001 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /*  999008 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /*  999015 */     // (shl:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_LSHLREV_B16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*  999015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_opsel_e64),
     /*  999018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  999025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  999030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /*  999035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /*  999040 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  999043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  999046 */     GIR_RootConstrainSelectedInstOperands,
     /*  999047 */     // GIR_Coverage, 2655,
     /*  999047 */     GIR_EraseRootFromParent_Done,
     /*  999048 */   // Label 15826: @999048
     /*  999048 */   GIM_Try, /*On fail goto*//*Label 15827*/ GIMT_Encode4(999104), // Rule ID 2657 //
     /*  999053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /*  999056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /*  999060 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  999067 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /*  999074 */     // (shl:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_LSHLREV_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /*  999074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_t16_e64),
     /*  999077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /*  999084 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /*  999089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /*  999094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /*  999099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  999102 */     GIR_RootConstrainSelectedInstOperands,
     /*  999103 */     // GIR_Coverage, 2657,
     /*  999103 */     GIR_EraseRootFromParent_Done,
     /*  999104 */   // Label 15827: @999104
     /*  999104 */   GIM_Try, /*On fail goto*//*Label 15828*/ GIMT_Encode4(999159), // Rule ID 2654 //
     /*  999109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  999112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999124 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  999128 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  999132 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999136 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999140 */     // MIs[2] Operand 1
     /*  999140 */     // No operand predicates
     /*  999140 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  999144 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999146 */     // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHLREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*  999146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
     /*  999149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999151 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  999155 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*  999157 */     GIR_RootConstrainSelectedInstOperands,
     /*  999158 */     // GIR_Coverage, 2654,
     /*  999158 */     GIR_EraseRootFromParent_Done,
     /*  999159 */   // Label 15828: @999159
     /*  999159 */   GIM_Try, /*On fail goto*//*Label 15829*/ GIMT_Encode4(999214), // Rule ID 2660 //
     /*  999164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  999167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999171 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999175 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999179 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /*  999183 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /*  999187 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999191 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999195 */     // MIs[2] Operand 1
     /*  999195 */     // No operand predicates
     /*  999195 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /*  999199 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999201 */     // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHLREV_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*  999201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_fake16_e64),
     /*  999204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  999210 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*  999212 */     GIR_RootConstrainSelectedInstOperands,
     /*  999213 */     // GIR_Coverage, 2660,
     /*  999213 */     GIR_EraseRootFromParent_Done,
     /*  999214 */   // Label 15829: @999214
     /*  999214 */   GIM_Try, /*On fail goto*//*Label 15830*/ GIMT_Encode4(999237), // Rule ID 2653 //
     /*  999219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /*  999222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999226 */     // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHLREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*  999226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
     /*  999229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999231 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  999233 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*  999235 */     GIR_RootConstrainSelectedInstOperands,
     /*  999236 */     // GIR_Coverage, 2653,
     /*  999236 */     GIR_EraseRootFromParent_Done,
     /*  999237 */   // Label 15830: @999237
     /*  999237 */   GIM_Try, /*On fail goto*//*Label 15831*/ GIMT_Encode4(999260), // Rule ID 2659 //
     /*  999242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /*  999245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999249 */     // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHLREV_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /*  999249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_fake16_e64),
     /*  999252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999254 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  999256 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*  999258 */     GIR_RootConstrainSelectedInstOperands,
     /*  999259 */     // GIR_Coverage, 2659,
     /*  999259 */     GIR_EraseRootFromParent_Done,
     /*  999260 */   // Label 15831: @999260
     /*  999260 */   GIM_Reject,
     /*  999261 */ // Label 15823: @999261
     /*  999261 */ GIM_Reject,
     /*  999262 */ // Label 15819: @999262
     /*  999262 */ GIM_Try, /*On fail goto*//*Label 15832*/ GIMT_Encode4(999902),
     /*  999267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  999270 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  999273 */   GIM_Try, /*On fail goto*//*Label 15833*/ GIMT_Encode4(999341), // Rule ID 28493 //
     /*  999278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999282 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  999286 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  999290 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999294 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999298 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  999302 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  999306 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  999310 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*  999314 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1,
     /*  999318 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  999322 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45448),
     /*  999326 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999328 */     // (shl:{ *:[i32] } (add:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), -1:{ *:[i32] }), i32:{ *:[i32] }:$b)<<P:Predicate_anonymous_45448>>  =>  (S_BFM_B32:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b)
     /*  999328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BFM_B32),
     /*  999331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  999333 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // a
     /*  999337 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*  999339 */     GIR_RootConstrainSelectedInstOperands,
     /*  999340 */     // GIR_Coverage, 28493,
     /*  999340 */     GIR_EraseRootFromParent_Done,
     /*  999341 */   // Label 15833: @999341
     /*  999341 */   GIM_Try, /*On fail goto*//*Label 15834*/ GIMT_Encode4(999409), // Rule ID 28495 //
     /*  999346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999350 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  999354 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  999358 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999362 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999366 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  999370 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  999374 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  999378 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*  999382 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 1,
     /*  999386 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  999390 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_45450),
     /*  999394 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999396 */     // (shl:{ *:[i32] } (add:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, i32:{ *:[i32] }:$a), -1:{ *:[i32] }), i32:{ *:[i32] }:$b)<<P:Predicate_anonymous_45450>>  =>  (V_BFM_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b)
     /*  999396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFM_B32_e64),
     /*  999399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999401 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // a
     /*  999405 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /*  999407 */     GIR_RootConstrainSelectedInstOperands,
     /*  999408 */     // GIR_Coverage, 28495,
     /*  999408 */     GIR_EraseRootFromParent_Done,
     /*  999409 */   // Label 15834: @999409
     /*  999409 */   GIM_Try, /*On fail goto*//*Label 15835*/ GIMT_Encode4(999504), // Rule ID 7270 //
     /*  999414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  999417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  999425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  999429 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999433 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999437 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  999439 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x
     /*  999443 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y
     /*  999447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  999451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999455 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  999459 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /*  999463 */     GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/2, // Name : pred:2:z
     /*  999467 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  999471 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999475 */     // MIs[3] Operand 1
     /*  999475 */     // No operand predicates
     /*  999475 */     GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*  999479 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28482),
     /*  999483 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  999485 */     // (shl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y)<<P:Predicate_anonymous_28483>>, (and:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:2:Predicate_anonymous_28482>>  =>  (V_ADD_LSHL_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*  999485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_LSHL_U32_e64),
     /*  999488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  999494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  999498 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
     /*  999502 */     GIR_RootConstrainSelectedInstOperands,
     /*  999503 */     // GIR_Coverage, 7270,
     /*  999503 */     GIR_EraseRootFromParent_Done,
     /*  999504 */   // Label 15835: @999504
     /*  999504 */   GIM_Try, /*On fail goto*//*Label 15836*/ GIMT_Encode4(999572), // Rule ID 69 //
     /*  999509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999529 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999533 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999546 */     // MIs[2] Operand 1
     /*  999546 */     // No operand predicates
     /*  999546 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*  999550 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20783),
     /*  999554 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999556 */     // (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_20783>>  =>  (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*  999556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
     /*  999559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  999561 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  999563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  999567 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  999570 */     GIR_RootConstrainSelectedInstOperands,
     /*  999571 */     // GIR_Coverage, 69,
     /*  999571 */     GIR_EraseRootFromParent_Done,
     /*  999572 */   // Label 15836: @999572
     /*  999572 */   GIM_Try, /*On fail goto*//*Label 15837*/ GIMT_Encode4(999628), // Rule ID 7120 //
     /*  999577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999593 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999597 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999601 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999605 */     // MIs[2] Operand 1
     /*  999605 */     // No operand predicates
     /*  999605 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*  999609 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27130),
     /*  999613 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999615 */     // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_27130>>  =>  (V_LSHLREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
     /*  999615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*  999618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  999624 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  999626 */     GIR_RootConstrainSelectedInstOperands,
     /*  999627 */     // GIR_Coverage, 7120,
     /*  999627 */     GIR_EraseRootFromParent_Done,
     /*  999628 */   // Label 15837: @999628
     /*  999628 */   GIM_Try, /*On fail goto*//*Label 15838*/ GIMT_Encode4(999693), // Rule ID 7269 //
     /*  999633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
     /*  999636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  999644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  999648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999652 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999656 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  999658 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x
     /*  999662 */     GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y
     /*  999666 */     GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:2:z
     /*  999670 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_28482),
     /*  999674 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  999676 */     // (shl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y)<<P:Predicate_anonymous_28483>>, i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_anonymous_28482>>  =>  (V_ADD_LSHL_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
     /*  999676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_LSHL_U32_e64),
     /*  999679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  999685 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /*  999689 */     GIR_RootToRootCopy, /*OpIdx*/2, // src2
     /*  999691 */     GIR_RootConstrainSelectedInstOperands,
     /*  999692 */     // GIR_Coverage, 7269,
     /*  999692 */     GIR_EraseRootFromParent_Done,
     /*  999693 */   // Label 15838: @999693
     /*  999693 */   GIM_Try, /*On fail goto*//*Label 15839*/ GIMT_Encode4(999727), // Rule ID 68 //
     /*  999698 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999702 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999710 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20783),
     /*  999714 */     // (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20783>>  =>  (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*  999714 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
     /*  999719 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /*  999725 */     GIR_RootConstrainSelectedInstOperands,
     /*  999726 */     // GIR_Coverage, 68,
     /*  999726 */     GIR_Done,
     /*  999727 */   // Label 15839: @999727
     /*  999727 */   GIM_Try, /*On fail goto*//*Label 15840*/ GIMT_Encode4(999751), // Rule ID 7119 //
     /*  999732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999736 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27130),
     /*  999740 */     // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27130>>  =>  (V_LSHLREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
     /*  999740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*  999743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999745 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /*  999747 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  999749 */     GIR_RootConstrainSelectedInstOperands,
     /*  999750 */     // GIR_Coverage, 7119,
     /*  999750 */     GIR_EraseRootFromParent_Done,
     /*  999751 */   // Label 15840: @999751
     /*  999751 */   GIM_Try, /*On fail goto*//*Label 15841*/ GIMT_Encode4(999803), // Rule ID 2621 //
     /*  999756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999760 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999764 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999768 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999772 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999776 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999780 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999784 */     // MIs[2] Operand 1
     /*  999784 */     // No operand predicates
     /*  999784 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*  999788 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999790 */     // (shl:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHLREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  999790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*  999793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /*  999799 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*  999801 */     GIR_RootConstrainSelectedInstOperands,
     /*  999802 */     // GIR_Coverage, 2621,
     /*  999802 */     GIR_EraseRootFromParent_Done,
     /*  999803 */   // Label 15841: @999803
     /*  999803 */   GIM_Try, /*On fail goto*//*Label 15842*/ GIMT_Encode4(999858), // Rule ID 2652 //
     /*  999808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /*  999811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999827 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999831 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999835 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999839 */     // MIs[2] Operand 1
     /*  999839 */     // No operand predicates
     /*  999839 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /*  999843 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999845 */     // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  999845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B32_e64),
     /*  999848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999850 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  999852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  999856 */     GIR_RootConstrainSelectedInstOperands,
     /*  999857 */     // GIR_Coverage, 2652,
     /*  999857 */     GIR_EraseRootFromParent_Done,
     /*  999858 */   // Label 15842: @999858
     /*  999858 */   GIM_Try, /*On fail goto*//*Label 15843*/ GIMT_Encode4(999878), // Rule ID 2620 //
     /*  999863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999867 */     // (shl:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  999867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
     /*  999870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /*  999872 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /*  999874 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /*  999876 */     GIR_RootConstrainSelectedInstOperands,
     /*  999877 */     // GIR_Coverage, 2620,
     /*  999877 */     GIR_EraseRootFromParent_Done,
     /*  999878 */   // Label 15843: @999878
     /*  999878 */   GIM_Try, /*On fail goto*//*Label 15844*/ GIMT_Encode4(999901), // Rule ID 2651 //
     /*  999883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /*  999886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /*  999890 */     // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /*  999890 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B32_e64),
     /*  999895 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /*  999899 */     GIR_RootConstrainSelectedInstOperands,
     /*  999900 */     // GIR_Coverage, 2651,
     /*  999900 */     GIR_Done,
     /*  999901 */   // Label 15844: @999901
     /*  999901 */   GIM_Reject,
     /*  999902 */ // Label 15832: @999902
     /*  999902 */ GIM_Reject,
     /*  999903 */ // Label 15820: @999903
     /*  999903 */ GIM_Try, /*On fail goto*//*Label 15845*/ GIMT_Encode4(1001377),
     /*  999908 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  999911 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  999914 */   GIM_Try, /*On fail goto*//*Label 15846*/ GIMT_Encode4(999982), // Rule ID 71 //
     /*  999919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  999923 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_EncodableRegClassID),
     /*  999927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  999931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  999935 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  999939 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  999943 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999948 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  999952 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  999956 */     // MIs[2] Operand 1
     /*  999956 */     // No operand predicates
     /*  999956 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /*  999960 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20784),
     /*  999964 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  999966 */     // (shl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_20784>>  =>  (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /*  999966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B64),
     /*  999969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /*  999971 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /*  999973 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /*  999977 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /*  999980 */     GIR_RootConstrainSelectedInstOperands,
     /*  999981 */     // GIR_Coverage, 71,
     /*  999981 */     GIR_EraseRootFromParent_Done,
     /*  999982 */   // Label 15846: @999982
     /*  999982 */   GIM_Try, /*On fail goto*//*Label 15847*/ GIMT_Encode4(1000016), // Rule ID 70 //
     /*  999987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /*  999991 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_EncodableRegClassID),
     /*  999995 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /*  999999 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20784),
     /* 1000003 */     // (shl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20784>>  =>  (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1000003 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B64),
     /* 1000008 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /* 1000014 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000015 */     // GIR_Coverage, 70,
     /* 1000015 */     GIR_Done,
     /* 1000016 */   // Label 15847: @1000016
     /* 1000016 */   GIM_Try, /*On fail goto*//*Label 15848*/ GIMT_Encode4(1000081), // Rule ID 2936 //
     /* 1000021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /* 1000024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000036 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000040 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000044 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000048 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000052 */     // MIs[2] Operand 1
     /* 1000052 */     // No operand predicates
     /* 1000052 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000056 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000058 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000065 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000070 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000075 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1000079 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000080 */     // GIR_Coverage, 2936,
     /* 1000080 */     GIR_EraseRootFromParent_Done,
     /* 1000081 */   // Label 15848: @1000081
     /* 1000081 */   GIM_Try, /*On fail goto*//*Label 15849*/ GIMT_Encode4(1000146), // Rule ID 2937 //
     /* 1000086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /* 1000089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000117 */     // MIs[2] Operand 1
     /* 1000117 */     // No operand predicates
     /* 1000117 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000121 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000123 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000130 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1000144 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000145 */     // GIR_Coverage, 2937,
     /* 1000145 */     GIR_EraseRootFromParent_Done,
     /* 1000146 */   // Label 15849: @1000146
     /* 1000146 */   GIM_Try, /*On fail goto*//*Label 15850*/ GIMT_Encode4(1000211), // Rule ID 2938 //
     /* 1000151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /* 1000154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000166 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000174 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000178 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000182 */     // MIs[2] Operand 1
     /* 1000182 */     // No operand predicates
     /* 1000182 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000186 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000188 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000195 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1000209 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000210 */     // GIR_Coverage, 2938,
     /* 1000210 */     GIR_EraseRootFromParent_Done,
     /* 1000211 */   // Label 15850: @1000211
     /* 1000211 */   GIM_Try, /*On fail goto*//*Label 15851*/ GIMT_Encode4(1000276), // Rule ID 2939 //
     /* 1000216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /* 1000219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000239 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000243 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000247 */     // MIs[2] Operand 1
     /* 1000247 */     // No operand predicates
     /* 1000247 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000251 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000253 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000260 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000270 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1000274 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000275 */     // GIR_Coverage, 2939,
     /* 1000275 */     GIR_EraseRootFromParent_Done,
     /* 1000276 */   // Label 15851: @1000276
     /* 1000276 */   GIM_Try, /*On fail goto*//*Label 15852*/ GIMT_Encode4(1000341), // Rule ID 2940 //
     /* 1000281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /* 1000284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000288 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000292 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000296 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000300 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000304 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000308 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000312 */     // MIs[2] Operand 1
     /* 1000312 */     // No operand predicates
     /* 1000312 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000316 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000318 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000325 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000330 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1000339 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000340 */     // GIR_Coverage, 2940,
     /* 1000340 */     GIR_EraseRootFromParent_Done,
     /* 1000341 */   // Label 15852: @1000341
     /* 1000341 */   GIM_Try, /*On fail goto*//*Label 15853*/ GIMT_Encode4(1000404), // Rule ID 2986 //
     /* 1000346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode0),
     /* 1000349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000353 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000357 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000361 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000365 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000369 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000373 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000377 */     // MIs[2] Operand 1
     /* 1000377 */     // No operand predicates
     /* 1000377 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000381 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000383 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000390 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000395 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000400 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000402 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000403 */     // GIR_Coverage, 2986,
     /* 1000403 */     GIR_EraseRootFromParent_Done,
     /* 1000404 */   // Label 15853: @1000404
     /* 1000404 */   GIM_Try, /*On fail goto*//*Label 15854*/ GIMT_Encode4(1000467), // Rule ID 2987 //
     /* 1000409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode1),
     /* 1000412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000416 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000420 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000424 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000428 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000432 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000436 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000440 */     // MIs[2] Operand 1
     /* 1000440 */     // No operand predicates
     /* 1000440 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000444 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000446 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000453 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000463 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000465 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000466 */     // GIR_Coverage, 2987,
     /* 1000466 */     GIR_EraseRootFromParent_Done,
     /* 1000467 */   // Label 15854: @1000467
     /* 1000467 */   GIM_Try, /*On fail goto*//*Label 15855*/ GIMT_Encode4(1000530), // Rule ID 2988 //
     /* 1000472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode2),
     /* 1000475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000487 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000491 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000495 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000499 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000503 */     // MIs[2] Operand 1
     /* 1000503 */     // No operand predicates
     /* 1000503 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000507 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000509 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000516 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000521 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000526 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000528 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000529 */     // GIR_Coverage, 2988,
     /* 1000529 */     GIR_EraseRootFromParent_Done,
     /* 1000530 */   // Label 15855: @1000530
     /* 1000530 */   GIM_Try, /*On fail goto*//*Label 15856*/ GIMT_Encode4(1000593), // Rule ID 2989 //
     /* 1000535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode3),
     /* 1000538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000542 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000546 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000550 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000554 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000558 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000562 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000566 */     // MIs[2] Operand 1
     /* 1000566 */     // No operand predicates
     /* 1000566 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000570 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000572 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000579 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000589 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000591 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000592 */     // GIR_Coverage, 2989,
     /* 1000592 */     GIR_EraseRootFromParent_Done,
     /* 1000593 */   // Label 15856: @1000593
     /* 1000593 */   GIM_Try, /*On fail goto*//*Label 15857*/ GIMT_Encode4(1000656), // Rule ID 2990 //
     /* 1000598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode4),
     /* 1000601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1000609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1000613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1000617 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1000621 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1000625 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1000629 */     // MIs[2] Operand 1
     /* 1000629 */     // No operand predicates
     /* 1000629 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1000633 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1000635 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000642 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000652 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000654 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000655 */     // GIR_Coverage, 2990,
     /* 1000655 */     GIR_EraseRootFromParent_Done,
     /* 1000656 */   // Label 15857: @1000656
     /* 1000656 */   GIM_Try, /*On fail goto*//*Label 15858*/ GIMT_Encode4(1000689), // Rule ID 2931 //
     /* 1000661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /* 1000664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000675 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000685 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1000687 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000688 */     // GIR_Coverage, 2931,
     /* 1000688 */     GIR_EraseRootFromParent_Done,
     /* 1000689 */   // Label 15858: @1000689
     /* 1000689 */   GIM_Try, /*On fail goto*//*Label 15859*/ GIMT_Encode4(1000722), // Rule ID 2932 //
     /* 1000694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /* 1000697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000701 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000708 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000718 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1000720 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000721 */     // GIR_Coverage, 2932,
     /* 1000721 */     GIR_EraseRootFromParent_Done,
     /* 1000722 */   // Label 15859: @1000722
     /* 1000722 */   GIM_Try, /*On fail goto*//*Label 15860*/ GIMT_Encode4(1000755), // Rule ID 2933 //
     /* 1000727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /* 1000730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000734 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000741 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000751 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1000753 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000754 */     // GIR_Coverage, 2933,
     /* 1000754 */     GIR_EraseRootFromParent_Done,
     /* 1000755 */   // Label 15860: @1000755
     /* 1000755 */   GIM_Try, /*On fail goto*//*Label 15861*/ GIMT_Encode4(1000788), // Rule ID 2934 //
     /* 1000760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /* 1000763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000774 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000784 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1000786 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000787 */     // GIR_Coverage, 2934,
     /* 1000787 */     GIR_EraseRootFromParent_Done,
     /* 1000788 */   // Label 15861: @1000788
     /* 1000788 */   GIM_Try, /*On fail goto*//*Label 15862*/ GIMT_Encode4(1000821), // Rule ID 2935 //
     /* 1000793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /* 1000796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000800 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000807 */     // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1000807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
     /* 1000810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000812 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000817 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1000819 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000820 */     // GIR_Coverage, 2935,
     /* 1000820 */     GIR_EraseRootFromParent_Done,
     /* 1000821 */   // Label 15862: @1000821
     /* 1000821 */   GIM_Try, /*On fail goto*//*Label 15863*/ GIMT_Encode4(1000854), // Rule ID 2981 //
     /* 1000826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode0),
     /* 1000829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000840 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000850 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000852 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000853 */     // GIR_Coverage, 2981,
     /* 1000853 */     GIR_EraseRootFromParent_Done,
     /* 1000854 */   // Label 15863: @1000854
     /* 1000854 */   GIM_Try, /*On fail goto*//*Label 15864*/ GIMT_Encode4(1000887), // Rule ID 2982 //
     /* 1000859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode1),
     /* 1000862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000873 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000883 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000885 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000886 */     // GIR_Coverage, 2982,
     /* 1000886 */     GIR_EraseRootFromParent_Done,
     /* 1000887 */   // Label 15864: @1000887
     /* 1000887 */   GIM_Try, /*On fail goto*//*Label 15865*/ GIMT_Encode4(1000920), // Rule ID 2983 //
     /* 1000892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode2),
     /* 1000895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000899 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000906 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000916 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000918 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000919 */     // GIR_Coverage, 2983,
     /* 1000919 */     GIR_EraseRootFromParent_Done,
     /* 1000920 */   // Label 15865: @1000920
     /* 1000920 */   GIM_Try, /*On fail goto*//*Label 15866*/ GIMT_Encode4(1000953), // Rule ID 2984 //
     /* 1000925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode3),
     /* 1000928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000932 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000939 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000944 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000949 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000951 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000952 */     // GIR_Coverage, 2984,
     /* 1000952 */     GIR_EraseRootFromParent_Done,
     /* 1000953 */   // Label 15866: @1000953
     /* 1000953 */   GIM_Try, /*On fail goto*//*Label 15867*/ GIMT_Encode4(1000986), // Rule ID 2985 //
     /* 1000958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11_HwMode4),
     /* 1000961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000965 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1000972 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1000972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
     /* 1000975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1000977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1000982 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1000984 */     GIR_RootConstrainSelectedInstOperands,
     /* 1000985 */     // GIR_Coverage, 2985,
     /* 1000985 */     GIR_EraseRootFromParent_Done,
     /* 1000986 */   // Label 15867: @1000986
     /* 1000986 */   GIM_Try, /*On fail goto*//*Label 15868*/ GIMT_Encode4(1001041), // Rule ID 2756 //
     /* 1000991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode0),
     /* 1000994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1000998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001006 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1001010 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1001014 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001018 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001022 */     // MIs[2] Operand 1
     /* 1001022 */     // No operand predicates
     /* 1001022 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1001026 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001028 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001033 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001037 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001039 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001040 */     // GIR_Coverage, 2756,
     /* 1001040 */     GIR_EraseRootFromParent_Done,
     /* 1001041 */   // Label 15868: @1001041
     /* 1001041 */   GIM_Try, /*On fail goto*//*Label 15869*/ GIMT_Encode4(1001096), // Rule ID 2757 //
     /* 1001046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode1),
     /* 1001049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1001065 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1001069 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001073 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001077 */     // MIs[2] Operand 1
     /* 1001077 */     // No operand predicates
     /* 1001077 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1001081 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001083 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001088 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001092 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001094 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001095 */     // GIR_Coverage, 2757,
     /* 1001095 */     GIR_EraseRootFromParent_Done,
     /* 1001096 */   // Label 15869: @1001096
     /* 1001096 */   GIM_Try, /*On fail goto*//*Label 15870*/ GIMT_Encode4(1001151), // Rule ID 2758 //
     /* 1001101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode2),
     /* 1001104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001108 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001112 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001116 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1001120 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1001124 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001128 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001132 */     // MIs[2] Operand 1
     /* 1001132 */     // No operand predicates
     /* 1001132 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1001136 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001138 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001147 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001149 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001150 */     // GIR_Coverage, 2758,
     /* 1001150 */     GIR_EraseRootFromParent_Done,
     /* 1001151 */   // Label 15870: @1001151
     /* 1001151 */   GIM_Try, /*On fail goto*//*Label 15871*/ GIMT_Encode4(1001206), // Rule ID 2759 //
     /* 1001156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode3),
     /* 1001159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1001175 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1001179 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001183 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001187 */     // MIs[2] Operand 1
     /* 1001187 */     // No operand predicates
     /* 1001187 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1001191 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001193 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001202 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001204 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001205 */     // GIR_Coverage, 2759,
     /* 1001205 */     GIR_EraseRootFromParent_Done,
     /* 1001206 */   // Label 15871: @1001206
     /* 1001206 */   GIM_Try, /*On fail goto*//*Label 15872*/ GIMT_Encode4(1001261), // Rule ID 2760 //
     /* 1001211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode4),
     /* 1001214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1001230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1001234 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001238 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001242 */     // MIs[2] Operand 1
     /* 1001242 */     // No operand predicates
     /* 1001242 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1001246 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001248 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001257 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001259 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001260 */     // GIR_Coverage, 2760,
     /* 1001260 */     GIR_EraseRootFromParent_Done,
     /* 1001261 */   // Label 15872: @1001261
     /* 1001261 */   GIM_Try, /*On fail goto*//*Label 15873*/ GIMT_Encode4(1001284), // Rule ID 2751 //
     /* 1001266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode0),
     /* 1001269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001273 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001278 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1001280 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001282 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001283 */     // GIR_Coverage, 2751,
     /* 1001283 */     GIR_EraseRootFromParent_Done,
     /* 1001284 */   // Label 15873: @1001284
     /* 1001284 */   GIM_Try, /*On fail goto*//*Label 15874*/ GIMT_Encode4(1001307), // Rule ID 2752 //
     /* 1001289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode1),
     /* 1001292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001296 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001301 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1001303 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001305 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001306 */     // GIR_Coverage, 2752,
     /* 1001306 */     GIR_EraseRootFromParent_Done,
     /* 1001307 */   // Label 15874: @1001307
     /* 1001307 */   GIM_Try, /*On fail goto*//*Label 15875*/ GIMT_Encode4(1001330), // Rule ID 2753 //
     /* 1001312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode2),
     /* 1001315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001319 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001324 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1001326 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001328 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001329 */     // GIR_Coverage, 2753,
     /* 1001329 */     GIR_EraseRootFromParent_Done,
     /* 1001330 */   // Label 15875: @1001330
     /* 1001330 */   GIM_Try, /*On fail goto*//*Label 15876*/ GIMT_Encode4(1001353), // Rule ID 2754 //
     /* 1001335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode3),
     /* 1001338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001342 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001347 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1001349 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001351 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001352 */     // GIR_Coverage, 2754,
     /* 1001352 */     GIR_EraseRootFromParent_Done,
     /* 1001353 */   // Label 15876: @1001353
     /* 1001353 */   GIM_Try, /*On fail goto*//*Label 15877*/ GIMT_Encode4(1001376), // Rule ID 2755 //
     /* 1001358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_HwMode4),
     /* 1001361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1001365 */     // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1001365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
     /* 1001368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001370 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1001372 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001374 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001375 */     // GIR_Coverage, 2755,
     /* 1001375 */     GIR_EraseRootFromParent_Done,
     /* 1001376 */   // Label 15877: @1001376
     /* 1001376 */   GIM_Reject,
     /* 1001377 */ // Label 15845: @1001377
     /* 1001377 */ GIM_Reject,
     /* 1001378 */ // Label 15821: @1001378
     /* 1001378 */ GIM_Try, /*On fail goto*//*Label 15878*/ GIMT_Encode4(1001546),
     /* 1001383 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 1001386 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 1001389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1001393 */   GIM_Try, /*On fail goto*//*Label 15879*/ GIMT_Encode4(1001484), // Rule ID 3328 //
     /* 1001398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 1001410 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 1001414 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001418 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001422 */     // MIs[2] Operand 1
     /* 1001422 */     // No operand predicates
     /* 1001422 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1001426 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1001435 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1001442 */     // (shl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_PK_LSHLREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /* 1001442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHLREV_B16),
     /* 1001445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001447 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1001452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1001457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1001462 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1001467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001470 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001473 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001476 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001479 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001482 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001483 */     // GIR_Coverage, 3328,
     /* 1001483 */     GIR_EraseRootFromParent_Done,
     /* 1001484 */   // Label 15879: @1001484
     /* 1001484 */   GIM_Try, /*On fail goto*//*Label 15880*/ GIMT_Encode4(1001545), // Rule ID 3327 //
     /* 1001489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1001496 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1001503 */     // (shl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_LSHLREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /* 1001503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHLREV_B16),
     /* 1001506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1001513 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1001518 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1001523 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1001528 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001531 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001534 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001537 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001540 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001543 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001544 */     // GIR_Coverage, 3327,
     /* 1001544 */     GIR_EraseRootFromParent_Done,
     /* 1001545 */   // Label 15880: @1001545
     /* 1001545 */   GIM_Reject,
     /* 1001546 */ // Label 15878: @1001546
     /* 1001546 */ GIM_Reject,
     /* 1001547 */ // Label 15822: @1001547
     /* 1001547 */ GIM_Reject,
     /* 1001548 */ // Label 49: @1001548
     /* 1001548 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 15885*/ GIMT_Encode4(1003633),
     /* 1001559 */ /*GILLT_s16*//*Label 15881*/ GIMT_Encode4(1001575),
     /* 1001563 */ /*GILLT_s32*//*Label 15882*/ GIMT_Encode4(1002034),
     /* 1001567 */ /*GILLT_s64*//*Label 15883*/ GIMT_Encode4(1002379),
     /* 1001571 */ /*GILLT_v2s16*//*Label 15884*/ GIMT_Encode4(1003464),
     /* 1001575 */ // Label 15881: @1001575
     /* 1001575 */ GIM_Try, /*On fail goto*//*Label 15886*/ GIMT_Encode4(1002033),
     /* 1001580 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 1001583 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 1001586 */   GIM_Try, /*On fail goto*//*Label 15887*/ GIMT_Encode4(1001675), // Rule ID 2664 //
     /* 1001591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /* 1001594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1001598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1001610 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1001614 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001618 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001622 */     // MIs[2] Operand 1
     /* 1001622 */     // No operand predicates
     /* 1001622 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1001626 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1001635 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1001642 */     // (srl:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHRREV_B16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1001642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_opsel_e64),
     /* 1001645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1001652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1001657 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1001662 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1001667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001670 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001673 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001674 */     // GIR_Coverage, 2664,
     /* 1001674 */     GIR_EraseRootFromParent_Done,
     /* 1001675 */   // Label 15887: @1001675
     /* 1001675 */   GIM_Try, /*On fail goto*//*Label 15888*/ GIMT_Encode4(1001761), // Rule ID 2666 //
     /* 1001680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /* 1001683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /* 1001687 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001691 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001695 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1001699 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1001703 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001707 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001711 */     // MIs[2] Operand 1
     /* 1001711 */     // No operand predicates
     /* 1001711 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1001715 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001717 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1001724 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1001731 */     // (srl:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHRREV_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1001731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_t16_e64),
     /* 1001734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1001741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1001746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1001751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1001756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001759 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001760 */     // GIR_Coverage, 2666,
     /* 1001760 */     GIR_EraseRootFromParent_Done,
     /* 1001761 */   // Label 15888: @1001761
     /* 1001761 */   GIM_Try, /*On fail goto*//*Label 15889*/ GIMT_Encode4(1001820), // Rule ID 2663 //
     /* 1001766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /* 1001769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1001773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1001780 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1001787 */     // (srl:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_LSHRREV_B16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1001787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_opsel_e64),
     /* 1001790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001792 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1001797 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1001802 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1001807 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1001812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001815 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001818 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001819 */     // GIR_Coverage, 2663,
     /* 1001819 */     GIR_EraseRootFromParent_Done,
     /* 1001820 */   // Label 15889: @1001820
     /* 1001820 */   GIM_Try, /*On fail goto*//*Label 15890*/ GIMT_Encode4(1001876), // Rule ID 2665 //
     /* 1001825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /* 1001828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /* 1001832 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1001839 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1001846 */     // (srl:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_LSHRREV_B16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1001846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_t16_e64),
     /* 1001849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1001856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1001861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1001866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1001871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1001874 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001875 */     // GIR_Coverage, 2665,
     /* 1001875 */     GIR_EraseRootFromParent_Done,
     /* 1001876 */   // Label 15890: @1001876
     /* 1001876 */   GIM_Try, /*On fail goto*//*Label 15891*/ GIMT_Encode4(1001931), // Rule ID 2662 //
     /* 1001881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /* 1001884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1001888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001896 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1001900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1001904 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001908 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001912 */     // MIs[2] Operand 1
     /* 1001912 */     // No operand predicates
     /* 1001912 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1001916 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001918 */     // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHRREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1001918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
     /* 1001921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001927 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001929 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001930 */     // GIR_Coverage, 2662,
     /* 1001930 */     GIR_EraseRootFromParent_Done,
     /* 1001931 */   // Label 15891: @1001931
     /* 1001931 */   GIM_Try, /*On fail goto*//*Label 15892*/ GIMT_Encode4(1001986), // Rule ID 2668 //
     /* 1001936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /* 1001939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1001943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1001947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1001951 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1001955 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1001959 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1001963 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1001967 */     // MIs[2] Operand 1
     /* 1001967 */     // No operand predicates
     /* 1001967 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1001971 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1001973 */     // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHRREV_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1001973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_fake16_e64),
     /* 1001976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1001978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1001982 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1001984 */     GIR_RootConstrainSelectedInstOperands,
     /* 1001985 */     // GIR_Coverage, 2668,
     /* 1001985 */     GIR_EraseRootFromParent_Done,
     /* 1001986 */   // Label 15892: @1001986
     /* 1001986 */   GIM_Try, /*On fail goto*//*Label 15893*/ GIMT_Encode4(1002009), // Rule ID 2661 //
     /* 1001991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /* 1001994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1001998 */     // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHRREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1001998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
     /* 1002001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002003 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1002005 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1002007 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002008 */     // GIR_Coverage, 2661,
     /* 1002008 */     GIR_EraseRootFromParent_Done,
     /* 1002009 */   // Label 15893: @1002009
     /* 1002009 */   GIM_Try, /*On fail goto*//*Label 15894*/ GIMT_Encode4(1002032), // Rule ID 2667 //
     /* 1002014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /* 1002017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002021 */     // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHRREV_B16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1002021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_fake16_e64),
     /* 1002024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002026 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1002028 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1002030 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002031 */     // GIR_Coverage, 2667,
     /* 1002031 */     GIR_EraseRootFromParent_Done,
     /* 1002032 */   // Label 15894: @1002032
     /* 1002032 */   GIM_Reject,
     /* 1002033 */ // Label 15886: @1002033
     /* 1002033 */ GIM_Reject,
     /* 1002034 */ // Label 15882: @1002034
     /* 1002034 */ GIM_Try, /*On fail goto*//*Label 15895*/ GIMT_Encode4(1002378),
     /* 1002039 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002042 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002045 */   GIM_Try, /*On fail goto*//*Label 15896*/ GIMT_Encode4(1002113), // Rule ID 73 //
     /* 1002050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002054 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002058 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002062 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002066 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002070 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002074 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002079 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002083 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002087 */     // MIs[2] Operand 1
     /* 1002087 */     // No operand predicates
     /* 1002087 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1002091 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20785),
     /* 1002095 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002097 */     // (srl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_20785>>  =>  (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1002097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B32),
     /* 1002100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1002102 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1002104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002108 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /* 1002111 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002112 */     // GIR_Coverage, 73,
     /* 1002112 */     GIR_EraseRootFromParent_Done,
     /* 1002113 */   // Label 15896: @1002113
     /* 1002113 */   GIM_Try, /*On fail goto*//*Label 15897*/ GIMT_Encode4(1002169), // Rule ID 7116 //
     /* 1002118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002134 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002138 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002142 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002146 */     // MIs[2] Operand 1
     /* 1002146 */     // No operand predicates
     /* 1002146 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1002150 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27126),
     /* 1002154 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002156 */     // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_27126>>  =>  (V_LSHRREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
     /* 1002156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
     /* 1002159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002161 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002165 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1002167 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002168 */     // GIR_Coverage, 7116,
     /* 1002168 */     GIR_EraseRootFromParent_Done,
     /* 1002169 */   // Label 15897: @1002169
     /* 1002169 */   GIM_Try, /*On fail goto*//*Label 15898*/ GIMT_Encode4(1002203), // Rule ID 72 //
     /* 1002174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002178 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002182 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002186 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20785),
     /* 1002190 */     // (srl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20785>>  =>  (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1002190 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B32),
     /* 1002195 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /* 1002201 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002202 */     // GIR_Coverage, 72,
     /* 1002202 */     GIR_Done,
     /* 1002203 */   // Label 15898: @1002203
     /* 1002203 */   GIM_Try, /*On fail goto*//*Label 15899*/ GIMT_Encode4(1002227), // Rule ID 7115 //
     /* 1002208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002212 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27126),
     /* 1002216 */     // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27126>>  =>  (V_LSHRREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
     /* 1002216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
     /* 1002219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002221 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1002223 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1002225 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002226 */     // GIR_Coverage, 7115,
     /* 1002226 */     GIR_EraseRootFromParent_Done,
     /* 1002227 */   // Label 15899: @1002227
     /* 1002227 */   GIM_Try, /*On fail goto*//*Label 15900*/ GIMT_Encode4(1002279), // Rule ID 2617 //
     /* 1002232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002236 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002240 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002244 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002248 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002252 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002256 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002260 */     // MIs[2] Operand 1
     /* 1002260 */     // No operand predicates
     /* 1002260 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1002264 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002266 */     // (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHRREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
     /* 1002269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002271 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1002275 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1002277 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002278 */     // GIR_Coverage, 2617,
     /* 1002278 */     GIR_EraseRootFromParent_Done,
     /* 1002279 */   // Label 15900: @1002279
     /* 1002279 */   GIM_Try, /*On fail goto*//*Label 15901*/ GIMT_Encode4(1002334), // Rule ID 2648 //
     /* 1002284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /* 1002287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002291 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002295 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002299 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002303 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002307 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002311 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002315 */     // MIs[2] Operand 1
     /* 1002315 */     // No operand predicates
     /* 1002315 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1002319 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002321 */     // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B32_e64),
     /* 1002324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002326 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1002328 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002332 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002333 */     // GIR_Coverage, 2648,
     /* 1002333 */     GIR_EraseRootFromParent_Done,
     /* 1002334 */   // Label 15901: @1002334
     /* 1002334 */   GIM_Try, /*On fail goto*//*Label 15902*/ GIMT_Encode4(1002354), // Rule ID 2616 //
     /* 1002339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002343 */     // (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHRREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
     /* 1002346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002348 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1002350 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1002352 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002353 */     // GIR_Coverage, 2616,
     /* 1002353 */     GIR_EraseRootFromParent_Done,
     /* 1002354 */   // Label 15902: @1002354
     /* 1002354 */   GIM_Try, /*On fail goto*//*Label 15903*/ GIMT_Encode4(1002377), // Rule ID 2647 //
     /* 1002359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /* 1002362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1002366 */     // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002366 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B32_e64),
     /* 1002371 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /* 1002375 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002376 */     // GIR_Coverage, 2647,
     /* 1002376 */     GIR_Done,
     /* 1002377 */   // Label 15903: @1002377
     /* 1002377 */   GIM_Reject,
     /* 1002378 */ // Label 15895: @1002378
     /* 1002378 */ GIM_Reject,
     /* 1002379 */ // Label 15883: @1002379
     /* 1002379 */ GIM_Try, /*On fail goto*//*Label 15904*/ GIMT_Encode4(1003463),
     /* 1002384 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 1002387 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002390 */   GIM_Try, /*On fail goto*//*Label 15905*/ GIMT_Encode4(1002458), // Rule ID 75 //
     /* 1002395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1002399 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_EncodableRegClassID),
     /* 1002403 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002407 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002411 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002415 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002419 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002424 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002428 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002432 */     // MIs[2] Operand 1
     /* 1002432 */     // No operand predicates
     /* 1002432 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002436 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20786),
     /* 1002440 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002442 */     // (srl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_20786>>  =>  (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1002442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64),
     /* 1002445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1002447 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1002449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002453 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /* 1002456 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002457 */     // GIR_Coverage, 75,
     /* 1002457 */     GIR_EraseRootFromParent_Done,
     /* 1002458 */   // Label 15905: @1002458
     /* 1002458 */   GIM_Try, /*On fail goto*//*Label 15906*/ GIMT_Encode4(1002492), // Rule ID 74 //
     /* 1002463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1002467 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_EncodableRegClassID),
     /* 1002471 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1002475 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20786),
     /* 1002479 */     // (srl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20786>>  =>  (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1002479 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64),
     /* 1002484 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /* 1002490 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002491 */     // GIR_Coverage, 74,
     /* 1002491 */     GIR_Done,
     /* 1002492 */   // Label 15906: @1002492
     /* 1002492 */   GIM_Try, /*On fail goto*//*Label 15907*/ GIMT_Encode4(1002557), // Rule ID 2946 //
     /* 1002497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /* 1002500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002516 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002520 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002524 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002528 */     // MIs[2] Operand 1
     /* 1002528 */     // No operand predicates
     /* 1002528 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002532 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002534 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002541 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1002544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002551 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002555 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002556 */     // GIR_Coverage, 2946,
     /* 1002556 */     GIR_EraseRootFromParent_Done,
     /* 1002557 */   // Label 15907: @1002557
     /* 1002557 */   GIM_Try, /*On fail goto*//*Label 15908*/ GIMT_Encode4(1002622), // Rule ID 2947 //
     /* 1002562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /* 1002565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002577 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002581 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002585 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002589 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002593 */     // MIs[2] Operand 1
     /* 1002593 */     // No operand predicates
     /* 1002593 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002597 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002599 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002606 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1002609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002620 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002621 */     // GIR_Coverage, 2947,
     /* 1002621 */     GIR_EraseRootFromParent_Done,
     /* 1002622 */   // Label 15908: @1002622
     /* 1002622 */   GIM_Try, /*On fail goto*//*Label 15909*/ GIMT_Encode4(1002687), // Rule ID 2948 //
     /* 1002627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /* 1002630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002634 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002638 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002642 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002646 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002650 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002654 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002658 */     // MIs[2] Operand 1
     /* 1002658 */     // No operand predicates
     /* 1002658 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002662 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002664 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002671 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1002674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002685 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002686 */     // GIR_Coverage, 2948,
     /* 1002686 */     GIR_EraseRootFromParent_Done,
     /* 1002687 */   // Label 15909: @1002687
     /* 1002687 */   GIM_Try, /*On fail goto*//*Label 15910*/ GIMT_Encode4(1002752), // Rule ID 2949 //
     /* 1002692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /* 1002695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002703 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002707 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002711 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002715 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002719 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002723 */     // MIs[2] Operand 1
     /* 1002723 */     // No operand predicates
     /* 1002723 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002727 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002729 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002736 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1002739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002741 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002750 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002751 */     // GIR_Coverage, 2949,
     /* 1002751 */     GIR_EraseRootFromParent_Done,
     /* 1002752 */   // Label 15910: @1002752
     /* 1002752 */   GIM_Try, /*On fail goto*//*Label 15911*/ GIMT_Encode4(1002817), // Rule ID 2950 //
     /* 1002757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /* 1002760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002764 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002768 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002772 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002776 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002780 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002784 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002788 */     // MIs[2] Operand 1
     /* 1002788 */     // No operand predicates
     /* 1002788 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002792 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002794 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002801 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1002801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1002804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1002815 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002816 */     // GIR_Coverage, 2950,
     /* 1002816 */     GIR_EraseRootFromParent_Done,
     /* 1002817 */   // Label 15911: @1002817
     /* 1002817 */   GIM_Try, /*On fail goto*//*Label 15912*/ GIMT_Encode4(1002880), // Rule ID 2966 //
     /* 1002822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode0),
     /* 1002825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002837 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002841 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002845 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002849 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002853 */     // MIs[2] Operand 1
     /* 1002853 */     // No operand predicates
     /* 1002853 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002857 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002859 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002866 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1002866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1002869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002871 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002876 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1002878 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002879 */     // GIR_Coverage, 2966,
     /* 1002879 */     GIR_EraseRootFromParent_Done,
     /* 1002880 */   // Label 15912: @1002880
     /* 1002880 */   GIM_Try, /*On fail goto*//*Label 15913*/ GIMT_Encode4(1002943), // Rule ID 2967 //
     /* 1002885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode1),
     /* 1002888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002892 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002896 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002900 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002904 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002908 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002912 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002916 */     // MIs[2] Operand 1
     /* 1002916 */     // No operand predicates
     /* 1002916 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002920 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002922 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002929 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1002929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1002932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002934 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1002939 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1002941 */     GIR_RootConstrainSelectedInstOperands,
     /* 1002942 */     // GIR_Coverage, 2967,
     /* 1002942 */     GIR_EraseRootFromParent_Done,
     /* 1002943 */   // Label 15913: @1002943
     /* 1002943 */   GIM_Try, /*On fail goto*//*Label 15914*/ GIMT_Encode4(1003006), // Rule ID 2968 //
     /* 1002948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode2),
     /* 1002951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1002955 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1002959 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1002963 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1002967 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1002971 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1002975 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1002979 */     // MIs[2] Operand 1
     /* 1002979 */     // No operand predicates
     /* 1002979 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1002983 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1002985 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1002992 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1002992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1002995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1002997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003002 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003004 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003005 */     // GIR_Coverage, 2968,
     /* 1003005 */     GIR_EraseRootFromParent_Done,
     /* 1003006 */   // Label 15914: @1003006
     /* 1003006 */   GIM_Try, /*On fail goto*//*Label 15915*/ GIMT_Encode4(1003069), // Rule ID 2969 //
     /* 1003011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode3),
     /* 1003014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003018 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1003022 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1003026 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1003030 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1003034 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1003038 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1003042 */     // MIs[2] Operand 1
     /* 1003042 */     // No operand predicates
     /* 1003042 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1003046 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1003048 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003055 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003060 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003065 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003067 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003068 */     // GIR_Coverage, 2969,
     /* 1003068 */     GIR_EraseRootFromParent_Done,
     /* 1003069 */   // Label 15915: @1003069
     /* 1003069 */   GIM_Try, /*On fail goto*//*Label 15916*/ GIMT_Encode4(1003132), // Rule ID 2970 //
     /* 1003074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode4),
     /* 1003077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003081 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1003085 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1003089 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1003093 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1003097 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1003101 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1003105 */     // MIs[2] Operand 1
     /* 1003105 */     // No operand predicates
     /* 1003105 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1003109 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1003111 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003118 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003123 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003128 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003130 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003131 */     // GIR_Coverage, 2970,
     /* 1003131 */     GIR_EraseRootFromParent_Done,
     /* 1003132 */   // Label 15916: @1003132
     /* 1003132 */   GIM_Try, /*On fail goto*//*Label 15917*/ GIMT_Encode4(1003165), // Rule ID 2941 //
     /* 1003137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /* 1003140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003144 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003151 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1003151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1003154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003156 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003161 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1003163 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003164 */     // GIR_Coverage, 2941,
     /* 1003164 */     GIR_EraseRootFromParent_Done,
     /* 1003165 */   // Label 15917: @1003165
     /* 1003165 */   GIM_Try, /*On fail goto*//*Label 15918*/ GIMT_Encode4(1003198), // Rule ID 2942 //
     /* 1003170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /* 1003173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003177 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003184 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1003184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1003187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003194 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1003196 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003197 */     // GIR_Coverage, 2942,
     /* 1003197 */     GIR_EraseRootFromParent_Done,
     /* 1003198 */   // Label 15918: @1003198
     /* 1003198 */   GIM_Try, /*On fail goto*//*Label 15919*/ GIMT_Encode4(1003231), // Rule ID 2943 //
     /* 1003203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /* 1003206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003217 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1003217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1003220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003227 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1003229 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003230 */     // GIR_Coverage, 2943,
     /* 1003230 */     GIR_EraseRootFromParent_Done,
     /* 1003231 */   // Label 15919: @1003231
     /* 1003231 */   GIM_Try, /*On fail goto*//*Label 15920*/ GIMT_Encode4(1003264), // Rule ID 2944 //
     /* 1003236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /* 1003239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003243 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003250 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1003250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1003253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003255 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003260 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1003262 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003263 */     // GIR_Coverage, 2944,
     /* 1003263 */     GIR_EraseRootFromParent_Done,
     /* 1003264 */   // Label 15920: @1003264
     /* 1003264 */   GIM_Try, /*On fail goto*//*Label 15921*/ GIMT_Encode4(1003297), // Rule ID 2945 //
     /* 1003269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /* 1003272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003283 */     // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1003283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
     /* 1003286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003293 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1003295 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003296 */     // GIR_Coverage, 2945,
     /* 1003296 */     GIR_EraseRootFromParent_Done,
     /* 1003297 */   // Label 15921: @1003297
     /* 1003297 */   GIM_Try, /*On fail goto*//*Label 15922*/ GIMT_Encode4(1003330), // Rule ID 2961 //
     /* 1003302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode0),
     /* 1003305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003309 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003316 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003326 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003328 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003329 */     // GIR_Coverage, 2961,
     /* 1003329 */     GIR_EraseRootFromParent_Done,
     /* 1003330 */   // Label 15922: @1003330
     /* 1003330 */   GIM_Try, /*On fail goto*//*Label 15923*/ GIMT_Encode4(1003363), // Rule ID 2962 //
     /* 1003335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode1),
     /* 1003338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003342 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003349 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003359 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003361 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003362 */     // GIR_Coverage, 2962,
     /* 1003362 */     GIR_EraseRootFromParent_Done,
     /* 1003363 */   // Label 15923: @1003363
     /* 1003363 */   GIM_Try, /*On fail goto*//*Label 15924*/ GIMT_Encode4(1003396), // Rule ID 2963 //
     /* 1003368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode2),
     /* 1003371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003375 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003382 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003392 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003394 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003395 */     // GIR_Coverage, 2963,
     /* 1003395 */     GIR_EraseRootFromParent_Done,
     /* 1003396 */   // Label 15924: @1003396
     /* 1003396 */   GIM_Try, /*On fail goto*//*Label 15925*/ GIMT_Encode4(1003429), // Rule ID 2964 //
     /* 1003401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode3),
     /* 1003404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003415 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003425 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003427 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003428 */     // GIR_Coverage, 2964,
     /* 1003428 */     GIR_EraseRootFromParent_Done,
     /* 1003429 */   // Label 15925: @1003429
     /* 1003429 */   GIM_Try, /*On fail goto*//*Label 15926*/ GIMT_Encode4(1003462), // Rule ID 2965 //
     /* 1003434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode4),
     /* 1003437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1003441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1003448 */     // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1003448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
     /* 1003451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1003458 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1003460 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003461 */     // GIR_Coverage, 2965,
     /* 1003461 */     GIR_EraseRootFromParent_Done,
     /* 1003462 */   // Label 15926: @1003462
     /* 1003462 */   GIM_Reject,
     /* 1003463 */ // Label 15904: @1003463
     /* 1003463 */ GIM_Reject,
     /* 1003464 */ // Label 15884: @1003464
     /* 1003464 */ GIM_Try, /*On fail goto*//*Label 15927*/ GIMT_Encode4(1003632),
     /* 1003469 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 1003472 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 1003475 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1003479 */   GIM_Try, /*On fail goto*//*Label 15928*/ GIMT_Encode4(1003570), // Rule ID 3332 //
     /* 1003484 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1003488 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1003492 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 1003496 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 1003500 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1003504 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1003508 */     // MIs[2] Operand 1
     /* 1003508 */     // No operand predicates
     /* 1003508 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1003512 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1003514 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1003521 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1003528 */     // (srl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_PK_LSHRREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /* 1003528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHRREV_B16),
     /* 1003531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003533 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1003538 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1003543 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1003548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1003553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003559 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003565 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003568 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003569 */     // GIR_Coverage, 3332,
     /* 1003569 */     GIR_EraseRootFromParent_Done,
     /* 1003570 */   // Label 15928: @1003570
     /* 1003570 */   GIM_Try, /*On fail goto*//*Label 15929*/ GIMT_Encode4(1003631), // Rule ID 3331 //
     /* 1003575 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1003582 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1003589 */     // (srl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_LSHRREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /* 1003589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHRREV_B16),
     /* 1003592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1003599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1003604 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1003609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1003614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003617 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003623 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003629 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003630 */     // GIR_Coverage, 3331,
     /* 1003630 */     GIR_EraseRootFromParent_Done,
     /* 1003631 */   // Label 15929: @1003631
     /* 1003631 */   GIM_Reject,
     /* 1003632 */ // Label 15927: @1003632
     /* 1003632 */ GIM_Reject,
     /* 1003633 */ // Label 15885: @1003633
     /* 1003633 */ GIM_Reject,
     /* 1003634 */ // Label 50: @1003634
     /* 1003634 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 15934*/ GIMT_Encode4(1005719),
     /* 1003645 */ /*GILLT_s16*//*Label 15930*/ GIMT_Encode4(1003661),
     /* 1003649 */ /*GILLT_s32*//*Label 15931*/ GIMT_Encode4(1004120),
     /* 1003653 */ /*GILLT_s64*//*Label 15932*/ GIMT_Encode4(1004465),
     /* 1003657 */ /*GILLT_v2s16*//*Label 15933*/ GIMT_Encode4(1005550),
     /* 1003661 */ // Label 15930: @1003661
     /* 1003661 */ GIM_Try, /*On fail goto*//*Label 15935*/ GIMT_Encode4(1004119),
     /* 1003666 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 1003669 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 1003672 */   GIM_Try, /*On fail goto*//*Label 15936*/ GIMT_Encode4(1003761), // Rule ID 2672 //
     /* 1003677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /* 1003680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1003684 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1003688 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1003692 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1003696 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1003700 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1003704 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1003708 */     // MIs[2] Operand 1
     /* 1003708 */     // No operand predicates
     /* 1003708 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1003712 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1003714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1003721 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1003728 */     // (sra:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_ASHRREV_I16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1003728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_opsel_e64),
     /* 1003731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003733 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1003738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1003743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1003748 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1003753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003759 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003760 */     // GIR_Coverage, 2672,
     /* 1003760 */     GIR_EraseRootFromParent_Done,
     /* 1003761 */   // Label 15936: @1003761
     /* 1003761 */   GIM_Try, /*On fail goto*//*Label 15937*/ GIMT_Encode4(1003847), // Rule ID 2674 //
     /* 1003766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /* 1003769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /* 1003773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1003777 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1003781 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1003785 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1003789 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1003793 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1003797 */     // MIs[2] Operand 1
     /* 1003797 */     // No operand predicates
     /* 1003797 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1003801 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1003803 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1003810 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1003817 */     // (sra:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_ASHRREV_I16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1003817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_t16_e64),
     /* 1003820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003822 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1003827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1003832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1003837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1003842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003845 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003846 */     // GIR_Coverage, 2674,
     /* 1003846 */     GIR_EraseRootFromParent_Done,
     /* 1003847 */   // Label 15937: @1003847
     /* 1003847 */   GIM_Try, /*On fail goto*//*Label 15938*/ GIMT_Encode4(1003906), // Rule ID 2671 //
     /* 1003852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts_isGFX10Only),
     /* 1003855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1003859 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1003866 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
     /* 1003873 */     // (sra:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_ASHRREV_I16_opsel_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1003873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_opsel_e64),
     /* 1003876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003878 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1003883 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1003888 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1003893 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1003898 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003901 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003904 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003905 */     // GIR_Coverage, 2671,
     /* 1003905 */     GIR_EraseRootFromParent_Done,
     /* 1003906 */   // Label 15938: @1003906
     /* 1003906 */   GIM_Try, /*On fail goto*//*Label 15939*/ GIMT_Encode4(1003962), // Rule ID 2673 //
     /* 1003911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /* 1003914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /* 1003918 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1003925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1003932 */     // (sra:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_ASHRREV_I16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1003932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_t16_e64),
     /* 1003935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1003937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1003942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1003947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1003952 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1003957 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1003960 */     GIR_RootConstrainSelectedInstOperands,
     /* 1003961 */     // GIR_Coverage, 2673,
     /* 1003961 */     GIR_EraseRootFromParent_Done,
     /* 1003962 */   // Label 15939: @1003962
     /* 1003962 */   GIM_Try, /*On fail goto*//*Label 15940*/ GIMT_Encode4(1004017), // Rule ID 2670 //
     /* 1003967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /* 1003970 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1003974 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1003978 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1003982 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1003986 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1003990 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1003994 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1003998 */     // MIs[2] Operand 1
     /* 1003998 */     // No operand predicates
     /* 1003998 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1004002 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004004 */     // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_ASHRREV_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1004004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
     /* 1004007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004009 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1004013 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004015 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004016 */     // GIR_Coverage, 2670,
     /* 1004016 */     GIR_EraseRootFromParent_Done,
     /* 1004017 */   // Label 15940: @1004017
     /* 1004017 */   GIM_Try, /*On fail goto*//*Label 15941*/ GIMT_Encode4(1004072), // Rule ID 2676 //
     /* 1004022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /* 1004025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 1004041 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 1004045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004049 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004053 */     // MIs[2] Operand 1
     /* 1004053 */     // No operand predicates
     /* 1004053 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1004057 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004059 */     // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_ASHRREV_I16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1004059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_fake16_e64),
     /* 1004062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1004068 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004070 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004071 */     // GIR_Coverage, 2676,
     /* 1004071 */     GIR_EraseRootFromParent_Done,
     /* 1004072 */   // Label 15941: @1004072
     /* 1004072 */   GIM_Try, /*On fail goto*//*Label 15942*/ GIMT_Encode4(1004095), // Rule ID 2669 //
     /* 1004077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
     /* 1004080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004084 */     // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_ASHRREV_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1004084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
     /* 1004087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004089 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1004091 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004093 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004094 */     // GIR_Coverage, 2669,
     /* 1004094 */     GIR_EraseRootFromParent_Done,
     /* 1004095 */   // Label 15942: @1004095
     /* 1004095 */   GIM_Try, /*On fail goto*//*Label 15943*/ GIMT_Encode4(1004118), // Rule ID 2675 //
     /* 1004100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /* 1004103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004107 */     // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_ASHRREV_I16_fake16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
     /* 1004107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_fake16_e64),
     /* 1004110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004112 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1004114 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004116 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004117 */     // GIR_Coverage, 2675,
     /* 1004117 */     GIR_EraseRootFromParent_Done,
     /* 1004118 */   // Label 15943: @1004118
     /* 1004118 */   GIM_Reject,
     /* 1004119 */ // Label 15935: @1004119
     /* 1004119 */ GIM_Reject,
     /* 1004120 */ // Label 15931: @1004120
     /* 1004120 */ GIM_Try, /*On fail goto*//*Label 15944*/ GIMT_Encode4(1004464),
     /* 1004125 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004128 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004131 */   GIM_Try, /*On fail goto*//*Label 15945*/ GIMT_Encode4(1004199), // Rule ID 77 //
     /* 1004136 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004140 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004156 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004160 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004173 */     // MIs[2] Operand 1
     /* 1004173 */     // No operand predicates
     /* 1004173 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1004177 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20787),
     /* 1004181 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004183 */     // (sra:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_20787>>  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1004183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32),
     /* 1004186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1004188 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1004190 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004194 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /* 1004197 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004198 */     // GIR_Coverage, 77,
     /* 1004198 */     GIR_EraseRootFromParent_Done,
     /* 1004199 */   // Label 15945: @1004199
     /* 1004199 */   GIM_Try, /*On fail goto*//*Label 15946*/ GIMT_Encode4(1004255), // Rule ID 7118 //
     /* 1004204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004208 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004212 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004216 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004220 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004224 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004228 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004232 */     // MIs[2] Operand 1
     /* 1004232 */     // No operand predicates
     /* 1004232 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1004236 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27128),
     /* 1004240 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004242 */     // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_27128>>  =>  (V_ASHRREV_I32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
     /* 1004242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
     /* 1004245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004247 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004251 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1004253 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004254 */     // GIR_Coverage, 7118,
     /* 1004254 */     GIR_EraseRootFromParent_Done,
     /* 1004255 */   // Label 15946: @1004255
     /* 1004255 */   GIM_Try, /*On fail goto*//*Label 15947*/ GIMT_Encode4(1004289), // Rule ID 76 //
     /* 1004260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004264 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004268 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004272 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20787),
     /* 1004276 */     // (sra:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20787>>  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1004276 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32),
     /* 1004281 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /* 1004287 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004288 */     // GIR_Coverage, 76,
     /* 1004288 */     GIR_Done,
     /* 1004289 */   // Label 15947: @1004289
     /* 1004289 */   GIM_Try, /*On fail goto*//*Label 15948*/ GIMT_Encode4(1004313), // Rule ID 7117 //
     /* 1004294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004298 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_27128),
     /* 1004302 */     // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_27128>>  =>  (V_ASHRREV_I32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
     /* 1004302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
     /* 1004305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004307 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1004309 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1004311 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004312 */     // GIR_Coverage, 7117,
     /* 1004312 */     GIR_EraseRootFromParent_Done,
     /* 1004313 */   // Label 15948: @1004313
     /* 1004313 */   GIM_Try, /*On fail goto*//*Label 15949*/ GIMT_Encode4(1004365), // Rule ID 2619 //
     /* 1004318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004338 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004342 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004346 */     // MIs[2] Operand 1
     /* 1004346 */     // No operand predicates
     /* 1004346 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1004350 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004352 */     // (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
     /* 1004355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     /* 1004361 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004363 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004364 */     // GIR_Coverage, 2619,
     /* 1004364 */     GIR_EraseRootFromParent_Done,
     /* 1004365 */   // Label 15949: @1004365
     /* 1004365 */   GIM_Try, /*On fail goto*//*Label 15950*/ GIMT_Encode4(1004420), // Rule ID 2650 //
     /* 1004370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /* 1004373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004377 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004381 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004385 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004389 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004393 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004397 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004401 */     // MIs[2] Operand 1
     /* 1004401 */     // No operand predicates
     /* 1004401 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
     /* 1004405 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004407 */     // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I32_e64),
     /* 1004410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004412 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1004414 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004418 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004419 */     // GIR_Coverage, 2650,
     /* 1004419 */     GIR_EraseRootFromParent_Done,
     /* 1004420 */   // Label 15950: @1004420
     /* 1004420 */   GIM_Try, /*On fail goto*//*Label 15951*/ GIMT_Encode4(1004440), // Rule ID 2618 //
     /* 1004425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004429 */     // (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
     /* 1004432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004434 */     GIR_RootToRootCopy, /*OpIdx*/2, // src0
     /* 1004436 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004438 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004439 */     // GIR_Coverage, 2618,
     /* 1004439 */     GIR_EraseRootFromParent_Done,
     /* 1004440 */   // Label 15951: @1004440
     /* 1004440 */   GIM_Try, /*On fail goto*//*Label 15952*/ GIMT_Encode4(1004463), // Rule ID 2649 //
     /* 1004445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
     /* 1004448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1004452 */     // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004452 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I32_e64),
     /* 1004457 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
     /* 1004461 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004462 */     // GIR_Coverage, 2649,
     /* 1004462 */     GIR_Done,
     /* 1004463 */   // Label 15952: @1004463
     /* 1004463 */   GIM_Reject,
     /* 1004464 */ // Label 15944: @1004464
     /* 1004464 */ GIM_Reject,
     /* 1004465 */ // Label 15932: @1004465
     /* 1004465 */ GIM_Try, /*On fail goto*//*Label 15953*/ GIMT_Encode4(1005549),
     /* 1004470 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 1004473 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004476 */   GIM_Try, /*On fail goto*//*Label 15954*/ GIMT_Encode4(1004544), // Rule ID 79 //
     /* 1004481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1004485 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_EncodableRegClassID),
     /* 1004489 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004493 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004497 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004501 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004505 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004510 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004514 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004518 */     // MIs[2] Operand 1
     /* 1004518 */     // No operand predicates
     /* 1004518 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004522 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20788),
     /* 1004526 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004528 */     // (sra:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_20788>>  =>  (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1004528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I64),
     /* 1004531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1004533 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1004535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004539 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
     /* 1004542 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004543 */     // GIR_Coverage, 79,
     /* 1004543 */     GIR_EraseRootFromParent_Done,
     /* 1004544 */   // Label 15954: @1004544
     /* 1004544 */   GIM_Try, /*On fail goto*//*Label 15955*/ GIMT_Encode4(1004578), // Rule ID 78 //
     /* 1004549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1004553 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_EncodableRegClassID),
     /* 1004557 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
     /* 1004561 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_20788),
     /* 1004565 */     // (sra:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_20788>>  =>  (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
     /* 1004565 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I64),
     /* 1004570 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
     /* 1004576 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004577 */     // GIR_Coverage, 78,
     /* 1004577 */     GIR_Done,
     /* 1004578 */   // Label 15955: @1004578
     /* 1004578 */   GIM_Try, /*On fail goto*//*Label 15956*/ GIMT_Encode4(1004643), // Rule ID 2956 //
     /* 1004583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /* 1004586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004590 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004594 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004598 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004602 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004606 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004610 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004614 */     // MIs[2] Operand 1
     /* 1004614 */     // No operand predicates
     /* 1004614 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004618 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1004627 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1004630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004632 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1004637 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004641 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004642 */     // GIR_Coverage, 2956,
     /* 1004642 */     GIR_EraseRootFromParent_Done,
     /* 1004643 */   // Label 15956: @1004643
     /* 1004643 */   GIM_Try, /*On fail goto*//*Label 15957*/ GIMT_Encode4(1004708), // Rule ID 2957 //
     /* 1004648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /* 1004651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004655 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004659 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004663 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004667 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004671 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004675 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004679 */     // MIs[2] Operand 1
     /* 1004679 */     // No operand predicates
     /* 1004679 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004683 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004685 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1004692 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1004695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004697 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1004702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004706 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004707 */     // GIR_Coverage, 2957,
     /* 1004707 */     GIR_EraseRootFromParent_Done,
     /* 1004708 */   // Label 15957: @1004708
     /* 1004708 */   GIM_Try, /*On fail goto*//*Label 15958*/ GIMT_Encode4(1004773), // Rule ID 2958 //
     /* 1004713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /* 1004716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004732 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004736 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004740 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004744 */     // MIs[2] Operand 1
     /* 1004744 */     // No operand predicates
     /* 1004744 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004748 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004750 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1004757 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1004760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004762 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1004767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004771 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004772 */     // GIR_Coverage, 2958,
     /* 1004772 */     GIR_EraseRootFromParent_Done,
     /* 1004773 */   // Label 15958: @1004773
     /* 1004773 */   GIM_Try, /*On fail goto*//*Label 15959*/ GIMT_Encode4(1004838), // Rule ID 2959 //
     /* 1004778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /* 1004781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004797 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004801 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004805 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004809 */     // MIs[2] Operand 1
     /* 1004809 */     // No operand predicates
     /* 1004809 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004813 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004815 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1004822 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1004825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004827 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1004832 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004836 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004837 */     // GIR_Coverage, 2959,
     /* 1004837 */     GIR_EraseRootFromParent_Done,
     /* 1004838 */   // Label 15959: @1004838
     /* 1004838 */   GIM_Try, /*On fail goto*//*Label 15960*/ GIMT_Encode4(1004903), // Rule ID 2960 //
     /* 1004843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /* 1004846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004850 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004854 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004858 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004862 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004866 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004870 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004874 */     // MIs[2] Operand 1
     /* 1004874 */     // No operand predicates
     /* 1004874 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004878 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004880 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1004887 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1004887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1004890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004892 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1004897 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
     /* 1004901 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004902 */     // GIR_Coverage, 2960,
     /* 1004902 */     GIR_EraseRootFromParent_Done,
     /* 1004903 */   // Label 15960: @1004903
     /* 1004903 */   GIM_Try, /*On fail goto*//*Label 15961*/ GIMT_Encode4(1004966), // Rule ID 2976 //
     /* 1004908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode0),
     /* 1004911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004927 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004935 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1004939 */     // MIs[2] Operand 1
     /* 1004939 */     // No operand predicates
     /* 1004939 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1004943 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1004945 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1004952 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1004952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1004955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1004957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1004962 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1004964 */     GIR_RootConstrainSelectedInstOperands,
     /* 1004965 */     // GIR_Coverage, 2976,
     /* 1004965 */     GIR_EraseRootFromParent_Done,
     /* 1004966 */   // Label 15961: @1004966
     /* 1004966 */   GIM_Try, /*On fail goto*//*Label 15962*/ GIMT_Encode4(1005029), // Rule ID 2977 //
     /* 1004971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode1),
     /* 1004974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1004978 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1004982 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1004986 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1004990 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1004994 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1004998 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1005002 */     // MIs[2] Operand 1
     /* 1005002 */     // No operand predicates
     /* 1005002 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1005006 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1005008 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005015 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005020 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005025 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005027 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005028 */     // GIR_Coverage, 2977,
     /* 1005028 */     GIR_EraseRootFromParent_Done,
     /* 1005029 */   // Label 15962: @1005029
     /* 1005029 */   GIM_Try, /*On fail goto*//*Label 15963*/ GIMT_Encode4(1005092), // Rule ID 2978 //
     /* 1005034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode2),
     /* 1005037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005041 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1005045 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1005049 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1005053 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1005057 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1005061 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1005065 */     // MIs[2] Operand 1
     /* 1005065 */     // No operand predicates
     /* 1005065 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1005069 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1005071 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005078 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005083 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005088 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005090 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005091 */     // GIR_Coverage, 2978,
     /* 1005091 */     GIR_EraseRootFromParent_Done,
     /* 1005092 */   // Label 15963: @1005092
     /* 1005092 */   GIM_Try, /*On fail goto*//*Label 15964*/ GIMT_Encode4(1005155), // Rule ID 2979 //
     /* 1005097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode3),
     /* 1005100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005104 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1005108 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1005112 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1005116 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1005120 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1005124 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1005128 */     // MIs[2] Operand 1
     /* 1005128 */     // No operand predicates
     /* 1005128 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1005132 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1005134 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005141 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005151 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005153 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005154 */     // GIR_Coverage, 2979,
     /* 1005154 */     GIR_EraseRootFromParent_Done,
     /* 1005155 */   // Label 15964: @1005155
     /* 1005155 */   GIM_Try, /*On fail goto*//*Label 15965*/ GIMT_Encode4(1005218), // Rule ID 2980 //
     /* 1005160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode4),
     /* 1005163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1005171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1005175 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 1005179 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 1005183 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1005187 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1005191 */     // MIs[2] Operand 1
     /* 1005191 */     // No operand predicates
     /* 1005191 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
     /* 1005195 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1005197 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005204 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005214 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005216 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005217 */     // GIR_Coverage, 2980,
     /* 1005217 */     GIR_EraseRootFromParent_Done,
     /* 1005218 */   // Label 15965: @1005218
     /* 1005218 */   GIM_Try, /*On fail goto*//*Label 15966*/ GIMT_Encode4(1005251), // Rule ID 2951 //
     /* 1005223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode0),
     /* 1005226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005230 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005237 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1005237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1005240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005247 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1005249 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005250 */     // GIR_Coverage, 2951,
     /* 1005250 */     GIR_EraseRootFromParent_Done,
     /* 1005251 */   // Label 15966: @1005251
     /* 1005251 */   GIM_Try, /*On fail goto*//*Label 15967*/ GIMT_Encode4(1005284), // Rule ID 2952 //
     /* 1005256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode1),
     /* 1005259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005263 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005270 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1005270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1005273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005280 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1005282 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005283 */     // GIR_Coverage, 2952,
     /* 1005283 */     GIR_EraseRootFromParent_Done,
     /* 1005284 */   // Label 15967: @1005284
     /* 1005284 */   GIM_Try, /*On fail goto*//*Label 15968*/ GIMT_Encode4(1005317), // Rule ID 2953 //
     /* 1005289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode2),
     /* 1005292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005303 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1005303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1005306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005313 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1005315 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005316 */     // GIR_Coverage, 2953,
     /* 1005316 */     GIR_EraseRootFromParent_Done,
     /* 1005317 */   // Label 15968: @1005317
     /* 1005317 */   GIM_Try, /*On fail goto*//*Label 15969*/ GIMT_Encode4(1005350), // Rule ID 2954 //
     /* 1005322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode3),
     /* 1005325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005329 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005336 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1005336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1005339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005341 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005346 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1005348 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005349 */     // GIR_Coverage, 2954,
     /* 1005349 */     GIR_EraseRootFromParent_Done,
     /* 1005350 */   // Label 15969: @1005350
     /* 1005350 */   GIM_Try, /*On fail goto*//*Label 15970*/ GIMT_Encode4(1005383), // Rule ID 2955 //
     /* 1005355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7_HwMode4),
     /* 1005358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005362 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005369 */     // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
     /* 1005369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
     /* 1005372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005374 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005379 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1005381 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005382 */     // GIR_Coverage, 2955,
     /* 1005382 */     GIR_EraseRootFromParent_Done,
     /* 1005383 */   // Label 15970: @1005383
     /* 1005383 */   GIM_Try, /*On fail goto*//*Label 15971*/ GIMT_Encode4(1005416), // Rule ID 2971 //
     /* 1005388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode0),
     /* 1005391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005395 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005402 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005407 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005412 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005414 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005415 */     // GIR_Coverage, 2971,
     /* 1005415 */     GIR_EraseRootFromParent_Done,
     /* 1005416 */   // Label 15971: @1005416
     /* 1005416 */   GIM_Try, /*On fail goto*//*Label 15972*/ GIMT_Encode4(1005449), // Rule ID 2972 //
     /* 1005421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode1),
     /* 1005424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005428 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005435 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005440 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005445 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005447 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005448 */     // GIR_Coverage, 2972,
     /* 1005448 */     GIR_EraseRootFromParent_Done,
     /* 1005449 */   // Label 15972: @1005449
     /* 1005449 */   GIM_Try, /*On fail goto*//*Label 15973*/ GIMT_Encode4(1005482), // Rule ID 2973 //
     /* 1005454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode2),
     /* 1005457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005461 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005468 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005478 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005480 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005481 */     // GIR_Coverage, 2973,
     /* 1005481 */     GIR_EraseRootFromParent_Done,
     /* 1005482 */   // Label 15973: @1005482
     /* 1005482 */   GIM_Try, /*On fail goto*//*Label 15974*/ GIMT_Encode4(1005515), // Rule ID 2974 //
     /* 1005487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode3),
     /* 1005490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005494 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005501 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005511 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005513 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005514 */     // GIR_Coverage, 2974,
     /* 1005514 */     GIR_EraseRootFromParent_Done,
     /* 1005515 */   // Label 15974: @1005515
     /* 1005515 */   GIM_Try, /*On fail goto*//*Label 15975*/ GIMT_Encode4(1005548), // Rule ID 2975 //
     /* 1005520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus_HwMode4),
     /* 1005523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
     /* 1005527 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1005534 */     // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
     /* 1005534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
     /* 1005537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005544 */     GIR_RootToRootCopy, /*OpIdx*/1, // src1
     /* 1005546 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005547 */     // GIR_Coverage, 2975,
     /* 1005547 */     GIR_EraseRootFromParent_Done,
     /* 1005548 */   // Label 15975: @1005548
     /* 1005548 */   GIM_Reject,
     /* 1005549 */ // Label 15953: @1005549
     /* 1005549 */ GIM_Reject,
     /* 1005550 */ // Label 15933: @1005550
     /* 1005550 */ GIM_Try, /*On fail goto*//*Label 15976*/ GIMT_Encode4(1005718),
     /* 1005555 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 1005558 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 1005561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1005565 */   GIM_Try, /*On fail goto*//*Label 15977*/ GIMT_Encode4(1005656), // Rule ID 3330 //
     /* 1005570 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 1005574 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 1005578 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 1005582 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 1005586 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 1005590 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1005594 */     // MIs[2] Operand 1
     /* 1005594 */     // No operand predicates
     /* 1005594 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
     /* 1005598 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 1005600 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1005607 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1005614 */     // (sra:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_PK_ASHRREV_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /* 1005614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ASHRREV_I16),
     /* 1005617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1005624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1005629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1005634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1005639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005651 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005654 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005655 */     // GIR_Coverage, 3330,
     /* 1005655 */     GIR_EraseRootFromParent_Done,
     /* 1005656 */   // Label 15977: @1005656
     /* 1005656 */   GIM_Try, /*On fail goto*//*Label 15978*/ GIMT_Encode4(1005717), // Rule ID 3329 //
     /* 1005661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1005668 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
     /* 1005675 */     // (sra:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_ASHRREV_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
     /* 1005675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ASHRREV_I16),
     /* 1005678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
     /* 1005685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
     /* 1005690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
     /* 1005695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
     /* 1005700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005706 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005709 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005715 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005716 */     // GIR_Coverage, 3329,
     /* 1005716 */     GIR_EraseRootFromParent_Done,
     /* 1005717 */   // Label 15978: @1005717
     /* 1005717 */   GIM_Reject,
     /* 1005718 */ // Label 15976: @1005718
     /* 1005718 */ GIM_Reject,
     /* 1005719 */ // Label 15934: @1005719
     /* 1005719 */ GIM_Reject,
     /* 1005720 */ // Label 51: @1005720
     /* 1005720 */ GIM_Try, /*On fail goto*//*Label 15979*/ GIMT_Encode4(1006258),
     /* 1005725 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 1005728 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 1005731 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 1005734 */   GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 15982*/ GIMT_Encode4(1006219),
     /* 1005745 */   /*GILLT_s16*//*Label 15980*/ GIMT_Encode4(1005753),
     /* 1005749 */   /*GILLT_s32*//*Label 15981*/ GIMT_Encode4(1005830),
     /* 1005753 */   // Label 15980: @1005753
     /* 1005753 */   GIM_Try, /*On fail goto*//*Label 15983*/ GIMT_Encode4(1005829), // Rule ID 2889 //
     /* 1005758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /* 1005761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1005765 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1005772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1005779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
     /* 1005786 */     // (fshr:{ *:[i32] } (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_ALIGNBIT_B32_fake16_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i16:{ *:[i16] }:$src2)
     /* 1005786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_fake16_e64),
     /* 1005789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1005791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1005796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1005801 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1005806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1005811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
     /* 1005816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
     /* 1005821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1005827 */     GIR_RootConstrainSelectedInstOperands,
     /* 1005828 */     // GIR_Coverage, 2889,
     /* 1005828 */     GIR_EraseRootFromParent_Done,
     /* 1005829 */   // Label 15983: @1005829
     /* 1005829 */   GIM_Reject,
     /* 1005830 */   // Label 15981: @1005830
     /* 1005830 */   GIM_Try, /*On fail goto*//*Label 15984*/ GIMT_Encode4(1005945), // Rule ID 27377 //
     /* 1005835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /* 1005839 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 1005843 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 1005847 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_ShiftAmt32Imm),
     /* 1005851 */     // MIs[1] Operand 1
     /* 1005851 */     // No operand predicates
     /* 1005851 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_44406),
     /* 1005855 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 1005857 */     // (fshr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_ShiftAmt32Imm>>:$src2)<<P:Predicate_anonymous_44406>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (S_LSHR_B64:{ *:[i1] }:{ *:[i1] } (REG_SEQUENCE:{ *:[i1] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src1, sub0:{ *:[i32] }, ?:{ *:[i32] }:$src0, sub1:{ *:[i32] }), ?:{ *:[i32] }:$src2), sub0:{ *:[i32] })
     /* 1005857 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /* 1005860 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /* 1005864 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 1005869 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1
     /* 1005873 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /* 1005876 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
     /* 1005880 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /* 1005883 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1005888 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /* 1005893 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /* 1005898 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /* 1005901 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64),
     /* 1005905 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 1005910 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 1005913 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src2
     /* 1005917 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AMDGPU::SCC*/0,
     /* 1005920 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 1005922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 1005925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 1005927 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /* 1005934 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /* 1005939 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1005944 */     // GIR_Coverage, 27377,
     /* 1005944 */     GIR_EraseRootFromParent_Done,
     /* 1005945 */   // Label 15984: @1005945
     /* 1005945 */   GIM_Try, /*On fail goto*//*Label 15985*/ GIMT_Encode4(1006069), // Rule ID 27376 //
     /* 1005950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /* 1005954 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_44406),
     /* 1005958 */     // (fshr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_44406>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (S_LSHR_B64:{ *:[i1] }:{ *:[i1] } (REG_SEQUENCE:{ *:[i1] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src1, sub0:{ *:[i32] }, ?:{ *:[i32] }:$src0, sub1:{ *:[i32] }), (S_AND_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i32] }:$src2, 31:{ *:[i32] })), sub0:{ *:[i32] })
     /* 1005958 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1,
     /* 1005961 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
     /* 1005965 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 1005970 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // src2
     /* 1005974 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/31,
     /* 1005977 */     GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for AMDGPU::SCC*/0,
     /* 1005980 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 1005982 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
     /* 1005985 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
     /* 1005989 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 1005994 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1
     /* 1005998 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
     /* 1006001 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
     /* 1006005 */     GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
     /* 1006008 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1006013 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /* 1006018 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
     /* 1006023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
     /* 1006026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64),
     /* 1006030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 1006035 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 1006038 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 1006041 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AMDGPU::SCC*/0,
     /* 1006044 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 1006046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 1006049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 1006051 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
     /* 1006058 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
     /* 1006063 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1006068 */     // GIR_Coverage, 27376,
     /* 1006068 */     GIR_EraseRootFromParent_Done,
     /* 1006069 */   // Label 15985: @1006069
     /* 1006069 */   GIM_Try, /*On fail goto*//*Label 15986*/ GIMT_Encode4(1006109), // Rule ID 28043 //
     /* 1006074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX9GFX10),
     /* 1006077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1006081 */     // (fshr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32_opsel_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
     /* 1006081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_opsel_e64),
     /* 1006084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1006086 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006089 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1006091 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006094 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1006096 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006099 */     GIR_RootToRootCopy, /*OpIdx*/3, // src2
     /* 1006101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006107 */     GIR_RootConstrainSelectedInstOperands,
     /* 1006108 */     // GIR_Coverage, 28043,
     /* 1006108 */     GIR_EraseRootFromParent_Done,
     /* 1006109 */   // Label 15986: @1006109
     /* 1006109 */   GIM_Try, /*On fail goto*//*Label 15987*/ GIMT_Encode4(1006178), // Rule ID 28045 //
     /* 1006114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
     /* 1006117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1006121 */     // (fshr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32_t16_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i16] } VGPR_32:{ *:[i32] }:$src2, lo16:{ *:[i32] }), 0:{ *:[i1] }, 0:{ *:[i32] })
     /* 1006121 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 1006124 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 1006128 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 1006133 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(2), // src2
     /* 1006139 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
     /* 1006144 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1006149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_t16_e64),
     /* 1006152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1006154 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006157 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1006159 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006162 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1006164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006167 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 1006170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006173 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006176 */     GIR_RootConstrainSelectedInstOperands,
     /* 1006177 */     // GIR_Coverage, 28045,
     /* 1006177 */     GIR_EraseRootFromParent_Done,
     /* 1006178 */   // Label 15987: @1006178
     /* 1006178 */   GIM_Try, /*On fail goto*//*Label 15988*/ GIMT_Encode4(1006218), // Rule ID 28048 //
     /* 1006183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
     /* 1006186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1006190 */     // (fshr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32_fake16_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
     /* 1006190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_fake16_e64),
     /* 1006193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1006195 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006198 */     GIR_RootToRootCopy, /*OpIdx*/1, // src0
     /* 1006200 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006203 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1006205 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006208 */     GIR_RootToRootCopy, /*OpIdx*/3, // src2
     /* 1006210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006213 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006216 */     GIR_RootConstrainSelectedInstOperands,
     /* 1006217 */     // GIR_Coverage, 28048,
     /* 1006217 */     GIR_EraseRootFromParent_Done,
     /* 1006218 */   // Label 15988: @1006218
     /* 1006218 */   GIM_Reject,
     /* 1006219 */   // Label 15982: @1006219
     /* 1006219 */   GIM_Try, /*On fail goto*//*Label 15989*/ GIMT_Encode4(1006257), // Rule ID 2888 //
     /* 1006224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
     /* 1006227 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 1006230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
     /* 1006234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006241 */     // (fshr:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
     /* 1006241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
     /* 1006244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst]
     /* 1006246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006251 */     GIR_RootToRootCopy, /*OpIdx*/2, // src1
     /* 1006253 */     GIR_RootToRootCopy, /*OpIdx*/3, // src2
     /* 1006255 */     GIR_RootConstrainSelectedInstOperands,
     /* 1006256 */     // GIR_Coverage, 2888,
     /* 1006256 */     GIR_EraseRootFromParent_Done,
     /* 1006257 */   // Label 15989: @1006257
     /* 1006257 */   GIM_Reject,
     /* 1006258 */ // Label 15979: @1006258
     /* 1006258 */ GIM_Reject,
     /* 1006259 */ // Label 52: @1006259
     /* 1006259 */ GIM_Try, /*On fail goto*//*Label 15990*/ GIMT_Encode4(1014030),
     /* 1006264 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1,
     /* 1006267 */   GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 15994*/ GIMT_Encode4(1012542),
     /* 1006278 */   /*GILLT_s16*//*Label 15991*/ GIMT_Encode4(1006290),
     /* 1006282 */   /*GILLT_s32*//*Label 15992*/ GIMT_Encode4(1011554),
     /* 1006286 */   /*GILLT_s64*//*Label 15993*/ GIMT_Encode4(1012048),
     /* 1006290 */   // Label 15991: @1006290
     /* 1006290 */   GIM_Try, /*On fail goto*//*Label 15995*/ GIMT_Encode4(1011553),
     /* 1006295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 1006298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
     /* 1006302 */     GIM_Try, /*On fail goto*//*Label 15996*/ GIMT_Encode4(1006359), // Rule ID 1499 //
     /* 1006307 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0),
     /* 1006310 */       // MIs[0] Operand 1
     /* 1006310 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 1006315 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006322 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006329 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006329 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64),
     /* 1006332 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006334 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006339 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006344 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006349 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006354 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006357 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006358 */       // GIR_Coverage, 1499,
     /* 1006358 */       GIR_EraseRootFromParent_Done,
     /* 1006359 */     // Label 15996: @1006359
     /* 1006359 */     GIM_Try, /*On fail goto*//*Label 15997*/ GIMT_Encode4(1006416), // Rule ID 1500 //
     /* 1006364 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1),
     /* 1006367 */       // MIs[0] Operand 1
     /* 1006367 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 1006372 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006379 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006386 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006386 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64),
     /* 1006389 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006391 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006396 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006401 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006406 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006411 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006414 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006415 */       // GIR_Coverage, 1500,
     /* 1006415 */       GIR_EraseRootFromParent_Done,
     /* 1006416 */     // Label 15997: @1006416
     /* 1006416 */     GIM_Try, /*On fail goto*//*Label 15998*/ GIMT_Encode4(1006473), // Rule ID 1501 //
     /* 1006421 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2),
     /* 1006424 */       // MIs[0] Operand 1
     /* 1006424 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 1006429 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006436 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006443 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006443 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64),
     /* 1006446 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006448 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006453 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006458 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006463 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006468 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006471 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006472 */       // GIR_Coverage, 1501,
     /* 1006472 */       GIR_EraseRootFromParent_Done,
     /* 1006473 */     // Label 15998: @1006473
     /* 1006473 */     GIM_Try, /*On fail goto*//*Label 15999*/ GIMT_Encode4(1006530), // Rule ID 1502 //
     /* 1006478 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode3),
     /* 1006481 */       // MIs[0] Operand 1
     /* 1006481 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 1006486 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006493 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006500 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006500 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64),
     /* 1006503 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006505 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006510 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006515 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006520 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006525 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006528 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006529 */       // GIR_Coverage, 1502,
     /* 1006529 */       GIR_EraseRootFromParent_Done,
     /* 1006530 */     // Label 15999: @1006530
     /* 1006530 */     GIM_Try, /*On fail goto*//*Label 16000*/ GIMT_Encode4(1006587), // Rule ID 1503 //
     /* 1006535 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode4),
     /* 1006538 */       // MIs[0] Operand 1
     /* 1006538 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 1006543 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006550 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006557 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006557 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64),
     /* 1006560 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006562 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006567 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006572 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006577 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006582 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006585 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006586 */       // GIR_Coverage, 1503,
     /* 1006586 */       GIR_EraseRootFromParent_Done,
     /* 1006587 */     // Label 16000: @1006587
     /* 1006587 */     GIM_Try, /*On fail goto*//*Label 16001*/ GIMT_Encode4(1006644), // Rule ID 1529 //
     /* 1006592 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0),
     /* 1006595 */       // MIs[0] Operand 1
     /* 1006595 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 1006600 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006607 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006614 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006614 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64),
     /* 1006617 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006619 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006624 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006629 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006634 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006639 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006642 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006643 */       // GIR_Coverage, 1529,
     /* 1006643 */       GIR_EraseRootFromParent_Done,
     /* 1006644 */     // Label 16001: @1006644
     /* 1006644 */     GIM_Try, /*On fail goto*//*Label 16002*/ GIMT_Encode4(1006701), // Rule ID 1530 //
     /* 1006649 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1),
     /* 1006652 */       // MIs[0] Operand 1
     /* 1006652 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 1006657 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006664 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006671 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006671 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64),
     /* 1006674 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006676 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006681 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006686 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006691 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006696 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006699 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006700 */       // GIR_Coverage, 1530,
     /* 1006700 */       GIR_EraseRootFromParent_Done,
     /* 1006701 */     // Label 16002: @1006701
     /* 1006701 */     GIM_Try, /*On fail goto*//*Label 16003*/ GIMT_Encode4(1006758), // Rule ID 1531 //
     /* 1006706 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2),
     /* 1006709 */       // MIs[0] Operand 1
     /* 1006709 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 1006714 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006721 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006728 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006728 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64),
     /* 1006731 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006733 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006738 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006743 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006748 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006753 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006756 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006757 */       // GIR_Coverage, 1531,
     /* 1006757 */       GIR_EraseRootFromParent_Done,
     /* 1006758 */     // Label 16003: @1006758
     /* 1006758 */     GIM_Try, /*On fail goto*//*Label 16004*/ GIMT_Encode4(1006815), // Rule ID 1532 //
     /* 1006763 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode3),
     /* 1006766 */       // MIs[0] Operand 1
     /* 1006766 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 1006771 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006778 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006785 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006785 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64),
     /* 1006788 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006790 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006795 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006800 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006805 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006810 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006813 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006814 */       // GIR_Coverage, 1532,
     /* 1006814 */       GIR_EraseRootFromParent_Done,
     /* 1006815 */     // Label 16004: @1006815
     /* 1006815 */     GIM_Try, /*On fail goto*//*Label 16005*/ GIMT_Encode4(1006872), // Rule ID 1533 //
     /* 1006820 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode4),
     /* 1006823 */       // MIs[0] Operand 1
     /* 1006823 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 1006828 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006835 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006842 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006842 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64),
     /* 1006845 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006847 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006852 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006857 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006862 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006867 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006870 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006871 */       // GIR_Coverage, 1533,
     /* 1006871 */       GIR_EraseRootFromParent_Done,
     /* 1006872 */     // Label 16005: @1006872
     /* 1006872 */     GIM_Try, /*On fail goto*//*Label 16006*/ GIMT_Encode4(1006929), // Rule ID 1544 //
     /* 1006877 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0),
     /* 1006880 */       // MIs[0] Operand 1
     /* 1006880 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 1006885 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006892 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006899 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006899 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64),
     /* 1006902 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006904 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006909 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006914 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006919 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006924 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006927 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006928 */       // GIR_Coverage, 1544,
     /* 1006928 */       GIR_EraseRootFromParent_Done,
     /* 1006929 */     // Label 16006: @1006929
     /* 1006929 */     GIM_Try, /*On fail goto*//*Label 16007*/ GIMT_Encode4(1006986), // Rule ID 1545 //
     /* 1006934 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1),
     /* 1006937 */       // MIs[0] Operand 1
     /* 1006937 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 1006942 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1006949 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1006956 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1006956 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64),
     /* 1006959 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1006961 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1006966 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1006971 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1006976 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1006981 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1006984 */       GIR_RootConstrainSelectedInstOperands,
     /* 1006985 */       // GIR_Coverage, 1545,
     /* 1006985 */       GIR_EraseRootFromParent_Done,
     /* 1006986 */     // Label 16007: @1006986
     /* 1006986 */     GIM_Try, /*On fail goto*//*Label 16008*/ GIMT_Encode4(1007043), // Rule ID 1546 //
     /* 1006991 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2),
     /* 1006994 */       // MIs[0] Operand 1
     /* 1006994 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 1006999 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007006 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007013 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007013 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64),
     /* 1007016 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007018 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007023 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007028 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007033 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007038 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007041 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007042 */       // GIR_Coverage, 1546,
     /* 1007042 */       GIR_EraseRootFromParent_Done,
     /* 1007043 */     // Label 16008: @1007043
     /* 1007043 */     GIM_Try, /*On fail goto*//*Label 16009*/ GIMT_Encode4(1007100), // Rule ID 1547 //
     /* 1007048 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode3),
     /* 1007051 */       // MIs[0] Operand 1
     /* 1007051 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 1007056 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007063 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007070 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007070 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64),
     /* 1007073 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007075 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007080 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007085 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007090 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007095 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007098 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007099 */       // GIR_Coverage, 1547,
     /* 1007099 */       GIR_EraseRootFromParent_Done,
     /* 1007100 */     // Label 16009: @1007100
     /* 1007100 */     GIM_Try, /*On fail goto*//*Label 16010*/ GIMT_Encode4(1007157), // Rule ID 1548 //
     /* 1007105 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode4),
     /* 1007108 */       // MIs[0] Operand 1
     /* 1007108 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 1007113 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007120 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007127 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007127 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64),
     /* 1007130 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007132 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007137 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007142 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007147 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007152 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007155 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007156 */       // GIR_Coverage, 1548,
     /* 1007156 */       GIR_EraseRootFromParent_Done,
     /* 1007157 */     // Label 16010: @1007157
     /* 1007157 */     GIM_Try, /*On fail goto*//*Label 16011*/ GIMT_Encode4(1007214), // Rule ID 1574 //
     /* 1007162 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0),
     /* 1007165 */       // MIs[0] Operand 1
     /* 1007165 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 1007170 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007177 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007184 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007184 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64),
     /* 1007187 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007189 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007194 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007199 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007204 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007209 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007212 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007213 */       // GIR_Coverage, 1574,
     /* 1007213 */       GIR_EraseRootFromParent_Done,
     /* 1007214 */     // Label 16011: @1007214
     /* 1007214 */     GIM_Try, /*On fail goto*//*Label 16012*/ GIMT_Encode4(1007271), // Rule ID 1575 //
     /* 1007219 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1),
     /* 1007222 */       // MIs[0] Operand 1
     /* 1007222 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 1007227 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007234 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007241 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007241 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64),
     /* 1007244 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007246 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007251 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007256 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007261 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007266 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007269 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007270 */       // GIR_Coverage, 1575,
     /* 1007270 */       GIR_EraseRootFromParent_Done,
     /* 1007271 */     // Label 16012: @1007271
     /* 1007271 */     GIM_Try, /*On fail goto*//*Label 16013*/ GIMT_Encode4(1007328), // Rule ID 1576 //
     /* 1007276 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2),
     /* 1007279 */       // MIs[0] Operand 1
     /* 1007279 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 1007284 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007291 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007298 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007298 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64),
     /* 1007301 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007303 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007308 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007313 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007318 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007323 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007326 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007327 */       // GIR_Coverage, 1576,
     /* 1007327 */       GIR_EraseRootFromParent_Done,
     /* 1007328 */     // Label 16013: @1007328
     /* 1007328 */     GIM_Try, /*On fail goto*//*Label 16014*/ GIMT_Encode4(1007385), // Rule ID 1577 //
     /* 1007333 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode3),
     /* 1007336 */       // MIs[0] Operand 1
     /* 1007336 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 1007341 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007348 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007355 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007355 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64),
     /* 1007358 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007360 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007365 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007370 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007375 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007380 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007383 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007384 */       // GIR_Coverage, 1577,
     /* 1007384 */       GIR_EraseRootFromParent_Done,
     /* 1007385 */     // Label 16014: @1007385
     /* 1007385 */     GIM_Try, /*On fail goto*//*Label 16015*/ GIMT_Encode4(1007442), // Rule ID 1578 //
     /* 1007390 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode4),
     /* 1007393 */       // MIs[0] Operand 1
     /* 1007393 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 1007398 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007405 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007412 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007412 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64),
     /* 1007415 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007417 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007422 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007427 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007432 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007437 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007440 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007441 */       // GIR_Coverage, 1578,
     /* 1007441 */       GIR_EraseRootFromParent_Done,
     /* 1007442 */     // Label 16015: @1007442
     /* 1007442 */     GIM_Try, /*On fail goto*//*Label 16016*/ GIMT_Encode4(1007499), // Rule ID 1619 //
     /* 1007447 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0),
     /* 1007450 */       // MIs[0] Operand 1
     /* 1007450 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 1007455 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007462 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007469 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007469 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64),
     /* 1007472 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007474 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007479 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007484 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007489 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007494 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007497 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007498 */       // GIR_Coverage, 1619,
     /* 1007498 */       GIR_EraseRootFromParent_Done,
     /* 1007499 */     // Label 16016: @1007499
     /* 1007499 */     GIM_Try, /*On fail goto*//*Label 16017*/ GIMT_Encode4(1007556), // Rule ID 1620 //
     /* 1007504 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1),
     /* 1007507 */       // MIs[0] Operand 1
     /* 1007507 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 1007512 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007519 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007526 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007526 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64),
     /* 1007529 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007531 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007536 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007541 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007546 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007551 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007554 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007555 */       // GIR_Coverage, 1620,
     /* 1007555 */       GIR_EraseRootFromParent_Done,
     /* 1007556 */     // Label 16017: @1007556
     /* 1007556 */     GIM_Try, /*On fail goto*//*Label 16018*/ GIMT_Encode4(1007613), // Rule ID 1621 //
     /* 1007561 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2),
     /* 1007564 */       // MIs[0] Operand 1
     /* 1007564 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 1007569 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007576 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007583 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007583 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64),
     /* 1007586 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007588 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007593 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007598 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007603 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007608 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007611 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007612 */       // GIR_Coverage, 1621,
     /* 1007612 */       GIR_EraseRootFromParent_Done,
     /* 1007613 */     // Label 16018: @1007613
     /* 1007613 */     GIM_Try, /*On fail goto*//*Label 16019*/ GIMT_Encode4(1007670), // Rule ID 1622 //
     /* 1007618 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode3),
     /* 1007621 */       // MIs[0] Operand 1
     /* 1007621 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 1007626 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007633 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007640 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007640 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64),
     /* 1007643 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007645 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007650 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007655 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007660 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007665 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007668 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007669 */       // GIR_Coverage, 1622,
     /* 1007669 */       GIR_EraseRootFromParent_Done,
     /* 1007670 */     // Label 16019: @1007670
     /* 1007670 */     GIM_Try, /*On fail goto*//*Label 16020*/ GIMT_Encode4(1007727), // Rule ID 1623 //
     /* 1007675 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode4),
     /* 1007678 */       // MIs[0] Operand 1
     /* 1007678 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 1007683 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007690 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007697 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007697 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64),
     /* 1007700 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007702 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007707 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007712 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007717 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007722 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007725 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007726 */       // GIR_Coverage, 1623,
     /* 1007726 */       GIR_EraseRootFromParent_Done,
     /* 1007727 */     // Label 16020: @1007727
     /* 1007727 */     GIM_Try, /*On fail goto*//*Label 16021*/ GIMT_Encode4(1007784), // Rule ID 1639 //
     /* 1007732 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode0),
     /* 1007735 */       // MIs[0] Operand 1
     /* 1007735 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 1007740 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007747 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007754 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETEQ:{ *:[Other] })  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007754 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /* 1007757 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007759 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007764 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007769 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007774 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007779 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007782 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007783 */       // GIR_Coverage, 1639,
     /* 1007783 */       GIR_EraseRootFromParent_Done,
     /* 1007784 */     // Label 16021: @1007784
     /* 1007784 */     GIM_Try, /*On fail goto*//*Label 16022*/ GIMT_Encode4(1007841), // Rule ID 1640 //
     /* 1007789 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode1),
     /* 1007792 */       // MIs[0] Operand 1
     /* 1007792 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 1007797 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
     /* 1007804 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
     /* 1007811 */       // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETEQ:{ *:[Other] })  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
     /* 1007811 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
     /* 1007814 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst]
     /* 1007816 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
     /* 1007821 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
     /* 1007826 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
     /* 1007831 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
     /* 1007836 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 1007839 */       GIR_RootConstrainSelectedInstOperands,
     /* 1007840 */       // GIR_Coverage, 1640,
     /* 1007840 */       GIR_EraseRootFromParent_Done,
     /* 1007841 */     // Label 16022: @1007841
     /* 1007841 */     GIM_Try, /*On fail goto*//*Label 16023*/ GIMT_Encode4(1007898), // Rule ID 1641 //
     /* 1007846 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_UseRealTrue16Insts_HwMode2),
     /* 1007849 */       // MIs[0] Operand 1
     /* 1007849 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 1007854 */       GIM_CheckComplexPatte